1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
29 /* #define SPARC_BI_ARCH */
31 /* Macro used later in this file to determine default architecture. */
32 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
34 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
35 architectures to compile for. We allow targets to choose compile time or
38 #if defined(__sparcv9) || defined(__arch64__)
39 #define TARGET_ARCH32 0
41 #define TARGET_ARCH32 1
45 #define TARGET_ARCH32 (! TARGET_64BIT)
47 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
48 #endif /* SPARC_BI_ARCH */
49 #endif /* IN_LIBGCC2 */
50 #define TARGET_ARCH64 (! TARGET_ARCH32)
52 /* Code model selection.
53 -mcmodel is used to select the v9 code model.
54 Different code models aren't supported for v7/8 code.
56 TARGET_CM_32: 32 bit address space, top 32 bits = 0,
57 pointers are 32 bits. Note that this isn't intended
60 TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0,
61 avoid generating %uhi and %ulo terms,
64 TARGET_CM_MEDMID: 64 bit address space.
65 The executable must be in the low 16 TB of memory.
66 This corresponds to the low 44 bits, and the %[hml]44
67 relocs are used. The text segment has a maximum size
70 TARGET_CM_MEDANY: 64 bit address space.
71 The text and data segments have a maximum size of 31
72 bits and may be located anywhere. The maximum offset
73 from any instruction to the label _GLOBAL_OFFSET_TABLE_
76 TARGET_CM_EMBMEDANY: 64 bit address space.
77 The text and data segments have a maximum size of 31 bits
78 and may be located anywhere. Register %g4 contains
79 the start address of the data segment.
90 /* Value of -mcmodel specified by user. */
91 extern const char *sparc_cmodel_string;
93 extern enum cmodel sparc_cmodel;
95 /* V9 code model selection. */
96 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
97 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
98 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
99 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
101 #define SPARC_DEFAULT_CMODEL CM_32
103 /* This is call-clobbered in the normal ABI, but is reserved in the
104 home grown (aka upward compatible) embedded ABI. */
105 #define EMBMEDANY_BASE_REG "%g4"
107 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
108 and specified by the user via --with-cpu=foo.
109 This specifies the cpu implementation, not the architecture size. */
110 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
112 #define TARGET_CPU_sparc 0
113 #define TARGET_CPU_v7 0 /* alias for previous */
114 #define TARGET_CPU_sparclet 1
115 #define TARGET_CPU_sparclite 2
116 #define TARGET_CPU_v8 3 /* generic v8 implementation */
117 #define TARGET_CPU_supersparc 4
118 #define TARGET_CPU_hypersparc 5
119 #define TARGET_CPU_sparc86x 6
120 #define TARGET_CPU_sparclite86x 6
121 #define TARGET_CPU_v9 7 /* generic v9 implementation */
122 #define TARGET_CPU_sparcv9 7 /* alias */
123 #define TARGET_CPU_sparc64 7 /* alias */
124 #define TARGET_CPU_ultrasparc 8
125 #define TARGET_CPU_ultrasparc3 9
127 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
128 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
129 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
131 #define CPP_CPU32_DEFAULT_SPEC ""
132 #define ASM_CPU32_DEFAULT_SPEC ""
134 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
135 /* ??? What does Sun's CC pass? */
136 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
137 /* ??? It's not clear how other assemblers will handle this, so by default
138 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
139 is handled in sol2.h. */
140 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
142 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
143 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
144 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
146 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
147 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
148 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
153 #define CPP_CPU64_DEFAULT_SPEC ""
154 #define ASM_CPU64_DEFAULT_SPEC ""
156 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
157 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
158 #define CPP_CPU32_DEFAULT_SPEC ""
159 #define ASM_CPU32_DEFAULT_SPEC ""
162 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
163 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
164 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
167 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
168 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
169 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
172 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
173 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
174 #define ASM_CPU32_DEFAULT_SPEC ""
177 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
178 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
179 #define ASM_CPU32_DEFAULT_SPEC ""
182 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
183 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
184 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
189 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
190 Unrecognized value in TARGET_CPU_DEFAULT.
195 #define CPP_CPU_DEFAULT_SPEC \
196 (DEFAULT_ARCH32_P ? "\
197 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
198 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
200 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
201 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
203 #define ASM_CPU_DEFAULT_SPEC \
204 (DEFAULT_ARCH32_P ? "\
205 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
206 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
208 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
209 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
212 #else /* !SPARC_BI_ARCH */
214 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
215 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
217 #endif /* !SPARC_BI_ARCH */
219 /* Define macros to distinguish architectures. */
221 /* Common CPP definitions used by CPP_SPEC amongst the various targets
222 for handling -mcpu=xxx switches. */
223 #define CPP_CPU_SPEC "\
224 %{msoft-float:-D_SOFT_FLOAT} \
226 %{msparclite:-D__sparclite__} \
227 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
228 %{mv8:-D__sparc_v8__} \
229 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
230 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
231 %{mcpu=sparclite:-D__sparclite__} \
232 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
233 %{mcpu=v8:-D__sparc_v8__} \
234 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
235 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
236 %{mcpu=sparclite86x:-D__sparclite86x__} \
237 %{mcpu=v9:-D__sparc_v9__} \
238 %{mcpu=ultrasparc:-D__sparc_v9__} \
239 %{mcpu=ultrasparc3:-D__sparc_v9__} \
240 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
243 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
244 the right varags.h file when bootstrapping. */
245 /* ??? It's not clear what value we want to use for -Acpu/machine for
246 sparc64 in 32 bit environments, so for now we only use `sparc64' in
247 64 bit environments. */
251 #define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \
252 -D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
253 #define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
254 -D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
258 #define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
259 #define CPP_ARCH64_SPEC "-D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
263 #define CPP_ARCH_DEFAULT_SPEC \
264 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
266 #define CPP_ARCH_SPEC "\
267 %{m32:%(cpp_arch32)} \
268 %{m64:%(cpp_arch64)} \
269 %{!m32:%{!m64:%(cpp_arch_default)}} \
272 /* Macros to distinguish endianness. */
273 #define CPP_ENDIAN_SPEC "\
274 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
275 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
277 /* Macros to distinguish the particular subtarget. */
278 #define CPP_SUBTARGET_SPEC ""
280 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
282 /* Prevent error on `-sun4' and `-target sun4' options. */
283 /* This used to translate -dalign to -malign, but that is no good
284 because it can't turn off the usual meaning of making debugging dumps. */
285 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
286 ??? Delete support for -m<cpu> for 2.9. */
289 %{sun4:} %{target:} \
290 %{mcypress:-mcpu=cypress} \
291 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
292 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
295 /* Override in target specific files. */
296 #define ASM_CPU_SPEC "\
297 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
298 %{msparclite:-Asparclite} \
299 %{mf930:-Asparclite} %{mf934:-Asparclite} \
300 %{mcpu=sparclite:-Asparclite} \
301 %{mcpu=sparclite86x:-Asparclite} \
302 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
303 %{mv8plus:-Av8plus} \
305 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
306 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
307 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
310 /* Word size selection, among other things.
311 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
313 #define ASM_ARCH32_SPEC "-32"
314 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
315 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
317 #define ASM_ARCH64_SPEC "-64"
319 #define ASM_ARCH_DEFAULT_SPEC \
320 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
322 #define ASM_ARCH_SPEC "\
323 %{m32:%(asm_arch32)} \
324 %{m64:%(asm_arch64)} \
325 %{!m32:%{!m64:%(asm_arch_default)}} \
328 #ifdef HAVE_AS_RELAX_OPTION
329 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
331 #define ASM_RELAX_SPEC ""
334 /* Special flags to the Sun-4 assembler when using pipe for input. */
337 %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
338 %(asm_cpu) %(asm_relax)"
340 /* This macro defines names of additional specifications to put in the specs
341 that can be used in various specifications like CC1_SPEC. Its definition
342 is an initializer with a subgrouping for each command option.
344 Each subgrouping contains a string constant, that defines the
345 specification name, and a string constant that used by the GNU CC driver
348 Do not define this macro if it does not need to do anything. */
350 #define EXTRA_SPECS \
351 { "cpp_cpu", CPP_CPU_SPEC }, \
352 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
353 { "cpp_arch32", CPP_ARCH32_SPEC }, \
354 { "cpp_arch64", CPP_ARCH64_SPEC }, \
355 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
356 { "cpp_arch", CPP_ARCH_SPEC }, \
357 { "cpp_endian", CPP_ENDIAN_SPEC }, \
358 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
359 { "asm_cpu", ASM_CPU_SPEC }, \
360 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
361 { "asm_arch32", ASM_ARCH32_SPEC }, \
362 { "asm_arch64", ASM_ARCH64_SPEC }, \
363 { "asm_relax", ASM_RELAX_SPEC }, \
364 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
365 { "asm_arch", ASM_ARCH_SPEC }, \
366 SUBTARGET_EXTRA_SPECS
368 #define SUBTARGET_EXTRA_SPECS
370 /* Because libgcc can generate references back to libc (via .umul etc.) we have
371 to list libc again after the second libgcc. */
372 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
376 #define NO_BUILTIN_PTRDIFF_TYPE
377 #define NO_BUILTIN_SIZE_TYPE
379 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
380 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
382 /* ??? This should be 32 bits for v9 but what can we do? */
383 #define WCHAR_TYPE "short unsigned int"
384 #define WCHAR_TYPE_SIZE 16
386 /* Show we can debug even without a frame pointer. */
387 #define CAN_DEBUG_WITHOUT_FP
389 #define OVERRIDE_OPTIONS sparc_override_options ()
391 /* Generate DBX debugging information. */
393 #define DBX_DEBUGGING_INFO
395 /* Run-time compilation parameters selecting different hardware subsets. */
397 extern int target_flags;
399 /* Nonzero if we should generate code to use the fpu. */
401 #define TARGET_FPU (target_flags & MASK_FPU)
403 /* Nonzero if we should assume that double pointers might be unaligned.
404 This can happen when linking gcc compiled code with other compilers,
405 because the ABI only guarantees 4 byte alignment. */
406 #define MASK_UNALIGNED_DOUBLES 4
407 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
409 /* Nonzero means that we should generate code for a v8 sparc. */
411 #define TARGET_V8 (target_flags & MASK_V8)
413 /* Nonzero means that we should generate code for a sparclite.
414 This enables the sparclite specific instructions, but does not affect
415 whether FPU instructions are emitted. */
416 #define MASK_SPARCLITE 0x10
417 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
419 /* Nonzero if we're compiling for the sparclet. */
420 #define MASK_SPARCLET 0x20
421 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
423 /* Nonzero if we're compiling for v9 sparc.
424 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
425 the word size is 64. */
427 #define TARGET_V9 (target_flags & MASK_V9)
429 /* Non-zero to generate code that uses the instructions deprecated in
430 the v9 architecture. This option only applies to v9 systems. */
431 /* ??? This isn't user selectable yet. It's used to enable such insns
432 on 32 bit v9 systems and for the moment they're permanently disabled
433 on 64 bit v9 systems. */
434 #define MASK_DEPRECATED_V8_INSNS 0x80
435 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
437 /* Mask of all CPU selection flags. */
439 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
441 /* Non-zero means don't pass `-assert pure-text' to the linker. */
442 #define MASK_IMPURE_TEXT 0x100
443 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
445 /* Nonzero means that we should generate code using a flat register window
446 model, i.e. no save/restore instructions are generated, which is
447 compatible with normal sparc code.
448 The frame pointer is %i7 instead of %fp. */
449 #define MASK_FLAT 0x200
450 #define TARGET_FLAT (target_flags & MASK_FLAT)
452 /* Nonzero means use the registers that the Sparc ABI reserves for
453 application software. This must be the default to coincide with the
454 setting in FIXED_REGISTERS. */
455 #define MASK_APP_REGS 0x400
456 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
458 /* Option to select how quad word floating point is implemented.
459 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
460 Otherwise, we use the SPARC ABI quad library functions. */
461 #define MASK_HARD_QUAD 0x800
462 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
464 /* Non-zero on little-endian machines. */
465 /* ??? Little endian support currently only exists for sparclet-aout and
466 sparc64-elf configurations. May eventually want to expand the support
467 to all targets, but for now it's kept local to only those two. */
468 #define MASK_LITTLE_ENDIAN 0x1000
469 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
471 /* 0x2000, 0x4000 are unused */
473 /* Nonzero if pointers are 64 bits. */
474 #define MASK_PTR64 0x8000
475 #define TARGET_PTR64 (target_flags & MASK_PTR64)
477 /* Nonzero if generating code to run in a 64 bit environment.
478 This is intended to only be used by TARGET_ARCH{32,64} as they are the
479 mechanism used to control compile time or run time selection. */
480 #define MASK_64BIT 0x10000
481 #define TARGET_64BIT (target_flags & MASK_64BIT)
483 /* 0x20000,0x40000 unused */
485 /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
486 adding 2047 to %sp. This option is for v9 only and is the default. */
487 #define MASK_STACK_BIAS 0x80000
488 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
490 /* 0x100000,0x200000 unused */
492 /* Non-zero means -m{,no-}fpu was passed on the command line. */
493 #define MASK_FPU_SET 0x400000
494 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
496 /* Use the UltraSPARC Visual Instruction Set extensions. */
497 #define MASK_VIS 0x1000000
498 #define TARGET_VIS (target_flags & MASK_VIS)
500 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
501 the current out and global registers and Linux 2.2+ as well. */
502 #define MASK_V8PLUS 0x2000000
503 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
505 /* Force a the fastest alignment on structures to take advantage of
507 #define MASK_FASTER_STRUCTS 0x4000000
508 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
510 /* Use IEEE quad long double. */
511 #define MASK_LONG_DOUBLE_128 0x8000000
512 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
514 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
515 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
516 to get high 32 bits. False in V8+ or V9 because multiply stores
517 a 64 bit result in a register. */
519 #define TARGET_HARD_MUL32 \
520 ((TARGET_V8 || TARGET_SPARCLITE \
521 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
522 && ! TARGET_V8PLUS && TARGET_ARCH32)
524 #define TARGET_HARD_MUL \
525 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
526 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
529 /* Macro to define tables used to set the flags.
530 This is a list in braces of pairs in braces,
531 each pair being { "NAME", VALUE }
532 where VALUE is the bits to set or minus the bits to clear.
533 An empty string NAME is used to identify the default VALUE. */
535 #define TARGET_SWITCHES \
536 { {"fpu", MASK_FPU | MASK_FPU_SET, \
537 N_("Use hardware fp") }, \
538 {"no-fpu", -MASK_FPU, \
539 N_("Do not use hardware fp") }, \
540 {"no-fpu", MASK_FPU_SET, NULL, }, \
541 {"hard-float", MASK_FPU | MASK_FPU_SET, \
542 N_("Use hardware fp") }, \
543 {"soft-float", -MASK_FPU, \
544 N_("Do not use hardware fp") }, \
545 {"soft-float", MASK_FPU_SET, NULL }, \
546 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
547 N_("Assume possible double misalignment") }, \
548 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
549 N_("Assume all doubles are aligned") }, \
550 {"impure-text", MASK_IMPURE_TEXT, \
551 N_("Pass -assert pure-text to linker") }, \
552 {"no-impure-text", -MASK_IMPURE_TEXT, \
553 N_("Do not pass -assert pure-text to linker") }, \
554 {"flat", MASK_FLAT, \
555 N_("Use flat register window model") }, \
556 {"no-flat", -MASK_FLAT, \
557 N_("Do not use flat register window model") }, \
558 {"app-regs", MASK_APP_REGS, \
559 N_("Use ABI reserved registers") }, \
560 {"no-app-regs", -MASK_APP_REGS, \
561 N_("Do not use ABI reserved registers") }, \
562 {"hard-quad-float", MASK_HARD_QUAD, \
563 N_("Use hardware quad fp instructions") }, \
564 {"soft-quad-float", -MASK_HARD_QUAD, \
565 N_("Do not use hardware quad fp instructions") }, \
566 {"v8plus", MASK_V8PLUS, \
567 N_("Compile for v8plus ABI") }, \
568 {"no-v8plus", -MASK_V8PLUS, \
569 N_("Do not compile for v8plus ABI") }, \
571 N_("Utilize Visual Instruction Set") }, \
572 {"no-vis", -MASK_VIS, \
573 N_("Do not utilize Visual Instruction Set") }, \
574 /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
576 N_("Optimize for Cypress processors") }, \
578 N_("Optimize for SparcLite processors") }, \
580 N_("Optimize for F930 processors") }, \
582 N_("Optimize for F934 processors") }, \
584 N_("Use V8 Sparc ISA") }, \
586 N_("Optimize for SuperSparc processors") }, \
587 /* End of deprecated options. */ \
588 {"ptr64", MASK_PTR64, \
589 N_("Pointers are 64-bit") }, \
590 {"ptr32", -MASK_PTR64, \
591 N_("Pointers are 32-bit") }, \
592 {"32", -MASK_64BIT, \
593 N_("Use 32-bit ABI") }, \
595 N_("Use 64-bit ABI") }, \
596 {"stack-bias", MASK_STACK_BIAS, \
597 N_("Use stack bias") }, \
598 {"no-stack-bias", -MASK_STACK_BIAS, \
599 N_("Do not use stack bias") }, \
600 {"faster-structs", MASK_FASTER_STRUCTS, \
601 N_("Use structs on stronger alignment for double-word copies") }, \
602 {"no-faster-structs", -MASK_FASTER_STRUCTS, \
603 N_("Do not use structs on stronger alignment for double-word copies") }, \
605 N_("Optimize tail call instructions in assembler and linker") }, \
607 N_("Do not optimize tail call instructions in assembler or linker") }, \
609 { "", TARGET_DEFAULT, ""}}
611 /* MASK_APP_REGS must always be the default because that's what
612 FIXED_REGISTERS is set to and -ffixed- is processed before
613 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
614 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
616 /* This is meant to be redefined in target specific files. */
617 #define SUBTARGET_SWITCHES
620 These must match the values for the cpu attribute in sparc.md. */
621 enum processor_type {
625 PROCESSOR_SUPERSPARC,
629 PROCESSOR_HYPERSPARC,
630 PROCESSOR_SPARCLITE86X,
634 PROCESSOR_ULTRASPARC,
635 PROCESSOR_ULTRASPARC3
638 /* This is set from -m{cpu,tune}=xxx. */
639 extern enum processor_type sparc_cpu;
641 /* Recast the cpu class to be the cpu attribute.
642 Every file includes us, but not every file includes insn-attr.h. */
643 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
645 #define TARGET_OPTIONS \
647 { "cpu=", &sparc_select[1].string, \
648 N_("Use features of and schedule code for given CPU") }, \
649 { "tune=", &sparc_select[2].string, \
650 N_("Schedule code for given CPU") }, \
651 { "cmodel=", &sparc_cmodel_string, \
652 N_("Use given Sparc code model") }, \
656 /* This is meant to be redefined in target specific files. */
657 #define SUBTARGET_OPTIONS
659 /* sparc_select[0] is reserved for the default cpu. */
660 struct sparc_cpu_select
663 const char *const name;
664 const int set_tune_p;
665 const int set_arch_p;
668 extern struct sparc_cpu_select sparc_select[];
670 /* target machine storage layout */
672 /* Define this if most significant bit is lowest numbered
673 in instructions that operate on numbered bit-fields. */
674 #define BITS_BIG_ENDIAN 1
676 /* Define this if most significant byte of a word is the lowest numbered. */
677 #define BYTES_BIG_ENDIAN 1
679 /* Define this if most significant word of a multiword number is the lowest
681 #define WORDS_BIG_ENDIAN 1
683 /* Define this to set the endianness to use in libgcc2.c, which can
684 not depend on target_flags. */
685 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
686 #define LIBGCC2_WORDS_BIG_ENDIAN 0
688 #define LIBGCC2_WORDS_BIG_ENDIAN 1
691 #define MAX_BITS_PER_WORD 64
693 /* Width of a word, in units (bytes). */
694 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
696 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
698 #define MIN_UNITS_PER_WORD 4
701 /* Now define the sizes of the C data types. */
703 #define SHORT_TYPE_SIZE 16
704 #define INT_TYPE_SIZE 32
705 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
706 #define LONG_LONG_TYPE_SIZE 64
707 #define FLOAT_TYPE_SIZE 32
708 #define DOUBLE_TYPE_SIZE 64
711 #define MAX_LONG_TYPE_SIZE 64
715 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
716 Instead, it is enabled in sol2.h, because it does work under Solaris. */
717 /* Define for support of TFmode long double.
718 Sparc ABI says that long double is 4 words. */
719 #define LONG_DOUBLE_TYPE_SIZE 128
722 /* Width in bits of a pointer.
723 See also the macro `Pmode' defined below. */
724 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
726 /* If we have to extend pointers (only when TARGET_ARCH64 and not
727 TARGET_PTR64), we want to do it unsigned. This macro does nothing
728 if ptr_mode and Pmode are the same. */
729 #define POINTERS_EXTEND_UNSIGNED 1
731 /* A macro to update MODE and UNSIGNEDP when an object whose type
732 is TYPE and which has the specified mode and signedness is to be
733 stored in a register. This macro is only called when TYPE is a
735 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
737 && GET_MODE_CLASS (MODE) == MODE_INT \
738 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
741 /* Define this macro if the promotion described by PROMOTE_MODE
742 should also be done for outgoing function arguments. */
743 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
744 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
746 #define PROMOTE_FUNCTION_ARGS
748 /* Define this macro if the promotion described by PROMOTE_MODE
749 should also be done for the return value of functions.
750 If this macro is defined, FUNCTION_VALUE must perform the same
751 promotions done by PROMOTE_MODE. */
752 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
753 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
755 #define PROMOTE_FUNCTION_RETURN
757 /* Define this macro if the promotion described by PROMOTE_MODE
758 should _only_ be performed for outgoing function arguments or
759 function return values, as specified by PROMOTE_FUNCTION_ARGS
760 and PROMOTE_FUNCTION_RETURN, respectively. */
761 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
762 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
763 for this value. For TARGET_ARCH64 we need it, as we don't have instructions
764 for arithmetic operations which do zero/sign extension at the same time,
765 so without this we end up with a srl/sra after every assignment to an
766 user variable, which means very very bad code. */
767 #define PROMOTE_FOR_CALL_ONLY
769 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
770 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
772 /* Boundary (in *bits*) on which stack pointer should be aligned. */
773 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
775 /* ALIGN FRAMES on double word boundaries */
777 #define SPARC_STACK_ALIGN(LOC) \
778 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
780 /* Allocation boundary (in *bits*) for the code of a function. */
781 #define FUNCTION_BOUNDARY 32
783 /* Alignment of field after `int : 0' in a structure. */
784 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
786 /* Every structure's size must be a multiple of this. */
787 #define STRUCTURE_SIZE_BOUNDARY 8
789 /* A bitfield declared as `int' forces `int' alignment for the struct. */
790 #define PCC_BITFIELD_TYPE_MATTERS 1
792 /* No data type wants to be aligned rounder than this. */
793 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
795 /* The best alignment to use in cases where we have a choice. */
796 #define FASTEST_ALIGNMENT 64
798 /* Define this macro as an expression for the alignment of a structure
799 (given by STRUCT as a tree node) if the alignment computed in the
800 usual way is COMPUTED and the alignment explicitly specified was
803 The default is to use SPECIFIED if it is larger; otherwise, use
804 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
805 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
806 (TARGET_FASTER_STRUCTS ? \
807 ((TREE_CODE (STRUCT) == RECORD_TYPE \
808 || TREE_CODE (STRUCT) == UNION_TYPE \
809 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
810 && TYPE_FIELDS (STRUCT) != 0 \
811 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
812 : MAX ((COMPUTED), (SPECIFIED))) \
813 : MAX ((COMPUTED), (SPECIFIED)))
815 /* Make strings word-aligned so strcpy from constants will be faster. */
816 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
817 ((TREE_CODE (EXP) == STRING_CST \
818 && (ALIGN) < FASTEST_ALIGNMENT) \
819 ? FASTEST_ALIGNMENT : (ALIGN))
821 /* Make arrays of chars word-aligned for the same reasons. */
822 #define DATA_ALIGNMENT(TYPE, ALIGN) \
823 (TREE_CODE (TYPE) == ARRAY_TYPE \
824 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
825 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
827 /* Set this nonzero if move instructions will actually fail to work
828 when given unaligned data. */
829 #define STRICT_ALIGNMENT 1
831 /* Things that must be doubleword aligned cannot go in the text section,
832 because the linker fails to align the text section enough!
833 Put them in the data section. This macro is only used in this file. */
834 #define MAX_TEXT_ALIGN 32
836 /* This forces all variables and constants to the data section when PIC.
837 This is because the SunOS 4 shared library scheme thinks everything in
838 text is a function, and patches the address to point to a loader stub. */
839 /* This is defined to zero for every system which doesn't use the a.out object
841 #ifndef SUNOS4_SHARED_LIBRARIES
842 #define SUNOS4_SHARED_LIBRARIES 0
846 /* Use text section for a constant
847 unless we need more alignment than that offers. */
848 /* This is defined differently for v9 in a cover file. */
849 #define SELECT_RTX_SECTION(MODE, X, ALIGN) \
851 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
852 && ! (flag_pic && (symbolic_operand ((X), (MODE)) || SUNOS4_SHARED_LIBRARIES))) \
858 /* Standard register usage. */
860 /* Number of actual hardware registers.
861 The hardware registers are assigned numbers for the compiler
862 from 0 to just below FIRST_PSEUDO_REGISTER.
863 All registers that the compiler knows about must be given numbers,
864 even those that are not normally considered general registers.
866 SPARC has 32 integer registers and 32 floating point registers.
867 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
868 accessible. We still account for them to simplify register computations
869 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
871 Register 100 is used as the integer condition code register.
872 Register 101 is used as the soft frame pointer register. */
874 #define FIRST_PSEUDO_REGISTER 102
876 #define SPARC_FIRST_FP_REG 32
877 /* Additional V9 fp regs. */
878 #define SPARC_FIRST_V9_FP_REG 64
879 #define SPARC_LAST_V9_FP_REG 95
880 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
881 #define SPARC_FIRST_V9_FCC_REG 96
882 #define SPARC_LAST_V9_FCC_REG 99
884 #define SPARC_FCC_REG 96
885 /* Integer CC reg. We don't distinguish %icc from %xcc. */
886 #define SPARC_ICC_REG 100
888 /* Nonzero if REGNO is an fp reg. */
889 #define SPARC_FP_REG_P(REGNO) \
890 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
892 /* Argument passing regs. */
893 #define SPARC_OUTGOING_INT_ARG_FIRST 8
894 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24)
895 #define SPARC_FP_ARG_FIRST 32
897 /* 1 for registers that have pervasive standard uses
898 and are not available for the register allocator.
901 g1 is free to use as temporary.
902 g2-g4 are reserved for applications. Gcc normally uses them as
903 temporaries, but this can be disabled via the -mno-app-regs option.
904 g5 through g7 are reserved for the operating system.
907 g1,g5 are free to use as temporaries, and are free to use between calls
908 if the call is to an external function via the PLT.
909 g4 is free to use as a temporary in the non-embedded case.
910 g4 is reserved in the embedded case.
911 g2-g3 are reserved for applications. Gcc normally uses them as
912 temporaries, but this can be disabled via the -mno-app-regs option.
913 g6-g7 are reserved for the operating system (or application in
915 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
916 currently be a fixed register until this pattern is rewritten.
917 Register 1 is also used when restoring call-preserved registers in large
920 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
921 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
924 #define FIXED_REGISTERS \
925 {1, 0, 2, 2, 2, 2, 1, 1, \
926 0, 0, 0, 0, 0, 0, 1, 0, \
927 0, 0, 0, 0, 0, 0, 0, 0, \
928 0, 0, 0, 0, 0, 0, 1, 1, \
930 0, 0, 0, 0, 0, 0, 0, 0, \
931 0, 0, 0, 0, 0, 0, 0, 0, \
932 0, 0, 0, 0, 0, 0, 0, 0, \
933 0, 0, 0, 0, 0, 0, 0, 0, \
935 0, 0, 0, 0, 0, 0, 0, 0, \
936 0, 0, 0, 0, 0, 0, 0, 0, \
937 0, 0, 0, 0, 0, 0, 0, 0, \
938 0, 0, 0, 0, 0, 0, 0, 0, \
942 /* 1 for registers not available across function calls.
943 These must include the FIXED_REGISTERS and also any
944 registers that can be used without being saved.
945 The latter must include the registers where values are returned
946 and the register where structure-value addresses are passed.
947 Aside from that, you can include as many other registers as you like. */
949 #define CALL_USED_REGISTERS \
950 {1, 1, 1, 1, 1, 1, 1, 1, \
951 1, 1, 1, 1, 1, 1, 1, 1, \
952 0, 0, 0, 0, 0, 0, 0, 0, \
953 0, 0, 0, 0, 0, 0, 1, 1, \
955 1, 1, 1, 1, 1, 1, 1, 1, \
956 1, 1, 1, 1, 1, 1, 1, 1, \
957 1, 1, 1, 1, 1, 1, 1, 1, \
958 1, 1, 1, 1, 1, 1, 1, 1, \
960 1, 1, 1, 1, 1, 1, 1, 1, \
961 1, 1, 1, 1, 1, 1, 1, 1, \
962 1, 1, 1, 1, 1, 1, 1, 1, \
963 1, 1, 1, 1, 1, 1, 1, 1, \
967 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
968 they won't be allocated. */
970 #define CONDITIONAL_REGISTER_USAGE \
973 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
975 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
976 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
978 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
979 /* then honour it. */ \
980 if (TARGET_ARCH32 && fixed_regs[5]) \
982 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
987 for (regno = SPARC_FIRST_V9_FP_REG; \
988 regno <= SPARC_LAST_V9_FP_REG; \
990 fixed_regs[regno] = 1; \
991 /* %fcc0 is used by v8 and v9. */ \
992 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
993 regno <= SPARC_LAST_V9_FCC_REG; \
995 fixed_regs[regno] = 1; \
1000 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
1001 fixed_regs[regno] = 1; \
1003 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
1004 /* then honour it. Likewise with g3 and g4. */ \
1005 if (fixed_regs[2] == 2) \
1006 fixed_regs[2] = ! TARGET_APP_REGS; \
1007 if (fixed_regs[3] == 2) \
1008 fixed_regs[3] = ! TARGET_APP_REGS; \
1009 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
1010 fixed_regs[4] = ! TARGET_APP_REGS; \
1011 else if (TARGET_CM_EMBMEDANY) \
1012 fixed_regs[4] = 1; \
1013 else if (fixed_regs[4] == 2) \
1014 fixed_regs[4] = 0; \
1017 /* Let the compiler believe the frame pointer is still \
1018 %fp, but output it as %i7. */ \
1019 fixed_regs[31] = 1; \
1020 reg_names[HARD_FRAME_POINTER_REGNUM] = "%i7"; \
1021 /* Disable leaf functions */ \
1022 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); \
1027 /* Return number of consecutive hard regs needed starting at reg REGNO
1028 to hold something of mode MODE.
1029 This is ordinarily the length in words of a value of mode MODE
1030 but can be less for certain modes in special long registers.
1032 On SPARC, ordinary registers hold 32 bits worth;
1033 this means both integer and floating point registers.
1034 On v9, integer regs hold 64 bits worth; floating point regs hold
1035 32 bits worth (this includes the new fp regs as even the odd ones are
1036 included in the hard register count). */
1038 #define HARD_REGNO_NREGS(REGNO, MODE) \
1040 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
1041 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
1042 : (GET_MODE_SIZE (MODE) + 3) / 4) \
1043 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1045 /* Due to the ARCH64 descrepancy above we must override this next
1047 #define REGMODE_NATURAL_SIZE(MODE) \
1048 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
1050 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1051 See sparc.c for how we initialize this. */
1052 extern const int *hard_regno_mode_classes;
1053 extern int sparc_mode_class[];
1055 /* ??? Because of the funny way we pass parameters we should allow certain
1056 ??? types of float/complex values to be in integer registers during
1057 ??? RTL generation. This only matters on arch32. */
1058 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1059 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
1061 /* Value is 1 if it is a good idea to tie two pseudo registers
1062 when one has mode MODE1 and one has mode MODE2.
1063 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1064 for any hard reg, then this must be 0 for correct output.
1066 For V9: SFmode can't be combined with other float modes, because they can't
1067 be allocated to the %d registers. Also, DFmode won't fit in odd %f
1068 registers, but SFmode will. */
1069 #define MODES_TIEABLE_P(MODE1, MODE2) \
1070 ((MODE1) == (MODE2) \
1071 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1073 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
1074 || (MODE1 != SFmode && MODE2 != SFmode)))))
1076 /* Specify the registers used for certain standard purposes.
1077 The values of these macros are register numbers. */
1079 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
1080 /* #define PC_REGNUM */
1082 /* Register to use for pushing function arguments. */
1083 #define STACK_POINTER_REGNUM 14
1085 /* The stack bias (amount by which the hardware register is offset by). */
1086 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
1088 /* Actual top-of-stack address is 92/176 greater than the contents of the
1089 stack pointer register for !v9/v9. That is:
1090 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
1091 address, and 6*4 bytes for the 6 register parameters.
1092 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
1094 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
1096 /* Base register for access to local variables of the function. */
1097 #define HARD_FRAME_POINTER_REGNUM 30
1099 /* The soft frame pointer does not have the stack bias applied. */
1100 #define FRAME_POINTER_REGNUM 101
1102 /* Given the stack bias, the stack pointer isn't actually aligned. */
1103 #define INIT_EXPANDERS \
1105 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
1107 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
1108 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
1112 /* Value should be nonzero if functions must have frame pointers.
1113 Zero means the frame pointer need not be set up (and parms
1114 may be accessed via the stack pointer) in functions that seem suitable.
1115 This is computed in `reload', in reload1.c.
1116 Used in flow.c, global.c, and reload1.c.
1118 Being a non-leaf function does not mean a frame pointer is needed in the
1119 flat window model. However, the debugger won't be able to backtrace through
1121 #define FRAME_POINTER_REQUIRED \
1123 ? (current_function_calls_alloca \
1124 || current_function_varargs \
1125 || !leaf_function_p ()) \
1126 : ! (leaf_function_p () && only_leaf_regs_used ()))
1128 /* Base register for access to arguments of the function. */
1129 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1131 /* Register in which static-chain is passed to a function. This must
1132 not be a register used by the prologue. */
1133 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1135 /* Register which holds offset table for position-independent
1138 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
1140 /* Pick a default value we can notice from override_options:
1142 v9: Default is off. */
1144 #define DEFAULT_PCC_STRUCT_RETURN -1
1146 /* Sparc ABI says that quad-precision floats and all structures are returned
1148 For v9: unions <= 32 bytes in size are returned in int regs,
1149 structures up to 32 bytes are returned in int and fp regs. */
1151 #define RETURN_IN_MEMORY(TYPE) \
1153 ? (TYPE_MODE (TYPE) == BLKmode \
1154 || TYPE_MODE (TYPE) == TFmode \
1155 || TYPE_MODE (TYPE) == TCmode) \
1156 : (TYPE_MODE (TYPE) == BLKmode \
1157 && (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 32))
1159 /* Functions which return large structures get the address
1160 to place the wanted value at offset 64 from the frame.
1161 Must reserve 64 bytes for the in and local registers.
1162 v9: Functions which return large structures get the address to place the
1163 wanted value from an invisible first argument. */
1164 /* Used only in other #defines in this file. */
1165 #define STRUCT_VALUE_OFFSET 64
1167 #define STRUCT_VALUE \
1170 : gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
1171 STRUCT_VALUE_OFFSET)))
1173 #define STRUCT_VALUE_INCOMING \
1176 : gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, \
1177 STRUCT_VALUE_OFFSET)))
1179 /* Define the classes of registers for register constraints in the
1180 machine description. Also define ranges of constants.
1182 One of the classes must always be named ALL_REGS and include all hard regs.
1183 If there is more than one class, another class must be named NO_REGS
1184 and contain no registers.
1186 The name GENERAL_REGS must be the name of a class (or an alias for
1187 another name such as ALL_REGS). This is the class of registers
1188 that is allowed by "g" or "r" in a register constraint.
1189 Also, registers outside this class are allocated only when
1190 instructions express preferences for them.
1192 The classes must be numbered in nondecreasing order; that is,
1193 a larger-numbered class must never be contained completely
1194 in a smaller-numbered class.
1196 For any two classes, it is very desirable that there be another
1197 class that represents their union. */
1199 /* The SPARC has various kinds of registers: general, floating point,
1200 and condition codes [well, it has others as well, but none that we
1201 care directly about].
1203 For v9 we must distinguish between the upper and lower floating point
1204 registers because the upper ones can't hold SFmode values.
1205 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1206 satisfying a group need for a class will also satisfy a single need for
1207 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1210 It is important that one class contains all the general and all the standard
1211 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1212 because reg_class_record() will bias the selection in favor of fp regs,
1213 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1214 because FP_REGS > GENERAL_REGS.
1216 It is also important that one class contain all the general and all the
1217 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1218 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1219 allocate_reload_reg() to bypass it causing an abort because the compiler
1220 thinks it doesn't have a spill reg when in fact it does.
1222 v9 also has 4 floating point condition code registers. Since we don't
1223 have a class that is the union of FPCC_REGS with either of the others,
1224 it is important that it appear first. Otherwise the compiler will die
1225 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1228 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1229 may try to use it to hold an SImode value. See register_operand.
1230 ??? Should %fcc[0123] be handled similarly?
1233 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1234 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1235 ALL_REGS, LIM_REG_CLASSES };
1237 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1239 /* Give names of register classes as strings for dump file. */
1241 #define REG_CLASS_NAMES \
1242 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1243 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1246 /* Define which registers fit in which classes.
1247 This is an initializer for a vector of HARD_REG_SET
1248 of length N_REG_CLASSES. */
1250 #define REG_CLASS_CONTENTS \
1251 {{0, 0, 0, 0}, /* NO_REGS */ \
1252 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1253 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1254 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1255 {0, -1, 0, 0}, /* FP_REGS */ \
1256 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1257 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1258 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1259 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1261 /* The same information, inverted:
1262 Return the class number of the smallest class containing
1263 reg number REGNO. This could be a conditional expression
1264 or could index an array. */
1266 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1268 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1270 /* This is the order in which to allocate registers normally.
1272 We put %f0/%f1 last among the float registers, so as to make it more
1273 likely that a pseudo-register which dies in the float return register
1274 will get allocated to the float return register, thus saving a move
1275 instruction at the end of the function. */
1277 #define REG_ALLOC_ORDER \
1278 { 8, 9, 10, 11, 12, 13, 2, 3, \
1279 15, 16, 17, 18, 19, 20, 21, 22, \
1280 23, 24, 25, 26, 27, 28, 29, 31, \
1281 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \
1282 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1283 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1284 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1285 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1286 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1287 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1288 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1289 32, 33, /* %f0,%f1 */ \
1290 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \
1291 1, 4, 5, 6, 7, 0, 14, 30, 101}
1293 /* This is the order in which to allocate registers for
1294 leaf functions. If all registers can fit in the "gi" registers,
1295 then we have the possibility of having a leaf function. */
1297 #define REG_LEAF_ALLOC_ORDER \
1298 { 2, 3, 24, 25, 26, 27, 28, 29, \
1300 15, 8, 9, 10, 11, 12, 13, \
1301 16, 17, 18, 19, 20, 21, 22, 23, \
1302 34, 35, 36, 37, 38, 39, \
1303 40, 41, 42, 43, 44, 45, 46, 47, \
1304 48, 49, 50, 51, 52, 53, 54, 55, \
1305 56, 57, 58, 59, 60, 61, 62, 63, \
1306 64, 65, 66, 67, 68, 69, 70, 71, \
1307 72, 73, 74, 75, 76, 77, 78, 79, \
1308 80, 81, 82, 83, 84, 85, 86, 87, \
1309 88, 89, 90, 91, 92, 93, 94, 95, \
1311 96, 97, 98, 99, 100, \
1314 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1316 extern char sparc_leaf_regs[];
1317 #define LEAF_REGISTERS sparc_leaf_regs
1319 extern const char leaf_reg_remap[];
1320 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1322 /* The class value for index registers, and the one for base regs. */
1323 #define INDEX_REG_CLASS GENERAL_REGS
1324 #define BASE_REG_CLASS GENERAL_REGS
1326 /* Local macro to handle the two v9 classes of FP regs. */
1327 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1329 /* Get reg_class from a letter such as appears in the machine description.
1330 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1331 .md file for v8 and v9.
1332 'd' and 'b' are used for single and double precision VIS operations,
1334 'h' is used for V8+ 64 bit global and out registers. */
1336 #define REG_CLASS_FROM_LETTER(C) \
1338 ? ((C) == 'f' ? FP_REGS \
1339 : (C) == 'e' ? EXTRA_FP_REGS \
1340 : (C) == 'c' ? FPCC_REGS \
1341 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1342 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1343 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1345 : ((C) == 'f' ? FP_REGS \
1346 : (C) == 'e' ? FP_REGS \
1347 : (C) == 'c' ? FPCC_REGS \
1350 /* The letters I, J, K, L and M in a register constraint string
1351 can be used to stand for particular ranges of immediate operands.
1352 This macro defines what the ranges are.
1353 C is the letter, and VALUE is a constant value.
1354 Return 1 if VALUE is in the range specified by C.
1356 `I' is used for the range of constants an insn can actually contain.
1357 `J' is used for the range which is just zero (since that is R0).
1358 `K' is used for constants which can be loaded with a single sethi insn.
1359 `L' is used for the range of constants supported by the movcc insns.
1360 `M' is used for the range of constants supported by the movrcc insns.
1361 `N' is like K, but for constants wider than 32 bits. */
1363 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1364 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1365 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1366 /* 10 and 11 bit immediates are only used for a few specific insns.
1367 SMALL_INT is used throughout the port so we continue to use it. */
1368 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1369 /* 13 bit immediate, considering only the low 32 bits */
1370 #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
1371 (INTVAL (X), SImode)))
1372 #define SPARC_SETHI_P(X) \
1373 (((unsigned HOST_WIDE_INT) (X) \
1374 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1375 #define SPARC_SETHI32_P(X) \
1376 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1378 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1379 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1380 : (C) == 'J' ? (VALUE) == 0 \
1381 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1382 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1383 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1384 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1387 /* Similar, but for floating constants, and defining letters G and H.
1388 Here VALUE is the CONST_DOUBLE rtx itself. */
1390 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1391 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1392 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1395 /* Given an rtx X being reloaded into a reg required to be
1396 in class CLASS, return the class of reg to actually use.
1397 In general this is just CLASS; but on some machines
1398 in some cases it is preferable to use a more restrictive class. */
1399 /* - We can't load constants into FP registers.
1400 - We can't load FP constants into integer registers when soft-float,
1401 because there is no soft-float pattern with a r/F constraint.
1402 - We can't load FP constants into integer registers for TFmode unless
1403 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1404 - Try and reload integer constants (symbolic or otherwise) back into
1405 registers directly, rather than having them dumped to memory. */
1407 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1409 ? ((FP_REG_CLASS_P (CLASS) \
1410 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1412 || (GET_MODE (X) == TFmode \
1413 && ! fp_zero_operand (X, TFmode))) \
1415 : (!FP_REG_CLASS_P (CLASS) \
1416 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1421 /* Return the register class of a scratch register needed to load IN into
1422 a register of class CLASS in MODE.
1424 We need a temporary when loading/storing a HImode/QImode value
1425 between memory and the FPU registers. This can happen when combine puts
1426 a paradoxical subreg in a float/fix conversion insn. */
1428 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1429 ((FP_REG_CLASS_P (CLASS) \
1430 && ((MODE) == HImode || (MODE) == QImode) \
1431 && (GET_CODE (IN) == MEM \
1432 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1433 && true_regnum (IN) == -1))) \
1435 : (((TARGET_CM_MEDANY \
1436 && symbolic_operand ((IN), (MODE))) \
1437 || (TARGET_CM_EMBMEDANY \
1438 && text_segment_operand ((IN), (MODE)))) \
1443 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1444 ((FP_REG_CLASS_P (CLASS) \
1445 && ((MODE) == HImode || (MODE) == QImode) \
1446 && (GET_CODE (IN) == MEM \
1447 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1448 && true_regnum (IN) == -1))) \
1450 : (((TARGET_CM_MEDANY \
1451 && symbolic_operand ((IN), (MODE))) \
1452 || (TARGET_CM_EMBMEDANY \
1453 && text_segment_operand ((IN), (MODE)))) \
1458 /* On SPARC it is not possible to directly move data between
1459 GENERAL_REGS and FP_REGS. */
1460 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1461 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1463 /* Return the stack location to use for secondary memory needed reloads.
1464 We want to use the reserved location just below the frame pointer.
1465 However, we must ensure that there is a frame, so use assign_stack_local
1466 if the frame size is zero. */
1467 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1468 (get_frame_size () == 0 \
1469 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1470 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1471 STARTING_FRAME_OFFSET)))
1473 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1474 because the movsi and movsf patterns don't handle r/f moves.
1475 For v8 we copy the default definition. */
1476 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1478 ? (GET_MODE_BITSIZE (MODE) < 32 \
1479 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1481 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1482 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1485 /* Return the maximum number of consecutive registers
1486 needed to represent mode MODE in a register of class CLASS. */
1487 /* On SPARC, this is the size of MODE in words. */
1488 #define CLASS_MAX_NREGS(CLASS, MODE) \
1489 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1490 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1492 /* Stack layout; function entry, exit and calling. */
1494 /* Define the number of register that can hold parameters.
1495 This macro is only used in other macro definitions below and in sparc.c.
1496 MODE is the mode of the argument.
1497 !v9: All args are passed in %o0-%o5.
1498 v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values.
1499 See the description in sparc.c. */
1500 #define NPARM_REGS(MODE) \
1502 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \
1505 /* Define this if pushing a word on the stack
1506 makes the stack pointer a smaller address. */
1507 #define STACK_GROWS_DOWNWARD
1509 /* Define this if the nominal address of the stack frame
1510 is at the high-address end of the local variables;
1511 that is, each additional local variable allocated
1512 goes at a more negative offset in the frame. */
1513 #define FRAME_GROWS_DOWNWARD
1515 /* Offset within stack frame to start allocating local variables at.
1516 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1517 first local allocated. Otherwise, it is the offset to the BEGINNING
1518 of the first local allocated. */
1519 /* This allows space for one TFmode floating point value. */
1520 #define STARTING_FRAME_OFFSET \
1521 (TARGET_ARCH64 ? -16 \
1522 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1524 /* If we generate an insn to push BYTES bytes,
1525 this says how many the stack pointer really advances by.
1526 On SPARC, don't define this because there are no push insns. */
1527 /* #define PUSH_ROUNDING(BYTES) */
1529 /* Offset of first parameter from the argument pointer register value.
1530 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1531 even if this function isn't going to use it.
1532 v9: This is 128 for the ins and locals. */
1533 #define FIRST_PARM_OFFSET(FNDECL) \
1534 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1536 /* Offset from the argument pointer register value to the CFA.
1537 This is different from FIRST_PARM_OFFSET because the register window
1538 comes between the CFA and the arguments. */
1539 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1541 /* When a parameter is passed in a register, stack space is still
1543 !v9: All 6 possible integer registers have backing store allocated.
1544 v9: Only space for the arguments passed is allocated. */
1545 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1546 meaning to the backend. Further, we need to be able to detect if a
1547 varargs/unprototyped function is called, as they may want to spill more
1548 registers than we've provided space. Ugly, ugly. So for now we retain
1549 all 6 slots even for v9. */
1550 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1552 /* Definitions for register elimination. */
1553 /* ??? In TARGET_FLAT mode we needn't have a hard frame pointer. */
1555 #define ELIMINABLE_REGS \
1556 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1557 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1559 /* The way this is structured, we can't eliminate SFP in favor of SP
1560 if the frame pointer is required: we want to use the SFP->HFP elimination
1561 in that case. But the test in update_eliminables doesn't know we are
1562 assuming below that we only do the former elimination. */
1563 #define CAN_ELIMINATE(FROM, TO) \
1564 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
1566 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1569 if ((TO) == STACK_POINTER_REGNUM) \
1571 /* Note, we always pretend that this is a leaf function \
1572 because if it's not, there's no point in trying to \
1573 eliminate the frame pointer. If it is a leaf \
1574 function, we guessed right! */ \
1577 sparc_flat_compute_frame_size (get_frame_size ()); \
1579 (OFFSET) = compute_frame_size (get_frame_size (), 1); \
1581 (OFFSET) += SPARC_STACK_BIAS; \
1584 /* Keep the stack pointer constant throughout the function.
1585 This is both an optimization and a necessity: longjmp
1586 doesn't behave itself when the stack pointer moves within
1588 #define ACCUMULATE_OUTGOING_ARGS 1
1590 /* Value is the number of bytes of arguments automatically
1591 popped when returning from a subroutine call.
1592 FUNDECL is the declaration node of the function (as a tree),
1593 FUNTYPE is the data type of the function (as a tree),
1594 or for a library call it is an identifier node for the subroutine name.
1595 SIZE is the number of bytes of arguments passed on the stack. */
1597 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1599 /* Some subroutine macros specific to this machine.
1600 When !TARGET_FPU, put float return values in the general registers,
1601 since we don't have any fp registers. */
1602 #define BASE_RETURN_VALUE_REG(MODE) \
1604 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1605 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1607 #define BASE_OUTGOING_VALUE_REG(MODE) \
1609 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1610 : TARGET_FLAT ? 8 : 24) \
1611 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1612 : (TARGET_FLAT ? 8 : 24)))
1614 #define BASE_PASSING_ARG_REG(MODE) \
1616 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1619 /* ??? FIXME -- seems wrong for v9 structure passing... */
1620 #define BASE_INCOMING_ARG_REG(MODE) \
1622 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1623 : TARGET_FLAT ? 8 : 24) \
1624 : (TARGET_FLAT ? 8 : 24))
1626 /* Define this macro if the target machine has "register windows". This
1627 C expression returns the register number as seen by the called function
1628 corresponding to register number OUT as seen by the calling function.
1629 Return OUT if register number OUT is not an outbound register. */
1631 #define INCOMING_REGNO(OUT) \
1632 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1634 /* Define this macro if the target machine has "register windows". This
1635 C expression returns the register number as seen by the calling function
1636 corresponding to register number IN as seen by the called function.
1637 Return IN if register number IN is not an inbound register. */
1639 #define OUTGOING_REGNO(IN) \
1640 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1642 /* Define this macro if the target machine has register windows. This
1643 C expression returns true if the register is call-saved but is in the
1646 #define LOCAL_REGNO(REGNO) \
1647 (TARGET_FLAT ? 0 : (REGNO) >= 16 && (REGNO) <= 31)
1649 /* Define how to find the value returned by a function.
1650 VALTYPE is the data type of the value (as a tree).
1651 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1652 otherwise, FUNC is 0. */
1654 /* On SPARC the value is found in the first "output" register. */
1656 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1657 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1659 /* But the called function leaves it in the first "input" register. */
1661 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1662 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1664 /* Define how to find the value returned by a library function
1665 assuming the value has mode MODE. */
1667 #define LIBCALL_VALUE(MODE) \
1668 function_value (NULL_TREE, (MODE), 1)
1670 /* 1 if N is a possible register number for a function value
1671 as seen by the caller.
1672 On SPARC, the first "output" reg is used for integer values,
1673 and the first floating point register is used for floating point values. */
1675 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1677 /* Define the size of space to allocate for the return value of an
1680 #define APPLY_RESULT_SIZE 16
1682 /* 1 if N is a possible register number for function argument passing.
1683 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1685 #define FUNCTION_ARG_REGNO_P(N) \
1687 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1688 : ((N) >= 8 && (N) <= 13))
1690 /* Define a data type for recording info about an argument list
1691 during the scan of that argument list. This data type should
1692 hold all necessary information about the function itself
1693 and about the args processed so far, enough to enable macros
1694 such as FUNCTION_ARG to determine where the next arg should go.
1696 On SPARC (!v9), this is a single integer, which is a number of words
1697 of arguments scanned so far (including the invisible argument,
1698 if any, which holds the structure-value-address).
1699 Thus 7 or more means all following args should go on the stack.
1701 For v9, we also need to know whether a prototype is present. */
1704 int words; /* number of words passed so far */
1705 int prototype_p; /* non-zero if a prototype is present */
1706 int libcall_p; /* non-zero if a library call */
1708 #define CUMULATIVE_ARGS struct sparc_args
1710 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1711 for a call to a function whose data type is FNTYPE.
1712 For a library call, FNTYPE is 0. */
1714 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1715 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (INDIRECT));
1717 /* Update the data in CUM to advance over an argument
1718 of mode MODE and data type TYPE.
1719 TYPE is null for libcalls where that information may not be available. */
1721 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1722 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1724 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1726 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1728 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1729 || TREE_ADDRESSABLE (TYPE)))
1731 /* Determine where to put an argument to a function.
1732 Value is zero to push the argument on the stack,
1733 or a hard register in which to store the argument.
1735 MODE is the argument's machine mode.
1736 TYPE is the data type of the argument (as a tree).
1737 This is null for libcalls where that information may
1739 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1740 the preceding args and about the function being called.
1741 NAMED is nonzero if this argument is a named parameter
1742 (otherwise it is an extra parameter matching an ellipsis). */
1744 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1745 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1747 /* Define where a function finds its arguments.
1748 This is different from FUNCTION_ARG because of register windows. */
1750 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1751 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1753 /* For an arg passed partly in registers and partly in memory,
1754 this is the number of registers used.
1755 For args passed entirely in registers or entirely in memory, zero. */
1757 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1758 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
1760 /* A C expression that indicates when an argument must be passed by reference.
1761 If nonzero for an argument, a copy of that argument is made in memory and a
1762 pointer to the argument is passed instead of the argument itself.
1763 The pointer is passed in whatever way is appropriate for passing a pointer
1766 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1767 function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1769 /* If defined, a C expression which determines whether, and in which direction,
1770 to pad out an argument with extra space. The value should be of type
1771 `enum direction': either `upward' to pad above the argument,
1772 `downward' to pad below, or `none' to inhibit padding. */
1774 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1775 function_arg_padding ((MODE), (TYPE))
1777 /* If defined, a C expression that gives the alignment boundary, in bits,
1778 of an argument with the specified mode and type. If it is not defined,
1779 PARM_BOUNDARY is used for all arguments.
1780 For sparc64, objects requiring 16 byte alignment are passed that way. */
1782 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1784 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1785 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1786 ? 128 : PARM_BOUNDARY)
1788 /* Define the information needed to generate branch and scc insns. This is
1789 stored from the compare operation. Note that we can't use "rtx" here
1790 since it hasn't been defined! */
1792 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
1795 /* Generate the special assembly code needed to tell the assembler whatever
1796 it might need to know about the return value of a function.
1798 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
1799 information to the assembler relating to peephole optimization (done in
1802 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1803 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1805 /* Output the special assembly code needed to tell the assembler some
1806 register is used as global register variable.
1808 SPARC 64bit psABI declares registers %g2 and %g3 as application
1809 registers and %g6 and %g7 as OS registers. Any object using them
1810 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1811 and how they are used (scratch or some global variable).
1812 Linker will then refuse to link together objects which use those
1813 registers incompatibly.
1815 Unless the registers are used for scratch, two different global
1816 registers cannot be declared to the same name, so in the unlikely
1817 case of a global register variable occupying more than one register
1818 we prefix the second and following registers with .gnu.part1. etc. */
1820 extern char sparc_hard_reg_printed[8];
1822 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1823 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1825 if (TARGET_ARCH64) \
1827 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1829 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1830 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1832 if (reg == (REGNO)) \
1833 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1835 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1836 reg, reg - (REGNO), (NAME)); \
1837 sparc_hard_reg_printed[reg] = 1; \
1844 /* Emit rtl for profiling. */
1845 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1847 /* All the work done in PROFILE_HOOK, but still required. */
1848 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1850 /* Set the name of the mcount function for the system. */
1851 #define MCOUNT_FUNCTION "*mcount"
1853 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1854 the stack pointer does not matter. The value is tested only in
1855 functions that have frame pointers.
1856 No definition is equivalent to always zero. */
1858 #define EXIT_IGNORE_STACK \
1859 (get_frame_size () != 0 \
1860 || current_function_calls_alloca || current_function_outgoing_args_size)
1862 #define DELAY_SLOTS_FOR_EPILOGUE \
1863 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
1864 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
1865 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
1866 : eligible_for_epilogue_delay (trial, slots_filled))
1868 /* Define registers used by the epilogue and return instruction. */
1869 #define EPILOGUE_USES(REGNO) \
1870 (!TARGET_FLAT && REGNO == 31)
1872 /* Length in units of the trampoline for entering a nested function. */
1874 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1876 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1878 /* Emit RTL insns to initialize the variable parts of a trampoline.
1879 FNADDR is an RTX for the address of the function's pure code.
1880 CXT is an RTX for the static chain value for the function. */
1882 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1883 if (TARGET_ARCH64) \
1884 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1886 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1888 /* Generate necessary RTL for __builtin_saveregs(). */
1890 #define EXPAND_BUILTIN_SAVEREGS() sparc_builtin_saveregs ()
1892 /* Implement `va_start' for varargs and stdarg. */
1893 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1894 sparc_va_start (stdarg, valist, nextarg)
1896 /* Implement `va_arg'. */
1897 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1898 sparc_va_arg (valist, type)
1900 /* Define this macro if the location where a function argument is passed
1901 depends on whether or not it is a named argument.
1903 This macro controls how the NAMED argument to FUNCTION_ARG
1904 is set for varargs and stdarg functions. With this macro defined,
1905 the NAMED argument is always true for named arguments, and false for
1906 unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS
1907 is defined, then all arguments are treated as named. Otherwise, all named
1908 arguments except the last are treated as named.
1909 For the v9 we want NAMED to mean what it says it means. */
1911 #define STRICT_ARGUMENT_NAMING TARGET_V9
1913 /* We do not allow sibling calls if -mflat, nor
1914 we do not allow indirect calls to be optimized into sibling calls.
1916 Also, on sparc 32-bit we cannot emit a sibling call when the
1917 current function returns a structure. This is because the "unimp
1918 after call" convention would cause the callee to return to the
1919 wrong place. The generic code already disallows cases where the
1920 function being called returns a structure.
1922 It may seem strange how this last case could occur. Usually there
1923 is code after the call which jumps to epilogue code which dumps the
1924 return value into the struct return area. That ought to invalidate
1925 the sibling call right? Well, in the c++ case we can end up passing
1926 the pointer to the struct return area to a constructor (which returns
1927 void) and then nothing else happens. Such a sibling call would look
1928 valid without the added check here. */
1929 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1932 && (TARGET_ARCH64 || ! current_function_returns_struct))
1934 /* Generate RTL to flush the register windows so as to make arbitrary frames
1936 #define SETUP_FRAME_ADDRESSES() \
1937 emit_insn (gen_flush_register_windows ())
1939 /* Given an rtx for the address of a frame,
1940 return an rtx for the address of the word in the frame
1941 that holds the dynamic chain--the previous frame's address.
1942 ??? -mflat support? */
1943 #define DYNAMIC_CHAIN_ADDRESS(frame) plus_constant (frame, 14 * UNITS_PER_WORD)
1945 /* The return address isn't on the stack, it is in a register, so we can't
1946 access it from the current frame pointer. We can access it from the
1947 previous frame pointer though by reading a value from the register window
1949 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1951 /* This is the offset of the return address to the true next instruction to be
1952 executed for the current function. */
1953 #define RETURN_ADDR_OFFSET \
1954 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
1956 /* The current return address is in %i7. The return address of anything
1957 farther back is in the register window save area at [%fp+60]. */
1958 /* ??? This ignores the fact that the actual return address is +8 for normal
1959 returns, and +12 for structure returns. */
1960 #define RETURN_ADDR_RTX(count, frame) \
1962 ? gen_rtx_REG (Pmode, 31) \
1963 : gen_rtx_MEM (Pmode, \
1964 memory_address (Pmode, plus_constant (frame, \
1965 15 * UNITS_PER_WORD \
1966 + SPARC_STACK_BIAS))))
1968 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1969 +12, but always using +8 is close enough for frame unwind purposes.
1970 Actually, just using %o7 is close enough for unwinding, but %o7+8
1971 is something you can return to. */
1972 #define INCOMING_RETURN_ADDR_RTX \
1973 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1974 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1976 /* The offset from the incoming value of %sp to the top of the stack frame
1977 for the current function. On sparc64, we have to account for the stack
1979 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1981 /* Describe how we implement __builtin_eh_return. */
1982 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1983 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1984 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1986 /* Select a format to encode pointers in exception handling data. CODE
1987 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1988 true if the symbol may be affected by dynamic relocations.
1990 If assembler and linker properly support .uaword %r_disp32(foo),
1991 then use PC relative 32-bit relocations instead of absolute relocs
1992 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1993 for binaries, to save memory.
1995 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1996 symbol %r_disp32() is against was not local, but .hidden. In that
1997 case, we have to use DW_EH_PE_absptr for pic personality. */
1998 #ifdef HAVE_AS_SPARC_UA_PCREL
1999 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
2000 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2002 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2003 : ((TARGET_ARCH64 && ! GLOBAL) \
2004 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
2007 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2009 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
2010 : ((TARGET_ARCH64 && ! GLOBAL) \
2011 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
2015 /* Emit a PC-relative relocation. */
2016 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
2018 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2019 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
2020 assemble_name (FILE, LABEL); \
2021 fputc (')', FILE); \
2025 /* Addressing modes, and classification of registers for them. */
2027 /* #define HAVE_POST_INCREMENT 0 */
2028 /* #define HAVE_POST_DECREMENT 0 */
2030 /* #define HAVE_PRE_DECREMENT 0 */
2031 /* #define HAVE_PRE_INCREMENT 0 */
2033 /* Macros to check register numbers against specific register classes. */
2035 /* These assume that REGNO is a hard or pseudo reg number.
2036 They give nonzero only if REGNO is a hard reg of the suitable class
2037 or a pseudo reg currently allocated to a suitable hard reg.
2038 Since they use reg_renumber, they are safe only once reg_renumber
2039 has been allocated, which happens in local-alloc.c. */
2041 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2042 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
2043 || (REGNO) == FRAME_POINTER_REGNUM \
2044 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
2046 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
2048 #define REGNO_OK_FOR_FP_P(REGNO) \
2049 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
2050 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
2051 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2053 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
2054 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
2056 /* Now macros that check whether X is a register and also,
2057 strictly, whether it is in a specified class.
2059 These macros are specific to the SPARC, and may be used only
2060 in code for printing assembler insns and in conditions for
2061 define_optimization. */
2063 /* 1 if X is an fp register. */
2065 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2067 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
2068 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
2070 /* Maximum number of registers that can appear in a valid memory address. */
2072 #define MAX_REGS_PER_ADDRESS 2
2074 /* Recognize any constant value that is a valid address.
2075 When PIC, we do not accept an address that would require a scratch reg
2076 to load into a register. */
2078 #define CONSTANT_ADDRESS_P(X) \
2079 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2080 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2081 || (GET_CODE (X) == CONST \
2082 && ! (flag_pic && pic_address_needs_scratch (X))))
2084 /* Define this, so that when PIC, reload won't try to reload invalid
2085 addresses which require two reload registers. */
2087 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2089 /* Nonzero if the constant value X is a legitimate general operand.
2090 Anything can be made to work except floating point constants.
2091 If TARGET_VIS, 0.0 can be made to work as well. */
2093 #define LEGITIMATE_CONSTANT_P(X) \
2094 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || \
2096 (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode || \
2097 GET_MODE (X) == TFmode) && \
2098 fp_zero_operand (X, GET_MODE (X))))
2100 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2101 and check its validity for a certain class.
2102 We have two alternate definitions for each of them.
2103 The usual definition accepts all pseudo regs; the other rejects
2104 them unless they have been allocated suitable hard regs.
2105 The symbol REG_OK_STRICT causes the latter definition to be used.
2107 Most source files want to accept pseudo regs in the hope that
2108 they will get allocated to the class that the insn wants them to be in.
2109 Source files for reload pass need to be strict.
2110 After reload, it makes no difference, since pseudo regs have
2111 been eliminated by then. */
2113 /* Optional extra constraints for this machine.
2115 'Q' handles floating point constants which can be moved into
2116 an integer register with a single sethi instruction.
2118 'R' handles floating point constants which can be moved into
2119 an integer register with a single mov instruction.
2121 'S' handles floating point constants which can be moved into
2122 an integer register using a high/lo_sum sequence.
2124 'T' handles memory addresses where the alignment is known to
2125 be at least 8 bytes.
2127 `U' handles all pseudo registers or a hard even numbered
2128 integer register, needed for ldd/std instructions.
2130 'W' handles the memory operand when moving operands in/out
2131 of 'e' constraint floating point registers. */
2133 #ifndef REG_OK_STRICT
2135 /* Nonzero if X is a hard reg that can be used as an index
2136 or if it is a pseudo reg. */
2137 #define REG_OK_FOR_INDEX_P(X) \
2139 || REGNO (X) == FRAME_POINTER_REGNUM \
2140 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2142 /* Nonzero if X is a hard reg that can be used as a base reg
2143 or if it is a pseudo reg. */
2144 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
2146 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
2147 'W' is like 'T' but is assumed true on arch64.
2149 Remember to accept pseudo-registers for memory constraints if reload is
2152 #define EXTRA_CONSTRAINT(OP, C) \
2153 sparc_extra_constraint_check(OP, C, 0)
2157 /* Nonzero if X is a hard reg that can be used as an index. */
2158 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2159 /* Nonzero if X is a hard reg that can be used as a base reg. */
2160 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2162 #define EXTRA_CONSTRAINT(OP, C) \
2163 sparc_extra_constraint_check(OP, C, 1)
2167 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
2169 #ifdef HAVE_AS_OFFSETABLE_LO10
2170 #define USE_AS_OFFSETABLE_LO10 1
2172 #define USE_AS_OFFSETABLE_LO10 0
2175 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2176 that is a valid memory address for an instruction.
2177 The MODE argument is the machine mode for the MEM expression
2178 that wants to use this address.
2180 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2181 ordinarily. This changes a bit when generating PIC.
2183 If you change this, execute "rm explow.o recog.o reload.o". */
2185 #define RTX_OK_FOR_BASE_P(X) \
2186 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2187 || (GET_CODE (X) == SUBREG \
2188 && GET_CODE (SUBREG_REG (X)) == REG \
2189 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2191 #define RTX_OK_FOR_INDEX_P(X) \
2192 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2193 || (GET_CODE (X) == SUBREG \
2194 && GET_CODE (SUBREG_REG (X)) == REG \
2195 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2197 #define RTX_OK_FOR_OFFSET_P(X) \
2198 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
2200 #define RTX_OK_FOR_OLO10_P(X) \
2201 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
2203 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2204 { if (RTX_OK_FOR_BASE_P (X)) \
2206 else if (GET_CODE (X) == PLUS) \
2208 register rtx op0 = XEXP (X, 0); \
2209 register rtx op1 = XEXP (X, 1); \
2210 if (flag_pic && op0 == pic_offset_table_rtx) \
2212 if (RTX_OK_FOR_BASE_P (op1)) \
2214 else if (flag_pic == 1 \
2215 && GET_CODE (op1) != REG \
2216 && GET_CODE (op1) != LO_SUM \
2217 && GET_CODE (op1) != MEM \
2218 && (GET_CODE (op1) != CONST_INT \
2219 || SMALL_INT (op1))) \
2222 else if (RTX_OK_FOR_BASE_P (op0)) \
2224 if ((RTX_OK_FOR_INDEX_P (op1) \
2225 /* We prohibit REG + REG for TFmode when \
2226 there are no instructions which accept \
2227 REG+REG instructions. We do this \
2228 because REG+REG is not an offsetable \
2229 address. If we get the situation \
2230 in reload where source and destination \
2231 of a movtf pattern are both MEMs with \
2232 REG+REG address, then only one of them \
2233 gets converted to an offsetable \
2235 && (MODE != TFmode \
2236 || (TARGET_FPU && TARGET_ARCH64 \
2238 && TARGET_HARD_QUAD)) \
2239 /* We prohibit REG + REG on ARCH32 if \
2240 not optimizing for DFmode/DImode \
2241 because then mem_min_alignment is \
2242 likely to be zero after reload and the \
2243 forced split would lack a matching \
2244 splitter pattern. */ \
2245 && (TARGET_ARCH64 || optimize \
2246 || (MODE != DFmode \
2247 && MODE != DImode))) \
2248 || RTX_OK_FOR_OFFSET_P (op1)) \
2251 else if (RTX_OK_FOR_BASE_P (op1)) \
2253 if ((RTX_OK_FOR_INDEX_P (op0) \
2254 /* See the previous comment. */ \
2255 && (MODE != TFmode \
2256 || (TARGET_FPU && TARGET_ARCH64 \
2258 && TARGET_HARD_QUAD)) \
2259 && (TARGET_ARCH64 || optimize \
2260 || (MODE != DFmode \
2261 && MODE != DImode))) \
2262 || RTX_OK_FOR_OFFSET_P (op0)) \
2265 else if (USE_AS_OFFSETABLE_LO10 \
2266 && GET_CODE (op0) == LO_SUM \
2268 && ! TARGET_CM_MEDMID \
2269 && RTX_OK_FOR_OLO10_P (op1)) \
2271 register rtx op00 = XEXP (op0, 0); \
2272 register rtx op01 = XEXP (op0, 1); \
2273 if (RTX_OK_FOR_BASE_P (op00) \
2274 && CONSTANT_P (op01)) \
2277 else if (USE_AS_OFFSETABLE_LO10 \
2278 && GET_CODE (op1) == LO_SUM \
2280 && ! TARGET_CM_MEDMID \
2281 && RTX_OK_FOR_OLO10_P (op0)) \
2283 register rtx op10 = XEXP (op1, 0); \
2284 register rtx op11 = XEXP (op1, 1); \
2285 if (RTX_OK_FOR_BASE_P (op10) \
2286 && CONSTANT_P (op11)) \
2290 else if (GET_CODE (X) == LO_SUM) \
2292 register rtx op0 = XEXP (X, 0); \
2293 register rtx op1 = XEXP (X, 1); \
2294 if (RTX_OK_FOR_BASE_P (op0) \
2295 && CONSTANT_P (op1) \
2296 /* We can't allow TFmode, because an offset \
2297 greater than or equal to the alignment (8) \
2298 may cause the LO_SUM to overflow if !v9. */\
2299 && (MODE != TFmode || TARGET_V9)) \
2302 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
2306 /* Try machine-dependent ways of modifying an illegitimate address
2307 to be legitimate. If we find one, return the new, valid address.
2308 This macro is used in only one place: `memory_address' in explow.c.
2310 OLDX is the address as it was before break_out_memory_refs was called.
2311 In some cases it is useful to look at this to decide what needs to be done.
2313 MODE and WIN are passed so that this macro can use
2314 GO_IF_LEGITIMATE_ADDRESS.
2316 It is always safe for this macro to do nothing. It exists to recognize
2317 opportunities to optimize the output. */
2319 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2320 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2321 { rtx sparc_x = (X); \
2322 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
2323 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2324 force_operand (XEXP (X, 0), NULL_RTX)); \
2325 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
2326 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2327 force_operand (XEXP (X, 1), NULL_RTX)); \
2328 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
2329 (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
2331 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
2332 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2333 force_operand (XEXP (X, 1), NULL_RTX)); \
2334 if (sparc_x != (X) && memory_address_p (MODE, X)) \
2336 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
2337 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
2338 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2339 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
2340 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
2341 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2342 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
2343 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
2344 || GET_CODE (X) == LABEL_REF) \
2345 (X) = copy_to_suggested_reg (X, NULL_RTX, Pmode); \
2346 if (memory_address_p (MODE, X)) \
2349 /* Try a machine-dependent way of reloading an illegitimate address
2350 operand. If we find one, push the reload and jump to WIN. This
2351 macro is used in only one place: `find_reloads_address' in reload.c.
2353 For Sparc 32, we wish to handle addresses by splitting them into
2354 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2355 This cuts the number of extra insns by one.
2357 Do nothing when generating PIC code and the address is a
2358 symbolic operand or requires a scratch register. */
2360 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2362 /* Decompose SImode constants into hi+lo_sum. We do have to \
2363 rerecognize what we produce, so be careful. */ \
2364 if (CONSTANT_P (X) \
2365 && (MODE != TFmode || TARGET_ARCH64) \
2366 && GET_MODE (X) == SImode \
2367 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2369 && (symbolic_operand (X, Pmode) \
2370 || pic_address_needs_scratch (X))) \
2371 && sparc_cmodel <= CM_MEDLOW) \
2373 X = gen_rtx_LO_SUM (GET_MODE (X), \
2374 gen_rtx_HIGH (GET_MODE (X), X), X); \
2375 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2376 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2380 /* ??? 64-bit reloads. */ \
2383 /* Go to LABEL if ADDR (a legitimate address expression)
2384 has an effect that depends on the machine mode it is used for.
2385 On the SPARC this is never true. */
2387 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2389 /* If we are referencing a function make the SYMBOL_REF special.
2390 In the Embedded Medium/Anywhere code model, %g4 points to the data segment
2391 so we must not add it to function addresses. */
2393 #define ENCODE_SECTION_INFO(DECL, FIRST) \
2395 if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
2396 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2399 /* Specify the machine mode that this machine uses
2400 for the index in the tablejump instruction. */
2401 /* If we ever implement any of the full models (such as CM_FULLANY),
2402 this has to be DImode in that case */
2403 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2404 #define CASE_VECTOR_MODE \
2405 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2407 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2408 we have to sign extend which slows things down. */
2409 #define CASE_VECTOR_MODE \
2410 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2413 /* Define as C expression which evaluates to nonzero if the tablejump
2414 instruction expects the table to contain offsets from the address of the
2416 Do not define this if the table should contain absolute addresses. */
2417 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2419 /* Define this as 1 if `char' should by default be signed; else as 0. */
2420 #define DEFAULT_SIGNED_CHAR 1
2422 /* Max number of bytes we can move from memory to memory
2423 in one reasonably fast instruction. */
2426 #if 0 /* Sun 4 has matherr, so this is no good. */
2427 /* This is the value of the error code EDOM for this machine,
2428 used by the sqrt instruction. */
2429 #define TARGET_EDOM 33
2431 /* This is how to refer to the variable errno. */
2432 #define GEN_ERRNO_RTX \
2433 gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno"))
2436 /* Define if operations between registers always perform the operation
2437 on the full register even if a narrower mode is specified. */
2438 #define WORD_REGISTER_OPERATIONS
2440 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2441 will either zero-extend or sign-extend. The value of this macro should
2442 be the code that says which one of the two operations is implicitly
2443 done, NIL if none. */
2444 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2446 /* Nonzero if access to memory by bytes is slow and undesirable.
2447 For RISC chips, it means that access to memory by bytes is no
2448 better than access by words when possible, so grab a whole word
2449 and maybe make use of that. */
2450 #define SLOW_BYTE_ACCESS 1
2452 /* We assume that the store-condition-codes instructions store 0 for false
2453 and some other value for true. This is the value stored for true. */
2455 #define STORE_FLAG_VALUE 1
2457 /* When a prototype says `char' or `short', really pass an `int'. */
2458 #define PROMOTE_PROTOTYPES (TARGET_ARCH32)
2460 /* Define this to be nonzero if shift instructions ignore all but the low-order
2462 #define SHIFT_COUNT_TRUNCATED 1
2464 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2465 is done just by pretending it is already truncated. */
2466 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2468 /* Specify the machine mode that pointers have.
2469 After generation of rtl, the compiler makes no further distinction
2470 between pointers and any other objects of this machine mode. */
2471 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2473 /* Generate calls to memcpy, memcmp and memset. */
2474 #define TARGET_MEM_FUNCTIONS
2476 /* Add any extra modes needed to represent the condition code.
2478 On the Sparc, we have a "no-overflow" mode which is used when an add or
2479 subtract insn is used to set the condition code. Different branches are
2480 used in this case for some operations.
2482 We also have two modes to indicate that the relevant condition code is
2483 in the floating-point condition code register. One for comparisons which
2484 will generate an exception if the result is unordered (CCFPEmode) and
2485 one for comparisons which will never trap (CCFPmode).
2487 CCXmode and CCX_NOOVmode are only used by v9. */
2489 #define EXTRA_CC_MODES \
2490 CC(CCXmode, "CCX") \
2491 CC(CC_NOOVmode, "CC_NOOV") \
2492 CC(CCX_NOOVmode, "CCX_NOOV") \
2493 CC(CCFPmode, "CCFP") \
2494 CC(CCFPEmode, "CCFPE")
2496 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2497 return the mode to be used for the comparison. For floating-point,
2498 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2499 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2500 processing is needed. */
2501 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2503 /* Return non-zero if MODE implies a floating point inequality can be
2504 reversed. For Sparc this is always true because we have a full
2505 compliment of ordered and unordered comparisons, but until generic
2506 code knows how to reverse it correctly we keep the old definition. */
2507 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2509 /* A function address in a call instruction for indexing purposes. */
2510 #define FUNCTION_MODE Pmode
2512 /* Define this if addresses of constant functions
2513 shouldn't be put through pseudo regs where they can be cse'd.
2514 Desirable on machines where ordinary constants are expensive
2515 but a CALL with constant address is cheap. */
2516 #define NO_FUNCTION_CSE
2518 /* alloca should avoid clobbering the old register save area. */
2519 #define SETJMP_VIA_SAVE_AREA
2521 /* Define subroutines to call to handle multiply and divide.
2522 Use the subroutines that Sun's library provides.
2523 The `*' prevents an underscore from being prepended by the compiler. */
2525 #define DIVSI3_LIBCALL "*.div"
2526 #define UDIVSI3_LIBCALL "*.udiv"
2527 #define MODSI3_LIBCALL "*.rem"
2528 #define UMODSI3_LIBCALL "*.urem"
2529 /* .umul is a little faster than .mul. */
2530 #define MULSI3_LIBCALL "*.umul"
2532 /* Define library calls for quad FP operations. These are all part of the
2534 #define ADDTF3_LIBCALL "_Q_add"
2535 #define SUBTF3_LIBCALL "_Q_sub"
2536 #define NEGTF2_LIBCALL "_Q_neg"
2537 #define MULTF3_LIBCALL "_Q_mul"
2538 #define DIVTF3_LIBCALL "_Q_div"
2539 #define FLOATSITF2_LIBCALL "_Q_itoq"
2540 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2541 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2542 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2543 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2544 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2545 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2546 #define EQTF2_LIBCALL "_Q_feq"
2547 #define NETF2_LIBCALL "_Q_fne"
2548 #define GTTF2_LIBCALL "_Q_fgt"
2549 #define GETF2_LIBCALL "_Q_fge"
2550 #define LTTF2_LIBCALL "_Q_flt"
2551 #define LETF2_LIBCALL "_Q_fle"
2553 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
2554 with soft-float, the SFmode and DFmode sqrt instructions will be absent,
2555 and the compiler will notice and try to use the TFmode sqrt instruction
2556 for calls to the builtin function sqrt, but this fails. */
2557 #define INIT_TARGET_OPTABS \
2559 if (TARGET_ARCH32) \
2561 add_optab->handlers[(int) TFmode].libfunc \
2562 = init_one_libfunc (ADDTF3_LIBCALL); \
2563 sub_optab->handlers[(int) TFmode].libfunc \
2564 = init_one_libfunc (SUBTF3_LIBCALL); \
2565 neg_optab->handlers[(int) TFmode].libfunc \
2566 = init_one_libfunc (NEGTF2_LIBCALL); \
2567 smul_optab->handlers[(int) TFmode].libfunc \
2568 = init_one_libfunc (MULTF3_LIBCALL); \
2569 sdiv_optab->handlers[(int) TFmode].libfunc \
2570 = init_one_libfunc (DIVTF3_LIBCALL); \
2571 eqtf2_libfunc = init_one_libfunc (EQTF2_LIBCALL); \
2572 netf2_libfunc = init_one_libfunc (NETF2_LIBCALL); \
2573 gttf2_libfunc = init_one_libfunc (GTTF2_LIBCALL); \
2574 getf2_libfunc = init_one_libfunc (GETF2_LIBCALL); \
2575 lttf2_libfunc = init_one_libfunc (LTTF2_LIBCALL); \
2576 letf2_libfunc = init_one_libfunc (LETF2_LIBCALL); \
2577 trunctfsf2_libfunc = init_one_libfunc (TRUNCTFSF2_LIBCALL); \
2578 trunctfdf2_libfunc = init_one_libfunc (TRUNCTFDF2_LIBCALL); \
2579 extendsftf2_libfunc = init_one_libfunc (EXTENDSFTF2_LIBCALL); \
2580 extenddftf2_libfunc = init_one_libfunc (EXTENDDFTF2_LIBCALL); \
2581 floatsitf_libfunc = init_one_libfunc (FLOATSITF2_LIBCALL); \
2582 fixtfsi_libfunc = init_one_libfunc (FIX_TRUNCTFSI2_LIBCALL); \
2583 fixunstfsi_libfunc \
2584 = init_one_libfunc (FIXUNS_TRUNCTFSI2_LIBCALL); \
2586 sqrt_optab->handlers[(int) TFmode].libfunc \
2587 = init_one_libfunc ("_Q_sqrt"); \
2589 INIT_SUBTARGET_OPTABS; \
2592 /* This is meant to be redefined in the host dependent files */
2593 #define INIT_SUBTARGET_OPTABS
2595 /* Nonzero if a floating point comparison library call for
2596 mode MODE that will return a boolean value. Zero if one
2597 of the libgcc2 functions is used. */
2598 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2600 /* Compute the cost of computing a constant rtl expression RTX
2601 whose rtx-code is CODE. The body of this macro is a portion
2602 of a switch statement. If the code is computed here,
2603 return it with a return statement. Otherwise, break from the switch. */
2605 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2607 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
2615 case CONST_DOUBLE: \
2616 if (GET_MODE (RTX) == DImode) \
2617 if ((XINT (RTX, 3) == 0 \
2618 && (unsigned) XINT (RTX, 2) < 0x1000) \
2619 || (XINT (RTX, 3) == -1 \
2620 && XINT (RTX, 2) < 0 \
2621 && XINT (RTX, 2) >= -0x1000)) \
2625 #define ADDRESS_COST(RTX) 1
2627 /* Compute extra cost of moving data between one register class
2629 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2630 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2631 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2632 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2633 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2634 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
2635 || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2)
2637 /* Provide the cost of a branch. For pre-v9 processors we use
2638 a value of 3 to take into account the potential annulling of
2639 the delay slot (which ends up being a bubble in the pipeline slot)
2640 plus a cycle to take into consideration the instruction cache
2643 On v9 and later, which have branch prediction facilities, we set
2644 it to the depth of the pipeline as that is the cost of a
2645 mispredicted branch. */
2647 #define BRANCH_COST \
2648 ((sparc_cpu == PROCESSOR_V9 \
2649 || sparc_cpu == PROCESSOR_ULTRASPARC) \
2651 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2654 /* Provide the costs of a rtl expression. This is in the body of a
2655 switch on CODE. The purpose for the cost of MULT is to encourage
2656 `synth_mult' to find a synthetic multiply when reasonable.
2658 If we need more than 12 insns to do a multiply, then go out-of-line,
2659 since the call overhead will be < 10% of the cost of the multiply. */
2661 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2663 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2664 return (GET_MODE (X) == DImode ? \
2665 COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); \
2666 if (sparc_cpu == PROCESSOR_ULTRASPARC3) \
2667 return COSTS_N_INSNS (6); \
2668 return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
2673 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2674 return (GET_MODE (X) == DImode ? \
2675 COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); \
2676 if (sparc_cpu == PROCESSOR_ULTRASPARC3) \
2677 return (GET_MODE (X) == DImode ? \
2678 COSTS_N_INSNS (71) : COSTS_N_INSNS (40)); \
2679 return COSTS_N_INSNS (25); \
2680 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
2681 so that cse will favor the latter. */ \
2686 #define PREFETCH_BLOCK \
2687 ((sparc_cpu == PROCESSOR_ULTRASPARC \
2688 || sparc_cpu == PROCESSOR_ULTRASPARC3) \
2691 #define SIMULTANEOUS_PREFETCHES \
2692 ((sparc_cpu == PROCESSOR_ULTRASPARC) \
2694 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2697 /* Control the assembler format that we output. */
2699 /* Output at beginning of assembler file. */
2701 #define ASM_FILE_START(file)
2703 /* A C string constant describing how to begin a comment in the target
2704 assembler language. The compiler assumes that the comment will end at
2705 the end of the line. */
2707 #define ASM_COMMENT_START "!"
2709 /* Output to assembler file text saying following lines
2710 may contain character constants, extra white space, comments, etc. */
2712 #define ASM_APP_ON ""
2714 /* Output to assembler file text saying following lines
2715 no longer contain unusual constructs. */
2717 #define ASM_APP_OFF ""
2719 /* ??? Try to make the style consistent here (_OP?). */
2721 #define ASM_FLOAT ".single"
2722 #define ASM_DOUBLE ".double"
2723 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2725 /* How to refer to registers in assembler output.
2726 This sequence is indexed by compiler's hard-register-number (see above). */
2728 #define REGISTER_NAMES \
2729 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2730 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2731 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2732 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2733 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2734 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2735 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2736 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2737 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2738 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2739 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2740 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2741 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2743 /* Define additional names for use in asm clobbers and asm declarations. */
2745 #define ADDITIONAL_REGISTER_NAMES \
2746 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2748 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2749 can run past this up to a continuation point. Once we used 1500, but
2750 a single entry in C++ can run more than 500 bytes, due to the length of
2751 mangled symbol names. dbxout.c should really be fixed to do
2752 continuations when they are actually needed instead of trying to
2754 #define DBX_CONTIN_LENGTH 1000
2756 /* This is how to output the definition of a user-level label named NAME,
2757 such as the label on a static function or variable NAME. */
2759 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2760 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2762 /* This is how to output a command to make the user-level label named NAME
2763 defined for reference from other files. */
2765 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2766 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2768 /* The prefix to add to user-visible assembler symbols. */
2770 #define USER_LABEL_PREFIX "_"
2772 /* This is how to output a definition of an internal numbered label where
2773 PREFIX is the class of label and NUM is the number within the class. */
2775 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2776 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2778 /* This is how to store into the string LABEL
2779 the symbol_ref name of an internal numbered label where
2780 PREFIX is the class of label and NUM is the number within the class.
2781 This is suitable for output with `assemble_name'. */
2783 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2784 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2786 /* This is how we hook in and defer the case-vector until the end of
2788 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2789 sparc_defer_case_vector ((LAB),(VEC), 0)
2791 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2792 sparc_defer_case_vector ((LAB),(VEC), 1)
2794 /* This is how to output an element of a case-vector that is absolute. */
2796 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2799 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2800 if (CASE_VECTOR_MODE == SImode) \
2801 fprintf (FILE, "\t.word\t"); \
2803 fprintf (FILE, "\t.xword\t"); \
2804 assemble_name (FILE, label); \
2805 fputc ('\n', FILE); \
2808 /* This is how to output an element of a case-vector that is relative.
2809 (SPARC uses such vectors only when generating PIC.) */
2811 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2814 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2815 if (CASE_VECTOR_MODE == SImode) \
2816 fprintf (FILE, "\t.word\t"); \
2818 fprintf (FILE, "\t.xword\t"); \
2819 assemble_name (FILE, label); \
2820 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2821 fputc ('-', FILE); \
2822 assemble_name (FILE, label); \
2823 fputc ('\n', FILE); \
2826 /* This is what to output before and after case-vector (both
2827 relative and absolute). If .subsection -1 works, we put case-vectors
2828 at the beginning of the current section. */
2830 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2832 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2833 fprintf(FILE, "\t.subsection\t-1\n")
2835 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2836 fprintf(FILE, "\t.previous\n")
2840 /* This is how to output an assembler line
2841 that says to advance the location counter
2842 to a multiple of 2**LOG bytes. */
2844 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2846 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2848 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2849 fprintf (FILE, "\t.skip %u\n", (SIZE))
2851 /* This says how to output an assembler line
2852 to define a global common symbol. */
2854 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2855 ( fputs ("\t.common ", (FILE)), \
2856 assemble_name ((FILE), (NAME)), \
2857 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
2859 /* This says how to output an assembler line to define a local common
2862 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2863 ( fputs ("\t.reserve ", (FILE)), \
2864 assemble_name ((FILE), (NAME)), \
2865 fprintf ((FILE), ",%u,\"bss\",%u\n", \
2866 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2868 /* A C statement (sans semicolon) to output to the stdio stream
2869 FILE the assembler definition of uninitialized global DECL named
2870 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2871 Try to use asm_output_aligned_bss to implement this macro. */
2873 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2875 fputs (".globl ", (FILE)); \
2876 assemble_name ((FILE), (NAME)); \
2877 fputs ("\n", (FILE)); \
2878 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2881 /* Store in OUTPUT a string (made with alloca) containing
2882 an assembler-name for a local static variable named NAME.
2883 LABELNO is an integer which is different for each call. */
2885 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2886 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2887 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2889 #define IDENT_ASM_OP "\t.ident\t"
2891 /* Output #ident as a .ident. */
2893 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2894 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2896 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2897 Used for C++ multiple inheritance. */
2898 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2903 && aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION)))) \
2905 if ((DELTA) >= 4096 || (DELTA) < -4096) \
2906 fprintf (FILE, "\tset\t%d, %%g1\n\tadd\t%%o%d, %%g1, %%o%d\n", \
2907 (int)(DELTA), reg, reg); \
2909 fprintf (FILE, "\tadd\t%%o%d, %d, %%o%d\n", reg, (int)(DELTA), reg);\
2910 fprintf (FILE, "\tor\t%%o7, %%g0, %%g1\n"); \
2911 fprintf (FILE, "\tcall\t"); \
2912 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2913 fprintf (FILE, ", 0\n"); \
2914 fprintf (FILE, "\t or\t%%g1, %%g0, %%o7\n"); \
2917 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2918 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
2920 /* Print operand X (an rtx) in assembler syntax to file FILE.
2921 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2922 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2924 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2926 /* Print a memory address as an operand to reference that memory location. */
2928 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2929 { register rtx base, index = 0; \
2931 register rtx addr = ADDR; \
2932 if (GET_CODE (addr) == REG) \
2933 fputs (reg_names[REGNO (addr)], FILE); \
2934 else if (GET_CODE (addr) == PLUS) \
2936 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2937 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2938 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2939 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2941 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2942 if (GET_CODE (base) == LO_SUM) \
2944 if (! USE_AS_OFFSETABLE_LO10 \
2946 || TARGET_CM_MEDMID) \
2948 output_operand (XEXP (base, 0), 0); \
2949 fputs ("+%lo(", FILE); \
2950 output_address (XEXP (base, 1)); \
2951 fprintf (FILE, ")+%d", offset); \
2955 fputs (reg_names[REGNO (base)], FILE); \
2957 fprintf (FILE, "%+d", offset); \
2958 else if (GET_CODE (index) == REG) \
2959 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2960 else if (GET_CODE (index) == SYMBOL_REF \
2961 || GET_CODE (index) == CONST) \
2962 fputc ('+', FILE), output_addr_const (FILE, index); \
2966 else if (GET_CODE (addr) == MINUS \
2967 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2969 output_addr_const (FILE, XEXP (addr, 0)); \
2970 fputs ("-(", FILE); \
2971 output_addr_const (FILE, XEXP (addr, 1)); \
2972 fputs ("-.)", FILE); \
2974 else if (GET_CODE (addr) == LO_SUM) \
2976 output_operand (XEXP (addr, 0), 0); \
2977 if (TARGET_CM_MEDMID) \
2978 fputs ("+%l44(", FILE); \
2980 fputs ("+%lo(", FILE); \
2981 output_address (XEXP (addr, 1)); \
2982 fputc (')', FILE); \
2984 else if (flag_pic && GET_CODE (addr) == CONST \
2985 && GET_CODE (XEXP (addr, 0)) == MINUS \
2986 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2987 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2988 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2990 addr = XEXP (addr, 0); \
2991 output_addr_const (FILE, XEXP (addr, 0)); \
2992 /* Group the args of the second CONST in parenthesis. */ \
2993 fputs ("-(", FILE); \
2994 /* Skip past the second CONST--it does nothing for us. */\
2995 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2996 /* Close the parenthesis. */ \
2997 fputc (')', FILE); \
3001 output_addr_const (FILE, addr); \
3005 /* Define the codes that are matched by predicates in sparc.c. */
3007 #define PREDICATE_CODES \
3008 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3009 {"fp_zero_operand", {CONST_DOUBLE}}, \
3010 {"fp_register_operand", {SUBREG, REG}}, \
3011 {"intreg_operand", {SUBREG, REG}}, \
3012 {"fcc_reg_operand", {REG}}, \
3013 {"fcc0_reg_operand", {REG}}, \
3014 {"icc_or_fcc_reg_operand", {REG}}, \
3015 {"restore_operand", {REG}}, \
3016 {"call_operand", {MEM}}, \
3017 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
3018 ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
3019 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3020 {"symbolic_memory_operand", {SUBREG, MEM}}, \
3021 {"label_ref_operand", {LABEL_REF}}, \
3022 {"sp64_medium_pic_operand", {CONST}}, \
3023 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
3024 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
3025 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
3026 {"splittable_symbolic_memory_operand", {MEM}}, \
3027 {"splittable_immediate_memory_operand", {MEM}}, \
3028 {"eq_or_neq", {EQ, NE}}, \
3029 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
3030 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
3031 {"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
3032 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
3033 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
3034 {"cc_arithop", {AND, IOR, XOR}}, \
3035 {"cc_arithopn", {AND, IOR}}, \
3036 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3037 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
3038 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
3039 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
3040 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3041 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3042 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3043 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3044 {"small_int", {CONST_INT}}, \
3045 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
3046 {"uns_small_int", {CONST_INT}}, \
3047 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
3048 {"clobbered_register", {REG}}, \
3049 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
3050 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
3051 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}},
3053 /* The number of Pmode words for the setjmp buffer. */
3054 #define JMP_BUF_SIZE 12
3056 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)
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