1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
29 /* #define SPARC_BI_ARCH */
31 /* Macro used later in this file to determine default architecture. */
32 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
34 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
35 architectures to compile for. We allow targets to choose compile time or
38 #if defined(__sparcv9) || defined(__arch64__)
39 #define TARGET_ARCH32 0
41 #define TARGET_ARCH32 1
45 #define TARGET_ARCH32 (! TARGET_64BIT)
47 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
48 #endif /* SPARC_BI_ARCH */
49 #endif /* IN_LIBGCC2 */
50 #define TARGET_ARCH64 (! TARGET_ARCH32)
52 /* Code model selection.
53 -mcmodel is used to select the v9 code model.
54 Different code models aren't supported for v7/8 code.
56 TARGET_CM_32: 32 bit address space, top 32 bits = 0,
57 pointers are 32 bits. Note that this isn't intended
60 TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0,
61 avoid generating %uhi and %ulo terms,
64 TARGET_CM_MEDMID: 64 bit address space.
65 The executable must be in the low 16 TB of memory.
66 This corresponds to the low 44 bits, and the %[hml]44
67 relocs are used. The text segment has a maximum size
70 TARGET_CM_MEDANY: 64 bit address space.
71 The text and data segments have a maximum size of 31
72 bits and may be located anywhere. The maximum offset
73 from any instruction to the label _GLOBAL_OFFSET_TABLE_
76 TARGET_CM_EMBMEDANY: 64 bit address space.
77 The text and data segments have a maximum size of 31 bits
78 and may be located anywhere. Register %g4 contains
79 the start address of the data segment.
90 /* Value of -mcmodel specified by user. */
91 extern const char *sparc_cmodel_string;
93 extern enum cmodel sparc_cmodel;
95 /* V9 code model selection. */
96 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
97 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
98 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
99 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
101 #define SPARC_DEFAULT_CMODEL CM_32
103 /* This is call-clobbered in the normal ABI, but is reserved in the
104 home grown (aka upward compatible) embedded ABI. */
105 #define EMBMEDANY_BASE_REG "%g4"
107 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
108 and specified by the user via --with-cpu=foo.
109 This specifies the cpu implementation, not the architecture size. */
110 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
112 #define TARGET_CPU_sparc 0
113 #define TARGET_CPU_v7 0 /* alias for previous */
114 #define TARGET_CPU_sparclet 1
115 #define TARGET_CPU_sparclite 2
116 #define TARGET_CPU_v8 3 /* generic v8 implementation */
117 #define TARGET_CPU_supersparc 4
118 #define TARGET_CPU_hypersparc 5
119 #define TARGET_CPU_sparc86x 6
120 #define TARGET_CPU_sparclite86x 6
121 #define TARGET_CPU_v9 7 /* generic v9 implementation */
122 #define TARGET_CPU_sparcv9 7 /* alias */
123 #define TARGET_CPU_sparc64 7 /* alias */
124 #define TARGET_CPU_ultrasparc 8
126 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
127 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
129 #define CPP_CPU32_DEFAULT_SPEC ""
130 #define ASM_CPU32_DEFAULT_SPEC ""
132 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
133 /* ??? What does Sun's CC pass? */
134 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
135 /* ??? It's not clear how other assemblers will handle this, so by default
136 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
137 is handled in sol2.h. */
138 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
140 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
141 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
142 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
147 #define CPP_CPU64_DEFAULT_SPEC ""
148 #define ASM_CPU64_DEFAULT_SPEC ""
150 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
151 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
152 #define CPP_CPU32_DEFAULT_SPEC ""
153 #define ASM_CPU32_DEFAULT_SPEC ""
156 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
157 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
158 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
161 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
162 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
163 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
166 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
167 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
168 #define ASM_CPU32_DEFAULT_SPEC ""
171 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
172 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
173 #define ASM_CPU32_DEFAULT_SPEC ""
176 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
177 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
178 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
183 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
184 Unrecognized value in TARGET_CPU_DEFAULT.
189 #define CPP_CPU_DEFAULT_SPEC \
190 (DEFAULT_ARCH32_P ? "\
191 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
192 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
194 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
195 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
197 #define ASM_CPU_DEFAULT_SPEC \
198 (DEFAULT_ARCH32_P ? "\
199 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
200 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
202 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
203 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
206 #else /* !SPARC_BI_ARCH */
208 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
209 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
211 #endif /* !SPARC_BI_ARCH */
213 /* Names to predefine in the preprocessor for this target machine.
214 ??? It would be nice to not include any subtarget specific values here,
215 however there's no way to portably provide subtarget values to
216 CPP_PREFINES. Also, -D values in CPP_SUBTARGET_SPEC don't get turned into
217 foo, __foo and __foo__. */
219 #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix -Asystem(unix) -Asystem(bsd)"
221 /* Define macros to distinguish architectures. */
223 /* Common CPP definitions used by CPP_SPEC amongst the various targets
224 for handling -mcpu=xxx switches. */
225 #define CPP_CPU_SPEC "\
227 %{msparclite:-D__sparclite__} \
228 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
229 %{mv8:-D__sparc_v8__} \
230 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
231 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
232 %{mcpu=sparclite:-D__sparclite__} \
233 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
234 %{mcpu=v8:-D__sparc_v8__} \
235 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
236 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
237 %{mcpu=sparclite86x:-D__sparclite86x__} \
238 %{mcpu=v9:-D__sparc_v9__} \
239 %{mcpu=ultrasparc:-D__sparc_v9__} \
240 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
243 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
244 the right varags.h file when bootstrapping. */
245 /* ??? It's not clear what value we want to use for -Acpu/machine for
246 sparc64 in 32 bit environments, so for now we only use `sparc64' in
247 64 bit environments. */
251 #define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \
252 -D__GCC_NEW_VARARGS__ -Acpu(sparc) -Amachine(sparc)"
253 #define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
254 -D__arch64__ -Acpu(sparc64) -Amachine(sparc64)"
258 #define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu(sparc) -Amachine(sparc)"
259 #define CPP_ARCH64_SPEC "-D__arch64__ -Acpu(sparc64) -Amachine(sparc64)"
263 #define CPP_ARCH_DEFAULT_SPEC \
264 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
266 #define CPP_ARCH_SPEC "\
267 %{m32:%(cpp_arch32)} \
268 %{m64:%(cpp_arch64)} \
269 %{!m32:%{!m64:%(cpp_arch_default)}} \
272 /* Macros to distinguish endianness. */
273 #define CPP_ENDIAN_SPEC "\
274 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
275 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
277 /* Macros to distinguish the particular subtarget. */
278 #define CPP_SUBTARGET_SPEC ""
280 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
282 /* Prevent error on `-sun4' and `-target sun4' options. */
283 /* This used to translate -dalign to -malign, but that is no good
284 because it can't turn off the usual meaning of making debugging dumps. */
285 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
286 ??? Delete support for -m<cpu> for 2.9. */
289 %{sun4:} %{target:} \
290 %{mcypress:-mcpu=cypress} \
291 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
292 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
295 /* Override in target specific files. */
296 #define ASM_CPU_SPEC "\
297 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
298 %{msparclite:-Asparclite} \
299 %{mf930:-Asparclite} %{mf934:-Asparclite} \
300 %{mcpu=sparclite:-Asparclite} \
301 %{mcpu=sparclite86x:-Asparclite} \
302 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
303 %{mv8plus:-Av8plus} \
305 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
306 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
309 /* Word size selection, among other things.
310 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
312 #define ASM_ARCH32_SPEC "-32"
313 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
314 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
316 #define ASM_ARCH64_SPEC "-64"
318 #define ASM_ARCH_DEFAULT_SPEC \
319 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
321 #define ASM_ARCH_SPEC "\
322 %{m32:%(asm_arch32)} \
323 %{m64:%(asm_arch64)} \
324 %{!m32:%{!m64:%(asm_arch_default)}} \
327 #ifdef HAVE_AS_RELAX_OPTION
328 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
330 #define ASM_RELAX_SPEC ""
333 /* Special flags to the Sun-4 assembler when using pipe for input. */
336 %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
337 %(asm_cpu) %(asm_relax)"
339 #define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}"
341 /* Provide required defaults for linker -e and -d switches. */
344 "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \
345 %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}"
347 /* This macro defines names of additional specifications to put in the specs
348 that can be used in various specifications like CC1_SPEC. Its definition
349 is an initializer with a subgrouping for each command option.
351 Each subgrouping contains a string constant, that defines the
352 specification name, and a string constant that used by the GNU CC driver
355 Do not define this macro if it does not need to do anything. */
357 #define EXTRA_SPECS \
358 { "cpp_cpu", CPP_CPU_SPEC }, \
359 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
360 { "cpp_arch32", CPP_ARCH32_SPEC }, \
361 { "cpp_arch64", CPP_ARCH64_SPEC }, \
362 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
363 { "cpp_arch", CPP_ARCH_SPEC }, \
364 { "cpp_endian", CPP_ENDIAN_SPEC }, \
365 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
366 { "asm_cpu", ASM_CPU_SPEC }, \
367 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
368 { "asm_arch32", ASM_ARCH32_SPEC }, \
369 { "asm_arch64", ASM_ARCH64_SPEC }, \
370 { "asm_relax", ASM_RELAX_SPEC }, \
371 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
372 { "asm_arch", ASM_ARCH_SPEC }, \
373 SUBTARGET_EXTRA_SPECS
375 #define SUBTARGET_EXTRA_SPECS
378 #define NO_BUILTIN_PTRDIFF_TYPE
379 #define NO_BUILTIN_SIZE_TYPE
381 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
382 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
384 /* ??? This should be 32 bits for v9 but what can we do? */
385 #define WCHAR_TYPE "short unsigned int"
386 #define WCHAR_TYPE_SIZE 16
387 #define MAX_WCHAR_TYPE_SIZE 16
389 /* Show we can debug even without a frame pointer. */
390 #define CAN_DEBUG_WITHOUT_FP
392 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
393 code into the rtl. Also, if we are profiling, we cannot eliminate
394 the frame pointer (because the return address will get smashed). */
396 #define OVERRIDE_OPTIONS \
398 if (profile_flag || profile_block_flag || profile_arc_flag) \
402 const char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC";\
403 warning ("%s and profiling conflict: disabling %s", \
404 pic_string, pic_string); \
407 flag_omit_frame_pointer = 0; \
409 sparc_override_options (); \
410 SUBTARGET_OVERRIDE_OPTIONS; \
413 /* This is meant to be redefined in the host dependent files. */
414 #define SUBTARGET_OVERRIDE_OPTIONS
416 /* These compiler options take an argument. We ignore -target for now. */
418 #define WORD_SWITCH_TAKES_ARG(STR) \
419 (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
420 || !strcmp (STR, "target") || !strcmp (STR, "assert"))
422 /* Print subsidiary information on the compiler version in use. */
424 #define TARGET_VERSION fprintf (stderr, " (sparc)");
426 /* Generate DBX debugging information. */
428 #define DBX_DEBUGGING_INFO
430 /* Run-time compilation parameters selecting different hardware subsets. */
432 extern int target_flags;
434 /* Nonzero if we should generate code to use the fpu. */
436 #define TARGET_FPU (target_flags & MASK_FPU)
438 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
439 use fast return insns, but lose some generality. */
440 #define MASK_EPILOGUE 2
441 #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
443 /* Nonzero if we should assume that double pointers might be unaligned.
444 This can happen when linking gcc compiled code with other compilers,
445 because the ABI only guarantees 4 byte alignment. */
446 #define MASK_UNALIGNED_DOUBLES 4
447 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
449 /* Nonzero means that we should generate code for a v8 sparc. */
451 #define TARGET_V8 (target_flags & MASK_V8)
453 /* Nonzero means that we should generate code for a sparclite.
454 This enables the sparclite specific instructions, but does not affect
455 whether FPU instructions are emitted. */
456 #define MASK_SPARCLITE 0x10
457 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
459 /* Nonzero if we're compiling for the sparclet. */
460 #define MASK_SPARCLET 0x20
461 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
463 /* Nonzero if we're compiling for v9 sparc.
464 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
465 the word size is 64. */
467 #define TARGET_V9 (target_flags & MASK_V9)
469 /* Non-zero to generate code that uses the instructions deprecated in
470 the v9 architecture. This option only applies to v9 systems. */
471 /* ??? This isn't user selectable yet. It's used to enable such insns
472 on 32 bit v9 systems and for the moment they're permanently disabled
473 on 64 bit v9 systems. */
474 #define MASK_DEPRECATED_V8_INSNS 0x80
475 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
477 /* Mask of all CPU selection flags. */
479 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
481 /* Non-zero means don't pass `-assert pure-text' to the linker. */
482 #define MASK_IMPURE_TEXT 0x100
483 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
485 /* Nonzero means that we should generate code using a flat register window
486 model, i.e. no save/restore instructions are generated, which is
487 compatible with normal sparc code.
488 The frame pointer is %i7 instead of %fp. */
489 #define MASK_FLAT 0x200
490 #define TARGET_FLAT (target_flags & MASK_FLAT)
492 /* Nonzero means use the registers that the Sparc ABI reserves for
493 application software. This must be the default to coincide with the
494 setting in FIXED_REGISTERS. */
495 #define MASK_APP_REGS 0x400
496 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
498 /* Option to select how quad word floating point is implemented.
499 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
500 Otherwise, we use the SPARC ABI quad library functions. */
501 #define MASK_HARD_QUAD 0x800
502 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
504 /* Non-zero on little-endian machines. */
505 /* ??? Little endian support currently only exists for sparclet-aout and
506 sparc64-elf configurations. May eventually want to expand the support
507 to all targets, but for now it's kept local to only those two. */
508 #define MASK_LITTLE_ENDIAN 0x1000
509 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
511 /* 0x2000, 0x4000 are unused */
513 /* Nonzero if pointers are 64 bits.
514 At the moment it must follow architecture size flag. */
515 #define MASK_PTR64 0x8000
516 #define TARGET_PTR64 (target_flags & MASK_PTR64)
518 /* Nonzero if generating code to run in a 64 bit environment.
519 This is intended to only be used by TARGET_ARCH{32,64} as they are the
520 mechanism used to control compile time or run time selection. */
521 #define MASK_64BIT 0x10000
522 #define TARGET_64BIT (target_flags & MASK_64BIT)
524 /* 0x20000,0x40000 unused */
526 /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
527 adding 2047 to %sp. This option is for v9 only and is the default. */
528 #define MASK_STACK_BIAS 0x80000
529 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
531 /* 0x100000,0x200000 unused */
533 /* Non-zero means -m{,no-}fpu was passed on the command line. */
534 #define MASK_FPU_SET 0x400000
535 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
537 /* Use the UltraSPARC Visual Instruction Set extensions. */
538 #define MASK_VIS 0x1000000
539 #define TARGET_VIS (target_flags & MASK_VIS)
541 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
542 the current out and global registers and Linux 2.2+ as well. */
543 #define MASK_V8PLUS 0x2000000
544 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
546 /* Force a the fastest alignment on structures to take advantage of
548 #define MASK_FASTER_STRUCTS 0x4000000
549 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
551 /* Use IEEE quad long double. */
552 #define MASK_LONG_DOUBLE_128 0x8000000
553 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
555 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
556 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
557 to get high 32 bits. False in V8+ or V9 because multiply stores
558 a 64 bit result in a register. */
560 #define TARGET_HARD_MUL32 \
561 ((TARGET_V8 || TARGET_SPARCLITE \
562 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
563 && ! TARGET_V8PLUS && TARGET_ARCH32)
565 #define TARGET_HARD_MUL \
566 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
567 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
570 /* Macro to define tables used to set the flags.
571 This is a list in braces of pairs in braces,
572 each pair being { "NAME", VALUE }
573 where VALUE is the bits to set or minus the bits to clear.
574 An empty string NAME is used to identify the default VALUE. */
576 #define TARGET_SWITCHES \
577 { {"fpu", MASK_FPU | MASK_FPU_SET, "Use hardware fp" }, \
578 {"no-fpu", -MASK_FPU, "Do not use hardware fp" }, \
579 {"no-fpu", MASK_FPU_SET, NULL, }, \
580 {"hard-float", MASK_FPU | MASK_FPU_SET, "Use hardware fp" }, \
581 {"soft-float", -MASK_FPU, "Do not use hardware fp" }, \
582 {"soft-float", MASK_FPU_SET, NULL }, \
583 {"epilogue", MASK_EPILOGUE, "Use FUNCTION_EPILOGUE" }, \
584 {"no-epilogue", -MASK_EPILOGUE, "Do not use FUNCTION_EPILOGUE" }, \
585 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, "Assume possible double misalignment" },\
586 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, "Assume all doubles are aligned" }, \
587 {"impure-text", MASK_IMPURE_TEXT, "Pass -assert pure-text to linker" }, \
588 {"no-impure-text", -MASK_IMPURE_TEXT, "Do not pass -assert pure-text to linker" }, \
589 {"flat", MASK_FLAT, "Use flat register window model" }, \
590 {"no-flat", -MASK_FLAT, "Do not use flat register window model" }, \
591 {"app-regs", MASK_APP_REGS, "Use ABI reserved registers" }, \
592 {"no-app-regs", -MASK_APP_REGS, "Do not use ABI reserved registers" }, \
593 {"hard-quad-float", MASK_HARD_QUAD, "Use hardware quad fp instructions" }, \
594 {"soft-quad-float", -MASK_HARD_QUAD, "Do not use hardware quad fp instructions" }, \
595 {"v8plus", MASK_V8PLUS, "Compile for v8plus ABI" }, \
596 {"no-v8plus", -MASK_V8PLUS, "Do not compile for v8plus ABI" }, \
597 {"vis", MASK_VIS, "Utilize Visual Instruction Set" }, \
598 {"no-vis", -MASK_VIS, "Do not utilize Visual Instruction Set" }, \
599 /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
600 {"cypress", 0, "Optimize for Cypress processors" }, \
601 {"sparclite", 0, "Optimize for SparcLite processors" }, \
602 {"f930", 0, "Optimize for F930 processors" }, \
603 {"f934", 0, "Optimize for F934 processors" }, \
604 {"v8", 0, "Use V8 Sparc ISA" }, \
605 {"supersparc", 0, "Optimize for SuperSparc processors" }, \
606 /* End of deprecated options. */ \
607 {"ptr64", MASK_PTR64, "Pointers are 64-bit" }, \
608 {"ptr32", -MASK_PTR64, "Pointers are 32-bit" }, \
609 {"32", -MASK_64BIT, "Use 32-bit ABI" }, \
610 {"64", MASK_64BIT, "Use 64-bit ABI" }, \
611 {"stack-bias", MASK_STACK_BIAS, "Use stack bias" }, \
612 {"no-stack-bias", -MASK_STACK_BIAS, "Do not use stack bias" }, \
613 {"faster-structs", MASK_FASTER_STRUCTS, "Use structs on stronger alignment for double-word copies" }, \
614 {"no-faster-structs", -MASK_FASTER_STRUCTS, "Do not use structs on stronger alignment for double-word copies" }, \
615 {"relax", 0, "Optimize tail call instructions in assembler and linker" }, \
616 {"no-relax", 0, "Do not optimize tail call instructions in assembler or linker" }, \
618 { "", TARGET_DEFAULT, ""}}
620 /* MASK_APP_REGS must always be the default because that's what
621 FIXED_REGISTERS is set to and -ffixed- is processed before
622 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
623 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
625 /* This is meant to be redefined in target specific files. */
626 #define SUBTARGET_SWITCHES
629 These must match the values for the cpu attribute in sparc.md. */
630 enum processor_type {
634 PROCESSOR_SUPERSPARC,
638 PROCESSOR_HYPERSPARC,
639 PROCESSOR_SPARCLITE86X,
646 /* This is set from -m{cpu,tune}=xxx. */
647 extern enum processor_type sparc_cpu;
649 /* Recast the cpu class to be the cpu attribute.
650 Every file includes us, but not every file includes insn-attr.h. */
651 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
653 /* This macro is similar to `TARGET_SWITCHES' but defines names of
654 command options that have values. Its definition is an
655 initializer with a subgrouping for each command option.
657 Each subgrouping contains a string constant, that defines the
658 fixed part of the option name, and the address of a variable.
659 The variable, type `char *', is set to the variable part of the
660 given option if the fixed part matches. The actual option name
661 is made by appending `-m' to the specified name.
663 Here is an example which defines `-mshort-data-NUMBER'. If the
664 given option is `-mshort-data-512', the variable `m88k_short_data'
665 will be set to the string `"512"'.
667 extern char *m88k_short_data;
668 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
670 #define TARGET_OPTIONS \
672 { "cpu=", &sparc_select[1].string, "Use features of and schedule code for given CPU" }, \
673 { "tune=", &sparc_select[2].string, "Schedule code for given CPU" }, \
674 { "cmodel=", &sparc_cmodel_string, "Use given Sparc code model" }, \
678 /* This is meant to be redefined in target specific files. */
679 #define SUBTARGET_OPTIONS
681 /* sparc_select[0] is reserved for the default cpu. */
682 struct sparc_cpu_select
690 extern struct sparc_cpu_select sparc_select[];
692 /* target machine storage layout */
694 /* Define for cross-compilation to a sparc target with no TFmode from a host
695 with a different float format (e.g. VAX). */
696 #define REAL_ARITHMETIC
698 /* Define this if most significant bit is lowest numbered
699 in instructions that operate on numbered bit-fields. */
700 #define BITS_BIG_ENDIAN 1
702 /* Define this if most significant byte of a word is the lowest numbered. */
703 #define BYTES_BIG_ENDIAN 1
705 /* Define this if most significant word of a multiword number is the lowest
707 #define WORDS_BIG_ENDIAN 1
709 /* Define this to set the endianness to use in libgcc2.c, which can
710 not depend on target_flags. */
711 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
712 #define LIBGCC2_WORDS_BIG_ENDIAN 0
714 #define LIBGCC2_WORDS_BIG_ENDIAN 1
717 /* number of bits in an addressable storage unit */
718 #define BITS_PER_UNIT 8
720 /* Width in bits of a "word", which is the contents of a machine register.
721 Note that this is not necessarily the width of data type `int';
722 if using 16-bit ints on a 68000, this would still be 32.
723 But on a machine with 16-bit registers, this would be 16. */
724 #define BITS_PER_WORD (TARGET_ARCH64 ? 64 : 32)
725 #define MAX_BITS_PER_WORD 64
727 /* Width of a word, in units (bytes). */
728 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
729 #define MIN_UNITS_PER_WORD 4
731 /* Now define the sizes of the C data types. */
733 #define SHORT_TYPE_SIZE 16
734 #define INT_TYPE_SIZE 32
735 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
736 #define LONG_LONG_TYPE_SIZE 64
737 #define FLOAT_TYPE_SIZE 32
738 #define DOUBLE_TYPE_SIZE 64
740 #if defined (SPARC_BI_ARCH)
741 #define MAX_LONG_TYPE_SIZE 64
745 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
746 Instead, it is enabled in sol2.h, because it does work under Solaris. */
747 /* Define for support of TFmode long double and REAL_ARITHMETIC.
748 Sparc ABI says that long double is 4 words. */
749 #define LONG_DOUBLE_TYPE_SIZE 128
752 /* Width in bits of a pointer.
753 See also the macro `Pmode' defined below. */
754 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
756 /* A macro to update MODE and UNSIGNEDP when an object whose type
757 is TYPE and which has the specified mode and signedness is to be
758 stored in a register. This macro is only called when TYPE is a
760 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
762 && GET_MODE_CLASS (MODE) == MODE_INT \
763 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
768 /* Define this macro if the promotion described by PROMOTE_MODE
769 should also be done for outgoing function arguments. */
770 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
771 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
773 #define PROMOTE_FUNCTION_ARGS
775 /* Define this macro if the promotion described by PROMOTE_MODE
776 should also be done for the return value of functions.
777 If this macro is defined, FUNCTION_VALUE must perform the same
778 promotions done by PROMOTE_MODE. */
779 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
780 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
782 #define PROMOTE_FUNCTION_RETURN
784 /* Define this macro if the promotion described by PROMOTE_MODE
785 should _only_ be performed for outgoing function arguments or
786 function return values, as specified by PROMOTE_FUNCTION_ARGS
787 and PROMOTE_FUNCTION_RETURN, respectively. */
788 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
789 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
790 for this value. For TARGET_ARCH64 we need it, as we don't have instructions
791 for arithmetic operations which do zero/sign extension at the same time,
792 so without this we end up with a srl/sra after every assignment to an
793 user variable, which means very very bad code. */
794 #define PROMOTE_FOR_CALL_ONLY
796 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
797 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
799 /* Boundary (in *bits*) on which stack pointer should be aligned. */
800 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
802 /* ALIGN FRAMES on double word boundaries */
804 #define SPARC_STACK_ALIGN(LOC) \
805 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
807 /* Allocation boundary (in *bits*) for the code of a function. */
808 #define FUNCTION_BOUNDARY 32
810 /* Alignment of field after `int : 0' in a structure. */
811 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
813 /* Every structure's size must be a multiple of this. */
814 #define STRUCTURE_SIZE_BOUNDARY 8
816 /* A bitfield declared as `int' forces `int' alignment for the struct. */
817 #define PCC_BITFIELD_TYPE_MATTERS 1
819 /* No data type wants to be aligned rounder than this. */
820 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
822 /* The best alignment to use in cases where we have a choice. */
823 #define FASTEST_ALIGNMENT 64
825 /* Define this macro as an expression for the alignment of a structure
826 (given by STRUCT as a tree node) if the alignment computed in the
827 usual way is COMPUTED and the alignment explicitly specified was
830 The default is to use SPECIFIED if it is larger; otherwise, use
831 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
832 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
833 (TARGET_FASTER_STRUCTS ? \
834 ((TREE_CODE (STRUCT) == RECORD_TYPE \
835 || TREE_CODE (STRUCT) == UNION_TYPE \
836 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
837 && TYPE_FIELDS (STRUCT) != 0 \
838 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
839 : MAX ((COMPUTED), (SPECIFIED))) \
840 : MAX ((COMPUTED), (SPECIFIED)))
842 /* Make strings word-aligned so strcpy from constants will be faster. */
843 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
844 ((TREE_CODE (EXP) == STRING_CST \
845 && (ALIGN) < FASTEST_ALIGNMENT) \
846 ? FASTEST_ALIGNMENT : (ALIGN))
848 /* Make arrays of chars word-aligned for the same reasons. */
849 #define DATA_ALIGNMENT(TYPE, ALIGN) \
850 (TREE_CODE (TYPE) == ARRAY_TYPE \
851 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
852 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
854 /* Set this nonzero if move instructions will actually fail to work
855 when given unaligned data. */
856 #define STRICT_ALIGNMENT 1
858 /* Things that must be doubleword aligned cannot go in the text section,
859 because the linker fails to align the text section enough!
860 Put them in the data section. This macro is only used in this file. */
861 #define MAX_TEXT_ALIGN 32
863 /* This forces all variables and constants to the data section when PIC.
864 This is because the SunOS 4 shared library scheme thinks everything in
865 text is a function, and patches the address to point to a loader stub. */
866 /* This is defined to zero for every system which doesn't use the a.out object
868 #ifndef SUNOS4_SHARED_LIBRARIES
869 #define SUNOS4_SHARED_LIBRARIES 0
872 /* This is defined differently for v9 in a cover file. */
873 #define SELECT_SECTION(T,RELOC) \
875 if (TREE_CODE (T) == VAR_DECL) \
877 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
878 && DECL_INITIAL (T) \
879 && (DECL_INITIAL (T) == error_mark_node \
880 || TREE_CONSTANT (DECL_INITIAL (T))) \
881 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
882 && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
887 else if (TREE_CODE (T) == CONSTRUCTOR) \
889 if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \
892 else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c') \
894 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
895 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \
896 || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
903 /* Use text section for a constant
904 unless we need more alignment than that offers. */
905 /* This is defined differently for v9 in a cover file. */
906 #define SELECT_RTX_SECTION(MODE, X) \
908 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
909 && ! (flag_pic && (symbolic_operand ((X), (MODE)) || SUNOS4_SHARED_LIBRARIES))) \
915 /* Standard register usage. */
917 /* Number of actual hardware registers.
918 The hardware registers are assigned numbers for the compiler
919 from 0 to just below FIRST_PSEUDO_REGISTER.
920 All registers that the compiler knows about must be given numbers,
921 even those that are not normally considered general registers.
923 SPARC has 32 integer registers and 32 floating point registers.
924 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
925 accessible. We still account for them to simplify register computations
926 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
928 Register 100 is used as the integer condition code register. */
930 #define FIRST_PSEUDO_REGISTER 101
932 #define SPARC_FIRST_FP_REG 32
933 /* Additional V9 fp regs. */
934 #define SPARC_FIRST_V9_FP_REG 64
935 #define SPARC_LAST_V9_FP_REG 95
936 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
937 #define SPARC_FIRST_V9_FCC_REG 96
938 #define SPARC_LAST_V9_FCC_REG 99
940 #define SPARC_FCC_REG 96
941 /* Integer CC reg. We don't distinguish %icc from %xcc. */
942 #define SPARC_ICC_REG 100
944 /* Nonzero if REGNO is an fp reg. */
945 #define SPARC_FP_REG_P(REGNO) \
946 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
948 /* Argument passing regs. */
949 #define SPARC_OUTGOING_INT_ARG_FIRST 8
950 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24)
951 #define SPARC_FP_ARG_FIRST 32
953 /* 1 for registers that have pervasive standard uses
954 and are not available for the register allocator.
957 g1 is free to use as temporary.
958 g2-g4 are reserved for applications. Gcc normally uses them as
959 temporaries, but this can be disabled via the -mno-app-regs option.
960 g5 through g7 are reserved for the operating system.
963 g1,g5 are free to use as temporaries, and are free to use between calls
964 if the call is to an external function via the PLT.
965 g4 is free to use as a temporary in the non-embedded case.
966 g4 is reserved in the embedded case.
967 g2-g3 are reserved for applications. Gcc normally uses them as
968 temporaries, but this can be disabled via the -mno-app-regs option.
969 g6-g7 are reserved for the operating system (or application in
971 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
972 currently be a fixed register until this pattern is rewritten.
973 Register 1 is also used when restoring call-preserved registers in large
976 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
977 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
980 #define FIXED_REGISTERS \
981 {1, 0, 2, 2, 2, 2, 1, 1, \
982 0, 0, 0, 0, 0, 0, 1, 0, \
983 0, 0, 0, 0, 0, 0, 0, 0, \
984 0, 0, 0, 0, 0, 0, 1, 1, \
986 0, 0, 0, 0, 0, 0, 0, 0, \
987 0, 0, 0, 0, 0, 0, 0, 0, \
988 0, 0, 0, 0, 0, 0, 0, 0, \
989 0, 0, 0, 0, 0, 0, 0, 0, \
991 0, 0, 0, 0, 0, 0, 0, 0, \
992 0, 0, 0, 0, 0, 0, 0, 0, \
993 0, 0, 0, 0, 0, 0, 0, 0, \
994 0, 0, 0, 0, 0, 0, 0, 0, \
998 /* 1 for registers not available across function calls.
999 These must include the FIXED_REGISTERS and also any
1000 registers that can be used without being saved.
1001 The latter must include the registers where values are returned
1002 and the register where structure-value addresses are passed.
1003 Aside from that, you can include as many other registers as you like. */
1005 #define CALL_USED_REGISTERS \
1006 {1, 1, 1, 1, 1, 1, 1, 1, \
1007 1, 1, 1, 1, 1, 1, 1, 1, \
1008 0, 0, 0, 0, 0, 0, 0, 0, \
1009 0, 0, 0, 0, 0, 0, 1, 1, \
1011 1, 1, 1, 1, 1, 1, 1, 1, \
1012 1, 1, 1, 1, 1, 1, 1, 1, \
1013 1, 1, 1, 1, 1, 1, 1, 1, \
1014 1, 1, 1, 1, 1, 1, 1, 1, \
1016 1, 1, 1, 1, 1, 1, 1, 1, \
1017 1, 1, 1, 1, 1, 1, 1, 1, \
1018 1, 1, 1, 1, 1, 1, 1, 1, \
1019 1, 1, 1, 1, 1, 1, 1, 1, \
1023 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
1024 they won't be allocated. */
1026 #define CONDITIONAL_REGISTER_USAGE \
1031 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1032 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1034 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
1035 /* then honour it. */ \
1036 if (TARGET_ARCH32 && fixed_regs[5]) \
1037 fixed_regs[5] = 1; \
1038 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
1039 fixed_regs[5] = 0; \
1043 for (regno = SPARC_FIRST_V9_FP_REG; \
1044 regno <= SPARC_LAST_V9_FP_REG; \
1046 fixed_regs[regno] = 1; \
1047 /* %fcc0 is used by v8 and v9. */ \
1048 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
1049 regno <= SPARC_LAST_V9_FCC_REG; \
1051 fixed_regs[regno] = 1; \
1056 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
1057 fixed_regs[regno] = 1; \
1059 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
1060 /* then honour it. Likewise with g3 and g4. */ \
1061 if (fixed_regs[2] == 2) \
1062 fixed_regs[2] = ! TARGET_APP_REGS; \
1063 if (fixed_regs[3] == 2) \
1064 fixed_regs[3] = ! TARGET_APP_REGS; \
1065 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
1066 fixed_regs[4] = ! TARGET_APP_REGS; \
1067 else if (TARGET_CM_EMBMEDANY) \
1068 fixed_regs[4] = 1; \
1069 else if (fixed_regs[4] == 2) \
1070 fixed_regs[4] = 0; \
1073 /* Let the compiler believe the frame pointer is still \
1074 %fp, but output it as %i7. */ \
1075 fixed_regs[31] = 1; \
1076 reg_names[FRAME_POINTER_REGNUM] = "%i7"; \
1077 /* Disable leaf functions */ \
1078 bzero (sparc_leaf_regs, FIRST_PSEUDO_REGISTER); \
1080 if (profile_block_flag) \
1082 /* %g1 and %g2 (sparc32) resp. %g4 (sparc64) must be \
1083 fixed, because BLOCK_PROFILER uses them. */ \
1084 fixed_regs[1] = 1; \
1085 fixed_regs[TARGET_ARCH64 ? 4 : 2] = 1; \
1090 /* Return number of consecutive hard regs needed starting at reg REGNO
1091 to hold something of mode MODE.
1092 This is ordinarily the length in words of a value of mode MODE
1093 but can be less for certain modes in special long registers.
1095 On SPARC, ordinary registers hold 32 bits worth;
1096 this means both integer and floating point registers.
1097 On v9, integer regs hold 64 bits worth; floating point regs hold
1098 32 bits worth (this includes the new fp regs as even the odd ones are
1099 included in the hard register count). */
1101 #define HARD_REGNO_NREGS(REGNO, MODE) \
1104 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
1105 : (GET_MODE_SIZE (MODE) + 3) / 4) \
1106 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1108 /* A subreg in 64 bit mode will have the wrong offset for a floating point
1109 register. The least significant part is at offset 1, compared to 0 for
1110 integer registers. This only applies when FMODE is a larger mode.
1111 We also need to handle a special case of TF-->DF conversions. */
1112 #define ALTER_HARD_SUBREG(TMODE, WORD, FMODE, REGNO) \
1114 && (REGNO) >= SPARC_FIRST_FP_REG \
1115 && (REGNO) <= SPARC_LAST_V9_FP_REG \
1116 && (TMODE) == SImode \
1117 && !((FMODE) == QImode || (FMODE) == HImode) \
1119 : ((TMODE) == DFmode && (FMODE) == TFmode) \
1120 ? ((REGNO) + ((WORD) * 2)) \
1121 : ((REGNO) + (WORD)))
1123 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1124 See sparc.c for how we initialize this. */
1125 extern int *hard_regno_mode_classes;
1126 extern int sparc_mode_class[];
1127 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1128 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
1130 /* Value is 1 if it is a good idea to tie two pseudo registers
1131 when one has mode MODE1 and one has mode MODE2.
1132 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1133 for any hard reg, then this must be 0 for correct output.
1135 For V9: SFmode can't be combined with other float modes, because they can't
1136 be allocated to the %d registers. Also, DFmode won't fit in odd %f
1137 registers, but SFmode will. */
1138 #define MODES_TIEABLE_P(MODE1, MODE2) \
1139 ((MODE1) == (MODE2) \
1140 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1142 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
1143 || (MODE1 != SFmode && MODE2 != SFmode)))))
1145 /* Specify the registers used for certain standard purposes.
1146 The values of these macros are register numbers. */
1148 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
1149 /* #define PC_REGNUM */
1151 /* Register to use for pushing function arguments. */
1152 #define STACK_POINTER_REGNUM 14
1154 /* Actual top-of-stack address is 92/176 greater than the contents of the
1155 stack pointer register for !v9/v9. That is:
1156 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
1157 address, and 6*4 bytes for the 6 register parameters.
1158 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
1160 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
1162 /* The stack bias (amount by which the hardware register is offset by). */
1163 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
1165 /* Is stack biased? */
1166 #define STACK_BIAS SPARC_STACK_BIAS
1168 /* Base register for access to local variables of the function. */
1169 #define FRAME_POINTER_REGNUM 30
1172 /* Register that is used for the return address for the flat model. */
1173 #define RETURN_ADDR_REGNUM 15
1176 /* Value should be nonzero if functions must have frame pointers.
1177 Zero means the frame pointer need not be set up (and parms
1178 may be accessed via the stack pointer) in functions that seem suitable.
1179 This is computed in `reload', in reload1.c.
1180 Used in flow.c, global.c, and reload1.c.
1182 Being a non-leaf function does not mean a frame pointer is needed in the
1183 flat window model. However, the debugger won't be able to backtrace through
1185 #define FRAME_POINTER_REQUIRED \
1186 (TARGET_FLAT ? (current_function_calls_alloca || current_function_varargs \
1187 || !leaf_function_p ()) \
1188 : ! (leaf_function_p () && only_leaf_regs_used ()))
1190 /* C statement to store the difference between the frame pointer
1191 and the stack pointer values immediately after the function prologue.
1193 Note, we always pretend that this is a leaf function because if
1194 it's not, there's no point in trying to eliminate the
1195 frame pointer. If it is a leaf function, we guessed right! */
1196 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
1197 ((VAR) = (TARGET_FLAT ? sparc_flat_compute_frame_size (get_frame_size ()) \
1198 : compute_frame_size (get_frame_size (), 1)))
1200 /* Base register for access to arguments of the function. */
1201 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1203 /* Register in which static-chain is passed to a function. This must
1204 not be a register used by the prologue. */
1205 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1207 /* Register which holds offset table for position-independent
1210 #define PIC_OFFSET_TABLE_REGNUM 23
1212 #define FINALIZE_PIC finalize_pic ()
1214 /* Pick a default value we can notice from override_options:
1216 v9: Default is off. */
1218 #define DEFAULT_PCC_STRUCT_RETURN -1
1220 /* Sparc ABI says that quad-precision floats and all structures are returned
1222 For v9: unions <= 32 bytes in size are returned in int regs,
1223 structures up to 32 bytes are returned in int and fp regs. */
1225 #define RETURN_IN_MEMORY(TYPE) \
1227 ? (TYPE_MODE (TYPE) == BLKmode \
1228 || TYPE_MODE (TYPE) == TFmode \
1229 || TYPE_MODE (TYPE) == TCmode) \
1230 : (TYPE_MODE (TYPE) == BLKmode \
1231 && int_size_in_bytes (TYPE) > 32))
1233 /* Functions which return large structures get the address
1234 to place the wanted value at offset 64 from the frame.
1235 Must reserve 64 bytes for the in and local registers.
1236 v9: Functions which return large structures get the address to place the
1237 wanted value from an invisible first argument. */
1238 /* Used only in other #defines in this file. */
1239 #define STRUCT_VALUE_OFFSET 64
1241 #define STRUCT_VALUE \
1244 : gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
1245 STRUCT_VALUE_OFFSET)))
1247 #define STRUCT_VALUE_INCOMING \
1250 : gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, \
1251 STRUCT_VALUE_OFFSET)))
1253 /* Define the classes of registers for register constraints in the
1254 machine description. Also define ranges of constants.
1256 One of the classes must always be named ALL_REGS and include all hard regs.
1257 If there is more than one class, another class must be named NO_REGS
1258 and contain no registers.
1260 The name GENERAL_REGS must be the name of a class (or an alias for
1261 another name such as ALL_REGS). This is the class of registers
1262 that is allowed by "g" or "r" in a register constraint.
1263 Also, registers outside this class are allocated only when
1264 instructions express preferences for them.
1266 The classes must be numbered in nondecreasing order; that is,
1267 a larger-numbered class must never be contained completely
1268 in a smaller-numbered class.
1270 For any two classes, it is very desirable that there be another
1271 class that represents their union. */
1273 /* The SPARC has various kinds of registers: general, floating point,
1274 and condition codes [well, it has others as well, but none that we
1275 care directly about].
1277 For v9 we must distinguish between the upper and lower floating point
1278 registers because the upper ones can't hold SFmode values.
1279 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1280 satisfying a group need for a class will also satisfy a single need for
1281 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1284 It is important that one class contains all the general and all the standard
1285 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1286 because reg_class_record() will bias the selection in favor of fp regs,
1287 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1288 because FP_REGS > GENERAL_REGS.
1290 It is also important that one class contain all the general and all the
1291 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1292 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1293 allocate_reload_reg() to bypass it causing an abort because the compiler
1294 thinks it doesn't have a spill reg when in fact it does.
1296 v9 also has 4 floating point condition code registers. Since we don't
1297 have a class that is the union of FPCC_REGS with either of the others,
1298 it is important that it appear first. Otherwise the compiler will die
1299 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1302 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1303 may try to use it to hold an SImode value. See register_operand.
1304 ??? Should %fcc[0123] be handled similarly?
1307 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1308 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1309 ALL_REGS, LIM_REG_CLASSES };
1311 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1313 /* Give names of register classes as strings for dump file. */
1315 #define REG_CLASS_NAMES \
1316 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1317 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1320 /* Define which registers fit in which classes.
1321 This is an initializer for a vector of HARD_REG_SET
1322 of length N_REG_CLASSES. */
1324 #define REG_CLASS_CONTENTS \
1325 {{0, 0, 0, 0}, {0, 0, 0, 0xf}, {0xffff, 0, 0, 0}, \
1326 {-1, 0, 0, 0}, {0, -1, 0, 0}, {0, -1, -1, 0}, \
1327 {-1, -1, 0, 0}, {-1, -1, -1, 0}, {-1, -1, -1, 0x1f}}
1329 /* The same information, inverted:
1330 Return the class number of the smallest class containing
1331 reg number REGNO. This could be a conditional expression
1332 or could index an array. */
1334 extern enum reg_class sparc_regno_reg_class[];
1336 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1338 /* This is the order in which to allocate registers normally.
1340 We put %f0/%f1 last among the float registers, so as to make it more
1341 likely that a pseudo-register which dies in the float return register
1342 will get allocated to the float return register, thus saving a move
1343 instruction at the end of the function. */
1345 #define REG_ALLOC_ORDER \
1346 { 8, 9, 10, 11, 12, 13, 2, 3, \
1347 15, 16, 17, 18, 19, 20, 21, 22, \
1348 23, 24, 25, 26, 27, 28, 29, 31, \
1349 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \
1350 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1351 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1352 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1353 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1354 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1355 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1356 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1357 32, 33, /* %f0,%f1 */ \
1358 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \
1359 1, 4, 5, 6, 7, 0, 14, 30}
1361 /* This is the order in which to allocate registers for
1362 leaf functions. If all registers can fit in the "gi" registers,
1363 then we have the possibility of having a leaf function. */
1365 #define REG_LEAF_ALLOC_ORDER \
1366 { 2, 3, 24, 25, 26, 27, 28, 29, \
1368 15, 8, 9, 10, 11, 12, 13, \
1369 16, 17, 18, 19, 20, 21, 22, 23, \
1370 34, 35, 36, 37, 38, 39, \
1371 40, 41, 42, 43, 44, 45, 46, 47, \
1372 48, 49, 50, 51, 52, 53, 54, 55, \
1373 56, 57, 58, 59, 60, 61, 62, 63, \
1374 64, 65, 66, 67, 68, 69, 70, 71, \
1375 72, 73, 74, 75, 76, 77, 78, 79, \
1376 80, 81, 82, 83, 84, 85, 86, 87, \
1377 88, 89, 90, 91, 92, 93, 94, 95, \
1379 96, 97, 98, 99, 100, \
1382 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1384 extern char sparc_leaf_regs[];
1385 #define LEAF_REGISTERS sparc_leaf_regs
1387 extern char leaf_reg_remap[];
1388 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1390 /* The class value for index registers, and the one for base regs. */
1391 #define INDEX_REG_CLASS GENERAL_REGS
1392 #define BASE_REG_CLASS GENERAL_REGS
1394 /* Local macro to handle the two v9 classes of FP regs. */
1395 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1397 /* Get reg_class from a letter such as appears in the machine description.
1398 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1399 .md file for v8 and v9.
1400 'd' and 'b' are used for single and double precision VIS operations,
1402 'h' is used for V8+ 64 bit global and out registers. */
1404 #define REG_CLASS_FROM_LETTER(C) \
1406 ? ((C) == 'f' ? FP_REGS \
1407 : (C) == 'e' ? EXTRA_FP_REGS \
1408 : (C) == 'c' ? FPCC_REGS \
1409 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1410 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1411 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1413 : ((C) == 'f' ? FP_REGS \
1414 : (C) == 'e' ? FP_REGS \
1415 : (C) == 'c' ? FPCC_REGS \
1418 /* The letters I, J, K, L and M in a register constraint string
1419 can be used to stand for particular ranges of immediate operands.
1420 This macro defines what the ranges are.
1421 C is the letter, and VALUE is a constant value.
1422 Return 1 if VALUE is in the range specified by C.
1424 `I' is used for the range of constants an insn can actually contain.
1425 `J' is used for the range which is just zero (since that is R0).
1426 `K' is used for constants which can be loaded with a single sethi insn.
1427 `L' is used for the range of constants supported by the movcc insns.
1428 `M' is used for the range of constants supported by the movrcc insns. */
1430 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1431 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1432 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1433 /* 10 and 11 bit immediates are only used for a few specific insns.
1434 SMALL_INT is used throughout the port so we continue to use it. */
1435 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1436 /* 13 bit immediate, considering only the low 32 bits */
1437 #define SMALL_INT32(X) (SPARC_SIMM13_P ((int)INTVAL (X) & 0xffffffff))
1438 #define SPARC_SETHI_P(X) \
1439 (((unsigned HOST_WIDE_INT) (X) & \
1440 (TARGET_ARCH64 ? ~(unsigned HOST_WIDE_INT) 0xfffffc00 : 0x3ff)) == 0)
1442 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1443 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1444 : (C) == 'J' ? (VALUE) == 0 \
1445 : (C) == 'K' ? SPARC_SETHI_P (VALUE) \
1446 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1447 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1450 /* Similar, but for floating constants, and defining letters G and H.
1451 Here VALUE is the CONST_DOUBLE rtx itself. */
1453 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1454 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1455 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1458 /* Given an rtx X being reloaded into a reg required to be
1459 in class CLASS, return the class of reg to actually use.
1460 In general this is just CLASS; but on some machines
1461 in some cases it is preferable to use a more restrictive class. */
1462 /* - We can't load constants into FP registers.
1463 - We can't load FP constants into integer registers when soft-float,
1464 because there is no soft-float pattern with a r/F constraint.
1465 - We can't load FP constants into integer registers for TFmode unless
1466 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1467 - Try and reload integer constants (symbolic or otherwise) back into
1468 registers directly, rather than having them dumped to memory. */
1470 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1472 ? ((FP_REG_CLASS_P (CLASS) \
1473 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1475 || (GET_MODE (X) == TFmode \
1476 && ! fp_zero_operand (X, TFmode))) \
1478 : (!FP_REG_CLASS_P (CLASS) \
1479 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1484 /* Return the register class of a scratch register needed to load IN into
1485 a register of class CLASS in MODE.
1487 We need a temporary when loading/storing a HImode/QImode value
1488 between memory and the FPU registers. This can happen when combine puts
1489 a paradoxical subreg in a float/fix conversion insn. */
1491 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1492 ((FP_REG_CLASS_P (CLASS) \
1493 && ((MODE) == HImode || (MODE) == QImode) \
1494 && (GET_CODE (IN) == MEM \
1495 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1496 && true_regnum (IN) == -1))) \
1498 : (((TARGET_CM_MEDANY \
1499 && symbolic_operand ((IN), (MODE))) \
1500 || (TARGET_CM_EMBMEDANY \
1501 && text_segment_operand ((IN), (MODE)))) \
1506 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1507 ((FP_REG_CLASS_P (CLASS) \
1508 && ((MODE) == HImode || (MODE) == QImode) \
1509 && (GET_CODE (IN) == MEM \
1510 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1511 && true_regnum (IN) == -1))) \
1513 : (((TARGET_CM_MEDANY \
1514 && symbolic_operand ((IN), (MODE))) \
1515 || (TARGET_CM_EMBMEDANY \
1516 && text_segment_operand ((IN), (MODE)))) \
1521 /* On SPARC it is not possible to directly move data between
1522 GENERAL_REGS and FP_REGS. */
1523 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1524 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1526 /* Return the stack location to use for secondary memory needed reloads.
1527 We want to use the reserved location just below the frame pointer.
1528 However, we must ensure that there is a frame, so use assign_stack_local
1529 if the frame size is zero. */
1530 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1531 (get_frame_size () == 0 \
1532 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1533 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1534 STARTING_FRAME_OFFSET)))
1536 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1537 because the movsi and movsf patterns don't handle r/f moves.
1538 For v8 we copy the default definition. */
1539 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1541 ? (GET_MODE_BITSIZE (MODE) < 32 \
1542 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1544 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1545 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1548 /* Return the maximum number of consecutive registers
1549 needed to represent mode MODE in a register of class CLASS. */
1550 /* On SPARC, this is the size of MODE in words. */
1551 #define CLASS_MAX_NREGS(CLASS, MODE) \
1552 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1553 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1555 /* Stack layout; function entry, exit and calling. */
1557 /* Define the number of register that can hold parameters.
1558 This macro is only used in other macro definitions below and in sparc.c.
1559 MODE is the mode of the argument.
1560 !v9: All args are passed in %o0-%o5.
1561 v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values.
1562 See the description in sparc.c. */
1563 #define NPARM_REGS(MODE) \
1565 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \
1568 /* Define this if pushing a word on the stack
1569 makes the stack pointer a smaller address. */
1570 #define STACK_GROWS_DOWNWARD
1572 /* Define this if the nominal address of the stack frame
1573 is at the high-address end of the local variables;
1574 that is, each additional local variable allocated
1575 goes at a more negative offset in the frame. */
1576 #define FRAME_GROWS_DOWNWARD
1578 /* Offset within stack frame to start allocating local variables at.
1579 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1580 first local allocated. Otherwise, it is the offset to the BEGINNING
1581 of the first local allocated. */
1582 /* This allows space for one TFmode floating point value. */
1583 #define STARTING_FRAME_OFFSET \
1584 (TARGET_ARCH64 ? (SPARC_STACK_BIAS - 16) \
1585 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1587 /* If we generate an insn to push BYTES bytes,
1588 this says how many the stack pointer really advances by.
1589 On SPARC, don't define this because there are no push insns. */
1590 /* #define PUSH_ROUNDING(BYTES) */
1592 /* Offset of first parameter from the argument pointer register value.
1593 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1594 even if this function isn't going to use it.
1595 v9: This is 128 for the ins and locals. */
1596 #define FIRST_PARM_OFFSET(FNDECL) \
1597 (TARGET_ARCH64 ? (SPARC_STACK_BIAS + 16 * UNITS_PER_WORD) \
1598 : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD))
1600 /* Offset from the argument pointer register value to the CFA.
1601 This is different from FIRST_PARM_OFFSET because the register window
1602 comes between the CFA and the arguments. */
1604 #define ARG_POINTER_CFA_OFFSET(FNDECL) SPARC_STACK_BIAS
1606 /* When a parameter is passed in a register, stack space is still
1608 !v9: All 6 possible integer registers have backing store allocated.
1609 v9: Only space for the arguments passed is allocated. */
1610 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1611 meaning to the backend. Further, we need to be able to detect if a
1612 varargs/unprototyped function is called, as they may want to spill more
1613 registers than we've provided space. Ugly, ugly. So for now we retain
1614 all 6 slots even for v9. */
1615 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1617 /* Keep the stack pointer constant throughout the function.
1618 This is both an optimization and a necessity: longjmp
1619 doesn't behave itself when the stack pointer moves within
1621 #define ACCUMULATE_OUTGOING_ARGS 1
1623 /* Value is the number of bytes of arguments automatically
1624 popped when returning from a subroutine call.
1625 FUNDECL is the declaration node of the function (as a tree),
1626 FUNTYPE is the data type of the function (as a tree),
1627 or for a library call it is an identifier node for the subroutine name.
1628 SIZE is the number of bytes of arguments passed on the stack. */
1630 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1632 /* Some subroutine macros specific to this machine.
1633 When !TARGET_FPU, put float return values in the general registers,
1634 since we don't have any fp registers. */
1635 #define BASE_RETURN_VALUE_REG(MODE) \
1637 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1638 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1640 #define BASE_OUTGOING_VALUE_REG(MODE) \
1642 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1643 : TARGET_FLAT ? 8 : 24) \
1644 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1645 : (TARGET_FLAT ? 8 : 24)))
1647 #define BASE_PASSING_ARG_REG(MODE) \
1649 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1652 /* ??? FIXME -- seems wrong for v9 structure passing... */
1653 #define BASE_INCOMING_ARG_REG(MODE) \
1655 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1656 : TARGET_FLAT ? 8 : 24) \
1657 : (TARGET_FLAT ? 8 : 24))
1659 /* Define this macro if the target machine has "register windows". This
1660 C expression returns the register number as seen by the called function
1661 corresponding to register number OUT as seen by the calling function.
1662 Return OUT if register number OUT is not an outbound register. */
1664 #define INCOMING_REGNO(OUT) \
1665 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1667 /* Define this macro if the target machine has "register windows". This
1668 C expression returns the register number as seen by the calling function
1669 corresponding to register number IN as seen by the called function.
1670 Return IN if register number IN is not an inbound register. */
1672 #define OUTGOING_REGNO(IN) \
1673 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1675 /* Define how to find the value returned by a function.
1676 VALTYPE is the data type of the value (as a tree).
1677 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1678 otherwise, FUNC is 0. */
1680 /* On SPARC the value is found in the first "output" register. */
1682 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1683 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1685 /* But the called function leaves it in the first "input" register. */
1687 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1688 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1690 /* Define how to find the value returned by a library function
1691 assuming the value has mode MODE. */
1693 #define LIBCALL_VALUE(MODE) \
1694 function_value (NULL_TREE, (MODE), 1)
1696 /* 1 if N is a possible register number for a function value
1697 as seen by the caller.
1698 On SPARC, the first "output" reg is used for integer values,
1699 and the first floating point register is used for floating point values. */
1701 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1703 /* Define the size of space to allocate for the return value of an
1706 #define APPLY_RESULT_SIZE 16
1708 /* 1 if N is a possible register number for function argument passing.
1709 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1711 #define FUNCTION_ARG_REGNO_P(N) \
1713 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1714 : ((N) >= 8 && (N) <= 13))
1716 /* Define a data type for recording info about an argument list
1717 during the scan of that argument list. This data type should
1718 hold all necessary information about the function itself
1719 and about the args processed so far, enough to enable macros
1720 such as FUNCTION_ARG to determine where the next arg should go.
1722 On SPARC (!v9), this is a single integer, which is a number of words
1723 of arguments scanned so far (including the invisible argument,
1724 if any, which holds the structure-value-address).
1725 Thus 7 or more means all following args should go on the stack.
1727 For v9, we also need to know whether a prototype is present. */
1730 int words; /* number of words passed so far */
1731 int prototype_p; /* non-zero if a prototype is present */
1732 int libcall_p; /* non-zero if a library call */
1734 #define CUMULATIVE_ARGS struct sparc_args
1736 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1737 for a call to a function whose data type is FNTYPE.
1738 For a library call, FNTYPE is 0. */
1740 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1741 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (INDIRECT));
1743 /* Update the data in CUM to advance over an argument
1744 of mode MODE and data type TYPE.
1745 TYPE is null for libcalls where that information may not be available. */
1747 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1748 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1750 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1752 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1754 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1755 || TREE_ADDRESSABLE (TYPE)))
1757 /* Determine where to put an argument to a function.
1758 Value is zero to push the argument on the stack,
1759 or a hard register in which to store the argument.
1761 MODE is the argument's machine mode.
1762 TYPE is the data type of the argument (as a tree).
1763 This is null for libcalls where that information may
1765 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1766 the preceding args and about the function being called.
1767 NAMED is nonzero if this argument is a named parameter
1768 (otherwise it is an extra parameter matching an ellipsis). */
1770 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1771 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1773 /* Define where a function finds its arguments.
1774 This is different from FUNCTION_ARG because of register windows. */
1776 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1777 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1779 /* For an arg passed partly in registers and partly in memory,
1780 this is the number of registers used.
1781 For args passed entirely in registers or entirely in memory, zero. */
1783 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1784 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
1786 /* A C expression that indicates when an argument must be passed by reference.
1787 If nonzero for an argument, a copy of that argument is made in memory and a
1788 pointer to the argument is passed instead of the argument itself.
1789 The pointer is passed in whatever way is appropriate for passing a pointer
1792 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1793 function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1795 /* If defined, a C expression which determines whether, and in which direction,
1796 to pad out an argument with extra space. The value should be of type
1797 `enum direction': either `upward' to pad above the argument,
1798 `downward' to pad below, or `none' to inhibit padding. */
1800 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1801 function_arg_padding ((MODE), (TYPE))
1803 /* If defined, a C expression that gives the alignment boundary, in bits,
1804 of an argument with the specified mode and type. If it is not defined,
1805 PARM_BOUNDARY is used for all arguments.
1806 For sparc64, objects requiring 16 byte alignment are passed that way. */
1808 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1810 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1811 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1812 ? 128 : PARM_BOUNDARY)
1814 /* Define the information needed to generate branch and scc insns. This is
1815 stored from the compare operation. Note that we can't use "rtx" here
1816 since it hasn't been defined! */
1818 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
1821 /* Generate the special assembly code needed to tell the assembler whatever
1822 it might need to know about the return value of a function.
1824 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
1825 information to the assembler relating to peephole optimization (done in
1828 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1829 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1831 /* Output the label for a function definition. */
1833 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
1835 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
1836 ASM_OUTPUT_LABEL (FILE, NAME); \
1839 /* Output the special assembly code needed to tell the assembler some
1840 register is used as global register variable.
1842 SPARC 64bit psABI declares registers %g2 and %g3 as application
1843 registers and %g6 and %g7 as OS registers. Any object using them
1844 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1845 and how they are used (scratch or some global variable).
1846 Linker will then refuse to link together objects which use those
1847 registers incompatibly.
1849 Unless the registers are used for scratch, two different global
1850 registers cannot be declared to the same name, so in the unlikely
1851 case of a global register variable occupying more than one register
1852 we prefix the second and following registers with .gnu.part1. etc. */
1854 extern char sparc_hard_reg_printed[8];
1856 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1857 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1859 if (TARGET_ARCH64) \
1861 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1863 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1864 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1866 if (reg == (REGNO)) \
1867 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1869 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1870 reg, reg - (REGNO), (NAME)); \
1871 sparc_hard_reg_printed[reg] = 1; \
1877 /* This macro generates the assembly code for function entry.
1878 FILE is a stdio stream to output the code to.
1879 SIZE is an int: how many units of temporary storage to allocate.
1880 Refer to the array `regs_ever_live' to determine which registers
1881 to save; `regs_ever_live[I]' is nonzero if register number I
1882 is ever used in the function. This macro is responsible for
1883 knowing which registers should not be saved even if used. */
1885 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
1886 of memory. If any fpu reg is used in the function, we allocate
1887 such a block here, at the bottom of the frame, just in case it's needed.
1889 If this function is a leaf procedure, then we may choose not
1890 to do a "save" insn. The decision about whether or not
1891 to do this is made in regclass.c. */
1893 #define FUNCTION_PROLOGUE(FILE, SIZE) \
1894 (TARGET_FLAT ? sparc_flat_output_function_prologue (FILE, (int)SIZE) \
1895 : output_function_prologue (FILE, (int)SIZE, \
1896 current_function_uses_only_leaf_regs))
1898 /* Output assembler code to FILE to increment profiler label # LABELNO
1899 for profiling a function entry. */
1901 #define FUNCTION_PROFILER(FILE, LABELNO) \
1902 sparc_function_profiler(FILE, LABELNO)
1904 /* Set the name of the mcount function for the system. */
1906 #define MCOUNT_FUNCTION "*mcount"
1908 /* The following macro shall output assembler code to FILE
1909 to initialize basic-block profiling. */
1911 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1912 sparc_function_block_profiler(FILE, BLOCK_OR_LABEL)
1914 /* The following macro shall output assembler code to FILE
1915 to increment a counter associated with basic block number BLOCKNO. */
1917 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1918 sparc_block_profiler (FILE, BLOCKNO)
1920 /* The following macro shall output assembler code to FILE
1921 to indicate a return from function during basic-block profiling. */
1923 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1924 sparc_function_block_profiler_exit(FILE)
1928 /* The function `__bb_trace_func' is called in every basic block
1929 and is not allowed to change the machine state. Saving (restoring)
1930 the state can either be done in the BLOCK_PROFILER macro,
1931 before calling function (rsp. after returning from function)
1932 `__bb_trace_func', or it can be done inside the function by
1933 defining the macros:
1935 MACHINE_STATE_SAVE(ID)
1936 MACHINE_STATE_RESTORE(ID)
1938 In the latter case care must be taken, that the prologue code
1939 of function `__bb_trace_func' does not already change the
1940 state prior to saving it with MACHINE_STATE_SAVE.
1942 The parameter `ID' is a string identifying a unique macro use.
1944 On sparc it is sufficient to save the psw register to memory.
1945 Unfortunately the psw register can be read in supervisor mode only,
1946 so we read only the condition codes by using branch instructions
1947 and hope that this is enough.
1949 On V9, life is much sweater: there is a user accessible %ccr
1950 register, but we use it for 64bit libraries only. */
1954 #define MACHINE_STATE_SAVE(ID) \
1955 int ms_flags, ms_saveret; \
1968 bneg,a LFLGNN"ID"\n\
1971 : "=r"(ms_flags), "=r"(ms_saveret));
1975 #define MACHINE_STATE_SAVE(ID) \
1976 unsigned long ms_flags, ms_saveret; \
1980 : "=r"(ms_flags), "=r"(ms_saveret));
1984 /* On sparc MACHINE_STATE_RESTORE restores the psw register from memory.
1985 The psw register can be written in supervisor mode only,
1986 which is true even for simple condition codes.
1987 We use some combination of instructions to produce the
1988 proper condition codes, but some flag combinations can not
1989 be generated in this way. If this happens an unimplemented
1990 instruction will be executed to abort the program. */
1994 #define MACHINE_STATE_RESTORE(ID) \
1995 { extern char flgtab[] __asm__("LFLGTAB"ID); \
1999 ! Do part of VC in the delay slot here, as it needs 3 insns.\n\
2016 subcc %%g0,%%g0,%%g0\n\
2025 orcc %%g0,-1,%%g0\n\
2028 addcc %%g0,%3,%%g0\n\
2050 : "r"(ms_flags*8), "r"(flgtab), "r"(-1), \
2051 "r"(0x80000000), "r"(ms_saveret) \
2056 #define MACHINE_STATE_RESTORE(ID) \
2060 : : "r"(ms_flags), "r"(ms_saveret) \
2065 #endif /* IN_LIBGCC2 */
2067 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2068 the stack pointer does not matter. The value is tested only in
2069 functions that have frame pointers.
2070 No definition is equivalent to always zero. */
2072 #define EXIT_IGNORE_STACK \
2073 (get_frame_size () != 0 \
2074 || current_function_calls_alloca || current_function_outgoing_args_size)
2076 /* This macro generates the assembly code for function exit,
2077 on machines that need it. If FUNCTION_EPILOGUE is not defined
2078 then individual return instructions are generated for each
2079 return statement. Args are same as for FUNCTION_PROLOGUE.
2081 The function epilogue should not depend on the current stack pointer!
2082 It should use the frame pointer only. This is mandatory because
2083 of alloca; we also take advantage of it to omit stack adjustments
2084 before returning. */
2086 #define FUNCTION_EPILOGUE(FILE, SIZE) \
2087 (TARGET_FLAT ? sparc_flat_output_function_epilogue (FILE, (int)SIZE) \
2088 : output_function_epilogue (FILE, (int)SIZE, \
2089 current_function_uses_only_leaf_regs))
2091 #define DELAY_SLOTS_FOR_EPILOGUE \
2092 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
2093 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
2094 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
2095 : eligible_for_epilogue_delay (trial, slots_filled))
2097 /* Define registers used by the epilogue and return instruction. */
2098 #define EPILOGUE_USES(REGNO) \
2099 (!TARGET_FLAT && REGNO == 31)
2101 /* Length in units of the trampoline for entering a nested function. */
2103 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
2105 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
2107 /* Emit RTL insns to initialize the variable parts of a trampoline.
2108 FNADDR is an RTX for the address of the function's pure code.
2109 CXT is an RTX for the static chain value for the function. */
2111 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2112 if (TARGET_ARCH64) \
2113 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
2115 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
2117 /* Generate necessary RTL for __builtin_saveregs(). */
2119 #define EXPAND_BUILTIN_SAVEREGS() sparc_builtin_saveregs ()
2121 /* Implement `va_start' for varargs and stdarg. */
2122 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2123 sparc_va_start (stdarg, valist, nextarg)
2125 /* Implement `va_arg'. */
2126 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2127 sparc_va_arg (valist, type)
2129 /* Define this macro if the location where a function argument is passed
2130 depends on whether or not it is a named argument.
2132 This macro controls how the NAMED argument to FUNCTION_ARG
2133 is set for varargs and stdarg functions. With this macro defined,
2134 the NAMED argument is always true for named arguments, and false for
2135 unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS
2136 is defined, then all arguments are treated as named. Otherwise, all named
2137 arguments except the last are treated as named.
2138 For the v9 we want NAMED to mean what it says it means. */
2140 #define STRICT_ARGUMENT_NAMING TARGET_V9
2142 /* We do not allow sibling calls if -mflat, nor
2143 we do not allow indirect calls to be optimized into sibling calls. */
2144 #define FUNCTION_OK_FOR_SIBCALL(DECL) (DECL && ! TARGET_FLAT)
2146 /* Generate RTL to flush the register windows so as to make arbitrary frames
2148 #define SETUP_FRAME_ADDRESSES() \
2149 emit_insn (gen_flush_register_windows ())
2151 /* Given an rtx for the address of a frame,
2152 return an rtx for the address of the word in the frame
2153 that holds the dynamic chain--the previous frame's address.
2154 ??? -mflat support? */
2155 #define DYNAMIC_CHAIN_ADDRESS(frame) plus_constant (frame, 14 * UNITS_PER_WORD)
2157 /* The return address isn't on the stack, it is in a register, so we can't
2158 access it from the current frame pointer. We can access it from the
2159 previous frame pointer though by reading a value from the register window
2161 #define RETURN_ADDR_IN_PREVIOUS_FRAME
2163 /* This is the offset of the return address to the true next instruction to be
2164 executed for the current function. */
2165 #define RETURN_ADDR_OFFSET \
2166 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
2168 /* The current return address is in %i7. The return address of anything
2169 farther back is in the register window save area at [%fp+60]. */
2170 /* ??? This ignores the fact that the actual return address is +8 for normal
2171 returns, and +12 for structure returns. */
2172 #define RETURN_ADDR_RTX(count, frame) \
2174 ? gen_rtx_REG (Pmode, 31) \
2175 : gen_rtx_MEM (Pmode, \
2176 memory_address (Pmode, plus_constant (frame, \
2177 15 * UNITS_PER_WORD))))
2179 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
2180 +12, but always using +8 is close enough for frame unwind purposes.
2181 Actually, just using %o7 is close enough for unwinding, but %o7+8
2182 is something you can return to. */
2183 #define INCOMING_RETURN_ADDR_RTX \
2184 plus_constant (gen_rtx_REG (word_mode, 15), 8)
2185 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
2187 /* The offset from the incoming value of %sp to the top of the stack frame
2188 for the current function. On sparc64, we have to account for the stack
2190 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
2192 #define DOESNT_NEED_UNWINDER (! TARGET_FLAT)
2194 /* Addressing modes, and classification of registers for them. */
2196 /* #define HAVE_POST_INCREMENT 0 */
2197 /* #define HAVE_POST_DECREMENT 0 */
2199 /* #define HAVE_PRE_DECREMENT 0 */
2200 /* #define HAVE_PRE_INCREMENT 0 */
2202 /* Macros to check register numbers against specific register classes. */
2204 /* These assume that REGNO is a hard or pseudo reg number.
2205 They give nonzero only if REGNO is a hard reg of the suitable class
2206 or a pseudo reg currently allocated to a suitable hard reg.
2207 Since they use reg_renumber, they are safe only once reg_renumber
2208 has been allocated, which happens in local-alloc.c. */
2210 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2211 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32)
2212 #define REGNO_OK_FOR_BASE_P(REGNO) \
2213 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32)
2214 #define REGNO_OK_FOR_FP_P(REGNO) \
2215 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
2216 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
2217 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2219 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
2220 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
2222 /* Now macros that check whether X is a register and also,
2223 strictly, whether it is in a specified class.
2225 These macros are specific to the SPARC, and may be used only
2226 in code for printing assembler insns and in conditions for
2227 define_optimization. */
2229 /* 1 if X is an fp register. */
2231 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2233 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
2234 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
2236 /* Maximum number of registers that can appear in a valid memory address. */
2238 #define MAX_REGS_PER_ADDRESS 2
2240 /* Recognize any constant value that is a valid address.
2241 When PIC, we do not accept an address that would require a scratch reg
2242 to load into a register. */
2244 #define CONSTANT_ADDRESS_P(X) \
2245 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2246 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2247 || (GET_CODE (X) == CONST \
2248 && ! (flag_pic && pic_address_needs_scratch (X))))
2250 /* Define this, so that when PIC, reload won't try to reload invalid
2251 addresses which require two reload registers. */
2253 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2255 /* Nonzero if the constant value X is a legitimate general operand.
2256 Anything can be made to work except floating point constants.
2257 If TARGET_VIS, 0.0 can be made to work as well. */
2259 #define LEGITIMATE_CONSTANT_P(X) \
2260 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || \
2262 (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode || \
2263 GET_MODE (X) == TFmode) && \
2264 fp_zero_operand (X, GET_MODE (X))))
2266 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2267 and check its validity for a certain class.
2268 We have two alternate definitions for each of them.
2269 The usual definition accepts all pseudo regs; the other rejects
2270 them unless they have been allocated suitable hard regs.
2271 The symbol REG_OK_STRICT causes the latter definition to be used.
2273 Most source files want to accept pseudo regs in the hope that
2274 they will get allocated to the class that the insn wants them to be in.
2275 Source files for reload pass need to be strict.
2276 After reload, it makes no difference, since pseudo regs have
2277 been eliminated by then. */
2279 /* Optional extra constraints for this machine.
2281 'Q' handles floating point constants which can be moved into
2282 an integer register with a single sethi instruction.
2284 'R' handles floating point constants which can be moved into
2285 an integer register with a single mov instruction.
2287 'S' handles floating point constants which can be moved into
2288 an integer register using a high/lo_sum sequence.
2290 'T' handles memory addresses where the alignment is known to
2291 be at least 8 bytes.
2293 `U' handles all pseudo registers or a hard even numbered
2294 integer register, needed for ldd/std instructions. */
2296 #define EXTRA_CONSTRAINT_BASE(OP, C) \
2297 ((C) == 'Q' ? fp_sethi_p(OP) \
2298 : (C) == 'R' ? fp_mov_p(OP) \
2299 : (C) == 'S' ? fp_high_losum_p(OP) \
2302 #ifndef REG_OK_STRICT
2304 /* Nonzero if X is a hard reg that can be used as an index
2305 or if it is a pseudo reg. */
2306 #define REG_OK_FOR_INDEX_P(X) \
2307 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
2308 /* Nonzero if X is a hard reg that can be used as a base reg
2309 or if it is a pseudo reg. */
2310 #define REG_OK_FOR_BASE_P(X) \
2311 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
2313 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64. */
2315 #define EXTRA_CONSTRAINT(OP, C) \
2316 (EXTRA_CONSTRAINT_BASE(OP, C) \
2317 || ((! TARGET_ARCH64 && (C) == 'T') \
2318 ? (mem_min_alignment (OP, 8)) \
2319 : ((! TARGET_ARCH64 && (C) == 'U') \
2320 ? (register_ok_for_ldd (OP)) \
2325 /* Nonzero if X is a hard reg that can be used as an index. */
2326 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2327 /* Nonzero if X is a hard reg that can be used as a base reg. */
2328 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2330 #define EXTRA_CONSTRAINT(OP, C) \
2331 (EXTRA_CONSTRAINT_BASE(OP, C) \
2332 || ((! TARGET_ARCH64 && (C) == 'T') \
2333 ? mem_min_alignment (OP, 8) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
2334 : ((! TARGET_ARCH64 && (C) == 'U') \
2335 ? (GET_CODE (OP) == REG \
2336 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
2337 || reg_renumber[REGNO (OP)] >= 0) \
2338 && register_ok_for_ldd (OP)) \
2343 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
2345 #ifdef HAVE_AS_OFFSETABLE_LO10
2346 #define USE_AS_OFFSETABLE_LO10 1
2348 #define USE_AS_OFFSETABLE_LO10 0
2351 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2352 that is a valid memory address for an instruction.
2353 The MODE argument is the machine mode for the MEM expression
2354 that wants to use this address.
2356 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2357 ordinarily. This changes a bit when generating PIC.
2359 If you change this, execute "rm explow.o recog.o reload.o". */
2361 #define RTX_OK_FOR_BASE_P(X) \
2362 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2363 || (GET_CODE (X) == SUBREG \
2364 && GET_CODE (SUBREG_REG (X)) == REG \
2365 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2367 #define RTX_OK_FOR_INDEX_P(X) \
2368 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2369 || (GET_CODE (X) == SUBREG \
2370 && GET_CODE (SUBREG_REG (X)) == REG \
2371 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2373 #define RTX_OK_FOR_OFFSET_P(X) \
2374 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
2376 #define RTX_OK_FOR_OLO10_P(X) \
2377 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
2379 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2380 { if (RTX_OK_FOR_BASE_P (X)) \
2382 else if (GET_CODE (X) == PLUS) \
2384 register rtx op0 = XEXP (X, 0); \
2385 register rtx op1 = XEXP (X, 1); \
2386 if (flag_pic && op0 == pic_offset_table_rtx) \
2388 if (RTX_OK_FOR_BASE_P (op1)) \
2390 else if (flag_pic == 1 \
2391 && GET_CODE (op1) != REG \
2392 && GET_CODE (op1) != LO_SUM \
2393 && GET_CODE (op1) != MEM \
2394 && (GET_CODE (op1) != CONST_INT \
2395 || SMALL_INT (op1))) \
2398 else if (RTX_OK_FOR_BASE_P (op0)) \
2400 if ((RTX_OK_FOR_INDEX_P (op1) \
2401 /* We prohibit REG + REG for TFmode when \
2402 there are no instructions which accept \
2403 REG+REG instructions. We do this \
2404 because REG+REG is not an offsetable \
2405 address. If we get the situation \
2406 in reload where source and destination \
2407 of a movtf pattern are both MEMs with \
2408 REG+REG address, then only one of them \
2409 gets converted to an offsetable \
2411 && (MODE != TFmode \
2412 || (TARGET_FPU && TARGET_ARCH64 \
2414 && TARGET_HARD_QUAD)) \
2415 /* We prohibit REG + REG on ARCH32 if \
2416 not optimizing for DFmode/DImode \
2417 because then mem_min_alignment is \
2418 likely to be zero after reload and the \
2419 forced split would lack a matching \
2420 splitter pattern. */ \
2421 && (TARGET_ARCH64 || optimize \
2422 || (MODE != DFmode \
2423 && MODE != DImode))) \
2424 || RTX_OK_FOR_OFFSET_P (op1)) \
2427 else if (RTX_OK_FOR_BASE_P (op1)) \
2429 if ((RTX_OK_FOR_INDEX_P (op0) \
2430 /* See the previous comment. */ \
2431 && (MODE != TFmode \
2432 || (TARGET_FPU && TARGET_ARCH64 \
2434 && TARGET_HARD_QUAD)) \
2435 && (TARGET_ARCH64 || optimize \
2436 || (MODE != DFmode \
2437 && MODE != DImode))) \
2438 || RTX_OK_FOR_OFFSET_P (op0)) \
2441 else if (USE_AS_OFFSETABLE_LO10 \
2442 && GET_CODE (op0) == LO_SUM \
2444 && ! TARGET_CM_MEDMID \
2445 && RTX_OK_FOR_OLO10_P (op1)) \
2447 register rtx op00 = XEXP (op0, 0); \
2448 register rtx op01 = XEXP (op0, 1); \
2449 if (RTX_OK_FOR_BASE_P (op00) \
2450 && CONSTANT_P (op01)) \
2453 else if (USE_AS_OFFSETABLE_LO10 \
2454 && GET_CODE (op1) == LO_SUM \
2456 && ! TARGET_CM_MEDMID \
2457 && RTX_OK_FOR_OLO10_P (op0)) \
2459 register rtx op10 = XEXP (op1, 0); \
2460 register rtx op11 = XEXP (op1, 1); \
2461 if (RTX_OK_FOR_BASE_P (op10) \
2462 && CONSTANT_P (op11)) \
2466 else if (GET_CODE (X) == LO_SUM) \
2468 register rtx op0 = XEXP (X, 0); \
2469 register rtx op1 = XEXP (X, 1); \
2470 if (RTX_OK_FOR_BASE_P (op0) \
2471 && CONSTANT_P (op1) \
2472 /* We can't allow TFmode, because an offset \
2473 greater than or equal to the alignment (8) \
2474 may cause the LO_SUM to overflow if !v9. */\
2475 && (MODE != TFmode || TARGET_V9)) \
2478 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
2482 /* Try machine-dependent ways of modifying an illegitimate address
2483 to be legitimate. If we find one, return the new, valid address.
2484 This macro is used in only one place: `memory_address' in explow.c.
2486 OLDX is the address as it was before break_out_memory_refs was called.
2487 In some cases it is useful to look at this to decide what needs to be done.
2489 MODE and WIN are passed so that this macro can use
2490 GO_IF_LEGITIMATE_ADDRESS.
2492 It is always safe for this macro to do nothing. It exists to recognize
2493 opportunities to optimize the output. */
2495 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2496 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2497 { rtx sparc_x = (X); \
2498 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
2499 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2500 force_operand (XEXP (X, 0), NULL_RTX)); \
2501 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
2502 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2503 force_operand (XEXP (X, 1), NULL_RTX)); \
2504 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
2505 (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
2507 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
2508 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2509 force_operand (XEXP (X, 1), NULL_RTX)); \
2510 if (sparc_x != (X) && memory_address_p (MODE, X)) \
2512 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
2513 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
2514 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2515 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
2516 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
2517 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2518 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
2519 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
2520 || GET_CODE (X) == LABEL_REF) \
2521 (X) = copy_to_suggested_reg (X, NULL_RTX, Pmode); \
2522 if (memory_address_p (MODE, X)) \
2525 /* Try a machine-dependent way of reloading an illegitimate address
2526 operand. If we find one, push the reload and jump to WIN. This
2527 macro is used in only one place: `find_reloads_address' in reload.c.
2529 For Sparc 32, we wish to handle addresses by splitting them into
2530 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2531 This cuts the number of extra insns by one.
2533 Do nothing when generating PIC code and the address is a
2534 symbolic operand or requires a scratch register. */
2536 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2538 /* Decompose SImode constants into hi+lo_sum. We do have to \
2539 rerecognize what we produce, so be careful. */ \
2540 if (CONSTANT_P (X) \
2541 && (MODE != TFmode || TARGET_V9) \
2542 && GET_MODE (X) == SImode \
2543 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2545 && (symbolic_operand (X, Pmode) \
2546 || pic_address_needs_scratch (X)))) \
2548 X = gen_rtx_LO_SUM (GET_MODE (X), \
2549 gen_rtx_HIGH (GET_MODE (X), X), X); \
2550 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
2551 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2555 /* ??? 64-bit reloads. */ \
2558 /* Go to LABEL if ADDR (a legitimate address expression)
2559 has an effect that depends on the machine mode it is used for.
2560 On the SPARC this is never true. */
2562 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2564 /* If we are referencing a function make the SYMBOL_REF special.
2565 In the Embedded Medium/Anywhere code model, %g4 points to the data segment
2566 so we must not add it to function addresses. */
2568 #define ENCODE_SECTION_INFO(DECL) \
2570 if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
2571 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2574 /* Specify the machine mode that this machine uses
2575 for the index in the tablejump instruction. */
2576 /* If we ever implement any of the full models (such as CM_FULLANY),
2577 this has to be DImode in that case */
2578 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2579 #define CASE_VECTOR_MODE \
2580 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2582 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2583 we have to sign extend which slows things down. */
2584 #define CASE_VECTOR_MODE \
2585 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2588 /* Define as C expression which evaluates to nonzero if the tablejump
2589 instruction expects the table to contain offsets from the address of the
2591 Do not define this if the table should contain absolute addresses. */
2592 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2594 /* Specify the tree operation to be used to convert reals to integers. */
2595 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2597 /* This is the kind of divide that is easiest to do in the general case. */
2598 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2600 /* Define this as 1 if `char' should by default be signed; else as 0. */
2601 #define DEFAULT_SIGNED_CHAR 1
2603 /* Max number of bytes we can move from memory to memory
2604 in one reasonably fast instruction. */
2607 #if 0 /* Sun 4 has matherr, so this is no good. */
2608 /* This is the value of the error code EDOM for this machine,
2609 used by the sqrt instruction. */
2610 #define TARGET_EDOM 33
2612 /* This is how to refer to the variable errno. */
2613 #define GEN_ERRNO_RTX \
2614 gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno"))
2617 /* Define if operations between registers always perform the operation
2618 on the full register even if a narrower mode is specified. */
2619 #define WORD_REGISTER_OPERATIONS
2621 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2622 will either zero-extend or sign-extend. The value of this macro should
2623 be the code that says which one of the two operations is implicitly
2624 done, NIL if none. */
2625 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2627 /* Nonzero if access to memory by bytes is slow and undesirable.
2628 For RISC chips, it means that access to memory by bytes is no
2629 better than access by words when possible, so grab a whole word
2630 and maybe make use of that. */
2631 #define SLOW_BYTE_ACCESS 1
2633 /* We assume that the store-condition-codes instructions store 0 for false
2634 and some other value for true. This is the value stored for true. */
2636 #define STORE_FLAG_VALUE 1
2638 /* When a prototype says `char' or `short', really pass an `int'. */
2639 #define PROMOTE_PROTOTYPES (TARGET_ARCH32)
2641 /* Define this to be nonzero if shift instructions ignore all but the low-order
2643 #define SHIFT_COUNT_TRUNCATED 1
2645 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2646 is done just by pretending it is already truncated. */
2647 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2649 /* Specify the machine mode that pointers have.
2650 After generation of rtl, the compiler makes no further distinction
2651 between pointers and any other objects of this machine mode. */
2652 #define Pmode (TARGET_PTR64 ? DImode : SImode)
2654 /* Generate calls to memcpy, memcmp and memset. */
2655 #define TARGET_MEM_FUNCTIONS
2657 /* Add any extra modes needed to represent the condition code.
2659 On the Sparc, we have a "no-overflow" mode which is used when an add or
2660 subtract insn is used to set the condition code. Different branches are
2661 used in this case for some operations.
2663 We also have two modes to indicate that the relevant condition code is
2664 in the floating-point condition code register. One for comparisons which
2665 will generate an exception if the result is unordered (CCFPEmode) and
2666 one for comparisons which will never trap (CCFPmode).
2668 CCXmode and CCX_NOOVmode are only used by v9. */
2670 #define EXTRA_CC_MODES \
2671 CC(CCXmode, "CCX") \
2672 CC(CC_NOOVmode, "CC_NOOV") \
2673 CC(CCX_NOOVmode, "CCX_NOOV") \
2674 CC(CCFPmode, "CCFP") \
2675 CC(CCFPEmode, "CCFPE")
2677 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2678 return the mode to be used for the comparison. For floating-point,
2679 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2680 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2681 processing is needed. */
2682 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2684 /* Return non-zero if MODE implies a floating point inequality can be
2685 reversed. For Sparc this is always true because we have a full
2686 compliment of ordered and unordered comparisons, but until generic
2687 code knows how to reverse it correctly we keep the old definition. */
2688 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2690 /* A function address in a call instruction
2691 is a byte address (for indexing purposes)
2692 so give the MEM rtx a byte's mode. */
2693 #define FUNCTION_MODE SImode
2695 /* Define this if addresses of constant functions
2696 shouldn't be put through pseudo regs where they can be cse'd.
2697 Desirable on machines where ordinary constants are expensive
2698 but a CALL with constant address is cheap. */
2699 #define NO_FUNCTION_CSE
2701 /* alloca should avoid clobbering the old register save area. */
2702 #define SETJMP_VIA_SAVE_AREA
2704 /* Define subroutines to call to handle multiply and divide.
2705 Use the subroutines that Sun's library provides.
2706 The `*' prevents an underscore from being prepended by the compiler. */
2708 #define DIVSI3_LIBCALL "*.div"
2709 #define UDIVSI3_LIBCALL "*.udiv"
2710 #define MODSI3_LIBCALL "*.rem"
2711 #define UMODSI3_LIBCALL "*.urem"
2712 /* .umul is a little faster than .mul. */
2713 #define MULSI3_LIBCALL "*.umul"
2715 /* Define library calls for quad FP operations. These are all part of the
2717 #define ADDTF3_LIBCALL "_Q_add"
2718 #define SUBTF3_LIBCALL "_Q_sub"
2719 #define NEGTF2_LIBCALL "_Q_neg"
2720 #define MULTF3_LIBCALL "_Q_mul"
2721 #define DIVTF3_LIBCALL "_Q_div"
2722 #define FLOATSITF2_LIBCALL "_Q_itoq"
2723 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2724 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2725 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2726 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2727 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2728 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2729 #define EQTF2_LIBCALL "_Q_feq"
2730 #define NETF2_LIBCALL "_Q_fne"
2731 #define GTTF2_LIBCALL "_Q_fgt"
2732 #define GETF2_LIBCALL "_Q_fge"
2733 #define LTTF2_LIBCALL "_Q_flt"
2734 #define LETF2_LIBCALL "_Q_fle"
2736 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
2737 with soft-float, the SFmode and DFmode sqrt instructions will be absent,
2738 and the compiler will notice and try to use the TFmode sqrt instruction
2739 for calls to the builtin function sqrt, but this fails. */
2740 #define INIT_TARGET_OPTABS \
2742 if (TARGET_ARCH32) \
2744 add_optab->handlers[(int) TFmode].libfunc \
2745 = init_one_libfunc (ADDTF3_LIBCALL); \
2746 sub_optab->handlers[(int) TFmode].libfunc \
2747 = init_one_libfunc (SUBTF3_LIBCALL); \
2748 neg_optab->handlers[(int) TFmode].libfunc \
2749 = init_one_libfunc (NEGTF2_LIBCALL); \
2750 smul_optab->handlers[(int) TFmode].libfunc \
2751 = init_one_libfunc (MULTF3_LIBCALL); \
2752 flodiv_optab->handlers[(int) TFmode].libfunc \
2753 = init_one_libfunc (DIVTF3_LIBCALL); \
2754 eqtf2_libfunc = init_one_libfunc (EQTF2_LIBCALL); \
2755 netf2_libfunc = init_one_libfunc (NETF2_LIBCALL); \
2756 gttf2_libfunc = init_one_libfunc (GTTF2_LIBCALL); \
2757 getf2_libfunc = init_one_libfunc (GETF2_LIBCALL); \
2758 lttf2_libfunc = init_one_libfunc (LTTF2_LIBCALL); \
2759 letf2_libfunc = init_one_libfunc (LETF2_LIBCALL); \
2760 trunctfsf2_libfunc = init_one_libfunc (TRUNCTFSF2_LIBCALL); \
2761 trunctfdf2_libfunc = init_one_libfunc (TRUNCTFDF2_LIBCALL); \
2762 extendsftf2_libfunc = init_one_libfunc (EXTENDSFTF2_LIBCALL); \
2763 extenddftf2_libfunc = init_one_libfunc (EXTENDDFTF2_LIBCALL); \
2764 floatsitf_libfunc = init_one_libfunc (FLOATSITF2_LIBCALL); \
2765 fixtfsi_libfunc = init_one_libfunc (FIX_TRUNCTFSI2_LIBCALL); \
2766 fixunstfsi_libfunc \
2767 = init_one_libfunc (FIXUNS_TRUNCTFSI2_LIBCALL); \
2769 sqrt_optab->handlers[(int) TFmode].libfunc \
2770 = init_one_libfunc ("_Q_sqrt"); \
2772 INIT_SUBTARGET_OPTABS; \
2775 /* This is meant to be redefined in the host dependent files */
2776 #define INIT_SUBTARGET_OPTABS
2778 /* Nonzero if a floating point comparison library call for
2779 mode MODE that will return a boolean value. Zero if one
2780 of the libgcc2 functions is used. */
2781 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2783 /* Compute the cost of computing a constant rtl expression RTX
2784 whose rtx-code is CODE. The body of this macro is a portion
2785 of a switch statement. If the code is computed here,
2786 return it with a return statement. Otherwise, break from the switch. */
2788 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2790 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
2798 case CONST_DOUBLE: \
2799 if (GET_MODE (RTX) == DImode) \
2800 if ((XINT (RTX, 3) == 0 \
2801 && (unsigned) XINT (RTX, 2) < 0x1000) \
2802 || (XINT (RTX, 3) == -1 \
2803 && XINT (RTX, 2) < 0 \
2804 && XINT (RTX, 2) >= -0x1000)) \
2808 #define ADDRESS_COST(RTX) 1
2810 /* Compute extra cost of moving data between one register class
2812 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2813 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
2814 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2815 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2816 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2817 ? (sparc_cpu == PROCESSOR_ULTRASPARC ? 12 : 6) : 2)
2819 /* Provide the costs of a rtl expression. This is in the body of a
2820 switch on CODE. The purpose for the cost of MULT is to encourage
2821 `synth_mult' to find a synthetic multiply when reasonable.
2823 If we need more than 12 insns to do a multiply, then go out-of-line,
2824 since the call overhead will be < 10% of the cost of the multiply. */
2826 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2828 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2829 return (GET_MODE (X) == DImode ? \
2830 COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); \
2831 return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
2836 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2837 return (GET_MODE (X) == DImode ? \
2838 COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); \
2839 return COSTS_N_INSNS (25); \
2840 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
2841 so that cse will favor the latter. */ \
2846 #define ISSUE_RATE sparc_issue_rate()
2848 /* Adjust the cost of dependencies. */
2849 #define ADJUST_COST(INSN,LINK,DEP,COST) \
2850 (COST) = sparc_adjust_cost(INSN, LINK, DEP, COST)
2852 #define MD_SCHED_INIT(DUMP, SCHED_VERBOSE) \
2853 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2854 ultrasparc_sched_init (DUMP, SCHED_VERBOSE)
2856 #define MD_SCHED_REORDER(DUMP, SCHED_VERBOSE, READY, N_READY, CLOCK, CIM) \
2858 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2859 ultrasparc_sched_reorder (DUMP, SCHED_VERBOSE, READY, N_READY); \
2863 #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
2865 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2866 (CAN_ISSUE_MORE) = ultrasparc_variable_issue (INSN); \
2868 (CAN_ISSUE_MORE)--; \
2871 /* Conditional branches with empty delay slots have a length of two. */
2872 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2874 if (GET_CODE (INSN) == CALL_INSN \
2875 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
2879 /* Control the assembler format that we output. */
2881 /* Output at beginning of assembler file. */
2883 #define ASM_FILE_START(file)
2885 /* A C string constant describing how to begin a comment in the target
2886 assembler language. The compiler assumes that the comment will end at
2887 the end of the line. */
2889 #define ASM_COMMENT_START "!"
2891 /* Output to assembler file text saying following lines
2892 may contain character constants, extra white space, comments, etc. */
2894 #define ASM_APP_ON ""
2896 /* Output to assembler file text saying following lines
2897 no longer contain unusual constructs. */
2899 #define ASM_APP_OFF ""
2901 /* ??? Try to make the style consistent here (_OP?). */
2903 #define ASM_LONGLONG ".xword"
2904 #define ASM_LONG ".word"
2905 #define ASM_SHORT ".half"
2906 #define ASM_BYTE_OP ".byte"
2907 #define ASM_FLOAT ".single"
2908 #define ASM_DOUBLE ".double"
2909 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2911 /* Output before read-only data. */
2913 #define TEXT_SECTION_ASM_OP ".text"
2915 /* Output before writable data. */
2917 #define DATA_SECTION_ASM_OP ".data"
2919 /* How to refer to registers in assembler output.
2920 This sequence is indexed by compiler's hard-register-number (see above). */
2922 #define REGISTER_NAMES \
2923 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2924 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2925 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2926 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2927 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2928 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2929 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2930 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2931 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2932 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2933 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2934 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2935 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc"}
2937 /* Define additional names for use in asm clobbers and asm declarations. */
2939 #define ADDITIONAL_REGISTER_NAMES \
2940 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2942 /* How to renumber registers for dbx and gdb. In the flat model, the frame
2943 pointer is really %i7. */
2945 #define DBX_REGISTER_NUMBER(REGNO) \
2946 (TARGET_FLAT && REGNO == FRAME_POINTER_REGNUM ? 31 : REGNO)
2948 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2949 can run past this up to a continuation point. Once we used 1500, but
2950 a single entry in C++ can run more than 500 bytes, due to the length of
2951 mangled symbol names. dbxout.c should really be fixed to do
2952 continuations when they are actually needed instead of trying to
2954 #define DBX_CONTIN_LENGTH 1000
2956 /* This is how to output a note to DBX telling it the line number
2957 to which the following sequence of instructions corresponds.
2959 This is needed for SunOS 4.0, and should not hurt for 3.2
2961 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
2962 { static int sym_lineno = 1; \
2963 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
2964 line, sym_lineno, sym_lineno); \
2967 /* This is how to output the definition of a user-level label named NAME,
2968 such as the label on a static function or variable NAME. */
2970 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2971 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2973 /* This is how to output a command to make the user-level label named NAME
2974 defined for reference from other files. */
2976 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2977 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2979 /* The prefix to add to user-visible assembler symbols. */
2981 #define USER_LABEL_PREFIX "_"
2983 /* This is how to output a definition of an internal numbered label where
2984 PREFIX is the class of label and NUM is the number within the class. */
2986 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2987 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2989 /* This is how to store into the string LABEL
2990 the symbol_ref name of an internal numbered label where
2991 PREFIX is the class of label and NUM is the number within the class.
2992 This is suitable for output with `assemble_name'. */
2994 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2995 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2997 /* This is how to output an assembler line defining a `float' constant.
2998 We always have to use a .long pseudo-op to do this because the native
2999 SVR4 ELF assembler is buggy and it generates incorrect values when we
3000 try to use the .float pseudo-op instead. */
3002 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
3006 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
3007 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
3008 fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t, \
3009 ASM_COMMENT_START, str); \
3012 /* This is how to output an assembler line defining a `double' constant.
3013 We always have to use a .long pseudo-op to do this because the native
3014 SVR4 ELF assembler is buggy and it generates incorrect values when we
3015 try to use the .float pseudo-op instead. */
3017 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
3021 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
3022 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
3023 fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0], \
3024 ASM_COMMENT_START, str); \
3025 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]); \
3028 /* This is how to output an assembler line defining a `long double'
3031 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
3035 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
3036 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
3037 fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0], \
3038 ASM_COMMENT_START, str); \
3039 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]); \
3040 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[2]); \
3041 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[3]); \
3044 /* This is how to output an assembler line defining an `int' constant. */
3046 #define ASM_OUTPUT_INT(FILE,VALUE) \
3047 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
3048 output_addr_const (FILE, (VALUE)), \
3049 fprintf (FILE, "\n"))
3051 /* This is how to output an assembler line defining a DImode constant. */
3052 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
3053 output_double_int (FILE, VALUE)
3055 /* Likewise for `char' and `short' constants. */
3057 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
3058 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
3059 output_addr_const (FILE, (VALUE)), \
3060 fprintf (FILE, "\n"))
3062 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
3063 ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
3064 output_addr_const (FILE, (VALUE)), \
3065 fprintf (FILE, "\n"))
3067 /* This is how to output an assembler line for a numeric constant byte. */
3069 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
3070 fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
3072 /* This is how we hook in and defer the case-vector until the end of
3074 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
3075 sparc_defer_case_vector ((LAB),(VEC), 0)
3077 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
3078 sparc_defer_case_vector ((LAB),(VEC), 1)
3080 /* This is how to output an element of a case-vector that is absolute. */
3082 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
3085 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
3086 if (CASE_VECTOR_MODE == SImode) \
3087 fprintf (FILE, "\t.word\t"); \
3089 fprintf (FILE, "\t.xword\t"); \
3090 assemble_name (FILE, label); \
3091 fputc ('\n', FILE); \
3094 /* This is how to output an element of a case-vector that is relative.
3095 (SPARC uses such vectors only when generating PIC.) */
3097 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
3100 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
3101 if (CASE_VECTOR_MODE == SImode) \
3102 fprintf (FILE, "\t.word\t"); \
3104 fprintf (FILE, "\t.xword\t"); \
3105 assemble_name (FILE, label); \
3106 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
3107 fputc ('-', FILE); \
3108 assemble_name (FILE, label); \
3109 fputc ('\n', FILE); \
3112 /* This is what to output before and after case-vector (both
3113 relative and absolute). If .subsection -1 works, we put case-vectors
3114 at the beginning of the current section. */
3116 #ifdef HAVE_GAS_SUBSECTION_ORDERING
3118 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
3119 fprintf(FILE, "\t.subsection\t-1\n")
3121 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
3122 fprintf(FILE, "\t.previous\n")
3126 /* This is how to output an assembler line
3127 that says to advance the location counter
3128 to a multiple of 2**LOG bytes. */
3130 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3132 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
3134 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
3135 fprintf (FILE, "\t.skip %u\n", (SIZE))
3137 /* This says how to output an assembler line
3138 to define a global common symbol. */
3140 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
3141 ( fputs ("\t.common ", (FILE)), \
3142 assemble_name ((FILE), (NAME)), \
3143 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
3145 /* This says how to output an assembler line to define a local common
3148 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
3149 ( fputs ("\t.reserve ", (FILE)), \
3150 assemble_name ((FILE), (NAME)), \
3151 fprintf ((FILE), ",%u,\"bss\",%u\n", \
3152 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
3154 /* A C statement (sans semicolon) to output to the stdio stream
3155 FILE the assembler definition of uninitialized global DECL named
3156 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
3157 Try to use asm_output_aligned_bss to implement this macro. */
3159 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
3161 fputs (".globl ", (FILE)); \
3162 assemble_name ((FILE), (NAME)); \
3163 fputs ("\n", (FILE)); \
3164 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
3167 /* Store in OUTPUT a string (made with alloca) containing
3168 an assembler-name for a local static variable named NAME.
3169 LABELNO is an integer which is different for each call. */
3171 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
3172 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
3173 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
3175 #define IDENT_ASM_OP ".ident"
3177 /* Output #ident as a .ident. */
3179 #define ASM_OUTPUT_IDENT(FILE, NAME) \
3180 fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
3182 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
3183 Used for C++ multiple inheritance. */
3184 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
3186 int big_delta = (DELTA) >= 4096 || (DELTA) < -4096; \
3188 fprintf (FILE, "\tset %d,%%g1\n\tadd %%o0,%%g1,%%o0\n", (DELTA)); \
3189 /* Don't use the jmp solution unless we know the target is local to \
3190 the application or shared object. \
3191 XXX: Wimp out and don't actually check anything except if this is \
3192 an embedded target where we assume there are no shared libs. */ \
3193 if (!TARGET_CM_EMBMEDANY || flag_pic) \
3196 fprintf (FILE, "\tadd %%o0,%d,%%o0\n", DELTA); \
3197 fprintf (FILE, "\tmov %%o7,%%g1\n"); \
3198 fprintf (FILE, "\tcall "); \
3199 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
3200 fprintf (FILE, ",0\n"); \
3202 else if (TARGET_CM_EMBMEDANY) \
3204 fprintf (FILE, "\tsetx "); \
3205 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
3206 fprintf (FILE, ",%%g5,%%g1\n\tjmp %%g1\n"); \
3210 fprintf (FILE, "\tsethi %%hi("); \
3211 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
3212 fprintf (FILE, "),%%g1\n\tjmp %%g1+%%lo("); \
3213 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
3214 fprintf (FILE, ")\n"); \
3216 if (!TARGET_CM_EMBMEDANY || flag_pic) \
3217 fprintf (FILE, "\tmov %%g1,%%o7\n"); \
3218 else if (big_delta) \
3219 fprintf (FILE, "\tnop\n"); \
3221 fprintf (FILE, "\tadd %%o0,%d,%%o0\n", DELTA); \
3224 /* Define the parentheses used to group arithmetic operations
3225 in assembler code. */
3227 #define ASM_OPEN_PAREN "("
3228 #define ASM_CLOSE_PAREN ")"
3230 /* Define results of standard character escape sequences. */
3231 #define TARGET_BELL 007
3232 #define TARGET_BS 010
3233 #define TARGET_TAB 011
3234 #define TARGET_NEWLINE 012
3235 #define TARGET_VT 013
3236 #define TARGET_FF 014
3237 #define TARGET_CR 015
3239 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3240 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
3242 /* Print operand X (an rtx) in assembler syntax to file FILE.
3243 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3244 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3246 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3248 /* Print a memory address as an operand to reference that memory location. */
3250 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
3251 { register rtx base, index = 0; \
3253 register rtx addr = ADDR; \
3254 if (GET_CODE (addr) == REG) \
3255 fputs (reg_names[REGNO (addr)], FILE); \
3256 else if (GET_CODE (addr) == PLUS) \
3258 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
3259 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
3260 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
3261 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
3263 base = XEXP (addr, 0), index = XEXP (addr, 1); \
3264 if (GET_CODE (base) == LO_SUM) \
3266 if (! USE_AS_OFFSETABLE_LO10 \
3268 || TARGET_CM_MEDMID) \
3270 output_operand (XEXP (base, 0), 0); \
3271 fputs ("+%lo(", FILE); \
3272 output_address (XEXP (base, 1)); \
3273 fprintf (FILE, ")+%d", offset); \
3277 fputs (reg_names[REGNO (base)], FILE); \
3279 fprintf (FILE, "%+d", offset); \
3280 else if (GET_CODE (index) == REG) \
3281 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
3282 else if (GET_CODE (index) == SYMBOL_REF \
3283 || GET_CODE (index) == CONST) \
3284 fputc ('+', FILE), output_addr_const (FILE, index); \
3288 else if (GET_CODE (addr) == MINUS \
3289 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
3291 output_addr_const (FILE, XEXP (addr, 0)); \
3292 fputs ("-(", FILE); \
3293 output_addr_const (FILE, XEXP (addr, 1)); \
3294 fputs ("-.)", FILE); \
3296 else if (GET_CODE (addr) == LO_SUM) \
3298 output_operand (XEXP (addr, 0), 0); \
3299 if (TARGET_CM_MEDMID) \
3300 fputs ("+%l44(", FILE); \
3302 fputs ("+%lo(", FILE); \
3303 output_address (XEXP (addr, 1)); \
3304 fputc (')', FILE); \
3306 else if (flag_pic && GET_CODE (addr) == CONST \
3307 && GET_CODE (XEXP (addr, 0)) == MINUS \
3308 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
3309 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
3310 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
3312 addr = XEXP (addr, 0); \
3313 output_addr_const (FILE, XEXP (addr, 0)); \
3314 /* Group the args of the second CONST in parenthesis. */ \
3315 fputs ("-(", FILE); \
3316 /* Skip past the second CONST--it does nothing for us. */\
3317 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
3318 /* Close the parenthesis. */ \
3319 fputc (')', FILE); \
3323 output_addr_const (FILE, addr); \
3327 /* Define the codes that are matched by predicates in sparc.c. */
3329 #define PREDICATE_CODES \
3330 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3331 {"fp_zero_operand", {CONST_DOUBLE}}, \
3332 {"fp_sethi_p", {CONST_DOUBLE}}, \
3333 {"fp_mov_p", {CONST_DOUBLE}}, \
3334 {"fp_high_losum_p", {CONST_DOUBLE}}, \
3335 {"intreg_operand", {SUBREG, REG}}, \
3336 {"fcc_reg_operand", {REG}}, \
3337 {"icc_or_fcc_reg_operand", {REG}}, \
3338 {"restore_operand", {REG}}, \
3339 {"call_operand", {MEM}}, \
3340 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
3341 ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
3342 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3343 {"symbolic_memory_operand", {SUBREG, MEM}}, \
3344 {"label_ref_operand", {LABEL_REF}}, \
3345 {"sp64_medium_pic_operand", {CONST}}, \
3346 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
3347 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
3348 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
3349 {"splittable_symbolic_memory_operand", {MEM}}, \
3350 {"splittable_immediate_memory_operand", {MEM}}, \
3351 {"eq_or_neq", {EQ, NE}}, \
3352 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
3353 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
3354 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
3355 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
3356 {"cc_arithop", {AND, IOR, XOR}}, \
3357 {"cc_arithopn", {AND, IOR}}, \
3358 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3359 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
3360 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
3361 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
3362 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3363 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3364 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3365 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3366 {"small_int", {CONST_INT}}, \
3367 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
3368 {"uns_small_int", {CONST_INT}}, \
3369 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
3370 {"clobbered_register", {REG}}, \
3371 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
3372 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
3373 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}},
3375 /* The number of Pmode words for the setjmp buffer. */
3376 #define JMP_BUF_SIZE 12
3378 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)
3380 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
3382 extern int flag_pic;
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