1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92, 94, 95, 1996 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions that relate to assembler syntax. */
27 /* Sparc64 support has been added by trying to allow for a day when one
28 compiler can handle both v8 and v9. There are a few cases where this
29 isn't doable, but keep them to a minimum!
31 TARGET_V9 is used to select at runtime the sparc64 chip.
32 TARGET_ARCH64 is used to select at runtime a 64 bit environment.
33 SPARC_V9 is defined as 0 or 1 (so it may be used inside and outside
34 #define's), and says whether the cpu is a sparc64 chip (which may be
35 running in a 32 or 64 bit environment).
36 SPARC_ARCH64 is defined as 0 for a 32 bit environment and 1 for a 64 bit
39 In places where it is possible to choose at runtime, use TARGET_V9 and
40 TARGET_ARCH64. In places where it is currently not possible to select
41 between the two at runtime use SPARC_{V9,ARCH64}. Again, keep uses of
42 SPARC_{V9,ARCH64} to a minimum. No attempt is made to support both v8
43 and v9 in the v9 compiler.
45 ??? All uses of SPARC_V9 have been removed. Try not to add new ones.
52 #define SPARC_ARCH64 0
55 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile. */
56 #define TARGET_CPU_sparc 0
57 #define TARGET_CPU_sparclet 1
58 #define TARGET_CPU_sparclite 2
59 #define TARGET_CPU_sparc64 3
61 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc
62 #define CPP_DEFAULT_SPEC ""
63 #define ASM_DEFAULT_SPEC ""
65 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
66 #define CPP_DEFAULT_SPEC "-D__sparclet__"
67 #define ASM_DEFAULT_SPEC "-Asparclet"
69 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
70 #define CPP_DEFAULT_SPEC "-D__sparclite__"
71 #define ASM_DEFAULT_SPEC "-Asparclite"
73 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc64
74 /* ??? What does Sun's CC pass? */
75 #define CPP_DEFAULT_SPEC "-D__sparc_v9__"
76 /* ??? It's not clear how other assemblers will handle this, so by default
77 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
78 is handled in sol2.h. */
79 #define ASM_DEFAULT_SPEC "-Av9"
81 Unrecognized value in TARGET_CPU_DEFAULT.
87 /* Names to predefine in the preprocessor for this target machine. */
89 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
90 the right varags.h file when bootstrapping. */
91 /* ??? It's not clear what value we want to use for -Acpu/machine for
92 sparc64 in 32 bit environments, so for now we only use `sparc64' in
93 64 bit environments. */
94 /* ??? __arch64__ is subject to change. */
97 #define CPP_PREDEFINES \
98 "-Dsparc -Dsun -Dunix -D__arch64__ \
99 -Asystem(unix) -Asystem(bsd) -Acpu(sparc64) -Amachine(sparc64)"
101 #define CPP_PREDEFINES \
102 "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \
103 -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)"
106 /* Define macros to distinguish architectures. */
110 %{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \
111 %{mlong64:-D__LONG_MAX__=9223372036854775807LL} \
114 #define CPP_SPEC "%(cpp_cpu)"
117 /* Common CPP definitions used by CPP_SPEC amongst the various targets
118 for handling -mcpu=xxx switches. */
119 /* ??? v8plus/v9/ultrasparc handling is tentative */
120 #define CPP_CPU_SPEC "\
122 %{msparclite:-D__sparclite__} \
123 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
124 %{mv8:-D__sparc_v8__} \
125 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
126 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
127 %{mcpu=sparclite:-D__sparclite__} \
128 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
129 %{mcpu=v8:-D__sparc_v8__} \
130 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
131 %{mcpu=v8plus:-D__sparc_v9__} \
132 %{mcpu=v9:-D__sparc_v9__} \
133 %{mcpu=ultrasparc:-D__sparc_v9__} \
134 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_default)}}}}}}} \
137 /* Prevent error on `-sun4' and `-target sun4' options. */
138 /* This used to translate -dalign to -malign, but that is no good
139 because it can't turn off the usual meaning of making debugging dumps. */
140 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
141 ??? Delete support for -m<cpu> for 2.9. */
144 %{sun4:} %{target:} \
145 %{mcypress:-mcpu=cypress} \
146 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
147 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
150 #define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}"
152 /* Provide required defaults for linker -e and -d switches. */
155 "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \
156 %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}"
158 /* Special flags to the Sun-4 assembler when using pipe for input. */
161 %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
165 /* Override in target specific files. */
166 #define ASM_CPU_SPEC "\
167 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
168 %{msparclite:-Asparclite} \
169 %{mf930:-Asparclite} %{mf934:-Asparclite} \
170 %{mcpu=sparclite:-Asparclite} \
171 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
172 %{mcpu=v8plus:-Av9} \
174 %{mcpu=ultrasparc:-Av9} \
175 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_default)}}}}}}} \
178 /* This macro defines names of additional specifications to put in the specs
179 that can be used in various specifications like CC1_SPEC. Its definition
180 is an initializer with a subgrouping for each command option.
182 Each subgrouping contains a string constant, that defines the
183 specification name, and a string constant that used by the GNU CC driver
186 Do not define this macro if it does not need to do anything. */
188 #define EXTRA_SPECS \
189 { "cpp_cpu", CPP_CPU_SPEC }, \
190 { "cpp_default", CPP_DEFAULT_SPEC }, \
191 { "asm_cpu", ASM_CPU_SPEC }, \
192 { "asm_default", ASM_DEFAULT_SPEC }, \
193 SUBTARGET_EXTRA_SPECS
195 #define SUBTARGET_EXTRA_SPECS
198 #define PTRDIFF_TYPE "long long int"
199 #define SIZE_TYPE "long long unsigned int"
201 #define PTRDIFF_TYPE "int"
202 /* The default value for SIZE_TYPE is "unsigned int" which is what we want. */
205 /* ??? This should be 32 bits for v9 but what can we do? */
206 #define WCHAR_TYPE "short unsigned int"
207 #define WCHAR_TYPE_SIZE 16
208 #define MAX_WCHAR_TYPE_SIZE 16
210 /* Show we can debug even without a frame pointer. */
211 #define CAN_DEBUG_WITHOUT_FP
213 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
214 code into the rtl. Also, if we are profiling, we cannot eliminate
215 the frame pointer (because the return address will get smashed). */
217 void sparc_override_options ();
219 #define OVERRIDE_OPTIONS \
221 if (profile_flag || profile_block_flag) \
225 char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC"; \
226 warning ("%s and profiling conflict: disabling %s", \
227 pic_string, pic_string); \
230 flag_omit_frame_pointer = 0; \
232 sparc_override_options (); \
233 SUBTARGET_OVERRIDE_OPTIONS; \
236 /* This is meant to be redefined in the host dependent files. */
237 #define SUBTARGET_OVERRIDE_OPTIONS
239 /* These compiler options take an argument. We ignore -target for now. */
241 #define WORD_SWITCH_TAKES_ARG(STR) \
242 (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
243 || !strcmp (STR, "target") || !strcmp (STR, "assert"))
245 /* Print subsidiary information on the compiler version in use. */
247 #define TARGET_VERSION fprintf (stderr, " (sparc)");
249 /* Generate DBX debugging information. */
251 #define DBX_DEBUGGING_INFO
253 /* Run-time compilation parameters selecting different hardware subsets. */
255 extern int target_flags;
257 /* Nonzero if we should generate code to use the fpu. */
259 #define TARGET_FPU (target_flags & MASK_FPU)
261 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
262 use fast return insns, but lose some generality. */
263 #define MASK_EPILOGUE 2
264 #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
266 /* Nonzero if we should assume that double pointers might be unaligned.
267 This can happen when linking gcc compiled code with other compilers,
268 because the ABI only guarantees 4 byte alignment. */
269 #define MASK_UNALIGNED_DOUBLES 4
270 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
272 /* Nonzero means that we should generate code for a v8 sparc. */
274 #define TARGET_V8 (target_flags & MASK_V8)
276 /* Nonzero means that we should generate code for a sparclite.
277 This enables the sparclite specific instructions, but does not affect
278 whether FPU instructions are emitted. */
279 #define MASK_SPARCLITE 0x10
280 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
282 /* Nonzero if we're compiling for the sparclet. */
283 #define MASK_SPARCLET 0x20
284 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
286 /* Nonzero if we're compiling for v9 sparc.
287 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
288 the word size is 64. */
290 #define TARGET_V9 (target_flags & MASK_V9)
292 /* Non-zero to generate code that uses the instructions deprecated in
293 the v9 architecture. This option only applies to v9 systems. */
294 /* ??? This isn't user selectable yet. It's used to enable such insns
295 on 32 bit v9 systems and for the moment they're permanently disabled
296 on 64 bit v9 systems. */
297 #define MASK_DEPRECATED_V8_INSNS 0x80
298 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
300 /* Mask of all CPU selection flags. */
302 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
304 /* Non-zero means don't pass `-assert pure-text' to the linker. */
305 #define MASK_IMPURE_TEXT 0x100
306 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
308 /* Nonzero means that we should generate code using a flat register window
309 model, i.e. no save/restore instructions are generated, which is
310 compatible with normal sparc code.
311 The frame pointer is %i7 instead of %fp. */
312 #define MASK_FLAT 0x200
313 #define TARGET_FLAT (target_flags & MASK_FLAT)
315 /* Nonzero means use the registers that the Sparc ABI reserves for
316 application software. This must be the default to coincide with the
317 setting in FIXED_REGISTERS. */
318 #define MASK_APP_REGS 0x400
319 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
321 /* Option to select how quad word floating point is implemented.
322 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
323 Otherwise, we use the SPARC ABI quad library functions. */
324 #define MASK_HARD_QUAD 0x800
325 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
327 /* Bit 0x1000 currently unused. */
329 /* Nonzero if ints are 64 bits.
330 This automatically implies longs are 64 bits too.
331 This option is for v9 only. */
332 #define MASK_INT64 0x2000
333 #define TARGET_INT64 (target_flags & MASK_INT64)
335 /* Nonzero if longs are 64 bits.
336 This option is for v9 only. */
337 #define MASK_LONG64 0x4000
338 #define TARGET_LONG64 (target_flags & MASK_LONG64)
340 /* Nonzero if pointers are 64 bits.
341 This is not a user selectable option, though it may be one day -
342 so it is used to determine pointer size instead of an architecture flag. */
343 #define MASK_PTR64 0x8000
344 #define TARGET_PTR64 (target_flags & MASK_PTR64)
346 /* Nonzero if generating code to run in a 64 bit environment. */
347 #define MASK_ARCH64 0x10000
348 #define TARGET_ARCH64 (target_flags & MASK_ARCH64)
349 #define TARGET_ARCH32 (! TARGET_ARCH64)
351 /* SPARC64 memory models.
352 TARGET_MEDLOW: 32 bit address space, top 32 bits = 0,
353 avoid generating %uhi and %ulo terms.
354 (pointers can be 32 or 64 bits)
355 TARGET_MEDANY: 64 bit address space, data segment restricted to 4G, but
356 can be loaded anywhere (use %g4 as offset).
357 TARGET_FULLANY: 64 bit address space, no restrictions.
358 This option is not fully supported yet.
359 These options are for v9 only. All mask values are nonzero so the v8
360 compiler can assume this stuff won't interfere. */
361 #define MASK_MEDLOW 0x20000
362 #define MASK_MEDANY 0x40000
363 #define MASK_FULLANY 0x60000
364 #define MASK_CODE_MODEL (MASK_MEDLOW + MASK_MEDANY)
365 #define TARGET_MEDLOW ((target_flags & MASK_CODE_MODEL) == MASK_MEDLOW)
366 #define TARGET_MEDANY ((target_flags & MASK_CODE_MODEL) == MASK_MEDANY)
367 #define TARGET_FULLANY ((target_flags & MASK_CODE_MODEL) == MASK_FULLANY)
369 /* ??? There are hardcoded references to this reg in the .md file. */
370 #define MEDANY_BASE_REG "%g4"
372 /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
373 adding 2047 to %sp. This option is for v9 only and is the default. */
374 #define MASK_STACK_BIAS 0x80000
375 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
377 /* Non-zero means %g0 is a normal register.
378 We still clobber it as necessary, but we can't rely on it always having
380 We don't bother to support this in true 64 bit mode. */
381 #define MASK_LIVE_G0 0x100000
382 #define TARGET_LIVE_G0 (target_flags & MASK_LIVE_G0)
384 /* Non-zero means the cpu has broken `save' and `restore' insns, only
385 the trivial versions work (save %g0,%g0,%g0; restore %g0,%g0,%g0).
386 We assume the environment will properly handle or otherwise avoid
387 trouble associated with an interrupt occuring after the `save' or trap
388 occuring during it. */
389 #define MASK_BROKEN_SAVERESTORE 0x200000
390 #define TARGET_BROKEN_SAVERESTORE (target_flags & MASK_BROKEN_SAVERESTORE)
392 /* Macro to define tables used to set the flags.
393 This is a list in braces of pairs in braces,
394 each pair being { "NAME", VALUE }
395 where VALUE is the bits to set or minus the bits to clear.
396 An empty string NAME is used to identify the default VALUE. */
398 #define TARGET_SWITCHES \
399 { {"fpu", MASK_FPU}, \
400 {"no-fpu", -MASK_FPU}, \
401 {"hard-float", MASK_FPU}, \
402 {"soft-float", -MASK_FPU}, \
403 {"epilogue", MASK_EPILOGUE}, \
404 {"no-epilogue", -MASK_EPILOGUE}, \
405 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES}, \
406 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES}, \
407 {"impure-text", MASK_IMPURE_TEXT}, \
408 {"no-impure-text", -MASK_IMPURE_TEXT}, \
409 {"flat", MASK_FLAT}, \
410 {"no-flat", -MASK_FLAT}, \
411 {"app-regs", MASK_APP_REGS}, \
412 {"no-app-regs", -MASK_APP_REGS}, \
413 {"hard-quad-float", MASK_HARD_QUAD}, \
414 {"soft-quad-float", -MASK_HARD_QUAD}, \
415 /* ??? These are coerced to -mcpu=. Delete in 2.9. */ \
424 { "", TARGET_DEFAULT}}
426 /* MASK_APP_REGS must always be the default because that's what
427 FIXED_REGISTERS is set to and -ffixed- is processed before
428 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
429 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
431 /* This is meant to be redefined in target specific files. */
432 #define SUBTARGET_SWITCHES
434 /* ??? Until we support a combination 32/64 bit compiler, these options
435 are only defined for the v9 compiler in a true 64 bit environment. */
437 #define ARCH64_SWITCHES \
438 /* {"arch32", -MASK_ARCH64}, */ \
439 /* {"arch64", MASK_ARCH64}, */ \
440 {"int64", MASK_INT64+MASK_LONG64}, \
441 {"int32", -MASK_INT64}, \
442 {"int32", MASK_LONG64}, \
443 {"long64", -MASK_INT64}, \
444 {"long64", MASK_LONG64}, \
445 {"long32", -(MASK_INT64+MASK_LONG64)}, \
446 /* {"ptr64", MASK_PTR64}, */ \
447 /* {"ptr32", -MASK_PTR64}, */ \
448 {"stack-bias", MASK_STACK_BIAS}, \
449 {"no-stack-bias", -MASK_STACK_BIAS}, \
450 {"medlow", -MASK_CODE_MODEL}, \
451 {"medlow", MASK_MEDLOW}, \
452 {"medany", -MASK_CODE_MODEL}, \
453 {"medany", MASK_MEDANY}, \
454 {"fullany", -MASK_CODE_MODEL}, \
455 {"fullany", MASK_FULLANY},
457 #define ARCH64_SWITCHES
461 These must match the values for the cpu attribute in sparc.md. */
462 enum processor_type {
466 PROCESSOR_SUPERSPARC,
477 /* This is set from -m{cpu,tune}=xxx. */
478 extern enum processor_type sparc_cpu;
480 /* Recast the cpu class to be the cpu attribute.
481 Every file includes us, but not every file includes insn-attr.h. */
482 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
484 /* This macro is similar to `TARGET_SWITCHES' but defines names of
485 command options that have values. Its definition is an
486 initializer with a subgrouping for each command option.
488 Each subgrouping contains a string constant, that defines the
489 fixed part of the option name, and the address of a variable.
490 The variable, type `char *', is set to the variable part of the
491 given option if the fixed part matches. The actual option name
492 is made by appending `-m' to the specified name.
494 Here is an example which defines `-mshort-data-NUMBER'. If the
495 given option is `-mshort-data-512', the variable `m88k_short_data'
496 will be set to the string `"512"'.
498 extern char *m88k_short_data;
499 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
501 #define TARGET_OPTIONS \
503 {"cpu=", &sparc_select[1].string}, \
504 {"tune=", &sparc_select[2].string}, \
508 /* This is meant to be redefined in target specific files. */
509 #define SUBTARGET_OPTIONS
511 /* sparc_select[0] is reserved for the default cpu. */
512 struct sparc_cpu_select
520 extern struct sparc_cpu_select sparc_select[];
522 /* target machine storage layout */
524 /* Define for cross-compilation to a sparc target with no TFmode from a host
525 with a different float format (e.g. VAX). */
526 #define REAL_ARITHMETIC
528 /* Define this if most significant bit is lowest numbered
529 in instructions that operate on numbered bit-fields. */
530 #define BITS_BIG_ENDIAN 1
532 /* Define this if most significant byte of a word is the lowest numbered. */
533 /* This is true on the SPARC. */
534 #define BYTES_BIG_ENDIAN 1
536 /* Define this if most significant word of a multiword number is the lowest
538 /* Doubles are stored in memory with the high order word first. This
539 matters when cross-compiling. */
540 #define WORDS_BIG_ENDIAN 1
542 /* number of bits in an addressable storage unit */
543 #define BITS_PER_UNIT 8
545 /* Width in bits of a "word", which is the contents of a machine register.
546 Note that this is not necessarily the width of data type `int';
547 if using 16-bit ints on a 68000, this would still be 32.
548 But on a machine with 16-bit registers, this would be 16. */
549 #define BITS_PER_WORD (TARGET_ARCH64 ? 64 : 32)
550 #define MAX_BITS_PER_WORD 64
552 /* Width of a word, in units (bytes). */
553 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
554 #define MIN_UNITS_PER_WORD 4
556 /* Now define the sizes of the C data types. */
558 #define SHORT_TYPE_SIZE 16
559 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
560 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
561 #define LONG_LONG_TYPE_SIZE 64
562 #define FLOAT_TYPE_SIZE 32
563 #define DOUBLE_TYPE_SIZE 64
565 #define MAX_INT_TYPE_SIZE 64
566 #define MAX_LONG_TYPE_SIZE 64
569 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
570 Instead, it is enabled in sol2.h, because it does work under Solaris. */
571 /* Define for support of TFmode long double and REAL_ARITHMETIC.
572 Sparc ABI says that long double is 4 words. */
573 #define LONG_DOUBLE_TYPE_SIZE 128
576 /* Width in bits of a pointer.
577 See also the macro `Pmode' defined below. */
578 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
580 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
581 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
583 /* Boundary (in *bits*) on which stack pointer should be aligned. */
584 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
586 /* ALIGN FRAMES on double word boundaries */
588 #define SPARC_STACK_ALIGN(LOC) \
589 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
591 /* Allocation boundary (in *bits*) for the code of a function. */
592 #define FUNCTION_BOUNDARY 32
594 /* Alignment of field after `int : 0' in a structure. */
595 /* ??? Should this be based on TARGET_INT64? */
596 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
598 /* Every structure's size must be a multiple of this. */
599 #define STRUCTURE_SIZE_BOUNDARY 8
601 /* A bitfield declared as `int' forces `int' alignment for the struct. */
602 #define PCC_BITFIELD_TYPE_MATTERS 1
604 /* No data type wants to be aligned rounder than this. */
605 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
607 /* The best alignment to use in cases where we have a choice. */
608 #define FASTEST_ALIGNMENT 64
610 /* Make strings word-aligned so strcpy from constants will be faster. */
611 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
612 ((TREE_CODE (EXP) == STRING_CST \
613 && (ALIGN) < FASTEST_ALIGNMENT) \
614 ? FASTEST_ALIGNMENT : (ALIGN))
616 /* Make arrays of chars word-aligned for the same reasons. */
617 #define DATA_ALIGNMENT(TYPE, ALIGN) \
618 (TREE_CODE (TYPE) == ARRAY_TYPE \
619 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
620 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
622 /* Set this nonzero if move instructions will actually fail to work
623 when given unaligned data. */
624 #define STRICT_ALIGNMENT 1
626 /* Things that must be doubleword aligned cannot go in the text section,
627 because the linker fails to align the text section enough!
628 Put them in the data section. This macro is only used in this file. */
629 #define MAX_TEXT_ALIGN 32
631 /* This forces all variables and constants to the data section when PIC.
632 This is because the SunOS 4 shared library scheme thinks everything in
633 text is a function, and patches the address to point to a loader stub. */
634 /* This is defined to zero for every system which doesn't use the a.out object
636 #ifndef SUNOS4_SHARED_LIBRARIES
637 #define SUNOS4_SHARED_LIBRARIES 0
640 /* This is defined differently for v9 in a cover file. */
641 #define SELECT_SECTION(T,RELOC) \
643 if (TREE_CODE (T) == VAR_DECL) \
645 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
646 && DECL_INITIAL (T) \
647 && (DECL_INITIAL (T) == error_mark_node \
648 || TREE_CONSTANT (DECL_INITIAL (T))) \
649 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
650 && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
655 else if (TREE_CODE (T) == CONSTRUCTOR) \
657 if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \
660 else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c') \
662 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
663 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \
664 || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
671 /* Use text section for a constant
672 unless we need more alignment than that offers. */
673 /* This is defined differently for v9 in a cover file. */
674 #define SELECT_RTX_SECTION(MODE, X) \
676 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
677 && ! (flag_pic && (symbolic_operand (X) || SUNOS4_SHARED_LIBRARIES))) \
683 /* Standard register usage. */
685 /* Number of actual hardware registers.
686 The hardware registers are assigned numbers for the compiler
687 from 0 to just below FIRST_PSEUDO_REGISTER.
688 All registers that the compiler knows about must be given numbers,
689 even those that are not normally considered general registers.
691 SPARC has 32 integer registers and 32 floating point registers.
692 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
693 accessible. We still account for them to simplify register computations
694 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
696 Register 100 is used as the integer condition code register. */
698 #define FIRST_PSEUDO_REGISTER 101
700 /* Additional V9 fp regs. */
701 #define SPARC_FIRST_V9_FP_REG 64
702 #define SPARC_LAST_V9_FP_REG 95
703 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
704 #define SPARC_FIRST_V9_FCC_REG 96
705 #define SPARC_LAST_V9_FCC_REG 99
707 #define SPARC_FCC_REG 96
708 /* Integer CC reg. We don't distinguish %icc from %xcc. */
709 #define SPARC_ICC_REG 100
711 /* 1 for registers that have pervasive standard uses
712 and are not available for the register allocator.
714 g1 is free to use as temporary.
715 g2-g4 are reserved for applications. Gcc normally uses them as
716 temporaries, but this can be disabled via the -mno-app-regs option.
717 g5 through g7 are reserved for the operating system.
719 g1 and g5 are free to use as temporaries.
720 g2-g4 are reserved for applications. Gcc normally uses them as
721 temporaries, but this can be disabled via the -mno-app-regs option.
722 g6-g7 are reserved for the operating system.
723 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
724 currently be a fixed register until this pattern is rewritten.
725 Register 1 is also used when restoring call-preserved registers in large
728 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
729 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
732 #define FIXED_REGISTERS \
733 {1, 0, 0, 0, 0, 0, 1, 1, \
734 0, 0, 0, 0, 0, 0, 1, 0, \
735 0, 0, 0, 0, 0, 0, 0, 0, \
736 0, 0, 0, 0, 0, 0, 1, 1, \
738 0, 0, 0, 0, 0, 0, 0, 0, \
739 0, 0, 0, 0, 0, 0, 0, 0, \
740 0, 0, 0, 0, 0, 0, 0, 0, \
741 0, 0, 0, 0, 0, 0, 0, 0, \
743 0, 0, 0, 0, 0, 0, 0, 0, \
744 0, 0, 0, 0, 0, 0, 0, 0, \
745 0, 0, 0, 0, 0, 0, 0, 0, \
746 0, 0, 0, 0, 0, 0, 0, 0, \
750 /* 1 for registers not available across function calls.
751 These must include the FIXED_REGISTERS and also any
752 registers that can be used without being saved.
753 The latter must include the registers where values are returned
754 and the register where structure-value addresses are passed.
755 Aside from that, you can include as many other registers as you like. */
757 #define CALL_USED_REGISTERS \
758 {1, 1, 1, 1, 1, 1, 1, 1, \
759 1, 1, 1, 1, 1, 1, 1, 1, \
760 0, 0, 0, 0, 0, 0, 0, 0, \
761 0, 0, 0, 0, 0, 0, 1, 1, \
763 1, 1, 1, 1, 1, 1, 1, 1, \
764 1, 1, 1, 1, 1, 1, 1, 1, \
765 1, 1, 1, 1, 1, 1, 1, 1, \
766 1, 1, 1, 1, 1, 1, 1, 1, \
768 1, 1, 1, 1, 1, 1, 1, 1, \
769 1, 1, 1, 1, 1, 1, 1, 1, \
770 1, 1, 1, 1, 1, 1, 1, 1, \
771 1, 1, 1, 1, 1, 1, 1, 1, \
775 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
776 they won't be allocated. */
778 #define CONDITIONAL_REGISTER_USAGE \
781 if (! SPARC_ARCH64) \
789 /* ??? We need to scan argv for -fcall-used-. */ \
790 for (regno = 48; regno < 80; regno++) \
791 call_used_regs[regno] = 0; \
796 for (regno = SPARC_FIRST_V9_FP_REG; \
797 regno <= SPARC_LAST_V9_FP_REG; \
799 fixed_regs[regno] = 1; \
800 /* %fcc0 is used by v8 and v9. */ \
801 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
802 regno <= SPARC_LAST_V9_FCC_REG; \
804 fixed_regs[regno] = 1; \
809 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
810 fixed_regs[regno] = 1; \
812 /* Don't unfix g2-g4 if they were fixed with -ffixed-. */ \
813 fixed_regs[2] |= ! TARGET_APP_REGS; \
814 fixed_regs[3] |= ! TARGET_APP_REGS; \
815 fixed_regs[4] |= ! TARGET_APP_REGS || TARGET_MEDANY; \
818 /* Let the compiler believe the frame pointer is still \
819 %fp, but output it as %i7. */ \
820 fixed_regs[31] = 1; \
821 reg_names[FRAME_POINTER_REGNUM] = "%i7"; \
822 /* ??? This is a hack to disable leaf functions. */ \
823 global_regs[7] = 1; \
825 if (profile_block_flag) \
827 /* %g1 and %g2 must be fixed, because BLOCK_PROFILER \
835 /* Return number of consecutive hard regs needed starting at reg REGNO
836 to hold something of mode MODE.
837 This is ordinarily the length in words of a value of mode MODE
838 but can be less for certain modes in special long registers.
840 On SPARC, ordinary registers hold 32 bits worth;
841 this means both integer and floating point registers.
842 On v9, integer regs hold 64 bits worth; floating point regs hold
843 32 bits worth (this includes the new fp regs as even the odd ones are
844 included in the hard register count). */
846 #define HARD_REGNO_NREGS(REGNO, MODE) \
849 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
850 : (GET_MODE_SIZE (MODE) + 3) / 4) \
851 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
853 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
854 See sparc.c for how we initialize this. */
855 extern int *hard_regno_mode_classes;
856 extern int sparc_mode_class[];
857 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
858 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
860 /* Value is 1 if it is a good idea to tie two pseudo registers
861 when one has mode MODE1 and one has mode MODE2.
862 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
863 for any hard reg, then this must be 0 for correct output.
865 For V9: SFmode can't be combined with other float modes, because they can't
866 be allocated to the %d registers. Also, DFmode won't fit in odd %f
867 registers, but SFmode will. */
868 #define MODES_TIEABLE_P(MODE1, MODE2) \
869 ((MODE1) == (MODE2) \
870 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
872 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
873 || (MODE1 != SFmode && MODE2 != SFmode)))))
875 /* Specify the registers used for certain standard purposes.
876 The values of these macros are register numbers. */
878 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
879 /* #define PC_REGNUM */
881 /* Register to use for pushing function arguments. */
882 #define STACK_POINTER_REGNUM 14
884 /* Actual top-of-stack address is 92/136 greater than the contents of the
885 stack pointer register for !v9/v9. That is:
886 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
887 address, and 24 bytes for the 6 register parameters.
888 - v9: 128 bytes for the in and local registers + 8 bytes reserved. */
889 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
891 /* The stack bias (amount by which the hardware register is offset by). */
892 #define SPARC_STACK_BIAS (TARGET_STACK_BIAS ? 2047 : 0)
894 /* Base register for access to local variables of the function. */
895 #define FRAME_POINTER_REGNUM 30
898 /* Register that is used for the return address. */
899 #define RETURN_ADDR_REGNUM 15
902 /* Value should be nonzero if functions must have frame pointers.
903 Zero means the frame pointer need not be set up (and parms
904 may be accessed via the stack pointer) in functions that seem suitable.
905 This is computed in `reload', in reload1.c.
906 Used in flow.c, global.c, and reload1.c.
908 Being a non-leaf function does not mean a frame pointer is needed in the
909 flat window model. However, the debugger won't be able to backtrace through
911 #define FRAME_POINTER_REQUIRED \
912 (TARGET_FLAT ? (current_function_calls_alloca || current_function_varargs \
913 || !leaf_function_p ()) \
914 : ! (leaf_function_p () && only_leaf_regs_used ()))
916 /* C statement to store the difference between the frame pointer
917 and the stack pointer values immediately after the function prologue.
919 Note, we always pretend that this is a leaf function because if
920 it's not, there's no point in trying to eliminate the
921 frame pointer. If it is a leaf function, we guessed right! */
922 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
923 ((VAR) = (TARGET_FLAT ? sparc_flat_compute_frame_size (get_frame_size ()) \
924 : compute_frame_size (get_frame_size (), 1)))
926 /* Base register for access to arguments of the function. */
927 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
929 /* Register in which static-chain is passed to a function. This must
930 not be a register used by the prologue. */
931 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
933 /* Register which holds offset table for position-independent
936 #define PIC_OFFSET_TABLE_REGNUM 23
938 #define INITIALIZE_PIC initialize_pic ()
939 #define FINALIZE_PIC finalize_pic ()
941 /* Sparc ABI says that quad-precision floats and all structures are returned
943 For v9, all aggregates are returned in memory. */
944 #define RETURN_IN_MEMORY(TYPE) \
945 (TYPE_MODE (TYPE) == BLKmode \
946 || (! TARGET_ARCH64 && (TYPE_MODE (TYPE) == TFmode \
947 || TYPE_MODE (TYPE) == TCmode)))
949 /* Functions which return large structures get the address
950 to place the wanted value at offset 64 from the frame.
951 Must reserve 64 bytes for the in and local registers.
952 v9: Functions which return large structures get the address to place the
953 wanted value from an invisible first argument. */
954 /* Used only in other #defines in this file. */
955 #define STRUCT_VALUE_OFFSET 64
957 #define STRUCT_VALUE \
960 : gen_rtx (MEM, Pmode, \
961 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
962 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))))
963 #define STRUCT_VALUE_INCOMING \
966 : gen_rtx (MEM, Pmode, \
967 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
968 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))))
970 /* Define the classes of registers for register constraints in the
971 machine description. Also define ranges of constants.
973 One of the classes must always be named ALL_REGS and include all hard regs.
974 If there is more than one class, another class must be named NO_REGS
975 and contain no registers.
977 The name GENERAL_REGS must be the name of a class (or an alias for
978 another name such as ALL_REGS). This is the class of registers
979 that is allowed by "g" or "r" in a register constraint.
980 Also, registers outside this class are allocated only when
981 instructions express preferences for them.
983 The classes must be numbered in nondecreasing order; that is,
984 a larger-numbered class must never be contained completely
985 in a smaller-numbered class.
987 For any two classes, it is very desirable that there be another
988 class that represents their union. */
990 /* The SPARC has two kinds of registers, general and floating point.
992 For v9 we must distinguish between the upper and lower floating point
993 registers because the upper ones can't hold SFmode values.
994 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
995 satisfying a group need for a class will also satisfy a single need for
996 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
999 It is important that one class contains all the general and all the standard
1000 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1001 because reg_class_record() will bias the selection in favor of fp regs,
1002 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1003 because FP_REGS > GENERAL_REGS.
1005 It is also important that one class contain all the general and all the
1006 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1007 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1008 allocate_reload_reg() to bypass it causing an abort because the compiler
1009 thinks it doesn't have a spill reg when in fact it does.
1011 v9 also has 4 floating point condition code registers. Since we don't
1012 have a class that is the union of FPCC_REGS with either of the others,
1013 it is important that it appear first. Otherwise the compiler will die
1014 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1017 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1018 may try to use it to hold an SImode value. See register_operand.
1019 ??? Should %fcc[0123] be handled similarily?
1022 enum reg_class { NO_REGS, FPCC_REGS, GENERAL_REGS, FP_REGS, EXTRA_FP_REGS,
1023 GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1024 ALL_REGS, LIM_REG_CLASSES };
1026 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1028 /* Give names of register classes as strings for dump file. */
1030 #define REG_CLASS_NAMES \
1031 { "NO_REGS", "FPCC_REGS", "GENERAL_REGS", "FP_REGS", "EXTRA_FP_REGS", \
1032 "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", "ALL_REGS" }
1034 /* Define which registers fit in which classes.
1035 This is an initializer for a vector of HARD_REG_SET
1036 of length N_REG_CLASSES. */
1038 #define REG_CLASS_CONTENTS \
1039 {{0, 0, 0, 0}, {0, 0, 0, 0xf}, \
1040 {-1, 0, 0, 0}, {0, -1, 0, 0}, {0, -1, -1, 0}, \
1041 {-1, -1, 0, 0}, {-1, -1, -1, 0}, {-1, -1, -1, 0x1f}}
1043 /* The same information, inverted:
1044 Return the class number of the smallest class containing
1045 reg number REGNO. This could be a conditional expression
1046 or could index an array. */
1048 extern enum reg_class sparc_regno_reg_class[];
1050 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1052 /* This is the order in which to allocate registers normally.
1054 We put %f0/%f1 last among the float registers, so as to make it more
1055 likely that a pseudo-register which dies in the float return register
1056 will get allocated to the float return register, thus saving a move
1057 instruction at the end of the function.
1059 The float registers are ordered a little "funny" because in the 64 bit
1060 architecture, some of them (%f16-%f47) are call-preserved. */
1062 #define REG_ALLOC_ORDER \
1063 { 8, 9, 10, 11, 12, 13, 2, 3, \
1064 15, 16, 17, 18, 19, 20, 21, 22, \
1065 23, 24, 25, 26, 27, 28, 29, 31, \
1066 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \
1067 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1068 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1069 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1070 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1071 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1072 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1073 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1074 32, 33, /* %f0,%f1 */ \
1075 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \
1076 1, 4, 5, 6, 7, 0, 14, 30}
1078 /* This is the order in which to allocate registers for
1079 leaf functions. If all registers can fit in the "i" registers,
1080 then we have the possibility of having a leaf function.
1081 The floating point registers are ordered a little "funny" because in the
1082 64 bit architecture some of them (%f16-%f47) are call-preserved. */
1084 #define REG_LEAF_ALLOC_ORDER \
1085 { 2, 3, 24, 25, 26, 27, 28, 29, \
1086 15, 8, 9, 10, 11, 12, 13, \
1087 16, 17, 18, 19, 20, 21, 22, 23, \
1088 34, 35, 36, 37, 38, 39, \
1089 40, 41, 42, 43, 44, 45, 46, 47, \
1090 80, 81, 82, 83, 84, 85, 86, 87, \
1091 88, 89, 90, 91, 92, 93, 94, 95, \
1092 48, 49, 50, 51, 52, 53, 54, 55, \
1093 56, 57, 58, 59, 60, 61, 62, 63, \
1094 64, 65, 66, 67, 68, 69, 70, 71, \
1095 72, 73, 74, 75, 76, 77, 78, 79, \
1097 96, 97, 98, 99, 100, \
1098 1, 4, 5, 6, 7, 0, 14, 30, 31}
1100 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1102 /* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when
1103 -mflat is used. Function only_leaf_regs_used will return 0 if a global
1104 register is used and is not permitted in a leaf function. We make %g7
1105 a global reg if -mflat and voila. Since %g7 is a system register and is
1106 fixed it won't be used by gcc anyway. */
1108 #define LEAF_REGISTERS \
1109 { 1, 1, 1, 1, 1, 1, 1, 0, \
1110 0, 0, 0, 0, 0, 0, 1, 0, \
1111 0, 0, 0, 0, 0, 0, 0, 0, \
1112 1, 1, 1, 1, 1, 1, 0, 1, \
1113 1, 1, 1, 1, 1, 1, 1, 1, \
1114 1, 1, 1, 1, 1, 1, 1, 1, \
1115 1, 1, 1, 1, 1, 1, 1, 1, \
1116 1, 1, 1, 1, 1, 1, 1, 1, \
1117 1, 1, 1, 1, 1, 1, 1, 1, \
1118 1, 1, 1, 1, 1, 1, 1, 1, \
1119 1, 1, 1, 1, 1, 1, 1, 1, \
1120 1, 1, 1, 1, 1, 1, 1, 1, \
1123 extern char leaf_reg_remap[];
1124 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1126 /* The class value for index registers, and the one for base regs. */
1127 #define INDEX_REG_CLASS GENERAL_REGS
1128 #define BASE_REG_CLASS GENERAL_REGS
1130 /* Local macro to handle the two v9 classes of FP regs. */
1131 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1133 /* Get reg_class from a letter such as appears in the machine description.
1134 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1135 .md file for v8 and v9. */
1137 #define REG_CLASS_FROM_LETTER(C) \
1139 ? ((C) == 'f' ? FP_REGS \
1140 : (C) == 'e' ? EXTRA_FP_REGS \
1141 : (C) == 'c' ? FPCC_REGS \
1143 : ((C) == 'f' ? FP_REGS \
1144 : (C) == 'e' ? FP_REGS \
1145 : (C) == 'c' ? FPCC_REGS \
1148 /* The letters I, J, K, L and M in a register constraint string
1149 can be used to stand for particular ranges of immediate operands.
1150 This macro defines what the ranges are.
1151 C is the letter, and VALUE is a constant value.
1152 Return 1 if VALUE is in the range specified by C.
1154 `I' is used for the range of constants an insn can actually contain.
1155 `J' is used for the range which is just zero (since that is R0).
1156 `K' is used for constants which can be loaded with a single sethi insn.
1157 `L' is used for the range of constants supported by the movcc insns.
1158 `M' is used for the range of constants supported by the movrcc insns. */
1160 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) ((X) + 0x200) < 0x400)
1161 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) ((X) + 0x400) < 0x800)
1162 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) ((X) + 0x1000) < 0x2000)
1163 /* 10 and 11 bit immediates are only used for a few specific insns.
1164 SMALL_INT is used throughout the port so we continue to use it. */
1165 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1167 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1168 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1169 : (C) == 'J' ? (VALUE) == 0 \
1170 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
1171 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1172 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1175 /* Similar, but for floating constants, and defining letters G and H.
1176 Here VALUE is the CONST_DOUBLE rtx itself. */
1178 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1179 ((C) == 'G' ? fp_zero_operand (VALUE) \
1180 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1183 /* Given an rtx X being reloaded into a reg required to be
1184 in class CLASS, return the class of reg to actually use.
1185 In general this is just CLASS; but on some machines
1186 in some cases it is preferable to use a more restrictive class. */
1187 /* We can't load constants into FP registers. We can't load any FP constant
1188 if an 'E' constraint fails to match it. */
1189 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1191 && (FP_REG_CLASS_P (CLASS) \
1192 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1193 && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
1194 || HOST_BITS_PER_INT != BITS_PER_WORD))) \
1195 ? NO_REGS : (CLASS))
1197 /* Return the register class of a scratch register needed to load IN into
1198 a register of class CLASS in MODE.
1200 On the SPARC, when PIC, we need a temporary when loading some addresses
1203 Also, we need a temporary when loading/storing a HImode/QImode value
1204 between memory and the FPU registers. This can happen when combine puts
1205 a paradoxical subreg in a float/fix conversion insn. */
1207 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1208 ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \
1209 && (GET_CODE (IN) == MEM \
1210 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1211 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
1213 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1214 ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \
1215 && (GET_CODE (IN) == MEM \
1216 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1217 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
1219 /* On SPARC it is not possible to directly move data between
1220 GENERAL_REGS and FP_REGS. */
1221 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1222 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1224 /* Return the stack location to use for secondary memory needed reloads.
1225 We want to use the reserved location just below the frame pointer.
1226 However, we must ensure that there is a frame, so use assign_stack_local
1227 if the frame size is zero. */
1228 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1229 (get_frame_size () == 0 \
1230 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1231 : gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
1232 GEN_INT (STARTING_FRAME_OFFSET))))
1234 /* Get_secondary_mem widens it's argument to BITS_PER_WORD which loses on v9
1235 because the movsi and movsf patterns don't handle r/f moves.
1236 For v8 we copy the default definition. */
1237 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1239 ? (GET_MODE_BITSIZE (MODE) < 32 \
1240 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1242 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1243 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1246 /* Return the maximum number of consecutive registers
1247 needed to represent mode MODE in a register of class CLASS. */
1248 /* On SPARC, this is the size of MODE in words. */
1249 #define CLASS_MAX_NREGS(CLASS, MODE) \
1250 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1251 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1253 /* Stack layout; function entry, exit and calling. */
1255 /* Define the number of register that can hold parameters.
1256 These two macros are used only in other macro definitions below.
1257 MODE is the mode of the argument.
1258 !v9: All args are passed in %o0-%o5.
1259 v9: Non-float args are passed in %o0-5 and float args are passed in
1261 #define NPARM_REGS(MODE) \
1262 (TARGET_ARCH64 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 16 : 6) : 6)
1264 /* Define this if pushing a word on the stack
1265 makes the stack pointer a smaller address. */
1266 #define STACK_GROWS_DOWNWARD
1268 /* Define this if the nominal address of the stack frame
1269 is at the high-address end of the local variables;
1270 that is, each additional local variable allocated
1271 goes at a more negative offset in the frame. */
1272 #define FRAME_GROWS_DOWNWARD
1274 /* Offset within stack frame to start allocating local variables at.
1275 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1276 first local allocated. Otherwise, it is the offset to the BEGINNING
1277 of the first local allocated. */
1278 /* This allows space for one TFmode floating point value. */
1279 #define STARTING_FRAME_OFFSET \
1280 (TARGET_ARCH64 ? (SPARC_STACK_BIAS - 16) \
1281 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1283 /* If we generate an insn to push BYTES bytes,
1284 this says how many the stack pointer really advances by.
1285 On SPARC, don't define this because there are no push insns. */
1286 /* #define PUSH_ROUNDING(BYTES) */
1288 /* Offset of first parameter from the argument pointer register value.
1289 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1290 even if this function isn't going to use it.
1291 v9: This is 128 for the ins and locals, plus a reserved space of 8. */
1292 #define FIRST_PARM_OFFSET(FNDECL) \
1293 (TARGET_ARCH64 ? (SPARC_STACK_BIAS + 136) \
1294 : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD))
1296 /* When a parameter is passed in a register, stack space is still
1297 allocated for it. */
1299 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS (SImode) * UNITS_PER_WORD)
1302 /* Keep the stack pointer constant throughout the function.
1303 This is both an optimization and a necessity: longjmp
1304 doesn't behave itself when the stack pointer moves within
1306 #define ACCUMULATE_OUTGOING_ARGS
1308 /* Value is the number of bytes of arguments automatically
1309 popped when returning from a subroutine call.
1310 FUNDECL is the declaration node of the function (as a tree),
1311 FUNTYPE is the data type of the function (as a tree),
1312 or for a library call it is an identifier node for the subroutine name.
1313 SIZE is the number of bytes of arguments passed on the stack. */
1315 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1317 /* Some subroutine macros specific to this machine.
1318 When !TARGET_FPU, put float return values in the general registers,
1319 since we don't have any fp registers. */
1320 #define BASE_RETURN_VALUE_REG(MODE) \
1322 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \
1323 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1324 #define BASE_OUTGOING_VALUE_REG(MODE) \
1326 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \
1327 : TARGET_FLAT ? 8 : 24) \
1328 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1329 : (TARGET_FLAT ? 8 : 24)))
1330 #define BASE_PASSING_ARG_REG(MODE) \
1332 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \
1334 #define BASE_INCOMING_ARG_REG(MODE) \
1336 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \
1337 : TARGET_FLAT ? 8 : 24) \
1338 : (TARGET_FLAT ? 8 : 24))
1340 /* Define this macro if the target machine has "register windows". This
1341 C expression returns the register number as seen by the called function
1342 corresponding to register number OUT as seen by the calling function.
1343 Return OUT if register number OUT is not an outbound register. */
1345 #define INCOMING_REGNO(OUT) \
1346 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1348 /* Define this macro if the target machine has "register windows". This
1349 C expression returns the register number as seen by the calling function
1350 corresponding to register number IN as seen by the called function.
1351 Return IN if register number IN is not an inbound register. */
1353 #define OUTGOING_REGNO(IN) \
1354 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1356 /* Define how to find the value returned by a function.
1357 VALTYPE is the data type of the value (as a tree).
1358 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1359 otherwise, FUNC is 0. */
1361 /* On SPARC the value is found in the first "output" register. */
1363 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1364 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1366 /* But the called function leaves it in the first "input" register. */
1368 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1369 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
1371 /* Define how to find the value returned by a library function
1372 assuming the value has mode MODE. */
1374 #define LIBCALL_VALUE(MODE) \
1375 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
1377 /* 1 if N is a possible register number for a function value
1378 as seen by the caller.
1379 On SPARC, the first "output" reg is used for integer values,
1380 and the first floating point register is used for floating point values. */
1382 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1384 /* Define the size of space to allocate for the return value of an
1387 #define APPLY_RESULT_SIZE 16
1389 /* 1 if N is a possible register number for function argument passing.
1390 On SPARC, these are the "output" registers. v9 also uses %f0-%f15. */
1392 #define FUNCTION_ARG_REGNO_P(N) \
1393 (TARGET_ARCH64 ? (((N) < 14 && (N) > 7) || (N) > 31 && (N) < 48) \
1394 : ((N) < 14 && (N) > 7))
1396 /* Define a data type for recording info about an argument list
1397 during the scan of that argument list. This data type should
1398 hold all necessary information about the function itself
1399 and about the args processed so far, enough to enable macros
1400 such as FUNCTION_ARG to determine where the next arg should go.
1402 On SPARC (!v9), this is a single integer, which is a number of words
1403 of arguments scanned so far (including the invisible argument,
1404 if any, which holds the structure-value-address).
1405 Thus 7 or more means all following args should go on the stack.
1407 For v9, we record how many of each type has been passed. Different
1408 types get passed differently.
1410 - Float args are passed in %f0-15, after which they go to the stack
1411 where floats and doubles are passed 8 byte aligned and long doubles
1412 are passed 16 byte aligned.
1413 - All aggregates are passed by reference. The callee copies
1414 the structure if necessary, except if stdarg/varargs and the struct
1415 matches the ellipse in which case the caller makes a copy.
1416 - Any non-float argument might be split between memory and reg %o5.
1417 ??? I don't think this can ever happen now that structs are no
1418 longer passed in regs.
1420 For v9 return values:
1422 - For all aggregates, the caller allocates space for the return value,
1423 and passes the pointer as an implicit first argument, which is
1424 allocated like all other arguments.
1425 - The unimp instruction stuff for structure returns is gone. */
1428 enum sparc_arg_class { SPARC_ARG_INT = 0, SPARC_ARG_FLOAT = 1 };
1430 int arg_count[2]; /* must be int! (for __builtin_args_info) */
1432 #define CUMULATIVE_ARGS struct sparc_args
1434 /* Return index into CUMULATIVE_ARGS. */
1436 #define GET_SPARC_ARG_CLASS(MODE) \
1437 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? SPARC_ARG_FLOAT : SPARC_ARG_INT)
1439 /* Round a register number up to a proper boundary for an arg of mode MODE.
1440 This macro is only used in this file.
1442 The "& (0x10000 - ...)" is used to round up to the next appropriate reg. */
1444 #define ROUND_REG(CUM, MODE) \
1445 (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1446 ? (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \
1447 : ((CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \
1448 + GET_MODE_UNIT_SIZE (MODE) / 4 - 1) \
1449 & (0x10000 - GET_MODE_UNIT_SIZE (MODE) / 4))
1451 #define ROUND_ADVANCE(SIZE) \
1452 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1454 #else /* ! SPARC_ARCH64 */
1456 #define CUMULATIVE_ARGS int
1458 #define ROUND_REG(CUM, MODE) (CUM)
1460 #define ROUND_ADVANCE(SIZE) \
1461 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1462 #endif /* ! SPARC_ARCH64 */
1464 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1465 for a call to a function whose data type is FNTYPE.
1466 For a library call, FNTYPE is 0.
1468 On SPARC, the offset always starts at 0: the first parm reg is always
1472 extern int sparc_arg_count,sparc_n_named_args;
1473 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1475 (CUM).arg_count[(int) SPARC_ARG_INT] = 0; \
1476 (CUM).arg_count[(int) SPARC_ARG_FLOAT] = 0; \
1477 sparc_arg_count = 0; \
1478 sparc_n_named_args = \
1479 ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE) \
1480 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) \
1481 + (TREE_CODE (TREE_TYPE (FNTYPE)) == RECORD_TYPE \
1482 || TREE_CODE (TREE_TYPE (FNTYPE)) == QUAL_UNION_TYPE\
1483 || TREE_CODE (TREE_TYPE (FNTYPE)) == SET_TYPE \
1484 || TREE_CODE (TREE_TYPE (FNTYPE)) == UNION_TYPE)) \
1485 /* Can't tell, treat 'em all as named. */ \
1489 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) ((CUM) = 0)
1492 /* Update the data in CUM to advance over an argument
1493 of mode MODE and data type TYPE.
1494 (TYPE is null for libcalls where that information may not be available.) */
1497 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1499 (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] = \
1500 ROUND_REG ((CUM), (MODE)) \
1501 + (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1502 ? GET_MODE_SIZE (MODE) / 4 \
1503 : ROUND_ADVANCE ((MODE) == BLKmode \
1504 ? GET_MODE_SIZE (Pmode) \
1505 : GET_MODE_SIZE (MODE))); \
1506 sparc_arg_count++; \
1509 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1510 ((CUM) += ((MODE) != BLKmode \
1511 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
1512 : ROUND_ADVANCE (int_size_in_bytes (TYPE))))
1515 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1516 This macro is only used in this file. */
1519 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1520 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \
1521 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1522 && ((TYPE)==0 || (MODE) != BLKmode))
1524 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1525 ((CUM) < NPARM_REGS (SImode) \
1526 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1527 && ((TYPE)==0 || (MODE) != BLKmode \
1528 || (TYPE_ALIGN (TYPE) % PARM_BOUNDARY == 0)))
1531 /* Determine where to put an argument to a function.
1532 Value is zero to push the argument on the stack,
1533 or a hard register in which to store the argument.
1535 MODE is the argument's machine mode.
1536 TYPE is the data type of the argument (as a tree).
1537 This is null for libcalls where that information may
1539 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1540 the preceding args and about the function being called.
1541 NAMED is nonzero if this argument is a named parameter
1542 (otherwise it is an extra parameter matching an ellipsis). */
1544 /* On SPARC the first six args are normally in registers
1545 and the rest are pushed. Any arg that starts within the first 6 words
1546 is at least partially passed in a register unless its data type forbids.
1547 For v9, the first 6 int args are passed in regs and the first N
1548 float args are passed in regs (where N is such that %f0-15 are filled).
1549 The rest are pushed. Any arg that starts within the first 6 words
1550 is at least partially passed in a register unless its data type forbids. */
1552 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1553 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1554 ? gen_rtx (REG, (MODE), \
1555 (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\
1558 /* Define where a function finds its arguments.
1559 This is different from FUNCTION_ARG because of register windows. */
1561 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1562 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1563 ? gen_rtx (REG, (MODE), \
1564 (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\
1567 /* For an arg passed partly in registers and partly in memory,
1568 this is the number of registers used.
1569 For args passed entirely in registers or entirely in memory, zero.
1570 Any arg that starts in the first 6 regs but won't entirely fit in them
1571 needs partial registers on the Sparc (!v9). On v9, there are no arguments
1572 that are passed partially in registers (??? complex values?). */
1575 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1576 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1577 && ((CUM) + ((MODE) == BLKmode \
1578 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1579 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS (SImode) > 0)\
1580 ? (NPARM_REGS (SImode) - (CUM)) \
1584 /* The SPARC ABI stipulates passing struct arguments (of any size) and
1585 (!v9) quad-precision floats by invisible reference.
1586 For Pascal, also pass arrays by reference. */
1587 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1588 ((TYPE && AGGREGATE_TYPE_P (TYPE)) \
1589 || (!TARGET_ARCH64 && MODE == TFmode))
1591 /* A C expression that indicates when it is the called function's
1592 responsibility to make copies of arguments passed by reference.
1593 If the callee can determine that the argument won't be modified, it can
1595 /* ??? We'd love to be able to use NAMED here. Unfortunately, it doesn't
1596 include the last named argument so we keep track of the args ourselves. */
1599 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
1600 (sparc_arg_count < sparc_n_named_args)
1603 /* Initialize data used by insn expanders. This is called from
1604 init_emit, once for each function, before code is generated.
1605 For v9, clear the temp slot used by float/int DImode conversions.
1606 ??? There is the 16 bytes at [%fp-16], however we'd like to delete this
1607 space at some point.
1608 ??? Use assign_stack_temp? */
1610 extern void sparc64_init_expanders ();
1611 extern struct rtx_def *sparc64_fpconv_stack_temp ();
1613 #define INIT_EXPANDERS sparc64_init_expanders ()
1616 /* Define the information needed to generate branch and scc insns. This is
1617 stored from the compare operation. Note that we can't use "rtx" here
1618 since it hasn't been defined! */
1620 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
1622 /* Define the function that build the compare insn for scc and bcc. */
1624 extern struct rtx_def *gen_compare_reg ();
1626 /* This function handles all v9 scc insns */
1628 extern int gen_v9_scc ();
1630 /* Generate the special assembly code needed to tell the assembler whatever
1631 it might need to know about the return value of a function.
1633 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
1634 information to the assembler relating to peephole optimization (done in
1637 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1638 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
1640 /* Output the label for a function definition. */
1642 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
1644 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
1645 ASM_OUTPUT_LABEL (FILE, NAME); \
1648 /* This macro generates the assembly code for function entry.
1649 FILE is a stdio stream to output the code to.
1650 SIZE is an int: how many units of temporary storage to allocate.
1651 Refer to the array `regs_ever_live' to determine which registers
1652 to save; `regs_ever_live[I]' is nonzero if register number I
1653 is ever used in the function. This macro is responsible for
1654 knowing which registers should not be saved even if used. */
1656 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
1657 of memory. If any fpu reg is used in the function, we allocate
1658 such a block here, at the bottom of the frame, just in case it's needed.
1660 If this function is a leaf procedure, then we may choose not
1661 to do a "save" insn. The decision about whether or not
1662 to do this is made in regclass.c. */
1664 extern int leaf_function;
1665 #define FUNCTION_PROLOGUE(FILE, SIZE) \
1666 (TARGET_FLAT ? sparc_flat_output_function_prologue (FILE, SIZE) \
1667 : output_function_prologue (FILE, SIZE, leaf_function))
1669 /* Output assembler code to FILE to increment profiler label # LABELNO
1670 for profiling a function entry.
1672 32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered
1673 during profiling so we need to save/restore it around the call to mcount.
1674 We're guaranteed that a save has just been done, and we use the space
1675 allocated for intreg/fpreg value passing. */
1677 #define FUNCTION_PROFILER(FILE, LABELNO) \
1679 if (! TARGET_ARCH64) \
1680 fputs ("\tst %g2,[%fp-4]\n", FILE); \
1681 fputs ("\tsethi %hi(", (FILE)); \
1682 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
1683 fputs ("),%o0\n", (FILE)); \
1684 if (TARGET_MEDANY) \
1685 fprintf (FILE, "\tadd %%o0,%s,%%o0\n", \
1687 fputs ("\tcall mcount\n\tadd %lo(", (FILE)); \
1688 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
1689 fputs ("),%o0,%o0\n", (FILE)); \
1690 if (! TARGET_ARCH64) \
1691 fputs ("\tld [%fp-4],%g2\n", FILE); \
1694 /* There are three profiling modes for basic blocks available.
1695 The modes are selected at compile time by using the options
1696 -a or -ax of the gnu compiler.
1697 The variable `profile_block_flag' will be set according to the
1700 profile_block_flag == 0, no option used:
1704 profile_block_flag == 1, -a option used.
1706 Count frequency of execution of every basic block.
1708 profile_block_flag == 2, -ax option used.
1710 Generate code to allow several different profiling modes at run time.
1711 Available modes are:
1712 Produce a trace of all basic blocks.
1713 Count frequency of jump instructions executed.
1714 In every mode it is possible to start profiling upon entering
1715 certain functions and to disable profiling of some other functions.
1717 The result of basic-block profiling will be written to a file `bb.out'.
1718 If the -ax option is used parameters for the profiling will be read
1723 /* The following macro shall output assembler code to FILE
1724 to initialize basic-block profiling.
1726 If profile_block_flag == 2
1728 Output code to call the subroutine `__bb_init_trace_func'
1729 and pass two parameters to it. The first parameter is
1730 the address of a block allocated in the object module.
1731 The second parameter is the number of the first basic block
1734 The name of the block is a local symbol made with this statement:
1736 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
1738 Of course, since you are writing the definition of
1739 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1740 can take a short cut in the definition of this macro and use the
1741 name that you know will result.
1743 The number of the first basic block of the function is
1744 passed to the macro in BLOCK_OR_LABEL.
1746 If described in a virtual assembler language the code to be
1750 parameter2 <- BLOCK_OR_LABEL
1751 call __bb_init_trace_func
1753 else if profile_block_flag != 0
1755 Output code to call the subroutine `__bb_init_func'
1756 and pass one single parameter to it, which is the same
1757 as the first parameter to `__bb_init_trace_func'.
1759 The first word of this parameter is a flag which will be nonzero if
1760 the object module has already been initialized. So test this word
1761 first, and do not call `__bb_init_func' if the flag is nonzero.
1762 Note: When profile_block_flag == 2 the test need not be done
1763 but `__bb_init_trace_func' *must* be called.
1765 BLOCK_OR_LABEL may be used to generate a label number as a
1766 branch destination in case `__bb_init_func' will not be called.
1768 If described in a virtual assembler language the code to be
1779 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1782 int bol = (BLOCK_OR_LABEL); \
1783 switch (profile_block_flag) \
1786 if (TARGET_MEDANY) \
1787 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tadd %%o0,%s,%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tadd %g0,%%lo(%d),%%o1\n",\
1788 MEDANY_BASE_REG, bol, bol); \
1790 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%o0,%%lo(LPBX0),%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tor %%o1,%%lo(%d),%%o1\n",\
1794 if (TARGET_MEDANY) \
1795 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%s,%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\
1796 MEDANY_BASE_REG, bol, MEDANY_BASE_REG, bol);\
1798 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\
1805 /* The following macro shall output assembler code to FILE
1806 to increment a counter associated with basic block number BLOCKNO.
1808 If profile_block_flag == 2
1810 Output code to initialize the global structure `__bb' and
1811 call the function `__bb_trace_func' which will increment the
1814 `__bb' consists of two words. In the first word the number
1815 of the basic block has to be stored. In the second word
1816 the address of a block allocated in the object module
1819 The basic block number is given by BLOCKNO.
1821 The address of the block is given by the label created with
1823 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
1825 by FUNCTION_BLOCK_PROFILER.
1827 Of course, since you are writing the definition of
1828 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1829 can take a short cut in the definition of this macro and use the
1830 name that you know will result.
1832 If described in a virtual assembler language the code to be
1835 move BLOCKNO -> (__bb)
1836 move LPBX0 -> (__bb+4)
1837 call __bb_trace_func
1839 Note that function `__bb_trace_func' must not change the
1840 machine state, especially the flag register. To grant
1841 this, you must output code to save and restore registers
1842 either in this macro or in the macros MACHINE_STATE_SAVE
1843 and MACHINE_STATE_RESTORE. The last two macros will be
1844 used in the function `__bb_trace_func', so you must make
1845 sure that the function prologue does not change any
1846 register prior to saving it with MACHINE_STATE_SAVE.
1848 else if profile_block_flag != 0
1850 Output code to increment the counter directly.
1851 Basic blocks are numbered separately from zero within each
1852 compiled object module. The count associated with block number
1853 BLOCKNO is at index BLOCKNO in an array of words; the name of
1854 this array is a local symbol made with this statement:
1856 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
1858 Of course, since you are writing the definition of
1859 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1860 can take a short cut in the definition of this macro and use the
1861 name that you know will result.
1863 If described in a virtual assembler language, the code to be
1866 inc (LPBX2+4*BLOCKNO)
1870 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1873 int blockn = (BLOCKNO); \
1874 switch (profile_block_flag) \
1877 if (TARGET_MEDANY) \
1878 fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tor %%0,%%lo(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%s+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%0,%%lo(LPBX0),%%g2\n\tadd %%g2,%s,%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%g1+%%lo(___bb)]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\
1879 blockn, blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
1881 fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%g2,%%lo(LPBX0),%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\
1885 if (TARGET_MEDANY) \
1886 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tor %%g1,%%lo(LPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \
1887 4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
1889 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
1890 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
1891 4 * blockn, 4 * blockn, 4 * blockn); \
1897 /* The following macro shall output assembler code to FILE
1898 to indicate a return from function during basic-block profiling.
1900 If profiling_block_flag == 2:
1902 Output assembler code to call function `__bb_trace_ret'.
1904 Note that function `__bb_trace_ret' must not change the
1905 machine state, especially the flag register. To grant
1906 this, you must output code to save and restore registers
1907 either in this macro or in the macros MACHINE_STATE_SAVE_RET
1908 and MACHINE_STATE_RESTORE_RET. The last two macros will be
1909 used in the function `__bb_trace_ret', so you must make
1910 sure that the function prologue does not change any
1911 register prior to saving it with MACHINE_STATE_SAVE_RET.
1913 else if profiling_block_flag != 0:
1915 The macro will not be used, so it need not distinguish
1919 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1920 fprintf (FILE, "\tcall ___bb_trace_ret\n\tnop\n" );
1922 /* The function `__bb_trace_func' is called in every basic block
1923 and is not allowed to change the machine state. Saving (restoring)
1924 the state can either be done in the BLOCK_PROFILER macro,
1925 before calling function (rsp. after returning from function)
1926 `__bb_trace_func', or it can be done inside the function by
1927 defining the macros:
1929 MACHINE_STATE_SAVE(ID)
1930 MACHINE_STATE_RESTORE(ID)
1932 In the latter case care must be taken, that the prologue code
1933 of function `__bb_trace_func' does not already change the
1934 state prior to saving it with MACHINE_STATE_SAVE.
1936 The parameter `ID' is a string identifying a unique macro use.
1938 On sparc it is sufficient to save the psw register to memory.
1939 Unfortunately the psw register can be read in supervisor mode only,
1940 so we read only the condition codes by using branch instructions
1941 and hope that this is enough. */
1943 #define MACHINE_STATE_SAVE(ID) \
1944 asm (" mov %g0,%l0");\
1945 asm (" be,a LFLGNZ" ID);\
1946 asm (" or %l0,4,%l0");\
1947 asm ("LFLGNZ" ID ": bcs,a LFLGNC" ID);\
1948 asm (" or %l0,1,%l0");\
1949 asm ("LFLGNC" ID ": bvs,a LFLGNV" ID);\
1950 asm (" or %l0,2,%l0");\
1951 asm ("LFLGNV" ID ": bneg,a LFLGNN" ID);\
1952 asm (" or %l0,8,%l0");\
1953 asm ("LFLGNN" ID ": sethi %hi(LFLAGS" ID "),%l1");\
1954 asm (" st %l0,[%l1+%lo(LFLAGS" ID ")]"); \
1955 asm (" st %g2,[%l1+%lo(LSAVRET" ID ")]");
1957 /* On sparc MACHINE_STATE_RESTORE restores the psw register from memory.
1958 The psw register can be written in supervisor mode only,
1959 which is true even for simple condition codes.
1960 We use some combination of instructions to produce the
1961 proper condition codes, but some flag combinations can not
1962 be generated in this way. If this happens an unimplemented
1963 instruction will be executed to abort the program. */
1965 #define MACHINE_STATE_RESTORE(ID) \
1966 asm (" sethi %hi(LFLGTAB" ID "),%l1");\
1967 asm (" ld [%l1+%lo(LFLGTAB" ID "-(LFLGTAB" ID "-LFLAGS" ID "))],%l0");\
1968 asm (" ld [%l1+%lo(LFLGTAB" ID "-(LFLGTAB" ID "-LSAVRET" ID "))],%g2");\
1969 asm (" sll %l0,2,%l0");\
1970 asm (" add %l0,%l1,%l0");\
1971 asm (" ld [%l0+%lo(LFLGTAB" ID ")],%l1");\
1976 asm ("LFLAGS" ID ":");\
1978 asm ("LSAVRET" ID ":");\
1980 asm ("LFLGTAB" ID ": ");\
1981 asm (" .word LSFLG0" ID);\
1982 asm (" .word LSFLGC" ID);\
1983 asm (" .word LSFLGV" ID);\
1984 asm (" .word LSFLGVC" ID);\
1985 asm (" .word LSFLGZ" ID);\
1986 asm (" .word LSFLGZC" ID);\
1987 asm (" .word LSFLGZV" ID);\
1988 asm (" .word LSFLGZVC" ID);\
1989 asm (" .word LSFLGN" ID);\
1990 asm (" .word LSFLGNC" ID);\
1991 asm (" .word LSFLGNV" ID);\
1992 asm (" .word LSFLGNVC" ID);\
1993 asm (" .word LSFLGNZ" ID);\
1994 asm (" .word LSFLGNZC" ID);\
1995 asm (" .word LSFLGNZV" ID);\
1996 asm (" .word LSFLGNZVC" ID);\
1998 asm ("LSFLGVC" ID ": mov -1,%l0");\
1999 asm (" addcc 2,%l0,%g0");\
2000 asm (" sethi %hi(0x80000000),%l0");\
2001 asm (" mov %l0,%l1");\
2002 asm (" ba LFLGRET" ID);\
2003 asm (" addxcc %l0,%l1,%l0");\
2004 asm ("LSFLGC" ID ": mov -1,%l0");\
2005 asm (" ba LFLGRET" ID);\
2006 asm (" addcc 2,%l0,%g0");\
2007 asm ("LSFLGZC" ID ": mov -1,%l0");\
2008 asm (" ba LFLGRET" ID);\
2009 asm (" addcc 1,%l0,%l0");\
2010 asm ("LSFLGZVC" ID ": sethi %hi(0x80000000),%l0");\
2011 asm (" mov %l0,%l1");\
2012 asm (" ba LFLGRET" ID);\
2013 asm (" addcc %l0,%l1,%l0");\
2014 asm ("LSFLGZ" ID ": ba LFLGRET" ID);\
2015 asm (" subcc %g0,%g0,%g0");\
2016 asm ("LSFLGNC" ID ": add %g0,1,%l0");\
2017 asm (" ba LFLGRET" ID);\
2018 asm (" subcc %g0,%l0,%g0");\
2019 asm ("LSFLG0" ID ": ba LFLGRET" ID);\
2020 asm (" orcc 1,%g0,%g0");\
2021 asm ("LSFLGN" ID ": ba LFLGRET" ID);\
2022 asm (" orcc -1,%g0,%g0");\
2023 asm ("LSFLGV" ID ":");\
2024 asm ("LSFLGZV" ID ":");\
2025 asm ("LSFLGNV" ID ":");\
2026 asm ("LSFLGNVC" ID ":");\
2027 asm ("LSFLGNZ" ID ":");\
2028 asm ("LSFLGNZC" ID ":");\
2029 asm ("LSFLGNZV" ID ":");\
2030 asm ("LSFLGNZVC" ID ":");\
2032 asm ("LFLGRET" ID ":");
2034 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2035 the stack pointer does not matter. The value is tested only in
2036 functions that have frame pointers.
2037 No definition is equivalent to always zero. */
2039 extern int current_function_calls_alloca;
2040 extern int current_function_outgoing_args_size;
2042 #define EXIT_IGNORE_STACK \
2043 (get_frame_size () != 0 \
2044 || current_function_calls_alloca || current_function_outgoing_args_size)
2046 /* This macro generates the assembly code for function exit,
2047 on machines that need it. If FUNCTION_EPILOGUE is not defined
2048 then individual return instructions are generated for each
2049 return statement. Args are same as for FUNCTION_PROLOGUE.
2051 The function epilogue should not depend on the current stack pointer!
2052 It should use the frame pointer only. This is mandatory because
2053 of alloca; we also take advantage of it to omit stack adjustments
2054 before returning. */
2056 /* This declaration is needed due to traditional/ANSI
2057 incompatibilities which cannot be #ifdefed away
2058 because they occur inside of macros. Sigh. */
2059 extern union tree_node *current_function_decl;
2061 #define FUNCTION_EPILOGUE(FILE, SIZE) \
2062 (TARGET_FLAT ? sparc_flat_output_function_epilogue (FILE, SIZE) \
2063 : output_function_epilogue (FILE, SIZE, leaf_function))
2065 #define DELAY_SLOTS_FOR_EPILOGUE \
2066 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
2067 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
2068 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
2069 : eligible_for_epilogue_delay (trial, slots_filled))
2071 /* Output assembler code for a block containing the constant parts
2072 of a trampoline, leaving space for the variable parts. */
2074 /* On 32 bit sparcs, the trampoline contains five instructions:
2075 sethi #TOP_OF_FUNCTION,%g1
2076 or #BOTTOM_OF_FUNCTION,%g1,%g1
2077 sethi #TOP_OF_STATIC,%g2
2079 or #BOTTOM_OF_STATIC,%g2,%g2
2081 On 64 bit sparcs, the trampoline contains 4 insns and two pseudo-immediate
2082 constants (plus some padding):
2092 #define TRAMPOLINE_TEMPLATE(FILE) \
2094 if (TARGET_ARCH64) \
2096 fprintf (FILE, "\trd %%pc,%%g1\n"); \
2097 fprintf (FILE, "\tldx [%%g1+24],%%g5\n"); \
2098 fprintf (FILE, "\tldx [%%g1+32],%%g1\n"); \
2099 fprintf (FILE, "\tjmp %%g1\n"); \
2100 fprintf (FILE, "\tnop\n"); \
2101 fprintf (FILE, "\tnop\n"); \
2102 /* -mmedlow shouldn't generate .xwords, so don't use them at all */ \
2103 fprintf (FILE, "\t.word 0,0,0,0\n"); \
2107 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2108 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2109 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2110 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C04000)); \
2111 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2115 /* Length in units of the trampoline for entering a nested function. */
2117 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 40 : 20)
2119 /* Emit RTL insns to initialize the variable parts of a trampoline.
2120 FNADDR is an RTX for the address of the function's pure code.
2121 CXT is an RTX for the static chain value for the function. */
2123 void sparc_initialize_trampoline ();
2124 void sparc64_initialize_trampoline ();
2125 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2127 if (TARGET_ARCH64) \
2128 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
2130 sparc_initialize_trampoline (TRAMP, FNADDR, CXT); \
2133 /* Generate necessary RTL for __builtin_saveregs().
2134 ARGLIST is the argument list; see expr.c. */
2135 extern struct rtx_def *sparc_builtin_saveregs ();
2136 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST)
2138 /* Generate RTL to flush the register windows so as to make arbitrary frames
2140 #define SETUP_FRAME_ADDRESSES() \
2141 emit_insn (gen_flush_register_windows ())
2143 /* Given an rtx for the address of a frame,
2144 return an rtx for the address of the word in the frame
2145 that holds the dynamic chain--the previous frame's address.
2146 ??? -mflat support? */
2147 #define DYNAMIC_CHAIN_ADDRESS(frame) \
2148 gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 14 * UNITS_PER_WORD))
2150 /* The return address isn't on the stack, it is in a register, so we can't
2151 access it from the current frame pointer. We can access it from the
2152 previous frame pointer though by reading a value from the register window
2154 #define RETURN_ADDR_IN_PREVIOUS_FRAME
2156 /* This is the offset of the return address to the true next instruction to be
2157 executed for the current function. */
2158 #define RETURN_ADDR_OFFSET \
2159 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
2161 /* The current return address is in %i7. The return address of anything
2162 farther back is in the register window save area at [%fp+60]. */
2163 /* ??? This ignores the fact that the actual return address is +8 for normal
2164 returns, and +12 for structure returns. */
2165 #define RETURN_ADDR_RTX(count, frame) \
2167 ? gen_rtx (REG, Pmode, 31) \
2168 : gen_rtx (MEM, Pmode, \
2169 memory_address (Pmode, plus_constant (frame, 15 * UNITS_PER_WORD))))
2171 /* Addressing modes, and classification of registers for them. */
2173 /* #define HAVE_POST_INCREMENT */
2174 /* #define HAVE_POST_DECREMENT */
2176 /* #define HAVE_PRE_DECREMENT */
2177 /* #define HAVE_PRE_INCREMENT */
2179 /* Macros to check register numbers against specific register classes. */
2181 /* These assume that REGNO is a hard or pseudo reg number.
2182 They give nonzero only if REGNO is a hard reg of the suitable class
2183 or a pseudo reg currently allocated to a suitable hard reg.
2184 Since they use reg_renumber, they are safe only once reg_renumber
2185 has been allocated, which happens in local-alloc.c. */
2187 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2188 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
2189 #define REGNO_OK_FOR_BASE_P(REGNO) \
2190 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
2191 #define REGNO_OK_FOR_FP_P(REGNO) \
2192 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? 64 : 32)) \
2193 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? 64 : 32)))
2194 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2196 && (((unsigned) (REGNO) - 96 < 4) \
2197 || ((unsigned) reg_renumber[REGNO] - 96 < 4)))
2199 /* Now macros that check whether X is a register and also,
2200 strictly, whether it is in a specified class.
2202 These macros are specific to the SPARC, and may be used only
2203 in code for printing assembler insns and in conditions for
2204 define_optimization. */
2206 /* 1 if X is an fp register. */
2208 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2210 /* Maximum number of registers that can appear in a valid memory address. */
2212 #define MAX_REGS_PER_ADDRESS 2
2214 /* Recognize any constant value that is a valid address.
2215 When PIC, we do not accept an address that would require a scratch reg
2216 to load into a register. */
2218 #define CONSTANT_ADDRESS_P(X) \
2219 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2220 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2221 || (GET_CODE (X) == CONST \
2222 && ! (flag_pic && pic_address_needs_scratch (X))))
2224 /* Define this, so that when PIC, reload won't try to reload invalid
2225 addresses which require two reload registers. */
2227 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2229 /* Nonzero if the constant value X is a legitimate general operand.
2230 Anything can be made to work except floating point constants. */
2232 #define LEGITIMATE_CONSTANT_P(X) \
2233 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
2235 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2236 and check its validity for a certain class.
2237 We have two alternate definitions for each of them.
2238 The usual definition accepts all pseudo regs; the other rejects
2239 them unless they have been allocated suitable hard regs.
2240 The symbol REG_OK_STRICT causes the latter definition to be used.
2242 Most source files want to accept pseudo regs in the hope that
2243 they will get allocated to the class that the insn wants them to be in.
2244 Source files for reload pass need to be strict.
2245 After reload, it makes no difference, since pseudo regs have
2246 been eliminated by then. */
2248 /* Optional extra constraints for this machine. Borrowed from romp.h.
2250 For the SPARC, `Q' means that this is a memory operand but not a
2251 symbolic memory operand. Note that an unassigned pseudo register
2252 is such a memory operand. Needed because reload will generate
2253 these things in insns and then not re-recognize the insns, causing
2254 constrain_operands to fail.
2256 `S' handles constraints for calls. ??? So where is it? */
2258 #ifndef REG_OK_STRICT
2260 /* Nonzero if X is a hard reg that can be used as an index
2261 or if it is a pseudo reg. */
2262 #define REG_OK_FOR_INDEX_P(X) \
2263 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
2264 /* Nonzero if X is a hard reg that can be used as a base reg
2265 or if it is a pseudo reg. */
2266 #define REG_OK_FOR_BASE_P(X) \
2267 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
2269 /* 'T', 'U' are for aligned memory loads which aren't needed for v9. */
2271 #define EXTRA_CONSTRAINT(OP, C) \
2273 ? ((GET_CODE (OP) == MEM \
2274 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
2275 && ! symbolic_memory_operand (OP, VOIDmode)) \
2276 || (reload_in_progress && GET_CODE (OP) == REG \
2277 && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
2278 : (! TARGET_ARCH64 && (C) == 'T') \
2279 ? (mem_aligned_8 (OP)) \
2280 : (! TARGET_ARCH64 && (C) == 'U') \
2281 ? (register_ok_for_ldd (OP)) \
2286 /* Nonzero if X is a hard reg that can be used as an index. */
2287 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2288 /* Nonzero if X is a hard reg that can be used as a base reg. */
2289 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2291 #define EXTRA_CONSTRAINT(OP, C) \
2293 ? (GET_CODE (OP) == REG \
2294 ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
2295 && reg_renumber[REGNO (OP)] < 0) \
2296 : GET_CODE (OP) == MEM) \
2297 : (! TARGET_ARCH64 && (C) == 'T') \
2298 ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
2299 : (! TARGET_ARCH64 && (C) == 'U') \
2300 ? (GET_CODE (OP) == REG \
2301 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
2302 || reg_renumber[REGNO (OP)] >= 0) \
2303 && register_ok_for_ldd (OP)) \
2307 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2308 that is a valid memory address for an instruction.
2309 The MODE argument is the machine mode for the MEM expression
2310 that wants to use this address.
2312 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2313 ordinarily. This changes a bit when generating PIC.
2315 If you change this, execute "rm explow.o recog.o reload.o". */
2317 #define RTX_OK_FOR_BASE_P(X) \
2318 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2319 || (GET_CODE (X) == SUBREG \
2320 && GET_CODE (SUBREG_REG (X)) == REG \
2321 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2323 #define RTX_OK_FOR_INDEX_P(X) \
2324 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2325 || (GET_CODE (X) == SUBREG \
2326 && GET_CODE (SUBREG_REG (X)) == REG \
2327 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2329 #define RTX_OK_FOR_OFFSET_P(X) \
2330 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
2332 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2333 { if (RTX_OK_FOR_BASE_P (X)) \
2335 else if (GET_CODE (X) == PLUS) \
2337 register rtx op0 = XEXP (X, 0); \
2338 register rtx op1 = XEXP (X, 1); \
2339 if (flag_pic && op0 == pic_offset_table_rtx) \
2341 if (RTX_OK_FOR_BASE_P (op1)) \
2343 else if (flag_pic == 1 \
2344 && GET_CODE (op1) != REG \
2345 && GET_CODE (op1) != LO_SUM \
2346 && GET_CODE (op1) != MEM \
2347 && (GET_CODE (op1) != CONST_INT \
2348 || SMALL_INT (op1))) \
2351 else if (RTX_OK_FOR_BASE_P (op0)) \
2353 if (RTX_OK_FOR_INDEX_P (op1) \
2354 || RTX_OK_FOR_OFFSET_P (op1)) \
2357 else if (RTX_OK_FOR_BASE_P (op1)) \
2359 if (RTX_OK_FOR_INDEX_P (op0) \
2360 || RTX_OK_FOR_OFFSET_P (op0)) \
2364 else if (GET_CODE (X) == LO_SUM) \
2366 register rtx op0 = XEXP (X, 0); \
2367 register rtx op1 = XEXP (X, 1); \
2368 if (RTX_OK_FOR_BASE_P (op0) \
2369 && CONSTANT_P (op1) \
2370 /* We can't allow TFmode, because an offset \
2371 greater than or equal to the alignment (8) \
2372 may cause the LO_SUM to overflow. */ \
2373 && MODE != TFmode) \
2376 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
2380 /* Try machine-dependent ways of modifying an illegitimate address
2381 to be legitimate. If we find one, return the new, valid address.
2382 This macro is used in only one place: `memory_address' in explow.c.
2384 OLDX is the address as it was before break_out_memory_refs was called.
2385 In some cases it is useful to look at this to decide what needs to be done.
2387 MODE and WIN are passed so that this macro can use
2388 GO_IF_LEGITIMATE_ADDRESS.
2390 It is always safe for this macro to do nothing. It exists to recognize
2391 opportunities to optimize the output. */
2393 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2394 extern struct rtx_def *legitimize_pic_address ();
2395 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2396 { rtx sparc_x = (X); \
2397 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
2398 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
2399 force_operand (XEXP (X, 0), NULL_RTX)); \
2400 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
2401 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2402 force_operand (XEXP (X, 1), NULL_RTX)); \
2403 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
2404 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
2406 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
2407 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2408 force_operand (XEXP (X, 1), NULL_RTX)); \
2409 if (sparc_x != (X) && memory_address_p (MODE, X)) \
2411 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
2412 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
2413 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2414 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
2415 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
2416 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
2417 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
2418 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
2419 || GET_CODE (X) == LABEL_REF) \
2420 (X) = gen_rtx (LO_SUM, Pmode, \
2421 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2422 if (memory_address_p (MODE, X)) \
2425 /* Go to LABEL if ADDR (a legitimate address expression)
2426 has an effect that depends on the machine mode it is used for.
2427 On the SPARC this is never true. */
2429 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2431 /* If we are referencing a function make the SYMBOL_REF special.
2432 In the Medium/Anywhere code model, %g4 points to the data segment so we
2433 must not add it to function addresses. */
2435 #define ENCODE_SECTION_INFO(DECL) \
2437 if (TARGET_MEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
2438 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2441 /* Specify the machine mode that this machine uses
2442 for the index in the tablejump instruction. */
2443 #define CASE_VECTOR_MODE Pmode
2445 /* Define this if the tablejump instruction expects the table
2446 to contain offsets from the address of the table.
2447 Do not define this if the table should contain absolute addresses. */
2448 /* #define CASE_VECTOR_PC_RELATIVE */
2450 /* Specify the tree operation to be used to convert reals to integers. */
2451 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2453 /* This is the kind of divide that is easiest to do in the general case. */
2454 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2456 /* Define this as 1 if `char' should by default be signed; else as 0. */
2457 #define DEFAULT_SIGNED_CHAR 1
2459 /* Max number of bytes we can move from memory to memory
2460 in one reasonably fast instruction. */
2463 #if 0 /* Sun 4 has matherr, so this is no good. */
2464 /* This is the value of the error code EDOM for this machine,
2465 used by the sqrt instruction. */
2466 #define TARGET_EDOM 33
2468 /* This is how to refer to the variable errno. */
2469 #define GEN_ERRNO_RTX \
2470 gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
2473 /* Define if operations between registers always perform the operation
2474 on the full register even if a narrower mode is specified. */
2475 #define WORD_REGISTER_OPERATIONS
2477 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2478 will either zero-extend or sign-extend. The value of this macro should
2479 be the code that says which one of the two operations is implicitly
2480 done, NIL if none. */
2481 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2483 /* Nonzero if access to memory by bytes is slow and undesirable.
2484 For RISC chips, it means that access to memory by bytes is no
2485 better than access by words when possible, so grab a whole word
2486 and maybe make use of that. */
2487 #define SLOW_BYTE_ACCESS 1
2489 /* We assume that the store-condition-codes instructions store 0 for false
2490 and some other value for true. This is the value stored for true. */
2492 #define STORE_FLAG_VALUE 1
2494 /* When a prototype says `char' or `short', really pass an `int'. */
2495 #define PROMOTE_PROTOTYPES
2497 /* Define this to be nonzero if shift instructions ignore all but the low-order
2499 #define SHIFT_COUNT_TRUNCATED 1
2501 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2502 is done just by pretending it is already truncated. */
2503 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2505 /* Specify the machine mode that pointers have.
2506 After generation of rtl, the compiler makes no further distinction
2507 between pointers and any other objects of this machine mode. */
2508 #define Pmode (TARGET_PTR64 ? DImode : SImode)
2510 /* Generate calls to memcpy, memcmp and memset. */
2511 #define TARGET_MEM_FUNCTIONS
2513 /* Add any extra modes needed to represent the condition code.
2515 On the Sparc, we have a "no-overflow" mode which is used when an add or
2516 subtract insn is used to set the condition code. Different branches are
2517 used in this case for some operations.
2519 We also have two modes to indicate that the relevant condition code is
2520 in the floating-point condition code register. One for comparisons which
2521 will generate an exception if the result is unordered (CCFPEmode) and
2522 one for comparisons which will never trap (CCFPmode).
2524 CCXmode and CCX_NOOVmode are only used by v9. */
2526 #define EXTRA_CC_MODES CCXmode, CC_NOOVmode, CCX_NOOVmode, CCFPmode, CCFPEmode
2528 /* Define the names for the modes specified above. */
2530 #define EXTRA_CC_NAMES "CCX", "CC_NOOV", "CCX_NOOV", "CCFP", "CCFPE"
2532 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2533 return the mode to be used for the comparison. For floating-point,
2534 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
2535 PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2536 processing is needed. */
2537 #define SELECT_CC_MODE(OP,X,Y) \
2538 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2539 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
2540 : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
2541 || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \
2542 ? (TARGET_ARCH64 && GET_MODE (X) == DImode ? CCX_NOOVmode : CC_NOOVmode) \
2543 : (TARGET_ARCH64 && GET_MODE (X) == DImode ? CCXmode : CCmode)))
2545 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
2546 floating point inequality comparison. */
2548 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2550 /* A function address in a call instruction
2551 is a byte address (for indexing purposes)
2552 so give the MEM rtx a byte's mode. */
2553 #define FUNCTION_MODE SImode
2555 /* Define this if addresses of constant functions
2556 shouldn't be put through pseudo regs where they can be cse'd.
2557 Desirable on machines where ordinary constants are expensive
2558 but a CALL with constant address is cheap. */
2559 #define NO_FUNCTION_CSE
2561 /* alloca should avoid clobbering the old register save area. */
2562 #define SETJMP_VIA_SAVE_AREA
2564 /* Define subroutines to call to handle multiply and divide.
2565 Use the subroutines that Sun's library provides.
2566 The `*' prevents an underscore from being prepended by the compiler. */
2568 #define DIVSI3_LIBCALL "*.div"
2569 #define UDIVSI3_LIBCALL "*.udiv"
2570 #define MODSI3_LIBCALL "*.rem"
2571 #define UMODSI3_LIBCALL "*.urem"
2572 /* .umul is a little faster than .mul. */
2573 #define MULSI3_LIBCALL "*.umul"
2575 /* Define library calls for quad FP operations. These are all part of the
2577 #define ADDTF3_LIBCALL "_Q_add"
2578 #define SUBTF3_LIBCALL "_Q_sub"
2579 #define NEGTF2_LIBCALL "_Q_neg"
2580 #define MULTF3_LIBCALL "_Q_mul"
2581 #define DIVTF3_LIBCALL "_Q_div"
2582 #define FLOATSITF2_LIBCALL "_Q_itoq"
2583 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2584 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2585 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2586 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2587 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2588 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2589 #define EQTF2_LIBCALL "_Q_feq"
2590 #define NETF2_LIBCALL "_Q_fne"
2591 #define GTTF2_LIBCALL "_Q_fgt"
2592 #define GETF2_LIBCALL "_Q_fge"
2593 #define LTTF2_LIBCALL "_Q_flt"
2594 #define LETF2_LIBCALL "_Q_fle"
2596 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
2597 with soft-float, the SFmode and DFmode sqrt instructions will be absent,
2598 and the compiler will notice and try to use the TFmode sqrt instruction
2599 for calls to the builtin function sqrt, but this fails. */
2600 #define INIT_TARGET_OPTABS \
2602 add_optab->handlers[(int) TFmode].libfunc \
2603 = gen_rtx (SYMBOL_REF, Pmode, ADDTF3_LIBCALL); \
2604 sub_optab->handlers[(int) TFmode].libfunc \
2605 = gen_rtx (SYMBOL_REF, Pmode, SUBTF3_LIBCALL); \
2606 neg_optab->handlers[(int) TFmode].libfunc \
2607 = gen_rtx (SYMBOL_REF, Pmode, NEGTF2_LIBCALL); \
2608 smul_optab->handlers[(int) TFmode].libfunc \
2609 = gen_rtx (SYMBOL_REF, Pmode, MULTF3_LIBCALL); \
2610 flodiv_optab->handlers[(int) TFmode].libfunc \
2611 = gen_rtx (SYMBOL_REF, Pmode, DIVTF3_LIBCALL); \
2612 eqtf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EQTF2_LIBCALL); \
2613 netf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, NETF2_LIBCALL); \
2614 gttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GTTF2_LIBCALL); \
2615 getf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GETF2_LIBCALL); \
2616 lttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LTTF2_LIBCALL); \
2617 letf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LETF2_LIBCALL); \
2618 trunctfsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFSF2_LIBCALL); \
2619 trunctfdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFDF2_LIBCALL); \
2620 extendsftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDSFTF2_LIBCALL); \
2621 extenddftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDDFTF2_LIBCALL); \
2622 floatsitf_libfunc = gen_rtx (SYMBOL_REF, Pmode, FLOATSITF2_LIBCALL); \
2623 fixtfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, FIX_TRUNCTFSI2_LIBCALL); \
2624 fixunstfsi_libfunc \
2625 = gen_rtx (SYMBOL_REF, Pmode, FIXUNS_TRUNCTFSI2_LIBCALL); \
2627 sqrt_optab->handlers[(int) TFmode].libfunc \
2628 = gen_rtx (SYMBOL_REF, Pmode, "_Q_sqrt"); \
2629 INIT_SUBTARGET_OPTABS; \
2632 /* This is meant to be redefined in the host dependent files */
2633 #define INIT_SUBTARGET_OPTABS
2635 /* Compute the cost of computing a constant rtl expression RTX
2636 whose rtx-code is CODE. The body of this macro is a portion
2637 of a switch statement. If the code is computed here,
2638 return it with a return statement. Otherwise, break from the switch. */
2640 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2642 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
2650 case CONST_DOUBLE: \
2651 if (GET_MODE (RTX) == DImode) \
2652 if ((XINT (RTX, 3) == 0 \
2653 && (unsigned) XINT (RTX, 2) < 0x1000) \
2654 || (XINT (RTX, 3) == -1 \
2655 && XINT (RTX, 2) < 0 \
2656 && XINT (RTX, 2) >= -0x1000)) \
2660 /* Compute the cost of an address. For the sparc, all valid addresses are
2662 ??? Is this true for v9? */
2664 #define ADDRESS_COST(RTX) 1
2666 /* Compute extra cost of moving data between one register class
2668 ??? v9: We ignore FPCC_REGS on the assumption they'll never be seen. */
2669 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
2670 (((FP_REG_CLASS_P (CLASS1) && (CLASS2) == GENERAL_REGS) \
2671 || ((CLASS1) == GENERAL_REGS && FP_REG_CLASS_P (CLASS2))) ? 6 : 2)
2673 /* Provide the costs of a rtl expression. This is in the body of a
2674 switch on CODE. The purpose for the cost of MULT is to encourage
2675 `synth_mult' to find a synthetic multiply when reasonable.
2677 If we need more than 12 insns to do a multiply, then go out-of-line,
2678 since the call overhead will be < 10% of the cost of the multiply. */
2680 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2682 return (TARGET_V8 || TARGET_SPARCLITE || TARGET_V9) \
2683 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
2688 return COSTS_N_INSNS (25); \
2689 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
2690 so that cse will favor the latter. */ \
2695 /* Adjust the cost of dependencies. */
2696 #define ADJUST_COST(INSN,LINK,DEP,COST) \
2697 if (sparc_cpu == PROCESSOR_SUPERSPARC) \
2698 (COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST)
2700 /* Conditional branches with empty delay slots have a length of two. */
2701 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2702 if (GET_CODE (INSN) == CALL_INSN \
2703 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
2706 /* Control the assembler format that we output. */
2708 /* Output at beginning of assembler file. */
2710 #define ASM_FILE_START(file)
2712 /* Output to assembler file text saying following lines
2713 may contain character constants, extra white space, comments, etc. */
2715 #define ASM_APP_ON ""
2717 /* Output to assembler file text saying following lines
2718 no longer contain unusual constructs. */
2720 #define ASM_APP_OFF ""
2722 /* ??? Try to make the style consistent here (_OP?). */
2724 #define ASM_LONGLONG ".xword"
2725 #define ASM_LONG ".word"
2726 #define ASM_SHORT ".half"
2727 #define ASM_BYTE_OP ".byte"
2728 #define ASM_FLOAT ".single"
2729 #define ASM_DOUBLE ".double"
2730 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2732 /* Output before read-only data. */
2734 #define TEXT_SECTION_ASM_OP ".text"
2736 /* Output before writable data. */
2738 #define DATA_SECTION_ASM_OP ".data"
2740 /* How to refer to registers in assembler output.
2741 This sequence is indexed by compiler's hard-register-number (see above). */
2743 #define REGISTER_NAMES \
2744 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2745 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2746 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2747 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2748 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2749 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2750 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2751 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2752 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2753 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2754 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2755 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2756 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc"}
2758 /* Define additional names for use in asm clobbers and asm declarations. */
2760 #define ADDITIONAL_REGISTER_NAMES \
2761 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2763 /* How to renumber registers for dbx and gdb. */
2765 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2767 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
2768 since the length can run past this up to a continuation point. */
2769 #define DBX_CONTIN_LENGTH 1500
2771 /* This is how to output a note to DBX telling it the line number
2772 to which the following sequence of instructions corresponds.
2774 This is needed for SunOS 4.0, and should not hurt for 3.2
2776 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
2777 { static int sym_lineno = 1; \
2778 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
2779 line, sym_lineno, sym_lineno); \
2782 /* This is how to output the definition of a user-level label named NAME,
2783 such as the label on a static function or variable NAME. */
2785 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2786 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2788 /* This is how to output a command to make the user-level label named NAME
2789 defined for reference from other files. */
2791 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2792 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2794 /* This is how to output a reference to a user-level label named NAME.
2795 `assemble_name' uses this. */
2797 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2798 fprintf (FILE, "_%s", NAME)
2800 /* This is how to output a definition of an internal numbered label where
2801 PREFIX is the class of label and NUM is the number within the class. */
2803 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2804 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2806 /* This is how to output a reference to an internal numbered label where
2807 PREFIX is the class of label and NUM is the number within the class. */
2808 /* FIXME: This should be used throughout gcc, and documented in the texinfo
2809 files. There is no reason you should have to allocate a buffer and
2810 `sprintf' to reference an internal label (as opposed to defining it). */
2812 #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \
2813 fprintf (FILE, "%s%d", PREFIX, NUM)
2815 /* This is how to store into the string LABEL
2816 the symbol_ref name of an internal numbered label where
2817 PREFIX is the class of label and NUM is the number within the class.
2818 This is suitable for output with `assemble_name'. */
2820 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2821 sprintf (LABEL, "*%s%d", PREFIX, NUM)
2823 /* This is how to output an assembler line defining a `double' constant. */
2825 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2828 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2829 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \
2830 ASM_LONG, t[0], ASM_LONG, t[1]); \
2833 /* This is how to output an assembler line defining a `float' constant. */
2835 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2838 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2839 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \
2842 /* This is how to output an assembler line defining a `long double'
2845 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2848 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
2849 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \
2850 ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \
2853 /* This is how to output an assembler line defining an `int' constant. */
2855 #define ASM_OUTPUT_INT(FILE,VALUE) \
2856 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
2857 output_addr_const (FILE, (VALUE)), \
2858 fprintf (FILE, "\n"))
2860 /* This is how to output an assembler line defining a DImode constant. */
2861 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2862 output_double_int (FILE, VALUE)
2864 /* Likewise for `char' and `short' constants. */
2866 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2867 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
2868 output_addr_const (FILE, (VALUE)), \
2869 fprintf (FILE, "\n"))
2871 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2872 ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
2873 output_addr_const (FILE, (VALUE)), \
2874 fprintf (FILE, "\n"))
2876 /* This is how to output an assembler line for a numeric constant byte. */
2878 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2879 fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
2881 /* This is how to output an element of a case-vector that is absolute. */
2883 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2886 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2887 if (Pmode == SImode) \
2888 fprintf (FILE, "\t.word\t"); \
2889 else if (TARGET_MEDLOW) \
2890 fprintf (FILE, "\t.word\t0\n\t.word\t"); \
2892 fprintf (FILE, "\t.xword\t"); \
2893 assemble_name (FILE, label); \
2894 fprintf (FILE, "\n"); \
2897 /* This is how to output an element of a case-vector that is relative.
2898 (SPARC uses such vectors only when generating PIC.) */
2900 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
2903 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2904 if (Pmode == SImode) \
2905 fprintf (FILE, "\t.word\t"); \
2906 else if (TARGET_MEDLOW) \
2907 fprintf (FILE, "\t.word\t0\n\t.word\t"); \
2909 fprintf (FILE, "\t.xword\t"); \
2910 assemble_name (FILE, label); \
2911 fprintf (FILE, "-1b\n"); \
2914 /* This is how to output an assembler line
2915 that says to advance the location counter
2916 to a multiple of 2**LOG bytes. */
2918 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2920 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2922 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2923 fprintf (FILE, "\t.skip %u\n", (SIZE))
2925 /* This says how to output an assembler line
2926 to define a global common symbol. */
2928 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2929 ( fputs ("\t.common ", (FILE)), \
2930 assemble_name ((FILE), (NAME)), \
2931 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
2933 /* This says how to output an assembler line to define a local common
2936 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2937 ( fputs ("\t.reserve ", (FILE)), \
2938 assemble_name ((FILE), (NAME)), \
2939 fprintf ((FILE), ",%u,\"bss\",%u\n", \
2940 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2942 /* Store in OUTPUT a string (made with alloca) containing
2943 an assembler-name for a local static variable named NAME.
2944 LABELNO is an integer which is different for each call. */
2946 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2947 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2948 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2950 #define IDENT_ASM_OP ".ident"
2952 /* Output #ident as a .ident. */
2954 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2955 fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
2957 /* Define the parentheses used to group arithmetic operations
2958 in assembler code. */
2960 #define ASM_OPEN_PAREN "("
2961 #define ASM_CLOSE_PAREN ")"
2963 /* Define results of standard character escape sequences. */
2964 #define TARGET_BELL 007
2965 #define TARGET_BS 010
2966 #define TARGET_TAB 011
2967 #define TARGET_NEWLINE 012
2968 #define TARGET_VT 013
2969 #define TARGET_FF 014
2970 #define TARGET_CR 015
2972 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2973 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(')
2975 /* Print operand X (an rtx) in assembler syntax to file FILE.
2976 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2977 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2979 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2981 /* Print a memory address as an operand to reference that memory location. */
2983 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2984 { register rtx base, index = 0; \
2986 register rtx addr = ADDR; \
2987 if (GET_CODE (addr) == REG) \
2988 fputs (reg_names[REGNO (addr)], FILE); \
2989 else if (GET_CODE (addr) == PLUS) \
2991 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2992 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2993 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2994 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2996 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2997 fputs (reg_names[REGNO (base)], FILE); \
2999 fprintf (FILE, "%+d", offset); \
3000 else if (GET_CODE (index) == REG) \
3001 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
3002 else if (GET_CODE (index) == SYMBOL_REF \
3003 || GET_CODE (index) == CONST) \
3004 fputc ('+', FILE), output_addr_const (FILE, index); \
3007 else if (GET_CODE (addr) == MINUS \
3008 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
3010 output_addr_const (FILE, XEXP (addr, 0)); \
3011 fputs ("-(", FILE); \
3012 output_addr_const (FILE, XEXP (addr, 1)); \
3013 fputs ("-.)", FILE); \
3015 else if (GET_CODE (addr) == LO_SUM) \
3017 output_operand (XEXP (addr, 0), 0); \
3018 fputs ("+%lo(", FILE); \
3019 output_address (XEXP (addr, 1)); \
3020 fputc (')', FILE); \
3022 else if (flag_pic && GET_CODE (addr) == CONST \
3023 && GET_CODE (XEXP (addr, 0)) == MINUS \
3024 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
3025 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
3026 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
3028 addr = XEXP (addr, 0); \
3029 output_addr_const (FILE, XEXP (addr, 0)); \
3030 /* Group the args of the second CONST in parenthesis. */ \
3031 fputs ("-(", FILE); \
3032 /* Skip past the second CONST--it does nothing for us. */\
3033 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
3034 /* Close the parenthesis. */ \
3035 fputc (')', FILE); \
3039 output_addr_const (FILE, addr); \
3043 /* Declare functions defined in sparc.c and used in templates. */
3045 extern char *singlemove_string ();
3046 extern char *output_move_double ();
3047 extern char *output_move_quad ();
3048 extern char *output_fp_move_double ();
3049 extern char *output_fp_move_quad ();
3050 extern char *output_block_move ();
3051 extern char *output_scc_insn ();
3052 extern char *output_cbranch ();
3053 extern char *output_v9branch ();
3054 extern char *output_return ();
3056 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
3058 extern int flag_pic;