1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
49 #include "target-def.h"
51 /* 1 if the caller has placed an "unimp" insn immediately after the call.
52 This is used in v8 code when calling a function that returns a structure.
53 v9 doesn't have this. Be careful to have this test be the same as that
56 #define SKIP_CALLERS_UNIMP_P \
57 (!TARGET_ARCH64 && current_function_returns_struct \
58 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
59 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
62 /* Global variables for machine-dependent things. */
64 /* Size of frame. Need to know this to emit return insns from leaf procedures.
65 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
66 reload pass. This is important as the value is later used in insn
67 scheduling (to see what can go in a delay slot).
68 APPARENT_FSIZE is the size of the stack less the register save area and less
69 the outgoing argument area. It is used when saving call preserved regs. */
70 static int apparent_fsize;
71 static int actual_fsize;
73 /* Number of live general or floating point registers needed to be
74 saved (as 4-byte quantities). */
75 static int num_gfregs;
77 /* Save the operands last given to a compare for use when we
78 generate a scc or bcc insn. */
79 rtx sparc_compare_op0, sparc_compare_op1;
81 /* Coordinate with the md file wrt special insns created by
82 sparc_nonflat_function_epilogue. */
83 bool sparc_emitting_epilogue;
85 /* Vector to say how input registers are mapped to output registers.
86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
87 eliminate it. You must use -fomit-frame-pointer to get that. */
88 char leaf_reg_remap[] =
89 { 0, 1, 2, 3, 4, 5, 6, 7,
90 -1, -1, -1, -1, -1, -1, 14, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1,
92 8, 9, 10, 11, 12, 13, -1, 15,
94 32, 33, 34, 35, 36, 37, 38, 39,
95 40, 41, 42, 43, 44, 45, 46, 47,
96 48, 49, 50, 51, 52, 53, 54, 55,
97 56, 57, 58, 59, 60, 61, 62, 63,
98 64, 65, 66, 67, 68, 69, 70, 71,
99 72, 73, 74, 75, 76, 77, 78, 79,
100 80, 81, 82, 83, 84, 85, 86, 87,
101 88, 89, 90, 91, 92, 93, 94, 95,
102 96, 97, 98, 99, 100};
104 /* Vector, indexed by hard register number, which contains 1
105 for a register that is allowable in a candidate for leaf
106 function treatment. */
107 char sparc_leaf_regs[] =
108 { 1, 1, 1, 1, 1, 1, 1, 1,
109 0, 0, 0, 0, 0, 0, 1, 0,
110 0, 0, 0, 0, 0, 0, 0, 0,
111 1, 1, 1, 1, 1, 1, 0, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
122 /* Name of where we pretend to think the frame pointer points.
123 Normally, this is "%fp", but if we are in a leaf procedure,
124 this is "%sp+something". We record "something" separately as it may be
125 too big for reg+constant addressing. */
127 static const char *frame_base_name;
128 static int frame_base_offset;
130 static void sparc_init_modes PARAMS ((void));
131 static int save_regs PARAMS ((FILE *, int, int, const char *,
133 static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int));
134 static void build_big_number PARAMS ((FILE *, int, const char *));
135 static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *,
136 enum machine_mode, tree, int, int,
139 static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
140 static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
142 static void sparc_output_addr_vec PARAMS ((rtx));
143 static void sparc_output_addr_diff_vec PARAMS ((rtx));
144 static void sparc_output_deferred_case_vectors PARAMS ((void));
145 static int check_return_regs PARAMS ((rtx));
146 static int epilogue_renumber PARAMS ((rtx *, int));
147 static bool sparc_assemble_integer PARAMS ((rtx, unsigned int, int));
148 static int set_extends PARAMS ((rtx));
149 static void output_restore_regs PARAMS ((FILE *, int));
150 static void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
151 static void sparc_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
152 static void sparc_flat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
153 static void sparc_flat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
154 static void sparc_nonflat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT,
156 static void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT,
158 #ifdef OBJECT_FORMAT_ELF
159 static void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int));
161 static void sparc_aout_select_section PARAMS ((tree, int,
162 unsigned HOST_WIDE_INT))
164 static void sparc_aout_select_rtx_section PARAMS ((enum machine_mode, rtx,
165 unsigned HOST_WIDE_INT))
168 static int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
169 static int sparc_issue_rate PARAMS ((void));
170 static void sparc_sched_init PARAMS ((FILE *, int, int));
171 static int sparc_use_dfa_pipeline_interface PARAMS ((void));
172 static int sparc_use_sched_lookahead PARAMS ((void));
174 static void emit_soft_tfmode_libcall PARAMS ((const char *, int, rtx *));
175 static void emit_soft_tfmode_binop PARAMS ((enum rtx_code, rtx *));
176 static void emit_soft_tfmode_unop PARAMS ((enum rtx_code, rtx *));
177 static void emit_soft_tfmode_cvt PARAMS ((enum rtx_code, rtx *));
178 static void emit_hard_tfmode_operation PARAMS ((enum rtx_code, rtx *));
180 static void sparc_encode_section_info PARAMS ((tree, int));
181 static bool sparc_function_ok_for_sibcall PARAMS ((tree, tree));
182 static void sparc_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
183 HOST_WIDE_INT, tree));
184 static bool sparc_rtx_costs PARAMS ((rtx, int, int, int *));
186 /* Option handling. */
188 /* Code model option as passed by user. */
189 const char *sparc_cmodel_string;
191 enum cmodel sparc_cmodel;
193 char sparc_hard_reg_printed[8];
195 struct sparc_cpu_select sparc_select[] =
197 /* switch name, tune arch */
198 { (char *)0, "default", 1, 1 },
199 { (char *)0, "-mcpu=", 1, 1 },
200 { (char *)0, "-mtune=", 1, 0 },
204 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
205 enum processor_type sparc_cpu;
207 /* Initialize the GCC target structure. */
209 /* The sparc default is to use .half rather than .short for aligned
210 HI objects. Use .word instead of .long on non-ELF systems. */
211 #undef TARGET_ASM_ALIGNED_HI_OP
212 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
213 #ifndef OBJECT_FORMAT_ELF
214 #undef TARGET_ASM_ALIGNED_SI_OP
215 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
218 #undef TARGET_ASM_UNALIGNED_HI_OP
219 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
220 #undef TARGET_ASM_UNALIGNED_SI_OP
221 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
222 #undef TARGET_ASM_UNALIGNED_DI_OP
223 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
225 /* The target hook has to handle DI-mode values. */
226 #undef TARGET_ASM_INTEGER
227 #define TARGET_ASM_INTEGER sparc_assemble_integer
229 #undef TARGET_ASM_FUNCTION_PROLOGUE
230 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
231 #undef TARGET_ASM_FUNCTION_EPILOGUE
232 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
234 #undef TARGET_SCHED_ADJUST_COST
235 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
236 #undef TARGET_SCHED_ISSUE_RATE
237 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
238 #undef TARGET_SCHED_INIT
239 #define TARGET_SCHED_INIT sparc_sched_init
240 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
241 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
242 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
243 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
245 #undef TARGET_ENCODE_SECTION_INFO
246 #define TARGET_ENCODE_SECTION_INFO sparc_encode_section_info
248 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
249 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
251 #undef TARGET_ASM_OUTPUT_MI_THUNK
252 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
253 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
254 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
256 #undef TARGET_RTX_COSTS
257 #define TARGET_RTX_COSTS sparc_rtx_costs
259 struct gcc_target targetm = TARGET_INITIALIZER;
261 /* Validate and override various options, and do some machine dependent
265 sparc_override_options ()
267 static struct code_model {
268 const char *const name;
270 } const cmodels[] = {
272 { "medlow", CM_MEDLOW },
273 { "medmid", CM_MEDMID },
274 { "medany", CM_MEDANY },
275 { "embmedany", CM_EMBMEDANY },
278 const struct code_model *cmodel;
279 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
280 static struct cpu_default {
282 const char *const name;
283 } const cpu_default[] = {
284 /* There must be one entry here for each TARGET_CPU value. */
285 { TARGET_CPU_sparc, "cypress" },
286 { TARGET_CPU_sparclet, "tsc701" },
287 { TARGET_CPU_sparclite, "f930" },
288 { TARGET_CPU_v8, "v8" },
289 { TARGET_CPU_hypersparc, "hypersparc" },
290 { TARGET_CPU_sparclite86x, "sparclite86x" },
291 { TARGET_CPU_supersparc, "supersparc" },
292 { TARGET_CPU_v9, "v9" },
293 { TARGET_CPU_ultrasparc, "ultrasparc" },
294 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
297 const struct cpu_default *def;
298 /* Table of values for -m{cpu,tune}=. */
299 static struct cpu_table {
300 const char *const name;
301 const enum processor_type processor;
304 } const cpu_table[] = {
305 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
306 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
307 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
308 /* TI TMS390Z55 supersparc */
309 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
310 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
311 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
312 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
313 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
314 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
315 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
316 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
318 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
320 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
321 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
322 /* TI ultrasparc I, II, IIi */
323 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
324 /* Although insns using %y are deprecated, it is a clear win on current
326 |MASK_DEPRECATED_V8_INSNS},
327 /* TI ultrasparc III */
328 /* ??? Check if %y issue still holds true in ultra3. */
329 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
332 const struct cpu_table *cpu;
333 const struct sparc_cpu_select *sel;
336 #ifndef SPARC_BI_ARCH
337 /* Check for unsupported architecture size. */
338 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
339 error ("%s is not supported by this configuration",
340 DEFAULT_ARCH32_P ? "-m64" : "-m32");
343 /* We force all 64bit archs to use 128 bit long double */
344 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
346 error ("-mlong-double-64 not allowed with -m64");
347 target_flags |= MASK_LONG_DOUBLE_128;
350 /* Code model selection. */
351 sparc_cmodel = SPARC_DEFAULT_CMODEL;
355 sparc_cmodel = CM_32;
358 if (sparc_cmodel_string != NULL)
362 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
363 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
365 if (cmodel->name == NULL)
366 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
368 sparc_cmodel = cmodel->value;
371 error ("-mcmodel= is not supported on 32 bit systems");
374 fpu = TARGET_FPU; /* save current -mfpu status */
376 /* Set the default CPU. */
377 for (def = &cpu_default[0]; def->name; ++def)
378 if (def->cpu == TARGET_CPU_DEFAULT)
382 sparc_select[0].string = def->name;
384 for (sel = &sparc_select[0]; sel->name; ++sel)
388 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
389 if (! strcmp (sel->string, cpu->name))
392 sparc_cpu = cpu->processor;
396 target_flags &= ~cpu->disable;
397 target_flags |= cpu->enable;
403 error ("bad value (%s) for %s switch", sel->string, sel->name);
407 /* If -mfpu or -mno-fpu was explicitly used, don't override with
408 the processor default. Clear MASK_FPU_SET to avoid confusing
409 the reverse mapping from switch values to names. */
412 target_flags = (target_flags & ~MASK_FPU) | fpu;
413 target_flags &= ~MASK_FPU_SET;
416 /* Don't allow -mvis if FPU is disabled. */
418 target_flags &= ~MASK_VIS;
420 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
422 -m64 also implies v9. */
423 if (TARGET_VIS || TARGET_ARCH64)
425 target_flags |= MASK_V9;
426 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
429 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
430 if (TARGET_V9 && TARGET_ARCH32)
431 target_flags |= MASK_DEPRECATED_V8_INSNS;
433 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
434 if (! TARGET_V9 || TARGET_ARCH64)
435 target_flags &= ~MASK_V8PLUS;
437 /* Don't use stack biasing in 32 bit mode. */
439 target_flags &= ~MASK_STACK_BIAS;
441 /* Supply a default value for align_functions. */
442 if (align_functions == 0
443 && (sparc_cpu == PROCESSOR_ULTRASPARC
444 || sparc_cpu == PROCESSOR_ULTRASPARC3))
445 align_functions = 32;
447 /* Validate PCC_STRUCT_RETURN. */
448 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
449 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
451 /* Only use .uaxword when compiling for a 64-bit target. */
453 targetm.asm_out.unaligned_op.di = NULL;
455 /* Do various machine dependent initializations. */
459 /* Miscellaneous utilities. */
461 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
462 or branch on register contents instructions. */
468 return (code == EQ || code == NE || code == GE || code == LT
469 || code == LE || code == GT);
473 /* Operand constraints. */
475 /* Return nonzero only if OP is a register of mode MODE,
479 reg_or_0_operand (op, mode)
481 enum machine_mode mode;
483 if (register_operand (op, mode))
485 if (op == const0_rtx)
487 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
488 && CONST_DOUBLE_HIGH (op) == 0
489 && CONST_DOUBLE_LOW (op) == 0)
491 if (fp_zero_operand (op, mode))
496 /* Return nonzero only if OP is const1_rtx. */
499 const1_operand (op, mode)
501 enum machine_mode mode ATTRIBUTE_UNUSED;
503 return op == const1_rtx;
506 /* Nonzero if OP is a floating point value with value 0.0. */
509 fp_zero_operand (op, mode)
511 enum machine_mode mode;
513 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
515 return op == CONST0_RTX (mode);
518 /* Nonzero if OP is a register operand in floating point register. */
521 fp_register_operand (op, mode)
523 enum machine_mode mode;
525 if (! register_operand (op, mode))
527 if (GET_CODE (op) == SUBREG)
528 op = SUBREG_REG (op);
529 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
532 /* Nonzero if OP is a floating point constant which can
533 be loaded into an integer register using a single
534 sethi instruction. */
540 if (GET_CODE (op) == CONST_DOUBLE)
545 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
546 if (REAL_VALUES_EQUAL (r, dconst0) &&
547 ! REAL_VALUE_MINUS_ZERO (r))
549 REAL_VALUE_TO_TARGET_SINGLE (r, i);
550 if (SPARC_SETHI_P (i))
557 /* Nonzero if OP is a floating point constant which can
558 be loaded into an integer register using a single
565 if (GET_CODE (op) == CONST_DOUBLE)
570 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
571 if (REAL_VALUES_EQUAL (r, dconst0) &&
572 ! REAL_VALUE_MINUS_ZERO (r))
574 REAL_VALUE_TO_TARGET_SINGLE (r, i);
575 if (SPARC_SIMM13_P (i))
582 /* Nonzero if OP is a floating point constant which can
583 be loaded into an integer register using a high/losum
584 instruction sequence. */
590 /* The constraints calling this should only be in
591 SFmode move insns, so any constant which cannot
592 be moved using a single insn will do. */
593 if (GET_CODE (op) == CONST_DOUBLE)
598 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
599 if (REAL_VALUES_EQUAL (r, dconst0) &&
600 ! REAL_VALUE_MINUS_ZERO (r))
602 REAL_VALUE_TO_TARGET_SINGLE (r, i);
603 if (! SPARC_SETHI_P (i)
604 && ! SPARC_SIMM13_P (i))
611 /* Nonzero if OP is an integer register. */
614 intreg_operand (op, mode)
616 enum machine_mode mode ATTRIBUTE_UNUSED;
618 return (register_operand (op, SImode)
619 || (TARGET_ARCH64 && register_operand (op, DImode)));
622 /* Nonzero if OP is a floating point condition code register. */
625 fcc_reg_operand (op, mode)
627 enum machine_mode mode;
629 /* This can happen when recog is called from combine. Op may be a MEM.
630 Fail instead of calling abort in this case. */
631 if (GET_CODE (op) != REG)
634 if (mode != VOIDmode && mode != GET_MODE (op))
637 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
640 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
641 if (reg_renumber == 0)
642 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
643 return REGNO_OK_FOR_CCFP_P (REGNO (op));
645 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
649 /* Nonzero if OP is a floating point condition code fcc0 register. */
652 fcc0_reg_operand (op, mode)
654 enum machine_mode mode;
656 /* This can happen when recog is called from combine. Op may be a MEM.
657 Fail instead of calling abort in this case. */
658 if (GET_CODE (op) != REG)
661 if (mode != VOIDmode && mode != GET_MODE (op))
664 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
667 return REGNO (op) == SPARC_FCC_REG;
670 /* Nonzero if OP is an integer or floating point condition code register. */
673 icc_or_fcc_reg_operand (op, mode)
675 enum machine_mode mode;
677 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
679 if (mode != VOIDmode && mode != GET_MODE (op))
682 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
687 return fcc_reg_operand (op, mode);
690 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
692 restore_operand (op, mode)
694 enum machine_mode mode;
696 return (GET_CODE (op) == REG && GET_MODE (op) == mode
697 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
700 /* Call insn on SPARC can take a PC-relative constant address, or any regular
704 call_operand (op, mode)
706 enum machine_mode mode;
708 if (GET_CODE (op) != MEM)
711 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
715 call_operand_address (op, mode)
717 enum machine_mode mode;
719 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
722 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
723 reference and a constant. */
726 symbolic_operand (op, mode)
728 enum machine_mode mode;
730 enum machine_mode omode = GET_MODE (op);
732 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
735 switch (GET_CODE (op))
743 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
744 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
745 && GET_CODE (XEXP (op, 1)) == CONST_INT);
752 /* Return truth value of statement that OP is a symbolic memory
753 operand of mode MODE. */
756 symbolic_memory_operand (op, mode)
758 enum machine_mode mode ATTRIBUTE_UNUSED;
760 if (GET_CODE (op) == SUBREG)
761 op = SUBREG_REG (op);
762 if (GET_CODE (op) != MEM)
765 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
766 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
769 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
772 label_ref_operand (op, mode)
774 enum machine_mode mode;
776 if (GET_CODE (op) != LABEL_REF)
778 if (GET_MODE (op) != mode)
783 /* Return 1 if the operand is an argument used in generating pic references
784 in either the medium/low or medium/anywhere code models of sparc64. */
787 sp64_medium_pic_operand (op, mode)
789 enum machine_mode mode ATTRIBUTE_UNUSED;
791 /* Check for (const (minus (symbol_ref:GOT)
792 (const (minus (label) (pc))))). */
793 if (GET_CODE (op) != CONST)
796 if (GET_CODE (op) != MINUS)
798 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
800 /* ??? Ensure symbol is GOT. */
801 if (GET_CODE (XEXP (op, 1)) != CONST)
803 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
808 /* Return 1 if the operand is a data segment reference. This includes
809 the readonly data segment, or in other words anything but the text segment.
810 This is needed in the medium/anywhere code model on v9. These values
811 are accessed with EMBMEDANY_BASE_REG. */
814 data_segment_operand (op, mode)
816 enum machine_mode mode ATTRIBUTE_UNUSED;
818 switch (GET_CODE (op))
821 return ! SYMBOL_REF_FLAG (op);
823 /* Assume canonical format of symbol + constant.
826 return data_segment_operand (XEXP (op, 0), VOIDmode);
832 /* Return 1 if the operand is a text segment reference.
833 This is needed in the medium/anywhere code model on v9. */
836 text_segment_operand (op, mode)
838 enum machine_mode mode ATTRIBUTE_UNUSED;
840 switch (GET_CODE (op))
845 return SYMBOL_REF_FLAG (op);
847 /* Assume canonical format of symbol + constant.
850 return text_segment_operand (XEXP (op, 0), VOIDmode);
856 /* Return 1 if the operand is either a register or a memory operand that is
860 reg_or_nonsymb_mem_operand (op, mode)
862 enum machine_mode mode;
864 if (register_operand (op, mode))
867 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
874 splittable_symbolic_memory_operand (op, mode)
876 enum machine_mode mode ATTRIBUTE_UNUSED;
878 if (GET_CODE (op) != MEM)
880 if (! symbolic_operand (XEXP (op, 0), Pmode))
886 splittable_immediate_memory_operand (op, mode)
888 enum machine_mode mode ATTRIBUTE_UNUSED;
890 if (GET_CODE (op) != MEM)
892 if (! immediate_operand (XEXP (op, 0), Pmode))
897 /* Return truth value of whether OP is EQ or NE. */
902 enum machine_mode mode ATTRIBUTE_UNUSED;
904 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
907 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
908 or LTU for non-floating-point. We handle those specially. */
911 normal_comp_operator (op, mode)
913 enum machine_mode mode ATTRIBUTE_UNUSED;
915 enum rtx_code code = GET_CODE (op);
917 if (GET_RTX_CLASS (code) != '<')
920 if (GET_MODE (XEXP (op, 0)) == CCFPmode
921 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
924 return (code != NE && code != EQ && code != GEU && code != LTU);
927 /* Return 1 if this is a comparison operator. This allows the use of
928 MATCH_OPERATOR to recognize all the branch insns. */
931 noov_compare_op (op, mode)
933 enum machine_mode mode ATTRIBUTE_UNUSED;
935 enum rtx_code code = GET_CODE (op);
937 if (GET_RTX_CLASS (code) != '<')
940 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
941 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
942 /* These are the only branches which work with CC_NOOVmode. */
943 return (code == EQ || code == NE || code == GE || code == LT);
947 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
948 MATCH_OPERATOR to recognize all the branch insns. */
951 noov_compare64_op (op, mode)
953 enum machine_mode mode ATTRIBUTE_UNUSED;
955 enum rtx_code code = GET_CODE (op);
960 if (GET_RTX_CLASS (code) != '<')
963 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
964 /* These are the only branches which work with CCX_NOOVmode. */
965 return (code == EQ || code == NE || code == GE || code == LT);
966 return (GET_MODE (XEXP (op, 0)) == CCXmode);
969 /* Nonzero if OP is a comparison operator suitable for use in v9
970 conditional move or branch on register contents instructions. */
973 v9_regcmp_op (op, mode)
975 enum machine_mode mode ATTRIBUTE_UNUSED;
977 enum rtx_code code = GET_CODE (op);
979 if (GET_RTX_CLASS (code) != '<')
982 return v9_regcmp_p (code);
985 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
990 enum machine_mode mode ATTRIBUTE_UNUSED;
992 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
995 /* Return nonzero if OP is an operator of mode MODE which can set
996 the condition codes explicitly. We do not include PLUS and MINUS
997 because these require CC_NOOVmode, which we handle explicitly. */
1000 cc_arithop (op, mode)
1002 enum machine_mode mode ATTRIBUTE_UNUSED;
1004 if (GET_CODE (op) == AND
1005 || GET_CODE (op) == IOR
1006 || GET_CODE (op) == XOR)
1012 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1013 complement its second operand and set the condition codes explicitly. */
1016 cc_arithopn (op, mode)
1018 enum machine_mode mode ATTRIBUTE_UNUSED;
1020 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1021 and (xor ... (not ...)) to (not (xor ...)). */
1022 return (GET_CODE (op) == AND
1023 || GET_CODE (op) == IOR);
1026 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1027 signed 13 bit immediate field. This is an acceptable SImode operand for
1028 most 3 address instructions. */
1031 arith_operand (op, mode)
1033 enum machine_mode mode;
1035 if (register_operand (op, mode))
1037 if (GET_CODE (op) != CONST_INT)
1039 return SMALL_INT32 (op);
1042 /* Return true if OP is a constant 4096 */
1045 arith_4096_operand (op, mode)
1047 enum machine_mode mode ATTRIBUTE_UNUSED;
1049 if (GET_CODE (op) != CONST_INT)
1052 return INTVAL (op) == 4096;
1055 /* Return true if OP is suitable as second operand for add/sub */
1058 arith_add_operand (op, mode)
1060 enum machine_mode mode;
1062 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1065 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1066 immediate field of OR and XOR instructions. Used for 64-bit
1067 constant formation patterns. */
1069 const64_operand (op, mode)
1071 enum machine_mode mode ATTRIBUTE_UNUSED;
1073 return ((GET_CODE (op) == CONST_INT
1074 && SPARC_SIMM13_P (INTVAL (op)))
1075 #if HOST_BITS_PER_WIDE_INT != 64
1076 || (GET_CODE (op) == CONST_DOUBLE
1077 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1078 && (CONST_DOUBLE_HIGH (op) ==
1079 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1080 (HOST_WIDE_INT)-1 : 0)))
1085 /* The same, but only for sethi instructions. */
1087 const64_high_operand (op, mode)
1089 enum machine_mode mode;
1091 return ((GET_CODE (op) == CONST_INT
1092 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1093 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1095 || (GET_CODE (op) == CONST_DOUBLE
1096 && CONST_DOUBLE_HIGH (op) == 0
1097 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1098 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1101 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1102 signed 11 bit immediate field. This is an acceptable SImode operand for
1103 the movcc instructions. */
1106 arith11_operand (op, mode)
1108 enum machine_mode mode;
1110 return (register_operand (op, mode)
1111 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1114 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1115 signed 10 bit immediate field. This is an acceptable SImode operand for
1116 the movrcc instructions. */
1119 arith10_operand (op, mode)
1121 enum machine_mode mode;
1123 return (register_operand (op, mode)
1124 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1127 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1128 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1130 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1131 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1132 for most 3 address instructions. */
1135 arith_double_operand (op, mode)
1137 enum machine_mode mode;
1139 return (register_operand (op, mode)
1140 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1142 && GET_CODE (op) == CONST_DOUBLE
1143 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1144 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1146 && GET_CODE (op) == CONST_DOUBLE
1147 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1148 && ((CONST_DOUBLE_HIGH (op) == -1
1149 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1150 || (CONST_DOUBLE_HIGH (op) == 0
1151 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1154 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1157 arith_double_4096_operand (op, mode)
1159 enum machine_mode mode ATTRIBUTE_UNUSED;
1161 return (TARGET_ARCH64 &&
1162 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1163 (GET_CODE (op) == CONST_DOUBLE &&
1164 CONST_DOUBLE_LOW (op) == 4096 &&
1165 CONST_DOUBLE_HIGH (op) == 0)));
1168 /* Return true if OP is suitable as second operand for add/sub in DImode */
1171 arith_double_add_operand (op, mode)
1173 enum machine_mode mode;
1175 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1178 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1179 can fit in an 11 bit immediate field. This is an acceptable DImode
1180 operand for the movcc instructions. */
1181 /* ??? Replace with arith11_operand? */
1184 arith11_double_operand (op, mode)
1186 enum machine_mode mode;
1188 return (register_operand (op, mode)
1189 || (GET_CODE (op) == CONST_DOUBLE
1190 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1191 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1192 && ((CONST_DOUBLE_HIGH (op) == -1
1193 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1194 || (CONST_DOUBLE_HIGH (op) == 0
1195 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1196 || (GET_CODE (op) == CONST_INT
1197 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1198 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1201 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1202 can fit in an 10 bit immediate field. This is an acceptable DImode
1203 operand for the movrcc instructions. */
1204 /* ??? Replace with arith10_operand? */
1207 arith10_double_operand (op, mode)
1209 enum machine_mode mode;
1211 return (register_operand (op, mode)
1212 || (GET_CODE (op) == CONST_DOUBLE
1213 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1214 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1215 && ((CONST_DOUBLE_HIGH (op) == -1
1216 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1217 || (CONST_DOUBLE_HIGH (op) == 0
1218 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1219 || (GET_CODE (op) == CONST_INT
1220 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1221 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1224 /* Return truth value of whether OP is an integer which fits the
1225 range constraining immediate operands in most three-address insns,
1226 which have a 13 bit immediate field. */
1229 small_int (op, mode)
1231 enum machine_mode mode ATTRIBUTE_UNUSED;
1233 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1237 small_int_or_double (op, mode)
1239 enum machine_mode mode ATTRIBUTE_UNUSED;
1241 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1242 || (GET_CODE (op) == CONST_DOUBLE
1243 && CONST_DOUBLE_HIGH (op) == 0
1244 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1247 /* Recognize operand values for the umul instruction. That instruction sign
1248 extends immediate values just like all other sparc instructions, but
1249 interprets the extended result as an unsigned number. */
1252 uns_small_int (op, mode)
1254 enum machine_mode mode ATTRIBUTE_UNUSED;
1256 #if HOST_BITS_PER_WIDE_INT > 32
1257 /* All allowed constants will fit a CONST_INT. */
1258 return (GET_CODE (op) == CONST_INT
1259 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1260 || (INTVAL (op) >= 0xFFFFF000
1261 && INTVAL (op) <= 0xFFFFFFFF)));
1263 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1264 || (GET_CODE (op) == CONST_DOUBLE
1265 && CONST_DOUBLE_HIGH (op) == 0
1266 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1271 uns_arith_operand (op, mode)
1273 enum machine_mode mode;
1275 return register_operand (op, mode) || uns_small_int (op, mode);
1278 /* Return truth value of statement that OP is a call-clobbered register. */
1280 clobbered_register (op, mode)
1282 enum machine_mode mode ATTRIBUTE_UNUSED;
1284 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1287 /* Return 1 if OP is a valid operand for the source of a move insn. */
1290 input_operand (op, mode)
1292 enum machine_mode mode;
1294 /* If both modes are non-void they must be the same. */
1295 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1298 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1299 if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX)
1302 /* Allow any one instruction integer constant, and all CONST_INT
1303 variants when we are working in DImode and !arch64. */
1304 if (GET_MODE_CLASS (mode) == MODE_INT
1305 && ((GET_CODE (op) == CONST_INT
1306 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1307 || SPARC_SIMM13_P (INTVAL (op))
1309 && ! TARGET_ARCH64)))
1311 && GET_CODE (op) == CONST_DOUBLE
1312 && ((CONST_DOUBLE_HIGH (op) == 0
1313 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1315 #if HOST_BITS_PER_WIDE_INT == 64
1316 (CONST_DOUBLE_HIGH (op) == 0
1317 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1319 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1320 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1321 && CONST_DOUBLE_HIGH (op) == 0)
1322 || (CONST_DOUBLE_HIGH (op) == -1
1323 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1328 /* If !arch64 and this is a DImode const, allow it so that
1329 the splits can be generated. */
1332 && GET_CODE (op) == CONST_DOUBLE)
1335 if (register_operand (op, mode))
1338 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1339 && GET_CODE (op) == CONST_DOUBLE)
1342 /* If this is a SUBREG, look inside so that we handle
1343 paradoxical ones. */
1344 if (GET_CODE (op) == SUBREG)
1345 op = SUBREG_REG (op);
1347 /* Check for valid MEM forms. */
1348 if (GET_CODE (op) == MEM)
1350 rtx inside = XEXP (op, 0);
1352 if (GET_CODE (inside) == LO_SUM)
1354 /* We can't allow these because all of the splits
1355 (eventually as they trickle down into DFmode
1356 splits) require offsettable memory references. */
1358 && GET_MODE (op) == TFmode)
1361 return (register_operand (XEXP (inside, 0), Pmode)
1362 && CONSTANT_P (XEXP (inside, 1)));
1364 return memory_address_p (mode, inside);
1371 /* We know it can't be done in one insn when we get here,
1372 the movsi expander guarentees this. */
1374 sparc_emit_set_const32 (op0, op1)
1378 enum machine_mode mode = GET_MODE (op0);
1381 if (GET_CODE (op1) == CONST_INT)
1383 HOST_WIDE_INT value = INTVAL (op1);
1385 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1386 || SPARC_SIMM13_P (value))
1390 /* Full 2-insn decomposition is needed. */
1391 if (reload_in_progress || reload_completed)
1394 temp = gen_reg_rtx (mode);
1396 if (GET_CODE (op1) == CONST_INT)
1398 /* Emit them as real moves instead of a HIGH/LO_SUM,
1399 this way CSE can see everything and reuse intermediate
1400 values if it wants. */
1402 && HOST_BITS_PER_WIDE_INT != 64
1403 && (INTVAL (op1) & 0x80000000) != 0)
1404 emit_insn (gen_rtx_SET
1406 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1409 emit_insn (gen_rtx_SET (VOIDmode, temp,
1410 GEN_INT (INTVAL (op1)
1411 & ~(HOST_WIDE_INT)0x3ff)));
1413 emit_insn (gen_rtx_SET (VOIDmode,
1415 gen_rtx_IOR (mode, temp,
1416 GEN_INT (INTVAL (op1) & 0x3ff))));
1420 /* A symbol, emit in the traditional way. */
1421 emit_insn (gen_rtx_SET (VOIDmode, temp,
1422 gen_rtx_HIGH (mode, op1)));
1423 emit_insn (gen_rtx_SET (VOIDmode,
1424 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1430 /* SPARC-v9 code-model support. */
1432 sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1439 if (temp1 && GET_MODE (temp1) == TImode)
1442 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1445 switch (sparc_cmodel)
1448 /* The range spanned by all instructions in the object is less
1449 than 2^31 bytes (2GB) and the distance from any instruction
1450 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1451 than 2^31 bytes (2GB).
1453 The executable must be in the low 4TB of the virtual address
1456 sethi %hi(symbol), %temp
1457 or %temp, %lo(symbol), %reg */
1458 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1459 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1463 /* The range spanned by all instructions in the object is less
1464 than 2^31 bytes (2GB) and the distance from any instruction
1465 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1466 than 2^31 bytes (2GB).
1468 The executable must be in the low 16TB of the virtual address
1471 sethi %h44(symbol), %temp1
1472 or %temp1, %m44(symbol), %temp2
1473 sllx %temp2, 12, %temp3
1474 or %temp3, %l44(symbol), %reg */
1475 emit_insn (gen_seth44 (op0, op1));
1476 emit_insn (gen_setm44 (op0, op0, op1));
1477 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1478 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1479 emit_insn (gen_setl44 (op0, temp1, op1));
1483 /* The range spanned by all instructions in the object is less
1484 than 2^31 bytes (2GB) and the distance from any instruction
1485 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1486 than 2^31 bytes (2GB).
1488 The executable can be placed anywhere in the virtual address
1491 sethi %hh(symbol), %temp1
1492 sethi %lm(symbol), %temp2
1493 or %temp1, %hm(symbol), %temp3
1494 or %temp2, %lo(symbol), %temp4
1495 sllx %temp3, 32, %temp5
1496 or %temp4, %temp5, %reg */
1498 /* It is possible that one of the registers we got for operands[2]
1499 might coincide with that of operands[0] (which is why we made
1500 it TImode). Pick the other one to use as our scratch. */
1501 if (rtx_equal_p (temp1, op0))
1504 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1509 emit_insn (gen_sethh (op0, op1));
1510 emit_insn (gen_setlm (temp1, op1));
1511 emit_insn (gen_sethm (op0, op0, op1));
1512 emit_insn (gen_rtx_SET (VOIDmode, op0,
1513 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1514 emit_insn (gen_rtx_SET (VOIDmode, op0,
1515 gen_rtx_PLUS (DImode, op0, temp1)));
1516 emit_insn (gen_setlo (op0, op0, op1));
1520 /* Old old old backwards compatibility kruft here.
1521 Essentially it is MEDLOW with a fixed 64-bit
1522 virtual base added to all data segment addresses.
1523 Text-segment stuff is computed like MEDANY, we can't
1524 reuse the code above because the relocation knobs
1527 Data segment: sethi %hi(symbol), %temp1
1528 or %temp1, %lo(symbol), %temp2
1529 add %temp2, EMBMEDANY_BASE_REG, %reg
1531 Text segment: sethi %uhi(symbol), %temp1
1532 sethi %hi(symbol), %temp2
1533 or %temp1, %ulo(symbol), %temp3
1534 or %temp2, %lo(symbol), %temp4
1535 sllx %temp3, 32, %temp5
1536 or %temp4, %temp5, %reg */
1537 if (data_segment_operand (op1, GET_MODE (op1)))
1539 emit_insn (gen_embmedany_sethi (temp1, op1));
1540 emit_insn (gen_embmedany_brsum (op0, temp1));
1541 emit_insn (gen_embmedany_losum (op0, op0, op1));
1545 /* It is possible that one of the registers we got for operands[2]
1546 might coincide with that of operands[0] (which is why we made
1547 it TImode). Pick the other one to use as our scratch. */
1548 if (rtx_equal_p (temp1, op0))
1551 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1556 emit_insn (gen_embmedany_textuhi (op0, op1));
1557 emit_insn (gen_embmedany_texthi (temp1, op1));
1558 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1559 emit_insn (gen_rtx_SET (VOIDmode, op0,
1560 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1561 emit_insn (gen_rtx_SET (VOIDmode, op0,
1562 gen_rtx_PLUS (DImode, op0, temp1)));
1563 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1572 /* These avoid problems when cross compiling. If we do not
1573 go through all this hair then the optimizer will see
1574 invalid REG_EQUAL notes or in some cases none at all. */
1575 static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT));
1576 static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT));
1577 static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT));
1578 static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
1580 #if HOST_BITS_PER_WIDE_INT == 64
1581 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1582 #define GEN_INT64(__x) GEN_INT (__x)
1584 #define GEN_HIGHINT64(__x) \
1585 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1586 #define GEN_INT64(__x) \
1587 immed_double_const ((__x) & 0xffffffff, \
1588 ((__x) & 0x80000000 ? -1 : 0), DImode)
1591 /* The optimizer is not to assume anything about exactly
1592 which bits are set for a HIGH, they are unspecified.
1593 Unfortunately this leads to many missed optimizations
1594 during CSE. We mask out the non-HIGH bits, and matches
1595 a plain movdi, to alleviate this problem. */
1597 sparc_emit_set_safe_HIGH64 (dest, val)
1601 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1605 gen_safe_SET64 (dest, val)
1609 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1613 gen_safe_OR64 (src, val)
1617 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1621 gen_safe_XOR64 (src, val)
1625 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1628 /* Worker routines for 64-bit constant formation on arch64.
1629 One of the key things to be doing in these emissions is
1630 to create as many temp REGs as possible. This makes it
1631 possible for half-built constants to be used later when
1632 such values are similar to something required later on.
1633 Without doing this, the optimizer cannot see such
1636 static void sparc_emit_set_const64_quick1
1637 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int));
1640 sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1643 unsigned HOST_WIDE_INT low_bits;
1646 unsigned HOST_WIDE_INT high_bits;
1649 high_bits = (~low_bits) & 0xffffffff;
1651 high_bits = low_bits;
1653 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1656 emit_insn (gen_rtx_SET (VOIDmode, op0,
1657 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1661 /* If we are XOR'ing with -1, then we should emit a one's complement
1662 instead. This way the combiner will notice logical operations
1663 such as ANDN later on and substitute. */
1664 if ((low_bits & 0x3ff) == 0x3ff)
1666 emit_insn (gen_rtx_SET (VOIDmode, op0,
1667 gen_rtx_NOT (DImode, temp)));
1671 emit_insn (gen_rtx_SET (VOIDmode, op0,
1672 gen_safe_XOR64 (temp,
1673 (-(HOST_WIDE_INT)0x400
1674 | (low_bits & 0x3ff)))));
1679 static void sparc_emit_set_const64_quick2
1680 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT,
1681 unsigned HOST_WIDE_INT, int));
1684 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1687 unsigned HOST_WIDE_INT high_bits;
1688 unsigned HOST_WIDE_INT low_immediate;
1693 if ((high_bits & 0xfffffc00) != 0)
1695 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1696 if ((high_bits & ~0xfffffc00) != 0)
1697 emit_insn (gen_rtx_SET (VOIDmode, op0,
1698 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1704 emit_insn (gen_safe_SET64 (temp, high_bits));
1708 /* Now shift it up into place. */
1709 emit_insn (gen_rtx_SET (VOIDmode, op0,
1710 gen_rtx_ASHIFT (DImode, temp2,
1711 GEN_INT (shift_count))));
1713 /* If there is a low immediate part piece, finish up by
1714 putting that in as well. */
1715 if (low_immediate != 0)
1716 emit_insn (gen_rtx_SET (VOIDmode, op0,
1717 gen_safe_OR64 (op0, low_immediate)));
1720 static void sparc_emit_set_const64_longway
1721 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1723 /* Full 64-bit constant decomposition. Even though this is the
1724 'worst' case, we still optimize a few things away. */
1726 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1729 unsigned HOST_WIDE_INT high_bits;
1730 unsigned HOST_WIDE_INT low_bits;
1734 if (reload_in_progress || reload_completed)
1737 sub_temp = gen_reg_rtx (DImode);
1739 if ((high_bits & 0xfffffc00) != 0)
1741 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1742 if ((high_bits & ~0xfffffc00) != 0)
1743 emit_insn (gen_rtx_SET (VOIDmode,
1745 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1751 emit_insn (gen_safe_SET64 (temp, high_bits));
1755 if (!reload_in_progress && !reload_completed)
1757 rtx temp2 = gen_reg_rtx (DImode);
1758 rtx temp3 = gen_reg_rtx (DImode);
1759 rtx temp4 = gen_reg_rtx (DImode);
1761 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1762 gen_rtx_ASHIFT (DImode, sub_temp,
1765 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1766 if ((low_bits & ~0xfffffc00) != 0)
1768 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1769 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1770 emit_insn (gen_rtx_SET (VOIDmode, op0,
1771 gen_rtx_PLUS (DImode, temp4, temp3)));
1775 emit_insn (gen_rtx_SET (VOIDmode, op0,
1776 gen_rtx_PLUS (DImode, temp4, temp2)));
1781 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1782 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1783 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1786 /* We are in the middle of reload, so this is really
1787 painful. However we do still make an attempt to
1788 avoid emitting truly stupid code. */
1789 if (low1 != const0_rtx)
1791 emit_insn (gen_rtx_SET (VOIDmode, op0,
1792 gen_rtx_ASHIFT (DImode, sub_temp,
1793 GEN_INT (to_shift))));
1794 emit_insn (gen_rtx_SET (VOIDmode, op0,
1795 gen_rtx_IOR (DImode, op0, low1)));
1803 if (low2 != const0_rtx)
1805 emit_insn (gen_rtx_SET (VOIDmode, op0,
1806 gen_rtx_ASHIFT (DImode, sub_temp,
1807 GEN_INT (to_shift))));
1808 emit_insn (gen_rtx_SET (VOIDmode, op0,
1809 gen_rtx_IOR (DImode, op0, low2)));
1817 emit_insn (gen_rtx_SET (VOIDmode, op0,
1818 gen_rtx_ASHIFT (DImode, sub_temp,
1819 GEN_INT (to_shift))));
1820 if (low3 != const0_rtx)
1821 emit_insn (gen_rtx_SET (VOIDmode, op0,
1822 gen_rtx_IOR (DImode, op0, low3)));
1827 /* Analyze a 64-bit constant for certain properties. */
1828 static void analyze_64bit_constant
1829 PARAMS ((unsigned HOST_WIDE_INT,
1830 unsigned HOST_WIDE_INT,
1831 int *, int *, int *));
1834 analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
1835 unsigned HOST_WIDE_INT high_bits, low_bits;
1836 int *hbsp, *lbsp, *abbasp;
1838 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1841 lowest_bit_set = highest_bit_set = -1;
1845 if ((lowest_bit_set == -1)
1846 && ((low_bits >> i) & 1))
1848 if ((highest_bit_set == -1)
1849 && ((high_bits >> (32 - i - 1)) & 1))
1850 highest_bit_set = (64 - i - 1);
1853 && ((highest_bit_set == -1)
1854 || (lowest_bit_set == -1)));
1860 if ((lowest_bit_set == -1)
1861 && ((high_bits >> i) & 1))
1862 lowest_bit_set = i + 32;
1863 if ((highest_bit_set == -1)
1864 && ((low_bits >> (32 - i - 1)) & 1))
1865 highest_bit_set = 32 - i - 1;
1868 && ((highest_bit_set == -1)
1869 || (lowest_bit_set == -1)));
1871 /* If there are no bits set this should have gone out
1872 as one instruction! */
1873 if (lowest_bit_set == -1
1874 || highest_bit_set == -1)
1876 all_bits_between_are_set = 1;
1877 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1881 if ((low_bits & (1 << i)) != 0)
1886 if ((high_bits & (1 << (i - 32))) != 0)
1889 all_bits_between_are_set = 0;
1892 *hbsp = highest_bit_set;
1893 *lbsp = lowest_bit_set;
1894 *abbasp = all_bits_between_are_set;
1897 static int const64_is_2insns
1898 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1901 const64_is_2insns (high_bits, low_bits)
1902 unsigned HOST_WIDE_INT high_bits, low_bits;
1904 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1907 || high_bits == 0xffffffff)
1910 analyze_64bit_constant (high_bits, low_bits,
1911 &highest_bit_set, &lowest_bit_set,
1912 &all_bits_between_are_set);
1914 if ((highest_bit_set == 63
1915 || lowest_bit_set == 0)
1916 && all_bits_between_are_set != 0)
1919 if ((highest_bit_set - lowest_bit_set) < 21)
1925 static unsigned HOST_WIDE_INT create_simple_focus_bits
1926 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
1929 static unsigned HOST_WIDE_INT
1930 create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
1931 unsigned HOST_WIDE_INT high_bits, low_bits;
1932 int lowest_bit_set, shift;
1934 HOST_WIDE_INT hi, lo;
1936 if (lowest_bit_set < 32)
1938 lo = (low_bits >> lowest_bit_set) << shift;
1939 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1944 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1951 /* Here we are sure to be arch64 and this is an integer constant
1952 being loaded into a register. Emit the most efficient
1953 insn sequence possible. Detection of all the 1-insn cases
1954 has been done already. */
1956 sparc_emit_set_const64 (op0, op1)
1960 unsigned HOST_WIDE_INT high_bits, low_bits;
1961 int lowest_bit_set, highest_bit_set;
1962 int all_bits_between_are_set;
1965 /* Sanity check that we know what we are working with. */
1966 if (! TARGET_ARCH64)
1969 if (GET_CODE (op0) != SUBREG)
1971 if (GET_CODE (op0) != REG
1972 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1973 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1977 if (reload_in_progress || reload_completed)
1980 temp = gen_reg_rtx (DImode);
1982 if (GET_CODE (op1) != CONST_DOUBLE
1983 && GET_CODE (op1) != CONST_INT)
1985 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1989 if (GET_CODE (op1) == CONST_DOUBLE)
1991 #if HOST_BITS_PER_WIDE_INT == 64
1992 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1993 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1995 high_bits = CONST_DOUBLE_HIGH (op1);
1996 low_bits = CONST_DOUBLE_LOW (op1);
2001 #if HOST_BITS_PER_WIDE_INT == 64
2002 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2003 low_bits = (INTVAL (op1) & 0xffffffff);
2005 high_bits = ((INTVAL (op1) < 0) ?
2008 low_bits = INTVAL (op1);
2012 /* low_bits bits 0 --> 31
2013 high_bits bits 32 --> 63 */
2015 analyze_64bit_constant (high_bits, low_bits,
2016 &highest_bit_set, &lowest_bit_set,
2017 &all_bits_between_are_set);
2019 /* First try for a 2-insn sequence. */
2021 /* These situations are preferred because the optimizer can
2022 * do more things with them:
2024 * sllx %reg, shift, %reg
2026 * srlx %reg, shift, %reg
2027 * 3) mov some_small_const, %reg
2028 * sllx %reg, shift, %reg
2030 if (((highest_bit_set == 63
2031 || lowest_bit_set == 0)
2032 && all_bits_between_are_set != 0)
2033 || ((highest_bit_set - lowest_bit_set) < 12))
2035 HOST_WIDE_INT the_const = -1;
2036 int shift = lowest_bit_set;
2038 if ((highest_bit_set != 63
2039 && lowest_bit_set != 0)
2040 || all_bits_between_are_set == 0)
2043 create_simple_focus_bits (high_bits, low_bits,
2046 else if (lowest_bit_set == 0)
2047 shift = -(63 - highest_bit_set);
2049 if (! SPARC_SIMM13_P (the_const))
2052 emit_insn (gen_safe_SET64 (temp, the_const));
2054 emit_insn (gen_rtx_SET (VOIDmode,
2056 gen_rtx_ASHIFT (DImode,
2060 emit_insn (gen_rtx_SET (VOIDmode,
2062 gen_rtx_LSHIFTRT (DImode,
2064 GEN_INT (-shift))));
2070 /* Now a range of 22 or less bits set somewhere.
2071 * 1) sethi %hi(focus_bits), %reg
2072 * sllx %reg, shift, %reg
2073 * 2) sethi %hi(focus_bits), %reg
2074 * srlx %reg, shift, %reg
2076 if ((highest_bit_set - lowest_bit_set) < 21)
2078 unsigned HOST_WIDE_INT focus_bits =
2079 create_simple_focus_bits (high_bits, low_bits,
2080 lowest_bit_set, 10);
2082 if (! SPARC_SETHI_P (focus_bits))
2085 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2087 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2088 if (lowest_bit_set < 10)
2089 emit_insn (gen_rtx_SET (VOIDmode,
2091 gen_rtx_LSHIFTRT (DImode, temp,
2092 GEN_INT (10 - lowest_bit_set))));
2093 else if (lowest_bit_set > 10)
2094 emit_insn (gen_rtx_SET (VOIDmode,
2096 gen_rtx_ASHIFT (DImode, temp,
2097 GEN_INT (lowest_bit_set - 10))));
2103 /* 1) sethi %hi(low_bits), %reg
2104 * or %reg, %lo(low_bits), %reg
2105 * 2) sethi %hi(~low_bits), %reg
2106 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2109 || high_bits == 0xffffffff)
2111 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2112 (high_bits == 0xffffffff));
2116 /* Now, try 3-insn sequences. */
2118 /* 1) sethi %hi(high_bits), %reg
2119 * or %reg, %lo(high_bits), %reg
2120 * sllx %reg, 32, %reg
2124 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2128 /* We may be able to do something quick
2129 when the constant is negated, so try that. */
2130 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2131 (~low_bits) & 0xfffffc00))
2133 /* NOTE: The trailing bits get XOR'd so we need the
2134 non-negated bits, not the negated ones. */
2135 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2137 if ((((~high_bits) & 0xffffffff) == 0
2138 && ((~low_bits) & 0x80000000) == 0)
2139 || (((~high_bits) & 0xffffffff) == 0xffffffff
2140 && ((~low_bits) & 0x80000000) != 0))
2142 int fast_int = (~low_bits & 0xffffffff);
2144 if ((SPARC_SETHI_P (fast_int)
2145 && (~high_bits & 0xffffffff) == 0)
2146 || SPARC_SIMM13_P (fast_int))
2147 emit_insn (gen_safe_SET64 (temp, fast_int));
2149 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2154 #if HOST_BITS_PER_WIDE_INT == 64
2155 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2156 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2158 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2159 (~high_bits) & 0xffffffff,
2162 sparc_emit_set_const64 (temp, negated_const);
2165 /* If we are XOR'ing with -1, then we should emit a one's complement
2166 instead. This way the combiner will notice logical operations
2167 such as ANDN later on and substitute. */
2168 if (trailing_bits == 0x3ff)
2170 emit_insn (gen_rtx_SET (VOIDmode, op0,
2171 gen_rtx_NOT (DImode, temp)));
2175 emit_insn (gen_rtx_SET (VOIDmode,
2177 gen_safe_XOR64 (temp,
2178 (-0x400 | trailing_bits))));
2183 /* 1) sethi %hi(xxx), %reg
2184 * or %reg, %lo(xxx), %reg
2185 * sllx %reg, yyy, %reg
2187 * ??? This is just a generalized version of the low_bits==0
2188 * thing above, FIXME...
2190 if ((highest_bit_set - lowest_bit_set) < 32)
2192 unsigned HOST_WIDE_INT focus_bits =
2193 create_simple_focus_bits (high_bits, low_bits,
2196 /* We can't get here in this state. */
2197 if (highest_bit_set < 32
2198 || lowest_bit_set >= 32)
2201 /* So what we know is that the set bits straddle the
2202 middle of the 64-bit word. */
2203 sparc_emit_set_const64_quick2 (op0, temp,
2209 /* 1) sethi %hi(high_bits), %reg
2210 * or %reg, %lo(high_bits), %reg
2211 * sllx %reg, 32, %reg
2212 * or %reg, low_bits, %reg
2214 if (SPARC_SIMM13_P(low_bits)
2215 && ((int)low_bits > 0))
2217 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2221 /* The easiest way when all else fails, is full decomposition. */
2223 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2224 high_bits, low_bits, ~high_bits, ~low_bits);
2226 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2229 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2230 return the mode to be used for the comparison. For floating-point,
2231 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2232 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2233 processing is needed. */
2236 select_cc_mode (op, x, y)
2239 rtx y ATTRIBUTE_UNUSED;
2241 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2267 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2268 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2270 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2271 return CCX_NOOVmode;
2277 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2284 /* X and Y are two things to compare using CODE. Emit the compare insn and
2285 return the rtx for the cc reg in the proper mode. */
2288 gen_compare_reg (code, x, y)
2292 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2295 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2296 fcc regs (cse can't tell they're really call clobbered regs and will
2297 remove a duplicate comparison even if there is an intervening function
2298 call - it will then try to reload the cc reg via an int reg which is why
2299 we need the movcc patterns). It is possible to provide the movcc
2300 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2301 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2302 to tell cse that CCFPE mode registers (even pseudos) are call
2305 /* ??? This is an experiment. Rather than making changes to cse which may
2306 or may not be easy/clean, we do our own cse. This is possible because
2307 we will generate hard registers. Cse knows they're call clobbered (it
2308 doesn't know the same thing about pseudos). If we guess wrong, no big
2309 deal, but if we win, great! */
2311 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2312 #if 1 /* experiment */
2315 /* We cycle through the registers to ensure they're all exercised. */
2316 static int next_fcc_reg = 0;
2317 /* Previous x,y for each fcc reg. */
2318 static rtx prev_args[4][2];
2320 /* Scan prev_args for x,y. */
2321 for (reg = 0; reg < 4; reg++)
2322 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2327 prev_args[reg][0] = x;
2328 prev_args[reg][1] = y;
2329 next_fcc_reg = (next_fcc_reg + 1) & 3;
2331 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2334 cc_reg = gen_reg_rtx (mode);
2335 #endif /* ! experiment */
2336 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2337 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2339 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2341 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2342 gen_rtx_COMPARE (mode, x, y)));
2347 /* This function is used for v9 only.
2348 CODE is the code for an Scc's comparison.
2349 OPERANDS[0] is the target of the Scc insn.
2350 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2351 been generated yet).
2353 This function is needed to turn
2356 (gt (reg:CCX 100 %icc)
2360 (gt:DI (reg:CCX 100 %icc)
2363 IE: The instruction recognizer needs to see the mode of the comparison to
2364 find the right instruction. We could use "gt:DI" right in the
2365 define_expand, but leaving it out allows us to handle DI, SI, etc.
2367 We refer to the global sparc compare operands sparc_compare_op0 and
2368 sparc_compare_op1. */
2371 gen_v9_scc (compare_code, operands)
2372 enum rtx_code compare_code;
2373 register rtx *operands;
2378 && (GET_MODE (sparc_compare_op0) == DImode
2379 || GET_MODE (operands[0]) == DImode))
2382 op0 = sparc_compare_op0;
2383 op1 = sparc_compare_op1;
2385 /* Try to use the movrCC insns. */
2387 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2388 && op1 == const0_rtx
2389 && v9_regcmp_p (compare_code))
2391 /* Special case for op0 != 0. This can be done with one instruction if
2392 operands[0] == sparc_compare_op0. */
2394 if (compare_code == NE
2395 && GET_MODE (operands[0]) == DImode
2396 && rtx_equal_p (op0, operands[0]))
2398 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2399 gen_rtx_IF_THEN_ELSE (DImode,
2400 gen_rtx_fmt_ee (compare_code, DImode,
2407 if (reg_overlap_mentioned_p (operands[0], op0))
2409 /* Handle the case where operands[0] == sparc_compare_op0.
2410 We "early clobber" the result. */
2411 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2412 emit_move_insn (op0, sparc_compare_op0);
2415 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2416 if (GET_MODE (op0) != DImode)
2418 temp = gen_reg_rtx (DImode);
2419 convert_move (temp, op0, 0);
2423 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2424 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2425 gen_rtx_fmt_ee (compare_code, DImode,
2433 operands[1] = gen_compare_reg (compare_code, op0, op1);
2435 switch (GET_MODE (operands[1]))
2445 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2446 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2447 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2448 gen_rtx_fmt_ee (compare_code,
2449 GET_MODE (operands[1]),
2450 operands[1], const0_rtx),
2451 const1_rtx, operands[0])));
2456 /* Emit a conditional jump insn for the v9 architecture using comparison code
2457 CODE and jump target LABEL.
2458 This function exists to take advantage of the v9 brxx insns. */
2461 emit_v9_brxx_insn (code, op0, label)
2465 emit_jump_insn (gen_rtx_SET (VOIDmode,
2467 gen_rtx_IF_THEN_ELSE (VOIDmode,
2468 gen_rtx_fmt_ee (code, GET_MODE (op0),
2470 gen_rtx_LABEL_REF (VOIDmode, label),
2474 /* Generate a DFmode part of a hard TFmode register.
2475 REG is the TFmode hard register, LOW is 1 for the
2476 low 64bit of the register and 0 otherwise.
2479 gen_df_reg (reg, low)
2483 int regno = REGNO (reg);
2485 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2486 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2487 return gen_rtx_REG (DFmode, regno);
2490 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2491 Unlike normal calls, TFmode operands are passed by reference. It is
2492 assumed that no more than 3 operands are required. */
2495 emit_soft_tfmode_libcall (func_name, nargs, operands)
2496 const char *func_name;
2500 rtx ret_slot = NULL, arg[3], func_sym;
2503 /* We only expect to be called for conversions, unary, and binary ops. */
2504 if (nargs < 2 || nargs > 3)
2507 for (i = 0; i < nargs; ++i)
2509 rtx this_arg = operands[i];
2512 /* TFmode arguments and return values are passed by reference. */
2513 if (GET_MODE (this_arg) == TFmode)
2515 int force_stack_temp;
2517 force_stack_temp = 0;
2518 if (TARGET_BUGGY_QP_LIB && i == 0)
2519 force_stack_temp = 1;
2521 if (GET_CODE (this_arg) == MEM
2522 && ! force_stack_temp)
2523 this_arg = XEXP (this_arg, 0);
2524 else if (CONSTANT_P (this_arg)
2525 && ! force_stack_temp)
2527 this_slot = force_const_mem (TFmode, this_arg);
2528 this_arg = XEXP (this_slot, 0);
2532 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2534 /* Operand 0 is the return value. We'll copy it out later. */
2536 emit_move_insn (this_slot, this_arg);
2538 ret_slot = this_slot;
2540 this_arg = XEXP (this_slot, 0);
2547 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2549 if (GET_MODE (operands[0]) == TFmode)
2552 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2553 arg[0], GET_MODE (arg[0]),
2554 arg[1], GET_MODE (arg[1]));
2556 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2557 arg[0], GET_MODE (arg[0]),
2558 arg[1], GET_MODE (arg[1]),
2559 arg[2], GET_MODE (arg[2]));
2562 emit_move_insn (operands[0], ret_slot);
2571 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2572 GET_MODE (operands[0]), 1,
2573 arg[1], GET_MODE (arg[1]));
2575 if (ret != operands[0])
2576 emit_move_insn (operands[0], ret);
2580 /* Expand soft-float TFmode calls to sparc abi routines. */
2583 emit_soft_tfmode_binop (code, operands)
2607 emit_soft_tfmode_libcall (func, 3, operands);
2611 emit_soft_tfmode_unop (code, operands)
2626 emit_soft_tfmode_libcall (func, 2, operands);
2630 emit_soft_tfmode_cvt (code, operands)
2639 switch (GET_MODE (operands[1]))
2652 case FLOAT_TRUNCATE:
2653 switch (GET_MODE (operands[0]))
2667 switch (GET_MODE (operands[1]))
2680 case UNSIGNED_FLOAT:
2681 switch (GET_MODE (operands[1]))
2695 switch (GET_MODE (operands[0]))
2709 switch (GET_MODE (operands[0]))
2726 emit_soft_tfmode_libcall (func, 2, operands);
2729 /* Expand a hard-float tfmode operation. All arguments must be in
2733 emit_hard_tfmode_operation (code, operands)
2739 if (GET_RTX_CLASS (code) == '1')
2741 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2742 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2746 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2747 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2748 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2749 operands[1], operands[2]);
2752 if (register_operand (operands[0], VOIDmode))
2755 dest = gen_reg_rtx (GET_MODE (operands[0]));
2757 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2759 if (dest != operands[0])
2760 emit_move_insn (operands[0], dest);
2764 emit_tfmode_binop (code, operands)
2768 if (TARGET_HARD_QUAD)
2769 emit_hard_tfmode_operation (code, operands);
2771 emit_soft_tfmode_binop (code, operands);
2775 emit_tfmode_unop (code, operands)
2779 if (TARGET_HARD_QUAD)
2780 emit_hard_tfmode_operation (code, operands);
2782 emit_soft_tfmode_unop (code, operands);
2786 emit_tfmode_cvt (code, operands)
2790 if (TARGET_HARD_QUAD)
2791 emit_hard_tfmode_operation (code, operands);
2793 emit_soft_tfmode_cvt (code, operands);
2796 /* Return nonzero if a return peephole merging return with
2797 setting of output register is ok. */
2799 leaf_return_peephole_ok ()
2801 return (actual_fsize == 0);
2804 /* Return nonzero if a branch/jump/call instruction will be emitting
2805 nop into its delay slot. */
2808 empty_delay_slot (insn)
2813 /* If no previous instruction (should not happen), return true. */
2814 if (PREV_INSN (insn) == NULL)
2817 seq = NEXT_INSN (PREV_INSN (insn));
2818 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2824 /* Return nonzero if TRIAL can go into the function epilogue's
2825 delay slot. SLOT is the slot we are trying to fill. */
2828 eligible_for_epilogue_delay (trial, slot)
2837 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2840 if (get_attr_length (trial) != 1)
2843 /* If there are any call-saved registers, we should scan TRIAL if it
2844 does not reference them. For now just make it easy. */
2848 /* If the function uses __builtin_eh_return, the eh_return machinery
2849 occupies the delay slot. */
2850 if (current_function_calls_eh_return)
2853 /* In the case of a true leaf function, anything can go into the delay slot.
2854 A delay slot only exists however if the frame size is zero, otherwise
2855 we will put an insn to adjust the stack after the return. */
2856 if (current_function_uses_only_leaf_regs)
2858 if (leaf_return_peephole_ok ())
2859 return ((get_attr_in_uncond_branch_delay (trial)
2860 == IN_BRANCH_DELAY_TRUE));
2864 pat = PATTERN (trial);
2866 /* Otherwise, only operations which can be done in tandem with
2867 a `restore' or `return' insn can go into the delay slot. */
2868 if (GET_CODE (SET_DEST (pat)) != REG
2869 || REGNO (SET_DEST (pat)) < 24)
2872 /* If this instruction sets up floating point register and we have a return
2873 instruction, it can probably go in. But restore will not work
2875 if (REGNO (SET_DEST (pat)) >= 32)
2877 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2878 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2883 /* The set of insns matched here must agree precisely with the set of
2884 patterns paired with a RETURN in sparc.md. */
2886 src = SET_SRC (pat);
2888 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2889 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2890 && arith_operand (src, GET_MODE (src)))
2893 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2895 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2898 /* This matches "*return_di". */
2899 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2900 && arith_double_operand (src, GET_MODE (src)))
2901 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2903 /* This matches "*return_sf_no_fpu". */
2904 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2905 && register_operand (src, SFmode))
2908 /* If we have return instruction, anything that does not use
2909 local or output registers and can go into a delay slot wins. */
2910 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2911 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2914 /* This matches "*return_addsi". */
2915 else if (GET_CODE (src) == PLUS
2916 && arith_operand (XEXP (src, 0), SImode)
2917 && arith_operand (XEXP (src, 1), SImode)
2918 && (register_operand (XEXP (src, 0), SImode)
2919 || register_operand (XEXP (src, 1), SImode)))
2922 /* This matches "*return_adddi". */
2923 else if (GET_CODE (src) == PLUS
2924 && arith_double_operand (XEXP (src, 0), DImode)
2925 && arith_double_operand (XEXP (src, 1), DImode)
2926 && (register_operand (XEXP (src, 0), DImode)
2927 || register_operand (XEXP (src, 1), DImode)))
2930 /* This can match "*return_losum_[sd]i".
2931 Catch only some cases, so that return_losum* don't have
2933 else if (GET_CODE (src) == LO_SUM
2934 && ! TARGET_CM_MEDMID
2935 && ((register_operand (XEXP (src, 0), SImode)
2936 && immediate_operand (XEXP (src, 1), SImode))
2938 && register_operand (XEXP (src, 0), DImode)
2939 && immediate_operand (XEXP (src, 1), DImode))))
2942 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2943 else if (GET_CODE (src) == ASHIFT
2944 && (register_operand (XEXP (src, 0), SImode)
2945 || register_operand (XEXP (src, 0), DImode))
2946 && XEXP (src, 1) == const1_rtx)
2952 /* Return nonzero if TRIAL can go into the sibling call
2956 eligible_for_sibcall_delay (trial)
2961 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2964 if (get_attr_length (trial) != 1)
2967 pat = PATTERN (trial);
2969 if (current_function_uses_only_leaf_regs)
2971 /* If the tail call is done using the call instruction,
2972 we have to restore %o7 in the delay slot. */
2973 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2976 /* %g1 is used to build the function address */
2977 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2983 /* Otherwise, only operations which can be done in tandem with
2984 a `restore' insn can go into the delay slot. */
2985 if (GET_CODE (SET_DEST (pat)) != REG
2986 || REGNO (SET_DEST (pat)) < 24
2987 || REGNO (SET_DEST (pat)) >= 32)
2990 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2992 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2995 src = SET_SRC (pat);
2997 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2998 && arith_operand (src, GET_MODE (src)))
3001 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3003 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3006 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3007 && arith_double_operand (src, GET_MODE (src)))
3008 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3010 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
3011 && register_operand (src, SFmode))
3014 else if (GET_CODE (src) == PLUS
3015 && arith_operand (XEXP (src, 0), SImode)
3016 && arith_operand (XEXP (src, 1), SImode)
3017 && (register_operand (XEXP (src, 0), SImode)
3018 || register_operand (XEXP (src, 1), SImode)))
3021 else if (GET_CODE (src) == PLUS
3022 && arith_double_operand (XEXP (src, 0), DImode)
3023 && arith_double_operand (XEXP (src, 1), DImode)
3024 && (register_operand (XEXP (src, 0), DImode)
3025 || register_operand (XEXP (src, 1), DImode)))
3028 else if (GET_CODE (src) == LO_SUM
3029 && ! TARGET_CM_MEDMID
3030 && ((register_operand (XEXP (src, 0), SImode)
3031 && immediate_operand (XEXP (src, 1), SImode))
3033 && register_operand (XEXP (src, 0), DImode)
3034 && immediate_operand (XEXP (src, 1), DImode))))
3037 else if (GET_CODE (src) == ASHIFT
3038 && (register_operand (XEXP (src, 0), SImode)
3039 || register_operand (XEXP (src, 0), DImode))
3040 && XEXP (src, 1) == const1_rtx)
3047 check_return_regs (x)
3050 switch (GET_CODE (x))
3053 return IN_OR_GLOBAL_P (x);
3068 if (check_return_regs (XEXP (x, 1)) == 0)
3073 return check_return_regs (XEXP (x, 0));
3082 short_branch (uid1, uid2)
3085 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3087 /* Leave a few words of "slop". */
3088 if (delta >= -1023 && delta <= 1022)
3094 /* Return nonzero if REG is not used after INSN.
3095 We assume REG is a reload reg, and therefore does
3096 not live past labels or calls or jumps. */
3098 reg_unused_after (reg, insn)
3102 enum rtx_code code, prev_code = UNKNOWN;
3104 while ((insn = NEXT_INSN (insn)))
3106 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3109 code = GET_CODE (insn);
3110 if (GET_CODE (insn) == CODE_LABEL)
3113 if (GET_RTX_CLASS (code) == 'i')
3115 rtx set = single_set (insn);
3116 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3119 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3121 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3129 /* The table we use to reference PIC data. */
3130 static GTY(()) rtx global_offset_table;
3132 /* The function we use to get at it. */
3133 static GTY(()) rtx get_pc_symbol;
3134 static char get_pc_symbol_name[256];
3136 /* Ensure that we are not using patterns that are not OK with PIC. */
3145 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3146 || (GET_CODE (recog_data.operand[i]) == CONST
3147 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3148 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3149 == global_offset_table)
3150 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3159 /* Return true if X is an address which needs a temporary register when
3160 reloaded while generating PIC code. */
3163 pic_address_needs_scratch (x)
3166 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3167 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3168 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3169 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3170 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3176 /* Legitimize PIC addresses. If the address is already position-independent,
3177 we return ORIG. Newly generated position-independent addresses go into a
3178 reg. This is REG if nonzero, otherwise we allocate register(s) as
3182 legitimize_pic_address (orig, mode, reg)
3184 enum machine_mode mode ATTRIBUTE_UNUSED;
3187 if (GET_CODE (orig) == SYMBOL_REF)
3189 rtx pic_ref, address;
3194 if (reload_in_progress || reload_completed)
3197 reg = gen_reg_rtx (Pmode);
3202 /* If not during reload, allocate another temp reg here for loading
3203 in the address, so that these instructions can be optimized
3205 rtx temp_reg = ((reload_in_progress || reload_completed)
3206 ? reg : gen_reg_rtx (Pmode));
3208 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3209 won't get confused into thinking that these two instructions
3210 are loading in the true address of the symbol. If in the
3211 future a PIC rtx exists, that should be used instead. */
3212 if (Pmode == SImode)
3214 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3215 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3219 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3220 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3227 pic_ref = gen_rtx_MEM (Pmode,
3228 gen_rtx_PLUS (Pmode,
3229 pic_offset_table_rtx, address));
3230 current_function_uses_pic_offset_table = 1;
3231 RTX_UNCHANGING_P (pic_ref) = 1;
3232 insn = emit_move_insn (reg, pic_ref);
3233 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3235 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3239 else if (GET_CODE (orig) == CONST)
3243 if (GET_CODE (XEXP (orig, 0)) == PLUS
3244 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3249 if (reload_in_progress || reload_completed)
3252 reg = gen_reg_rtx (Pmode);
3255 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3257 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3258 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3259 base == reg ? 0 : reg);
3264 if (GET_CODE (offset) == CONST_INT)
3266 if (SMALL_INT (offset))
3267 return plus_constant (base, INTVAL (offset));
3268 else if (! reload_in_progress && ! reload_completed)
3269 offset = force_reg (Pmode, offset);
3271 /* If we reach here, then something is seriously wrong. */
3274 return gen_rtx_PLUS (Pmode, base, offset);
3276 else if (GET_CODE (orig) == LABEL_REF)
3277 /* ??? Why do we do this? */
3278 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3279 the register is live instead, in case it is eliminated. */
3280 current_function_uses_pic_offset_table = 1;
3285 /* Emit special PIC prologues. */
3288 load_pic_register ()
3290 /* Labels to get the PC in the prologue of this function. */
3291 int orig_flag_pic = flag_pic;
3296 /* If we haven't emitted the special get_pc helper function, do so now. */
3297 if (get_pc_symbol_name[0] == 0)
3301 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3304 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3306 ASM_OUTPUT_ALIGN (asm_out_file, align);
3307 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
3308 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3311 /* Initialize every time through, since we can't easily
3312 know this to be permanent. */
3313 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3314 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3317 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3320 flag_pic = orig_flag_pic;
3322 /* Need to emit this whether or not we obey regdecls,
3323 since setjmp/longjmp can cause life info to screw up.
3324 ??? In the case where we don't obey regdecls, this is not sufficient
3325 since we may not fall out the bottom. */
3326 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3329 /* Return 1 if RTX is a MEM which is known to be aligned to at
3330 least a DESIRED byte boundary. */
3333 mem_min_alignment (mem, desired)
3337 rtx addr, base, offset;
3339 /* If it's not a MEM we can't accept it. */
3340 if (GET_CODE (mem) != MEM)
3343 addr = XEXP (mem, 0);
3344 base = offset = NULL_RTX;
3345 if (GET_CODE (addr) == PLUS)
3347 if (GET_CODE (XEXP (addr, 0)) == REG)
3349 base = XEXP (addr, 0);
3351 /* What we are saying here is that if the base
3352 REG is aligned properly, the compiler will make
3353 sure any REG based index upon it will be so
3355 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3356 offset = XEXP (addr, 1);
3358 offset = const0_rtx;
3361 else if (GET_CODE (addr) == REG)
3364 offset = const0_rtx;
3367 if (base != NULL_RTX)
3369 int regno = REGNO (base);
3371 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3373 /* Check if the compiler has recorded some information
3374 about the alignment of the base REG. If reload has
3375 completed, we already matched with proper alignments.
3376 If not running global_alloc, reload might give us
3377 unaligned pointer to local stack though. */
3379 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3380 || (optimize && reload_completed))
3381 && (INTVAL (offset) & (desired - 1)) == 0)
3386 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3390 else if (! TARGET_UNALIGNED_DOUBLES
3391 || CONSTANT_P (addr)
3392 || GET_CODE (addr) == LO_SUM)
3394 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3395 is true, in which case we can only assume that an access is aligned if
3396 it is to a constant address, or the address involves a LO_SUM. */
3400 /* An obviously unaligned address. */
3405 /* Vectors to keep interesting information about registers where it can easily
3406 be got. We use to use the actual mode value as the bit number, but there
3407 are more than 32 modes now. Instead we use two tables: one indexed by
3408 hard register number, and one indexed by mode. */
3410 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3411 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3412 mapped into one sparc_mode_class mode. */
3414 enum sparc_mode_class {
3415 S_MODE, D_MODE, T_MODE, O_MODE,
3416 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3420 /* Modes for single-word and smaller quantities. */
3421 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3423 /* Modes for double-word and smaller quantities. */
3424 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3426 /* Modes for quad-word and smaller quantities. */
3427 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3429 /* Modes for 8-word and smaller quantities. */
3430 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3432 /* Modes for single-float quantities. We must allow any single word or
3433 smaller quantity. This is because the fix/float conversion instructions
3434 take integer inputs/outputs from the float registers. */
3435 #define SF_MODES (S_MODES)
3437 /* Modes for double-float and smaller quantities. */
3438 #define DF_MODES (S_MODES | D_MODES)
3440 /* Modes for double-float only quantities. */
3441 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3443 /* Modes for quad-float only quantities. */
3444 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3446 /* Modes for quad-float and smaller quantities. */
3447 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3449 /* Modes for quad-float and double-float quantities. */
3450 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3452 /* Modes for quad-float pair only quantities. */
3453 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3455 /* Modes for quad-float pairs and smaller quantities. */
3456 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3458 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3460 /* Modes for condition codes. */
3461 #define CC_MODES (1 << (int) CC_MODE)
3462 #define CCFP_MODES (1 << (int) CCFP_MODE)
3464 /* Value is 1 if register/mode pair is acceptable on sparc.
3465 The funny mixture of D and T modes is because integer operations
3466 do not specially operate on tetra quantities, so non-quad-aligned
3467 registers can hold quadword quantities (except %o4 and %i4 because
3468 they cross fixed registers). */
3470 /* This points to either the 32 bit or the 64 bit version. */
3471 const int *hard_regno_mode_classes;
3473 static const int hard_32bit_mode_classes[] = {
3474 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3475 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3476 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3477 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3479 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3480 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3481 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3482 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3484 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3485 and none can hold SFmode/SImode values. */
3486 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3487 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3488 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3489 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3492 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3498 static const int hard_64bit_mode_classes[] = {
3499 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3500 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3501 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3502 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3504 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3505 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3506 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3507 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3509 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3510 and none can hold SFmode/SImode values. */
3511 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3512 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3513 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3514 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3517 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3523 int sparc_mode_class [NUM_MACHINE_MODES];
3525 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3532 for (i = 0; i < NUM_MACHINE_MODES; i++)
3534 switch (GET_MODE_CLASS (i))
3537 case MODE_PARTIAL_INT:
3538 case MODE_COMPLEX_INT:
3539 if (GET_MODE_SIZE (i) <= 4)
3540 sparc_mode_class[i] = 1 << (int) S_MODE;
3541 else if (GET_MODE_SIZE (i) == 8)
3542 sparc_mode_class[i] = 1 << (int) D_MODE;
3543 else if (GET_MODE_SIZE (i) == 16)
3544 sparc_mode_class[i] = 1 << (int) T_MODE;
3545 else if (GET_MODE_SIZE (i) == 32)
3546 sparc_mode_class[i] = 1 << (int) O_MODE;
3548 sparc_mode_class[i] = 0;
3551 case MODE_COMPLEX_FLOAT:
3552 if (GET_MODE_SIZE (i) <= 4)
3553 sparc_mode_class[i] = 1 << (int) SF_MODE;
3554 else if (GET_MODE_SIZE (i) == 8)
3555 sparc_mode_class[i] = 1 << (int) DF_MODE;
3556 else if (GET_MODE_SIZE (i) == 16)
3557 sparc_mode_class[i] = 1 << (int) TF_MODE;
3558 else if (GET_MODE_SIZE (i) == 32)
3559 sparc_mode_class[i] = 1 << (int) OF_MODE;
3561 sparc_mode_class[i] = 0;
3565 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3566 we must explicitly check for them here. */
3567 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3568 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3569 else if (i == (int) CCmode || i == (int) CC_NOOVmode
3570 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3571 sparc_mode_class[i] = 1 << (int) CC_MODE;
3573 sparc_mode_class[i] = 0;
3579 hard_regno_mode_classes = hard_64bit_mode_classes;
3581 hard_regno_mode_classes = hard_32bit_mode_classes;
3583 /* Initialize the array used by REGNO_REG_CLASS. */
3584 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3586 if (i < 16 && TARGET_V8PLUS)
3587 sparc_regno_reg_class[i] = I64_REGS;
3588 else if (i < 32 || i == FRAME_POINTER_REGNUM)
3589 sparc_regno_reg_class[i] = GENERAL_REGS;
3591 sparc_regno_reg_class[i] = FP_REGS;
3593 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3595 sparc_regno_reg_class[i] = FPCC_REGS;
3597 sparc_regno_reg_class[i] = NO_REGS;
3601 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3602 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3603 v9 int regs as it simplifies the code. */
3606 save_regs (file, low, high, base, offset, n_regs, real_offset)
3616 if (TARGET_ARCH64 && high <= 32)
3618 for (i = low; i < high; i++)
3620 if (regs_ever_live[i] && ! call_used_regs[i])
3622 fprintf (file, "\tstx\t%s, [%s+%d]\n",
3623 reg_names[i], base, offset + 4 * n_regs);
3624 if (dwarf2out_do_frame ())
3625 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3632 for (i = low; i < high; i += 2)
3634 if (regs_ever_live[i] && ! call_used_regs[i])
3636 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3638 fprintf (file, "\tstd\t%s, [%s+%d]\n",
3639 reg_names[i], base, offset + 4 * n_regs);
3640 if (dwarf2out_do_frame ())
3642 char *l = dwarf2out_cfi_label ();
3643 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
3644 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
3650 fprintf (file, "\tst\t%s, [%s+%d]\n",
3651 reg_names[i], base, offset + 4 * n_regs);
3652 if (dwarf2out_do_frame ())
3653 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3659 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3661 fprintf (file, "\tst\t%s, [%s+%d]\n",
3662 reg_names[i+1], base, offset + 4 * n_regs + 4);
3663 if (dwarf2out_do_frame ())
3664 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
3673 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3675 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3676 v9 int regs as it simplifies the code. */
3679 restore_regs (file, low, high, base, offset, n_regs)
3688 if (TARGET_ARCH64 && high <= 32)
3690 for (i = low; i < high; i++)
3692 if (regs_ever_live[i] && ! call_used_regs[i])
3693 fprintf (file, "\tldx\t[%s+%d], %s\n",
3694 base, offset + 4 * n_regs, reg_names[i]),
3700 for (i = low; i < high; i += 2)
3702 if (regs_ever_live[i] && ! call_used_regs[i])
3703 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3704 fprintf (file, "\tldd\t[%s+%d], %s\n",
3705 base, offset + 4 * n_regs, reg_names[i]),
3708 fprintf (file, "\tld\t[%s+%d], %s\n",
3709 base, offset + 4 * n_regs, reg_names[i]),
3711 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3712 fprintf (file, "\tld\t[%s+%d], %s\n",
3713 base, offset + 4 * n_regs + 4, reg_names[i+1]),
3720 /* Compute the frame size required by the function. This function is called
3721 during the reload pass and also by output_function_prologue(). */
3724 compute_frame_size (size, leaf_function)
3729 int outgoing_args_size = (current_function_outgoing_args_size
3730 + REG_PARM_STACK_SPACE (current_function_decl));
3732 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3733 even to v9 int regs to be consistent with save_regs/restore_regs. */
3737 for (i = 0; i < 8; i++)
3738 if (regs_ever_live[i] && ! call_used_regs[i])
3743 for (i = 0; i < 8; i += 2)
3744 if ((regs_ever_live[i] && ! call_used_regs[i])
3745 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3749 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3750 if ((regs_ever_live[i] && ! call_used_regs[i])
3751 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3754 /* Set up values for use in `function_epilogue'. */
3755 num_gfregs = n_regs;
3757 if (leaf_function && n_regs == 0
3758 && size == 0 && current_function_outgoing_args_size == 0)
3760 actual_fsize = apparent_fsize = 0;
3764 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3765 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
3766 apparent_fsize += n_regs * 4;
3767 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3770 /* Make sure nothing can clobber our register windows.
3771 If a SAVE must be done, or there is a stack-local variable,
3772 the register window area must be allocated.
3773 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3774 if (leaf_function == 0 || size > 0)
3775 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3777 return SPARC_STACK_ALIGN (actual_fsize);
3780 /* Build a (32 bit) big number in a register. */
3781 /* ??? We may be able to use the set macro here too. */
3784 build_big_number (file, num, reg)
3789 if (num >= 0 || ! TARGET_ARCH64)
3791 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
3792 if ((num & 0x3ff) != 0)
3793 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
3795 else /* num < 0 && TARGET_ARCH64 */
3797 /* Sethi does not sign extend, so we must use a little trickery
3798 to use it for negative numbers. Invert the constant before
3799 loading it in, then use xor immediate to invert the loaded bits
3800 (along with the upper 32 bits) to the desired constant. This
3801 works because the sethi and immediate fields overlap. */
3804 int low = -0x400 + (asize & 0x3FF);
3806 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3807 inv, reg, reg, low, reg);
3811 /* Output any necessary .register pseudo-ops. */
3813 sparc_output_scratch_registers (file)
3814 FILE *file ATTRIBUTE_UNUSED;
3816 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3822 /* Check if %g[2367] were used without
3823 .register being printed for them already. */
3824 for (i = 2; i < 8; i++)
3826 if (regs_ever_live [i]
3827 && ! sparc_hard_reg_printed [i])
3829 sparc_hard_reg_printed [i] = 1;
3830 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
3837 /* This function generates the assembly code for function entry.
3838 FILE is a stdio stream to output the code to.
3839 SIZE is an int: how many units of temporary storage to allocate.
3840 Refer to the array `regs_ever_live' to determine which registers
3841 to save; `regs_ever_live[I]' is nonzero if register number I
3842 is ever used in the function. This macro is responsible for
3843 knowing which registers should not be saved even if used. */
3845 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
3846 of memory. If any fpu reg is used in the function, we allocate
3847 such a block here, at the bottom of the frame, just in case it's needed.
3849 If this function is a leaf procedure, then we may choose not
3850 to do a "save" insn. The decision about whether or not
3851 to do this is made in regclass.c. */
3854 sparc_output_function_prologue (file, size)
3859 sparc_flat_function_prologue (file, size);
3861 sparc_nonflat_function_prologue (file, size,
3862 current_function_uses_only_leaf_regs);
3865 /* Output code for the function prologue. */
3868 sparc_nonflat_function_prologue (file, size, leaf_function)
3873 sparc_output_scratch_registers (file);
3875 /* Need to use actual_fsize, since we are also allocating
3876 space for our callee (and our own register save area). */
3877 actual_fsize = compute_frame_size (size, leaf_function);
3881 frame_base_name = "%sp";
3882 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3886 frame_base_name = "%fp";
3887 frame_base_offset = SPARC_STACK_BIAS;
3890 /* This is only for the human reader. */
3891 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3893 if (actual_fsize == 0)
3895 else if (! leaf_function)
3897 if (actual_fsize <= 4096)
3898 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3899 else if (actual_fsize <= 8192)
3901 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3902 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3906 build_big_number (file, -actual_fsize, "%g1");
3907 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
3910 else /* leaf function */
3912 if (actual_fsize <= 4096)
3913 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3914 else if (actual_fsize <= 8192)
3916 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3917 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3921 build_big_number (file, -actual_fsize, "%g1");
3922 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3926 if (dwarf2out_do_frame () && actual_fsize)
3928 char *label = dwarf2out_cfi_label ();
3930 /* The canonical frame address refers to the top of the frame. */
3931 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3932 : HARD_FRAME_POINTER_REGNUM),
3935 if (! leaf_function)
3937 /* Note the register window save. This tells the unwinder that
3938 it needs to restore the window registers from the previous
3939 frame's window save area at 0(cfa). */
3940 dwarf2out_window_save (label);
3942 /* The return address (-8) is now in %i7. */
3943 dwarf2out_return_reg (label, 31);
3947 /* If doing anything with PIC, do it now. */
3949 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3951 /* Call saved registers are saved just above the outgoing argument area. */
3954 int offset, real_offset, n_regs;
3957 real_offset = -apparent_fsize;
3958 offset = -apparent_fsize + frame_base_offset;
3959 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3961 /* ??? This might be optimized a little as %g1 might already have a
3962 value close enough that a single add insn will do. */
3963 /* ??? Although, all of this is probably only a temporary fix
3964 because if %g1 can hold a function result, then
3965 output_function_epilogue will lose (the result will get
3967 build_big_number (file, offset, "%g1");
3968 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3974 base = frame_base_name;
3977 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3978 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3983 /* Output code to restore any call saved registers. */
3986 output_restore_regs (file, leaf_function)
3988 int leaf_function ATTRIBUTE_UNUSED;
3993 offset = -apparent_fsize + frame_base_offset;
3994 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3996 build_big_number (file, offset, "%g1");
3997 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4003 base = frame_base_name;
4006 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4007 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4010 /* This function generates the assembly code for function exit,
4011 on machines that need it.
4013 The function epilogue should not depend on the current stack pointer!
4014 It should use the frame pointer only. This is mandatory because
4015 of alloca; we also take advantage of it to omit stack adjustments
4016 before returning. */
4019 sparc_output_function_epilogue (file, size)
4024 sparc_flat_function_epilogue (file, size);
4026 sparc_nonflat_function_epilogue (file, size,
4027 current_function_uses_only_leaf_regs);
4030 /* Output code for the function epilogue. */
4033 sparc_nonflat_function_epilogue (file, size, leaf_function)
4035 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
4040 if (current_function_epilogue_delay_list == 0)
4042 /* If code does not drop into the epilogue, we need
4043 do nothing except output pending case vectors.
4045 We have to still output a dummy nop for the sake of
4046 sane backtraces. Otherwise, if the last two instructions
4047 of a function were call foo; dslot; this can make the return
4048 PC of foo (ie. address of call instruction plus 8) point to
4049 the first instruction in the next function. */
4052 fputs("\tnop\n", file);
4054 insn = get_last_insn ();
4055 if (GET_CODE (insn) == NOTE)
4056 insn = prev_nonnote_insn (insn);
4057 if (insn && GET_CODE (insn) == BARRIER)
4058 goto output_vectors;
4062 output_restore_regs (file, leaf_function);
4064 /* Work out how to skip the caller's unimp instruction if required. */
4066 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4068 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4070 if (! leaf_function)
4072 if (current_function_calls_eh_return)
4074 if (current_function_epilogue_delay_list)
4076 if (SKIP_CALLERS_UNIMP_P)
4079 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4081 /* If we wound up with things in our delay slot, flush them here. */
4082 else if (current_function_epilogue_delay_list)
4084 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4086 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4088 epilogue_renumber (&delay, 0);
4089 fputs (SKIP_CALLERS_UNIMP_P
4090 ? "\treturn\t%i7+12\n"
4091 : "\treturn\t%i7+8\n", file);
4092 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4099 if (GET_CODE (delay) != SET)
4102 src = SET_SRC (delay);
4103 if (GET_CODE (src) == ASHIFT)
4105 if (XEXP (src, 1) != const1_rtx)
4108 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4112 insn = gen_rtx_PARALLEL (VOIDmode,
4113 gen_rtvec (2, delay,
4114 gen_rtx_RETURN (VOIDmode)));
4115 insn = emit_jump_insn (insn);
4117 sparc_emitting_epilogue = true;
4118 final_scan_insn (insn, file, 1, 0, 1);
4119 sparc_emitting_epilogue = false;
4122 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4123 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4125 fprintf (file, "\t%s\n\trestore\n", ret);
4127 /* All of the following cases are for leaf functions. */
4128 else if (current_function_calls_eh_return)
4130 else if (current_function_epilogue_delay_list)
4132 /* eligible_for_epilogue_delay_slot ensures that if this is a
4133 leaf function, then we will only have insn in the delay slot
4134 if the frame size is zero, thus no adjust for the stack is
4136 if (actual_fsize != 0)
4138 fprintf (file, "\t%s\n", ret);
4139 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4142 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4143 avoid generating confusing assembly language output. */
4144 else if (actual_fsize == 0)
4145 fprintf (file, "\t%s\n\tnop\n", ret);
4146 else if (actual_fsize <= 4096)
4147 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
4148 else if (actual_fsize <= 8192)
4149 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4150 ret, actual_fsize - 4096);
4151 else if ((actual_fsize & 0x3ff) == 0)
4152 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4155 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4156 actual_fsize, actual_fsize, ret);
4159 sparc_output_deferred_case_vectors ();
4162 /* Output a sibling call. */
4165 output_sibcall (insn, call_operand)
4166 rtx insn, call_operand;
4168 int leaf_regs = current_function_uses_only_leaf_regs;
4170 int delay_slot = dbr_sequence_length () > 0;
4174 /* Call to restore global regs might clobber
4175 the delay slot. Instead of checking for this
4176 output the delay slot now. */
4179 rtx delay = NEXT_INSN (insn);
4184 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4185 PATTERN (delay) = gen_blockage ();
4186 INSN_CODE (delay) = -1;
4189 output_restore_regs (asm_out_file, leaf_regs);
4192 operands[0] = call_operand;
4196 #ifdef HAVE_AS_RELAX_OPTION
4197 /* If as and ld are relaxing tail call insns into branch always,
4198 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4199 be optimized. With sethi/jmpl as nor ld has no easy way how to
4200 find out if somebody does not branch between the sethi and jmpl. */
4203 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4207 if ((actual_fsize || ! spare_slot) && delay_slot)
4209 rtx delay = NEXT_INSN (insn);
4214 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4215 PATTERN (delay) = gen_blockage ();
4216 INSN_CODE (delay) = -1;
4221 if (actual_fsize <= 4096)
4222 size = actual_fsize;
4223 else if (actual_fsize <= 8192)
4225 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4226 size = actual_fsize - 4096;
4228 else if ((actual_fsize & 0x3ff) == 0)
4229 fprintf (asm_out_file,
4230 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4234 fprintf (asm_out_file,
4235 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4236 actual_fsize, actual_fsize);
4237 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4242 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4243 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4245 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size);
4246 else if (! delay_slot)
4247 fputs ("\t nop\n", asm_out_file);
4252 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size);
4253 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4254 it into branch if possible. */
4255 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4256 output_asm_insn ("call\t%a0, 0", operands);
4257 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4262 output_asm_insn ("call\t%a0, 0", operands);
4265 rtx delay = NEXT_INSN (insn), pat;
4270 pat = PATTERN (delay);
4271 if (GET_CODE (pat) != SET)
4274 operands[0] = SET_DEST (pat);
4275 pat = SET_SRC (pat);
4276 switch (GET_CODE (pat))
4279 operands[1] = XEXP (pat, 0);
4280 operands[2] = XEXP (pat, 1);
4281 output_asm_insn (" restore %r1, %2, %Y0", operands);
4284 operands[1] = XEXP (pat, 0);
4285 operands[2] = XEXP (pat, 1);
4286 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4289 operands[1] = XEXP (pat, 0);
4290 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4294 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4297 PATTERN (delay) = gen_blockage ();
4298 INSN_CODE (delay) = -1;
4301 fputs ("\t restore\n", asm_out_file);
4305 /* Functions for handling argument passing.
4307 For v8 the first six args are normally in registers and the rest are
4308 pushed. Any arg that starts within the first 6 words is at least
4309 partially passed in a register unless its data type forbids.
4311 For v9, the argument registers are laid out as an array of 16 elements
4312 and arguments are added sequentially. The first 6 int args and up to the
4313 first 16 fp args (depending on size) are passed in regs.
4315 Slot Stack Integral Float Float in structure Double Long Double
4316 ---- ----- -------- ----- ------------------ ------ -----------
4317 15 [SP+248] %f31 %f30,%f31 %d30
4318 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4319 13 [SP+232] %f27 %f26,%f27 %d26
4320 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4321 11 [SP+216] %f23 %f22,%f23 %d22
4322 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4323 9 [SP+200] %f19 %f18,%f19 %d18
4324 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4325 7 [SP+184] %f15 %f14,%f15 %d14
4326 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4327 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4328 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4329 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4330 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4331 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4332 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4334 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4336 Integral arguments are always passed as 64 bit quantities appropriately
4339 Passing of floating point values is handled as follows.
4340 If a prototype is in scope:
4341 If the value is in a named argument (i.e. not a stdarg function or a
4342 value not part of the `...') then the value is passed in the appropriate
4344 If the value is part of the `...' and is passed in one of the first 6
4345 slots then the value is passed in the appropriate int reg.
4346 If the value is part of the `...' and is not passed in one of the first 6
4347 slots then the value is passed in memory.
4348 If a prototype is not in scope:
4349 If the value is one of the first 6 arguments the value is passed in the
4350 appropriate integer reg and the appropriate fp reg.
4351 If the value is not one of the first 6 arguments the value is passed in
4352 the appropriate fp reg and in memory.
4355 /* Maximum number of int regs for args. */
4356 #define SPARC_INT_ARG_MAX 6
4357 /* Maximum number of fp regs for args. */
4358 #define SPARC_FP_ARG_MAX 16
4360 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4362 /* Handle the INIT_CUMULATIVE_ARGS macro.
4363 Initialize a variable CUM of type CUMULATIVE_ARGS
4364 for a call to a function whose data type is FNTYPE.
4365 For a library call, FNTYPE is 0. */
4368 init_cumulative_args (cum, fntype, libname, indirect)
4369 CUMULATIVE_ARGS *cum;
4371 rtx libname ATTRIBUTE_UNUSED;
4372 int indirect ATTRIBUTE_UNUSED;
4375 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4376 cum->libcall_p = fntype == 0;
4379 /* Compute the slot number to pass an argument in.
4380 Returns the slot number or -1 if passing on the stack.
4382 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4383 the preceding args and about the function being called.
4384 MODE is the argument's machine mode.
4385 TYPE is the data type of the argument (as a tree).
4386 This is null for libcalls where that information may
4388 NAMED is nonzero if this argument is a named parameter
4389 (otherwise it is an extra parameter matching an ellipsis).
4390 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4391 *PREGNO records the register number to use if scalar type.
4392 *PPADDING records the amount of padding needed in words. */
4395 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
4396 const CUMULATIVE_ARGS *cum;
4397 enum machine_mode mode;
4404 int regbase = (incoming_p
4405 ? SPARC_INCOMING_INT_ARG_FIRST
4406 : SPARC_OUTGOING_INT_ARG_FIRST);
4407 int slotno = cum->words;
4412 if (type != 0 && TREE_ADDRESSABLE (type))
4415 && type != 0 && mode == BLKmode
4416 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4422 /* MODE is VOIDmode when generating the actual call.
4426 case QImode : case CQImode :
4427 case HImode : case CHImode :
4428 case SImode : case CSImode :
4429 case DImode : case CDImode :
4430 case TImode : case CTImode :
4431 if (slotno >= SPARC_INT_ARG_MAX)
4433 regno = regbase + slotno;
4436 case SFmode : case SCmode :
4437 case DFmode : case DCmode :
4438 case TFmode : case TCmode :
4441 if (slotno >= SPARC_INT_ARG_MAX)
4443 regno = regbase + slotno;
4447 if ((mode == TFmode || mode == TCmode)
4448 && (slotno & 1) != 0)
4449 slotno++, *ppadding = 1;
4450 if (TARGET_FPU && named)
4452 if (slotno >= SPARC_FP_ARG_MAX)
4454 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4460 if (slotno >= SPARC_INT_ARG_MAX)
4462 regno = regbase + slotno;
4468 /* For sparc64, objects requiring 16 byte alignment get it. */
4471 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
4472 slotno++, *ppadding = 1;
4476 || (type && TREE_CODE (type) == UNION_TYPE))
4478 if (slotno >= SPARC_INT_ARG_MAX)
4480 regno = regbase + slotno;
4485 int intregs_p = 0, fpregs_p = 0;
4486 /* The ABI obviously doesn't specify how packed
4487 structures are passed. These are defined to be passed
4488 in int regs if possible, otherwise memory. */
4491 /* First see what kinds of registers we need. */
4492 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4494 if (TREE_CODE (field) == FIELD_DECL)
4496 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4501 if (DECL_PACKED (field))
4505 if (packed_p || !named)
4506 fpregs_p = 0, intregs_p = 1;
4508 /* If all arg slots are filled, then must pass on stack. */
4509 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4511 /* If there are only int args and all int arg slots are filled,
4512 then must pass on stack. */
4513 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4515 /* Note that even if all int arg slots are filled, fp members may
4516 still be passed in regs if such regs are available.
4517 *PREGNO isn't set because there may be more than one, it's up
4518 to the caller to compute them. */
4531 /* Handle recursive register counting for structure field layout. */
4533 struct function_arg_record_value_parms
4536 int slotno, named, regbase;
4541 static void function_arg_record_value_3
4542 PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *));
4543 static void function_arg_record_value_2
4544 PARAMS ((tree, HOST_WIDE_INT,
4545 struct function_arg_record_value_parms *));
4546 static void function_arg_record_value_1
4547 PARAMS ((tree, HOST_WIDE_INT,
4548 struct function_arg_record_value_parms *));
4549 static rtx function_arg_record_value
4550 PARAMS ((tree, enum machine_mode, int, int, int));
4552 /* A subroutine of function_arg_record_value. Traverse the structure
4553 recusively and determine how many registers will be required. */
4556 function_arg_record_value_1 (type, startbitpos, parms)
4558 HOST_WIDE_INT startbitpos;
4559 struct function_arg_record_value_parms *parms;
4563 /* The ABI obviously doesn't specify how packed structures are
4564 passed. These are defined to be passed in int regs if possible,
4565 otherwise memory. */
4568 /* We need to compute how many registers are needed so we can
4569 allocate the PARALLEL but before we can do that we need to know
4570 whether there are any packed fields. If there are, int regs are
4571 used regardless of whether there are fp values present. */
4572 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4574 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4581 /* Compute how many registers we need. */
4582 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4584 if (TREE_CODE (field) == FIELD_DECL)
4586 HOST_WIDE_INT bitpos = startbitpos;
4588 if (DECL_SIZE (field) != 0
4589 && host_integerp (bit_position (field), 1))
4590 bitpos += int_bit_position (field);
4592 /* ??? FIXME: else assume zero offset. */
4594 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4595 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
4596 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4597 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4598 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4604 if (parms->intoffset != -1)
4606 int intslots, this_slotno;
4608 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
4610 this_slotno = parms->slotno + parms->intoffset
4613 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4614 intslots = MAX (intslots, 0);
4615 parms->nregs += intslots;
4616 parms->intoffset = -1;
4619 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4620 If it wasn't true we wouldn't be here. */
4622 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4627 if (parms->intoffset == -1)
4628 parms->intoffset = bitpos;
4634 /* A subroutine of function_arg_record_value. Assign the bits of the
4635 structure between parms->intoffset and bitpos to integer registers. */
4638 function_arg_record_value_3 (bitpos, parms)
4639 HOST_WIDE_INT bitpos;
4640 struct function_arg_record_value_parms *parms;
4642 enum machine_mode mode;
4644 unsigned int startbit, endbit;
4645 int this_slotno, intslots, intoffset;
4648 if (parms->intoffset == -1)
4651 intoffset = parms->intoffset;
4652 parms->intoffset = -1;
4654 startbit = intoffset & -BITS_PER_WORD;
4655 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4656 intslots = (endbit - startbit) / BITS_PER_WORD;
4657 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
4659 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4663 /* If this is the trailing part of a word, only load that much into
4664 the register. Otherwise load the whole register. Note that in
4665 the latter case we may pick up unwanted bits. It's not a problem
4666 at the moment but may wish to revisit. */
4668 if (intoffset % BITS_PER_WORD != 0)
4669 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4674 intoffset /= BITS_PER_UNIT;
4677 regno = parms->regbase + this_slotno;
4678 reg = gen_rtx_REG (mode, regno);
4679 XVECEXP (parms->ret, 0, parms->nregs)
4680 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4683 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4687 while (intslots > 0);
4690 /* A subroutine of function_arg_record_value. Traverse the structure
4691 recursively and assign bits to floating point registers. Track which
4692 bits in between need integer registers; invoke function_arg_record_value_3
4693 to make that happen. */
4696 function_arg_record_value_2 (type, startbitpos, parms)
4698 HOST_WIDE_INT startbitpos;
4699 struct function_arg_record_value_parms *parms;
4704 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4706 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4713 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4715 if (TREE_CODE (field) == FIELD_DECL)
4717 HOST_WIDE_INT bitpos = startbitpos;
4719 if (DECL_SIZE (field) != 0
4720 && host_integerp (bit_position (field), 1))
4721 bitpos += int_bit_position (field);
4723 /* ??? FIXME: else assume zero offset. */
4725 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4726 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
4727 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4728 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4729 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4735 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
4737 enum machine_mode mode = DECL_MODE (field);
4740 function_arg_record_value_3 (bitpos, parms);
4741 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
4742 + ((mode == SFmode || mode == SCmode)
4743 && (bitpos & 32) != 0);
4746 case SCmode: mode = SFmode; break;
4747 case DCmode: mode = DFmode; break;
4748 case TCmode: mode = TFmode; break;
4751 reg = gen_rtx_REG (mode, regno);
4752 XVECEXP (parms->ret, 0, parms->nregs)
4753 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4754 GEN_INT (bitpos / BITS_PER_UNIT));
4756 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4758 regno += GET_MODE_SIZE (mode) / 4;
4759 reg = gen_rtx_REG (mode, regno);
4760 XVECEXP (parms->ret, 0, parms->nregs)
4761 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4762 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
4769 if (parms->intoffset == -1)
4770 parms->intoffset = bitpos;
4776 /* Used by function_arg and function_value to implement the complex
4777 SPARC64 structure calling conventions. */
4780 function_arg_record_value (type, mode, slotno, named, regbase)
4782 enum machine_mode mode;
4783 int slotno, named, regbase;
4785 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4786 struct function_arg_record_value_parms parms;
4789 parms.ret = NULL_RTX;
4790 parms.slotno = slotno;
4791 parms.named = named;
4792 parms.regbase = regbase;
4794 /* Compute how many registers we need. */
4796 parms.intoffset = 0;
4797 function_arg_record_value_1 (type, 0, &parms);
4799 if (parms.intoffset != -1)
4801 unsigned int startbit, endbit;
4802 int intslots, this_slotno;
4804 startbit = parms.intoffset & -BITS_PER_WORD;
4805 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4806 intslots = (endbit - startbit) / BITS_PER_WORD;
4807 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
4809 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4810 intslots = MAX (intslots, 0);
4812 parms.nregs += intslots;
4814 nregs = parms.nregs;
4816 /* Allocate the vector and handle some annoying special cases. */
4819 /* ??? Empty structure has no value? Duh? */
4822 /* Though there's nothing really to store, return a word register
4823 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4824 leads to breakage due to the fact that there are zero bytes to
4826 return gen_rtx_REG (mode, regbase);
4830 /* ??? C++ has structures with no fields, and yet a size. Give up
4831 for now and pass everything back in integer registers. */
4832 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4834 if (nregs + slotno > SPARC_INT_ARG_MAX)
4835 nregs = SPARC_INT_ARG_MAX - slotno;
4840 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
4842 /* Fill in the entries. */
4844 parms.intoffset = 0;
4845 function_arg_record_value_2 (type, 0, &parms);
4846 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
4848 if (parms.nregs != nregs)
4854 /* Handle the FUNCTION_ARG macro.
4855 Determine where to put an argument to a function.
4856 Value is zero to push the argument on the stack,
4857 or a hard register in which to store the argument.
4859 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4860 the preceding args and about the function being called.
4861 MODE is the argument's machine mode.
4862 TYPE is the data type of the argument (as a tree).
4863 This is null for libcalls where that information may
4865 NAMED is nonzero if this argument is a named parameter
4866 (otherwise it is an extra parameter matching an ellipsis).
4867 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4870 function_arg (cum, mode, type, named, incoming_p)
4871 const CUMULATIVE_ARGS *cum;
4872 enum machine_mode mode;
4877 int regbase = (incoming_p
4878 ? SPARC_INCOMING_INT_ARG_FIRST
4879 : SPARC_OUTGOING_INT_ARG_FIRST);
4880 int slotno, regno, padding;
4883 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
4891 reg = gen_rtx_REG (mode, regno);
4895 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4896 but also have the slot allocated for them.
4897 If no prototype is in scope fp values in register slots get passed
4898 in two places, either fp regs and int regs or fp regs and memory. */
4899 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4900 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4901 && SPARC_FP_REG_P (regno))
4903 reg = gen_rtx_REG (mode, regno);
4904 if (cum->prototype_p || cum->libcall_p)
4906 /* "* 2" because fp reg numbers are recorded in 4 byte
4909 /* ??? This will cause the value to be passed in the fp reg and
4910 in the stack. When a prototype exists we want to pass the
4911 value in the reg but reserve space on the stack. That's an
4912 optimization, and is deferred [for a bit]. */
4913 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
4914 return gen_rtx_PARALLEL (mode,
4916 gen_rtx_EXPR_LIST (VOIDmode,
4917 NULL_RTX, const0_rtx),
4918 gen_rtx_EXPR_LIST (VOIDmode,
4922 /* ??? It seems that passing back a register even when past
4923 the area declared by REG_PARM_STACK_SPACE will allocate
4924 space appropriately, and will not copy the data onto the
4925 stack, exactly as we desire.
4927 This is due to locate_and_pad_parm being called in
4928 expand_call whenever reg_parm_stack_space > 0, which
4929 while benefical to our example here, would seem to be
4930 in error from what had been intended. Ho hum... -- r~ */
4938 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
4942 /* On incoming, we don't need to know that the value
4943 is passed in %f0 and %i0, and it confuses other parts
4944 causing needless spillage even on the simplest cases. */
4948 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
4949 + (regno - SPARC_FP_ARG_FIRST) / 2);
4951 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4952 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
4954 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4958 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4959 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4960 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4964 else if (type && TREE_CODE (type) == RECORD_TYPE)
4966 /* Structures up to 16 bytes in size are passed in arg slots on the
4967 stack and are promoted to registers where possible. */
4969 if (int_size_in_bytes (type) > 16)
4970 abort (); /* shouldn't get here */
4972 return function_arg_record_value (type, mode, slotno, named, regbase);
4974 else if (type && TREE_CODE (type) == UNION_TYPE)
4976 enum machine_mode mode;
4977 int bytes = int_size_in_bytes (type);
4982 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4983 reg = gen_rtx_REG (mode, regno);
4987 /* Scalar or complex int. */
4988 reg = gen_rtx_REG (mode, regno);
4994 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4995 For an arg passed partly in registers and partly in memory,
4996 this is the number of registers used.
4997 For args passed entirely in registers or entirely in memory, zero.
4999 Any arg that starts in the first 6 regs but won't entirely fit in them
5000 needs partial registers on v8. On v9, structures with integer
5001 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5002 values that begin in the last fp reg [where "last fp reg" varies with the
5003 mode] will be split between that reg and memory. */
5006 function_arg_partial_nregs (cum, mode, type, named)
5007 const CUMULATIVE_ARGS *cum;
5008 enum machine_mode mode;
5012 int slotno, regno, padding;
5014 /* We pass 0 for incoming_p here, it doesn't matter. */
5015 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5022 if ((slotno + (mode == BLKmode
5023 ? ROUND_ADVANCE (int_size_in_bytes (type))
5024 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5025 > NPARM_REGS (SImode))
5026 return NPARM_REGS (SImode) - slotno;
5031 if (type && AGGREGATE_TYPE_P (type))
5033 int size = int_size_in_bytes (type);
5034 int align = TYPE_ALIGN (type);
5037 slotno += slotno & 1;
5038 if (size > 8 && size <= 16
5039 && slotno == SPARC_INT_ARG_MAX - 1)
5042 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5043 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5046 if (GET_MODE_ALIGNMENT (mode) == 128)
5048 slotno += slotno & 1;
5049 if (slotno == SPARC_INT_ARG_MAX - 2)
5054 if (slotno == SPARC_INT_ARG_MAX - 1)
5058 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5060 if (GET_MODE_ALIGNMENT (mode) == 128)
5061 slotno += slotno & 1;
5062 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5070 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5071 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5072 quad-precision floats by invisible reference.
5073 v9: Aggregates greater than 16 bytes are passed by reference.
5074 For Pascal, also pass arrays by reference. */
5077 function_arg_pass_by_reference (cum, mode, type, named)
5078 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
5079 enum machine_mode mode;
5081 int named ATTRIBUTE_UNUSED;
5085 return ((type && AGGREGATE_TYPE_P (type))
5086 || mode == TFmode || mode == TCmode);
5090 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5091 /* Consider complex values as aggregates, so care for TCmode. */
5092 || GET_MODE_SIZE (mode) > 16
5094 && AGGREGATE_TYPE_P (type)
5095 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5099 /* Handle the FUNCTION_ARG_ADVANCE macro.
5100 Update the data in CUM to advance over an argument
5101 of mode MODE and data type TYPE.
5102 TYPE is null for libcalls where that information may not be available. */
5105 function_arg_advance (cum, mode, type, named)
5106 CUMULATIVE_ARGS *cum;
5107 enum machine_mode mode;
5111 int slotno, regno, padding;
5113 /* We pass 0 for incoming_p here, it doesn't matter. */
5114 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5116 /* If register required leading padding, add it. */
5118 cum->words += padding;
5122 cum->words += (mode != BLKmode
5123 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5124 : ROUND_ADVANCE (int_size_in_bytes (type)));
5128 if (type && AGGREGATE_TYPE_P (type))
5130 int size = int_size_in_bytes (type);
5134 else if (size <= 16)
5136 else /* passed by reference */
5139 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
5143 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5145 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
5149 cum->words += (mode != BLKmode
5150 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5151 : ROUND_ADVANCE (int_size_in_bytes (type)));
5156 /* Handle the FUNCTION_ARG_PADDING macro.
5157 For the 64 bit ABI structs are always stored left shifted in their
5161 function_arg_padding (mode, type)
5162 enum machine_mode mode;
5165 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5168 /* This is the default definition. */
5169 return (! BYTES_BIG_ENDIAN
5172 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5173 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
5174 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5175 ? downward : upward));
5178 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5179 For v9, function return values are subject to the same rules as arguments,
5180 except that up to 32-bytes may be returned in registers. */
5183 function_value (type, mode, incoming_p)
5185 enum machine_mode mode;
5189 int regbase = (incoming_p
5190 ? SPARC_OUTGOING_INT_ARG_FIRST
5191 : SPARC_INCOMING_INT_ARG_FIRST);
5193 if (TARGET_ARCH64 && type)
5195 if (TREE_CODE (type) == RECORD_TYPE)
5197 /* Structures up to 32 bytes in size are passed in registers,
5198 promoted to fp registers where possible. */
5200 if (int_size_in_bytes (type) > 32)
5201 abort (); /* shouldn't get here */
5203 return function_arg_record_value (type, mode, 0, 1, regbase);
5205 else if (AGGREGATE_TYPE_P (type))
5207 /* All other aggregate types are passed in an integer register
5208 in a mode corresponding to the size of the type. */
5209 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5214 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5219 && GET_MODE_CLASS (mode) == MODE_INT
5220 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5221 && type && ! AGGREGATE_TYPE_P (type))
5225 regno = BASE_RETURN_VALUE_REG (mode);
5227 regno = BASE_OUTGOING_VALUE_REG (mode);
5229 return gen_rtx_REG (mode, regno);
5232 /* Do what is necessary for `va_start'. We look at the current function
5233 to determine if stdarg or varargs is used and return the address of
5234 the first unnamed parameter. */
5237 sparc_builtin_saveregs ()
5239 int first_reg = current_function_args_info.words;
5243 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5244 emit_move_insn (gen_rtx_MEM (word_mode,
5245 gen_rtx_PLUS (Pmode,
5247 GEN_INT (FIRST_PARM_OFFSET (0)
5250 gen_rtx_REG (word_mode,
5251 BASE_INCOMING_ARG_REG (word_mode) + regno));
5253 address = gen_rtx_PLUS (Pmode,
5255 GEN_INT (FIRST_PARM_OFFSET (0)
5256 + UNITS_PER_WORD * first_reg));
5261 /* Implement `va_start' for varargs and stdarg. */
5264 sparc_va_start (valist, nextarg)
5268 nextarg = expand_builtin_saveregs ();
5269 std_expand_builtin_va_start (valist, nextarg);
5272 /* Implement `va_arg'. */
5275 sparc_va_arg (valist, type)
5278 HOST_WIDE_INT size, rsize, align;
5283 /* Round up sizeof(type) to a word. */
5284 size = int_size_in_bytes (type);
5285 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5290 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5291 align = 2 * UNITS_PER_WORD;
5293 if (AGGREGATE_TYPE_P (type))
5295 if ((unsigned HOST_WIDE_INT) size > 16)
5298 size = rsize = UNITS_PER_WORD;
5300 /* SPARC v9 ABI states that structures up to 8 bytes in size are
5301 given one 8 byte slot. */
5303 size = rsize = UNITS_PER_WORD;
5310 if (AGGREGATE_TYPE_P (type)
5311 || TYPE_MODE (type) == TFmode
5312 || TYPE_MODE (type) == TCmode)
5315 size = rsize = UNITS_PER_WORD;
5322 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5323 build_int_2 (align - 1, 0)));
5324 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5325 build_int_2 (-align, -1)));
5328 addr = incr = save_expr (incr);
5329 if (BYTES_BIG_ENDIAN && size < rsize)
5331 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5332 build_int_2 (rsize - size, 0)));
5334 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5335 build_int_2 (rsize, 0)));
5337 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5338 TREE_SIDE_EFFECTS (incr) = 1;
5339 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5341 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5343 /* If the address isn't aligned properly for the type,
5344 we may need to copy to a temporary.
5345 FIXME: This is inefficient. Usually we can do this
5348 && TYPE_ALIGN (type) > BITS_PER_WORD
5351 /* FIXME: We really need to specify that the temporary is live
5352 for the whole function because expand_builtin_va_arg wants
5353 the alias set to be get_varargs_alias_set (), but in this
5354 case the alias set is that for TYPE and if the memory gets
5355 reused it will be reused with alias set TYPE. */
5356 rtx tmp = assign_temp (type, 0, 1, 0);
5359 addr_rtx = force_reg (Pmode, addr_rtx);
5360 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5361 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5362 set_mem_align (addr_rtx, BITS_PER_WORD);
5363 tmp = shallow_copy_rtx (tmp);
5364 PUT_MODE (tmp, BLKmode);
5365 set_mem_alias_set (tmp, 0);
5367 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
5369 if (dest_addr != NULL_RTX)
5370 addr_rtx = dest_addr;
5372 addr_rtx = XCEXP (tmp, 0, MEM);
5377 addr_rtx = force_reg (Pmode, addr_rtx);
5378 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5379 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5385 /* Return the string to output a conditional branch to LABEL, which is
5386 the operand number of the label. OP is the conditional expression.
5387 XEXP (OP, 0) is assumed to be a condition code register (integer or
5388 floating point) and its mode specifies what kind of comparison we made.
5390 REVERSED is nonzero if we should reverse the sense of the comparison.
5392 ANNUL is nonzero if we should generate an annulling branch.
5394 NOOP is nonzero if we have to follow this branch by a noop.
5396 INSN, if set, is the insn. */
5399 output_cbranch (op, dest, label, reversed, annul, noop, insn)
5402 int reversed, annul, noop;
5405 static char string[50];
5406 enum rtx_code code = GET_CODE (op);
5407 rtx cc_reg = XEXP (op, 0);
5408 enum machine_mode mode = GET_MODE (cc_reg);
5409 const char *labelno, *branch;
5410 int spaces = 8, far;
5413 /* v9 branches are limited to +-1MB. If it is too far away,
5426 fbne,a,pn %fcc2, .LC29
5434 far = get_attr_length (insn) >= 3;
5437 /* Reversal of FP compares takes care -- an ordered compare
5438 becomes an unordered compare and vice versa. */
5439 if (mode == CCFPmode || mode == CCFPEmode)
5440 code = reverse_condition_maybe_unordered (code);
5442 code = reverse_condition (code);
5445 /* Start by writing the branch condition. */
5446 if (mode == CCFPmode || mode == CCFPEmode)
5497 /* ??? !v9: FP branches cannot be preceded by another floating point
5498 insn. Because there is currently no concept of pre-delay slots,
5499 we can fix this only by always emitting a nop before a floating
5504 strcpy (string, "nop\n\t");
5505 strcat (string, branch);
5518 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5530 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5551 strcpy (string, branch);
5553 spaces -= strlen (branch);
5554 p = strchr (string, '\0');
5556 /* Now add the annulling, the label, and a possible noop. */
5571 if (! far && insn && INSN_ADDRESSES_SET_P ())
5573 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5574 - INSN_ADDRESSES (INSN_UID (insn)));
5575 /* Leave some instructions for "slop". */
5576 if (delta < -260000 || delta >= 260000)
5580 if (mode == CCFPmode || mode == CCFPEmode)
5582 static char v9_fcc_labelno[] = "%%fccX, ";
5583 /* Set the char indicating the number of the fcc reg to use. */
5584 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5585 labelno = v9_fcc_labelno;
5588 if (REGNO (cc_reg) == SPARC_FCC_REG)
5594 else if (mode == CCXmode || mode == CCX_NOOVmode)
5596 labelno = "%%xcc, ";
5602 labelno = "%%icc, ";
5607 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5610 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5620 strcpy (p, labelno);
5621 p = strchr (p, '\0');
5624 strcpy (p, ".+12\n\tnop\n\tb\t");
5631 /* Set the char indicating the number of the operand containing the
5636 strcpy (p, "\n\tnop");
5641 /* Emit a library call comparison between floating point X and Y.
5642 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5643 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5644 values as arguments instead of the TFmode registers themselves,
5645 that's why we cannot call emit_float_lib_cmp. */
5647 sparc_emit_float_lib_cmp (x, y, comparison)
5649 enum rtx_code comparison;
5652 rtx slot0, slot1, result, tem, tem2;
5653 enum machine_mode mode;
5658 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
5662 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
5666 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
5670 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
5674 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
5678 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
5689 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
5699 if (GET_CODE (x) != MEM)
5701 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5702 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
5707 if (GET_CODE (y) != MEM)
5709 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5710 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
5715 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5717 XEXP (slot0, 0), Pmode,
5718 XEXP (slot1, 0), Pmode);
5724 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5726 x, TFmode, y, TFmode);
5732 /* Immediately move the result of the libcall into a pseudo
5733 register so reload doesn't clobber the value if it needs
5734 the return register for a spill reg. */
5735 result = gen_reg_rtx (mode);
5736 emit_move_insn (result, hard_libcall_value (mode));
5741 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
5745 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
5750 emit_cmp_insn (result, const1_rtx,
5751 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
5754 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
5757 tem = gen_reg_rtx (mode);
5759 emit_insn (gen_andsi3 (tem, result, const1_rtx));
5761 emit_insn (gen_anddi3 (tem, result, const1_rtx));
5762 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
5766 tem = gen_reg_rtx (mode);
5768 emit_insn (gen_addsi3 (tem, result, const1_rtx));
5770 emit_insn (gen_adddi3 (tem, result, const1_rtx));
5771 tem2 = gen_reg_rtx (mode);
5773 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
5775 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
5776 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
5782 /* Generate an unsigned DImode to FP conversion. This is the same code
5783 optabs would emit if we didn't have TFmode patterns. */
5786 sparc_emit_floatunsdi (operands)
5789 rtx neglab, donelab, i0, i1, f0, in, out;
5790 enum machine_mode mode;
5793 in = force_reg (DImode, operands[1]);
5794 mode = GET_MODE (out);
5795 neglab = gen_label_rtx ();
5796 donelab = gen_label_rtx ();
5797 i0 = gen_reg_rtx (DImode);
5798 i1 = gen_reg_rtx (DImode);
5799 f0 = gen_reg_rtx (mode);
5801 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
5803 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
5804 emit_jump_insn (gen_jump (donelab));
5807 emit_label (neglab);
5809 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
5810 emit_insn (gen_anddi3 (i1, in, const1_rtx));
5811 emit_insn (gen_iordi3 (i0, i0, i1));
5812 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
5813 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
5815 emit_label (donelab);
5818 /* Return the string to output a conditional branch to LABEL, testing
5819 register REG. LABEL is the operand number of the label; REG is the
5820 operand number of the reg. OP is the conditional expression. The mode
5821 of REG says what kind of comparison we made.
5823 REVERSED is nonzero if we should reverse the sense of the comparison.
5825 ANNUL is nonzero if we should generate an annulling branch.
5827 NOOP is nonzero if we have to follow this branch by a noop. */
5830 output_v9branch (op, dest, reg, label, reversed, annul, noop, insn)
5833 int reversed, annul, noop;
5836 static char string[50];
5837 enum rtx_code code = GET_CODE (op);
5838 enum machine_mode mode = GET_MODE (XEXP (op, 0));
5843 /* branch on register are limited to +-128KB. If it is too far away,
5856 brgez,a,pn %o1, .LC29
5862 ba,pt %xcc, .LC29 */
5864 far = get_attr_length (insn) >= 3;
5866 /* If not floating-point or if EQ or NE, we can just reverse the code. */
5868 code = reverse_condition (code);
5870 /* Only 64 bit versions of these instructions exist. */
5874 /* Start by writing the branch condition. */
5879 strcpy (string, "brnz");
5883 strcpy (string, "brz");
5887 strcpy (string, "brgez");
5891 strcpy (string, "brlz");
5895 strcpy (string, "brlez");
5899 strcpy (string, "brgz");
5906 p = strchr (string, '\0');
5908 /* Now add the annulling, reg, label, and nop. */
5915 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5918 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5923 *p = p < string + 8 ? '\t' : ' ';
5931 int veryfar = 1, delta;
5933 if (INSN_ADDRESSES_SET_P ())
5935 delta = (INSN_ADDRESSES (INSN_UID (dest))
5936 - INSN_ADDRESSES (INSN_UID (insn)));
5937 /* Leave some instructions for "slop". */
5938 if (delta >= -260000 && delta < 260000)
5942 strcpy (p, ".+12\n\tnop\n\t");
5953 strcpy (p, "ba,pt\t%%xcc, ");
5963 strcpy (p, "\n\tnop");
5968 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
5969 Such instructions cannot be used in the delay slot of return insn on v9.
5970 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
5974 epilogue_renumber (where, test)
5975 register rtx *where;
5978 register const char *fmt;
5980 register enum rtx_code code;
5985 code = GET_CODE (*where);
5990 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
5992 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
5993 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6001 /* Do not replace the frame pointer with the stack pointer because
6002 it can cause the delayed instruction to load below the stack.
6003 This occurs when instructions like:
6005 (set (reg/i:SI 24 %i0)
6006 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6007 (const_int -20 [0xffffffec])) 0))
6009 are in the return delayed slot. */
6011 if (GET_CODE (XEXP (*where, 0)) == REG
6012 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6013 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6014 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6019 if (SPARC_STACK_BIAS
6020 && GET_CODE (XEXP (*where, 0)) == REG
6021 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6029 fmt = GET_RTX_FORMAT (code);
6031 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6036 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6037 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6040 else if (fmt[i] == 'e'
6041 && epilogue_renumber (&(XEXP (*where, i)), test))
6047 /* Leaf functions and non-leaf functions have different needs. */
6050 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6053 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6055 static const int *const reg_alloc_orders[] = {
6056 reg_leaf_alloc_order,
6057 reg_nonleaf_alloc_order};
6060 order_regs_for_local_alloc ()
6062 static int last_order_nonleaf = 1;
6064 if (regs_ever_live[15] != last_order_nonleaf)
6066 last_order_nonleaf = !last_order_nonleaf;
6067 memcpy ((char *) reg_alloc_order,
6068 (const char *) reg_alloc_orders[last_order_nonleaf],
6069 FIRST_PSEUDO_REGISTER * sizeof (int));
6073 /* Return 1 if REG and MEM are legitimate enough to allow the various
6074 mem<-->reg splits to be run. */
6077 sparc_splitdi_legitimate (reg, mem)
6081 /* Punt if we are here by mistake. */
6082 if (! reload_completed)
6085 /* We must have an offsettable memory reference. */
6086 if (! offsettable_memref_p (mem))
6089 /* If we have legitimate args for ldd/std, we do not want
6090 the split to happen. */
6091 if ((REGNO (reg) % 2) == 0
6092 && mem_min_alignment (mem, 8))
6099 /* Return 1 if x and y are some kind of REG and they refer to
6100 different hard registers. This test is guarenteed to be
6101 run after reload. */
6104 sparc_absnegfloat_split_legitimate (x, y)
6107 if (GET_CODE (x) != REG)
6109 if (GET_CODE (y) != REG)
6111 if (REGNO (x) == REGNO (y))
6116 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6117 This makes them candidates for using ldd and std insns.
6119 Note reg1 and reg2 *must* be hard registers. */
6122 registers_ok_for_ldd_peep (reg1, reg2)
6125 /* We might have been passed a SUBREG. */
6126 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6129 if (REGNO (reg1) % 2 != 0)
6132 /* Integer ldd is deprecated in SPARC V9 */
6133 if (TARGET_V9 && REGNO (reg1) < 32)
6136 return (REGNO (reg1) == REGNO (reg2) - 1);
6139 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6142 This can only happen when addr1 and addr2, the addresses in mem1
6143 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6144 addr1 must also be aligned on a 64-bit boundary.
6146 Also iff dependent_reg_rtx is not null it should not be used to
6147 compute the address for mem1, i.e. we cannot optimize a sequence
6159 But, note that the transformation from:
6164 is perfectly fine. Thus, the peephole2 patterns always pass us
6165 the destination register of the first load, never the second one.
6167 For stores we don't have a similar problem, so dependent_reg_rtx is
6171 mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx)
6172 rtx mem1, mem2, dependent_reg_rtx;
6178 /* The mems cannot be volatile. */
6179 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6182 /* MEM1 should be aligned on a 64-bit boundary. */
6183 if (MEM_ALIGN (mem1) < 64)
6186 addr1 = XEXP (mem1, 0);
6187 addr2 = XEXP (mem2, 0);
6189 /* Extract a register number and offset (if used) from the first addr. */
6190 if (GET_CODE (addr1) == PLUS)
6192 /* If not a REG, return zero. */
6193 if (GET_CODE (XEXP (addr1, 0)) != REG)
6197 reg1 = REGNO (XEXP (addr1, 0));
6198 /* The offset must be constant! */
6199 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6201 offset1 = INTVAL (XEXP (addr1, 1));
6204 else if (GET_CODE (addr1) != REG)
6208 reg1 = REGNO (addr1);
6209 /* This was a simple (mem (reg)) expression. Offset is 0. */
6213 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6214 if (GET_CODE (addr2) != PLUS)
6217 if (GET_CODE (XEXP (addr2, 0)) != REG
6218 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6221 if (reg1 != REGNO (XEXP (addr2, 0)))
6224 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6227 /* The first offset must be evenly divisible by 8 to ensure the
6228 address is 64 bit aligned. */
6229 if (offset1 % 8 != 0)
6232 /* The offset for the second addr must be 4 more than the first addr. */
6233 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6236 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6241 /* Return 1 if reg is a pseudo, or is the first register in
6242 a hard register pair. This makes it a candidate for use in
6243 ldd and std insns. */
6246 register_ok_for_ldd (reg)
6249 /* We might have been passed a SUBREG. */
6250 if (GET_CODE (reg) != REG)
6253 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6254 return (REGNO (reg) % 2 == 0);
6259 /* Print operand X (an rtx) in assembler syntax to file FILE.
6260 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6261 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6264 print_operand (file, x, code)
6272 /* Output a 'nop' if there's nothing for the delay slot. */
6273 if (dbr_sequence_length () == 0)
6274 fputs ("\n\t nop", file);
6277 /* Output an annul flag if there's nothing for the delay slot and we
6278 are optimizing. This is always used with '(' below. */
6279 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6280 this is a dbx bug. So, we only do this when optimizing. */
6281 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6282 Always emit a nop in case the next instruction is a branch. */
6283 if (dbr_sequence_length () == 0
6284 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6288 /* Output a 'nop' if there's nothing for the delay slot and we are
6289 not optimizing. This is always used with '*' above. */
6290 if (dbr_sequence_length () == 0
6291 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6292 fputs ("\n\t nop", file);
6295 /* Output the Embedded Medium/Anywhere code model base register. */
6296 fputs (EMBMEDANY_BASE_REG, file);
6299 /* Print out what we are using as the frame pointer. This might
6300 be %fp, or might be %sp+offset. */
6301 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6302 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
6305 /* Adjust the operand to take into account a RESTORE operation. */
6306 if (GET_CODE (x) == CONST_INT)
6308 else if (GET_CODE (x) != REG)
6309 output_operand_lossage ("invalid %%Y operand");
6310 else if (REGNO (x) < 8)
6311 fputs (reg_names[REGNO (x)], file);
6312 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6313 fputs (reg_names[REGNO (x)-16], file);
6315 output_operand_lossage ("invalid %%Y operand");
6318 /* Print out the low order register name of a register pair. */
6319 if (WORDS_BIG_ENDIAN)
6320 fputs (reg_names[REGNO (x)+1], file);
6322 fputs (reg_names[REGNO (x)], file);
6325 /* Print out the high order register name of a register pair. */
6326 if (WORDS_BIG_ENDIAN)
6327 fputs (reg_names[REGNO (x)], file);
6329 fputs (reg_names[REGNO (x)+1], file);
6332 /* Print out the second register name of a register pair or quad.
6333 I.e., R (%o0) => %o1. */
6334 fputs (reg_names[REGNO (x)+1], file);
6337 /* Print out the third register name of a register quad.
6338 I.e., S (%o0) => %o2. */
6339 fputs (reg_names[REGNO (x)+2], file);
6342 /* Print out the fourth register name of a register quad.
6343 I.e., T (%o0) => %o3. */
6344 fputs (reg_names[REGNO (x)+3], file);
6347 /* Print a condition code register. */
6348 if (REGNO (x) == SPARC_ICC_REG)
6350 /* We don't handle CC[X]_NOOVmode because they're not supposed
6352 if (GET_MODE (x) == CCmode)
6353 fputs ("%icc", file);
6354 else if (GET_MODE (x) == CCXmode)
6355 fputs ("%xcc", file);
6360 /* %fccN register */
6361 fputs (reg_names[REGNO (x)], file);
6364 /* Print the operand's address only. */
6365 output_address (XEXP (x, 0));
6368 /* In this case we need a register. Use %g0 if the
6369 operand is const0_rtx. */
6371 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
6373 fputs ("%g0", file);
6380 switch (GET_CODE (x))
6382 case IOR: fputs ("or", file); break;
6383 case AND: fputs ("and", file); break;
6384 case XOR: fputs ("xor", file); break;
6385 default: output_operand_lossage ("invalid %%A operand");
6390 switch (GET_CODE (x))
6392 case IOR: fputs ("orn", file); break;
6393 case AND: fputs ("andn", file); break;
6394 case XOR: fputs ("xnor", file); break;
6395 default: output_operand_lossage ("invalid %%B operand");
6399 /* These are used by the conditional move instructions. */
6403 enum rtx_code rc = GET_CODE (x);
6407 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6408 if (mode == CCFPmode || mode == CCFPEmode)
6409 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6411 rc = reverse_condition (GET_CODE (x));
6415 case NE: fputs ("ne", file); break;
6416 case EQ: fputs ("e", file); break;
6417 case GE: fputs ("ge", file); break;
6418 case GT: fputs ("g", file); break;
6419 case LE: fputs ("le", file); break;
6420 case LT: fputs ("l", file); break;
6421 case GEU: fputs ("geu", file); break;
6422 case GTU: fputs ("gu", file); break;
6423 case LEU: fputs ("leu", file); break;
6424 case LTU: fputs ("lu", file); break;
6425 case LTGT: fputs ("lg", file); break;
6426 case UNORDERED: fputs ("u", file); break;
6427 case ORDERED: fputs ("o", file); break;
6428 case UNLT: fputs ("ul", file); break;
6429 case UNLE: fputs ("ule", file); break;
6430 case UNGT: fputs ("ug", file); break;
6431 case UNGE: fputs ("uge", file); break;
6432 case UNEQ: fputs ("ue", file); break;
6433 default: output_operand_lossage (code == 'c'
6434 ? "invalid %%c operand"
6435 : "invalid %%C operand");
6440 /* These are used by the movr instruction pattern. */
6444 enum rtx_code rc = (code == 'd'
6445 ? reverse_condition (GET_CODE (x))
6449 case NE: fputs ("ne", file); break;
6450 case EQ: fputs ("e", file); break;
6451 case GE: fputs ("gez", file); break;
6452 case LT: fputs ("lz", file); break;
6453 case LE: fputs ("lez", file); break;
6454 case GT: fputs ("gz", file); break;
6455 default: output_operand_lossage (code == 'd'
6456 ? "invalid %%d operand"
6457 : "invalid %%D operand");
6464 /* Print a sign-extended character. */
6465 int i = trunc_int_for_mode (INTVAL (x), QImode);
6466 fprintf (file, "%d", i);
6471 /* Operand must be a MEM; write its address. */
6472 if (GET_CODE (x) != MEM)
6473 output_operand_lossage ("invalid %%f operand");
6474 output_address (XEXP (x, 0));
6478 /* Do nothing special. */
6482 /* Undocumented flag. */
6483 output_operand_lossage ("invalid operand output code");
6486 if (GET_CODE (x) == REG)
6487 fputs (reg_names[REGNO (x)], file);
6488 else if (GET_CODE (x) == MEM)
6491 /* Poor Sun assembler doesn't understand absolute addressing. */
6492 if (CONSTANT_P (XEXP (x, 0)))
6493 fputs ("%g0+", file);
6494 output_address (XEXP (x, 0));
6497 else if (GET_CODE (x) == HIGH)
6499 fputs ("%hi(", file);
6500 output_addr_const (file, XEXP (x, 0));
6503 else if (GET_CODE (x) == LO_SUM)
6505 print_operand (file, XEXP (x, 0), 0);
6506 if (TARGET_CM_MEDMID)
6507 fputs ("+%l44(", file);
6509 fputs ("+%lo(", file);
6510 output_addr_const (file, XEXP (x, 1));
6513 else if (GET_CODE (x) == CONST_DOUBLE
6514 && (GET_MODE (x) == VOIDmode
6515 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
6517 if (CONST_DOUBLE_HIGH (x) == 0)
6518 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
6519 else if (CONST_DOUBLE_HIGH (x) == -1
6520 && CONST_DOUBLE_LOW (x) < 0)
6521 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
6523 output_operand_lossage ("long long constant not a valid immediate operand");
6525 else if (GET_CODE (x) == CONST_DOUBLE)
6526 output_operand_lossage ("floating point constant not a valid immediate operand");
6527 else { output_addr_const (file, x); }
6530 /* Target hook for assembling integer objects. The sparc version has
6531 special handling for aligned DI-mode objects. */
6534 sparc_assemble_integer (x, size, aligned_p)
6539 /* ??? We only output .xword's for symbols and only then in environments
6540 where the assembler can handle them. */
6541 if (aligned_p && size == 8
6542 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
6546 assemble_integer_with_op ("\t.xword\t", x);
6551 assemble_aligned_integer (4, const0_rtx);
6552 assemble_aligned_integer (4, x);
6556 return default_assemble_integer (x, size, aligned_p);
6559 /* Return the value of a code used in the .proc pseudo-op that says
6560 what kind of result this function returns. For non-C types, we pick
6561 the closest C type. */
6563 #ifndef SHORT_TYPE_SIZE
6564 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6567 #ifndef INT_TYPE_SIZE
6568 #define INT_TYPE_SIZE BITS_PER_WORD
6571 #ifndef LONG_TYPE_SIZE
6572 #define LONG_TYPE_SIZE BITS_PER_WORD
6575 #ifndef LONG_LONG_TYPE_SIZE
6576 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6579 #ifndef FLOAT_TYPE_SIZE
6580 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6583 #ifndef DOUBLE_TYPE_SIZE
6584 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6587 #ifndef LONG_DOUBLE_TYPE_SIZE
6588 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6592 sparc_type_code (type)
6595 register unsigned long qualifiers = 0;
6596 register unsigned shift;
6598 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6599 setting more, since some assemblers will give an error for this. Also,
6600 we must be careful to avoid shifts of 32 bits or more to avoid getting
6601 unpredictable results. */
6603 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
6605 switch (TREE_CODE (type))
6611 qualifiers |= (3 << shift);
6616 qualifiers |= (2 << shift);
6620 case REFERENCE_TYPE:
6622 qualifiers |= (1 << shift);
6626 return (qualifiers | 8);
6629 case QUAL_UNION_TYPE:
6630 return (qualifiers | 9);
6633 return (qualifiers | 10);
6636 return (qualifiers | 16);
6639 /* If this is a range type, consider it to be the underlying
6641 if (TREE_TYPE (type) != 0)
6644 /* Carefully distinguish all the standard types of C,
6645 without messing up if the language is not C. We do this by
6646 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6647 look at both the names and the above fields, but that's redundant.
6648 Any type whose size is between two C types will be considered
6649 to be the wider of the two types. Also, we do not have a
6650 special code to use for "long long", so anything wider than
6651 long is treated the same. Note that we can't distinguish
6652 between "int" and "long" in this code if they are the same
6653 size, but that's fine, since neither can the assembler. */
6655 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
6656 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
6658 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
6659 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
6661 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
6662 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
6665 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
6668 /* If this is a range type, consider it to be the underlying
6670 if (TREE_TYPE (type) != 0)
6673 /* Carefully distinguish all the standard types of C,
6674 without messing up if the language is not C. */
6676 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
6677 return (qualifiers | 6);
6680 return (qualifiers | 7);
6682 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
6683 /* ??? We need to distinguish between double and float complex types,
6684 but I don't know how yet because I can't reach this code from
6685 existing front-ends. */
6686 return (qualifiers | 7); /* Who knows? */
6688 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
6689 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
6690 case FILE_TYPE: /* GNU Pascal FILE type. */
6691 case SET_TYPE: /* GNU Pascal SET type. */
6692 case LANG_TYPE: /* ? */
6696 abort (); /* Not a type! */
6703 /* Nested function support. */
6705 /* Emit RTL insns to initialize the variable parts of a trampoline.
6706 FNADDR is an RTX for the address of the function's pure code.
6707 CXT is an RTX for the static chain value for the function.
6709 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6710 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6711 (to store insns). This is a bit excessive. Perhaps a different
6712 mechanism would be better here.
6714 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6717 sparc_initialize_trampoline (tramp, fnaddr, cxt)
6718 rtx tramp, fnaddr, cxt;
6720 /* SPARC 32 bit trampoline:
6723 sethi %hi(static), %g2
6725 or %g2, %lo(static), %g2
6727 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6728 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6730 #ifdef TRANSFER_FROM_TRAMPOLINE
6731 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6732 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
6736 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
6737 expand_binop (SImode, ior_optab,
6738 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
6739 size_int (10), 0, 1),
6740 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
6741 NULL_RTX, 1, OPTAB_DIRECT));
6744 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6745 expand_binop (SImode, ior_optab,
6746 expand_shift (RSHIFT_EXPR, SImode, cxt,
6747 size_int (10), 0, 1),
6748 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
6749 NULL_RTX, 1, OPTAB_DIRECT));
6752 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6753 expand_binop (SImode, ior_optab,
6754 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
6755 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
6756 NULL_RTX, 1, OPTAB_DIRECT));
6759 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6760 expand_binop (SImode, ior_optab,
6761 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
6762 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
6763 NULL_RTX, 1, OPTAB_DIRECT));
6765 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6766 aligned on a 16 byte boundary so one flush clears it all. */
6767 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
6768 if (sparc_cpu != PROCESSOR_ULTRASPARC
6769 && sparc_cpu != PROCESSOR_ULTRASPARC3)
6770 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
6771 plus_constant (tramp, 8)))));
6774 /* The 64 bit version is simpler because it makes more sense to load the
6775 values as "immediate" data out of the trampoline. It's also easier since
6776 we can read the PC without clobbering a register. */
6779 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
6780 rtx tramp, fnaddr, cxt;
6782 #ifdef TRANSFER_FROM_TRAMPOLINE
6783 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6784 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
6795 emit_move_insn (gen_rtx_MEM (SImode, tramp),
6796 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
6797 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6798 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
6799 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6800 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
6801 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6802 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
6803 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
6804 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
6805 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
6807 if (sparc_cpu != PROCESSOR_ULTRASPARC
6808 && sparc_cpu != PROCESSOR_ULTRASPARC3)
6809 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
6812 /* Subroutines to support a flat (single) register window calling
6815 /* Single-register window sparc stack frames look like:
6817 Before call After call
6818 +-----------------------+ +-----------------------+
6820 mem | caller's temps. | | caller's temps. |
6822 +-----------------------+ +-----------------------+
6824 | arguments on stack. | | arguments on stack. |
6826 +-----------------------+FP+92->+-----------------------+
6827 | 6 words to save | | 6 words to save |
6828 | arguments passed | | arguments passed |
6829 | in registers, even | | in registers, even |
6830 | if not passed. | | if not passed. |
6831 SP+68->+-----------------------+FP+68->+-----------------------+
6832 | 1 word struct addr | | 1 word struct addr |
6833 +-----------------------+FP+64->+-----------------------+
6835 | 16 word reg save area | | 16 word reg save area |
6837 SP->+-----------------------+ FP->+-----------------------+
6839 | fp/alu reg moves |
6840 FP-16->+-----------------------+
6844 +-----------------------+
6846 | fp register save |
6848 +-----------------------+
6850 | gp register save |
6852 +-----------------------+
6854 | alloca allocations |
6856 +-----------------------+
6858 | arguments on stack |
6860 SP+92->+-----------------------+
6862 | arguments passed |
6863 | in registers, even |
6864 low | if not passed. |
6865 memory SP+68->+-----------------------+
6866 | 1 word struct addr |
6867 SP+64->+-----------------------+
6869 I 16 word reg save area |
6871 SP->+-----------------------+ */
6873 /* Structure to be filled in by sparc_flat_compute_frame_size with register
6874 save masks, and offsets for the current function. */
6876 struct sparc_frame_info
6878 unsigned long total_size; /* # bytes that the entire frame takes up. */
6879 unsigned long var_size; /* # bytes that variables take up. */
6880 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6881 unsigned long extra_size; /* # bytes of extra gunk. */
6882 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6883 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6884 unsigned long gmask; /* Mask of saved gp registers. */
6885 unsigned long fmask; /* Mask of saved fp registers. */
6886 unsigned long reg_offset; /* Offset from new sp to store regs. */
6887 int initialized; /* Nonzero if frame size already calculated. */
6890 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6891 struct sparc_frame_info current_frame_info;
6893 /* Zero structure to initialize current_frame_info. */
6894 struct sparc_frame_info zero_frame_info;
6896 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6898 #define RETURN_ADDR_REGNUM 15
6899 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
6900 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6902 #define MUST_SAVE_REGISTER(regno) \
6903 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6904 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
6905 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6907 /* Return the bytes needed to compute the frame pointer from the current
6911 sparc_flat_compute_frame_size (size)
6912 int size; /* # of var. bytes allocated. */
6915 unsigned long total_size; /* # bytes that the entire frame takes up. */
6916 unsigned long var_size; /* # bytes that variables take up. */
6917 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6918 unsigned long extra_size; /* # extra bytes. */
6919 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6920 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6921 unsigned long gmask; /* Mask of saved gp registers. */
6922 unsigned long fmask; /* Mask of saved fp registers. */
6923 unsigned long reg_offset; /* Offset to register save area. */
6924 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
6926 /* This is the size of the 16 word reg save area, 1 word struct addr
6927 area, and 4 word fp/alu register copy area. */
6928 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
6938 if (!leaf_function_p ())
6940 /* Also include the size needed for the 6 parameter registers. */
6941 args_size = current_function_outgoing_args_size + 24;
6943 total_size = var_size + args_size;
6945 /* Calculate space needed for gp registers. */
6946 for (regno = 1; regno <= 31; regno++)
6948 if (MUST_SAVE_REGISTER (regno))
6950 /* If we need to save two regs in a row, ensure there's room to bump
6951 up the address to align it to a doubleword boundary. */
6952 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
6954 if (gp_reg_size % 8 != 0)
6956 gp_reg_size += 2 * UNITS_PER_WORD;
6957 gmask |= 3 << regno;
6963 gp_reg_size += UNITS_PER_WORD;
6964 gmask |= 1 << regno;
6969 /* Calculate space needed for fp registers. */
6970 for (regno = 32; regno <= 63; regno++)
6972 if (regs_ever_live[regno] && !call_used_regs[regno])
6974 fp_reg_size += UNITS_PER_WORD;
6975 fmask |= 1 << (regno - 32);
6982 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
6983 /* Ensure save area is 8 byte aligned if we need it. */
6985 if (need_aligned_p && n != 0)
6987 total_size += 8 - n;
6988 reg_offset += 8 - n;
6990 total_size += gp_reg_size + fp_reg_size;
6993 /* If we must allocate a stack frame at all, we must also allocate
6994 room for register window spillage, so as to be binary compatible
6995 with libraries and operating systems that do not use -mflat. */
6997 total_size += extra_size;
7001 total_size = SPARC_STACK_ALIGN (total_size);
7003 /* Save other computed information. */
7004 current_frame_info.total_size = total_size;
7005 current_frame_info.var_size = var_size;
7006 current_frame_info.args_size = args_size;
7007 current_frame_info.extra_size = extra_size;
7008 current_frame_info.gp_reg_size = gp_reg_size;
7009 current_frame_info.fp_reg_size = fp_reg_size;
7010 current_frame_info.gmask = gmask;
7011 current_frame_info.fmask = fmask;
7012 current_frame_info.reg_offset = reg_offset;
7013 current_frame_info.initialized = reload_completed;
7015 /* Ok, we're done. */
7019 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7022 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7023 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7024 [BASE_REG+OFFSET] will always be a valid address.
7026 WORD_OP is either "st" for save, "ld" for restore.
7027 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7030 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
7031 doubleword_op, base_offset)
7033 const char *base_reg;
7034 unsigned int offset;
7035 unsigned long gmask;
7036 unsigned long fmask;
7037 const char *word_op;
7038 const char *doubleword_op;
7039 unsigned long base_offset;
7043 if (gmask == 0 && fmask == 0)
7046 /* Save registers starting from high to low. We've already saved the
7047 previous frame pointer and previous return address for the debugger's
7048 sake. The debugger allows us to not need a nop in the epilog if at least
7049 one register is reloaded in addition to return address. */
7053 for (regno = 1; regno <= 31; regno++)
7055 if ((gmask & (1L << regno)) != 0)
7057 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7059 /* We can save two registers in a row. If we're not at a
7060 double word boundary, move to one.
7061 sparc_flat_compute_frame_size ensures there's room to do
7063 if (offset % 8 != 0)
7064 offset += UNITS_PER_WORD;
7066 if (word_op[0] == 's')
7068 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7069 doubleword_op, reg_names[regno],
7071 if (dwarf2out_do_frame ())
7073 char *l = dwarf2out_cfi_label ();
7074 dwarf2out_reg_save (l, regno, offset + base_offset);
7076 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7080 fprintf (file, "\t%s\t[%s+%d], %s\n",
7081 doubleword_op, base_reg, offset,
7084 offset += 2 * UNITS_PER_WORD;
7089 if (word_op[0] == 's')
7091 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7092 word_op, reg_names[regno],
7094 if (dwarf2out_do_frame ())
7095 dwarf2out_reg_save ("", regno, offset + base_offset);
7098 fprintf (file, "\t%s\t[%s+%d], %s\n",
7099 word_op, base_reg, offset, reg_names[regno]);
7101 offset += UNITS_PER_WORD;
7109 for (regno = 32; regno <= 63; regno++)
7111 if ((fmask & (1L << (regno - 32))) != 0)
7113 if (word_op[0] == 's')
7115 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7116 word_op, reg_names[regno],
7118 if (dwarf2out_do_frame ())
7119 dwarf2out_reg_save ("", regno, offset + base_offset);
7122 fprintf (file, "\t%s\t[%s+%d], %s\n",
7123 word_op, base_reg, offset, reg_names[regno]);
7125 offset += UNITS_PER_WORD;
7131 /* Set up the stack and frame (if desired) for the function. */
7134 sparc_flat_function_prologue (file, size)
7138 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7139 unsigned long gmask = current_frame_info.gmask;
7141 sparc_output_scratch_registers (file);
7143 /* This is only for the human reader. */
7144 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7145 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7147 current_frame_info.var_size,
7148 current_frame_info.gp_reg_size / 4,
7149 current_frame_info.fp_reg_size / 4,
7150 current_function_outgoing_args_size,
7151 current_frame_info.extra_size);
7153 size = SPARC_STACK_ALIGN (size);
7154 size = (! current_frame_info.initialized
7155 ? sparc_flat_compute_frame_size (size)
7156 : current_frame_info.total_size);
7158 /* These cases shouldn't happen. Catch them now. */
7159 if (size == 0 && (gmask || current_frame_info.fmask))
7162 /* Allocate our stack frame by decrementing %sp.
7163 At present, the only algorithm gdb can use to determine if this is a
7164 flat frame is if we always set %i7 if we set %sp. This can be optimized
7165 in the future by putting in some sort of debugging information that says
7166 this is a `flat' function. However, there is still the case of debugging
7167 code without such debugging information (including cases where most fns
7168 have such info, but there is one that doesn't). So, always do this now
7169 so we don't get a lot of code out there that gdb can't handle.
7170 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7171 distinguish us from a non-flat function but there won't (and shouldn't)
7172 be any differences anyway. The return pc is saved (if necessary) right
7173 after %i7 so gdb won't have to look too far to find it. */
7176 unsigned int reg_offset = current_frame_info.reg_offset;
7177 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7178 static const char *const t1_str = "%g1";
7180 /* Things get a little tricky if local variables take up more than ~4096
7181 bytes and outgoing arguments take up more than ~4096 bytes. When that
7182 happens, the register save area can't be accessed from either end of
7183 the frame. Handle this by decrementing %sp to the start of the gp
7184 register save area, save the regs, update %i7, and then set %sp to its
7185 final value. Given that we only have one scratch register to play
7186 with it is the cheapest solution, and it helps gdb out as it won't
7187 slow down recognition of flat functions.
7188 Don't change the order of insns emitted here without checking with
7189 the gdb folk first. */
7191 /* Is the entire register save area offsettable from %sp? */
7192 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7196 fprintf (file, "\tadd\t%s, %d, %s\n",
7197 sp_str, (int) -size, sp_str);
7198 if (gmask & HARD_FRAME_POINTER_MASK)
7200 fprintf (file, "\tst\t%s, [%s+%d]\n",
7201 fp_str, sp_str, reg_offset);
7202 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7203 sp_str, (int) -size, fp_str, ASM_COMMENT_START);
7209 fprintf (file, "\tset\t");
7210 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7211 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7212 t1_str, sp_str, t1_str, sp_str);
7213 if (gmask & HARD_FRAME_POINTER_MASK)
7215 fprintf (file, "\tst\t%s, [%s+%d]\n",
7216 fp_str, sp_str, reg_offset);
7217 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7218 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7222 if (dwarf2out_do_frame ())
7224 char *l = dwarf2out_cfi_label ();
7225 if (gmask & HARD_FRAME_POINTER_MASK)
7227 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7228 reg_offset - 4 - size);
7229 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7232 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7234 if (gmask & RETURN_ADDR_MASK)
7236 fprintf (file, "\tst\t%s, [%s+%d]\n",
7237 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7238 if (dwarf2out_do_frame ())
7239 dwarf2out_return_save ("", reg_offset - size);
7242 sparc_flat_save_restore (file, sp_str, reg_offset,
7243 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7244 current_frame_info.fmask,
7245 "st", "std", -size);
7249 /* Subtract %sp in two steps, but make sure there is always a
7250 64 byte register save area, and %sp is properly aligned. */
7251 /* Amount to decrement %sp by, the first time. */
7252 unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7253 /* Offset to register save area from %sp. */
7254 unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset);
7258 fprintf (file, "\tadd\t%s, %d, %s\n",
7259 sp_str, (int) -size1, sp_str);
7260 if (gmask & HARD_FRAME_POINTER_MASK)
7262 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7263 fp_str, sp_str, (int) offset, sp_str, (int) -size1,
7264 fp_str, ASM_COMMENT_START);
7270 fprintf (file, "\tset\t");
7271 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1);
7272 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7273 t1_str, sp_str, t1_str, sp_str);
7274 if (gmask & HARD_FRAME_POINTER_MASK)
7276 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7277 fp_str, sp_str, (int) offset, sp_str, t1_str,
7278 fp_str, ASM_COMMENT_START);
7282 if (dwarf2out_do_frame ())
7284 char *l = dwarf2out_cfi_label ();
7285 if (gmask & HARD_FRAME_POINTER_MASK)
7287 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7288 offset - 4 - size1);
7289 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7292 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7294 if (gmask & RETURN_ADDR_MASK)
7296 fprintf (file, "\tst\t%s, [%s+%d]\n",
7297 reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset);
7298 if (dwarf2out_do_frame ())
7299 /* offset - size1 == reg_offset - size
7300 if reg_offset were updated above like offset. */
7301 dwarf2out_return_save ("", offset - size1);
7304 sparc_flat_save_restore (file, sp_str, offset,
7305 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7306 current_frame_info.fmask,
7307 "st", "std", -size1);
7308 fprintf (file, "\tset\t");
7309 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size - size1);
7310 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7311 t1_str, sp_str, t1_str, sp_str);
7312 if (dwarf2out_do_frame ())
7313 if (! (gmask & HARD_FRAME_POINTER_MASK))
7314 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
7318 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
7321 /* Do any necessary cleanup after a function to restore stack, frame,
7325 sparc_flat_function_epilogue (file, size)
7329 rtx epilogue_delay = current_function_epilogue_delay_list;
7330 int noepilogue = FALSE;
7332 /* This is only for the human reader. */
7333 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
7335 /* The epilogue does not depend on any registers, but the stack
7336 registers, so we assume that if we have 1 pending nop, it can be
7337 ignored, and 2 it must be filled (2 nops occur for integer
7338 multiply and divide). */
7340 size = SPARC_STACK_ALIGN (size);
7341 size = (!current_frame_info.initialized
7342 ? sparc_flat_compute_frame_size (size)
7343 : current_frame_info.total_size);
7345 if (size == 0 && epilogue_delay == 0)
7347 rtx insn = get_last_insn ();
7349 /* If the last insn was a BARRIER, we don't have to write any code
7350 because a jump (aka return) was put there. */
7351 if (GET_CODE (insn) == NOTE)
7352 insn = prev_nonnote_insn (insn);
7353 if (insn && GET_CODE (insn) == BARRIER)
7359 unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset;
7360 unsigned HOST_WIDE_INT size1;
7361 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7362 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7363 static const char *const t1_str = "%g1";
7365 /* In the reload sequence, we don't need to fill the load delay
7366 slots for most of the loads, also see if we can fill the final
7367 delay slot if not otherwise filled by the reload sequence. */
7371 fprintf (file, "\tset\t");
7372 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7373 fprintf (file, ", %s\n", t1_str);
7376 if (frame_pointer_needed)
7379 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7380 fp_str, t1_str, sp_str, ASM_COMMENT_START);
7382 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
7383 fp_str, (int) size, sp_str, ASM_COMMENT_START);
7386 /* Is the entire register save area offsettable from %sp? */
7387 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7393 /* Restore %sp in two steps, but make sure there is always a
7394 64 byte register save area, and %sp is properly aligned. */
7395 /* Amount to increment %sp by, the first time. */
7396 size1 = ((reg_offset - 64 - 16) + 15) & -16;
7397 /* Offset to register save area from %sp. */
7398 reg_offset = size1 - reg_offset;
7400 fprintf (file, "\tset\t");
7401 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1);
7402 fprintf (file, ", %s\n\tadd\t%s, %s, %s\n",
7403 t1_str, sp_str, t1_str, sp_str);
7406 /* We must restore the frame pointer and return address reg first
7407 because they are treated specially by the prologue output code. */
7408 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
7410 fprintf (file, "\tld\t[%s+%d], %s\n",
7411 sp_str, (int) reg_offset, fp_str);
7414 if (current_frame_info.gmask & RETURN_ADDR_MASK)
7416 fprintf (file, "\tld\t[%s+%d], %s\n",
7417 sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]);
7421 /* Restore any remaining saved registers. */
7422 sparc_flat_save_restore (file, sp_str, reg_offset,
7423 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7424 current_frame_info.fmask,
7427 /* If we had to increment %sp in two steps, record it so the second
7428 restoration in the epilogue finishes up. */
7434 fprintf (file, "\tset\t");
7435 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7436 fprintf (file, ", %s\n", t1_str);
7440 if (current_function_returns_struct)
7441 fprintf (file, "\tjmp\t%%o7+12\n");
7443 fprintf (file, "\tretl\n");
7445 /* If the only register saved is the return address, we need a
7446 nop, unless we have an instruction to put into it. Otherwise
7447 we don't since reloading multiple registers doesn't reference
7448 the register being loaded. */
7454 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
7457 else if (size > 4095)
7458 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7461 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str);
7464 fprintf (file, "\tnop\n");
7467 /* Reset state info for each function. */
7468 current_frame_info = zero_frame_info;
7470 sparc_output_deferred_case_vectors ();
7473 /* Define the number of delay slots needed for the function epilogue.
7475 On the sparc, we need a slot if either no stack has been allocated,
7476 or the only register saved is the return register. */
7479 sparc_flat_epilogue_delay_slots ()
7481 if (!current_frame_info.initialized)
7482 (void) sparc_flat_compute_frame_size (get_frame_size ());
7484 if (current_frame_info.total_size == 0)
7490 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7491 Any single length instruction which doesn't reference the stack or frame
7495 sparc_flat_eligible_for_epilogue_delay (trial, slot)
7497 int slot ATTRIBUTE_UNUSED;
7499 rtx pat = PATTERN (trial);
7501 if (get_attr_length (trial) != 1)
7504 if (! reg_mentioned_p (stack_pointer_rtx, pat)
7505 && ! reg_mentioned_p (frame_pointer_rtx, pat))
7511 /* Adjust the cost of a scheduling dependency. Return the new cost of
7512 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7515 supersparc_adjust_cost (insn, link, dep_insn, cost)
7521 enum attr_type insn_type;
7523 if (! recog_memoized (insn))
7526 insn_type = get_attr_type (insn);
7528 if (REG_NOTE_KIND (link) == 0)
7530 /* Data dependency; DEP_INSN writes a register that INSN reads some
7533 /* if a load, then the dependence must be on the memory address;
7534 add an extra "cycle". Note that the cost could be two cycles
7535 if the reg was written late in an instruction group; we ca not tell
7537 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7540 /* Get the delay only if the address of the store is the dependence. */
7541 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7543 rtx pat = PATTERN(insn);
7544 rtx dep_pat = PATTERN (dep_insn);
7546 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7547 return cost; /* This should not happen! */
7549 /* The dependency between the two instructions was on the data that
7550 is being stored. Assume that this implies that the address of the
7551 store is not dependent. */
7552 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7555 return cost + 3; /* An approximation. */
7558 /* A shift instruction cannot receive its data from an instruction
7559 in the same cycle; add a one cycle penalty. */
7560 if (insn_type == TYPE_SHIFT)
7561 return cost + 3; /* Split before cascade into shift. */
7565 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7566 INSN writes some cycles later. */
7568 /* These are only significant for the fpu unit; writing a fp reg before
7569 the fpu has finished with it stalls the processor. */
7571 /* Reusing an integer register causes no problems. */
7572 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7580 hypersparc_adjust_cost (insn, link, dep_insn, cost)
7586 enum attr_type insn_type, dep_type;
7587 rtx pat = PATTERN(insn);
7588 rtx dep_pat = PATTERN (dep_insn);
7590 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7593 insn_type = get_attr_type (insn);
7594 dep_type = get_attr_type (dep_insn);
7596 switch (REG_NOTE_KIND (link))
7599 /* Data dependency; DEP_INSN writes a register that INSN reads some
7606 /* Get the delay iff the address of the store is the dependence. */
7607 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7610 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7617 /* If a load, then the dependence must be on the memory address. If
7618 the addresses aren't equal, then it might be a false dependency */
7619 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7621 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7622 || GET_CODE (SET_DEST (dep_pat)) != MEM
7623 || GET_CODE (SET_SRC (pat)) != MEM
7624 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7625 XEXP (SET_SRC (pat), 0)))
7633 /* Compare to branch latency is 0. There is no benefit from
7634 separating compare and branch. */
7635 if (dep_type == TYPE_COMPARE)
7637 /* Floating point compare to branch latency is less than
7638 compare to conditional move. */
7639 if (dep_type == TYPE_FPCMP)
7648 /* Anti-dependencies only penalize the fpu unit. */
7649 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7661 sparc_adjust_cost(insn, link, dep, cost)
7669 case PROCESSOR_SUPERSPARC:
7670 cost = supersparc_adjust_cost (insn, link, dep, cost);
7672 case PROCESSOR_HYPERSPARC:
7673 case PROCESSOR_SPARCLITE86X:
7674 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7683 sparc_sched_init (dump, sched_verbose, max_ready)
7684 FILE *dump ATTRIBUTE_UNUSED;
7685 int sched_verbose ATTRIBUTE_UNUSED;
7686 int max_ready ATTRIBUTE_UNUSED;
7691 sparc_use_dfa_pipeline_interface ()
7693 if ((1 << sparc_cpu) &
7694 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
7695 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7696 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
7697 (1 << PROCESSOR_ULTRASPARC3)))
7703 sparc_use_sched_lookahead ()
7705 if (sparc_cpu == PROCESSOR_ULTRASPARC
7706 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7708 if ((1 << sparc_cpu) &
7709 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7710 (1 << PROCESSOR_SPARCLITE86X)))
7723 /* Assume V9 processors are capable of at least dual-issue. */
7725 case PROCESSOR_SUPERSPARC:
7727 case PROCESSOR_HYPERSPARC:
7728 case PROCESSOR_SPARCLITE86X:
7730 case PROCESSOR_ULTRASPARC:
7731 case PROCESSOR_ULTRASPARC3:
7740 register rtx pat = PATTERN (insn);
7742 switch (GET_CODE (SET_SRC (pat)))
7744 /* Load and some shift instructions zero extend. */
7747 /* sethi clears the high bits */
7749 /* LO_SUM is used with sethi. sethi cleared the high
7750 bits and the values used with lo_sum are positive */
7752 /* Store flag stores 0 or 1 */
7762 rtx op0 = XEXP (SET_SRC (pat), 0);
7763 rtx op1 = XEXP (SET_SRC (pat), 1);
7764 if (GET_CODE (op1) == CONST_INT)
7765 return INTVAL (op1) >= 0;
7766 if (GET_CODE (op0) != REG)
7768 if (sparc_check_64 (op0, insn) == 1)
7770 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7775 rtx op0 = XEXP (SET_SRC (pat), 0);
7776 rtx op1 = XEXP (SET_SRC (pat), 1);
7777 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7779 if (GET_CODE (op1) == CONST_INT)
7780 return INTVAL (op1) >= 0;
7781 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7784 return GET_MODE (SET_SRC (pat)) == SImode;
7785 /* Positive integers leave the high bits zero. */
7787 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7789 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7792 return - (GET_MODE (SET_SRC (pat)) == SImode);
7794 return sparc_check_64 (SET_SRC (pat), insn);
7800 /* We _ought_ to have only one kind per function, but... */
7801 static GTY(()) rtx sparc_addr_diff_list;
7802 static GTY(()) rtx sparc_addr_list;
7805 sparc_defer_case_vector (lab, vec, diff)
7809 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7811 sparc_addr_diff_list
7812 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7814 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7818 sparc_output_addr_vec (vec)
7821 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7822 int idx, vlen = XVECLEN (body, 0);
7824 #ifdef ASM_OUTPUT_ADDR_VEC_START
7825 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7828 #ifdef ASM_OUTPUT_CASE_LABEL
7829 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7832 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7835 for (idx = 0; idx < vlen; idx++)
7837 ASM_OUTPUT_ADDR_VEC_ELT
7838 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7841 #ifdef ASM_OUTPUT_ADDR_VEC_END
7842 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7847 sparc_output_addr_diff_vec (vec)
7850 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7851 rtx base = XEXP (XEXP (body, 0), 0);
7852 int idx, vlen = XVECLEN (body, 1);
7854 #ifdef ASM_OUTPUT_ADDR_VEC_START
7855 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7858 #ifdef ASM_OUTPUT_CASE_LABEL
7859 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7862 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7865 for (idx = 0; idx < vlen; idx++)
7867 ASM_OUTPUT_ADDR_DIFF_ELT
7870 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7871 CODE_LABEL_NUMBER (base));
7874 #ifdef ASM_OUTPUT_ADDR_VEC_END
7875 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7880 sparc_output_deferred_case_vectors ()
7885 if (sparc_addr_list == NULL_RTX
7886 && sparc_addr_diff_list == NULL_RTX)
7889 /* Align to cache line in the function's code section. */
7890 function_section (current_function_decl);
7892 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7894 ASM_OUTPUT_ALIGN (asm_out_file, align);
7896 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7897 sparc_output_addr_vec (XEXP (t, 0));
7898 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7899 sparc_output_addr_diff_vec (XEXP (t, 0));
7901 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7904 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7905 unknown. Return 1 if the high bits are zero, -1 if the register is
7908 sparc_check_64 (x, insn)
7911 /* If a register is set only once it is safe to ignore insns this
7912 code does not know how to handle. The loop will either recognize
7913 the single set and return the correct value or fail to recognize
7918 if (GET_CODE (x) != REG)
7921 if (GET_MODE (x) == DImode)
7922 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
7924 if (flag_expensive_optimizations
7925 && REG_N_SETS (REGNO (y)) == 1)
7931 insn = get_last_insn_anywhere ();
7936 while ((insn = PREV_INSN (insn)))
7938 switch (GET_CODE (insn))
7951 rtx pat = PATTERN (insn);
7952 if (GET_CODE (pat) != SET)
7954 if (rtx_equal_p (x, SET_DEST (pat)))
7955 return set_extends (insn);
7956 if (y && rtx_equal_p (y, SET_DEST (pat)))
7957 return set_extends (insn);
7958 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
7967 sparc_v8plus_shift (operands, insn, opcode)
7972 static char asm_code[60];
7974 if (GET_CODE (operands[3]) == SCRATCH)
7975 operands[3] = operands[0];
7976 if (GET_CODE (operands[1]) == CONST_INT)
7978 output_asm_insn ("mov\t%1, %3", operands);
7982 output_asm_insn ("sllx\t%H1, 32, %3", operands);
7983 if (sparc_check_64 (operands[1], insn) <= 0)
7984 output_asm_insn ("srl\t%L1, 0, %L1", operands);
7985 output_asm_insn ("or\t%L1, %3, %3", operands);
7988 strcpy(asm_code, opcode);
7989 if (which_alternative != 2)
7990 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7992 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7995 /* Output rtl to increment the profiler label LABELNO
7996 for profiling a function entry. */
7999 sparc_profile_hook (labelno)
8005 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8006 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8007 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8009 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8012 #ifdef OBJECT_FORMAT_ELF
8014 sparc_elf_asm_named_section (name, flags)
8018 if (flags & SECTION_MERGE)
8020 /* entsize cannot be expressed in this section attributes
8022 default_elf_asm_named_section (name, flags);
8026 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8028 if (!(flags & SECTION_DEBUG))
8029 fputs (",#alloc", asm_out_file);
8030 if (flags & SECTION_WRITE)
8031 fputs (",#write", asm_out_file);
8032 if (flags & SECTION_CODE)
8033 fputs (",#execinstr", asm_out_file);
8035 /* ??? Handle SECTION_BSS. */
8037 fputc ('\n', asm_out_file);
8039 #endif /* OBJECT_FORMAT_ELF */
8041 /* We do not allow sibling calls if -mflat, nor
8042 we do not allow indirect calls to be optimized into sibling calls.
8044 Also, on sparc 32-bit we cannot emit a sibling call when the
8045 current function returns a structure. This is because the "unimp
8046 after call" convention would cause the callee to return to the
8047 wrong place. The generic code already disallows cases where the
8048 function being called returns a structure.
8050 It may seem strange how this last case could occur. Usually there
8051 is code after the call which jumps to epilogue code which dumps the
8052 return value into the struct return area. That ought to invalidate
8053 the sibling call right? Well, in the c++ case we can end up passing
8054 the pointer to the struct return area to a constructor (which returns
8055 void) and then nothing else happens. Such a sibling call would look
8056 valid without the added check here. */
8058 sparc_function_ok_for_sibcall (decl, exp)
8060 tree exp ATTRIBUTE_UNUSED;
8064 && (TARGET_ARCH64 || ! current_function_returns_struct));
8067 /* ??? Similar to the standard section selection, but force reloc-y-ness
8068 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8069 pretending PIC always on), but that's what the old code did. */
8072 sparc_aout_select_section (t, reloc, align)
8075 unsigned HOST_WIDE_INT align;
8077 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
8080 /* Use text section for a constant unless we need more alignment than
8084 sparc_aout_select_rtx_section (mode, x, align)
8085 enum machine_mode mode;
8087 unsigned HOST_WIDE_INT align;
8089 if (align <= MAX_TEXT_ALIGN
8090 && ! (flag_pic && (symbolic_operand (x, mode)
8091 || SUNOS4_SHARED_LIBRARIES)))
8092 readonly_data_section ();
8098 sparc_extra_constraint_check (op, c, strict)
8106 && (c == 'T' || c == 'U'))
8112 return fp_sethi_p (op);
8115 return fp_mov_p (op);
8118 return fp_high_losum_p (op);
8122 || (GET_CODE (op) == REG
8123 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8124 || reg_renumber[REGNO (op)] >= 0)))
8125 return register_ok_for_ldd (op);
8137 /* Our memory extra constraints have to emulate the
8138 behavior of 'm' and 'o' in order for reload to work
8140 if (GET_CODE (op) == MEM)
8143 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8145 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8150 reload_ok_mem = (reload_in_progress
8151 && GET_CODE (op) == REG
8152 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8153 && reg_renumber [REGNO (op)] < 0);
8156 return reload_ok_mem;
8159 /* ??? This duplicates information provided to the compiler by the
8160 ??? scheduler description. Some day, teach genautomata to output
8161 ??? the latencies and then CSE will just use that. */
8164 sparc_rtx_costs (x, code, outer_code, total)
8166 int code, outer_code, *total;
8170 case PLUS: case MINUS: case ABS: case NEG:
8171 case FLOAT: case UNSIGNED_FLOAT:
8172 case FIX: case UNSIGNED_FIX:
8173 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8174 if (FLOAT_MODE_P (GET_MODE (x)))
8178 case PROCESSOR_ULTRASPARC:
8179 case PROCESSOR_ULTRASPARC3:
8180 *total = COSTS_N_INSNS (4);
8183 case PROCESSOR_SUPERSPARC:
8184 *total = COSTS_N_INSNS (3);
8187 case PROCESSOR_CYPRESS:
8188 *total = COSTS_N_INSNS (5);
8191 case PROCESSOR_HYPERSPARC:
8192 case PROCESSOR_SPARCLITE86X:
8194 *total = COSTS_N_INSNS (1);
8199 *total = COSTS_N_INSNS (1);
8205 case PROCESSOR_ULTRASPARC:
8206 if (GET_MODE (x) == SFmode)
8207 *total = COSTS_N_INSNS (13);
8209 *total = COSTS_N_INSNS (23);
8212 case PROCESSOR_ULTRASPARC3:
8213 if (GET_MODE (x) == SFmode)
8214 *total = COSTS_N_INSNS (20);
8216 *total = COSTS_N_INSNS (29);
8219 case PROCESSOR_SUPERSPARC:
8220 *total = COSTS_N_INSNS (12);
8223 case PROCESSOR_CYPRESS:
8224 *total = COSTS_N_INSNS (63);
8227 case PROCESSOR_HYPERSPARC:
8228 case PROCESSOR_SPARCLITE86X:
8229 *total = COSTS_N_INSNS (17);
8233 *total = COSTS_N_INSNS (30);
8238 if (FLOAT_MODE_P (GET_MODE (x)))
8242 case PROCESSOR_ULTRASPARC:
8243 case PROCESSOR_ULTRASPARC3:
8244 *total = COSTS_N_INSNS (1);
8247 case PROCESSOR_SUPERSPARC:
8248 *total = COSTS_N_INSNS (3);
8251 case PROCESSOR_CYPRESS:
8252 *total = COSTS_N_INSNS (5);
8255 case PROCESSOR_HYPERSPARC:
8256 case PROCESSOR_SPARCLITE86X:
8258 *total = COSTS_N_INSNS (1);
8263 /* ??? Maybe mark integer compares as zero cost on
8264 ??? all UltraSPARC processors because the result
8265 ??? can be bypassed to a branch in the same group. */
8267 *total = COSTS_N_INSNS (1);
8271 if (FLOAT_MODE_P (GET_MODE (x)))
8275 case PROCESSOR_ULTRASPARC:
8276 case PROCESSOR_ULTRASPARC3:
8277 *total = COSTS_N_INSNS (4);
8280 case PROCESSOR_SUPERSPARC:
8281 *total = COSTS_N_INSNS (3);
8284 case PROCESSOR_CYPRESS:
8285 *total = COSTS_N_INSNS (7);
8288 case PROCESSOR_HYPERSPARC:
8289 case PROCESSOR_SPARCLITE86X:
8290 *total = COSTS_N_INSNS (1);
8294 *total = COSTS_N_INSNS (5);
8299 /* The latency is actually variable for Ultra-I/II
8300 And if one of the inputs have a known constant
8301 value, we could calculate this precisely.
8303 However, for that to be useful we would need to
8304 add some machine description changes which would
8305 make sure small constants ended up in rs1 of the
8306 multiply instruction. This is because the multiply
8307 latency is determined by the number of clear (or
8308 set if the value is negative) bits starting from
8309 the most significant bit of the first input.
8311 The algorithm for computing num_cycles of a multiply
8315 highest_bit = highest_clear_bit(rs1);
8317 highest_bit = highest_set_bit(rs1);
8320 num_cycles = 4 + ((highest_bit - 3) / 2);
8322 If we did that we would have to also consider register
8323 allocation issues that would result from forcing such
8324 a value into a register.
8326 There are other similar tricks we could play if we
8327 knew, for example, that one input was an array index.
8329 Since we do not play any such tricks currently the
8330 safest thing to do is report the worst case latency. */
8331 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8333 *total = (GET_MODE (x) == DImode
8334 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8338 /* Multiply latency on Ultra-III, fortunately, is constant. */
8339 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8341 *total = COSTS_N_INSNS (6);
8345 if (sparc_cpu == PROCESSOR_HYPERSPARC
8346 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8348 *total = COSTS_N_INSNS (17);
8352 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
8359 if (FLOAT_MODE_P (GET_MODE (x)))
8363 case PROCESSOR_ULTRASPARC:
8364 if (GET_MODE (x) == SFmode)
8365 *total = COSTS_N_INSNS (13);
8367 *total = COSTS_N_INSNS (23);
8370 case PROCESSOR_ULTRASPARC3:
8371 if (GET_MODE (x) == SFmode)
8372 *total = COSTS_N_INSNS (17);
8374 *total = COSTS_N_INSNS (20);
8377 case PROCESSOR_SUPERSPARC:
8378 if (GET_MODE (x) == SFmode)
8379 *total = COSTS_N_INSNS (6);
8381 *total = COSTS_N_INSNS (9);
8384 case PROCESSOR_HYPERSPARC:
8385 case PROCESSOR_SPARCLITE86X:
8386 if (GET_MODE (x) == SFmode)
8387 *total = COSTS_N_INSNS (8);
8389 *total = COSTS_N_INSNS (12);
8393 *total = COSTS_N_INSNS (7);
8398 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8399 *total = (GET_MODE (x) == DImode
8400 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8401 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8402 *total = (GET_MODE (x) == DImode
8403 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8405 *total = COSTS_N_INSNS (25);
8409 /* Conditional moves. */
8412 case PROCESSOR_ULTRASPARC:
8413 *total = COSTS_N_INSNS (2);
8416 case PROCESSOR_ULTRASPARC3:
8417 if (FLOAT_MODE_P (GET_MODE (x)))
8418 *total = COSTS_N_INSNS (3);
8420 *total = COSTS_N_INSNS (2);
8424 *total = COSTS_N_INSNS (1);
8429 /* If outer-code is SIGN/ZERO extension we have to subtract
8430 out COSTS_N_INSNS (1) from whatever we return in determining
8434 case PROCESSOR_ULTRASPARC:
8435 if (outer_code == ZERO_EXTEND)
8436 *total = COSTS_N_INSNS (1);
8438 *total = COSTS_N_INSNS (2);
8441 case PROCESSOR_ULTRASPARC3:
8442 if (outer_code == ZERO_EXTEND)
8444 if (GET_MODE (x) == QImode
8445 || GET_MODE (x) == HImode
8446 || outer_code == SIGN_EXTEND)
8447 *total = COSTS_N_INSNS (2);
8449 *total = COSTS_N_INSNS (1);
8453 /* This handles sign extension (3 cycles)
8454 and everything else (2 cycles). */
8455 *total = COSTS_N_INSNS (2);
8459 case PROCESSOR_SUPERSPARC:
8460 if (FLOAT_MODE_P (GET_MODE (x))
8461 || outer_code == ZERO_EXTEND
8462 || outer_code == SIGN_EXTEND)
8463 *total = COSTS_N_INSNS (0);
8465 *total = COSTS_N_INSNS (1);
8468 case PROCESSOR_TSC701:
8469 if (outer_code == ZERO_EXTEND
8470 || outer_code == SIGN_EXTEND)
8471 *total = COSTS_N_INSNS (2);
8473 *total = COSTS_N_INSNS (3);
8476 case PROCESSOR_CYPRESS:
8477 if (outer_code == ZERO_EXTEND
8478 || outer_code == SIGN_EXTEND)
8479 *total = COSTS_N_INSNS (1);
8481 *total = COSTS_N_INSNS (2);
8484 case PROCESSOR_HYPERSPARC:
8485 case PROCESSOR_SPARCLITE86X:
8487 if (outer_code == ZERO_EXTEND
8488 || outer_code == SIGN_EXTEND)
8489 *total = COSTS_N_INSNS (0);
8491 *total = COSTS_N_INSNS (1);
8496 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8514 if (GET_MODE (x) == DImode
8515 && ((XINT (x, 3) == 0
8516 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8517 || (XINT (x, 3) == -1
8519 && XINT (x, 2) >= -0x1000)))
8530 /* If we are referencing a function make the SYMBOL_REF special. In
8531 the Embedded Medium/Anywhere code model, %g4 points to the data
8532 segment so we must not add it to function addresses. */
8535 sparc_encode_section_info (decl, first)
8537 int first ATTRIBUTE_UNUSED;
8539 if (TARGET_CM_EMBMEDANY && TREE_CODE (decl) == FUNCTION_DECL)
8540 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
8543 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8544 Used for C++ multiple inheritance. */
8547 sparc_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
8549 tree thunk_fndecl ATTRIBUTE_UNUSED;
8550 HOST_WIDE_INT delta;
8551 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
8554 rtx this, insn, funexp, delta_rtx, tmp;
8556 reload_completed = 1;
8558 current_function_uses_only_leaf_regs = 1;
8560 emit_note (NULL, NOTE_INSN_PROLOGUE_END);
8562 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8563 returns a structure, the structure return pointer is there instead. */
8564 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
8565 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
8567 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
8569 /* Add DELTA. When possible use a plain add, otherwise load it into
8570 a register first. */
8571 delta_rtx = GEN_INT (delta);
8572 if (!SPARC_SIMM13_P (delta))
8574 rtx scratch = gen_rtx_REG (Pmode, 1);
8576 sparc_emit_set_const64 (scratch, delta_rtx);
8578 sparc_emit_set_const32 (scratch, delta_rtx);
8579 delta_rtx = scratch;
8582 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
8583 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
8585 /* Generate a tail call to the target function. */
8586 if (! TREE_USED (function))
8588 assemble_external (function);
8589 TREE_USED (function) = 1;
8591 funexp = XEXP (DECL_RTL (function), 0);
8592 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8593 insn = emit_call_insn (gen_sibcall (funexp));
8594 SIBLING_CALL_P (insn) = 1;
8597 /* Run just enough of rest_of_compilation to get the insns emitted.
8598 There's not really enough bulk here to make other passes such as
8599 instruction scheduling worth while. Note that use_thunk calls
8600 assemble_start_function and assemble_end_function. */
8601 insn = get_insns ();
8602 shorten_branches (insn);
8603 final_start_function (insn, file, 1);
8604 final (insn, file, 1, 0);
8605 final_end_function ();
8607 reload_completed = 0;
8611 #include "gt-sparc.h"