1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
44 /* 1 if the caller has placed an "unimp" insn immediately after the call.
45 This is used in v8 code when calling a function that returns a structure.
46 v9 doesn't have this. Be careful to have this test be the same as that
49 #define SKIP_CALLERS_UNIMP_P \
50 (!TARGET_ARCH64 && current_function_returns_struct \
51 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
52 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
55 /* Global variables for machine-dependent things. */
57 /* Size of frame. Need to know this to emit return insns from leaf procedures.
58 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
59 reload pass. This is important as the value is later used in insn
60 scheduling (to see what can go in a delay slot).
61 APPARENT_FSIZE is the size of the stack less the register save area and less
62 the outgoing argument area. It is used when saving call preserved regs. */
63 static int apparent_fsize;
64 static int actual_fsize;
66 /* Number of live general or floating point registers needed to be saved
67 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
68 static int num_gfregs;
70 /* Save the operands last given to a compare for use when we
71 generate a scc or bcc insn. */
73 rtx sparc_compare_op0, sparc_compare_op1;
75 /* We may need an epilogue if we spill too many registers.
76 If this is non-zero, then we branch here for the epilogue. */
77 static rtx leaf_label;
81 /* Vector to say how input registers are mapped to output
82 registers. FRAME_POINTER_REGNUM cannot be remapped by
83 this function to eliminate it. You must use -fomit-frame-pointer
85 char leaf_reg_remap[] =
86 { 0, 1, 2, 3, 4, 5, 6, 7,
87 -1, -1, -1, -1, -1, -1, 14, -1,
88 -1, -1, -1, -1, -1, -1, -1, -1,
89 8, 9, 10, 11, 12, 13, -1, 15,
91 32, 33, 34, 35, 36, 37, 38, 39,
92 40, 41, 42, 43, 44, 45, 46, 47,
93 48, 49, 50, 51, 52, 53, 54, 55,
94 56, 57, 58, 59, 60, 61, 62, 63,
95 64, 65, 66, 67, 68, 69, 70, 71,
96 72, 73, 74, 75, 76, 77, 78, 79,
97 80, 81, 82, 83, 84, 85, 86, 87,
98 88, 89, 90, 91, 92, 93, 94, 95,
101 /* Vector, indexed by hard register number, which contains 1
102 for a register that is allowable in a candidate for leaf
103 function treatment. */
104 char sparc_leaf_regs[] =
105 { 1, 1, 1, 1, 1, 1, 1, 1,
106 0, 0, 0, 0, 0, 0, 1, 0,
107 0, 0, 0, 0, 0, 0, 0, 0,
108 1, 1, 1, 1, 1, 1, 0, 1,
109 1, 1, 1, 1, 1, 1, 1, 1,
110 1, 1, 1, 1, 1, 1, 1, 1,
111 1, 1, 1, 1, 1, 1, 1, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
121 /* Name of where we pretend to think the frame pointer points.
122 Normally, this is "%fp", but if we are in a leaf procedure,
123 this is "%sp+something". We record "something" separately as it may be
124 too big for reg+constant addressing. */
126 static const char *frame_base_name;
127 static int frame_base_offset;
129 static void sparc_init_modes PARAMS ((void));
130 static int save_regs PARAMS ((FILE *, int, int, const char *,
132 static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int));
133 static void build_big_number PARAMS ((FILE *, int, const char *));
134 static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *,
135 enum machine_mode, tree, int, int,
138 static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
139 static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
140 static int ultrasparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
142 static void sparc_output_addr_vec PARAMS ((rtx));
143 static void sparc_output_addr_diff_vec PARAMS ((rtx));
144 static void sparc_output_deferred_case_vectors PARAMS ((void));
145 static void sparc_add_gc_roots PARAMS ((void));
146 static void mark_ultrasparc_pipeline_state PARAMS ((void *));
147 static int check_return_regs PARAMS ((rtx));
148 static int epilogue_renumber PARAMS ((rtx *, int));
149 static int ultra_cmove_results_ready_p PARAMS ((rtx));
150 static int ultra_fpmode_conflict_exists PARAMS ((enum machine_mode));
151 static rtx *ultra_find_type PARAMS ((int, rtx *, int));
152 static void ultra_build_types_avail PARAMS ((rtx *, int));
153 static void ultra_flush_pipeline PARAMS ((void));
154 static void ultra_rescan_pipeline_state PARAMS ((rtx *, int));
155 static int set_extends PARAMS ((rtx));
156 static void output_restore_regs PARAMS ((FILE *, int));
158 /* Option handling. */
160 /* Code model option as passed by user. */
161 const char *sparc_cmodel_string;
163 enum cmodel sparc_cmodel;
165 char sparc_hard_reg_printed[8];
167 struct sparc_cpu_select sparc_select[] =
169 /* switch name, tune arch */
170 { (char *)0, "default", 1, 1 },
171 { (char *)0, "-mcpu=", 1, 1 },
172 { (char *)0, "-mtune=", 1, 0 },
176 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
177 enum processor_type sparc_cpu;
179 /* Validate and override various options, and do some machine dependent
183 sparc_override_options ()
185 static struct code_model {
190 { "medlow", CM_MEDLOW },
191 { "medmid", CM_MEDMID },
192 { "medany", CM_MEDANY },
193 { "embmedany", CM_EMBMEDANY },
196 struct code_model *cmodel;
197 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
198 static struct cpu_default {
202 /* There must be one entry here for each TARGET_CPU value. */
203 { TARGET_CPU_sparc, "cypress" },
204 { TARGET_CPU_sparclet, "tsc701" },
205 { TARGET_CPU_sparclite, "f930" },
206 { TARGET_CPU_v8, "v8" },
207 { TARGET_CPU_hypersparc, "hypersparc" },
208 { TARGET_CPU_sparclite86x, "sparclite86x" },
209 { TARGET_CPU_supersparc, "supersparc" },
210 { TARGET_CPU_v9, "v9" },
211 { TARGET_CPU_ultrasparc, "ultrasparc" },
214 struct cpu_default *def;
215 /* Table of values for -m{cpu,tune}=. */
216 static struct cpu_table {
218 enum processor_type processor;
222 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
223 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
224 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
225 /* TI TMS390Z55 supersparc */
226 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
227 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
228 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
229 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
230 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
231 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
232 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
233 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
235 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
237 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
238 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
239 /* TI ultrasparc I, II, IIi */
240 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
241 /* Although insns using %y are deprecated, it is a clear win on current
243 |MASK_DEPRECATED_V8_INSNS},
246 struct cpu_table *cpu;
247 struct sparc_cpu_select *sel;
250 #ifndef SPARC_BI_ARCH
251 /* Check for unsupported architecture size. */
252 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
253 error ("%s is not supported by this configuration",
254 DEFAULT_ARCH32_P ? "-m64" : "-m32");
257 /* We force all 64bit archs to use 128 bit long double */
258 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
260 error ("-mlong-double-64 not allowed with -m64");
261 target_flags |= MASK_LONG_DOUBLE_128;
264 /* Code model selection. */
265 sparc_cmodel = SPARC_DEFAULT_CMODEL;
269 sparc_cmodel = CM_32;
272 if (sparc_cmodel_string != NULL)
276 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
277 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
279 if (cmodel->name == NULL)
280 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
282 sparc_cmodel = cmodel->value;
285 error ("-mcmodel= is not supported on 32 bit systems");
288 fpu = TARGET_FPU; /* save current -mfpu status */
290 /* Set the default CPU. */
291 for (def = &cpu_default[0]; def->name; ++def)
292 if (def->cpu == TARGET_CPU_DEFAULT)
296 sparc_select[0].string = def->name;
298 for (sel = &sparc_select[0]; sel->name; ++sel)
302 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
303 if (! strcmp (sel->string, cpu->name))
306 sparc_cpu = cpu->processor;
310 target_flags &= ~cpu->disable;
311 target_flags |= cpu->enable;
317 error ("bad value (%s) for %s switch", sel->string, sel->name);
321 /* If -mfpu or -mno-fpu was explicitly used, don't override with
322 the processor default. Clear MASK_FPU_SET to avoid confusing
323 the reverse mapping from switch values to names. */
326 target_flags = (target_flags & ~MASK_FPU) | fpu;
327 target_flags &= ~MASK_FPU_SET;
330 /* Don't allow -mvis if FPU is disabled. */
332 target_flags &= ~MASK_VIS;
334 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
336 -m64 also implies v9. */
337 if (TARGET_VIS || TARGET_ARCH64)
338 target_flags |= MASK_V9;
340 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
341 if (TARGET_V9 && TARGET_ARCH32)
342 target_flags |= MASK_DEPRECATED_V8_INSNS;
344 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
345 if (! TARGET_V9 || TARGET_ARCH64)
346 target_flags &= ~MASK_V8PLUS;
348 /* Don't use stack biasing in 32 bit mode. */
350 target_flags &= ~MASK_STACK_BIAS;
352 /* Supply a default value for align_functions. */
353 if (align_functions == 0 && sparc_cpu == PROCESSOR_ULTRASPARC)
354 align_functions = 32;
356 /* Validate PCC_STRUCT_RETURN. */
357 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
358 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
360 /* Do various machine dependent initializations. */
363 if ((profile_flag || profile_block_flag)
364 && sparc_cmodel != CM_32 && sparc_cmodel != CM_MEDLOW)
366 error ("profiling does not support code models other than medlow");
369 /* Register global variables with the garbage collector. */
370 sparc_add_gc_roots ();
373 /* Miscellaneous utilities. */
375 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
376 or branch on register contents instructions. */
382 return (code == EQ || code == NE || code == GE || code == LT
383 || code == LE || code == GT);
387 /* Operand constraints. */
389 /* Return non-zero only if OP is a register of mode MODE,
393 reg_or_0_operand (op, mode)
395 enum machine_mode mode;
397 if (register_operand (op, mode))
399 if (op == const0_rtx)
401 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
402 && CONST_DOUBLE_HIGH (op) == 0
403 && CONST_DOUBLE_LOW (op) == 0)
405 if (fp_zero_operand (op, mode))
410 /* Nonzero if OP is a floating point value with value 0.0. */
413 fp_zero_operand (op, mode)
415 enum machine_mode mode;
417 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
419 return op == CONST0_RTX (mode);
422 /* Nonzero if OP is a floating point constant which can
423 be loaded into an integer register using a single
424 sethi instruction. */
430 if (GET_CODE (op) == CONST_DOUBLE)
435 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
436 if (REAL_VALUES_EQUAL (r, dconst0) &&
437 ! REAL_VALUE_MINUS_ZERO (r))
439 REAL_VALUE_TO_TARGET_SINGLE (r, i);
440 if (SPARC_SETHI_P (i))
447 /* Nonzero if OP is a floating point constant which can
448 be loaded into an integer register using a single
455 if (GET_CODE (op) == CONST_DOUBLE)
460 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
461 if (REAL_VALUES_EQUAL (r, dconst0) &&
462 ! REAL_VALUE_MINUS_ZERO (r))
464 REAL_VALUE_TO_TARGET_SINGLE (r, i);
465 if (SPARC_SIMM13_P (i))
472 /* Nonzero if OP is a floating point constant which can
473 be loaded into an integer register using a high/losum
474 instruction sequence. */
480 /* The constraints calling this should only be in
481 SFmode move insns, so any constant which cannot
482 be moved using a single insn will do. */
483 if (GET_CODE (op) == CONST_DOUBLE)
488 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
489 if (REAL_VALUES_EQUAL (r, dconst0) &&
490 ! REAL_VALUE_MINUS_ZERO (r))
492 REAL_VALUE_TO_TARGET_SINGLE (r, i);
493 if (! SPARC_SETHI_P (i)
494 && ! SPARC_SIMM13_P (i))
501 /* Nonzero if OP is an integer register. */
504 intreg_operand (op, mode)
506 enum machine_mode mode ATTRIBUTE_UNUSED;
508 return (register_operand (op, SImode)
509 || (TARGET_ARCH64 && register_operand (op, DImode)));
512 /* Nonzero if OP is a floating point condition code register. */
515 fcc_reg_operand (op, mode)
517 enum machine_mode mode;
519 /* This can happen when recog is called from combine. Op may be a MEM.
520 Fail instead of calling abort in this case. */
521 if (GET_CODE (op) != REG)
524 if (mode != VOIDmode && mode != GET_MODE (op))
527 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
530 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
531 if (reg_renumber == 0)
532 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
533 return REGNO_OK_FOR_CCFP_P (REGNO (op));
535 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
539 /* Nonzero if OP is an integer or floating point condition code register. */
542 icc_or_fcc_reg_operand (op, mode)
544 enum machine_mode mode;
546 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
548 if (mode != VOIDmode && mode != GET_MODE (op))
551 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
556 return fcc_reg_operand (op, mode);
559 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
561 restore_operand (op, mode)
563 enum machine_mode mode;
565 return (GET_CODE (op) == REG && GET_MODE (op) == mode
566 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
569 /* Call insn on SPARC can take a PC-relative constant address, or any regular
573 call_operand (op, mode)
575 enum machine_mode mode;
577 if (GET_CODE (op) != MEM)
580 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
584 call_operand_address (op, mode)
586 enum machine_mode mode;
588 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
591 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
592 reference and a constant. */
595 symbolic_operand (op, mode)
597 enum machine_mode mode;
599 enum machine_mode omode = GET_MODE (op);
601 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
604 switch (GET_CODE (op))
612 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
613 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
614 && GET_CODE (XEXP (op, 1)) == CONST_INT);
621 /* Return truth value of statement that OP is a symbolic memory
622 operand of mode MODE. */
625 symbolic_memory_operand (op, mode)
627 enum machine_mode mode ATTRIBUTE_UNUSED;
629 if (GET_CODE (op) == SUBREG)
630 op = SUBREG_REG (op);
631 if (GET_CODE (op) != MEM)
634 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
635 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
638 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
641 label_ref_operand (op, mode)
643 enum machine_mode mode;
645 if (GET_CODE (op) != LABEL_REF)
647 if (GET_MODE (op) != mode)
652 /* Return 1 if the operand is an argument used in generating pic references
653 in either the medium/low or medium/anywhere code models of sparc64. */
656 sp64_medium_pic_operand (op, mode)
658 enum machine_mode mode ATTRIBUTE_UNUSED;
660 /* Check for (const (minus (symbol_ref:GOT)
661 (const (minus (label) (pc))))). */
662 if (GET_CODE (op) != CONST)
665 if (GET_CODE (op) != MINUS)
667 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
669 /* ??? Ensure symbol is GOT. */
670 if (GET_CODE (XEXP (op, 1)) != CONST)
672 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
677 /* Return 1 if the operand is a data segment reference. This includes
678 the readonly data segment, or in other words anything but the text segment.
679 This is needed in the medium/anywhere code model on v9. These values
680 are accessed with EMBMEDANY_BASE_REG. */
683 data_segment_operand (op, mode)
685 enum machine_mode mode ATTRIBUTE_UNUSED;
687 switch (GET_CODE (op))
690 return ! SYMBOL_REF_FLAG (op);
692 /* Assume canonical format of symbol + constant.
695 return data_segment_operand (XEXP (op, 0), VOIDmode);
701 /* Return 1 if the operand is a text segment reference.
702 This is needed in the medium/anywhere code model on v9. */
705 text_segment_operand (op, mode)
707 enum machine_mode mode ATTRIBUTE_UNUSED;
709 switch (GET_CODE (op))
714 return SYMBOL_REF_FLAG (op);
716 /* Assume canonical format of symbol + constant.
719 return text_segment_operand (XEXP (op, 0), VOIDmode);
725 /* Return 1 if the operand is either a register or a memory operand that is
729 reg_or_nonsymb_mem_operand (op, mode)
731 enum machine_mode mode;
733 if (register_operand (op, mode))
736 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
743 splittable_symbolic_memory_operand (op, mode)
745 enum machine_mode mode ATTRIBUTE_UNUSED;
747 if (GET_CODE (op) != MEM)
749 if (! symbolic_operand (XEXP (op, 0), Pmode))
755 splittable_immediate_memory_operand (op, mode)
757 enum machine_mode mode ATTRIBUTE_UNUSED;
759 if (GET_CODE (op) != MEM)
761 if (! immediate_operand (XEXP (op, 0), Pmode))
766 /* Return truth value of whether OP is EQ or NE. */
771 enum machine_mode mode ATTRIBUTE_UNUSED;
773 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
776 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
777 or LTU for non-floating-point. We handle those specially. */
780 normal_comp_operator (op, mode)
782 enum machine_mode mode ATTRIBUTE_UNUSED;
784 enum rtx_code code = GET_CODE (op);
786 if (GET_RTX_CLASS (code) != '<')
789 if (GET_MODE (XEXP (op, 0)) == CCFPmode
790 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
793 return (code != NE && code != EQ && code != GEU && code != LTU);
796 /* Return 1 if this is a comparison operator. This allows the use of
797 MATCH_OPERATOR to recognize all the branch insns. */
800 noov_compare_op (op, mode)
802 enum machine_mode mode ATTRIBUTE_UNUSED;
804 enum rtx_code code = GET_CODE (op);
806 if (GET_RTX_CLASS (code) != '<')
809 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
810 /* These are the only branches which work with CC_NOOVmode. */
811 return (code == EQ || code == NE || code == GE || code == LT);
815 /* Nonzero if OP is a comparison operator suitable for use in v9
816 conditional move or branch on register contents instructions. */
819 v9_regcmp_op (op, mode)
821 enum machine_mode mode ATTRIBUTE_UNUSED;
823 enum rtx_code code = GET_CODE (op);
825 if (GET_RTX_CLASS (code) != '<')
828 return v9_regcmp_p (code);
831 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
836 enum machine_mode mode ATTRIBUTE_UNUSED;
838 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
841 /* Return nonzero if OP is an operator of mode MODE which can set
842 the condition codes explicitly. We do not include PLUS and MINUS
843 because these require CC_NOOVmode, which we handle explicitly. */
846 cc_arithop (op, mode)
848 enum machine_mode mode ATTRIBUTE_UNUSED;
850 if (GET_CODE (op) == AND
851 || GET_CODE (op) == IOR
852 || GET_CODE (op) == XOR)
858 /* Return nonzero if OP is an operator of mode MODE which can bitwise
859 complement its second operand and set the condition codes explicitly. */
862 cc_arithopn (op, mode)
864 enum machine_mode mode ATTRIBUTE_UNUSED;
866 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
867 and (xor ... (not ...)) to (not (xor ...)). */
868 return (GET_CODE (op) == AND
869 || GET_CODE (op) == IOR);
872 /* Return true if OP is a register, or is a CONST_INT that can fit in a
873 signed 13 bit immediate field. This is an acceptable SImode operand for
874 most 3 address instructions. */
877 arith_operand (op, mode)
879 enum machine_mode mode;
882 if (register_operand (op, mode))
884 if (GET_CODE (op) != CONST_INT)
886 val = INTVAL (op) & 0xffffffff;
887 return SPARC_SIMM13_P (val);
890 /* Return true if OP is a constant 4096 */
893 arith_4096_operand (op, mode)
895 enum machine_mode mode ATTRIBUTE_UNUSED;
898 if (GET_CODE (op) != CONST_INT)
900 val = INTVAL (op) & 0xffffffff;
904 /* Return true if OP is suitable as second operand for add/sub */
907 arith_add_operand (op, mode)
909 enum machine_mode mode;
911 return arith_operand (op, mode) || arith_4096_operand (op, mode);
914 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
915 immediate field of OR and XOR instructions. Used for 64-bit
916 constant formation patterns. */
918 const64_operand (op, mode)
920 enum machine_mode mode ATTRIBUTE_UNUSED;
922 return ((GET_CODE (op) == CONST_INT
923 && SPARC_SIMM13_P (INTVAL (op)))
924 #if HOST_BITS_PER_WIDE_INT != 64
925 || (GET_CODE (op) == CONST_DOUBLE
926 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
927 && (CONST_DOUBLE_HIGH (op) ==
928 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
929 (HOST_WIDE_INT)0xffffffff : 0)))
934 /* The same, but only for sethi instructions. */
936 const64_high_operand (op, mode)
938 enum machine_mode mode ATTRIBUTE_UNUSED;
940 return ((GET_CODE (op) == CONST_INT
941 && (INTVAL (op) & 0xfffffc00) != 0
942 && SPARC_SETHI_P (INTVAL (op))
943 #if HOST_BITS_PER_WIDE_INT != 64
944 /* Must be positive on non-64bit host else the
945 optimizer is fooled into thinking that sethi
946 sign extends, even though it does not. */
950 || (GET_CODE (op) == CONST_DOUBLE
951 && CONST_DOUBLE_HIGH (op) == 0
952 && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
953 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
956 /* Return true if OP is a register, or is a CONST_INT that can fit in a
957 signed 11 bit immediate field. This is an acceptable SImode operand for
958 the movcc instructions. */
961 arith11_operand (op, mode)
963 enum machine_mode mode;
965 return (register_operand (op, mode)
966 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
969 /* Return true if OP is a register, or is a CONST_INT that can fit in a
970 signed 10 bit immediate field. This is an acceptable SImode operand for
971 the movrcc instructions. */
974 arith10_operand (op, mode)
976 enum machine_mode mode;
978 return (register_operand (op, mode)
979 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
982 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
983 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
985 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
986 can fit in a 13 bit immediate field. This is an acceptable DImode operand
987 for most 3 address instructions. */
990 arith_double_operand (op, mode)
992 enum machine_mode mode;
994 return (register_operand (op, mode)
995 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
997 && GET_CODE (op) == CONST_DOUBLE
998 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
999 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1001 && GET_CODE (op) == CONST_DOUBLE
1002 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1003 && ((CONST_DOUBLE_HIGH (op) == -1
1004 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1005 || (CONST_DOUBLE_HIGH (op) == 0
1006 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1009 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1012 arith_double_4096_operand (op, mode)
1014 enum machine_mode mode ATTRIBUTE_UNUSED;
1016 return (TARGET_ARCH64 &&
1017 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1018 (GET_CODE (op) == CONST_DOUBLE &&
1019 CONST_DOUBLE_LOW (op) == 4096 &&
1020 CONST_DOUBLE_HIGH (op) == 0)));
1023 /* Return true if OP is suitable as second operand for add/sub in DImode */
1026 arith_double_add_operand (op, mode)
1028 enum machine_mode mode;
1030 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1033 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1034 can fit in an 11 bit immediate field. This is an acceptable DImode
1035 operand for the movcc instructions. */
1036 /* ??? Replace with arith11_operand? */
1039 arith11_double_operand (op, mode)
1041 enum machine_mode mode;
1043 return (register_operand (op, mode)
1044 || (GET_CODE (op) == CONST_DOUBLE
1045 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1046 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1047 && ((CONST_DOUBLE_HIGH (op) == -1
1048 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1049 || (CONST_DOUBLE_HIGH (op) == 0
1050 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1051 || (GET_CODE (op) == CONST_INT
1052 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1053 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1056 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1057 can fit in an 10 bit immediate field. This is an acceptable DImode
1058 operand for the movrcc instructions. */
1059 /* ??? Replace with arith10_operand? */
1062 arith10_double_operand (op, mode)
1064 enum machine_mode mode;
1066 return (register_operand (op, mode)
1067 || (GET_CODE (op) == CONST_DOUBLE
1068 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1069 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1070 && ((CONST_DOUBLE_HIGH (op) == -1
1071 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1072 || (CONST_DOUBLE_HIGH (op) == 0
1073 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1074 || (GET_CODE (op) == CONST_INT
1075 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1076 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1079 /* Return truth value of whether OP is a integer which fits the
1080 range constraining immediate operands in most three-address insns,
1081 which have a 13 bit immediate field. */
1084 small_int (op, mode)
1086 enum machine_mode mode ATTRIBUTE_UNUSED;
1088 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1092 small_int_or_double (op, mode)
1094 enum machine_mode mode ATTRIBUTE_UNUSED;
1096 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1097 || (GET_CODE (op) == CONST_DOUBLE
1098 && CONST_DOUBLE_HIGH (op) == 0
1099 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1102 /* Recognize operand values for the umul instruction. That instruction sign
1103 extends immediate values just like all other sparc instructions, but
1104 interprets the extended result as an unsigned number. */
1107 uns_small_int (op, mode)
1109 enum machine_mode mode ATTRIBUTE_UNUSED;
1111 #if HOST_BITS_PER_WIDE_INT > 32
1112 /* All allowed constants will fit a CONST_INT. */
1113 return (GET_CODE (op) == CONST_INT
1114 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1115 || (INTVAL (op) >= 0xFFFFF000
1116 && INTVAL (op) < 0x100000000)));
1118 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1119 || (GET_CODE (op) == CONST_DOUBLE
1120 && CONST_DOUBLE_HIGH (op) == 0
1121 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1126 uns_arith_operand (op, mode)
1128 enum machine_mode mode;
1130 return register_operand (op, mode) || uns_small_int (op, mode);
1133 /* Return truth value of statement that OP is a call-clobbered register. */
1135 clobbered_register (op, mode)
1137 enum machine_mode mode ATTRIBUTE_UNUSED;
1139 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1142 /* Return 1 if OP is a valid operand for the source of a move insn. */
1145 input_operand (op, mode)
1147 enum machine_mode mode;
1149 /* If both modes are non-void they must be the same. */
1150 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1153 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1154 if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX)
1157 /* Allow any one instruction integer constant, and all CONST_INT
1158 variants when we are working in DImode and !arch64. */
1159 if (GET_MODE_CLASS (mode) == MODE_INT
1160 && ((GET_CODE (op) == CONST_INT
1161 && ((SPARC_SETHI_P (INTVAL (op))
1163 || (INTVAL (op) >= 0)
1167 || SPARC_SIMM13_P (INTVAL (op))
1169 && ! TARGET_ARCH64)))
1171 && GET_CODE (op) == CONST_DOUBLE
1172 && ((CONST_DOUBLE_HIGH (op) == 0
1173 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1175 #if HOST_BITS_PER_WIDE_INT == 64
1176 (CONST_DOUBLE_HIGH (op) == 0
1177 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1179 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1180 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1181 && CONST_DOUBLE_HIGH (op) == 0)
1182 || (CONST_DOUBLE_HIGH (op) == -1
1183 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1188 /* If !arch64 and this is a DImode const, allow it so that
1189 the splits can be generated. */
1192 && GET_CODE (op) == CONST_DOUBLE)
1195 if (register_operand (op, mode))
1198 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1199 && GET_CODE (op) == CONST_DOUBLE)
1202 /* If this is a SUBREG, look inside so that we handle
1203 paradoxical ones. */
1204 if (GET_CODE (op) == SUBREG)
1205 op = SUBREG_REG (op);
1207 /* Check for valid MEM forms. */
1208 if (GET_CODE (op) == MEM)
1210 rtx inside = XEXP (op, 0);
1212 if (GET_CODE (inside) == LO_SUM)
1214 /* We can't allow these because all of the splits
1215 (eventually as they trickle down into DFmode
1216 splits) require offsettable memory references. */
1218 && GET_MODE (op) == TFmode)
1221 return (register_operand (XEXP (inside, 0), Pmode)
1222 && CONSTANT_P (XEXP (inside, 1)));
1224 return memory_address_p (mode, inside);
1231 /* We know it can't be done in one insn when we get here,
1232 the movsi expander guarentees this. */
1234 sparc_emit_set_const32 (op0, op1)
1238 enum machine_mode mode = GET_MODE (op0);
1241 if (GET_CODE (op1) == CONST_INT)
1243 HOST_WIDE_INT value = INTVAL (op1);
1245 if (SPARC_SETHI_P (value)
1246 || SPARC_SIMM13_P (value))
1250 /* Full 2-insn decomposition is needed. */
1251 if (reload_in_progress || reload_completed)
1254 temp = gen_reg_rtx (mode);
1256 if (GET_CODE (op1) == CONST_INT)
1258 /* Emit them as real moves instead of a HIGH/LO_SUM,
1259 this way CSE can see everything and reuse intermediate
1260 values if it wants. */
1262 && HOST_BITS_PER_WIDE_INT != 64
1263 && (INTVAL (op1) & 0x80000000) != 0)
1265 emit_insn (gen_rtx_SET (VOIDmode,
1267 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx,
1268 INTVAL (op1) & 0xfffffc00, 0)));
1272 emit_insn (gen_rtx_SET (VOIDmode,
1274 GEN_INT (INTVAL (op1) & 0xfffffc00)));
1276 emit_insn (gen_rtx_SET (VOIDmode,
1280 GEN_INT (INTVAL (op1) & 0x3ff))));
1284 /* A symbol, emit in the traditional way. */
1285 emit_insn (gen_rtx_SET (VOIDmode,
1289 emit_insn (gen_rtx_SET (VOIDmode,
1291 gen_rtx_LO_SUM (mode,
1299 /* Sparc-v9 code-model support. */
1301 sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1306 switch (sparc_cmodel)
1309 /* The range spanned by all instructions in the object is less
1310 than 2^31 bytes (2GB) and the distance from any instruction
1311 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1312 than 2^31 bytes (2GB).
1314 The executable must be in the low 4TB of the virtual address
1317 sethi %hi(symbol), %temp
1318 or %temp, %lo(symbol), %reg */
1319 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1320 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1324 /* The range spanned by all instructions in the object is less
1325 than 2^31 bytes (2GB) and the distance from any instruction
1326 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1327 than 2^31 bytes (2GB).
1329 The executable must be in the low 16TB of the virtual address
1332 sethi %h44(symbol), %temp1
1333 or %temp1, %m44(symbol), %temp2
1334 sllx %temp2, 12, %temp3
1335 or %temp3, %l44(symbol), %reg */
1336 emit_insn (gen_seth44 (op0, op1));
1337 emit_insn (gen_setm44 (op0, op0, op1));
1338 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1339 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1340 emit_insn (gen_setl44 (op0, temp1, op1));
1344 /* The range spanned by all instructions in the object is less
1345 than 2^31 bytes (2GB) and the distance from any instruction
1346 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1347 than 2^31 bytes (2GB).
1349 The executable can be placed anywhere in the virtual address
1352 sethi %hh(symbol), %temp1
1353 sethi %lm(symbol), %temp2
1354 or %temp1, %hm(symbol), %temp3
1355 or %temp2, %lo(symbol), %temp4
1356 sllx %temp3, 32, %temp5
1357 or %temp4, %temp5, %reg */
1359 /* Getting this right wrt. reloading is really tricky.
1360 We _MUST_ have a separate temporary at this point,
1361 if we don't barf immediately instead of generating
1366 emit_insn (gen_sethh (op0, op1));
1367 emit_insn (gen_setlm (temp1, op1));
1368 emit_insn (gen_sethm (op0, op0, op1));
1369 emit_insn (gen_rtx_SET (VOIDmode, op0,
1370 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1371 emit_insn (gen_rtx_SET (VOIDmode, op0,
1372 gen_rtx_PLUS (DImode, op0, temp1)));
1373 emit_insn (gen_setlo (op0, op0, op1));
1377 /* Old old old backwards compatibility kruft here.
1378 Essentially it is MEDLOW with a fixed 64-bit
1379 virtual base added to all data segment addresses.
1380 Text-segment stuff is computed like MEDANY, we can't
1381 reuse the code above because the relocation knobs
1384 Data segment: sethi %hi(symbol), %temp1
1385 or %temp1, %lo(symbol), %temp2
1386 add %temp2, EMBMEDANY_BASE_REG, %reg
1388 Text segment: sethi %uhi(symbol), %temp1
1389 sethi %hi(symbol), %temp2
1390 or %temp1, %ulo(symbol), %temp3
1391 or %temp2, %lo(symbol), %temp4
1392 sllx %temp3, 32, %temp5
1393 or %temp4, %temp5, %reg */
1394 if (data_segment_operand (op1, GET_MODE (op1)))
1396 emit_insn (gen_embmedany_sethi (temp1, op1));
1397 emit_insn (gen_embmedany_brsum (op0, temp1));
1398 emit_insn (gen_embmedany_losum (op0, op0, op1));
1402 /* Getting this right wrt. reloading is really tricky.
1403 We _MUST_ have a separate temporary at this point,
1404 so we barf immediately instead of generating
1409 emit_insn (gen_embmedany_textuhi (op0, op1));
1410 emit_insn (gen_embmedany_texthi (temp1, op1));
1411 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1412 emit_insn (gen_rtx_SET (VOIDmode, op0,
1413 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1414 emit_insn (gen_rtx_SET (VOIDmode, op0,
1415 gen_rtx_PLUS (DImode, op0, temp1)));
1416 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1425 /* These avoid problems when cross compiling. If we do not
1426 go through all this hair then the optimizer will see
1427 invalid REG_EQUAL notes or in some cases none at all. */
1428 static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT));
1429 static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT));
1430 static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT));
1431 static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
1433 #if HOST_BITS_PER_WIDE_INT == 64
1434 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
1435 #define GEN_INT64(__x) GEN_INT (__x)
1437 #define GEN_HIGHINT64(__x) \
1438 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1439 (__x) & 0xfffffc00, 0)
1440 #define GEN_INT64(__x) \
1441 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1442 (__x) & 0xffffffff, \
1443 ((__x) & 0x80000000 \
1447 /* The optimizer is not to assume anything about exactly
1448 which bits are set for a HIGH, they are unspecified.
1449 Unfortunately this leads to many missed optimizations
1450 during CSE. We mask out the non-HIGH bits, and matches
1451 a plain movdi, to alleviate this problem. */
1453 sparc_emit_set_safe_HIGH64 (dest, val)
1457 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1461 gen_safe_SET64 (dest, val)
1465 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1469 gen_safe_OR64 (src, val)
1473 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1477 gen_safe_XOR64 (src, val)
1481 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1484 /* Worker routines for 64-bit constant formation on arch64.
1485 One of the key things to be doing in these emissions is
1486 to create as many temp REGs as possible. This makes it
1487 possible for half-built constants to be used later when
1488 such values are similar to something required later on.
1489 Without doing this, the optimizer cannot see such
1492 static void sparc_emit_set_const64_quick1
1493 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int));
1496 sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1499 unsigned HOST_WIDE_INT low_bits;
1502 unsigned HOST_WIDE_INT high_bits;
1505 high_bits = (~low_bits) & 0xffffffff;
1507 high_bits = low_bits;
1509 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1512 emit_insn (gen_rtx_SET (VOIDmode, op0,
1513 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1517 /* If we are XOR'ing with -1, then we should emit a one's complement
1518 instead. This way the combiner will notice logical operations
1519 such as ANDN later on and substitute. */
1520 if ((low_bits & 0x3ff) == 0x3ff)
1522 emit_insn (gen_rtx_SET (VOIDmode, op0,
1523 gen_rtx_NOT (DImode, temp)));
1527 emit_insn (gen_rtx_SET (VOIDmode, op0,
1528 gen_safe_XOR64 (temp,
1529 (-0x400 | (low_bits & 0x3ff)))));
1534 static void sparc_emit_set_const64_quick2
1535 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT,
1536 unsigned HOST_WIDE_INT, int));
1539 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1542 unsigned HOST_WIDE_INT high_bits;
1543 unsigned HOST_WIDE_INT low_immediate;
1548 if ((high_bits & 0xfffffc00) != 0)
1550 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1551 if ((high_bits & ~0xfffffc00) != 0)
1552 emit_insn (gen_rtx_SET (VOIDmode, op0,
1553 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1559 emit_insn (gen_safe_SET64 (temp, high_bits));
1563 /* Now shift it up into place. */
1564 emit_insn (gen_rtx_SET (VOIDmode, op0,
1565 gen_rtx_ASHIFT (DImode, temp2,
1566 GEN_INT (shift_count))));
1568 /* If there is a low immediate part piece, finish up by
1569 putting that in as well. */
1570 if (low_immediate != 0)
1571 emit_insn (gen_rtx_SET (VOIDmode, op0,
1572 gen_safe_OR64 (op0, low_immediate)));
1575 static void sparc_emit_set_const64_longway
1576 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1578 /* Full 64-bit constant decomposition. Even though this is the
1579 'worst' case, we still optimize a few things away. */
1581 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1584 unsigned HOST_WIDE_INT high_bits;
1585 unsigned HOST_WIDE_INT low_bits;
1589 if (reload_in_progress || reload_completed)
1592 sub_temp = gen_reg_rtx (DImode);
1594 if ((high_bits & 0xfffffc00) != 0)
1596 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1597 if ((high_bits & ~0xfffffc00) != 0)
1598 emit_insn (gen_rtx_SET (VOIDmode,
1600 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1606 emit_insn (gen_safe_SET64 (temp, high_bits));
1610 if (!reload_in_progress && !reload_completed)
1612 rtx temp2 = gen_reg_rtx (DImode);
1613 rtx temp3 = gen_reg_rtx (DImode);
1614 rtx temp4 = gen_reg_rtx (DImode);
1616 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1617 gen_rtx_ASHIFT (DImode, sub_temp,
1620 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1621 if ((low_bits & ~0xfffffc00) != 0)
1623 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1624 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1625 emit_insn (gen_rtx_SET (VOIDmode, op0,
1626 gen_rtx_PLUS (DImode, temp4, temp3)));
1630 emit_insn (gen_rtx_SET (VOIDmode, op0,
1631 gen_rtx_PLUS (DImode, temp4, temp2)));
1636 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1637 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1638 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1641 /* We are in the middle of reload, so this is really
1642 painful. However we do still make an attempt to
1643 avoid emitting truly stupid code. */
1644 if (low1 != const0_rtx)
1646 emit_insn (gen_rtx_SET (VOIDmode, op0,
1647 gen_rtx_ASHIFT (DImode, sub_temp,
1648 GEN_INT (to_shift))));
1649 emit_insn (gen_rtx_SET (VOIDmode, op0,
1650 gen_rtx_IOR (DImode, op0, low1)));
1658 if (low2 != const0_rtx)
1660 emit_insn (gen_rtx_SET (VOIDmode, op0,
1661 gen_rtx_ASHIFT (DImode, sub_temp,
1662 GEN_INT (to_shift))));
1663 emit_insn (gen_rtx_SET (VOIDmode, op0,
1664 gen_rtx_IOR (DImode, op0, low2)));
1672 emit_insn (gen_rtx_SET (VOIDmode, op0,
1673 gen_rtx_ASHIFT (DImode, sub_temp,
1674 GEN_INT (to_shift))));
1675 if (low3 != const0_rtx)
1676 emit_insn (gen_rtx_SET (VOIDmode, op0,
1677 gen_rtx_IOR (DImode, op0, low3)));
1682 /* Analyze a 64-bit constant for certain properties. */
1683 static void analyze_64bit_constant
1684 PARAMS ((unsigned HOST_WIDE_INT,
1685 unsigned HOST_WIDE_INT,
1686 int *, int *, int *));
1689 analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
1690 unsigned HOST_WIDE_INT high_bits, low_bits;
1691 int *hbsp, *lbsp, *abbasp;
1693 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1696 lowest_bit_set = highest_bit_set = -1;
1700 if ((lowest_bit_set == -1)
1701 && ((low_bits >> i) & 1))
1703 if ((highest_bit_set == -1)
1704 && ((high_bits >> (32 - i - 1)) & 1))
1705 highest_bit_set = (64 - i - 1);
1708 && ((highest_bit_set == -1)
1709 || (lowest_bit_set == -1)));
1715 if ((lowest_bit_set == -1)
1716 && ((high_bits >> i) & 1))
1717 lowest_bit_set = i + 32;
1718 if ((highest_bit_set == -1)
1719 && ((low_bits >> (32 - i - 1)) & 1))
1720 highest_bit_set = 32 - i - 1;
1723 && ((highest_bit_set == -1)
1724 || (lowest_bit_set == -1)));
1726 /* If there are no bits set this should have gone out
1727 as one instruction! */
1728 if (lowest_bit_set == -1
1729 || highest_bit_set == -1)
1731 all_bits_between_are_set = 1;
1732 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1736 if ((low_bits & (1 << i)) != 0)
1741 if ((high_bits & (1 << (i - 32))) != 0)
1744 all_bits_between_are_set = 0;
1747 *hbsp = highest_bit_set;
1748 *lbsp = lowest_bit_set;
1749 *abbasp = all_bits_between_are_set;
1752 static int const64_is_2insns
1753 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1756 const64_is_2insns (high_bits, low_bits)
1757 unsigned HOST_WIDE_INT high_bits, low_bits;
1759 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1762 || high_bits == 0xffffffff)
1765 analyze_64bit_constant (high_bits, low_bits,
1766 &highest_bit_set, &lowest_bit_set,
1767 &all_bits_between_are_set);
1769 if ((highest_bit_set == 63
1770 || lowest_bit_set == 0)
1771 && all_bits_between_are_set != 0)
1774 if ((highest_bit_set - lowest_bit_set) < 21)
1780 static unsigned HOST_WIDE_INT create_simple_focus_bits
1781 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
1784 static unsigned HOST_WIDE_INT
1785 create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
1786 unsigned HOST_WIDE_INT high_bits, low_bits;
1787 int lowest_bit_set, shift;
1789 HOST_WIDE_INT hi, lo;
1791 if (lowest_bit_set < 32)
1793 lo = (low_bits >> lowest_bit_set) << shift;
1794 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1799 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1806 /* Here we are sure to be arch64 and this is an integer constant
1807 being loaded into a register. Emit the most efficient
1808 insn sequence possible. Detection of all the 1-insn cases
1809 has been done already. */
1811 sparc_emit_set_const64 (op0, op1)
1815 unsigned HOST_WIDE_INT high_bits, low_bits;
1816 int lowest_bit_set, highest_bit_set;
1817 int all_bits_between_are_set;
1820 /* Sanity check that we know what we are working with. */
1821 if (! TARGET_ARCH64)
1824 if (GET_CODE (op0) != SUBREG)
1826 if (GET_CODE (op0) != REG
1827 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1828 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1832 if (reload_in_progress || reload_completed)
1835 temp = gen_reg_rtx (DImode);
1837 if (GET_CODE (op1) != CONST_DOUBLE
1838 && GET_CODE (op1) != CONST_INT)
1840 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1844 if (GET_CODE (op1) == CONST_DOUBLE)
1846 #if HOST_BITS_PER_WIDE_INT == 64
1847 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1848 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1850 high_bits = CONST_DOUBLE_HIGH (op1);
1851 low_bits = CONST_DOUBLE_LOW (op1);
1856 #if HOST_BITS_PER_WIDE_INT == 64
1857 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1858 low_bits = (INTVAL (op1) & 0xffffffff);
1860 high_bits = ((INTVAL (op1) < 0) ?
1863 low_bits = INTVAL (op1);
1867 /* low_bits bits 0 --> 31
1868 high_bits bits 32 --> 63 */
1870 analyze_64bit_constant (high_bits, low_bits,
1871 &highest_bit_set, &lowest_bit_set,
1872 &all_bits_between_are_set);
1874 /* First try for a 2-insn sequence. */
1876 /* These situations are preferred because the optimizer can
1877 * do more things with them:
1879 * sllx %reg, shift, %reg
1881 * srlx %reg, shift, %reg
1882 * 3) mov some_small_const, %reg
1883 * sllx %reg, shift, %reg
1885 if (((highest_bit_set == 63
1886 || lowest_bit_set == 0)
1887 && all_bits_between_are_set != 0)
1888 || ((highest_bit_set - lowest_bit_set) < 12))
1890 HOST_WIDE_INT the_const = -1;
1891 int shift = lowest_bit_set;
1893 if ((highest_bit_set != 63
1894 && lowest_bit_set != 0)
1895 || all_bits_between_are_set == 0)
1898 create_simple_focus_bits (high_bits, low_bits,
1901 else if (lowest_bit_set == 0)
1902 shift = -(63 - highest_bit_set);
1904 if (! SPARC_SIMM13_P (the_const))
1907 emit_insn (gen_safe_SET64 (temp, the_const));
1909 emit_insn (gen_rtx_SET (VOIDmode,
1911 gen_rtx_ASHIFT (DImode,
1915 emit_insn (gen_rtx_SET (VOIDmode,
1917 gen_rtx_LSHIFTRT (DImode,
1919 GEN_INT (-shift))));
1925 /* Now a range of 22 or less bits set somewhere.
1926 * 1) sethi %hi(focus_bits), %reg
1927 * sllx %reg, shift, %reg
1928 * 2) sethi %hi(focus_bits), %reg
1929 * srlx %reg, shift, %reg
1931 if ((highest_bit_set - lowest_bit_set) < 21)
1933 unsigned HOST_WIDE_INT focus_bits =
1934 create_simple_focus_bits (high_bits, low_bits,
1935 lowest_bit_set, 10);
1937 if (! SPARC_SETHI_P (focus_bits))
1940 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
1942 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1943 if (lowest_bit_set < 10)
1944 emit_insn (gen_rtx_SET (VOIDmode,
1946 gen_rtx_LSHIFTRT (DImode, temp,
1947 GEN_INT (10 - lowest_bit_set))));
1948 else if (lowest_bit_set > 10)
1949 emit_insn (gen_rtx_SET (VOIDmode,
1951 gen_rtx_ASHIFT (DImode, temp,
1952 GEN_INT (lowest_bit_set - 10))));
1958 /* 1) sethi %hi(low_bits), %reg
1959 * or %reg, %lo(low_bits), %reg
1960 * 2) sethi %hi(~low_bits), %reg
1961 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1964 || high_bits == 0xffffffff)
1966 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1967 (high_bits == 0xffffffff));
1971 /* Now, try 3-insn sequences. */
1973 /* 1) sethi %hi(high_bits), %reg
1974 * or %reg, %lo(high_bits), %reg
1975 * sllx %reg, 32, %reg
1979 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
1983 /* We may be able to do something quick
1984 when the constant is negated, so try that. */
1985 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1986 (~low_bits) & 0xfffffc00))
1988 /* NOTE: The trailing bits get XOR'd so we need the
1989 non-negated bits, not the negated ones. */
1990 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
1992 if ((((~high_bits) & 0xffffffff) == 0
1993 && ((~low_bits) & 0x80000000) == 0)
1994 || (((~high_bits) & 0xffffffff) == 0xffffffff
1995 && ((~low_bits) & 0x80000000) != 0))
1997 int fast_int = (~low_bits & 0xffffffff);
1999 if ((SPARC_SETHI_P (fast_int)
2000 && (~high_bits & 0xffffffff) == 0)
2001 || SPARC_SIMM13_P (fast_int))
2002 emit_insn (gen_safe_SET64 (temp, fast_int));
2004 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2009 #if HOST_BITS_PER_WIDE_INT == 64
2010 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2011 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2013 negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx,
2014 (~low_bits) & 0xfffffc00,
2015 (~high_bits) & 0xffffffff);
2017 sparc_emit_set_const64 (temp, negated_const);
2020 /* If we are XOR'ing with -1, then we should emit a one's complement
2021 instead. This way the combiner will notice logical operations
2022 such as ANDN later on and substitute. */
2023 if (trailing_bits == 0x3ff)
2025 emit_insn (gen_rtx_SET (VOIDmode, op0,
2026 gen_rtx_NOT (DImode, temp)));
2030 emit_insn (gen_rtx_SET (VOIDmode,
2032 gen_safe_XOR64 (temp,
2033 (-0x400 | trailing_bits))));
2038 /* 1) sethi %hi(xxx), %reg
2039 * or %reg, %lo(xxx), %reg
2040 * sllx %reg, yyy, %reg
2042 * ??? This is just a generalized version of the low_bits==0
2043 * thing above, FIXME...
2045 if ((highest_bit_set - lowest_bit_set) < 32)
2047 unsigned HOST_WIDE_INT focus_bits =
2048 create_simple_focus_bits (high_bits, low_bits,
2051 /* We can't get here in this state. */
2052 if (highest_bit_set < 32
2053 || lowest_bit_set >= 32)
2056 /* So what we know is that the set bits straddle the
2057 middle of the 64-bit word. */
2058 sparc_emit_set_const64_quick2 (op0, temp,
2064 /* 1) sethi %hi(high_bits), %reg
2065 * or %reg, %lo(high_bits), %reg
2066 * sllx %reg, 32, %reg
2067 * or %reg, low_bits, %reg
2069 if (SPARC_SIMM13_P(low_bits)
2070 && ((int)low_bits > 0))
2072 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2076 /* The easiest way when all else fails, is full decomposition. */
2078 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2079 high_bits, low_bits, ~high_bits, ~low_bits);
2081 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2084 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2085 return the mode to be used for the comparison. For floating-point,
2086 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2087 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2088 processing is needed. */
2091 select_cc_mode (op, x, y)
2094 rtx y ATTRIBUTE_UNUSED;
2096 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2122 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2123 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2125 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2126 return CCX_NOOVmode;
2132 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2139 /* X and Y are two things to compare using CODE. Emit the compare insn and
2140 return the rtx for the cc reg in the proper mode. */
2143 gen_compare_reg (code, x, y)
2147 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2150 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2151 fcc regs (cse can't tell they're really call clobbered regs and will
2152 remove a duplicate comparison even if there is an intervening function
2153 call - it will then try to reload the cc reg via an int reg which is why
2154 we need the movcc patterns). It is possible to provide the movcc
2155 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2156 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2157 to tell cse that CCFPE mode registers (even pseudos) are call
2160 /* ??? This is an experiment. Rather than making changes to cse which may
2161 or may not be easy/clean, we do our own cse. This is possible because
2162 we will generate hard registers. Cse knows they're call clobbered (it
2163 doesn't know the same thing about pseudos). If we guess wrong, no big
2164 deal, but if we win, great! */
2166 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2167 #if 1 /* experiment */
2170 /* We cycle through the registers to ensure they're all exercised. */
2171 static int next_fcc_reg = 0;
2172 /* Previous x,y for each fcc reg. */
2173 static rtx prev_args[4][2];
2175 /* Scan prev_args for x,y. */
2176 for (reg = 0; reg < 4; reg++)
2177 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2182 prev_args[reg][0] = x;
2183 prev_args[reg][1] = y;
2184 next_fcc_reg = (next_fcc_reg + 1) & 3;
2186 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2189 cc_reg = gen_reg_rtx (mode);
2190 #endif /* ! experiment */
2191 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2192 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2194 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2196 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2197 gen_rtx_COMPARE (mode, x, y)));
2202 /* This function is used for v9 only.
2203 CODE is the code for an Scc's comparison.
2204 OPERANDS[0] is the target of the Scc insn.
2205 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2206 been generated yet).
2208 This function is needed to turn
2211 (gt (reg:CCX 100 %icc)
2215 (gt:DI (reg:CCX 100 %icc)
2218 IE: The instruction recognizer needs to see the mode of the comparison to
2219 find the right instruction. We could use "gt:DI" right in the
2220 define_expand, but leaving it out allows us to handle DI, SI, etc.
2222 We refer to the global sparc compare operands sparc_compare_op0 and
2223 sparc_compare_op1. */
2226 gen_v9_scc (compare_code, operands)
2227 enum rtx_code compare_code;
2228 register rtx *operands;
2233 && (GET_MODE (sparc_compare_op0) == DImode
2234 || GET_MODE (operands[0]) == DImode))
2237 /* Handle the case where operands[0] == sparc_compare_op0.
2238 We "early clobber" the result. */
2239 if (REGNO (operands[0]) == REGNO (sparc_compare_op0))
2241 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2242 emit_move_insn (op0, sparc_compare_op0);
2245 op0 = sparc_compare_op0;
2246 /* For consistency in the following. */
2247 op1 = sparc_compare_op1;
2249 /* Try to use the movrCC insns. */
2251 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2252 && op1 == const0_rtx
2253 && v9_regcmp_p (compare_code))
2255 /* Special case for op0 != 0. This can be done with one instruction if
2256 operands[0] == sparc_compare_op0. We don't assume they are equal
2259 if (compare_code == NE
2260 && GET_MODE (operands[0]) == DImode
2261 && GET_MODE (op0) == DImode)
2263 emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0));
2264 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2265 gen_rtx_IF_THEN_ELSE (DImode,
2266 gen_rtx_fmt_ee (compare_code, DImode,
2273 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2274 if (GET_MODE (op0) != DImode)
2276 temp = gen_reg_rtx (DImode);
2277 convert_move (temp, op0, 0);
2281 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2282 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2283 gen_rtx_fmt_ee (compare_code, DImode,
2291 operands[1] = gen_compare_reg (compare_code, op0, op1);
2293 switch (GET_MODE (operands[1]))
2303 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2304 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2305 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2306 gen_rtx_fmt_ee (compare_code,
2307 GET_MODE (operands[1]),
2308 operands[1], const0_rtx),
2309 const1_rtx, operands[0])));
2314 /* Emit a conditional jump insn for the v9 architecture using comparison code
2315 CODE and jump target LABEL.
2316 This function exists to take advantage of the v9 brxx insns. */
2319 emit_v9_brxx_insn (code, op0, label)
2323 emit_jump_insn (gen_rtx_SET (VOIDmode,
2325 gen_rtx_IF_THEN_ELSE (VOIDmode,
2326 gen_rtx_fmt_ee (code, GET_MODE (op0),
2328 gen_rtx_LABEL_REF (VOIDmode, label),
2332 /* Generate a DFmode part of a hard TFmode register.
2333 REG is the TFmode hard register, LOW is 1 for the
2334 low 64bit of the register and 0 otherwise.
2337 gen_df_reg (reg, low)
2341 int regno = REGNO (reg);
2343 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2344 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2345 return gen_rtx_REG (DFmode, regno);
2348 /* Return nonzero if a return peephole merging return with
2349 setting of output register is ok. */
2351 leaf_return_peephole_ok ()
2353 return (actual_fsize == 0);
2356 /* Return nonzero if TRIAL can go into the function epilogue's
2357 delay slot. SLOT is the slot we are trying to fill. */
2360 eligible_for_epilogue_delay (trial, slot)
2369 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2372 if (get_attr_length (trial) != 1)
2375 /* If there are any call-saved registers, we should scan TRIAL if it
2376 does not reference them. For now just make it easy. */
2380 /* If the function uses __builtin_eh_return, the eh_return machinery
2381 occupies the delay slot. */
2382 if (current_function_calls_eh_return)
2385 /* In the case of a true leaf function, anything can go into the delay slot.
2386 A delay slot only exists however if the frame size is zero, otherwise
2387 we will put an insn to adjust the stack after the return. */
2388 if (current_function_uses_only_leaf_regs)
2390 if (leaf_return_peephole_ok ())
2391 return ((get_attr_in_uncond_branch_delay (trial)
2392 == IN_BRANCH_DELAY_TRUE));
2396 pat = PATTERN (trial);
2398 /* Otherwise, only operations which can be done in tandem with
2399 a `restore' or `return' insn can go into the delay slot. */
2400 if (GET_CODE (SET_DEST (pat)) != REG
2401 || REGNO (SET_DEST (pat)) < 24)
2404 /* If this instruction sets up floating point register and we have a return
2405 instruction, it can probably go in. But restore will not work
2407 if (REGNO (SET_DEST (pat)) >= 32)
2409 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2410 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2415 /* The set of insns matched here must agree precisely with the set of
2416 patterns paired with a RETURN in sparc.md. */
2418 src = SET_SRC (pat);
2420 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2421 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2422 && arith_operand (src, GET_MODE (src)))
2425 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2427 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2430 /* This matches "*return_di". */
2431 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2432 && arith_double_operand (src, GET_MODE (src)))
2433 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2435 /* This matches "*return_sf_no_fpu". */
2436 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2437 && register_operand (src, SFmode))
2440 /* If we have return instruction, anything that does not use
2441 local or output registers and can go into a delay slot wins. */
2442 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2443 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2446 /* This matches "*return_addsi". */
2447 else if (GET_CODE (src) == PLUS
2448 && arith_operand (XEXP (src, 0), SImode)
2449 && arith_operand (XEXP (src, 1), SImode)
2450 && (register_operand (XEXP (src, 0), SImode)
2451 || register_operand (XEXP (src, 1), SImode)))
2454 /* This matches "*return_adddi". */
2455 else if (GET_CODE (src) == PLUS
2456 && arith_double_operand (XEXP (src, 0), DImode)
2457 && arith_double_operand (XEXP (src, 1), DImode)
2458 && (register_operand (XEXP (src, 0), DImode)
2459 || register_operand (XEXP (src, 1), DImode)))
2462 /* This can match "*return_losum_[sd]i".
2463 Catch only some cases, so that return_losum* don't have
2465 else if (GET_CODE (src) == LO_SUM
2466 && ! TARGET_CM_MEDMID
2467 && ((register_operand (XEXP (src, 0), SImode)
2468 && immediate_operand (XEXP (src, 1), SImode))
2470 && register_operand (XEXP (src, 0), DImode)
2471 && immediate_operand (XEXP (src, 1), DImode))))
2474 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2475 else if (GET_CODE (src) == ASHIFT
2476 && (register_operand (XEXP (src, 0), SImode)
2477 || register_operand (XEXP (src, 0), DImode))
2478 && XEXP (src, 1) == const1_rtx)
2484 /* Return nonzero if TRIAL can go into the sibling call
2488 eligible_for_sibcall_delay (trial)
2493 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2496 if (get_attr_length (trial) != 1 || profile_block_flag == 2)
2499 pat = PATTERN (trial);
2501 if (current_function_uses_only_leaf_regs)
2503 /* If the tail call is done using the call instruction,
2504 we have to restore %o7 in the delay slot. */
2505 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2508 /* %g1 is used to build the function address */
2509 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2515 /* Otherwise, only operations which can be done in tandem with
2516 a `restore' insn can go into the delay slot. */
2517 if (GET_CODE (SET_DEST (pat)) != REG
2518 || REGNO (SET_DEST (pat)) < 24
2519 || REGNO (SET_DEST (pat)) >= 32)
2522 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2524 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2527 src = SET_SRC (pat);
2529 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2530 && arith_operand (src, GET_MODE (src)))
2533 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2535 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2538 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2539 && arith_double_operand (src, GET_MODE (src)))
2540 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2542 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2543 && register_operand (src, SFmode))
2546 else if (GET_CODE (src) == PLUS
2547 && arith_operand (XEXP (src, 0), SImode)
2548 && arith_operand (XEXP (src, 1), SImode)
2549 && (register_operand (XEXP (src, 0), SImode)
2550 || register_operand (XEXP (src, 1), SImode)))
2553 else if (GET_CODE (src) == PLUS
2554 && arith_double_operand (XEXP (src, 0), DImode)
2555 && arith_double_operand (XEXP (src, 1), DImode)
2556 && (register_operand (XEXP (src, 0), DImode)
2557 || register_operand (XEXP (src, 1), DImode)))
2560 else if (GET_CODE (src) == LO_SUM
2561 && ! TARGET_CM_MEDMID
2562 && ((register_operand (XEXP (src, 0), SImode)
2563 && immediate_operand (XEXP (src, 1), SImode))
2565 && register_operand (XEXP (src, 0), DImode)
2566 && immediate_operand (XEXP (src, 1), DImode))))
2569 else if (GET_CODE (src) == ASHIFT
2570 && (register_operand (XEXP (src, 0), SImode)
2571 || register_operand (XEXP (src, 0), DImode))
2572 && XEXP (src, 1) == const1_rtx)
2579 check_return_regs (x)
2582 switch (GET_CODE (x))
2585 return IN_OR_GLOBAL_P (x);
2600 if (check_return_regs (XEXP (x, 1)) == 0)
2605 return check_return_regs (XEXP (x, 0));
2613 /* Return 1 if TRIAL references only in and global registers. */
2615 eligible_for_return_delay (trial)
2618 if (GET_CODE (PATTERN (trial)) != SET)
2621 return check_return_regs (PATTERN (trial));
2625 short_branch (uid1, uid2)
2628 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
2630 /* Leave a few words of "slop". */
2631 if (delta >= -1023 && delta <= 1022)
2637 /* Return non-zero if REG is not used after INSN.
2638 We assume REG is a reload reg, and therefore does
2639 not live past labels or calls or jumps. */
2641 reg_unused_after (reg, insn)
2645 enum rtx_code code, prev_code = UNKNOWN;
2647 while ((insn = NEXT_INSN (insn)))
2649 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2652 code = GET_CODE (insn);
2653 if (GET_CODE (insn) == CODE_LABEL)
2656 if (GET_RTX_CLASS (code) == 'i')
2658 rtx set = single_set (insn);
2659 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2662 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2664 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2672 /* The table we use to reference PIC data. */
2673 static rtx global_offset_table;
2675 /* The function we use to get at it. */
2676 static rtx get_pc_symbol;
2677 static char get_pc_symbol_name[256];
2679 /* Ensure that we are not using patterns that are not OK with PIC. */
2688 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
2689 || (GET_CODE (recog_data.operand[i]) == CONST
2690 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
2691 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
2692 == global_offset_table)
2693 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
2702 /* Return true if X is an address which needs a temporary register when
2703 reloaded while generating PIC code. */
2706 pic_address_needs_scratch (x)
2709 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2710 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2711 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2712 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2713 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2719 /* Legitimize PIC addresses. If the address is already position-independent,
2720 we return ORIG. Newly generated position-independent addresses go into a
2721 reg. This is REG if non zero, otherwise we allocate register(s) as
2725 legitimize_pic_address (orig, mode, reg)
2727 enum machine_mode mode ATTRIBUTE_UNUSED;
2730 if (GET_CODE (orig) == SYMBOL_REF)
2732 rtx pic_ref, address;
2737 if (reload_in_progress || reload_completed)
2740 reg = gen_reg_rtx (Pmode);
2745 /* If not during reload, allocate another temp reg here for loading
2746 in the address, so that these instructions can be optimized
2748 rtx temp_reg = ((reload_in_progress || reload_completed)
2749 ? reg : gen_reg_rtx (Pmode));
2751 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
2752 won't get confused into thinking that these two instructions
2753 are loading in the true address of the symbol. If in the
2754 future a PIC rtx exists, that should be used instead. */
2755 if (Pmode == SImode)
2757 emit_insn (gen_movsi_high_pic (temp_reg, orig));
2758 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
2762 emit_insn (gen_movdi_high_pic (temp_reg, orig));
2763 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
2770 pic_ref = gen_rtx_MEM (Pmode,
2771 gen_rtx_PLUS (Pmode,
2772 pic_offset_table_rtx, address));
2773 current_function_uses_pic_offset_table = 1;
2774 RTX_UNCHANGING_P (pic_ref) = 1;
2775 insn = emit_move_insn (reg, pic_ref);
2776 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2778 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2782 else if (GET_CODE (orig) == CONST)
2786 if (GET_CODE (XEXP (orig, 0)) == PLUS
2787 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2792 if (reload_in_progress || reload_completed)
2795 reg = gen_reg_rtx (Pmode);
2798 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2800 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2801 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2802 base == reg ? 0 : reg);
2807 if (GET_CODE (offset) == CONST_INT)
2809 if (SMALL_INT (offset))
2810 return plus_constant_for_output (base, INTVAL (offset));
2811 else if (! reload_in_progress && ! reload_completed)
2812 offset = force_reg (Pmode, offset);
2814 /* If we reach here, then something is seriously wrong. */
2817 return gen_rtx_PLUS (Pmode, base, offset);
2819 else if (GET_CODE (orig) == LABEL_REF)
2820 /* ??? Why do we do this? */
2821 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
2822 the register is live instead, in case it is eliminated. */
2823 current_function_uses_pic_offset_table = 1;
2828 /* Emit special PIC prologues. */
2831 load_pic_register ()
2833 /* Labels to get the PC in the prologue of this function. */
2834 int orig_flag_pic = flag_pic;
2839 /* If we havn't emitted the special get_pc helper function, do so now. */
2840 if (get_pc_symbol_name[0] == 0)
2844 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
2847 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
2849 ASM_OUTPUT_ALIGN (asm_out_file, align);
2850 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0);
2851 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
2854 /* Initialize every time through, since we can't easily
2855 know this to be permanent. */
2856 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2857 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
2860 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
2863 flag_pic = orig_flag_pic;
2865 /* Need to emit this whether or not we obey regdecls,
2866 since setjmp/longjmp can cause life info to screw up.
2867 ??? In the case where we don't obey regdecls, this is not sufficient
2868 since we may not fall out the bottom. */
2869 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2872 /* Return 1 if RTX is a MEM which is known to be aligned to at
2873 least an 8 byte boundary. */
2876 mem_min_alignment (mem, desired)
2880 rtx addr, base, offset;
2882 /* If it's not a MEM we can't accept it. */
2883 if (GET_CODE (mem) != MEM)
2886 addr = XEXP (mem, 0);
2887 base = offset = NULL_RTX;
2888 if (GET_CODE (addr) == PLUS)
2890 if (GET_CODE (XEXP (addr, 0)) == REG)
2892 base = XEXP (addr, 0);
2894 /* What we are saying here is that if the base
2895 REG is aligned properly, the compiler will make
2896 sure any REG based index upon it will be so
2898 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2899 offset = XEXP (addr, 1);
2901 offset = const0_rtx;
2904 else if (GET_CODE (addr) == REG)
2907 offset = const0_rtx;
2910 if (base != NULL_RTX)
2912 int regno = REGNO (base);
2914 if (regno != FRAME_POINTER_REGNUM
2915 && regno != STACK_POINTER_REGNUM)
2917 /* Check if the compiler has recorded some information
2918 about the alignment of the base REG. If reload has
2919 completed, we already matched with proper alignments.
2920 If not running global_alloc, reload might give us
2921 unaligned pointer to local stack though. */
2923 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
2924 || (optimize && reload_completed))
2925 && (INTVAL (offset) & (desired - 1)) == 0)
2930 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
2934 else if (! TARGET_UNALIGNED_DOUBLES
2935 || CONSTANT_P (addr)
2936 || GET_CODE (addr) == LO_SUM)
2938 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
2939 is true, in which case we can only assume that an access is aligned if
2940 it is to a constant address, or the address involves a LO_SUM. */
2944 /* An obviously unaligned address. */
2949 /* Vectors to keep interesting information about registers where it can easily
2950 be got. We use to use the actual mode value as the bit number, but there
2951 are more than 32 modes now. Instead we use two tables: one indexed by
2952 hard register number, and one indexed by mode. */
2954 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2955 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2956 mapped into one sparc_mode_class mode. */
2958 enum sparc_mode_class {
2959 S_MODE, D_MODE, T_MODE, O_MODE,
2960 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
2964 /* Modes for single-word and smaller quantities. */
2965 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2967 /* Modes for double-word and smaller quantities. */
2968 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2970 /* Modes for quad-word and smaller quantities. */
2971 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2973 /* Modes for 8-word and smaller quantities. */
2974 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
2976 /* Modes for single-float quantities. We must allow any single word or
2977 smaller quantity. This is because the fix/float conversion instructions
2978 take integer inputs/outputs from the float registers. */
2979 #define SF_MODES (S_MODES)
2981 /* Modes for double-float and smaller quantities. */
2982 #define DF_MODES (S_MODES | D_MODES)
2984 /* Modes for double-float only quantities. */
2985 #define DF_MODES_NO_S (D_MODES)
2987 /* Modes for quad-float only quantities. */
2988 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2990 /* Modes for quad-float and smaller quantities. */
2991 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2993 /* Modes for quad-float and double-float quantities. */
2994 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
2996 /* Modes for quad-float pair only quantities. */
2997 #define OF_ONLY_MODES (1 << (int) OF_MODE)
2999 /* Modes for quad-float pairs and smaller quantities. */
3000 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3002 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3004 /* Modes for condition codes. */
3005 #define CC_MODES (1 << (int) CC_MODE)
3006 #define CCFP_MODES (1 << (int) CCFP_MODE)
3008 /* Value is 1 if register/mode pair is acceptable on sparc.
3009 The funny mixture of D and T modes is because integer operations
3010 do not specially operate on tetra quantities, so non-quad-aligned
3011 registers can hold quadword quantities (except %o4 and %i4 because
3012 they cross fixed registers). */
3014 /* This points to either the 32 bit or the 64 bit version. */
3015 int *hard_regno_mode_classes;
3017 static int hard_32bit_mode_classes[] = {
3018 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3019 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3020 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3021 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3023 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3024 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3025 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3026 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3028 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3029 and none can hold SFmode/SImode values. */
3030 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3031 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3032 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3033 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3036 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3042 static int hard_64bit_mode_classes[] = {
3043 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3044 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3045 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3046 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3048 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3049 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3050 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3051 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3053 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3054 and none can hold SFmode/SImode values. */
3055 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3056 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3057 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3058 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3061 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3067 int sparc_mode_class [NUM_MACHINE_MODES];
3069 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3076 for (i = 0; i < NUM_MACHINE_MODES; i++)
3078 switch (GET_MODE_CLASS (i))
3081 case MODE_PARTIAL_INT:
3082 case MODE_COMPLEX_INT:
3083 if (GET_MODE_SIZE (i) <= 4)
3084 sparc_mode_class[i] = 1 << (int) S_MODE;
3085 else if (GET_MODE_SIZE (i) == 8)
3086 sparc_mode_class[i] = 1 << (int) D_MODE;
3087 else if (GET_MODE_SIZE (i) == 16)
3088 sparc_mode_class[i] = 1 << (int) T_MODE;
3089 else if (GET_MODE_SIZE (i) == 32)
3090 sparc_mode_class[i] = 1 << (int) O_MODE;
3092 sparc_mode_class[i] = 0;
3095 case MODE_COMPLEX_FLOAT:
3096 if (GET_MODE_SIZE (i) <= 4)
3097 sparc_mode_class[i] = 1 << (int) SF_MODE;
3098 else if (GET_MODE_SIZE (i) == 8)
3099 sparc_mode_class[i] = 1 << (int) DF_MODE;
3100 else if (GET_MODE_SIZE (i) == 16)
3101 sparc_mode_class[i] = 1 << (int) TF_MODE;
3102 else if (GET_MODE_SIZE (i) == 32)
3103 sparc_mode_class[i] = 1 << (int) OF_MODE;
3105 sparc_mode_class[i] = 0;
3109 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3110 we must explicitly check for them here. */
3111 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3112 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3113 else if (i == (int) CCmode || i == (int) CC_NOOVmode
3114 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3115 sparc_mode_class[i] = 1 << (int) CC_MODE;
3117 sparc_mode_class[i] = 0;
3123 hard_regno_mode_classes = hard_64bit_mode_classes;
3125 hard_regno_mode_classes = hard_32bit_mode_classes;
3127 /* Initialize the array used by REGNO_REG_CLASS. */
3128 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3130 if (i < 16 && TARGET_V8PLUS)
3131 sparc_regno_reg_class[i] = I64_REGS;
3133 sparc_regno_reg_class[i] = GENERAL_REGS;
3135 sparc_regno_reg_class[i] = FP_REGS;
3137 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3139 sparc_regno_reg_class[i] = FPCC_REGS;
3141 sparc_regno_reg_class[i] = NO_REGS;
3145 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3146 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3147 v9 int regs as it simplifies the code. */
3150 save_regs (file, low, high, base, offset, n_regs, real_offset)
3160 if (TARGET_ARCH64 && high <= 32)
3162 for (i = low; i < high; i++)
3164 if (regs_ever_live[i] && ! call_used_regs[i])
3166 fprintf (file, "\tstx\t%s, [%s+%d]\n",
3167 reg_names[i], base, offset + 4 * n_regs);
3168 if (dwarf2out_do_frame ())
3169 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3176 for (i = low; i < high; i += 2)
3178 if (regs_ever_live[i] && ! call_used_regs[i])
3180 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3182 fprintf (file, "\tstd\t%s, [%s+%d]\n",
3183 reg_names[i], base, offset + 4 * n_regs);
3184 if (dwarf2out_do_frame ())
3186 char *l = dwarf2out_cfi_label ();
3187 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
3188 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
3194 fprintf (file, "\tst\t%s, [%s+%d]\n",
3195 reg_names[i], base, offset + 4 * n_regs);
3196 if (dwarf2out_do_frame ())
3197 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3203 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3205 fprintf (file, "\tst\t%s, [%s+%d]\n",
3206 reg_names[i+1], base, offset + 4 * n_regs + 4);
3207 if (dwarf2out_do_frame ())
3208 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
3217 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3219 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3220 v9 int regs as it simplifies the code. */
3223 restore_regs (file, low, high, base, offset, n_regs)
3232 if (TARGET_ARCH64 && high <= 32)
3234 for (i = low; i < high; i++)
3236 if (regs_ever_live[i] && ! call_used_regs[i])
3237 fprintf (file, "\tldx\t[%s+%d], %s\n",
3238 base, offset + 4 * n_regs, reg_names[i]),
3244 for (i = low; i < high; i += 2)
3246 if (regs_ever_live[i] && ! call_used_regs[i])
3247 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3248 fprintf (file, "\tldd\t[%s+%d], %s\n",
3249 base, offset + 4 * n_regs, reg_names[i]),
3252 fprintf (file, "\tld\t[%s+%d], %s\n",
3253 base, offset + 4 * n_regs, reg_names[i]),
3255 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3256 fprintf (file, "\tld\t[%s+%d], %s\n",
3257 base, offset + 4 * n_regs + 4, reg_names[i+1]),
3264 /* Compute the frame size required by the function. This function is called
3265 during the reload pass and also by output_function_prologue(). */
3268 compute_frame_size (size, leaf_function)
3273 int outgoing_args_size = (current_function_outgoing_args_size
3274 + REG_PARM_STACK_SPACE (current_function_decl));
3276 if (TARGET_EPILOGUE)
3278 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3279 even to v9 int regs to be consistent with save_regs/restore_regs. */
3283 for (i = 0; i < 8; i++)
3284 if (regs_ever_live[i] && ! call_used_regs[i])
3289 for (i = 0; i < 8; i += 2)
3290 if ((regs_ever_live[i] && ! call_used_regs[i])
3291 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3295 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3296 if ((regs_ever_live[i] && ! call_used_regs[i])
3297 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3301 /* Set up values for use in `function_epilogue'. */
3302 num_gfregs = n_regs;
3304 if (leaf_function && n_regs == 0
3305 && size == 0 && current_function_outgoing_args_size == 0)
3307 actual_fsize = apparent_fsize = 0;
3311 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3312 The stack bias (if any) is taken out to undo its effects. */
3313 apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8;
3314 apparent_fsize += n_regs * 4;
3315 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3318 /* Make sure nothing can clobber our register windows.
3319 If a SAVE must be done, or there is a stack-local variable,
3320 the register window area must be allocated.
3321 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3322 if (leaf_function == 0 || size > 0)
3323 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3325 return SPARC_STACK_ALIGN (actual_fsize);
3328 /* Build a (32 bit) big number in a register. */
3329 /* ??? We may be able to use the set macro here too. */
3332 build_big_number (file, num, reg)
3337 if (num >= 0 || ! TARGET_ARCH64)
3339 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
3340 if ((num & 0x3ff) != 0)
3341 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
3343 else /* num < 0 && TARGET_ARCH64 */
3345 /* Sethi does not sign extend, so we must use a little trickery
3346 to use it for negative numbers. Invert the constant before
3347 loading it in, then use xor immediate to invert the loaded bits
3348 (along with the upper 32 bits) to the desired constant. This
3349 works because the sethi and immediate fields overlap. */
3352 int low = -0x400 + (asize & 0x3FF);
3354 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3355 inv, reg, reg, low, reg);
3359 /* Output any necessary .register pseudo-ops. */
3361 sparc_output_scratch_registers (file)
3362 FILE *file ATTRIBUTE_UNUSED;
3364 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3370 /* Check if %g[2367] were used without
3371 .register being printed for them already. */
3372 for (i = 2; i < 8; i++)
3374 if (regs_ever_live [i]
3375 && ! sparc_hard_reg_printed [i])
3377 sparc_hard_reg_printed [i] = 1;
3378 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
3385 /* Output code for the function prologue. */
3388 output_function_prologue (file, size, leaf_function)
3393 sparc_output_scratch_registers (file);
3395 /* Need to use actual_fsize, since we are also allocating
3396 space for our callee (and our own register save area). */
3397 actual_fsize = compute_frame_size (size, leaf_function);
3401 frame_base_name = "%sp";
3402 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3406 frame_base_name = "%fp";
3407 frame_base_offset = SPARC_STACK_BIAS;
3410 /* This is only for the human reader. */
3411 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3413 if (actual_fsize == 0)
3415 else if (! leaf_function)
3417 if (actual_fsize <= 4096)
3418 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3419 else if (actual_fsize <= 8192)
3421 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3422 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3426 build_big_number (file, -actual_fsize, "%g1");
3427 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
3430 else /* leaf function */
3432 if (actual_fsize <= 4096)
3433 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3434 else if (actual_fsize <= 8192)
3436 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3437 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3441 build_big_number (file, -actual_fsize, "%g1");
3442 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3446 if (dwarf2out_do_frame () && actual_fsize)
3448 char *label = dwarf2out_cfi_label ();
3450 /* The canonical frame address refers to the top of the frame. */
3451 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3452 : FRAME_POINTER_REGNUM),
3455 if (! leaf_function)
3457 /* Note the register window save. This tells the unwinder that
3458 it needs to restore the window registers from the previous
3459 frame's window save area at 0(cfa). */
3460 dwarf2out_window_save (label);
3462 /* The return address (-8) is now in %i7. */
3463 dwarf2out_return_reg (label, 31);
3467 /* If doing anything with PIC, do it now. */
3469 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3471 /* Call saved registers are saved just above the outgoing argument area. */
3474 int offset, real_offset, n_regs;
3477 real_offset = -apparent_fsize;
3478 offset = -apparent_fsize + frame_base_offset;
3479 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3481 /* ??? This might be optimized a little as %g1 might already have a
3482 value close enough that a single add insn will do. */
3483 /* ??? Although, all of this is probably only a temporary fix
3484 because if %g1 can hold a function result, then
3485 output_function_epilogue will lose (the result will get
3487 build_big_number (file, offset, "%g1");
3488 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3494 base = frame_base_name;
3498 if (TARGET_EPILOGUE && ! leaf_function)
3499 /* ??? Originally saved regs 0-15 here. */
3500 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3501 else if (leaf_function)
3502 /* ??? Originally saved regs 0-31 here. */
3503 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3504 if (TARGET_EPILOGUE)
3505 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3510 if (leaf_function && actual_fsize != 0)
3512 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3513 if (! TARGET_EPILOGUE)
3514 leaf_label = gen_label_rtx ();
3518 /* Output code to restore any call saved registers. */
3521 output_restore_regs (file, leaf_function)
3528 offset = -apparent_fsize + frame_base_offset;
3529 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3531 build_big_number (file, offset, "%g1");
3532 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3538 base = frame_base_name;
3542 if (TARGET_EPILOGUE && ! leaf_function)
3543 /* ??? Originally saved regs 0-15 here. */
3544 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3545 else if (leaf_function)
3546 /* ??? Originally saved regs 0-31 here. */
3547 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3548 if (TARGET_EPILOGUE)
3549 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
3552 /* Output code for the function epilogue. */
3555 output_function_epilogue (file, size, leaf_function)
3557 int size ATTRIBUTE_UNUSED;
3564 emit_label_after (leaf_label, get_last_insn ());
3565 final_scan_insn (get_last_insn (), file, 0, 0, 1);
3568 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3569 else if (profile_block_flag == 2)
3571 FUNCTION_BLOCK_PROFILER_EXIT(file);
3575 else if (current_function_epilogue_delay_list == 0)
3577 /* If code does not drop into the epilogue, we need
3578 do nothing except output pending case vectors. */
3579 rtx insn = get_last_insn ();
3580 if (GET_CODE (insn) == NOTE)
3581 insn = prev_nonnote_insn (insn);
3582 if (insn && GET_CODE (insn) == BARRIER)
3583 goto output_vectors;
3587 output_restore_regs (file, leaf_function);
3589 /* Work out how to skip the caller's unimp instruction if required. */
3591 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
3593 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
3595 if (TARGET_EPILOGUE || leaf_label)
3597 int old_target_epilogue = TARGET_EPILOGUE;
3598 target_flags &= ~old_target_epilogue;
3600 if (! leaf_function)
3602 if (current_function_calls_eh_return)
3604 if (current_function_epilogue_delay_list)
3606 if (SKIP_CALLERS_UNIMP_P)
3609 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
3611 /* If we wound up with things in our delay slot, flush them here. */
3612 else if (current_function_epilogue_delay_list)
3614 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
3616 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
3618 epilogue_renumber (&delay, 0);
3619 fputs (SKIP_CALLERS_UNIMP_P
3620 ? "\treturn\t%i7+12\n"
3621 : "\treturn\t%i7+8\n", file);
3622 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), file, 1, 0, 0);
3626 rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode),
3630 if (GET_CODE (delay) != SET)
3633 src = SET_SRC (delay);
3634 if (GET_CODE (src) == ASHIFT)
3636 if (XEXP (src, 1) != const1_rtx)
3638 SET_SRC (delay) = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
3642 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode,
3643 gen_rtvec (2, delay, PATTERN (insn)));
3644 final_scan_insn (insn, file, 1, 0, 1);
3647 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
3648 fputs ("\treturn\t%i7+8\n\tnop\n", file);
3650 fprintf (file, "\t%s\n\trestore\n", ret);
3652 else if (current_function_calls_eh_return)
3654 /* All of the following cases are for leaf functions. */
3655 else if (current_function_epilogue_delay_list)
3657 /* eligible_for_epilogue_delay_slot ensures that if this is a
3658 leaf function, then we will only have insn in the delay slot
3659 if the frame size is zero, thus no adjust for the stack is
3661 if (actual_fsize != 0)
3663 fprintf (file, "\t%s\n", ret);
3664 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
3667 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3668 avoid generating confusing assembly language output. */
3669 else if (actual_fsize == 0)
3670 fprintf (file, "\t%s\n\tnop\n", ret);
3671 else if (actual_fsize <= 4096)
3672 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
3673 else if (actual_fsize <= 8192)
3674 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
3675 ret, actual_fsize - 4096);
3676 else if ((actual_fsize & 0x3ff) == 0)
3677 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3680 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3681 actual_fsize, actual_fsize, ret);
3682 target_flags |= old_target_epilogue;
3686 sparc_output_deferred_case_vectors ();
3689 /* Output a sibling call. */
3692 output_sibcall (insn, call_operand)
3693 rtx insn, call_operand;
3695 int leaf_regs = current_function_uses_only_leaf_regs;
3697 int delay_slot = dbr_sequence_length () > 0;
3701 /* Call to restore global regs might clobber
3702 the delay slot. Instead of checking for this
3703 output the delay slot now. */
3706 rtx delay = NEXT_INSN (insn);
3711 final_scan_insn (delay, asm_out_file, 1, 0, 1);
3712 PATTERN (delay) = gen_blockage ();
3713 INSN_CODE (delay) = -1;
3716 output_restore_regs (asm_out_file, leaf_regs);
3719 operands[0] = call_operand;
3723 #ifdef HAVE_AS_RELAX_OPTION
3724 /* If as and ld are relaxing tail call insns into branch always,
3725 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
3726 be optimized. With sethi/jmpl as nor ld has no easy way how to
3727 find out if somebody does not branch between the sethi and jmpl. */
3730 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
3734 if ((actual_fsize || ! spare_slot) && delay_slot)
3736 rtx delay = NEXT_INSN (insn);
3741 final_scan_insn (delay, asm_out_file, 1, 0, 1);
3742 PATTERN (delay) = gen_blockage ();
3743 INSN_CODE (delay) = -1;
3748 if (actual_fsize <= 4096)
3749 size = actual_fsize;
3750 else if (actual_fsize <= 8192)
3752 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
3753 size = actual_fsize - 4096;
3755 else if ((actual_fsize & 0x3ff) == 0)
3756 fprintf (asm_out_file,
3757 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
3761 fprintf (asm_out_file,
3762 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
3763 actual_fsize, actual_fsize);
3764 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
3769 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
3770 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
3772 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size);
3773 else if (! delay_slot)
3774 fputs ("\t nop\n", asm_out_file);
3779 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size);
3780 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
3781 it into branch if possible. */
3782 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
3783 output_asm_insn ("call\t%a0, 0", operands);
3784 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
3789 output_asm_insn ("call\t%a0, 0", operands);
3792 rtx delay = NEXT_INSN (insn), pat;
3797 pat = PATTERN (delay);
3798 if (GET_CODE (pat) != SET)
3801 operands[0] = SET_DEST (pat);
3802 pat = SET_SRC (pat);
3803 switch (GET_CODE (pat))
3806 operands[1] = XEXP (pat, 0);
3807 operands[2] = XEXP (pat, 1);
3808 output_asm_insn (" restore %r1, %2, %Y0", operands);
3811 operands[1] = XEXP (pat, 0);
3812 operands[2] = XEXP (pat, 1);
3813 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
3816 operands[1] = XEXP (pat, 0);
3817 output_asm_insn (" restore %r1, %r1, %Y0", operands);
3821 output_asm_insn (" restore %%g0, %1, %Y0", operands);
3824 PATTERN (delay) = gen_blockage ();
3825 INSN_CODE (delay) = -1;
3828 fputs ("\t restore\n", asm_out_file);
3832 /* Functions for handling argument passing.
3834 For v8 the first six args are normally in registers and the rest are
3835 pushed. Any arg that starts within the first 6 words is at least
3836 partially passed in a register unless its data type forbids.
3838 For v9, the argument registers are laid out as an array of 16 elements
3839 and arguments are added sequentially. The first 6 int args and up to the
3840 first 16 fp args (depending on size) are passed in regs.
3842 Slot Stack Integral Float Float in structure Double Long Double
3843 ---- ----- -------- ----- ------------------ ------ -----------
3844 15 [SP+248] %f31 %f30,%f31 %d30
3845 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3846 13 [SP+232] %f27 %f26,%f27 %d26
3847 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3848 11 [SP+216] %f23 %f22,%f23 %d22
3849 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3850 9 [SP+200] %f19 %f18,%f19 %d18
3851 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3852 7 [SP+184] %f15 %f14,%f15 %d14
3853 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3854 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3855 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3856 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3857 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3858 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3859 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3861 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3863 Integral arguments are always passed as 64 bit quantities appropriately
3866 Passing of floating point values is handled as follows.
3867 If a prototype is in scope:
3868 If the value is in a named argument (i.e. not a stdarg function or a
3869 value not part of the `...') then the value is passed in the appropriate
3871 If the value is part of the `...' and is passed in one of the first 6
3872 slots then the value is passed in the appropriate int reg.
3873 If the value is part of the `...' and is not passed in one of the first 6
3874 slots then the value is passed in memory.
3875 If a prototype is not in scope:
3876 If the value is one of the first 6 arguments the value is passed in the
3877 appropriate integer reg and the appropriate fp reg.
3878 If the value is not one of the first 6 arguments the value is passed in
3879 the appropriate fp reg and in memory.
3882 /* Maximum number of int regs for args. */
3883 #define SPARC_INT_ARG_MAX 6
3884 /* Maximum number of fp regs for args. */
3885 #define SPARC_FP_ARG_MAX 16
3887 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3889 /* Handle the INIT_CUMULATIVE_ARGS macro.
3890 Initialize a variable CUM of type CUMULATIVE_ARGS
3891 for a call to a function whose data type is FNTYPE.
3892 For a library call, FNTYPE is 0. */
3895 init_cumulative_args (cum, fntype, libname, indirect)
3896 CUMULATIVE_ARGS *cum;
3898 rtx libname ATTRIBUTE_UNUSED;
3899 int indirect ATTRIBUTE_UNUSED;
3902 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
3903 cum->libcall_p = fntype == 0;
3906 /* Compute the slot number to pass an argument in.
3907 Returns the slot number or -1 if passing on the stack.
3909 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3910 the preceding args and about the function being called.
3911 MODE is the argument's machine mode.
3912 TYPE is the data type of the argument (as a tree).
3913 This is null for libcalls where that information may
3915 NAMED is nonzero if this argument is a named parameter
3916 (otherwise it is an extra parameter matching an ellipsis).
3917 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3918 *PREGNO records the register number to use if scalar type.
3919 *PPADDING records the amount of padding needed in words. */
3922 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
3923 const CUMULATIVE_ARGS *cum;
3924 enum machine_mode mode;
3931 int regbase = (incoming_p
3932 ? SPARC_INCOMING_INT_ARG_FIRST
3933 : SPARC_OUTGOING_INT_ARG_FIRST);
3934 int slotno = cum->words;
3939 if (type != 0 && TREE_ADDRESSABLE (type))
3942 && type != 0 && mode == BLKmode
3943 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
3949 /* MODE is VOIDmode when generating the actual call.
3953 case QImode : case CQImode :
3954 case HImode : case CHImode :
3955 case SImode : case CSImode :
3956 case DImode : case CDImode :
3957 case TImode : case CTImode :
3958 if (slotno >= SPARC_INT_ARG_MAX)
3960 regno = regbase + slotno;
3963 case SFmode : case SCmode :
3964 case DFmode : case DCmode :
3965 case TFmode : case TCmode :
3968 if (slotno >= SPARC_INT_ARG_MAX)
3970 regno = regbase + slotno;
3974 if ((mode == TFmode || mode == TCmode)
3975 && (slotno & 1) != 0)
3976 slotno++, *ppadding = 1;
3977 if (TARGET_FPU && named)
3979 if (slotno >= SPARC_FP_ARG_MAX)
3981 regno = SPARC_FP_ARG_FIRST + slotno * 2;
3987 if (slotno >= SPARC_INT_ARG_MAX)
3989 regno = regbase + slotno;
3995 /* For sparc64, objects requiring 16 byte alignment get it. */
3998 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
3999 slotno++, *ppadding = 1;
4003 || (type && TREE_CODE (type) == UNION_TYPE))
4005 if (slotno >= SPARC_INT_ARG_MAX)
4007 regno = regbase + slotno;
4012 int intregs_p = 0, fpregs_p = 0;
4013 /* The ABI obviously doesn't specify how packed
4014 structures are passed. These are defined to be passed
4015 in int regs if possible, otherwise memory. */
4018 /* First see what kinds of registers we need. */
4019 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4021 if (TREE_CODE (field) == FIELD_DECL)
4023 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4028 if (DECL_PACKED (field))
4032 if (packed_p || !named)
4033 fpregs_p = 0, intregs_p = 1;
4035 /* If all arg slots are filled, then must pass on stack. */
4036 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4038 /* If there are only int args and all int arg slots are filled,
4039 then must pass on stack. */
4040 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4042 /* Note that even if all int arg slots are filled, fp members may
4043 still be passed in regs if such regs are available.
4044 *PREGNO isn't set because there may be more than one, it's up
4045 to the caller to compute them. */
4058 /* Handle recursive register counting for structure field layout. */
4060 struct function_arg_record_value_parms
4063 int slotno, named, regbase;
4068 static void function_arg_record_value_3
4069 PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *));
4070 static void function_arg_record_value_2
4071 PARAMS ((tree, HOST_WIDE_INT,
4072 struct function_arg_record_value_parms *));
4073 static void function_arg_record_value_1
4074 PARAMS ((tree, HOST_WIDE_INT,
4075 struct function_arg_record_value_parms *));
4076 static rtx function_arg_record_value
4077 PARAMS ((tree, enum machine_mode, int, int, int));
4079 /* A subroutine of function_arg_record_value. Traverse the structure
4080 recusively and determine how many registers will be required. */
4083 function_arg_record_value_1 (type, startbitpos, parms)
4085 HOST_WIDE_INT startbitpos;
4086 struct function_arg_record_value_parms *parms;
4090 /* The ABI obviously doesn't specify how packed structures are
4091 passed. These are defined to be passed in int regs if possible,
4092 otherwise memory. */
4095 /* We need to compute how many registers are needed so we can
4096 allocate the PARALLEL but before we can do that we need to know
4097 whether there are any packed fields. If there are, int regs are
4098 used regardless of whether there are fp values present. */
4099 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4101 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4108 /* Compute how many registers we need. */
4109 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4111 if (TREE_CODE (field) == FIELD_DECL)
4113 HOST_WIDE_INT bitpos = startbitpos;
4115 if (DECL_SIZE (field) != 0
4116 && host_integerp (bit_position (field), 1))
4117 bitpos += int_bit_position (field);
4119 /* ??? FIXME: else assume zero offset. */
4121 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4122 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
4123 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4128 if (parms->intoffset != -1)
4130 int intslots, this_slotno;
4132 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
4134 this_slotno = parms->slotno + parms->intoffset
4137 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4138 intslots = MAX (intslots, 0);
4139 parms->nregs += intslots;
4140 parms->intoffset = -1;
4143 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4144 If it wasn't true we wouldn't be here. */
4149 if (parms->intoffset == -1)
4150 parms->intoffset = bitpos;
4156 /* A subroutine of function_arg_record_value. Assign the bits of the
4157 structure between parms->intoffset and bitpos to integer registers. */
4160 function_arg_record_value_3 (bitpos, parms)
4161 HOST_WIDE_INT bitpos;
4162 struct function_arg_record_value_parms *parms;
4164 enum machine_mode mode;
4166 unsigned int startbit, endbit;
4167 int this_slotno, intslots, intoffset;
4170 if (parms->intoffset == -1)
4173 intoffset = parms->intoffset;
4174 parms->intoffset = -1;
4176 startbit = intoffset & -BITS_PER_WORD;
4177 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4178 intslots = (endbit - startbit) / BITS_PER_WORD;
4179 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
4181 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4185 /* If this is the trailing part of a word, only load that much into
4186 the register. Otherwise load the whole register. Note that in
4187 the latter case we may pick up unwanted bits. It's not a problem
4188 at the moment but may wish to revisit. */
4190 if (intoffset % BITS_PER_WORD != 0)
4191 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4196 intoffset /= BITS_PER_UNIT;
4199 regno = parms->regbase + this_slotno;
4200 reg = gen_rtx_REG (mode, regno);
4201 XVECEXP (parms->ret, 0, parms->nregs)
4202 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4205 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4209 while (intslots > 0);
4212 /* A subroutine of function_arg_record_value. Traverse the structure
4213 recursively and assign bits to floating point registers. Track which
4214 bits in between need integer registers; invoke function_arg_record_value_3
4215 to make that happen. */
4218 function_arg_record_value_2 (type, startbitpos, parms)
4220 HOST_WIDE_INT startbitpos;
4221 struct function_arg_record_value_parms *parms;
4226 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4228 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4235 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4237 if (TREE_CODE (field) == FIELD_DECL)
4239 HOST_WIDE_INT bitpos = startbitpos;
4241 if (DECL_SIZE (field) != 0
4242 && host_integerp (bit_position (field), 1))
4243 bitpos += int_bit_position (field);
4245 /* ??? FIXME: else assume zero offset. */
4247 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4248 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
4249 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4254 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
4257 function_arg_record_value_3 (bitpos, parms);
4259 reg = gen_rtx_REG (DECL_MODE (field),
4260 (SPARC_FP_ARG_FIRST + this_slotno * 2
4261 + (DECL_MODE (field) == SFmode
4262 && (bitpos & 32) != 0)));
4263 XVECEXP (parms->ret, 0, parms->nregs)
4264 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4265 GEN_INT (bitpos / BITS_PER_UNIT));
4270 if (parms->intoffset == -1)
4271 parms->intoffset = bitpos;
4277 /* Used by function_arg and function_value to implement the complex
4278 Sparc64 structure calling conventions. */
4281 function_arg_record_value (type, mode, slotno, named, regbase)
4283 enum machine_mode mode;
4284 int slotno, named, regbase;
4286 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4287 struct function_arg_record_value_parms parms;
4290 parms.ret = NULL_RTX;
4291 parms.slotno = slotno;
4292 parms.named = named;
4293 parms.regbase = regbase;
4295 /* Compute how many registers we need. */
4297 parms.intoffset = 0;
4298 function_arg_record_value_1 (type, 0, &parms);
4300 if (parms.intoffset != -1)
4302 unsigned int startbit, endbit;
4303 int intslots, this_slotno;
4305 startbit = parms.intoffset & -BITS_PER_WORD;
4306 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4307 intslots = (endbit - startbit) / BITS_PER_WORD;
4308 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
4310 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4311 intslots = MAX (intslots, 0);
4313 parms.nregs += intslots;
4315 nregs = parms.nregs;
4317 /* Allocate the vector and handle some annoying special cases. */
4320 /* ??? Empty structure has no value? Duh? */
4323 /* Though there's nothing really to store, return a word register
4324 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4325 leads to breakage due to the fact that there are zero bytes to
4327 return gen_rtx_REG (mode, regbase);
4331 /* ??? C++ has structures with no fields, and yet a size. Give up
4332 for now and pass everything back in integer registers. */
4333 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4335 if (nregs + slotno > SPARC_INT_ARG_MAX)
4336 nregs = SPARC_INT_ARG_MAX - slotno;
4341 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
4343 /* Fill in the entries. */
4345 parms.intoffset = 0;
4346 function_arg_record_value_2 (type, 0, &parms);
4347 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
4349 if (parms.nregs != nregs)
4355 /* Handle the FUNCTION_ARG macro.
4356 Determine where to put an argument to a function.
4357 Value is zero to push the argument on the stack,
4358 or a hard register in which to store the argument.
4360 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4361 the preceding args and about the function being called.
4362 MODE is the argument's machine mode.
4363 TYPE is the data type of the argument (as a tree).
4364 This is null for libcalls where that information may
4366 NAMED is nonzero if this argument is a named parameter
4367 (otherwise it is an extra parameter matching an ellipsis).
4368 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4371 function_arg (cum, mode, type, named, incoming_p)
4372 const CUMULATIVE_ARGS *cum;
4373 enum machine_mode mode;
4378 int regbase = (incoming_p
4379 ? SPARC_INCOMING_INT_ARG_FIRST
4380 : SPARC_OUTGOING_INT_ARG_FIRST);
4381 int slotno, regno, padding;
4384 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
4392 reg = gen_rtx_REG (mode, regno);
4396 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4397 but also have the slot allocated for them.
4398 If no prototype is in scope fp values in register slots get passed
4399 in two places, either fp regs and int regs or fp regs and memory. */
4400 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4401 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4402 && SPARC_FP_REG_P (regno))
4404 reg = gen_rtx_REG (mode, regno);
4405 if (cum->prototype_p || cum->libcall_p)
4407 /* "* 2" because fp reg numbers are recorded in 4 byte
4410 /* ??? This will cause the value to be passed in the fp reg and
4411 in the stack. When a prototype exists we want to pass the
4412 value in the reg but reserve space on the stack. That's an
4413 optimization, and is deferred [for a bit]. */
4414 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
4415 return gen_rtx_PARALLEL (mode,
4417 gen_rtx_EXPR_LIST (VOIDmode,
4418 NULL_RTX, const0_rtx),
4419 gen_rtx_EXPR_LIST (VOIDmode,
4423 /* ??? It seems that passing back a register even when past
4424 the area declared by REG_PARM_STACK_SPACE will allocate
4425 space appropriately, and will not copy the data onto the
4426 stack, exactly as we desire.
4428 This is due to locate_and_pad_parm being called in
4429 expand_call whenever reg_parm_stack_space > 0, which
4430 while benefical to our example here, would seem to be
4431 in error from what had been intended. Ho hum... -- r~ */
4439 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
4443 /* On incoming, we don't need to know that the value
4444 is passed in %f0 and %i0, and it confuses other parts
4445 causing needless spillage even on the simplest cases. */
4449 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
4450 + (regno - SPARC_FP_ARG_FIRST) / 2);
4452 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4453 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
4455 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4459 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4460 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4461 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4465 else if (type && TREE_CODE (type) == RECORD_TYPE)
4467 /* Structures up to 16 bytes in size are passed in arg slots on the
4468 stack and are promoted to registers where possible. */
4470 if (int_size_in_bytes (type) > 16)
4471 abort (); /* shouldn't get here */
4473 return function_arg_record_value (type, mode, slotno, named, regbase);
4475 else if (type && TREE_CODE (type) == UNION_TYPE)
4477 enum machine_mode mode;
4478 int bytes = int_size_in_bytes (type);
4483 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4484 reg = gen_rtx_REG (mode, regno);
4488 /* Scalar or complex int. */
4489 reg = gen_rtx_REG (mode, regno);
4495 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4496 For an arg passed partly in registers and partly in memory,
4497 this is the number of registers used.
4498 For args passed entirely in registers or entirely in memory, zero.
4500 Any arg that starts in the first 6 regs but won't entirely fit in them
4501 needs partial registers on v8. On v9, structures with integer
4502 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4503 values that begin in the last fp reg [where "last fp reg" varies with the
4504 mode] will be split between that reg and memory. */
4507 function_arg_partial_nregs (cum, mode, type, named)
4508 const CUMULATIVE_ARGS *cum;
4509 enum machine_mode mode;
4513 int slotno, regno, padding;
4515 /* We pass 0 for incoming_p here, it doesn't matter. */
4516 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4523 if ((slotno + (mode == BLKmode
4524 ? ROUND_ADVANCE (int_size_in_bytes (type))
4525 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
4526 > NPARM_REGS (SImode))
4527 return NPARM_REGS (SImode) - slotno;
4532 if (type && AGGREGATE_TYPE_P (type))
4534 int size = int_size_in_bytes (type);
4535 int align = TYPE_ALIGN (type);
4538 slotno += slotno & 1;
4539 if (size > 8 && size <= 16
4540 && slotno == SPARC_INT_ARG_MAX - 1)
4543 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
4544 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4547 if (GET_MODE_ALIGNMENT (mode) == 128)
4549 slotno += slotno & 1;
4550 if (slotno == SPARC_INT_ARG_MAX - 2)
4555 if (slotno == SPARC_INT_ARG_MAX - 1)
4559 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4561 if (GET_MODE_ALIGNMENT (mode) == 128)
4562 slotno += slotno & 1;
4563 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
4571 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
4572 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
4573 quad-precision floats by invisible reference.
4574 v9: Aggregates greater than 16 bytes are passed by reference.
4575 For Pascal, also pass arrays by reference. */
4578 function_arg_pass_by_reference (cum, mode, type, named)
4579 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
4580 enum machine_mode mode;
4582 int named ATTRIBUTE_UNUSED;
4586 return ((type && AGGREGATE_TYPE_P (type))
4587 || mode == TFmode || mode == TCmode);
4591 return ((type && TREE_CODE (type) == ARRAY_TYPE)
4592 /* Consider complex values as aggregates, so care for TCmode. */
4593 || GET_MODE_SIZE (mode) > 16
4594 || (type && AGGREGATE_TYPE_P (type)
4595 && int_size_in_bytes (type) > 16));
4599 /* Handle the FUNCTION_ARG_ADVANCE macro.
4600 Update the data in CUM to advance over an argument
4601 of mode MODE and data type TYPE.
4602 TYPE is null for libcalls where that information may not be available. */
4605 function_arg_advance (cum, mode, type, named)
4606 CUMULATIVE_ARGS *cum;
4607 enum machine_mode mode;
4611 int slotno, regno, padding;
4613 /* We pass 0 for incoming_p here, it doesn't matter. */
4614 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4616 /* If register required leading padding, add it. */
4618 cum->words += padding;
4622 cum->words += (mode != BLKmode
4623 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4624 : ROUND_ADVANCE (int_size_in_bytes (type)));
4628 if (type && AGGREGATE_TYPE_P (type))
4630 int size = int_size_in_bytes (type);
4634 else if (size <= 16)
4636 else /* passed by reference */
4639 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
4643 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4645 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
4649 cum->words += (mode != BLKmode
4650 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4651 : ROUND_ADVANCE (int_size_in_bytes (type)));
4656 /* Handle the FUNCTION_ARG_PADDING macro.
4657 For the 64 bit ABI structs are always stored left shifted in their
4661 function_arg_padding (mode, type)
4662 enum machine_mode mode;
4665 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
4668 /* This is the default definition. */
4669 return (! BYTES_BIG_ENDIAN
4672 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
4673 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
4674 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
4675 ? downward : upward));
4678 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
4679 For v9, function return values are subject to the same rules as arguments,
4680 except that up to 32-bytes may be returned in registers. */
4683 function_value (type, mode, incoming_p)
4685 enum machine_mode mode;
4689 int regbase = (incoming_p
4690 ? SPARC_OUTGOING_INT_ARG_FIRST
4691 : SPARC_INCOMING_INT_ARG_FIRST);
4693 if (TARGET_ARCH64 && type)
4695 if (TREE_CODE (type) == RECORD_TYPE)
4697 /* Structures up to 32 bytes in size are passed in registers,
4698 promoted to fp registers where possible. */
4700 if (int_size_in_bytes (type) > 32)
4701 abort (); /* shouldn't get here */
4703 return function_arg_record_value (type, mode, 0, 1, regbase);
4705 else if (AGGREGATE_TYPE_P (type))
4707 /* All other aggregate types are passed in an integer register
4708 in a mode corresponding to the size of the type. */
4709 HOST_WIDE_INT bytes = int_size_in_bytes (type);
4714 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4719 && GET_MODE_CLASS (mode) == MODE_INT
4720 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
4721 && type && ! AGGREGATE_TYPE_P (type))
4725 regno = BASE_RETURN_VALUE_REG (mode);
4727 regno = BASE_OUTGOING_VALUE_REG (mode);
4729 return gen_rtx_REG (mode, regno);
4732 /* Do what is necessary for `va_start'. We look at the current function
4733 to determine if stdarg or varargs is used and return the address of
4734 the first unnamed parameter. */
4737 sparc_builtin_saveregs ()
4739 int first_reg = current_function_args_info.words;
4743 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
4744 emit_move_insn (gen_rtx_MEM (word_mode,
4745 gen_rtx_PLUS (Pmode,
4747 GEN_INT (STACK_POINTER_OFFSET
4748 + UNITS_PER_WORD * regno))),
4749 gen_rtx_REG (word_mode,
4750 BASE_INCOMING_ARG_REG (word_mode) + regno));
4752 address = gen_rtx_PLUS (Pmode,
4754 GEN_INT (STACK_POINTER_OFFSET
4755 + UNITS_PER_WORD * first_reg));
4757 if (current_function_check_memory_usage
4758 && first_reg < NPARM_REGS (word_mode))
4759 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4761 GEN_INT (UNITS_PER_WORD
4762 * (NPARM_REGS (word_mode) - first_reg)),
4763 TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW),
4764 TYPE_MODE (integer_type_node));
4769 /* Implement `va_start' for varargs and stdarg. */
4772 sparc_va_start (stdarg_p, valist, nextarg)
4773 int stdarg_p ATTRIBUTE_UNUSED;
4777 nextarg = expand_builtin_saveregs ();
4778 std_expand_builtin_va_start (1, valist, nextarg);
4781 /* Implement `va_arg'. */
4784 sparc_va_arg (valist, type)
4787 HOST_WIDE_INT size, rsize, align;
4792 /* Round up sizeof(type) to a word. */
4793 size = int_size_in_bytes (type);
4794 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4799 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
4800 align = 2 * UNITS_PER_WORD;
4802 if (AGGREGATE_TYPE_P (type))
4807 size = rsize = UNITS_PER_WORD;
4815 if (AGGREGATE_TYPE_P (type)
4816 || TYPE_MODE (type) == TFmode
4817 || TYPE_MODE (type) == TCmode)
4820 size = rsize = UNITS_PER_WORD;
4827 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4828 build_int_2 (align - 1, 0)));
4829 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
4830 build_int_2 (-align, -1)));
4833 addr = incr = save_expr (incr);
4834 if (BYTES_BIG_ENDIAN && size < rsize)
4836 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4837 build_int_2 (rsize - size, 0)));
4839 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4840 build_int_2 (rsize, 0)));
4842 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
4843 TREE_SIDE_EFFECTS (incr) = 1;
4844 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
4846 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
4848 /* If the address isn't aligned properly for the type,
4849 we may need to copy to a temporary.
4850 FIXME: This is inefficient. Usually we can do this
4853 && TYPE_ALIGN (type) > BITS_PER_WORD
4856 /* FIXME: We really need to specify that the temporary is live
4857 for the whole function because expand_builtin_va_arg wants
4858 the alias set to be get_varargs_alias_set (), but in this
4859 case the alias set is that for TYPE and if the memory gets
4860 reused it will be reused with alias set TYPE. */
4861 rtx tmp = assign_temp (type, 0, 1, 0);
4864 addr_rtx = force_reg (Pmode, addr_rtx);
4865 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
4866 MEM_ALIAS_SET (addr_rtx) = get_varargs_alias_set ();
4867 tmp = shallow_copy_rtx (tmp);
4868 PUT_MODE (tmp, BLKmode);
4869 MEM_ALIAS_SET (tmp) = 0;
4871 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
4873 if (dest_addr != NULL_RTX)
4874 addr_rtx = dest_addr;
4876 addr_rtx = XCEXP (tmp, 0, MEM);
4881 addr_rtx = force_reg (Pmode, addr_rtx);
4882 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
4883 MEM_ALIAS_SET (addr_rtx) = get_varargs_alias_set ();
4889 /* Return the string to output a conditional branch to LABEL, which is
4890 the operand number of the label. OP is the conditional expression.
4891 XEXP (OP, 0) is assumed to be a condition code register (integer or
4892 floating point) and its mode specifies what kind of comparison we made.
4894 REVERSED is non-zero if we should reverse the sense of the comparison.
4896 ANNUL is non-zero if we should generate an annulling branch.
4898 NOOP is non-zero if we have to follow this branch by a noop.
4900 INSN, if set, is the insn. */
4903 output_cbranch (op, label, reversed, annul, noop, insn)
4906 int reversed, annul, noop;
4909 static char string[32];
4910 enum rtx_code code = GET_CODE (op);
4911 rtx cc_reg = XEXP (op, 0);
4912 enum machine_mode mode = GET_MODE (cc_reg);
4913 static char v8_labelno[] = "%lX";
4914 static char v9_icc_labelno[] = "%%icc, %lX";
4915 static char v9_xcc_labelno[] = "%%xcc, %lX";
4916 static char v9_fcc_labelno[] = "%%fccX, %lY";
4919 int labeloff, spaces = 8;
4923 /* Reversal of FP compares takes care -- an ordered compare
4924 becomes an unordered compare and vice versa. */
4925 if (mode == CCFPmode || mode == CCFPEmode)
4926 code = reverse_condition_maybe_unordered (code);
4928 code = reverse_condition (code);
4931 /* Start by writing the branch condition. */
4932 if (mode == CCFPmode || mode == CCFPEmode)
4983 /* ??? !v9: FP branches cannot be preceded by another floating point
4984 insn. Because there is currently no concept of pre-delay slots,
4985 we can fix this only by always emitting a nop before a floating
4990 strcpy (string, "nop\n\t");
4991 strcat (string, branch);
5004 if (mode == CC_NOOVmode)
5016 if (mode == CC_NOOVmode)
5037 strcpy (string, branch);
5039 spaces -= strlen (branch);
5041 /* Now add the annulling, the label, and a possible noop. */
5044 strcat (string, ",a");
5051 labelno = v8_labelno;
5057 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
5060 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
5065 if (mode == CCFPmode || mode == CCFPEmode)
5068 labelno = v9_fcc_labelno;
5069 /* Set the char indicating the number of the fcc reg to use. */
5070 labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5072 else if (mode == CCXmode || mode == CCX_NOOVmode)
5073 labelno = v9_xcc_labelno;
5075 labelno = v9_icc_labelno;
5077 /* Set the char indicating the number of the operand containing the
5079 labelno[labeloff] = label + '0';
5081 strcat (string, "\t");
5083 strcat (string, " ");
5084 strcat (string, labelno);
5087 strcat (string, "\n\tnop");
5092 /* Emit a library call comparison between floating point X and Y.
5093 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5094 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5095 values as arguments instead of the TFmode registers themselves,
5096 that's why we cannot call emit_float_lib_cmp. */
5098 sparc_emit_float_lib_cmp (x, y, comparison)
5100 enum rtx_code comparison;
5103 rtx slot0, slot1, result, tem, tem2;
5104 enum machine_mode mode;
5109 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
5113 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
5117 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
5121 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
5125 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
5129 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
5140 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
5150 if (GET_CODE (x) != MEM)
5152 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5153 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
5158 if (GET_CODE (y) != MEM)
5160 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5161 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
5166 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), 1,
5168 XEXP (slot0, 0), Pmode,
5169 XEXP (slot1, 0), Pmode);
5175 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), 1,
5177 x, TFmode, y, TFmode);
5183 /* Immediately move the result of the libcall into a pseudo
5184 register so reload doesn't clobber the value if it needs
5185 the return register for a spill reg. */
5186 result = gen_reg_rtx (mode);
5187 emit_move_insn (result, hard_libcall_value (mode));
5192 emit_cmp_insn (result, const0_rtx, NE,
5193 NULL_RTX, mode, 0, 0);
5197 emit_cmp_insn (result, GEN_INT(3),
5198 (comparison == UNORDERED) ? EQ : NE,
5199 NULL_RTX, mode, 0, 0);
5203 emit_cmp_insn (result, const1_rtx,
5204 (comparison == UNGT) ? GT : NE,
5205 NULL_RTX, mode, 0, 0);
5208 emit_cmp_insn (result, const2_rtx, NE,
5209 NULL_RTX, mode, 0, 0);
5212 tem = gen_reg_rtx (mode);
5214 emit_insn (gen_andsi3 (tem, result, const1_rtx));
5216 emit_insn (gen_anddi3 (tem, result, const1_rtx));
5217 emit_cmp_insn (tem, const0_rtx, NE,
5218 NULL_RTX, mode, 0, 0);
5222 tem = gen_reg_rtx (mode);
5224 emit_insn (gen_addsi3 (tem, result, const1_rtx));
5226 emit_insn (gen_adddi3 (tem, result, const1_rtx));
5227 tem2 = gen_reg_rtx (mode);
5229 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
5231 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
5232 emit_cmp_insn (tem2, const0_rtx,
5233 (comparison == UNEQ) ? EQ : NE,
5234 NULL_RTX, mode, 0, 0);
5239 /* Return the string to output a conditional branch to LABEL, testing
5240 register REG. LABEL is the operand number of the label; REG is the
5241 operand number of the reg. OP is the conditional expression. The mode
5242 of REG says what kind of comparison we made.
5244 REVERSED is non-zero if we should reverse the sense of the comparison.
5246 ANNUL is non-zero if we should generate an annulling branch.
5248 NOOP is non-zero if we have to follow this branch by a noop. */
5251 output_v9branch (op, reg, label, reversed, annul, noop, insn)
5254 int reversed, annul, noop;
5257 static char string[20];
5258 enum rtx_code code = GET_CODE (op);
5259 enum machine_mode mode = GET_MODE (XEXP (op, 0));
5260 static char labelno[] = "%X, %lX";
5264 /* If not floating-point or if EQ or NE, we can just reverse the code. */
5266 code = reverse_condition (code), reversed = 0;
5268 /* Only 64 bit versions of these instructions exist. */
5272 /* Start by writing the branch condition. */
5277 strcpy (string, "brnz");
5282 strcpy (string, "brz");
5287 strcpy (string, "brgez");
5292 strcpy (string, "brlz");
5297 strcpy (string, "brlez");
5302 strcpy (string, "brgz");
5310 /* Now add the annulling, reg, label, and nop. */
5313 strcat (string, ",a");
5317 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
5320 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
5324 labelno[1] = reg + '0';
5325 labelno[6] = label + '0';
5327 strcat (string, "\t");
5329 strcat (string, " ");
5330 strcat (string, labelno);
5333 strcat (string, "\n\tnop");
5338 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
5339 Such instructions cannot be used in the delay slot of return insn on v9.
5340 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
5344 epilogue_renumber (where, test)
5345 register rtx *where;
5348 register const char *fmt;
5350 register enum rtx_code code;
5355 code = GET_CODE (*where);
5360 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
5362 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
5363 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
5375 fmt = GET_RTX_FORMAT (code);
5377 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5382 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5383 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
5386 else if (fmt[i] == 'e'
5387 && epilogue_renumber (&(XEXP (*where, i)), test))
5393 /* Output assembler code to return from a function. */
5396 output_return (operands)
5399 rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0;
5403 operands[0] = leaf_label;
5406 else if (current_function_uses_only_leaf_regs)
5408 /* No delay slot in a leaf function. */
5412 /* If we didn't allocate a frame pointer for the current function,
5413 the stack pointer might have been adjusted. Output code to
5416 operands[0] = GEN_INT (actual_fsize);
5418 /* Use sub of negated value in first two cases instead of add to
5419 allow actual_fsize == 4096. */
5421 if (actual_fsize <= 4096)
5423 if (SKIP_CALLERS_UNIMP_P)
5424 return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
5426 return "retl\n\tsub\t%%sp, -%0, %%sp";
5428 else if (actual_fsize <= 8192)
5430 operands[0] = GEN_INT (actual_fsize - 4096);
5431 if (SKIP_CALLERS_UNIMP_P)
5432 return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
5434 return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
5436 else if (SKIP_CALLERS_UNIMP_P)
5438 if ((actual_fsize & 0x3ff) != 0)
5439 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
5441 return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
5445 if ((actual_fsize & 0x3ff) != 0)
5446 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tretl\n\tadd\t%%sp, %%g1, %%sp";
5448 return "sethi\t%%hi(%a0), %%g1\n\tretl\n\tadd\t%%sp, %%g1, %%sp";
5455 epilogue_renumber (&SET_DEST (PATTERN (delay)), 0);
5456 epilogue_renumber (&SET_SRC (PATTERN (delay)), 0);
5458 if (SKIP_CALLERS_UNIMP_P)
5459 return "return\t%%i7+12%#";
5461 return "return\t%%i7+8%#";
5467 if (SKIP_CALLERS_UNIMP_P)
5468 return "jmp\t%%i7+12\n\trestore";
5470 return "ret\n\trestore";
5474 /* Leaf functions and non-leaf functions have different needs. */
5477 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
5480 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
5482 static int *reg_alloc_orders[] = {
5483 reg_leaf_alloc_order,
5484 reg_nonleaf_alloc_order};
5487 order_regs_for_local_alloc ()
5489 static int last_order_nonleaf = 1;
5491 if (regs_ever_live[15] != last_order_nonleaf)
5493 last_order_nonleaf = !last_order_nonleaf;
5494 memcpy ((char *) reg_alloc_order,
5495 (char *) reg_alloc_orders[last_order_nonleaf],
5496 FIRST_PSEUDO_REGISTER * sizeof (int));
5500 /* Return 1 if REG and MEM are legitimate enough to allow the various
5501 mem<-->reg splits to be run. */
5504 sparc_splitdi_legitimate (reg, mem)
5508 /* Punt if we are here by mistake. */
5509 if (! reload_completed)
5512 /* We must have an offsettable memory reference. */
5513 if (! offsettable_memref_p (mem))
5516 /* If we have legitimate args for ldd/std, we do not want
5517 the split to happen. */
5518 if ((REGNO (reg) % 2) == 0
5519 && mem_min_alignment (mem, 8))
5526 /* Return 1 if x and y are some kind of REG and they refer to
5527 different hard registers. This test is guarenteed to be
5528 run after reload. */
5531 sparc_absnegfloat_split_legitimate (x, y)
5534 if (GET_CODE (x) == SUBREG)
5535 x = alter_subreg (x);
5536 if (GET_CODE (x) != REG)
5538 if (GET_CODE (y) == SUBREG)
5539 y = alter_subreg (y);
5540 if (GET_CODE (y) != REG)
5542 if (REGNO (x) == REGNO (y))
5547 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
5548 This makes them candidates for using ldd and std insns.
5550 Note reg1 and reg2 *must* be hard registers. */
5553 registers_ok_for_ldd_peep (reg1, reg2)
5556 /* We might have been passed a SUBREG. */
5557 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
5560 if (REGNO (reg1) % 2 != 0)
5563 /* Integer ldd is deprecated in SPARC V9 */
5564 if (TARGET_V9 && REGNO (reg1) < 32)
5567 return (REGNO (reg1) == REGNO (reg2) - 1);
5570 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
5573 This can only happen when addr1 and addr2 are consecutive memory
5574 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
5575 64 bit boundary (addr1 % 8 == 0).
5577 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
5578 registers are assumed to *never* be properly aligned and are
5581 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
5582 need only check that the offset for addr1 % 8 == 0. */
5585 addrs_ok_for_ldd_peep (addr1, addr2)
5590 /* Extract a register number and offset (if used) from the first addr. */
5591 if (GET_CODE (addr1) == PLUS)
5593 /* If not a REG, return zero. */
5594 if (GET_CODE (XEXP (addr1, 0)) != REG)
5598 reg1 = REGNO (XEXP (addr1, 0));
5599 /* The offset must be constant! */
5600 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
5602 offset1 = INTVAL (XEXP (addr1, 1));
5605 else if (GET_CODE (addr1) != REG)
5609 reg1 = REGNO (addr1);
5610 /* This was a simple (mem (reg)) expression. Offset is 0. */
5614 /* Make sure the second address is a (mem (plus (reg) (const_int). */
5615 if (GET_CODE (addr2) != PLUS)
5618 if (GET_CODE (XEXP (addr2, 0)) != REG
5619 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
5622 /* Only %fp and %sp are allowed. Additionally both addresses must
5623 use the same register. */
5624 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
5627 if (reg1 != REGNO (XEXP (addr2, 0)))
5630 /* The first offset must be evenly divisible by 8 to ensure the
5631 address is 64 bit aligned. */
5632 if (offset1 % 8 != 0)
5635 /* The offset for the second addr must be 4 more than the first addr. */
5636 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
5639 /* All the tests passed. addr1 and addr2 are valid for ldd and std
5644 /* Return 1 if reg is a pseudo, or is the first register in
5645 a hard register pair. This makes it a candidate for use in
5646 ldd and std insns. */
5649 register_ok_for_ldd (reg)
5652 /* We might have been passed a SUBREG. */
5653 if (GET_CODE (reg) != REG)
5656 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
5657 return (REGNO (reg) % 2 == 0);
5662 /* Print operand X (an rtx) in assembler syntax to file FILE.
5663 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
5664 For `%' followed by punctuation, CODE is the punctuation and X is null. */
5667 print_operand (file, x, code)
5675 /* Output a 'nop' if there's nothing for the delay slot. */
5676 if (dbr_sequence_length () == 0)
5677 fputs ("\n\t nop", file);
5680 /* Output an annul flag if there's nothing for the delay slot and we
5681 are optimizing. This is always used with '(' below. */
5682 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
5683 this is a dbx bug. So, we only do this when optimizing. */
5684 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
5685 Always emit a nop in case the next instruction is a branch. */
5686 if (dbr_sequence_length () == 0
5687 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
5691 /* Output a 'nop' if there's nothing for the delay slot and we are
5692 not optimizing. This is always used with '*' above. */
5693 if (dbr_sequence_length () == 0
5694 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
5695 fputs ("\n\t nop", file);
5698 /* Output the Embedded Medium/Anywhere code model base register. */
5699 fputs (EMBMEDANY_BASE_REG, file);
5702 /* Print out what we are using as the frame pointer. This might
5703 be %fp, or might be %sp+offset. */
5704 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
5705 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
5708 /* Adjust the operand to take into account a RESTORE operation. */
5709 if (GET_CODE (x) == CONST_INT)
5711 else if (GET_CODE (x) != REG)
5712 output_operand_lossage ("Invalid %%Y operand");
5713 else if (REGNO (x) < 8)
5714 fputs (reg_names[REGNO (x)], file);
5715 else if (REGNO (x) >= 24 && REGNO (x) < 32)
5716 fputs (reg_names[REGNO (x)-16], file);
5718 output_operand_lossage ("Invalid %%Y operand");
5721 /* Print out the low order register name of a register pair. */
5722 if (WORDS_BIG_ENDIAN)
5723 fputs (reg_names[REGNO (x)+1], file);
5725 fputs (reg_names[REGNO (x)], file);
5728 /* Print out the high order register name of a register pair. */
5729 if (WORDS_BIG_ENDIAN)
5730 fputs (reg_names[REGNO (x)], file);
5732 fputs (reg_names[REGNO (x)+1], file);
5735 /* Print out the second register name of a register pair or quad.
5736 I.e., R (%o0) => %o1. */
5737 fputs (reg_names[REGNO (x)+1], file);
5740 /* Print out the third register name of a register quad.
5741 I.e., S (%o0) => %o2. */
5742 fputs (reg_names[REGNO (x)+2], file);
5745 /* Print out the fourth register name of a register quad.
5746 I.e., T (%o0) => %o3. */
5747 fputs (reg_names[REGNO (x)+3], file);
5750 /* Print a condition code register. */
5751 if (REGNO (x) == SPARC_ICC_REG)
5753 /* We don't handle CC[X]_NOOVmode because they're not supposed
5755 if (GET_MODE (x) == CCmode)
5756 fputs ("%icc", file);
5757 else if (GET_MODE (x) == CCXmode)
5758 fputs ("%xcc", file);
5763 /* %fccN register */
5764 fputs (reg_names[REGNO (x)], file);
5767 /* Print the operand's address only. */
5768 output_address (XEXP (x, 0));
5771 /* In this case we need a register. Use %g0 if the
5772 operand is const0_rtx. */
5774 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
5776 fputs ("%g0", file);
5783 switch (GET_CODE (x))
5785 case IOR: fputs ("or", file); break;
5786 case AND: fputs ("and", file); break;
5787 case XOR: fputs ("xor", file); break;
5788 default: output_operand_lossage ("Invalid %%A operand");
5793 switch (GET_CODE (x))
5795 case IOR: fputs ("orn", file); break;
5796 case AND: fputs ("andn", file); break;
5797 case XOR: fputs ("xnor", file); break;
5798 default: output_operand_lossage ("Invalid %%B operand");
5802 /* These are used by the conditional move instructions. */
5806 enum rtx_code rc = GET_CODE (x);
5810 enum machine_mode mode = GET_MODE (XEXP (x, 0));
5811 if (mode == CCFPmode || mode == CCFPEmode)
5812 rc = reverse_condition_maybe_unordered (GET_CODE (x));
5814 rc = reverse_condition (GET_CODE (x));
5818 case NE: fputs ("ne", file); break;
5819 case EQ: fputs ("e", file); break;
5820 case GE: fputs ("ge", file); break;
5821 case GT: fputs ("g", file); break;
5822 case LE: fputs ("le", file); break;
5823 case LT: fputs ("l", file); break;
5824 case GEU: fputs ("geu", file); break;
5825 case GTU: fputs ("gu", file); break;
5826 case LEU: fputs ("leu", file); break;
5827 case LTU: fputs ("lu", file); break;
5828 case LTGT: fputs ("lg", file); break;
5829 case UNORDERED: fputs ("u", file); break;
5830 case ORDERED: fputs ("o", file); break;
5831 case UNLT: fputs ("ul", file); break;
5832 case UNLE: fputs ("ule", file); break;
5833 case UNGT: fputs ("ug", file); break;
5834 case UNGE: fputs ("uge", file); break;
5835 case UNEQ: fputs ("ue", file); break;
5836 default: output_operand_lossage (code == 'c'
5837 ? "Invalid %%c operand"
5838 : "Invalid %%C operand");
5843 /* These are used by the movr instruction pattern. */
5847 enum rtx_code rc = (code == 'd'
5848 ? reverse_condition (GET_CODE (x))
5852 case NE: fputs ("ne", file); break;
5853 case EQ: fputs ("e", file); break;
5854 case GE: fputs ("gez", file); break;
5855 case LT: fputs ("lz", file); break;
5856 case LE: fputs ("lez", file); break;
5857 case GT: fputs ("gz", file); break;
5858 default: output_operand_lossage (code == 'd'
5859 ? "Invalid %%d operand"
5860 : "Invalid %%D operand");
5867 /* Print a sign-extended character. */
5868 int i = INTVAL (x) & 0xff;
5871 fprintf (file, "%d", i);
5876 /* Operand must be a MEM; write its address. */
5877 if (GET_CODE (x) != MEM)
5878 output_operand_lossage ("Invalid %%f operand");
5879 output_address (XEXP (x, 0));
5883 /* Do nothing special. */
5887 /* Undocumented flag. */
5888 output_operand_lossage ("invalid operand output code");
5891 if (GET_CODE (x) == REG)
5892 fputs (reg_names[REGNO (x)], file);
5893 else if (GET_CODE (x) == MEM)
5896 /* Poor Sun assembler doesn't understand absolute addressing. */
5897 if (CONSTANT_P (XEXP (x, 0)))
5898 fputs ("%g0+", file);
5899 output_address (XEXP (x, 0));
5902 else if (GET_CODE (x) == HIGH)
5904 fputs ("%hi(", file);
5905 output_addr_const (file, XEXP (x, 0));
5908 else if (GET_CODE (x) == LO_SUM)
5910 print_operand (file, XEXP (x, 0), 0);
5911 if (TARGET_CM_MEDMID)
5912 fputs ("+%l44(", file);
5914 fputs ("+%lo(", file);
5915 output_addr_const (file, XEXP (x, 1));
5918 else if (GET_CODE (x) == CONST_DOUBLE
5919 && (GET_MODE (x) == VOIDmode
5920 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
5922 if (CONST_DOUBLE_HIGH (x) == 0)
5923 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
5924 else if (CONST_DOUBLE_HIGH (x) == -1
5925 && CONST_DOUBLE_LOW (x) < 0)
5926 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
5928 output_operand_lossage ("long long constant not a valid immediate operand");
5930 else if (GET_CODE (x) == CONST_DOUBLE)
5931 output_operand_lossage ("floating point constant not a valid immediate operand");
5932 else { output_addr_const (file, x); }
5935 /* This function outputs assembler code for VALUE to FILE, where VALUE is
5936 a 64 bit (DImode) value. */
5938 /* ??? If there is a 64 bit counterpart to .word that the assembler
5939 understands, then using that would simply this code greatly. */
5940 /* ??? We only output .xword's for symbols and only then in environments
5941 where the assembler can handle them. */
5944 output_double_int (file, value)
5948 if (GET_CODE (value) == CONST_INT)
5950 /* ??? This has endianness issues. */
5951 #if HOST_BITS_PER_WIDE_INT == 64
5952 HOST_WIDE_INT xword = INTVAL (value);
5953 HOST_WIDE_INT high, low;
5955 high = (xword >> 32) & 0xffffffff;
5956 low = xword & 0xffffffff;
5957 ASM_OUTPUT_INT (file, GEN_INT (high));
5958 ASM_OUTPUT_INT (file, GEN_INT (low));
5960 if (INTVAL (value) < 0)
5961 ASM_OUTPUT_INT (file, constm1_rtx);
5963 ASM_OUTPUT_INT (file, const0_rtx);
5964 ASM_OUTPUT_INT (file, value);
5967 else if (GET_CODE (value) == CONST_DOUBLE)
5969 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value)));
5970 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value)));
5972 else if (GET_CODE (value) == SYMBOL_REF
5973 || GET_CODE (value) == CONST
5974 || GET_CODE (value) == PLUS
5975 || (TARGET_ARCH64 &&
5976 (GET_CODE (value) == LABEL_REF
5977 || GET_CODE (value) == CODE_LABEL
5978 || GET_CODE (value) == MINUS)))
5982 ASM_OUTPUT_INT (file, const0_rtx);
5983 ASM_OUTPUT_INT (file, value);
5987 fprintf (file, "\t%s\t", ASM_LONGLONG);
5988 output_addr_const (file, value);
5989 fprintf (file, "\n");
5996 /* Return the value of a code used in the .proc pseudo-op that says
5997 what kind of result this function returns. For non-C types, we pick
5998 the closest C type. */
6000 #ifndef CHAR_TYPE_SIZE
6001 #define CHAR_TYPE_SIZE BITS_PER_UNIT
6004 #ifndef SHORT_TYPE_SIZE
6005 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6008 #ifndef INT_TYPE_SIZE
6009 #define INT_TYPE_SIZE BITS_PER_WORD
6012 #ifndef LONG_TYPE_SIZE
6013 #define LONG_TYPE_SIZE BITS_PER_WORD
6016 #ifndef LONG_LONG_TYPE_SIZE
6017 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6020 #ifndef FLOAT_TYPE_SIZE
6021 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6024 #ifndef DOUBLE_TYPE_SIZE
6025 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6028 #ifndef LONG_DOUBLE_TYPE_SIZE
6029 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6033 sparc_type_code (type)
6036 register unsigned long qualifiers = 0;
6037 register unsigned shift;
6039 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6040 setting more, since some assemblers will give an error for this. Also,
6041 we must be careful to avoid shifts of 32 bits or more to avoid getting
6042 unpredictable results. */
6044 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
6046 switch (TREE_CODE (type))
6052 qualifiers |= (3 << shift);
6057 qualifiers |= (2 << shift);
6061 case REFERENCE_TYPE:
6063 qualifiers |= (1 << shift);
6067 return (qualifiers | 8);
6070 case QUAL_UNION_TYPE:
6071 return (qualifiers | 9);
6074 return (qualifiers | 10);
6077 return (qualifiers | 16);
6080 /* If this is a range type, consider it to be the underlying
6082 if (TREE_TYPE (type) != 0)
6085 /* Carefully distinguish all the standard types of C,
6086 without messing up if the language is not C. We do this by
6087 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6088 look at both the names and the above fields, but that's redundant.
6089 Any type whose size is between two C types will be considered
6090 to be the wider of the two types. Also, we do not have a
6091 special code to use for "long long", so anything wider than
6092 long is treated the same. Note that we can't distinguish
6093 between "int" and "long" in this code if they are the same
6094 size, but that's fine, since neither can the assembler. */
6096 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
6097 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
6099 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
6100 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
6102 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
6103 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
6106 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
6109 /* If this is a range type, consider it to be the underlying
6111 if (TREE_TYPE (type) != 0)
6114 /* Carefully distinguish all the standard types of C,
6115 without messing up if the language is not C. */
6117 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
6118 return (qualifiers | 6);
6121 return (qualifiers | 7);
6123 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
6124 /* ??? We need to distinguish between double and float complex types,
6125 but I don't know how yet because I can't reach this code from
6126 existing front-ends. */
6127 return (qualifiers | 7); /* Who knows? */
6129 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
6130 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
6131 case FILE_TYPE: /* GNU Pascal FILE type. */
6132 case SET_TYPE: /* GNU Pascal SET type. */
6133 case LANG_TYPE: /* ? */
6137 abort (); /* Not a type! */
6144 /* Nested function support. */
6146 /* Emit RTL insns to initialize the variable parts of a trampoline.
6147 FNADDR is an RTX for the address of the function's pure code.
6148 CXT is an RTX for the static chain value for the function.
6150 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6151 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6152 (to store insns). This is a bit excessive. Perhaps a different
6153 mechanism would be better here.
6155 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6158 sparc_initialize_trampoline (tramp, fnaddr, cxt)
6159 rtx tramp, fnaddr, cxt;
6161 /* SPARC 32 bit trampoline:
6164 sethi %hi(static), %g2
6166 or %g2, %lo(static), %g2
6168 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6169 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6171 #ifdef TRANSFER_FROM_TRAMPOLINE
6172 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6173 0, VOIDmode, 1, tramp, Pmode);
6176 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
6177 expand_binop (SImode, ior_optab,
6178 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
6179 size_int (10), 0, 1),
6180 GEN_INT (0x03000000),
6181 NULL_RTX, 1, OPTAB_DIRECT));
6183 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6184 expand_binop (SImode, ior_optab,
6185 expand_shift (RSHIFT_EXPR, SImode, cxt,
6186 size_int (10), 0, 1),
6187 GEN_INT (0x05000000),
6188 NULL_RTX, 1, OPTAB_DIRECT));
6190 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6191 expand_binop (SImode, ior_optab,
6192 expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX),
6193 GEN_INT (0x81c06000),
6194 NULL_RTX, 1, OPTAB_DIRECT));
6196 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6197 expand_binop (SImode, ior_optab,
6198 expand_and (cxt, GEN_INT (0x3ff), NULL_RTX),
6199 GEN_INT (0x8410a000),
6200 NULL_RTX, 1, OPTAB_DIRECT));
6202 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
6203 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6204 aligned on a 16 byte boundary so one flush clears it all. */
6205 if (sparc_cpu != PROCESSOR_ULTRASPARC)
6206 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
6207 plus_constant (tramp, 8)))));
6210 /* The 64 bit version is simpler because it makes more sense to load the
6211 values as "immediate" data out of the trampoline. It's also easier since
6212 we can read the PC without clobbering a register. */
6215 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
6216 rtx tramp, fnaddr, cxt;
6218 #ifdef TRANSFER_FROM_TRAMPOLINE
6219 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6220 0, VOIDmode, 1, tramp, Pmode);
6231 emit_move_insn (gen_rtx_MEM (SImode, tramp),
6232 GEN_INT (0x83414000));
6233 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6234 GEN_INT (0xca586018));
6235 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6236 GEN_INT (0x81c14000));
6237 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6238 GEN_INT (0xca586010));
6239 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
6240 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
6241 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
6243 if (sparc_cpu != PROCESSOR_ULTRASPARC)
6244 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
6247 /* Subroutines to support a flat (single) register window calling
6250 /* Single-register window sparc stack frames look like:
6252 Before call After call
6253 +-----------------------+ +-----------------------+
6255 mem | caller's temps. | | caller's temps. |
6257 +-----------------------+ +-----------------------+
6259 | arguments on stack. | | arguments on stack. |
6261 +-----------------------+FP+92->+-----------------------+
6262 | 6 words to save | | 6 words to save |
6263 | arguments passed | | arguments passed |
6264 | in registers, even | | in registers, even |
6265 | if not passed. | | if not passed. |
6266 SP+68->+-----------------------+FP+68->+-----------------------+
6267 | 1 word struct addr | | 1 word struct addr |
6268 +-----------------------+FP+64->+-----------------------+
6270 | 16 word reg save area | | 16 word reg save area |
6272 SP->+-----------------------+ FP->+-----------------------+
6274 | fp/alu reg moves |
6275 FP-16->+-----------------------+
6279 +-----------------------+
6281 | fp register save |
6283 +-----------------------+
6285 | gp register save |
6287 +-----------------------+
6289 | alloca allocations |
6291 +-----------------------+
6293 | arguments on stack |
6295 SP+92->+-----------------------+
6297 | arguments passed |
6298 | in registers, even |
6299 low | if not passed. |
6300 memory SP+68->+-----------------------+
6301 | 1 word struct addr |
6302 SP+64->+-----------------------+
6304 I 16 word reg save area |
6306 SP->+-----------------------+ */
6308 /* Structure to be filled in by sparc_flat_compute_frame_size with register
6309 save masks, and offsets for the current function. */
6311 struct sparc_frame_info
6313 unsigned long total_size; /* # bytes that the entire frame takes up. */
6314 unsigned long var_size; /* # bytes that variables take up. */
6315 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6316 unsigned long extra_size; /* # bytes of extra gunk. */
6317 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6318 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6319 unsigned long gmask; /* Mask of saved gp registers. */
6320 unsigned long fmask; /* Mask of saved fp registers. */
6321 unsigned long reg_offset; /* Offset from new sp to store regs. */
6322 int initialized; /* Nonzero if frame size already calculated. */
6325 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6326 struct sparc_frame_info current_frame_info;
6328 /* Zero structure to initialize current_frame_info. */
6329 struct sparc_frame_info zero_frame_info;
6331 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6333 #define RETURN_ADDR_REGNUM 15
6334 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
6335 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6337 #define MUST_SAVE_REGISTER(regno) \
6338 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6339 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
6340 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6342 /* Return the bytes needed to compute the frame pointer from the current
6346 sparc_flat_compute_frame_size (size)
6347 int size; /* # of var. bytes allocated. */
6350 unsigned long total_size; /* # bytes that the entire frame takes up. */
6351 unsigned long var_size; /* # bytes that variables take up. */
6352 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6353 unsigned long extra_size; /* # extra bytes. */
6354 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6355 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6356 unsigned long gmask; /* Mask of saved gp registers. */
6357 unsigned long fmask; /* Mask of saved fp registers. */
6358 unsigned long reg_offset; /* Offset to register save area. */
6359 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
6361 /* This is the size of the 16 word reg save area, 1 word struct addr
6362 area, and 4 word fp/alu register copy area. */
6363 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
6373 if (!leaf_function_p ())
6375 /* Also include the size needed for the 6 parameter registers. */
6376 args_size = current_function_outgoing_args_size + 24;
6378 total_size = var_size + args_size;
6380 /* Calculate space needed for gp registers. */
6381 for (regno = 1; regno <= 31; regno++)
6383 if (MUST_SAVE_REGISTER (regno))
6385 /* If we need to save two regs in a row, ensure there's room to bump
6386 up the address to align it to a doubleword boundary. */
6387 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
6389 if (gp_reg_size % 8 != 0)
6391 gp_reg_size += 2 * UNITS_PER_WORD;
6392 gmask |= 3 << regno;
6398 gp_reg_size += UNITS_PER_WORD;
6399 gmask |= 1 << regno;
6404 /* Calculate space needed for fp registers. */
6405 for (regno = 32; regno <= 63; regno++)
6407 if (regs_ever_live[regno] && !call_used_regs[regno])
6409 fp_reg_size += UNITS_PER_WORD;
6410 fmask |= 1 << (regno - 32);
6417 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
6418 /* Ensure save area is 8 byte aligned if we need it. */
6420 if (need_aligned_p && n != 0)
6422 total_size += 8 - n;
6423 reg_offset += 8 - n;
6425 total_size += gp_reg_size + fp_reg_size;
6428 /* If we must allocate a stack frame at all, we must also allocate
6429 room for register window spillage, so as to be binary compatible
6430 with libraries and operating systems that do not use -mflat. */
6432 total_size += extra_size;
6436 total_size = SPARC_STACK_ALIGN (total_size);
6438 /* Save other computed information. */
6439 current_frame_info.total_size = total_size;
6440 current_frame_info.var_size = var_size;
6441 current_frame_info.args_size = args_size;
6442 current_frame_info.extra_size = extra_size;
6443 current_frame_info.gp_reg_size = gp_reg_size;
6444 current_frame_info.fp_reg_size = fp_reg_size;
6445 current_frame_info.gmask = gmask;
6446 current_frame_info.fmask = fmask;
6447 current_frame_info.reg_offset = reg_offset;
6448 current_frame_info.initialized = reload_completed;
6450 /* Ok, we're done. */
6454 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
6457 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
6458 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
6459 [BASE_REG+OFFSET] will always be a valid address.
6461 WORD_OP is either "st" for save, "ld" for restore.
6462 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
6465 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
6466 doubleword_op, base_offset)
6468 const char *base_reg;
6469 unsigned int offset;
6470 unsigned long gmask;
6471 unsigned long fmask;
6472 const char *word_op;
6473 const char *doubleword_op;
6474 unsigned long base_offset;
6478 if (gmask == 0 && fmask == 0)
6481 /* Save registers starting from high to low. We've already saved the
6482 previous frame pointer and previous return address for the debugger's
6483 sake. The debugger allows us to not need a nop in the epilog if at least
6484 one register is reloaded in addition to return address. */
6488 for (regno = 1; regno <= 31; regno++)
6490 if ((gmask & (1L << regno)) != 0)
6492 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
6494 /* We can save two registers in a row. If we're not at a
6495 double word boundary, move to one.
6496 sparc_flat_compute_frame_size ensures there's room to do
6498 if (offset % 8 != 0)
6499 offset += UNITS_PER_WORD;
6501 if (word_op[0] == 's')
6503 fprintf (file, "\t%s\t%s, [%s+%d]\n",
6504 doubleword_op, reg_names[regno],
6506 if (dwarf2out_do_frame ())
6508 char *l = dwarf2out_cfi_label ();
6509 dwarf2out_reg_save (l, regno, offset + base_offset);
6511 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
6515 fprintf (file, "\t%s\t[%s+%d], %s\n",
6516 doubleword_op, base_reg, offset,
6519 offset += 2 * UNITS_PER_WORD;
6524 if (word_op[0] == 's')
6526 fprintf (file, "\t%s\t%s, [%s+%d]\n",
6527 word_op, reg_names[regno],
6529 if (dwarf2out_do_frame ())
6530 dwarf2out_reg_save ("", regno, offset + base_offset);
6533 fprintf (file, "\t%s\t[%s+%d], %s\n",
6534 word_op, base_reg, offset, reg_names[regno]);
6536 offset += UNITS_PER_WORD;
6544 for (regno = 32; regno <= 63; regno++)
6546 if ((fmask & (1L << (regno - 32))) != 0)
6548 if (word_op[0] == 's')
6550 fprintf (file, "\t%s\t%s, [%s+%d]\n",
6551 word_op, reg_names[regno],
6553 if (dwarf2out_do_frame ())
6554 dwarf2out_reg_save ("", regno, offset + base_offset);
6557 fprintf (file, "\t%s\t[%s+%d], %s\n",
6558 word_op, base_reg, offset, reg_names[regno]);
6560 offset += UNITS_PER_WORD;
6566 /* Set up the stack and frame (if desired) for the function. */
6569 sparc_flat_output_function_prologue (file, size)
6573 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
6574 unsigned long gmask = current_frame_info.gmask;
6576 sparc_output_scratch_registers (file);
6578 /* This is only for the human reader. */
6579 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
6580 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6582 current_frame_info.var_size,
6583 current_frame_info.gp_reg_size / 4,
6584 current_frame_info.fp_reg_size / 4,
6585 current_function_outgoing_args_size,
6586 current_frame_info.extra_size);
6588 size = SPARC_STACK_ALIGN (size);
6589 size = (! current_frame_info.initialized
6590 ? sparc_flat_compute_frame_size (size)
6591 : current_frame_info.total_size);
6593 /* These cases shouldn't happen. Catch them now. */
6594 if (size == 0 && (gmask || current_frame_info.fmask))
6597 /* Allocate our stack frame by decrementing %sp.
6598 At present, the only algorithm gdb can use to determine if this is a
6599 flat frame is if we always set %i7 if we set %sp. This can be optimized
6600 in the future by putting in some sort of debugging information that says
6601 this is a `flat' function. However, there is still the case of debugging
6602 code without such debugging information (including cases where most fns
6603 have such info, but there is one that doesn't). So, always do this now
6604 so we don't get a lot of code out there that gdb can't handle.
6605 If the frame pointer isn't needn't then that's ok - gdb won't be able to
6606 distinguish us from a non-flat function but there won't (and shouldn't)
6607 be any differences anyway. The return pc is saved (if necessary) right
6608 after %i7 so gdb won't have to look too far to find it. */
6611 unsigned int reg_offset = current_frame_info.reg_offset;
6612 const char *fp_str = reg_names[FRAME_POINTER_REGNUM];
6613 const char *t1_str = "%g1";
6615 /* Things get a little tricky if local variables take up more than ~4096
6616 bytes and outgoing arguments take up more than ~4096 bytes. When that
6617 happens, the register save area can't be accessed from either end of
6618 the frame. Handle this by decrementing %sp to the start of the gp
6619 register save area, save the regs, update %i7, and then set %sp to its
6620 final value. Given that we only have one scratch register to play
6621 with it is the cheapest solution, and it helps gdb out as it won't
6622 slow down recognition of flat functions.
6623 Don't change the order of insns emitted here without checking with
6624 the gdb folk first. */
6626 /* Is the entire register save area offsettable from %sp? */
6627 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
6631 fprintf (file, "\tadd\t%s, %d, %s\n",
6632 sp_str, -size, sp_str);
6633 if (gmask & FRAME_POINTER_MASK)
6635 fprintf (file, "\tst\t%s, [%s+%d]\n",
6636 fp_str, sp_str, reg_offset);
6637 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
6638 sp_str, -size, fp_str, ASM_COMMENT_START);
6644 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6645 size, t1_str, sp_str, t1_str, sp_str);
6646 if (gmask & FRAME_POINTER_MASK)
6648 fprintf (file, "\tst\t%s, [%s+%d]\n",
6649 fp_str, sp_str, reg_offset);
6650 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
6651 sp_str, t1_str, fp_str, ASM_COMMENT_START);
6655 if (dwarf2out_do_frame ())
6657 char *l = dwarf2out_cfi_label ();
6658 if (gmask & FRAME_POINTER_MASK)
6660 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
6661 reg_offset - 4 - size);
6662 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
6665 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
6667 if (gmask & RETURN_ADDR_MASK)
6669 fprintf (file, "\tst\t%s, [%s+%d]\n",
6670 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
6671 if (dwarf2out_do_frame ())
6672 dwarf2out_return_save ("", reg_offset - size);
6675 sparc_flat_save_restore (file, sp_str, reg_offset,
6676 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6677 current_frame_info.fmask,
6678 "st", "std", -size);
6682 /* Subtract %sp in two steps, but make sure there is always a
6683 64 byte register save area, and %sp is properly aligned. */
6684 /* Amount to decrement %sp by, the first time. */
6685 unsigned int size1 = ((size - reg_offset + 64) + 15) & -16;
6686 /* Offset to register save area from %sp. */
6687 unsigned int offset = size1 - (size - reg_offset);
6691 fprintf (file, "\tadd\t%s, %d, %s\n",
6692 sp_str, -size1, sp_str);
6693 if (gmask & FRAME_POINTER_MASK)
6695 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
6696 fp_str, sp_str, offset, sp_str, -size1, fp_str,
6703 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6704 size1, t1_str, sp_str, t1_str, sp_str);
6705 if (gmask & FRAME_POINTER_MASK)
6707 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
6708 fp_str, sp_str, offset, sp_str, t1_str, fp_str,
6713 if (dwarf2out_do_frame ())
6715 char *l = dwarf2out_cfi_label ();
6716 if (gmask & FRAME_POINTER_MASK)
6718 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
6719 offset - 4 - size1);
6720 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
6723 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
6725 if (gmask & RETURN_ADDR_MASK)
6727 fprintf (file, "\tst\t%s, [%s+%d]\n",
6728 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
6729 if (dwarf2out_do_frame ())
6730 /* offset - size1 == reg_offset - size
6731 if reg_offset were updated above like offset. */
6732 dwarf2out_return_save ("", offset - size1);
6735 sparc_flat_save_restore (file, sp_str, offset,
6736 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6737 current_frame_info.fmask,
6738 "st", "std", -size1);
6739 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6740 size - size1, t1_str, sp_str, t1_str, sp_str);
6741 if (dwarf2out_do_frame ())
6742 if (! (gmask & FRAME_POINTER_MASK))
6743 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
6747 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
6750 /* Do any necessary cleanup after a function to restore stack, frame,
6754 sparc_flat_output_function_epilogue (file, size)
6758 rtx epilogue_delay = current_function_epilogue_delay_list;
6759 int noepilogue = FALSE;
6761 /* This is only for the human reader. */
6762 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
6764 /* The epilogue does not depend on any registers, but the stack
6765 registers, so we assume that if we have 1 pending nop, it can be
6766 ignored, and 2 it must be filled (2 nops occur for integer
6767 multiply and divide). */
6769 size = SPARC_STACK_ALIGN (size);
6770 size = (!current_frame_info.initialized
6771 ? sparc_flat_compute_frame_size (size)
6772 : current_frame_info.total_size);
6774 if (size == 0 && epilogue_delay == 0)
6776 rtx insn = get_last_insn ();
6778 /* If the last insn was a BARRIER, we don't have to write any code
6779 because a jump (aka return) was put there. */
6780 if (GET_CODE (insn) == NOTE)
6781 insn = prev_nonnote_insn (insn);
6782 if (insn && GET_CODE (insn) == BARRIER)
6788 unsigned int reg_offset = current_frame_info.reg_offset;
6790 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
6791 const char *fp_str = reg_names[FRAME_POINTER_REGNUM];
6792 const char *t1_str = "%g1";
6794 /* In the reload sequence, we don't need to fill the load delay
6795 slots for most of the loads, also see if we can fill the final
6796 delay slot if not otherwise filled by the reload sequence. */
6799 fprintf (file, "\tset\t%d, %s\n", size, t1_str);
6801 if (frame_pointer_needed)
6804 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
6805 fp_str, t1_str, sp_str, ASM_COMMENT_START);
6807 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
6808 fp_str, size, sp_str, ASM_COMMENT_START);
6811 /* Is the entire register save area offsettable from %sp? */
6812 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
6818 /* Restore %sp in two steps, but make sure there is always a
6819 64 byte register save area, and %sp is properly aligned. */
6820 /* Amount to increment %sp by, the first time. */
6821 size1 = ((reg_offset - 64 - 16) + 15) & -16;
6822 /* Offset to register save area from %sp. */
6823 reg_offset = size1 - reg_offset;
6825 fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n",
6826 size1, t1_str, sp_str, t1_str, sp_str);
6829 /* We must restore the frame pointer and return address reg first
6830 because they are treated specially by the prologue output code. */
6831 if (current_frame_info.gmask & FRAME_POINTER_MASK)
6833 fprintf (file, "\tld\t[%s+%d], %s\n",
6834 sp_str, reg_offset, fp_str);
6837 if (current_frame_info.gmask & RETURN_ADDR_MASK)
6839 fprintf (file, "\tld\t[%s+%d], %s\n",
6840 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
6844 /* Restore any remaining saved registers. */
6845 sparc_flat_save_restore (file, sp_str, reg_offset,
6846 current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6847 current_frame_info.fmask,
6850 /* If we had to increment %sp in two steps, record it so the second
6851 restoration in the epilogue finishes up. */
6856 fprintf (file, "\tset\t%d, %s\n",
6860 if (current_function_returns_struct)
6861 fprintf (file, "\tjmp\t%%o7+12\n");
6863 fprintf (file, "\tretl\n");
6865 /* If the only register saved is the return address, we need a
6866 nop, unless we have an instruction to put into it. Otherwise
6867 we don't since reloading multiple registers doesn't reference
6868 the register being loaded. */
6874 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
6877 else if (size > 4095)
6878 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
6881 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str);
6884 fprintf (file, "\tnop\n");
6887 /* Reset state info for each function. */
6888 current_frame_info = zero_frame_info;
6890 sparc_output_deferred_case_vectors ();
6893 /* Define the number of delay slots needed for the function epilogue.
6895 On the sparc, we need a slot if either no stack has been allocated,
6896 or the only register saved is the return register. */
6899 sparc_flat_epilogue_delay_slots ()
6901 if (!current_frame_info.initialized)
6902 (void) sparc_flat_compute_frame_size (get_frame_size ());
6904 if (current_frame_info.total_size == 0)
6910 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
6911 Any single length instruction which doesn't reference the stack or frame
6915 sparc_flat_eligible_for_epilogue_delay (trial, slot)
6917 int slot ATTRIBUTE_UNUSED;
6919 rtx pat = PATTERN (trial);
6921 if (get_attr_length (trial) != 1)
6924 if (! reg_mentioned_p (stack_pointer_rtx, pat)
6925 && ! reg_mentioned_p (frame_pointer_rtx, pat))
6931 /* Adjust the cost of a scheduling dependency. Return the new cost of
6932 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6935 supersparc_adjust_cost (insn, link, dep_insn, cost)
6941 enum attr_type insn_type;
6943 if (! recog_memoized (insn))
6946 insn_type = get_attr_type (insn);
6948 if (REG_NOTE_KIND (link) == 0)
6950 /* Data dependency; DEP_INSN writes a register that INSN reads some
6953 /* if a load, then the dependence must be on the memory address;
6954 add an extra "cycle". Note that the cost could be two cycles
6955 if the reg was written late in an instruction group; we ca not tell
6957 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
6960 /* Get the delay only if the address of the store is the dependence. */
6961 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
6963 rtx pat = PATTERN(insn);
6964 rtx dep_pat = PATTERN (dep_insn);
6966 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6967 return cost; /* This should not happen! */
6969 /* The dependency between the two instructions was on the data that
6970 is being stored. Assume that this implies that the address of the
6971 store is not dependent. */
6972 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6975 return cost + 3; /* An approximation. */
6978 /* A shift instruction cannot receive its data from an instruction
6979 in the same cycle; add a one cycle penalty. */
6980 if (insn_type == TYPE_SHIFT)
6981 return cost + 3; /* Split before cascade into shift. */
6985 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
6986 INSN writes some cycles later. */
6988 /* These are only significant for the fpu unit; writing a fp reg before
6989 the fpu has finished with it stalls the processor. */
6991 /* Reusing an integer register causes no problems. */
6992 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7000 hypersparc_adjust_cost (insn, link, dep_insn, cost)
7006 enum attr_type insn_type, dep_type;
7007 rtx pat = PATTERN(insn);
7008 rtx dep_pat = PATTERN (dep_insn);
7010 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7013 insn_type = get_attr_type (insn);
7014 dep_type = get_attr_type (dep_insn);
7016 switch (REG_NOTE_KIND (link))
7019 /* Data dependency; DEP_INSN writes a register that INSN reads some
7026 /* Get the delay iff the address of the store is the dependence. */
7027 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7030 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7037 /* If a load, then the dependence must be on the memory address. If
7038 the addresses aren't equal, then it might be a false dependency */
7039 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7041 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7042 || GET_CODE (SET_DEST (dep_pat)) != MEM
7043 || GET_CODE (SET_SRC (pat)) != MEM
7044 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7045 XEXP (SET_SRC (pat), 0)))
7053 /* Compare to branch latency is 0. There is no benefit from
7054 separating compare and branch. */
7055 if (dep_type == TYPE_COMPARE)
7057 /* Floating point compare to branch latency is less than
7058 compare to conditional move. */
7059 if (dep_type == TYPE_FPCMP)
7068 /* Anti-dependencies only penalize the fpu unit. */
7069 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7081 ultrasparc_adjust_cost (insn, link, dep_insn, cost)
7087 enum attr_type insn_type, dep_type;
7088 rtx pat = PATTERN(insn);
7089 rtx dep_pat = PATTERN (dep_insn);
7091 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7094 insn_type = get_attr_type (insn);
7095 dep_type = get_attr_type (dep_insn);
7097 /* Nothing issues in parallel with integer multiplies, so
7098 mark as zero cost since the scheduler can not do anything
7100 if (insn_type == TYPE_IMUL)
7103 #define SLOW_FP(dep_type) \
7104 (dep_type == TYPE_FPSQRTS || dep_type == TYPE_FPSQRTD || \
7105 dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
7107 switch (REG_NOTE_KIND (link))
7110 /* Data dependency; DEP_INSN writes a register that INSN reads some
7113 if (dep_type == TYPE_CMOVE)
7115 /* Instructions that read the result of conditional moves cannot
7116 be in the same group or the following group. */
7122 /* UltraSPARC can dual issue a store and an instruction setting
7123 the value stored, except for divide and square root. */
7125 if (! SLOW_FP (dep_type))
7130 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7133 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7134 /* The dependency between the two instructions is on the data
7135 that is being stored. Assume that the address of the store
7136 is not also dependent. */
7143 /* A load does not return data until at least 11 cycles after
7144 a store to the same location. 3 cycles are accounted for
7145 in the load latency; add the other 8 here. */
7146 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7148 /* If the addresses are not equal this may be a false
7149 dependency because pointer aliasing could not be
7150 determined. Add only 2 cycles in that case. 2 is
7151 an arbitrary compromise between 8, which would cause
7152 the scheduler to generate worse code elsewhere to
7153 compensate for a dependency which might not really
7155 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7156 || GET_CODE (SET_SRC (pat)) != MEM
7157 || GET_CODE (SET_DEST (dep_pat)) != MEM
7158 || ! rtx_equal_p (XEXP (SET_SRC (pat), 0),
7159 XEXP (SET_DEST (dep_pat), 0)))
7167 /* Compare to branch latency is 0. There is no benefit from
7168 separating compare and branch. */
7169 if (dep_type == TYPE_COMPARE)
7171 /* Floating point compare to branch latency is less than
7172 compare to conditional move. */
7173 if (dep_type == TYPE_FPCMP)
7178 /* FMOVR class instructions can not issue in the same cycle
7179 or the cycle after an instruction which writes any
7180 integer register. Model this as cost 2 for dependent
7182 if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY
7183 || dep_type == TYPE_BINARY)
7186 /* Otherwise check as for integer conditional moves. */
7189 /* Conditional moves involving integer registers wait until
7190 3 cycles after loads return data. The interlock applies
7191 to all loads, not just dependent loads, but that is hard
7193 if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD)
7203 /* Divide and square root lock destination registers for full latency. */
7204 if (! SLOW_FP (dep_type))
7208 case REG_DEP_OUTPUT:
7209 /* IEU and FPU instruction that have the same destination
7210 register cannot be grouped together. */
7217 /* Other costs not accounted for:
7218 - Single precision floating point loads lock the other half of
7219 the even/odd register pair.
7220 - Several hazards associated with ldd/std are ignored because these
7221 instructions are rarely generated for V9.
7222 - The floating point pipeline can not have both a single and double
7223 precision operation active at the same time. Format conversions
7224 and graphics instructions are given honorary double precision status.
7225 - call and jmpl are always the first instruction in a group. */
7233 sparc_adjust_cost(insn, link, dep, cost)
7241 case PROCESSOR_SUPERSPARC:
7242 cost = supersparc_adjust_cost (insn, link, dep, cost);
7244 case PROCESSOR_HYPERSPARC:
7245 case PROCESSOR_SPARCLITE86X:
7246 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7248 case PROCESSOR_ULTRASPARC:
7249 cost = ultrasparc_adjust_cost (insn, link, dep, cost);
7257 /* This describes the state of the UltraSPARC pipeline during
7258 instruction scheduling. */
7260 #define TMASK(__x) ((unsigned)1 << ((int)(__x)))
7261 #define UMASK(__x) ((unsigned)1 << ((int)(__x)))
7263 enum ultra_code { NONE=0, /* no insn at all */
7264 IEU0, /* shifts and conditional moves */
7265 IEU1, /* condition code setting insns, calls+jumps */
7266 IEUN, /* all other single cycle ieu insns */
7267 LSU, /* loads and stores */
7269 FPM, /* FPU pipeline 1, multiplies and divides */
7270 FPA, /* FPU pipeline 2, all other operations */
7271 SINGLE, /* single issue instructions */
7274 static enum ultra_code ultra_code_from_mask PARAMS ((int));
7275 static void ultra_schedule_insn PARAMS ((rtx *, rtx *, int, enum ultra_code));
7277 static const char *ultra_code_names[NUM_ULTRA_CODES] = {
7278 "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI",
7279 "FPM", "FPA", "SINGLE" };
7281 struct ultrasparc_pipeline_state {
7282 /* The insns in this group. */
7285 /* The code for each insn. */
7286 enum ultra_code codes[4];
7288 /* Which insns in this group have been committed by the
7289 scheduler. This is how we determine how many more
7290 can issue this cycle. */
7293 /* How many insns in this group. */
7296 /* Mask of free slots still in this group. */
7297 char free_slot_mask;
7299 /* The slotter uses the following to determine what other
7300 insn types can still make their way into this group. */
7301 char contents [NUM_ULTRA_CODES];
7305 #define ULTRA_NUM_HIST 8
7306 static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST];
7307 static int ultra_cur_hist;
7308 static int ultra_cycles_elapsed;
7310 #define ultra_pipe (ultra_pipe_hist[ultra_cur_hist])
7312 /* Given TYPE_MASK compute the ultra_code it has. */
7313 static enum ultra_code
7314 ultra_code_from_mask (type_mask)
7317 if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE)))
7319 else if (type_mask & (TMASK (TYPE_COMPARE) |
7321 TMASK (TYPE_SIBCALL) |
7322 TMASK (TYPE_UNCOND_BRANCH)))
7324 else if (type_mask & (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
7325 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY)))
7327 else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
7328 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
7329 TMASK (TYPE_FPSTORE)))
7331 else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) |
7332 TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRTS) |
7333 TMASK (TYPE_FPSQRTD)))
7335 else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
7336 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)))
7338 else if (type_mask & TMASK (TYPE_BRANCH))
7344 /* Check INSN (a conditional move) and make sure that it's
7345 results are available at this cycle. Return 1 if the
7346 results are in fact ready. */
7348 ultra_cmove_results_ready_p (insn)
7351 struct ultrasparc_pipeline_state *up;
7354 /* If this got dispatched in the previous
7355 group, the results are not ready. */
7356 entry = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1);
7357 up = &ultra_pipe_hist[entry];
7360 if (up->group[slot] == insn)
7366 /* Walk backwards in pipeline history looking for FPU
7367 operations which use a mode different than FPMODE and
7368 will create a stall if an insn using FPMODE were to be
7369 dispatched this cycle. */
7371 ultra_fpmode_conflict_exists (fpmode)
7372 enum machine_mode fpmode;
7377 hist_ent = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1);
7378 if (ultra_cycles_elapsed < 4)
7379 hist_lim = ultra_cycles_elapsed;
7382 while (hist_lim > 0)
7384 struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent];
7389 rtx insn = up->group[slot];
7390 enum machine_mode this_mode;
7394 || GET_CODE (insn) != INSN
7395 || (pat = PATTERN (insn)) == 0
7396 || GET_CODE (pat) != SET)
7399 this_mode = GET_MODE (SET_DEST (pat));
7400 if ((this_mode != SFmode
7401 && this_mode != DFmode)
7402 || this_mode == fpmode)
7405 /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then
7406 we will get a stall. Loads and stores are independant
7408 if (GET_CODE (SET_SRC (pat)) != ABS
7409 && GET_CODE (SET_SRC (pat)) != NEG
7410 && ((TMASK (get_attr_type (insn)) &
7411 (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) |
7412 TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRTS) |
7413 TMASK (TYPE_FPSQRTD) |
7414 TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0))
7418 hist_ent = (hist_ent - 1) & (ULTRA_NUM_HIST - 1);
7421 /* No conflicts, safe to dispatch. */
7425 /* Find an instruction in LIST which has one of the
7426 type attributes enumerated in TYPE_MASK. START
7427 says where to begin the search.
7429 NOTE: This scheme depends upon the fact that we
7430 have less than 32 distinct type attributes. */
7432 static int ultra_types_avail;
7435 ultra_find_type (type_mask, list, start)
7442 /* Short circuit if no such insn exists in the ready
7444 if ((type_mask & ultra_types_avail) == 0)
7447 for (i = start; i >= 0; i--)
7451 if (recog_memoized (insn) >= 0
7452 && (TMASK(get_attr_type (insn)) & type_mask))
7454 enum machine_mode fpmode = SFmode;
7457 int check_depend = 0;
7458 int check_fpmode_conflict = 0;
7460 if (GET_CODE (insn) == INSN
7461 && (pat = PATTERN(insn)) != 0
7462 && GET_CODE (pat) == SET
7463 && !(type_mask & (TMASK (TYPE_STORE) |
7464 TMASK (TYPE_FPSTORE))))
7467 if (GET_MODE (SET_DEST (pat)) == SFmode
7468 || GET_MODE (SET_DEST (pat)) == DFmode)
7470 fpmode = GET_MODE (SET_DEST (pat));
7471 check_fpmode_conflict = 1;
7478 rtx slot_insn = ultra_pipe.group[slot];
7481 /* Already issued, bad dependency, or FPU
7484 && (slot_pat = PATTERN (slot_insn)) != 0
7485 && ((insn == slot_insn)
7486 || (check_depend == 1
7487 && GET_CODE (slot_insn) == INSN
7488 && GET_CODE (slot_pat) == SET
7489 && ((GET_CODE (SET_DEST (slot_pat)) == REG
7490 && GET_CODE (SET_SRC (pat)) == REG
7491 && REGNO (SET_DEST (slot_pat)) ==
7492 REGNO (SET_SRC (pat)))
7493 || (GET_CODE (SET_DEST (slot_pat)) == SUBREG
7494 && GET_CODE (SET_SRC (pat)) == SUBREG
7495 && REGNO (SUBREG_REG (SET_DEST (slot_pat))) ==
7496 REGNO (SUBREG_REG (SET_SRC (pat)))
7497 && SUBREG_WORD (SET_DEST (slot_pat)) ==
7498 SUBREG_WORD (SET_SRC (pat)))))
7499 || (check_fpmode_conflict == 1
7500 && GET_CODE (slot_insn) == INSN
7501 && GET_CODE (slot_pat) == SET
7502 && (GET_MODE (SET_DEST (slot_pat)) == SFmode
7503 || GET_MODE (SET_DEST (slot_pat)) == DFmode)
7504 && GET_MODE (SET_DEST (slot_pat)) != fpmode)))
7508 /* Check for peculiar result availability and dispatch
7509 interference situations. */
7511 && ultra_cycles_elapsed > 0)
7515 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
7517 rtx link_insn = XEXP (link, 0);
7518 if (GET_CODE (link_insn) == INSN
7519 && recog_memoized (link_insn) >= 0
7520 && (TMASK (get_attr_type (link_insn)) &
7521 (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE)))
7522 && ! ultra_cmove_results_ready_p (link_insn))
7526 if (check_fpmode_conflict
7527 && ultra_fpmode_conflict_exists (fpmode))
7540 ultra_build_types_avail (ready, n_ready)
7544 int i = n_ready - 1;
7546 ultra_types_avail = 0;
7549 rtx insn = ready[i];
7551 if (recog_memoized (insn) >= 0)
7552 ultra_types_avail |= TMASK (get_attr_type (insn));
7558 /* Place insn pointed to my IP into the pipeline.
7559 Make element THIS of READY be that insn if it
7560 is not already. TYPE indicates the pipeline class
7561 this insn falls into. */
7563 ultra_schedule_insn (ip, ready, this, type)
7567 enum ultra_code type;
7570 char mask = ultra_pipe.free_slot_mask;
7573 /* Obtain free slot. */
7574 for (pipe_slot = 0; pipe_slot < 4; pipe_slot++)
7575 if ((mask & (1 << pipe_slot)) != 0)
7580 /* In it goes, and it hasn't been committed yet. */
7581 ultra_pipe.group[pipe_slot] = *ip;
7582 ultra_pipe.codes[pipe_slot] = type;
7583 ultra_pipe.contents[type] = 1;
7585 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
7586 ultra_pipe.num_ieu_insns += 1;
7588 ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot));
7589 ultra_pipe.group_size += 1;
7590 ultra_pipe.commit[pipe_slot] = 0;
7592 /* Update ready list. */
7594 while (ip != &ready[this])
7602 /* Advance to the next pipeline group. */
7604 ultra_flush_pipeline ()
7606 ultra_cur_hist = (ultra_cur_hist + 1) & (ULTRA_NUM_HIST - 1);
7607 ultra_cycles_elapsed += 1;
7608 memset ((char *) &ultra_pipe, 0, sizeof ultra_pipe);
7609 ultra_pipe.free_slot_mask = 0xf;
7612 /* Init our data structures for this current block. */
7614 ultrasparc_sched_init (dump, sched_verbose)
7615 FILE *dump ATTRIBUTE_UNUSED;
7616 int sched_verbose ATTRIBUTE_UNUSED;
7618 memset ((char *) ultra_pipe_hist, 0, sizeof ultra_pipe_hist);
7620 ultra_cycles_elapsed = 0;
7621 ultra_pipe.free_slot_mask = 0xf;
7624 /* INSN has been scheduled, update pipeline commit state
7625 and return how many instructions are still to be
7626 scheduled in this group. */
7628 ultrasparc_variable_issue (insn)
7631 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7632 int i, left_to_fire;
7635 for (i = 0; i < 4; i++)
7637 if (up->group[i] == 0)
7640 if (up->group[i] == insn)
7644 else if (! up->commit[i])
7648 return left_to_fire;
7651 /* In actual_hazard_this_instance, we may have yanked some
7652 instructions from the ready list due to conflict cost
7653 adjustments. If so, and such an insn was in our pipeline
7654 group, remove it and update state. */
7656 ultra_rescan_pipeline_state (ready, n_ready)
7660 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7663 for (i = 0; i < 4; i++)
7665 rtx insn = up->group[i];
7671 /* If it has been committed, then it was removed from
7672 the ready list because it was actually scheduled,
7673 and that is not the case we are searching for here. */
7674 if (up->commit[i] != 0)
7677 for (j = n_ready - 1; j >= 0; j--)
7678 if (ready[j] == insn)
7681 /* If we didn't find it, toss it. */
7684 enum ultra_code ucode = up->codes[i];
7687 up->codes[i] = NONE;
7688 up->contents[ucode] = 0;
7690 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
7691 up->num_ieu_insns -= 1;
7693 up->free_slot_mask |= (1 << i);
7694 up->group_size -= 1;
7701 ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
7707 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7714 fprintf (dump, "\n;;\tUltraSPARC Looking at [");
7715 for (n = n_ready - 1; n >= 0; n--)
7717 rtx insn = ready[n];
7718 enum ultra_code ucode;
7720 if (recog_memoized (insn) < 0)
7722 ucode = ultra_code_from_mask (TMASK (get_attr_type (insn)));
7724 fprintf (dump, "%s(%d) ",
7725 ultra_code_names[ucode],
7728 fprintf (dump, "%s(%d)",
7729 ultra_code_names[ucode],
7732 fprintf (dump, "]\n");
7735 this_insn = n_ready - 1;
7737 /* Skip over junk we don't understand. */
7738 while ((this_insn >= 0)
7739 && recog_memoized (ready[this_insn]) < 0)
7742 ultra_build_types_avail (ready, this_insn + 1);
7744 while (this_insn >= 0) {
7745 int old_group_size = up->group_size;
7747 if (up->group_size != 0)
7751 num_committed = (up->commit[0] + up->commit[1] +
7752 up->commit[2] + up->commit[3]);
7753 /* If nothing has been commited from our group, or all of
7754 them have. Clear out the (current cycle's) pipeline
7755 state and start afresh. */
7756 if (num_committed == 0
7757 || num_committed == up->group_size)
7759 ultra_flush_pipeline ();
7765 /* OK, some ready list insns got requeued and thus removed
7766 from the ready list. Account for this fact. */
7767 ultra_rescan_pipeline_state (ready, n_ready);
7769 /* Something "changed", make this look like a newly
7770 formed group so the code at the end of the loop
7771 knows that progress was in fact made. */
7772 if (up->group_size != old_group_size)
7777 if (up->group_size == 0)
7779 /* If the pipeline is (still) empty and we have any single
7780 group insns, get them out now as this is a good time. */
7781 rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_ADDRESS) |
7782 TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) |
7783 TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)),
7787 ultra_schedule_insn (ip, ready, this_insn, SINGLE);
7791 /* If we are not in the process of emptying out the pipe, try to
7792 obtain an instruction which must be the first in it's group. */
7793 ip = ultra_find_type ((TMASK (TYPE_CALL) |
7794 TMASK (TYPE_SIBCALL) |
7795 TMASK (TYPE_CALL_NO_DELAY_SLOT) |
7796 TMASK (TYPE_UNCOND_BRANCH)),
7800 ultra_schedule_insn (ip, ready, this_insn, IEU1);
7803 else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) |
7804 TMASK (TYPE_FPDIVD) |
7805 TMASK (TYPE_FPSQRTS) |
7806 TMASK (TYPE_FPSQRTD)),
7807 ready, this_insn)) != 0)
7809 ultra_schedule_insn (ip, ready, this_insn, FPM);
7814 /* Try to fill the integer pipeline. First, look for an IEU0 specific
7815 operation. We can't do more IEU operations if the first 3 slots are
7816 all full or we have dispatched two IEU insns already. */
7817 if ((up->free_slot_mask & 0x7) != 0
7818 && up->num_ieu_insns < 2
7819 && up->contents[IEU0] == 0
7820 && up->contents[IEUN] == 0)
7822 rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn);
7825 ultra_schedule_insn (ip, ready, this_insn, IEU0);
7830 /* If we can, try to find an IEU1 specific or an unnamed
7832 if ((up->free_slot_mask & 0x7) != 0
7833 && up->num_ieu_insns < 2)
7835 rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
7836 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY) |
7837 (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)),
7843 ultra_schedule_insn (ip, ready, this_insn,
7844 (!up->contents[IEU1]
7845 && get_attr_type (insn) == TYPE_COMPARE)
7851 /* If only one IEU insn has been found, try to find another unnamed
7852 IEU operation or an IEU1 specific one. */
7853 if ((up->free_slot_mask & 0x7) != 0
7854 && up->num_ieu_insns < 2)
7857 int tmask = (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
7858 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY));
7860 if (!up->contents[IEU1])
7861 tmask |= TMASK (TYPE_COMPARE);
7862 ip = ultra_find_type (tmask, ready, this_insn);
7867 ultra_schedule_insn (ip, ready, this_insn,
7868 (!up->contents[IEU1]
7869 && get_attr_type (insn) == TYPE_COMPARE)
7875 /* Try for a load or store, but such an insn can only be issued
7876 if it is within' one of the first 3 slots. */
7877 if ((up->free_slot_mask & 0x7) != 0
7878 && up->contents[LSU] == 0)
7880 rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
7881 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
7882 TMASK (TYPE_FPSTORE)), ready, this_insn);
7885 ultra_schedule_insn (ip, ready, this_insn, LSU);
7890 /* Now find FPU operations, first FPM class. But not divisions or
7891 square-roots because those will break the group up. Unlike all
7892 the previous types, these can go in any slot. */
7893 if (up->free_slot_mask != 0
7894 && up->contents[FPM] == 0)
7896 rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn);
7899 ultra_schedule_insn (ip, ready, this_insn, FPM);
7904 /* Continue on with FPA class if we have not filled the group already. */
7905 if (up->free_slot_mask != 0
7906 && up->contents[FPA] == 0)
7908 rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
7909 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)),
7913 ultra_schedule_insn (ip, ready, this_insn, FPA);
7918 /* Finally, maybe stick a branch in here. */
7919 if (up->free_slot_mask != 0
7920 && up->contents[CTI] == 0)
7922 rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn);
7924 /* Try to slip in a branch only if it is one of the
7925 next 2 in the ready list. */
7926 if (ip && ((&ready[this_insn] - ip) < 2))
7928 ultra_schedule_insn (ip, ready, this_insn, CTI);
7934 for (i = 0; i < 4; i++)
7935 if ((up->free_slot_mask & (1 << i)) == 0)
7938 /* See if we made any progress... */
7939 if (old_group_size != up->group_size)
7942 /* Clean out the (current cycle's) pipeline state
7943 and try once more. If we placed no instructions
7944 into the pipeline at all, it means a real hard
7945 conflict exists with some earlier issued instruction
7946 so we must advance to the next cycle to clear it up. */
7947 if (up->group_size == 0)
7949 ultra_flush_pipeline ();
7954 memset ((char *) &ultra_pipe, 0, sizeof ultra_pipe);
7955 ultra_pipe.free_slot_mask = 0xf;
7963 fprintf (dump, ";;\tUltraSPARC Launched [");
7964 gsize = up->group_size;
7965 for (n = 0; n < 4; n++)
7967 rtx insn = up->group[n];
7974 fprintf (dump, "%s(%d) ",
7975 ultra_code_names[up->codes[n]],
7978 fprintf (dump, "%s(%d)",
7979 ultra_code_names[up->codes[n]],
7982 fprintf (dump, "]\n");
7994 /* Assume V9 processors are capable of at least dual-issue. */
7996 case PROCESSOR_SUPERSPARC:
7998 case PROCESSOR_HYPERSPARC:
7999 case PROCESSOR_SPARCLITE86X:
8001 case PROCESSOR_ULTRASPARC:
8010 register rtx pat = PATTERN (insn);
8012 switch (GET_CODE (SET_SRC (pat)))
8014 /* Load and some shift instructions zero extend. */
8017 /* sethi clears the high bits */
8019 /* LO_SUM is used with sethi. sethi cleared the high
8020 bits and the values used with lo_sum are positive */
8022 /* Store flag stores 0 or 1 */
8032 rtx op0 = XEXP (SET_SRC (pat), 0);
8033 rtx op1 = XEXP (SET_SRC (pat), 1);
8034 if (GET_CODE (op1) == CONST_INT)
8035 return INTVAL (op1) >= 0;
8036 if (GET_CODE (op0) != REG)
8038 if (sparc_check_64 (op0, insn) == 1)
8040 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8045 rtx op0 = XEXP (SET_SRC (pat), 0);
8046 rtx op1 = XEXP (SET_SRC (pat), 1);
8047 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8049 if (GET_CODE (op1) == CONST_INT)
8050 return INTVAL (op1) >= 0;
8051 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8055 return GET_MODE (SET_SRC (pat)) == SImode;
8056 /* Positive integers leave the high bits zero. */
8058 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8060 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8063 return - (GET_MODE (SET_SRC (pat)) == SImode);
8065 return sparc_check_64 (SET_SRC (pat), insn);
8071 /* We _ought_ to have only one kind per function, but... */
8072 static rtx sparc_addr_diff_list;
8073 static rtx sparc_addr_list;
8076 sparc_defer_case_vector (lab, vec, diff)
8080 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8082 sparc_addr_diff_list
8083 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8085 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8089 sparc_output_addr_vec (vec)
8092 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8093 int idx, vlen = XVECLEN (body, 0);
8095 #ifdef ASM_OUTPUT_ADDR_VEC_START
8096 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8099 #ifdef ASM_OUTPUT_CASE_LABEL
8100 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8103 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8106 for (idx = 0; idx < vlen; idx++)
8108 ASM_OUTPUT_ADDR_VEC_ELT
8109 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8112 #ifdef ASM_OUTPUT_ADDR_VEC_END
8113 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8118 sparc_output_addr_diff_vec (vec)
8121 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8122 rtx base = XEXP (XEXP (body, 0), 0);
8123 int idx, vlen = XVECLEN (body, 1);
8125 #ifdef ASM_OUTPUT_ADDR_VEC_START
8126 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8129 #ifdef ASM_OUTPUT_CASE_LABEL
8130 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8133 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8136 for (idx = 0; idx < vlen; idx++)
8138 ASM_OUTPUT_ADDR_DIFF_ELT
8141 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8142 CODE_LABEL_NUMBER (base));
8145 #ifdef ASM_OUTPUT_ADDR_VEC_END
8146 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8151 sparc_output_deferred_case_vectors ()
8156 if (sparc_addr_list == NULL_RTX
8157 && sparc_addr_diff_list == NULL_RTX)
8160 /* Align to cache line in the function's code section. */
8161 function_section (current_function_decl);
8163 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8165 ASM_OUTPUT_ALIGN (asm_out_file, align);
8167 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8168 sparc_output_addr_vec (XEXP (t, 0));
8169 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8170 sparc_output_addr_diff_vec (XEXP (t, 0));
8172 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8175 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8176 unknown. Return 1 if the high bits are zero, -1 if the register is
8179 sparc_check_64 (x, insn)
8182 /* If a register is set only once it is safe to ignore insns this
8183 code does not know how to handle. The loop will either recognize
8184 the single set and return the correct value or fail to recognize
8189 if (GET_CODE (x) != REG)
8192 if (GET_MODE (x) == DImode)
8193 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8195 if (flag_expensive_optimizations
8196 && REG_N_SETS (REGNO (y)) == 1)
8202 insn = get_last_insn_anywhere ();
8207 while ((insn = PREV_INSN (insn)))
8209 switch (GET_CODE (insn))
8222 rtx pat = PATTERN (insn);
8223 if (GET_CODE (pat) != SET)
8225 if (rtx_equal_p (x, SET_DEST (pat)))
8226 return set_extends (insn);
8227 if (y && rtx_equal_p (y, SET_DEST (pat)))
8228 return set_extends (insn);
8229 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8238 sparc_v8plus_shift (operands, insn, opcode)
8243 static char asm_code[60];
8245 if (GET_CODE (operands[3]) == SCRATCH)
8246 operands[3] = operands[0];
8247 if (GET_CODE (operands[1]) == CONST_INT)
8249 output_asm_insn ("mov\t%1, %3", operands);
8253 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8254 if (sparc_check_64 (operands[1], insn) <= 0)
8255 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8256 output_asm_insn ("or\t%L1, %3, %3", operands);
8259 strcpy(asm_code, opcode);
8260 if (which_alternative != 2)
8261 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8263 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8267 /* Return 1 if DEST and SRC reference only global and in registers. */
8270 sparc_return_peephole_ok (dest, src)
8275 if (current_function_uses_only_leaf_regs)
8277 if (GET_CODE (src) != CONST_INT
8278 && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src)))
8280 return IN_OR_GLOBAL_P (dest);
8283 /* Output assembler code to FILE to increment profiler label # LABELNO
8284 for profiling a function entry.
8286 32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered
8287 during profiling so we need to save/restore it around the call to mcount.
8288 We're guaranteed that a save has just been done, and we use the space
8289 allocated for intreg/fpreg value passing. */
8292 sparc_function_profiler (file, labelno)
8297 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8299 if (! TARGET_ARCH64)
8300 fputs ("\tst\t%g2, [%fp-4]\n", file);
8302 fputs ("\tsethi\t%hi(", file);
8303 assemble_name (file, buf);
8304 fputs ("), %o0\n", file);
8306 fputs ("\tcall\t", file);
8307 assemble_name (file, MCOUNT_FUNCTION);
8310 fputs ("\t or\t%o0, %lo(", file);
8311 assemble_name (file, buf);
8312 fputs ("), %o0\n", file);
8314 if (! TARGET_ARCH64)
8315 fputs ("\tld\t[%fp-4], %g2\n", file);
8319 /* The following macro shall output assembler code to FILE
8320 to initialize basic-block profiling.
8322 If profile_block_flag == 2
8324 Output code to call the subroutine `__bb_init_trace_func'
8325 and pass two parameters to it. The first parameter is
8326 the address of a block allocated in the object module.
8327 The second parameter is the number of the first basic block
8330 The name of the block is a local symbol made with this statement:
8332 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
8334 Of course, since you are writing the definition of
8335 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
8336 can take a short cut in the definition of this macro and use the
8337 name that you know will result.
8339 The number of the first basic block of the function is
8340 passed to the macro in BLOCK_OR_LABEL.
8342 If described in a virtual assembler language the code to be
8346 parameter2 <- BLOCK_OR_LABEL
8347 call __bb_init_trace_func
8349 else if profile_block_flag != 0
8351 Output code to call the subroutine `__bb_init_func'
8352 and pass one single parameter to it, which is the same
8353 as the first parameter to `__bb_init_trace_func'.
8355 The first word of this parameter is a flag which will be nonzero if
8356 the object module has already been initialized. So test this word
8357 first, and do not call `__bb_init_func' if the flag is nonzero.
8358 Note: When profile_block_flag == 2 the test need not be done
8359 but `__bb_init_trace_func' *must* be called.
8361 BLOCK_OR_LABEL may be used to generate a label number as a
8362 branch destination in case `__bb_init_func' will not be called.
8364 If described in a virtual assembler language the code to be
8376 sparc_function_block_profiler(file, block_or_label)
8381 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0);
8383 if (profile_block_flag == 2)
8385 fputs ("\tsethi\t%hi(", file);
8386 assemble_name (file, LPBX);
8387 fputs ("), %o0\n", file);
8389 fprintf (file, "\tsethi\t%%hi(%d), %%o1\n", block_or_label);
8391 fputs ("\tor\t%o0, %lo(", file);
8392 assemble_name (file, LPBX);
8393 fputs ("), %o0\n", file);
8395 fprintf (file, "\tcall\t%s__bb_init_trace_func\n", user_label_prefix);
8397 fprintf (file, "\t or\t%%o1, %%lo(%d), %%o1\n", block_or_label);
8399 else if (profile_block_flag != 0)
8402 ASM_GENERATE_INTERNAL_LABEL (LPBY, "LPBY", block_or_label);
8404 fputs ("\tsethi\t%hi(", file);
8405 assemble_name (file, LPBX);
8406 fputs ("), %o0\n", file);
8408 fputs ("\tld\t[%lo(", file);
8409 assemble_name (file, LPBX);
8410 fputs (")+%o0], %o1\n", file);
8412 fputs ("\ttst\t%o1\n", file);
8416 fputs ("\tbne,pn\t%icc,", file);
8417 assemble_name (file, LPBY);
8422 fputs ("\tbne\t", file);
8423 assemble_name (file, LPBY);
8427 fputs ("\t or\t%o0, %lo(", file);
8428 assemble_name (file, LPBX);
8429 fputs ("), %o0\n", file);
8431 fprintf (file, "\tcall\t%s__bb_init_func\n\t nop\n", user_label_prefix);
8433 ASM_OUTPUT_INTERNAL_LABEL (file, "LPBY", block_or_label);
8437 /* The following macro shall output assembler code to FILE
8438 to increment a counter associated with basic block number BLOCKNO.
8440 If profile_block_flag == 2
8442 Output code to initialize the global structure `__bb' and
8443 call the function `__bb_trace_func' which will increment the
8446 `__bb' consists of two words. In the first word the number
8447 of the basic block has to be stored. In the second word
8448 the address of a block allocated in the object module
8451 The basic block number is given by BLOCKNO.
8453 The address of the block is given by the label created with
8455 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
8457 by FUNCTION_BLOCK_PROFILER.
8459 Of course, since you are writing the definition of
8460 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
8461 can take a short cut in the definition of this macro and use the
8462 name that you know will result.
8464 If described in a virtual assembler language the code to be
8467 move BLOCKNO -> (__bb)
8468 move LPBX0 -> (__bb+4)
8469 call __bb_trace_func
8471 Note that function `__bb_trace_func' must not change the
8472 machine state, especially the flag register. To grant
8473 this, you must output code to save and restore registers
8474 either in this macro or in the macros MACHINE_STATE_SAVE
8475 and MACHINE_STATE_RESTORE. The last two macros will be
8476 used in the function `__bb_trace_func', so you must make
8477 sure that the function prologue does not change any
8478 register prior to saving it with MACHINE_STATE_SAVE.
8480 else if profile_block_flag != 0
8482 Output code to increment the counter directly.
8483 Basic blocks are numbered separately from zero within each
8484 compiled object module. The count associated with block number
8485 BLOCKNO is at index BLOCKNO in an array of words; the name of
8486 this array is a local symbol made with this statement:
8488 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
8490 Of course, since you are writing the definition of
8491 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
8492 can take a short cut in the definition of this macro and use the
8493 name that you know will result.
8495 If described in a virtual assembler language, the code to be
8498 inc (LPBX2+4*BLOCKNO)
8503 sparc_block_profiler(file, blockno)
8508 int bbreg = TARGET_ARCH64 ? 4 : 2;
8510 if (profile_block_flag == 2)
8512 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0);
8514 fprintf (file, "\tsethi\t%%hi(%s__bb), %%g1\n", user_label_prefix);
8515 fprintf (file, "\tsethi\t%%hi(%d), %%g%d\n", blockno, bbreg);
8516 fprintf (file, "\tor\t%%g1, %%lo(%s__bb), %%g1\n", user_label_prefix);
8517 fprintf (file, "\tor\t%%g%d, %%lo(%d), %%g%d\n", bbreg, blockno, bbreg);
8519 fprintf (file, "\tst\t%%g%d, [%%g1]\n", bbreg);
8521 fputs ("\tsethi\t%hi(", file);
8522 assemble_name (file, LPBX);
8523 fprintf (file, "), %%g%d\n", bbreg);
8525 fputs ("\tor\t%o2, %lo(", file);
8526 assemble_name (file, LPBX);
8527 fprintf (file, "), %%g%d\n", bbreg);
8529 fprintf (file, "\tst\t%%g%d, [%%g1 + 4]\n", bbreg);
8530 fprintf (file, "\tmov\t%%o7, %%g%d\n", bbreg);
8532 fprintf (file, "\tcall\t%s__bb_trace_func\n\t nop\n", user_label_prefix);
8534 fprintf (file, "\tmov\t%%g%d, %%o7\n", bbreg);
8536 else if (profile_block_flag != 0)
8538 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 2);
8540 fputs ("\tsethi\t%hi(", file);
8541 assemble_name (file, LPBX);
8542 fprintf (file, "+%d), %%g1\n", blockno*4);
8544 fputs ("\tld\t[%g1+%lo(", file);
8545 assemble_name (file, LPBX);
8546 if (TARGET_ARCH64 && USE_AS_OFFSETABLE_LO10)
8547 fprintf (file, ")+%d], %%g%d\n", blockno*4, bbreg);
8549 fprintf (file, "+%d)], %%g%d\n", blockno*4, bbreg);
8551 fprintf (file, "\tadd\t%%g%d, 1, %%g%d\n", bbreg, bbreg);
8553 fprintf (file, "\tst\t%%g%d, [%%g1+%%lo(", bbreg);
8554 assemble_name (file, LPBX);
8555 if (TARGET_ARCH64 && USE_AS_OFFSETABLE_LO10)
8556 fprintf (file, ")+%d]\n", blockno*4);
8558 fprintf (file, "+%d)]\n", blockno*4);
8562 /* The following macro shall output assembler code to FILE
8563 to indicate a return from function during basic-block profiling.
8565 If profile_block_flag == 2:
8567 Output assembler code to call function `__bb_trace_ret'.
8569 Note that function `__bb_trace_ret' must not change the
8570 machine state, especially the flag register. To grant
8571 this, you must output code to save and restore registers
8572 either in this macro or in the macros MACHINE_STATE_SAVE_RET
8573 and MACHINE_STATE_RESTORE_RET. The last two macros will be
8574 used in the function `__bb_trace_ret', so you must make
8575 sure that the function prologue does not change any
8576 register prior to saving it with MACHINE_STATE_SAVE_RET.
8578 else if profile_block_flag != 0:
8580 The macro will not be used, so it need not distinguish
8585 sparc_function_block_profiler_exit(file)
8588 if (profile_block_flag == 2)
8589 fprintf (file, "\tcall\t%s__bb_trace_ret\n\t nop\n", user_label_prefix);
8594 /* Mark ARG, which is really a struct ultrasparc_pipline_state *, for
8598 mark_ultrasparc_pipeline_state (arg)
8601 struct ultrasparc_pipeline_state *ups;
8604 ups = (struct ultrasparc_pipeline_state *) arg;
8605 for (i = 0; i < sizeof (ups->group) / sizeof (rtx); ++i)
8606 ggc_mark_rtx (ups->group[i]);
8609 /* Called to register all of our global variables with the garbage
8613 sparc_add_gc_roots ()
8615 ggc_add_rtx_root (&sparc_compare_op0, 1);
8616 ggc_add_rtx_root (&sparc_compare_op1, 1);
8617 ggc_add_rtx_root (&leaf_label, 1);
8618 ggc_add_rtx_root (&global_offset_table, 1);
8619 ggc_add_rtx_root (&get_pc_symbol, 1);
8620 ggc_add_rtx_root (&sparc_addr_diff_list, 1);
8621 ggc_add_rtx_root (&sparc_addr_list, 1);
8622 ggc_add_root (ultra_pipe_hist, ARRAY_SIZE (ultra_pipe_hist),
8623 sizeof (ultra_pipe_hist[0]), &mark_ultrasparc_pipeline_state);