1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
49 #include "target-def.h"
50 #include "cfglayout.h"
52 /* 1 if the caller has placed an "unimp" insn immediately after the call.
53 This is used in v8 code when calling a function that returns a structure.
54 v9 doesn't have this. Be careful to have this test be the same as that
57 #define SKIP_CALLERS_UNIMP_P \
58 (!TARGET_ARCH64 && current_function_returns_struct \
59 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
60 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
63 /* Global variables for machine-dependent things. */
65 /* Size of frame. Need to know this to emit return insns from leaf procedures.
66 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
67 reload pass. This is important as the value is later used in insn
68 scheduling (to see what can go in a delay slot).
69 APPARENT_FSIZE is the size of the stack less the register save area and less
70 the outgoing argument area. It is used when saving call preserved regs. */
71 static int apparent_fsize;
72 static int actual_fsize;
74 /* Number of live general or floating point registers needed to be
75 saved (as 4-byte quantities). */
76 static int num_gfregs;
78 /* Save the operands last given to a compare for use when we
79 generate a scc or bcc insn. */
80 rtx sparc_compare_op0, sparc_compare_op1;
82 /* Coordinate with the md file wrt special insns created by
83 sparc_nonflat_function_epilogue. */
84 bool sparc_emitting_epilogue;
86 /* Vector to say how input registers are mapped to output registers.
87 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
88 eliminate it. You must use -fomit-frame-pointer to get that. */
89 char leaf_reg_remap[] =
90 { 0, 1, 2, 3, 4, 5, 6, 7,
91 -1, -1, -1, -1, -1, -1, 14, -1,
92 -1, -1, -1, -1, -1, -1, -1, -1,
93 8, 9, 10, 11, 12, 13, -1, 15,
95 32, 33, 34, 35, 36, 37, 38, 39,
96 40, 41, 42, 43, 44, 45, 46, 47,
97 48, 49, 50, 51, 52, 53, 54, 55,
98 56, 57, 58, 59, 60, 61, 62, 63,
99 64, 65, 66, 67, 68, 69, 70, 71,
100 72, 73, 74, 75, 76, 77, 78, 79,
101 80, 81, 82, 83, 84, 85, 86, 87,
102 88, 89, 90, 91, 92, 93, 94, 95,
103 96, 97, 98, 99, 100};
105 /* Vector, indexed by hard register number, which contains 1
106 for a register that is allowable in a candidate for leaf
107 function treatment. */
108 char sparc_leaf_regs[] =
109 { 1, 1, 1, 1, 1, 1, 1, 1,
110 0, 0, 0, 0, 0, 0, 1, 0,
111 0, 0, 0, 0, 0, 0, 0, 0,
112 1, 1, 1, 1, 1, 1, 0, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
120 1, 1, 1, 1, 1, 1, 1, 1,
123 struct machine_function GTY(())
125 /* Some local-dynamic TLS symbol name. */
126 const char *some_ld_name;
129 /* Name of where we pretend to think the frame pointer points.
130 Normally, this is "%fp", but if we are in a leaf procedure,
131 this is "%sp+something". We record "something" separately as it may be
132 too big for reg+constant addressing. */
134 static const char *frame_base_name;
135 static int frame_base_offset;
137 static void sparc_init_modes (void);
138 static int save_regs (FILE *, int, int, const char *, int, int, int);
139 static int restore_regs (FILE *, int, int, const char *, int, int);
140 static void build_big_number (FILE *, int, const char *);
141 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
142 tree, int, int, int *, int *);
144 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
145 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
147 static void sparc_output_addr_vec (rtx);
148 static void sparc_output_addr_diff_vec (rtx);
149 static void sparc_output_deferred_case_vectors (void);
150 static int check_return_regs (rtx);
151 static int epilogue_renumber (rtx *, int);
152 static bool sparc_assemble_integer (rtx, unsigned int, int);
153 static int set_extends (rtx);
154 static void output_restore_regs (FILE *, int);
155 static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT);
156 static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT);
157 static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT);
158 static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT);
159 static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int);
160 static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int);
161 #ifdef OBJECT_FORMAT_ELF
162 static void sparc_elf_asm_named_section (const char *, unsigned int);
164 static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT)
166 static void sparc_aout_select_rtx_section (enum machine_mode, rtx,
167 unsigned HOST_WIDE_INT)
170 static int sparc_adjust_cost (rtx, rtx, rtx, int);
171 static int sparc_issue_rate (void);
172 static void sparc_sched_init (FILE *, int, int);
173 static int sparc_use_dfa_pipeline_interface (void);
174 static int sparc_use_sched_lookahead (void);
176 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
177 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
178 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
179 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
180 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
182 static bool sparc_function_ok_for_sibcall (tree, tree);
183 static void sparc_init_libfuncs (void);
184 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
185 HOST_WIDE_INT, tree);
186 static struct machine_function * sparc_init_machine_status (void);
187 static bool sparc_cannot_force_const_mem (rtx);
188 static rtx sparc_tls_get_addr (void);
189 static rtx sparc_tls_got (void);
190 static const char *get_some_local_dynamic_name (void);
191 static int get_some_local_dynamic_name_1 (rtx *, void *);
192 static bool sparc_rtx_costs (rtx, int, int, int *);
194 /* Option handling. */
196 /* Code model option as passed by user. */
197 const char *sparc_cmodel_string;
199 enum cmodel sparc_cmodel;
201 char sparc_hard_reg_printed[8];
203 struct sparc_cpu_select sparc_select[] =
205 /* switch name, tune arch */
206 { (char *)0, "default", 1, 1 },
207 { (char *)0, "-mcpu=", 1, 1 },
208 { (char *)0, "-mtune=", 1, 0 },
212 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
213 enum processor_type sparc_cpu;
215 /* Initialize the GCC target structure. */
217 /* The sparc default is to use .half rather than .short for aligned
218 HI objects. Use .word instead of .long on non-ELF systems. */
219 #undef TARGET_ASM_ALIGNED_HI_OP
220 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
221 #ifndef OBJECT_FORMAT_ELF
222 #undef TARGET_ASM_ALIGNED_SI_OP
223 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
226 #undef TARGET_ASM_UNALIGNED_HI_OP
227 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
228 #undef TARGET_ASM_UNALIGNED_SI_OP
229 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
230 #undef TARGET_ASM_UNALIGNED_DI_OP
231 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
233 /* The target hook has to handle DI-mode values. */
234 #undef TARGET_ASM_INTEGER
235 #define TARGET_ASM_INTEGER sparc_assemble_integer
237 #undef TARGET_ASM_FUNCTION_PROLOGUE
238 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
239 #undef TARGET_ASM_FUNCTION_EPILOGUE
240 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
242 #undef TARGET_SCHED_ADJUST_COST
243 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
244 #undef TARGET_SCHED_ISSUE_RATE
245 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
246 #undef TARGET_SCHED_INIT
247 #define TARGET_SCHED_INIT sparc_sched_init
248 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
249 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
250 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
251 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
253 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
254 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
256 #undef TARGET_INIT_LIBFUNCS
257 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
260 #undef TARGET_HAVE_TLS
261 #define TARGET_HAVE_TLS true
263 #undef TARGET_CANNOT_FORCE_CONST_MEM
264 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
266 #undef TARGET_ASM_OUTPUT_MI_THUNK
267 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
268 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
269 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
271 #undef TARGET_RTX_COSTS
272 #define TARGET_RTX_COSTS sparc_rtx_costs
273 #undef TARGET_ADDRESS_COST
274 #define TARGET_ADDRESS_COST hook_int_rtx_0
276 struct gcc_target targetm = TARGET_INITIALIZER;
278 /* Validate and override various options, and do some machine dependent
282 sparc_override_options (void)
284 static struct code_model {
285 const char *const name;
287 } const cmodels[] = {
289 { "medlow", CM_MEDLOW },
290 { "medmid", CM_MEDMID },
291 { "medany", CM_MEDANY },
292 { "embmedany", CM_EMBMEDANY },
295 const struct code_model *cmodel;
296 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
297 static struct cpu_default {
299 const char *const name;
300 } const cpu_default[] = {
301 /* There must be one entry here for each TARGET_CPU value. */
302 { TARGET_CPU_sparc, "cypress" },
303 { TARGET_CPU_sparclet, "tsc701" },
304 { TARGET_CPU_sparclite, "f930" },
305 { TARGET_CPU_v8, "v8" },
306 { TARGET_CPU_hypersparc, "hypersparc" },
307 { TARGET_CPU_sparclite86x, "sparclite86x" },
308 { TARGET_CPU_supersparc, "supersparc" },
309 { TARGET_CPU_v9, "v9" },
310 { TARGET_CPU_ultrasparc, "ultrasparc" },
311 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
314 const struct cpu_default *def;
315 /* Table of values for -m{cpu,tune}=. */
316 static struct cpu_table {
317 const char *const name;
318 const enum processor_type processor;
321 } const cpu_table[] = {
322 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
323 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
324 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
325 /* TI TMS390Z55 supersparc */
326 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
327 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
328 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
329 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
330 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
331 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
332 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
333 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
335 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
337 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
338 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
339 /* TI ultrasparc I, II, IIi */
340 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
341 /* Although insns using %y are deprecated, it is a clear win on current
343 |MASK_DEPRECATED_V8_INSNS},
344 /* TI ultrasparc III */
345 /* ??? Check if %y issue still holds true in ultra3. */
346 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
349 const struct cpu_table *cpu;
350 const struct sparc_cpu_select *sel;
353 #ifndef SPARC_BI_ARCH
354 /* Check for unsupported architecture size. */
355 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
356 error ("%s is not supported by this configuration",
357 DEFAULT_ARCH32_P ? "-m64" : "-m32");
360 /* We force all 64bit archs to use 128 bit long double */
361 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
363 error ("-mlong-double-64 not allowed with -m64");
364 target_flags |= MASK_LONG_DOUBLE_128;
367 /* Code model selection. */
368 sparc_cmodel = SPARC_DEFAULT_CMODEL;
372 sparc_cmodel = CM_32;
375 if (sparc_cmodel_string != NULL)
379 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
380 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
382 if (cmodel->name == NULL)
383 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
385 sparc_cmodel = cmodel->value;
388 error ("-mcmodel= is not supported on 32 bit systems");
391 fpu = TARGET_FPU; /* save current -mfpu status */
393 /* Set the default CPU. */
394 for (def = &cpu_default[0]; def->name; ++def)
395 if (def->cpu == TARGET_CPU_DEFAULT)
399 sparc_select[0].string = def->name;
401 for (sel = &sparc_select[0]; sel->name; ++sel)
405 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
406 if (! strcmp (sel->string, cpu->name))
409 sparc_cpu = cpu->processor;
413 target_flags &= ~cpu->disable;
414 target_flags |= cpu->enable;
420 error ("bad value (%s) for %s switch", sel->string, sel->name);
424 /* If -mfpu or -mno-fpu was explicitly used, don't override with
425 the processor default. Clear MASK_FPU_SET to avoid confusing
426 the reverse mapping from switch values to names. */
429 target_flags = (target_flags & ~MASK_FPU) | fpu;
430 target_flags &= ~MASK_FPU_SET;
433 /* Don't allow -mvis if FPU is disabled. */
435 target_flags &= ~MASK_VIS;
437 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
439 -m64 also implies v9. */
440 if (TARGET_VIS || TARGET_ARCH64)
442 target_flags |= MASK_V9;
443 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
446 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
447 if (TARGET_V9 && TARGET_ARCH32)
448 target_flags |= MASK_DEPRECATED_V8_INSNS;
450 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
451 if (! TARGET_V9 || TARGET_ARCH64)
452 target_flags &= ~MASK_V8PLUS;
454 /* Don't use stack biasing in 32 bit mode. */
456 target_flags &= ~MASK_STACK_BIAS;
458 /* Supply a default value for align_functions. */
459 if (align_functions == 0
460 && (sparc_cpu == PROCESSOR_ULTRASPARC
461 || sparc_cpu == PROCESSOR_ULTRASPARC3))
462 align_functions = 32;
464 /* Validate PCC_STRUCT_RETURN. */
465 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
466 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
468 /* Only use .uaxword when compiling for a 64-bit target. */
470 targetm.asm_out.unaligned_op.di = NULL;
472 /* Do various machine dependent initializations. */
475 /* Set up function hooks. */
476 init_machine_status = sparc_init_machine_status;
479 /* Miscellaneous utilities. */
481 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
482 or branch on register contents instructions. */
485 v9_regcmp_p (enum rtx_code code)
487 return (code == EQ || code == NE || code == GE || code == LT
488 || code == LE || code == GT);
492 /* Operand constraints. */
494 /* Return nonzero only if OP is a register of mode MODE,
498 reg_or_0_operand (rtx op, enum machine_mode mode)
500 if (register_operand (op, mode))
502 if (op == const0_rtx)
504 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
505 && CONST_DOUBLE_HIGH (op) == 0
506 && CONST_DOUBLE_LOW (op) == 0)
508 if (fp_zero_operand (op, mode))
513 /* Return nonzero only if OP is const1_rtx. */
516 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
518 return op == const1_rtx;
521 /* Nonzero if OP is a floating point value with value 0.0. */
524 fp_zero_operand (rtx op, enum machine_mode mode)
526 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
528 return op == CONST0_RTX (mode);
531 /* Nonzero if OP is a register operand in floating point register. */
534 fp_register_operand (rtx op, enum machine_mode mode)
536 if (! register_operand (op, mode))
538 if (GET_CODE (op) == SUBREG)
539 op = SUBREG_REG (op);
540 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
543 /* Nonzero if OP is a floating point constant which can
544 be loaded into an integer register using a single
545 sethi instruction. */
550 if (GET_CODE (op) == CONST_DOUBLE)
555 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
556 if (REAL_VALUES_EQUAL (r, dconst0) &&
557 ! REAL_VALUE_MINUS_ZERO (r))
559 REAL_VALUE_TO_TARGET_SINGLE (r, i);
560 if (SPARC_SETHI_P (i))
567 /* Nonzero if OP is a floating point constant which can
568 be loaded into an integer register using a single
574 if (GET_CODE (op) == CONST_DOUBLE)
579 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
580 if (REAL_VALUES_EQUAL (r, dconst0) &&
581 ! REAL_VALUE_MINUS_ZERO (r))
583 REAL_VALUE_TO_TARGET_SINGLE (r, i);
584 if (SPARC_SIMM13_P (i))
591 /* Nonzero if OP is a floating point constant which can
592 be loaded into an integer register using a high/losum
593 instruction sequence. */
596 fp_high_losum_p (rtx op)
598 /* The constraints calling this should only be in
599 SFmode move insns, so any constant which cannot
600 be moved using a single insn will do. */
601 if (GET_CODE (op) == CONST_DOUBLE)
606 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
607 if (REAL_VALUES_EQUAL (r, dconst0) &&
608 ! REAL_VALUE_MINUS_ZERO (r))
610 REAL_VALUE_TO_TARGET_SINGLE (r, i);
611 if (! SPARC_SETHI_P (i)
612 && ! SPARC_SIMM13_P (i))
619 /* Nonzero if OP is an integer register. */
622 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
624 return (register_operand (op, SImode)
625 || (TARGET_ARCH64 && register_operand (op, DImode)));
628 /* Nonzero if OP is a floating point condition code register. */
631 fcc_reg_operand (rtx op, enum machine_mode mode)
633 /* This can happen when recog is called from combine. Op may be a MEM.
634 Fail instead of calling abort in this case. */
635 if (GET_CODE (op) != REG)
638 if (mode != VOIDmode && mode != GET_MODE (op))
641 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
644 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
645 if (reg_renumber == 0)
646 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
647 return REGNO_OK_FOR_CCFP_P (REGNO (op));
649 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
653 /* Nonzero if OP is a floating point condition code fcc0 register. */
656 fcc0_reg_operand (rtx op, enum machine_mode mode)
658 /* This can happen when recog is called from combine. Op may be a MEM.
659 Fail instead of calling abort in this case. */
660 if (GET_CODE (op) != REG)
663 if (mode != VOIDmode && mode != GET_MODE (op))
666 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
669 return REGNO (op) == SPARC_FCC_REG;
672 /* Nonzero if OP is an integer or floating point condition code register. */
675 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
677 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
679 if (mode != VOIDmode && mode != GET_MODE (op))
682 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
687 return fcc_reg_operand (op, mode);
690 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
692 restore_operand (rtx op, enum machine_mode mode)
694 return (GET_CODE (op) == REG && GET_MODE (op) == mode
695 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
698 /* Call insn on SPARC can take a PC-relative constant address, or any regular
702 call_operand (rtx op, enum machine_mode mode)
704 if (GET_CODE (op) != MEM)
707 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
711 call_operand_address (rtx op, enum machine_mode mode)
713 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
716 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
717 otherwise return 0. */
720 tls_symbolic_operand (rtx op)
722 if (GET_CODE (op) != SYMBOL_REF)
724 return SYMBOL_REF_TLS_MODEL (op);
728 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
730 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
734 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
736 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
740 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
742 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
746 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
748 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
751 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
752 reference and a constant. */
755 symbolic_operand (register rtx op, enum machine_mode mode)
757 enum machine_mode omode = GET_MODE (op);
759 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
762 switch (GET_CODE (op))
765 return !SYMBOL_REF_TLS_MODEL (op);
772 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
773 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
774 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
775 && GET_CODE (XEXP (op, 1)) == CONST_INT);
782 /* Return truth value of statement that OP is a symbolic memory
783 operand of mode MODE. */
786 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
788 if (GET_CODE (op) == SUBREG)
789 op = SUBREG_REG (op);
790 if (GET_CODE (op) != MEM)
793 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
794 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
795 || GET_CODE (op) == LABEL_REF);
798 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
801 label_ref_operand (rtx op, enum machine_mode mode)
803 if (GET_CODE (op) != LABEL_REF)
805 if (GET_MODE (op) != mode)
810 /* Return 1 if the operand is an argument used in generating pic references
811 in either the medium/low or medium/anywhere code models of sparc64. */
814 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
816 /* Check for (const (minus (symbol_ref:GOT)
817 (const (minus (label) (pc))))). */
818 if (GET_CODE (op) != CONST)
821 if (GET_CODE (op) != MINUS)
823 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
825 /* ??? Ensure symbol is GOT. */
826 if (GET_CODE (XEXP (op, 1)) != CONST)
828 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
833 /* Return 1 if the operand is a data segment reference. This includes
834 the readonly data segment, or in other words anything but the text segment.
835 This is needed in the medium/anywhere code model on v9. These values
836 are accessed with EMBMEDANY_BASE_REG. */
839 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
841 switch (GET_CODE (op))
844 return ! SYMBOL_REF_FUNCTION_P (op);
846 /* Assume canonical format of symbol + constant.
849 return data_segment_operand (XEXP (op, 0), VOIDmode);
855 /* Return 1 if the operand is a text segment reference.
856 This is needed in the medium/anywhere code model on v9. */
859 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
861 switch (GET_CODE (op))
866 return SYMBOL_REF_FUNCTION_P (op);
868 /* Assume canonical format of symbol + constant.
871 return text_segment_operand (XEXP (op, 0), VOIDmode);
877 /* Return 1 if the operand is either a register or a memory operand that is
881 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
883 if (register_operand (op, mode))
886 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
893 splittable_symbolic_memory_operand (rtx op,
894 enum machine_mode mode ATTRIBUTE_UNUSED)
896 if (GET_CODE (op) != MEM)
898 if (! symbolic_operand (XEXP (op, 0), Pmode))
904 splittable_immediate_memory_operand (rtx op,
905 enum machine_mode mode ATTRIBUTE_UNUSED)
907 if (GET_CODE (op) != MEM)
909 if (! immediate_operand (XEXP (op, 0), Pmode))
914 /* Return truth value of whether OP is EQ or NE. */
917 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
919 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
922 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
923 or LTU for non-floating-point. We handle those specially. */
926 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
928 enum rtx_code code = GET_CODE (op);
930 if (GET_RTX_CLASS (code) != '<')
933 if (GET_MODE (XEXP (op, 0)) == CCFPmode
934 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
937 return (code != NE && code != EQ && code != GEU && code != LTU);
940 /* Return 1 if this is a comparison operator. This allows the use of
941 MATCH_OPERATOR to recognize all the branch insns. */
944 noov_compare_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
946 enum rtx_code code = GET_CODE (op);
948 if (GET_RTX_CLASS (code) != '<')
951 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
952 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
953 /* These are the only branches which work with CC_NOOVmode. */
954 return (code == EQ || code == NE || code == GE || code == LT);
958 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
959 MATCH_OPERATOR to recognize all the branch insns. */
962 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
964 enum rtx_code code = GET_CODE (op);
969 if (GET_RTX_CLASS (code) != '<')
972 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
973 /* These are the only branches which work with CCX_NOOVmode. */
974 return (code == EQ || code == NE || code == GE || code == LT);
975 return (GET_MODE (XEXP (op, 0)) == CCXmode);
978 /* Nonzero if OP is a comparison operator suitable for use in v9
979 conditional move or branch on register contents instructions. */
982 v9_regcmp_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
984 enum rtx_code code = GET_CODE (op);
986 if (GET_RTX_CLASS (code) != '<')
989 return v9_regcmp_p (code);
992 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
995 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
997 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1000 /* Return nonzero if OP is an operator of mode MODE which can set
1001 the condition codes explicitly. We do not include PLUS and MINUS
1002 because these require CC_NOOVmode, which we handle explicitly. */
1005 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1007 if (GET_CODE (op) == AND
1008 || GET_CODE (op) == IOR
1009 || GET_CODE (op) == XOR)
1015 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1016 complement its second operand and set the condition codes explicitly. */
1019 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1021 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1022 and (xor ... (not ...)) to (not (xor ...)). */
1023 return (GET_CODE (op) == AND
1024 || GET_CODE (op) == IOR);
1027 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1028 signed 13 bit immediate field. This is an acceptable SImode operand for
1029 most 3 address instructions. */
1032 arith_operand (rtx op, enum machine_mode mode)
1034 if (register_operand (op, mode))
1036 if (GET_CODE (op) != CONST_INT)
1038 return SMALL_INT32 (op);
1041 /* Return true if OP is a constant 4096 */
1044 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1046 if (GET_CODE (op) != CONST_INT)
1049 return INTVAL (op) == 4096;
1052 /* Return true if OP is suitable as second operand for add/sub */
1055 arith_add_operand (rtx op, enum machine_mode mode)
1057 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1060 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1061 immediate field of OR and XOR instructions. Used for 64-bit
1062 constant formation patterns. */
1064 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1066 return ((GET_CODE (op) == CONST_INT
1067 && SPARC_SIMM13_P (INTVAL (op)))
1068 #if HOST_BITS_PER_WIDE_INT != 64
1069 || (GET_CODE (op) == CONST_DOUBLE
1070 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1071 && (CONST_DOUBLE_HIGH (op) ==
1072 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1073 (HOST_WIDE_INT)-1 : 0)))
1078 /* The same, but only for sethi instructions. */
1080 const64_high_operand (rtx op, enum machine_mode mode)
1082 return ((GET_CODE (op) == CONST_INT
1083 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1084 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1086 || (GET_CODE (op) == CONST_DOUBLE
1087 && CONST_DOUBLE_HIGH (op) == 0
1088 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1089 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1092 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1093 signed 11 bit immediate field. This is an acceptable SImode operand for
1094 the movcc instructions. */
1097 arith11_operand (rtx op, enum machine_mode mode)
1099 return (register_operand (op, mode)
1100 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1103 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1104 signed 10 bit immediate field. This is an acceptable SImode operand for
1105 the movrcc instructions. */
1108 arith10_operand (rtx op, enum machine_mode mode)
1110 return (register_operand (op, mode)
1111 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1114 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1115 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1117 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1118 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1119 for most 3 address instructions. */
1122 arith_double_operand (rtx op, enum machine_mode mode)
1124 return (register_operand (op, mode)
1125 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1127 && GET_CODE (op) == CONST_DOUBLE
1128 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1129 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1131 && GET_CODE (op) == CONST_DOUBLE
1132 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1133 && ((CONST_DOUBLE_HIGH (op) == -1
1134 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1135 || (CONST_DOUBLE_HIGH (op) == 0
1136 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1139 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1142 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1144 return (TARGET_ARCH64 &&
1145 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1146 (GET_CODE (op) == CONST_DOUBLE &&
1147 CONST_DOUBLE_LOW (op) == 4096 &&
1148 CONST_DOUBLE_HIGH (op) == 0)));
1151 /* Return true if OP is suitable as second operand for add/sub in DImode */
1154 arith_double_add_operand (rtx op, enum machine_mode mode)
1156 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1159 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1160 can fit in an 11 bit immediate field. This is an acceptable DImode
1161 operand for the movcc instructions. */
1162 /* ??? Replace with arith11_operand? */
1165 arith11_double_operand (rtx op, enum machine_mode mode)
1167 return (register_operand (op, mode)
1168 || (GET_CODE (op) == CONST_DOUBLE
1169 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1170 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1171 && ((CONST_DOUBLE_HIGH (op) == -1
1172 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1173 || (CONST_DOUBLE_HIGH (op) == 0
1174 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1175 || (GET_CODE (op) == CONST_INT
1176 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1177 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1180 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1181 can fit in an 10 bit immediate field. This is an acceptable DImode
1182 operand for the movrcc instructions. */
1183 /* ??? Replace with arith10_operand? */
1186 arith10_double_operand (rtx op, enum machine_mode mode)
1188 return (register_operand (op, mode)
1189 || (GET_CODE (op) == CONST_DOUBLE
1190 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1191 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1192 && ((CONST_DOUBLE_HIGH (op) == -1
1193 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1194 || (CONST_DOUBLE_HIGH (op) == 0
1195 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1196 || (GET_CODE (op) == CONST_INT
1197 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1198 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1201 /* Return truth value of whether OP is an integer which fits the
1202 range constraining immediate operands in most three-address insns,
1203 which have a 13 bit immediate field. */
1206 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1208 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1212 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1214 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1215 || (GET_CODE (op) == CONST_DOUBLE
1216 && CONST_DOUBLE_HIGH (op) == 0
1217 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1220 /* Recognize operand values for the umul instruction. That instruction sign
1221 extends immediate values just like all other sparc instructions, but
1222 interprets the extended result as an unsigned number. */
1225 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1227 #if HOST_BITS_PER_WIDE_INT > 32
1228 /* All allowed constants will fit a CONST_INT. */
1229 return (GET_CODE (op) == CONST_INT
1230 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1231 || (INTVAL (op) >= 0xFFFFF000
1232 && INTVAL (op) <= 0xFFFFFFFF)));
1234 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1235 || (GET_CODE (op) == CONST_DOUBLE
1236 && CONST_DOUBLE_HIGH (op) == 0
1237 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1242 uns_arith_operand (rtx op, enum machine_mode mode)
1244 return register_operand (op, mode) || uns_small_int (op, mode);
1247 /* Return truth value of statement that OP is a call-clobbered register. */
1249 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1251 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1254 /* Return 1 if OP is a valid operand for the source of a move insn. */
1257 input_operand (rtx op, enum machine_mode mode)
1259 /* If both modes are non-void they must be the same. */
1260 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1263 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */
1264 if (GET_CODE (op) == CONSTANT_P_RTX)
1267 /* Allow any one instruction integer constant, and all CONST_INT
1268 variants when we are working in DImode and !arch64. */
1269 if (GET_MODE_CLASS (mode) == MODE_INT
1270 && ((GET_CODE (op) == CONST_INT
1271 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1272 || SPARC_SIMM13_P (INTVAL (op))
1274 && ! TARGET_ARCH64)))
1276 && GET_CODE (op) == CONST_DOUBLE
1277 && ((CONST_DOUBLE_HIGH (op) == 0
1278 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1280 #if HOST_BITS_PER_WIDE_INT == 64
1281 (CONST_DOUBLE_HIGH (op) == 0
1282 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1284 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1285 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1286 && CONST_DOUBLE_HIGH (op) == 0)
1287 || (CONST_DOUBLE_HIGH (op) == -1
1288 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1293 /* If !arch64 and this is a DImode const, allow it so that
1294 the splits can be generated. */
1297 && GET_CODE (op) == CONST_DOUBLE)
1300 if (register_operand (op, mode))
1303 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1304 && GET_CODE (op) == CONST_DOUBLE)
1307 /* If this is a SUBREG, look inside so that we handle
1308 paradoxical ones. */
1309 if (GET_CODE (op) == SUBREG)
1310 op = SUBREG_REG (op);
1312 /* Check for valid MEM forms. */
1313 if (GET_CODE (op) == MEM)
1315 rtx inside = XEXP (op, 0);
1317 if (GET_CODE (inside) == LO_SUM)
1319 /* We can't allow these because all of the splits
1320 (eventually as they trickle down into DFmode
1321 splits) require offsettable memory references. */
1323 && GET_MODE (op) == TFmode)
1326 return (register_operand (XEXP (inside, 0), Pmode)
1327 && CONSTANT_P (XEXP (inside, 1)));
1329 return memory_address_p (mode, inside);
1336 /* We know it can't be done in one insn when we get here,
1337 the movsi expander guarantees this. */
1339 sparc_emit_set_const32 (rtx op0, rtx op1)
1341 enum machine_mode mode = GET_MODE (op0);
1344 if (GET_CODE (op1) == CONST_INT)
1346 HOST_WIDE_INT value = INTVAL (op1);
1348 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1349 || SPARC_SIMM13_P (value))
1353 /* Full 2-insn decomposition is needed. */
1354 if (reload_in_progress || reload_completed)
1357 temp = gen_reg_rtx (mode);
1359 if (GET_CODE (op1) == CONST_INT)
1361 /* Emit them as real moves instead of a HIGH/LO_SUM,
1362 this way CSE can see everything and reuse intermediate
1363 values if it wants. */
1365 && HOST_BITS_PER_WIDE_INT != 64
1366 && (INTVAL (op1) & 0x80000000) != 0)
1367 emit_insn (gen_rtx_SET
1369 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1372 emit_insn (gen_rtx_SET (VOIDmode, temp,
1373 GEN_INT (INTVAL (op1)
1374 & ~(HOST_WIDE_INT)0x3ff)));
1376 emit_insn (gen_rtx_SET (VOIDmode,
1378 gen_rtx_IOR (mode, temp,
1379 GEN_INT (INTVAL (op1) & 0x3ff))));
1383 /* A symbol, emit in the traditional way. */
1384 emit_insn (gen_rtx_SET (VOIDmode, temp,
1385 gen_rtx_HIGH (mode, op1)));
1386 emit_insn (gen_rtx_SET (VOIDmode,
1387 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1393 /* SPARC-v9 code-model support. */
1395 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp1)
1399 if (temp1 && GET_MODE (temp1) == TImode)
1402 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1405 switch (sparc_cmodel)
1408 /* The range spanned by all instructions in the object is less
1409 than 2^31 bytes (2GB) and the distance from any instruction
1410 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1411 than 2^31 bytes (2GB).
1413 The executable must be in the low 4TB of the virtual address
1416 sethi %hi(symbol), %temp
1417 or %temp, %lo(symbol), %reg */
1418 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1419 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1423 /* The range spanned by all instructions in the object is less
1424 than 2^31 bytes (2GB) and the distance from any instruction
1425 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1426 than 2^31 bytes (2GB).
1428 The executable must be in the low 16TB of the virtual address
1431 sethi %h44(symbol), %temp1
1432 or %temp1, %m44(symbol), %temp2
1433 sllx %temp2, 12, %temp3
1434 or %temp3, %l44(symbol), %reg */
1435 emit_insn (gen_seth44 (op0, op1));
1436 emit_insn (gen_setm44 (op0, op0, op1));
1437 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1438 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1439 emit_insn (gen_setl44 (op0, temp1, op1));
1443 /* The range spanned by all instructions in the object is less
1444 than 2^31 bytes (2GB) and the distance from any instruction
1445 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1446 than 2^31 bytes (2GB).
1448 The executable can be placed anywhere in the virtual address
1451 sethi %hh(symbol), %temp1
1452 sethi %lm(symbol), %temp2
1453 or %temp1, %hm(symbol), %temp3
1454 or %temp2, %lo(symbol), %temp4
1455 sllx %temp3, 32, %temp5
1456 or %temp4, %temp5, %reg */
1458 /* It is possible that one of the registers we got for operands[2]
1459 might coincide with that of operands[0] (which is why we made
1460 it TImode). Pick the other one to use as our scratch. */
1461 if (rtx_equal_p (temp1, op0))
1464 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1469 emit_insn (gen_sethh (op0, op1));
1470 emit_insn (gen_setlm (temp1, op1));
1471 emit_insn (gen_sethm (op0, op0, op1));
1472 emit_insn (gen_rtx_SET (VOIDmode, op0,
1473 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1474 emit_insn (gen_rtx_SET (VOIDmode, op0,
1475 gen_rtx_PLUS (DImode, op0, temp1)));
1476 emit_insn (gen_setlo (op0, op0, op1));
1480 /* Old old old backwards compatibility kruft here.
1481 Essentially it is MEDLOW with a fixed 64-bit
1482 virtual base added to all data segment addresses.
1483 Text-segment stuff is computed like MEDANY, we can't
1484 reuse the code above because the relocation knobs
1487 Data segment: sethi %hi(symbol), %temp1
1488 or %temp1, %lo(symbol), %temp2
1489 add %temp2, EMBMEDANY_BASE_REG, %reg
1491 Text segment: sethi %uhi(symbol), %temp1
1492 sethi %hi(symbol), %temp2
1493 or %temp1, %ulo(symbol), %temp3
1494 or %temp2, %lo(symbol), %temp4
1495 sllx %temp3, 32, %temp5
1496 or %temp4, %temp5, %reg */
1497 if (data_segment_operand (op1, GET_MODE (op1)))
1499 emit_insn (gen_embmedany_sethi (temp1, op1));
1500 emit_insn (gen_embmedany_brsum (op0, temp1));
1501 emit_insn (gen_embmedany_losum (op0, op0, op1));
1505 /* It is possible that one of the registers we got for operands[2]
1506 might coincide with that of operands[0] (which is why we made
1507 it TImode). Pick the other one to use as our scratch. */
1508 if (rtx_equal_p (temp1, op0))
1511 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1516 emit_insn (gen_embmedany_textuhi (op0, op1));
1517 emit_insn (gen_embmedany_texthi (temp1, op1));
1518 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1519 emit_insn (gen_rtx_SET (VOIDmode, op0,
1520 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1521 emit_insn (gen_rtx_SET (VOIDmode, op0,
1522 gen_rtx_PLUS (DImode, op0, temp1)));
1523 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1532 /* These avoid problems when cross compiling. If we do not
1533 go through all this hair then the optimizer will see
1534 invalid REG_EQUAL notes or in some cases none at all. */
1535 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1536 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1537 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1538 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1540 #if HOST_BITS_PER_WIDE_INT == 64
1541 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1542 #define GEN_INT64(__x) GEN_INT (__x)
1544 #define GEN_HIGHINT64(__x) \
1545 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1546 #define GEN_INT64(__x) \
1547 immed_double_const ((__x) & 0xffffffff, \
1548 ((__x) & 0x80000000 ? -1 : 0), DImode)
1551 /* The optimizer is not to assume anything about exactly
1552 which bits are set for a HIGH, they are unspecified.
1553 Unfortunately this leads to many missed optimizations
1554 during CSE. We mask out the non-HIGH bits, and matches
1555 a plain movdi, to alleviate this problem. */
1557 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1559 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1563 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1565 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1569 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1571 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1575 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1577 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1580 /* Worker routines for 64-bit constant formation on arch64.
1581 One of the key things to be doing in these emissions is
1582 to create as many temp REGs as possible. This makes it
1583 possible for half-built constants to be used later when
1584 such values are similar to something required later on.
1585 Without doing this, the optimizer cannot see such
1588 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1589 unsigned HOST_WIDE_INT, int);
1592 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1593 unsigned HOST_WIDE_INT low_bits, int is_neg)
1595 unsigned HOST_WIDE_INT high_bits;
1598 high_bits = (~low_bits) & 0xffffffff;
1600 high_bits = low_bits;
1602 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1605 emit_insn (gen_rtx_SET (VOIDmode, op0,
1606 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1610 /* If we are XOR'ing with -1, then we should emit a one's complement
1611 instead. This way the combiner will notice logical operations
1612 such as ANDN later on and substitute. */
1613 if ((low_bits & 0x3ff) == 0x3ff)
1615 emit_insn (gen_rtx_SET (VOIDmode, op0,
1616 gen_rtx_NOT (DImode, temp)));
1620 emit_insn (gen_rtx_SET (VOIDmode, op0,
1621 gen_safe_XOR64 (temp,
1622 (-(HOST_WIDE_INT)0x400
1623 | (low_bits & 0x3ff)))));
1628 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1629 unsigned HOST_WIDE_INT, int);
1632 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1633 unsigned HOST_WIDE_INT high_bits,
1634 unsigned HOST_WIDE_INT low_immediate,
1639 if ((high_bits & 0xfffffc00) != 0)
1641 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1642 if ((high_bits & ~0xfffffc00) != 0)
1643 emit_insn (gen_rtx_SET (VOIDmode, op0,
1644 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1650 emit_insn (gen_safe_SET64 (temp, high_bits));
1654 /* Now shift it up into place. */
1655 emit_insn (gen_rtx_SET (VOIDmode, op0,
1656 gen_rtx_ASHIFT (DImode, temp2,
1657 GEN_INT (shift_count))));
1659 /* If there is a low immediate part piece, finish up by
1660 putting that in as well. */
1661 if (low_immediate != 0)
1662 emit_insn (gen_rtx_SET (VOIDmode, op0,
1663 gen_safe_OR64 (op0, low_immediate)));
1666 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1667 unsigned HOST_WIDE_INT);
1669 /* Full 64-bit constant decomposition. Even though this is the
1670 'worst' case, we still optimize a few things away. */
1672 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1673 unsigned HOST_WIDE_INT high_bits,
1674 unsigned HOST_WIDE_INT low_bits)
1678 if (reload_in_progress || reload_completed)
1681 sub_temp = gen_reg_rtx (DImode);
1683 if ((high_bits & 0xfffffc00) != 0)
1685 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1686 if ((high_bits & ~0xfffffc00) != 0)
1687 emit_insn (gen_rtx_SET (VOIDmode,
1689 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1695 emit_insn (gen_safe_SET64 (temp, high_bits));
1699 if (!reload_in_progress && !reload_completed)
1701 rtx temp2 = gen_reg_rtx (DImode);
1702 rtx temp3 = gen_reg_rtx (DImode);
1703 rtx temp4 = gen_reg_rtx (DImode);
1705 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1706 gen_rtx_ASHIFT (DImode, sub_temp,
1709 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1710 if ((low_bits & ~0xfffffc00) != 0)
1712 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1713 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1714 emit_insn (gen_rtx_SET (VOIDmode, op0,
1715 gen_rtx_PLUS (DImode, temp4, temp3)));
1719 emit_insn (gen_rtx_SET (VOIDmode, op0,
1720 gen_rtx_PLUS (DImode, temp4, temp2)));
1725 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1726 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1727 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1730 /* We are in the middle of reload, so this is really
1731 painful. However we do still make an attempt to
1732 avoid emitting truly stupid code. */
1733 if (low1 != const0_rtx)
1735 emit_insn (gen_rtx_SET (VOIDmode, op0,
1736 gen_rtx_ASHIFT (DImode, sub_temp,
1737 GEN_INT (to_shift))));
1738 emit_insn (gen_rtx_SET (VOIDmode, op0,
1739 gen_rtx_IOR (DImode, op0, low1)));
1747 if (low2 != const0_rtx)
1749 emit_insn (gen_rtx_SET (VOIDmode, op0,
1750 gen_rtx_ASHIFT (DImode, sub_temp,
1751 GEN_INT (to_shift))));
1752 emit_insn (gen_rtx_SET (VOIDmode, op0,
1753 gen_rtx_IOR (DImode, op0, low2)));
1761 emit_insn (gen_rtx_SET (VOIDmode, op0,
1762 gen_rtx_ASHIFT (DImode, sub_temp,
1763 GEN_INT (to_shift))));
1764 if (low3 != const0_rtx)
1765 emit_insn (gen_rtx_SET (VOIDmode, op0,
1766 gen_rtx_IOR (DImode, op0, low3)));
1771 /* Analyze a 64-bit constant for certain properties. */
1772 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1773 unsigned HOST_WIDE_INT,
1774 int *, int *, int *);
1777 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1778 unsigned HOST_WIDE_INT low_bits,
1779 int *hbsp, int *lbsp, int *abbasp)
1781 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1784 lowest_bit_set = highest_bit_set = -1;
1788 if ((lowest_bit_set == -1)
1789 && ((low_bits >> i) & 1))
1791 if ((highest_bit_set == -1)
1792 && ((high_bits >> (32 - i - 1)) & 1))
1793 highest_bit_set = (64 - i - 1);
1796 && ((highest_bit_set == -1)
1797 || (lowest_bit_set == -1)));
1803 if ((lowest_bit_set == -1)
1804 && ((high_bits >> i) & 1))
1805 lowest_bit_set = i + 32;
1806 if ((highest_bit_set == -1)
1807 && ((low_bits >> (32 - i - 1)) & 1))
1808 highest_bit_set = 32 - i - 1;
1811 && ((highest_bit_set == -1)
1812 || (lowest_bit_set == -1)));
1814 /* If there are no bits set this should have gone out
1815 as one instruction! */
1816 if (lowest_bit_set == -1
1817 || highest_bit_set == -1)
1819 all_bits_between_are_set = 1;
1820 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1824 if ((low_bits & (1 << i)) != 0)
1829 if ((high_bits & (1 << (i - 32))) != 0)
1832 all_bits_between_are_set = 0;
1835 *hbsp = highest_bit_set;
1836 *lbsp = lowest_bit_set;
1837 *abbasp = all_bits_between_are_set;
1840 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1843 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1844 unsigned HOST_WIDE_INT low_bits)
1846 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1849 || high_bits == 0xffffffff)
1852 analyze_64bit_constant (high_bits, low_bits,
1853 &highest_bit_set, &lowest_bit_set,
1854 &all_bits_between_are_set);
1856 if ((highest_bit_set == 63
1857 || lowest_bit_set == 0)
1858 && all_bits_between_are_set != 0)
1861 if ((highest_bit_set - lowest_bit_set) < 21)
1867 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1868 unsigned HOST_WIDE_INT,
1871 static unsigned HOST_WIDE_INT
1872 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1873 unsigned HOST_WIDE_INT low_bits,
1874 int lowest_bit_set, int shift)
1876 HOST_WIDE_INT hi, lo;
1878 if (lowest_bit_set < 32)
1880 lo = (low_bits >> lowest_bit_set) << shift;
1881 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1886 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1893 /* Here we are sure to be arch64 and this is an integer constant
1894 being loaded into a register. Emit the most efficient
1895 insn sequence possible. Detection of all the 1-insn cases
1896 has been done already. */
1898 sparc_emit_set_const64 (rtx op0, rtx op1)
1900 unsigned HOST_WIDE_INT high_bits, low_bits;
1901 int lowest_bit_set, highest_bit_set;
1902 int all_bits_between_are_set;
1905 /* Sanity check that we know what we are working with. */
1906 if (! TARGET_ARCH64)
1909 if (GET_CODE (op0) != SUBREG)
1911 if (GET_CODE (op0) != REG
1912 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1913 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1917 if (reload_in_progress || reload_completed)
1920 temp = gen_reg_rtx (DImode);
1922 if (GET_CODE (op1) != CONST_DOUBLE
1923 && GET_CODE (op1) != CONST_INT)
1925 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1929 if (GET_CODE (op1) == CONST_DOUBLE)
1931 #if HOST_BITS_PER_WIDE_INT == 64
1932 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1933 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1935 high_bits = CONST_DOUBLE_HIGH (op1);
1936 low_bits = CONST_DOUBLE_LOW (op1);
1941 #if HOST_BITS_PER_WIDE_INT == 64
1942 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1943 low_bits = (INTVAL (op1) & 0xffffffff);
1945 high_bits = ((INTVAL (op1) < 0) ?
1948 low_bits = INTVAL (op1);
1952 /* low_bits bits 0 --> 31
1953 high_bits bits 32 --> 63 */
1955 analyze_64bit_constant (high_bits, low_bits,
1956 &highest_bit_set, &lowest_bit_set,
1957 &all_bits_between_are_set);
1959 /* First try for a 2-insn sequence. */
1961 /* These situations are preferred because the optimizer can
1962 * do more things with them:
1964 * sllx %reg, shift, %reg
1966 * srlx %reg, shift, %reg
1967 * 3) mov some_small_const, %reg
1968 * sllx %reg, shift, %reg
1970 if (((highest_bit_set == 63
1971 || lowest_bit_set == 0)
1972 && all_bits_between_are_set != 0)
1973 || ((highest_bit_set - lowest_bit_set) < 12))
1975 HOST_WIDE_INT the_const = -1;
1976 int shift = lowest_bit_set;
1978 if ((highest_bit_set != 63
1979 && lowest_bit_set != 0)
1980 || all_bits_between_are_set == 0)
1983 create_simple_focus_bits (high_bits, low_bits,
1986 else if (lowest_bit_set == 0)
1987 shift = -(63 - highest_bit_set);
1989 if (! SPARC_SIMM13_P (the_const))
1992 emit_insn (gen_safe_SET64 (temp, the_const));
1994 emit_insn (gen_rtx_SET (VOIDmode,
1996 gen_rtx_ASHIFT (DImode,
2000 emit_insn (gen_rtx_SET (VOIDmode,
2002 gen_rtx_LSHIFTRT (DImode,
2004 GEN_INT (-shift))));
2010 /* Now a range of 22 or less bits set somewhere.
2011 * 1) sethi %hi(focus_bits), %reg
2012 * sllx %reg, shift, %reg
2013 * 2) sethi %hi(focus_bits), %reg
2014 * srlx %reg, shift, %reg
2016 if ((highest_bit_set - lowest_bit_set) < 21)
2018 unsigned HOST_WIDE_INT focus_bits =
2019 create_simple_focus_bits (high_bits, low_bits,
2020 lowest_bit_set, 10);
2022 if (! SPARC_SETHI_P (focus_bits))
2025 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2027 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2028 if (lowest_bit_set < 10)
2029 emit_insn (gen_rtx_SET (VOIDmode,
2031 gen_rtx_LSHIFTRT (DImode, temp,
2032 GEN_INT (10 - lowest_bit_set))));
2033 else if (lowest_bit_set > 10)
2034 emit_insn (gen_rtx_SET (VOIDmode,
2036 gen_rtx_ASHIFT (DImode, temp,
2037 GEN_INT (lowest_bit_set - 10))));
2043 /* 1) sethi %hi(low_bits), %reg
2044 * or %reg, %lo(low_bits), %reg
2045 * 2) sethi %hi(~low_bits), %reg
2046 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2049 || high_bits == 0xffffffff)
2051 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2052 (high_bits == 0xffffffff));
2056 /* Now, try 3-insn sequences. */
2058 /* 1) sethi %hi(high_bits), %reg
2059 * or %reg, %lo(high_bits), %reg
2060 * sllx %reg, 32, %reg
2064 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2068 /* We may be able to do something quick
2069 when the constant is negated, so try that. */
2070 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2071 (~low_bits) & 0xfffffc00))
2073 /* NOTE: The trailing bits get XOR'd so we need the
2074 non-negated bits, not the negated ones. */
2075 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2077 if ((((~high_bits) & 0xffffffff) == 0
2078 && ((~low_bits) & 0x80000000) == 0)
2079 || (((~high_bits) & 0xffffffff) == 0xffffffff
2080 && ((~low_bits) & 0x80000000) != 0))
2082 int fast_int = (~low_bits & 0xffffffff);
2084 if ((SPARC_SETHI_P (fast_int)
2085 && (~high_bits & 0xffffffff) == 0)
2086 || SPARC_SIMM13_P (fast_int))
2087 emit_insn (gen_safe_SET64 (temp, fast_int));
2089 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2094 #if HOST_BITS_PER_WIDE_INT == 64
2095 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2096 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2098 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2099 (~high_bits) & 0xffffffff,
2102 sparc_emit_set_const64 (temp, negated_const);
2105 /* If we are XOR'ing with -1, then we should emit a one's complement
2106 instead. This way the combiner will notice logical operations
2107 such as ANDN later on and substitute. */
2108 if (trailing_bits == 0x3ff)
2110 emit_insn (gen_rtx_SET (VOIDmode, op0,
2111 gen_rtx_NOT (DImode, temp)));
2115 emit_insn (gen_rtx_SET (VOIDmode,
2117 gen_safe_XOR64 (temp,
2118 (-0x400 | trailing_bits))));
2123 /* 1) sethi %hi(xxx), %reg
2124 * or %reg, %lo(xxx), %reg
2125 * sllx %reg, yyy, %reg
2127 * ??? This is just a generalized version of the low_bits==0
2128 * thing above, FIXME...
2130 if ((highest_bit_set - lowest_bit_set) < 32)
2132 unsigned HOST_WIDE_INT focus_bits =
2133 create_simple_focus_bits (high_bits, low_bits,
2136 /* We can't get here in this state. */
2137 if (highest_bit_set < 32
2138 || lowest_bit_set >= 32)
2141 /* So what we know is that the set bits straddle the
2142 middle of the 64-bit word. */
2143 sparc_emit_set_const64_quick2 (op0, temp,
2149 /* 1) sethi %hi(high_bits), %reg
2150 * or %reg, %lo(high_bits), %reg
2151 * sllx %reg, 32, %reg
2152 * or %reg, low_bits, %reg
2154 if (SPARC_SIMM13_P(low_bits)
2155 && ((int)low_bits > 0))
2157 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2161 /* The easiest way when all else fails, is full decomposition. */
2163 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2164 high_bits, low_bits, ~high_bits, ~low_bits);
2166 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2169 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2170 return the mode to be used for the comparison. For floating-point,
2171 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2172 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2173 processing is needed. */
2176 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2178 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2204 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2205 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2207 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2208 return CCX_NOOVmode;
2214 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2221 /* X and Y are two things to compare using CODE. Emit the compare insn and
2222 return the rtx for the cc reg in the proper mode. */
2225 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2227 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2230 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2231 fcc regs (cse can't tell they're really call clobbered regs and will
2232 remove a duplicate comparison even if there is an intervening function
2233 call - it will then try to reload the cc reg via an int reg which is why
2234 we need the movcc patterns). It is possible to provide the movcc
2235 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2236 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2237 to tell cse that CCFPE mode registers (even pseudos) are call
2240 /* ??? This is an experiment. Rather than making changes to cse which may
2241 or may not be easy/clean, we do our own cse. This is possible because
2242 we will generate hard registers. Cse knows they're call clobbered (it
2243 doesn't know the same thing about pseudos). If we guess wrong, no big
2244 deal, but if we win, great! */
2246 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2247 #if 1 /* experiment */
2250 /* We cycle through the registers to ensure they're all exercised. */
2251 static int next_fcc_reg = 0;
2252 /* Previous x,y for each fcc reg. */
2253 static rtx prev_args[4][2];
2255 /* Scan prev_args for x,y. */
2256 for (reg = 0; reg < 4; reg++)
2257 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2262 prev_args[reg][0] = x;
2263 prev_args[reg][1] = y;
2264 next_fcc_reg = (next_fcc_reg + 1) & 3;
2266 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2269 cc_reg = gen_reg_rtx (mode);
2270 #endif /* ! experiment */
2271 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2272 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2274 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2276 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2277 gen_rtx_COMPARE (mode, x, y)));
2282 /* This function is used for v9 only.
2283 CODE is the code for an Scc's comparison.
2284 OPERANDS[0] is the target of the Scc insn.
2285 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2286 been generated yet).
2288 This function is needed to turn
2291 (gt (reg:CCX 100 %icc)
2295 (gt:DI (reg:CCX 100 %icc)
2298 IE: The instruction recognizer needs to see the mode of the comparison to
2299 find the right instruction. We could use "gt:DI" right in the
2300 define_expand, but leaving it out allows us to handle DI, SI, etc.
2302 We refer to the global sparc compare operands sparc_compare_op0 and
2303 sparc_compare_op1. */
2306 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2311 && (GET_MODE (sparc_compare_op0) == DImode
2312 || GET_MODE (operands[0]) == DImode))
2315 op0 = sparc_compare_op0;
2316 op1 = sparc_compare_op1;
2318 /* Try to use the movrCC insns. */
2320 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2321 && op1 == const0_rtx
2322 && v9_regcmp_p (compare_code))
2324 /* Special case for op0 != 0. This can be done with one instruction if
2325 operands[0] == sparc_compare_op0. */
2327 if (compare_code == NE
2328 && GET_MODE (operands[0]) == DImode
2329 && rtx_equal_p (op0, operands[0]))
2331 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2332 gen_rtx_IF_THEN_ELSE (DImode,
2333 gen_rtx_fmt_ee (compare_code, DImode,
2340 if (reg_overlap_mentioned_p (operands[0], op0))
2342 /* Handle the case where operands[0] == sparc_compare_op0.
2343 We "early clobber" the result. */
2344 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2345 emit_move_insn (op0, sparc_compare_op0);
2348 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2349 if (GET_MODE (op0) != DImode)
2351 temp = gen_reg_rtx (DImode);
2352 convert_move (temp, op0, 0);
2356 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2357 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2358 gen_rtx_fmt_ee (compare_code, DImode,
2366 operands[1] = gen_compare_reg (compare_code, op0, op1);
2368 switch (GET_MODE (operands[1]))
2378 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2379 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2380 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2381 gen_rtx_fmt_ee (compare_code,
2382 GET_MODE (operands[1]),
2383 operands[1], const0_rtx),
2384 const1_rtx, operands[0])));
2389 /* Emit a conditional jump insn for the v9 architecture using comparison code
2390 CODE and jump target LABEL.
2391 This function exists to take advantage of the v9 brxx insns. */
2394 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2396 emit_jump_insn (gen_rtx_SET (VOIDmode,
2398 gen_rtx_IF_THEN_ELSE (VOIDmode,
2399 gen_rtx_fmt_ee (code, GET_MODE (op0),
2401 gen_rtx_LABEL_REF (VOIDmode, label),
2405 /* Generate a DFmode part of a hard TFmode register.
2406 REG is the TFmode hard register, LOW is 1 for the
2407 low 64bit of the register and 0 otherwise.
2410 gen_df_reg (rtx reg, int low)
2412 int regno = REGNO (reg);
2414 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2415 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2416 return gen_rtx_REG (DFmode, regno);
2419 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2420 Unlike normal calls, TFmode operands are passed by reference. It is
2421 assumed that no more than 3 operands are required. */
2424 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2426 rtx ret_slot = NULL, arg[3], func_sym;
2429 /* We only expect to be called for conversions, unary, and binary ops. */
2430 if (nargs < 2 || nargs > 3)
2433 for (i = 0; i < nargs; ++i)
2435 rtx this_arg = operands[i];
2438 /* TFmode arguments and return values are passed by reference. */
2439 if (GET_MODE (this_arg) == TFmode)
2441 int force_stack_temp;
2443 force_stack_temp = 0;
2444 if (TARGET_BUGGY_QP_LIB && i == 0)
2445 force_stack_temp = 1;
2447 if (GET_CODE (this_arg) == MEM
2448 && ! force_stack_temp)
2449 this_arg = XEXP (this_arg, 0);
2450 else if (CONSTANT_P (this_arg)
2451 && ! force_stack_temp)
2453 this_slot = force_const_mem (TFmode, this_arg);
2454 this_arg = XEXP (this_slot, 0);
2458 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2460 /* Operand 0 is the return value. We'll copy it out later. */
2462 emit_move_insn (this_slot, this_arg);
2464 ret_slot = this_slot;
2466 this_arg = XEXP (this_slot, 0);
2473 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2475 if (GET_MODE (operands[0]) == TFmode)
2478 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2479 arg[0], GET_MODE (arg[0]),
2480 arg[1], GET_MODE (arg[1]));
2482 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2483 arg[0], GET_MODE (arg[0]),
2484 arg[1], GET_MODE (arg[1]),
2485 arg[2], GET_MODE (arg[2]));
2488 emit_move_insn (operands[0], ret_slot);
2497 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2498 GET_MODE (operands[0]), 1,
2499 arg[1], GET_MODE (arg[1]));
2501 if (ret != operands[0])
2502 emit_move_insn (operands[0], ret);
2506 /* Expand soft-float TFmode calls to sparc abi routines. */
2509 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2531 emit_soft_tfmode_libcall (func, 3, operands);
2535 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2548 emit_soft_tfmode_libcall (func, 2, operands);
2552 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2559 switch (GET_MODE (operands[1]))
2572 case FLOAT_TRUNCATE:
2573 switch (GET_MODE (operands[0]))
2587 switch (GET_MODE (operands[1]))
2600 case UNSIGNED_FLOAT:
2601 switch (GET_MODE (operands[1]))
2615 switch (GET_MODE (operands[0]))
2629 switch (GET_MODE (operands[0]))
2646 emit_soft_tfmode_libcall (func, 2, operands);
2649 /* Expand a hard-float tfmode operation. All arguments must be in
2653 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2657 if (GET_RTX_CLASS (code) == '1')
2659 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2660 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2664 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2665 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2666 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2667 operands[1], operands[2]);
2670 if (register_operand (operands[0], VOIDmode))
2673 dest = gen_reg_rtx (GET_MODE (operands[0]));
2675 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2677 if (dest != operands[0])
2678 emit_move_insn (operands[0], dest);
2682 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2684 if (TARGET_HARD_QUAD)
2685 emit_hard_tfmode_operation (code, operands);
2687 emit_soft_tfmode_binop (code, operands);
2691 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2693 if (TARGET_HARD_QUAD)
2694 emit_hard_tfmode_operation (code, operands);
2696 emit_soft_tfmode_unop (code, operands);
2700 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2702 if (TARGET_HARD_QUAD)
2703 emit_hard_tfmode_operation (code, operands);
2705 emit_soft_tfmode_cvt (code, operands);
2708 /* Return nonzero if a return peephole merging return with
2709 setting of output register is ok. */
2711 leaf_return_peephole_ok (void)
2713 return (actual_fsize == 0);
2716 /* Return nonzero if a branch/jump/call instruction will be emitting
2717 nop into its delay slot. */
2720 empty_delay_slot (rtx insn)
2724 /* If no previous instruction (should not happen), return true. */
2725 if (PREV_INSN (insn) == NULL)
2728 seq = NEXT_INSN (PREV_INSN (insn));
2729 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2735 /* Return nonzero if TRIAL can go into the function epilogue's
2736 delay slot. SLOT is the slot we are trying to fill. */
2739 eligible_for_epilogue_delay (rtx trial, int slot)
2746 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2749 if (get_attr_length (trial) != 1)
2752 /* If there are any call-saved registers, we should scan TRIAL if it
2753 does not reference them. For now just make it easy. */
2757 /* If the function uses __builtin_eh_return, the eh_return machinery
2758 occupies the delay slot. */
2759 if (current_function_calls_eh_return)
2762 /* In the case of a true leaf function, anything can go into the delay slot.
2763 A delay slot only exists however if the frame size is zero, otherwise
2764 we will put an insn to adjust the stack after the return. */
2765 if (current_function_uses_only_leaf_regs)
2767 if (leaf_return_peephole_ok ())
2768 return ((get_attr_in_uncond_branch_delay (trial)
2769 == IN_BRANCH_DELAY_TRUE));
2773 pat = PATTERN (trial);
2775 /* Otherwise, only operations which can be done in tandem with
2776 a `restore' or `return' insn can go into the delay slot. */
2777 if (GET_CODE (SET_DEST (pat)) != REG
2778 || REGNO (SET_DEST (pat)) < 24)
2781 /* If this instruction sets up floating point register and we have a return
2782 instruction, it can probably go in. But restore will not work
2784 if (REGNO (SET_DEST (pat)) >= 32)
2786 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2787 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2792 /* The set of insns matched here must agree precisely with the set of
2793 patterns paired with a RETURN in sparc.md. */
2795 src = SET_SRC (pat);
2797 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2798 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2799 && arith_operand (src, GET_MODE (src)))
2802 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2804 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2807 /* This matches "*return_di". */
2808 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2809 && arith_double_operand (src, GET_MODE (src)))
2810 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2812 /* This matches "*return_sf_no_fpu". */
2813 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2814 && register_operand (src, SFmode))
2817 /* If we have return instruction, anything that does not use
2818 local or output registers and can go into a delay slot wins. */
2819 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2820 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2823 /* This matches "*return_addsi". */
2824 else if (GET_CODE (src) == PLUS
2825 && arith_operand (XEXP (src, 0), SImode)
2826 && arith_operand (XEXP (src, 1), SImode)
2827 && (register_operand (XEXP (src, 0), SImode)
2828 || register_operand (XEXP (src, 1), SImode)))
2831 /* This matches "*return_adddi". */
2832 else if (GET_CODE (src) == PLUS
2833 && arith_double_operand (XEXP (src, 0), DImode)
2834 && arith_double_operand (XEXP (src, 1), DImode)
2835 && (register_operand (XEXP (src, 0), DImode)
2836 || register_operand (XEXP (src, 1), DImode)))
2839 /* This can match "*return_losum_[sd]i".
2840 Catch only some cases, so that return_losum* don't have
2842 else if (GET_CODE (src) == LO_SUM
2843 && ! TARGET_CM_MEDMID
2844 && ((register_operand (XEXP (src, 0), SImode)
2845 && immediate_operand (XEXP (src, 1), SImode))
2847 && register_operand (XEXP (src, 0), DImode)
2848 && immediate_operand (XEXP (src, 1), DImode))))
2851 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2852 else if (GET_CODE (src) == ASHIFT
2853 && (register_operand (XEXP (src, 0), SImode)
2854 || register_operand (XEXP (src, 0), DImode))
2855 && XEXP (src, 1) == const1_rtx)
2861 /* Return nonzero if TRIAL can go into the call delay slot. */
2863 tls_call_delay (rtx trial)
2868 call __tls_get_addr, %tgd_call (foo)
2869 add %l7, %o0, %o0, %tgd_add (foo)
2870 while Sun as/ld does not. */
2871 if (TARGET_GNU_TLS || !TARGET_TLS)
2874 pat = PATTERN (trial);
2875 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
2878 unspec = XEXP (SET_DEST (pat), 1);
2879 if (GET_CODE (unspec) != UNSPEC
2880 || (XINT (unspec, 1) != UNSPEC_TLSGD
2881 && XINT (unspec, 1) != UNSPEC_TLSLDM))
2887 /* Return nonzero if TRIAL can go into the sibling call
2891 eligible_for_sibcall_delay (rtx trial)
2895 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2898 if (get_attr_length (trial) != 1)
2901 pat = PATTERN (trial);
2903 if (current_function_uses_only_leaf_regs)
2905 /* If the tail call is done using the call instruction,
2906 we have to restore %o7 in the delay slot. */
2907 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2910 /* %g1 is used to build the function address */
2911 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2917 /* Otherwise, only operations which can be done in tandem with
2918 a `restore' insn can go into the delay slot. */
2919 if (GET_CODE (SET_DEST (pat)) != REG
2920 || REGNO (SET_DEST (pat)) < 24
2921 || REGNO (SET_DEST (pat)) >= 32)
2924 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2926 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2929 src = SET_SRC (pat);
2931 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2932 && arith_operand (src, GET_MODE (src)))
2935 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2937 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2940 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2941 && arith_double_operand (src, GET_MODE (src)))
2942 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2944 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2945 && register_operand (src, SFmode))
2948 else if (GET_CODE (src) == PLUS
2949 && arith_operand (XEXP (src, 0), SImode)
2950 && arith_operand (XEXP (src, 1), SImode)
2951 && (register_operand (XEXP (src, 0), SImode)
2952 || register_operand (XEXP (src, 1), SImode)))
2955 else if (GET_CODE (src) == PLUS
2956 && arith_double_operand (XEXP (src, 0), DImode)
2957 && arith_double_operand (XEXP (src, 1), DImode)
2958 && (register_operand (XEXP (src, 0), DImode)
2959 || register_operand (XEXP (src, 1), DImode)))
2962 else if (GET_CODE (src) == LO_SUM
2963 && ! TARGET_CM_MEDMID
2964 && ((register_operand (XEXP (src, 0), SImode)
2965 && immediate_operand (XEXP (src, 1), SImode))
2967 && register_operand (XEXP (src, 0), DImode)
2968 && immediate_operand (XEXP (src, 1), DImode))))
2971 else if (GET_CODE (src) == ASHIFT
2972 && (register_operand (XEXP (src, 0), SImode)
2973 || register_operand (XEXP (src, 0), DImode))
2974 && XEXP (src, 1) == const1_rtx)
2981 check_return_regs (rtx x)
2983 switch (GET_CODE (x))
2986 return IN_OR_GLOBAL_P (x);
3001 if (check_return_regs (XEXP (x, 1)) == 0)
3006 return check_return_regs (XEXP (x, 0));
3015 short_branch (int uid1, int uid2)
3017 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3019 /* Leave a few words of "slop". */
3020 if (delta >= -1023 && delta <= 1022)
3026 /* Return nonzero if REG is not used after INSN.
3027 We assume REG is a reload reg, and therefore does
3028 not live past labels or calls or jumps. */
3030 reg_unused_after (rtx reg, rtx insn)
3032 enum rtx_code code, prev_code = UNKNOWN;
3034 while ((insn = NEXT_INSN (insn)))
3036 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3039 code = GET_CODE (insn);
3040 if (GET_CODE (insn) == CODE_LABEL)
3043 if (GET_RTX_CLASS (code) == 'i')
3045 rtx set = single_set (insn);
3046 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3049 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3051 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3059 /* Determine if it's legal to put X into the constant pool. This
3060 is not possible if X contains the address of a symbol that is
3061 not constant (TLS) or not known at final link time (PIC). */
3064 sparc_cannot_force_const_mem (rtx x)
3066 switch (GET_CODE (x))
3070 /* Accept all non-symbolic constants. */
3074 /* Labels are OK iff we are non-PIC. */
3075 return flag_pic != 0;
3078 /* 'Naked' TLS symbol references are never OK,
3079 non-TLS symbols are OK iff we are non-PIC. */
3080 if (SYMBOL_REF_TLS_MODEL (x))
3083 return flag_pic != 0;
3086 return sparc_cannot_force_const_mem (XEXP (x, 0));
3089 return sparc_cannot_force_const_mem (XEXP (x, 0))
3090 || sparc_cannot_force_const_mem (XEXP (x, 1));
3098 /* The table we use to reference PIC data. */
3099 static GTY(()) rtx global_offset_table;
3101 /* The function we use to get at it. */
3102 static GTY(()) rtx get_pc_symbol;
3103 static char get_pc_symbol_name[256];
3105 /* Ensure that we are not using patterns that are not OK with PIC. */
3113 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3114 || (GET_CODE (recog_data.operand[i]) == CONST
3115 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3116 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3117 == global_offset_table)
3118 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3127 /* Return true if X is an address which needs a temporary register when
3128 reloaded while generating PIC code. */
3131 pic_address_needs_scratch (rtx x)
3133 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3134 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3135 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3136 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3137 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3143 /* Determine if a given RTX is a valid constant. We already know this
3144 satisfies CONSTANT_P. */
3147 legitimate_constant_p (rtx x)
3151 switch (GET_CODE (x))
3154 /* TLS symbols are not constant. */
3155 if (SYMBOL_REF_TLS_MODEL (x))
3160 inner = XEXP (x, 0);
3162 /* Offsets of TLS symbols are never valid.
3163 Discourage CSE from creating them. */
3164 if (GET_CODE (inner) == PLUS
3165 && tls_symbolic_operand (XEXP (inner, 0)))
3170 if (GET_MODE (x) == VOIDmode)
3173 /* Floating point constants are generally not ok.
3174 The only exception is 0.0 in VIS. */
3176 && (GET_MODE (x) == SFmode
3177 || GET_MODE (x) == DFmode
3178 || GET_MODE (x) == TFmode)
3179 && fp_zero_operand (x, GET_MODE (x)))
3191 /* Determine if a given RTX is a valid constant address. */
3194 constant_address_p (rtx x)
3196 switch (GET_CODE (x))
3204 if (flag_pic && pic_address_needs_scratch (x))
3206 return legitimate_constant_p (x);
3209 return !flag_pic && legitimate_constant_p (x);
3216 /* Nonzero if the constant value X is a legitimate general operand
3217 when generating PIC code. It is given that flag_pic is on and
3218 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3221 legitimate_pic_operand_p (rtx x)
3223 if (pic_address_needs_scratch (x))
3225 if (tls_symbolic_operand (x)
3226 || (GET_CODE (x) == CONST
3227 && GET_CODE (XEXP (x, 0)) == PLUS
3228 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3233 /* Return nonzero if ADDR is a valid memory address.
3234 STRICT specifies whether strict register checking applies. */
3237 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3239 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3241 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3243 else if (GET_CODE (addr) == PLUS)
3245 rs1 = XEXP (addr, 0);
3246 rs2 = XEXP (addr, 1);
3248 /* Canonicalize. REG comes first, if there are no regs,
3249 LO_SUM comes first. */
3251 && GET_CODE (rs1) != SUBREG
3253 || GET_CODE (rs2) == SUBREG
3254 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3256 rs1 = XEXP (addr, 1);
3257 rs2 = XEXP (addr, 0);
3261 && rs1 == pic_offset_table_rtx
3263 && GET_CODE (rs2) != SUBREG
3264 && GET_CODE (rs2) != LO_SUM
3265 && GET_CODE (rs2) != MEM
3266 && !tls_symbolic_operand (rs2)
3267 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3268 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3270 || GET_CODE (rs1) == SUBREG)
3271 && RTX_OK_FOR_OFFSET_P (rs2)))
3276 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3277 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3279 /* We prohibit REG + REG for TFmode when there are no instructions
3280 which accept REG+REG instructions. We do this because REG+REG
3281 is not an offsetable address. If we get the situation in reload
3282 where source and destination of a movtf pattern are both MEMs with
3283 REG+REG address, then only one of them gets converted to an
3284 offsetable address. */
3286 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3287 && TARGET_HARD_QUAD))
3290 /* We prohibit REG + REG on ARCH32 if not optimizing for
3291 DFmode/DImode because then mem_min_alignment is likely to be zero
3292 after reload and the forced split would lack a matching splitter
3294 if (TARGET_ARCH32 && !optimize
3295 && (mode == DFmode || mode == DImode))
3298 else if (USE_AS_OFFSETABLE_LO10
3299 && GET_CODE (rs1) == LO_SUM
3301 && ! TARGET_CM_MEDMID
3302 && RTX_OK_FOR_OLO10_P (rs2))
3306 imm1 = XEXP (rs1, 1);
3307 rs1 = XEXP (rs1, 0);
3308 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3312 else if (GET_CODE (addr) == LO_SUM)
3314 rs1 = XEXP (addr, 0);
3315 imm1 = XEXP (addr, 1);
3317 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3320 /* We can't allow TFmode, because an offset greater than or equal to the
3321 alignment (8) may cause the LO_SUM to overflow if !v9. */
3322 if (mode == TFmode && !TARGET_V9)
3325 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3330 if (GET_CODE (rs1) == SUBREG)
3331 rs1 = SUBREG_REG (rs1);
3337 if (GET_CODE (rs2) == SUBREG)
3338 rs2 = SUBREG_REG (rs2);
3345 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3346 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3351 if ((REGNO (rs1) >= 32
3352 && REGNO (rs1) != FRAME_POINTER_REGNUM
3353 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3355 && (REGNO (rs2) >= 32
3356 && REGNO (rs2) != FRAME_POINTER_REGNUM
3357 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3363 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3365 static GTY(()) rtx sparc_tls_symbol;
3367 sparc_tls_get_addr (void)
3369 if (!sparc_tls_symbol)
3370 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3372 return sparc_tls_symbol;
3376 sparc_tls_got (void)
3381 current_function_uses_pic_offset_table = 1;
3382 return pic_offset_table_rtx;
3385 if (!global_offset_table)
3386 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3387 temp = gen_reg_rtx (Pmode);
3388 emit_move_insn (temp, global_offset_table);
3393 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3394 this (thread-local) address. */
3397 legitimize_tls_address (rtx addr)
3399 rtx temp1, temp2, temp3, ret, o0, got, insn;
3404 if (GET_CODE (addr) == SYMBOL_REF)
3405 switch (SYMBOL_REF_TLS_MODEL (addr))
3407 case TLS_MODEL_GLOBAL_DYNAMIC:
3409 temp1 = gen_reg_rtx (SImode);
3410 temp2 = gen_reg_rtx (SImode);
3411 ret = gen_reg_rtx (Pmode);
3412 o0 = gen_rtx_REG (Pmode, 8);
3413 got = sparc_tls_got ();
3414 emit_insn (gen_tgd_hi22 (temp1, addr));
3415 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3418 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3419 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3424 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3425 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3428 CALL_INSN_FUNCTION_USAGE (insn)
3429 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3430 CALL_INSN_FUNCTION_USAGE (insn));
3431 insn = get_insns ();
3433 emit_libcall_block (insn, ret, o0, addr);
3436 case TLS_MODEL_LOCAL_DYNAMIC:
3438 temp1 = gen_reg_rtx (SImode);
3439 temp2 = gen_reg_rtx (SImode);
3440 temp3 = gen_reg_rtx (Pmode);
3441 ret = gen_reg_rtx (Pmode);
3442 o0 = gen_rtx_REG (Pmode, 8);
3443 got = sparc_tls_got ();
3444 emit_insn (gen_tldm_hi22 (temp1));
3445 emit_insn (gen_tldm_lo10 (temp2, temp1));
3448 emit_insn (gen_tldm_add32 (o0, got, temp2));
3449 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3454 emit_insn (gen_tldm_add64 (o0, got, temp2));
3455 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3458 CALL_INSN_FUNCTION_USAGE (insn)
3459 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3460 CALL_INSN_FUNCTION_USAGE (insn));
3461 insn = get_insns ();
3463 emit_libcall_block (insn, temp3, o0,
3464 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3465 UNSPEC_TLSLD_BASE));
3466 temp1 = gen_reg_rtx (SImode);
3467 temp2 = gen_reg_rtx (SImode);
3468 emit_insn (gen_tldo_hix22 (temp1, addr));
3469 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3471 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3473 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3476 case TLS_MODEL_INITIAL_EXEC:
3477 temp1 = gen_reg_rtx (SImode);
3478 temp2 = gen_reg_rtx (SImode);
3479 temp3 = gen_reg_rtx (Pmode);
3480 got = sparc_tls_got ();
3481 emit_insn (gen_tie_hi22 (temp1, addr));
3482 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3484 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3486 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3489 ret = gen_reg_rtx (Pmode);
3491 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3494 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3498 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3501 case TLS_MODEL_LOCAL_EXEC:
3502 temp1 = gen_reg_rtx (Pmode);
3503 temp2 = gen_reg_rtx (Pmode);
3506 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3507 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3511 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3512 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3514 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3522 abort (); /* for now ... */
3528 /* Legitimize PIC addresses. If the address is already position-independent,
3529 we return ORIG. Newly generated position-independent addresses go into a
3530 reg. This is REG if nonzero, otherwise we allocate register(s) as
3534 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3537 if (GET_CODE (orig) == SYMBOL_REF)
3539 rtx pic_ref, address;
3544 if (reload_in_progress || reload_completed)
3547 reg = gen_reg_rtx (Pmode);
3552 /* If not during reload, allocate another temp reg here for loading
3553 in the address, so that these instructions can be optimized
3555 rtx temp_reg = ((reload_in_progress || reload_completed)
3556 ? reg : gen_reg_rtx (Pmode));
3558 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3559 won't get confused into thinking that these two instructions
3560 are loading in the true address of the symbol. If in the
3561 future a PIC rtx exists, that should be used instead. */
3562 if (Pmode == SImode)
3564 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3565 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3569 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3570 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3577 pic_ref = gen_rtx_MEM (Pmode,
3578 gen_rtx_PLUS (Pmode,
3579 pic_offset_table_rtx, address));
3580 current_function_uses_pic_offset_table = 1;
3581 RTX_UNCHANGING_P (pic_ref) = 1;
3582 insn = emit_move_insn (reg, pic_ref);
3583 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3585 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3589 else if (GET_CODE (orig) == CONST)
3593 if (GET_CODE (XEXP (orig, 0)) == PLUS
3594 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3599 if (reload_in_progress || reload_completed)
3602 reg = gen_reg_rtx (Pmode);
3605 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3607 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3608 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3609 base == reg ? 0 : reg);
3614 if (GET_CODE (offset) == CONST_INT)
3616 if (SMALL_INT (offset))
3617 return plus_constant (base, INTVAL (offset));
3618 else if (! reload_in_progress && ! reload_completed)
3619 offset = force_reg (Pmode, offset);
3621 /* If we reach here, then something is seriously wrong. */
3624 return gen_rtx_PLUS (Pmode, base, offset);
3626 else if (GET_CODE (orig) == LABEL_REF)
3627 /* ??? Why do we do this? */
3628 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3629 the register is live instead, in case it is eliminated. */
3630 current_function_uses_pic_offset_table = 1;
3635 /* Try machine-dependent ways of modifying an illegitimate address X
3636 to be legitimate. If we find one, return the new, valid address.
3638 OLDX is the address as it was before break_out_memory_refs was called.
3639 In some cases it is useful to look at this to decide what needs to be done.
3641 MODE is the mode of the operand pointed to by X. */
3644 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3648 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3649 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3650 force_operand (XEXP (x, 0), NULL_RTX));
3651 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3652 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3653 force_operand (XEXP (x, 1), NULL_RTX));
3654 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3655 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3657 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3658 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3659 force_operand (XEXP (x, 1), NULL_RTX));
3661 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3664 if (tls_symbolic_operand (x))
3665 x = legitimize_tls_address (x);
3667 x = legitimize_pic_address (x, mode, 0);
3668 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3669 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3670 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3671 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3672 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3673 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3674 else if (GET_CODE (x) == SYMBOL_REF
3675 || GET_CODE (x) == CONST
3676 || GET_CODE (x) == LABEL_REF)
3677 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3681 /* Emit special PIC prologues. */
3684 load_pic_register (void)
3686 /* Labels to get the PC in the prologue of this function. */
3687 int orig_flag_pic = flag_pic;
3692 /* If we haven't emitted the special get_pc helper function, do so now. */
3693 if (get_pc_symbol_name[0] == 0)
3697 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3700 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3702 ASM_OUTPUT_ALIGN (asm_out_file, align);
3703 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
3704 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3707 /* Initialize every time through, since we can't easily
3708 know this to be permanent. */
3709 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3710 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3713 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3716 flag_pic = orig_flag_pic;
3718 /* Need to emit this whether or not we obey regdecls,
3719 since setjmp/longjmp can cause life info to screw up.
3720 ??? In the case where we don't obey regdecls, this is not sufficient
3721 since we may not fall out the bottom. */
3722 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3725 /* Return 1 if RTX is a MEM which is known to be aligned to at
3726 least a DESIRED byte boundary. */
3729 mem_min_alignment (rtx mem, int desired)
3731 rtx addr, base, offset;
3733 /* If it's not a MEM we can't accept it. */
3734 if (GET_CODE (mem) != MEM)
3737 addr = XEXP (mem, 0);
3738 base = offset = NULL_RTX;
3739 if (GET_CODE (addr) == PLUS)
3741 if (GET_CODE (XEXP (addr, 0)) == REG)
3743 base = XEXP (addr, 0);
3745 /* What we are saying here is that if the base
3746 REG is aligned properly, the compiler will make
3747 sure any REG based index upon it will be so
3749 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3750 offset = XEXP (addr, 1);
3752 offset = const0_rtx;
3755 else if (GET_CODE (addr) == REG)
3758 offset = const0_rtx;
3761 if (base != NULL_RTX)
3763 int regno = REGNO (base);
3765 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3767 /* Check if the compiler has recorded some information
3768 about the alignment of the base REG. If reload has
3769 completed, we already matched with proper alignments.
3770 If not running global_alloc, reload might give us
3771 unaligned pointer to local stack though. */
3773 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3774 || (optimize && reload_completed))
3775 && (INTVAL (offset) & (desired - 1)) == 0)
3780 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3784 else if (! TARGET_UNALIGNED_DOUBLES
3785 || CONSTANT_P (addr)
3786 || GET_CODE (addr) == LO_SUM)
3788 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3789 is true, in which case we can only assume that an access is aligned if
3790 it is to a constant address, or the address involves a LO_SUM. */
3794 /* An obviously unaligned address. */
3799 /* Vectors to keep interesting information about registers where it can easily
3800 be got. We used to use the actual mode value as the bit number, but there
3801 are more than 32 modes now. Instead we use two tables: one indexed by
3802 hard register number, and one indexed by mode. */
3804 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3805 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3806 mapped into one sparc_mode_class mode. */
3808 enum sparc_mode_class {
3809 S_MODE, D_MODE, T_MODE, O_MODE,
3810 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3814 /* Modes for single-word and smaller quantities. */
3815 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3817 /* Modes for double-word and smaller quantities. */
3818 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3820 /* Modes for quad-word and smaller quantities. */
3821 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3823 /* Modes for 8-word and smaller quantities. */
3824 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3826 /* Modes for single-float quantities. We must allow any single word or
3827 smaller quantity. This is because the fix/float conversion instructions
3828 take integer inputs/outputs from the float registers. */
3829 #define SF_MODES (S_MODES)
3831 /* Modes for double-float and smaller quantities. */
3832 #define DF_MODES (S_MODES | D_MODES)
3834 /* Modes for double-float only quantities. */
3835 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3837 /* Modes for quad-float only quantities. */
3838 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3840 /* Modes for quad-float and smaller quantities. */
3841 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3843 /* Modes for quad-float and double-float quantities. */
3844 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3846 /* Modes for quad-float pair only quantities. */
3847 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3849 /* Modes for quad-float pairs and smaller quantities. */
3850 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3852 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3854 /* Modes for condition codes. */
3855 #define CC_MODES (1 << (int) CC_MODE)
3856 #define CCFP_MODES (1 << (int) CCFP_MODE)
3858 /* Value is 1 if register/mode pair is acceptable on sparc.
3859 The funny mixture of D and T modes is because integer operations
3860 do not specially operate on tetra quantities, so non-quad-aligned
3861 registers can hold quadword quantities (except %o4 and %i4 because
3862 they cross fixed registers). */
3864 /* This points to either the 32 bit or the 64 bit version. */
3865 const int *hard_regno_mode_classes;
3867 static const int hard_32bit_mode_classes[] = {
3868 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3869 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3870 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3871 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3873 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3874 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3875 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3876 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3878 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3879 and none can hold SFmode/SImode values. */
3880 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3881 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3882 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3883 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3886 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3892 static const int hard_64bit_mode_classes[] = {
3893 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3894 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3895 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3896 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3898 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3899 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3900 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3901 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3903 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3904 and none can hold SFmode/SImode values. */
3905 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3906 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3907 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3908 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3911 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3917 int sparc_mode_class [NUM_MACHINE_MODES];
3919 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3922 sparc_init_modes (void)
3926 for (i = 0; i < NUM_MACHINE_MODES; i++)
3928 switch (GET_MODE_CLASS (i))
3931 case MODE_PARTIAL_INT:
3932 case MODE_COMPLEX_INT:
3933 if (GET_MODE_SIZE (i) <= 4)
3934 sparc_mode_class[i] = 1 << (int) S_MODE;
3935 else if (GET_MODE_SIZE (i) == 8)
3936 sparc_mode_class[i] = 1 << (int) D_MODE;
3937 else if (GET_MODE_SIZE (i) == 16)
3938 sparc_mode_class[i] = 1 << (int) T_MODE;
3939 else if (GET_MODE_SIZE (i) == 32)
3940 sparc_mode_class[i] = 1 << (int) O_MODE;
3942 sparc_mode_class[i] = 0;
3945 case MODE_COMPLEX_FLOAT:
3946 if (GET_MODE_SIZE (i) <= 4)
3947 sparc_mode_class[i] = 1 << (int) SF_MODE;
3948 else if (GET_MODE_SIZE (i) == 8)
3949 sparc_mode_class[i] = 1 << (int) DF_MODE;
3950 else if (GET_MODE_SIZE (i) == 16)
3951 sparc_mode_class[i] = 1 << (int) TF_MODE;
3952 else if (GET_MODE_SIZE (i) == 32)
3953 sparc_mode_class[i] = 1 << (int) OF_MODE;
3955 sparc_mode_class[i] = 0;
3959 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3960 we must explicitly check for them here. */
3961 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3962 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3963 else if (i == (int) CCmode || i == (int) CC_NOOVmode
3964 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3965 sparc_mode_class[i] = 1 << (int) CC_MODE;
3967 sparc_mode_class[i] = 0;
3973 hard_regno_mode_classes = hard_64bit_mode_classes;
3975 hard_regno_mode_classes = hard_32bit_mode_classes;
3977 /* Initialize the array used by REGNO_REG_CLASS. */
3978 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3980 if (i < 16 && TARGET_V8PLUS)
3981 sparc_regno_reg_class[i] = I64_REGS;
3982 else if (i < 32 || i == FRAME_POINTER_REGNUM)
3983 sparc_regno_reg_class[i] = GENERAL_REGS;
3985 sparc_regno_reg_class[i] = FP_REGS;
3987 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3989 sparc_regno_reg_class[i] = FPCC_REGS;
3991 sparc_regno_reg_class[i] = NO_REGS;
3995 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3996 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3997 v9 int regs as it simplifies the code. */
4000 save_regs (FILE *file, int low, int high, const char *base,
4001 int offset, int n_regs, int real_offset)
4005 if (TARGET_ARCH64 && high <= 32)
4007 for (i = low; i < high; i++)
4009 if (regs_ever_live[i] && ! call_used_regs[i])
4011 fprintf (file, "\tstx\t%s, [%s+%d]\n",
4012 reg_names[i], base, offset + 4 * n_regs);
4013 if (dwarf2out_do_frame ())
4014 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4021 for (i = low; i < high; i += 2)
4023 if (regs_ever_live[i] && ! call_used_regs[i])
4025 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4027 fprintf (file, "\tstd\t%s, [%s+%d]\n",
4028 reg_names[i], base, offset + 4 * n_regs);
4029 if (dwarf2out_do_frame ())
4031 char *l = dwarf2out_cfi_label ();
4032 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
4033 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
4039 fprintf (file, "\tst\t%s, [%s+%d]\n",
4040 reg_names[i], base, offset + 4 * n_regs);
4041 if (dwarf2out_do_frame ())
4042 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4048 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4050 fprintf (file, "\tst\t%s, [%s+%d]\n",
4051 reg_names[i+1], base, offset + 4 * n_regs + 4);
4052 if (dwarf2out_do_frame ())
4053 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
4062 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
4064 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4065 v9 int regs as it simplifies the code. */
4068 restore_regs (FILE *file, int low, int high, const char *base,
4069 int offset, int n_regs)
4073 if (TARGET_ARCH64 && high <= 32)
4075 for (i = low; i < high; i++)
4077 if (regs_ever_live[i] && ! call_used_regs[i])
4078 fprintf (file, "\tldx\t[%s+%d], %s\n",
4079 base, offset + 4 * n_regs, reg_names[i]),
4085 for (i = low; i < high; i += 2)
4087 if (regs_ever_live[i] && ! call_used_regs[i])
4088 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4089 fprintf (file, "\tldd\t[%s+%d], %s\n",
4090 base, offset + 4 * n_regs, reg_names[i]),
4093 fprintf (file, "\tld\t[%s+%d], %s\n",
4094 base, offset + 4 * n_regs, reg_names[i]),
4096 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4097 fprintf (file, "\tld\t[%s+%d], %s\n",
4098 base, offset + 4 * n_regs + 4, reg_names[i+1]),
4105 /* Compute the frame size required by the function. This function is called
4106 during the reload pass and also by output_function_prologue(). */
4109 compute_frame_size (int size, int leaf_function)
4112 int outgoing_args_size = (current_function_outgoing_args_size
4113 + REG_PARM_STACK_SPACE (current_function_decl));
4115 /* N_REGS is the number of 4-byte regs saved thus far. This applies
4116 even to v9 int regs to be consistent with save_regs/restore_regs. */
4120 for (i = 0; i < 8; i++)
4121 if (regs_ever_live[i] && ! call_used_regs[i])
4126 for (i = 0; i < 8; i += 2)
4127 if ((regs_ever_live[i] && ! call_used_regs[i])
4128 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4132 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4133 if ((regs_ever_live[i] && ! call_used_regs[i])
4134 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4137 /* Set up values for use in `function_epilogue'. */
4138 num_gfregs = n_regs;
4140 if (leaf_function && n_regs == 0
4141 && size == 0 && current_function_outgoing_args_size == 0)
4143 actual_fsize = apparent_fsize = 0;
4147 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4148 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4149 apparent_fsize += n_regs * 4;
4150 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4153 /* Make sure nothing can clobber our register windows.
4154 If a SAVE must be done, or there is a stack-local variable,
4155 the register window area must be allocated.
4156 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4157 if (leaf_function == 0 || size > 0)
4158 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4160 return SPARC_STACK_ALIGN (actual_fsize);
4163 /* Build a (32 bit) big number in a register. */
4164 /* ??? We may be able to use the set macro here too. */
4167 build_big_number (FILE *file, int num, const char *reg)
4169 if (num >= 0 || ! TARGET_ARCH64)
4171 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
4172 if ((num & 0x3ff) != 0)
4173 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
4175 else /* num < 0 && TARGET_ARCH64 */
4177 /* Sethi does not sign extend, so we must use a little trickery
4178 to use it for negative numbers. Invert the constant before
4179 loading it in, then use xor immediate to invert the loaded bits
4180 (along with the upper 32 bits) to the desired constant. This
4181 works because the sethi and immediate fields overlap. */
4184 int low = -0x400 + (asize & 0x3FF);
4186 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
4187 inv, reg, reg, low, reg);
4191 /* Output any necessary .register pseudo-ops. */
4193 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4195 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4201 /* Check if %g[2367] were used without
4202 .register being printed for them already. */
4203 for (i = 2; i < 8; i++)
4205 if (regs_ever_live [i]
4206 && ! sparc_hard_reg_printed [i])
4208 sparc_hard_reg_printed [i] = 1;
4209 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4216 /* This function generates the assembly code for function entry.
4217 FILE is a stdio stream to output the code to.
4218 SIZE is an int: how many units of temporary storage to allocate.
4219 Refer to the array `regs_ever_live' to determine which registers
4220 to save; `regs_ever_live[I]' is nonzero if register number I
4221 is ever used in the function. This macro is responsible for
4222 knowing which registers should not be saved even if used. */
4224 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
4225 of memory. If any fpu reg is used in the function, we allocate
4226 such a block here, at the bottom of the frame, just in case it's needed.
4228 If this function is a leaf procedure, then we may choose not
4229 to do a "save" insn. The decision about whether or not
4230 to do this is made in regclass.c. */
4233 sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size)
4236 sparc_flat_function_prologue (file, size);
4238 sparc_nonflat_function_prologue (file, size,
4239 current_function_uses_only_leaf_regs);
4242 /* Output code for the function prologue. */
4245 sparc_nonflat_function_prologue (FILE *file, HOST_WIDE_INT size,
4248 sparc_output_scratch_registers (file);
4250 /* Need to use actual_fsize, since we are also allocating
4251 space for our callee (and our own register save area). */
4252 actual_fsize = compute_frame_size (size, leaf_function);
4256 frame_base_name = "%sp";
4257 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4261 frame_base_name = "%fp";
4262 frame_base_offset = SPARC_STACK_BIAS;
4265 /* This is only for the human reader. */
4266 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
4268 if (actual_fsize == 0)
4270 else if (! leaf_function)
4272 if (actual_fsize <= 4096)
4273 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
4274 else if (actual_fsize <= 8192)
4276 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
4277 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
4281 build_big_number (file, -actual_fsize, "%g1");
4282 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
4285 else /* leaf function */
4287 if (actual_fsize <= 4096)
4288 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
4289 else if (actual_fsize <= 8192)
4291 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
4292 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
4296 build_big_number (file, -actual_fsize, "%g1");
4297 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
4301 if (dwarf2out_do_frame () && actual_fsize)
4303 char *label = dwarf2out_cfi_label ();
4305 /* The canonical frame address refers to the top of the frame. */
4306 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
4307 : HARD_FRAME_POINTER_REGNUM),
4310 if (! leaf_function)
4312 /* Note the register window save. This tells the unwinder that
4313 it needs to restore the window registers from the previous
4314 frame's window save area at 0(cfa). */
4315 dwarf2out_window_save (label);
4317 /* The return address (-8) is now in %i7. */
4318 dwarf2out_return_reg (label, 31);
4322 /* If doing anything with PIC, do it now. */
4324 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
4326 /* Call saved registers are saved just above the outgoing argument area. */
4329 int offset, real_offset, n_regs;
4332 real_offset = -apparent_fsize;
4333 offset = -apparent_fsize + frame_base_offset;
4334 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4336 /* ??? This might be optimized a little as %g1 might already have a
4337 value close enough that a single add insn will do. */
4338 /* ??? Although, all of this is probably only a temporary fix
4339 because if %g1 can hold a function result, then
4340 output_function_epilogue will lose (the result will get
4342 build_big_number (file, offset, "%g1");
4343 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4349 base = frame_base_name;
4352 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
4353 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
4358 /* Output code to restore any call saved registers. */
4361 output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED)
4366 offset = -apparent_fsize + frame_base_offset;
4367 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4369 build_big_number (file, offset, "%g1");
4370 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4376 base = frame_base_name;
4379 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4380 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4383 /* This function generates the assembly code for function exit,
4384 on machines that need it.
4386 The function epilogue should not depend on the current stack pointer!
4387 It should use the frame pointer only. This is mandatory because
4388 of alloca; we also take advantage of it to omit stack adjustments
4389 before returning. */
4392 sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size)
4395 sparc_flat_function_epilogue (file, size);
4397 sparc_nonflat_function_epilogue (file, size,
4398 current_function_uses_only_leaf_regs);
4401 /* Output code for the function epilogue. */
4404 sparc_nonflat_function_epilogue (FILE *file,
4405 HOST_WIDE_INT size ATTRIBUTE_UNUSED,
4410 if (current_function_epilogue_delay_list == 0)
4412 /* If code does not drop into the epilogue, we need
4413 do nothing except output pending case vectors.
4415 We have to still output a dummy nop for the sake of
4416 sane backtraces. Otherwise, if the last two instructions
4417 of a function were call foo; dslot; this can make the return
4418 PC of foo (ie. address of call instruction plus 8) point to
4419 the first instruction in the next function. */
4420 rtx insn, last_real_insn;
4422 insn = get_last_insn ();
4424 last_real_insn = prev_real_insn (insn);
4426 && GET_CODE (last_real_insn) == INSN
4427 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4428 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4430 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4431 fputs("\tnop\n", file);
4433 if (GET_CODE (insn) == NOTE)
4434 insn = prev_nonnote_insn (insn);
4435 if (insn && GET_CODE (insn) == BARRIER)
4436 goto output_vectors;
4440 output_restore_regs (file, leaf_function);
4442 /* Work out how to skip the caller's unimp instruction if required. */
4444 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4446 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4448 if (! leaf_function)
4450 if (current_function_calls_eh_return)
4452 if (current_function_epilogue_delay_list)
4454 if (SKIP_CALLERS_UNIMP_P)
4457 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4459 /* If we wound up with things in our delay slot, flush them here. */
4460 else if (current_function_epilogue_delay_list)
4462 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4464 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4466 epilogue_renumber (&delay, 0);
4467 fputs (SKIP_CALLERS_UNIMP_P
4468 ? "\treturn\t%i7+12\n"
4469 : "\treturn\t%i7+8\n", file);
4470 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4477 if (GET_CODE (delay) != SET)
4480 src = SET_SRC (delay);
4481 if (GET_CODE (src) == ASHIFT)
4483 if (XEXP (src, 1) != const1_rtx)
4486 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4490 insn = gen_rtx_PARALLEL (VOIDmode,
4491 gen_rtvec (2, delay,
4492 gen_rtx_RETURN (VOIDmode)));
4493 insn = emit_jump_insn (insn);
4495 sparc_emitting_epilogue = true;
4496 final_scan_insn (insn, file, 1, 0, 1);
4497 sparc_emitting_epilogue = false;
4500 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4501 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4503 fprintf (file, "\t%s\n\trestore\n", ret);
4505 /* All of the following cases are for leaf functions. */
4506 else if (current_function_calls_eh_return)
4508 else if (current_function_epilogue_delay_list)
4510 /* eligible_for_epilogue_delay_slot ensures that if this is a
4511 leaf function, then we will only have insn in the delay slot
4512 if the frame size is zero, thus no adjust for the stack is
4514 if (actual_fsize != 0)
4516 fprintf (file, "\t%s\n", ret);
4517 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4520 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4521 avoid generating confusing assembly language output. */
4522 else if (actual_fsize == 0)
4523 fprintf (file, "\t%s\n\tnop\n", ret);
4524 else if (actual_fsize <= 4096)
4525 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
4526 else if (actual_fsize <= 8192)
4527 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4528 ret, actual_fsize - 4096);
4529 else if ((actual_fsize & 0x3ff) == 0)
4530 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4533 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4534 actual_fsize, actual_fsize, ret);
4537 sparc_output_deferred_case_vectors ();
4540 /* Output a sibling call. */
4543 output_sibcall (rtx insn, rtx call_operand)
4545 int leaf_regs = current_function_uses_only_leaf_regs;
4547 int delay_slot = dbr_sequence_length () > 0;
4551 /* Call to restore global regs might clobber
4552 the delay slot. Instead of checking for this
4553 output the delay slot now. */
4556 rtx delay = NEXT_INSN (insn);
4561 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4562 PATTERN (delay) = gen_blockage ();
4563 INSN_CODE (delay) = -1;
4566 output_restore_regs (asm_out_file, leaf_regs);
4569 operands[0] = call_operand;
4573 #ifdef HAVE_AS_RELAX_OPTION
4574 /* If as and ld are relaxing tail call insns into branch always,
4575 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4576 be optimized. With sethi/jmpl as nor ld has no easy way how to
4577 find out if somebody does not branch between the sethi and jmpl. */
4580 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4584 if ((actual_fsize || ! spare_slot) && delay_slot)
4586 rtx delay = NEXT_INSN (insn);
4591 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4592 PATTERN (delay) = gen_blockage ();
4593 INSN_CODE (delay) = -1;
4598 if (actual_fsize <= 4096)
4599 size = actual_fsize;
4600 else if (actual_fsize <= 8192)
4602 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4603 size = actual_fsize - 4096;
4605 else if ((actual_fsize & 0x3ff) == 0)
4606 fprintf (asm_out_file,
4607 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4611 fprintf (asm_out_file,
4612 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4613 actual_fsize, actual_fsize);
4614 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4619 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4620 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4622 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size);
4623 else if (! delay_slot)
4624 fputs ("\t nop\n", asm_out_file);
4629 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size);
4630 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4631 it into branch if possible. */
4632 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4633 output_asm_insn ("call\t%a0, 0", operands);
4634 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4639 output_asm_insn ("call\t%a0, 0", operands);
4642 rtx delay = NEXT_INSN (insn), pat;
4647 pat = PATTERN (delay);
4648 if (GET_CODE (pat) != SET)
4651 operands[0] = SET_DEST (pat);
4652 pat = SET_SRC (pat);
4653 switch (GET_CODE (pat))
4656 operands[1] = XEXP (pat, 0);
4657 operands[2] = XEXP (pat, 1);
4658 output_asm_insn (" restore %r1, %2, %Y0", operands);
4661 operands[1] = XEXP (pat, 0);
4662 operands[2] = XEXP (pat, 1);
4663 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4666 operands[1] = XEXP (pat, 0);
4667 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4671 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4674 PATTERN (delay) = gen_blockage ();
4675 INSN_CODE (delay) = -1;
4678 fputs ("\t restore\n", asm_out_file);
4682 /* Functions for handling argument passing.
4684 For v8 the first six args are normally in registers and the rest are
4685 pushed. Any arg that starts within the first 6 words is at least
4686 partially passed in a register unless its data type forbids.
4688 For v9, the argument registers are laid out as an array of 16 elements
4689 and arguments are added sequentially. The first 6 int args and up to the
4690 first 16 fp args (depending on size) are passed in regs.
4692 Slot Stack Integral Float Float in structure Double Long Double
4693 ---- ----- -------- ----- ------------------ ------ -----------
4694 15 [SP+248] %f31 %f30,%f31 %d30
4695 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4696 13 [SP+232] %f27 %f26,%f27 %d26
4697 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4698 11 [SP+216] %f23 %f22,%f23 %d22
4699 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4700 9 [SP+200] %f19 %f18,%f19 %d18
4701 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4702 7 [SP+184] %f15 %f14,%f15 %d14
4703 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4704 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4705 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4706 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4707 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4708 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4709 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4711 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4713 Integral arguments are always passed as 64 bit quantities appropriately
4716 Passing of floating point values is handled as follows.
4717 If a prototype is in scope:
4718 If the value is in a named argument (i.e. not a stdarg function or a
4719 value not part of the `...') then the value is passed in the appropriate
4721 If the value is part of the `...' and is passed in one of the first 6
4722 slots then the value is passed in the appropriate int reg.
4723 If the value is part of the `...' and is not passed in one of the first 6
4724 slots then the value is passed in memory.
4725 If a prototype is not in scope:
4726 If the value is one of the first 6 arguments the value is passed in the
4727 appropriate integer reg and the appropriate fp reg.
4728 If the value is not one of the first 6 arguments the value is passed in
4729 the appropriate fp reg and in memory.
4732 /* Maximum number of int regs for args. */
4733 #define SPARC_INT_ARG_MAX 6
4734 /* Maximum number of fp regs for args. */
4735 #define SPARC_FP_ARG_MAX 16
4737 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4739 /* Handle the INIT_CUMULATIVE_ARGS macro.
4740 Initialize a variable CUM of type CUMULATIVE_ARGS
4741 for a call to a function whose data type is FNTYPE.
4742 For a library call, FNTYPE is 0. */
4745 init_cumulative_args (struct sparc_args *cum, tree fntype,
4746 rtx libname ATTRIBUTE_UNUSED,
4747 tree fndecl ATTRIBUTE_UNUSED)
4750 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4751 cum->libcall_p = fntype == 0;
4754 /* Compute the slot number to pass an argument in.
4755 Returns the slot number or -1 if passing on the stack.
4757 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4758 the preceding args and about the function being called.
4759 MODE is the argument's machine mode.
4760 TYPE is the data type of the argument (as a tree).
4761 This is null for libcalls where that information may
4763 NAMED is nonzero if this argument is a named parameter
4764 (otherwise it is an extra parameter matching an ellipsis).
4765 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4766 *PREGNO records the register number to use if scalar type.
4767 *PPADDING records the amount of padding needed in words. */
4770 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
4771 tree type, int named, int incoming_p,
4772 int *pregno, int *ppadding)
4774 int regbase = (incoming_p
4775 ? SPARC_INCOMING_INT_ARG_FIRST
4776 : SPARC_OUTGOING_INT_ARG_FIRST);
4777 int slotno = cum->words;
4782 if (type != 0 && TREE_ADDRESSABLE (type))
4785 && type != 0 && mode == BLKmode
4786 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4792 /* MODE is VOIDmode when generating the actual call.
4796 case QImode : case CQImode :
4797 case HImode : case CHImode :
4798 case SImode : case CSImode :
4799 case DImode : case CDImode :
4800 case TImode : case CTImode :
4801 if (slotno >= SPARC_INT_ARG_MAX)
4803 regno = regbase + slotno;
4806 case SFmode : case SCmode :
4807 case DFmode : case DCmode :
4808 case TFmode : case TCmode :
4811 if (slotno >= SPARC_INT_ARG_MAX)
4813 regno = regbase + slotno;
4817 if ((mode == TFmode || mode == TCmode)
4818 && (slotno & 1) != 0)
4819 slotno++, *ppadding = 1;
4820 if (TARGET_FPU && named)
4822 if (slotno >= SPARC_FP_ARG_MAX)
4824 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4830 if (slotno >= SPARC_INT_ARG_MAX)
4832 regno = regbase + slotno;
4838 /* For sparc64, objects requiring 16 byte alignment get it. */
4841 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
4842 slotno++, *ppadding = 1;
4846 || (type && TREE_CODE (type) == UNION_TYPE))
4848 if (slotno >= SPARC_INT_ARG_MAX)
4850 regno = regbase + slotno;
4855 int intregs_p = 0, fpregs_p = 0;
4856 /* The ABI obviously doesn't specify how packed
4857 structures are passed. These are defined to be passed
4858 in int regs if possible, otherwise memory. */
4861 /* First see what kinds of registers we need. */
4862 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4864 if (TREE_CODE (field) == FIELD_DECL)
4866 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4871 if (DECL_PACKED (field))
4875 if (packed_p || !named)
4876 fpregs_p = 0, intregs_p = 1;
4878 /* If all arg slots are filled, then must pass on stack. */
4879 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4881 /* If there are only int args and all int arg slots are filled,
4882 then must pass on stack. */
4883 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4885 /* Note that even if all int arg slots are filled, fp members may
4886 still be passed in regs if such regs are available.
4887 *PREGNO isn't set because there may be more than one, it's up
4888 to the caller to compute them. */
4901 /* Handle recursive register counting for structure field layout. */
4903 struct function_arg_record_value_parms
4905 rtx ret; /* return expression being built. */
4906 int slotno; /* slot number of the argument. */
4907 int named; /* whether the argument is named. */
4908 int regbase; /* regno of the base register. */
4909 int stack; /* 1 if part of the argument is on the stack. */
4910 int intoffset; /* offset of the pending integer field. */
4911 unsigned int nregs; /* number of words passed in registers. */
4914 static void function_arg_record_value_3
4915 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
4916 static void function_arg_record_value_2
4917 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *);
4918 static void function_arg_record_value_1
4919 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *);
4920 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
4922 /* A subroutine of function_arg_record_value. Traverse the structure
4923 recursively and determine how many registers will be required. */
4926 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
4927 struct function_arg_record_value_parms *parms)
4931 /* The ABI obviously doesn't specify how packed structures are
4932 passed. These are defined to be passed in int regs if possible,
4933 otherwise memory. */
4936 /* We need to compute how many registers are needed so we can
4937 allocate the PARALLEL but before we can do that we need to know
4938 whether there are any packed fields. If there are, int regs are
4939 used regardless of whether there are fp values present. */
4940 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4942 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4949 /* Compute how many registers we need. */
4950 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4952 if (TREE_CODE (field) == FIELD_DECL)
4954 HOST_WIDE_INT bitpos = startbitpos;
4956 if (DECL_SIZE (field) != 0
4957 && host_integerp (bit_position (field), 1))
4958 bitpos += int_bit_position (field);
4960 /* ??? FIXME: else assume zero offset. */
4962 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4963 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
4964 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4965 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4966 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4972 if (parms->intoffset != -1)
4974 int intslots, this_slotno;
4976 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
4978 this_slotno = parms->slotno + parms->intoffset
4981 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
4983 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
4984 /* We need to pass this field on the stack. */
4988 parms->nregs += intslots;
4989 parms->intoffset = -1;
4992 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4993 If it wasn't true we wouldn't be here. */
4995 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5000 if (parms->intoffset == -1)
5001 parms->intoffset = bitpos;
5007 /* A subroutine of function_arg_record_value. Assign the bits of the
5008 structure between parms->intoffset and bitpos to integer registers. */
5011 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5012 struct function_arg_record_value_parms *parms)
5014 enum machine_mode mode;
5016 unsigned int startbit, endbit;
5017 int this_slotno, intslots, intoffset;
5020 if (parms->intoffset == -1)
5023 intoffset = parms->intoffset;
5024 parms->intoffset = -1;
5026 startbit = intoffset & -BITS_PER_WORD;
5027 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5028 intslots = (endbit - startbit) / BITS_PER_WORD;
5029 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5031 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5035 /* If this is the trailing part of a word, only load that much into
5036 the register. Otherwise load the whole register. Note that in
5037 the latter case we may pick up unwanted bits. It's not a problem
5038 at the moment but may wish to revisit. */
5040 if (intoffset % BITS_PER_WORD != 0)
5041 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5046 intoffset /= BITS_PER_UNIT;
5049 regno = parms->regbase + this_slotno;
5050 reg = gen_rtx_REG (mode, regno);
5051 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5052 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5055 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5059 while (intslots > 0);
5062 /* A subroutine of function_arg_record_value. Traverse the structure
5063 recursively and assign bits to floating point registers. Track which
5064 bits in between need integer registers; invoke function_arg_record_value_3
5065 to make that happen. */
5068 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5069 struct function_arg_record_value_parms *parms)
5074 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5076 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5083 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5085 if (TREE_CODE (field) == FIELD_DECL)
5087 HOST_WIDE_INT bitpos = startbitpos;
5089 if (DECL_SIZE (field) != 0
5090 && host_integerp (bit_position (field), 1))
5091 bitpos += int_bit_position (field);
5093 /* ??? FIXME: else assume zero offset. */
5095 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5096 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
5097 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
5098 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
5099 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
5105 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5107 enum machine_mode mode = DECL_MODE (field);
5110 function_arg_record_value_3 (bitpos, parms);
5111 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
5112 + ((mode == SFmode || mode == SCmode)
5113 && (bitpos & 32) != 0);
5116 case SCmode: mode = SFmode; break;
5117 case DCmode: mode = DFmode; break;
5118 case TCmode: mode = TFmode; break;
5121 reg = gen_rtx_REG (mode, regno);
5122 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5123 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5124 GEN_INT (bitpos / BITS_PER_UNIT));
5126 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5128 regno += GET_MODE_SIZE (mode) / 4;
5129 reg = gen_rtx_REG (mode, regno);
5130 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5131 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5132 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5139 if (parms->intoffset == -1)
5140 parms->intoffset = bitpos;
5146 /* Used by function_arg and function_value to implement the complex
5147 conventions of the 64-bit ABI for passing and returning structures.
5148 Return an expression valid as a return value for the two macros
5149 FUNCTION_ARG and FUNCTION_VALUE.
5151 TYPE is the data type of the argument (as a tree).
5152 This is null for libcalls where that information may
5154 MODE is the argument's machine mode.
5155 SLOTNO is the index number of the argument's slot in the parameter array.
5156 NAMED is nonzero if this argument is a named parameter
5157 (otherwise it is an extra parameter matching an ellipsis).
5158 REGBASE is the regno of the base register for the parameter array. */
5161 function_arg_record_value (tree type, enum machine_mode mode,
5162 int slotno, int named, int regbase)
5164 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5165 struct function_arg_record_value_parms parms;
5168 parms.ret = NULL_RTX;
5169 parms.slotno = slotno;
5170 parms.named = named;
5171 parms.regbase = regbase;
5174 /* Compute how many registers we need. */
5176 parms.intoffset = 0;
5177 function_arg_record_value_1 (type, 0, &parms);
5179 if (parms.intoffset != -1)
5181 unsigned int startbit, endbit;
5182 int intslots, this_slotno;
5184 startbit = parms.intoffset & -BITS_PER_WORD;
5185 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5186 intslots = (endbit - startbit) / BITS_PER_WORD;
5187 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5189 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5191 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5192 /* We need to pass this field on the stack. */
5196 parms.nregs += intslots;
5198 nregs = parms.nregs;
5200 /* Allocate the vector and handle some annoying special cases. */
5203 /* ??? Empty structure has no value? Duh? */
5206 /* Though there's nothing really to store, return a word register
5207 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5208 leads to breakage due to the fact that there are zero bytes to
5210 return gen_rtx_REG (mode, regbase);
5214 /* ??? C++ has structures with no fields, and yet a size. Give up
5215 for now and pass everything back in integer registers. */
5216 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5218 if (nregs + slotno > SPARC_INT_ARG_MAX)
5219 nregs = SPARC_INT_ARG_MAX - slotno;
5224 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5226 /* If at least one field must be passed on the stack, generate
5227 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5228 also be passed on the stack. We can't do much better because the
5229 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5230 of structures for which the fields passed exclusively in registers
5231 are not at the beginning of the structure. */
5233 XVECEXP (parms.ret, 0, 0)
5234 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5236 /* Fill in the entries. */
5238 parms.intoffset = 0;
5239 function_arg_record_value_2 (type, 0, &parms);
5240 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5242 if (parms.nregs != nregs)
5248 /* Handle the FUNCTION_ARG macro.
5249 Determine where to put an argument to a function.
5250 Value is zero to push the argument on the stack,
5251 or a hard register in which to store the argument.
5253 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5254 the preceding args and about the function being called.
5255 MODE is the argument's machine mode.
5256 TYPE is the data type of the argument (as a tree).
5257 This is null for libcalls where that information may
5259 NAMED is nonzero if this argument is a named parameter
5260 (otherwise it is an extra parameter matching an ellipsis).
5261 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5264 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5265 tree type, int named, int incoming_p)
5267 int regbase = (incoming_p
5268 ? SPARC_INCOMING_INT_ARG_FIRST
5269 : SPARC_OUTGOING_INT_ARG_FIRST);
5270 int slotno, regno, padding;
5273 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5281 reg = gen_rtx_REG (mode, regno);
5285 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5286 but also have the slot allocated for them.
5287 If no prototype is in scope fp values in register slots get passed
5288 in two places, either fp regs and int regs or fp regs and memory. */
5289 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5290 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5291 && SPARC_FP_REG_P (regno))
5293 reg = gen_rtx_REG (mode, regno);
5294 if (cum->prototype_p || cum->libcall_p)
5296 /* "* 2" because fp reg numbers are recorded in 4 byte
5299 /* ??? This will cause the value to be passed in the fp reg and
5300 in the stack. When a prototype exists we want to pass the
5301 value in the reg but reserve space on the stack. That's an
5302 optimization, and is deferred [for a bit]. */
5303 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5304 return gen_rtx_PARALLEL (mode,
5306 gen_rtx_EXPR_LIST (VOIDmode,
5307 NULL_RTX, const0_rtx),
5308 gen_rtx_EXPR_LIST (VOIDmode,
5312 /* ??? It seems that passing back a register even when past
5313 the area declared by REG_PARM_STACK_SPACE will allocate
5314 space appropriately, and will not copy the data onto the
5315 stack, exactly as we desire.
5317 This is due to locate_and_pad_parm being called in
5318 expand_call whenever reg_parm_stack_space > 0, which
5319 while beneficial to our example here, would seem to be
5320 in error from what had been intended. Ho hum... -- r~ */
5328 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5332 /* On incoming, we don't need to know that the value
5333 is passed in %f0 and %i0, and it confuses other parts
5334 causing needless spillage even on the simplest cases. */
5338 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5339 + (regno - SPARC_FP_ARG_FIRST) / 2);
5341 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5342 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5344 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5348 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5349 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5350 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5354 else if (type && TREE_CODE (type) == RECORD_TYPE)
5356 /* Structures up to 16 bytes in size are passed in arg slots on the
5357 stack and are promoted to registers where possible. */
5359 if (int_size_in_bytes (type) > 16)
5360 abort (); /* shouldn't get here */
5362 return function_arg_record_value (type, mode, slotno, named, regbase);
5364 else if (type && TREE_CODE (type) == UNION_TYPE)
5366 enum machine_mode mode;
5367 int bytes = int_size_in_bytes (type);
5372 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5373 reg = gen_rtx_REG (mode, regno);
5377 /* Scalar or complex int. */
5378 reg = gen_rtx_REG (mode, regno);
5384 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5385 For an arg passed partly in registers and partly in memory,
5386 this is the number of registers used.
5387 For args passed entirely in registers or entirely in memory, zero.
5389 Any arg that starts in the first 6 regs but won't entirely fit in them
5390 needs partial registers on v8. On v9, structures with integer
5391 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5392 values that begin in the last fp reg [where "last fp reg" varies with the
5393 mode] will be split between that reg and memory. */
5396 function_arg_partial_nregs (const struct sparc_args *cum,
5397 enum machine_mode mode, tree type, int named)
5399 int slotno, regno, padding;
5401 /* We pass 0 for incoming_p here, it doesn't matter. */
5402 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5409 if ((slotno + (mode == BLKmode
5410 ? ROUND_ADVANCE (int_size_in_bytes (type))
5411 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5412 > NPARM_REGS (SImode))
5413 return NPARM_REGS (SImode) - slotno;
5418 if (type && AGGREGATE_TYPE_P (type))
5420 int size = int_size_in_bytes (type);
5421 int align = TYPE_ALIGN (type);
5424 slotno += slotno & 1;
5425 if (size > 8 && size <= 16
5426 && slotno == SPARC_INT_ARG_MAX - 1)
5429 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5430 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5431 && ! (TARGET_FPU && named)))
5433 if (GET_MODE_ALIGNMENT (mode) == 128)
5435 slotno += slotno & 1;
5436 if (slotno == SPARC_INT_ARG_MAX - 2)
5441 if (slotno == SPARC_INT_ARG_MAX - 1)
5445 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5447 if (GET_MODE_ALIGNMENT (mode) == 128)
5448 slotno += slotno & 1;
5449 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5457 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5458 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5459 quad-precision floats by invisible reference.
5460 v9: Aggregates greater than 16 bytes are passed by reference.
5461 For Pascal, also pass arrays by reference. */
5464 function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
5465 enum machine_mode mode, tree type,
5466 int named ATTRIBUTE_UNUSED)
5470 return ((type && AGGREGATE_TYPE_P (type))
5471 || mode == TFmode || mode == TCmode);
5475 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5476 /* Consider complex values as aggregates, so care for TCmode. */
5477 || GET_MODE_SIZE (mode) > 16
5479 && AGGREGATE_TYPE_P (type)
5480 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5484 /* Handle the FUNCTION_ARG_ADVANCE macro.
5485 Update the data in CUM to advance over an argument
5486 of mode MODE and data type TYPE.
5487 TYPE is null for libcalls where that information may not be available. */
5490 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5491 tree type, int named)
5493 int slotno, regno, padding;
5495 /* We pass 0 for incoming_p here, it doesn't matter. */
5496 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5498 /* If register required leading padding, add it. */
5500 cum->words += padding;
5504 cum->words += (mode != BLKmode
5505 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5506 : ROUND_ADVANCE (int_size_in_bytes (type)));
5510 if (type && AGGREGATE_TYPE_P (type))
5512 int size = int_size_in_bytes (type);
5516 else if (size <= 16)
5518 else /* passed by reference */
5521 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
5525 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5527 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
5531 cum->words += (mode != BLKmode
5532 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5533 : ROUND_ADVANCE (int_size_in_bytes (type)));
5538 /* Handle the FUNCTION_ARG_PADDING macro.
5539 For the 64 bit ABI structs are always stored left shifted in their
5543 function_arg_padding (enum machine_mode mode, tree type)
5545 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5548 /* Fall back to the default. */
5549 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5552 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5553 For v9, function return values are subject to the same rules as arguments,
5554 except that up to 32-bytes may be returned in registers. */
5557 function_value (tree type, enum machine_mode mode, int incoming_p)
5560 int regbase = (incoming_p
5561 ? SPARC_OUTGOING_INT_ARG_FIRST
5562 : SPARC_INCOMING_INT_ARG_FIRST);
5564 if (TARGET_ARCH64 && type)
5566 if (TREE_CODE (type) == RECORD_TYPE)
5568 /* Structures up to 32 bytes in size are passed in registers,
5569 promoted to fp registers where possible. */
5571 if (int_size_in_bytes (type) > 32)
5572 abort (); /* shouldn't get here */
5574 return function_arg_record_value (type, mode, 0, 1, regbase);
5576 else if (AGGREGATE_TYPE_P (type))
5578 /* All other aggregate types are passed in an integer register
5579 in a mode corresponding to the size of the type. */
5580 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5585 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5590 && GET_MODE_CLASS (mode) == MODE_INT
5591 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5592 && type && ! AGGREGATE_TYPE_P (type))
5596 regno = BASE_RETURN_VALUE_REG (mode);
5598 regno = BASE_OUTGOING_VALUE_REG (mode);
5600 return gen_rtx_REG (mode, regno);
5603 /* Do what is necessary for `va_start'. We look at the current function
5604 to determine if stdarg or varargs is used and return the address of
5605 the first unnamed parameter. */
5608 sparc_builtin_saveregs (void)
5610 int first_reg = current_function_args_info.words;
5614 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5615 emit_move_insn (gen_rtx_MEM (word_mode,
5616 gen_rtx_PLUS (Pmode,
5618 GEN_INT (FIRST_PARM_OFFSET (0)
5621 gen_rtx_REG (word_mode,
5622 BASE_INCOMING_ARG_REG (word_mode) + regno));
5624 address = gen_rtx_PLUS (Pmode,
5626 GEN_INT (FIRST_PARM_OFFSET (0)
5627 + UNITS_PER_WORD * first_reg));
5632 /* Implement `va_start' for varargs and stdarg. */
5635 sparc_va_start (tree valist, rtx nextarg)
5637 nextarg = expand_builtin_saveregs ();
5638 std_expand_builtin_va_start (valist, nextarg);
5641 /* Implement `va_arg'. */
5644 sparc_va_arg (tree valist, tree type)
5646 HOST_WIDE_INT size, rsize, align;
5651 /* Round up sizeof(type) to a word. */
5652 size = int_size_in_bytes (type);
5653 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5658 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5659 align = 2 * UNITS_PER_WORD;
5661 if (AGGREGATE_TYPE_P (type))
5663 if ((unsigned HOST_WIDE_INT) size > 16)
5666 size = rsize = UNITS_PER_WORD;
5669 /* SPARC v9 ABI states that structures up to 8 bytes in size are
5670 given one 8 byte slot. */
5672 size = rsize = UNITS_PER_WORD;
5679 if (AGGREGATE_TYPE_P (type)
5680 || TYPE_MODE (type) == TFmode
5681 || TYPE_MODE (type) == TCmode)
5684 size = rsize = UNITS_PER_WORD;
5691 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5692 build_int_2 (align - 1, 0)));
5693 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5694 build_int_2 (-align, -1)));
5697 addr = incr = save_expr (incr);
5698 if (BYTES_BIG_ENDIAN && size < rsize)
5700 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5701 build_int_2 (rsize - size, 0)));
5703 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5704 build_int_2 (rsize, 0)));
5706 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5707 TREE_SIDE_EFFECTS (incr) = 1;
5708 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5710 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5712 /* If the address isn't aligned properly for the type,
5713 we may need to copy to a temporary.
5714 FIXME: This is inefficient. Usually we can do this
5717 && TYPE_ALIGN (type) > BITS_PER_WORD
5720 /* FIXME: We really need to specify that the temporary is live
5721 for the whole function because expand_builtin_va_arg wants
5722 the alias set to be get_varargs_alias_set (), but in this
5723 case the alias set is that for TYPE and if the memory gets
5724 reused it will be reused with alias set TYPE. */
5725 rtx tmp = assign_temp (type, 0, 1, 0);
5728 addr_rtx = force_reg (Pmode, addr_rtx);
5729 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5730 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5731 set_mem_align (addr_rtx, BITS_PER_WORD);
5732 tmp = shallow_copy_rtx (tmp);
5733 PUT_MODE (tmp, BLKmode);
5734 set_mem_alias_set (tmp, 0);
5736 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
5738 if (dest_addr != NULL_RTX)
5739 addr_rtx = dest_addr;
5741 addr_rtx = XCEXP (tmp, 0, MEM);
5746 addr_rtx = force_reg (Pmode, addr_rtx);
5747 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5748 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5754 /* Return the string to output a conditional branch to LABEL, which is
5755 the operand number of the label. OP is the conditional expression.
5756 XEXP (OP, 0) is assumed to be a condition code register (integer or
5757 floating point) and its mode specifies what kind of comparison we made.
5759 REVERSED is nonzero if we should reverse the sense of the comparison.
5761 ANNUL is nonzero if we should generate an annulling branch.
5763 NOOP is nonzero if we have to follow this branch by a noop.
5765 INSN, if set, is the insn. */
5768 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
5771 static char string[50];
5772 enum rtx_code code = GET_CODE (op);
5773 rtx cc_reg = XEXP (op, 0);
5774 enum machine_mode mode = GET_MODE (cc_reg);
5775 const char *labelno, *branch;
5776 int spaces = 8, far;
5779 /* v9 branches are limited to +-1MB. If it is too far away,
5792 fbne,a,pn %fcc2, .LC29
5800 far = get_attr_length (insn) >= 3;
5803 /* Reversal of FP compares takes care -- an ordered compare
5804 becomes an unordered compare and vice versa. */
5805 if (mode == CCFPmode || mode == CCFPEmode)
5806 code = reverse_condition_maybe_unordered (code);
5808 code = reverse_condition (code);
5811 /* Start by writing the branch condition. */
5812 if (mode == CCFPmode || mode == CCFPEmode)
5863 /* ??? !v9: FP branches cannot be preceded by another floating point
5864 insn. Because there is currently no concept of pre-delay slots,
5865 we can fix this only by always emitting a nop before a floating
5870 strcpy (string, "nop\n\t");
5871 strcat (string, branch);
5884 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5896 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5917 strcpy (string, branch);
5919 spaces -= strlen (branch);
5920 p = strchr (string, '\0');
5922 /* Now add the annulling, the label, and a possible noop. */
5937 if (! far && insn && INSN_ADDRESSES_SET_P ())
5939 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5940 - INSN_ADDRESSES (INSN_UID (insn)));
5941 /* Leave some instructions for "slop". */
5942 if (delta < -260000 || delta >= 260000)
5946 if (mode == CCFPmode || mode == CCFPEmode)
5948 static char v9_fcc_labelno[] = "%%fccX, ";
5949 /* Set the char indicating the number of the fcc reg to use. */
5950 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5951 labelno = v9_fcc_labelno;
5954 if (REGNO (cc_reg) == SPARC_FCC_REG)
5960 else if (mode == CCXmode || mode == CCX_NOOVmode)
5962 labelno = "%%xcc, ";
5968 labelno = "%%icc, ";
5973 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5976 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5986 strcpy (p, labelno);
5987 p = strchr (p, '\0');
5990 strcpy (p, ".+12\n\tnop\n\tb\t");
5997 /* Set the char indicating the number of the operand containing the
6002 strcpy (p, "\n\tnop");
6007 /* Emit a library call comparison between floating point X and Y.
6008 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6009 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6010 values as arguments instead of the TFmode registers themselves,
6011 that's why we cannot call emit_float_lib_cmp. */
6013 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6016 rtx slot0, slot1, result, tem, tem2;
6017 enum machine_mode mode;
6022 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6026 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6030 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6034 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6038 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6042 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6053 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6063 if (GET_CODE (x) != MEM)
6065 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6066 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6071 if (GET_CODE (y) != MEM)
6073 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6074 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6079 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6081 XEXP (slot0, 0), Pmode,
6082 XEXP (slot1, 0), Pmode);
6088 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6090 x, TFmode, y, TFmode);
6096 /* Immediately move the result of the libcall into a pseudo
6097 register so reload doesn't clobber the value if it needs
6098 the return register for a spill reg. */
6099 result = gen_reg_rtx (mode);
6100 emit_move_insn (result, hard_libcall_value (mode));
6105 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6109 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6114 emit_cmp_insn (result, const1_rtx,
6115 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6118 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6121 tem = gen_reg_rtx (mode);
6123 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6125 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6126 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6130 tem = gen_reg_rtx (mode);
6132 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6134 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6135 tem2 = gen_reg_rtx (mode);
6137 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6139 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6140 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6146 /* Generate an unsigned DImode to FP conversion. This is the same code
6147 optabs would emit if we didn't have TFmode patterns. */
6150 sparc_emit_floatunsdi (rtx *operands)
6152 rtx neglab, donelab, i0, i1, f0, in, out;
6153 enum machine_mode mode;
6156 in = force_reg (DImode, operands[1]);
6157 mode = GET_MODE (out);
6158 neglab = gen_label_rtx ();
6159 donelab = gen_label_rtx ();
6160 i0 = gen_reg_rtx (DImode);
6161 i1 = gen_reg_rtx (DImode);
6162 f0 = gen_reg_rtx (mode);
6164 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6166 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6167 emit_jump_insn (gen_jump (donelab));
6170 emit_label (neglab);
6172 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6173 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6174 emit_insn (gen_iordi3 (i0, i0, i1));
6175 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6176 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6178 emit_label (donelab);
6181 /* Return the string to output a conditional branch to LABEL, testing
6182 register REG. LABEL is the operand number of the label; REG is the
6183 operand number of the reg. OP is the conditional expression. The mode
6184 of REG says what kind of comparison we made.
6186 REVERSED is nonzero if we should reverse the sense of the comparison.
6188 ANNUL is nonzero if we should generate an annulling branch.
6190 NOOP is nonzero if we have to follow this branch by a noop. */
6193 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6194 int annul, int noop, rtx insn)
6196 static char string[50];
6197 enum rtx_code code = GET_CODE (op);
6198 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6203 /* branch on register are limited to +-128KB. If it is too far away,
6216 brgez,a,pn %o1, .LC29
6222 ba,pt %xcc, .LC29 */
6224 far = get_attr_length (insn) >= 3;
6226 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6228 code = reverse_condition (code);
6230 /* Only 64 bit versions of these instructions exist. */
6234 /* Start by writing the branch condition. */
6239 strcpy (string, "brnz");
6243 strcpy (string, "brz");
6247 strcpy (string, "brgez");
6251 strcpy (string, "brlz");
6255 strcpy (string, "brlez");
6259 strcpy (string, "brgz");
6266 p = strchr (string, '\0');
6268 /* Now add the annulling, reg, label, and nop. */
6275 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6278 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6283 *p = p < string + 8 ? '\t' : ' ';
6291 int veryfar = 1, delta;
6293 if (INSN_ADDRESSES_SET_P ())
6295 delta = (INSN_ADDRESSES (INSN_UID (dest))
6296 - INSN_ADDRESSES (INSN_UID (insn)));
6297 /* Leave some instructions for "slop". */
6298 if (delta >= -260000 && delta < 260000)
6302 strcpy (p, ".+12\n\tnop\n\t");
6313 strcpy (p, "ba,pt\t%%xcc, ");
6323 strcpy (p, "\n\tnop");
6328 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6329 Such instructions cannot be used in the delay slot of return insn on v9.
6330 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6334 epilogue_renumber (register rtx *where, int test)
6336 register const char *fmt;
6338 register enum rtx_code code;
6343 code = GET_CODE (*where);
6348 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6350 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6351 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6359 /* Do not replace the frame pointer with the stack pointer because
6360 it can cause the delayed instruction to load below the stack.
6361 This occurs when instructions like:
6363 (set (reg/i:SI 24 %i0)
6364 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6365 (const_int -20 [0xffffffec])) 0))
6367 are in the return delayed slot. */
6369 if (GET_CODE (XEXP (*where, 0)) == REG
6370 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6371 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6372 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6377 if (SPARC_STACK_BIAS
6378 && GET_CODE (XEXP (*where, 0)) == REG
6379 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6387 fmt = GET_RTX_FORMAT (code);
6389 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6394 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6395 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6398 else if (fmt[i] == 'e'
6399 && epilogue_renumber (&(XEXP (*where, i)), test))
6405 /* Leaf functions and non-leaf functions have different needs. */
6408 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6411 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6413 static const int *const reg_alloc_orders[] = {
6414 reg_leaf_alloc_order,
6415 reg_nonleaf_alloc_order};
6418 order_regs_for_local_alloc (void)
6420 static int last_order_nonleaf = 1;
6422 if (regs_ever_live[15] != last_order_nonleaf)
6424 last_order_nonleaf = !last_order_nonleaf;
6425 memcpy ((char *) reg_alloc_order,
6426 (const char *) reg_alloc_orders[last_order_nonleaf],
6427 FIRST_PSEUDO_REGISTER * sizeof (int));
6431 /* Return 1 if REG and MEM are legitimate enough to allow the various
6432 mem<-->reg splits to be run. */
6435 sparc_splitdi_legitimate (rtx reg, rtx mem)
6437 /* Punt if we are here by mistake. */
6438 if (! reload_completed)
6441 /* We must have an offsettable memory reference. */
6442 if (! offsettable_memref_p (mem))
6445 /* If we have legitimate args for ldd/std, we do not want
6446 the split to happen. */
6447 if ((REGNO (reg) % 2) == 0
6448 && mem_min_alignment (mem, 8))
6455 /* Return 1 if x and y are some kind of REG and they refer to
6456 different hard registers. This test is guaranteed to be
6457 run after reload. */
6460 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6462 if (GET_CODE (x) != REG)
6464 if (GET_CODE (y) != REG)
6466 if (REGNO (x) == REGNO (y))
6471 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6472 This makes them candidates for using ldd and std insns.
6474 Note reg1 and reg2 *must* be hard registers. */
6477 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6479 /* We might have been passed a SUBREG. */
6480 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6483 if (REGNO (reg1) % 2 != 0)
6486 /* Integer ldd is deprecated in SPARC V9 */
6487 if (TARGET_V9 && REGNO (reg1) < 32)
6490 return (REGNO (reg1) == REGNO (reg2) - 1);
6493 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6496 This can only happen when addr1 and addr2, the addresses in mem1
6497 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6498 addr1 must also be aligned on a 64-bit boundary.
6500 Also iff dependent_reg_rtx is not null it should not be used to
6501 compute the address for mem1, i.e. we cannot optimize a sequence
6513 But, note that the transformation from:
6518 is perfectly fine. Thus, the peephole2 patterns always pass us
6519 the destination register of the first load, never the second one.
6521 For stores we don't have a similar problem, so dependent_reg_rtx is
6525 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6531 /* The mems cannot be volatile. */
6532 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6535 /* MEM1 should be aligned on a 64-bit boundary. */
6536 if (MEM_ALIGN (mem1) < 64)
6539 addr1 = XEXP (mem1, 0);
6540 addr2 = XEXP (mem2, 0);
6542 /* Extract a register number and offset (if used) from the first addr. */
6543 if (GET_CODE (addr1) == PLUS)
6545 /* If not a REG, return zero. */
6546 if (GET_CODE (XEXP (addr1, 0)) != REG)
6550 reg1 = REGNO (XEXP (addr1, 0));
6551 /* The offset must be constant! */
6552 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6554 offset1 = INTVAL (XEXP (addr1, 1));
6557 else if (GET_CODE (addr1) != REG)
6561 reg1 = REGNO (addr1);
6562 /* This was a simple (mem (reg)) expression. Offset is 0. */
6566 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6567 if (GET_CODE (addr2) != PLUS)
6570 if (GET_CODE (XEXP (addr2, 0)) != REG
6571 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6574 if (reg1 != REGNO (XEXP (addr2, 0)))
6577 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6580 /* The first offset must be evenly divisible by 8 to ensure the
6581 address is 64 bit aligned. */
6582 if (offset1 % 8 != 0)
6585 /* The offset for the second addr must be 4 more than the first addr. */
6586 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6589 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6594 /* Return 1 if reg is a pseudo, or is the first register in
6595 a hard register pair. This makes it a candidate for use in
6596 ldd and std insns. */
6599 register_ok_for_ldd (rtx reg)
6601 /* We might have been passed a SUBREG. */
6602 if (GET_CODE (reg) != REG)
6605 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6606 return (REGNO (reg) % 2 == 0);
6611 /* Print operand X (an rtx) in assembler syntax to file FILE.
6612 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6613 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6616 print_operand (FILE *file, rtx x, int code)
6621 /* Output a 'nop' if there's nothing for the delay slot. */
6622 if (dbr_sequence_length () == 0)
6623 fputs ("\n\t nop", file);
6626 /* Output an annul flag if there's nothing for the delay slot and we
6627 are optimizing. This is always used with '(' below. */
6628 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6629 this is a dbx bug. So, we only do this when optimizing. */
6630 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6631 Always emit a nop in case the next instruction is a branch. */
6632 if (dbr_sequence_length () == 0
6633 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6637 /* Output a 'nop' if there's nothing for the delay slot and we are
6638 not optimizing. This is always used with '*' above. */
6639 if (dbr_sequence_length () == 0
6640 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6641 fputs ("\n\t nop", file);
6644 /* Output the Embedded Medium/Anywhere code model base register. */
6645 fputs (EMBMEDANY_BASE_REG, file);
6648 /* Print out what we are using as the frame pointer. This might
6649 be %fp, or might be %sp+offset. */
6650 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6651 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
6654 /* Print some local dynamic TLS name. */
6655 assemble_name (file, get_some_local_dynamic_name ());
6658 /* Adjust the operand to take into account a RESTORE operation. */
6659 if (GET_CODE (x) == CONST_INT)
6661 else if (GET_CODE (x) != REG)
6662 output_operand_lossage ("invalid %%Y operand");
6663 else if (REGNO (x) < 8)
6664 fputs (reg_names[REGNO (x)], file);
6665 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6666 fputs (reg_names[REGNO (x)-16], file);
6668 output_operand_lossage ("invalid %%Y operand");
6671 /* Print out the low order register name of a register pair. */
6672 if (WORDS_BIG_ENDIAN)
6673 fputs (reg_names[REGNO (x)+1], file);
6675 fputs (reg_names[REGNO (x)], file);
6678 /* Print out the high order register name of a register pair. */
6679 if (WORDS_BIG_ENDIAN)
6680 fputs (reg_names[REGNO (x)], file);
6682 fputs (reg_names[REGNO (x)+1], file);
6685 /* Print out the second register name of a register pair or quad.
6686 I.e., R (%o0) => %o1. */
6687 fputs (reg_names[REGNO (x)+1], file);
6690 /* Print out the third register name of a register quad.
6691 I.e., S (%o0) => %o2. */
6692 fputs (reg_names[REGNO (x)+2], file);
6695 /* Print out the fourth register name of a register quad.
6696 I.e., T (%o0) => %o3. */
6697 fputs (reg_names[REGNO (x)+3], file);
6700 /* Print a condition code register. */
6701 if (REGNO (x) == SPARC_ICC_REG)
6703 /* We don't handle CC[X]_NOOVmode because they're not supposed
6705 if (GET_MODE (x) == CCmode)
6706 fputs ("%icc", file);
6707 else if (GET_MODE (x) == CCXmode)
6708 fputs ("%xcc", file);
6713 /* %fccN register */
6714 fputs (reg_names[REGNO (x)], file);
6717 /* Print the operand's address only. */
6718 output_address (XEXP (x, 0));
6721 /* In this case we need a register. Use %g0 if the
6722 operand is const0_rtx. */
6724 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
6726 fputs ("%g0", file);
6733 switch (GET_CODE (x))
6735 case IOR: fputs ("or", file); break;
6736 case AND: fputs ("and", file); break;
6737 case XOR: fputs ("xor", file); break;
6738 default: output_operand_lossage ("invalid %%A operand");
6743 switch (GET_CODE (x))
6745 case IOR: fputs ("orn", file); break;
6746 case AND: fputs ("andn", file); break;
6747 case XOR: fputs ("xnor", file); break;
6748 default: output_operand_lossage ("invalid %%B operand");
6752 /* These are used by the conditional move instructions. */
6756 enum rtx_code rc = GET_CODE (x);
6760 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6761 if (mode == CCFPmode || mode == CCFPEmode)
6762 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6764 rc = reverse_condition (GET_CODE (x));
6768 case NE: fputs ("ne", file); break;
6769 case EQ: fputs ("e", file); break;
6770 case GE: fputs ("ge", file); break;
6771 case GT: fputs ("g", file); break;
6772 case LE: fputs ("le", file); break;
6773 case LT: fputs ("l", file); break;
6774 case GEU: fputs ("geu", file); break;
6775 case GTU: fputs ("gu", file); break;
6776 case LEU: fputs ("leu", file); break;
6777 case LTU: fputs ("lu", file); break;
6778 case LTGT: fputs ("lg", file); break;
6779 case UNORDERED: fputs ("u", file); break;
6780 case ORDERED: fputs ("o", file); break;
6781 case UNLT: fputs ("ul", file); break;
6782 case UNLE: fputs ("ule", file); break;
6783 case UNGT: fputs ("ug", file); break;
6784 case UNGE: fputs ("uge", file); break;
6785 case UNEQ: fputs ("ue", file); break;
6786 default: output_operand_lossage (code == 'c'
6787 ? "invalid %%c operand"
6788 : "invalid %%C operand");
6793 /* These are used by the movr instruction pattern. */
6797 enum rtx_code rc = (code == 'd'
6798 ? reverse_condition (GET_CODE (x))
6802 case NE: fputs ("ne", file); break;
6803 case EQ: fputs ("e", file); break;
6804 case GE: fputs ("gez", file); break;
6805 case LT: fputs ("lz", file); break;
6806 case LE: fputs ("lez", file); break;
6807 case GT: fputs ("gz", file); break;
6808 default: output_operand_lossage (code == 'd'
6809 ? "invalid %%d operand"
6810 : "invalid %%D operand");
6817 /* Print a sign-extended character. */
6818 int i = trunc_int_for_mode (INTVAL (x), QImode);
6819 fprintf (file, "%d", i);
6824 /* Operand must be a MEM; write its address. */
6825 if (GET_CODE (x) != MEM)
6826 output_operand_lossage ("invalid %%f operand");
6827 output_address (XEXP (x, 0));
6832 /* Print a sign-extended 32-bit value. */
6834 if (GET_CODE(x) == CONST_INT)
6836 else if (GET_CODE(x) == CONST_DOUBLE)
6837 i = CONST_DOUBLE_LOW (x);
6840 output_operand_lossage ("invalid %%s operand");
6843 i = trunc_int_for_mode (i, SImode);
6844 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
6849 /* Do nothing special. */
6853 /* Undocumented flag. */
6854 output_operand_lossage ("invalid operand output code");
6857 if (GET_CODE (x) == REG)
6858 fputs (reg_names[REGNO (x)], file);
6859 else if (GET_CODE (x) == MEM)
6862 /* Poor Sun assembler doesn't understand absolute addressing. */
6863 if (CONSTANT_P (XEXP (x, 0)))
6864 fputs ("%g0+", file);
6865 output_address (XEXP (x, 0));
6868 else if (GET_CODE (x) == HIGH)
6870 fputs ("%hi(", file);
6871 output_addr_const (file, XEXP (x, 0));
6874 else if (GET_CODE (x) == LO_SUM)
6876 print_operand (file, XEXP (x, 0), 0);
6877 if (TARGET_CM_MEDMID)
6878 fputs ("+%l44(", file);
6880 fputs ("+%lo(", file);
6881 output_addr_const (file, XEXP (x, 1));
6884 else if (GET_CODE (x) == CONST_DOUBLE
6885 && (GET_MODE (x) == VOIDmode
6886 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
6888 if (CONST_DOUBLE_HIGH (x) == 0)
6889 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
6890 else if (CONST_DOUBLE_HIGH (x) == -1
6891 && CONST_DOUBLE_LOW (x) < 0)
6892 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
6894 output_operand_lossage ("long long constant not a valid immediate operand");
6896 else if (GET_CODE (x) == CONST_DOUBLE)
6897 output_operand_lossage ("floating point constant not a valid immediate operand");
6898 else { output_addr_const (file, x); }
6901 /* Target hook for assembling integer objects. The sparc version has
6902 special handling for aligned DI-mode objects. */
6905 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
6907 /* ??? We only output .xword's for symbols and only then in environments
6908 where the assembler can handle them. */
6909 if (aligned_p && size == 8
6910 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
6914 assemble_integer_with_op ("\t.xword\t", x);
6919 assemble_aligned_integer (4, const0_rtx);
6920 assemble_aligned_integer (4, x);
6924 return default_assemble_integer (x, size, aligned_p);
6927 /* Return the value of a code used in the .proc pseudo-op that says
6928 what kind of result this function returns. For non-C types, we pick
6929 the closest C type. */
6931 #ifndef SHORT_TYPE_SIZE
6932 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6935 #ifndef INT_TYPE_SIZE
6936 #define INT_TYPE_SIZE BITS_PER_WORD
6939 #ifndef LONG_TYPE_SIZE
6940 #define LONG_TYPE_SIZE BITS_PER_WORD
6943 #ifndef LONG_LONG_TYPE_SIZE
6944 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6947 #ifndef FLOAT_TYPE_SIZE
6948 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6951 #ifndef DOUBLE_TYPE_SIZE
6952 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6955 #ifndef LONG_DOUBLE_TYPE_SIZE
6956 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6960 sparc_type_code (register tree type)
6962 register unsigned long qualifiers = 0;
6963 register unsigned shift;
6965 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6966 setting more, since some assemblers will give an error for this. Also,
6967 we must be careful to avoid shifts of 32 bits or more to avoid getting
6968 unpredictable results. */
6970 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
6972 switch (TREE_CODE (type))
6978 qualifiers |= (3 << shift);
6983 qualifiers |= (2 << shift);
6987 case REFERENCE_TYPE:
6989 qualifiers |= (1 << shift);
6993 return (qualifiers | 8);
6996 case QUAL_UNION_TYPE:
6997 return (qualifiers | 9);
7000 return (qualifiers | 10);
7003 return (qualifiers | 16);
7006 /* If this is a range type, consider it to be the underlying
7008 if (TREE_TYPE (type) != 0)
7011 /* Carefully distinguish all the standard types of C,
7012 without messing up if the language is not C. We do this by
7013 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
7014 look at both the names and the above fields, but that's redundant.
7015 Any type whose size is between two C types will be considered
7016 to be the wider of the two types. Also, we do not have a
7017 special code to use for "long long", so anything wider than
7018 long is treated the same. Note that we can't distinguish
7019 between "int" and "long" in this code if they are the same
7020 size, but that's fine, since neither can the assembler. */
7022 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7023 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
7025 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7026 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
7028 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7029 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
7032 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
7035 /* If this is a range type, consider it to be the underlying
7037 if (TREE_TYPE (type) != 0)
7040 /* Carefully distinguish all the standard types of C,
7041 without messing up if the language is not C. */
7043 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7044 return (qualifiers | 6);
7047 return (qualifiers | 7);
7049 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7050 /* ??? We need to distinguish between double and float complex types,
7051 but I don't know how yet because I can't reach this code from
7052 existing front-ends. */
7053 return (qualifiers | 7); /* Who knows? */
7055 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7056 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7057 case FILE_TYPE: /* GNU Pascal FILE type. */
7058 case SET_TYPE: /* GNU Pascal SET type. */
7059 case LANG_TYPE: /* ? */
7063 abort (); /* Not a type! */
7070 /* Nested function support. */
7072 /* Emit RTL insns to initialize the variable parts of a trampoline.
7073 FNADDR is an RTX for the address of the function's pure code.
7074 CXT is an RTX for the static chain value for the function.
7076 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7077 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7078 (to store insns). This is a bit excessive. Perhaps a different
7079 mechanism would be better here.
7081 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7084 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7086 /* SPARC 32 bit trampoline:
7089 sethi %hi(static), %g2
7091 or %g2, %lo(static), %g2
7093 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7094 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7096 #ifdef TRANSFER_FROM_TRAMPOLINE
7097 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7098 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7102 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7103 expand_binop (SImode, ior_optab,
7104 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7105 size_int (10), 0, 1),
7106 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7107 NULL_RTX, 1, OPTAB_DIRECT));
7110 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7111 expand_binop (SImode, ior_optab,
7112 expand_shift (RSHIFT_EXPR, SImode, cxt,
7113 size_int (10), 0, 1),
7114 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7115 NULL_RTX, 1, OPTAB_DIRECT));
7118 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7119 expand_binop (SImode, ior_optab,
7120 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7121 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7122 NULL_RTX, 1, OPTAB_DIRECT));
7125 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7126 expand_binop (SImode, ior_optab,
7127 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7128 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7129 NULL_RTX, 1, OPTAB_DIRECT));
7131 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7132 aligned on a 16 byte boundary so one flush clears it all. */
7133 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7134 if (sparc_cpu != PROCESSOR_ULTRASPARC
7135 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7136 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7137 plus_constant (tramp, 8)))));
7140 /* The 64 bit version is simpler because it makes more sense to load the
7141 values as "immediate" data out of the trampoline. It's also easier since
7142 we can read the PC without clobbering a register. */
7145 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7147 #ifdef TRANSFER_FROM_TRAMPOLINE
7148 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7149 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7160 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7161 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7162 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7163 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7164 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7165 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7166 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7167 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7168 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7169 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7170 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7172 if (sparc_cpu != PROCESSOR_ULTRASPARC
7173 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7174 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7177 /* Subroutines to support a flat (single) register window calling
7180 /* Single-register window sparc stack frames look like:
7182 Before call After call
7183 +-----------------------+ +-----------------------+
7185 mem | caller's temps. | | caller's temps. |
7187 +-----------------------+ +-----------------------+
7189 | arguments on stack. | | arguments on stack. |
7191 +-----------------------+FP+92->+-----------------------+
7192 | 6 words to save | | 6 words to save |
7193 | arguments passed | | arguments passed |
7194 | in registers, even | | in registers, even |
7195 | if not passed. | | if not passed. |
7196 SP+68->+-----------------------+FP+68->+-----------------------+
7197 | 1 word struct addr | | 1 word struct addr |
7198 +-----------------------+FP+64->+-----------------------+
7200 | 16 word reg save area | | 16 word reg save area |
7202 SP->+-----------------------+ FP->+-----------------------+
7204 | fp/alu reg moves |
7205 FP-16->+-----------------------+
7209 +-----------------------+
7211 | fp register save |
7213 +-----------------------+
7215 | gp register save |
7217 +-----------------------+
7219 | alloca allocations |
7221 +-----------------------+
7223 | arguments on stack |
7225 SP+92->+-----------------------+
7227 | arguments passed |
7228 | in registers, even |
7229 low | if not passed. |
7230 memory SP+68->+-----------------------+
7231 | 1 word struct addr |
7232 SP+64->+-----------------------+
7234 I 16 word reg save area |
7236 SP->+-----------------------+ */
7238 /* Structure to be filled in by sparc_flat_compute_frame_size with register
7239 save masks, and offsets for the current function. */
7241 struct sparc_frame_info
7243 unsigned long total_size; /* # bytes that the entire frame takes up. */
7244 unsigned long var_size; /* # bytes that variables take up. */
7245 unsigned long args_size; /* # bytes that outgoing arguments take up. */
7246 unsigned long extra_size; /* # bytes of extra gunk. */
7247 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
7248 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
7249 unsigned long gmask; /* Mask of saved gp registers. */
7250 unsigned long fmask; /* Mask of saved fp registers. */
7251 unsigned long reg_offset; /* Offset from new sp to store regs. */
7252 int initialized; /* Nonzero if frame size already calculated. */
7255 /* Current frame information calculated by sparc_flat_compute_frame_size. */
7256 struct sparc_frame_info current_frame_info;
7258 /* Zero structure to initialize current_frame_info. */
7259 struct sparc_frame_info zero_frame_info;
7261 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
7263 #define RETURN_ADDR_REGNUM 15
7264 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
7265 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
7267 #define MUST_SAVE_REGISTER(regno) \
7268 ((regs_ever_live[regno] && !call_used_regs[regno]) \
7269 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
7270 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
7272 /* Return the bytes needed to compute the frame pointer from the current
7276 sparc_flat_compute_frame_size (int size)
7277 /* # of var. bytes allocated. */
7280 unsigned long total_size; /* # bytes that the entire frame takes up. */
7281 unsigned long var_size; /* # bytes that variables take up. */
7282 unsigned long args_size; /* # bytes that outgoing arguments take up. */
7283 unsigned long extra_size; /* # extra bytes. */
7284 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
7285 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
7286 unsigned long gmask; /* Mask of saved gp registers. */
7287 unsigned long fmask; /* Mask of saved fp registers. */
7288 unsigned long reg_offset; /* Offset to register save area. */
7289 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
7291 /* This is the size of the 16 word reg save area, 1 word struct addr
7292 area, and 4 word fp/alu register copy area. */
7293 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
7303 if (!leaf_function_p ())
7305 /* Also include the size needed for the 6 parameter registers. */
7306 args_size = current_function_outgoing_args_size + 24;
7308 total_size = var_size + args_size;
7310 /* Calculate space needed for gp registers. */
7311 for (regno = 1; regno <= 31; regno++)
7313 if (MUST_SAVE_REGISTER (regno))
7315 /* If we need to save two regs in a row, ensure there's room to bump
7316 up the address to align it to a doubleword boundary. */
7317 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
7319 if (gp_reg_size % 8 != 0)
7321 gp_reg_size += 2 * UNITS_PER_WORD;
7322 gmask |= 3 << regno;
7328 gp_reg_size += UNITS_PER_WORD;
7329 gmask |= 1 << regno;
7334 /* Calculate space needed for fp registers. */
7335 for (regno = 32; regno <= 63; regno++)
7337 if (regs_ever_live[regno] && !call_used_regs[regno])
7339 fp_reg_size += UNITS_PER_WORD;
7340 fmask |= 1 << (regno - 32);
7347 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
7348 /* Ensure save area is 8 byte aligned if we need it. */
7350 if (need_aligned_p && n != 0)
7352 total_size += 8 - n;
7353 reg_offset += 8 - n;
7355 total_size += gp_reg_size + fp_reg_size;
7358 /* If we must allocate a stack frame at all, we must also allocate
7359 room for register window spillage, so as to be binary compatible
7360 with libraries and operating systems that do not use -mflat. */
7362 total_size += extra_size;
7366 total_size = SPARC_STACK_ALIGN (total_size);
7368 /* Save other computed information. */
7369 current_frame_info.total_size = total_size;
7370 current_frame_info.var_size = var_size;
7371 current_frame_info.args_size = args_size;
7372 current_frame_info.extra_size = extra_size;
7373 current_frame_info.gp_reg_size = gp_reg_size;
7374 current_frame_info.fp_reg_size = fp_reg_size;
7375 current_frame_info.gmask = gmask;
7376 current_frame_info.fmask = fmask;
7377 current_frame_info.reg_offset = reg_offset;
7378 current_frame_info.initialized = reload_completed;
7380 /* Ok, we're done. */
7384 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7387 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7388 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7389 [BASE_REG+OFFSET] will always be a valid address.
7391 WORD_OP is either "st" for save, "ld" for restore.
7392 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7395 sparc_flat_save_restore (FILE *file, const char *base_reg,
7396 unsigned int offset, long unsigned int gmask,
7397 long unsigned int fmask, const char *word_op,
7398 const char *doubleword_op,
7399 long unsigned int base_offset)
7403 if (gmask == 0 && fmask == 0)
7406 /* Save registers starting from high to low. We've already saved the
7407 previous frame pointer and previous return address for the debugger's
7408 sake. The debugger allows us to not need a nop in the epilog if at least
7409 one register is reloaded in addition to return address. */
7413 for (regno = 1; regno <= 31; regno++)
7415 if ((gmask & (1L << regno)) != 0)
7417 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7419 /* We can save two registers in a row. If we're not at a
7420 double word boundary, move to one.
7421 sparc_flat_compute_frame_size ensures there's room to do
7423 if (offset % 8 != 0)
7424 offset += UNITS_PER_WORD;
7426 if (word_op[0] == 's')
7428 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7429 doubleword_op, reg_names[regno],
7431 if (dwarf2out_do_frame ())
7433 char *l = dwarf2out_cfi_label ();
7434 dwarf2out_reg_save (l, regno, offset + base_offset);
7436 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7440 fprintf (file, "\t%s\t[%s+%d], %s\n",
7441 doubleword_op, base_reg, offset,
7444 offset += 2 * UNITS_PER_WORD;
7449 if (word_op[0] == 's')
7451 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7452 word_op, reg_names[regno],
7454 if (dwarf2out_do_frame ())
7455 dwarf2out_reg_save ("", regno, offset + base_offset);
7458 fprintf (file, "\t%s\t[%s+%d], %s\n",
7459 word_op, base_reg, offset, reg_names[regno]);
7461 offset += UNITS_PER_WORD;
7469 for (regno = 32; regno <= 63; regno++)
7471 if ((fmask & (1L << (regno - 32))) != 0)
7473 if (word_op[0] == 's')
7475 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7476 word_op, reg_names[regno],
7478 if (dwarf2out_do_frame ())
7479 dwarf2out_reg_save ("", regno, offset + base_offset);
7482 fprintf (file, "\t%s\t[%s+%d], %s\n",
7483 word_op, base_reg, offset, reg_names[regno]);
7485 offset += UNITS_PER_WORD;
7491 /* Set up the stack and frame (if desired) for the function. */
7494 sparc_flat_function_prologue (FILE *file, HOST_WIDE_INT size)
7496 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7497 unsigned long gmask = current_frame_info.gmask;
7499 sparc_output_scratch_registers (file);
7501 /* This is only for the human reader. */
7502 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7503 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7505 current_frame_info.var_size,
7506 current_frame_info.gp_reg_size / 4,
7507 current_frame_info.fp_reg_size / 4,
7508 current_function_outgoing_args_size,
7509 current_frame_info.extra_size);
7511 size = SPARC_STACK_ALIGN (size);
7512 size = (! current_frame_info.initialized
7513 ? sparc_flat_compute_frame_size (size)
7514 : current_frame_info.total_size);
7516 /* These cases shouldn't happen. Catch them now. */
7517 if (size == 0 && (gmask || current_frame_info.fmask))
7520 /* Allocate our stack frame by decrementing %sp.
7521 At present, the only algorithm gdb can use to determine if this is a
7522 flat frame is if we always set %i7 if we set %sp. This can be optimized
7523 in the future by putting in some sort of debugging information that says
7524 this is a `flat' function. However, there is still the case of debugging
7525 code without such debugging information (including cases where most fns
7526 have such info, but there is one that doesn't). So, always do this now
7527 so we don't get a lot of code out there that gdb can't handle.
7528 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7529 distinguish us from a non-flat function but there won't (and shouldn't)
7530 be any differences anyway. The return pc is saved (if necessary) right
7531 after %i7 so gdb won't have to look too far to find it. */
7534 unsigned int reg_offset = current_frame_info.reg_offset;
7535 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7536 static const char *const t1_str = "%g1";
7538 /* Things get a little tricky if local variables take up more than ~4096
7539 bytes and outgoing arguments take up more than ~4096 bytes. When that
7540 happens, the register save area can't be accessed from either end of
7541 the frame. Handle this by decrementing %sp to the start of the gp
7542 register save area, save the regs, update %i7, and then set %sp to its
7543 final value. Given that we only have one scratch register to play
7544 with it is the cheapest solution, and it helps gdb out as it won't
7545 slow down recognition of flat functions.
7546 Don't change the order of insns emitted here without checking with
7547 the gdb folk first. */
7549 /* Is the entire register save area offsettable from %sp? */
7550 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7554 fprintf (file, "\tadd\t%s, %d, %s\n",
7555 sp_str, (int) -size, sp_str);
7556 if (gmask & HARD_FRAME_POINTER_MASK)
7558 fprintf (file, "\tst\t%s, [%s+%d]\n",
7559 fp_str, sp_str, reg_offset);
7560 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7561 sp_str, (int) -size, fp_str, ASM_COMMENT_START);
7567 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7568 ", %s\n\tsub\t%s, %s, %s\n",
7569 size, t1_str, sp_str, t1_str, sp_str);
7570 if (gmask & HARD_FRAME_POINTER_MASK)
7572 fprintf (file, "\tst\t%s, [%s+%d]\n",
7573 fp_str, sp_str, reg_offset);
7574 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7575 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7579 if (dwarf2out_do_frame ())
7581 char *l = dwarf2out_cfi_label ();
7582 if (gmask & HARD_FRAME_POINTER_MASK)
7584 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7585 reg_offset - 4 - size);
7586 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7589 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7591 if (gmask & RETURN_ADDR_MASK)
7593 fprintf (file, "\tst\t%s, [%s+%d]\n",
7594 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7595 if (dwarf2out_do_frame ())
7596 dwarf2out_return_save ("", reg_offset - size);
7599 sparc_flat_save_restore (file, sp_str, reg_offset,
7600 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7601 current_frame_info.fmask,
7602 "st", "std", -size);
7606 /* Subtract %sp in two steps, but make sure there is always a
7607 64 byte register save area, and %sp is properly aligned. */
7608 /* Amount to decrement %sp by, the first time. */
7609 unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7610 /* Offset to register save area from %sp. */
7611 unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset);
7615 fprintf (file, "\tadd\t%s, %d, %s\n",
7616 sp_str, (int) -size1, sp_str);
7617 if (gmask & HARD_FRAME_POINTER_MASK)
7619 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7620 fp_str, sp_str, (int) offset, sp_str, (int) -size1,
7621 fp_str, ASM_COMMENT_START);
7627 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7628 ", %s\n\tsub\t%s, %s, %s\n",
7629 size1, t1_str, sp_str, t1_str, sp_str);
7630 if (gmask & HARD_FRAME_POINTER_MASK)
7632 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7633 fp_str, sp_str, (int) offset, sp_str, t1_str,
7634 fp_str, ASM_COMMENT_START);
7638 if (dwarf2out_do_frame ())
7640 char *l = dwarf2out_cfi_label ();
7641 if (gmask & HARD_FRAME_POINTER_MASK)
7643 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7644 offset - 4 - size1);
7645 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7648 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7650 if (gmask & RETURN_ADDR_MASK)
7652 fprintf (file, "\tst\t%s, [%s+%d]\n",
7653 reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset);
7654 if (dwarf2out_do_frame ())
7655 /* offset - size1 == reg_offset - size
7656 if reg_offset were updated above like offset. */
7657 dwarf2out_return_save ("", offset - size1);
7660 sparc_flat_save_restore (file, sp_str, offset,
7661 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7662 current_frame_info.fmask,
7663 "st", "std", -size1);
7664 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7665 ", %s\n\tsub\t%s, %s, %s\n",
7666 size - size1, t1_str, sp_str, t1_str, sp_str);
7667 if (dwarf2out_do_frame ())
7668 if (! (gmask & HARD_FRAME_POINTER_MASK))
7669 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
7673 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
7676 /* Do any necessary cleanup after a function to restore stack, frame,
7680 sparc_flat_function_epilogue (FILE *file, HOST_WIDE_INT size)
7682 rtx epilogue_delay = current_function_epilogue_delay_list;
7683 int noepilogue = FALSE;
7685 /* This is only for the human reader. */
7686 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
7688 /* The epilogue does not depend on any registers, but the stack
7689 registers, so we assume that if we have 1 pending nop, it can be
7690 ignored, and 2 it must be filled (2 nops occur for integer
7691 multiply and divide). */
7693 size = SPARC_STACK_ALIGN (size);
7694 size = (!current_frame_info.initialized
7695 ? sparc_flat_compute_frame_size (size)
7696 : current_frame_info.total_size);
7698 if (size == 0 && epilogue_delay == 0)
7700 rtx insn = get_last_insn ();
7702 /* If the last insn was a BARRIER, we don't have to write any code
7703 because a jump (aka return) was put there. */
7704 if (GET_CODE (insn) == NOTE)
7705 insn = prev_nonnote_insn (insn);
7706 if (insn && GET_CODE (insn) == BARRIER)
7712 unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset;
7713 unsigned HOST_WIDE_INT size1;
7714 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7715 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7716 static const char *const t1_str = "%g1";
7718 /* In the reload sequence, we don't need to fill the load delay
7719 slots for most of the loads, also see if we can fill the final
7720 delay slot if not otherwise filled by the reload sequence. */
7723 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC ", %s\n",
7726 if (frame_pointer_needed)
7729 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7730 fp_str, t1_str, sp_str, ASM_COMMENT_START);
7732 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
7733 fp_str, (int) size, sp_str, ASM_COMMENT_START);
7736 /* Is the entire register save area offsettable from %sp? */
7737 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7743 /* Restore %sp in two steps, but make sure there is always a
7744 64 byte register save area, and %sp is properly aligned. */
7745 /* Amount to increment %sp by, the first time. */
7746 size1 = ((reg_offset - 64 - 16) + 15) & -16;
7747 /* Offset to register save area from %sp. */
7748 reg_offset = size1 - reg_offset;
7750 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7751 ", %s\n\tadd\t%s, %s, %s\n",
7752 size1, t1_str, sp_str, t1_str, sp_str);
7755 /* We must restore the frame pointer and return address reg first
7756 because they are treated specially by the prologue output code. */
7757 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
7759 fprintf (file, "\tld\t[%s+%d], %s\n",
7760 sp_str, (int) reg_offset, fp_str);
7763 if (current_frame_info.gmask & RETURN_ADDR_MASK)
7765 fprintf (file, "\tld\t[%s+%d], %s\n",
7766 sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]);
7770 /* Restore any remaining saved registers. */
7771 sparc_flat_save_restore (file, sp_str, reg_offset,
7772 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7773 current_frame_info.fmask,
7776 /* If we had to increment %sp in two steps, record it so the second
7777 restoration in the epilogue finishes up. */
7782 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC ", %s\n",
7786 if (current_function_returns_struct)
7787 fprintf (file, "\tjmp\t%%o7+12\n");
7789 fprintf (file, "\tretl\n");
7791 /* If the only register saved is the return address, we need a
7792 nop, unless we have an instruction to put into it. Otherwise
7793 we don't since reloading multiple registers doesn't reference
7794 the register being loaded. */
7800 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
7803 else if (size > 4095)
7804 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7807 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str);
7810 fprintf (file, "\tnop\n");
7813 /* Reset state info for each function. */
7814 current_frame_info = zero_frame_info;
7816 sparc_output_deferred_case_vectors ();
7819 /* Define the number of delay slots needed for the function epilogue.
7821 On the sparc, we need a slot if either no stack has been allocated,
7822 or the only register saved is the return register. */
7825 sparc_flat_epilogue_delay_slots (void)
7827 if (!current_frame_info.initialized)
7828 (void) sparc_flat_compute_frame_size (get_frame_size ());
7830 if (current_frame_info.total_size == 0)
7836 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7837 Any single length instruction which doesn't reference the stack or frame
7841 sparc_flat_eligible_for_epilogue_delay (rtx trial, int slot ATTRIBUTE_UNUSED)
7843 rtx pat = PATTERN (trial);
7845 if (get_attr_length (trial) != 1)
7848 if (! reg_mentioned_p (stack_pointer_rtx, pat)
7849 && ! reg_mentioned_p (frame_pointer_rtx, pat))
7855 /* Adjust the cost of a scheduling dependency. Return the new cost of
7856 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7859 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7861 enum attr_type insn_type;
7863 if (! recog_memoized (insn))
7866 insn_type = get_attr_type (insn);
7868 if (REG_NOTE_KIND (link) == 0)
7870 /* Data dependency; DEP_INSN writes a register that INSN reads some
7873 /* if a load, then the dependence must be on the memory address;
7874 add an extra "cycle". Note that the cost could be two cycles
7875 if the reg was written late in an instruction group; we ca not tell
7877 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7880 /* Get the delay only if the address of the store is the dependence. */
7881 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7883 rtx pat = PATTERN(insn);
7884 rtx dep_pat = PATTERN (dep_insn);
7886 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7887 return cost; /* This should not happen! */
7889 /* The dependency between the two instructions was on the data that
7890 is being stored. Assume that this implies that the address of the
7891 store is not dependent. */
7892 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7895 return cost + 3; /* An approximation. */
7898 /* A shift instruction cannot receive its data from an instruction
7899 in the same cycle; add a one cycle penalty. */
7900 if (insn_type == TYPE_SHIFT)
7901 return cost + 3; /* Split before cascade into shift. */
7905 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7906 INSN writes some cycles later. */
7908 /* These are only significant for the fpu unit; writing a fp reg before
7909 the fpu has finished with it stalls the processor. */
7911 /* Reusing an integer register causes no problems. */
7912 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7920 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7922 enum attr_type insn_type, dep_type;
7923 rtx pat = PATTERN(insn);
7924 rtx dep_pat = PATTERN (dep_insn);
7926 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7929 insn_type = get_attr_type (insn);
7930 dep_type = get_attr_type (dep_insn);
7932 switch (REG_NOTE_KIND (link))
7935 /* Data dependency; DEP_INSN writes a register that INSN reads some
7942 /* Get the delay iff the address of the store is the dependence. */
7943 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7946 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7953 /* If a load, then the dependence must be on the memory address. If
7954 the addresses aren't equal, then it might be a false dependency */
7955 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7957 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7958 || GET_CODE (SET_DEST (dep_pat)) != MEM
7959 || GET_CODE (SET_SRC (pat)) != MEM
7960 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7961 XEXP (SET_SRC (pat), 0)))
7969 /* Compare to branch latency is 0. There is no benefit from
7970 separating compare and branch. */
7971 if (dep_type == TYPE_COMPARE)
7973 /* Floating point compare to branch latency is less than
7974 compare to conditional move. */
7975 if (dep_type == TYPE_FPCMP)
7984 /* Anti-dependencies only penalize the fpu unit. */
7985 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7997 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8001 case PROCESSOR_SUPERSPARC:
8002 cost = supersparc_adjust_cost (insn, link, dep, cost);
8004 case PROCESSOR_HYPERSPARC:
8005 case PROCESSOR_SPARCLITE86X:
8006 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8015 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8016 int sched_verbose ATTRIBUTE_UNUSED,
8017 int max_ready ATTRIBUTE_UNUSED)
8022 sparc_use_dfa_pipeline_interface (void)
8024 if ((1 << sparc_cpu) &
8025 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
8026 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8027 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
8028 (1 << PROCESSOR_ULTRASPARC3)))
8034 sparc_use_sched_lookahead (void)
8036 if (sparc_cpu == PROCESSOR_ULTRASPARC
8037 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8039 if ((1 << sparc_cpu) &
8040 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8041 (1 << PROCESSOR_SPARCLITE86X)))
8047 sparc_issue_rate (void)
8054 /* Assume V9 processors are capable of at least dual-issue. */
8056 case PROCESSOR_SUPERSPARC:
8058 case PROCESSOR_HYPERSPARC:
8059 case PROCESSOR_SPARCLITE86X:
8061 case PROCESSOR_ULTRASPARC:
8062 case PROCESSOR_ULTRASPARC3:
8068 set_extends (rtx insn)
8070 register rtx pat = PATTERN (insn);
8072 switch (GET_CODE (SET_SRC (pat)))
8074 /* Load and some shift instructions zero extend. */
8077 /* sethi clears the high bits */
8079 /* LO_SUM is used with sethi. sethi cleared the high
8080 bits and the values used with lo_sum are positive */
8082 /* Store flag stores 0 or 1 */
8092 rtx op0 = XEXP (SET_SRC (pat), 0);
8093 rtx op1 = XEXP (SET_SRC (pat), 1);
8094 if (GET_CODE (op1) == CONST_INT)
8095 return INTVAL (op1) >= 0;
8096 if (GET_CODE (op0) != REG)
8098 if (sparc_check_64 (op0, insn) == 1)
8100 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8105 rtx op0 = XEXP (SET_SRC (pat), 0);
8106 rtx op1 = XEXP (SET_SRC (pat), 1);
8107 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8109 if (GET_CODE (op1) == CONST_INT)
8110 return INTVAL (op1) >= 0;
8111 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8114 return GET_MODE (SET_SRC (pat)) == SImode;
8115 /* Positive integers leave the high bits zero. */
8117 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8119 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8122 return - (GET_MODE (SET_SRC (pat)) == SImode);
8124 return sparc_check_64 (SET_SRC (pat), insn);
8130 /* We _ought_ to have only one kind per function, but... */
8131 static GTY(()) rtx sparc_addr_diff_list;
8132 static GTY(()) rtx sparc_addr_list;
8135 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8137 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8139 sparc_addr_diff_list
8140 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8142 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8146 sparc_output_addr_vec (rtx vec)
8148 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8149 int idx, vlen = XVECLEN (body, 0);
8151 #ifdef ASM_OUTPUT_ADDR_VEC_START
8152 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8155 #ifdef ASM_OUTPUT_CASE_LABEL
8156 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8159 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8162 for (idx = 0; idx < vlen; idx++)
8164 ASM_OUTPUT_ADDR_VEC_ELT
8165 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8168 #ifdef ASM_OUTPUT_ADDR_VEC_END
8169 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8174 sparc_output_addr_diff_vec (rtx vec)
8176 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8177 rtx base = XEXP (XEXP (body, 0), 0);
8178 int idx, vlen = XVECLEN (body, 1);
8180 #ifdef ASM_OUTPUT_ADDR_VEC_START
8181 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8184 #ifdef ASM_OUTPUT_CASE_LABEL
8185 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8188 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8191 for (idx = 0; idx < vlen; idx++)
8193 ASM_OUTPUT_ADDR_DIFF_ELT
8196 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8197 CODE_LABEL_NUMBER (base));
8200 #ifdef ASM_OUTPUT_ADDR_VEC_END
8201 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8206 sparc_output_deferred_case_vectors (void)
8211 if (sparc_addr_list == NULL_RTX
8212 && sparc_addr_diff_list == NULL_RTX)
8215 /* Align to cache line in the function's code section. */
8216 function_section (current_function_decl);
8218 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8220 ASM_OUTPUT_ALIGN (asm_out_file, align);
8222 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8223 sparc_output_addr_vec (XEXP (t, 0));
8224 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8225 sparc_output_addr_diff_vec (XEXP (t, 0));
8227 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8230 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8231 unknown. Return 1 if the high bits are zero, -1 if the register is
8234 sparc_check_64 (rtx x, rtx insn)
8236 /* If a register is set only once it is safe to ignore insns this
8237 code does not know how to handle. The loop will either recognize
8238 the single set and return the correct value or fail to recognize
8243 if (GET_CODE (x) != REG)
8246 if (GET_MODE (x) == DImode)
8247 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8249 if (flag_expensive_optimizations
8250 && REG_N_SETS (REGNO (y)) == 1)
8256 insn = get_last_insn_anywhere ();
8261 while ((insn = PREV_INSN (insn)))
8263 switch (GET_CODE (insn))
8276 rtx pat = PATTERN (insn);
8277 if (GET_CODE (pat) != SET)
8279 if (rtx_equal_p (x, SET_DEST (pat)))
8280 return set_extends (insn);
8281 if (y && rtx_equal_p (y, SET_DEST (pat)))
8282 return set_extends (insn);
8283 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8291 /* Returns assembly code to perform a DImode shift using
8292 a 64-bit global or out register on SPARC-V8+. */
8294 sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8296 static char asm_code[60];
8298 /* The scratch register is only required when the destination
8299 register is not a 64-bit global or out register. */
8300 if (which_alternative != 2)
8301 operands[3] = operands[0];
8303 /* We can only shift by constants <= 63. */
8304 if (GET_CODE (operands[2]) == CONST_INT)
8305 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8307 if (GET_CODE (operands[1]) == CONST_INT)
8309 output_asm_insn ("mov\t%1, %3", operands);
8313 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8314 if (sparc_check_64 (operands[1], insn) <= 0)
8315 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8316 output_asm_insn ("or\t%L1, %3, %3", operands);
8319 strcpy(asm_code, opcode);
8321 if (which_alternative != 2)
8322 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8324 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8327 /* Output rtl to increment the profiler label LABELNO
8328 for profiling a function entry. */
8331 sparc_profile_hook (int labelno)
8336 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8337 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8338 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8340 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8343 #ifdef OBJECT_FORMAT_ELF
8345 sparc_elf_asm_named_section (const char *name, unsigned int flags)
8347 if (flags & SECTION_MERGE)
8349 /* entsize cannot be expressed in this section attributes
8351 default_elf_asm_named_section (name, flags);
8355 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8357 if (!(flags & SECTION_DEBUG))
8358 fputs (",#alloc", asm_out_file);
8359 if (flags & SECTION_WRITE)
8360 fputs (",#write", asm_out_file);
8361 if (flags & SECTION_CODE)
8362 fputs (",#execinstr", asm_out_file);
8364 /* ??? Handle SECTION_BSS. */
8366 fputc ('\n', asm_out_file);
8368 #endif /* OBJECT_FORMAT_ELF */
8370 /* We do not allow sibling calls if -mflat, nor
8371 we do not allow indirect calls to be optimized into sibling calls.
8373 Also, on sparc 32-bit we cannot emit a sibling call when the
8374 current function returns a structure. This is because the "unimp
8375 after call" convention would cause the callee to return to the
8376 wrong place. The generic code already disallows cases where the
8377 function being called returns a structure.
8379 It may seem strange how this last case could occur. Usually there
8380 is code after the call which jumps to epilogue code which dumps the
8381 return value into the struct return area. That ought to invalidate
8382 the sibling call right? Well, in the c++ case we can end up passing
8383 the pointer to the struct return area to a constructor (which returns
8384 void) and then nothing else happens. Such a sibling call would look
8385 valid without the added check here. */
8387 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8391 && (TARGET_ARCH64 || ! current_function_returns_struct));
8394 /* libfunc renaming. */
8395 #include "config/gofast.h"
8398 sparc_init_libfuncs (void)
8402 /* Use the subroutines that Sun's library provides for integer
8403 multiply and divide. The `*' prevents an underscore from
8404 being prepended by the compiler. .umul is a little faster
8406 set_optab_libfunc (smul_optab, SImode, "*.umul");
8407 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8408 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8409 set_optab_libfunc (smod_optab, SImode, "*.rem");
8410 set_optab_libfunc (umod_optab, SImode, "*.urem");
8412 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8413 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8414 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8415 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8416 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8417 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8419 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8420 is because with soft-float, the SFmode and DFmode sqrt
8421 instructions will be absent, and the compiler will notice and
8422 try to use the TFmode sqrt instruction for calls to the
8423 builtin function sqrt, but this fails. */
8425 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8427 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8428 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8429 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8430 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8431 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8432 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8434 trunctfsf2_libfunc = init_one_libfunc ("_Q_qtos");
8435 trunctfdf2_libfunc = init_one_libfunc ("_Q_qtod");
8436 extendsftf2_libfunc = init_one_libfunc ("_Q_stoq");
8437 extenddftf2_libfunc = init_one_libfunc ("_Q_dtoq");
8438 floatsitf_libfunc = init_one_libfunc ("_Q_itoq");
8439 fixtfsi_libfunc = init_one_libfunc ("_Q_qtoi");
8440 fixunstfsi_libfunc = init_one_libfunc ("_Q_qtou");
8442 if (SUN_CONVERSION_LIBFUNCS)
8444 fixsfdi_libfunc = init_one_libfunc ("__ftoll");
8445 fixunssfdi_libfunc = init_one_libfunc ("__ftoull");
8446 fixdfdi_libfunc = init_one_libfunc ("__dtoll");
8447 fixunsdfdi_libfunc = init_one_libfunc ("__dtoull");
8452 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8453 do not exist in the library. Make sure the compiler does not
8454 emit calls to them by accident. (It should always use the
8455 hardware instructions.) */
8456 set_optab_libfunc (smul_optab, SImode, 0);
8457 set_optab_libfunc (sdiv_optab, SImode, 0);
8458 set_optab_libfunc (udiv_optab, SImode, 0);
8459 set_optab_libfunc (smod_optab, SImode, 0);
8460 set_optab_libfunc (umod_optab, SImode, 0);
8462 if (SUN_INTEGER_MULTIPLY_64)
8464 set_optab_libfunc (smul_optab, DImode, "__mul64");
8465 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8466 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8467 set_optab_libfunc (smod_optab, DImode, "__rem64");
8468 set_optab_libfunc (umod_optab, DImode, "__urem64");
8471 if (SUN_CONVERSION_LIBFUNCS)
8473 fixsfdi_libfunc = init_one_libfunc ("__ftol");
8474 fixunssfdi_libfunc = init_one_libfunc ("__ftoul");
8475 fixdfdi_libfunc = init_one_libfunc ("__dtol");
8476 fixunsdfdi_libfunc = init_one_libfunc ("__dtoul");
8480 gofast_maybe_init_libfuncs ();
8483 /* ??? Similar to the standard section selection, but force reloc-y-ness
8484 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8485 pretending PIC always on), but that's what the old code did. */
8488 sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align)
8490 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
8493 /* Use text section for a constant unless we need more alignment than
8497 sparc_aout_select_rtx_section (enum machine_mode mode, rtx x,
8498 unsigned HOST_WIDE_INT align)
8500 if (align <= MAX_TEXT_ALIGN
8501 && ! (flag_pic && (symbolic_operand (x, mode)
8502 || SUNOS4_SHARED_LIBRARIES)))
8503 readonly_data_section ();
8509 sparc_extra_constraint_check (rtx op, int c, int strict)
8514 && (c == 'T' || c == 'U'))
8520 return fp_sethi_p (op);
8523 return fp_mov_p (op);
8526 return fp_high_losum_p (op);
8530 || (GET_CODE (op) == REG
8531 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8532 || reg_renumber[REGNO (op)] >= 0)))
8533 return register_ok_for_ldd (op);
8545 /* Our memory extra constraints have to emulate the
8546 behavior of 'm' and 'o' in order for reload to work
8548 if (GET_CODE (op) == MEM)
8551 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8553 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8558 reload_ok_mem = (reload_in_progress
8559 && GET_CODE (op) == REG
8560 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8561 && reg_renumber [REGNO (op)] < 0);
8564 return reload_ok_mem;
8567 /* ??? This duplicates information provided to the compiler by the
8568 ??? scheduler description. Some day, teach genautomata to output
8569 ??? the latencies and then CSE will just use that. */
8572 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8576 case PLUS: case MINUS: case ABS: case NEG:
8577 case FLOAT: case UNSIGNED_FLOAT:
8578 case FIX: case UNSIGNED_FIX:
8579 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8580 if (FLOAT_MODE_P (GET_MODE (x)))
8584 case PROCESSOR_ULTRASPARC:
8585 case PROCESSOR_ULTRASPARC3:
8586 *total = COSTS_N_INSNS (4);
8589 case PROCESSOR_SUPERSPARC:
8590 *total = COSTS_N_INSNS (3);
8593 case PROCESSOR_CYPRESS:
8594 *total = COSTS_N_INSNS (5);
8597 case PROCESSOR_HYPERSPARC:
8598 case PROCESSOR_SPARCLITE86X:
8600 *total = COSTS_N_INSNS (1);
8605 *total = COSTS_N_INSNS (1);
8611 case PROCESSOR_ULTRASPARC:
8612 if (GET_MODE (x) == SFmode)
8613 *total = COSTS_N_INSNS (13);
8615 *total = COSTS_N_INSNS (23);
8618 case PROCESSOR_ULTRASPARC3:
8619 if (GET_MODE (x) == SFmode)
8620 *total = COSTS_N_INSNS (20);
8622 *total = COSTS_N_INSNS (29);
8625 case PROCESSOR_SUPERSPARC:
8626 *total = COSTS_N_INSNS (12);
8629 case PROCESSOR_CYPRESS:
8630 *total = COSTS_N_INSNS (63);
8633 case PROCESSOR_HYPERSPARC:
8634 case PROCESSOR_SPARCLITE86X:
8635 *total = COSTS_N_INSNS (17);
8639 *total = COSTS_N_INSNS (30);
8644 if (FLOAT_MODE_P (GET_MODE (x)))
8648 case PROCESSOR_ULTRASPARC:
8649 case PROCESSOR_ULTRASPARC3:
8650 *total = COSTS_N_INSNS (1);
8653 case PROCESSOR_SUPERSPARC:
8654 *total = COSTS_N_INSNS (3);
8657 case PROCESSOR_CYPRESS:
8658 *total = COSTS_N_INSNS (5);
8661 case PROCESSOR_HYPERSPARC:
8662 case PROCESSOR_SPARCLITE86X:
8664 *total = COSTS_N_INSNS (1);
8669 /* ??? Maybe mark integer compares as zero cost on
8670 ??? all UltraSPARC processors because the result
8671 ??? can be bypassed to a branch in the same group. */
8673 *total = COSTS_N_INSNS (1);
8677 if (FLOAT_MODE_P (GET_MODE (x)))
8681 case PROCESSOR_ULTRASPARC:
8682 case PROCESSOR_ULTRASPARC3:
8683 *total = COSTS_N_INSNS (4);
8686 case PROCESSOR_SUPERSPARC:
8687 *total = COSTS_N_INSNS (3);
8690 case PROCESSOR_CYPRESS:
8691 *total = COSTS_N_INSNS (7);
8694 case PROCESSOR_HYPERSPARC:
8695 case PROCESSOR_SPARCLITE86X:
8696 *total = COSTS_N_INSNS (1);
8700 *total = COSTS_N_INSNS (5);
8705 /* The latency is actually variable for Ultra-I/II
8706 And if one of the inputs have a known constant
8707 value, we could calculate this precisely.
8709 However, for that to be useful we would need to
8710 add some machine description changes which would
8711 make sure small constants ended up in rs1 of the
8712 multiply instruction. This is because the multiply
8713 latency is determined by the number of clear (or
8714 set if the value is negative) bits starting from
8715 the most significant bit of the first input.
8717 The algorithm for computing num_cycles of a multiply
8721 highest_bit = highest_clear_bit(rs1);
8723 highest_bit = highest_set_bit(rs1);
8726 num_cycles = 4 + ((highest_bit - 3) / 2);
8728 If we did that we would have to also consider register
8729 allocation issues that would result from forcing such
8730 a value into a register.
8732 There are other similar tricks we could play if we
8733 knew, for example, that one input was an array index.
8735 Since we do not play any such tricks currently the
8736 safest thing to do is report the worst case latency. */
8737 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8739 *total = (GET_MODE (x) == DImode
8740 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8744 /* Multiply latency on Ultra-III, fortunately, is constant. */
8745 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8747 *total = COSTS_N_INSNS (6);
8751 if (sparc_cpu == PROCESSOR_HYPERSPARC
8752 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8754 *total = COSTS_N_INSNS (17);
8758 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
8765 if (FLOAT_MODE_P (GET_MODE (x)))
8769 case PROCESSOR_ULTRASPARC:
8770 if (GET_MODE (x) == SFmode)
8771 *total = COSTS_N_INSNS (13);
8773 *total = COSTS_N_INSNS (23);
8776 case PROCESSOR_ULTRASPARC3:
8777 if (GET_MODE (x) == SFmode)
8778 *total = COSTS_N_INSNS (17);
8780 *total = COSTS_N_INSNS (20);
8783 case PROCESSOR_SUPERSPARC:
8784 if (GET_MODE (x) == SFmode)
8785 *total = COSTS_N_INSNS (6);
8787 *total = COSTS_N_INSNS (9);
8790 case PROCESSOR_HYPERSPARC:
8791 case PROCESSOR_SPARCLITE86X:
8792 if (GET_MODE (x) == SFmode)
8793 *total = COSTS_N_INSNS (8);
8795 *total = COSTS_N_INSNS (12);
8799 *total = COSTS_N_INSNS (7);
8804 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8805 *total = (GET_MODE (x) == DImode
8806 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8807 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8808 *total = (GET_MODE (x) == DImode
8809 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8811 *total = COSTS_N_INSNS (25);
8815 /* Conditional moves. */
8818 case PROCESSOR_ULTRASPARC:
8819 *total = COSTS_N_INSNS (2);
8822 case PROCESSOR_ULTRASPARC3:
8823 if (FLOAT_MODE_P (GET_MODE (x)))
8824 *total = COSTS_N_INSNS (3);
8826 *total = COSTS_N_INSNS (2);
8830 *total = COSTS_N_INSNS (1);
8835 /* If outer-code is SIGN/ZERO extension we have to subtract
8836 out COSTS_N_INSNS (1) from whatever we return in determining
8840 case PROCESSOR_ULTRASPARC:
8841 if (outer_code == ZERO_EXTEND)
8842 *total = COSTS_N_INSNS (1);
8844 *total = COSTS_N_INSNS (2);
8847 case PROCESSOR_ULTRASPARC3:
8848 if (outer_code == ZERO_EXTEND)
8850 if (GET_MODE (x) == QImode
8851 || GET_MODE (x) == HImode
8852 || outer_code == SIGN_EXTEND)
8853 *total = COSTS_N_INSNS (2);
8855 *total = COSTS_N_INSNS (1);
8859 /* This handles sign extension (3 cycles)
8860 and everything else (2 cycles). */
8861 *total = COSTS_N_INSNS (2);
8865 case PROCESSOR_SUPERSPARC:
8866 if (FLOAT_MODE_P (GET_MODE (x))
8867 || outer_code == ZERO_EXTEND
8868 || outer_code == SIGN_EXTEND)
8869 *total = COSTS_N_INSNS (0);
8871 *total = COSTS_N_INSNS (1);
8874 case PROCESSOR_TSC701:
8875 if (outer_code == ZERO_EXTEND
8876 || outer_code == SIGN_EXTEND)
8877 *total = COSTS_N_INSNS (2);
8879 *total = COSTS_N_INSNS (3);
8882 case PROCESSOR_CYPRESS:
8883 if (outer_code == ZERO_EXTEND
8884 || outer_code == SIGN_EXTEND)
8885 *total = COSTS_N_INSNS (1);
8887 *total = COSTS_N_INSNS (2);
8890 case PROCESSOR_HYPERSPARC:
8891 case PROCESSOR_SPARCLITE86X:
8893 if (outer_code == ZERO_EXTEND
8894 || outer_code == SIGN_EXTEND)
8895 *total = COSTS_N_INSNS (0);
8897 *total = COSTS_N_INSNS (1);
8902 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8920 if (GET_MODE (x) == DImode
8921 && ((XINT (x, 3) == 0
8922 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8923 || (XINT (x, 3) == -1
8925 && XINT (x, 2) >= -0x1000)))
8936 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8937 Used for C++ multiple inheritance. */
8940 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8941 HOST_WIDE_INT delta,
8942 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8945 rtx this, insn, funexp, delta_rtx, tmp;
8947 reload_completed = 1;
8948 epilogue_completed = 1;
8950 current_function_uses_only_leaf_regs = 1;
8952 emit_note (NOTE_INSN_PROLOGUE_END);
8954 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8955 returns a structure, the structure return pointer is there instead. */
8956 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8957 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
8959 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
8961 /* Add DELTA. When possible use a plain add, otherwise load it into
8962 a register first. */
8963 delta_rtx = GEN_INT (delta);
8964 if (!SPARC_SIMM13_P (delta))
8966 rtx scratch = gen_rtx_REG (Pmode, 1);
8968 sparc_emit_set_const64 (scratch, delta_rtx);
8970 sparc_emit_set_const32 (scratch, delta_rtx);
8971 delta_rtx = scratch;
8974 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
8975 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
8977 /* Generate a tail call to the target function. */
8978 if (! TREE_USED (function))
8980 assemble_external (function);
8981 TREE_USED (function) = 1;
8983 funexp = XEXP (DECL_RTL (function), 0);
8984 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8985 insn = emit_call_insn (gen_sibcall (funexp));
8986 SIBLING_CALL_P (insn) = 1;
8989 /* Run just enough of rest_of_compilation to get the insns emitted.
8990 There's not really enough bulk here to make other passes such as
8991 instruction scheduling worth while. Note that use_thunk calls
8992 assemble_start_function and assemble_end_function. */
8993 insn = get_insns ();
8994 insn_locators_initialize ();
8995 shorten_branches (insn);
8996 final_start_function (insn, file, 1);
8997 final (insn, file, 1, 0);
8998 final_end_function ();
9000 reload_completed = 0;
9001 epilogue_completed = 0;
9005 /* How to allocate a 'struct machine_function'. */
9007 static struct machine_function *
9008 sparc_init_machine_status (void)
9010 return ggc_alloc_cleared (sizeof (struct machine_function));
9013 /* Locate some local-dynamic symbol still in use by this function
9014 so that we can print its name in local-dynamic base patterns. */
9017 get_some_local_dynamic_name (void)
9021 if (cfun->machine->some_ld_name)
9022 return cfun->machine->some_ld_name;
9024 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9026 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
9027 return cfun->machine->some_ld_name;
9033 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9038 && GET_CODE (x) == SYMBOL_REF
9039 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9041 cfun->machine->some_ld_name = XSTR (x, 0);
9048 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
9049 We need to emit DTP-relative relocations. */
9052 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
9057 fputs ("\t.word\t%r_tls_dtpoff32(", file);
9060 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
9065 output_addr_const (file, x);
9069 #include "gt-sparc.h"