1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
41 /* 1 if the caller has placed an "unimp" insn immediately after the call.
42 This is used in v8 code when calling a function that returns a structure.
43 v9 doesn't have this. Be careful to have this test be the same as that
46 #define SKIP_CALLERS_UNIMP_P \
47 (!TARGET_ARCH64 && current_function_returns_struct \
48 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
49 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
52 /* Global variables for machine-dependent things. */
54 /* Size of frame. Need to know this to emit return insns from leaf procedures.
55 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
56 reload pass. This is important as the value is later used in insn
57 scheduling (to see what can go in a delay slot).
58 APPARENT_FSIZE is the size of the stack less the register save area and less
59 the outgoing argument area. It is used when saving call preserved regs. */
60 static int apparent_fsize;
61 static int actual_fsize;
63 /* Save the operands last given to a compare for use when we
64 generate a scc or bcc insn. */
66 rtx sparc_compare_op0, sparc_compare_op1;
68 /* We may need an epilogue if we spill too many registers.
69 If this is non-zero, then we branch here for the epilogue. */
70 static rtx leaf_label;
74 /* Vector to say how input registers are mapped to output
75 registers. FRAME_POINTER_REGNUM cannot be remapped by
76 this function to eliminate it. You must use -fomit-frame-pointer
78 char leaf_reg_remap[] =
79 { 0, 1, 2, 3, 4, 5, 6, 7,
80 -1, -1, -1, -1, -1, -1, 14, -1,
81 -1, -1, -1, -1, -1, -1, -1, -1,
82 8, 9, 10, 11, 12, 13, -1, 15,
84 32, 33, 34, 35, 36, 37, 38, 39,
85 40, 41, 42, 43, 44, 45, 46, 47,
86 48, 49, 50, 51, 52, 53, 54, 55,
87 56, 57, 58, 59, 60, 61, 62, 63,
88 64, 65, 66, 67, 68, 69, 70, 71,
89 72, 73, 74, 75, 76, 77, 78, 79,
90 80, 81, 82, 83, 84, 85, 86, 87,
91 88, 89, 90, 91, 92, 93, 94, 95,
96 /* Name of where we pretend to think the frame pointer points.
97 Normally, this is "%fp", but if we are in a leaf procedure,
98 this is "%sp+something". We record "something" separately as it may be
99 too big for reg+constant addressing. */
101 static char *frame_base_name;
102 static int frame_base_offset;
104 static rtx pic_setup_code PROTO((void));
105 static void sparc_init_modes PROTO((void));
106 static int save_regs PROTO((FILE *, int, int, char *,
108 static int restore_regs PROTO((FILE *, int, int, char *, int, int));
109 static void build_big_number PROTO((FILE *, int, char *));
110 static int function_arg_slotno PROTO((const CUMULATIVE_ARGS *,
111 enum machine_mode, tree, int, int,
113 static void sparc_output_addr_vec PROTO((rtx));
114 static void sparc_output_addr_diff_vec PROTO((rtx));
115 static void sparc_output_deferred_case_vectors PROTO((void));
118 #ifdef DWARF2_DEBUGGING_INFO
119 extern char *dwarf2out_cfi_label ();
122 /* Option handling. */
124 /* Code model option as passed by user. */
125 char *sparc_cmodel_string;
127 enum cmodel sparc_cmodel;
129 /* Record alignment options as passed by user. */
130 char *sparc_align_loops_string;
131 char *sparc_align_jumps_string;
132 char *sparc_align_funcs_string;
134 /* Parsed values, as a power of two. */
135 int sparc_align_loops;
136 int sparc_align_jumps;
137 int sparc_align_funcs;
139 struct sparc_cpu_select sparc_select[] =
141 /* switch name, tune arch */
142 { (char *)0, "default", 1, 1 },
143 { (char *)0, "-mcpu=", 1, 1 },
144 { (char *)0, "-mtune=", 1, 0 },
148 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
149 enum processor_type sparc_cpu;
151 /* Validate and override various options, and do some machine dependent
155 sparc_override_options ()
157 static struct code_model {
162 { "medlow", CM_MEDLOW },
163 { "medmid", CM_MEDMID },
164 { "medany", CM_MEDANY },
165 { "embmedany", CM_EMBMEDANY },
168 struct code_model *cmodel;
169 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
170 static struct cpu_default {
174 /* There must be one entry here for each TARGET_CPU value. */
175 { TARGET_CPU_sparc, "cypress" },
176 { TARGET_CPU_sparclet, "tsc701" },
177 { TARGET_CPU_sparclite, "f930" },
178 { TARGET_CPU_v8, "v8" },
179 { TARGET_CPU_supersparc, "supersparc" },
180 { TARGET_CPU_v9, "v9" },
181 { TARGET_CPU_ultrasparc, "ultrasparc" },
184 struct cpu_default *def;
185 /* Table of values for -m{cpu,tune}=. */
186 static struct cpu_table {
188 enum processor_type processor;
192 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
193 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
194 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
195 /* TI TMS390Z55 supersparc */
196 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
197 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
198 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
199 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
200 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
201 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
202 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
204 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
205 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
207 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 },
210 struct cpu_table *cpu;
211 struct sparc_cpu_select *sel;
214 #ifndef SPARC_BI_ARCH
215 /* Check for unsupported architecture size. */
216 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
218 error ("%s is not supported by this configuration",
219 DEFAULT_ARCH32_P ? "-m64" : "-m32");
223 /* Code model selection. */
224 sparc_cmodel = SPARC_DEFAULT_CMODEL;
225 if (sparc_cmodel_string != NULL)
229 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
230 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
232 if (cmodel->name == NULL)
233 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
235 sparc_cmodel = cmodel->value;
238 error ("-mcmodel= is not supported on 32 bit systems");
241 fpu = TARGET_FPU; /* save current -mfpu status */
243 /* Set the default CPU. */
244 for (def = &cpu_default[0]; def->name; ++def)
245 if (def->cpu == TARGET_CPU_DEFAULT)
249 sparc_select[0].string = def->name;
251 for (sel = &sparc_select[0]; sel->name; ++sel)
255 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
256 if (! strcmp (sel->string, cpu->name))
259 sparc_cpu = cpu->processor;
263 target_flags &= ~cpu->disable;
264 target_flags |= cpu->enable;
270 error ("bad value (%s) for %s switch", sel->string, sel->name);
274 /* If -mfpu or -mno-fpu was explicitly used, don't override with
275 the processor default. */
277 target_flags = (target_flags & ~MASK_FPU) | fpu;
279 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
280 if (TARGET_V9 && TARGET_ARCH32)
281 target_flags |= MASK_DEPRECATED_V8_INSNS;
283 /* V8PLUS requires V9 */
285 target_flags &= ~MASK_V8PLUS;
287 /* Don't use stack biasing in 32 bit mode. */
289 target_flags &= ~MASK_STACK_BIAS;
291 /* Don't allow -mvis if FPU is disabled. */
293 target_flags &= ~MASK_VIS;
295 /* Validate -malign-loops= value, or provide default. */
296 if (sparc_align_loops_string)
298 sparc_align_loops = exact_log2 (atoi (sparc_align_loops_string));
299 if (sparc_align_loops < 2 || sparc_align_loops > 7)
300 fatal ("-malign-loops=%s is not between 4 and 128 or is not a power of two",
301 sparc_align_loops_string);
305 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
306 its 0. This sounds a bit kludgey. */
307 sparc_align_loops = 0;
310 /* Validate -malign-jumps= value, or provide default. */
311 if (sparc_align_jumps_string)
313 sparc_align_jumps = exact_log2 (atoi (sparc_align_jumps_string));
314 if (sparc_align_jumps < 2 || sparc_align_loops > 7)
315 fatal ("-malign-jumps=%s is not between 4 and 128 or is not a power of two",
316 sparc_align_jumps_string);
320 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
321 its 0. This sounds a bit kludgey. */
322 sparc_align_jumps = 0;
325 /* Validate -malign-functions= value, or provide default. */
326 if (sparc_align_funcs_string)
328 sparc_align_funcs = exact_log2 (atoi (sparc_align_funcs_string));
329 if (sparc_align_funcs < 2 || sparc_align_loops > 7)
330 fatal ("-malign-functions=%s is not between 4 and 128 or is not a power of two",
331 sparc_align_funcs_string);
334 sparc_align_funcs = DEFAULT_SPARC_ALIGN_FUNCS;
336 /* Validate PCC_STRUCT_RETURN. */
337 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
338 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
340 /* Do various machine dependent initializations. */
344 /* Miscellaneous utilities. */
346 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
347 or branch on register contents instructions. */
353 return (code == EQ || code == NE || code == GE || code == LT
354 || code == LE || code == GT);
358 /* Operand constraints. */
360 /* Return non-zero only if OP is a register of mode MODE,
361 or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because
362 %g0 may contain anything. */
365 reg_or_0_operand (op, mode)
367 enum machine_mode mode;
369 if (register_operand (op, mode))
373 if (op == const0_rtx)
375 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
376 && CONST_DOUBLE_HIGH (op) == 0
377 && CONST_DOUBLE_LOW (op) == 0)
379 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
380 && GET_CODE (op) == CONST_DOUBLE
381 && fp_zero_operand (op))
386 /* Nonzero if OP is a floating point value with value 0.0. */
394 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
395 return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r));
398 /* Nonzero if OP is an integer register. */
401 intreg_operand (op, mode)
403 enum machine_mode mode ATTRIBUTE_UNUSED;
405 return (register_operand (op, SImode)
406 || (TARGET_ARCH64 && register_operand (op, DImode)));
409 /* Nonzero if OP is a floating point condition code register. */
412 fcc_reg_operand (op, mode)
414 enum machine_mode mode;
416 /* This can happen when recog is called from combine. Op may be a MEM.
417 Fail instead of calling abort in this case. */
418 if (GET_CODE (op) != REG)
421 if (mode != VOIDmode && mode != GET_MODE (op))
424 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
427 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
428 if (reg_renumber == 0)
429 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
430 return REGNO_OK_FOR_CCFP_P (REGNO (op));
432 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
436 /* Nonzero if OP is an integer or floating point condition code register. */
439 icc_or_fcc_reg_operand (op, mode)
441 enum machine_mode mode;
443 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
445 if (mode != VOIDmode && mode != GET_MODE (op))
448 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
453 return fcc_reg_operand (op, mode);
456 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
458 restore_operand (op, mode)
460 enum machine_mode mode;
462 return (GET_CODE (op) == REG && GET_MODE (op) == mode
463 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
466 /* Call insn on SPARC can take a PC-relative constant address, or any regular
470 call_operand (op, mode)
472 enum machine_mode mode;
474 if (GET_CODE (op) != MEM)
477 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
481 call_operand_address (op, mode)
483 enum machine_mode mode;
485 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
488 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
489 reference and a constant. */
492 symbolic_operand (op, mode)
494 enum machine_mode mode;
496 switch (GET_CODE (op))
504 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
505 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
506 && GET_CODE (XEXP (op, 1)) == CONST_INT);
508 /* ??? This clause seems to be irrelevant. */
510 return GET_MODE (op) == mode;
517 /* Return truth value of statement that OP is a symbolic memory
518 operand of mode MODE. */
521 symbolic_memory_operand (op, mode)
523 enum machine_mode mode ATTRIBUTE_UNUSED;
525 if (GET_CODE (op) == SUBREG)
526 op = SUBREG_REG (op);
527 if (GET_CODE (op) != MEM)
530 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
531 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
534 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
537 label_ref_operand (op, mode)
539 enum machine_mode mode;
541 if (GET_CODE (op) != LABEL_REF)
543 if (GET_MODE (op) != mode)
548 /* Return 1 if the operand is an argument used in generating pic references
549 in either the medium/low or medium/anywhere code models of sparc64. */
552 sp64_medium_pic_operand (op, mode)
554 enum machine_mode mode ATTRIBUTE_UNUSED;
556 /* Check for (const (minus (symbol_ref:GOT)
557 (const (minus (label) (pc))))). */
558 if (GET_CODE (op) != CONST)
561 if (GET_CODE (op) != MINUS)
563 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
565 /* ??? Ensure symbol is GOT. */
566 if (GET_CODE (XEXP (op, 1)) != CONST)
568 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
573 /* Return 1 if the operand is a data segment reference. This includes
574 the readonly data segment, or in other words anything but the text segment.
575 This is needed in the medium/anywhere code model on v9. These values
576 are accessed with EMBMEDANY_BASE_REG. */
579 data_segment_operand (op, mode)
581 enum machine_mode mode ATTRIBUTE_UNUSED;
583 switch (GET_CODE (op))
586 return ! SYMBOL_REF_FLAG (op);
588 /* Assume canonical format of symbol + constant.
591 return data_segment_operand (XEXP (op, 0));
597 /* Return 1 if the operand is a text segment reference.
598 This is needed in the medium/anywhere code model on v9. */
601 text_segment_operand (op, mode)
603 enum machine_mode mode ATTRIBUTE_UNUSED;
605 switch (GET_CODE (op))
610 return SYMBOL_REF_FLAG (op);
612 /* Assume canonical format of symbol + constant.
615 return text_segment_operand (XEXP (op, 0));
621 /* Return 1 if the operand is either a register or a memory operand that is
625 reg_or_nonsymb_mem_operand (op, mode)
627 enum machine_mode mode;
629 if (register_operand (op, mode))
632 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
639 splittable_symbolic_memory_operand (op, mode)
641 enum machine_mode mode ATTRIBUTE_UNUSED;
643 if (GET_CODE (op) != MEM)
645 if (! symbolic_operand (XEXP (op, 0), Pmode))
651 splittable_immediate_memory_operand (op, mode)
653 enum machine_mode mode ATTRIBUTE_UNUSED;
655 if (GET_CODE (op) != MEM)
657 if (! immediate_operand (XEXP (op, 0), Pmode))
662 /* Return truth value of whether OP is EQ or NE. */
667 enum machine_mode mode ATTRIBUTE_UNUSED;
669 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
672 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
673 or LTU for non-floating-point. We handle those specially. */
676 normal_comp_operator (op, mode)
678 enum machine_mode mode ATTRIBUTE_UNUSED;
680 enum rtx_code code = GET_CODE (op);
682 if (GET_RTX_CLASS (code) != '<')
685 if (GET_MODE (XEXP (op, 0)) == CCFPmode
686 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
689 return (code != NE && code != EQ && code != GEU && code != LTU);
692 /* Return 1 if this is a comparison operator. This allows the use of
693 MATCH_OPERATOR to recognize all the branch insns. */
696 noov_compare_op (op, mode)
698 enum machine_mode mode ATTRIBUTE_UNUSED;
700 enum rtx_code code = GET_CODE (op);
702 if (GET_RTX_CLASS (code) != '<')
705 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
706 /* These are the only branches which work with CC_NOOVmode. */
707 return (code == EQ || code == NE || code == GE || code == LT);
711 /* Nonzero if OP is a comparison operator suitable for use in v9
712 conditional move or branch on register contents instructions. */
715 v9_regcmp_op (op, mode)
717 enum machine_mode mode ATTRIBUTE_UNUSED;
719 enum rtx_code code = GET_CODE (op);
721 if (GET_RTX_CLASS (code) != '<')
724 return v9_regcmp_p (code);
727 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
732 enum machine_mode mode ATTRIBUTE_UNUSED;
734 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
737 /* Return nonzero if OP is an operator of mode MODE which can set
738 the condition codes explicitly. We do not include PLUS and MINUS
739 because these require CC_NOOVmode, which we handle explicitly. */
742 cc_arithop (op, mode)
744 enum machine_mode mode ATTRIBUTE_UNUSED;
746 if (GET_CODE (op) == AND
747 || GET_CODE (op) == IOR
748 || GET_CODE (op) == XOR)
754 /* Return nonzero if OP is an operator of mode MODE which can bitwise
755 complement its second operand and set the condition codes explicitly. */
758 cc_arithopn (op, mode)
760 enum machine_mode mode ATTRIBUTE_UNUSED;
762 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
763 and (xor ... (not ...)) to (not (xor ...)). */
764 return (GET_CODE (op) == AND
765 || GET_CODE (op) == IOR);
768 /* Return true if OP is a register, or is a CONST_INT that can fit in a
769 signed 13 bit immediate field. This is an acceptable SImode operand for
770 most 3 address instructions. */
773 arith_operand (op, mode)
775 enum machine_mode mode;
778 if (register_operand (op, mode)
779 || GET_CODE (op) == CONSTANT_P_RTX)
781 if (GET_CODE (op) != CONST_INT)
783 val = INTVAL (op) & 0xffffffff;
784 return SPARC_SIMM13_P (val);
787 /* Return true if OP is a constant 4096 */
790 arith_4096_operand (op, mode)
792 enum machine_mode mode ATTRIBUTE_UNUSED;
795 if (GET_CODE (op) != CONST_INT)
797 val = INTVAL (op) & 0xffffffff;
801 /* Return true if OP is suitable as second operand for add/sub */
804 arith_add_operand (op, mode)
806 enum machine_mode mode;
808 return arith_operand (op, mode) || arith_4096_operand (op, mode);
811 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
812 immediate field of OR and XOR instructions. Used for 64-bit
813 constant formation patterns. */
815 const64_operand (op, mode)
817 enum machine_mode mode ATTRIBUTE_UNUSED;
819 return ((GET_CODE (op) == CONST_INT
820 && SPARC_SIMM13_P (INTVAL (op)))
821 #if HOST_BITS_PER_WIDE_INT != 64
822 || (GET_CODE (op) == CONST_DOUBLE
823 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
824 && (CONST_DOUBLE_HIGH (op) ==
825 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
826 (HOST_WIDE_INT)0xffffffff : 0)))
828 || GET_CODE (op) == CONSTANT_P_RTX);
831 /* The same, but only for sethi instructions. */
833 const64_high_operand (op, mode)
835 enum machine_mode mode ATTRIBUTE_UNUSED;
837 return ((GET_CODE (op) == CONST_INT
838 && (INTVAL (op) & 0xfffffc00) != 0
839 && SPARC_SETHI_P (INTVAL (op))
840 #if HOST_BITS_PER_WIDE_INT != 64
841 /* Must be positive on non-64bit host else the
842 optimizer is fooled into thinking that sethi
843 sign extends, even though it does not. */
847 || (GET_CODE (op) == CONST_DOUBLE
848 && CONST_DOUBLE_HIGH (op) == 0
849 && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
850 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
851 || GET_CODE (op) == CONSTANT_P_RTX);
854 /* Return true if OP is a register, or is a CONST_INT that can fit in a
855 signed 11 bit immediate field. This is an acceptable SImode operand for
856 the movcc instructions. */
859 arith11_operand (op, mode)
861 enum machine_mode mode;
863 return (register_operand (op, mode)
864 || GET_CODE (op) == CONSTANT_P_RTX
865 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
868 /* Return true if OP is a register, or is a CONST_INT that can fit in a
869 signed 10 bit immediate field. This is an acceptable SImode operand for
870 the movrcc instructions. */
873 arith10_operand (op, mode)
875 enum machine_mode mode;
877 return (register_operand (op, mode)
878 || GET_CODE (op) == CONSTANT_P_RTX
879 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
882 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
883 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
885 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
886 can fit in a 13 bit immediate field. This is an acceptable DImode operand
887 for most 3 address instructions. */
890 arith_double_operand (op, mode)
892 enum machine_mode mode;
894 return (register_operand (op, mode)
895 || GET_CODE (op) == CONSTANT_P_RTX
896 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
898 && GET_CODE (op) == CONST_DOUBLE
899 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
900 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
902 && GET_CODE (op) == CONST_DOUBLE
903 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
904 && ((CONST_DOUBLE_HIGH (op) == -1
905 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
906 || (CONST_DOUBLE_HIGH (op) == 0
907 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
910 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
913 arith_double_4096_operand (op, mode)
915 enum machine_mode mode ATTRIBUTE_UNUSED;
917 return (TARGET_ARCH64 &&
918 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
919 (GET_CODE (op) == CONST_DOUBLE &&
920 CONST_DOUBLE_LOW (op) == 4096 &&
921 CONST_DOUBLE_HIGH (op) == 0)));
924 /* Return true if OP is suitable as second operand for add/sub in DImode */
927 arith_double_add_operand (op, mode)
929 enum machine_mode mode;
931 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
934 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
935 can fit in an 11 bit immediate field. This is an acceptable DImode
936 operand for the movcc instructions. */
937 /* ??? Replace with arith11_operand? */
940 arith11_double_operand (op, mode)
942 enum machine_mode mode;
944 return (register_operand (op, mode)
945 || GET_CODE (op) == CONSTANT_P_RTX
946 || (GET_CODE (op) == CONST_DOUBLE
947 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
948 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
949 && ((CONST_DOUBLE_HIGH (op) == -1
950 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
951 || (CONST_DOUBLE_HIGH (op) == 0
952 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
953 || (GET_CODE (op) == CONST_INT
954 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
955 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
958 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
959 can fit in an 10 bit immediate field. This is an acceptable DImode
960 operand for the movrcc instructions. */
961 /* ??? Replace with arith10_operand? */
964 arith10_double_operand (op, mode)
966 enum machine_mode mode;
968 return (register_operand (op, mode)
969 || GET_CODE (op) == CONSTANT_P_RTX
970 || (GET_CODE (op) == CONST_DOUBLE
971 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
972 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
973 && ((CONST_DOUBLE_HIGH (op) == -1
974 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
975 || (CONST_DOUBLE_HIGH (op) == 0
976 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
977 || (GET_CODE (op) == CONST_INT
978 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
979 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
982 /* Return truth value of whether OP is a integer which fits the
983 range constraining immediate operands in most three-address insns,
984 which have a 13 bit immediate field. */
989 enum machine_mode mode ATTRIBUTE_UNUSED;
991 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
992 || GET_CODE (op) == CONSTANT_P_RTX);
996 small_int_or_double (op, mode)
998 enum machine_mode mode ATTRIBUTE_UNUSED;
1000 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1001 || (GET_CODE (op) == CONST_DOUBLE
1002 && CONST_DOUBLE_HIGH (op) == 0
1003 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1004 || GET_CODE (op) == CONSTANT_P_RTX);
1007 /* Recognize operand values for the umul instruction. That instruction sign
1008 extends immediate values just like all other sparc instructions, but
1009 interprets the extended result as an unsigned number. */
1012 uns_small_int (op, mode)
1014 enum machine_mode mode ATTRIBUTE_UNUSED;
1016 #if HOST_BITS_PER_WIDE_INT > 32
1017 /* All allowed constants will fit a CONST_INT. */
1018 return ((GET_CODE (op) == CONST_INT
1019 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1020 || (INTVAL (op) >= 0xFFFFF000
1021 && INTVAL (op) < 0x100000000)))
1022 || GET_CODE (op) == CONSTANT_P_RTX);
1024 return (((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1025 || (GET_CODE (op) == CONST_DOUBLE
1026 && CONST_DOUBLE_HIGH (op) == 0
1027 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000))
1028 || GET_CODE (op) == CONSTANT_P_RTX);
1033 uns_arith_operand (op, mode)
1035 enum machine_mode mode;
1037 return register_operand (op, mode) || uns_small_int (op, mode);
1040 /* Return truth value of statement that OP is a call-clobbered register. */
1042 clobbered_register (op, mode)
1044 enum machine_mode mode ATTRIBUTE_UNUSED;
1046 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1049 /* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns. */
1052 zero_operand (op, mode)
1054 enum machine_mode mode ATTRIBUTE_UNUSED;
1056 return (op == const0_rtx || GET_CODE (op) == CONSTANT_P_RTX);
1059 /* Return 1 if OP is a valid operand for the source of a move insn. */
1062 input_operand (op, mode)
1064 enum machine_mode mode;
1066 /* If both modes are non-void they must be the same. */
1067 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1070 /* Allow any one instruction integer constant, and all CONST_INT
1071 variants when we are working in DImode and !arch64. */
1072 if (GET_MODE_CLASS (mode) == MODE_INT
1073 && ((GET_CODE (op) == CONST_INT
1074 && ((SPARC_SETHI_P (INTVAL (op))
1076 || (INTVAL (op) >= 0)
1078 || SPARC_SIMM13_P (INTVAL (op))
1080 && ! TARGET_ARCH64)))
1082 && GET_CODE (op) == CONST_DOUBLE
1083 && ((CONST_DOUBLE_HIGH (op) == 0
1084 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1086 #if HOST_BITS_PER_WIDE_INT == 64
1087 (CONST_DOUBLE_HIGH (op) == 0
1088 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1090 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1091 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1092 && CONST_DOUBLE_HIGH (op) == 0)
1093 || (CONST_DOUBLE_HIGH (op) == -1)))
1098 /* Always match this. */
1099 if (GET_CODE (op) == CONSTANT_P_RTX)
1102 /* If !arch64 and this is a DImode const, allow it so that
1103 the splits can be generated. */
1106 && GET_CODE (op) == CONST_DOUBLE)
1109 if (register_operand (op, mode))
1112 /* If this is a SUBREG, look inside so that we handle
1113 paradoxical ones. */
1114 if (GET_CODE (op) == SUBREG)
1115 op = SUBREG_REG (op);
1117 /* Check for valid MEM forms. */
1118 if (GET_CODE (op) == MEM)
1120 rtx inside = XEXP (op, 0);
1122 if (GET_CODE (inside) == LO_SUM)
1124 /* We can't allow these because all of the splits
1125 (eventually as they trickle down into DFmode
1126 splits) require offsettable memory references. */
1128 && GET_MODE (op) == TFmode)
1131 return (register_operand (XEXP (inside, 0), Pmode)
1132 && CONSTANT_P (XEXP (inside, 1)));
1134 return memory_address_p (mode, inside);
1141 /* We know it can't be done in one insn when we get here,
1142 the movsi expander guarentees this. */
1144 sparc_emit_set_const32 (op0, op1)
1148 enum machine_mode mode = GET_MODE (op0);
1151 if (GET_CODE (op1) == CONST_INT)
1153 HOST_WIDE_INT value = INTVAL (op1);
1155 if (SPARC_SETHI_P (value)
1156 || SPARC_SIMM13_P (value))
1160 /* Full 2-insn decomposition is needed. */
1161 if (reload_in_progress || reload_completed)
1164 temp = gen_reg_rtx (mode);
1166 if (GET_CODE (op1) == CONST_INT)
1168 /* Emit them as real moves instead of a HIGH/LO_SUM,
1169 this way CSE can see everything and reuse intermediate
1170 values if it wants. */
1172 && HOST_BITS_PER_WIDE_INT != 64
1173 && (INTVAL (op1) & 0x80000000) != 0)
1175 emit_insn (gen_rtx_SET (VOIDmode,
1177 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx,
1178 INTVAL (op1) & 0xfffffc00, 0)));
1182 emit_insn (gen_rtx_SET (VOIDmode,
1184 GEN_INT (INTVAL (op1) & 0xfffffc00)));
1186 emit_insn (gen_rtx_SET (VOIDmode,
1190 GEN_INT (INTVAL (op1) & 0x3ff))));
1194 /* A symbol, emit in the traditional way. */
1195 emit_insn (gen_rtx_SET (VOIDmode,
1199 emit_insn (gen_rtx_SET (VOIDmode,
1201 gen_rtx_LO_SUM (mode,
1209 /* Sparc-v9 code-model support. */
1211 sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1216 switch (sparc_cmodel)
1219 /* The range spanned by all instructions in the object is less
1220 than 2^31 bytes (2GB) and the distance from any instruction
1221 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1222 than 2^31 bytes (2GB).
1224 The executable must be in the low 4TB of the virtual address
1227 sethi %hi(symbol), %temp
1228 or %temp, %lo(symbol), %reg */
1229 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1230 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1234 /* The range spanned by all instructions in the object is less
1235 than 2^31 bytes (2GB) and the distance from any instruction
1236 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1237 than 2^31 bytes (2GB).
1239 The executable must be in the low 16TB of the virtual address
1242 sethi %h44(symbol), %temp1
1243 or %temp1, %m44(symbol), %temp2
1244 sllx %temp2, 12, %temp3
1245 or %temp3, %l44(symbol), %reg */
1246 emit_insn (gen_seth44 (op0, op1));
1247 emit_insn (gen_setm44 (op0, op0, op1));
1248 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1249 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1250 emit_insn (gen_setl44 (op0, temp1, op1));
1254 /* The range spanned by all instructions in the object is less
1255 than 2^31 bytes (2GB) and the distance from any instruction
1256 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1257 than 2^31 bytes (2GB).
1259 The executable can be placed anywhere in the virtual address
1262 sethi %hh(symbol), %temp1
1263 sethi %lm(symbol), %temp2
1264 or %temp1, %hm(symbol), %temp3
1265 or %temp2, %lo(symbol), %temp4
1266 sllx %temp3, 32, %temp5
1267 or %temp4, %temp5, %reg */
1269 /* Getting this right wrt. reloading is really tricky.
1270 We _MUST_ have a seperate temporary at this point,
1271 if we don't barf immediately instead of generating
1276 emit_insn (gen_sethh (op0, op1));
1277 emit_insn (gen_setlm (temp1, op1));
1278 emit_insn (gen_sethm (op0, op0, op1));
1279 emit_insn (gen_rtx_SET (VOIDmode, op0,
1280 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1281 emit_insn (gen_rtx_SET (VOIDmode, op0,
1282 gen_rtx_PLUS (DImode, op0, temp1)));
1283 emit_insn (gen_setlo (op0, op0, op1));
1287 /* Old old old backwards compatibility kruft here.
1288 Essentially it is MEDLOW with a fixed 64-bit
1289 virtual base added to all data segment addresses.
1290 Text-segment stuff is computed like MEDANY, we can't
1291 reuse the code above because the relocation knobs
1294 Data segment: sethi %hi(symbol), %temp1
1295 or %temp1, %lo(symbol), %temp2
1296 add %temp2, EMBMEDANY_BASE_REG, %reg
1298 Text segment: sethi %uhi(symbol), %temp1
1299 sethi %hi(symbol), %temp2
1300 or %temp1, %ulo(symbol), %temp3
1301 or %temp2, %lo(symbol), %temp4
1302 sllx %temp3, 32, %temp5
1303 or %temp4, %temp5, %reg */
1304 if (data_segment_operand (op1, GET_MODE (op1)))
1306 emit_insn (gen_embmedany_sethi (temp1, op1));
1307 emit_insn (gen_embmedany_brsum (op0, temp1));
1308 emit_insn (gen_embmedany_losum (op0, op0, op1));
1312 /* Getting this right wrt. reloading is really tricky.
1313 We _MUST_ have a seperate temporary at this point,
1314 so we barf immediately instead of generating
1319 emit_insn (gen_embmedany_textuhi (op0, op1));
1320 emit_insn (gen_embmedany_texthi (temp1, op1));
1321 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1322 emit_insn (gen_rtx_SET (VOIDmode, op0,
1323 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1324 emit_insn (gen_rtx_SET (VOIDmode, op0,
1325 gen_rtx_PLUS (DImode, op0, temp1)));
1326 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1335 /* These avoid problems when cross compiling. If we do not
1336 go through all this hair then the optimizer will see
1337 invalid REG_EQUAL notes or in some cases none at all. */
1338 static void sparc_emit_set_safe_HIGH64 PROTO ((rtx, HOST_WIDE_INT));
1339 static rtx gen_safe_SET64 PROTO ((rtx, HOST_WIDE_INT));
1340 static rtx gen_safe_OR64 PROTO ((rtx, HOST_WIDE_INT));
1341 static rtx gen_safe_XOR64 PROTO ((rtx, HOST_WIDE_INT));
1343 #if HOST_BITS_PER_WIDE_INT == 64
1344 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
1345 #define GEN_INT64(__x) GEN_INT (__x)
1347 #define GEN_HIGHINT64(__x) \
1348 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1349 (__x) & 0xfffffc00, 0)
1350 #define GEN_INT64(__x) \
1351 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1352 (__x) & 0xffffffff, \
1353 ((__x) & 0x80000000 \
1357 /* The optimizer is not to assume anything about exactly
1358 which bits are set for a HIGH, they are unspecified.
1359 Unfortunately this leads to many missed optimizations
1360 during CSE. We mask out the non-HIGH bits, and matches
1361 a plain movdi, to alleviate this problem. */
1363 sparc_emit_set_safe_HIGH64 (dest, val)
1367 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1371 gen_safe_SET64 (dest, val)
1375 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1379 gen_safe_OR64 (src, val)
1383 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1387 gen_safe_XOR64 (src, val)
1391 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1394 /* Worker routines for 64-bit constant formation on arch64.
1395 One of the key things to be doing in these emissions is
1396 to create as many temp REGs as possible. This makes it
1397 possible for half-built constants to be used later when
1398 such values are similar to something required later on.
1399 Without doing this, the optimizer cannot see such
1402 static void sparc_emit_set_const64_quick1
1403 PROTO((rtx, rtx, unsigned HOST_WIDE_INT, int));
1406 sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1409 unsigned HOST_WIDE_INT low_bits;
1412 unsigned HOST_WIDE_INT high_bits;
1415 high_bits = (~low_bits) & 0xffffffff;
1417 high_bits = low_bits;
1419 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1422 emit_insn (gen_rtx_SET (VOIDmode, op0,
1423 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1427 /* If we are XOR'ing with -1, then we should emit a one's complement
1428 instead. This way the combiner will notice logical operations
1429 such as ANDN later on and substitute. */
1430 if ((low_bits & 0x3ff) == 0x3ff)
1432 emit_insn (gen_rtx_SET (VOIDmode, op0,
1433 gen_rtx_NOT (DImode, temp)));
1437 emit_insn (gen_rtx_SET (VOIDmode, op0,
1438 gen_safe_XOR64 (temp,
1439 (-0x400 | (low_bits & 0x3ff)))));
1444 static void sparc_emit_set_const64_quick2
1445 PROTO((rtx, rtx, unsigned HOST_WIDE_INT,
1446 unsigned HOST_WIDE_INT, int));
1449 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1452 unsigned HOST_WIDE_INT high_bits;
1453 unsigned HOST_WIDE_INT low_immediate;
1458 if ((high_bits & 0xfffffc00) != 0)
1460 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1461 if ((high_bits & ~0xfffffc00) != 0)
1462 emit_insn (gen_rtx_SET (VOIDmode, op0,
1463 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1469 emit_insn (gen_safe_SET64 (temp, high_bits));
1473 /* Now shift it up into place. */
1474 emit_insn (gen_rtx_SET (VOIDmode, op0,
1475 gen_rtx_ASHIFT (DImode, temp2,
1476 GEN_INT (shift_count))));
1478 /* If there is a low immediate part piece, finish up by
1479 putting that in as well. */
1480 if (low_immediate != 0)
1481 emit_insn (gen_rtx_SET (VOIDmode, op0,
1482 gen_safe_OR64 (op0, low_immediate)));
1485 static void sparc_emit_set_const64_longway
1486 PROTO((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1488 /* Full 64-bit constant decomposition. Even though this is the
1489 'worst' case, we still optimize a few things away. */
1491 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1494 unsigned HOST_WIDE_INT high_bits;
1495 unsigned HOST_WIDE_INT low_bits;
1499 if (reload_in_progress || reload_completed)
1502 sub_temp = gen_reg_rtx (DImode);
1504 if ((high_bits & 0xfffffc00) != 0)
1506 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1507 if ((high_bits & ~0xfffffc00) != 0)
1508 emit_insn (gen_rtx_SET (VOIDmode,
1510 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1516 emit_insn (gen_safe_SET64 (temp, high_bits));
1520 if (!reload_in_progress && !reload_completed)
1522 rtx temp2 = gen_reg_rtx (DImode);
1523 rtx temp3 = gen_reg_rtx (DImode);
1524 rtx temp4 = gen_reg_rtx (DImode);
1526 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1527 gen_rtx_ASHIFT (DImode, sub_temp,
1530 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1531 if ((low_bits & ~0xfffffc00) != 0)
1533 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1534 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1535 emit_insn (gen_rtx_SET (VOIDmode, op0,
1536 gen_rtx_PLUS (DImode, temp4, temp3)));
1540 emit_insn (gen_rtx_SET (VOIDmode, op0,
1541 gen_rtx_PLUS (DImode, temp4, temp2)));
1546 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1547 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1548 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1551 /* We are in the middle of reload, so this is really
1552 painful. However we do still make an attempt to
1553 avoid emitting truly stupid code. */
1554 if (low1 != const0_rtx)
1556 emit_insn (gen_rtx_SET (VOIDmode, op0,
1557 gen_rtx_ASHIFT (DImode, sub_temp,
1558 GEN_INT (to_shift))));
1559 emit_insn (gen_rtx_SET (VOIDmode, op0,
1560 gen_rtx_IOR (DImode, op0, low1)));
1568 if (low2 != const0_rtx)
1570 emit_insn (gen_rtx_SET (VOIDmode, op0,
1571 gen_rtx_ASHIFT (DImode, sub_temp,
1572 GEN_INT (to_shift))));
1573 emit_insn (gen_rtx_SET (VOIDmode, op0,
1574 gen_rtx_IOR (DImode, op0, low2)));
1582 emit_insn (gen_rtx_SET (VOIDmode, op0,
1583 gen_rtx_ASHIFT (DImode, sub_temp,
1584 GEN_INT (to_shift))));
1585 if (low3 != const0_rtx)
1586 emit_insn (gen_rtx_SET (VOIDmode, op0,
1587 gen_rtx_IOR (DImode, op0, low3)));
1592 /* Analyze a 64-bit constant for certain properties. */
1593 static void analyze_64bit_constant
1594 PROTO((unsigned HOST_WIDE_INT,
1595 unsigned HOST_WIDE_INT,
1596 int *, int *, int *));
1599 analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
1600 unsigned HOST_WIDE_INT high_bits, low_bits;
1601 int *hbsp, *lbsp, *abbasp;
1603 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1606 lowest_bit_set = highest_bit_set = -1;
1610 if ((lowest_bit_set == -1)
1611 && ((low_bits >> i) & 1))
1613 if ((highest_bit_set == -1)
1614 && ((high_bits >> (32 - i - 1)) & 1))
1615 highest_bit_set = (64 - i - 1);
1618 && ((highest_bit_set == -1)
1619 || (lowest_bit_set == -1)));
1625 if ((lowest_bit_set == -1)
1626 && ((high_bits >> i) & 1))
1627 lowest_bit_set = i + 32;
1628 if ((highest_bit_set == -1)
1629 && ((low_bits >> (32 - i - 1)) & 1))
1630 highest_bit_set = 32 - i - 1;
1633 && ((highest_bit_set == -1)
1634 || (lowest_bit_set == -1)));
1636 /* If there are no bits set this should have gone out
1637 as one instruction! */
1638 if (lowest_bit_set == -1
1639 || highest_bit_set == -1)
1641 all_bits_between_are_set = 1;
1642 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1646 if ((low_bits & (1 << i)) != 0)
1651 if ((high_bits & (1 << (i - 32))) != 0)
1654 all_bits_between_are_set = 0;
1657 *hbsp = highest_bit_set;
1658 *lbsp = lowest_bit_set;
1659 *abbasp = all_bits_between_are_set;
1662 static int const64_is_2insns
1663 PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1666 const64_is_2insns (high_bits, low_bits)
1667 unsigned HOST_WIDE_INT high_bits, low_bits;
1669 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1672 || high_bits == 0xffffffff)
1675 analyze_64bit_constant (high_bits, low_bits,
1676 &highest_bit_set, &lowest_bit_set,
1677 &all_bits_between_are_set);
1679 if ((highest_bit_set == 63
1680 || lowest_bit_set == 0)
1681 && all_bits_between_are_set != 0)
1684 if ((highest_bit_set - lowest_bit_set) < 21)
1690 static unsigned HOST_WIDE_INT create_simple_focus_bits
1691 PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
1694 static unsigned HOST_WIDE_INT
1695 create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
1696 unsigned HOST_WIDE_INT high_bits, low_bits;
1697 int lowest_bit_set, shift;
1699 HOST_WIDE_INT hi, lo;
1701 if (lowest_bit_set < 32)
1703 lo = (low_bits >> lowest_bit_set) << shift;
1704 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1709 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1716 /* Here we are sure to be arch64 and this is an integer constant
1717 being loaded into a register. Emit the most efficient
1718 insn sequence possible. Detection of all the 1-insn cases
1719 has been done already. */
1721 sparc_emit_set_const64 (op0, op1)
1725 unsigned HOST_WIDE_INT high_bits, low_bits;
1726 int lowest_bit_set, highest_bit_set;
1727 int all_bits_between_are_set;
1730 /* Sanity check that we know what we are working with. */
1732 || GET_CODE (op0) != REG
1733 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1734 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1737 if (reload_in_progress || reload_completed)
1740 temp = gen_reg_rtx (DImode);
1742 if (GET_CODE (op1) != CONST_DOUBLE
1743 && GET_CODE (op1) != CONST_INT)
1745 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1749 if (GET_CODE (op1) == CONST_DOUBLE)
1751 #if HOST_BITS_PER_WIDE_INT == 64
1752 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1753 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1755 high_bits = CONST_DOUBLE_HIGH (op1);
1756 low_bits = CONST_DOUBLE_LOW (op1);
1761 #if HOST_BITS_PER_WIDE_INT == 64
1762 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1763 low_bits = (INTVAL (op1) & 0xffffffff);
1765 high_bits = ((INTVAL (op1) < 0) ?
1768 low_bits = INTVAL (op1);
1772 /* low_bits bits 0 --> 31
1773 high_bits bits 32 --> 63 */
1775 analyze_64bit_constant (high_bits, low_bits,
1776 &highest_bit_set, &lowest_bit_set,
1777 &all_bits_between_are_set);
1779 /* First try for a 2-insn sequence. */
1781 /* These situations are preferred because the optimizer can
1782 * do more things with them:
1784 * sllx %reg, shift, %reg
1786 * srlx %reg, shift, %reg
1787 * 3) mov some_small_const, %reg
1788 * sllx %reg, shift, %reg
1790 if (((highest_bit_set == 63
1791 || lowest_bit_set == 0)
1792 && all_bits_between_are_set != 0)
1793 || ((highest_bit_set - lowest_bit_set) < 12))
1795 HOST_WIDE_INT the_const = -1;
1796 int shift = lowest_bit_set;
1798 if ((highest_bit_set != 63
1799 && lowest_bit_set != 0)
1800 || all_bits_between_are_set == 0)
1803 create_simple_focus_bits (high_bits, low_bits,
1806 else if (lowest_bit_set == 0)
1807 shift = -(63 - highest_bit_set);
1809 if (! SPARC_SIMM13_P (the_const))
1812 emit_insn (gen_safe_SET64 (temp, the_const));
1814 emit_insn (gen_rtx_SET (VOIDmode,
1816 gen_rtx_ASHIFT (DImode,
1820 emit_insn (gen_rtx_SET (VOIDmode,
1822 gen_rtx_LSHIFTRT (DImode,
1824 GEN_INT (-shift))));
1830 /* Now a range of 22 or less bits set somewhere.
1831 * 1) sethi %hi(focus_bits), %reg
1832 * sllx %reg, shift, %reg
1833 * 2) sethi %hi(focus_bits), %reg
1834 * srlx %reg, shift, %reg
1836 if ((highest_bit_set - lowest_bit_set) < 21)
1838 unsigned HOST_WIDE_INT focus_bits =
1839 create_simple_focus_bits (high_bits, low_bits,
1840 lowest_bit_set, 10);
1842 if (! SPARC_SETHI_P (focus_bits))
1845 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
1847 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1848 if (lowest_bit_set < 10)
1849 emit_insn (gen_rtx_SET (VOIDmode,
1851 gen_rtx_LSHIFTRT (DImode, temp,
1852 GEN_INT (10 - lowest_bit_set))));
1853 else if (lowest_bit_set > 10)
1854 emit_insn (gen_rtx_SET (VOIDmode,
1856 gen_rtx_ASHIFT (DImode, temp,
1857 GEN_INT (lowest_bit_set - 10))));
1863 /* 1) sethi %hi(low_bits), %reg
1864 * or %reg, %lo(low_bits), %reg
1865 * 2) sethi %hi(~low_bits), %reg
1866 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1869 || high_bits == 0xffffffff)
1871 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1872 (high_bits == 0xffffffff));
1876 /* Now, try 3-insn sequences. */
1878 /* 1) sethi %hi(high_bits), %reg
1879 * or %reg, %lo(high_bits), %reg
1880 * sllx %reg, 32, %reg
1884 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
1888 /* We may be able to do something quick
1889 when the constant is negated, so try that. */
1890 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1891 (~low_bits) & 0xfffffc00))
1893 /* NOTE: The trailing bits get XOR'd so we need the
1894 non-negated bits, not the negated ones. */
1895 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
1897 if ((((~high_bits) & 0xffffffff) == 0
1898 && ((~low_bits) & 0x80000000) == 0)
1899 || (((~high_bits) & 0xffffffff) == 0xffffffff
1900 && ((~low_bits) & 0x80000000) != 0))
1902 int fast_int = (~low_bits & 0xffffffff);
1904 if ((SPARC_SETHI_P (fast_int)
1905 && (~high_bits & 0xffffffff) == 0)
1906 || SPARC_SIMM13_P (fast_int))
1907 emit_insn (gen_safe_SET64 (temp, fast_int));
1909 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
1914 #if HOST_BITS_PER_WIDE_INT == 64
1915 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
1916 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
1918 negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx,
1919 (~low_bits) & 0xfffffc00,
1920 (~high_bits) & 0xffffffff);
1922 sparc_emit_set_const64 (temp, negated_const);
1925 /* If we are XOR'ing with -1, then we should emit a one's complement
1926 instead. This way the combiner will notice logical operations
1927 such as ANDN later on and substitute. */
1928 if (trailing_bits == 0x3ff)
1930 emit_insn (gen_rtx_SET (VOIDmode, op0,
1931 gen_rtx_NOT (DImode, temp)));
1935 emit_insn (gen_rtx_SET (VOIDmode,
1937 gen_safe_XOR64 (temp,
1938 (-0x400 | trailing_bits))));
1943 /* 1) sethi %hi(xxx), %reg
1944 * or %reg, %lo(xxx), %reg
1945 * sllx %reg, yyy, %reg
1947 * ??? This is just a generalized version of the low_bits==0
1948 * thing above, FIXME...
1950 if ((highest_bit_set - lowest_bit_set) < 32)
1952 unsigned HOST_WIDE_INT focus_bits =
1953 create_simple_focus_bits (high_bits, low_bits,
1956 /* We can't get here in this state. */
1957 if (highest_bit_set < 32
1958 || lowest_bit_set >= 32)
1961 /* So what we know is that the set bits straddle the
1962 middle of the 64-bit word. */
1963 sparc_emit_set_const64_quick2 (op0, temp,
1969 /* 1) sethi %hi(high_bits), %reg
1970 * or %reg, %lo(high_bits), %reg
1971 * sllx %reg, 32, %reg
1972 * or %reg, low_bits, %reg
1974 if (SPARC_SIMM13_P(low_bits)
1975 && ((int)low_bits > 0))
1977 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
1981 /* The easiest way when all else fails, is full decomposition. */
1983 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
1984 high_bits, low_bits, ~high_bits, ~low_bits);
1986 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
1989 /* X and Y are two things to compare using CODE. Emit the compare insn and
1990 return the rtx for the cc reg in the proper mode. */
1993 gen_compare_reg (code, x, y)
1997 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2000 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2001 fcc regs (cse can't tell they're really call clobbered regs and will
2002 remove a duplicate comparison even if there is an intervening function
2003 call - it will then try to reload the cc reg via an int reg which is why
2004 we need the movcc patterns). It is possible to provide the movcc
2005 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2006 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2007 to tell cse that CCFPE mode registers (even pseudos) are call
2010 /* ??? This is an experiment. Rather than making changes to cse which may
2011 or may not be easy/clean, we do our own cse. This is possible because
2012 we will generate hard registers. Cse knows they're call clobbered (it
2013 doesn't know the same thing about pseudos). If we guess wrong, no big
2014 deal, but if we win, great! */
2016 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2017 #if 1 /* experiment */
2020 /* We cycle through the registers to ensure they're all exercised. */
2021 static int next_fcc_reg = 0;
2022 /* Previous x,y for each fcc reg. */
2023 static rtx prev_args[4][2];
2025 /* Scan prev_args for x,y. */
2026 for (reg = 0; reg < 4; reg++)
2027 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2032 prev_args[reg][0] = x;
2033 prev_args[reg][1] = y;
2034 next_fcc_reg = (next_fcc_reg + 1) & 3;
2036 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2039 cc_reg = gen_reg_rtx (mode);
2040 #endif /* ! experiment */
2041 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2042 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2044 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2046 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2047 gen_rtx_COMPARE (mode, x, y)));
2052 /* This function is used for v9 only.
2053 CODE is the code for an Scc's comparison.
2054 OPERANDS[0] is the target of the Scc insn.
2055 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2056 been generated yet).
2058 This function is needed to turn
2061 (gt (reg:CCX 100 %icc)
2065 (gt:DI (reg:CCX 100 %icc)
2068 IE: The instruction recognizer needs to see the mode of the comparison to
2069 find the right instruction. We could use "gt:DI" right in the
2070 define_expand, but leaving it out allows us to handle DI, SI, etc.
2072 We refer to the global sparc compare operands sparc_compare_op0 and
2073 sparc_compare_op1. */
2076 gen_v9_scc (compare_code, operands)
2077 enum rtx_code compare_code;
2078 register rtx *operands;
2083 && (GET_MODE (sparc_compare_op0) == DImode
2084 || GET_MODE (operands[0]) == DImode))
2087 /* Handle the case where operands[0] == sparc_compare_op0.
2088 We "early clobber" the result. */
2089 if (REGNO (operands[0]) == REGNO (sparc_compare_op0))
2091 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2092 emit_move_insn (op0, sparc_compare_op0);
2095 op0 = sparc_compare_op0;
2096 /* For consistency in the following. */
2097 op1 = sparc_compare_op1;
2099 /* Try to use the movrCC insns. */
2101 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2102 && op1 == const0_rtx
2103 && v9_regcmp_p (compare_code))
2105 /* Special case for op0 != 0. This can be done with one instruction if
2106 operands[0] == sparc_compare_op0. We don't assume they are equal
2109 if (compare_code == NE
2110 && GET_MODE (operands[0]) == DImode
2111 && GET_MODE (op0) == DImode)
2113 emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0));
2114 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2115 gen_rtx_IF_THEN_ELSE (DImode,
2116 gen_rtx_fmt_ee (compare_code, DImode,
2123 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2124 if (GET_MODE (op0) != DImode)
2126 temp = gen_reg_rtx (DImode);
2127 convert_move (temp, op0, 0);
2131 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2132 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2133 gen_rtx_fmt_ee (compare_code, DImode,
2141 operands[1] = gen_compare_reg (compare_code, op0, op1);
2143 switch (GET_MODE (operands[1]))
2153 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2154 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2155 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2156 gen_rtx_fmt_ee (compare_code,
2157 GET_MODE (operands[1]),
2158 operands[1], const0_rtx),
2159 const1_rtx, operands[0])));
2164 /* Emit a conditional jump insn for the v9 architecture using comparison code
2165 CODE and jump target LABEL.
2166 This function exists to take advantage of the v9 brxx insns. */
2169 emit_v9_brxx_insn (code, op0, label)
2173 emit_jump_insn (gen_rtx_SET (VOIDmode,
2175 gen_rtx_IF_THEN_ELSE (VOIDmode,
2176 gen_rtx_fmt_ee (code, GET_MODE (op0),
2178 gen_rtx_LABEL_REF (VOIDmode, label),
2182 /* Return nonzero if a return peephole merging return with
2183 setting of output register is ok. */
2185 leaf_return_peephole_ok ()
2187 return (actual_fsize == 0);
2190 /* Return nonzero if TRIAL can go into the function epilogue's
2191 delay slot. SLOT is the slot we are trying to fill. */
2194 eligible_for_epilogue_delay (trial, slot)
2203 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2206 if (get_attr_length (trial) != 1)
2209 /* If %g0 is live, there are lots of things we can't handle.
2210 Rather than trying to find them all now, let's punt and only
2211 optimize things as necessary. */
2215 /* In the case of a true leaf function, anything can go into the delay slot.
2216 A delay slot only exists however if the frame size is zero, otherwise
2217 we will put an insn to adjust the stack after the return. */
2220 if (leaf_return_peephole_ok ())
2221 return ((get_attr_in_uncond_branch_delay (trial)
2222 == IN_BRANCH_DELAY_TRUE));
2226 /* If only trivial `restore' insns work, nothing can go in the
2228 else if (TARGET_BROKEN_SAVERESTORE)
2231 pat = PATTERN (trial);
2233 /* Otherwise, only operations which can be done in tandem with
2234 a `restore' insn can go into the delay slot. */
2235 if (GET_CODE (SET_DEST (pat)) != REG
2236 || REGNO (SET_DEST (pat)) >= 32
2237 || REGNO (SET_DEST (pat)) < 24)
2240 /* The set of insns matched here must agree precisely with the set of
2241 patterns paired with a RETURN in sparc.md. */
2243 src = SET_SRC (pat);
2245 /* This matches "*return_[qhs]i". */
2246 if (arith_operand (src, GET_MODE (src)))
2247 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2249 /* This matches "*return_di". */
2250 else if (arith_double_operand (src, GET_MODE (src)))
2251 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2253 /* This matches "*return_sf_no_fpu". */
2254 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2255 && register_operand (src, SFmode))
2258 /* This matches "*return_addsi". */
2259 else if (GET_CODE (src) == PLUS
2260 && arith_operand (XEXP (src, 0), SImode)
2261 && arith_operand (XEXP (src, 1), SImode)
2262 && (register_operand (XEXP (src, 0), SImode)
2263 || register_operand (XEXP (src, 1), SImode)))
2266 /* This matches "*return_adddi". */
2267 else if (GET_CODE (src) == PLUS
2268 && arith_double_operand (XEXP (src, 0), DImode)
2269 && arith_double_operand (XEXP (src, 1), DImode)
2270 && (register_operand (XEXP (src, 0), DImode)
2271 || register_operand (XEXP (src, 1), DImode)))
2278 check_return_regs (x)
2281 switch (GET_CODE (x))
2284 return IN_OR_GLOBAL_P (x);
2299 if (check_return_regs (XEXP (x, 1)) == 0)
2304 return check_return_regs (XEXP (x, 0));
2312 /* Return 1 if TRIAL references only in and global registers. */
2314 eligible_for_return_delay (trial)
2317 if (GET_CODE (PATTERN (trial)) != SET)
2320 return check_return_regs (PATTERN (trial));
2324 short_branch (uid1, uid2)
2327 unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2];
2328 if (delta + 1024 < 2048)
2330 /* warning ("long branch, distance %d", delta); */
2334 /* Return non-zero if REG is not used after INSN.
2335 We assume REG is a reload reg, and therefore does
2336 not live past labels or calls or jumps. */
2338 reg_unused_after (reg, insn)
2342 enum rtx_code code, prev_code = UNKNOWN;
2344 while ((insn = NEXT_INSN (insn)))
2346 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2349 code = GET_CODE (insn);
2350 if (GET_CODE (insn) == CODE_LABEL)
2353 if (GET_RTX_CLASS (code) == 'i')
2355 rtx set = single_set (insn);
2356 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2359 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2361 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2369 /* The table we use to reference PIC data. */
2370 static rtx global_offset_table;
2372 /* The function we use to get at it. */
2373 static rtx get_pc_symbol;
2374 static char get_pc_symbol_name[256];
2376 /* Ensure that we are not using patterns that are not OK with PIC. */
2385 if (GET_CODE (recog_operand[i]) == SYMBOL_REF
2386 || (GET_CODE (recog_operand[i]) == CONST
2387 && ! (GET_CODE (XEXP (recog_operand[i], 0)) == MINUS
2388 && (XEXP (XEXP (recog_operand[i], 0), 0)
2389 == global_offset_table)
2390 && (GET_CODE (XEXP (XEXP (recog_operand[i], 0), 1))
2399 /* Return true if X is an address which needs a temporary register when
2400 reloaded while generating PIC code. */
2403 pic_address_needs_scratch (x)
2406 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2407 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2408 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2409 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2410 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2416 /* Legitimize PIC addresses. If the address is already position-independent,
2417 we return ORIG. Newly generated position-independent addresses go into a
2418 reg. This is REG if non zero, otherwise we allocate register(s) as
2422 legitimize_pic_address (orig, mode, reg)
2424 enum machine_mode mode ATTRIBUTE_UNUSED;
2427 if (GET_CODE (orig) == SYMBOL_REF)
2429 rtx pic_ref, address;
2434 if (reload_in_progress || reload_completed)
2437 reg = gen_reg_rtx (Pmode);
2442 /* If not during reload, allocate another temp reg here for loading
2443 in the address, so that these instructions can be optimized
2445 rtx temp_reg = ((reload_in_progress || reload_completed)
2446 ? reg : gen_reg_rtx (Pmode));
2448 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
2449 won't get confused into thinking that these two instructions
2450 are loading in the true address of the symbol. If in the
2451 future a PIC rtx exists, that should be used instead. */
2452 if (Pmode == SImode)
2454 emit_insn (gen_movsi_high_pic (temp_reg, orig));
2455 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
2459 emit_insn (gen_movdi_high_pic (temp_reg, orig));
2460 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
2467 pic_ref = gen_rtx_MEM (Pmode,
2468 gen_rtx_PLUS (Pmode,
2469 pic_offset_table_rtx, address));
2470 current_function_uses_pic_offset_table = 1;
2471 RTX_UNCHANGING_P (pic_ref) = 1;
2472 insn = emit_move_insn (reg, pic_ref);
2473 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2475 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2479 else if (GET_CODE (orig) == CONST)
2483 if (GET_CODE (XEXP (orig, 0)) == PLUS
2484 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2489 if (reload_in_progress || reload_completed)
2492 reg = gen_reg_rtx (Pmode);
2495 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2497 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2498 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2499 base == reg ? 0 : reg);
2504 if (GET_CODE (offset) == CONST_INT)
2506 if (SMALL_INT (offset))
2507 return plus_constant_for_output (base, INTVAL (offset));
2508 else if (! reload_in_progress && ! reload_completed)
2509 offset = force_reg (Pmode, offset);
2511 /* If we reach here, then something is seriously wrong. */
2514 return gen_rtx_PLUS (Pmode, base, offset);
2516 else if (GET_CODE (orig) == LABEL_REF)
2517 /* ??? Why do we do this? */
2518 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
2519 the register is live instead, in case it is eliminated. */
2520 current_function_uses_pic_offset_table = 1;
2525 /* Return the RTX for insns to set the PIC register. */
2533 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
2535 seq = gen_sequence ();
2541 /* Emit special PIC prologues and epilogues. */
2546 /* Labels to get the PC in the prologue of this function. */
2547 int orig_flag_pic = flag_pic;
2550 if (current_function_uses_pic_offset_table == 0)
2556 /* If we havn't emitted the special get_pc helper function, do so now. */
2557 if (get_pc_symbol_name[0] == 0)
2559 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
2562 ASM_OUTPUT_ALIGN (asm_out_file, 3);
2563 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0);
2564 fputs ("\tretl\n\tadd %o7,%l7,%l7\n", asm_out_file);
2567 /* Initialize every time through, since we can't easily
2568 know this to be permanent. */
2569 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2570 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
2573 emit_insn_after (pic_setup_code (), get_insns ());
2575 /* Insert the code in each nonlocal goto receiver.
2576 If you make changes here or to the nonlocal_goto_receiver
2577 pattern, make sure the unspec_volatile numbers still
2579 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2580 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
2581 && XINT (PATTERN (insn), 1) == 5)
2582 emit_insn_after (pic_setup_code (), insn);
2584 flag_pic = orig_flag_pic;
2586 /* Need to emit this whether or not we obey regdecls,
2587 since setjmp/longjmp can cause life info to screw up.
2588 ??? In the case where we don't obey regdecls, this is not sufficient
2589 since we may not fall out the bottom. */
2590 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2593 /* Return 1 if RTX is a MEM which is known to be aligned to at
2594 least an 8 byte boundary. */
2597 mem_min_alignment (mem, desired)
2601 rtx addr, base, offset;
2603 /* If it's not a MEM we can't accept it. */
2604 if (GET_CODE (mem) != MEM)
2607 addr = XEXP (mem, 0);
2608 base = offset = NULL_RTX;
2609 if (GET_CODE (addr) == PLUS)
2611 if (GET_CODE (XEXP (addr, 0)) == REG)
2613 base = XEXP (addr, 0);
2615 /* What we are saying here is that if the base
2616 REG is aligned properly, the compiler will make
2617 sure any REG based index upon it will be so
2619 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2620 offset = XEXP (addr, 1);
2622 offset = const0_rtx;
2625 else if (GET_CODE (addr) == REG)
2628 offset = const0_rtx;
2631 if (base != NULL_RTX)
2633 int regno = REGNO (base);
2635 if (regno != FRAME_POINTER_REGNUM
2636 && regno != STACK_POINTER_REGNUM)
2638 /* Check if the compiler has recorded some information
2639 about the alignment of the base REG. If reload has
2640 completed, we already matched with proper alignments. */
2641 if (((regno_pointer_align != NULL
2642 && REGNO_POINTER_ALIGN (regno) >= desired)
2643 || reload_completed)
2644 && ((INTVAL (offset) & (desired - 1)) == 0))
2649 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
2653 else if (! TARGET_UNALIGNED_DOUBLES
2654 || CONSTANT_P (addr)
2655 || GET_CODE (addr) == LO_SUM)
2657 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
2658 is true, in which case we can only assume that an access is aligned if
2659 it is to a constant address, or the address involves a LO_SUM. */
2663 /* An obviously unaligned address. */
2668 /* Vectors to keep interesting information about registers where it can easily
2669 be got. We use to use the actual mode value as the bit number, but there
2670 are more than 32 modes now. Instead we use two tables: one indexed by
2671 hard register number, and one indexed by mode. */
2673 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2674 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2675 mapped into one sparc_mode_class mode. */
2677 enum sparc_mode_class {
2678 S_MODE, D_MODE, T_MODE, O_MODE,
2679 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
2683 /* Modes for single-word and smaller quantities. */
2684 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2686 /* Modes for double-word and smaller quantities. */
2687 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2689 /* Modes for quad-word and smaller quantities. */
2690 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2692 /* Modes for single-float quantities. We must allow any single word or
2693 smaller quantity. This is because the fix/float conversion instructions
2694 take integer inputs/outputs from the float registers. */
2695 #define SF_MODES (S_MODES)
2697 /* Modes for double-float and smaller quantities. */
2698 #define DF_MODES (S_MODES | D_MODES)
2700 #define DF_MODES64 DF_MODES
2702 /* Modes for double-float only quantities. */
2703 #define DF_ONLY_MODES ((1 << (int) DF_MODE) | (1 << (int) D_MODE))
2705 /* Modes for double-float and larger quantities. */
2706 #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES)
2708 /* Modes for quad-float only quantities. */
2709 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2711 /* Modes for quad-float and smaller quantities. */
2712 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2714 #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES)
2716 /* Modes for condition codes. */
2717 #define CC_MODES (1 << (int) CC_MODE)
2718 #define CCFP_MODES (1 << (int) CCFP_MODE)
2720 /* Value is 1 if register/mode pair is acceptable on sparc.
2721 The funny mixture of D and T modes is because integer operations
2722 do not specially operate on tetra quantities, so non-quad-aligned
2723 registers can hold quadword quantities (except %o4 and %i4 because
2724 they cross fixed registers). */
2726 /* This points to either the 32 bit or the 64 bit version. */
2727 int *hard_regno_mode_classes;
2729 static int hard_32bit_mode_classes[] = {
2730 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2731 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2732 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2733 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2735 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2736 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2737 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2738 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2740 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2741 and none can hold SFmode/SImode values. */
2742 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2743 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2744 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2745 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2748 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2754 static int hard_64bit_mode_classes[] = {
2755 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2756 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2757 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2758 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2760 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2761 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2762 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2763 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2765 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2766 and none can hold SFmode/SImode values. */
2767 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2768 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2769 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2770 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2773 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2779 int sparc_mode_class [NUM_MACHINE_MODES];
2781 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
2788 for (i = 0; i < NUM_MACHINE_MODES; i++)
2790 switch (GET_MODE_CLASS (i))
2793 case MODE_PARTIAL_INT:
2794 case MODE_COMPLEX_INT:
2795 if (GET_MODE_SIZE (i) <= 4)
2796 sparc_mode_class[i] = 1 << (int) S_MODE;
2797 else if (GET_MODE_SIZE (i) == 8)
2798 sparc_mode_class[i] = 1 << (int) D_MODE;
2799 else if (GET_MODE_SIZE (i) == 16)
2800 sparc_mode_class[i] = 1 << (int) T_MODE;
2801 else if (GET_MODE_SIZE (i) == 32)
2802 sparc_mode_class[i] = 1 << (int) O_MODE;
2804 sparc_mode_class[i] = 0;
2807 case MODE_COMPLEX_FLOAT:
2808 if (GET_MODE_SIZE (i) <= 4)
2809 sparc_mode_class[i] = 1 << (int) SF_MODE;
2810 else if (GET_MODE_SIZE (i) == 8)
2811 sparc_mode_class[i] = 1 << (int) DF_MODE;
2812 else if (GET_MODE_SIZE (i) == 16)
2813 sparc_mode_class[i] = 1 << (int) TF_MODE;
2814 else if (GET_MODE_SIZE (i) == 32)
2815 sparc_mode_class[i] = 1 << (int) OF_MODE;
2817 sparc_mode_class[i] = 0;
2821 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
2822 we must explicitly check for them here. */
2823 if (i == (int) CCFPmode || i == (int) CCFPEmode)
2824 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
2825 else if (i == (int) CCmode || i == (int) CC_NOOVmode
2826 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
2827 sparc_mode_class[i] = 1 << (int) CC_MODE;
2829 sparc_mode_class[i] = 0;
2835 hard_regno_mode_classes = hard_64bit_mode_classes;
2837 hard_regno_mode_classes = hard_32bit_mode_classes;
2839 /* Initialize the array used by REGNO_REG_CLASS. */
2840 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2842 if (i < 16 && TARGET_V8PLUS)
2843 sparc_regno_reg_class[i] = I64_REGS;
2845 sparc_regno_reg_class[i] = GENERAL_REGS;
2847 sparc_regno_reg_class[i] = FP_REGS;
2849 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
2851 sparc_regno_reg_class[i] = FPCC_REGS;
2853 sparc_regno_reg_class[i] = NO_REGS;
2857 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
2858 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2859 v9 int regs as it simplifies the code. */
2862 save_regs (file, low, high, base, offset, n_regs, real_offset)
2872 if (TARGET_ARCH64 && high <= 32)
2874 for (i = low; i < high; i++)
2876 if (regs_ever_live[i] && ! call_used_regs[i])
2878 fprintf (file, "\tstx\t%s, [%s+%d]\n",
2879 reg_names[i], base, offset + 4 * n_regs);
2880 if (dwarf2out_do_frame ())
2881 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
2888 for (i = low; i < high; i += 2)
2890 if (regs_ever_live[i] && ! call_used_regs[i])
2892 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2894 fprintf (file, "\tstd\t%s, [%s+%d]\n",
2895 reg_names[i], base, offset + 4 * n_regs);
2896 if (dwarf2out_do_frame ())
2898 char *l = dwarf2out_cfi_label ();
2899 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
2900 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
2906 fprintf (file, "\tst\t%s, [%s+%d]\n",
2907 reg_names[i], base, offset + 4 * n_regs);
2908 if (dwarf2out_do_frame ())
2909 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
2915 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2917 fprintf (file, "\tst\t%s, [%s+%d]\n",
2918 reg_names[i+1], base, offset + 4 * n_regs + 4);
2919 if (dwarf2out_do_frame ())
2920 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
2929 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
2931 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2932 v9 int regs as it simplifies the code. */
2935 restore_regs (file, low, high, base, offset, n_regs)
2944 if (TARGET_ARCH64 && high <= 32)
2946 for (i = low; i < high; i++)
2948 if (regs_ever_live[i] && ! call_used_regs[i])
2949 fprintf (file, "\tldx\t[%s+%d], %s\n",
2950 base, offset + 4 * n_regs, reg_names[i]),
2956 for (i = low; i < high; i += 2)
2958 if (regs_ever_live[i] && ! call_used_regs[i])
2959 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2960 fprintf (file, "\tldd\t[%s+%d], %s\n",
2961 base, offset + 4 * n_regs, reg_names[i]),
2964 fprintf (file, "\tld\t[%s+%d],%s\n",
2965 base, offset + 4 * n_regs, reg_names[i]),
2967 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2968 fprintf (file, "\tld\t[%s+%d],%s\n",
2969 base, offset + 4 * n_regs + 4, reg_names[i+1]),
2976 /* Static variables we want to share between prologue and epilogue. */
2978 /* Number of live general or floating point registers needed to be saved
2979 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
2980 static int num_gfregs;
2982 /* Compute the frame size required by the function. This function is called
2983 during the reload pass and also by output_function_prologue(). */
2986 compute_frame_size (size, leaf_function)
2991 int outgoing_args_size = (current_function_outgoing_args_size
2992 + REG_PARM_STACK_SPACE (current_function_decl));
2994 if (TARGET_EPILOGUE)
2996 /* N_REGS is the number of 4-byte regs saved thus far. This applies
2997 even to v9 int regs to be consistent with save_regs/restore_regs. */
3001 for (i = 0; i < 8; i++)
3002 if (regs_ever_live[i] && ! call_used_regs[i])
3007 for (i = 0; i < 8; i += 2)
3008 if ((regs_ever_live[i] && ! call_used_regs[i])
3009 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3013 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3014 if ((regs_ever_live[i] && ! call_used_regs[i])
3015 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3019 /* Set up values for use in `function_epilogue'. */
3020 num_gfregs = n_regs;
3022 if (leaf_function && n_regs == 0
3023 && size == 0 && current_function_outgoing_args_size == 0)
3025 actual_fsize = apparent_fsize = 0;
3029 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3030 The stack bias (if any) is taken out to undo its effects. */
3031 apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8;
3032 apparent_fsize += n_regs * 4;
3033 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3036 /* Make sure nothing can clobber our register windows.
3037 If a SAVE must be done, or there is a stack-local variable,
3038 the register window area must be allocated.
3039 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3040 if (leaf_function == 0 || size > 0)
3041 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3043 return SPARC_STACK_ALIGN (actual_fsize);
3046 /* Build a (32 bit) big number in a register. */
3047 /* ??? We may be able to use the set macro here too. */
3050 build_big_number (file, num, reg)
3055 if (num >= 0 || ! TARGET_ARCH64)
3057 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
3058 if ((num & 0x3ff) != 0)
3059 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
3061 else /* num < 0 && TARGET_ARCH64 */
3063 /* Sethi does not sign extend, so we must use a little trickery
3064 to use it for negative numbers. Invert the constant before
3065 loading it in, then use xor immediate to invert the loaded bits
3066 (along with the upper 32 bits) to the desired constant. This
3067 works because the sethi and immediate fields overlap. */
3070 int low = -0x400 + (asize & 0x3FF);
3072 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3073 inv, reg, reg, low, reg);
3077 /* Output code for the function prologue. */
3080 output_function_prologue (file, size, leaf_function)
3085 /* Need to use actual_fsize, since we are also allocating
3086 space for our callee (and our own register save area). */
3087 actual_fsize = compute_frame_size (size, leaf_function);
3091 frame_base_name = "%sp";
3092 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3096 frame_base_name = "%fp";
3097 frame_base_offset = SPARC_STACK_BIAS;
3100 /* This is only for the human reader. */
3101 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3103 if (actual_fsize == 0)
3105 else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE)
3107 if (actual_fsize <= 4096)
3108 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3109 else if (actual_fsize <= 8192)
3111 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3112 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3116 build_big_number (file, -actual_fsize, "%g1");
3117 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
3120 else if (! leaf_function && TARGET_BROKEN_SAVERESTORE)
3122 /* We assume the environment will properly handle or otherwise avoid
3123 trouble associated with an interrupt occurring after the `save' or
3124 trap occurring during it. */
3125 fprintf (file, "\tsave\n");
3127 if (actual_fsize <= 4096)
3128 fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize);
3129 else if (actual_fsize <= 8192)
3131 fprintf (file, "\tadd\t%%fp, -4096, %%sp\n");
3132 fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize - 4096);
3136 build_big_number (file, -actual_fsize, "%g1");
3137 fprintf (file, "\tadd\t%%fp, %%g1, %%sp\n");
3140 else /* leaf function */
3142 if (actual_fsize <= 4096)
3143 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3144 else if (actual_fsize <= 8192)
3146 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3147 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3151 build_big_number (file, -actual_fsize, "%g1");
3152 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3156 if (dwarf2out_do_frame () && actual_fsize)
3158 char *label = dwarf2out_cfi_label ();
3160 /* The canonical frame address refers to the top of the frame. */
3161 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3162 : FRAME_POINTER_REGNUM),
3165 if (! leaf_function)
3167 /* Note the register window save. This tells the unwinder that
3168 it needs to restore the window registers from the previous
3169 frame's window save area at 0(cfa). */
3170 dwarf2out_window_save (label);
3172 /* The return address (-8) is now in %i7. */
3173 dwarf2out_return_reg (label, 31);
3177 /* If doing anything with PIC, do it now. */
3179 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3181 /* Call saved registers are saved just above the outgoing argument area. */
3184 int offset, real_offset, n_regs;
3187 real_offset = -apparent_fsize;
3188 offset = -apparent_fsize + frame_base_offset;
3189 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3191 /* ??? This might be optimized a little as %g1 might already have a
3192 value close enough that a single add insn will do. */
3193 /* ??? Although, all of this is probably only a temporary fix
3194 because if %g1 can hold a function result, then
3195 output_function_epilogue will lose (the result will get
3197 build_big_number (file, offset, "%g1");
3198 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3204 base = frame_base_name;
3208 if (TARGET_EPILOGUE && ! leaf_function)
3209 /* ??? Originally saved regs 0-15 here. */
3210 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3211 else if (leaf_function)
3212 /* ??? Originally saved regs 0-31 here. */
3213 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3214 if (TARGET_EPILOGUE)
3215 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3220 if (leaf_function && actual_fsize != 0)
3222 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3223 if (! TARGET_EPILOGUE)
3224 leaf_label = gen_label_rtx ();
3228 /* Output code for the function epilogue. */
3231 output_function_epilogue (file, size, leaf_function)
3233 int size ATTRIBUTE_UNUSED;
3240 emit_label_after (leaf_label, get_last_insn ());
3241 final_scan_insn (get_last_insn (), file, 0, 0, 1);
3244 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3245 else if (profile_block_flag == 2)
3247 FUNCTION_BLOCK_PROFILER_EXIT(file);
3251 else if (current_function_epilogue_delay_list == 0)
3253 /* If code does not drop into the epilogue, we need
3254 do nothing except output pending case vectors. */
3255 rtx insn = get_last_insn ();
3256 if (GET_CODE (insn) == NOTE)
3257 insn = prev_nonnote_insn (insn);
3258 if (insn && GET_CODE (insn) == BARRIER)
3259 goto output_vectors;
3262 /* Restore any call saved registers. */
3268 offset = -apparent_fsize + frame_base_offset;
3269 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3271 build_big_number (file, offset, "%g1");
3272 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3278 base = frame_base_name;
3282 if (TARGET_EPILOGUE && ! leaf_function)
3283 /* ??? Originally saved regs 0-15 here. */
3284 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3285 else if (leaf_function)
3286 /* ??? Originally saved regs 0-31 here. */
3287 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3288 if (TARGET_EPILOGUE)
3289 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
3292 /* Work out how to skip the caller's unimp instruction if required. */
3294 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
3296 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
3298 if (TARGET_EPILOGUE || leaf_label)
3300 int old_target_epilogue = TARGET_EPILOGUE;
3301 target_flags &= ~old_target_epilogue;
3303 if (! leaf_function)
3305 /* If we wound up with things in our delay slot, flush them here. */
3306 if (current_function_epilogue_delay_list)
3308 rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode),
3310 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode,
3312 PATTERN (XEXP (current_function_epilogue_delay_list, 0)),
3314 final_scan_insn (insn, file, 1, 0, 1);
3316 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
3317 fputs ("\treturn\t%i7+8\n\tnop\n", file);
3319 fprintf (file, "\t%s\n\trestore\n", ret);
3321 /* All of the following cases are for leaf functions. */
3322 else if (current_function_epilogue_delay_list)
3324 /* eligible_for_epilogue_delay_slot ensures that if this is a
3325 leaf function, then we will only have insn in the delay slot
3326 if the frame size is zero, thus no adjust for the stack is
3328 if (actual_fsize != 0)
3330 fprintf (file, "\t%s\n", ret);
3331 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
3334 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3335 avoid generating confusing assembly language output. */
3336 else if (actual_fsize == 0)
3337 fprintf (file, "\t%s\n\tnop\n", ret);
3338 else if (actual_fsize <= 4096)
3339 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
3340 else if (actual_fsize <= 8192)
3341 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
3342 ret, actual_fsize - 4096);
3343 else if ((actual_fsize & 0x3ff) == 0)
3344 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3347 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3348 actual_fsize, actual_fsize, ret);
3349 target_flags |= old_target_epilogue;
3353 sparc_output_deferred_case_vectors ();
3356 /* Functions for handling argument passing.
3358 For v8 the first six args are normally in registers and the rest are
3359 pushed. Any arg that starts within the first 6 words is at least
3360 partially passed in a register unless its data type forbids.
3362 For v9, the argument registers are laid out as an array of 16 elements
3363 and arguments are added sequentially. The first 6 int args and up to the
3364 first 16 fp args (depending on size) are passed in regs.
3366 Slot Stack Integral Float Float in structure Double Long Double
3367 ---- ----- -------- ----- ------------------ ------ -----------
3368 15 [SP+248] %f31 %f30,%f31 %d30
3369 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3370 13 [SP+232] %f27 %f26,%f27 %d26
3371 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3372 11 [SP+216] %f23 %f22,%f23 %d22
3373 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3374 9 [SP+200] %f19 %f18,%f19 %d18
3375 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3376 7 [SP+184] %f15 %f14,%f15 %d14
3377 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3378 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3379 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3380 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3381 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3382 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3383 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3385 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3387 Integral arguments are always passed as 64 bit quantities appropriately
3390 Passing of floating point values is handled as follows.
3391 If a prototype is in scope:
3392 If the value is in a named argument (i.e. not a stdarg function or a
3393 value not part of the `...') then the value is passed in the appropriate
3395 If the value is part of the `...' and is passed in one of the first 6
3396 slots then the value is passed in the appropriate int reg.
3397 If the value is part of the `...' and is not passed in one of the first 6
3398 slots then the value is passed in memory.
3399 If a prototype is not in scope:
3400 If the value is one of the first 6 arguments the value is passed in the
3401 appropriate integer reg and the appropriate fp reg.
3402 If the value is not one of the first 6 arguments the value is passed in
3403 the appropriate fp reg and in memory.
3406 /* Maximum number of int regs for args. */
3407 #define SPARC_INT_ARG_MAX 6
3408 /* Maximum number of fp regs for args. */
3409 #define SPARC_FP_ARG_MAX 16
3411 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3413 /* Handle the INIT_CUMULATIVE_ARGS macro.
3414 Initialize a variable CUM of type CUMULATIVE_ARGS
3415 for a call to a function whose data type is FNTYPE.
3416 For a library call, FNTYPE is 0. */
3419 init_cumulative_args (cum, fntype, libname, indirect)
3420 CUMULATIVE_ARGS *cum;
3422 tree libname ATTRIBUTE_UNUSED;
3423 int indirect ATTRIBUTE_UNUSED;
3426 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
3427 cum->libcall_p = fntype == 0;
3430 /* Compute the slot number to pass an argument in.
3431 Returns the slot number or -1 if passing on the stack.
3433 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3434 the preceding args and about the function being called.
3435 MODE is the argument's machine mode.
3436 TYPE is the data type of the argument (as a tree).
3437 This is null for libcalls where that information may
3439 NAMED is nonzero if this argument is a named parameter
3440 (otherwise it is an extra parameter matching an ellipsis).
3441 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3442 *PREGNO records the register number to use if scalar type.
3443 *PPADDING records the amount of padding needed in words. */
3446 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
3447 const CUMULATIVE_ARGS *cum;
3448 enum machine_mode mode;
3455 int regbase = (incoming_p
3456 ? SPARC_INCOMING_INT_ARG_FIRST
3457 : SPARC_OUTGOING_INT_ARG_FIRST);
3458 int slotno = cum->words;
3463 if (type != 0 && TREE_ADDRESSABLE (type))
3466 && type != 0 && mode == BLKmode
3467 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
3473 /* MODE is VOIDmode when generating the actual call.
3477 case QImode : case CQImode :
3478 case HImode : case CHImode :
3479 case SImode : case CSImode :
3480 case DImode : case CDImode :
3481 if (slotno >= SPARC_INT_ARG_MAX)
3483 regno = regbase + slotno;
3486 case SFmode : case SCmode :
3487 case DFmode : case DCmode :
3488 case TFmode : case TCmode :
3491 if (slotno >= SPARC_INT_ARG_MAX)
3493 regno = regbase + slotno;
3497 if ((mode == TFmode || mode == TCmode)
3498 && (slotno & 1) != 0)
3499 slotno++, *ppadding = 1;
3500 if (TARGET_FPU && named)
3502 if (slotno >= SPARC_FP_ARG_MAX)
3504 regno = SPARC_FP_ARG_FIRST + slotno * 2;
3510 if (slotno >= SPARC_INT_ARG_MAX)
3512 regno = regbase + slotno;
3518 /* For sparc64, objects requiring 16 byte alignment get it. */
3521 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
3522 slotno++, *ppadding = 1;
3526 || (type && TREE_CODE (type) == UNION_TYPE))
3528 if (slotno >= SPARC_INT_ARG_MAX)
3530 regno = regbase + slotno;
3535 int intregs_p = 0, fpregs_p = 0;
3536 /* The ABI obviously doesn't specify how packed
3537 structures are passed. These are defined to be passed
3538 in int regs if possible, otherwise memory. */
3541 /* First see what kinds of registers we need. */
3542 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3544 if (TREE_CODE (field) == FIELD_DECL)
3546 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3551 if (DECL_PACKED (field))
3555 if (packed_p || !named)
3556 fpregs_p = 0, intregs_p = 1;
3558 /* If all arg slots are filled, then must pass on stack. */
3559 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
3561 /* If there are only int args and all int arg slots are filled,
3562 then must pass on stack. */
3563 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
3565 /* Note that even if all int arg slots are filled, fp members may
3566 still be passed in regs if such regs are available.
3567 *PREGNO isn't set because there may be more than one, it's up
3568 to the caller to compute them. */
3581 /* Handle recursive register counting for structure field layout. */
3583 struct function_arg_record_value_parms
3586 int slotno, named, regbase;
3587 int nregs, intoffset;
3590 static void function_arg_record_value_3
3591 PROTO((int, struct function_arg_record_value_parms *));
3592 static void function_arg_record_value_2
3593 PROTO((tree, int, struct function_arg_record_value_parms *));
3594 static rtx function_arg_record_value
3595 PROTO((tree, enum machine_mode, int, int, int));
3598 function_arg_record_value_1 (type, startbitpos, parms)
3601 struct function_arg_record_value_parms *parms;
3605 /* The ABI obviously doesn't specify how packed structures are
3606 passed. These are defined to be passed in int regs if possible,
3607 otherwise memory. */
3610 /* We need to compute how many registers are needed so we can
3611 allocate the PARALLEL but before we can do that we need to know
3612 whether there are any packed fields. If there are, int regs are
3613 used regardless of whether there are fp values present. */
3614 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3616 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
3623 /* Compute how many registers we need. */
3624 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3626 if (TREE_CODE (field) == FIELD_DECL)
3628 int bitpos = startbitpos;
3629 if (DECL_FIELD_BITPOS (field))
3630 bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3631 /* ??? FIXME: else assume zero offset. */
3633 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
3635 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
3637 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3642 if (parms->intoffset != -1)
3644 int intslots, this_slotno;
3646 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
3648 this_slotno = parms->slotno + parms->intoffset
3651 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3652 intslots = MAX (intslots, 0);
3653 parms->nregs += intslots;
3654 parms->intoffset = -1;
3657 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
3658 If it wasn't true we wouldn't be here. */
3663 if (parms->intoffset == -1)
3664 parms->intoffset = bitpos;
3670 /* Handle recursive structure field register assignment. */
3673 function_arg_record_value_3 (bitpos, parms)
3675 struct function_arg_record_value_parms *parms;
3677 enum machine_mode mode;
3678 int regno, this_slotno, intslots, intoffset;
3681 if (parms->intoffset == -1)
3683 intoffset = parms->intoffset;
3684 parms->intoffset = -1;
3686 intslots = (bitpos - intoffset + BITS_PER_WORD - 1) / BITS_PER_WORD;
3687 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
3689 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3693 /* If this is the trailing part of a word, only load that much into
3694 the register. Otherwise load the whole register. Note that in
3695 the latter case we may pick up unwanted bits. It's not a problem
3696 at the moment but may wish to revisit. */
3698 if (intoffset % BITS_PER_WORD != 0)
3700 mode = mode_for_size (BITS_PER_WORD - intoffset%BITS_PER_WORD,
3706 intoffset /= BITS_PER_UNIT;
3709 regno = parms->regbase + this_slotno;
3710 reg = gen_rtx_REG (mode, regno);
3711 XVECEXP (parms->ret, 0, parms->nregs)
3712 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
3715 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
3719 while (intslots > 0);
3723 function_arg_record_value_2 (type, startbitpos, parms)
3726 struct function_arg_record_value_parms *parms;
3731 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3733 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
3740 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3742 if (TREE_CODE (field) == FIELD_DECL)
3744 int bitpos = startbitpos;
3745 if (DECL_FIELD_BITPOS (field))
3746 bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3747 /* ??? FIXME: else assume zero offset. */
3749 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
3751 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
3753 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3758 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
3761 function_arg_record_value_3 (bitpos, parms);
3763 reg = gen_rtx_REG (DECL_MODE (field),
3764 (SPARC_FP_ARG_FIRST + this_slotno * 2
3765 + (DECL_MODE (field) == SFmode
3766 && (bitpos & 32) != 0)));
3767 XVECEXP (parms->ret, 0, parms->nregs)
3768 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3769 GEN_INT (bitpos / BITS_PER_UNIT));
3774 if (parms->intoffset == -1)
3775 parms->intoffset = bitpos;
3782 function_arg_record_value (type, mode, slotno, named, regbase)
3784 enum machine_mode mode;
3785 int slotno, named, regbase;
3787 HOST_WIDE_INT typesize = int_size_in_bytes (type);
3788 struct function_arg_record_value_parms parms;
3791 parms.ret = NULL_RTX;
3792 parms.slotno = slotno;
3793 parms.named = named;
3794 parms.regbase = regbase;
3796 /* Compute how many registers we need. */
3798 parms.intoffset = 0;
3799 function_arg_record_value_1 (type, 0, &parms);
3801 if (parms.intoffset != -1)
3803 int intslots, this_slotno;
3805 intslots = (typesize*BITS_PER_UNIT - parms.intoffset + BITS_PER_WORD - 1)
3807 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
3809 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3810 intslots = MAX (intslots, 0);
3812 parms.nregs += intslots;
3814 nregs = parms.nregs;
3816 /* Allocate the vector and handle some annoying special cases. */
3819 /* ??? Empty structure has no value? Duh? */
3822 /* Though there's nothing really to store, return a word register
3823 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
3824 leads to breakage due to the fact that there are zero bytes to
3826 return gen_rtx_REG (mode, regbase);
3830 /* ??? C++ has structures with no fields, and yet a size. Give up
3831 for now and pass everything back in integer registers. */
3832 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3834 if (nregs + slotno > SPARC_INT_ARG_MAX)
3835 nregs = SPARC_INT_ARG_MAX - slotno;
3840 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
3842 /* Fill in the entries. */
3844 parms.intoffset = 0;
3845 function_arg_record_value_2 (type, 0, &parms);
3846 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
3848 if (parms.nregs != nregs)
3854 /* Handle the FUNCTION_ARG macro.
3855 Determine where to put an argument to a function.
3856 Value is zero to push the argument on the stack,
3857 or a hard register in which to store the argument.
3859 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3860 the preceding args and about the function being called.
3861 MODE is the argument's machine mode.
3862 TYPE is the data type of the argument (as a tree).
3863 This is null for libcalls where that information may
3865 NAMED is nonzero if this argument is a named parameter
3866 (otherwise it is an extra parameter matching an ellipsis).
3867 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
3870 function_arg (cum, mode, type, named, incoming_p)
3871 const CUMULATIVE_ARGS *cum;
3872 enum machine_mode mode;
3877 int regbase = (incoming_p
3878 ? SPARC_INCOMING_INT_ARG_FIRST
3879 : SPARC_OUTGOING_INT_ARG_FIRST);
3880 int slotno, regno, padding;
3883 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
3891 reg = gen_rtx_REG (mode, regno);
3895 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
3896 but also have the slot allocated for them.
3897 If no prototype is in scope fp values in register slots get passed
3898 in two places, either fp regs and int regs or fp regs and memory. */
3899 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
3900 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3901 && SPARC_FP_REG_P (regno))
3903 reg = gen_rtx_REG (mode, regno);
3904 if (cum->prototype_p || cum->libcall_p)
3906 /* "* 2" because fp reg numbers are recorded in 4 byte
3909 /* ??? This will cause the value to be passed in the fp reg and
3910 in the stack. When a prototype exists we want to pass the
3911 value in the reg but reserve space on the stack. That's an
3912 optimization, and is deferred [for a bit]. */
3913 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
3914 return gen_rtx_PARALLEL (mode,
3916 gen_rtx_EXPR_LIST (VOIDmode,
3917 NULL_RTX, const0_rtx),
3918 gen_rtx_EXPR_LIST (VOIDmode,
3922 /* ??? It seems that passing back a register even when past
3923 the area declared by REG_PARM_STACK_SPACE will allocate
3924 space appropriately, and will not copy the data onto the
3925 stack, exactly as we desire.
3927 This is due to locate_and_pad_parm being called in
3928 expand_call whenever reg_parm_stack_space > 0, which
3929 while benefical to our example here, would seem to be
3930 in error from what had been intended. Ho hum... -- r~ */
3938 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
3942 /* On incoming, we don't need to know that the value
3943 is passed in %f0 and %i0, and it confuses other parts
3944 causing needless spillage even on the simplest cases. */
3948 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
3949 + (regno - SPARC_FP_ARG_FIRST) / 2);
3951 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
3952 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
3954 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
3958 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
3959 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
3960 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
3964 else if (type && TREE_CODE (type) == RECORD_TYPE)
3966 /* Structures up to 16 bytes in size are passed in arg slots on the
3967 stack and are promoted to registers where possible. */
3969 if (int_size_in_bytes (type) > 16)
3970 abort (); /* shouldn't get here */
3972 return function_arg_record_value (type, mode, slotno, named, regbase);
3974 else if (type && TREE_CODE (type) == UNION_TYPE)
3976 enum machine_mode mode;
3977 int bytes = int_size_in_bytes (type);
3982 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
3983 reg = gen_rtx_REG (mode, regno);
3987 /* Scalar or complex int. */
3988 reg = gen_rtx_REG (mode, regno);
3994 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
3995 For an arg passed partly in registers and partly in memory,
3996 this is the number of registers used.
3997 For args passed entirely in registers or entirely in memory, zero.
3999 Any arg that starts in the first 6 regs but won't entirely fit in them
4000 needs partial registers on v8. On v9, structures with integer
4001 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4002 values that begin in the last fp reg [where "last fp reg" varies with the
4003 mode] will be split between that reg and memory. */
4006 function_arg_partial_nregs (cum, mode, type, named)
4007 const CUMULATIVE_ARGS *cum;
4008 enum machine_mode mode;
4012 int slotno, regno, padding;
4014 /* We pass 0 for incoming_p here, it doesn't matter. */
4015 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4022 if ((slotno + (mode == BLKmode
4023 ? ROUND_ADVANCE (int_size_in_bytes (type))
4024 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
4025 > NPARM_REGS (SImode))
4026 return NPARM_REGS (SImode) - slotno;
4031 if (type && AGGREGATE_TYPE_P (type))
4033 int size = int_size_in_bytes (type);
4034 int align = TYPE_ALIGN (type);
4037 slotno += slotno & 1;
4038 if (size > 8 && size <= 16
4039 && slotno == SPARC_INT_ARG_MAX - 1)
4042 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
4043 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4046 if (GET_MODE_ALIGNMENT (mode) == 128)
4048 slotno += slotno & 1;
4049 if (slotno == SPARC_INT_ARG_MAX - 2)
4054 if (slotno == SPARC_INT_ARG_MAX - 1)
4058 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4060 if (GET_MODE_ALIGNMENT (mode) == 128)
4061 slotno += slotno & 1;
4062 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
4070 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
4071 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
4072 quad-precision floats by invisible reference.
4073 v9: Aggregates greater than 16 bytes are passed by reference.
4074 For Pascal, also pass arrays by reference. */
4077 function_arg_pass_by_reference (cum, mode, type, named)
4078 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
4079 enum machine_mode mode;
4081 int named ATTRIBUTE_UNUSED;
4085 return ((type && AGGREGATE_TYPE_P (type))
4086 || mode == TFmode || mode == TCmode);
4090 return ((type && TREE_CODE (type) == ARRAY_TYPE)
4091 /* Consider complex values as aggregates, so care for TCmode. */
4092 || GET_MODE_SIZE (mode) > 16
4093 || (type && AGGREGATE_TYPE_P (type)
4094 && int_size_in_bytes (type) > 16));
4098 /* Handle the FUNCTION_ARG_ADVANCE macro.
4099 Update the data in CUM to advance over an argument
4100 of mode MODE and data type TYPE.
4101 TYPE is null for libcalls where that information may not be available. */
4104 function_arg_advance (cum, mode, type, named)
4105 CUMULATIVE_ARGS *cum;
4106 enum machine_mode mode;
4110 int slotno, regno, padding;
4112 /* We pass 0 for incoming_p here, it doesn't matter. */
4113 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4115 /* If register required leading padding, add it. */
4117 cum->words += padding;
4121 cum->words += (mode != BLKmode
4122 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4123 : ROUND_ADVANCE (int_size_in_bytes (type)));
4127 if (type && AGGREGATE_TYPE_P (type))
4129 int size = int_size_in_bytes (type);
4133 else if (size <= 16)
4135 else /* passed by reference */
4138 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
4142 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4144 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
4148 cum->words += (mode != BLKmode
4149 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4150 : ROUND_ADVANCE (int_size_in_bytes (type)));
4155 /* Handle the FUNCTION_ARG_PADDING macro.
4156 For the 64 bit ABI structs are always stored left shifted in their
4160 function_arg_padding (mode, type)
4161 enum machine_mode mode;
4164 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
4167 /* This is the default definition. */
4168 return (! BYTES_BIG_ENDIAN
4171 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
4172 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
4173 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
4174 ? downward : upward));
4177 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
4178 For v9, function return values are subject to the same rules as arguments,
4179 except that up to 32-bytes may be returned in registers. */
4182 function_value (type, mode, incoming_p)
4184 enum machine_mode mode;
4188 int regbase = (incoming_p
4189 ? SPARC_OUTGOING_INT_ARG_FIRST
4190 : SPARC_INCOMING_INT_ARG_FIRST);
4192 if (TARGET_ARCH64 && type)
4194 if (TREE_CODE (type) == RECORD_TYPE)
4196 /* Structures up to 32 bytes in size are passed in registers,
4197 promoted to fp registers where possible. */
4199 if (int_size_in_bytes (type) > 32)
4200 abort (); /* shouldn't get here */
4202 return function_arg_record_value (type, mode, 0, 1, regbase);
4204 else if (TREE_CODE (type) == UNION_TYPE)
4206 int bytes = int_size_in_bytes (type);
4211 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4216 regno = BASE_RETURN_VALUE_REG (mode);
4218 regno = BASE_OUTGOING_VALUE_REG (mode);
4220 return gen_rtx_REG (mode, regno);
4223 /* Do what is necessary for `va_start'. The argument is ignored.
4225 We look at the current function to determine if stdarg or varargs
4226 is used and return the address of the first unnamed parameter. */
4229 sparc_builtin_saveregs (arglist)
4230 tree arglist ATTRIBUTE_UNUSED;
4232 int first_reg = current_function_args_info.words;
4236 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
4237 emit_move_insn (gen_rtx_MEM (word_mode,
4238 gen_rtx_PLUS (Pmode,
4240 GEN_INT (STACK_POINTER_OFFSET
4241 + UNITS_PER_WORD * regno))),
4242 gen_rtx_REG (word_mode,
4243 BASE_INCOMING_ARG_REG (word_mode) + regno));
4245 address = gen_rtx_PLUS (Pmode,
4247 GEN_INT (STACK_POINTER_OFFSET
4248 + UNITS_PER_WORD * first_reg));
4250 if (flag_check_memory_usage
4251 && first_reg < NPARM_REGS (word_mode))
4252 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4254 GEN_INT (UNITS_PER_WORD
4255 * (NPARM_REGS (word_mode) - first_reg)),
4256 TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW),
4257 TYPE_MODE (integer_type_node));
4262 /* Return the string to output a conditional branch to LABEL, which is
4263 the operand number of the label. OP is the conditional expression.
4264 XEXP (OP, 0) is assumed to be a condition code register (integer or
4265 floating point) and its mode specifies what kind of comparison we made.
4267 REVERSED is non-zero if we should reverse the sense of the comparison.
4269 ANNUL is non-zero if we should generate an annulling branch.
4271 NOOP is non-zero if we have to follow this branch by a noop.
4273 INSN, if set, is the insn. */
4276 output_cbranch (op, label, reversed, annul, noop, insn)
4279 int reversed, annul, noop;
4282 static char string[32];
4283 enum rtx_code code = GET_CODE (op);
4284 rtx cc_reg = XEXP (op, 0);
4285 enum machine_mode mode = GET_MODE (cc_reg);
4286 static char v8_labelno[] = "%lX";
4287 static char v9_icc_labelno[] = "%%icc, %lX";
4288 static char v9_xcc_labelno[] = "%%xcc, %lX";
4289 static char v9_fcc_labelno[] = "%%fccX, %lY";
4291 int labeloff, spaces = 8;
4293 /* ??? !v9: FP branches cannot be preceded by another floating point insn.
4294 Because there is currently no concept of pre-delay slots, we can fix
4295 this only by always emitting a nop before a floating point branch. */
4297 if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9)
4298 strcpy (string, "nop\n\t");
4302 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4304 && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE))
4305 code = reverse_condition (code), reversed = 0;
4307 /* Start by writing the branch condition. */
4311 if (mode == CCFPmode || mode == CCFPEmode)
4313 strcat (string, "fbne");
4318 strcpy (string, "bne");
4324 if (mode == CCFPmode || mode == CCFPEmode)
4326 strcat (string, "fbe");
4331 strcpy (string, "be");
4337 if (mode == CCFPmode || mode == CCFPEmode)
4340 strcat (string, "fbul");
4342 strcat (string, "fbge");
4345 else if (mode == CC_NOOVmode)
4347 strcpy (string, "bpos");
4352 strcpy (string, "bge");
4358 if (mode == CCFPmode || mode == CCFPEmode)
4362 strcat (string, "fbule");
4367 strcat (string, "fbg");
4373 strcpy (string, "bg");
4379 if (mode == CCFPmode || mode == CCFPEmode)
4382 strcat (string, "fbug");
4384 strcat (string, "fble");
4389 strcpy (string, "ble");
4395 if (mode == CCFPmode || mode == CCFPEmode)
4399 strcat (string, "fbuge");
4404 strcat (string, "fbl");
4408 else if (mode == CC_NOOVmode)
4410 strcpy (string, "bneg");
4415 strcpy (string, "bl");
4421 strcpy (string, "bgeu");
4426 strcpy (string, "bgu");
4431 strcpy (string, "bleu");
4436 strcpy (string, "blu");
4444 /* Now add the annulling, the label, and a possible noop. */
4447 strcat (string, ",a");
4454 labelno = v8_labelno;
4460 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
4463 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
4468 if (mode == CCFPmode || mode == CCFPEmode)
4471 labelno = v9_fcc_labelno;
4472 /* Set the char indicating the number of the fcc reg to use. */
4473 labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
4475 else if (mode == CCXmode || mode == CCX_NOOVmode)
4476 labelno = v9_xcc_labelno;
4478 labelno = v9_icc_labelno;
4480 /* Set the char indicating the number of the operand containing the
4482 labelno[labeloff] = label + '0';
4484 strcat (string, "\t");
4486 strcat (string, " ");
4487 strcat (string, labelno);
4490 strcat (string, "\n\tnop");
4495 /* Return the string to output a conditional branch to LABEL, testing
4496 register REG. LABEL is the operand number of the label; REG is the
4497 operand number of the reg. OP is the conditional expression. The mode
4498 of REG says what kind of comparison we made.
4500 REVERSED is non-zero if we should reverse the sense of the comparison.
4502 ANNUL is non-zero if we should generate an annulling branch.
4504 NOOP is non-zero if we have to follow this branch by a noop. */
4507 output_v9branch (op, reg, label, reversed, annul, noop, insn)
4510 int reversed, annul, noop;
4513 static char string[20];
4514 enum rtx_code code = GET_CODE (op);
4515 enum machine_mode mode = GET_MODE (XEXP (op, 0));
4516 static char labelno[] = "%X, %lX";
4520 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4522 code = reverse_condition (code), reversed = 0;
4524 /* Only 64 bit versions of these instructions exist. */
4528 /* Start by writing the branch condition. */
4533 strcpy (string, "brnz");
4538 strcpy (string, "brz");
4543 strcpy (string, "brgez");
4548 strcpy (string, "brlz");
4553 strcpy (string, "brlez");
4558 strcpy (string, "brgz");
4566 /* Now add the annulling, reg, label, and nop. */
4569 strcat (string, ",a");
4573 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
4576 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
4580 labelno[1] = reg + '0';
4581 labelno[6] = label + '0';
4583 strcat (string, "\t");
4585 strcat (string, " ");
4586 strcat (string, labelno);
4589 strcat (string, "\n\tnop");
4594 /* Renumber registers in delay slot. Replace registers instead of
4595 renumbering because they may be shared.
4597 This does not handle instructions other than move. */
4600 epilogue_renumber (where)
4604 enum rtx_code code = GET_CODE (x);
4609 *where = x = copy_rtx (x);
4610 epilogue_renumber (&XEXP (x, 0));
4615 int regno = REGNO (x);
4616 if (regno > 8 && regno < 24)
4618 if (regno >= 24 && regno < 32)
4619 *where = gen_rtx_REG (GET_MODE (x), regno - 16);
4634 epilogue_renumber (&XEXP (x, 1));
4637 epilogue_renumber (&XEXP (x, 0));
4646 /* Output assembler code to return from a function. */
4649 output_return (operands)
4652 rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0;
4656 operands[0] = leaf_label;
4659 else if (leaf_function)
4661 /* No delay slot in a leaf function. */
4665 /* If we didn't allocate a frame pointer for the current function,
4666 the stack pointer might have been adjusted. Output code to
4669 operands[0] = GEN_INT (actual_fsize);
4671 /* Use sub of negated value in first two cases instead of add to
4672 allow actual_fsize == 4096. */
4674 if (actual_fsize <= 4096)
4676 if (SKIP_CALLERS_UNIMP_P)
4677 return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
4679 return "retl\n\tsub\t%%sp, -%0, %%sp";
4681 else if (actual_fsize <= 8192)
4683 operands[0] = GEN_INT (actual_fsize - 4096);
4684 if (SKIP_CALLERS_UNIMP_P)
4685 return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
4687 return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
4689 else if (SKIP_CALLERS_UNIMP_P)
4691 if ((actual_fsize & 0x3ff) != 0)
4692 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
4694 return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
4698 if ((actual_fsize & 0x3ff) != 0)
4699 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4701 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4708 epilogue_renumber (&SET_DEST (PATTERN (delay)));
4709 epilogue_renumber (&SET_SRC (PATTERN (delay)));
4711 if (SKIP_CALLERS_UNIMP_P)
4712 return "return\t%%i7+12%#";
4714 return "return\t%%i7+8%#";
4720 if (SKIP_CALLERS_UNIMP_P)
4721 return "jmp\t%%i7+12\n\trestore";
4723 return "ret\n\trestore";
4727 /* Leaf functions and non-leaf functions have different needs. */
4730 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
4733 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
4735 static int *reg_alloc_orders[] = {
4736 reg_leaf_alloc_order,
4737 reg_nonleaf_alloc_order};
4740 order_regs_for_local_alloc ()
4742 static int last_order_nonleaf = 1;
4744 if (regs_ever_live[15] != last_order_nonleaf)
4746 last_order_nonleaf = !last_order_nonleaf;
4747 bcopy ((char *) reg_alloc_orders[last_order_nonleaf],
4748 (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int));
4752 /* Return 1 if REG and MEM are legitimate enough to allow the various
4753 mem<-->reg splits to be run. */
4756 sparc_splitdi_legitimate (reg, mem)
4760 /* Punt if we are here by mistake. */
4761 if (! reload_completed)
4764 /* We must have an offsettable memory reference. */
4765 if (! offsettable_memref_p (mem))
4768 /* If we have legitimate args for ldd/std, we do not want
4769 the split to happen. */
4770 if ((REGNO (reg) % 2) == 0
4771 && mem_min_alignment (mem, 8))
4778 /* Return 1 if x and y are some kind of REG and they refer to
4779 different hard registers. This test is guarenteed to be
4780 run after reload. */
4783 sparc_absnegfloat_split_legitimate (x, y)
4786 if (GET_CODE (x) == SUBREG)
4787 x = alter_subreg (x);
4788 if (GET_CODE (x) != REG)
4790 if (GET_CODE (y) == SUBREG)
4791 y = alter_subreg (y);
4792 if (GET_CODE (y) != REG)
4794 if (REGNO (x) == REGNO (y))
4799 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
4800 This makes them candidates for using ldd and std insns.
4802 Note reg1 and reg2 *must* be hard registers. */
4805 registers_ok_for_ldd_peep (reg1, reg2)
4808 /* We might have been passed a SUBREG. */
4809 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
4812 if (REGNO (reg1) % 2 != 0)
4815 /* Integer ldd is deprecated in SPARC V9 */
4816 if (TARGET_V9 && REGNO (reg1) < 32)
4819 return (REGNO (reg1) == REGNO (reg2) - 1);
4822 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
4825 This can only happen when addr1 and addr2 are consecutive memory
4826 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
4827 64 bit boundary (addr1 % 8 == 0).
4829 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
4830 registers are assumed to *never* be properly aligned and are
4833 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
4834 need only check that the offset for addr1 % 8 == 0. */
4837 addrs_ok_for_ldd_peep (addr1, addr2)
4842 /* Extract a register number and offset (if used) from the first addr. */
4843 if (GET_CODE (addr1) == PLUS)
4845 /* If not a REG, return zero. */
4846 if (GET_CODE (XEXP (addr1, 0)) != REG)
4850 reg1 = REGNO (XEXP (addr1, 0));
4851 /* The offset must be constant! */
4852 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
4854 offset1 = INTVAL (XEXP (addr1, 1));
4857 else if (GET_CODE (addr1) != REG)
4861 reg1 = REGNO (addr1);
4862 /* This was a simple (mem (reg)) expression. Offset is 0. */
4866 /* Make sure the second address is a (mem (plus (reg) (const_int). */
4867 if (GET_CODE (addr2) != PLUS)
4870 if (GET_CODE (XEXP (addr2, 0)) != REG
4871 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
4874 /* Only %fp and %sp are allowed. Additionally both addresses must
4875 use the same register. */
4876 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
4879 if (reg1 != REGNO (XEXP (addr2, 0)))
4882 /* The first offset must be evenly divisible by 8 to ensure the
4883 address is 64 bit aligned. */
4884 if (offset1 % 8 != 0)
4887 /* The offset for the second addr must be 4 more than the first addr. */
4888 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
4891 /* All the tests passed. addr1 and addr2 are valid for ldd and std
4896 /* Return 1 if reg is a pseudo, or is the first register in
4897 a hard register pair. This makes it a candidate for use in
4898 ldd and std insns. */
4901 register_ok_for_ldd (reg)
4904 /* We might have been passed a SUBREG. */
4905 if (GET_CODE (reg) != REG)
4908 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
4909 return (REGNO (reg) % 2 == 0);
4914 /* Print operand X (an rtx) in assembler syntax to file FILE.
4915 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4916 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4919 print_operand (file, x, code)
4927 /* Output a 'nop' if there's nothing for the delay slot. */
4928 if (dbr_sequence_length () == 0)
4929 fputs ("\n\t nop", file);
4932 /* Output an annul flag if there's nothing for the delay slot and we
4933 are optimizing. This is always used with '(' below. */
4934 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
4935 this is a dbx bug. So, we only do this when optimizing. */
4936 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
4937 Always emit a nop in case the next instruction is a branch. */
4938 if (dbr_sequence_length () == 0
4939 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
4943 /* Output a 'nop' if there's nothing for the delay slot and we are
4944 not optimizing. This is always used with '*' above. */
4945 if (dbr_sequence_length () == 0
4946 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
4947 fputs ("\n\t nop", file);
4950 /* Output the Embedded Medium/Anywhere code model base register. */
4951 fputs (EMBMEDANY_BASE_REG, file);
4954 /* Print out what we are using as the frame pointer. This might
4955 be %fp, or might be %sp+offset. */
4956 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
4957 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
4960 /* Adjust the operand to take into account a RESTORE operation. */
4961 if (GET_CODE (x) == CONST_INT)
4963 else if (GET_CODE (x) != REG)
4964 output_operand_lossage ("Invalid %%Y operand");
4965 else if (REGNO (x) < 8)
4966 fputs (reg_names[REGNO (x)], file);
4967 else if (REGNO (x) >= 24 && REGNO (x) < 32)
4968 fputs (reg_names[REGNO (x)-16], file);
4970 output_operand_lossage ("Invalid %%Y operand");
4973 /* Print out the low order register name of a register pair. */
4974 if (WORDS_BIG_ENDIAN)
4975 fputs (reg_names[REGNO (x)+1], file);
4977 fputs (reg_names[REGNO (x)], file);
4980 /* Print out the high order register name of a register pair. */
4981 if (WORDS_BIG_ENDIAN)
4982 fputs (reg_names[REGNO (x)], file);
4984 fputs (reg_names[REGNO (x)+1], file);
4987 /* Print out the second register name of a register pair or quad.
4988 I.e., R (%o0) => %o1. */
4989 fputs (reg_names[REGNO (x)+1], file);
4992 /* Print out the third register name of a register quad.
4993 I.e., S (%o0) => %o2. */
4994 fputs (reg_names[REGNO (x)+2], file);
4997 /* Print out the fourth register name of a register quad.
4998 I.e., T (%o0) => %o3. */
4999 fputs (reg_names[REGNO (x)+3], file);
5002 /* Print a condition code register. */
5003 if (REGNO (x) == SPARC_ICC_REG)
5005 /* We don't handle CC[X]_NOOVmode because they're not supposed
5007 if (GET_MODE (x) == CCmode)
5008 fputs ("%icc", file);
5009 else if (GET_MODE (x) == CCXmode)
5010 fputs ("%xcc", file);
5015 /* %fccN register */
5016 fputs (reg_names[REGNO (x)], file);
5019 /* Print the operand's address only. */
5020 output_address (XEXP (x, 0));
5023 /* In this case we need a register. Use %g0 if the
5024 operand is const0_rtx. */
5026 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
5028 fputs ("%g0", file);
5035 switch (GET_CODE (x))
5037 case IOR: fputs ("or", file); break;
5038 case AND: fputs ("and", file); break;
5039 case XOR: fputs ("xor", file); break;
5040 default: output_operand_lossage ("Invalid %%A operand");
5045 switch (GET_CODE (x))
5047 case IOR: fputs ("orn", file); break;
5048 case AND: fputs ("andn", file); break;
5049 case XOR: fputs ("xnor", file); break;
5050 default: output_operand_lossage ("Invalid %%B operand");
5054 /* These are used by the conditional move instructions. */
5058 enum rtx_code rc = (code == 'c'
5059 ? reverse_condition (GET_CODE (x))
5063 case NE: fputs ("ne", file); break;
5064 case EQ: fputs ("e", file); break;
5065 case GE: fputs ("ge", file); break;
5066 case GT: fputs ("g", file); break;
5067 case LE: fputs ("le", file); break;
5068 case LT: fputs ("l", file); break;
5069 case GEU: fputs ("geu", file); break;
5070 case GTU: fputs ("gu", file); break;
5071 case LEU: fputs ("leu", file); break;
5072 case LTU: fputs ("lu", file); break;
5073 default: output_operand_lossage (code == 'c'
5074 ? "Invalid %%c operand"
5075 : "Invalid %%C operand");
5080 /* These are used by the movr instruction pattern. */
5084 enum rtx_code rc = (code == 'd'
5085 ? reverse_condition (GET_CODE (x))
5089 case NE: fputs ("ne", file); break;
5090 case EQ: fputs ("e", file); break;
5091 case GE: fputs ("gez", file); break;
5092 case LT: fputs ("lz", file); break;
5093 case LE: fputs ("lez", file); break;
5094 case GT: fputs ("gz", file); break;
5095 default: output_operand_lossage (code == 'd'
5096 ? "Invalid %%d operand"
5097 : "Invalid %%D operand");
5104 /* Print a sign-extended character. */
5105 int i = INTVAL (x) & 0xff;
5108 fprintf (file, "%d", i);
5113 /* Operand must be a MEM; write its address. */
5114 if (GET_CODE (x) != MEM)
5115 output_operand_lossage ("Invalid %%f operand");
5116 output_address (XEXP (x, 0));
5120 /* Do nothing special. */
5124 /* Undocumented flag. */
5125 output_operand_lossage ("invalid operand output code");
5128 if (GET_CODE (x) == REG)
5129 fputs (reg_names[REGNO (x)], file);
5130 else if (GET_CODE (x) == MEM)
5133 /* Poor Sun assembler doesn't understand absolute addressing. */
5134 if (CONSTANT_P (XEXP (x, 0))
5135 && ! TARGET_LIVE_G0)
5136 fputs ("%g0+", file);
5137 output_address (XEXP (x, 0));
5140 else if (GET_CODE (x) == HIGH)
5142 fputs ("%hi(", file);
5143 output_addr_const (file, XEXP (x, 0));
5146 else if (GET_CODE (x) == LO_SUM)
5148 print_operand (file, XEXP (x, 0), 0);
5149 if (TARGET_CM_MEDMID)
5150 fputs ("+%l44(", file);
5152 fputs ("+%lo(", file);
5153 output_addr_const (file, XEXP (x, 1));
5156 else if (GET_CODE (x) == CONST_DOUBLE
5157 && (GET_MODE (x) == VOIDmode
5158 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
5160 if (CONST_DOUBLE_HIGH (x) == 0)
5161 fprintf (file, "%u", CONST_DOUBLE_LOW (x));
5162 else if (CONST_DOUBLE_HIGH (x) == -1
5163 && CONST_DOUBLE_LOW (x) < 0)
5164 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
5166 output_operand_lossage ("long long constant not a valid immediate operand");
5168 else if (GET_CODE (x) == CONST_DOUBLE)
5169 output_operand_lossage ("floating point constant not a valid immediate operand");
5170 else { output_addr_const (file, x); }
5173 /* This function outputs assembler code for VALUE to FILE, where VALUE is
5174 a 64 bit (DImode) value. */
5176 /* ??? If there is a 64 bit counterpart to .word that the assembler
5177 understands, then using that would simply this code greatly. */
5178 /* ??? We only output .xword's for symbols and only then in environments
5179 where the assembler can handle them. */
5182 output_double_int (file, value)
5186 if (GET_CODE (value) == CONST_INT)
5188 /* ??? This has endianness issues. */
5189 #if HOST_BITS_PER_WIDE_INT == 64
5190 HOST_WIDE_INT xword = INTVAL (value);
5191 HOST_WIDE_INT high, low;
5193 high = (xword >> 32) & 0xffffffff;
5194 low = xword & 0xffffffff;
5195 ASM_OUTPUT_INT (file, GEN_INT (high));
5196 ASM_OUTPUT_INT (file, GEN_INT (low));
5198 if (INTVAL (value) < 0)
5199 ASM_OUTPUT_INT (file, constm1_rtx);
5201 ASM_OUTPUT_INT (file, const0_rtx);
5202 ASM_OUTPUT_INT (file, value);
5205 else if (GET_CODE (value) == CONST_DOUBLE)
5207 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value)));
5208 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value)));
5210 else if (GET_CODE (value) == SYMBOL_REF
5211 || GET_CODE (value) == CONST
5212 || GET_CODE (value) == PLUS
5213 || (TARGET_ARCH64 &&
5214 (GET_CODE (value) == LABEL_REF
5215 || GET_CODE (value) == CODE_LABEL
5216 || GET_CODE (value) == MINUS)))
5218 if (!TARGET_V9 || TARGET_CM_MEDLOW)
5220 ASM_OUTPUT_INT (file, const0_rtx);
5221 ASM_OUTPUT_INT (file, value);
5225 fprintf (file, "\t%s\t", ASM_LONGLONG);
5226 output_addr_const (file, value);
5227 fprintf (file, "\n");
5234 /* Return the value of a code used in the .proc pseudo-op that says
5235 what kind of result this function returns. For non-C types, we pick
5236 the closest C type. */
5238 #ifndef CHAR_TYPE_SIZE
5239 #define CHAR_TYPE_SIZE BITS_PER_UNIT
5242 #ifndef SHORT_TYPE_SIZE
5243 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
5246 #ifndef INT_TYPE_SIZE
5247 #define INT_TYPE_SIZE BITS_PER_WORD
5250 #ifndef LONG_TYPE_SIZE
5251 #define LONG_TYPE_SIZE BITS_PER_WORD
5254 #ifndef LONG_LONG_TYPE_SIZE
5255 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
5258 #ifndef FLOAT_TYPE_SIZE
5259 #define FLOAT_TYPE_SIZE BITS_PER_WORD
5262 #ifndef DOUBLE_TYPE_SIZE
5263 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5266 #ifndef LONG_DOUBLE_TYPE_SIZE
5267 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5271 sparc_type_code (type)
5274 register unsigned long qualifiers = 0;
5275 register unsigned shift;
5277 /* Only the first 30 bits of the qualifier are valid. We must refrain from
5278 setting more, since some assemblers will give an error for this. Also,
5279 we must be careful to avoid shifts of 32 bits or more to avoid getting
5280 unpredictable results. */
5282 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
5284 switch (TREE_CODE (type))
5290 qualifiers |= (3 << shift);
5295 qualifiers |= (2 << shift);
5299 case REFERENCE_TYPE:
5301 qualifiers |= (1 << shift);
5305 return (qualifiers | 8);
5308 case QUAL_UNION_TYPE:
5309 return (qualifiers | 9);
5312 return (qualifiers | 10);
5315 return (qualifiers | 16);
5318 /* If this is a range type, consider it to be the underlying
5320 if (TREE_TYPE (type) != 0)
5323 /* Carefully distinguish all the standard types of C,
5324 without messing up if the language is not C. We do this by
5325 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
5326 look at both the names and the above fields, but that's redundant.
5327 Any type whose size is between two C types will be considered
5328 to be the wider of the two types. Also, we do not have a
5329 special code to use for "long long", so anything wider than
5330 long is treated the same. Note that we can't distinguish
5331 between "int" and "long" in this code if they are the same
5332 size, but that's fine, since neither can the assembler. */
5334 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
5335 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
5337 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
5338 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
5340 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
5341 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
5344 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
5347 /* If this is a range type, consider it to be the underlying
5349 if (TREE_TYPE (type) != 0)
5352 /* Carefully distinguish all the standard types of C,
5353 without messing up if the language is not C. */
5355 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
5356 return (qualifiers | 6);
5359 return (qualifiers | 7);
5361 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
5362 /* ??? We need to distinguish between double and float complex types,
5363 but I don't know how yet because I can't reach this code from
5364 existing front-ends. */
5365 return (qualifiers | 7); /* Who knows? */
5367 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
5368 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
5369 case FILE_TYPE: /* GNU Pascal FILE type. */
5370 case SET_TYPE: /* GNU Pascal SET type. */
5371 case LANG_TYPE: /* ? */
5375 abort (); /* Not a type! */
5382 /* Nested function support. */
5384 /* Emit RTL insns to initialize the variable parts of a trampoline.
5385 FNADDR is an RTX for the address of the function's pure code.
5386 CXT is an RTX for the static chain value for the function.
5388 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
5389 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
5390 (to store insns). This is a bit excessive. Perhaps a different
5391 mechanism would be better here.
5393 Emit enough FLUSH insns to synchronize the data and instruction caches. */
5396 sparc_initialize_trampoline (tramp, fnaddr, cxt)
5397 rtx tramp, fnaddr, cxt;
5399 /* SPARC 32 bit trampoline:
5402 sethi %hi(static), %g2
5404 or %g2, %lo(static), %g2
5406 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
5407 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
5410 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
5411 expand_binop (SImode, ior_optab,
5412 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
5413 size_int (10), 0, 1),
5414 GEN_INT (0x03000000),
5415 NULL_RTX, 1, OPTAB_DIRECT));
5417 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
5418 expand_binop (SImode, ior_optab,
5419 expand_shift (RSHIFT_EXPR, SImode, cxt,
5420 size_int (10), 0, 1),
5421 GEN_INT (0x05000000),
5422 NULL_RTX, 1, OPTAB_DIRECT));
5424 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
5425 expand_binop (SImode, ior_optab,
5426 expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX),
5427 GEN_INT (0x81c06000),
5428 NULL_RTX, 1, OPTAB_DIRECT));
5430 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
5431 expand_binop (SImode, ior_optab,
5432 expand_and (cxt, GEN_INT (0x3ff), NULL_RTX),
5433 GEN_INT (0x8410a000),
5434 NULL_RTX, 1, OPTAB_DIRECT));
5436 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
5437 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
5438 aligned on a 16 byte boundary so one flush clears it all. */
5439 if (sparc_cpu != PROCESSOR_ULTRASPARC)
5440 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
5441 plus_constant (tramp, 8)))));
5444 /* The 64 bit version is simpler because it makes more sense to load the
5445 values as "immediate" data out of the trampoline. It's also easier since
5446 we can read the PC without clobbering a register. */
5449 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
5450 rtx tramp, fnaddr, cxt;
5460 emit_move_insn (gen_rtx_MEM (SImode, tramp),
5461 GEN_INT (0x83414000));
5462 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
5463 GEN_INT (0xca586018));
5464 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
5465 GEN_INT (0x81c04000));
5466 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
5467 GEN_INT (0xca586010));
5468 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
5469 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 20)), fnaddr);
5470 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, tramp))));
5471 if (sparc_cpu != PROCESSOR_ULTRASPARC)
5472 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
5475 /* Subroutines to support a flat (single) register window calling
5478 /* Single-register window sparc stack frames look like:
5480 Before call After call
5481 +-----------------------+ +-----------------------+
5483 mem | caller's temps. | | caller's temps. |
5485 +-----------------------+ +-----------------------+
5487 | arguments on stack. | | arguments on stack. |
5489 +-----------------------+FP+92->+-----------------------+
5490 | 6 words to save | | 6 words to save |
5491 | arguments passed | | arguments passed |
5492 | in registers, even | | in registers, even |
5493 | if not passed. | | if not passed. |
5494 SP+68->+-----------------------+FP+68->+-----------------------+
5495 | 1 word struct addr | | 1 word struct addr |
5496 +-----------------------+FP+64->+-----------------------+
5498 | 16 word reg save area | | 16 word reg save area |
5500 SP->+-----------------------+ FP->+-----------------------+
5502 | fp/alu reg moves |
5503 FP-16->+-----------------------+
5507 +-----------------------+
5509 | fp register save |
5511 +-----------------------+
5513 | gp register save |
5515 +-----------------------+
5517 | alloca allocations |
5519 +-----------------------+
5521 | arguments on stack |
5523 SP+92->+-----------------------+
5525 | arguments passed |
5526 | in registers, even |
5527 low | if not passed. |
5528 memory SP+68->+-----------------------+
5529 | 1 word struct addr |
5530 SP+64->+-----------------------+
5532 I 16 word reg save area |
5534 SP->+-----------------------+ */
5536 /* Structure to be filled in by sparc_flat_compute_frame_size with register
5537 save masks, and offsets for the current function. */
5539 struct sparc_frame_info
5541 unsigned long total_size; /* # bytes that the entire frame takes up. */
5542 unsigned long var_size; /* # bytes that variables take up. */
5543 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5544 unsigned long extra_size; /* # bytes of extra gunk. */
5545 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5546 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5547 unsigned long gmask; /* Mask of saved gp registers. */
5548 unsigned long fmask; /* Mask of saved fp registers. */
5549 unsigned long reg_offset; /* Offset from new sp to store regs. */
5550 int initialized; /* Nonzero if frame size already calculated. */
5553 /* Current frame information calculated by sparc_flat_compute_frame_size. */
5554 struct sparc_frame_info current_frame_info;
5556 /* Zero structure to initialize current_frame_info. */
5557 struct sparc_frame_info zero_frame_info;
5559 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
5561 #define RETURN_ADDR_REGNUM 15
5562 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
5563 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
5565 #define MUST_SAVE_REGISTER(regno) \
5566 ((regs_ever_live[regno] && !call_used_regs[regno]) \
5567 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
5568 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
5570 /* Return the bytes needed to compute the frame pointer from the current
5574 sparc_flat_compute_frame_size (size)
5575 int size; /* # of var. bytes allocated. */
5578 unsigned long total_size; /* # bytes that the entire frame takes up. */
5579 unsigned long var_size; /* # bytes that variables take up. */
5580 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5581 unsigned long extra_size; /* # extra bytes. */
5582 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5583 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5584 unsigned long gmask; /* Mask of saved gp registers. */
5585 unsigned long fmask; /* Mask of saved fp registers. */
5586 unsigned long reg_offset; /* Offset to register save area. */
5587 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
5589 /* This is the size of the 16 word reg save area, 1 word struct addr
5590 area, and 4 word fp/alu register copy area. */
5591 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
5593 /* Also include the size needed for the 6 parameter registers. */
5594 args_size = current_function_outgoing_args_size + 24;
5595 total_size = var_size + args_size + extra_size;
5603 /* Calculate space needed for gp registers. */
5604 for (regno = 1; regno <= 31; regno++)
5606 if (MUST_SAVE_REGISTER (regno))
5608 /* If we need to save two regs in a row, ensure there's room to bump
5609 up the address to align it to a doubleword boundary. */
5610 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
5612 if (gp_reg_size % 8 != 0)
5614 gp_reg_size += 2 * UNITS_PER_WORD;
5615 gmask |= 3 << regno;
5621 gp_reg_size += UNITS_PER_WORD;
5622 gmask |= 1 << regno;
5627 /* Calculate space needed for fp registers. */
5628 for (regno = 32; regno <= 63; regno++)
5630 if (regs_ever_live[regno] && !call_used_regs[regno])
5632 fp_reg_size += UNITS_PER_WORD;
5633 fmask |= 1 << (regno - 32);
5640 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
5641 /* Ensure save area is 8 byte aligned if we need it. */
5643 if (need_aligned_p && n != 0)
5645 total_size += 8 - n;
5646 reg_offset += 8 - n;
5648 total_size += gp_reg_size + fp_reg_size;
5651 /* ??? This looks a little suspicious. Clarify. */
5652 if (total_size == extra_size)
5653 total_size = extra_size = 0;
5655 total_size = SPARC_STACK_ALIGN (total_size);
5657 /* Save other computed information. */
5658 current_frame_info.total_size = total_size;
5659 current_frame_info.var_size = var_size;
5660 current_frame_info.args_size = args_size;
5661 current_frame_info.extra_size = extra_size;
5662 current_frame_info.gp_reg_size = gp_reg_size;
5663 current_frame_info.fp_reg_size = fp_reg_size;
5664 current_frame_info.gmask = gmask;
5665 current_frame_info.fmask = fmask;
5666 current_frame_info.reg_offset = reg_offset;
5667 current_frame_info.initialized = reload_completed;
5669 /* Ok, we're done. */
5673 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
5676 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
5677 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
5678 [BASE_REG+OFFSET] will always be a valid address.
5680 WORD_OP is either "st" for save, "ld" for restore.
5681 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
5684 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
5685 doubleword_op, base_offset)
5688 unsigned int offset;
5689 unsigned long gmask;
5690 unsigned long fmask;
5692 char *doubleword_op;
5693 unsigned long base_offset;
5697 if (gmask == 0 && fmask == 0)
5700 /* Save registers starting from high to low. We've already saved the
5701 previous frame pointer and previous return address for the debugger's
5702 sake. The debugger allows us to not need a nop in the epilog if at least
5703 one register is reloaded in addition to return address. */
5707 for (regno = 1; regno <= 31; regno++)
5709 if ((gmask & (1L << regno)) != 0)
5711 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
5713 /* We can save two registers in a row. If we're not at a
5714 double word boundary, move to one.
5715 sparc_flat_compute_frame_size ensures there's room to do
5717 if (offset % 8 != 0)
5718 offset += UNITS_PER_WORD;
5720 if (word_op[0] == 's')
5722 fprintf (file, "\t%s\t%s, [%s+%d]\n",
5723 doubleword_op, reg_names[regno],
5725 if (dwarf2out_do_frame ())
5727 char *l = dwarf2out_cfi_label ();
5728 dwarf2out_reg_save (l, regno, offset + base_offset);
5730 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
5734 fprintf (file, "\t%s\t[%s+%d], %s\n",
5735 doubleword_op, base_reg, offset,
5738 offset += 2 * UNITS_PER_WORD;
5743 if (word_op[0] == 's')
5745 fprintf (file, "\t%s\t%s, [%s+%d]\n",
5746 word_op, reg_names[regno],
5748 if (dwarf2out_do_frame ())
5749 dwarf2out_reg_save ("", regno, offset + base_offset);
5752 fprintf (file, "\t%s\t[%s+%d], %s\n",
5753 word_op, base_reg, offset, reg_names[regno]);
5755 offset += UNITS_PER_WORD;
5763 for (regno = 32; regno <= 63; regno++)
5765 if ((fmask & (1L << (regno - 32))) != 0)
5767 if (word_op[0] == 's')
5769 fprintf (file, "\t%s\t%s, [%s+%d]\n",
5770 word_op, reg_names[regno],
5772 if (dwarf2out_do_frame ())
5773 dwarf2out_reg_save ("", regno, offset + base_offset);
5776 fprintf (file, "\t%s\t[%s+%d], %s\n",
5777 word_op, base_reg, offset, reg_names[regno]);
5779 offset += UNITS_PER_WORD;
5785 /* Set up the stack and frame (if desired) for the function. */
5788 sparc_flat_output_function_prologue (file, size)
5792 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5793 unsigned long gmask = current_frame_info.gmask;
5795 /* This is only for the human reader. */
5796 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
5797 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
5799 current_frame_info.var_size,
5800 current_frame_info.gp_reg_size / 4,
5801 current_frame_info.fp_reg_size / 4,
5802 current_function_outgoing_args_size,
5803 current_frame_info.extra_size);
5805 size = SPARC_STACK_ALIGN (size);
5806 size = (! current_frame_info.initialized
5807 ? sparc_flat_compute_frame_size (size)
5808 : current_frame_info.total_size);
5810 /* These cases shouldn't happen. Catch them now. */
5811 if (size == 0 && (gmask || current_frame_info.fmask))
5814 /* Allocate our stack frame by decrementing %sp.
5815 At present, the only algorithm gdb can use to determine if this is a
5816 flat frame is if we always set %i7 if we set %sp. This can be optimized
5817 in the future by putting in some sort of debugging information that says
5818 this is a `flat' function. However, there is still the case of debugging
5819 code without such debugging information (including cases where most fns
5820 have such info, but there is one that doesn't). So, always do this now
5821 so we don't get a lot of code out there that gdb can't handle.
5822 If the frame pointer isn't needn't then that's ok - gdb won't be able to
5823 distinguish us from a non-flat function but there won't (and shouldn't)
5824 be any differences anyway. The return pc is saved (if necessary) right
5825 after %i7 so gdb won't have to look too far to find it. */
5828 unsigned int reg_offset = current_frame_info.reg_offset;
5829 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
5830 char *t1_str = "%g1";
5832 /* Things get a little tricky if local variables take up more than ~4096
5833 bytes and outgoing arguments take up more than ~4096 bytes. When that
5834 happens, the register save area can't be accessed from either end of
5835 the frame. Handle this by decrementing %sp to the start of the gp
5836 register save area, save the regs, update %i7, and then set %sp to its
5837 final value. Given that we only have one scratch register to play
5838 with it is the cheapest solution, and it helps gdb out as it won't
5839 slow down recognition of flat functions.
5840 Don't change the order of insns emitted here without checking with
5841 the gdb folk first. */
5843 /* Is the entire register save area offsettable from %sp? */
5844 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
5848 fprintf (file, "\tadd\t%s, %d, %s\n",
5849 sp_str, -size, sp_str);
5850 if (gmask & FRAME_POINTER_MASK)
5852 fprintf (file, "\tst\t%s, [%s+%d]\n",
5853 fp_str, sp_str, reg_offset);
5854 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
5855 sp_str, -size, fp_str, ASM_COMMENT_START);
5861 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
5862 size, t1_str, sp_str, t1_str, sp_str);
5863 if (gmask & FRAME_POINTER_MASK)
5865 fprintf (file, "\tst\t%s, [%s+%d]\n",
5866 fp_str, sp_str, reg_offset);
5867 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
5868 sp_str, t1_str, fp_str, ASM_COMMENT_START);
5872 if (dwarf2out_do_frame ())
5874 char *l = dwarf2out_cfi_label ();
5875 if (gmask & FRAME_POINTER_MASK)
5877 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
5878 reg_offset - 4 - size);
5879 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
5882 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
5884 if (gmask & RETURN_ADDR_MASK)
5886 fprintf (file, "\tst\t%s, [%s+%d]\n",
5887 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
5888 if (dwarf2out_do_frame ())
5889 dwarf2out_return_save ("", reg_offset - size);
5892 sparc_flat_save_restore (file, sp_str, reg_offset,
5893 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5894 current_frame_info.fmask,
5895 "st", "std", -size);
5899 /* Subtract %sp in two steps, but make sure there is always a
5900 64 byte register save area, and %sp is properly aligned. */
5901 /* Amount to decrement %sp by, the first time. */
5902 unsigned int size1 = ((size - reg_offset + 64) + 15) & -16;
5903 /* Offset to register save area from %sp. */
5904 unsigned int offset = size1 - (size - reg_offset);
5908 fprintf (file, "\tadd\t%s, %d, %s\n",
5909 sp_str, -size1, sp_str);
5910 if (gmask & FRAME_POINTER_MASK)
5912 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
5913 fp_str, sp_str, offset, sp_str, -size1, fp_str,
5920 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
5921 size1, t1_str, sp_str, t1_str, sp_str);
5922 if (gmask & FRAME_POINTER_MASK)
5924 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
5925 fp_str, sp_str, offset, sp_str, t1_str, fp_str,
5930 if (dwarf2out_do_frame ())
5932 char *l = dwarf2out_cfi_label ();
5933 if (gmask & FRAME_POINTER_MASK)
5935 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
5936 offset - 4 - size1);
5937 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
5940 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
5942 if (gmask & RETURN_ADDR_MASK)
5944 fprintf (file, "\tst\t%s, [%s+%d]\n",
5945 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
5946 if (dwarf2out_do_frame ())
5947 /* offset - size1 == reg_offset - size
5948 if reg_offset were updated above like offset. */
5949 dwarf2out_return_save ("", offset - size1);
5952 sparc_flat_save_restore (file, sp_str, offset,
5953 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5954 current_frame_info.fmask,
5955 "st", "std", -size1);
5956 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
5957 size - size1, t1_str, sp_str, t1_str, sp_str);
5958 if (dwarf2out_do_frame ())
5959 if (! (gmask & FRAME_POINTER_MASK))
5960 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
5964 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
5967 /* Do any necessary cleanup after a function to restore stack, frame,
5971 sparc_flat_output_function_epilogue (file, size)
5975 rtx epilogue_delay = current_function_epilogue_delay_list;
5976 int noepilogue = FALSE;
5978 /* This is only for the human reader. */
5979 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
5981 /* The epilogue does not depend on any registers, but the stack
5982 registers, so we assume that if we have 1 pending nop, it can be
5983 ignored, and 2 it must be filled (2 nops occur for integer
5984 multiply and divide). */
5986 size = SPARC_STACK_ALIGN (size);
5987 size = (!current_frame_info.initialized
5988 ? sparc_flat_compute_frame_size (size)
5989 : current_frame_info.total_size);
5991 if (size == 0 && epilogue_delay == 0)
5993 rtx insn = get_last_insn ();
5995 /* If the last insn was a BARRIER, we don't have to write any code
5996 because a jump (aka return) was put there. */
5997 if (GET_CODE (insn) == NOTE)
5998 insn = prev_nonnote_insn (insn);
5999 if (insn && GET_CODE (insn) == BARRIER)
6005 unsigned int reg_offset = current_frame_info.reg_offset;
6007 char *sp_str = reg_names[STACK_POINTER_REGNUM];
6008 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
6009 char *t1_str = "%g1";
6011 /* In the reload sequence, we don't need to fill the load delay
6012 slots for most of the loads, also see if we can fill the final
6013 delay slot if not otherwise filled by the reload sequence. */
6016 fprintf (file, "\tset\t%d, %s\n", size, t1_str);
6018 if (frame_pointer_needed)
6021 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
6022 fp_str, t1_str, sp_str, ASM_COMMENT_START);
6024 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
6025 fp_str, size, sp_str, ASM_COMMENT_START);
6028 /* Is the entire register save area offsettable from %sp? */
6029 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
6035 /* Restore %sp in two steps, but make sure there is always a
6036 64 byte register save area, and %sp is properly aligned. */
6037 /* Amount to increment %sp by, the first time. */
6038 size1 = ((reg_offset - 64 - 16) + 15) & -16;
6039 /* Offset to register save area from %sp. */
6040 reg_offset = size1 - reg_offset;
6042 fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n",
6043 size1, t1_str, sp_str, t1_str, sp_str);
6046 /* We must restore the frame pointer and return address reg first
6047 because they are treated specially by the prologue output code. */
6048 if (current_frame_info.gmask & FRAME_POINTER_MASK)
6050 fprintf (file, "\tld\t[%s+%d], %s\n",
6051 sp_str, reg_offset, fp_str);
6054 if (current_frame_info.gmask & RETURN_ADDR_MASK)
6056 fprintf (file, "\tld\t[%s+%d], %s\n",
6057 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
6061 /* Restore any remaining saved registers. */
6062 sparc_flat_save_restore (file, sp_str, reg_offset,
6063 current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6064 current_frame_info.fmask,
6067 /* If we had to increment %sp in two steps, record it so the second
6068 restoration in the epilogue finishes up. */
6073 fprintf (file, "\tset\t%d, %s\n",
6077 if (current_function_returns_struct)
6078 fprintf (file, "\tjmp\t%%o7+12\n");
6080 fprintf (file, "\tretl\n");
6082 /* If the only register saved is the return address, we need a
6083 nop, unless we have an instruction to put into it. Otherwise
6084 we don't since reloading multiple registers doesn't reference
6085 the register being loaded. */
6091 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
6094 else if (size > 4095)
6095 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
6098 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str);
6101 fprintf (file, "\tnop\n");
6104 /* Reset state info for each function. */
6105 current_frame_info = zero_frame_info;
6107 sparc_output_deferred_case_vectors ();
6110 /* Define the number of delay slots needed for the function epilogue.
6112 On the sparc, we need a slot if either no stack has been allocated,
6113 or the only register saved is the return register. */
6116 sparc_flat_epilogue_delay_slots ()
6118 if (!current_frame_info.initialized)
6119 (void) sparc_flat_compute_frame_size (get_frame_size ());
6121 if (current_frame_info.total_size == 0)
6127 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
6128 Any single length instruction which doesn't reference the stack or frame
6132 sparc_flat_eligible_for_epilogue_delay (trial, slot)
6134 int slot ATTRIBUTE_UNUSED;
6136 rtx pat = PATTERN (trial);
6138 if (get_attr_length (trial) != 1)
6141 /* If %g0 is live, there are lots of things we can't handle.
6142 Rather than trying to find them all now, let's punt and only
6143 optimize things as necessary. */
6147 if (! reg_mentioned_p (stack_pointer_rtx, pat)
6148 && ! reg_mentioned_p (frame_pointer_rtx, pat))
6154 /* Adjust the cost of a scheduling dependency. Return the new cost of
6155 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6158 supersparc_adjust_cost (insn, link, dep_insn, cost)
6164 enum attr_type insn_type;
6166 if (! recog_memoized (insn))
6169 insn_type = get_attr_type (insn);
6171 if (REG_NOTE_KIND (link) == 0)
6173 /* Data dependency; DEP_INSN writes a register that INSN reads some
6176 /* if a load, then the dependence must be on the memory address;
6177 add an extra "cycle". Note that the cost could be two cycles
6178 if the reg was written late in an instruction group; we ca not tell
6180 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
6183 /* Get the delay only if the address of the store is the dependence. */
6184 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
6186 rtx pat = PATTERN(insn);
6187 rtx dep_pat = PATTERN (dep_insn);
6189 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6190 return cost; /* This should not happen! */
6192 /* The dependency between the two instructions was on the data that
6193 is being stored. Assume that this implies that the address of the
6194 store is not dependent. */
6195 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6198 return cost + 3; /* An approximation. */
6201 /* A shift instruction cannot receive its data from an instruction
6202 in the same cycle; add a one cycle penalty. */
6203 if (insn_type == TYPE_SHIFT)
6204 return cost + 3; /* Split before cascade into shift. */
6208 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
6209 INSN writes some cycles later. */
6211 /* These are only significant for the fpu unit; writing a fp reg before
6212 the fpu has finished with it stalls the processor. */
6214 /* Reusing an integer register causes no problems. */
6215 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
6222 /* This describes the state of the UltraSPARC pipeline during
6223 instruction scheduling. */
6225 #define TMASK(__x) ((unsigned)1 << ((int)(__x)))
6226 #define UMASK(__x) ((unsigned)1 << ((int)(__x)))
6228 enum ultra_code { NONE=0, /* no insn at all */
6229 IEU0, /* shifts and conditional moves */
6230 IEU1, /* condition code setting insns, calls+jumps */
6231 IEUN, /* all other single cycle ieu insns */
6232 LSU, /* loads and stores */
6234 FPM, /* FPU pipeline 1, multiplies and divides */
6235 FPA, /* FPU pipeline 2, all other operations */
6236 SINGLE, /* single issue instructions */
6239 static char *ultra_code_names[NUM_ULTRA_CODES] = {
6240 "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI",
6241 "FPM", "FPA", "SINGLE" };
6243 struct ultrasparc_pipeline_state {
6244 /* The insns in this group. */
6247 /* The code for each insn. */
6248 enum ultra_code codes[4];
6250 /* Which insns in this group have been committed by the
6251 scheduler. This is how we determine how many more
6252 can issue this cycle. */
6255 /* How many insns in this group. */
6258 /* Mask of free slots still in this group. */
6259 char free_slot_mask;
6261 /* The slotter uses the following to determine what other
6262 insn types can still make their way into this group. */
6263 char contents [NUM_ULTRA_CODES];
6267 #define ULTRA_NUM_HIST 8
6268 static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST];
6269 static int ultra_cur_hist;
6270 static int ultra_cycles_elapsed;
6272 #define ultra_pipe (ultra_pipe_hist[ultra_cur_hist])
6274 /* Given TYPE_MASK compute the ultra_code it has. */
6275 static enum ultra_code
6276 ultra_code_from_mask (type_mask)
6279 if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE)))
6281 else if (type_mask & (TMASK (TYPE_COMPARE) |
6283 TMASK (TYPE_UNCOND_BRANCH)))
6285 else if (type_mask & (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
6286 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY)))
6288 else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
6289 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
6290 TMASK (TYPE_FPSTORE)))
6292 else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) |
6293 TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRT)))
6295 else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
6296 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)))
6298 else if (type_mask & TMASK (TYPE_BRANCH))
6304 /* Check INSN (a conditional move) and make sure that it's
6305 results are available at this cycle. Return 1 if the
6306 results are in fact ready. */
6308 ultra_cmove_results_ready_p (insn)
6311 struct ultrasparc_pipeline_state *up;
6314 /* If this got dispatched in the previous
6315 group, the results are not ready. */
6316 entry = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1);
6317 up = &ultra_pipe_hist[entry];
6320 if (up->group[slot] == insn)
6326 /* Walk backwards in pipeline history looking for FPU
6327 operations which use a mode different than FPMODE and
6328 will create a stall if an insn using FPMODE were to be
6329 dispatched this cycle. */
6331 ultra_fpmode_conflict_exists (fpmode)
6332 enum machine_mode fpmode;
6337 hist_ent = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1);
6338 if (ultra_cycles_elapsed < 4)
6339 hist_lim = ultra_cycles_elapsed;
6342 while (hist_lim > 0)
6344 struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent];
6349 rtx insn = up->group[slot];
6350 enum machine_mode this_mode;
6354 || GET_CODE (insn) != INSN
6355 || (pat = PATTERN (insn)) == 0
6356 || GET_CODE (pat) != SET)
6359 this_mode = GET_MODE (SET_DEST (pat));
6360 if ((this_mode != SFmode
6361 && this_mode != DFmode)
6362 || this_mode == fpmode)
6365 /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then
6366 we will get a stall. Loads and stores are independant
6368 if (GET_CODE (SET_SRC (pat)) != ABS
6369 && GET_CODE (SET_SRC (pat)) != NEG
6370 && ((TMASK (get_attr_type (insn)) &
6371 (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) |
6372 TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRT) |
6373 TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0))
6377 hist_ent = (hist_ent - 1) % (ULTRA_NUM_HIST - 1);
6380 /* No conflicts, safe to dispatch. */
6384 /* Find an instruction in LIST which has one of the
6385 type attributes enumerated in TYPE_MASK. START
6386 says where to begin the search.
6388 NOTE: This scheme depends upon the fact that we
6389 have less than 32 distinct type attributes. */
6391 static int ultra_types_avail;
6394 ultra_find_type (type_mask, list, start)
6401 /* Short circuit if no such insn exists in the ready
6403 if ((type_mask & ultra_types_avail) == 0)
6406 for (i = start; i >= 0; i--)
6410 if (recog_memoized (insn) >= 0
6411 && (TMASK(get_attr_type (insn)) & type_mask))
6413 enum machine_mode fpmode = SFmode;
6416 int check_depend = 0;
6417 int check_fpmode_conflict = 0;
6419 if (GET_CODE (insn) == INSN
6420 && (pat = PATTERN(insn)) != 0
6421 && GET_CODE (pat) == SET
6422 && !(type_mask & (TMASK (TYPE_STORE) |
6423 TMASK (TYPE_FPSTORE))))
6426 if (GET_MODE (SET_DEST (pat)) == SFmode
6427 || GET_MODE (SET_DEST (pat)) == DFmode)
6429 fpmode = GET_MODE (SET_DEST (pat));
6430 check_fpmode_conflict = 1;
6437 rtx slot_insn = ultra_pipe.group[slot];
6440 /* Already issued, bad dependency, or FPU
6443 && (slot_pat = PATTERN (slot_insn)) != 0
6444 && ((insn == slot_insn)
6445 || (check_depend == 1
6446 && GET_CODE (slot_insn) == INSN
6447 && GET_CODE (slot_pat) == SET
6448 && ((GET_CODE (SET_DEST (slot_pat)) == REG
6449 && GET_CODE (SET_SRC (pat)) == REG
6450 && REGNO (SET_DEST (slot_pat)) ==
6451 REGNO (SET_SRC (pat)))
6452 || (GET_CODE (SET_DEST (slot_pat)) == SUBREG
6453 && GET_CODE (SET_SRC (pat)) == SUBREG
6454 && REGNO (SUBREG_REG (SET_DEST (slot_pat))) ==
6455 REGNO (SUBREG_REG (SET_SRC (pat)))
6456 && SUBREG_WORD (SET_DEST (slot_pat)) ==
6457 SUBREG_WORD (SET_SRC (pat)))))
6458 || (check_fpmode_conflict == 1
6459 && GET_CODE (slot_insn) == INSN
6460 && GET_CODE (slot_pat) == SET
6461 && (GET_MODE (SET_DEST (slot_pat)) == SFmode
6462 || GET_MODE (SET_DEST (slot_pat)) == DFmode)
6463 && GET_MODE (SET_DEST (slot_pat)) != fpmode)))
6467 /* Check for peculiar result availability and dispatch
6468 interference situations. */
6470 && ultra_cycles_elapsed > 0)
6474 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6476 rtx link_insn = XEXP (link, 0);
6477 if (GET_CODE (link_insn) == INSN
6478 && recog_memoized (link_insn) >= 0
6479 && (TMASK (get_attr_type (link_insn)) &
6480 (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE)))
6481 && ! ultra_cmove_results_ready_p (link_insn))
6485 if (check_fpmode_conflict
6486 && ultra_fpmode_conflict_exists (fpmode))
6499 ultra_build_types_avail (ready, n_ready)
6503 int i = n_ready - 1;
6505 ultra_types_avail = 0;
6508 rtx insn = ready[i];
6510 if (recog_memoized (insn) >= 0)
6511 ultra_types_avail |= TMASK (get_attr_type (insn));
6517 /* Place insn pointed to my IP into the pipeline.
6518 Make element THIS of READY be that insn if it
6519 is not already. TYPE indicates the pipeline class
6520 this insn falls into. */
6522 ultra_schedule_insn (ip, ready, this, type)
6526 enum ultra_code type;
6529 char mask = ultra_pipe.free_slot_mask;
6531 /* Obtain free slot. */
6532 for (pipe_slot = 0; pipe_slot < 4; pipe_slot++)
6533 if ((mask & (1 << pipe_slot)) != 0)
6538 /* In it goes, and it hasn't been committed yet. */
6539 ultra_pipe.group[pipe_slot] = *ip;
6540 ultra_pipe.codes[pipe_slot] = type;
6541 ultra_pipe.contents[type] = 1;
6543 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
6544 ultra_pipe.num_ieu_insns += 1;
6546 ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot));
6547 ultra_pipe.group_size += 1;
6548 ultra_pipe.commit[pipe_slot] = 0;
6550 /* Update ready list. */
6551 if (ip != &ready[this])
6560 /* Advance to the next pipeline group. */
6562 ultra_flush_pipeline ()
6564 ultra_cur_hist = (ultra_cur_hist + 1) % (ULTRA_NUM_HIST - 1);
6565 ultra_cycles_elapsed += 1;
6566 bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
6567 ultra_pipe.free_slot_mask = 0xf;
6570 static int ultra_reorder_called_this_block;
6572 /* Init our data structures for this current block. */
6574 ultrasparc_sched_init (dump, sched_verbose)
6575 FILE *dump ATTRIBUTE_UNUSED;
6576 int sched_verbose ATTRIBUTE_UNUSED;
6578 bzero ((char *) ultra_pipe_hist, sizeof ultra_pipe_hist);
6580 ultra_cycles_elapsed = 0;
6581 ultra_reorder_called_this_block = 0;
6582 ultra_pipe.free_slot_mask = 0xf;
6585 /* INSN has been scheduled, update pipeline commit state
6586 and return how many instructions are still to be
6587 scheduled in this group. */
6589 ultrasparc_variable_issue (insn)
6592 struct ultrasparc_pipeline_state *up = &ultra_pipe;
6593 int i, left_to_fire;
6596 for (i = 0; i < 4; i++)
6598 if (up->group[i] == 0)
6601 if (up->group[i] == insn)
6605 else if (! up->commit[i])
6609 return left_to_fire;
6612 /* In actual_hazard_this_instance, we may have yanked some
6613 instructions from the ready list due to conflict cost
6614 adjustments. If so, and such an insn was in our pipeline
6615 group, remove it and update state. */
6617 ultra_rescan_pipeline_state (ready, n_ready)
6621 struct ultrasparc_pipeline_state *up = &ultra_pipe;
6624 for (i = 0; i < 4; i++)
6626 rtx insn = up->group[i];
6632 /* If it has been committed, then it was removed from
6633 the ready list because it was actually scheduled,
6634 and that is not the case we are searching for here. */
6635 if (up->commit[i] != 0)
6638 for (j = n_ready - 1; j >= 0; j--)
6639 if (ready[j] == insn)
6642 /* If we didn't find it, toss it. */
6645 enum ultra_code ucode = up->codes[i];
6648 up->codes[i] = NONE;
6649 up->contents[ucode] = 0;
6651 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
6652 up->num_ieu_insns -= 1;
6654 up->free_slot_mask |= (1 << i);
6655 up->group_size -= 1;
6662 ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
6668 struct ultrasparc_pipeline_state *up = &ultra_pipe;
6671 /* We get called once unnecessarily per block of insns
6673 if (ultra_reorder_called_this_block == 0)
6675 ultra_reorder_called_this_block = 1;
6683 fprintf (dump, "\n;;\tUltraSPARC Looking at [");
6684 for (n = n_ready - 1; n >= 0; n--)
6686 rtx insn = ready[n];
6687 enum ultra_code ucode;
6689 if (recog_memoized (insn) < 0)
6691 ucode = ultra_code_from_mask (TMASK (get_attr_type (insn)));
6693 fprintf (dump, "%s(%d) ",
6694 ultra_code_names[ucode],
6697 fprintf (dump, "%s(%d)",
6698 ultra_code_names[ucode],
6701 fprintf (dump, "]\n");
6704 this_insn = n_ready - 1;
6706 /* Skip over junk we don't understand. */
6707 while ((this_insn >= 0)
6708 && recog_memoized (ready[this_insn]) < 0)
6711 ultra_build_types_avail (ready, this_insn + 1);
6713 while (this_insn >= 0) {
6714 int old_group_size = up->group_size;
6716 if (up->group_size != 0)
6720 num_committed = (up->commit[0] + up->commit[1] +
6721 up->commit[2] + up->commit[3]);
6722 /* If nothing has been commited from our group, or all of
6723 them have. Clear out the (current cycle's) pipeline
6724 state and start afresh. */
6725 if (num_committed == 0
6726 || num_committed == up->group_size)
6728 ultra_flush_pipeline ();
6734 /* OK, some ready list insns got requeued and thus removed
6735 from the ready list. Account for this fact. */
6736 ultra_rescan_pipeline_state (ready, n_ready);
6738 /* Something "changed", make this look like a newly
6739 formed group so the code at the end of the loop
6740 knows that progress was in fact made. */
6741 if (up->group_size != old_group_size)
6746 if (up->group_size == 0)
6748 /* If the pipeline is (still) empty and we have any single
6749 group insns, get them out now as this is a good time. */
6750 rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_ADDRESS) |
6751 TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) |
6752 TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)),
6756 ultra_schedule_insn (ip, ready, this_insn, SINGLE);
6760 /* If we are not in the process of emptying out the pipe, try to
6761 obtain an instruction which must be the first in it's group. */
6762 ip = ultra_find_type ((TMASK (TYPE_CALL) |
6763 TMASK (TYPE_CALL_NO_DELAY_SLOT) |
6764 TMASK (TYPE_UNCOND_BRANCH)),
6768 ultra_schedule_insn (ip, ready, this_insn, IEU1);
6771 else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) |
6772 TMASK (TYPE_FPDIVD) |
6773 TMASK (TYPE_FPSQRT)),
6774 ready, this_insn)) != 0)
6776 ultra_schedule_insn (ip, ready, this_insn, FPM);
6781 /* Try to fill the integer pipeline. First, look for an IEU0 specific
6782 operation. We can't do more IEU operations if the first 3 slots are
6783 all full or we have dispatched two IEU insns already. */
6784 if ((up->free_slot_mask & 0x7) != 0
6785 && up->num_ieu_insns < 2
6786 && up->contents[IEU0] == 0
6787 && up->contents[IEUN] == 0)
6789 rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn);
6792 ultra_schedule_insn (ip, ready, this_insn, IEU0);
6797 /* If we can, try to find an IEU1 specific or an unnamed
6799 if ((up->free_slot_mask & 0x7) != 0
6800 && up->num_ieu_insns < 2)
6802 rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
6803 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY) |
6804 (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)),
6810 ultra_schedule_insn (ip, ready, this_insn,
6811 (!up->contents[IEU1]
6812 && get_attr_type (insn) == TYPE_COMPARE)
6818 /* If only one IEU insn has been found, try to find another unnamed
6819 IEU operation or an IEU1 specific one. */
6820 if ((up->free_slot_mask & 0x7) != 0
6821 && up->num_ieu_insns < 2)
6824 int tmask = (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
6825 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY));
6827 if (!up->contents[IEU1])
6828 tmask |= TMASK (TYPE_COMPARE);
6829 ip = ultra_find_type (tmask, ready, this_insn);
6834 ultra_schedule_insn (ip, ready, this_insn,
6835 (!up->contents[IEU1]
6836 && get_attr_type (insn) == TYPE_COMPARE)
6842 /* Try for a load or store, but such an insn can only be issued
6843 if it is within' one of the first 3 slots. */
6844 if ((up->free_slot_mask & 0x7) != 0
6845 && up->contents[LSU] == 0)
6847 rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
6848 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
6849 TMASK (TYPE_FPSTORE)), ready, this_insn);
6852 ultra_schedule_insn (ip, ready, this_insn, LSU);
6857 /* Now find FPU operations, first FPM class. But not divisions or
6858 square-roots because those will break the group up. Unlike all
6859 the previous types, these can go in any slot. */
6860 if (up->free_slot_mask != 0
6861 && up->contents[FPM] == 0)
6863 rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn);
6866 ultra_schedule_insn (ip, ready, this_insn, FPM);
6871 /* Continue on with FPA class if we have not filled the group already. */
6872 if (up->free_slot_mask != 0
6873 && up->contents[FPA] == 0)
6875 rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
6876 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)),
6880 ultra_schedule_insn (ip, ready, this_insn, FPA);
6885 /* Finally, maybe stick a branch in here. */
6886 if (up->free_slot_mask != 0
6887 && up->contents[CTI] == 0)
6889 rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn);
6891 /* Try to slip in a branch only if it is one of the
6892 next 2 in the ready list. */
6893 if (ip && ((&ready[this_insn] - ip) < 2))
6895 ultra_schedule_insn (ip, ready, this_insn, CTI);
6901 for (i = 0; i < 4; i++)
6902 if ((up->free_slot_mask & (1 << i)) == 0)
6905 /* See if we made any progress... */
6906 if (old_group_size != up->group_size)
6909 /* Clean out the (current cycle's) pipeline state
6910 and try once more. If we placed no instructions
6911 into the pipeline at all, it means a real hard
6912 conflict exists with some earlier issued instruction
6913 so we must advance to the next cycle to clear it up. */
6914 if (up->group_size == 0)
6916 ultra_flush_pipeline ();
6921 bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
6922 ultra_pipe.free_slot_mask = 0xf;
6930 fprintf (dump, ";;\tUltraSPARC Launched [");
6931 gsize = up->group_size;
6932 for (n = 0; n < 4; n++)
6934 rtx insn = up->group[n];
6941 fprintf (dump, "%s(%d) ",
6942 ultra_code_names[up->codes[n]],
6945 fprintf (dump, "%s(%d)",
6946 ultra_code_names[up->codes[n]],
6949 fprintf (dump, "]\n");
6954 ultrasparc_adjust_cost (insn, link, dep_insn, cost)
6960 enum attr_type insn_type, dep_type;
6961 rtx pat = PATTERN(insn);
6962 rtx dep_pat = PATTERN (dep_insn);
6964 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
6967 insn_type = get_attr_type (insn);
6968 dep_type = get_attr_type (dep_insn);
6970 /* Nothing issues in parallel with integer multiplies, so
6971 mark as zero cost since the scheduler can not do anything
6973 if (insn_type == TYPE_IMUL)
6976 #define SLOW_FP(dep_type) \
6977 (dep_type == TYPE_FPSQRT || dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
6979 switch (REG_NOTE_KIND (link))
6982 /* Data dependency; DEP_INSN writes a register that INSN reads some
6985 if (dep_type == TYPE_CMOVE)
6987 /* Instructions that read the result of conditional moves cannot
6988 be in the same group or the following group. */
6994 /* UltraSPARC can dual issue a store and an instruction setting
6995 the value stored, except for divide and square root. */
6997 if (! SLOW_FP (dep_type))
7002 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7005 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7006 /* The dependency between the two instructions is on the data
7007 that is being stored. Assume that the address of the store
7008 is not also dependent. */
7015 /* A load does not return data until at least 11 cycles after
7016 a store to the same location. 3 cycles are accounted for
7017 in the load latency; add the other 8 here. */
7018 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7020 /* If the addresses are not equal this may be a false
7021 dependency because pointer aliasing could not be
7022 determined. Add only 2 cycles in that case. 2 is
7023 an arbitrary compromise between 8, which would cause
7024 the scheduler to generate worse code elsewhere to
7025 compensate for a dependency which might not really
7027 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7028 || GET_CODE (SET_SRC (pat)) != MEM
7029 || GET_CODE (SET_DEST (dep_pat)) != MEM
7030 || ! rtx_equal_p (XEXP (SET_SRC (pat), 0),
7031 XEXP (SET_DEST (dep_pat), 0)))
7039 /* Compare to branch latency is 0. There is no benefit from
7040 separating compare and branch. */
7041 if (dep_type == TYPE_COMPARE)
7043 /* Floating point compare to branch latency is less than
7044 compare to conditional move. */
7045 if (dep_type == TYPE_FPCMP)
7050 /* FMOVR class instructions can not issue in the same cycle
7051 or the cycle after an instruction which writes any
7052 integer register. Model this as cost 2 for dependent
7054 if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY
7055 || dep_type == TYPE_BINARY)
7058 /* Otherwise check as for integer conditional moves. */
7061 /* Conditional moves involving integer registers wait until
7062 3 cycles after loads return data. The interlock applies
7063 to all loads, not just dependent loads, but that is hard
7065 if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD)
7075 /* Divide and square root lock destination registers for full latency. */
7076 if (! SLOW_FP (dep_type))
7080 case REG_DEP_OUTPUT:
7081 /* IEU and FPU instruction that have the same destination
7082 register cannot be grouped together. */
7089 /* Other costs not accounted for:
7090 - Single precision floating point loads lock the other half of
7091 the even/odd register pair.
7092 - Several hazards associated with ldd/std are ignored because these
7093 instructions are rarely generated for V9.
7094 - The floating point pipeline can not have both a single and double
7095 precision operation active at the same time. Format conversions
7096 and graphics instructions are given honorary double precision status.
7097 - call and jmpl are always the first instruction in a group. */
7110 /* Assume V9 processors are capable of at least dual-issue. */
7112 case PROCESSOR_SUPERSPARC:
7114 case PROCESSOR_ULTRASPARC:
7120 set_extends(x, insn)
7123 register rtx pat = PATTERN (insn);
7125 switch (GET_CODE (SET_SRC (pat)))
7127 /* Load and some shift instructions zero extend. */
7130 /* sethi clears the high bits */
7132 /* LO_SUM is used with sethi. sethi cleared the high
7133 bits and the values used with lo_sum are positive */
7135 /* Store flag stores 0 or 1 */
7145 rtx op1 = XEXP (SET_SRC (pat), 1);
7146 if (GET_CODE (op1) == CONST_INT)
7147 return INTVAL (op1) >= 0;
7148 if (GET_CODE (XEXP (SET_SRC (pat), 0)) == REG
7149 && sparc_check_64 (XEXP (SET_SRC (pat), 0), insn) == 1)
7151 if (GET_CODE (op1) == REG
7152 && sparc_check_64 ((op1), insn) == 1)
7157 return GET_MODE (SET_SRC (pat)) == SImode;
7158 /* Positive integers leave the high bits zero. */
7160 return ! (CONST_DOUBLE_LOW (x) & 0x80000000);
7162 return ! (INTVAL (x) & 0x80000000);
7165 return - (GET_MODE (SET_SRC (pat)) == SImode);
7171 /* We _ought_ to have only one kind per function, but... */
7172 static rtx sparc_addr_diff_list;
7173 static rtx sparc_addr_list;
7176 sparc_defer_case_vector (lab, vec, diff)
7180 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7182 sparc_addr_diff_list
7183 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7185 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7189 sparc_output_addr_vec (vec)
7192 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7193 int idx, vlen = XVECLEN (body, 0);
7195 #ifdef ASM_OUTPUT_CASE_LABEL
7196 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7199 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7202 for (idx = 0; idx < vlen; idx++)
7204 ASM_OUTPUT_ADDR_VEC_ELT
7205 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7210 sparc_output_addr_diff_vec (vec)
7213 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7214 rtx base = XEXP (XEXP (body, 0), 0);
7215 int idx, vlen = XVECLEN (body, 1);
7217 #ifdef ASM_OUTPUT_CASE_LABEL
7218 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7221 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7224 for (idx = 0; idx < vlen; idx++)
7226 ASM_OUTPUT_ADDR_DIFF_ELT
7229 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7230 CODE_LABEL_NUMBER (base));
7235 sparc_output_deferred_case_vectors ()
7239 /* Align to cache line in the function's code section. */
7240 function_section (current_function_decl);
7241 ASM_OUTPUT_ALIGN (asm_out_file, 5);
7243 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7244 sparc_output_addr_vec (XEXP (t, 0));
7245 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7246 sparc_output_addr_diff_vec (XEXP (t, 0));
7248 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7251 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7252 unknown. Return 1 if the high bits are zero, -1 if the register is
7255 sparc_check_64 (x, insn)
7258 /* If a register is set only once it is safe to ignore insns this
7259 code does not know how to handle. The loop will either recognize
7260 the single set and return the correct value or fail to recognize
7264 if (GET_CODE (x) == REG
7265 && flag_expensive_optimizations
7266 && REG_N_SETS (REGNO (x)) == 1)
7272 insn = get_last_insn_anywhere ();
7277 while ((insn = PREV_INSN (insn)))
7279 switch (GET_CODE (insn))
7292 rtx pat = PATTERN (insn);
7293 if (GET_CODE (pat) != SET)
7295 if (rtx_equal_p (x, SET_DEST (pat)))
7296 return set_extends (x, insn);
7297 if (reg_overlap_mentioned_p (SET_DEST (pat), x))
7306 sparc_v8plus_shift (operands, insn, opcode)
7311 static char asm_code[60];
7313 if (GET_CODE (operands[3]) == SCRATCH)
7314 operands[3] = operands[0];
7315 if (GET_CODE (operands[1]) == CONST_INT)
7317 output_asm_insn ("mov %1,%3", operands);
7321 output_asm_insn ("sllx %H1,32,%3", operands);
7322 if (sparc_check_64 (operands[1], insn) <= 0)
7323 output_asm_insn ("srl %L1,0,%L1", operands);
7324 output_asm_insn ("or %L1,%3,%3", operands);
7327 strcpy(asm_code, opcode);
7328 if (which_alternative != 2)
7329 return strcat (asm_code, " %0,%2,%L0\n\tsrlx %L0,32,%H0");
7331 return strcat (asm_code, " %3,%2,%3\n\tsrlx %3,32,%H0\n\tmov %3,%L0");
7335 /* Return 1 if DEST and SRC reference only global and in registers. */
7338 sparc_return_peephole_ok (dest, src)
7345 if (GET_CODE (src) != CONST_INT
7346 && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src)))
7348 return IN_OR_GLOBAL_P (dest);