1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
41 /* 1 if the caller has placed an "unimp" insn immediately after the call.
42 This is used in v8 code when calling a function that returns a structure.
43 v9 doesn't have this. Be careful to have this test be the same as that
46 #define SKIP_CALLERS_UNIMP_P \
47 (!TARGET_ARCH64 && current_function_returns_struct \
48 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
49 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
52 /* Global variables for machine-dependent things. */
54 /* Size of frame. Need to know this to emit return insns from leaf procedures.
55 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
56 reload pass. This is important as the value is later used in insn
57 scheduling (to see what can go in a delay slot).
58 APPARENT_FSIZE is the size of the stack less the register save area and less
59 the outgoing argument area. It is used when saving call preserved regs. */
60 static int apparent_fsize;
61 static int actual_fsize;
63 /* Save the operands last given to a compare for use when we
64 generate a scc or bcc insn. */
66 rtx sparc_compare_op0, sparc_compare_op1;
68 /* We may need an epilogue if we spill too many registers.
69 If this is non-zero, then we branch here for the epilogue. */
70 static rtx leaf_label;
74 /* Vector to say how input registers are mapped to output
75 registers. FRAME_POINTER_REGNUM cannot be remapped by
76 this function to eliminate it. You must use -fomit-frame-pointer
78 char leaf_reg_remap[] =
79 { 0, 1, 2, 3, 4, 5, 6, 7,
80 -1, -1, -1, -1, -1, -1, 14, -1,
81 -1, -1, -1, -1, -1, -1, -1, -1,
82 8, 9, 10, 11, 12, 13, -1, 15,
84 32, 33, 34, 35, 36, 37, 38, 39,
85 40, 41, 42, 43, 44, 45, 46, 47,
86 48, 49, 50, 51, 52, 53, 54, 55,
87 56, 57, 58, 59, 60, 61, 62, 63,
88 64, 65, 66, 67, 68, 69, 70, 71,
89 72, 73, 74, 75, 76, 77, 78, 79,
90 80, 81, 82, 83, 84, 85, 86, 87,
91 88, 89, 90, 91, 92, 93, 94, 95,
96 /* Name of where we pretend to think the frame pointer points.
97 Normally, this is "%fp", but if we are in a leaf procedure,
98 this is "%sp+something". We record "something" separately as it may be
99 too big for reg+constant addressing. */
101 static char *frame_base_name;
102 static int frame_base_offset;
104 static rtx pic_setup_code PROTO((void));
105 static void sparc_init_modes PROTO((void));
106 static int save_regs PROTO((FILE *, int, int, char *,
108 static int restore_regs PROTO((FILE *, int, int, char *, int, int));
109 static void build_big_number PROTO((FILE *, int, char *));
110 static int function_arg_slotno PROTO((const CUMULATIVE_ARGS *,
111 enum machine_mode, tree, int, int,
113 static void sparc_output_addr_vec PROTO((rtx));
114 static void sparc_output_addr_diff_vec PROTO((rtx));
115 static void sparc_output_deferred_case_vectors PROTO((void));
118 #ifdef DWARF2_DEBUGGING_INFO
119 extern char *dwarf2out_cfi_label ();
122 /* Option handling. */
124 /* Code model option as passed by user. */
125 char *sparc_cmodel_string;
127 enum cmodel sparc_cmodel;
129 /* Record alignment options as passed by user. */
130 char *sparc_align_loops_string;
131 char *sparc_align_jumps_string;
132 char *sparc_align_funcs_string;
134 /* Parsed values, as a power of two. */
135 int sparc_align_loops;
136 int sparc_align_jumps;
137 int sparc_align_funcs;
139 struct sparc_cpu_select sparc_select[] =
141 /* switch name, tune arch */
142 { (char *)0, "default", 1, 1 },
143 { (char *)0, "-mcpu=", 1, 1 },
144 { (char *)0, "-mtune=", 1, 0 },
148 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
149 enum processor_type sparc_cpu;
151 /* Validate and override various options, and do some machine dependent
155 sparc_override_options ()
157 static struct code_model {
162 { "medlow", CM_MEDLOW },
163 { "medmid", CM_MEDMID },
164 { "medany", CM_MEDANY },
165 { "embmedany", CM_EMBMEDANY },
168 struct code_model *cmodel;
169 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
170 static struct cpu_default {
174 /* There must be one entry here for each TARGET_CPU value. */
175 { TARGET_CPU_sparc, "cypress" },
176 { TARGET_CPU_sparclet, "tsc701" },
177 { TARGET_CPU_sparclite, "f930" },
178 { TARGET_CPU_v8, "v8" },
179 { TARGET_CPU_supersparc, "supersparc" },
180 { TARGET_CPU_v9, "v9" },
181 { TARGET_CPU_ultrasparc, "ultrasparc" },
184 struct cpu_default *def;
185 /* Table of values for -m{cpu,tune}=. */
186 static struct cpu_table {
188 enum processor_type processor;
192 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
193 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
194 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
195 /* TI TMS390Z55 supersparc */
196 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
197 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
198 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
199 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
200 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
201 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
202 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
204 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
205 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
207 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 },
210 struct cpu_table *cpu;
211 struct sparc_cpu_select *sel;
214 #ifndef SPARC_BI_ARCH
215 /* Check for unsupported architecture size. */
216 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
218 error ("%s is not supported by this configuration",
219 DEFAULT_ARCH32_P ? "-m64" : "-m32");
223 /* Code model selection. */
224 sparc_cmodel = SPARC_DEFAULT_CMODEL;
225 if (sparc_cmodel_string != NULL)
229 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
230 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
232 if (cmodel->name == NULL)
233 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
235 sparc_cmodel = cmodel->value;
238 error ("-mcmodel= is not supported on 32 bit systems");
241 fpu = TARGET_FPU; /* save current -mfpu status */
243 /* Set the default CPU. */
244 for (def = &cpu_default[0]; def->name; ++def)
245 if (def->cpu == TARGET_CPU_DEFAULT)
249 sparc_select[0].string = def->name;
251 for (sel = &sparc_select[0]; sel->name; ++sel)
255 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
256 if (! strcmp (sel->string, cpu->name))
259 sparc_cpu = cpu->processor;
263 target_flags &= ~cpu->disable;
264 target_flags |= cpu->enable;
270 error ("bad value (%s) for %s switch", sel->string, sel->name);
274 /* If -mfpu or -mno-fpu was explicitly used, don't override with
275 the processor default. */
277 target_flags = (target_flags & ~MASK_FPU) | fpu;
279 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
280 if (TARGET_V9 && TARGET_ARCH32)
281 target_flags |= MASK_DEPRECATED_V8_INSNS;
283 /* V8PLUS requires V9 */
285 target_flags &= ~MASK_V8PLUS;
287 /* Don't use stack biasing in 32 bit mode. */
289 target_flags &= ~MASK_STACK_BIAS;
291 /* Validate -malign-loops= value, or provide default. */
292 if (sparc_align_loops_string)
294 sparc_align_loops = exact_log2 (atoi (sparc_align_loops_string));
295 if (sparc_align_loops < 2 || sparc_align_loops > 7)
296 fatal ("-malign-loops=%s is not between 4 and 128 or is not a power of two",
297 sparc_align_loops_string);
301 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
302 its 0. This sounds a bit kludgey. */
303 sparc_align_loops = 0;
306 /* Validate -malign-jumps= value, or provide default. */
307 if (sparc_align_jumps_string)
309 sparc_align_jumps = exact_log2 (atoi (sparc_align_jumps_string));
310 if (sparc_align_jumps < 2 || sparc_align_loops > 7)
311 fatal ("-malign-jumps=%s is not between 4 and 128 or is not a power of two",
312 sparc_align_jumps_string);
316 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
317 its 0. This sounds a bit kludgey. */
318 sparc_align_jumps = 0;
321 /* Validate -malign-functions= value, or provide default. */
322 if (sparc_align_funcs_string)
324 sparc_align_funcs = exact_log2 (atoi (sparc_align_funcs_string));
325 if (sparc_align_funcs < 2 || sparc_align_loops > 7)
326 fatal ("-malign-functions=%s is not between 4 and 128 or is not a power of two",
327 sparc_align_funcs_string);
330 sparc_align_funcs = DEFAULT_SPARC_ALIGN_FUNCS;
332 /* Validate PCC_STRUCT_RETURN. */
333 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
334 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
336 /* Do various machine dependent initializations. */
340 /* Miscellaneous utilities. */
342 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
343 or branch on register contents instructions. */
349 return (code == EQ || code == NE || code == GE || code == LT
350 || code == LE || code == GT);
354 /* Operand constraints. */
356 /* Return non-zero only if OP is a register of mode MODE,
357 or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because
358 %g0 may contain anything. */
361 reg_or_0_operand (op, mode)
363 enum machine_mode mode;
365 if (register_operand (op, mode))
369 if (op == const0_rtx)
371 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
372 && CONST_DOUBLE_HIGH (op) == 0
373 && CONST_DOUBLE_LOW (op) == 0)
375 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
376 && GET_CODE (op) == CONST_DOUBLE
377 && fp_zero_operand (op))
382 /* Nonzero if OP is a floating point value with value 0.0. */
390 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
391 return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r));
394 /* Nonzero if OP is an integer register. */
397 intreg_operand (op, mode)
399 enum machine_mode mode ATTRIBUTE_UNUSED;
401 return (register_operand (op, SImode)
402 || (TARGET_ARCH64 && register_operand (op, DImode)));
405 /* Nonzero if OP is a floating point condition code register. */
408 fcc_reg_operand (op, mode)
410 enum machine_mode mode;
412 /* This can happen when recog is called from combine. Op may be a MEM.
413 Fail instead of calling abort in this case. */
414 if (GET_CODE (op) != REG)
417 if (mode != VOIDmode && mode != GET_MODE (op))
420 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
423 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
424 if (reg_renumber == 0)
425 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
426 return REGNO_OK_FOR_CCFP_P (REGNO (op));
428 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
432 /* Nonzero if OP is an integer or floating point condition code register. */
435 icc_or_fcc_reg_operand (op, mode)
437 enum machine_mode mode;
439 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
441 if (mode != VOIDmode && mode != GET_MODE (op))
444 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
449 return fcc_reg_operand (op, mode);
452 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
454 restore_operand (op, mode)
456 enum machine_mode mode;
458 return (GET_CODE (op) == REG && GET_MODE (op) == mode
459 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
462 /* Call insn on SPARC can take a PC-relative constant address, or any regular
466 call_operand (op, mode)
468 enum machine_mode mode;
470 if (GET_CODE (op) != MEM)
473 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
477 call_operand_address (op, mode)
479 enum machine_mode mode;
481 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
484 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
485 reference and a constant. */
488 symbolic_operand (op, mode)
490 enum machine_mode mode;
492 switch (GET_CODE (op))
500 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
501 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
502 && GET_CODE (XEXP (op, 1)) == CONST_INT);
504 /* ??? This clause seems to be irrelevant. */
506 return GET_MODE (op) == mode;
513 /* Return truth value of statement that OP is a symbolic memory
514 operand of mode MODE. */
517 symbolic_memory_operand (op, mode)
519 enum machine_mode mode ATTRIBUTE_UNUSED;
521 if (GET_CODE (op) == SUBREG)
522 op = SUBREG_REG (op);
523 if (GET_CODE (op) != MEM)
526 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
527 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
530 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
533 label_ref_operand (op, mode)
535 enum machine_mode mode;
537 if (GET_CODE (op) != LABEL_REF)
539 if (GET_MODE (op) != mode)
544 /* Return 1 if the operand is an argument used in generating pic references
545 in either the medium/low or medium/anywhere code models of sparc64. */
548 sp64_medium_pic_operand (op, mode)
550 enum machine_mode mode ATTRIBUTE_UNUSED;
552 /* Check for (const (minus (symbol_ref:GOT)
553 (const (minus (label) (pc))))). */
554 if (GET_CODE (op) != CONST)
557 if (GET_CODE (op) != MINUS)
559 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
561 /* ??? Ensure symbol is GOT. */
562 if (GET_CODE (XEXP (op, 1)) != CONST)
564 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
569 /* Return 1 if the operand is a data segment reference. This includes
570 the readonly data segment, or in other words anything but the text segment.
571 This is needed in the medium/anywhere code model on v9. These values
572 are accessed with EMBMEDANY_BASE_REG. */
575 data_segment_operand (op, mode)
577 enum machine_mode mode ATTRIBUTE_UNUSED;
579 switch (GET_CODE (op))
582 return ! SYMBOL_REF_FLAG (op);
584 /* Assume canonical format of symbol + constant.
587 return data_segment_operand (XEXP (op, 0));
593 /* Return 1 if the operand is a text segment reference.
594 This is needed in the medium/anywhere code model on v9. */
597 text_segment_operand (op, mode)
599 enum machine_mode mode ATTRIBUTE_UNUSED;
601 switch (GET_CODE (op))
606 return SYMBOL_REF_FLAG (op);
608 /* Assume canonical format of symbol + constant.
611 return text_segment_operand (XEXP (op, 0));
617 /* Return 1 if the operand is either a register or a memory operand that is
621 reg_or_nonsymb_mem_operand (op, mode)
623 enum machine_mode mode;
625 if (register_operand (op, mode))
628 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
635 splittable_symbolic_memory_operand (op, mode)
637 enum machine_mode mode ATTRIBUTE_UNUSED;
639 if (GET_CODE (op) != MEM)
641 if (! symbolic_operand (XEXP (op, 0), Pmode))
647 splittable_immediate_memory_operand (op, mode)
649 enum machine_mode mode ATTRIBUTE_UNUSED;
651 if (GET_CODE (op) != MEM)
653 if (! immediate_operand (XEXP (op, 0), Pmode))
658 /* Return truth value of whether OP is EQ or NE. */
663 enum machine_mode mode ATTRIBUTE_UNUSED;
665 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
668 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
669 or LTU for non-floating-point. We handle those specially. */
672 normal_comp_operator (op, mode)
674 enum machine_mode mode ATTRIBUTE_UNUSED;
676 enum rtx_code code = GET_CODE (op);
678 if (GET_RTX_CLASS (code) != '<')
681 if (GET_MODE (XEXP (op, 0)) == CCFPmode
682 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
685 return (code != NE && code != EQ && code != GEU && code != LTU);
688 /* Return 1 if this is a comparison operator. This allows the use of
689 MATCH_OPERATOR to recognize all the branch insns. */
692 noov_compare_op (op, mode)
694 enum machine_mode mode ATTRIBUTE_UNUSED;
696 enum rtx_code code = GET_CODE (op);
698 if (GET_RTX_CLASS (code) != '<')
701 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
702 /* These are the only branches which work with CC_NOOVmode. */
703 return (code == EQ || code == NE || code == GE || code == LT);
707 /* Nonzero if OP is a comparison operator suitable for use in v9
708 conditional move or branch on register contents instructions. */
711 v9_regcmp_op (op, mode)
713 enum machine_mode mode ATTRIBUTE_UNUSED;
715 enum rtx_code code = GET_CODE (op);
717 if (GET_RTX_CLASS (code) != '<')
720 return v9_regcmp_p (code);
723 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
728 enum machine_mode mode ATTRIBUTE_UNUSED;
730 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
733 /* Return nonzero if OP is an operator of mode MODE which can set
734 the condition codes explicitly. We do not include PLUS and MINUS
735 because these require CC_NOOVmode, which we handle explicitly. */
738 cc_arithop (op, mode)
740 enum machine_mode mode ATTRIBUTE_UNUSED;
742 if (GET_CODE (op) == AND
743 || GET_CODE (op) == IOR
744 || GET_CODE (op) == XOR)
750 /* Return nonzero if OP is an operator of mode MODE which can bitwise
751 complement its second operand and set the condition codes explicitly. */
754 cc_arithopn (op, mode)
756 enum machine_mode mode ATTRIBUTE_UNUSED;
758 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
759 and (xor ... (not ...)) to (not (xor ...)). */
760 return (GET_CODE (op) == AND
761 || GET_CODE (op) == IOR);
764 /* Return true if OP is a register, or is a CONST_INT that can fit in a
765 signed 13 bit immediate field. This is an acceptable SImode operand for
766 most 3 address instructions. */
769 arith_operand (op, mode)
771 enum machine_mode mode;
774 if (register_operand (op, mode)
775 || GET_CODE (op) == CONSTANT_P_RTX)
777 if (GET_CODE (op) != CONST_INT)
779 val = INTVAL (op) & 0xffffffff;
780 return SPARC_SIMM13_P (val);
783 /* Return true if OP is a constant 4096 */
786 arith_4096_operand (op, mode)
788 enum machine_mode mode;
791 if (GET_CODE (op) != CONST_INT)
793 val = INTVAL (op) & 0xffffffff;
797 /* Return true if OP is suitable as second operand for add/sub */
800 arith_add_operand (op, mode)
802 enum machine_mode mode;
804 return arith_operand (op, mode) || arith_4096_operand (op, mode);
807 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
808 immediate field of OR and XOR instructions. Used for 64-bit
809 constant formation patterns. */
811 const64_operand (op, mode)
813 enum machine_mode mode;
815 return ((GET_CODE (op) == CONST_INT
816 && SPARC_SIMM13_P (INTVAL (op)))
817 #if HOST_BITS_PER_WIDE_INT != 64
818 || (GET_CODE (op) == CONST_DOUBLE
819 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
820 && (CONST_DOUBLE_HIGH (op) ==
821 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
824 || GET_CODE (op) == CONSTANT_P_RTX);
827 /* The same, but only for sethi instructions. */
829 const64_high_operand (op, mode)
831 enum machine_mode mode;
833 return ((GET_CODE (op) == CONST_INT
834 && (INTVAL (op) & 0xfffffc00) != 0
835 && SPARC_SETHI_P (INTVAL (op))
836 #if HOST_BITS_PER_WIDE_INT != 64
837 /* Must be positive on non-64bit host else the
838 optimizer is fooled into thinking that sethi
839 sign extends, even though it does not. */
843 || (GET_CODE (op) == CONST_DOUBLE
844 && CONST_DOUBLE_HIGH (op) == 0
845 && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
846 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
847 || GET_CODE (op) == CONSTANT_P_RTX);
850 /* Return true if OP is a register, or is a CONST_INT that can fit in a
851 signed 11 bit immediate field. This is an acceptable SImode operand for
852 the movcc instructions. */
855 arith11_operand (op, mode)
857 enum machine_mode mode;
859 return (register_operand (op, mode)
860 || GET_CODE (op) == CONSTANT_P_RTX
861 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
864 /* Return true if OP is a register, or is a CONST_INT that can fit in a
865 signed 10 bit immediate field. This is an acceptable SImode operand for
866 the movrcc instructions. */
869 arith10_operand (op, mode)
871 enum machine_mode mode;
873 return (register_operand (op, mode)
874 || GET_CODE (op) == CONSTANT_P_RTX
875 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
878 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
879 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
881 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
882 can fit in a 13 bit immediate field. This is an acceptable DImode operand
883 for most 3 address instructions. */
886 arith_double_operand (op, mode)
888 enum machine_mode mode;
890 return (register_operand (op, mode)
891 || GET_CODE (op) == CONSTANT_P_RTX
892 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
894 && GET_CODE (op) == CONST_DOUBLE
895 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
896 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
898 && GET_CODE (op) == CONST_DOUBLE
899 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
900 && ((CONST_DOUBLE_HIGH (op) == -1
901 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
902 || (CONST_DOUBLE_HIGH (op) == 0
903 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
906 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
909 arith_double_4096_operand (op, mode)
911 enum machine_mode mode;
913 return (TARGET_ARCH64 &&
914 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
915 (GET_CODE (op) == CONST_DOUBLE &&
916 CONST_DOUBLE_LOW (op) == 4096 &&
917 CONST_DOUBLE_HIGH (op) == 0)));
920 /* Return true if OP is suitable as second operand for add/sub in DImode */
923 arith_double_add_operand (op, mode)
925 enum machine_mode mode;
927 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
930 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
931 can fit in an 11 bit immediate field. This is an acceptable DImode
932 operand for the movcc instructions. */
933 /* ??? Replace with arith11_operand? */
936 arith11_double_operand (op, mode)
938 enum machine_mode mode;
940 return (register_operand (op, mode)
941 || GET_CODE (op) == CONSTANT_P_RTX
942 || (GET_CODE (op) == CONST_DOUBLE
943 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
944 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
945 && ((CONST_DOUBLE_HIGH (op) == -1
946 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
947 || (CONST_DOUBLE_HIGH (op) == 0
948 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
949 || (GET_CODE (op) == CONST_INT
950 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
951 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
954 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
955 can fit in an 10 bit immediate field. This is an acceptable DImode
956 operand for the movrcc instructions. */
957 /* ??? Replace with arith10_operand? */
960 arith10_double_operand (op, mode)
962 enum machine_mode mode;
964 return (register_operand (op, mode)
965 || GET_CODE (op) == CONSTANT_P_RTX
966 || (GET_CODE (op) == CONST_DOUBLE
967 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
968 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
969 && ((CONST_DOUBLE_HIGH (op) == -1
970 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
971 || (CONST_DOUBLE_HIGH (op) == 0
972 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
973 || (GET_CODE (op) == CONST_INT
974 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
975 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
978 /* Return truth value of whether OP is a integer which fits the
979 range constraining immediate operands in most three-address insns,
980 which have a 13 bit immediate field. */
985 enum machine_mode mode ATTRIBUTE_UNUSED;
987 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
988 || GET_CODE (op) == CONSTANT_P_RTX);
992 small_int_or_double (op, mode)
994 enum machine_mode mode ATTRIBUTE_UNUSED;
996 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
997 || (GET_CODE (op) == CONST_DOUBLE
998 && CONST_DOUBLE_HIGH (op) == 0
999 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1000 || GET_CODE (op) == CONSTANT_P_RTX);
1003 /* Recognize operand values for the umul instruction. That instruction sign
1004 extends immediate values just like all other sparc instructions, but
1005 interprets the extended result as an unsigned number. */
1008 uns_small_int (op, mode)
1010 enum machine_mode mode ATTRIBUTE_UNUSED;
1012 #if HOST_BITS_PER_WIDE_INT > 32
1013 /* All allowed constants will fit a CONST_INT. */
1014 return ((GET_CODE (op) == CONST_INT
1015 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1016 || (INTVAL (op) >= 0xFFFFF000
1017 && INTVAL (op) < 0x100000000)))
1018 || GET_CODE (op) == CONSTANT_P_RTX);
1020 return (((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1021 || (GET_CODE (op) == CONST_DOUBLE
1022 && CONST_DOUBLE_HIGH (op) == 0
1023 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000))
1024 || GET_CODE (op) == CONSTANT_P_RTX);
1029 uns_arith_operand (op, mode)
1031 enum machine_mode mode;
1033 return register_operand (op, mode) || uns_small_int (op, mode);
1036 /* Return truth value of statement that OP is a call-clobbered register. */
1038 clobbered_register (op, mode)
1040 enum machine_mode mode ATTRIBUTE_UNUSED;
1042 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1045 /* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns. */
1048 zero_operand (op, mode)
1050 enum machine_mode mode ATTRIBUTE_UNUSED;
1052 return (op == const0_rtx || GET_CODE (op) == CONSTANT_P_RTX);
1055 /* Return 1 if OP is a valid operand for the source of a move insn. */
1058 input_operand (op, mode)
1060 enum machine_mode mode;
1062 /* If both modes are non-void they must be the same. */
1063 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1066 /* Allow any one instruction integer constant, and all CONST_INT
1067 variants when we are working in DImode and !arch64. */
1068 if (GET_MODE_CLASS (mode) == MODE_INT
1069 && ((GET_CODE (op) == CONST_INT
1070 && ((SPARC_SETHI_P (INTVAL (op))
1072 || (INTVAL (op) >= 0)
1074 || SPARC_SIMM13_P (INTVAL (op))
1076 && ! TARGET_ARCH64)))
1078 && GET_CODE (op) == CONST_DOUBLE
1079 && ((CONST_DOUBLE_HIGH (op) == 0
1080 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1082 #if HOST_BITS_PER_WIDE_INT == 64
1083 (CONST_DOUBLE_HIGH (op) == 0
1084 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1086 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1087 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1088 && CONST_DOUBLE_HIGH (op) == 0)
1089 || (CONST_DOUBLE_HIGH (op) == -1)))
1094 /* Always match this. */
1095 if (GET_CODE (op) == CONSTANT_P_RTX)
1098 /* If !arch64 and this is a DImode const, allow it so that
1099 the splits can be generated. */
1102 && GET_CODE (op) == CONST_DOUBLE)
1105 if (register_operand (op, mode))
1108 /* If this is a SUBREG, look inside so that we handle
1109 paradoxical ones. */
1110 if (GET_CODE (op) == SUBREG)
1111 op = SUBREG_REG (op);
1113 /* Check for valid MEM forms. */
1114 if (GET_CODE (op) == MEM)
1116 rtx inside = XEXP (op, 0);
1118 if (GET_CODE (inside) == LO_SUM)
1120 /* We can't allow these because all of the splits
1121 (eventually as they trickle down into DFmode
1122 splits) require offsettable memory references. */
1124 && GET_MODE (op) == TFmode)
1127 return (register_operand (XEXP (inside, 0), Pmode)
1128 && CONSTANT_P (XEXP (inside, 1)));
1130 return memory_address_p (mode, inside);
1137 /* We know it can't be done in one insn when we get here,
1138 the movsi expander guarentees this. */
1140 sparc_emit_set_const32 (op0, op1)
1144 enum machine_mode mode = GET_MODE (op0);
1147 if (GET_CODE (op1) == CONST_INT)
1149 HOST_WIDE_INT value = INTVAL (op1);
1151 if (SPARC_SETHI_P (value)
1152 || SPARC_SIMM13_P (value))
1156 /* Full 2-insn decomposition is needed. */
1157 if (reload_in_progress || reload_completed)
1160 temp = gen_reg_rtx (mode);
1162 if (GET_CODE (op1) == CONST_INT)
1164 /* Emit them as real moves instead of a HIGH/LO_SUM,
1165 this way CSE can see everything and reuse intermediate
1166 values if it wants. */
1168 && HOST_BITS_PER_WIDE_INT != 64
1169 && (INTVAL (op1) & 0x80000000) != 0)
1171 emit_insn (gen_rtx_SET (VOIDmode,
1173 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx,
1174 INTVAL (op1) & 0xfffffc00, 0)));
1178 emit_insn (gen_rtx_SET (VOIDmode,
1180 GEN_INT (INTVAL (op1) & 0xfffffc00)));
1182 emit_insn (gen_rtx_SET (VOIDmode,
1186 GEN_INT (INTVAL (op1) & 0x3ff))));
1190 /* A symbol, emit in the traditional way. */
1191 emit_insn (gen_rtx_SET (VOIDmode,
1195 emit_insn (gen_rtx_SET (VOIDmode,
1197 gen_rtx_LO_SUM (mode,
1205 /* Sparc-v9 code-model support. */
1207 sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1212 switch (sparc_cmodel)
1215 /* The range spanned by all instructions in the object is less
1216 than 2^31 bytes (2GB) and the distance from any instruction
1217 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1218 than 2^31 bytes (2GB).
1220 The executable must be in the low 4TB of the virtual address
1223 sethi %hi(symbol), %temp
1224 or %temp, %lo(symbol), %reg */
1225 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1226 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1230 /* The range spanned by all instructions in the object is less
1231 than 2^31 bytes (2GB) and the distance from any instruction
1232 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1233 than 2^31 bytes (2GB).
1235 The executable must be in the low 16TB of the virtual address
1238 sethi %h44(symbol), %temp1
1239 or %temp1, %m44(symbol), %temp2
1240 sllx %temp2, 12, %temp3
1241 or %temp3, %l44(symbol), %reg */
1242 emit_insn (gen_seth44 (op0, op1));
1243 emit_insn (gen_setm44 (op0, op0, op1));
1244 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1245 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1246 emit_insn (gen_setl44 (op0, temp1, op1));
1250 /* The range spanned by all instructions in the object is less
1251 than 2^31 bytes (2GB) and the distance from any instruction
1252 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1253 than 2^31 bytes (2GB).
1255 The executable can be placed anywhere in the virtual address
1258 sethi %hh(symbol), %temp1
1259 sethi %lm(symbol), %temp2
1260 or %temp1, %hm(symbol), %temp3
1261 or %temp2, %lo(symbol), %temp4
1262 sllx %temp3, 32, %temp5
1263 or %temp4, %temp5, %reg */
1265 /* Getting this right wrt. reloading is really tricky.
1266 We _MUST_ have a seperate temporary at this point,
1267 if we don't barf immediately instead of generating
1272 emit_insn (gen_sethh (op0, op1));
1273 emit_insn (gen_setlm (temp1, op1));
1274 emit_insn (gen_sethm (op0, op0, op1));
1275 emit_insn (gen_rtx_SET (VOIDmode, op0,
1276 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1277 emit_insn (gen_rtx_SET (VOIDmode, op0,
1278 gen_rtx_PLUS (DImode, op0, temp1)));
1279 emit_insn (gen_setlo (op0, op0, op1));
1283 /* Old old old backwards compatibility kruft here.
1284 Essentially it is MEDLOW with a fixed 64-bit
1285 virtual base added to all data segment addresses.
1286 Text-segment stuff is computed like MEDANY, we can't
1287 reuse the code above because the relocation knobs
1290 Data segment: sethi %hi(symbol), %temp1
1291 or %temp1, %lo(symbol), %temp2
1292 add %temp2, EMBMEDANY_BASE_REG, %reg
1294 Text segment: sethi %uhi(symbol), %temp1
1295 sethi %hi(symbol), %temp2
1296 or %temp1, %ulo(symbol), %temp3
1297 or %temp2, %lo(symbol), %temp4
1298 sllx %temp3, 32, %temp5
1299 or %temp4, %temp5, %reg */
1300 if (data_segment_operand (op1, GET_MODE (op1)))
1302 emit_insn (gen_embmedany_sethi (temp1, op1));
1303 emit_insn (gen_embmedany_brsum (op0, temp1));
1304 emit_insn (gen_embmedany_losum (op0, op0, op1));
1308 /* Getting this right wrt. reloading is really tricky.
1309 We _MUST_ have a seperate temporary at this point,
1310 so we barf immediately instead of generating
1315 emit_insn (gen_embmedany_textuhi (op0, op1));
1316 emit_insn (gen_embmedany_texthi (temp1, op1));
1317 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1318 emit_insn (gen_rtx_SET (VOIDmode, op0,
1319 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1320 emit_insn (gen_rtx_SET (VOIDmode, op0,
1321 gen_rtx_PLUS (DImode, op0, temp1)));
1322 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1331 /* These avoid problems when cross compiling. If we do not
1332 go through all this hair then the optimizer will see
1333 invalid REG_EQUAL notes or in some cases none at all. */
1334 static void sparc_emit_set_safe_HIGH64 PROTO ((rtx, HOST_WIDE_INT));
1335 static rtx gen_safe_SET64 PROTO ((rtx, HOST_WIDE_INT));
1336 static rtx gen_safe_OR64 PROTO ((rtx, HOST_WIDE_INT));
1337 static rtx gen_safe_XOR64 PROTO ((rtx, HOST_WIDE_INT));
1339 #if HOST_BITS_PER_WIDE_INT == 64
1340 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
1341 #define GEN_INT64(__x) GEN_INT (__x)
1343 #define GEN_HIGHINT64(__x) \
1344 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1345 (__x) & 0xfffffc00, 0)
1346 #define GEN_INT64(__x) \
1347 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1348 (__x) & 0xffffffff, \
1349 ((__x) & 0x80000000 \
1353 /* The optimizer is not to assume anything about exactly
1354 which bits are set for a HIGH, they are unspecified.
1355 Unfortunately this leads to many missed optimizations
1356 during CSE. We mask out the non-HIGH bits, and matches
1357 a plain movdi, to alleviate this problem. */
1359 sparc_emit_set_safe_HIGH64 (dest, val)
1363 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1367 gen_safe_SET64 (dest, val)
1371 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1375 gen_safe_OR64 (src, val)
1379 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1383 gen_safe_XOR64 (src, val)
1387 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1390 /* Worker routines for 64-bit constant formation on arch64.
1391 One of the key things to be doing in these emissions is
1392 to create as many temp REGs as possible. This makes it
1393 possible for half-built constants to be used later when
1394 such values are similar to something required later on.
1395 Without doing this, the optimizer cannot see such
1398 static void sparc_emit_set_const64_quick1
1399 PROTO((rtx, rtx, unsigned HOST_WIDE_INT, int));
1402 sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1405 unsigned HOST_WIDE_INT low_bits;
1408 unsigned HOST_WIDE_INT high_bits;
1411 high_bits = (~low_bits) & 0xffffffff;
1413 high_bits = low_bits;
1415 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1418 emit_insn (gen_rtx_SET (VOIDmode, op0,
1419 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1423 /* If we are XOR'ing with -1, then we should emit a one's complement
1424 instead. This way the combiner will notice logical operations
1425 such as ANDN later on and substitute. */
1426 if ((low_bits & 0x3ff) == 0x3ff)
1428 emit_insn (gen_rtx_SET (VOIDmode, op0,
1429 gen_rtx_NOT (DImode, temp)));
1433 emit_insn (gen_rtx_SET (VOIDmode, op0,
1434 gen_safe_XOR64 (temp,
1435 (-0x400 | (low_bits & 0x3ff)))));
1440 static void sparc_emit_set_const64_quick2
1441 PROTO((rtx, rtx, unsigned HOST_WIDE_INT,
1442 unsigned HOST_WIDE_INT, int));
1445 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1448 unsigned HOST_WIDE_INT high_bits;
1449 unsigned HOST_WIDE_INT low_immediate;
1454 if ((high_bits & 0xfffffc00) != 0)
1456 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1457 if ((high_bits & ~0xfffffc00) != 0)
1458 emit_insn (gen_rtx_SET (VOIDmode, op0,
1459 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1465 emit_insn (gen_safe_SET64 (temp, high_bits));
1469 /* Now shift it up into place. */
1470 emit_insn (gen_rtx_SET (VOIDmode, op0,
1471 gen_rtx_ASHIFT (DImode, temp2,
1472 GEN_INT (shift_count))));
1474 /* If there is a low immediate part piece, finish up by
1475 putting that in as well. */
1476 if (low_immediate != 0)
1477 emit_insn (gen_rtx_SET (VOIDmode, op0,
1478 gen_safe_OR64 (op0, low_immediate)));
1481 static void sparc_emit_set_const64_longway
1482 PROTO((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1484 /* Full 64-bit constant decomposition. Even though this is the
1485 'worst' case, we still optimize a few things away. */
1487 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1490 unsigned HOST_WIDE_INT high_bits;
1491 unsigned HOST_WIDE_INT low_bits;
1495 if (reload_in_progress || reload_completed)
1498 sub_temp = gen_reg_rtx (DImode);
1500 if ((high_bits & 0xfffffc00) != 0)
1502 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1503 if ((high_bits & ~0xfffffc00) != 0)
1504 emit_insn (gen_rtx_SET (VOIDmode,
1506 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1512 emit_insn (gen_safe_SET64 (temp, high_bits));
1516 if (!reload_in_progress && !reload_completed)
1518 rtx temp2 = gen_reg_rtx (DImode);
1519 rtx temp3 = gen_reg_rtx (DImode);
1520 rtx temp4 = gen_reg_rtx (DImode);
1522 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1523 gen_rtx_ASHIFT (DImode, sub_temp,
1526 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1527 if ((low_bits & ~0xfffffc00) != 0)
1529 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1530 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1531 emit_insn (gen_rtx_SET (VOIDmode, op0,
1532 gen_rtx_PLUS (DImode, temp4, temp3)));
1536 emit_insn (gen_rtx_SET (VOIDmode, op0,
1537 gen_rtx_PLUS (DImode, temp4, temp2)));
1542 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1543 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1544 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1547 /* We are in the middle of reload, so this is really
1548 painful. However we do still make an attempt to
1549 avoid emitting truly stupid code. */
1550 if (low1 != const0_rtx)
1552 emit_insn (gen_rtx_SET (VOIDmode, op0,
1553 gen_rtx_ASHIFT (DImode, sub_temp,
1554 GEN_INT (to_shift))));
1555 emit_insn (gen_rtx_SET (VOIDmode, op0,
1556 gen_rtx_IOR (DImode, op0, low1)));
1564 if (low2 != const0_rtx)
1566 emit_insn (gen_rtx_SET (VOIDmode, op0,
1567 gen_rtx_ASHIFT (DImode, sub_temp,
1568 GEN_INT (to_shift))));
1569 emit_insn (gen_rtx_SET (VOIDmode, op0,
1570 gen_rtx_IOR (DImode, op0, low2)));
1578 emit_insn (gen_rtx_SET (VOIDmode, op0,
1579 gen_rtx_ASHIFT (DImode, sub_temp,
1580 GEN_INT (to_shift))));
1581 if (low3 != const0_rtx)
1582 emit_insn (gen_rtx_SET (VOIDmode, op0,
1583 gen_rtx_IOR (DImode, op0, low3)));
1588 /* Analyze a 64-bit constant for certain properties. */
1589 static void analyze_64bit_constant
1590 PROTO((unsigned HOST_WIDE_INT,
1591 unsigned HOST_WIDE_INT,
1592 int *, int *, int *));
1595 analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
1596 unsigned HOST_WIDE_INT high_bits, low_bits;
1597 int *hbsp, *lbsp, *abbasp;
1599 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1602 lowest_bit_set = highest_bit_set = -1;
1606 if ((lowest_bit_set == -1)
1607 && ((low_bits >> i) & 1))
1609 if ((highest_bit_set == -1)
1610 && ((high_bits >> (32 - i - 1)) & 1))
1611 highest_bit_set = (64 - i - 1);
1614 && ((highest_bit_set == -1)
1615 || (lowest_bit_set == -1)));
1621 if ((lowest_bit_set == -1)
1622 && ((high_bits >> i) & 1))
1623 lowest_bit_set = i + 32;
1624 if ((highest_bit_set == -1)
1625 && ((low_bits >> (32 - i - 1)) & 1))
1626 highest_bit_set = 32 - i - 1;
1629 && ((highest_bit_set == -1)
1630 || (lowest_bit_set == -1)));
1632 /* If there are no bits set this should have gone out
1633 as one instruction! */
1634 if (lowest_bit_set == -1
1635 || highest_bit_set == -1)
1637 all_bits_between_are_set = 1;
1638 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1642 if ((low_bits & (1 << i)) != 0)
1647 if ((high_bits & (1 << (i - 32))) != 0)
1650 all_bits_between_are_set = 0;
1653 *hbsp = highest_bit_set;
1654 *lbsp = lowest_bit_set;
1655 *abbasp = all_bits_between_are_set;
1658 static int const64_is_2insns
1659 PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1662 const64_is_2insns (high_bits, low_bits)
1663 unsigned HOST_WIDE_INT high_bits, low_bits;
1665 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1668 || high_bits == 0xffffffff)
1671 analyze_64bit_constant (high_bits, low_bits,
1672 &highest_bit_set, &lowest_bit_set,
1673 &all_bits_between_are_set);
1675 if ((highest_bit_set == 63
1676 || lowest_bit_set == 0)
1677 && all_bits_between_are_set != 0)
1680 if ((highest_bit_set - lowest_bit_set) < 21)
1686 static unsigned HOST_WIDE_INT create_simple_focus_bits
1687 PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
1690 static unsigned HOST_WIDE_INT
1691 create_simple_focus_bits (high_bits, low_bits, highest_bit_set, lowest_bit_set, shift)
1692 unsigned HOST_WIDE_INT high_bits, low_bits;
1693 int highest_bit_set, lowest_bit_set, shift;
1695 HOST_WIDE_INT hi, lo;
1697 if (lowest_bit_set < 32)
1699 lo = (low_bits >> lowest_bit_set) << shift;
1700 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1705 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1712 /* Here we are sure to be arch64 and this is an integer constant
1713 being loaded into a register. Emit the most efficient
1714 insn sequence possible. Detection of all the 1-insn cases
1715 has been done already. */
1717 sparc_emit_set_const64 (op0, op1)
1721 unsigned HOST_WIDE_INT high_bits, low_bits;
1722 int lowest_bit_set, highest_bit_set;
1723 int all_bits_between_are_set;
1727 /* Sanity check that we know what we are working with. */
1729 || GET_CODE (op0) != REG
1730 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1731 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1734 if (reload_in_progress || reload_completed)
1737 temp = gen_reg_rtx (DImode);
1739 if (GET_CODE (op1) != CONST_DOUBLE
1740 && GET_CODE (op1) != CONST_INT)
1742 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1746 if (GET_CODE (op1) == CONST_DOUBLE)
1748 #if HOST_BITS_PER_WIDE_INT == 64
1749 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1750 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1752 high_bits = CONST_DOUBLE_HIGH (op1);
1753 low_bits = CONST_DOUBLE_LOW (op1);
1758 #if HOST_BITS_PER_WIDE_INT == 64
1759 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1760 low_bits = (INTVAL (op1) & 0xffffffff);
1762 high_bits = ((INTVAL (op1) < 0) ?
1765 low_bits = INTVAL (op1);
1769 /* low_bits bits 0 --> 31
1770 high_bits bits 32 --> 63 */
1772 analyze_64bit_constant (high_bits, low_bits,
1773 &highest_bit_set, &lowest_bit_set,
1774 &all_bits_between_are_set);
1776 /* First try for a 2-insn sequence. */
1778 /* These situations are preferred because the optimizer can
1779 * do more things with them:
1781 * sllx %reg, shift, %reg
1783 * srlx %reg, shift, %reg
1784 * 3) mov some_small_const, %reg
1785 * sllx %reg, shift, %reg
1787 if (((highest_bit_set == 63
1788 || lowest_bit_set == 0)
1789 && all_bits_between_are_set != 0)
1790 || ((highest_bit_set - lowest_bit_set) < 12))
1792 HOST_WIDE_INT the_const = -1;
1793 int shift = lowest_bit_set;
1795 if ((highest_bit_set != 63
1796 && lowest_bit_set != 0)
1797 || all_bits_between_are_set == 0)
1800 create_simple_focus_bits (high_bits, low_bits,
1804 else if (lowest_bit_set == 0)
1805 shift = -(63 - highest_bit_set);
1807 if (! SPARC_SIMM13_P (the_const))
1810 emit_insn (gen_safe_SET64 (temp, the_const));
1812 emit_insn (gen_rtx_SET (VOIDmode,
1814 gen_rtx_ASHIFT (DImode,
1818 emit_insn (gen_rtx_SET (VOIDmode,
1820 gen_rtx_LSHIFTRT (DImode,
1822 GEN_INT (-shift))));
1828 /* Now a range of 22 or less bits set somewhere.
1829 * 1) sethi %hi(focus_bits), %reg
1830 * sllx %reg, shift, %reg
1831 * 2) sethi %hi(focus_bits), %reg
1832 * srlx %reg, shift, %reg
1834 if ((highest_bit_set - lowest_bit_set) < 21)
1836 unsigned HOST_WIDE_INT focus_bits =
1837 create_simple_focus_bits (high_bits, low_bits,
1838 highest_bit_set, lowest_bit_set, 10);
1840 if (! SPARC_SETHI_P (focus_bits))
1843 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
1845 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1846 if (lowest_bit_set < 10)
1847 emit_insn (gen_rtx_SET (VOIDmode,
1849 gen_rtx_LSHIFTRT (DImode, temp,
1850 GEN_INT (10 - lowest_bit_set))));
1851 else if (lowest_bit_set > 10)
1852 emit_insn (gen_rtx_SET (VOIDmode,
1854 gen_rtx_ASHIFT (DImode, temp,
1855 GEN_INT (lowest_bit_set - 10))));
1861 /* 1) sethi %hi(low_bits), %reg
1862 * or %reg, %lo(low_bits), %reg
1863 * 2) sethi %hi(~low_bits), %reg
1864 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1867 || high_bits == 0xffffffff)
1869 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1870 (high_bits == 0xffffffff));
1874 /* Now, try 3-insn sequences. */
1876 /* 1) sethi %hi(high_bits), %reg
1877 * or %reg, %lo(high_bits), %reg
1878 * sllx %reg, 32, %reg
1882 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
1886 /* We may be able to do something quick
1887 when the constant is negated, so try that. */
1888 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1889 (~low_bits) & 0xfffffc00))
1891 /* NOTE: The trailing bits get XOR'd so we need the
1892 non-negated bits, not the negated ones. */
1893 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
1895 if ((((~high_bits) & 0xffffffff) == 0
1896 && ((~low_bits) & 0x80000000) == 0)
1897 || (((~high_bits) & 0xffffffff) == 0xffffffff
1898 && ((~low_bits) & 0x80000000) != 0))
1900 int fast_int = (~low_bits & 0xffffffff);
1902 if ((SPARC_SETHI_P (fast_int)
1903 && (~high_bits & 0xffffffff) == 0)
1904 || SPARC_SIMM13_P (fast_int))
1905 emit_insn (gen_safe_SET64 (temp, fast_int));
1907 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
1912 #if HOST_BITS_PER_WIDE_INT == 64
1913 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
1914 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
1916 negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx,
1917 (~low_bits) & 0xfffffc00,
1918 (~high_bits) & 0xffffffff);
1920 sparc_emit_set_const64 (temp, negated_const);
1923 /* If we are XOR'ing with -1, then we should emit a one's complement
1924 instead. This way the combiner will notice logical operations
1925 such as ANDN later on and substitute. */
1926 if (trailing_bits == 0x3ff)
1928 emit_insn (gen_rtx_SET (VOIDmode, op0,
1929 gen_rtx_NOT (DImode, temp)));
1933 emit_insn (gen_rtx_SET (VOIDmode,
1935 gen_safe_XOR64 (temp,
1936 (-0x400 | trailing_bits))));
1941 /* 1) sethi %hi(xxx), %reg
1942 * or %reg, %lo(xxx), %reg
1943 * sllx %reg, yyy, %reg
1945 * ??? This is just a generalized version of the low_bits==0
1946 * thing above, FIXME...
1948 if ((highest_bit_set - lowest_bit_set) < 32)
1950 unsigned HOST_WIDE_INT focus_bits =
1951 create_simple_focus_bits (high_bits, low_bits,
1952 highest_bit_set, lowest_bit_set, 0);
1954 /* We can't get here in this state. */
1955 if (highest_bit_set < 32
1956 || lowest_bit_set >= 32)
1959 /* So what we know is that the set bits straddle the
1960 middle of the 64-bit word. */
1961 sparc_emit_set_const64_quick2 (op0, temp,
1967 /* 1) sethi %hi(high_bits), %reg
1968 * or %reg, %lo(high_bits), %reg
1969 * sllx %reg, 32, %reg
1970 * or %reg, low_bits, %reg
1972 if (SPARC_SIMM13_P(low_bits)
1973 && ((int)low_bits > 0))
1975 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
1979 /* The easiest way when all else fails, is full decomposition. */
1981 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
1982 high_bits, low_bits, ~high_bits, ~low_bits);
1984 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
1987 /* X and Y are two things to compare using CODE. Emit the compare insn and
1988 return the rtx for the cc reg in the proper mode. */
1991 gen_compare_reg (code, x, y)
1995 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1998 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
1999 fcc regs (cse can't tell they're really call clobbered regs and will
2000 remove a duplicate comparison even if there is an intervening function
2001 call - it will then try to reload the cc reg via an int reg which is why
2002 we need the movcc patterns). It is possible to provide the movcc
2003 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2004 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2005 to tell cse that CCFPE mode registers (even pseudos) are call
2008 /* ??? This is an experiment. Rather than making changes to cse which may
2009 or may not be easy/clean, we do our own cse. This is possible because
2010 we will generate hard registers. Cse knows they're call clobbered (it
2011 doesn't know the same thing about pseudos). If we guess wrong, no big
2012 deal, but if we win, great! */
2014 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2015 #if 1 /* experiment */
2018 /* We cycle through the registers to ensure they're all exercised. */
2019 static int next_fcc_reg = 0;
2020 /* Previous x,y for each fcc reg. */
2021 static rtx prev_args[4][2];
2023 /* Scan prev_args for x,y. */
2024 for (reg = 0; reg < 4; reg++)
2025 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2030 prev_args[reg][0] = x;
2031 prev_args[reg][1] = y;
2032 next_fcc_reg = (next_fcc_reg + 1) & 3;
2034 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2037 cc_reg = gen_reg_rtx (mode);
2038 #endif /* ! experiment */
2039 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2040 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2042 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2044 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2045 gen_rtx_COMPARE (mode, x, y)));
2050 /* This function is used for v9 only.
2051 CODE is the code for an Scc's comparison.
2052 OPERANDS[0] is the target of the Scc insn.
2053 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2054 been generated yet).
2056 This function is needed to turn
2059 (gt (reg:CCX 100 %icc)
2063 (gt:DI (reg:CCX 100 %icc)
2066 IE: The instruction recognizer needs to see the mode of the comparison to
2067 find the right instruction. We could use "gt:DI" right in the
2068 define_expand, but leaving it out allows us to handle DI, SI, etc.
2070 We refer to the global sparc compare operands sparc_compare_op0 and
2071 sparc_compare_op1. */
2074 gen_v9_scc (compare_code, operands)
2075 enum rtx_code compare_code;
2076 register rtx *operands;
2081 && (GET_MODE (sparc_compare_op0) == DImode
2082 || GET_MODE (operands[0]) == DImode))
2085 /* Handle the case where operands[0] == sparc_compare_op0.
2086 We "early clobber" the result. */
2087 if (REGNO (operands[0]) == REGNO (sparc_compare_op0))
2089 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2090 emit_move_insn (op0, sparc_compare_op0);
2093 op0 = sparc_compare_op0;
2094 /* For consistency in the following. */
2095 op1 = sparc_compare_op1;
2097 /* Try to use the movrCC insns. */
2099 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2100 && op1 == const0_rtx
2101 && v9_regcmp_p (compare_code))
2103 /* Special case for op0 != 0. This can be done with one instruction if
2104 operands[0] == sparc_compare_op0. We don't assume they are equal
2107 if (compare_code == NE
2108 && GET_MODE (operands[0]) == DImode
2109 && GET_MODE (op0) == DImode)
2111 emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0));
2112 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2113 gen_rtx_IF_THEN_ELSE (DImode,
2114 gen_rtx_fmt_ee (compare_code, DImode,
2121 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2122 if (GET_MODE (op0) != DImode)
2124 temp = gen_reg_rtx (DImode);
2125 convert_move (temp, op0, 0);
2129 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2130 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2131 gen_rtx_fmt_ee (compare_code, DImode,
2139 operands[1] = gen_compare_reg (compare_code, op0, op1);
2141 switch (GET_MODE (operands[1]))
2151 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2152 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2153 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2154 gen_rtx_fmt_ee (compare_code,
2155 GET_MODE (operands[1]),
2156 operands[1], const0_rtx),
2157 const1_rtx, operands[0])));
2162 /* Emit a conditional jump insn for the v9 architecture using comparison code
2163 CODE and jump target LABEL.
2164 This function exists to take advantage of the v9 brxx insns. */
2167 emit_v9_brxx_insn (code, op0, label)
2171 emit_jump_insn (gen_rtx_SET (VOIDmode,
2173 gen_rtx_IF_THEN_ELSE (VOIDmode,
2174 gen_rtx_fmt_ee (code, GET_MODE (op0),
2176 gen_rtx_LABEL_REF (VOIDmode, label),
2180 /* Return nonzero if a return peephole merging return with
2181 setting of output register is ok. */
2183 leaf_return_peephole_ok ()
2185 return (actual_fsize == 0);
2188 /* Return nonzero if TRIAL can go into the function epilogue's
2189 delay slot. SLOT is the slot we are trying to fill. */
2192 eligible_for_epilogue_delay (trial, slot)
2201 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2204 if (get_attr_length (trial) != 1)
2207 /* If %g0 is live, there are lots of things we can't handle.
2208 Rather than trying to find them all now, let's punt and only
2209 optimize things as necessary. */
2213 /* In the case of a true leaf function, anything can go into the delay slot.
2214 A delay slot only exists however if the frame size is zero, otherwise
2215 we will put an insn to adjust the stack after the return. */
2218 if (leaf_return_peephole_ok ())
2219 return ((get_attr_in_uncond_branch_delay (trial)
2220 == IN_BRANCH_DELAY_TRUE));
2224 /* If only trivial `restore' insns work, nothing can go in the
2226 else if (TARGET_BROKEN_SAVERESTORE)
2229 pat = PATTERN (trial);
2231 /* Otherwise, only operations which can be done in tandem with
2232 a `restore' insn can go into the delay slot. */
2233 if (GET_CODE (SET_DEST (pat)) != REG
2234 || REGNO (SET_DEST (pat)) >= 32
2235 || REGNO (SET_DEST (pat)) < 24)
2238 /* The set of insns matched here must agree precisely with the set of
2239 patterns paired with a RETURN in sparc.md. */
2241 src = SET_SRC (pat);
2243 /* This matches "*return_[qhs]i". */
2244 if (arith_operand (src, GET_MODE (src)))
2245 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2247 /* This matches "*return_di". */
2248 else if (arith_double_operand (src, GET_MODE (src)))
2249 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2251 /* This matches "*return_sf_no_fpu". */
2252 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2253 && register_operand (src, SFmode))
2256 /* This matches "*return_addsi". */
2257 else if (GET_CODE (src) == PLUS
2258 && arith_operand (XEXP (src, 0), SImode)
2259 && arith_operand (XEXP (src, 1), SImode)
2260 && (register_operand (XEXP (src, 0), SImode)
2261 || register_operand (XEXP (src, 1), SImode)))
2264 /* This matches "*return_adddi". */
2265 else if (GET_CODE (src) == PLUS
2266 && arith_double_operand (XEXP (src, 0), DImode)
2267 && arith_double_operand (XEXP (src, 1), DImode)
2268 && (register_operand (XEXP (src, 0), DImode)
2269 || register_operand (XEXP (src, 1), DImode)))
2276 check_return_regs (x)
2279 switch (GET_CODE (x))
2282 return IN_OR_GLOBAL_P (x);
2297 if (check_return_regs (XEXP (x, 1)) == 0)
2302 return check_return_regs (XEXP (x, 0));
2310 /* Return 1 if TRIAL references only in and global registers. */
2312 eligible_for_return_delay (trial)
2315 if (GET_CODE (PATTERN (trial)) != SET)
2318 return check_return_regs (PATTERN (trial));
2322 short_branch (uid1, uid2)
2325 unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2];
2326 if (delta + 1024 < 2048)
2328 /* warning ("long branch, distance %d", delta); */
2332 /* Return non-zero if REG is not used after INSN.
2333 We assume REG is a reload reg, and therefore does
2334 not live past labels or calls or jumps. */
2336 reg_unused_after (reg, insn)
2340 enum rtx_code code, prev_code = UNKNOWN;
2342 while ((insn = NEXT_INSN (insn)))
2344 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2347 code = GET_CODE (insn);
2348 if (GET_CODE (insn) == CODE_LABEL)
2351 if (GET_RTX_CLASS (code) == 'i')
2353 rtx set = single_set (insn);
2354 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2357 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2359 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2367 /* The table we use to reference PIC data. */
2368 static rtx global_offset_table;
2370 /* The function we use to get at it. */
2371 static rtx get_pc_symbol;
2372 static char get_pc_symbol_name[256];
2374 /* Ensure that we are not using patterns that are not OK with PIC. */
2383 if (GET_CODE (recog_operand[i]) == SYMBOL_REF
2384 || (GET_CODE (recog_operand[i]) == CONST
2385 && ! (GET_CODE (XEXP (recog_operand[i], 0)) == MINUS
2386 && (XEXP (XEXP (recog_operand[i], 0), 0)
2387 == global_offset_table)
2388 && (GET_CODE (XEXP (XEXP (recog_operand[i], 0), 1))
2397 /* Return true if X is an address which needs a temporary register when
2398 reloaded while generating PIC code. */
2401 pic_address_needs_scratch (x)
2404 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2405 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2406 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2407 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2408 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2414 /* Legitimize PIC addresses. If the address is already position-independent,
2415 we return ORIG. Newly generated position-independent addresses go into a
2416 reg. This is REG if non zero, otherwise we allocate register(s) as
2420 legitimize_pic_address (orig, mode, reg)
2422 enum machine_mode mode ATTRIBUTE_UNUSED;
2425 if (GET_CODE (orig) == SYMBOL_REF)
2427 rtx pic_ref, address;
2432 if (reload_in_progress || reload_completed)
2435 reg = gen_reg_rtx (Pmode);
2440 /* If not during reload, allocate another temp reg here for loading
2441 in the address, so that these instructions can be optimized
2443 rtx temp_reg = ((reload_in_progress || reload_completed)
2444 ? reg : gen_reg_rtx (Pmode));
2446 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
2447 won't get confused into thinking that these two instructions
2448 are loading in the true address of the symbol. If in the
2449 future a PIC rtx exists, that should be used instead. */
2450 emit_insn (gen_movsi_high_pic (temp_reg, orig));
2451 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
2457 pic_ref = gen_rtx_MEM (Pmode,
2458 gen_rtx_PLUS (Pmode,
2459 pic_offset_table_rtx, address));
2460 current_function_uses_pic_offset_table = 1;
2461 RTX_UNCHANGING_P (pic_ref) = 1;
2462 insn = emit_move_insn (reg, pic_ref);
2463 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2465 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2469 else if (GET_CODE (orig) == CONST)
2473 if (GET_CODE (XEXP (orig, 0)) == PLUS
2474 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2479 if (reload_in_progress || reload_completed)
2482 reg = gen_reg_rtx (Pmode);
2485 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2487 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2488 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2489 base == reg ? 0 : reg);
2494 if (GET_CODE (offset) == CONST_INT)
2496 if (SMALL_INT (offset))
2497 return plus_constant_for_output (base, INTVAL (offset));
2498 else if (! reload_in_progress && ! reload_completed)
2499 offset = force_reg (Pmode, offset);
2501 /* If we reach here, then something is seriously wrong. */
2504 return gen_rtx_PLUS (Pmode, base, offset);
2506 else if (GET_CODE (orig) == LABEL_REF)
2507 /* ??? Why do we do this? */
2508 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
2509 the register is live instead, in case it is eliminated. */
2510 current_function_uses_pic_offset_table = 1;
2515 /* Return the RTX for insns to set the PIC register. */
2523 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
2525 seq = gen_sequence ();
2531 /* Emit special PIC prologues and epilogues. */
2536 /* Labels to get the PC in the prologue of this function. */
2537 int orig_flag_pic = flag_pic;
2540 if (current_function_uses_pic_offset_table == 0)
2546 /* If we havn't emitted the special get_pc helper function, do so now. */
2547 if (get_pc_symbol_name[0] == 0)
2549 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
2552 ASM_OUTPUT_ALIGN (asm_out_file, 3);
2553 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0);
2554 fputs ("\tretl\n\tadd %o7,%l7,%l7\n", asm_out_file);
2557 /* Initialize every time through, since we can't easily
2558 know this to be permanent. */
2559 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2560 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
2563 emit_insn_after (pic_setup_code (), get_insns ());
2565 /* Insert the code in each nonlocal goto receiver.
2566 If you make changes here or to the nonlocal_goto_receiver
2567 pattern, make sure the unspec_volatile numbers still
2569 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2570 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
2571 && XINT (PATTERN (insn), 1) == 5)
2572 emit_insn_after (pic_setup_code (), insn);
2574 flag_pic = orig_flag_pic;
2576 /* Need to emit this whether or not we obey regdecls,
2577 since setjmp/longjmp can cause life info to screw up.
2578 ??? In the case where we don't obey regdecls, this is not sufficient
2579 since we may not fall out the bottom. */
2580 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2583 /* Return 1 if RTX is a MEM which is known to be aligned to at
2584 least an 8 byte boundary. */
2587 mem_min_alignment (mem, desired)
2591 rtx addr, base, offset;
2593 /* If it's not a MEM we can't accept it. */
2594 if (GET_CODE (mem) != MEM)
2597 addr = XEXP (mem, 0);
2598 base = offset = NULL_RTX;
2599 if (GET_CODE (addr) == PLUS)
2601 if (GET_CODE (XEXP (addr, 0)) == REG)
2603 base = XEXP (addr, 0);
2605 /* What we are saying here is that if the base
2606 REG is aligned properly, the compiler will make
2607 sure any REG based index upon it will be so
2609 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2610 offset = XEXP (addr, 1);
2612 offset = const0_rtx;
2615 else if (GET_CODE (addr) == REG)
2618 offset = const0_rtx;
2621 if (base != NULL_RTX)
2623 int regno = REGNO (base);
2625 if (regno != FRAME_POINTER_REGNUM
2626 && regno != STACK_POINTER_REGNUM)
2628 /* Check if the compiler has recorded some information
2629 about the alignment of the base REG. If reload has
2630 completed, we already matched with proper alignments. */
2631 if (((regno_pointer_align != NULL
2632 && REGNO_POINTER_ALIGN (regno) >= desired)
2633 || reload_completed)
2634 && ((INTVAL (offset) & (desired - 1)) == 0))
2639 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
2643 else if (! TARGET_UNALIGNED_DOUBLES
2644 || CONSTANT_P (addr)
2645 || GET_CODE (addr) == LO_SUM)
2647 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
2648 is true, in which case we can only assume that an access is aligned if
2649 it is to a constant address, or the address involves a LO_SUM. */
2653 /* An obviously unaligned address. */
2658 /* Vectors to keep interesting information about registers where it can easily
2659 be got. We use to use the actual mode value as the bit number, but there
2660 are more than 32 modes now. Instead we use two tables: one indexed by
2661 hard register number, and one indexed by mode. */
2663 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2664 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2665 mapped into one sparc_mode_class mode. */
2667 enum sparc_mode_class {
2668 S_MODE, D_MODE, T_MODE, O_MODE,
2669 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
2673 /* Modes for single-word and smaller quantities. */
2674 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2676 /* Modes for double-word and smaller quantities. */
2677 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2679 /* Modes for quad-word and smaller quantities. */
2680 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2682 /* Modes for single-float quantities. We must allow any single word or
2683 smaller quantity. This is because the fix/float conversion instructions
2684 take integer inputs/outputs from the float registers. */
2685 #define SF_MODES (S_MODES)
2687 /* Modes for double-float and smaller quantities. */
2688 #define DF_MODES (S_MODES | D_MODES)
2690 #define DF_MODES64 DF_MODES
2692 /* Modes for double-float only quantities. */
2693 #define DF_ONLY_MODES ((1 << (int) DF_MODE) | (1 << (int) D_MODE))
2695 /* Modes for double-float and larger quantities. */
2696 #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES)
2698 /* Modes for quad-float only quantities. */
2699 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2701 /* Modes for quad-float and smaller quantities. */
2702 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2704 #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES)
2706 /* Modes for condition codes. */
2707 #define CC_MODES (1 << (int) CC_MODE)
2708 #define CCFP_MODES (1 << (int) CCFP_MODE)
2710 /* Value is 1 if register/mode pair is acceptable on sparc.
2711 The funny mixture of D and T modes is because integer operations
2712 do not specially operate on tetra quantities, so non-quad-aligned
2713 registers can hold quadword quantities (except %o4 and %i4 because
2714 they cross fixed registers). */
2716 /* This points to either the 32 bit or the 64 bit version. */
2717 int *hard_regno_mode_classes;
2719 static int hard_32bit_mode_classes[] = {
2720 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2721 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2722 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2723 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2725 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2726 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2727 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2728 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2730 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2731 and none can hold SFmode/SImode values. */
2732 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2733 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2734 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2735 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2738 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2744 static int hard_64bit_mode_classes[] = {
2745 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2746 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2747 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2748 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2750 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2751 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2752 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2753 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2755 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2756 and none can hold SFmode/SImode values. */
2757 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2758 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2759 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2760 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2763 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2769 int sparc_mode_class [NUM_MACHINE_MODES];
2771 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
2778 for (i = 0; i < NUM_MACHINE_MODES; i++)
2780 switch (GET_MODE_CLASS (i))
2783 case MODE_PARTIAL_INT:
2784 case MODE_COMPLEX_INT:
2785 if (GET_MODE_SIZE (i) <= 4)
2786 sparc_mode_class[i] = 1 << (int) S_MODE;
2787 else if (GET_MODE_SIZE (i) == 8)
2788 sparc_mode_class[i] = 1 << (int) D_MODE;
2789 else if (GET_MODE_SIZE (i) == 16)
2790 sparc_mode_class[i] = 1 << (int) T_MODE;
2791 else if (GET_MODE_SIZE (i) == 32)
2792 sparc_mode_class[i] = 1 << (int) O_MODE;
2794 sparc_mode_class[i] = 0;
2797 case MODE_COMPLEX_FLOAT:
2798 if (GET_MODE_SIZE (i) <= 4)
2799 sparc_mode_class[i] = 1 << (int) SF_MODE;
2800 else if (GET_MODE_SIZE (i) == 8)
2801 sparc_mode_class[i] = 1 << (int) DF_MODE;
2802 else if (GET_MODE_SIZE (i) == 16)
2803 sparc_mode_class[i] = 1 << (int) TF_MODE;
2804 else if (GET_MODE_SIZE (i) == 32)
2805 sparc_mode_class[i] = 1 << (int) OF_MODE;
2807 sparc_mode_class[i] = 0;
2811 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
2812 we must explicitly check for them here. */
2813 if (i == (int) CCFPmode || i == (int) CCFPEmode)
2814 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
2815 else if (i == (int) CCmode || i == (int) CC_NOOVmode
2816 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
2817 sparc_mode_class[i] = 1 << (int) CC_MODE;
2819 sparc_mode_class[i] = 0;
2825 hard_regno_mode_classes = hard_64bit_mode_classes;
2827 hard_regno_mode_classes = hard_32bit_mode_classes;
2829 /* Initialize the array used by REGNO_REG_CLASS. */
2830 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2832 if (i < 16 && TARGET_V8PLUS)
2833 sparc_regno_reg_class[i] = I64_REGS;
2835 sparc_regno_reg_class[i] = GENERAL_REGS;
2837 sparc_regno_reg_class[i] = FP_REGS;
2839 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
2841 sparc_regno_reg_class[i] = FPCC_REGS;
2843 sparc_regno_reg_class[i] = NO_REGS;
2847 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
2848 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2849 v9 int regs as it simplifies the code. */
2852 save_regs (file, low, high, base, offset, n_regs, real_offset)
2862 if (TARGET_ARCH64 && high <= 32)
2864 for (i = low; i < high; i++)
2866 if (regs_ever_live[i] && ! call_used_regs[i])
2868 fprintf (file, "\tstx\t%s, [%s+%d]\n",
2869 reg_names[i], base, offset + 4 * n_regs);
2870 if (dwarf2out_do_frame ())
2871 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
2878 for (i = low; i < high; i += 2)
2880 if (regs_ever_live[i] && ! call_used_regs[i])
2882 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2884 fprintf (file, "\tstd\t%s, [%s+%d]\n",
2885 reg_names[i], base, offset + 4 * n_regs);
2886 if (dwarf2out_do_frame ())
2888 char *l = dwarf2out_cfi_label ();
2889 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
2890 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
2896 fprintf (file, "\tst\t%s, [%s+%d]\n",
2897 reg_names[i], base, offset + 4 * n_regs);
2898 if (dwarf2out_do_frame ())
2899 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
2905 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2907 fprintf (file, "\tst\t%s, [%s+%d]\n",
2908 reg_names[i+1], base, offset + 4 * n_regs + 4);
2909 if (dwarf2out_do_frame ())
2910 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
2919 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
2921 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2922 v9 int regs as it simplifies the code. */
2925 restore_regs (file, low, high, base, offset, n_regs)
2934 if (TARGET_ARCH64 && high <= 32)
2936 for (i = low; i < high; i++)
2938 if (regs_ever_live[i] && ! call_used_regs[i])
2939 fprintf (file, "\tldx\t[%s+%d], %s\n",
2940 base, offset + 4 * n_regs, reg_names[i]),
2946 for (i = low; i < high; i += 2)
2948 if (regs_ever_live[i] && ! call_used_regs[i])
2949 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2950 fprintf (file, "\tldd\t[%s+%d], %s\n",
2951 base, offset + 4 * n_regs, reg_names[i]),
2954 fprintf (file, "\tld\t[%s+%d],%s\n",
2955 base, offset + 4 * n_regs, reg_names[i]),
2957 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2958 fprintf (file, "\tld\t[%s+%d],%s\n",
2959 base, offset + 4 * n_regs + 4, reg_names[i+1]),
2966 /* Static variables we want to share between prologue and epilogue. */
2968 /* Number of live general or floating point registers needed to be saved
2969 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
2970 static int num_gfregs;
2972 /* Compute the frame size required by the function. This function is called
2973 during the reload pass and also by output_function_prologue(). */
2976 compute_frame_size (size, leaf_function)
2981 int outgoing_args_size = (current_function_outgoing_args_size
2982 + REG_PARM_STACK_SPACE (current_function_decl));
2984 if (TARGET_EPILOGUE)
2986 /* N_REGS is the number of 4-byte regs saved thus far. This applies
2987 even to v9 int regs to be consistent with save_regs/restore_regs. */
2991 for (i = 0; i < 8; i++)
2992 if (regs_ever_live[i] && ! call_used_regs[i])
2997 for (i = 0; i < 8; i += 2)
2998 if ((regs_ever_live[i] && ! call_used_regs[i])
2999 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3003 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3004 if ((regs_ever_live[i] && ! call_used_regs[i])
3005 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3009 /* Set up values for use in `function_epilogue'. */
3010 num_gfregs = n_regs;
3012 if (leaf_function && n_regs == 0
3013 && size == 0 && current_function_outgoing_args_size == 0)
3015 actual_fsize = apparent_fsize = 0;
3019 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3020 The stack bias (if any) is taken out to undo its effects. */
3021 apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8;
3022 apparent_fsize += n_regs * 4;
3023 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3026 /* Make sure nothing can clobber our register windows.
3027 If a SAVE must be done, or there is a stack-local variable,
3028 the register window area must be allocated.
3029 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3030 if (leaf_function == 0 || size > 0)
3031 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3033 return SPARC_STACK_ALIGN (actual_fsize);
3036 /* Build a (32 bit) big number in a register. */
3037 /* ??? We may be able to use the set macro here too. */
3040 build_big_number (file, num, reg)
3045 if (num >= 0 || ! TARGET_ARCH64)
3047 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
3048 if ((num & 0x3ff) != 0)
3049 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
3051 else /* num < 0 && TARGET_ARCH64 */
3053 /* Sethi does not sign extend, so we must use a little trickery
3054 to use it for negative numbers. Invert the constant before
3055 loading it in, then use xor immediate to invert the loaded bits
3056 (along with the upper 32 bits) to the desired constant. This
3057 works because the sethi and immediate fields overlap. */
3060 int low = -0x400 + (asize & 0x3FF);
3062 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3063 inv, reg, reg, low, reg);
3067 /* Output code for the function prologue. */
3070 output_function_prologue (file, size, leaf_function)
3075 /* Need to use actual_fsize, since we are also allocating
3076 space for our callee (and our own register save area). */
3077 actual_fsize = compute_frame_size (size, leaf_function);
3081 frame_base_name = "%sp";
3082 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3086 frame_base_name = "%fp";
3087 frame_base_offset = SPARC_STACK_BIAS;
3090 /* This is only for the human reader. */
3091 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3093 if (actual_fsize == 0)
3095 else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE)
3097 if (actual_fsize <= 4096)
3098 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3099 else if (actual_fsize <= 8192)
3101 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3102 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3106 build_big_number (file, -actual_fsize, "%g1");
3107 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
3110 else if (! leaf_function && TARGET_BROKEN_SAVERESTORE)
3112 /* We assume the environment will properly handle or otherwise avoid
3113 trouble associated with an interrupt occurring after the `save' or
3114 trap occurring during it. */
3115 fprintf (file, "\tsave\n");
3117 if (actual_fsize <= 4096)
3118 fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize);
3119 else if (actual_fsize <= 8192)
3121 fprintf (file, "\tadd\t%%fp, -4096, %%sp\n");
3122 fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize - 4096);
3126 build_big_number (file, -actual_fsize, "%g1");
3127 fprintf (file, "\tadd\t%%fp, %%g1, %%sp\n");
3130 else /* leaf function */
3132 if (actual_fsize <= 4096)
3133 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3134 else if (actual_fsize <= 8192)
3136 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3137 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3141 build_big_number (file, -actual_fsize, "%g1");
3142 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3146 if (dwarf2out_do_frame () && actual_fsize)
3148 char *label = dwarf2out_cfi_label ();
3150 /* The canonical frame address refers to the top of the frame. */
3151 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3152 : FRAME_POINTER_REGNUM),
3155 if (! leaf_function)
3157 /* Note the register window save. This tells the unwinder that
3158 it needs to restore the window registers from the previous
3159 frame's window save area at 0(cfa). */
3160 dwarf2out_window_save (label);
3162 /* The return address (-8) is now in %i7. */
3163 dwarf2out_return_reg (label, 31);
3167 /* If doing anything with PIC, do it now. */
3169 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3171 /* Call saved registers are saved just above the outgoing argument area. */
3174 int offset, real_offset, n_regs;
3177 real_offset = -apparent_fsize;
3178 offset = -apparent_fsize + frame_base_offset;
3179 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3181 /* ??? This might be optimized a little as %g1 might already have a
3182 value close enough that a single add insn will do. */
3183 /* ??? Although, all of this is probably only a temporary fix
3184 because if %g1 can hold a function result, then
3185 output_function_epilogue will lose (the result will get
3187 build_big_number (file, offset, "%g1");
3188 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3194 base = frame_base_name;
3198 if (TARGET_EPILOGUE && ! leaf_function)
3199 /* ??? Originally saved regs 0-15 here. */
3200 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3201 else if (leaf_function)
3202 /* ??? Originally saved regs 0-31 here. */
3203 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3204 if (TARGET_EPILOGUE)
3205 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3210 if (leaf_function && actual_fsize != 0)
3212 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3213 if (! TARGET_EPILOGUE)
3214 leaf_label = gen_label_rtx ();
3218 /* Output code for the function epilogue. */
3221 output_function_epilogue (file, size, leaf_function)
3223 int size ATTRIBUTE_UNUSED;
3230 emit_label_after (leaf_label, get_last_insn ());
3231 final_scan_insn (get_last_insn (), file, 0, 0, 1);
3234 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3235 else if (profile_block_flag == 2)
3237 FUNCTION_BLOCK_PROFILER_EXIT(file);
3241 else if (current_function_epilogue_delay_list == 0)
3243 /* If code does not drop into the epilogue, we need
3244 do nothing except output pending case vectors. */
3245 rtx insn = get_last_insn ();
3246 if (GET_CODE (insn) == NOTE)
3247 insn = prev_nonnote_insn (insn);
3248 if (insn && GET_CODE (insn) == BARRIER)
3249 goto output_vectors;
3252 /* Restore any call saved registers. */
3258 offset = -apparent_fsize + frame_base_offset;
3259 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3261 build_big_number (file, offset, "%g1");
3262 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3268 base = frame_base_name;
3272 if (TARGET_EPILOGUE && ! leaf_function)
3273 /* ??? Originally saved regs 0-15 here. */
3274 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3275 else if (leaf_function)
3276 /* ??? Originally saved regs 0-31 here. */
3277 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3278 if (TARGET_EPILOGUE)
3279 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
3282 /* Work out how to skip the caller's unimp instruction if required. */
3284 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
3286 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
3288 if (TARGET_EPILOGUE || leaf_label)
3290 int old_target_epilogue = TARGET_EPILOGUE;
3291 target_flags &= ~old_target_epilogue;
3293 if (! leaf_function)
3295 /* If we wound up with things in our delay slot, flush them here. */
3296 if (current_function_epilogue_delay_list)
3298 rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode),
3300 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode,
3302 PATTERN (XEXP (current_function_epilogue_delay_list, 0)),
3304 final_scan_insn (insn, file, 1, 0, 1);
3306 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
3307 fputs ("\treturn\t%i7+8\n\tnop\n", file);
3309 fprintf (file, "\t%s\n\trestore\n", ret);
3311 /* All of the following cases are for leaf functions. */
3312 else if (current_function_epilogue_delay_list)
3314 /* eligible_for_epilogue_delay_slot ensures that if this is a
3315 leaf function, then we will only have insn in the delay slot
3316 if the frame size is zero, thus no adjust for the stack is
3318 if (actual_fsize != 0)
3320 fprintf (file, "\t%s\n", ret);
3321 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
3324 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3325 avoid generating confusing assembly language output. */
3326 else if (actual_fsize == 0)
3327 fprintf (file, "\t%s\n\tnop\n", ret);
3328 else if (actual_fsize <= 4096)
3329 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
3330 else if (actual_fsize <= 8192)
3331 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
3332 ret, actual_fsize - 4096);
3333 else if ((actual_fsize & 0x3ff) == 0)
3334 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3337 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3338 actual_fsize, actual_fsize, ret);
3339 target_flags |= old_target_epilogue;
3343 sparc_output_deferred_case_vectors ();
3346 /* Functions for handling argument passing.
3348 For v8 the first six args are normally in registers and the rest are
3349 pushed. Any arg that starts within the first 6 words is at least
3350 partially passed in a register unless its data type forbids.
3352 For v9, the argument registers are laid out as an array of 16 elements
3353 and arguments are added sequentially. The first 6 int args and up to the
3354 first 16 fp args (depending on size) are passed in regs.
3356 Slot Stack Integral Float Float in structure Double Long Double
3357 ---- ----- -------- ----- ------------------ ------ -----------
3358 15 [SP+248] %f31 %f30,%f31 %d30
3359 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3360 13 [SP+232] %f27 %f26,%f27 %d26
3361 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3362 11 [SP+216] %f23 %f22,%f23 %d22
3363 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3364 9 [SP+200] %f19 %f18,%f19 %d18
3365 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3366 7 [SP+184] %f15 %f14,%f15 %d14
3367 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3368 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3369 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3370 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3371 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3372 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3373 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3375 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3377 Integral arguments are always passed as 64 bit quantities appropriately
3380 Passing of floating point values is handled as follows.
3381 If a prototype is in scope:
3382 If the value is in a named argument (i.e. not a stdarg function or a
3383 value not part of the `...') then the value is passed in the appropriate
3385 If the value is part of the `...' and is passed in one of the first 6
3386 slots then the value is passed in the appropriate int reg.
3387 If the value is part of the `...' and is not passed in one of the first 6
3388 slots then the value is passed in memory.
3389 If a prototype is not in scope:
3390 If the value is one of the first 6 arguments the value is passed in the
3391 appropriate integer reg and the appropriate fp reg.
3392 If the value is not one of the first 6 arguments the value is passed in
3393 the appropriate fp reg and in memory.
3396 /* Maximum number of int regs for args. */
3397 #define SPARC_INT_ARG_MAX 6
3398 /* Maximum number of fp regs for args. */
3399 #define SPARC_FP_ARG_MAX 16
3401 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3403 /* Handle the INIT_CUMULATIVE_ARGS macro.
3404 Initialize a variable CUM of type CUMULATIVE_ARGS
3405 for a call to a function whose data type is FNTYPE.
3406 For a library call, FNTYPE is 0. */
3409 init_cumulative_args (cum, fntype, libname, indirect)
3410 CUMULATIVE_ARGS *cum;
3412 tree libname ATTRIBUTE_UNUSED;
3413 int indirect ATTRIBUTE_UNUSED;
3416 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
3417 cum->libcall_p = fntype == 0;
3420 /* Compute the slot number to pass an argument in.
3421 Returns the slot number or -1 if passing on the stack.
3423 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3424 the preceding args and about the function being called.
3425 MODE is the argument's machine mode.
3426 TYPE is the data type of the argument (as a tree).
3427 This is null for libcalls where that information may
3429 NAMED is nonzero if this argument is a named parameter
3430 (otherwise it is an extra parameter matching an ellipsis).
3431 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3432 *PREGNO records the register number to use if scalar type.
3433 *PPADDING records the amount of padding needed in words. */
3436 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
3437 const CUMULATIVE_ARGS *cum;
3438 enum machine_mode mode;
3445 int regbase = (incoming_p
3446 ? SPARC_INCOMING_INT_ARG_FIRST
3447 : SPARC_OUTGOING_INT_ARG_FIRST);
3448 int slotno = cum->words;
3453 if (type != 0 && TREE_ADDRESSABLE (type))
3456 && type != 0 && mode == BLKmode
3457 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
3463 /* MODE is VOIDmode when generating the actual call.
3467 case QImode : case CQImode :
3468 case HImode : case CHImode :
3469 case SImode : case CSImode :
3470 case DImode : case CDImode :
3471 if (slotno >= SPARC_INT_ARG_MAX)
3473 regno = regbase + slotno;
3476 case SFmode : case SCmode :
3477 case DFmode : case DCmode :
3478 case TFmode : case TCmode :
3481 if (slotno >= SPARC_INT_ARG_MAX)
3483 regno = regbase + slotno;
3487 if ((mode == TFmode || mode == TCmode)
3488 && (slotno & 1) != 0)
3489 slotno++, *ppadding = 1;
3490 if (TARGET_FPU && named)
3492 if (slotno >= SPARC_FP_ARG_MAX)
3494 regno = SPARC_FP_ARG_FIRST + slotno * 2;
3500 if (slotno >= SPARC_INT_ARG_MAX)
3502 regno = regbase + slotno;
3508 /* For sparc64, objects requiring 16 byte alignment get it. */
3511 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
3512 slotno++, *ppadding = 1;
3516 || (type && TREE_CODE (type) == UNION_TYPE))
3518 if (slotno >= SPARC_INT_ARG_MAX)
3520 regno = regbase + slotno;
3525 int intregs_p = 0, fpregs_p = 0;
3526 /* The ABI obviously doesn't specify how packed
3527 structures are passed. These are defined to be passed
3528 in int regs if possible, otherwise memory. */
3531 /* First see what kinds of registers we need. */
3532 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3534 if (TREE_CODE (field) == FIELD_DECL)
3536 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3541 if (DECL_PACKED (field))
3545 if (packed_p || !named)
3546 fpregs_p = 0, intregs_p = 1;
3548 /* If all arg slots are filled, then must pass on stack. */
3549 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
3551 /* If there are only int args and all int arg slots are filled,
3552 then must pass on stack. */
3553 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
3555 /* Note that even if all int arg slots are filled, fp members may
3556 still be passed in regs if such regs are available.
3557 *PREGNO isn't set because there may be more than one, it's up
3558 to the caller to compute them. */
3571 /* Handle recursive register counting for structure field layout. */
3573 struct function_arg_record_value_parms
3576 int slotno, named, regbase;
3577 int nregs, intoffset;
3580 static void function_arg_record_value_3
3581 PROTO((int, struct function_arg_record_value_parms *));
3582 static void function_arg_record_value_2
3583 PROTO((tree, int, struct function_arg_record_value_parms *));
3584 static rtx function_arg_record_value
3585 PROTO((tree, enum machine_mode, int, int, int));
3588 function_arg_record_value_1 (type, startbitpos, parms)
3591 struct function_arg_record_value_parms *parms;
3595 /* The ABI obviously doesn't specify how packed structures are
3596 passed. These are defined to be passed in int regs if possible,
3597 otherwise memory. */
3600 /* We need to compute how many registers are needed so we can
3601 allocate the PARALLEL but before we can do that we need to know
3602 whether there are any packed fields. If there are, int regs are
3603 used regardless of whether there are fp values present. */
3604 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3606 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
3613 /* Compute how many registers we need. */
3614 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3616 if (TREE_CODE (field) == FIELD_DECL)
3618 int bitpos = startbitpos;
3619 if (DECL_FIELD_BITPOS (field))
3620 bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3621 /* ??? FIXME: else assume zero offset. */
3623 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
3625 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
3627 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3632 if (parms->intoffset != -1)
3634 int intslots, this_slotno;
3636 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
3638 this_slotno = parms->slotno + parms->intoffset
3641 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3642 intslots = MAX (intslots, 0);
3643 parms->nregs += intslots;
3644 parms->intoffset = -1;
3647 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
3648 If it wasn't true we wouldn't be here. */
3653 if (parms->intoffset == -1)
3654 parms->intoffset = bitpos;
3660 /* Handle recursive structure field register assignment. */
3663 function_arg_record_value_3 (bitpos, parms)
3665 struct function_arg_record_value_parms *parms;
3667 enum machine_mode mode;
3668 int regno, this_slotno, intslots, intoffset;
3671 if (parms->intoffset == -1)
3673 intoffset = parms->intoffset;
3674 parms->intoffset = -1;
3676 intslots = (bitpos - intoffset + BITS_PER_WORD - 1) / BITS_PER_WORD;
3677 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
3679 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3683 /* If this is the trailing part of a word, only load that much into
3684 the register. Otherwise load the whole register. Note that in
3685 the latter case we may pick up unwanted bits. It's not a problem
3686 at the moment but may wish to revisit. */
3688 if (intoffset % BITS_PER_WORD != 0)
3690 mode = mode_for_size (BITS_PER_WORD - intoffset%BITS_PER_WORD,
3696 intoffset /= BITS_PER_UNIT;
3699 regno = parms->regbase + this_slotno;
3700 reg = gen_rtx_REG (mode, regno);
3701 XVECEXP (parms->ret, 0, parms->nregs)
3702 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
3705 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
3709 while (intslots > 0);
3713 function_arg_record_value_2 (type, startbitpos, parms)
3716 struct function_arg_record_value_parms *parms;
3721 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3723 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
3730 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3732 if (TREE_CODE (field) == FIELD_DECL)
3734 int bitpos = startbitpos;
3735 if (DECL_FIELD_BITPOS (field))
3736 bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3737 /* ??? FIXME: else assume zero offset. */
3739 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
3741 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
3743 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3748 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
3751 function_arg_record_value_3 (bitpos, parms);
3753 reg = gen_rtx_REG (DECL_MODE (field),
3754 (SPARC_FP_ARG_FIRST + this_slotno * 2
3755 + (DECL_MODE (field) == SFmode
3756 && (bitpos & 32) != 0)));
3757 XVECEXP (parms->ret, 0, parms->nregs)
3758 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3759 GEN_INT (bitpos / BITS_PER_UNIT));
3764 if (parms->intoffset == -1)
3765 parms->intoffset = bitpos;
3772 function_arg_record_value (type, mode, slotno, named, regbase)
3774 enum machine_mode mode;
3775 int slotno, named, regbase;
3777 HOST_WIDE_INT typesize = int_size_in_bytes (type);
3778 struct function_arg_record_value_parms parms;
3781 parms.ret = NULL_RTX;
3782 parms.slotno = slotno;
3783 parms.named = named;
3784 parms.regbase = regbase;
3786 /* Compute how many registers we need. */
3788 parms.intoffset = 0;
3789 function_arg_record_value_1 (type, 0, &parms);
3791 if (parms.intoffset != -1)
3793 int intslots, this_slotno;
3795 intslots = (typesize*BITS_PER_UNIT - parms.intoffset + BITS_PER_WORD - 1)
3797 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
3799 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3800 intslots = MAX (intslots, 0);
3802 parms.nregs += intslots;
3804 nregs = parms.nregs;
3806 /* Allocate the vector and handle some annoying special cases. */
3809 /* ??? Empty structure has no value? Duh? */
3812 /* Though there's nothing really to store, return a word register
3813 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
3814 leads to breakage due to the fact that there are zero bytes to
3816 return gen_rtx_REG (mode, regbase);
3820 /* ??? C++ has structures with no fields, and yet a size. Give up
3821 for now and pass everything back in integer registers. */
3822 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3824 if (nregs + slotno > SPARC_INT_ARG_MAX)
3825 nregs = SPARC_INT_ARG_MAX - slotno;
3830 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
3832 /* Fill in the entries. */
3834 parms.intoffset = 0;
3835 function_arg_record_value_2 (type, 0, &parms);
3836 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
3838 if (parms.nregs != nregs)
3844 /* Handle the FUNCTION_ARG macro.
3845 Determine where to put an argument to a function.
3846 Value is zero to push the argument on the stack,
3847 or a hard register in which to store the argument.
3849 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3850 the preceding args and about the function being called.
3851 MODE is the argument's machine mode.
3852 TYPE is the data type of the argument (as a tree).
3853 This is null for libcalls where that information may
3855 NAMED is nonzero if this argument is a named parameter
3856 (otherwise it is an extra parameter matching an ellipsis).
3857 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
3860 function_arg (cum, mode, type, named, incoming_p)
3861 const CUMULATIVE_ARGS *cum;
3862 enum machine_mode mode;
3867 int regbase = (incoming_p
3868 ? SPARC_INCOMING_INT_ARG_FIRST
3869 : SPARC_OUTGOING_INT_ARG_FIRST);
3870 int slotno, regno, padding;
3873 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
3881 reg = gen_rtx_REG (mode, regno);
3885 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
3886 but also have the slot allocated for them.
3887 If no prototype is in scope fp values in register slots get passed
3888 in two places, either fp regs and int regs or fp regs and memory. */
3889 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
3890 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3891 && SPARC_FP_REG_P (regno))
3893 reg = gen_rtx_REG (mode, regno);
3894 if (cum->prototype_p || cum->libcall_p)
3896 /* "* 2" because fp reg numbers are recorded in 4 byte
3899 /* ??? This will cause the value to be passed in the fp reg and
3900 in the stack. When a prototype exists we want to pass the
3901 value in the reg but reserve space on the stack. That's an
3902 optimization, and is deferred [for a bit]. */
3903 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
3904 return gen_rtx_PARALLEL (mode,
3906 gen_rtx_EXPR_LIST (VOIDmode,
3907 NULL_RTX, const0_rtx),
3908 gen_rtx_EXPR_LIST (VOIDmode,
3912 /* ??? It seems that passing back a register even when past
3913 the area declared by REG_PARM_STACK_SPACE will allocate
3914 space appropriately, and will not copy the data onto the
3915 stack, exactly as we desire.
3917 This is due to locate_and_pad_parm being called in
3918 expand_call whenever reg_parm_stack_space > 0, which
3919 while benefical to our example here, would seem to be
3920 in error from what had been intended. Ho hum... -- r~ */
3928 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
3932 /* On incoming, we don't need to know that the value
3933 is passed in %f0 and %i0, and it confuses other parts
3934 causing needless spillage even on the simplest cases. */
3938 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
3939 + (regno - SPARC_FP_ARG_FIRST) / 2);
3941 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
3942 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
3944 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
3948 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
3949 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
3950 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
3954 else if (type && TREE_CODE (type) == RECORD_TYPE)
3956 /* Structures up to 16 bytes in size are passed in arg slots on the
3957 stack and are promoted to registers where possible. */
3959 if (int_size_in_bytes (type) > 16)
3960 abort (); /* shouldn't get here */
3962 return function_arg_record_value (type, mode, slotno, named, regbase);
3964 else if (type && TREE_CODE (type) == UNION_TYPE)
3966 enum machine_mode mode;
3967 int bytes = int_size_in_bytes (type);
3972 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
3973 reg = gen_rtx_REG (mode, regno);
3977 /* Scalar or complex int. */
3978 reg = gen_rtx_REG (mode, regno);
3984 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
3985 For an arg passed partly in registers and partly in memory,
3986 this is the number of registers used.
3987 For args passed entirely in registers or entirely in memory, zero.
3989 Any arg that starts in the first 6 regs but won't entirely fit in them
3990 needs partial registers on v8. On v9, structures with integer
3991 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
3992 values that begin in the last fp reg [where "last fp reg" varies with the
3993 mode] will be split between that reg and memory. */
3996 function_arg_partial_nregs (cum, mode, type, named)
3997 const CUMULATIVE_ARGS *cum;
3998 enum machine_mode mode;
4002 int slotno, regno, padding;
4004 /* We pass 0 for incoming_p here, it doesn't matter. */
4005 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4012 if ((slotno + (mode == BLKmode
4013 ? ROUND_ADVANCE (int_size_in_bytes (type))
4014 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
4015 > NPARM_REGS (SImode))
4016 return NPARM_REGS (SImode) - slotno;
4021 if (type && AGGREGATE_TYPE_P (type))
4023 int size = int_size_in_bytes (type);
4024 int align = TYPE_ALIGN (type);
4027 slotno += slotno & 1;
4028 if (size > 8 && size <= 16
4029 && slotno == SPARC_INT_ARG_MAX - 1)
4032 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
4033 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4036 if (GET_MODE_ALIGNMENT (mode) == 128)
4038 slotno += slotno & 1;
4039 if (slotno == SPARC_INT_ARG_MAX - 2)
4044 if (slotno == SPARC_INT_ARG_MAX - 1)
4048 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4050 if (GET_MODE_ALIGNMENT (mode) == 128)
4051 slotno += slotno & 1;
4052 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
4060 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
4061 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
4062 quad-precision floats by invisible reference.
4063 v9: Aggregates greater than 16 bytes are passed by reference.
4064 For Pascal, also pass arrays by reference. */
4067 function_arg_pass_by_reference (cum, mode, type, named)
4068 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
4069 enum machine_mode mode;
4071 int named ATTRIBUTE_UNUSED;
4075 return ((type && AGGREGATE_TYPE_P (type))
4076 || mode == TFmode || mode == TCmode);
4080 return ((type && TREE_CODE (type) == ARRAY_TYPE)
4081 /* Consider complex values as aggregates, so care for TCmode. */
4082 || GET_MODE_SIZE (mode) > 16
4083 || (type && AGGREGATE_TYPE_P (type)
4084 && int_size_in_bytes (type) > 16));
4088 /* Handle the FUNCTION_ARG_ADVANCE macro.
4089 Update the data in CUM to advance over an argument
4090 of mode MODE and data type TYPE.
4091 TYPE is null for libcalls where that information may not be available. */
4094 function_arg_advance (cum, mode, type, named)
4095 CUMULATIVE_ARGS *cum;
4096 enum machine_mode mode;
4100 int slotno, regno, padding;
4102 /* We pass 0 for incoming_p here, it doesn't matter. */
4103 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4105 /* If register required leading padding, add it. */
4107 cum->words += padding;
4111 cum->words += (mode != BLKmode
4112 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4113 : ROUND_ADVANCE (int_size_in_bytes (type)));
4117 if (type && AGGREGATE_TYPE_P (type))
4119 int size = int_size_in_bytes (type);
4123 else if (size <= 16)
4125 else /* passed by reference */
4128 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
4132 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4134 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
4138 cum->words += (mode != BLKmode
4139 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4140 : ROUND_ADVANCE (int_size_in_bytes (type)));
4145 /* Handle the FUNCTION_ARG_PADDING macro.
4146 For the 64 bit ABI structs are always stored left shifted in their
4150 function_arg_padding (mode, type)
4151 enum machine_mode mode;
4154 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
4157 /* This is the default definition. */
4158 return (! BYTES_BIG_ENDIAN
4161 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
4162 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
4163 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
4164 ? downward : upward));
4167 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
4168 For v9, function return values are subject to the same rules as arguments,
4169 except that up to 32-bytes may be returned in registers. */
4172 function_value (type, mode, incoming_p)
4174 enum machine_mode mode;
4178 int regbase = (incoming_p
4179 ? SPARC_OUTGOING_INT_ARG_FIRST
4180 : SPARC_INCOMING_INT_ARG_FIRST);
4182 if (TARGET_ARCH64 && type)
4184 if (TREE_CODE (type) == RECORD_TYPE)
4186 /* Structures up to 32 bytes in size are passed in registers,
4187 promoted to fp registers where possible. */
4189 if (int_size_in_bytes (type) > 32)
4190 abort (); /* shouldn't get here */
4192 return function_arg_record_value (type, mode, 0, 1, regbase);
4194 else if (TREE_CODE (type) == UNION_TYPE)
4196 int bytes = int_size_in_bytes (type);
4201 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4206 regno = BASE_RETURN_VALUE_REG (mode);
4208 regno = BASE_OUTGOING_VALUE_REG (mode);
4210 return gen_rtx_REG (mode, regno);
4213 /* Do what is necessary for `va_start'. The argument is ignored.
4215 We look at the current function to determine if stdarg or varargs
4216 is used and return the address of the first unnamed parameter. */
4219 sparc_builtin_saveregs (arglist)
4220 tree arglist ATTRIBUTE_UNUSED;
4222 int first_reg = current_function_args_info.words;
4226 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
4227 emit_move_insn (gen_rtx_MEM (word_mode,
4228 gen_rtx_PLUS (Pmode,
4230 GEN_INT (STACK_POINTER_OFFSET
4231 + UNITS_PER_WORD * regno))),
4232 gen_rtx_REG (word_mode,
4233 BASE_INCOMING_ARG_REG (word_mode) + regno));
4235 address = gen_rtx_PLUS (Pmode,
4237 GEN_INT (STACK_POINTER_OFFSET
4238 + UNITS_PER_WORD * first_reg));
4240 if (flag_check_memory_usage
4241 && first_reg < NPARM_REGS (word_mode))
4242 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4244 GEN_INT (UNITS_PER_WORD
4245 * (NPARM_REGS (word_mode) - first_reg)),
4246 TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW),
4247 TYPE_MODE (integer_type_node));
4252 /* Return the string to output a conditional branch to LABEL, which is
4253 the operand number of the label. OP is the conditional expression.
4254 XEXP (OP, 0) is assumed to be a condition code register (integer or
4255 floating point) and its mode specifies what kind of comparison we made.
4257 REVERSED is non-zero if we should reverse the sense of the comparison.
4259 ANNUL is non-zero if we should generate an annulling branch.
4261 NOOP is non-zero if we have to follow this branch by a noop.
4263 INSN, if set, is the insn. */
4266 output_cbranch (op, label, reversed, annul, noop, insn)
4269 int reversed, annul, noop;
4272 static char string[32];
4273 enum rtx_code code = GET_CODE (op);
4274 rtx cc_reg = XEXP (op, 0);
4275 enum machine_mode mode = GET_MODE (cc_reg);
4276 static char v8_labelno[] = "%lX";
4277 static char v9_icc_labelno[] = "%%icc, %lX";
4278 static char v9_xcc_labelno[] = "%%xcc, %lX";
4279 static char v9_fcc_labelno[] = "%%fccX, %lY";
4281 int labeloff, spaces = 8;
4283 /* ??? !v9: FP branches cannot be preceded by another floating point insn.
4284 Because there is currently no concept of pre-delay slots, we can fix
4285 this only by always emitting a nop before a floating point branch. */
4287 if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9)
4288 strcpy (string, "nop\n\t");
4292 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4294 && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE))
4295 code = reverse_condition (code), reversed = 0;
4297 /* Start by writing the branch condition. */
4301 if (mode == CCFPmode || mode == CCFPEmode)
4303 strcat (string, "fbne");
4308 strcpy (string, "bne");
4314 if (mode == CCFPmode || mode == CCFPEmode)
4316 strcat (string, "fbe");
4321 strcpy (string, "be");
4327 if (mode == CCFPmode || mode == CCFPEmode)
4330 strcat (string, "fbul");
4332 strcat (string, "fbge");
4335 else if (mode == CC_NOOVmode)
4337 strcpy (string, "bpos");
4342 strcpy (string, "bge");
4348 if (mode == CCFPmode || mode == CCFPEmode)
4352 strcat (string, "fbule");
4357 strcat (string, "fbg");
4363 strcpy (string, "bg");
4369 if (mode == CCFPmode || mode == CCFPEmode)
4372 strcat (string, "fbug");
4374 strcat (string, "fble");
4379 strcpy (string, "ble");
4385 if (mode == CCFPmode || mode == CCFPEmode)
4389 strcat (string, "fbuge");
4394 strcat (string, "fbl");
4398 else if (mode == CC_NOOVmode)
4400 strcpy (string, "bneg");
4405 strcpy (string, "bl");
4411 strcpy (string, "bgeu");
4416 strcpy (string, "bgu");
4421 strcpy (string, "bleu");
4426 strcpy (string, "blu");
4434 /* Now add the annulling, the label, and a possible noop. */
4437 strcat (string, ",a");
4444 labelno = v8_labelno;
4450 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
4453 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
4458 if (mode == CCFPmode || mode == CCFPEmode)
4461 labelno = v9_fcc_labelno;
4462 /* Set the char indicating the number of the fcc reg to use. */
4463 labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
4465 else if (mode == CCXmode || mode == CCX_NOOVmode)
4466 labelno = v9_xcc_labelno;
4468 labelno = v9_icc_labelno;
4470 /* Set the char indicating the number of the operand containing the
4472 labelno[labeloff] = label + '0';
4474 strcat (string, "\t");
4476 strcat (string, " ");
4477 strcat (string, labelno);
4480 strcat (string, "\n\tnop");
4485 /* Return the string to output a conditional branch to LABEL, testing
4486 register REG. LABEL is the operand number of the label; REG is the
4487 operand number of the reg. OP is the conditional expression. The mode
4488 of REG says what kind of comparison we made.
4490 REVERSED is non-zero if we should reverse the sense of the comparison.
4492 ANNUL is non-zero if we should generate an annulling branch.
4494 NOOP is non-zero if we have to follow this branch by a noop. */
4497 output_v9branch (op, reg, label, reversed, annul, noop, insn)
4500 int reversed, annul, noop;
4503 static char string[20];
4504 enum rtx_code code = GET_CODE (op);
4505 enum machine_mode mode = GET_MODE (XEXP (op, 0));
4506 static char labelno[] = "%X, %lX";
4510 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4512 code = reverse_condition (code), reversed = 0;
4514 /* Only 64 bit versions of these instructions exist. */
4518 /* Start by writing the branch condition. */
4523 strcpy (string, "brnz");
4528 strcpy (string, "brz");
4533 strcpy (string, "brgez");
4538 strcpy (string, "brlz");
4543 strcpy (string, "brlez");
4548 strcpy (string, "brgz");
4556 /* Now add the annulling, reg, label, and nop. */
4559 strcat (string, ",a");
4563 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
4566 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
4570 labelno[1] = reg + '0';
4571 labelno[6] = label + '0';
4573 strcat (string, "\t");
4575 strcat (string, " ");
4576 strcat (string, labelno);
4579 strcat (string, "\n\tnop");
4584 /* Renumber registers in delay slot. Replace registers instead of
4585 renumbering because they may be shared.
4587 This does not handle instructions other than move. */
4590 epilogue_renumber (where)
4594 enum rtx_code code = GET_CODE (x);
4599 *where = x = copy_rtx (x);
4600 epilogue_renumber (&XEXP (x, 0));
4605 int regno = REGNO (x);
4606 if (regno > 8 && regno < 24)
4608 if (regno >= 24 && regno < 32)
4609 *where = gen_rtx_REG (GET_MODE (x), regno - 16);
4624 epilogue_renumber (&XEXP (x, 1));
4627 epilogue_renumber (&XEXP (x, 0));
4636 /* Output assembler code to return from a function. */
4639 output_return (operands)
4642 rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0;
4646 operands[0] = leaf_label;
4649 else if (leaf_function)
4651 /* No delay slot in a leaf function. */
4655 /* If we didn't allocate a frame pointer for the current function,
4656 the stack pointer might have been adjusted. Output code to
4659 operands[0] = GEN_INT (actual_fsize);
4661 /* Use sub of negated value in first two cases instead of add to
4662 allow actual_fsize == 4096. */
4664 if (actual_fsize <= 4096)
4666 if (SKIP_CALLERS_UNIMP_P)
4667 return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
4669 return "retl\n\tsub\t%%sp, -%0, %%sp";
4671 else if (actual_fsize <= 8192)
4673 operands[0] = GEN_INT (actual_fsize - 4096);
4674 if (SKIP_CALLERS_UNIMP_P)
4675 return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
4677 return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
4679 else if (SKIP_CALLERS_UNIMP_P)
4681 if ((actual_fsize & 0x3ff) != 0)
4682 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
4684 return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
4688 if ((actual_fsize & 0x3ff) != 0)
4689 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4691 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4698 epilogue_renumber (&SET_DEST (PATTERN (delay)));
4699 epilogue_renumber (&SET_SRC (PATTERN (delay)));
4701 if (SKIP_CALLERS_UNIMP_P)
4702 return "return\t%%i7+12%#";
4704 return "return\t%%i7+8%#";
4710 if (SKIP_CALLERS_UNIMP_P)
4711 return "jmp\t%%i7+12\n\trestore";
4713 return "ret\n\trestore";
4717 /* Leaf functions and non-leaf functions have different needs. */
4720 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
4723 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
4725 static int *reg_alloc_orders[] = {
4726 reg_leaf_alloc_order,
4727 reg_nonleaf_alloc_order};
4730 order_regs_for_local_alloc ()
4732 static int last_order_nonleaf = 1;
4734 if (regs_ever_live[15] != last_order_nonleaf)
4736 last_order_nonleaf = !last_order_nonleaf;
4737 bcopy ((char *) reg_alloc_orders[last_order_nonleaf],
4738 (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int));
4742 /* Return 1 if REG and MEM are legitimate enough to allow the various
4743 mem<-->reg splits to be run. */
4746 sparc_splitdi_legitimate (reg, mem)
4750 rtx addr_part = XEXP (mem, 0);
4752 /* Punt if we are here by mistake. */
4753 if (! reload_completed)
4756 /* We must have an offsettable memory reference. */
4757 if (! offsettable_memref_p (mem))
4760 /* If we have legitimate args for ldd/std, we do not want
4761 the split to happen. */
4762 if ((REGNO (reg) % 2) == 0
4763 && mem_min_alignment (mem, 8))
4770 /* Return 1 if x and y are some kind of REG and they refer to
4771 different hard registers. This test is guarenteed to be
4772 run after reload. */
4775 sparc_absnegfloat_split_legitimate (x, y)
4778 if (GET_CODE (x) == SUBREG)
4779 x = alter_subreg (x);
4780 if (GET_CODE (x) != REG)
4782 if (GET_CODE (y) == SUBREG)
4783 y = alter_subreg (y);
4784 if (GET_CODE (y) != REG)
4786 if (REGNO (x) == REGNO (y))
4791 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
4792 This makes them candidates for using ldd and std insns.
4794 Note reg1 and reg2 *must* be hard registers. */
4797 registers_ok_for_ldd_peep (reg1, reg2)
4800 /* We might have been passed a SUBREG. */
4801 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
4804 if (REGNO (reg1) % 2 != 0)
4807 /* Integer ldd is deprecated in SPARC V9 */
4808 if (TARGET_V9 && REGNO (reg1) < 32)
4811 return (REGNO (reg1) == REGNO (reg2) - 1);
4814 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
4817 This can only happen when addr1 and addr2 are consecutive memory
4818 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
4819 64 bit boundary (addr1 % 8 == 0).
4821 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
4822 registers are assumed to *never* be properly aligned and are
4825 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
4826 need only check that the offset for addr1 % 8 == 0. */
4829 addrs_ok_for_ldd_peep (addr1, addr2)
4834 /* Extract a register number and offset (if used) from the first addr. */
4835 if (GET_CODE (addr1) == PLUS)
4837 /* If not a REG, return zero. */
4838 if (GET_CODE (XEXP (addr1, 0)) != REG)
4842 reg1 = REGNO (XEXP (addr1, 0));
4843 /* The offset must be constant! */
4844 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
4846 offset1 = INTVAL (XEXP (addr1, 1));
4849 else if (GET_CODE (addr1) != REG)
4853 reg1 = REGNO (addr1);
4854 /* This was a simple (mem (reg)) expression. Offset is 0. */
4858 /* Make sure the second address is a (mem (plus (reg) (const_int). */
4859 if (GET_CODE (addr2) != PLUS)
4862 if (GET_CODE (XEXP (addr2, 0)) != REG
4863 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
4866 /* Only %fp and %sp are allowed. Additionally both addresses must
4867 use the same register. */
4868 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
4871 if (reg1 != REGNO (XEXP (addr2, 0)))
4874 /* The first offset must be evenly divisible by 8 to ensure the
4875 address is 64 bit aligned. */
4876 if (offset1 % 8 != 0)
4879 /* The offset for the second addr must be 4 more than the first addr. */
4880 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
4883 /* All the tests passed. addr1 and addr2 are valid for ldd and std
4888 /* Return 1 if reg is a pseudo, or is the first register in
4889 a hard register pair. This makes it a candidate for use in
4890 ldd and std insns. */
4893 register_ok_for_ldd (reg)
4896 /* We might have been passed a SUBREG. */
4897 if (GET_CODE (reg) != REG)
4900 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
4901 return (REGNO (reg) % 2 == 0);
4906 /* Print operand X (an rtx) in assembler syntax to file FILE.
4907 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4908 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4911 print_operand (file, x, code)
4919 /* Output a 'nop' if there's nothing for the delay slot. */
4920 if (dbr_sequence_length () == 0)
4921 fputs ("\n\t nop", file);
4924 /* Output an annul flag if there's nothing for the delay slot and we
4925 are optimizing. This is always used with '(' below. */
4926 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
4927 this is a dbx bug. So, we only do this when optimizing. */
4928 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
4929 Always emit a nop in case the next instruction is a branch. */
4930 if (dbr_sequence_length () == 0
4931 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
4935 /* Output a 'nop' if there's nothing for the delay slot and we are
4936 not optimizing. This is always used with '*' above. */
4937 if (dbr_sequence_length () == 0
4938 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
4939 fputs ("\n\t nop", file);
4942 /* Output the Embedded Medium/Anywhere code model base register. */
4943 fputs (EMBMEDANY_BASE_REG, file);
4946 /* Print out what we are using as the frame pointer. This might
4947 be %fp, or might be %sp+offset. */
4948 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
4949 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
4952 /* Adjust the operand to take into account a RESTORE operation. */
4953 if (GET_CODE (x) == CONST_INT)
4955 else if (GET_CODE (x) != REG)
4956 output_operand_lossage ("Invalid %%Y operand");
4957 else if (REGNO (x) < 8)
4958 fputs (reg_names[REGNO (x)], file);
4959 else if (REGNO (x) >= 24 && REGNO (x) < 32)
4960 fputs (reg_names[REGNO (x)-16], file);
4962 output_operand_lossage ("Invalid %%Y operand");
4965 /* Print out the low order register name of a register pair. */
4966 if (WORDS_BIG_ENDIAN)
4967 fputs (reg_names[REGNO (x)+1], file);
4969 fputs (reg_names[REGNO (x)], file);
4972 /* Print out the high order register name of a register pair. */
4973 if (WORDS_BIG_ENDIAN)
4974 fputs (reg_names[REGNO (x)], file);
4976 fputs (reg_names[REGNO (x)+1], file);
4979 /* Print out the second register name of a register pair or quad.
4980 I.e., R (%o0) => %o1. */
4981 fputs (reg_names[REGNO (x)+1], file);
4984 /* Print out the third register name of a register quad.
4985 I.e., S (%o0) => %o2. */
4986 fputs (reg_names[REGNO (x)+2], file);
4989 /* Print out the fourth register name of a register quad.
4990 I.e., T (%o0) => %o3. */
4991 fputs (reg_names[REGNO (x)+3], file);
4994 /* Print a condition code register. */
4995 if (REGNO (x) == SPARC_ICC_REG)
4997 /* We don't handle CC[X]_NOOVmode because they're not supposed
4999 if (GET_MODE (x) == CCmode)
5000 fputs ("%icc", file);
5001 else if (GET_MODE (x) == CCXmode)
5002 fputs ("%xcc", file);
5007 /* %fccN register */
5008 fputs (reg_names[REGNO (x)], file);
5011 /* Print the operand's address only. */
5012 output_address (XEXP (x, 0));
5015 /* In this case we need a register. Use %g0 if the
5016 operand is const0_rtx. */
5018 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
5020 fputs ("%g0", file);
5027 switch (GET_CODE (x))
5029 case IOR: fputs ("or", file); break;
5030 case AND: fputs ("and", file); break;
5031 case XOR: fputs ("xor", file); break;
5032 default: output_operand_lossage ("Invalid %%A operand");
5037 switch (GET_CODE (x))
5039 case IOR: fputs ("orn", file); break;
5040 case AND: fputs ("andn", file); break;
5041 case XOR: fputs ("xnor", file); break;
5042 default: output_operand_lossage ("Invalid %%B operand");
5046 /* These are used by the conditional move instructions. */
5050 enum rtx_code rc = (code == 'c'
5051 ? reverse_condition (GET_CODE (x))
5055 case NE: fputs ("ne", file); break;
5056 case EQ: fputs ("e", file); break;
5057 case GE: fputs ("ge", file); break;
5058 case GT: fputs ("g", file); break;
5059 case LE: fputs ("le", file); break;
5060 case LT: fputs ("l", file); break;
5061 case GEU: fputs ("geu", file); break;
5062 case GTU: fputs ("gu", file); break;
5063 case LEU: fputs ("leu", file); break;
5064 case LTU: fputs ("lu", file); break;
5065 default: output_operand_lossage (code == 'c'
5066 ? "Invalid %%c operand"
5067 : "Invalid %%C operand");
5072 /* These are used by the movr instruction pattern. */
5076 enum rtx_code rc = (code == 'd'
5077 ? reverse_condition (GET_CODE (x))
5081 case NE: fputs ("ne", file); break;
5082 case EQ: fputs ("e", file); break;
5083 case GE: fputs ("gez", file); break;
5084 case LT: fputs ("lz", file); break;
5085 case LE: fputs ("lez", file); break;
5086 case GT: fputs ("gz", file); break;
5087 default: output_operand_lossage (code == 'd'
5088 ? "Invalid %%d operand"
5089 : "Invalid %%D operand");
5096 /* Print a sign-extended character. */
5097 int i = INTVAL (x) & 0xff;
5100 fprintf (file, "%d", i);
5105 /* Operand must be a MEM; write its address. */
5106 if (GET_CODE (x) != MEM)
5107 output_operand_lossage ("Invalid %%f operand");
5108 output_address (XEXP (x, 0));
5112 /* Do nothing special. */
5116 /* Undocumented flag. */
5117 output_operand_lossage ("invalid operand output code");
5120 if (GET_CODE (x) == REG)
5121 fputs (reg_names[REGNO (x)], file);
5122 else if (GET_CODE (x) == MEM)
5125 /* Poor Sun assembler doesn't understand absolute addressing. */
5126 if (CONSTANT_P (XEXP (x, 0))
5127 && ! TARGET_LIVE_G0)
5128 fputs ("%g0+", file);
5129 output_address (XEXP (x, 0));
5132 else if (GET_CODE (x) == HIGH)
5134 fputs ("%hi(", file);
5135 output_addr_const (file, XEXP (x, 0));
5138 else if (GET_CODE (x) == LO_SUM)
5140 print_operand (file, XEXP (x, 0), 0);
5141 if (TARGET_CM_MEDMID)
5142 fputs ("+%l44(", file);
5144 fputs ("+%lo(", file);
5145 output_addr_const (file, XEXP (x, 1));
5148 else if (GET_CODE (x) == CONST_DOUBLE
5149 && (GET_MODE (x) == VOIDmode
5150 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
5152 if (CONST_DOUBLE_HIGH (x) == 0)
5153 fprintf (file, "%u", CONST_DOUBLE_LOW (x));
5154 else if (CONST_DOUBLE_HIGH (x) == -1
5155 && CONST_DOUBLE_LOW (x) < 0)
5156 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
5158 output_operand_lossage ("long long constant not a valid immediate operand");
5160 else if (GET_CODE (x) == CONST_DOUBLE)
5161 output_operand_lossage ("floating point constant not a valid immediate operand");
5162 else { output_addr_const (file, x); }
5165 /* This function outputs assembler code for VALUE to FILE, where VALUE is
5166 a 64 bit (DImode) value. */
5168 /* ??? If there is a 64 bit counterpart to .word that the assembler
5169 understands, then using that would simply this code greatly. */
5170 /* ??? We only output .xword's for symbols and only then in environments
5171 where the assembler can handle them. */
5174 output_double_int (file, value)
5178 if (GET_CODE (value) == CONST_INT)
5180 /* ??? This has endianness issues. */
5181 #if HOST_BITS_PER_WIDE_INT == 64
5182 HOST_WIDE_INT xword = INTVAL (value);
5183 HOST_WIDE_INT high, low;
5185 high = (xword >> 32) & 0xffffffff;
5186 low = xword & 0xffffffff;
5187 ASM_OUTPUT_INT (file, GEN_INT (high));
5188 ASM_OUTPUT_INT (file, GEN_INT (low));
5190 if (INTVAL (value) < 0)
5191 ASM_OUTPUT_INT (file, constm1_rtx);
5193 ASM_OUTPUT_INT (file, const0_rtx);
5194 ASM_OUTPUT_INT (file, value);
5197 else if (GET_CODE (value) == CONST_DOUBLE)
5199 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value)));
5200 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value)));
5202 else if (GET_CODE (value) == SYMBOL_REF
5203 || GET_CODE (value) == CONST
5204 || GET_CODE (value) == PLUS
5205 || (TARGET_ARCH64 &&
5206 (GET_CODE (value) == LABEL_REF
5207 || GET_CODE (value) == CODE_LABEL
5208 || GET_CODE (value) == MINUS)))
5210 if (!TARGET_V9 || TARGET_CM_MEDLOW)
5212 ASM_OUTPUT_INT (file, const0_rtx);
5213 ASM_OUTPUT_INT (file, value);
5217 fprintf (file, "\t%s\t", ASM_LONGLONG);
5218 output_addr_const (file, value);
5219 fprintf (file, "\n");
5226 /* Return the value of a code used in the .proc pseudo-op that says
5227 what kind of result this function returns. For non-C types, we pick
5228 the closest C type. */
5230 #ifndef CHAR_TYPE_SIZE
5231 #define CHAR_TYPE_SIZE BITS_PER_UNIT
5234 #ifndef SHORT_TYPE_SIZE
5235 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
5238 #ifndef INT_TYPE_SIZE
5239 #define INT_TYPE_SIZE BITS_PER_WORD
5242 #ifndef LONG_TYPE_SIZE
5243 #define LONG_TYPE_SIZE BITS_PER_WORD
5246 #ifndef LONG_LONG_TYPE_SIZE
5247 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
5250 #ifndef FLOAT_TYPE_SIZE
5251 #define FLOAT_TYPE_SIZE BITS_PER_WORD
5254 #ifndef DOUBLE_TYPE_SIZE
5255 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5258 #ifndef LONG_DOUBLE_TYPE_SIZE
5259 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5263 sparc_type_code (type)
5266 register unsigned long qualifiers = 0;
5267 register unsigned shift;
5269 /* Only the first 30 bits of the qualifier are valid. We must refrain from
5270 setting more, since some assemblers will give an error for this. Also,
5271 we must be careful to avoid shifts of 32 bits or more to avoid getting
5272 unpredictable results. */
5274 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
5276 switch (TREE_CODE (type))
5282 qualifiers |= (3 << shift);
5287 qualifiers |= (2 << shift);
5291 case REFERENCE_TYPE:
5293 qualifiers |= (1 << shift);
5297 return (qualifiers | 8);
5300 case QUAL_UNION_TYPE:
5301 return (qualifiers | 9);
5304 return (qualifiers | 10);
5307 return (qualifiers | 16);
5310 /* If this is a range type, consider it to be the underlying
5312 if (TREE_TYPE (type) != 0)
5315 /* Carefully distinguish all the standard types of C,
5316 without messing up if the language is not C. We do this by
5317 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
5318 look at both the names and the above fields, but that's redundant.
5319 Any type whose size is between two C types will be considered
5320 to be the wider of the two types. Also, we do not have a
5321 special code to use for "long long", so anything wider than
5322 long is treated the same. Note that we can't distinguish
5323 between "int" and "long" in this code if they are the same
5324 size, but that's fine, since neither can the assembler. */
5326 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
5327 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
5329 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
5330 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
5332 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
5333 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
5336 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
5339 /* If this is a range type, consider it to be the underlying
5341 if (TREE_TYPE (type) != 0)
5344 /* Carefully distinguish all the standard types of C,
5345 without messing up if the language is not C. */
5347 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
5348 return (qualifiers | 6);
5351 return (qualifiers | 7);
5353 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
5354 /* ??? We need to distinguish between double and float complex types,
5355 but I don't know how yet because I can't reach this code from
5356 existing front-ends. */
5357 return (qualifiers | 7); /* Who knows? */
5359 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
5360 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
5361 case FILE_TYPE: /* GNU Pascal FILE type. */
5362 case SET_TYPE: /* GNU Pascal SET type. */
5363 case LANG_TYPE: /* ? */
5367 abort (); /* Not a type! */
5374 /* Nested function support. */
5376 /* Emit RTL insns to initialize the variable parts of a trampoline.
5377 FNADDR is an RTX for the address of the function's pure code.
5378 CXT is an RTX for the static chain value for the function.
5380 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
5381 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
5382 (to store insns). This is a bit excessive. Perhaps a different
5383 mechanism would be better here.
5385 Emit enough FLUSH insns to synchronize the data and instruction caches. */
5388 sparc_initialize_trampoline (tramp, fnaddr, cxt)
5389 rtx tramp, fnaddr, cxt;
5391 /* SPARC 32 bit trampoline:
5394 sethi %hi(static), %g2
5396 or %g2, %lo(static), %g2
5398 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
5399 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
5402 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
5403 expand_binop (SImode, ior_optab,
5404 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
5405 size_int (10), 0, 1),
5406 GEN_INT (0x03000000),
5407 NULL_RTX, 1, OPTAB_DIRECT));
5409 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
5410 expand_binop (SImode, ior_optab,
5411 expand_shift (RSHIFT_EXPR, SImode, cxt,
5412 size_int (10), 0, 1),
5413 GEN_INT (0x05000000),
5414 NULL_RTX, 1, OPTAB_DIRECT));
5416 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
5417 expand_binop (SImode, ior_optab,
5418 expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX),
5419 GEN_INT (0x81c06000),
5420 NULL_RTX, 1, OPTAB_DIRECT));
5422 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
5423 expand_binop (SImode, ior_optab,
5424 expand_and (cxt, GEN_INT (0x3ff), NULL_RTX),
5425 GEN_INT (0x8410a000),
5426 NULL_RTX, 1, OPTAB_DIRECT));
5428 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
5429 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
5430 aligned on a 16 byte boundary so one flush clears it all. */
5431 if (sparc_cpu != PROCESSOR_ULTRASPARC)
5432 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
5433 plus_constant (tramp, 8)))));
5436 /* The 64 bit version is simpler because it makes more sense to load the
5437 values as "immediate" data out of the trampoline. It's also easier since
5438 we can read the PC without clobbering a register. */
5441 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
5442 rtx tramp, fnaddr, cxt;
5452 emit_move_insn (gen_rtx_MEM (SImode, tramp),
5453 GEN_INT (0x83414000));
5454 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
5455 GEN_INT (0xca586018));
5456 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
5457 GEN_INT (0x81c04000));
5458 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
5459 GEN_INT (0xca586010));
5460 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
5461 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 20)), fnaddr);
5462 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, tramp))));
5463 if (sparc_cpu != PROCESSOR_ULTRASPARC)
5464 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
5467 /* Subroutines to support a flat (single) register window calling
5470 /* Single-register window sparc stack frames look like:
5472 Before call After call
5473 +-----------------------+ +-----------------------+
5475 mem | caller's temps. | | caller's temps. |
5477 +-----------------------+ +-----------------------+
5479 | arguments on stack. | | arguments on stack. |
5481 +-----------------------+FP+92->+-----------------------+
5482 | 6 words to save | | 6 words to save |
5483 | arguments passed | | arguments passed |
5484 | in registers, even | | in registers, even |
5485 | if not passed. | | if not passed. |
5486 SP+68->+-----------------------+FP+68->+-----------------------+
5487 | 1 word struct addr | | 1 word struct addr |
5488 +-----------------------+FP+64->+-----------------------+
5490 | 16 word reg save area | | 16 word reg save area |
5492 SP->+-----------------------+ FP->+-----------------------+
5494 | fp/alu reg moves |
5495 FP-16->+-----------------------+
5499 +-----------------------+
5501 | fp register save |
5503 +-----------------------+
5505 | gp register save |
5507 +-----------------------+
5509 | alloca allocations |
5511 +-----------------------+
5513 | arguments on stack |
5515 SP+92->+-----------------------+
5517 | arguments passed |
5518 | in registers, even |
5519 low | if not passed. |
5520 memory SP+68->+-----------------------+
5521 | 1 word struct addr |
5522 SP+64->+-----------------------+
5524 I 16 word reg save area |
5526 SP->+-----------------------+ */
5528 /* Structure to be filled in by sparc_flat_compute_frame_size with register
5529 save masks, and offsets for the current function. */
5531 struct sparc_frame_info
5533 unsigned long total_size; /* # bytes that the entire frame takes up. */
5534 unsigned long var_size; /* # bytes that variables take up. */
5535 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5536 unsigned long extra_size; /* # bytes of extra gunk. */
5537 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5538 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5539 unsigned long gmask; /* Mask of saved gp registers. */
5540 unsigned long fmask; /* Mask of saved fp registers. */
5541 unsigned long reg_offset; /* Offset from new sp to store regs. */
5542 int initialized; /* Nonzero if frame size already calculated. */
5545 /* Current frame information calculated by sparc_flat_compute_frame_size. */
5546 struct sparc_frame_info current_frame_info;
5548 /* Zero structure to initialize current_frame_info. */
5549 struct sparc_frame_info zero_frame_info;
5551 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
5553 #define RETURN_ADDR_REGNUM 15
5554 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
5555 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
5557 #define MUST_SAVE_REGISTER(regno) \
5558 ((regs_ever_live[regno] && !call_used_regs[regno]) \
5559 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
5560 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
5562 /* Return the bytes needed to compute the frame pointer from the current
5566 sparc_flat_compute_frame_size (size)
5567 int size; /* # of var. bytes allocated. */
5570 unsigned long total_size; /* # bytes that the entire frame takes up. */
5571 unsigned long var_size; /* # bytes that variables take up. */
5572 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5573 unsigned long extra_size; /* # extra bytes. */
5574 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5575 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5576 unsigned long gmask; /* Mask of saved gp registers. */
5577 unsigned long fmask; /* Mask of saved fp registers. */
5578 unsigned long reg_offset; /* Offset to register save area. */
5579 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
5581 /* This is the size of the 16 word reg save area, 1 word struct addr
5582 area, and 4 word fp/alu register copy area. */
5583 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
5585 /* Also include the size needed for the 6 parameter registers. */
5586 args_size = current_function_outgoing_args_size + 24;
5587 total_size = var_size + args_size + extra_size;
5595 /* Calculate space needed for gp registers. */
5596 for (regno = 1; regno <= 31; regno++)
5598 if (MUST_SAVE_REGISTER (regno))
5600 /* If we need to save two regs in a row, ensure there's room to bump
5601 up the address to align it to a doubleword boundary. */
5602 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
5604 if (gp_reg_size % 8 != 0)
5606 gp_reg_size += 2 * UNITS_PER_WORD;
5607 gmask |= 3 << regno;
5613 gp_reg_size += UNITS_PER_WORD;
5614 gmask |= 1 << regno;
5619 /* Calculate space needed for fp registers. */
5620 for (regno = 32; regno <= 63; regno++)
5622 if (regs_ever_live[regno] && !call_used_regs[regno])
5624 fp_reg_size += UNITS_PER_WORD;
5625 fmask |= 1 << (regno - 32);
5632 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
5633 /* Ensure save area is 8 byte aligned if we need it. */
5635 if (need_aligned_p && n != 0)
5637 total_size += 8 - n;
5638 reg_offset += 8 - n;
5640 total_size += gp_reg_size + fp_reg_size;
5643 /* ??? This looks a little suspicious. Clarify. */
5644 if (total_size == extra_size)
5645 total_size = extra_size = 0;
5647 total_size = SPARC_STACK_ALIGN (total_size);
5649 /* Save other computed information. */
5650 current_frame_info.total_size = total_size;
5651 current_frame_info.var_size = var_size;
5652 current_frame_info.args_size = args_size;
5653 current_frame_info.extra_size = extra_size;
5654 current_frame_info.gp_reg_size = gp_reg_size;
5655 current_frame_info.fp_reg_size = fp_reg_size;
5656 current_frame_info.gmask = gmask;
5657 current_frame_info.fmask = fmask;
5658 current_frame_info.reg_offset = reg_offset;
5659 current_frame_info.initialized = reload_completed;
5661 /* Ok, we're done. */
5665 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
5668 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
5669 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
5670 [BASE_REG+OFFSET] will always be a valid address.
5672 WORD_OP is either "st" for save, "ld" for restore.
5673 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
5676 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
5677 doubleword_op, base_offset)
5680 unsigned int offset;
5681 unsigned long gmask;
5682 unsigned long fmask;
5684 char *doubleword_op;
5685 unsigned long base_offset;
5689 if (gmask == 0 && fmask == 0)
5692 /* Save registers starting from high to low. We've already saved the
5693 previous frame pointer and previous return address for the debugger's
5694 sake. The debugger allows us to not need a nop in the epilog if at least
5695 one register is reloaded in addition to return address. */
5699 for (regno = 1; regno <= 31; regno++)
5701 if ((gmask & (1L << regno)) != 0)
5703 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
5705 /* We can save two registers in a row. If we're not at a
5706 double word boundary, move to one.
5707 sparc_flat_compute_frame_size ensures there's room to do
5709 if (offset % 8 != 0)
5710 offset += UNITS_PER_WORD;
5712 if (word_op[0] == 's')
5714 fprintf (file, "\t%s\t%s, [%s+%d]\n",
5715 doubleword_op, reg_names[regno],
5717 if (dwarf2out_do_frame ())
5719 char *l = dwarf2out_cfi_label ();
5720 dwarf2out_reg_save (l, regno, offset + base_offset);
5722 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
5726 fprintf (file, "\t%s\t[%s+%d], %s\n",
5727 doubleword_op, base_reg, offset,
5730 offset += 2 * UNITS_PER_WORD;
5735 if (word_op[0] == 's')
5737 fprintf (file, "\t%s\t%s, [%s+%d]\n",
5738 word_op, reg_names[regno],
5740 if (dwarf2out_do_frame ())
5741 dwarf2out_reg_save ("", regno, offset + base_offset);
5744 fprintf (file, "\t%s\t[%s+%d], %s\n",
5745 word_op, base_reg, offset, reg_names[regno]);
5747 offset += UNITS_PER_WORD;
5755 for (regno = 32; regno <= 63; regno++)
5757 if ((fmask & (1L << (regno - 32))) != 0)
5759 if (word_op[0] == 's')
5761 fprintf (file, "\t%s\t%s, [%s+%d]\n",
5762 word_op, reg_names[regno],
5764 if (dwarf2out_do_frame ())
5765 dwarf2out_reg_save ("", regno, offset + base_offset);
5768 fprintf (file, "\t%s\t[%s+%d], %s\n",
5769 word_op, base_reg, offset, reg_names[regno]);
5771 offset += UNITS_PER_WORD;
5777 /* Set up the stack and frame (if desired) for the function. */
5780 sparc_flat_output_function_prologue (file, size)
5784 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5785 unsigned long gmask = current_frame_info.gmask;
5787 /* This is only for the human reader. */
5788 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
5789 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
5791 current_frame_info.var_size,
5792 current_frame_info.gp_reg_size / 4,
5793 current_frame_info.fp_reg_size / 4,
5794 current_function_outgoing_args_size,
5795 current_frame_info.extra_size);
5797 size = SPARC_STACK_ALIGN (size);
5798 size = (! current_frame_info.initialized
5799 ? sparc_flat_compute_frame_size (size)
5800 : current_frame_info.total_size);
5802 /* These cases shouldn't happen. Catch them now. */
5803 if (size == 0 && (gmask || current_frame_info.fmask))
5806 /* Allocate our stack frame by decrementing %sp.
5807 At present, the only algorithm gdb can use to determine if this is a
5808 flat frame is if we always set %i7 if we set %sp. This can be optimized
5809 in the future by putting in some sort of debugging information that says
5810 this is a `flat' function. However, there is still the case of debugging
5811 code without such debugging information (including cases where most fns
5812 have such info, but there is one that doesn't). So, always do this now
5813 so we don't get a lot of code out there that gdb can't handle.
5814 If the frame pointer isn't needn't then that's ok - gdb won't be able to
5815 distinguish us from a non-flat function but there won't (and shouldn't)
5816 be any differences anyway. The return pc is saved (if necessary) right
5817 after %i7 so gdb won't have to look too far to find it. */
5820 unsigned int reg_offset = current_frame_info.reg_offset;
5821 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
5822 char *t1_str = "%g1";
5824 /* Things get a little tricky if local variables take up more than ~4096
5825 bytes and outgoing arguments take up more than ~4096 bytes. When that
5826 happens, the register save area can't be accessed from either end of
5827 the frame. Handle this by decrementing %sp to the start of the gp
5828 register save area, save the regs, update %i7, and then set %sp to its
5829 final value. Given that we only have one scratch register to play
5830 with it is the cheapest solution, and it helps gdb out as it won't
5831 slow down recognition of flat functions.
5832 Don't change the order of insns emitted here without checking with
5833 the gdb folk first. */
5835 /* Is the entire register save area offsettable from %sp? */
5836 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
5840 fprintf (file, "\tadd\t%s, %d, %s\n",
5841 sp_str, -size, sp_str);
5842 if (gmask & FRAME_POINTER_MASK)
5844 fprintf (file, "\tst\t%s, [%s+%d]\n",
5845 fp_str, sp_str, reg_offset);
5846 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
5847 sp_str, -size, fp_str, ASM_COMMENT_START);
5853 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
5854 size, t1_str, sp_str, t1_str, sp_str);
5855 if (gmask & FRAME_POINTER_MASK)
5857 fprintf (file, "\tst\t%s, [%s+%d]\n",
5858 fp_str, sp_str, reg_offset);
5859 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
5860 sp_str, t1_str, fp_str, ASM_COMMENT_START);
5864 if (dwarf2out_do_frame ())
5866 char *l = dwarf2out_cfi_label ();
5867 if (gmask & FRAME_POINTER_MASK)
5869 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
5870 reg_offset - 4 - size);
5871 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
5874 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
5876 if (gmask & RETURN_ADDR_MASK)
5878 fprintf (file, "\tst\t%s, [%s+%d]\n",
5879 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
5880 if (dwarf2out_do_frame ())
5881 dwarf2out_return_save ("", reg_offset - size);
5884 sparc_flat_save_restore (file, sp_str, reg_offset,
5885 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5886 current_frame_info.fmask,
5887 "st", "std", -size);
5891 /* Subtract %sp in two steps, but make sure there is always a
5892 64 byte register save area, and %sp is properly aligned. */
5893 /* Amount to decrement %sp by, the first time. */
5894 unsigned int size1 = ((size - reg_offset + 64) + 15) & -16;
5895 /* Offset to register save area from %sp. */
5896 unsigned int offset = size1 - (size - reg_offset);
5900 fprintf (file, "\tadd\t%s, %d, %s\n",
5901 sp_str, -size1, sp_str);
5902 if (gmask & FRAME_POINTER_MASK)
5904 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
5905 fp_str, sp_str, offset, sp_str, -size1, fp_str,
5912 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
5913 size1, t1_str, sp_str, t1_str, sp_str);
5914 if (gmask & FRAME_POINTER_MASK)
5916 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
5917 fp_str, sp_str, offset, sp_str, t1_str, fp_str,
5922 if (dwarf2out_do_frame ())
5924 char *l = dwarf2out_cfi_label ();
5925 if (gmask & FRAME_POINTER_MASK)
5927 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
5928 offset - 4 - size1);
5929 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
5932 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
5934 if (gmask & RETURN_ADDR_MASK)
5936 fprintf (file, "\tst\t%s, [%s+%d]\n",
5937 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
5938 if (dwarf2out_do_frame ())
5939 /* offset - size1 == reg_offset - size
5940 if reg_offset were updated above like offset. */
5941 dwarf2out_return_save ("", offset - size1);
5944 sparc_flat_save_restore (file, sp_str, offset,
5945 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5946 current_frame_info.fmask,
5947 "st", "std", -size1);
5948 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
5949 size - size1, t1_str, sp_str, t1_str, sp_str);
5950 if (dwarf2out_do_frame ())
5951 if (! (gmask & FRAME_POINTER_MASK))
5952 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
5956 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
5959 /* Do any necessary cleanup after a function to restore stack, frame,
5963 sparc_flat_output_function_epilogue (file, size)
5967 rtx epilogue_delay = current_function_epilogue_delay_list;
5968 int noepilogue = FALSE;
5970 /* This is only for the human reader. */
5971 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
5973 /* The epilogue does not depend on any registers, but the stack
5974 registers, so we assume that if we have 1 pending nop, it can be
5975 ignored, and 2 it must be filled (2 nops occur for integer
5976 multiply and divide). */
5978 size = SPARC_STACK_ALIGN (size);
5979 size = (!current_frame_info.initialized
5980 ? sparc_flat_compute_frame_size (size)
5981 : current_frame_info.total_size);
5983 if (size == 0 && epilogue_delay == 0)
5985 rtx insn = get_last_insn ();
5987 /* If the last insn was a BARRIER, we don't have to write any code
5988 because a jump (aka return) was put there. */
5989 if (GET_CODE (insn) == NOTE)
5990 insn = prev_nonnote_insn (insn);
5991 if (insn && GET_CODE (insn) == BARRIER)
5997 unsigned int reg_offset = current_frame_info.reg_offset;
5999 char *sp_str = reg_names[STACK_POINTER_REGNUM];
6000 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
6001 char *t1_str = "%g1";
6003 /* In the reload sequence, we don't need to fill the load delay
6004 slots for most of the loads, also see if we can fill the final
6005 delay slot if not otherwise filled by the reload sequence. */
6008 fprintf (file, "\tset\t%d, %s\n", size, t1_str);
6010 if (frame_pointer_needed)
6013 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
6014 fp_str, t1_str, sp_str, ASM_COMMENT_START);
6016 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
6017 fp_str, size, sp_str, ASM_COMMENT_START);
6020 /* Is the entire register save area offsettable from %sp? */
6021 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
6027 /* Restore %sp in two steps, but make sure there is always a
6028 64 byte register save area, and %sp is properly aligned. */
6029 /* Amount to increment %sp by, the first time. */
6030 size1 = ((reg_offset - 64 - 16) + 15) & -16;
6031 /* Offset to register save area from %sp. */
6032 reg_offset = size1 - reg_offset;
6034 fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n",
6035 size1, t1_str, sp_str, t1_str, sp_str);
6038 /* We must restore the frame pointer and return address reg first
6039 because they are treated specially by the prologue output code. */
6040 if (current_frame_info.gmask & FRAME_POINTER_MASK)
6042 fprintf (file, "\tld\t[%s+%d], %s\n",
6043 sp_str, reg_offset, fp_str);
6046 if (current_frame_info.gmask & RETURN_ADDR_MASK)
6048 fprintf (file, "\tld\t[%s+%d], %s\n",
6049 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
6053 /* Restore any remaining saved registers. */
6054 sparc_flat_save_restore (file, sp_str, reg_offset,
6055 current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6056 current_frame_info.fmask,
6059 /* If we had to increment %sp in two steps, record it so the second
6060 restoration in the epilogue finishes up. */
6065 fprintf (file, "\tset\t%d, %s\n",
6069 if (current_function_returns_struct)
6070 fprintf (file, "\tjmp\t%%o7+12\n");
6072 fprintf (file, "\tretl\n");
6074 /* If the only register saved is the return address, we need a
6075 nop, unless we have an instruction to put into it. Otherwise
6076 we don't since reloading multiple registers doesn't reference
6077 the register being loaded. */
6083 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
6086 else if (size > 4095)
6087 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
6090 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str);
6093 fprintf (file, "\tnop\n");
6096 /* Reset state info for each function. */
6097 current_frame_info = zero_frame_info;
6099 sparc_output_deferred_case_vectors ();
6102 /* Define the number of delay slots needed for the function epilogue.
6104 On the sparc, we need a slot if either no stack has been allocated,
6105 or the only register saved is the return register. */
6108 sparc_flat_epilogue_delay_slots ()
6110 if (!current_frame_info.initialized)
6111 (void) sparc_flat_compute_frame_size (get_frame_size ());
6113 if (current_frame_info.total_size == 0)
6119 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
6120 Any single length instruction which doesn't reference the stack or frame
6124 sparc_flat_eligible_for_epilogue_delay (trial, slot)
6126 int slot ATTRIBUTE_UNUSED;
6128 rtx pat = PATTERN (trial);
6130 if (get_attr_length (trial) != 1)
6133 /* If %g0 is live, there are lots of things we can't handle.
6134 Rather than trying to find them all now, let's punt and only
6135 optimize things as necessary. */
6139 if (! reg_mentioned_p (stack_pointer_rtx, pat)
6140 && ! reg_mentioned_p (frame_pointer_rtx, pat))
6146 /* Adjust the cost of a scheduling dependency. Return the new cost of
6147 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6150 supersparc_adjust_cost (insn, link, dep_insn, cost)
6156 enum attr_type insn_type;
6158 if (! recog_memoized (insn))
6161 insn_type = get_attr_type (insn);
6163 if (REG_NOTE_KIND (link) == 0)
6165 /* Data dependency; DEP_INSN writes a register that INSN reads some
6168 /* if a load, then the dependence must be on the memory address;
6169 add an extra "cycle". Note that the cost could be two cycles
6170 if the reg was written late in an instruction group; we ca not tell
6172 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
6175 /* Get the delay only if the address of the store is the dependence. */
6176 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
6178 rtx pat = PATTERN(insn);
6179 rtx dep_pat = PATTERN (dep_insn);
6181 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6182 return cost; /* This should not happen! */
6184 /* The dependency between the two instructions was on the data that
6185 is being stored. Assume that this implies that the address of the
6186 store is not dependent. */
6187 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6190 return cost + 3; /* An approximation. */
6193 /* A shift instruction cannot receive its data from an instruction
6194 in the same cycle; add a one cycle penalty. */
6195 if (insn_type == TYPE_SHIFT)
6196 return cost + 3; /* Split before cascade into shift. */
6200 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
6201 INSN writes some cycles later. */
6203 /* These are only significant for the fpu unit; writing a fp reg before
6204 the fpu has finished with it stalls the processor. */
6206 /* Reusing an integer register causes no problems. */
6207 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
6214 /* This describes the state of the UltraSPARC pipeline during
6215 instruction scheduling. */
6217 #define TMASK(__x) (1U << ((int)(__x)))
6218 #define UMASK(__x) (1U << ((int)(__x)))
6220 enum ultra_code { NONE=0, /* no insn at all */
6221 IEU0, /* shifts and conditional moves */
6222 IEU1, /* condition code setting insns, calls+jumps */
6223 IEUN, /* all other single cycle ieu insns */
6224 LSU, /* loads and stores */
6226 FPM, /* FPU pipeline 1, multiplies and divides */
6227 FPA, /* FPU pipeline 2, all other operations */
6228 SINGLE, /* single issue instructions */
6231 static char *ultra_code_names[NUM_ULTRA_CODES] = {
6232 "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI",
6233 "FPM", "FPA", "SINGLE" };
6235 struct ultrasparc_pipeline_state {
6236 /* The insns in this group. */
6239 /* The code for each insn. */
6240 enum ultra_code codes[4];
6242 /* Which insns in this group have been committed by the
6243 scheduler. This is how we determine how many more
6244 can issue this cycle. */
6247 /* How many insns in this group. */
6250 /* Mask of free slots still in this group. */
6251 char free_slot_mask;
6253 /* The slotter uses the following to determine what other
6254 insn types can still make their way into this group. */
6255 char contents [NUM_ULTRA_CODES];
6259 #define ULTRA_NUM_HIST 8
6260 static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST];
6261 static int ultra_cur_hist;
6262 static int ultra_cycles_elapsed;
6264 #define ultra_pipe (ultra_pipe_hist[ultra_cur_hist])
6266 /* Given TYPE_MASK compute the ultra_code it has. */
6267 static enum ultra_code
6268 ultra_code_from_mask (type_mask)
6273 if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE)))
6275 else if (type_mask & (TMASK (TYPE_COMPARE) |
6277 TMASK (TYPE_UNCOND_BRANCH)))
6279 else if (type_mask & (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
6280 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY)))
6282 else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
6283 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
6284 TMASK (TYPE_FPSTORE)))
6286 else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) |
6287 TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRT)))
6289 else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
6290 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)))
6292 else if (type_mask & TMASK (TYPE_BRANCH))
6298 /* Check INSN (a conditional move) and make sure that it's
6299 results are available at this cycle. Return 1 if the
6300 results are in fact ready. */
6302 ultra_cmove_results_ready_p (insn)
6305 struct ultrasparc_pipeline_state *up;
6308 /* If this got dispatched in the previous
6309 group, the results are not ready. */
6310 entry = (ultra_cur_hist - 1) % ULTRA_NUM_HIST;
6311 up = &ultra_pipe_hist[entry];
6314 if (up->group[slot] == insn)
6320 /* Walk backwards in pipeline history looking for FPU
6321 operations which use a mode different than FPMODE and
6322 will create a stall if an insn using FPMODE were to be
6323 dispatched this cycle. */
6325 ultra_fpmode_conflict_exists (fpmode)
6326 enum machine_mode fpmode;
6331 hist_ent = (ultra_cur_hist - 1) % ULTRA_NUM_HIST;
6332 if (ultra_cycles_elapsed < 4)
6333 hist_lim = ultra_cycles_elapsed;
6336 while (hist_lim > 0)
6338 struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent];
6343 rtx insn = up->group[slot];
6344 enum machine_mode this_mode;
6345 enum attr_type this_type;
6349 || GET_CODE (insn) != INSN
6350 || (pat = PATTERN (insn)) == 0
6351 || GET_CODE (pat) != SET)
6354 this_mode = GET_MODE (SET_DEST (pat));
6355 if ((this_mode != SFmode
6356 && this_mode != DFmode)
6357 || this_mode == fpmode)
6360 /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then
6361 we will get a stall. */
6362 if (GET_CODE (SET_SRC (pat)) != ABS
6363 && GET_CODE (SET_SRC (pat)) != NEG
6364 && ((TMASK (get_attr_type (insn)) &
6365 (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) |
6366 TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRT))) == 0))
6370 hist_ent = (hist_ent - 1) % ULTRA_NUM_HIST;
6373 /* No conflicts, safe to dispatch. */
6377 /* Find an instruction in LIST which has one of the
6378 type attributes enumerated in TYPE_MASK. START
6379 says where to begin the search.
6381 NOTE: This scheme depends upon the fact that we
6382 have less than 32 distinct type attributes. */
6384 static int ultra_types_avail;
6387 ultra_find_type (type_mask, list, start)
6394 /* Short circuit if no such insn exists in the ready
6396 if ((type_mask & ultra_types_avail) == 0)
6399 for (i = start; i >= 0; i--)
6403 if (recog_memoized (insn) >= 0
6404 && (TMASK(get_attr_type (insn)) & type_mask))
6406 enum machine_mode fpmode;
6409 int check_depend = 0;
6410 int check_fpmode_conflict = 0;
6412 if (GET_CODE (insn) == INSN
6413 && (pat = PATTERN(insn)) != 0
6414 && GET_CODE (pat) == SET
6415 && !(type_mask & (TMASK (TYPE_STORE) |
6416 TMASK (TYPE_FPSTORE))))
6419 if (GET_MODE (SET_DEST (pat)) == SFmode
6420 || GET_MODE (SET_DEST (pat)) == DFmode)
6422 fpmode = GET_MODE (SET_DEST (pat));
6423 check_fpmode_conflict = 1;
6430 rtx slot_insn = ultra_pipe.group[slot];
6433 /* Already issued, bad dependency, or FPU
6436 && (slot_pat = PATTERN (slot_insn)) != 0
6437 && ((insn == slot_insn)
6438 || (check_depend == 1
6439 && GET_CODE (slot_insn) == INSN
6440 && GET_CODE (slot_pat) == SET
6441 && ((GET_CODE (SET_DEST (slot_pat)) == REG
6442 && GET_CODE (SET_SRC (pat)) == REG
6443 && REGNO (SET_DEST (slot_pat)) ==
6444 REGNO (SET_SRC (pat)))
6445 || (GET_CODE (SET_DEST (slot_pat)) == SUBREG
6446 && GET_CODE (SET_SRC (pat)) == SUBREG
6447 && REGNO (SUBREG_REG (SET_DEST (slot_pat))) ==
6448 REGNO (SUBREG_REG (SET_SRC (pat)))
6449 && SUBREG_WORD (SET_DEST (slot_pat)) ==
6450 SUBREG_WORD (SET_SRC (pat))))
6451 || (check_fpmode_conflict == 1
6452 && GET_CODE (slot_insn) == INSN
6453 && GET_CODE (slot_pat) == SET
6454 && ((GET_MODE (SET_DEST (slot_pat)) == SFmode
6455 || GET_MODE (SET_DEST (slot_pat)) == DFmode)
6456 && GET_MODE (SET_DEST (slot_pat)) != fpmode)))))
6460 /* Check for peculiar result availability and dispatch
6461 interference situations. */
6463 && ultra_cycles_elapsed > 0)
6467 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6469 rtx link_insn = XEXP (link, 0);
6470 if (GET_CODE (link_insn) == INSN
6471 && recog_memoized (link_insn) >= 0
6472 && (TMASK (get_attr_type (link_insn)) &
6473 (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE)))
6474 && ! ultra_cmove_results_ready_p (link_insn))
6478 if (check_fpmode_conflict
6479 && ultra_fpmode_conflict_exists (fpmode))
6492 ultra_build_types_avail (ready, n_ready)
6496 int i = n_ready - 1;
6498 ultra_types_avail = 0;
6501 rtx insn = ready[i];
6503 if (recog_memoized (insn) >= 0)
6504 ultra_types_avail |= TMASK (get_attr_type (insn));
6510 /* Place insn pointed to my IP into the pipeline.
6511 Make element THIS of READY be that insn if it
6512 is not already. TYPE indicates the pipeline class
6513 this insn falls into. */
6515 ultra_schedule_insn (ip, ready, this, type)
6519 enum ultra_code type;
6522 char mask = ultra_pipe.free_slot_mask;
6524 /* Obtain free slot. */
6525 for (pipe_slot = 0; pipe_slot < 4; pipe_slot++)
6526 if ((mask & (1 << pipe_slot)) != 0)
6531 /* In it goes, and it hasn't been committed yet. */
6532 ultra_pipe.group[pipe_slot] = *ip;
6533 ultra_pipe.codes[pipe_slot] = type;
6534 ultra_pipe.contents[type] = 1;
6536 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
6537 ultra_pipe.num_ieu_insns += 1;
6539 ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot));
6540 ultra_pipe.group_size += 1;
6541 ultra_pipe.commit[pipe_slot] = 0;
6543 /* Update ready list. */
6544 if (ip != &ready[this])
6553 /* Advance to the next pipeline group. */
6555 ultra_flush_pipeline ()
6557 ultra_cur_hist = (ultra_cur_hist + 1) % ULTRA_NUM_HIST;
6558 ultra_cycles_elapsed += 1;
6559 bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
6560 ultra_pipe.free_slot_mask = 0xf;
6563 static int ultra_reorder_called_this_block;
6565 /* Init our data structures for this current block. */
6567 ultrasparc_sched_init (dump, sched_verbose)
6571 bzero ((char *) &ultra_pipe_hist, sizeof ultra_pipe_hist);
6572 ultra_pipe.free_slot_mask = 0xf;
6574 ultra_cycles_elapsed = 0;
6575 ultra_reorder_called_this_block = 0;
6578 /* INSN has been scheduled, update pipeline commit state
6579 and return how many instructions are still to be
6580 scheduled in this group. */
6582 ultrasparc_variable_issue (insn)
6585 struct ultrasparc_pipeline_state *up = &ultra_pipe;
6586 int i, left_to_fire;
6589 for (i = 0; i < 4; i++)
6591 if (up->group[i] == 0)
6594 if (up->group[i] == insn)
6598 else if (! up->commit[i])
6602 return left_to_fire;
6605 /* In actual_hazard_this_instance, we may have yanked some
6606 instructions from the ready list due to conflict cost
6607 adjustments. If so, and such an insn was in our pipeline
6608 group, remove it and update state. */
6610 ultra_rescan_pipeline_state (ready, n_ready)
6614 struct ultrasparc_pipeline_state *up = &ultra_pipe;
6617 for (i = 0; i < 4; i++)
6619 rtx insn = up->group[i];
6620 enum ultra_code ucode;
6626 /* If it has been committed, then it was removed from
6627 the ready list because it was actually scheduled,
6628 and that is not the case we are searching for here. */
6629 if (up->commit[i] != 0)
6632 for (j = n_ready - 1; j >= 0; j--)
6633 if (ready[j] == insn)
6636 /* If we didn't find it, toss it. */
6639 enum ultra_code ucode = up->codes[i];
6642 up->codes[i] = NONE;
6643 up->contents[ucode] = 0;
6645 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
6646 up->num_ieu_insns -= 1;
6648 up->free_slot_mask |= (1 << i);
6649 up->group_size -= 1;
6656 ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
6662 struct ultrasparc_pipeline_state *up = &ultra_pipe;
6665 /* We get called once unnecessarily per block of insns
6667 if (ultra_reorder_called_this_block == 0)
6669 ultra_reorder_called_this_block = 1;
6677 fprintf (dump, "\n;;\tUltraSPARC Looking at [");
6678 for (n = n_ready - 1; n >= 0; n--)
6680 rtx insn = ready[n];
6681 enum ultra_code ucode;
6683 if (recog_memoized (insn) < 0)
6685 ucode = ultra_code_from_mask (TMASK (get_attr_type (insn)));
6687 fprintf (dump, "%s(%d) ",
6688 ultra_code_names[ucode],
6691 fprintf (dump, "%s(%d)",
6692 ultra_code_names[ucode],
6695 fprintf (dump, "]\n");
6698 this_insn = n_ready - 1;
6700 /* Skip over junk we don't understand. */
6701 while ((this_insn >= 0)
6702 && recog_memoized (ready[this_insn]) < 0)
6705 ultra_build_types_avail (ready, this_insn + 1);
6707 while (this_insn >= 0) {
6708 int old_group_size = up->group_size;
6710 if (up->group_size != 0)
6714 num_committed = (up->commit[0] + up->commit[1] +
6715 up->commit[2] + up->commit[3]);
6716 /* If nothing has been commited from our group, or all of
6717 them have. Clear out the (current cycle's) pipeline
6718 state and start afresh. */
6719 if (num_committed == 0
6720 || num_committed == up->group_size)
6722 bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
6723 ultra_pipe.free_slot_mask = 0xf;
6728 /* OK, some ready list insns got requeued and thus removed
6729 from the ready list. Account for this fact. */
6730 ultra_rescan_pipeline_state (ready, n_ready);
6732 /* Something "changed", make this look like a newly
6733 formed group so the code at the end of the loop
6734 knows that progress was in fact made. */
6735 if (up->group_size != old_group_size)
6736 old_group_size == 0;
6740 if (up->group_size == 0)
6742 /* If the pipeline is (still) empty and we have any single
6743 group insns, get them out now as this is a good time. */
6744 rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_ADDRESS) |
6745 TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) |
6746 TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)),
6750 ultra_schedule_insn (ip, ready, this_insn, SINGLE);
6754 /* If we are not in the process of emptying out the pipe, try to
6755 obtain an instruction which must be the first in it's group. */
6756 ip = ultra_find_type ((TMASK (TYPE_CALL) |
6757 TMASK (TYPE_CALL_NO_DELAY_SLOT) |
6758 TMASK (TYPE_UNCOND_BRANCH)),
6762 ultra_schedule_insn (ip, ready, this_insn, IEU1);
6765 else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) |
6766 TMASK (TYPE_FPDIVD) |
6767 TMASK (TYPE_FPSQRT)),
6768 ready, this_insn)) != 0)
6770 ultra_schedule_insn (ip, ready, this_insn, FPM);
6775 /* Try to fill the integer pipeline. First, look for an IEU0 specific
6776 operation. We can't do more IEU operations if the first 3 slots are
6777 all full or we have dispatched two IEU insns already. */
6778 if ((up->free_slot_mask & 0x7) != 0
6779 && up->num_ieu_insns < 2
6780 && up->contents[IEU0] == 0
6781 && up->contents[IEUN] == 0)
6783 rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn);
6786 ultra_schedule_insn (ip, ready, this_insn, IEU0);
6791 /* If we can, try to find an IEU1 specific or an unnamed
6793 if ((up->free_slot_mask & 0x7) != 0
6794 && up->num_ieu_insns < 2)
6796 rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
6797 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY) |
6798 (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)),
6804 ultra_schedule_insn (ip, ready, this_insn,
6805 (!up->contents[IEU1]
6806 && get_attr_type (insn) == TYPE_COMPARE)
6812 /* If only one IEU insn has been found, try to find another unnamed
6813 IEU operation or an IEU1 specific one. */
6814 if ((up->free_slot_mask & 0x7) != 0
6815 && up->num_ieu_insns < 2)
6818 int tmask = (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
6819 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY));
6821 if (!up->contents[IEU1])
6822 tmask |= TMASK (TYPE_COMPARE);
6823 ip = ultra_find_type (tmask, ready, this_insn);
6828 ultra_schedule_insn (ip, ready, this_insn,
6829 (!up->contents[IEU1]
6830 && get_attr_type (insn) == TYPE_COMPARE)
6836 /* Try for a load or store, but such an insn can only be issued
6837 if it is within' one of the first 3 slots. */
6838 if ((up->free_slot_mask & 0x7) != 0
6839 && up->contents[LSU] == 0)
6841 rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
6842 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
6843 TMASK (TYPE_FPSTORE)), ready, this_insn);
6846 ultra_schedule_insn (ip, ready, this_insn, LSU);
6851 /* Now find FPU operations, first FPM class. But not divisions or
6852 square-roots because those will break the group up. Unlike all
6853 the previous types, these can go in any slot. */
6854 if (up->free_slot_mask != 0
6855 && up->contents[FPM] == 0)
6857 rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn);
6860 ultra_schedule_insn (ip, ready, this_insn, FPM);
6865 /* Continue on with FPA class if we have not filled the group already. */
6866 if (up->free_slot_mask != 0
6867 && up->contents[FPA] == 0)
6869 rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
6870 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)),
6874 ultra_schedule_insn (ip, ready, this_insn, FPA);
6879 /* Finally, maybe stick a branch in here. */
6880 if (up->free_slot_mask != 0
6881 && up->contents[CTI] == 0)
6883 rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn);
6885 /* Try to slip in a branch only if it is one of the
6886 next 2 in the ready list. */
6887 if (ip && ((&ready[this_insn] - ip) < 2))
6889 ultra_schedule_insn (ip, ready, this_insn, CTI);
6895 for (i = 0; i < 4; i++)
6896 if ((up->free_slot_mask & (1 << i)) == 0)
6899 /* See if we made any progress... */
6900 if (old_group_size != up->group_size)
6903 /* Clean out the (current cycle's) pipeline state
6904 and try once more. */
6905 bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
6906 ultra_pipe.free_slot_mask = 0xf;
6913 fprintf (dump, ";;\tUltraSPARC Launched [");
6914 gsize = up->group_size;
6915 for (n = 0; n < 4; n++)
6917 rtx insn = up->group[n];
6924 fprintf (dump, "%s(%d) ",
6925 ultra_code_names[up->codes[n]],
6928 fprintf (dump, "%s(%d)",
6929 ultra_code_names[up->codes[n]],
6932 fprintf (dump, "]\n");
6937 ultrasparc_adjust_cost (insn, link, dep_insn, previous, cost)
6944 enum attr_type insn_type, dep_type;
6945 rtx pat = PATTERN(insn);
6946 rtx dep_pat = PATTERN (dep_insn);
6948 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
6951 insn_type = get_attr_type (insn);
6952 dep_type = get_attr_type (dep_insn);
6954 /* Nothing issues in parallel with integer multiplies, so
6955 mark as zero cost since the scheduler can not do anything
6957 if (insn_type == TYPE_IMUL)
6960 #define SLOW_FP(dep_type) \
6961 (dep_type == TYPE_FPSQRT || dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
6963 switch (REG_NOTE_KIND (link))
6966 /* Data dependency; DEP_INSN writes a register that INSN reads some
6969 if (dep_type == TYPE_CMOVE)
6971 /* Instructions that read the result of conditional moves cannot
6972 be in the same group or the following group. */
6978 /* UltraSPARC can dual issue a store and an instruction setting
6979 the value stored, except for divide and square root. */
6981 if (! SLOW_FP (dep_type))
6986 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6989 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6990 /* The dependency between the two instructions is on the data
6991 that is being stored. Assume that the address of the store
6992 is not also dependent. */
6999 /* A load does not return data until at least 11 cycles after
7000 a store to the same location. 3 cycles are accounted for
7001 in the load latency; add the other 8 here. */
7002 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7004 /* If the addresses are not equal this may be a false
7005 dependency because pointer aliasing could not be
7006 determined. Add only 2 cycles in that case. 2 is
7007 an arbitrary compromise between 8, which would cause
7008 the scheduler to generate worse code elsewhere to
7009 compensate for a dependency which might not really
7011 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7012 || GET_CODE (SET_SRC (pat)) != MEM
7013 || GET_CODE (SET_DEST (dep_pat)) != MEM
7014 || ! rtx_equal_p (XEXP (SET_SRC (pat), 0),
7015 XEXP (SET_DEST (dep_pat), 0)))
7023 /* Compare to branch latency is 0. There is no benefit from
7024 separating compare and branch. */
7025 if (dep_type == TYPE_COMPARE)
7027 /* Floating point compare to branch latency is less than
7028 compare to conditional move. */
7029 if (dep_type == TYPE_FPCMP)
7034 /* FMOVR class instructions can not issue in the same cycle
7035 or the cycle after an instruction which writes any
7036 integer register. Model this as cost 2 for dependent
7038 if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY
7039 || dep_type == TYPE_BINARY)
7042 /* Otherwise check as for integer conditional moves. */
7045 /* Conditional moves involving integer registers wait until
7046 3 cycles after loads return data. The interlock applies
7047 to all loads, not just dependent loads, but that is hard
7049 if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD)
7059 /* Divide and square root lock destination registers for full latency. */
7060 if (! SLOW_FP (dep_type))
7064 case REG_DEP_OUTPUT:
7065 /* IEU and FPU instruction that have the same destination
7066 register cannot be grouped together. */
7073 /* Other costs not accounted for:
7074 - Single precision floating point loads lock the other half of
7075 the even/odd register pair.
7076 - Several hazards associated with ldd/std are ignored because these
7077 instructions are rarely generated for V9.
7078 - The floating point pipeline can not have both a single and double
7079 precision operation active at the same time. Format conversions
7080 and graphics instructions are given honorary double precision status.
7081 - call and jmpl are always the first instruction in a group. */
7094 /* Assume V9 processors are capable of at least dual-issue. */
7096 case PROCESSOR_SUPERSPARC:
7098 case PROCESSOR_ULTRASPARC:
7104 set_extends(x, insn)
7107 register rtx pat = PATTERN (insn);
7109 switch (GET_CODE (SET_SRC (pat)))
7111 /* Load and some shift instructions zero extend. */
7114 /* sethi clears the high bits */
7116 /* LO_SUM is used with sethi. sethi cleared the high
7117 bits and the values used with lo_sum are positive */
7119 /* Store flag stores 0 or 1 */
7129 rtx op1 = XEXP (SET_SRC (pat), 1);
7130 if (GET_CODE (op1) == CONST_INT)
7131 return INTVAL (op1) >= 0;
7132 if (GET_CODE (XEXP (SET_SRC (pat), 0)) == REG
7133 && sparc_check_64 (XEXP (SET_SRC (pat), 0), insn) == 1)
7135 if (GET_CODE (op1) == REG
7136 && sparc_check_64 ((op1), insn) == 1)
7141 return GET_MODE (SET_SRC (pat)) == SImode;
7142 /* Positive integers leave the high bits zero. */
7144 return ! (CONST_DOUBLE_LOW (x) & 0x80000000);
7146 return ! (INTVAL (x) & 0x80000000);
7149 return - (GET_MODE (SET_SRC (pat)) == SImode);
7155 /* We _ought_ to have only one kind per function, but... */
7156 static rtx sparc_addr_diff_list;
7157 static rtx sparc_addr_list;
7160 sparc_defer_case_vector (lab, vec, diff)
7164 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7166 sparc_addr_diff_list
7167 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7169 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7173 sparc_output_addr_vec (vec)
7176 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7177 int idx, vlen = XVECLEN (body, 0);
7179 #ifdef ASM_OUTPUT_CASE_LABEL
7180 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7183 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7186 for (idx = 0; idx < vlen; idx++)
7188 ASM_OUTPUT_ADDR_VEC_ELT
7189 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7194 sparc_output_addr_diff_vec (vec)
7197 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7198 rtx base = XEXP (XEXP (body, 0), 0);
7199 int idx, vlen = XVECLEN (body, 1);
7201 #ifdef ASM_OUTPUT_CASE_LABEL
7202 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7205 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7208 for (idx = 0; idx < vlen; idx++)
7210 ASM_OUTPUT_ADDR_DIFF_ELT
7213 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7214 CODE_LABEL_NUMBER (base));
7219 sparc_output_deferred_case_vectors ()
7223 /* Align to cache line in the function's code section. */
7224 function_section (current_function_decl);
7225 ASM_OUTPUT_ALIGN (asm_out_file, 5);
7227 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7228 sparc_output_addr_vec (XEXP (t, 0));
7229 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7230 sparc_output_addr_diff_vec (XEXP (t, 0));
7232 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7235 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7236 unknown. Return 1 if the high bits are zero, -1 if the register is
7239 sparc_check_64 (x, insn)
7242 /* If a register is set only once it is safe to ignore insns this
7243 code does not know how to handle. The loop will either recognize
7244 the single set and return the correct value or fail to recognize
7248 if (GET_CODE (x) == REG
7249 && flag_expensive_optimizations
7250 && REG_N_SETS (REGNO (x)) == 1)
7256 insn = get_last_insn_anywhere ();
7261 while ((insn = PREV_INSN (insn)))
7263 switch (GET_CODE (insn))
7276 rtx pat = PATTERN (insn);
7277 if (GET_CODE (pat) != SET)
7279 if (rtx_equal_p (x, SET_DEST (pat)))
7280 return set_extends (x, insn);
7281 if (reg_overlap_mentioned_p (SET_DEST (pat), x))
7290 sparc_v8plus_shift (operands, insn, opcode)
7295 static char asm_code[60];
7297 if (GET_CODE (operands[3]) == SCRATCH)
7298 operands[3] = operands[0];
7299 if (GET_CODE (operands[1]) == CONST_INT)
7301 output_asm_insn ("mov %1,%3", operands);
7305 output_asm_insn ("sllx %H1,32,%3", operands);
7306 if (sparc_check_64 (operands[1], insn) <= 0)
7307 output_asm_insn ("srl %L1,0,%L1", operands);
7308 output_asm_insn ("or %L1,%3,%3", operands);
7311 strcpy(asm_code, opcode);
7312 if (which_alternative != 2)
7313 return strcat (asm_code, " %0,%2,%L0\n\tsrlx %L0,32,%H0");
7315 return strcat (asm_code, " %3,%2,%3\n\tsrlx %3,32,%H0\n\tmov %3,%L0");
7319 /* Return 1 if DEST and SRC reference only global and in registers. */
7322 sparc_return_peephole_ok (dest, src)
7329 if (GET_CODE (src) != CONST_INT
7330 && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src)))
7332 return IN_OR_GLOBAL_P (dest);