1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
41 /* 1 if the caller has placed an "unimp" insn immediately after the call.
42 This is used in v8 code when calling a function that returns a structure.
43 v9 doesn't have this. Be careful to have this test be the same as that
46 #define SKIP_CALLERS_UNIMP_P \
47 (!TARGET_ARCH64 && current_function_returns_struct \
48 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
49 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
52 /* Global variables for machine-dependent things. */
54 /* Size of frame. Need to know this to emit return insns from leaf procedures.
55 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
56 reload pass. This is important as the value is later used in insn
57 scheduling (to see what can go in a delay slot).
58 APPARENT_FSIZE is the size of the stack less the register save area and less
59 the outgoing argument area. It is used when saving call preserved regs. */
60 static int apparent_fsize;
61 static int actual_fsize;
63 /* Save the operands last given to a compare for use when we
64 generate a scc or bcc insn. */
66 rtx sparc_compare_op0, sparc_compare_op1;
68 /* We may need an epilogue if we spill too many registers.
69 If this is non-zero, then we branch here for the epilogue. */
70 static rtx leaf_label;
74 /* Vector to say how input registers are mapped to output
75 registers. FRAME_POINTER_REGNUM cannot be remapped by
76 this function to eliminate it. You must use -fomit-frame-pointer
78 char leaf_reg_remap[] =
79 { 0, 1, 2, 3, 4, 5, 6, 7,
80 -1, -1, -1, -1, -1, -1, 14, -1,
81 -1, -1, -1, -1, -1, -1, -1, -1,
82 8, 9, 10, 11, 12, 13, -1, 15,
84 32, 33, 34, 35, 36, 37, 38, 39,
85 40, 41, 42, 43, 44, 45, 46, 47,
86 48, 49, 50, 51, 52, 53, 54, 55,
87 56, 57, 58, 59, 60, 61, 62, 63,
88 64, 65, 66, 67, 68, 69, 70, 71,
89 72, 73, 74, 75, 76, 77, 78, 79,
90 80, 81, 82, 83, 84, 85, 86, 87,
91 88, 89, 90, 91, 92, 93, 94, 95,
96 /* Name of where we pretend to think the frame pointer points.
97 Normally, this is "%fp", but if we are in a leaf procedure,
98 this is "%sp+something". We record "something" separately as it may be
99 too big for reg+constant addressing. */
101 static char *frame_base_name;
102 static int frame_base_offset;
104 static rtx pic_setup_code PROTO((void));
105 static rtx find_addr_reg PROTO((rtx));
106 static void sparc_init_modes PROTO((void));
107 static int save_regs PROTO((FILE *, int, int, char *,
109 static int restore_regs PROTO((FILE *, int, int, char *, int, int));
110 static void build_big_number PROTO((FILE *, int, char *));
111 static int function_arg_slotno PROTO((const CUMULATIVE_ARGS *,
112 enum machine_mode, tree, int, int,
114 static void sparc_output_addr_vec PROTO((rtx));
115 static void sparc_output_addr_diff_vec PROTO((rtx));
116 static void sparc_output_deferred_case_vectors PROTO((void));
118 #ifdef DWARF2_DEBUGGING_INFO
119 extern char *dwarf2out_cfi_label ();
122 /* Option handling. */
124 /* Code model option as passed by user. */
125 char *sparc_cmodel_string;
127 enum cmodel sparc_cmodel;
129 /* Record alignment options as passed by user. */
130 char *sparc_align_loops_string;
131 char *sparc_align_jumps_string;
132 char *sparc_align_funcs_string;
134 /* Parsed values, as a power of two. */
135 int sparc_align_loops;
136 int sparc_align_jumps;
137 int sparc_align_funcs;
139 struct sparc_cpu_select sparc_select[] =
141 /* switch name, tune arch */
142 { (char *)0, "default", 1, 1 },
143 { (char *)0, "-mcpu=", 1, 1 },
144 { (char *)0, "-mtune=", 1, 0 },
148 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
149 enum processor_type sparc_cpu;
151 /* Validate and override various options, and do some machine dependent
155 sparc_override_options ()
157 static struct code_model {
162 { "medlow", CM_MEDLOW },
163 { "medmid", CM_MEDMID },
164 { "medany", CM_MEDANY },
165 { "embmedany", CM_EMBMEDANY },
168 struct code_model *cmodel;
169 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
170 static struct cpu_default {
174 /* There must be one entry here for each TARGET_CPU value. */
175 { TARGET_CPU_sparc, "cypress" },
176 { TARGET_CPU_sparclet, "tsc701" },
177 { TARGET_CPU_sparclite, "f930" },
178 { TARGET_CPU_v8, "v8" },
179 { TARGET_CPU_supersparc, "supersparc" },
180 { TARGET_CPU_v9, "v9" },
181 { TARGET_CPU_ultrasparc, "ultrasparc" },
184 struct cpu_default *def;
185 /* Table of values for -m{cpu,tune}=. */
186 static struct cpu_table {
188 enum processor_type processor;
192 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
193 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
194 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
195 /* TI TMS390Z55 supersparc */
196 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
197 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
198 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
199 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
200 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
201 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
202 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
204 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
205 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
207 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 },
210 struct cpu_table *cpu;
211 struct sparc_cpu_select *sel;
214 #ifndef SPARC_BI_ARCH
215 /* Check for unsupported architecture size. */
216 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
218 error ("%s is not supported by this configuration",
219 DEFAULT_ARCH32_P ? "-m64" : "-m32");
223 /* Code model selection. */
224 sparc_cmodel = SPARC_DEFAULT_CMODEL;
225 if (sparc_cmodel_string != NULL)
229 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
230 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
232 if (cmodel->name == NULL)
233 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
235 sparc_cmodel = cmodel->value;
238 error ("-mcmodel= is not supported on 32 bit systems");
241 fpu = TARGET_FPU; /* save current -mfpu status */
243 /* Set the default CPU. */
244 for (def = &cpu_default[0]; def->name; ++def)
245 if (def->cpu == TARGET_CPU_DEFAULT)
249 sparc_select[0].string = def->name;
251 for (sel = &sparc_select[0]; sel->name; ++sel)
255 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
256 if (! strcmp (sel->string, cpu->name))
259 sparc_cpu = cpu->processor;
263 target_flags &= ~cpu->disable;
264 target_flags |= cpu->enable;
270 error ("bad value (%s) for %s switch", sel->string, sel->name);
274 /* If -mfpu or -mno-fpu was explicitly used, don't override with
275 the processor default. */
277 target_flags = (target_flags & ~MASK_FPU) | fpu;
279 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
280 if (TARGET_V9 && TARGET_ARCH32)
281 target_flags |= MASK_DEPRECATED_V8_INSNS;
283 /* V8PLUS requires V9 */
285 target_flags &= ~MASK_V8PLUS;
287 /* Don't use stack biasing in 32 bit mode. */
289 target_flags &= ~MASK_STACK_BIAS;
291 /* Validate -malign-loops= value, or provide default. */
292 if (sparc_align_loops_string)
294 sparc_align_loops = exact_log2 (atoi (sparc_align_loops_string));
295 if (sparc_align_loops < 2 || sparc_align_loops > 7)
296 fatal ("-malign-loops=%s is not between 4 and 128 or is not a power of two",
297 sparc_align_loops_string);
301 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
302 its 0. This sounds a bit kludgey. */
303 sparc_align_loops = 0;
306 /* Validate -malign-jumps= value, or provide default. */
307 if (sparc_align_jumps_string)
309 sparc_align_jumps = exact_log2 (atoi (sparc_align_jumps_string));
310 if (sparc_align_jumps < 2 || sparc_align_loops > 7)
311 fatal ("-malign-jumps=%s is not between 4 and 128 or is not a power of two",
312 sparc_align_jumps_string);
316 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
317 its 0. This sounds a bit kludgey. */
318 sparc_align_jumps = 0;
321 /* Validate -malign-functions= value, or provide default. */
322 if (sparc_align_funcs_string)
324 sparc_align_funcs = exact_log2 (atoi (sparc_align_funcs_string));
325 if (sparc_align_funcs < 2 || sparc_align_loops > 7)
326 fatal ("-malign-functions=%s is not between 4 and 128 or is not a power of two",
327 sparc_align_funcs_string);
330 sparc_align_funcs = DEFAULT_SPARC_ALIGN_FUNCS;
332 /* Validate PCC_STRUCT_RETURN. */
333 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
334 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
336 /* Do various machine dependent initializations. */
340 /* Miscellaneous utilities. */
342 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
343 or branch on register contents instructions. */
349 return (code == EQ || code == NE || code == GE || code == LT
350 || code == LE || code == GT);
354 /* Operand constraints. */
356 /* Return non-zero only if OP is a register of mode MODE,
357 or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because
358 %g0 may contain anything. */
361 reg_or_0_operand (op, mode)
363 enum machine_mode mode;
365 if (register_operand (op, mode))
369 if (op == const0_rtx)
371 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
372 && CONST_DOUBLE_HIGH (op) == 0
373 && CONST_DOUBLE_LOW (op) == 0)
375 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
376 && GET_CODE (op) == CONST_DOUBLE
377 && fp_zero_operand (op))
382 /* Nonzero if OP is a floating point value with value 0.0. */
390 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
391 return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r));
394 /* Nonzero if OP is an integer register. */
397 intreg_operand (op, mode)
399 enum machine_mode mode ATTRIBUTE_UNUSED;
401 return (register_operand (op, SImode)
402 || (TARGET_ARCH64 && register_operand (op, DImode)));
405 /* Nonzero if OP is a floating point condition code register. */
408 fcc_reg_operand (op, mode)
410 enum machine_mode mode;
412 /* This can happen when recog is called from combine. Op may be a MEM.
413 Fail instead of calling abort in this case. */
414 if (GET_CODE (op) != REG)
417 if (mode != VOIDmode && mode != GET_MODE (op))
420 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
423 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
424 if (reg_renumber == 0)
425 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
426 return REGNO_OK_FOR_CCFP_P (REGNO (op));
428 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
432 /* Nonzero if OP is an integer or floating point condition code register. */
435 icc_or_fcc_reg_operand (op, mode)
437 enum machine_mode mode;
439 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
441 if (mode != VOIDmode && mode != GET_MODE (op))
444 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
449 return fcc_reg_operand (op, mode);
452 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
454 restore_operand (op, mode)
456 enum machine_mode mode;
458 return (GET_CODE (op) == REG && GET_MODE (op) == mode
459 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
462 /* Call insn on SPARC can take a PC-relative constant address, or any regular
466 call_operand (op, mode)
468 enum machine_mode mode;
470 if (GET_CODE (op) != MEM)
473 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
477 call_operand_address (op, mode)
479 enum machine_mode mode;
481 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
484 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
485 reference and a constant. */
488 symbolic_operand (op, mode)
490 enum machine_mode mode;
492 switch (GET_CODE (op))
500 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
501 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
502 && GET_CODE (XEXP (op, 1)) == CONST_INT);
504 /* ??? This clause seems to be irrelevant. */
506 return GET_MODE (op) == mode;
513 /* Return truth value of statement that OP is a symbolic memory
514 operand of mode MODE. */
517 symbolic_memory_operand (op, mode)
519 enum machine_mode mode ATTRIBUTE_UNUSED;
521 if (GET_CODE (op) == SUBREG)
522 op = SUBREG_REG (op);
523 if (GET_CODE (op) != MEM)
526 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
527 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
530 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
533 label_ref_operand (op, mode)
535 enum machine_mode mode;
537 if (GET_CODE (op) != LABEL_REF)
539 if (GET_MODE (op) != mode)
544 /* Return 1 if the operand is an argument used in generating pic references
545 in either the medium/low or medium/anywhere code models of sparc64. */
548 sp64_medium_pic_operand (op, mode)
550 enum machine_mode mode ATTRIBUTE_UNUSED;
552 /* Check for (const (minus (symbol_ref:GOT)
553 (const (minus (label) (pc))))). */
554 if (GET_CODE (op) != CONST)
557 if (GET_CODE (op) != MINUS)
559 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
561 /* ??? Ensure symbol is GOT. */
562 if (GET_CODE (XEXP (op, 1)) != CONST)
564 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
569 /* Return 1 if the operand is a data segment reference. This includes
570 the readonly data segment, or in other words anything but the text segment.
571 This is needed in the medium/anywhere code model on v9. These values
572 are accessed with EMBMEDANY_BASE_REG. */
575 data_segment_operand (op, mode)
577 enum machine_mode mode ATTRIBUTE_UNUSED;
579 switch (GET_CODE (op))
582 return ! SYMBOL_REF_FLAG (op);
584 /* Assume canonical format of symbol + constant.
587 return data_segment_operand (XEXP (op, 0));
593 /* Return 1 if the operand is a text segment reference.
594 This is needed in the medium/anywhere code model on v9. */
597 text_segment_operand (op, mode)
599 enum machine_mode mode ATTRIBUTE_UNUSED;
601 switch (GET_CODE (op))
606 return SYMBOL_REF_FLAG (op);
608 /* Assume canonical format of symbol + constant.
611 return text_segment_operand (XEXP (op, 0));
617 /* Return 1 if the operand is either a register or a memory operand that is
621 reg_or_nonsymb_mem_operand (op, mode)
623 enum machine_mode mode;
625 if (register_operand (op, mode))
628 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
635 splittable_symbolic_memory_operand (op, mode)
637 enum machine_mode mode ATTRIBUTE_UNUSED;
639 if (GET_CODE (op) != MEM)
641 if (! symbolic_operand (XEXP (op, 0), Pmode))
647 splittable_immediate_memory_operand (op, mode)
649 enum machine_mode mode ATTRIBUTE_UNUSED;
651 if (GET_CODE (op) != MEM)
653 if (! immediate_operand (XEXP (op, 0), Pmode))
658 /* Return truth value of whether OP is EQ or NE. */
663 enum machine_mode mode ATTRIBUTE_UNUSED;
665 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
668 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
669 or LTU for non-floating-point. We handle those specially. */
672 normal_comp_operator (op, mode)
674 enum machine_mode mode ATTRIBUTE_UNUSED;
676 enum rtx_code code = GET_CODE (op);
678 if (GET_RTX_CLASS (code) != '<')
681 if (GET_MODE (XEXP (op, 0)) == CCFPmode
682 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
685 return (code != NE && code != EQ && code != GEU && code != LTU);
688 /* Return 1 if this is a comparison operator. This allows the use of
689 MATCH_OPERATOR to recognize all the branch insns. */
692 noov_compare_op (op, mode)
694 enum machine_mode mode ATTRIBUTE_UNUSED;
696 enum rtx_code code = GET_CODE (op);
698 if (GET_RTX_CLASS (code) != '<')
701 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
702 /* These are the only branches which work with CC_NOOVmode. */
703 return (code == EQ || code == NE || code == GE || code == LT);
707 /* Nonzero if OP is a comparison operator suitable for use in v9
708 conditional move or branch on register contents instructions. */
711 v9_regcmp_op (op, mode)
713 enum machine_mode mode ATTRIBUTE_UNUSED;
715 enum rtx_code code = GET_CODE (op);
717 if (GET_RTX_CLASS (code) != '<')
720 return v9_regcmp_p (code);
723 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
728 enum machine_mode mode ATTRIBUTE_UNUSED;
730 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
733 /* Return nonzero if OP is an operator of mode MODE which can set
734 the condition codes explicitly. We do not include PLUS and MINUS
735 because these require CC_NOOVmode, which we handle explicitly. */
738 cc_arithop (op, mode)
740 enum machine_mode mode ATTRIBUTE_UNUSED;
742 if (GET_CODE (op) == AND
743 || GET_CODE (op) == IOR
744 || GET_CODE (op) == XOR)
750 /* Return nonzero if OP is an operator of mode MODE which can bitwise
751 complement its second operand and set the condition codes explicitly. */
754 cc_arithopn (op, mode)
756 enum machine_mode mode ATTRIBUTE_UNUSED;
758 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
759 and (xor ... (not ...)) to (not (xor ...)). */
760 return (GET_CODE (op) == AND
761 || GET_CODE (op) == IOR);
764 /* Return true if OP is a register, or is a CONST_INT that can fit in a
765 signed 13 bit immediate field. This is an acceptable SImode operand for
766 most 3 address instructions. */
769 arith_operand (op, mode)
771 enum machine_mode mode;
774 if (register_operand (op, mode)
775 || GET_CODE (op) == CONSTANT_P_RTX)
777 if (GET_CODE (op) != CONST_INT)
779 val = INTVAL (op) & 0xffffffff;
780 return SPARC_SIMM13_P (val);
783 /* Return true if OP is a register, or is a CONST_INT that can fit in a
784 signed 11 bit immediate field. This is an acceptable SImode operand for
785 the movcc instructions. */
788 arith11_operand (op, mode)
790 enum machine_mode mode;
792 return (register_operand (op, mode)
793 || GET_CODE (op) == CONSTANT_P_RTX
794 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
797 /* Return true if OP is a register, or is a CONST_INT that can fit in a
798 signed 10 bit immediate field. This is an acceptable SImode operand for
799 the movrcc instructions. */
802 arith10_operand (op, mode)
804 enum machine_mode mode;
806 return (register_operand (op, mode)
807 || GET_CODE (op) == CONSTANT_P_RTX
808 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
811 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
812 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
814 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
815 can fit in a 13 bit immediate field. This is an acceptable DImode operand
816 for most 3 address instructions. */
819 arith_double_operand (op, mode)
821 enum machine_mode mode;
823 return (register_operand (op, mode)
824 || GET_CODE (op) == CONSTANT_P_RTX
825 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
827 && GET_CODE (op) == CONST_DOUBLE
828 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
829 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
831 && GET_CODE (op) == CONST_DOUBLE
832 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
833 && ((CONST_DOUBLE_HIGH (op) == -1
834 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
835 || (CONST_DOUBLE_HIGH (op) == 0
836 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
839 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
840 can fit in an 11 bit immediate field. This is an acceptable DImode
841 operand for the movcc instructions. */
842 /* ??? Replace with arith11_operand? */
845 arith11_double_operand (op, mode)
847 enum machine_mode mode;
849 return (register_operand (op, mode)
850 || GET_CODE (op) == CONSTANT_P_RTX
851 || (GET_CODE (op) == CONST_DOUBLE
852 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
853 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
854 && ((CONST_DOUBLE_HIGH (op) == -1
855 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
856 || (CONST_DOUBLE_HIGH (op) == 0
857 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
858 || (GET_CODE (op) == CONST_INT
859 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
860 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
863 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
864 can fit in an 10 bit immediate field. This is an acceptable DImode
865 operand for the movrcc instructions. */
866 /* ??? Replace with arith10_operand? */
869 arith10_double_operand (op, mode)
871 enum machine_mode mode;
873 return (register_operand (op, mode)
874 || GET_CODE (op) == CONSTANT_P_RTX
875 || (GET_CODE (op) == CONST_DOUBLE
876 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
877 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
878 && ((CONST_DOUBLE_HIGH (op) == -1
879 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
880 || (CONST_DOUBLE_HIGH (op) == 0
881 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
882 || (GET_CODE (op) == CONST_INT
883 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
884 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
887 /* Return truth value of whether OP is a integer which fits the
888 range constraining immediate operands in most three-address insns,
889 which have a 13 bit immediate field. */
894 enum machine_mode mode ATTRIBUTE_UNUSED;
896 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
897 || GET_CODE (op) == CONSTANT_P_RTX);
901 small_int_or_double (op, mode)
903 enum machine_mode mode ATTRIBUTE_UNUSED;
905 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
906 || (GET_CODE (op) == CONST_DOUBLE
907 && CONST_DOUBLE_HIGH (op) == 0
908 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
909 || GET_CODE (op) == CONSTANT_P_RTX);
912 /* Recognize operand values for the umul instruction. That instruction sign
913 extends immediate values just like all other sparc instructions, but
914 interprets the extended result as an unsigned number. */
917 uns_small_int (op, mode)
919 enum machine_mode mode ATTRIBUTE_UNUSED;
921 #if HOST_BITS_PER_WIDE_INT > 32
922 /* All allowed constants will fit a CONST_INT. */
923 return ((GET_CODE (op) == CONST_INT
924 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
925 || (INTVAL (op) >= 0xFFFFF000
926 && INTVAL (op) < 0x100000000)))
927 || GET_CODE (op) == CONSTANT_P_RTX);
929 return (((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
930 || (GET_CODE (op) == CONST_DOUBLE
931 && CONST_DOUBLE_HIGH (op) == 0
932 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000))
933 || GET_CODE (op) == CONSTANT_P_RTX);
938 uns_arith_operand (op, mode)
940 enum machine_mode mode;
942 return register_operand (op, mode) || uns_small_int (op, mode);
945 /* Return truth value of statement that OP is a call-clobbered register. */
947 clobbered_register (op, mode)
949 enum machine_mode mode ATTRIBUTE_UNUSED;
951 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
954 /* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns. */
957 zero_operand (op, mode)
959 enum machine_mode mode ATTRIBUTE_UNUSED;
961 return (op == const0_rtx || GET_CODE (op) == CONSTANT_P_RTX);
964 /* Return 1 if OP is a valid operand for the source of a move insn. */
967 input_operand (op, mode)
969 enum machine_mode mode;
971 /* If both modes are non-void they must be the same. */
972 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
975 /* Allow any one instruction integer constant, and all CONST_INT
976 variants when we are working in DImode and !arch64. */
977 if (GET_MODE_CLASS (mode) == MODE_INT
978 && GET_CODE (op) == CONST_INT
979 && ((SPARC_SETHI_P (INTVAL (op))
981 || (INTVAL (op) >= 0)
983 || SPARC_SIMM13_P (INTVAL (op))
985 && ! TARGET_ARCH64)))
988 /* Always match this. */
989 if (GET_CODE (op) == CONSTANT_P_RTX)
992 /* If !arch64 and this is a DImode const, allow it so that
993 the splits can be generated. */
996 && GET_CODE (op) == CONST_DOUBLE)
999 if (register_operand (op, mode))
1002 /* If this is a SUBREG, look inside so that we handle
1003 paradoxical ones. */
1004 if (GET_CODE (op) == SUBREG)
1005 op = SUBREG_REG (op);
1007 /* Check for valid MEM forms. */
1008 if (GET_CODE (op) == MEM)
1010 rtx inside = XEXP (op, 0);
1012 if (GET_CODE (inside) == LO_SUM)
1013 return (register_operand (XEXP (inside, 0), Pmode)
1014 && CONSTANT_P (XEXP (inside, 1)));
1015 return memory_address_p (mode, inside);
1022 /* We know it can't be done in one insn when we get here,
1023 the movsi expander guarentees this. */
1025 sparc_emit_set_const32 (op0, op1)
1029 enum machine_mode mode = GET_MODE (op0);
1032 if (GET_CODE (op1) == CONST_INT)
1034 int value = INTVAL (op1);
1036 if (SPARC_SETHI_P (value)
1037 || SPARC_SIMM13_P (value))
1041 /* Full 2-insn decomposition is needed. */
1042 if (reload_in_progress || reload_completed)
1045 temp = gen_reg_rtx (mode);
1047 emit_insn (gen_rtx_SET (mode,
1051 emit_insn (gen_rtx_SET (mode,
1053 gen_rtx_LO_SUM (mode,
1059 /* Sparc-v9 code-model support. */
1061 sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1066 switch (sparc_cmodel)
1069 /* The range spanned by all instructions in the object is less
1070 than 2^31 bytes (2GB) and the distance from any instruction
1071 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1072 than 2^31 bytes (2GB).
1074 The executable must be in the low 4TB of the virtual address
1077 sethi %hi(symbol), %temp
1078 or %temp, %lo(symbol), %reg */
1079 emit_insn (gen_rtx_SET (DImode, temp1, gen_rtx_HIGH (DImode, op1)));
1080 emit_insn (gen_rtx_SET (DImode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1084 /* The range spanned by all instructions in the object is less
1085 than 2^31 bytes (2GB) and the distance from any instruction
1086 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1087 than 2^31 bytes (2GB).
1089 The executable must be in the low 16TB of the virtual address
1092 sethi %h44(symbol), %temp1
1093 or %temp1, %m44(symbol), %temp2
1094 sllx %temp2, 12, %temp3
1095 or %temp3, %l44(symbol), %reg */
1096 emit_insn (gen_seth44 (op0, op1));
1097 emit_insn (gen_setm44 (op0, op0, op1));
1098 emit_insn (gen_rtx_SET (DImode, temp1,
1099 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1100 emit_insn (gen_setl44 (op0, temp1, op1));
1104 /* The range spanned by all instructions in the object is less
1105 than 2^31 bytes (2GB) and the distance from any instruction
1106 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1107 than 2^31 bytes (2GB).
1109 The executable can be placed anywhere in the virtual address
1112 sethi %hh(symbol), %temp1
1113 sethi %lm(symbol), %temp2
1114 or %temp1, %hm(symbol), %temp3
1115 or %temp2, %lo(symbol), %temp4
1116 sllx %temp3, 32, %temp5
1117 or %temp4, %temp5, %reg */
1119 /* Getting this right wrt. reloading is really tricky.
1120 We _MUST_ have a seperate temporary at this point,
1121 if we don't barf immediately instead of generating
1126 emit_insn (gen_sethh (op0, op1));
1127 emit_insn (gen_setlm (temp1, op1));
1128 emit_insn (gen_sethm (op0, op0, op1));
1129 emit_insn (gen_rtx_SET (DImode, op0,
1130 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1131 emit_insn (gen_rtx_SET (DImode, op0,
1132 gen_rtx_PLUS (DImode, op0, temp1)));
1133 emit_insn (gen_setlo (op0, op0, op1));
1137 /* Old old old backwards compatibility kruft here.
1138 Essentially it is MEDLOW with a fixed 64-bit
1139 virtual base added to all data segment addresses.
1140 Text-segment stuff is computed like MEDANY, we can't
1141 reuse the code above because the relocation knobs
1144 Data segment: sethi %hi(symbol), %temp1
1145 or %temp1, %lo(symbol), %temp2
1146 add %temp2, EMBMEDANY_BASE_REG, %reg
1148 Text segment: sethi %uhi(symbol), %temp1
1149 sethi %hi(symbol), %temp2
1150 or %temp1, %ulo(symbol), %temp3
1151 or %temp2, %lo(symbol), %temp4
1152 sllx %temp3, 32, %temp5
1153 or %temp4, %temp5, %reg */
1154 if (data_segment_operand (op1, GET_MODE (op1)))
1156 emit_insn (gen_embmedany_sethi (temp1, op1));
1157 emit_insn (gen_embmedany_brsum (op0, temp1));
1158 emit_insn (gen_embmedany_losum (op0, op0, op1));
1162 /* Getting this right wrt. reloading is really tricky.
1163 We _MUST_ have a seperate temporary at this point,
1164 if we don't barf immediately instead of generating
1169 emit_insn (gen_embmedany_textuhi (op0, op1));
1170 emit_insn (gen_embmedany_texthi (temp1, op1));
1171 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1172 emit_insn (gen_rtx_SET (DImode, op0,
1173 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1174 emit_insn (gen_rtx_SET (DImode, op0,
1175 gen_rtx_PLUS (DImode, op0, temp1)));
1176 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1185 /* This avoids problems when cross compiling. */
1190 #if HOST_BITS_PER_WIDE_INT != 64
1191 if (val & 0x80000000)
1192 return immed_double_const (val, 0, DImode);
1195 return GEN_INT (val);
1198 /* Worker routines for 64-bit constant formation on arch64.
1199 One of the key things to be doing in these emissions is
1200 to create as many temp REGs as possible. This makes it
1201 possible for half-built constants to be used later when
1202 such values are similar to something required later on.
1203 Without doing this, the optimizer cannot see such
1206 sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1209 unsigned int low_bits;
1212 unsigned int high_bits;
1215 high_bits = ~low_bits;
1217 high_bits = low_bits;
1219 emit_insn (gen_rtx_SET (DImode, temp,
1220 gen_rtx_HIGH (DImode,
1221 safe_constDI (high_bits))));
1224 emit_insn (gen_rtx_SET (DImode, op0,
1225 gen_rtx_LO_SUM (DImode, temp,
1226 safe_constDI (high_bits))));
1229 { /* as opposed to, say, tricky dick... */
1230 rtx tricky_bits = safe_constDI (-0x400 | (low_bits & 0x3ff));
1231 emit_insn (gen_rtx_SET (DImode, op0,
1232 gen_rtx_XOR (DImode, temp, tricky_bits)));
1237 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1240 unsigned int high_bits;
1241 unsigned int low_immediate;
1246 if ((high_bits & 0xfffffc00) != 0)
1248 emit_insn (gen_rtx_SET (DImode, temp,
1249 gen_rtx_HIGH (DImode,
1250 safe_constDI (high_bits))));
1251 if ((high_bits & ~0xfffffc00) != 0)
1252 emit_insn (gen_rtx_SET (DImode, op0,
1253 gen_rtx_LO_SUM (DImode, temp,
1254 safe_constDI (high_bits))));
1260 emit_insn (gen_rtx_SET (DImode, temp, safe_constDI (high_bits)));
1264 /* Now shift it up into place. */
1265 emit_insn (gen_rtx_SET (DImode, op0,
1266 gen_rtx_ASHIFT (DImode, temp2,
1267 GEN_INT (shift_count))));
1269 /* If there is a low immediate part piece, finish up by
1270 putting that in as well. */
1271 if (low_immediate != 0)
1272 emit_insn (gen_rtx_SET (DImode, op0,
1273 gen_rtx_IOR (DImode, op0,
1274 safe_constDI (low_immediate & 0x3ff))));
1277 /* Full 64-bit constant decomposition. Even though this is the
1278 'worst' case, we still optimize a few things away. */
1280 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1283 unsigned int high_bits;
1284 unsigned int low_bits;
1288 if (reload_in_progress || reload_completed)
1291 sub_temp = gen_reg_rtx (DImode);
1293 if ((high_bits & 0xfffffc00) != 0)
1295 emit_insn (gen_rtx_SET (DImode,
1297 gen_rtx_HIGH (DImode,
1298 safe_constDI (high_bits))));
1299 if ((high_bits & ~0xfffffc00) != 0)
1300 emit_insn (gen_rtx_SET (DImode,
1302 gen_rtx_LO_SUM (DImode, temp,
1303 safe_constDI (high_bits))));
1309 emit_insn (gen_rtx_SET (DImode, temp, safe_constDI (high_bits)));
1313 if (!reload_in_progress && !reload_completed)
1315 rtx temp2 = gen_reg_rtx (DImode);
1316 rtx temp3 = gen_reg_rtx (DImode);
1317 rtx temp4 = gen_reg_rtx (DImode);
1319 emit_insn (gen_rtx_SET (DImode, temp4,
1320 gen_rtx_ASHIFT (DImode, sub_temp,
1323 /* Be careful, we must mask the bits here because otherwise
1324 on a 32-bit host the optimizer will think we're putting
1325 something like "-1" here and optimize it away. */
1326 emit_insn (gen_rtx_SET (DImode, temp2,
1327 gen_rtx_HIGH (DImode,
1328 safe_constDI (low_bits))));
1329 if ((low_bits & ~0xfffffc00) != 0)
1330 emit_insn (gen_rtx_SET (DImode, temp3,
1331 gen_rtx_LO_SUM (DImode, temp2,
1332 safe_constDI (low_bits))));
1333 emit_insn (gen_rtx_SET (DImode, op0,
1334 gen_rtx_PLUS (DImode, temp4, temp3)));
1338 rtx low1 = safe_constDI ((low_bits >> (32 - 12)) & 0xfff);
1339 rtx low2 = safe_constDI ((low_bits >> (32 - 12 - 12)) & 0xfff);
1340 rtx low3 = safe_constDI ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1343 /* We are in the middle of reload, so this is really
1344 painful. However we do still make an attempt to
1345 avoid emmitting truly stupid code. */
1346 if (low1 != const0_rtx)
1348 emit_insn (gen_rtx_SET (DImode, op0,
1349 gen_rtx_ASHIFT (DImode, sub_temp,
1350 GEN_INT(to_shift))));
1351 emit_insn (gen_rtx_SET (DImode, op0,
1352 gen_rtx_IOR (DImode, op0, low1)));
1360 if (low2 != const0_rtx)
1362 emit_insn (gen_rtx_SET (DImode, op0,
1363 gen_rtx_ASHIFT (DImode, sub_temp,
1364 GEN_INT (to_shift))));
1365 emit_insn (gen_rtx_SET (DImode, op0,
1366 gen_rtx_IOR (DImode, op0, low2)));
1374 emit_insn (gen_rtx_SET (DImode, op0,
1375 gen_rtx_ASHIFT (DImode, sub_temp,
1376 GEN_INT (to_shift))));
1377 if (low3 != const0_rtx)
1378 emit_insn (gen_rtx_SET (DImode, op0,
1379 gen_rtx_IOR (DImode, op0, low3)));
1384 /* Analyze a 64-bit constant for certain properties. */
1386 analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
1387 unsigned int high_bits, low_bits;
1388 int *hbsp, *lbsp, *abbasp;
1390 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1393 lowest_bit_set = highest_bit_set = -1;
1397 if ((lowest_bit_set == -1)
1398 && ((low_bits >> i) & 1))
1400 if ((highest_bit_set == -1)
1401 && ((high_bits >> (32 - i - 1)) & 1))
1402 highest_bit_set = (64 - i - 1);
1405 && ((highest_bit_set == -1)
1406 || (lowest_bit_set == -1)));
1412 if ((lowest_bit_set == -1)
1413 && ((high_bits >> i) & 1))
1414 lowest_bit_set = i + 32;
1415 if ((highest_bit_set == -1)
1416 && ((low_bits >> (32 - i - 1)) & 1))
1417 highest_bit_set = 32 - i - 1;
1420 && ((highest_bit_set == -1)
1421 || (lowest_bit_set == -1)));
1423 /* If there are no bits set this should have gone out
1424 as one instruction! */
1425 if (lowest_bit_set == -1
1426 || highest_bit_set == -1)
1428 all_bits_between_are_set = 1;
1429 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1433 if ((low_bits & (1 << i)) != 0)
1438 if ((high_bits & (1 << (i - 32))) != 0)
1441 all_bits_between_are_set = 0;
1444 *hbsp = highest_bit_set;
1445 *lbsp = lowest_bit_set;
1446 *abbasp = all_bits_between_are_set;
1450 const64_is_2insns (high_bits, low_bits)
1451 unsigned int high_bits, low_bits;
1453 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1459 analyze_64bit_constant (high_bits, low_bits,
1460 &highest_bit_set, &lowest_bit_set,
1461 &all_bits_between_are_set);
1463 if (highest_bit_set == 63
1464 && all_bits_between_are_set != 0)
1467 if ((highest_bit_set - lowest_bit_set) < 22)
1474 create_simple_focus_bits (high_bits, low_bits, highest_bit_set, lowest_bit_set, shift)
1475 unsigned int high_bits, low_bits;
1476 int highest_bit_set, lowest_bit_set, shift;
1478 unsigned int hi, lo;
1480 if (lowest_bit_set < 32)
1482 lo = (low_bits >> lowest_bit_set) << shift;
1483 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1488 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1495 /* Here we are sure to be arch64 and this is an integer constant
1496 being loaded into a register. Emit the most efficient
1497 insn sequence possible. Detection of all the 1-insn cases
1498 has been done already. */
1500 sparc_emit_set_const64 (op0, op1)
1504 unsigned int high_bits, low_bits;
1505 int lowest_bit_set, highest_bit_set;
1506 int all_bits_between_are_set;
1510 /* Sanity check that we know what we are working with. */
1512 || GET_CODE (op0) != REG
1513 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1514 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1517 if (GET_CODE (op1) != CONST_DOUBLE
1518 && GET_CODE (op1) != CONST_INT)
1520 if (reload_in_progress || reload_completed)
1523 temp = gen_reg_rtx (DImode);
1524 return sparc_emit_set_symbolic_const64 (op0, op1, temp);
1527 if (GET_CODE (op1) == CONST_DOUBLE)
1529 #if HOST_BITS_PER_WIDE_INT == 64
1530 high_bits = CONST_DOUBLE_LOW (op1) >> 32;
1531 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1533 high_bits = CONST_DOUBLE_HIGH (op1);
1534 low_bits = CONST_DOUBLE_LOW (op1);
1539 #if HOST_BITS_PER_WIDE_INT == 64
1540 high_bits = (INTVAL (op1) >> 32);
1541 low_bits = (INTVAL (op1) & 0xffffffff);
1543 high_bits = ((INTVAL (op1) < 0) ?
1546 low_bits = INTVAL (op1);
1550 /* low_bits bits 0 --> 31
1551 high_bits bits 32 --> 63 */
1553 if (reload_in_progress || reload_completed)
1556 temp = gen_reg_rtx (DImode);
1558 analyze_64bit_constant (high_bits, low_bits,
1559 &highest_bit_set, &lowest_bit_set,
1560 &all_bits_between_are_set);
1562 /* First try for a 2-insn sequence. */
1564 /* These situations are preferred because the optimizer can
1565 * do more things with them:
1567 * sllx %reg, shift, %reg
1569 * srlx %reg, shift, %reg
1570 * 3) mov some_small_const, %reg
1571 * sllx %reg, shift, %reg
1573 if (((highest_bit_set == 63
1574 || lowest_bit_set == 0)
1575 && all_bits_between_are_set != 0)
1576 || ((highest_bit_set - lowest_bit_set) < 13))
1578 rtx the_const = constm1_rtx;
1579 int shift = lowest_bit_set;
1581 if (highest_bit_set == lowest_bit_set)
1583 /* There is no way to get here like this, because this case
1584 can be done in one instruction. */
1585 if (lowest_bit_set < 32)
1587 the_const = const1_rtx;
1589 else if (all_bits_between_are_set == 0)
1592 safe_constDI (create_simple_focus_bits (high_bits, low_bits,
1594 lowest_bit_set, 0));
1596 else if (lowest_bit_set == 0)
1597 shift = -(64 - highest_bit_set);
1598 emit_insn (gen_rtx_SET (DImode, temp, the_const));
1601 emit_insn (gen_rtx_SET (DImode,
1603 gen_rtx_ASHIFT (DImode,
1607 emit_insn (gen_rtx_SET (DImode,
1609 gen_rtx_ASHIFTRT (DImode,
1611 GEN_INT (-shift))));
1617 /* Now a range of 22 or less bits set somewhere.
1618 * 1) sethi %hi(focus_bits), %reg
1619 * sllx %reg, shift, %reg
1620 * 2) sethi %hi(focus_bits), %reg
1621 * srlx %reg, shift, %reg
1623 if ((highest_bit_set - lowest_bit_set) < 22)
1625 unsigned int focus_bits =
1626 create_simple_focus_bits (high_bits, low_bits,
1627 highest_bit_set, lowest_bit_set, 10);
1628 emit_insn (gen_rtx_SET (DImode,
1630 gen_rtx_HIGH (DImode, safe_constDI (focus_bits))));
1632 if (lowest_bit_set < 10)
1633 emit_insn (gen_rtx_SET (DImode,
1635 gen_rtx_ASHIFTRT (DImode, temp,
1636 GEN_INT (10 - lowest_bit_set))));
1637 else if (lowest_bit_set >= 10)
1638 emit_insn (gen_rtx_SET (DImode,
1640 gen_rtx_ASHIFT (DImode, temp,
1641 GEN_INT (lowest_bit_set - 10))));
1647 /* 1) sethi %hi(low_bits), %reg
1648 * or %reg, %lo(low_bits), %reg
1649 * 2) sethi %hi(~low_bits), %reg
1650 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1654 return sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1657 /* 1) sethi %hi(high_bits), %reg
1658 * or %reg, %lo(high_bits), %reg
1659 * sllx %reg, 32, %reg
1662 || (SPARC_SIMM13_P(low_bits)
1663 && ((int)low_bits > 0)))
1664 return sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
1666 /* Now, try 3-insn sequences. But first we may be able to do something
1667 quick when the constant is negated, so try that. */
1668 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1669 (~low_bits) & 0xfffffc00))
1671 unsigned int trailing_bits = (~low_bits) & 0x3ff;
1673 if ((((~high_bits) & 0xffffffff) == 0
1674 && ((~low_bits) & 0x80000000) == 0)
1675 || (((~high_bits) & 0xffffffff) == 0xffffffff
1676 && ((~low_bits) & 0x80000000) != 0))
1678 rtx fast_int = GEN_INT (~low_bits & 0xffffffff);
1680 if (input_operand (fast_int, DImode))
1681 emit_insn (gen_rtx_SET (DImode, temp,
1682 safe_constDI (~low_bits & 0xffffffff)));
1684 sparc_emit_set_const64 (temp, fast_int);
1689 #if HOST_BITS_PER_WIDE_INT == 64
1690 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
1691 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
1693 negated_const = gen_rtx_CONST_DOUBLE (DImode, NULL_RTX,
1694 (~low_bits) & 0xfffffc00,
1695 (~high_bits) & 0xffffffff);
1697 sparc_emit_set_const64 (temp, negated_const);
1699 emit_insn (gen_rtx_SET (DImode,
1701 gen_rtx_XOR (DImode, temp,
1702 safe_constDI (-0x400 | trailing_bits))));
1706 /* 1) sethi %hi(xxx), %reg
1707 * or %reg, %lo(xxx), %reg
1708 * sllx %reg, yyy, %reg
1710 if ((highest_bit_set - lowest_bit_set) < 32)
1712 unsigned int hi, lo, focus_bits;
1714 /* We can't get here in this state. */
1715 if (highest_bit_set < 32
1716 || lowest_bit_set >= 32)
1719 /* So what we know is that the set bits straddle the
1720 middle of the 64-bit word. */
1721 hi = (low_bits >> lowest_bit_set);
1722 lo = (high_bits << (32 - lowest_bit_set));
1725 focus_bits = (hi | lo);
1726 return sparc_emit_set_const64_quick2 (op0, temp,
1731 /* The easiest way when all else fails, is full decomposition. */
1733 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
1734 high_bits, low_bits, ~high_bits, ~low_bits);
1736 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
1739 /* X and Y are two things to compare using CODE. Emit the compare insn and
1740 return the rtx for the cc reg in the proper mode. */
1743 gen_compare_reg (code, x, y)
1747 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1750 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
1751 fcc regs (cse can't tell they're really call clobbered regs and will
1752 remove a duplicate comparison even if there is an intervening function
1753 call - it will then try to reload the cc reg via an int reg which is why
1754 we need the movcc patterns). It is possible to provide the movcc
1755 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
1756 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
1757 to tell cse that CCFPE mode registers (even pseudos) are call
1760 /* ??? This is an experiment. Rather than making changes to cse which may
1761 or may not be easy/clean, we do our own cse. This is possible because
1762 we will generate hard registers. Cse knows they're call clobbered (it
1763 doesn't know the same thing about pseudos). If we guess wrong, no big
1764 deal, but if we win, great! */
1766 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1767 #if 1 /* experiment */
1770 /* We cycle through the registers to ensure they're all exercised. */
1771 static int next_fcc_reg = 0;
1772 /* Previous x,y for each fcc reg. */
1773 static rtx prev_args[4][2];
1775 /* Scan prev_args for x,y. */
1776 for (reg = 0; reg < 4; reg++)
1777 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
1782 prev_args[reg][0] = x;
1783 prev_args[reg][1] = y;
1784 next_fcc_reg = (next_fcc_reg + 1) & 3;
1786 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
1789 cc_reg = gen_reg_rtx (mode);
1790 #endif /* ! experiment */
1791 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1792 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
1794 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
1796 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
1797 gen_rtx_COMPARE (mode, x, y)));
1802 /* This function is used for v9 only.
1803 CODE is the code for an Scc's comparison.
1804 OPERANDS[0] is the target of the Scc insn.
1805 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
1806 been generated yet).
1808 This function is needed to turn
1811 (gt (reg:CCX 100 %icc)
1815 (gt:DI (reg:CCX 100 %icc)
1818 IE: The instruction recognizer needs to see the mode of the comparison to
1819 find the right instruction. We could use "gt:DI" right in the
1820 define_expand, but leaving it out allows us to handle DI, SI, etc.
1822 We refer to the global sparc compare operands sparc_compare_op0 and
1823 sparc_compare_op1. */
1826 gen_v9_scc (compare_code, operands)
1827 enum rtx_code compare_code;
1828 register rtx *operands;
1833 && (GET_MODE (sparc_compare_op0) == DImode
1834 || GET_MODE (operands[0]) == DImode))
1837 /* Handle the case where operands[0] == sparc_compare_op0.
1838 We "early clobber" the result. */
1839 if (REGNO (operands[0]) == REGNO (sparc_compare_op0))
1841 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
1842 emit_move_insn (op0, sparc_compare_op0);
1845 op0 = sparc_compare_op0;
1846 /* For consistency in the following. */
1847 op1 = sparc_compare_op1;
1849 /* Try to use the movrCC insns. */
1851 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
1852 && op1 == const0_rtx
1853 && v9_regcmp_p (compare_code))
1855 /* Special case for op0 != 0. This can be done with one instruction if
1856 operands[0] == sparc_compare_op0. We don't assume they are equal
1859 if (compare_code == NE
1860 && GET_MODE (operands[0]) == DImode
1861 && GET_MODE (op0) == DImode)
1863 emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0));
1864 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
1865 gen_rtx_IF_THEN_ELSE (DImode,
1866 gen_rtx_fmt_ee (compare_code, DImode,
1873 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
1874 if (GET_MODE (op0) != DImode)
1876 temp = gen_reg_rtx (DImode);
1877 convert_move (temp, op0, 0);
1881 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
1882 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
1883 gen_rtx_fmt_ee (compare_code, DImode,
1891 operands[1] = gen_compare_reg (compare_code, op0, op1);
1893 switch (GET_MODE (operands[1]))
1903 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
1904 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
1905 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
1906 gen_rtx_fmt_ee (compare_code,
1907 GET_MODE (operands[1]),
1908 operands[1], const0_rtx),
1909 const1_rtx, operands[0])));
1914 /* Emit a conditional jump insn for the v9 architecture using comparison code
1915 CODE and jump target LABEL.
1916 This function exists to take advantage of the v9 brxx insns. */
1919 emit_v9_brxx_insn (code, op0, label)
1923 emit_jump_insn (gen_rtx_SET (VOIDmode,
1925 gen_rtx_IF_THEN_ELSE (VOIDmode,
1926 gen_rtx_fmt_ee (code, GET_MODE (op0),
1928 gen_rtx_LABEL_REF (VOIDmode, label),
1932 /* Return nonzero if a return peephole merging return with
1933 setting of output register is ok. */
1935 leaf_return_peephole_ok ()
1937 return (actual_fsize == 0);
1940 /* Return nonzero if TRIAL can go into the function epilogue's
1941 delay slot. SLOT is the slot we are trying to fill. */
1944 eligible_for_epilogue_delay (trial, slot)
1953 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
1956 if (get_attr_length (trial) != 1)
1959 /* If %g0 is live, there are lots of things we can't handle.
1960 Rather than trying to find them all now, let's punt and only
1961 optimize things as necessary. */
1965 /* In the case of a true leaf function, anything can go into the delay slot.
1966 A delay slot only exists however if the frame size is zero, otherwise
1967 we will put an insn to adjust the stack after the return. */
1970 if (leaf_return_peephole_ok ())
1971 return ((get_attr_in_uncond_branch_delay (trial)
1972 == IN_BRANCH_DELAY_TRUE));
1976 /* If only trivial `restore' insns work, nothing can go in the
1978 else if (TARGET_BROKEN_SAVERESTORE)
1981 pat = PATTERN (trial);
1983 /* Otherwise, only operations which can be done in tandem with
1984 a `restore' insn can go into the delay slot. */
1985 if (GET_CODE (SET_DEST (pat)) != REG
1986 || REGNO (SET_DEST (pat)) >= 32
1987 || REGNO (SET_DEST (pat)) < 24)
1990 /* The set of insns matched here must agree precisely with the set of
1991 patterns paired with a RETURN in sparc.md. */
1993 src = SET_SRC (pat);
1995 /* This matches "*return_[qhs]i". */
1996 if (arith_operand (src, GET_MODE (src)))
1997 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
1999 /* This matches "*return_di". */
2000 else if (arith_double_operand (src, GET_MODE (src)))
2001 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2003 /* This matches "*return_sf_no_fpu". */
2004 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2005 && register_operand (src, SFmode))
2008 /* This matches "*return_addsi". */
2009 else if (GET_CODE (src) == PLUS
2010 && arith_operand (XEXP (src, 0), SImode)
2011 && arith_operand (XEXP (src, 1), SImode)
2012 && (register_operand (XEXP (src, 0), SImode)
2013 || register_operand (XEXP (src, 1), SImode)))
2016 /* This matches "*return_adddi". */
2017 else if (GET_CODE (src) == PLUS
2018 && arith_double_operand (XEXP (src, 0), DImode)
2019 && arith_double_operand (XEXP (src, 1), DImode)
2020 && (register_operand (XEXP (src, 0), DImode)
2021 || register_operand (XEXP (src, 1), DImode)))
2028 check_return_regs (x)
2031 switch (GET_CODE (x))
2034 return IN_OR_GLOBAL_P (x);
2049 if (check_return_regs (XEXP (x, 1)) == 0)
2054 return check_return_regs (XEXP (x, 0));
2062 /* Return 1 if TRIAL references only in and global registers. */
2064 eligible_for_return_delay (trial)
2067 if (GET_CODE (PATTERN (trial)) != SET)
2070 return check_return_regs (PATTERN (trial));
2074 short_branch (uid1, uid2)
2077 unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2];
2078 if (delta + 1024 < 2048)
2080 /* warning ("long branch, distance %d", delta); */
2084 /* Return non-zero if REG is not used after INSN.
2085 We assume REG is a reload reg, and therefore does
2086 not live past labels or calls or jumps. */
2088 reg_unused_after (reg, insn)
2092 enum rtx_code code, prev_code = UNKNOWN;
2094 while ((insn = NEXT_INSN (insn)))
2096 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2099 code = GET_CODE (insn);
2100 if (GET_CODE (insn) == CODE_LABEL)
2103 if (GET_RTX_CLASS (code) == 'i')
2105 rtx set = single_set (insn);
2106 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2109 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2111 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2119 /* The table we use to reference PIC data. */
2120 static rtx global_offset_table;
2122 /* The function we use to get at it. */
2123 static rtx get_pc_symbol;
2124 static char get_pc_symbol_name[256];
2126 /* Ensure that we are not using patterns that are not OK with PIC. */
2135 if (GET_CODE (recog_operand[i]) == SYMBOL_REF
2136 || (GET_CODE (recog_operand[i]) == CONST
2137 && ! (GET_CODE (XEXP (recog_operand[i], 0)) == MINUS
2138 && (XEXP (XEXP (recog_operand[i], 0), 0)
2139 == global_offset_table)
2140 && (GET_CODE (XEXP (XEXP (recog_operand[i], 0), 1))
2149 /* Return true if X is an address which needs a temporary register when
2150 reloaded while generating PIC code. */
2153 pic_address_needs_scratch (x)
2156 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2157 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2158 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2159 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2160 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2166 /* Legitimize PIC addresses. If the address is already position-independent,
2167 we return ORIG. Newly generated position-independent addresses go into a
2168 reg. This is REG if non zero, otherwise we allocate register(s) as
2172 legitimize_pic_address (orig, mode, reg)
2174 enum machine_mode mode ATTRIBUTE_UNUSED;
2177 if (GET_CODE (orig) == SYMBOL_REF)
2179 rtx pic_ref, address;
2184 if (reload_in_progress || reload_completed)
2187 reg = gen_reg_rtx (Pmode);
2192 /* If not during reload, allocate another temp reg here for loading
2193 in the address, so that these instructions can be optimized
2195 rtx temp_reg = ((reload_in_progress || reload_completed)
2196 ? reg : gen_reg_rtx (Pmode));
2198 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
2199 won't get confused into thinking that these two instructions
2200 are loading in the true address of the symbol. If in the
2201 future a PIC rtx exists, that should be used instead. */
2202 emit_insn (gen_movsi_high_pic (temp_reg, orig));
2203 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
2209 pic_ref = gen_rtx_MEM (Pmode,
2210 gen_rtx_PLUS (Pmode,
2211 pic_offset_table_rtx, address));
2212 current_function_uses_pic_offset_table = 1;
2213 RTX_UNCHANGING_P (pic_ref) = 1;
2214 insn = emit_move_insn (reg, pic_ref);
2215 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2217 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2221 else if (GET_CODE (orig) == CONST)
2225 if (GET_CODE (XEXP (orig, 0)) == PLUS
2226 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2231 if (reload_in_progress || reload_completed)
2234 reg = gen_reg_rtx (Pmode);
2237 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2239 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2240 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2241 base == reg ? 0 : reg);
2246 if (GET_CODE (offset) == CONST_INT)
2248 if (SMALL_INT (offset))
2249 return plus_constant_for_output (base, INTVAL (offset));
2250 else if (! reload_in_progress && ! reload_completed)
2251 offset = force_reg (Pmode, offset);
2253 /* If we reach here, then something is seriously wrong. */
2256 return gen_rtx_PLUS (Pmode, base, offset);
2258 else if (GET_CODE (orig) == LABEL_REF)
2259 /* ??? Why do we do this? */
2260 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
2261 the register is live instead, in case it is eliminated. */
2262 current_function_uses_pic_offset_table = 1;
2267 /* Set up PIC-specific rtl. This should not cause any insns
2275 /* Return the RTX for insns to set the PIC register. */
2283 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
2285 seq = gen_sequence ();
2291 /* Emit special PIC prologues and epilogues. */
2296 /* Labels to get the PC in the prologue of this function. */
2297 int orig_flag_pic = flag_pic;
2300 if (current_function_uses_pic_offset_table == 0)
2306 /* If we havn't emitted the special get_pc helper function, do so now. */
2307 if (get_pc_symbol_name[0] == 0)
2309 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
2312 ASM_OUTPUT_ALIGN (asm_out_file, 3);
2313 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0);
2314 fputs ("\tretl\n\tadd %o7,%l7,%l7\n", asm_out_file);
2317 /* Initialize every time through, since we can't easily
2318 know this to be permanent. */
2319 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2320 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
2323 emit_insn_after (pic_setup_code (), get_insns ());
2325 /* Insert the code in each nonlocal goto receiver. */
2326 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2327 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
2328 && XINT (PATTERN (insn), 1) == 4)
2329 emit_insn_after (pic_setup_code (), insn);
2331 flag_pic = orig_flag_pic;
2333 /* Need to emit this whether or not we obey regdecls,
2334 since setjmp/longjmp can cause life info to screw up.
2335 ??? In the case where we don't obey regdecls, this is not sufficient
2336 since we may not fall out the bottom. */
2337 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2340 /* Return 1 if RTX is a MEM which is known to be aligned to at
2341 least an 8 byte boundary. */
2344 mem_min_alignment (mem, desired)
2348 rtx addr, base, offset;
2350 /* If it's not a MEM we can't accept it. */
2351 if (GET_CODE (mem) != MEM)
2354 addr = XEXP (mem, 0);
2355 base = offset = NULL_RTX;
2356 if (GET_CODE (addr) == PLUS)
2358 if (GET_CODE (XEXP (addr, 0)) == REG)
2360 base = XEXP (addr, 0);
2362 /* What we are saying here is that if the base
2363 REG is aligned properly, the compiler will make
2364 sure any REG based index upon it will be so
2366 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2367 offset = XEXP (addr, 1);
2369 offset = const0_rtx;
2372 else if (GET_CODE (addr) == REG)
2375 offset = const0_rtx;
2378 if (base != NULL_RTX)
2380 int regno = REGNO (base);
2382 if (regno != FRAME_POINTER_REGNUM
2383 && regno != STACK_POINTER_REGNUM)
2385 /* Check if the compiler has recorded some information
2386 about the alignment of the base REG. If reload has
2387 completed, we already matched with proper alignments. */
2388 if (((regno_pointer_align != NULL
2389 && REGNO_POINTER_ALIGN (regno) >= desired)
2390 || reload_completed)
2391 && ((INTVAL (offset) & (desired - 1)) == 0))
2396 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
2400 else if (! TARGET_UNALIGNED_DOUBLES
2401 || CONSTANT_P (addr)
2402 || GET_CODE (addr) == LO_SUM)
2404 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
2405 is true, in which case we can only assume that an access is aligned if
2406 it is to a constant address, or the address involves a LO_SUM. */
2410 /* An obviously unaligned address. */
2415 /* Return a REG that occurs in ADDR with coefficient 1.
2416 ADDR can be effectively incremented by incrementing REG. */
2419 find_addr_reg (addr)
2422 while (GET_CODE (addr) == PLUS)
2424 /* We absolutely can not fudge the frame pointer here, because the
2425 frame pointer must always be 8 byte aligned. It also confuses
2427 if (GET_CODE (XEXP (addr, 0)) == REG
2428 && REGNO (XEXP (addr, 0)) != FRAME_POINTER_REGNUM)
2429 addr = XEXP (addr, 0);
2430 else if (GET_CODE (XEXP (addr, 1)) == REG
2431 && REGNO (XEXP (addr, 1)) != FRAME_POINTER_REGNUM)
2432 addr = XEXP (addr, 1);
2433 else if (CONSTANT_P (XEXP (addr, 0)))
2434 addr = XEXP (addr, 1);
2435 else if (CONSTANT_P (XEXP (addr, 1)))
2436 addr = XEXP (addr, 0);
2440 if (GET_CODE (addr) == REG)
2445 /* Vectors to keep interesting information about registers where it can easily
2446 be got. We use to use the actual mode value as the bit number, but there
2447 are more than 32 modes now. Instead we use two tables: one indexed by
2448 hard register number, and one indexed by mode. */
2450 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2451 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2452 mapped into one sparc_mode_class mode. */
2454 enum sparc_mode_class {
2455 S_MODE, D_MODE, T_MODE, O_MODE,
2456 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
2460 /* Modes for single-word and smaller quantities. */
2461 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2463 /* Modes for double-word and smaller quantities. */
2464 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2466 /* Modes for quad-word and smaller quantities. */
2467 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2469 /* Modes for single-float quantities. We must allow any single word or
2470 smaller quantity. This is because the fix/float conversion instructions
2471 take integer inputs/outputs from the float registers. */
2472 #define SF_MODES (S_MODES)
2474 /* Modes for double-float and smaller quantities. */
2475 #define DF_MODES (S_MODES | D_MODES)
2477 #define DF_MODES64 DF_MODES
2479 /* Modes for double-float only quantities. */
2480 #define DF_ONLY_MODES ((1 << (int) DF_MODE) | (1 << (int) D_MODE))
2482 /* Modes for double-float and larger quantities. */
2483 #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES)
2485 /* Modes for quad-float only quantities. */
2486 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2488 /* Modes for quad-float and smaller quantities. */
2489 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2491 #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES)
2493 /* Modes for condition codes. */
2494 #define CC_MODES (1 << (int) CC_MODE)
2495 #define CCFP_MODES (1 << (int) CCFP_MODE)
2497 /* Value is 1 if register/mode pair is acceptable on sparc.
2498 The funny mixture of D and T modes is because integer operations
2499 do not specially operate on tetra quantities, so non-quad-aligned
2500 registers can hold quadword quantities (except %o4 and %i4 because
2501 they cross fixed registers). */
2503 /* This points to either the 32 bit or the 64 bit version. */
2504 int *hard_regno_mode_classes;
2506 static int hard_32bit_mode_classes[] = {
2507 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2508 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2509 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2510 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2512 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2513 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2514 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2515 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2517 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2518 and none can hold SFmode/SImode values. */
2519 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2520 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2521 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2522 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2525 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2531 static int hard_64bit_mode_classes[] = {
2532 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2533 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2534 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2535 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2537 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2538 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2539 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2540 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2542 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2543 and none can hold SFmode/SImode values. */
2544 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2545 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2546 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2547 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2550 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2556 int sparc_mode_class [NUM_MACHINE_MODES];
2558 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
2565 for (i = 0; i < NUM_MACHINE_MODES; i++)
2567 switch (GET_MODE_CLASS (i))
2570 case MODE_PARTIAL_INT:
2571 case MODE_COMPLEX_INT:
2572 if (GET_MODE_SIZE (i) <= 4)
2573 sparc_mode_class[i] = 1 << (int) S_MODE;
2574 else if (GET_MODE_SIZE (i) == 8)
2575 sparc_mode_class[i] = 1 << (int) D_MODE;
2576 else if (GET_MODE_SIZE (i) == 16)
2577 sparc_mode_class[i] = 1 << (int) T_MODE;
2578 else if (GET_MODE_SIZE (i) == 32)
2579 sparc_mode_class[i] = 1 << (int) O_MODE;
2581 sparc_mode_class[i] = 0;
2584 case MODE_COMPLEX_FLOAT:
2585 if (GET_MODE_SIZE (i) <= 4)
2586 sparc_mode_class[i] = 1 << (int) SF_MODE;
2587 else if (GET_MODE_SIZE (i) == 8)
2588 sparc_mode_class[i] = 1 << (int) DF_MODE;
2589 else if (GET_MODE_SIZE (i) == 16)
2590 sparc_mode_class[i] = 1 << (int) TF_MODE;
2591 else if (GET_MODE_SIZE (i) == 32)
2592 sparc_mode_class[i] = 1 << (int) OF_MODE;
2594 sparc_mode_class[i] = 0;
2598 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
2599 we must explicitly check for them here. */
2600 if (i == (int) CCFPmode || i == (int) CCFPEmode)
2601 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
2602 else if (i == (int) CCmode || i == (int) CC_NOOVmode
2603 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
2604 sparc_mode_class[i] = 1 << (int) CC_MODE;
2606 sparc_mode_class[i] = 0;
2612 hard_regno_mode_classes = hard_64bit_mode_classes;
2614 hard_regno_mode_classes = hard_32bit_mode_classes;
2616 /* Initialize the array used by REGNO_REG_CLASS. */
2617 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2619 if (i < 16 && TARGET_V8PLUS)
2620 sparc_regno_reg_class[i] = I64_REGS;
2622 sparc_regno_reg_class[i] = GENERAL_REGS;
2624 sparc_regno_reg_class[i] = FP_REGS;
2626 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
2628 sparc_regno_reg_class[i] = FPCC_REGS;
2630 sparc_regno_reg_class[i] = NO_REGS;
2634 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
2635 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2636 v9 int regs as it simplifies the code. */
2639 save_regs (file, low, high, base, offset, n_regs, real_offset)
2649 if (TARGET_ARCH64 && high <= 32)
2651 for (i = low; i < high; i++)
2653 if (regs_ever_live[i] && ! call_used_regs[i])
2655 fprintf (file, "\tstx\t%s, [%s+%d]\n",
2656 reg_names[i], base, offset + 4 * n_regs);
2657 if (dwarf2out_do_frame ())
2658 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
2665 for (i = low; i < high; i += 2)
2667 if (regs_ever_live[i] && ! call_used_regs[i])
2669 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2671 fprintf (file, "\tstd\t%s, [%s+%d]\n",
2672 reg_names[i], base, offset + 4 * n_regs);
2673 if (dwarf2out_do_frame ())
2675 char *l = dwarf2out_cfi_label ();
2676 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
2677 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
2683 fprintf (file, "\tst\t%s, [%s+%d]\n",
2684 reg_names[i], base, offset + 4 * n_regs);
2685 if (dwarf2out_do_frame ())
2686 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
2692 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2694 fprintf (file, "\tst\t%s, [%s+%d]\n",
2695 reg_names[i+1], base, offset + 4 * n_regs + 4);
2696 if (dwarf2out_do_frame ())
2697 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
2706 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
2708 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2709 v9 int regs as it simplifies the code. */
2712 restore_regs (file, low, high, base, offset, n_regs)
2721 if (TARGET_ARCH64 && high <= 32)
2723 for (i = low; i < high; i++)
2725 if (regs_ever_live[i] && ! call_used_regs[i])
2726 fprintf (file, "\tldx\t[%s+%d], %s\n",
2727 base, offset + 4 * n_regs, reg_names[i]),
2733 for (i = low; i < high; i += 2)
2735 if (regs_ever_live[i] && ! call_used_regs[i])
2736 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2737 fprintf (file, "\tldd\t[%s+%d], %s\n",
2738 base, offset + 4 * n_regs, reg_names[i]),
2741 fprintf (file, "\tld\t[%s+%d],%s\n",
2742 base, offset + 4 * n_regs, reg_names[i]),
2744 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2745 fprintf (file, "\tld\t[%s+%d],%s\n",
2746 base, offset + 4 * n_regs + 4, reg_names[i+1]),
2753 /* Static variables we want to share between prologue and epilogue. */
2755 /* Number of live general or floating point registers needed to be saved
2756 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
2757 static int num_gfregs;
2759 /* Compute the frame size required by the function. This function is called
2760 during the reload pass and also by output_function_prologue(). */
2763 compute_frame_size (size, leaf_function)
2768 int outgoing_args_size = (current_function_outgoing_args_size
2769 + REG_PARM_STACK_SPACE (current_function_decl));
2771 if (TARGET_EPILOGUE)
2773 /* N_REGS is the number of 4-byte regs saved thus far. This applies
2774 even to v9 int regs to be consistent with save_regs/restore_regs. */
2778 for (i = 0; i < 8; i++)
2779 if (regs_ever_live[i] && ! call_used_regs[i])
2784 for (i = 0; i < 8; i += 2)
2785 if ((regs_ever_live[i] && ! call_used_regs[i])
2786 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
2790 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
2791 if ((regs_ever_live[i] && ! call_used_regs[i])
2792 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
2796 /* Set up values for use in `function_epilogue'. */
2797 num_gfregs = n_regs;
2799 if (leaf_function && n_regs == 0
2800 && size == 0 && current_function_outgoing_args_size == 0)
2802 actual_fsize = apparent_fsize = 0;
2806 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
2807 The stack bias (if any) is taken out to undo its effects. */
2808 apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8;
2809 apparent_fsize += n_regs * 4;
2810 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
2813 /* Make sure nothing can clobber our register windows.
2814 If a SAVE must be done, or there is a stack-local variable,
2815 the register window area must be allocated.
2816 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
2817 if (leaf_function == 0 || size > 0)
2818 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
2820 return SPARC_STACK_ALIGN (actual_fsize);
2823 /* Build a (32 bit) big number in a register. */
2824 /* ??? We may be able to use the set macro here too. */
2827 build_big_number (file, num, reg)
2832 if (num >= 0 || ! TARGET_ARCH64)
2834 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
2835 if ((num & 0x3ff) != 0)
2836 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
2838 else /* num < 0 && TARGET_ARCH64 */
2840 /* Sethi does not sign extend, so we must use a little trickery
2841 to use it for negative numbers. Invert the constant before
2842 loading it in, then use xor immediate to invert the loaded bits
2843 (along with the upper 32 bits) to the desired constant. This
2844 works because the sethi and immediate fields overlap. */
2847 int low = -0x400 + (asize & 0x3FF);
2849 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
2850 inv, reg, reg, low, reg);
2854 /* Output code for the function prologue. */
2857 output_function_prologue (file, size, leaf_function)
2862 /* Need to use actual_fsize, since we are also allocating
2863 space for our callee (and our own register save area). */
2864 actual_fsize = compute_frame_size (size, leaf_function);
2868 frame_base_name = "%sp";
2869 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
2873 frame_base_name = "%fp";
2874 frame_base_offset = SPARC_STACK_BIAS;
2877 /* This is only for the human reader. */
2878 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
2880 if (actual_fsize == 0)
2882 else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE)
2884 if (actual_fsize <= 4096)
2885 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
2886 else if (actual_fsize <= 8192)
2888 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
2889 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
2893 build_big_number (file, -actual_fsize, "%g1");
2894 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
2897 else if (! leaf_function && TARGET_BROKEN_SAVERESTORE)
2899 /* We assume the environment will properly handle or otherwise avoid
2900 trouble associated with an interrupt occurring after the `save' or
2901 trap occurring during it. */
2902 fprintf (file, "\tsave\n");
2904 if (actual_fsize <= 4096)
2905 fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize);
2906 else if (actual_fsize <= 8192)
2908 fprintf (file, "\tadd\t%%fp, -4096, %%sp\n");
2909 fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize - 4096);
2913 build_big_number (file, -actual_fsize, "%g1");
2914 fprintf (file, "\tadd\t%%fp, %%g1, %%sp\n");
2917 else /* leaf function */
2919 if (actual_fsize <= 4096)
2920 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
2921 else if (actual_fsize <= 8192)
2923 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
2924 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
2928 build_big_number (file, -actual_fsize, "%g1");
2929 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
2933 if (dwarf2out_do_frame () && actual_fsize)
2935 char *label = dwarf2out_cfi_label ();
2937 /* The canonical frame address refers to the top of the frame. */
2938 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
2939 : FRAME_POINTER_REGNUM),
2942 if (! leaf_function)
2944 /* Note the register window save. This tells the unwinder that
2945 it needs to restore the window registers from the previous
2946 frame's window save area at 0(cfa). */
2947 dwarf2out_window_save (label);
2949 /* The return address (-8) is now in %i7. */
2950 dwarf2out_return_reg (label, 31);
2954 /* If doing anything with PIC, do it now. */
2956 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
2958 /* Call saved registers are saved just above the outgoing argument area. */
2961 int offset, real_offset, n_regs;
2964 real_offset = -apparent_fsize;
2965 offset = -apparent_fsize + frame_base_offset;
2966 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
2968 /* ??? This might be optimized a little as %g1 might already have a
2969 value close enough that a single add insn will do. */
2970 /* ??? Although, all of this is probably only a temporary fix
2971 because if %g1 can hold a function result, then
2972 output_function_epilogue will lose (the result will get
2974 build_big_number (file, offset, "%g1");
2975 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
2981 base = frame_base_name;
2985 if (TARGET_EPILOGUE && ! leaf_function)
2986 /* ??? Originally saved regs 0-15 here. */
2987 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
2988 else if (leaf_function)
2989 /* ??? Originally saved regs 0-31 here. */
2990 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
2991 if (TARGET_EPILOGUE)
2992 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
2997 if (leaf_function && actual_fsize != 0)
2999 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3000 if (! TARGET_EPILOGUE)
3001 leaf_label = gen_label_rtx ();
3005 /* Output code for the function epilogue. */
3008 output_function_epilogue (file, size, leaf_function)
3010 int size ATTRIBUTE_UNUSED;
3017 emit_label_after (leaf_label, get_last_insn ());
3018 final_scan_insn (get_last_insn (), file, 0, 0, 1);
3021 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3022 else if (profile_block_flag == 2)
3024 FUNCTION_BLOCK_PROFILER_EXIT(file);
3028 else if (current_function_epilogue_delay_list == 0)
3030 /* If code does not drop into the epilogue, we need
3031 do nothing except output pending case vectors. */
3032 rtx insn = get_last_insn ();
3033 if (GET_CODE (insn) == NOTE)
3034 insn = prev_nonnote_insn (insn);
3035 if (insn && GET_CODE (insn) == BARRIER)
3036 goto output_vectors;
3039 /* Restore any call saved registers. */
3045 offset = -apparent_fsize + frame_base_offset;
3046 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3048 build_big_number (file, offset, "%g1");
3049 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3055 base = frame_base_name;
3059 if (TARGET_EPILOGUE && ! leaf_function)
3060 /* ??? Originally saved regs 0-15 here. */
3061 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3062 else if (leaf_function)
3063 /* ??? Originally saved regs 0-31 here. */
3064 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3065 if (TARGET_EPILOGUE)
3066 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
3069 /* Work out how to skip the caller's unimp instruction if required. */
3071 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
3073 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
3075 if (TARGET_EPILOGUE || leaf_label)
3077 int old_target_epilogue = TARGET_EPILOGUE;
3078 target_flags &= ~old_target_epilogue;
3080 if (! leaf_function)
3082 /* If we wound up with things in our delay slot, flush them here. */
3083 if (current_function_epilogue_delay_list)
3085 rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode),
3087 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode,
3089 PATTERN (XEXP (current_function_epilogue_delay_list, 0)),
3091 final_scan_insn (insn, file, 1, 0, 1);
3093 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
3094 fputs ("\treturn\t%i7+8\n\tnop\n", file);
3096 fprintf (file, "\t%s\n\trestore\n", ret);
3098 /* All of the following cases are for leaf functions. */
3099 else if (current_function_epilogue_delay_list)
3101 /* eligible_for_epilogue_delay_slot ensures that if this is a
3102 leaf function, then we will only have insn in the delay slot
3103 if the frame size is zero, thus no adjust for the stack is
3105 if (actual_fsize != 0)
3107 fprintf (file, "\t%s\n", ret);
3108 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
3111 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3112 avoid generating confusing assembly language output. */
3113 else if (actual_fsize == 0)
3114 fprintf (file, "\t%s\n\tnop\n", ret);
3115 else if (actual_fsize <= 4096)
3116 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
3117 else if (actual_fsize <= 8192)
3118 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
3119 ret, actual_fsize - 4096);
3120 else if ((actual_fsize & 0x3ff) == 0)
3121 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3124 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3125 actual_fsize, actual_fsize, ret);
3126 target_flags |= old_target_epilogue;
3130 sparc_output_deferred_case_vectors ();
3133 /* Functions for handling argument passing.
3135 For v8 the first six args are normally in registers and the rest are
3136 pushed. Any arg that starts within the first 6 words is at least
3137 partially passed in a register unless its data type forbids.
3139 For v9, the argument registers are laid out as an array of 16 elements
3140 and arguments are added sequentially. The first 6 int args and up to the
3141 first 16 fp args (depending on size) are passed in regs.
3143 Slot Stack Integral Float Float in structure Double Long Double
3144 ---- ----- -------- ----- ------------------ ------ -----------
3145 15 [SP+248] %f31 %f30,%f31 %d30
3146 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3147 13 [SP+232] %f27 %f26,%f27 %d26
3148 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3149 11 [SP+216] %f23 %f22,%f23 %d22
3150 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3151 9 [SP+200] %f19 %f18,%f19 %d18
3152 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3153 7 [SP+184] %f15 %f14,%f15 %d14
3154 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3155 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3156 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3157 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3158 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3159 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3160 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3162 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3164 Integral arguments are always passed as 64 bit quantities appropriately
3167 Passing of floating point values is handled as follows.
3168 If a prototype is in scope:
3169 If the value is in a named argument (i.e. not a stdarg function or a
3170 value not part of the `...') then the value is passed in the appropriate
3172 If the value is part of the `...' and is passed in one of the first 6
3173 slots then the value is passed in the appropriate int reg.
3174 If the value is part of the `...' and is not passed in one of the first 6
3175 slots then the value is passed in memory.
3176 If a prototype is not in scope:
3177 If the value is one of the first 6 arguments the value is passed in the
3178 appropriate integer reg and the appropriate fp reg.
3179 If the value is not one of the first 6 arguments the value is passed in
3180 the appropriate fp reg and in memory.
3183 /* Maximum number of int regs for args. */
3184 #define SPARC_INT_ARG_MAX 6
3185 /* Maximum number of fp regs for args. */
3186 #define SPARC_FP_ARG_MAX 16
3188 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3190 /* Handle the INIT_CUMULATIVE_ARGS macro.
3191 Initialize a variable CUM of type CUMULATIVE_ARGS
3192 for a call to a function whose data type is FNTYPE.
3193 For a library call, FNTYPE is 0. */
3196 init_cumulative_args (cum, fntype, libname, indirect)
3197 CUMULATIVE_ARGS *cum;
3199 tree libname ATTRIBUTE_UNUSED;
3200 int indirect ATTRIBUTE_UNUSED;
3203 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
3204 cum->libcall_p = fntype == 0;
3207 /* Compute the slot number to pass an argument in.
3208 Returns the slot number or -1 if passing on the stack.
3210 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3211 the preceding args and about the function being called.
3212 MODE is the argument's machine mode.
3213 TYPE is the data type of the argument (as a tree).
3214 This is null for libcalls where that information may
3216 NAMED is nonzero if this argument is a named parameter
3217 (otherwise it is an extra parameter matching an ellipsis).
3218 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3219 *PREGNO records the register number to use if scalar type.
3220 *PPADDING records the amount of padding needed in words. */
3223 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
3224 const CUMULATIVE_ARGS *cum;
3225 enum machine_mode mode;
3232 int regbase = (incoming_p
3233 ? SPARC_INCOMING_INT_ARG_FIRST
3234 : SPARC_OUTGOING_INT_ARG_FIRST);
3235 int slotno = cum->words;
3240 if (type != 0 && TREE_ADDRESSABLE (type))
3243 && type != 0 && mode == BLKmode
3244 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
3250 /* MODE is VOIDmode when generating the actual call.
3254 case QImode : case CQImode :
3255 case HImode : case CHImode :
3256 case SImode : case CSImode :
3257 case DImode : case CDImode :
3258 if (slotno >= SPARC_INT_ARG_MAX)
3260 regno = regbase + slotno;
3263 case SFmode : case SCmode :
3264 case DFmode : case DCmode :
3265 case TFmode : case TCmode :
3268 if (slotno >= SPARC_INT_ARG_MAX)
3270 regno = regbase + slotno;
3274 if ((mode == TFmode || mode == TCmode)
3275 && (slotno & 1) != 0)
3276 slotno++, *ppadding = 1;
3277 if (TARGET_FPU && named)
3279 if (slotno >= SPARC_FP_ARG_MAX)
3281 regno = SPARC_FP_ARG_FIRST + slotno * 2;
3287 if (slotno >= SPARC_INT_ARG_MAX)
3289 regno = regbase + slotno;
3295 /* For sparc64, objects requiring 16 byte alignment get it. */
3298 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
3299 slotno++, *ppadding = 1;
3303 || (type && TREE_CODE (type) == UNION_TYPE))
3305 if (slotno >= SPARC_INT_ARG_MAX)
3307 regno = regbase + slotno;
3312 int intregs_p = 0, fpregs_p = 0;
3313 /* The ABI obviously doesn't specify how packed
3314 structures are passed. These are defined to be passed
3315 in int regs if possible, otherwise memory. */
3318 /* First see what kinds of registers we need. */
3319 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3321 if (TREE_CODE (field) == FIELD_DECL)
3323 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3328 if (DECL_PACKED (field))
3332 if (packed_p || !named)
3333 fpregs_p = 0, intregs_p = 1;
3335 /* If all arg slots are filled, then must pass on stack. */
3336 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
3338 /* If there are only int args and all int arg slots are filled,
3339 then must pass on stack. */
3340 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
3342 /* Note that even if all int arg slots are filled, fp members may
3343 still be passed in regs if such regs are available.
3344 *PREGNO isn't set because there may be more than one, it's up
3345 to the caller to compute them. */
3358 /* Handle recursive register counting for structure field layout. */
3360 struct function_arg_record_value_parms
3363 int slotno, named, regbase;
3364 int nregs, intoffset;
3368 function_arg_record_value_1 (type, startbitpos, parms)
3371 struct function_arg_record_value_parms *parms;
3375 /* The ABI obviously doesn't specify how packed structures are
3376 passed. These are defined to be passed in int regs if possible,
3377 otherwise memory. */
3380 /* We need to compute how many registers are needed so we can
3381 allocate the PARALLEL but before we can do that we need to know
3382 whether there are any packed fields. If there are, int regs are
3383 used regardless of whether there are fp values present. */
3384 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3386 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
3393 /* Compute how many registers we need. */
3394 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3396 if (TREE_CODE (field) == FIELD_DECL)
3398 int bitpos = startbitpos;
3399 if (DECL_FIELD_BITPOS (field))
3400 bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3401 /* ??? FIXME: else assume zero offset. */
3403 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
3405 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
3407 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3412 if (parms->intoffset != -1)
3414 int intslots, this_slotno;
3416 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
3418 this_slotno = parms->slotno + parms->intoffset
3421 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3422 intslots = MAX (intslots, 0);
3423 parms->nregs += intslots;
3424 parms->intoffset = -1;
3427 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
3428 If it wasn't true we wouldn't be here. */
3433 if (parms->intoffset == -1)
3434 parms->intoffset = bitpos;
3440 /* Handle recursive structure field register assignment. */
3443 function_arg_record_value_3 (bitpos, parms)
3445 struct function_arg_record_value_parms *parms;
3447 enum machine_mode mode;
3448 int regno, this_slotno, intslots, intoffset;
3451 if (parms->intoffset == -1)
3453 intoffset = parms->intoffset;
3454 parms->intoffset = -1;
3456 intslots = (bitpos - intoffset + BITS_PER_WORD - 1) / BITS_PER_WORD;
3457 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
3459 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3463 /* If this is the trailing part of a word, only load that much into
3464 the register. Otherwise load the whole register. Note that in
3465 the latter case we may pick up unwanted bits. It's not a problem
3466 at the moment but may wish to revisit. */
3468 if (intoffset % BITS_PER_WORD != 0)
3470 mode = mode_for_size (BITS_PER_WORD - intoffset%BITS_PER_WORD,
3476 intoffset /= BITS_PER_UNIT;
3479 regno = parms->regbase + this_slotno;
3480 reg = gen_rtx_REG (mode, regno);
3481 XVECEXP (parms->ret, 0, parms->nregs)
3482 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
3485 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
3489 while (intslots > 0);
3493 function_arg_record_value_2 (type, startbitpos, parms)
3496 struct function_arg_record_value_parms *parms;
3501 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3503 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
3510 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3512 if (TREE_CODE (field) == FIELD_DECL)
3514 int bitpos = startbitpos;
3515 if (DECL_FIELD_BITPOS (field))
3516 bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3517 /* ??? FIXME: else assume zero offset. */
3519 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
3521 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
3523 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3528 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
3531 function_arg_record_value_3 (bitpos, parms);
3533 reg = gen_rtx_REG (DECL_MODE (field),
3534 (SPARC_FP_ARG_FIRST + this_slotno * 2
3535 + (DECL_MODE (field) == SFmode
3536 && (bitpos & 32) != 0)));
3537 XVECEXP (parms->ret, 0, parms->nregs)
3538 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3539 GEN_INT (bitpos / BITS_PER_UNIT));
3544 if (parms->intoffset == -1)
3545 parms->intoffset = bitpos;
3552 function_arg_record_value (type, mode, slotno, named, regbase)
3554 enum machine_mode mode;
3555 int slotno, named, regbase;
3557 HOST_WIDE_INT typesize = int_size_in_bytes (type);
3558 struct function_arg_record_value_parms parms;
3561 parms.ret = NULL_RTX;
3562 parms.slotno = slotno;
3563 parms.named = named;
3564 parms.regbase = regbase;
3566 /* Compute how many registers we need. */
3568 parms.intoffset = 0;
3569 function_arg_record_value_1 (type, 0, &parms);
3571 if (parms.intoffset != -1)
3573 int intslots, this_slotno;
3575 intslots = (typesize*BITS_PER_UNIT - parms.intoffset + BITS_PER_WORD - 1)
3577 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
3579 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3580 intslots = MAX (intslots, 0);
3582 parms.nregs += intslots;
3584 nregs = parms.nregs;
3586 /* Allocate the vector and handle some annoying special cases. */
3589 /* ??? Empty structure has no value? Duh? */
3592 /* Though there's nothing really to store, return a word register
3593 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
3594 leads to breakage due to the fact that there are zero bytes to
3596 return gen_rtx_REG (mode, regbase);
3600 /* ??? C++ has structures with no fields, and yet a size. Give up
3601 for now and pass everything back in integer registers. */
3602 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3604 if (nregs + slotno > SPARC_INT_ARG_MAX)
3605 nregs = SPARC_INT_ARG_MAX - slotno;
3610 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
3612 /* Fill in the entries. */
3614 parms.intoffset = 0;
3615 function_arg_record_value_2 (type, 0, &parms);
3616 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
3618 if (parms.nregs != nregs)
3624 /* Handle the FUNCTION_ARG macro.
3625 Determine where to put an argument to a function.
3626 Value is zero to push the argument on the stack,
3627 or a hard register in which to store the argument.
3629 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3630 the preceding args and about the function being called.
3631 MODE is the argument's machine mode.
3632 TYPE is the data type of the argument (as a tree).
3633 This is null for libcalls where that information may
3635 NAMED is nonzero if this argument is a named parameter
3636 (otherwise it is an extra parameter matching an ellipsis).
3637 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
3640 function_arg (cum, mode, type, named, incoming_p)
3641 const CUMULATIVE_ARGS *cum;
3642 enum machine_mode mode;
3647 int regbase = (incoming_p
3648 ? SPARC_INCOMING_INT_ARG_FIRST
3649 : SPARC_OUTGOING_INT_ARG_FIRST);
3650 int slotno, regno, padding;
3653 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
3661 reg = gen_rtx_REG (mode, regno);
3665 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
3666 but also have the slot allocated for them.
3667 If no prototype is in scope fp values in register slots get passed
3668 in two places, either fp regs and int regs or fp regs and memory. */
3669 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
3670 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3671 && SPARC_FP_REG_P (regno))
3673 reg = gen_rtx_REG (mode, regno);
3674 if (cum->prototype_p || cum->libcall_p)
3676 /* "* 2" because fp reg numbers are recorded in 4 byte
3679 /* ??? This will cause the value to be passed in the fp reg and
3680 in the stack. When a prototype exists we want to pass the
3681 value in the reg but reserve space on the stack. That's an
3682 optimization, and is deferred [for a bit]. */
3683 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
3684 return gen_rtx_PARALLEL (mode,
3686 gen_rtx_EXPR_LIST (VOIDmode,
3687 NULL_RTX, const0_rtx),
3688 gen_rtx_EXPR_LIST (VOIDmode,
3692 /* ??? It seems that passing back a register even when past
3693 the area declared by REG_PARM_STACK_SPACE will allocate
3694 space appropriately, and will not copy the data onto the
3695 stack, exactly as we desire.
3697 This is due to locate_and_pad_parm being called in
3698 expand_call whenever reg_parm_stack_space > 0, which
3699 while benefical to our example here, would seem to be
3700 in error from what had been intended. Ho hum... -- r~ */
3708 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
3712 /* On incoming, we don't need to know that the value
3713 is passed in %f0 and %i0, and it confuses other parts
3714 causing needless spillage even on the simplest cases. */
3718 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
3719 + (regno - SPARC_FP_ARG_FIRST) / 2);
3721 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
3722 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
3724 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
3728 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
3729 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
3730 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
3734 else if (type && TREE_CODE (type) == RECORD_TYPE)
3736 /* Structures up to 16 bytes in size are passed in arg slots on the
3737 stack and are promoted to registers where possible. */
3739 if (int_size_in_bytes (type) > 16)
3740 abort (); /* shouldn't get here */
3742 return function_arg_record_value (type, mode, slotno, named, regbase);
3744 else if (type && TREE_CODE (type) == UNION_TYPE)
3746 enum machine_mode mode;
3747 int bytes = int_size_in_bytes (type);
3752 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
3753 reg = gen_rtx_REG (mode, regno);
3757 /* Scalar or complex int. */
3758 reg = gen_rtx_REG (mode, regno);
3764 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
3765 For an arg passed partly in registers and partly in memory,
3766 this is the number of registers used.
3767 For args passed entirely in registers or entirely in memory, zero.
3769 Any arg that starts in the first 6 regs but won't entirely fit in them
3770 needs partial registers on v8. On v9, structures with integer
3771 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
3772 values that begin in the last fp reg [where "last fp reg" varies with the
3773 mode] will be split between that reg and memory. */
3776 function_arg_partial_nregs (cum, mode, type, named)
3777 const CUMULATIVE_ARGS *cum;
3778 enum machine_mode mode;
3782 int slotno, regno, padding;
3784 /* We pass 0 for incoming_p here, it doesn't matter. */
3785 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
3792 if ((slotno + (mode == BLKmode
3793 ? ROUND_ADVANCE (int_size_in_bytes (type))
3794 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
3795 > NPARM_REGS (SImode))
3796 return NPARM_REGS (SImode) - slotno;
3801 if (type && AGGREGATE_TYPE_P (type))
3803 int size = int_size_in_bytes (type);
3804 int align = TYPE_ALIGN (type);
3807 slotno += slotno & 1;
3808 if (size > 8 && size <= 16
3809 && slotno == SPARC_INT_ARG_MAX - 1)
3812 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
3813 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3816 if (GET_MODE_ALIGNMENT (mode) == 128)
3818 slotno += slotno & 1;
3819 if (slotno == SPARC_INT_ARG_MAX - 2)
3824 if (slotno == SPARC_INT_ARG_MAX - 1)
3828 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3830 if (GET_MODE_ALIGNMENT (mode) == 128)
3831 slotno += slotno & 1;
3832 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
3840 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
3841 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
3842 quad-precision floats by invisible reference.
3843 v9: Aggregates greater than 16 bytes are passed by reference.
3844 For Pascal, also pass arrays by reference. */
3847 function_arg_pass_by_reference (cum, mode, type, named)
3848 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3849 enum machine_mode mode;
3851 int named ATTRIBUTE_UNUSED;
3855 return ((type && AGGREGATE_TYPE_P (type))
3856 || mode == TFmode || mode == TCmode);
3860 return ((type && TREE_CODE (type) == ARRAY_TYPE)
3861 /* Consider complex values as aggregates, so care for TCmode. */
3862 || GET_MODE_SIZE (mode) > 16
3863 || (type && AGGREGATE_TYPE_P (type)
3864 && int_size_in_bytes (type) > 16));
3868 /* Handle the FUNCTION_ARG_ADVANCE macro.
3869 Update the data in CUM to advance over an argument
3870 of mode MODE and data type TYPE.
3871 TYPE is null for libcalls where that information may not be available. */
3874 function_arg_advance (cum, mode, type, named)
3875 CUMULATIVE_ARGS *cum;
3876 enum machine_mode mode;
3880 int slotno, regno, padding;
3882 /* We pass 0 for incoming_p here, it doesn't matter. */
3883 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
3885 /* If register required leading padding, add it. */
3887 cum->words += padding;
3891 cum->words += (mode != BLKmode
3892 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
3893 : ROUND_ADVANCE (int_size_in_bytes (type)));
3897 if (type && AGGREGATE_TYPE_P (type))
3899 int size = int_size_in_bytes (type);
3903 else if (size <= 16)
3905 else /* passed by reference */
3908 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
3912 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3914 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
3918 cum->words += (mode != BLKmode
3919 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
3920 : ROUND_ADVANCE (int_size_in_bytes (type)));
3925 /* Handle the FUNCTION_ARG_PADDING macro.
3926 For the 64 bit ABI structs are always stored left shifted in their
3930 function_arg_padding (mode, type)
3931 enum machine_mode mode;
3934 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
3937 /* This is the default definition. */
3938 return (! BYTES_BIG_ENDIAN
3941 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
3942 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
3943 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
3944 ? downward : upward));
3947 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
3948 For v9, function return values are subject to the same rules as arguments,
3949 except that up to 32-bytes may be returned in registers. */
3952 function_value (type, mode, incoming_p)
3954 enum machine_mode mode;
3958 int regbase = (incoming_p
3959 ? SPARC_OUTGOING_INT_ARG_FIRST
3960 : SPARC_INCOMING_INT_ARG_FIRST);
3962 if (TARGET_ARCH64 && type)
3964 if (TREE_CODE (type) == RECORD_TYPE)
3966 /* Structures up to 32 bytes in size are passed in registers,
3967 promoted to fp registers where possible. */
3969 if (int_size_in_bytes (type) > 32)
3970 abort (); /* shouldn't get here */
3972 return function_arg_record_value (type, mode, 0, 1, regbase);
3974 else if (TREE_CODE (type) == UNION_TYPE)
3976 int bytes = int_size_in_bytes (type);
3981 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
3986 regno = BASE_RETURN_VALUE_REG (mode);
3988 regno = BASE_OUTGOING_VALUE_REG (mode);
3990 return gen_rtx_REG (mode, regno);
3993 /* Do what is necessary for `va_start'. The argument is ignored.
3995 We look at the current function to determine if stdarg or varargs
3996 is used and return the address of the first unnamed parameter. */
3999 sparc_builtin_saveregs (arglist)
4000 tree arglist ATTRIBUTE_UNUSED;
4002 int first_reg = current_function_args_info.words;
4006 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
4007 emit_move_insn (gen_rtx_MEM (word_mode,
4008 gen_rtx_PLUS (Pmode,
4010 GEN_INT (STACK_POINTER_OFFSET
4011 + UNITS_PER_WORD * regno))),
4012 gen_rtx_REG (word_mode,
4013 BASE_INCOMING_ARG_REG (word_mode) + regno));
4015 address = gen_rtx_PLUS (Pmode,
4017 GEN_INT (STACK_POINTER_OFFSET
4018 + UNITS_PER_WORD * first_reg));
4020 if (flag_check_memory_usage
4021 && first_reg < NPARM_REGS (word_mode))
4022 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4024 GEN_INT (UNITS_PER_WORD
4025 * (NPARM_REGS (word_mode) - first_reg)),
4026 TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW),
4027 TYPE_MODE (integer_type_node));
4032 /* Return the string to output a conditional branch to LABEL, which is
4033 the operand number of the label. OP is the conditional expression.
4034 XEXP (OP, 0) is assumed to be a condition code register (integer or
4035 floating point) and its mode specifies what kind of comparison we made.
4037 REVERSED is non-zero if we should reverse the sense of the comparison.
4039 ANNUL is non-zero if we should generate an annulling branch.
4041 NOOP is non-zero if we have to follow this branch by a noop.
4043 INSN, if set, is the insn. */
4046 output_cbranch (op, label, reversed, annul, noop, insn)
4049 int reversed, annul, noop;
4052 static char string[32];
4053 enum rtx_code code = GET_CODE (op);
4054 rtx cc_reg = XEXP (op, 0);
4055 enum machine_mode mode = GET_MODE (cc_reg);
4056 static char v8_labelno[] = "%lX";
4057 static char v9_icc_labelno[] = "%%icc, %lX";
4058 static char v9_xcc_labelno[] = "%%xcc, %lX";
4059 static char v9_fcc_labelno[] = "%%fccX, %lY";
4061 int labeloff, spaces = 8;
4063 /* ??? !v9: FP branches cannot be preceded by another floating point insn.
4064 Because there is currently no concept of pre-delay slots, we can fix
4065 this only by always emitting a nop before a floating point branch. */
4067 if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9)
4068 strcpy (string, "nop\n\t");
4072 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4074 && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE))
4075 code = reverse_condition (code), reversed = 0;
4077 /* Start by writing the branch condition. */
4081 if (mode == CCFPmode || mode == CCFPEmode)
4083 strcat (string, "fbne");
4088 strcpy (string, "bne");
4094 if (mode == CCFPmode || mode == CCFPEmode)
4096 strcat (string, "fbe");
4101 strcpy (string, "be");
4107 if (mode == CCFPmode || mode == CCFPEmode)
4110 strcat (string, "fbul");
4112 strcat (string, "fbge");
4115 else if (mode == CC_NOOVmode)
4117 strcpy (string, "bpos");
4122 strcpy (string, "bge");
4128 if (mode == CCFPmode || mode == CCFPEmode)
4132 strcat (string, "fbule");
4137 strcat (string, "fbg");
4143 strcpy (string, "bg");
4149 if (mode == CCFPmode || mode == CCFPEmode)
4152 strcat (string, "fbug");
4154 strcat (string, "fble");
4159 strcpy (string, "ble");
4165 if (mode == CCFPmode || mode == CCFPEmode)
4169 strcat (string, "fbuge");
4174 strcat (string, "fbl");
4178 else if (mode == CC_NOOVmode)
4180 strcpy (string, "bneg");
4185 strcpy (string, "bl");
4191 strcpy (string, "bgeu");
4196 strcpy (string, "bgu");
4201 strcpy (string, "bleu");
4206 strcpy (string, "blu");
4214 /* Now add the annulling, the label, and a possible noop. */
4217 strcat (string, ",a");
4224 labelno = v8_labelno;
4230 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
4233 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
4238 if (mode == CCFPmode || mode == CCFPEmode)
4241 labelno = v9_fcc_labelno;
4242 /* Set the char indicating the number of the fcc reg to use. */
4243 labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
4245 else if (mode == CCXmode || mode == CCX_NOOVmode)
4246 labelno = v9_xcc_labelno;
4248 labelno = v9_icc_labelno;
4250 /* Set the char indicating the number of the operand containing the
4252 labelno[labeloff] = label + '0';
4254 strcat (string, "\t");
4256 strcat (string, " ");
4257 strcat (string, labelno);
4260 strcat (string, "\n\tnop");
4265 /* Return the string to output a conditional branch to LABEL, testing
4266 register REG. LABEL is the operand number of the label; REG is the
4267 operand number of the reg. OP is the conditional expression. The mode
4268 of REG says what kind of comparison we made.
4270 REVERSED is non-zero if we should reverse the sense of the comparison.
4272 ANNUL is non-zero if we should generate an annulling branch.
4274 NOOP is non-zero if we have to follow this branch by a noop. */
4277 output_v9branch (op, reg, label, reversed, annul, noop, insn)
4280 int reversed, annul, noop;
4283 static char string[20];
4284 enum rtx_code code = GET_CODE (op);
4285 enum machine_mode mode = GET_MODE (XEXP (op, 0));
4286 static char labelno[] = "%X, %lX";
4290 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4292 code = reverse_condition (code), reversed = 0;
4294 /* Only 64 bit versions of these instructions exist. */
4298 /* Start by writing the branch condition. */
4303 strcpy (string, "brnz");
4308 strcpy (string, "brz");
4313 strcpy (string, "brgez");
4318 strcpy (string, "brlz");
4323 strcpy (string, "brlez");
4328 strcpy (string, "brgz");
4336 /* Now add the annulling, reg, label, and nop. */
4339 strcat (string, ",a");
4343 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
4346 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
4350 labelno[1] = reg + '0';
4351 labelno[6] = label + '0';
4353 strcat (string, "\t");
4355 strcat (string, " ");
4356 strcat (string, labelno);
4359 strcat (string, "\n\tnop");
4364 /* Renumber registers in delay slot. Replace registers instead of
4365 renumbering because they may be shared.
4367 This does not handle instructions other than move. */
4370 epilogue_renumber (where)
4374 enum rtx_code code = GET_CODE (x);
4379 *where = x = copy_rtx (x);
4380 epilogue_renumber (&XEXP (x, 0));
4385 int regno = REGNO (x);
4386 if (regno > 8 && regno < 24)
4388 if (regno >= 24 && regno < 32)
4389 *where = gen_rtx_REG (GET_MODE (x), regno - 16);
4404 epilogue_renumber (&XEXP (x, 1));
4407 epilogue_renumber (&XEXP (x, 0));
4416 /* Output assembler code to return from a function. */
4419 output_return (operands)
4422 rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0;
4426 operands[0] = leaf_label;
4429 else if (leaf_function)
4431 /* No delay slot in a leaf function. */
4435 /* If we didn't allocate a frame pointer for the current function,
4436 the stack pointer might have been adjusted. Output code to
4439 operands[0] = GEN_INT (actual_fsize);
4441 /* Use sub of negated value in first two cases instead of add to
4442 allow actual_fsize == 4096. */
4444 if (actual_fsize <= 4096)
4446 if (SKIP_CALLERS_UNIMP_P)
4447 return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
4449 return "retl\n\tsub\t%%sp, -%0, %%sp";
4451 else if (actual_fsize <= 8192)
4453 operands[0] = GEN_INT (actual_fsize - 4096);
4454 if (SKIP_CALLERS_UNIMP_P)
4455 return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
4457 return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
4459 else if (SKIP_CALLERS_UNIMP_P)
4461 if ((actual_fsize & 0x3ff) != 0)
4462 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
4464 return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
4468 if ((actual_fsize & 0x3ff) != 0)
4469 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4471 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4478 epilogue_renumber (&SET_DEST (PATTERN (delay)));
4479 epilogue_renumber (&SET_SRC (PATTERN (delay)));
4481 if (SKIP_CALLERS_UNIMP_P)
4482 return "return\t%%i7+12%#";
4484 return "return\t%%i7+8%#";
4490 if (SKIP_CALLERS_UNIMP_P)
4491 return "jmp\t%%i7+12\n\trestore";
4493 return "ret\n\trestore";
4497 /* Leaf functions and non-leaf functions have different needs. */
4500 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
4503 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
4505 static int *reg_alloc_orders[] = {
4506 reg_leaf_alloc_order,
4507 reg_nonleaf_alloc_order};
4510 order_regs_for_local_alloc ()
4512 static int last_order_nonleaf = 1;
4514 if (regs_ever_live[15] != last_order_nonleaf)
4516 last_order_nonleaf = !last_order_nonleaf;
4517 bcopy ((char *) reg_alloc_orders[last_order_nonleaf],
4518 (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int));
4522 /* Return 1 if REG and MEM are legitimate enough to allow the various
4523 mem<-->reg splits to be run. */
4526 sparc_splitdi_legitimate(reg, mem)
4530 rtx addr_part = XEXP (mem, 0);
4532 /* Punt if we are here by mistake. */
4533 if (! reload_completed)
4536 /* We must have an offsettable memory reference. */
4537 if (! offsettable_memref_p (mem))
4540 /* If we have legitimate args for ldd/std, we do not want
4541 the split to happen. */
4542 if ((REGNO (reg) % 2) == 0
4543 && mem_min_alignment (mem, 8))
4550 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
4551 This makes them candidates for using ldd and std insns.
4553 Note reg1 and reg2 *must* be hard registers. */
4556 registers_ok_for_ldd_peep (reg1, reg2)
4559 /* We might have been passed a SUBREG. */
4560 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
4563 if (REGNO (reg1) % 2 != 0)
4566 /* Integer ldd is deprecated in SPARC V9 */
4567 if (TARGET_V9 && REGNO (reg1) < 32)
4570 return (REGNO (reg1) == REGNO (reg2) - 1);
4573 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
4576 This can only happen when addr1 and addr2 are consecutive memory
4577 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
4578 64 bit boundary (addr1 % 8 == 0).
4580 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
4581 registers are assumed to *never* be properly aligned and are
4584 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
4585 need only check that the offset for addr1 % 8 == 0. */
4588 addrs_ok_for_ldd_peep (addr1, addr2)
4593 /* Extract a register number and offset (if used) from the first addr. */
4594 if (GET_CODE (addr1) == PLUS)
4596 /* If not a REG, return zero. */
4597 if (GET_CODE (XEXP (addr1, 0)) != REG)
4601 reg1 = REGNO (XEXP (addr1, 0));
4602 /* The offset must be constant! */
4603 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
4605 offset1 = INTVAL (XEXP (addr1, 1));
4608 else if (GET_CODE (addr1) != REG)
4612 reg1 = REGNO (addr1);
4613 /* This was a simple (mem (reg)) expression. Offset is 0. */
4617 /* Make sure the second address is a (mem (plus (reg) (const_int). */
4618 if (GET_CODE (addr2) != PLUS)
4621 if (GET_CODE (XEXP (addr2, 0)) != REG
4622 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
4625 /* Only %fp and %sp are allowed. Additionally both addresses must
4626 use the same register. */
4627 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
4630 if (reg1 != REGNO (XEXP (addr2, 0)))
4633 /* The first offset must be evenly divisible by 8 to ensure the
4634 address is 64 bit aligned. */
4635 if (offset1 % 8 != 0)
4638 /* The offset for the second addr must be 4 more than the first addr. */
4639 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
4642 /* All the tests passed. addr1 and addr2 are valid for ldd and std
4647 /* Return 1 if reg is a pseudo, or is the first register in
4648 a hard register pair. This makes it a candidate for use in
4649 ldd and std insns. */
4652 register_ok_for_ldd (reg)
4655 /* We might have been passed a SUBREG. */
4656 if (GET_CODE (reg) != REG)
4659 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
4660 return (REGNO (reg) % 2 == 0);
4665 /* Print operand X (an rtx) in assembler syntax to file FILE.
4666 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4667 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4670 print_operand (file, x, code)
4678 /* Output a 'nop' if there's nothing for the delay slot. */
4679 if (dbr_sequence_length () == 0)
4680 fputs ("\n\t nop", file);
4683 /* Output an annul flag if there's nothing for the delay slot and we
4684 are optimizing. This is always used with '(' below. */
4685 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
4686 this is a dbx bug. So, we only do this when optimizing. */
4687 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
4688 Always emit a nop in case the next instruction is a branch. */
4689 if (dbr_sequence_length () == 0
4690 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
4694 /* Output a 'nop' if there's nothing for the delay slot and we are
4695 not optimizing. This is always used with '*' above. */
4696 if (dbr_sequence_length () == 0
4697 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
4698 fputs ("\n\t nop", file);
4701 /* Output the Embedded Medium/Anywhere code model base register. */
4702 fputs (EMBMEDANY_BASE_REG, file);
4705 /* Print out what we are using as the frame pointer. This might
4706 be %fp, or might be %sp+offset. */
4707 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
4708 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
4711 /* Adjust the operand to take into account a RESTORE operation. */
4712 if (GET_CODE (x) == CONST_INT)
4714 else if (GET_CODE (x) != REG)
4715 output_operand_lossage ("Invalid %%Y operand");
4716 else if (REGNO (x) < 8)
4717 fputs (reg_names[REGNO (x)], file);
4718 else if (REGNO (x) >= 24 && REGNO (x) < 32)
4719 fputs (reg_names[REGNO (x)-16], file);
4721 output_operand_lossage ("Invalid %%Y operand");
4724 /* Print out the low order register name of a register pair. */
4725 if (WORDS_BIG_ENDIAN)
4726 fputs (reg_names[REGNO (x)+1], file);
4728 fputs (reg_names[REGNO (x)], file);
4731 /* Print out the high order register name of a register pair. */
4732 if (WORDS_BIG_ENDIAN)
4733 fputs (reg_names[REGNO (x)], file);
4735 fputs (reg_names[REGNO (x)+1], file);
4738 /* Print out the second register name of a register pair or quad.
4739 I.e., R (%o0) => %o1. */
4740 fputs (reg_names[REGNO (x)+1], file);
4743 /* Print out the third register name of a register quad.
4744 I.e., S (%o0) => %o2. */
4745 fputs (reg_names[REGNO (x)+2], file);
4748 /* Print out the fourth register name of a register quad.
4749 I.e., T (%o0) => %o3. */
4750 fputs (reg_names[REGNO (x)+3], file);
4753 /* Print a condition code register. */
4754 if (REGNO (x) == SPARC_ICC_REG)
4756 /* We don't handle CC[X]_NOOVmode because they're not supposed
4758 if (GET_MODE (x) == CCmode)
4759 fputs ("%icc", file);
4760 else if (GET_MODE (x) == CCXmode)
4761 fputs ("%xcc", file);
4766 /* %fccN register */
4767 fputs (reg_names[REGNO (x)], file);
4770 /* Print the operand's address only. */
4771 output_address (XEXP (x, 0));
4774 /* In this case we need a register. Use %g0 if the
4775 operand is const0_rtx. */
4777 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
4779 fputs ("%g0", file);
4786 switch (GET_CODE (x))
4788 case IOR: fputs ("or", file); break;
4789 case AND: fputs ("and", file); break;
4790 case XOR: fputs ("xor", file); break;
4791 default: output_operand_lossage ("Invalid %%A operand");
4796 switch (GET_CODE (x))
4798 case IOR: fputs ("orn", file); break;
4799 case AND: fputs ("andn", file); break;
4800 case XOR: fputs ("xnor", file); break;
4801 default: output_operand_lossage ("Invalid %%B operand");
4805 /* These are used by the conditional move instructions. */
4809 enum rtx_code rc = (code == 'c'
4810 ? reverse_condition (GET_CODE (x))
4814 case NE: fputs ("ne", file); break;
4815 case EQ: fputs ("e", file); break;
4816 case GE: fputs ("ge", file); break;
4817 case GT: fputs ("g", file); break;
4818 case LE: fputs ("le", file); break;
4819 case LT: fputs ("l", file); break;
4820 case GEU: fputs ("geu", file); break;
4821 case GTU: fputs ("gu", file); break;
4822 case LEU: fputs ("leu", file); break;
4823 case LTU: fputs ("lu", file); break;
4824 default: output_operand_lossage (code == 'c'
4825 ? "Invalid %%c operand"
4826 : "Invalid %%C operand");
4831 /* These are used by the movr instruction pattern. */
4835 enum rtx_code rc = (code == 'd'
4836 ? reverse_condition (GET_CODE (x))
4840 case NE: fputs ("ne", file); break;
4841 case EQ: fputs ("e", file); break;
4842 case GE: fputs ("gez", file); break;
4843 case LT: fputs ("lz", file); break;
4844 case LE: fputs ("lez", file); break;
4845 case GT: fputs ("gz", file); break;
4846 default: output_operand_lossage (code == 'd'
4847 ? "Invalid %%d operand"
4848 : "Invalid %%D operand");
4855 /* Print a sign-extended character. */
4856 int i = INTVAL (x) & 0xff;
4859 fprintf (file, "%d", i);
4864 /* Operand must be a MEM; write its address. */
4865 if (GET_CODE (x) != MEM)
4866 output_operand_lossage ("Invalid %%f operand");
4867 output_address (XEXP (x, 0));
4871 /* Do nothing special. */
4875 /* Undocumented flag. */
4876 output_operand_lossage ("invalid operand output code");
4879 if (GET_CODE (x) == REG)
4880 fputs (reg_names[REGNO (x)], file);
4881 else if (GET_CODE (x) == MEM)
4884 /* Poor Sun assembler doesn't understand absolute addressing. */
4885 if (CONSTANT_P (XEXP (x, 0))
4886 && ! TARGET_LIVE_G0)
4887 fputs ("%g0+", file);
4888 output_address (XEXP (x, 0));
4891 else if (GET_CODE (x) == HIGH)
4893 fputs ("%hi(", file);
4894 output_addr_const (file, XEXP (x, 0));
4897 else if (GET_CODE (x) == LO_SUM)
4899 print_operand (file, XEXP (x, 0), 0);
4900 if (TARGET_CM_MEDMID)
4901 fputs ("+%l44(", file);
4903 fputs ("+%lo(", file);
4904 output_addr_const (file, XEXP (x, 1));
4907 else if (GET_CODE (x) == CONST_DOUBLE
4908 && (GET_MODE (x) == VOIDmode
4909 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
4911 if (CONST_DOUBLE_HIGH (x) == 0)
4912 fprintf (file, "%u", CONST_DOUBLE_LOW (x));
4913 else if (CONST_DOUBLE_HIGH (x) == -1
4914 && CONST_DOUBLE_LOW (x) < 0)
4915 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
4917 output_operand_lossage ("long long constant not a valid immediate operand");
4919 else if (GET_CODE (x) == CONST_DOUBLE)
4920 output_operand_lossage ("floating point constant not a valid immediate operand");
4921 else { output_addr_const (file, x); }
4924 /* This function outputs assembler code for VALUE to FILE, where VALUE is
4925 a 64 bit (DImode) value. */
4927 /* ??? If there is a 64 bit counterpart to .word that the assembler
4928 understands, then using that would simply this code greatly. */
4929 /* ??? We only output .xword's for symbols and only then in environments
4930 where the assembler can handle them. */
4933 output_double_int (file, value)
4937 if (GET_CODE (value) == CONST_INT)
4939 /* ??? This has endianness issues. */
4940 #if HOST_BITS_PER_WIDE_INT == 64
4941 HOST_WIDE_INT xword = INTVAL (value);
4942 HOST_WIDE_INT high, low;
4944 high = (xword >> 32) & 0xffffffff;
4945 low = xword & 0xffffffff;
4946 ASM_OUTPUT_INT (file, GEN_INT (high));
4947 ASM_OUTPUT_INT (file, GEN_INT (low));
4949 if (INTVAL (value) < 0)
4950 ASM_OUTPUT_INT (file, constm1_rtx);
4952 ASM_OUTPUT_INT (file, const0_rtx);
4953 ASM_OUTPUT_INT (file, value);
4956 else if (GET_CODE (value) == CONST_DOUBLE)
4958 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value)));
4959 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value)));
4961 else if (GET_CODE (value) == SYMBOL_REF
4962 || GET_CODE (value) == CONST
4963 || GET_CODE (value) == PLUS
4964 || (TARGET_ARCH64 &&
4965 (GET_CODE (value) == LABEL_REF
4966 || GET_CODE (value) == CODE_LABEL
4967 || GET_CODE (value) == MINUS)))
4969 if (!TARGET_V9 || TARGET_CM_MEDLOW)
4971 ASM_OUTPUT_INT (file, const0_rtx);
4972 ASM_OUTPUT_INT (file, value);
4976 fprintf (file, "\t%s\t", ASM_LONGLONG);
4977 output_addr_const (file, value);
4978 fprintf (file, "\n");
4985 /* Return the value of a code used in the .proc pseudo-op that says
4986 what kind of result this function returns. For non-C types, we pick
4987 the closest C type. */
4989 #ifndef CHAR_TYPE_SIZE
4990 #define CHAR_TYPE_SIZE BITS_PER_UNIT
4993 #ifndef SHORT_TYPE_SIZE
4994 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
4997 #ifndef INT_TYPE_SIZE
4998 #define INT_TYPE_SIZE BITS_PER_WORD
5001 #ifndef LONG_TYPE_SIZE
5002 #define LONG_TYPE_SIZE BITS_PER_WORD
5005 #ifndef LONG_LONG_TYPE_SIZE
5006 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
5009 #ifndef FLOAT_TYPE_SIZE
5010 #define FLOAT_TYPE_SIZE BITS_PER_WORD
5013 #ifndef DOUBLE_TYPE_SIZE
5014 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5017 #ifndef LONG_DOUBLE_TYPE_SIZE
5018 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5022 sparc_type_code (type)
5025 register unsigned long qualifiers = 0;
5026 register unsigned shift;
5028 /* Only the first 30 bits of the qualifier are valid. We must refrain from
5029 setting more, since some assemblers will give an error for this. Also,
5030 we must be careful to avoid shifts of 32 bits or more to avoid getting
5031 unpredictable results. */
5033 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
5035 switch (TREE_CODE (type))
5041 qualifiers |= (3 << shift);
5046 qualifiers |= (2 << shift);
5050 case REFERENCE_TYPE:
5052 qualifiers |= (1 << shift);
5056 return (qualifiers | 8);
5059 case QUAL_UNION_TYPE:
5060 return (qualifiers | 9);
5063 return (qualifiers | 10);
5066 return (qualifiers | 16);
5069 /* If this is a range type, consider it to be the underlying
5071 if (TREE_TYPE (type) != 0)
5074 /* Carefully distinguish all the standard types of C,
5075 without messing up if the language is not C. We do this by
5076 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
5077 look at both the names and the above fields, but that's redundant.
5078 Any type whose size is between two C types will be considered
5079 to be the wider of the two types. Also, we do not have a
5080 special code to use for "long long", so anything wider than
5081 long is treated the same. Note that we can't distinguish
5082 between "int" and "long" in this code if they are the same
5083 size, but that's fine, since neither can the assembler. */
5085 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
5086 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
5088 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
5089 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
5091 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
5092 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
5095 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
5098 /* If this is a range type, consider it to be the underlying
5100 if (TREE_TYPE (type) != 0)
5103 /* Carefully distinguish all the standard types of C,
5104 without messing up if the language is not C. */
5106 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
5107 return (qualifiers | 6);
5110 return (qualifiers | 7);
5112 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
5113 /* ??? We need to distinguish between double and float complex types,
5114 but I don't know how yet because I can't reach this code from
5115 existing front-ends. */
5116 return (qualifiers | 7); /* Who knows? */
5118 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
5119 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
5120 case FILE_TYPE: /* GNU Pascal FILE type. */
5121 case SET_TYPE: /* GNU Pascal SET type. */
5122 case LANG_TYPE: /* ? */
5126 abort (); /* Not a type! */
5133 /* Nested function support. */
5135 /* Emit RTL insns to initialize the variable parts of a trampoline.
5136 FNADDR is an RTX for the address of the function's pure code.
5137 CXT is an RTX for the static chain value for the function.
5139 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
5140 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
5141 (to store insns). This is a bit excessive. Perhaps a different
5142 mechanism would be better here.
5144 Emit enough FLUSH insns to synchronize the data and instruction caches. */
5147 sparc_initialize_trampoline (tramp, fnaddr, cxt)
5148 rtx tramp, fnaddr, cxt;
5150 /* SPARC 32 bit trampoline:
5153 sethi %hi(static), %g2
5155 or %g2, %lo(static), %g2
5157 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
5158 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
5161 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
5162 expand_binop (SImode, ior_optab,
5163 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
5164 size_int (10), 0, 1),
5165 GEN_INT (0x03000000),
5166 NULL_RTX, 1, OPTAB_DIRECT));
5168 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
5169 expand_binop (SImode, ior_optab,
5170 expand_shift (RSHIFT_EXPR, SImode, cxt,
5171 size_int (10), 0, 1),
5172 GEN_INT (0x05000000),
5173 NULL_RTX, 1, OPTAB_DIRECT));
5175 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
5176 expand_binop (SImode, ior_optab,
5177 expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX),
5178 GEN_INT (0x81c06000),
5179 NULL_RTX, 1, OPTAB_DIRECT));
5181 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
5182 expand_binop (SImode, ior_optab,
5183 expand_and (cxt, GEN_INT (0x3ff), NULL_RTX),
5184 GEN_INT (0x8410a000),
5185 NULL_RTX, 1, OPTAB_DIRECT));
5187 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
5188 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
5189 aligned on a 16 byte boundary so one flush clears it all. */
5190 if (sparc_cpu != PROCESSOR_ULTRASPARC)
5191 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
5192 plus_constant (tramp, 8)))));
5195 /* The 64 bit version is simpler because it makes more sense to load the
5196 values as "immediate" data out of the trampoline. It's also easier since
5197 we can read the PC without clobbering a register. */
5200 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
5201 rtx tramp, fnaddr, cxt;
5211 emit_move_insn (gen_rtx_MEM (SImode, tramp),
5212 GEN_INT (0x83414000));
5213 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
5214 GEN_INT (0xca586018));
5215 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
5216 GEN_INT (0x81c04000));
5217 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
5218 GEN_INT (0xca586010));
5219 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
5220 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 20)), fnaddr);
5221 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, tramp))));
5222 if (sparc_cpu != PROCESSOR_ULTRASPARC)
5223 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
5226 /* Subroutines to support a flat (single) register window calling
5229 /* Single-register window sparc stack frames look like:
5231 Before call After call
5232 +-----------------------+ +-----------------------+
5234 mem | caller's temps. | | caller's temps. |
5236 +-----------------------+ +-----------------------+
5238 | arguments on stack. | | arguments on stack. |
5240 +-----------------------+FP+92->+-----------------------+
5241 | 6 words to save | | 6 words to save |
5242 | arguments passed | | arguments passed |
5243 | in registers, even | | in registers, even |
5244 | if not passed. | | if not passed. |
5245 SP+68->+-----------------------+FP+68->+-----------------------+
5246 | 1 word struct addr | | 1 word struct addr |
5247 +-----------------------+FP+64->+-----------------------+
5249 | 16 word reg save area | | 16 word reg save area |
5251 SP->+-----------------------+ FP->+-----------------------+
5253 | fp/alu reg moves |
5254 FP-16->+-----------------------+
5258 +-----------------------+
5260 | fp register save |
5262 +-----------------------+
5264 | gp register save |
5266 +-----------------------+
5268 | alloca allocations |
5270 +-----------------------+
5272 | arguments on stack |
5274 SP+92->+-----------------------+
5276 | arguments passed |
5277 | in registers, even |
5278 low | if not passed. |
5279 memory SP+68->+-----------------------+
5280 | 1 word struct addr |
5281 SP+64->+-----------------------+
5283 I 16 word reg save area |
5285 SP->+-----------------------+ */
5287 /* Structure to be filled in by sparc_flat_compute_frame_size with register
5288 save masks, and offsets for the current function. */
5290 struct sparc_frame_info
5292 unsigned long total_size; /* # bytes that the entire frame takes up. */
5293 unsigned long var_size; /* # bytes that variables take up. */
5294 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5295 unsigned long extra_size; /* # bytes of extra gunk. */
5296 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5297 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5298 unsigned long gmask; /* Mask of saved gp registers. */
5299 unsigned long fmask; /* Mask of saved fp registers. */
5300 unsigned long reg_offset; /* Offset from new sp to store regs. */
5301 int initialized; /* Nonzero if frame size already calculated. */
5304 /* Current frame information calculated by sparc_flat_compute_frame_size. */
5305 struct sparc_frame_info current_frame_info;
5307 /* Zero structure to initialize current_frame_info. */
5308 struct sparc_frame_info zero_frame_info;
5310 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
5312 #define RETURN_ADDR_REGNUM 15
5313 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
5314 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
5316 #define MUST_SAVE_REGISTER(regno) \
5317 ((regs_ever_live[regno] && !call_used_regs[regno]) \
5318 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
5319 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
5321 /* Return the bytes needed to compute the frame pointer from the current
5325 sparc_flat_compute_frame_size (size)
5326 int size; /* # of var. bytes allocated. */
5329 unsigned long total_size; /* # bytes that the entire frame takes up. */
5330 unsigned long var_size; /* # bytes that variables take up. */
5331 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5332 unsigned long extra_size; /* # extra bytes. */
5333 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5334 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5335 unsigned long gmask; /* Mask of saved gp registers. */
5336 unsigned long fmask; /* Mask of saved fp registers. */
5337 unsigned long reg_offset; /* Offset to register save area. */
5338 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
5340 /* This is the size of the 16 word reg save area, 1 word struct addr
5341 area, and 4 word fp/alu register copy area. */
5342 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
5344 /* Also include the size needed for the 6 parameter registers. */
5345 args_size = current_function_outgoing_args_size + 24;
5346 total_size = var_size + args_size + extra_size;
5354 /* Calculate space needed for gp registers. */
5355 for (regno = 1; regno <= 31; regno++)
5357 if (MUST_SAVE_REGISTER (regno))
5359 /* If we need to save two regs in a row, ensure there's room to bump
5360 up the address to align it to a doubleword boundary. */
5361 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
5363 if (gp_reg_size % 8 != 0)
5365 gp_reg_size += 2 * UNITS_PER_WORD;
5366 gmask |= 3 << regno;
5372 gp_reg_size += UNITS_PER_WORD;
5373 gmask |= 1 << regno;
5378 /* Calculate space needed for fp registers. */
5379 for (regno = 32; regno <= 63; regno++)
5381 if (regs_ever_live[regno] && !call_used_regs[regno])
5383 fp_reg_size += UNITS_PER_WORD;
5384 fmask |= 1 << (regno - 32);
5391 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
5392 /* Ensure save area is 8 byte aligned if we need it. */
5394 if (need_aligned_p && n != 0)
5396 total_size += 8 - n;
5397 reg_offset += 8 - n;
5399 total_size += gp_reg_size + fp_reg_size;
5402 /* ??? This looks a little suspicious. Clarify. */
5403 if (total_size == extra_size)
5404 total_size = extra_size = 0;
5406 total_size = SPARC_STACK_ALIGN (total_size);
5408 /* Save other computed information. */
5409 current_frame_info.total_size = total_size;
5410 current_frame_info.var_size = var_size;
5411 current_frame_info.args_size = args_size;
5412 current_frame_info.extra_size = extra_size;
5413 current_frame_info.gp_reg_size = gp_reg_size;
5414 current_frame_info.fp_reg_size = fp_reg_size;
5415 current_frame_info.gmask = gmask;
5416 current_frame_info.fmask = fmask;
5417 current_frame_info.reg_offset = reg_offset;
5418 current_frame_info.initialized = reload_completed;
5420 /* Ok, we're done. */
5424 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
5427 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
5428 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
5429 [BASE_REG+OFFSET] will always be a valid address.
5431 WORD_OP is either "st" for save, "ld" for restore.
5432 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
5435 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
5436 doubleword_op, base_offset)
5439 unsigned int offset;
5440 unsigned long gmask;
5441 unsigned long fmask;
5443 char *doubleword_op;
5444 unsigned long base_offset;
5448 if (gmask == 0 && fmask == 0)
5451 /* Save registers starting from high to low. We've already saved the
5452 previous frame pointer and previous return address for the debugger's
5453 sake. The debugger allows us to not need a nop in the epilog if at least
5454 one register is reloaded in addition to return address. */
5458 for (regno = 1; regno <= 31; regno++)
5460 if ((gmask & (1L << regno)) != 0)
5462 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
5464 /* We can save two registers in a row. If we're not at a
5465 double word boundary, move to one.
5466 sparc_flat_compute_frame_size ensures there's room to do
5468 if (offset % 8 != 0)
5469 offset += UNITS_PER_WORD;
5471 if (word_op[0] == 's')
5473 fprintf (file, "\t%s\t%s, [%s+%d]\n",
5474 doubleword_op, reg_names[regno],
5476 if (dwarf2out_do_frame ())
5478 char *l = dwarf2out_cfi_label ();
5479 dwarf2out_reg_save (l, regno, offset + base_offset);
5481 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
5485 fprintf (file, "\t%s\t[%s+%d], %s\n",
5486 doubleword_op, base_reg, offset,
5489 offset += 2 * UNITS_PER_WORD;
5494 if (word_op[0] == 's')
5496 fprintf (file, "\t%s\t%s, [%s+%d]\n",
5497 word_op, reg_names[regno],
5499 if (dwarf2out_do_frame ())
5500 dwarf2out_reg_save ("", regno, offset + base_offset);
5503 fprintf (file, "\t%s\t[%s+%d], %s\n",
5504 word_op, base_reg, offset, reg_names[regno]);
5506 offset += UNITS_PER_WORD;
5514 for (regno = 32; regno <= 63; regno++)
5516 if ((fmask & (1L << (regno - 32))) != 0)
5518 if (word_op[0] == 's')
5520 fprintf (file, "\t%s\t%s, [%s+%d]\n",
5521 word_op, reg_names[regno],
5523 if (dwarf2out_do_frame ())
5524 dwarf2out_reg_save ("", regno, offset + base_offset);
5527 fprintf (file, "\t%s\t[%s+%d], %s\n",
5528 word_op, base_reg, offset, reg_names[regno]);
5530 offset += UNITS_PER_WORD;
5536 /* Set up the stack and frame (if desired) for the function. */
5539 sparc_flat_output_function_prologue (file, size)
5543 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5544 unsigned long gmask = current_frame_info.gmask;
5546 /* This is only for the human reader. */
5547 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
5548 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
5550 current_frame_info.var_size,
5551 current_frame_info.gp_reg_size / 4,
5552 current_frame_info.fp_reg_size / 4,
5553 current_function_outgoing_args_size,
5554 current_frame_info.extra_size);
5556 size = SPARC_STACK_ALIGN (size);
5557 size = (! current_frame_info.initialized
5558 ? sparc_flat_compute_frame_size (size)
5559 : current_frame_info.total_size);
5561 /* These cases shouldn't happen. Catch them now. */
5562 if (size == 0 && (gmask || current_frame_info.fmask))
5565 /* Allocate our stack frame by decrementing %sp.
5566 At present, the only algorithm gdb can use to determine if this is a
5567 flat frame is if we always set %i7 if we set %sp. This can be optimized
5568 in the future by putting in some sort of debugging information that says
5569 this is a `flat' function. However, there is still the case of debugging
5570 code without such debugging information (including cases where most fns
5571 have such info, but there is one that doesn't). So, always do this now
5572 so we don't get a lot of code out there that gdb can't handle.
5573 If the frame pointer isn't needn't then that's ok - gdb won't be able to
5574 distinguish us from a non-flat function but there won't (and shouldn't)
5575 be any differences anyway. The return pc is saved (if necessary) right
5576 after %i7 so gdb won't have to look too far to find it. */
5579 unsigned int reg_offset = current_frame_info.reg_offset;
5580 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
5581 char *t1_str = "%g1";
5583 /* Things get a little tricky if local variables take up more than ~4096
5584 bytes and outgoing arguments take up more than ~4096 bytes. When that
5585 happens, the register save area can't be accessed from either end of
5586 the frame. Handle this by decrementing %sp to the start of the gp
5587 register save area, save the regs, update %i7, and then set %sp to its
5588 final value. Given that we only have one scratch register to play
5589 with it is the cheapest solution, and it helps gdb out as it won't
5590 slow down recognition of flat functions.
5591 Don't change the order of insns emitted here without checking with
5592 the gdb folk first. */
5594 /* Is the entire register save area offsettable from %sp? */
5595 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
5599 fprintf (file, "\tadd\t%s, %d, %s\n",
5600 sp_str, -size, sp_str);
5601 if (gmask & FRAME_POINTER_MASK)
5603 fprintf (file, "\tst\t%s, [%s+%d]\n",
5604 fp_str, sp_str, reg_offset);
5605 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
5606 sp_str, -size, fp_str, ASM_COMMENT_START);
5612 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
5613 size, t1_str, sp_str, t1_str, sp_str);
5614 if (gmask & FRAME_POINTER_MASK)
5616 fprintf (file, "\tst\t%s, [%s+%d]\n",
5617 fp_str, sp_str, reg_offset);
5618 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
5619 sp_str, t1_str, fp_str, ASM_COMMENT_START);
5623 if (dwarf2out_do_frame ())
5625 char *l = dwarf2out_cfi_label ();
5626 if (gmask & FRAME_POINTER_MASK)
5628 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
5629 reg_offset - 4 - size);
5630 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
5633 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
5635 if (gmask & RETURN_ADDR_MASK)
5637 fprintf (file, "\tst\t%s, [%s+%d]\n",
5638 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
5639 if (dwarf2out_do_frame ())
5640 dwarf2out_return_save ("", reg_offset - size);
5643 sparc_flat_save_restore (file, sp_str, reg_offset,
5644 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5645 current_frame_info.fmask,
5646 "st", "std", -size);
5650 /* Subtract %sp in two steps, but make sure there is always a
5651 64 byte register save area, and %sp is properly aligned. */
5652 /* Amount to decrement %sp by, the first time. */
5653 unsigned int size1 = ((size - reg_offset + 64) + 15) & -16;
5654 /* Offset to register save area from %sp. */
5655 unsigned int offset = size1 - (size - reg_offset);
5659 fprintf (file, "\tadd\t%s, %d, %s\n",
5660 sp_str, -size1, sp_str);
5661 if (gmask & FRAME_POINTER_MASK)
5663 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
5664 fp_str, sp_str, offset, sp_str, -size1, fp_str,
5671 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
5672 size1, t1_str, sp_str, t1_str, sp_str);
5673 if (gmask & FRAME_POINTER_MASK)
5675 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
5676 fp_str, sp_str, offset, sp_str, t1_str, fp_str,
5681 if (dwarf2out_do_frame ())
5683 char *l = dwarf2out_cfi_label ();
5684 if (gmask & FRAME_POINTER_MASK)
5686 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
5687 offset - 4 - size1);
5688 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
5691 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
5693 if (gmask & RETURN_ADDR_MASK)
5695 fprintf (file, "\tst\t%s, [%s+%d]\n",
5696 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
5697 if (dwarf2out_do_frame ())
5698 /* offset - size1 == reg_offset - size
5699 if reg_offset were updated above like offset. */
5700 dwarf2out_return_save ("", offset - size1);
5703 sparc_flat_save_restore (file, sp_str, offset,
5704 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5705 current_frame_info.fmask,
5706 "st", "std", -size1);
5707 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
5708 size - size1, t1_str, sp_str, t1_str, sp_str);
5709 if (dwarf2out_do_frame ())
5710 if (! (gmask & FRAME_POINTER_MASK))
5711 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
5715 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
5718 /* Do any necessary cleanup after a function to restore stack, frame,
5722 sparc_flat_output_function_epilogue (file, size)
5726 rtx epilogue_delay = current_function_epilogue_delay_list;
5727 int noepilogue = FALSE;
5729 /* This is only for the human reader. */
5730 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
5732 /* The epilogue does not depend on any registers, but the stack
5733 registers, so we assume that if we have 1 pending nop, it can be
5734 ignored, and 2 it must be filled (2 nops occur for integer
5735 multiply and divide). */
5737 size = SPARC_STACK_ALIGN (size);
5738 size = (!current_frame_info.initialized
5739 ? sparc_flat_compute_frame_size (size)
5740 : current_frame_info.total_size);
5742 if (size == 0 && epilogue_delay == 0)
5744 rtx insn = get_last_insn ();
5746 /* If the last insn was a BARRIER, we don't have to write any code
5747 because a jump (aka return) was put there. */
5748 if (GET_CODE (insn) == NOTE)
5749 insn = prev_nonnote_insn (insn);
5750 if (insn && GET_CODE (insn) == BARRIER)
5756 unsigned int reg_offset = current_frame_info.reg_offset;
5758 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5759 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
5760 char *t1_str = "%g1";
5762 /* In the reload sequence, we don't need to fill the load delay
5763 slots for most of the loads, also see if we can fill the final
5764 delay slot if not otherwise filled by the reload sequence. */
5767 fprintf (file, "\tset\t%d, %s\n", size, t1_str);
5769 if (frame_pointer_needed)
5772 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
5773 fp_str, t1_str, sp_str, ASM_COMMENT_START);
5775 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
5776 fp_str, size, sp_str, ASM_COMMENT_START);
5779 /* Is the entire register save area offsettable from %sp? */
5780 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
5786 /* Restore %sp in two steps, but make sure there is always a
5787 64 byte register save area, and %sp is properly aligned. */
5788 /* Amount to increment %sp by, the first time. */
5789 size1 = ((reg_offset - 64 - 16) + 15) & -16;
5790 /* Offset to register save area from %sp. */
5791 reg_offset = size1 - reg_offset;
5793 fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n",
5794 size1, t1_str, sp_str, t1_str, sp_str);
5797 /* We must restore the frame pointer and return address reg first
5798 because they are treated specially by the prologue output code. */
5799 if (current_frame_info.gmask & FRAME_POINTER_MASK)
5801 fprintf (file, "\tld\t[%s+%d], %s\n",
5802 sp_str, reg_offset, fp_str);
5805 if (current_frame_info.gmask & RETURN_ADDR_MASK)
5807 fprintf (file, "\tld\t[%s+%d], %s\n",
5808 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
5812 /* Restore any remaining saved registers. */
5813 sparc_flat_save_restore (file, sp_str, reg_offset,
5814 current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5815 current_frame_info.fmask,
5818 /* If we had to increment %sp in two steps, record it so the second
5819 restoration in the epilogue finishes up. */
5824 fprintf (file, "\tset\t%d, %s\n",
5828 if (current_function_returns_struct)
5829 fprintf (file, "\tjmp\t%%o7+12\n");
5831 fprintf (file, "\tretl\n");
5833 /* If the only register saved is the return address, we need a
5834 nop, unless we have an instruction to put into it. Otherwise
5835 we don't since reloading multiple registers doesn't reference
5836 the register being loaded. */
5842 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
5845 else if (size > 4095)
5846 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
5849 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str);
5852 fprintf (file, "\tnop\n");
5855 /* Reset state info for each function. */
5856 current_frame_info = zero_frame_info;
5858 sparc_output_deferred_case_vectors ();
5861 /* Define the number of delay slots needed for the function epilogue.
5863 On the sparc, we need a slot if either no stack has been allocated,
5864 or the only register saved is the return register. */
5867 sparc_flat_epilogue_delay_slots ()
5869 if (!current_frame_info.initialized)
5870 (void) sparc_flat_compute_frame_size (get_frame_size ());
5872 if (current_frame_info.total_size == 0)
5878 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
5879 Any single length instruction which doesn't reference the stack or frame
5883 sparc_flat_eligible_for_epilogue_delay (trial, slot)
5885 int slot ATTRIBUTE_UNUSED;
5887 rtx pat = PATTERN (trial);
5889 if (get_attr_length (trial) != 1)
5892 /* If %g0 is live, there are lots of things we can't handle.
5893 Rather than trying to find them all now, let's punt and only
5894 optimize things as necessary. */
5898 if (! reg_mentioned_p (stack_pointer_rtx, pat)
5899 && ! reg_mentioned_p (frame_pointer_rtx, pat))
5905 /* Adjust the cost of a scheduling dependency. Return the new cost of
5906 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5909 supersparc_adjust_cost (insn, link, dep_insn, cost)
5915 enum attr_type insn_type;
5917 if (! recog_memoized (insn))
5920 insn_type = get_attr_type (insn);
5922 if (REG_NOTE_KIND (link) == 0)
5924 /* Data dependency; DEP_INSN writes a register that INSN reads some
5927 /* if a load, then the dependence must be on the memory address;
5928 add an extra 'cycle'. Note that the cost could be two cycles
5929 if the reg was written late in an instruction group; we can't tell
5931 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
5934 /* Get the delay only if the address of the store is the dependence. */
5935 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
5937 rtx pat = PATTERN(insn);
5938 rtx dep_pat = PATTERN (dep_insn);
5940 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
5941 return cost; /* This shouldn't happen! */
5943 /* The dependency between the two instructions was on the data that
5944 is being stored. Assume that this implies that the address of the
5945 store is not dependent. */
5946 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
5949 return cost + 3; /* An approximation. */
5952 /* A shift instruction cannot receive its data from an instruction
5953 in the same cycle; add a one cycle penalty. */
5954 if (insn_type == TYPE_SHIFT)
5955 return cost + 3; /* Split before cascade into shift. */
5959 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
5960 INSN writes some cycles later. */
5962 /* These are only significant for the fpu unit; writing a fp reg before
5963 the fpu has finished with it stalls the processor. */
5965 /* Reusing an integer register causes no problems. */
5966 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
5974 ultrasparc_adjust_cost (insn, link, dep_insn, cost)
5980 enum attr_type insn_type, dep_type;
5981 rtx pat = PATTERN(insn);
5982 rtx dep_pat = PATTERN (dep_insn);
5984 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
5987 insn_type = get_attr_type (insn);
5988 dep_type = get_attr_type (dep_insn);
5990 #define SLOW_FP(dep_type) \
5991 (dep_type == TYPE_FPSQRT || dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
5993 switch (REG_NOTE_KIND (link))
5996 /* Data dependency; DEP_INSN writes a register that INSN reads some
6001 /* UltraSPARC can dual issue a store and an instruction setting
6002 the value stored, except for divide and square root. */
6004 if (! SLOW_FP (dep_type))
6009 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6012 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6013 /* The dependency between the two instructions is on the data
6014 that is being stored. Assume that the address of the store
6015 is not also dependent. */
6022 /* A load does not return data until at least 11 cycles after
6023 a store to the same location. 3 cycles are accounted for
6024 in the load latency; add the other 8 here. */
6025 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
6027 /* If the addresses are not equal this may be a false
6028 dependency because pointer aliasing could not be
6029 determined. Add only 2 cycles in that case. 2 is
6030 an arbitrary compromise between 8, which would cause
6031 the scheduler to generate worse code elsewhere to
6032 compensate for a dependency which might not really
6034 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
6035 || GET_CODE (SET_SRC (pat)) != MEM
6036 || GET_CODE (SET_DEST (dep_pat)) != MEM
6037 || ! rtx_equal_p (XEXP (SET_SRC (pat), 0),
6038 XEXP (SET_DEST (dep_pat), 0)))
6046 /* Compare to branch latency is 0. There is no benefit from
6047 separating compare and branch. */
6048 if (dep_type == TYPE_COMPARE)
6050 /* Floating point compare to branch latency is less than
6051 compare to conditional move. */
6052 if (dep_type == TYPE_FPCMP)
6057 /* FMOVR class instructions can not issue in the same cycle
6058 or the cycle after an instruction which writes any
6059 integer register. Model this as cost 2 for dependent
6061 if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY
6062 || dep_type == TYPE_BINARY)
6065 /* Otherwise check as for integer conditional moves. */
6068 /* Conditional moves involving integer registers wait until
6069 3 cycles after loads return data. The interlock applies
6070 to all loads, not just dependent loads, but that is hard
6072 if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD)
6082 /* Divide and square root lock destination registers for full latency. */
6083 if (! SLOW_FP (dep_type))
6091 /* Other costs not accounted for:
6092 - Multiply should be modeled as having no latency because there is
6093 nothing the scheduler can do about it.
6094 - Single precision floating point loads lock the other half of
6095 the even/odd register pair.
6096 - Several hazards associated with ldd/std are ignored because these
6097 instructions are rarely generated for V9.
6098 - A shift following an integer instruction which does not set the
6099 condition codes can not issue in the same cycle.
6100 - The floating point pipeline can not have both a single and double
6101 precision operation active at the same time. Format conversions
6102 and graphics instructions are given honorary double precision status.
6103 - call and jmpl are always the first instruction in a group. */
6116 /* Assume V9 processors are capable of at least dual-issue. */
6118 case PROCESSOR_SUPERSPARC:
6120 case PROCESSOR_ULTRASPARC:
6126 set_extends(x, insn)
6129 register rtx pat = PATTERN (insn);
6131 switch (GET_CODE (SET_SRC (pat)))
6133 /* Load and some shift instructions zero extend. */
6136 /* sethi clears the high bits */
6138 /* LO_SUM is used with sethi. sethi cleared the high
6139 bits and the values used with lo_sum are positive */
6141 /* Store flag stores 0 or 1 */
6151 rtx op1 = XEXP (SET_SRC (pat), 1);
6152 if (GET_CODE (op1) == CONST_INT)
6153 return INTVAL (op1) >= 0;
6154 if (GET_CODE (XEXP (SET_SRC (pat), 0)) == REG
6155 && sparc_check_64 (XEXP (SET_SRC (pat), 0), insn) == 1)
6157 if (GET_CODE (op1) == REG
6158 && sparc_check_64 ((op1), insn) == 1)
6163 return GET_MODE (SET_SRC (pat)) == SImode;
6164 /* Positive integers leave the high bits zero. */
6166 return ! (CONST_DOUBLE_LOW (x) & 0x80000000);
6168 return ! (INTVAL (x) & 0x80000000);
6171 return - (GET_MODE (SET_SRC (pat)) == SImode);
6177 /* We _ought_ to have only one kind per function, but... */
6178 static rtx sparc_addr_diff_list;
6179 static rtx sparc_addr_list;
6182 sparc_defer_case_vector (lab, vec, diff)
6186 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
6188 sparc_addr_diff_list
6189 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
6191 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
6195 sparc_output_addr_vec (vec)
6198 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
6199 int idx, vlen = XVECLEN (body, 0);
6201 #ifdef ASM_OUTPUT_CASE_LABEL
6202 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
6205 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
6208 for (idx = 0; idx < vlen; idx++)
6210 ASM_OUTPUT_ADDR_VEC_ELT
6211 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
6216 sparc_output_addr_diff_vec (vec)
6219 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
6220 rtx base = XEXP (XEXP (body, 0), 0);
6221 int idx, vlen = XVECLEN (body, 1);
6223 #ifdef ASM_OUTPUT_CASE_LABEL
6224 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
6227 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
6230 for (idx = 0; idx < vlen; idx++)
6232 ASM_OUTPUT_ADDR_DIFF_ELT
6235 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
6236 CODE_LABEL_NUMBER (base));
6241 sparc_output_deferred_case_vectors ()
6245 /* Align to cache line in the function's code section. */
6246 function_section (current_function_decl);
6247 ASM_OUTPUT_ALIGN (asm_out_file, 5);
6249 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
6250 sparc_output_addr_vec (XEXP (t, 0));
6251 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
6252 sparc_output_addr_diff_vec (XEXP (t, 0));
6254 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
6257 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
6258 unknown. Return 1 if the high bits are zero, -1 if the register is
6261 sparc_check_64 (x, insn)
6264 /* If a register is set only once it is safe to ignore insns this
6265 code does not know how to handle. The loop will either recognize
6266 the single set and return the correct value or fail to recognize
6270 if (GET_CODE (x) == REG
6271 && flag_expensive_optimizations
6272 && REG_N_SETS (REGNO (x)) == 1)
6278 insn = get_last_insn_anywhere ();
6283 while ((insn = PREV_INSN (insn)))
6285 switch (GET_CODE (insn))
6298 rtx pat = PATTERN (insn);
6299 if (GET_CODE (pat) != SET)
6301 if (rtx_equal_p (x, SET_DEST (pat)))
6302 return set_extends (x, insn);
6303 if (reg_overlap_mentioned_p (SET_DEST (pat), x))
6312 sparc_v8plus_shift (operands, insn, opcode)
6317 static char asm_code[60];
6319 if (GET_CODE (operands[3]) == SCRATCH)
6320 operands[3] = operands[0];
6321 if (GET_CODE (operands[1]) == CONST_INT)
6323 output_asm_insn ("mov %1,%3", operands);
6327 output_asm_insn ("sllx %H1,32,%3", operands);
6328 if (sparc_check_64 (operands[1], insn) <= 0)
6329 output_asm_insn ("srl %L1,0,%L1", operands);
6330 output_asm_insn ("or %L1,%3,%3", operands);
6333 strcpy(asm_code, opcode);
6334 if (which_alternative != 2)
6335 return strcat (asm_code, " %0,%2,%L0\n\tsrlx %L0,32,%H0");
6337 return strcat (asm_code, " %3,%2,%3\n\tsrlx %3,32,%H0\n\tmov %3,%L0");
6341 /* Return 1 if DEST and SRC reference only global and in registers. */
6344 sparc_return_peephole_ok (dest, src)
6351 if (GET_CODE (src) != CONST_INT
6352 && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src)))
6354 return IN_OR_GLOBAL_P (dest);