1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92-98, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
44 /* 1 if the caller has placed an "unimp" insn immediately after the call.
45 This is used in v8 code when calling a function that returns a structure.
46 v9 doesn't have this. Be careful to have this test be the same as that
49 #define SKIP_CALLERS_UNIMP_P \
50 (!TARGET_ARCH64 && current_function_returns_struct \
51 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
52 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
55 /* Global variables for machine-dependent things. */
57 /* Size of frame. Need to know this to emit return insns from leaf procedures.
58 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
59 reload pass. This is important as the value is later used in insn
60 scheduling (to see what can go in a delay slot).
61 APPARENT_FSIZE is the size of the stack less the register save area and less
62 the outgoing argument area. It is used when saving call preserved regs. */
63 static int apparent_fsize;
64 static int actual_fsize;
66 /* Number of live general or floating point registers needed to be saved
67 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
68 static int num_gfregs;
70 /* Save the operands last given to a compare for use when we
71 generate a scc or bcc insn. */
73 rtx sparc_compare_op0, sparc_compare_op1;
75 /* We may need an epilogue if we spill too many registers.
76 If this is non-zero, then we branch here for the epilogue. */
77 static rtx leaf_label;
81 /* Vector to say how input registers are mapped to output
82 registers. FRAME_POINTER_REGNUM cannot be remapped by
83 this function to eliminate it. You must use -fomit-frame-pointer
85 char leaf_reg_remap[] =
86 { 0, 1, 2, 3, 4, 5, 6, 7,
87 -1, -1, -1, -1, -1, -1, 14, -1,
88 -1, -1, -1, -1, -1, -1, -1, -1,
89 8, 9, 10, 11, 12, 13, -1, 15,
91 32, 33, 34, 35, 36, 37, 38, 39,
92 40, 41, 42, 43, 44, 45, 46, 47,
93 48, 49, 50, 51, 52, 53, 54, 55,
94 56, 57, 58, 59, 60, 61, 62, 63,
95 64, 65, 66, 67, 68, 69, 70, 71,
96 72, 73, 74, 75, 76, 77, 78, 79,
97 80, 81, 82, 83, 84, 85, 86, 87,
98 88, 89, 90, 91, 92, 93, 94, 95,
103 /* Name of where we pretend to think the frame pointer points.
104 Normally, this is "%fp", but if we are in a leaf procedure,
105 this is "%sp+something". We record "something" separately as it may be
106 too big for reg+constant addressing. */
108 static const char *frame_base_name;
109 static int frame_base_offset;
111 static rtx pic_setup_code PARAMS ((void));
112 static void sparc_init_modes PARAMS ((void));
113 static int save_regs PARAMS ((FILE *, int, int, const char *,
115 static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int));
116 static void build_big_number PARAMS ((FILE *, int, const char *));
117 static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *,
118 enum machine_mode, tree, int, int,
121 static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
122 static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
123 static int ultrasparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
125 static void sparc_output_addr_vec PARAMS ((rtx));
126 static void sparc_output_addr_diff_vec PARAMS ((rtx));
127 static void sparc_output_deferred_case_vectors PARAMS ((void));
128 static void sparc_add_gc_roots PARAMS ((void));
129 static void mark_ultrasparc_pipeline_state PARAMS ((void *));
130 static int check_return_regs PARAMS ((rtx));
131 static int epilogue_renumber PARAMS ((rtx *, int));
132 static int ultra_cmove_results_ready_p PARAMS ((rtx));
133 static int ultra_fpmode_conflict_exists PARAMS ((enum machine_mode));
134 static rtx *ultra_find_type PARAMS ((int, rtx *, int));
135 static void ultra_build_types_avail PARAMS ((rtx *, int));
136 static void ultra_flush_pipeline PARAMS ((void));
137 static void ultra_rescan_pipeline_state PARAMS ((rtx *, int));
138 static int set_extends PARAMS ((rtx, rtx));
140 /* Option handling. */
142 /* Code model option as passed by user. */
143 const char *sparc_cmodel_string;
145 enum cmodel sparc_cmodel;
147 char sparc_hard_reg_printed[8];
149 struct sparc_cpu_select sparc_select[] =
151 /* switch name, tune arch */
152 { (char *)0, "default", 1, 1 },
153 { (char *)0, "-mcpu=", 1, 1 },
154 { (char *)0, "-mtune=", 1, 0 },
158 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
159 enum processor_type sparc_cpu;
161 /* Validate and override various options, and do some machine dependent
165 sparc_override_options ()
167 static struct code_model {
172 { "medlow", CM_MEDLOW },
173 { "medmid", CM_MEDMID },
174 { "medany", CM_MEDANY },
175 { "embmedany", CM_EMBMEDANY },
178 struct code_model *cmodel;
179 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
180 static struct cpu_default {
184 /* There must be one entry here for each TARGET_CPU value. */
185 { TARGET_CPU_sparc, "cypress" },
186 { TARGET_CPU_sparclet, "tsc701" },
187 { TARGET_CPU_sparclite, "f930" },
188 { TARGET_CPU_v8, "v8" },
189 { TARGET_CPU_hypersparc, "hypersparc" },
190 { TARGET_CPU_sparclite86x, "sparclite86x" },
191 { TARGET_CPU_supersparc, "supersparc" },
192 { TARGET_CPU_v9, "v9" },
193 { TARGET_CPU_ultrasparc, "ultrasparc" },
196 struct cpu_default *def;
197 /* Table of values for -m{cpu,tune}=. */
198 static struct cpu_table {
200 enum processor_type processor;
204 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
205 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
206 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
207 /* TI TMS390Z55 supersparc */
208 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
209 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
210 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
211 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
212 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
213 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
214 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
215 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
217 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
219 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
220 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
221 /* TI ultrasparc I, II, IIi */
222 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
223 /* Although insns using %y are deprecated, it is a clear win on current
225 |MASK_DEPRECATED_V8_INSNS },
228 struct cpu_table *cpu;
229 struct sparc_cpu_select *sel;
232 #ifndef SPARC_BI_ARCH
233 /* Check for unsupported architecture size. */
234 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
236 error ("%s is not supported by this configuration",
237 DEFAULT_ARCH32_P ? "-m64" : "-m32");
241 /* At the moment we don't allow different pointer size and architecture */
242 if (! TARGET_64BIT != ! TARGET_PTR64)
244 error ("-mptr%d not allowed on -m%d",
245 TARGET_PTR64 ? 64 : 32, TARGET_64BIT ? 64 : 32);
247 target_flags |= MASK_PTR64;
249 target_flags &= ~MASK_PTR64;
252 /* Code model selection. */
253 sparc_cmodel = SPARC_DEFAULT_CMODEL;
257 sparc_cmodel = CM_32;
260 if (sparc_cmodel_string != NULL)
264 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
265 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
267 if (cmodel->name == NULL)
268 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
270 sparc_cmodel = cmodel->value;
273 error ("-mcmodel= is not supported on 32 bit systems");
276 fpu = TARGET_FPU; /* save current -mfpu status */
278 /* Set the default CPU. */
279 for (def = &cpu_default[0]; def->name; ++def)
280 if (def->cpu == TARGET_CPU_DEFAULT)
284 sparc_select[0].string = def->name;
286 for (sel = &sparc_select[0]; sel->name; ++sel)
290 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
291 if (! strcmp (sel->string, cpu->name))
294 sparc_cpu = cpu->processor;
298 target_flags &= ~cpu->disable;
299 target_flags |= cpu->enable;
305 error ("bad value (%s) for %s switch", sel->string, sel->name);
309 /* If -mfpu or -mno-fpu was explicitly used, don't override with
310 the processor default. Clear MASK_FPU_SET to avoid confusing
311 the reverse mapping from switch values to names. */
314 target_flags = (target_flags & ~MASK_FPU) | fpu;
315 target_flags &= ~MASK_FPU_SET;
318 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
319 if (TARGET_V9 && TARGET_ARCH32)
320 target_flags |= MASK_DEPRECATED_V8_INSNS;
322 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
323 if (! TARGET_V9 || TARGET_ARCH64)
324 target_flags &= ~MASK_V8PLUS;
326 /* Don't use stack biasing in 32 bit mode. */
328 target_flags &= ~MASK_STACK_BIAS;
330 /* Don't allow -mvis if FPU is disabled. */
332 target_flags &= ~MASK_VIS;
334 /* Supply a default value for align_functions. */
335 if (align_functions == 0 && sparc_cpu == PROCESSOR_ULTRASPARC)
336 align_functions = 32;
338 /* Validate PCC_STRUCT_RETURN. */
339 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
340 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
342 /* Do various machine dependent initializations. */
345 if ((profile_flag || profile_block_flag)
346 && sparc_cmodel != CM_32 && sparc_cmodel != CM_MEDLOW)
348 error ("profiling does not support code models other than medlow");
351 /* Register global variables with the garbage collector. */
352 sparc_add_gc_roots ();
355 /* Miscellaneous utilities. */
357 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
358 or branch on register contents instructions. */
364 return (code == EQ || code == NE || code == GE || code == LT
365 || code == LE || code == GT);
369 /* Operand constraints. */
371 /* Return non-zero only if OP is a register of mode MODE,
372 or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because
373 %g0 may contain anything. */
376 reg_or_0_operand (op, mode)
378 enum machine_mode mode;
380 if (register_operand (op, mode))
384 if (op == const0_rtx)
386 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
387 && CONST_DOUBLE_HIGH (op) == 0
388 && CONST_DOUBLE_LOW (op) == 0)
390 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
391 && GET_CODE (op) == CONST_DOUBLE
392 && fp_zero_operand (op))
397 /* Nonzero if OP is a floating point value with value 0.0. */
405 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
406 return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r));
409 /* Nonzero if OP is a floating point constant which can
410 be loaded into an integer register using a single
411 sethi instruction. */
417 if (GET_CODE (op) == CONST_DOUBLE)
422 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
423 if (REAL_VALUES_EQUAL (r, dconst0) &&
424 ! REAL_VALUE_MINUS_ZERO (r))
426 REAL_VALUE_TO_TARGET_SINGLE (r, i);
427 if (SPARC_SETHI_P (i))
434 /* Nonzero if OP is a floating point constant which can
435 be loaded into an integer register using a single
442 if (GET_CODE (op) == CONST_DOUBLE)
447 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
448 if (REAL_VALUES_EQUAL (r, dconst0) &&
449 ! REAL_VALUE_MINUS_ZERO (r))
451 REAL_VALUE_TO_TARGET_SINGLE (r, i);
452 if (SPARC_SIMM13_P (i))
459 /* Nonzero if OP is a floating point constant which can
460 be loaded into an integer register using a high/losum
461 instruction sequence. */
467 /* The constraints calling this should only be in
468 SFmode move insns, so any constant which cannot
469 be moved using a single insn will do. */
470 if (GET_CODE (op) == CONST_DOUBLE)
475 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
476 if (REAL_VALUES_EQUAL (r, dconst0) &&
477 ! REAL_VALUE_MINUS_ZERO (r))
479 REAL_VALUE_TO_TARGET_SINGLE (r, i);
480 if (! SPARC_SETHI_P (i)
481 && ! SPARC_SIMM13_P (i))
488 /* Nonzero if OP is an integer register. */
491 intreg_operand (op, mode)
493 enum machine_mode mode ATTRIBUTE_UNUSED;
495 return (register_operand (op, SImode)
496 || (TARGET_ARCH64 && register_operand (op, DImode)));
499 /* Nonzero if OP is a floating point condition code register. */
502 fcc_reg_operand (op, mode)
504 enum machine_mode mode;
506 /* This can happen when recog is called from combine. Op may be a MEM.
507 Fail instead of calling abort in this case. */
508 if (GET_CODE (op) != REG)
511 if (mode != VOIDmode && mode != GET_MODE (op))
514 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
517 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
518 if (reg_renumber == 0)
519 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
520 return REGNO_OK_FOR_CCFP_P (REGNO (op));
522 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
526 /* Nonzero if OP is an integer or floating point condition code register. */
529 icc_or_fcc_reg_operand (op, mode)
531 enum machine_mode mode;
533 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
535 if (mode != VOIDmode && mode != GET_MODE (op))
538 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
543 return fcc_reg_operand (op, mode);
546 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
548 restore_operand (op, mode)
550 enum machine_mode mode;
552 return (GET_CODE (op) == REG && GET_MODE (op) == mode
553 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
556 /* Call insn on SPARC can take a PC-relative constant address, or any regular
560 call_operand (op, mode)
562 enum machine_mode mode;
564 if (GET_CODE (op) != MEM)
567 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
571 call_operand_address (op, mode)
573 enum machine_mode mode;
575 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
578 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
579 reference and a constant. */
582 symbolic_operand (op, mode)
584 enum machine_mode mode;
586 enum machine_mode omode = GET_MODE (op);
588 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
591 switch (GET_CODE (op))
599 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
600 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
601 && GET_CODE (XEXP (op, 1)) == CONST_INT);
608 /* Return truth value of statement that OP is a symbolic memory
609 operand of mode MODE. */
612 symbolic_memory_operand (op, mode)
614 enum machine_mode mode ATTRIBUTE_UNUSED;
616 if (GET_CODE (op) == SUBREG)
617 op = SUBREG_REG (op);
618 if (GET_CODE (op) != MEM)
621 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
622 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
625 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
628 label_ref_operand (op, mode)
630 enum machine_mode mode;
632 if (GET_CODE (op) != LABEL_REF)
634 if (GET_MODE (op) != mode)
639 /* Return 1 if the operand is an argument used in generating pic references
640 in either the medium/low or medium/anywhere code models of sparc64. */
643 sp64_medium_pic_operand (op, mode)
645 enum machine_mode mode ATTRIBUTE_UNUSED;
647 /* Check for (const (minus (symbol_ref:GOT)
648 (const (minus (label) (pc))))). */
649 if (GET_CODE (op) != CONST)
652 if (GET_CODE (op) != MINUS)
654 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
656 /* ??? Ensure symbol is GOT. */
657 if (GET_CODE (XEXP (op, 1)) != CONST)
659 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
664 /* Return 1 if the operand is a data segment reference. This includes
665 the readonly data segment, or in other words anything but the text segment.
666 This is needed in the medium/anywhere code model on v9. These values
667 are accessed with EMBMEDANY_BASE_REG. */
670 data_segment_operand (op, mode)
672 enum machine_mode mode ATTRIBUTE_UNUSED;
674 switch (GET_CODE (op))
677 return ! SYMBOL_REF_FLAG (op);
679 /* Assume canonical format of symbol + constant.
682 return data_segment_operand (XEXP (op, 0), VOIDmode);
688 /* Return 1 if the operand is a text segment reference.
689 This is needed in the medium/anywhere code model on v9. */
692 text_segment_operand (op, mode)
694 enum machine_mode mode ATTRIBUTE_UNUSED;
696 switch (GET_CODE (op))
701 return SYMBOL_REF_FLAG (op);
703 /* Assume canonical format of symbol + constant.
706 return text_segment_operand (XEXP (op, 0), VOIDmode);
712 /* Return 1 if the operand is either a register or a memory operand that is
716 reg_or_nonsymb_mem_operand (op, mode)
718 enum machine_mode mode;
720 if (register_operand (op, mode))
723 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
730 splittable_symbolic_memory_operand (op, mode)
732 enum machine_mode mode ATTRIBUTE_UNUSED;
734 if (GET_CODE (op) != MEM)
736 if (! symbolic_operand (XEXP (op, 0), Pmode))
742 splittable_immediate_memory_operand (op, mode)
744 enum machine_mode mode ATTRIBUTE_UNUSED;
746 if (GET_CODE (op) != MEM)
748 if (! immediate_operand (XEXP (op, 0), Pmode))
753 /* Return truth value of whether OP is EQ or NE. */
758 enum machine_mode mode ATTRIBUTE_UNUSED;
760 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
763 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
764 or LTU for non-floating-point. We handle those specially. */
767 normal_comp_operator (op, mode)
769 enum machine_mode mode ATTRIBUTE_UNUSED;
771 enum rtx_code code = GET_CODE (op);
773 if (GET_RTX_CLASS (code) != '<')
776 if (GET_MODE (XEXP (op, 0)) == CCFPmode
777 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
780 return (code != NE && code != EQ && code != GEU && code != LTU);
783 /* Return 1 if this is a comparison operator. This allows the use of
784 MATCH_OPERATOR to recognize all the branch insns. */
787 noov_compare_op (op, mode)
789 enum machine_mode mode ATTRIBUTE_UNUSED;
791 enum rtx_code code = GET_CODE (op);
793 if (GET_RTX_CLASS (code) != '<')
796 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
797 /* These are the only branches which work with CC_NOOVmode. */
798 return (code == EQ || code == NE || code == GE || code == LT);
802 /* Nonzero if OP is a comparison operator suitable for use in v9
803 conditional move or branch on register contents instructions. */
806 v9_regcmp_op (op, mode)
808 enum machine_mode mode ATTRIBUTE_UNUSED;
810 enum rtx_code code = GET_CODE (op);
812 if (GET_RTX_CLASS (code) != '<')
815 return v9_regcmp_p (code);
818 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
823 enum machine_mode mode ATTRIBUTE_UNUSED;
825 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
828 /* Return nonzero if OP is an operator of mode MODE which can set
829 the condition codes explicitly. We do not include PLUS and MINUS
830 because these require CC_NOOVmode, which we handle explicitly. */
833 cc_arithop (op, mode)
835 enum machine_mode mode ATTRIBUTE_UNUSED;
837 if (GET_CODE (op) == AND
838 || GET_CODE (op) == IOR
839 || GET_CODE (op) == XOR)
845 /* Return nonzero if OP is an operator of mode MODE which can bitwise
846 complement its second operand and set the condition codes explicitly. */
849 cc_arithopn (op, mode)
851 enum machine_mode mode ATTRIBUTE_UNUSED;
853 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
854 and (xor ... (not ...)) to (not (xor ...)). */
855 return (GET_CODE (op) == AND
856 || GET_CODE (op) == IOR);
859 /* Return true if OP is a register, or is a CONST_INT that can fit in a
860 signed 13 bit immediate field. This is an acceptable SImode operand for
861 most 3 address instructions. */
864 arith_operand (op, mode)
866 enum machine_mode mode;
869 if (register_operand (op, mode))
871 if (GET_CODE (op) != CONST_INT)
873 val = INTVAL (op) & 0xffffffff;
874 return SPARC_SIMM13_P (val);
877 /* Return true if OP is a constant 4096 */
880 arith_4096_operand (op, mode)
882 enum machine_mode mode ATTRIBUTE_UNUSED;
885 if (GET_CODE (op) != CONST_INT)
887 val = INTVAL (op) & 0xffffffff;
891 /* Return true if OP is suitable as second operand for add/sub */
894 arith_add_operand (op, mode)
896 enum machine_mode mode;
898 return arith_operand (op, mode) || arith_4096_operand (op, mode);
901 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
902 immediate field of OR and XOR instructions. Used for 64-bit
903 constant formation patterns. */
905 const64_operand (op, mode)
907 enum machine_mode mode ATTRIBUTE_UNUSED;
909 return ((GET_CODE (op) == CONST_INT
910 && SPARC_SIMM13_P (INTVAL (op)))
911 #if HOST_BITS_PER_WIDE_INT != 64
912 || (GET_CODE (op) == CONST_DOUBLE
913 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
914 && (CONST_DOUBLE_HIGH (op) ==
915 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
916 (HOST_WIDE_INT)0xffffffff : 0)))
921 /* The same, but only for sethi instructions. */
923 const64_high_operand (op, mode)
925 enum machine_mode mode ATTRIBUTE_UNUSED;
927 return ((GET_CODE (op) == CONST_INT
928 && (INTVAL (op) & 0xfffffc00) != 0
929 && SPARC_SETHI_P (INTVAL (op))
930 #if HOST_BITS_PER_WIDE_INT != 64
931 /* Must be positive on non-64bit host else the
932 optimizer is fooled into thinking that sethi
933 sign extends, even though it does not. */
937 || (GET_CODE (op) == CONST_DOUBLE
938 && CONST_DOUBLE_HIGH (op) == 0
939 && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
940 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
943 /* Return true if OP is a register, or is a CONST_INT that can fit in a
944 signed 11 bit immediate field. This is an acceptable SImode operand for
945 the movcc instructions. */
948 arith11_operand (op, mode)
950 enum machine_mode mode;
952 return (register_operand (op, mode)
953 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
956 /* Return true if OP is a register, or is a CONST_INT that can fit in a
957 signed 10 bit immediate field. This is an acceptable SImode operand for
958 the movrcc instructions. */
961 arith10_operand (op, mode)
963 enum machine_mode mode;
965 return (register_operand (op, mode)
966 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
969 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
970 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
972 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
973 can fit in a 13 bit immediate field. This is an acceptable DImode operand
974 for most 3 address instructions. */
977 arith_double_operand (op, mode)
979 enum machine_mode mode;
981 return (register_operand (op, mode)
982 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
984 && GET_CODE (op) == CONST_DOUBLE
985 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
986 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
988 && GET_CODE (op) == CONST_DOUBLE
989 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
990 && ((CONST_DOUBLE_HIGH (op) == -1
991 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
992 || (CONST_DOUBLE_HIGH (op) == 0
993 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
996 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
999 arith_double_4096_operand (op, mode)
1001 enum machine_mode mode ATTRIBUTE_UNUSED;
1003 return (TARGET_ARCH64 &&
1004 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1005 (GET_CODE (op) == CONST_DOUBLE &&
1006 CONST_DOUBLE_LOW (op) == 4096 &&
1007 CONST_DOUBLE_HIGH (op) == 0)));
1010 /* Return true if OP is suitable as second operand for add/sub in DImode */
1013 arith_double_add_operand (op, mode)
1015 enum machine_mode mode;
1017 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1020 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1021 can fit in an 11 bit immediate field. This is an acceptable DImode
1022 operand for the movcc instructions. */
1023 /* ??? Replace with arith11_operand? */
1026 arith11_double_operand (op, mode)
1028 enum machine_mode mode;
1030 return (register_operand (op, mode)
1031 || (GET_CODE (op) == CONST_DOUBLE
1032 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1033 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1034 && ((CONST_DOUBLE_HIGH (op) == -1
1035 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1036 || (CONST_DOUBLE_HIGH (op) == 0
1037 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1038 || (GET_CODE (op) == CONST_INT
1039 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1040 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1043 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1044 can fit in an 10 bit immediate field. This is an acceptable DImode
1045 operand for the movrcc instructions. */
1046 /* ??? Replace with arith10_operand? */
1049 arith10_double_operand (op, mode)
1051 enum machine_mode mode;
1053 return (register_operand (op, mode)
1054 || (GET_CODE (op) == CONST_DOUBLE
1055 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1056 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1057 && ((CONST_DOUBLE_HIGH (op) == -1
1058 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1059 || (CONST_DOUBLE_HIGH (op) == 0
1060 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1061 || (GET_CODE (op) == CONST_INT
1062 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1063 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1066 /* Return truth value of whether OP is a integer which fits the
1067 range constraining immediate operands in most three-address insns,
1068 which have a 13 bit immediate field. */
1071 small_int (op, mode)
1073 enum machine_mode mode ATTRIBUTE_UNUSED;
1075 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1079 small_int_or_double (op, mode)
1081 enum machine_mode mode ATTRIBUTE_UNUSED;
1083 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1084 || (GET_CODE (op) == CONST_DOUBLE
1085 && CONST_DOUBLE_HIGH (op) == 0
1086 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1089 /* Recognize operand values for the umul instruction. That instruction sign
1090 extends immediate values just like all other sparc instructions, but
1091 interprets the extended result as an unsigned number. */
1094 uns_small_int (op, mode)
1096 enum machine_mode mode ATTRIBUTE_UNUSED;
1098 #if HOST_BITS_PER_WIDE_INT > 32
1099 /* All allowed constants will fit a CONST_INT. */
1100 return (GET_CODE (op) == CONST_INT
1101 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1102 || (INTVAL (op) >= 0xFFFFF000
1103 && INTVAL (op) < 0x100000000)));
1105 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1106 || (GET_CODE (op) == CONST_DOUBLE
1107 && CONST_DOUBLE_HIGH (op) == 0
1108 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1113 uns_arith_operand (op, mode)
1115 enum machine_mode mode;
1117 return register_operand (op, mode) || uns_small_int (op, mode);
1120 /* Return truth value of statement that OP is a call-clobbered register. */
1122 clobbered_register (op, mode)
1124 enum machine_mode mode ATTRIBUTE_UNUSED;
1126 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1129 /* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns. */
1132 zero_operand (op, mode)
1134 enum machine_mode mode ATTRIBUTE_UNUSED;
1136 return op == const0_rtx;
1139 /* Return 1 if OP is a valid operand for the source of a move insn. */
1142 input_operand (op, mode)
1144 enum machine_mode mode;
1146 /* If both modes are non-void they must be the same. */
1147 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1150 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1151 if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX)
1154 /* Allow any one instruction integer constant, and all CONST_INT
1155 variants when we are working in DImode and !arch64. */
1156 if (GET_MODE_CLASS (mode) == MODE_INT
1157 && ((GET_CODE (op) == CONST_INT
1158 && ((SPARC_SETHI_P (INTVAL (op))
1160 || (INTVAL (op) >= 0)
1164 || SPARC_SIMM13_P (INTVAL (op))
1166 && ! TARGET_ARCH64)))
1168 && GET_CODE (op) == CONST_DOUBLE
1169 && ((CONST_DOUBLE_HIGH (op) == 0
1170 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1172 #if HOST_BITS_PER_WIDE_INT == 64
1173 (CONST_DOUBLE_HIGH (op) == 0
1174 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1176 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1177 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1178 && CONST_DOUBLE_HIGH (op) == 0)
1179 || (CONST_DOUBLE_HIGH (op) == -1)))
1184 /* If !arch64 and this is a DImode const, allow it so that
1185 the splits can be generated. */
1188 && GET_CODE (op) == CONST_DOUBLE)
1191 if (register_operand (op, mode))
1194 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1195 && GET_CODE (op) == CONST_DOUBLE)
1198 /* If this is a SUBREG, look inside so that we handle
1199 paradoxical ones. */
1200 if (GET_CODE (op) == SUBREG)
1201 op = SUBREG_REG (op);
1203 /* Check for valid MEM forms. */
1204 if (GET_CODE (op) == MEM)
1206 rtx inside = XEXP (op, 0);
1208 if (GET_CODE (inside) == LO_SUM)
1210 /* We can't allow these because all of the splits
1211 (eventually as they trickle down into DFmode
1212 splits) require offsettable memory references. */
1214 && GET_MODE (op) == TFmode)
1217 return (register_operand (XEXP (inside, 0), Pmode)
1218 && CONSTANT_P (XEXP (inside, 1)));
1220 return memory_address_p (mode, inside);
1227 /* We know it can't be done in one insn when we get here,
1228 the movsi expander guarentees this. */
1230 sparc_emit_set_const32 (op0, op1)
1234 enum machine_mode mode = GET_MODE (op0);
1237 if (GET_CODE (op1) == CONST_INT)
1239 HOST_WIDE_INT value = INTVAL (op1);
1241 if (SPARC_SETHI_P (value)
1242 || SPARC_SIMM13_P (value))
1246 /* Full 2-insn decomposition is needed. */
1247 if (reload_in_progress || reload_completed)
1250 temp = gen_reg_rtx (mode);
1252 if (GET_CODE (op1) == CONST_INT)
1254 /* Emit them as real moves instead of a HIGH/LO_SUM,
1255 this way CSE can see everything and reuse intermediate
1256 values if it wants. */
1258 && HOST_BITS_PER_WIDE_INT != 64
1259 && (INTVAL (op1) & 0x80000000) != 0)
1261 emit_insn (gen_rtx_SET (VOIDmode,
1263 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx,
1264 INTVAL (op1) & 0xfffffc00, 0)));
1268 emit_insn (gen_rtx_SET (VOIDmode,
1270 GEN_INT (INTVAL (op1) & 0xfffffc00)));
1272 emit_insn (gen_rtx_SET (VOIDmode,
1276 GEN_INT (INTVAL (op1) & 0x3ff))));
1280 /* A symbol, emit in the traditional way. */
1281 emit_insn (gen_rtx_SET (VOIDmode,
1285 emit_insn (gen_rtx_SET (VOIDmode,
1287 gen_rtx_LO_SUM (mode,
1295 /* Sparc-v9 code-model support. */
1297 sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1302 switch (sparc_cmodel)
1305 /* The range spanned by all instructions in the object is less
1306 than 2^31 bytes (2GB) and the distance from any instruction
1307 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1308 than 2^31 bytes (2GB).
1310 The executable must be in the low 4TB of the virtual address
1313 sethi %hi(symbol), %temp
1314 or %temp, %lo(symbol), %reg */
1315 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1316 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1320 /* The range spanned by all instructions in the object is less
1321 than 2^31 bytes (2GB) and the distance from any instruction
1322 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1323 than 2^31 bytes (2GB).
1325 The executable must be in the low 16TB of the virtual address
1328 sethi %h44(symbol), %temp1
1329 or %temp1, %m44(symbol), %temp2
1330 sllx %temp2, 12, %temp3
1331 or %temp3, %l44(symbol), %reg */
1332 emit_insn (gen_seth44 (op0, op1));
1333 emit_insn (gen_setm44 (op0, op0, op1));
1334 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1335 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1336 emit_insn (gen_setl44 (op0, temp1, op1));
1340 /* The range spanned by all instructions in the object is less
1341 than 2^31 bytes (2GB) and the distance from any instruction
1342 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1343 than 2^31 bytes (2GB).
1345 The executable can be placed anywhere in the virtual address
1348 sethi %hh(symbol), %temp1
1349 sethi %lm(symbol), %temp2
1350 or %temp1, %hm(symbol), %temp3
1351 or %temp2, %lo(symbol), %temp4
1352 sllx %temp3, 32, %temp5
1353 or %temp4, %temp5, %reg */
1355 /* Getting this right wrt. reloading is really tricky.
1356 We _MUST_ have a separate temporary at this point,
1357 if we don't barf immediately instead of generating
1362 emit_insn (gen_sethh (op0, op1));
1363 emit_insn (gen_setlm (temp1, op1));
1364 emit_insn (gen_sethm (op0, op0, op1));
1365 emit_insn (gen_rtx_SET (VOIDmode, op0,
1366 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1367 emit_insn (gen_rtx_SET (VOIDmode, op0,
1368 gen_rtx_PLUS (DImode, op0, temp1)));
1369 emit_insn (gen_setlo (op0, op0, op1));
1373 /* Old old old backwards compatibility kruft here.
1374 Essentially it is MEDLOW with a fixed 64-bit
1375 virtual base added to all data segment addresses.
1376 Text-segment stuff is computed like MEDANY, we can't
1377 reuse the code above because the relocation knobs
1380 Data segment: sethi %hi(symbol), %temp1
1381 or %temp1, %lo(symbol), %temp2
1382 add %temp2, EMBMEDANY_BASE_REG, %reg
1384 Text segment: sethi %uhi(symbol), %temp1
1385 sethi %hi(symbol), %temp2
1386 or %temp1, %ulo(symbol), %temp3
1387 or %temp2, %lo(symbol), %temp4
1388 sllx %temp3, 32, %temp5
1389 or %temp4, %temp5, %reg */
1390 if (data_segment_operand (op1, GET_MODE (op1)))
1392 emit_insn (gen_embmedany_sethi (temp1, op1));
1393 emit_insn (gen_embmedany_brsum (op0, temp1));
1394 emit_insn (gen_embmedany_losum (op0, op0, op1));
1398 /* Getting this right wrt. reloading is really tricky.
1399 We _MUST_ have a separate temporary at this point,
1400 so we barf immediately instead of generating
1405 emit_insn (gen_embmedany_textuhi (op0, op1));
1406 emit_insn (gen_embmedany_texthi (temp1, op1));
1407 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1408 emit_insn (gen_rtx_SET (VOIDmode, op0,
1409 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1410 emit_insn (gen_rtx_SET (VOIDmode, op0,
1411 gen_rtx_PLUS (DImode, op0, temp1)));
1412 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1421 /* These avoid problems when cross compiling. If we do not
1422 go through all this hair then the optimizer will see
1423 invalid REG_EQUAL notes or in some cases none at all. */
1424 static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT));
1425 static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT));
1426 static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT));
1427 static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
1429 #if HOST_BITS_PER_WIDE_INT == 64
1430 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
1431 #define GEN_INT64(__x) GEN_INT (__x)
1433 #define GEN_HIGHINT64(__x) \
1434 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1435 (__x) & 0xfffffc00, 0)
1436 #define GEN_INT64(__x) \
1437 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1438 (__x) & 0xffffffff, \
1439 ((__x) & 0x80000000 \
1443 /* The optimizer is not to assume anything about exactly
1444 which bits are set for a HIGH, they are unspecified.
1445 Unfortunately this leads to many missed optimizations
1446 during CSE. We mask out the non-HIGH bits, and matches
1447 a plain movdi, to alleviate this problem. */
1449 sparc_emit_set_safe_HIGH64 (dest, val)
1453 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1457 gen_safe_SET64 (dest, val)
1461 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1465 gen_safe_OR64 (src, val)
1469 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1473 gen_safe_XOR64 (src, val)
1477 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1480 /* Worker routines for 64-bit constant formation on arch64.
1481 One of the key things to be doing in these emissions is
1482 to create as many temp REGs as possible. This makes it
1483 possible for half-built constants to be used later when
1484 such values are similar to something required later on.
1485 Without doing this, the optimizer cannot see such
1488 static void sparc_emit_set_const64_quick1
1489 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int));
1492 sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1495 unsigned HOST_WIDE_INT low_bits;
1498 unsigned HOST_WIDE_INT high_bits;
1501 high_bits = (~low_bits) & 0xffffffff;
1503 high_bits = low_bits;
1505 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1508 emit_insn (gen_rtx_SET (VOIDmode, op0,
1509 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1513 /* If we are XOR'ing with -1, then we should emit a one's complement
1514 instead. This way the combiner will notice logical operations
1515 such as ANDN later on and substitute. */
1516 if ((low_bits & 0x3ff) == 0x3ff)
1518 emit_insn (gen_rtx_SET (VOIDmode, op0,
1519 gen_rtx_NOT (DImode, temp)));
1523 emit_insn (gen_rtx_SET (VOIDmode, op0,
1524 gen_safe_XOR64 (temp,
1525 (-0x400 | (low_bits & 0x3ff)))));
1530 static void sparc_emit_set_const64_quick2
1531 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT,
1532 unsigned HOST_WIDE_INT, int));
1535 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1538 unsigned HOST_WIDE_INT high_bits;
1539 unsigned HOST_WIDE_INT low_immediate;
1544 if ((high_bits & 0xfffffc00) != 0)
1546 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1547 if ((high_bits & ~0xfffffc00) != 0)
1548 emit_insn (gen_rtx_SET (VOIDmode, op0,
1549 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1555 emit_insn (gen_safe_SET64 (temp, high_bits));
1559 /* Now shift it up into place. */
1560 emit_insn (gen_rtx_SET (VOIDmode, op0,
1561 gen_rtx_ASHIFT (DImode, temp2,
1562 GEN_INT (shift_count))));
1564 /* If there is a low immediate part piece, finish up by
1565 putting that in as well. */
1566 if (low_immediate != 0)
1567 emit_insn (gen_rtx_SET (VOIDmode, op0,
1568 gen_safe_OR64 (op0, low_immediate)));
1571 static void sparc_emit_set_const64_longway
1572 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1574 /* Full 64-bit constant decomposition. Even though this is the
1575 'worst' case, we still optimize a few things away. */
1577 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1580 unsigned HOST_WIDE_INT high_bits;
1581 unsigned HOST_WIDE_INT low_bits;
1585 if (reload_in_progress || reload_completed)
1588 sub_temp = gen_reg_rtx (DImode);
1590 if ((high_bits & 0xfffffc00) != 0)
1592 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1593 if ((high_bits & ~0xfffffc00) != 0)
1594 emit_insn (gen_rtx_SET (VOIDmode,
1596 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1602 emit_insn (gen_safe_SET64 (temp, high_bits));
1606 if (!reload_in_progress && !reload_completed)
1608 rtx temp2 = gen_reg_rtx (DImode);
1609 rtx temp3 = gen_reg_rtx (DImode);
1610 rtx temp4 = gen_reg_rtx (DImode);
1612 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1613 gen_rtx_ASHIFT (DImode, sub_temp,
1616 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1617 if ((low_bits & ~0xfffffc00) != 0)
1619 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1620 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1621 emit_insn (gen_rtx_SET (VOIDmode, op0,
1622 gen_rtx_PLUS (DImode, temp4, temp3)));
1626 emit_insn (gen_rtx_SET (VOIDmode, op0,
1627 gen_rtx_PLUS (DImode, temp4, temp2)));
1632 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1633 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1634 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1637 /* We are in the middle of reload, so this is really
1638 painful. However we do still make an attempt to
1639 avoid emitting truly stupid code. */
1640 if (low1 != const0_rtx)
1642 emit_insn (gen_rtx_SET (VOIDmode, op0,
1643 gen_rtx_ASHIFT (DImode, sub_temp,
1644 GEN_INT (to_shift))));
1645 emit_insn (gen_rtx_SET (VOIDmode, op0,
1646 gen_rtx_IOR (DImode, op0, low1)));
1654 if (low2 != const0_rtx)
1656 emit_insn (gen_rtx_SET (VOIDmode, op0,
1657 gen_rtx_ASHIFT (DImode, sub_temp,
1658 GEN_INT (to_shift))));
1659 emit_insn (gen_rtx_SET (VOIDmode, op0,
1660 gen_rtx_IOR (DImode, op0, low2)));
1668 emit_insn (gen_rtx_SET (VOIDmode, op0,
1669 gen_rtx_ASHIFT (DImode, sub_temp,
1670 GEN_INT (to_shift))));
1671 if (low3 != const0_rtx)
1672 emit_insn (gen_rtx_SET (VOIDmode, op0,
1673 gen_rtx_IOR (DImode, op0, low3)));
1678 /* Analyze a 64-bit constant for certain properties. */
1679 static void analyze_64bit_constant
1680 PARAMS ((unsigned HOST_WIDE_INT,
1681 unsigned HOST_WIDE_INT,
1682 int *, int *, int *));
1685 analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
1686 unsigned HOST_WIDE_INT high_bits, low_bits;
1687 int *hbsp, *lbsp, *abbasp;
1689 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1692 lowest_bit_set = highest_bit_set = -1;
1696 if ((lowest_bit_set == -1)
1697 && ((low_bits >> i) & 1))
1699 if ((highest_bit_set == -1)
1700 && ((high_bits >> (32 - i - 1)) & 1))
1701 highest_bit_set = (64 - i - 1);
1704 && ((highest_bit_set == -1)
1705 || (lowest_bit_set == -1)));
1711 if ((lowest_bit_set == -1)
1712 && ((high_bits >> i) & 1))
1713 lowest_bit_set = i + 32;
1714 if ((highest_bit_set == -1)
1715 && ((low_bits >> (32 - i - 1)) & 1))
1716 highest_bit_set = 32 - i - 1;
1719 && ((highest_bit_set == -1)
1720 || (lowest_bit_set == -1)));
1722 /* If there are no bits set this should have gone out
1723 as one instruction! */
1724 if (lowest_bit_set == -1
1725 || highest_bit_set == -1)
1727 all_bits_between_are_set = 1;
1728 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1732 if ((low_bits & (1 << i)) != 0)
1737 if ((high_bits & (1 << (i - 32))) != 0)
1740 all_bits_between_are_set = 0;
1743 *hbsp = highest_bit_set;
1744 *lbsp = lowest_bit_set;
1745 *abbasp = all_bits_between_are_set;
1748 static int const64_is_2insns
1749 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1752 const64_is_2insns (high_bits, low_bits)
1753 unsigned HOST_WIDE_INT high_bits, low_bits;
1755 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1758 || high_bits == 0xffffffff)
1761 analyze_64bit_constant (high_bits, low_bits,
1762 &highest_bit_set, &lowest_bit_set,
1763 &all_bits_between_are_set);
1765 if ((highest_bit_set == 63
1766 || lowest_bit_set == 0)
1767 && all_bits_between_are_set != 0)
1770 if ((highest_bit_set - lowest_bit_set) < 21)
1776 static unsigned HOST_WIDE_INT create_simple_focus_bits
1777 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
1780 static unsigned HOST_WIDE_INT
1781 create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
1782 unsigned HOST_WIDE_INT high_bits, low_bits;
1783 int lowest_bit_set, shift;
1785 HOST_WIDE_INT hi, lo;
1787 if (lowest_bit_set < 32)
1789 lo = (low_bits >> lowest_bit_set) << shift;
1790 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1795 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1802 /* Here we are sure to be arch64 and this is an integer constant
1803 being loaded into a register. Emit the most efficient
1804 insn sequence possible. Detection of all the 1-insn cases
1805 has been done already. */
1807 sparc_emit_set_const64 (op0, op1)
1811 unsigned HOST_WIDE_INT high_bits, low_bits;
1812 int lowest_bit_set, highest_bit_set;
1813 int all_bits_between_are_set;
1816 /* Sanity check that we know what we are working with. */
1818 || GET_CODE (op0) != REG
1819 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1820 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1823 if (reload_in_progress || reload_completed)
1826 temp = gen_reg_rtx (DImode);
1828 if (GET_CODE (op1) != CONST_DOUBLE
1829 && GET_CODE (op1) != CONST_INT)
1831 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1835 if (GET_CODE (op1) == CONST_DOUBLE)
1837 #if HOST_BITS_PER_WIDE_INT == 64
1838 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1839 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1841 high_bits = CONST_DOUBLE_HIGH (op1);
1842 low_bits = CONST_DOUBLE_LOW (op1);
1847 #if HOST_BITS_PER_WIDE_INT == 64
1848 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1849 low_bits = (INTVAL (op1) & 0xffffffff);
1851 high_bits = ((INTVAL (op1) < 0) ?
1854 low_bits = INTVAL (op1);
1858 /* low_bits bits 0 --> 31
1859 high_bits bits 32 --> 63 */
1861 analyze_64bit_constant (high_bits, low_bits,
1862 &highest_bit_set, &lowest_bit_set,
1863 &all_bits_between_are_set);
1865 /* First try for a 2-insn sequence. */
1867 /* These situations are preferred because the optimizer can
1868 * do more things with them:
1870 * sllx %reg, shift, %reg
1872 * srlx %reg, shift, %reg
1873 * 3) mov some_small_const, %reg
1874 * sllx %reg, shift, %reg
1876 if (((highest_bit_set == 63
1877 || lowest_bit_set == 0)
1878 && all_bits_between_are_set != 0)
1879 || ((highest_bit_set - lowest_bit_set) < 12))
1881 HOST_WIDE_INT the_const = -1;
1882 int shift = lowest_bit_set;
1884 if ((highest_bit_set != 63
1885 && lowest_bit_set != 0)
1886 || all_bits_between_are_set == 0)
1889 create_simple_focus_bits (high_bits, low_bits,
1892 else if (lowest_bit_set == 0)
1893 shift = -(63 - highest_bit_set);
1895 if (! SPARC_SIMM13_P (the_const))
1898 emit_insn (gen_safe_SET64 (temp, the_const));
1900 emit_insn (gen_rtx_SET (VOIDmode,
1902 gen_rtx_ASHIFT (DImode,
1906 emit_insn (gen_rtx_SET (VOIDmode,
1908 gen_rtx_LSHIFTRT (DImode,
1910 GEN_INT (-shift))));
1916 /* Now a range of 22 or less bits set somewhere.
1917 * 1) sethi %hi(focus_bits), %reg
1918 * sllx %reg, shift, %reg
1919 * 2) sethi %hi(focus_bits), %reg
1920 * srlx %reg, shift, %reg
1922 if ((highest_bit_set - lowest_bit_set) < 21)
1924 unsigned HOST_WIDE_INT focus_bits =
1925 create_simple_focus_bits (high_bits, low_bits,
1926 lowest_bit_set, 10);
1928 if (! SPARC_SETHI_P (focus_bits))
1931 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
1933 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1934 if (lowest_bit_set < 10)
1935 emit_insn (gen_rtx_SET (VOIDmode,
1937 gen_rtx_LSHIFTRT (DImode, temp,
1938 GEN_INT (10 - lowest_bit_set))));
1939 else if (lowest_bit_set > 10)
1940 emit_insn (gen_rtx_SET (VOIDmode,
1942 gen_rtx_ASHIFT (DImode, temp,
1943 GEN_INT (lowest_bit_set - 10))));
1949 /* 1) sethi %hi(low_bits), %reg
1950 * or %reg, %lo(low_bits), %reg
1951 * 2) sethi %hi(~low_bits), %reg
1952 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1955 || high_bits == 0xffffffff)
1957 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1958 (high_bits == 0xffffffff));
1962 /* Now, try 3-insn sequences. */
1964 /* 1) sethi %hi(high_bits), %reg
1965 * or %reg, %lo(high_bits), %reg
1966 * sllx %reg, 32, %reg
1970 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
1974 /* We may be able to do something quick
1975 when the constant is negated, so try that. */
1976 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1977 (~low_bits) & 0xfffffc00))
1979 /* NOTE: The trailing bits get XOR'd so we need the
1980 non-negated bits, not the negated ones. */
1981 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
1983 if ((((~high_bits) & 0xffffffff) == 0
1984 && ((~low_bits) & 0x80000000) == 0)
1985 || (((~high_bits) & 0xffffffff) == 0xffffffff
1986 && ((~low_bits) & 0x80000000) != 0))
1988 int fast_int = (~low_bits & 0xffffffff);
1990 if ((SPARC_SETHI_P (fast_int)
1991 && (~high_bits & 0xffffffff) == 0)
1992 || SPARC_SIMM13_P (fast_int))
1993 emit_insn (gen_safe_SET64 (temp, fast_int));
1995 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2000 #if HOST_BITS_PER_WIDE_INT == 64
2001 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2002 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2004 negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx,
2005 (~low_bits) & 0xfffffc00,
2006 (~high_bits) & 0xffffffff);
2008 sparc_emit_set_const64 (temp, negated_const);
2011 /* If we are XOR'ing with -1, then we should emit a one's complement
2012 instead. This way the combiner will notice logical operations
2013 such as ANDN later on and substitute. */
2014 if (trailing_bits == 0x3ff)
2016 emit_insn (gen_rtx_SET (VOIDmode, op0,
2017 gen_rtx_NOT (DImode, temp)));
2021 emit_insn (gen_rtx_SET (VOIDmode,
2023 gen_safe_XOR64 (temp,
2024 (-0x400 | trailing_bits))));
2029 /* 1) sethi %hi(xxx), %reg
2030 * or %reg, %lo(xxx), %reg
2031 * sllx %reg, yyy, %reg
2033 * ??? This is just a generalized version of the low_bits==0
2034 * thing above, FIXME...
2036 if ((highest_bit_set - lowest_bit_set) < 32)
2038 unsigned HOST_WIDE_INT focus_bits =
2039 create_simple_focus_bits (high_bits, low_bits,
2042 /* We can't get here in this state. */
2043 if (highest_bit_set < 32
2044 || lowest_bit_set >= 32)
2047 /* So what we know is that the set bits straddle the
2048 middle of the 64-bit word. */
2049 sparc_emit_set_const64_quick2 (op0, temp,
2055 /* 1) sethi %hi(high_bits), %reg
2056 * or %reg, %lo(high_bits), %reg
2057 * sllx %reg, 32, %reg
2058 * or %reg, low_bits, %reg
2060 if (SPARC_SIMM13_P(low_bits)
2061 && ((int)low_bits > 0))
2063 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2067 /* The easiest way when all else fails, is full decomposition. */
2069 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2070 high_bits, low_bits, ~high_bits, ~low_bits);
2072 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2075 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2076 return the mode to be used for the comparison. For floating-point,
2077 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2078 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2079 processing is needed. */
2082 select_cc_mode (op, x, y)
2085 rtx y ATTRIBUTE_UNUSED;
2087 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2113 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2114 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2116 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2117 return CCX_NOOVmode;
2123 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2130 /* X and Y are two things to compare using CODE. Emit the compare insn and
2131 return the rtx for the cc reg in the proper mode. */
2134 gen_compare_reg (code, x, y)
2138 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2141 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2142 fcc regs (cse can't tell they're really call clobbered regs and will
2143 remove a duplicate comparison even if there is an intervening function
2144 call - it will then try to reload the cc reg via an int reg which is why
2145 we need the movcc patterns). It is possible to provide the movcc
2146 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2147 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2148 to tell cse that CCFPE mode registers (even pseudos) are call
2151 /* ??? This is an experiment. Rather than making changes to cse which may
2152 or may not be easy/clean, we do our own cse. This is possible because
2153 we will generate hard registers. Cse knows they're call clobbered (it
2154 doesn't know the same thing about pseudos). If we guess wrong, no big
2155 deal, but if we win, great! */
2157 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2158 #if 1 /* experiment */
2161 /* We cycle through the registers to ensure they're all exercised. */
2162 static int next_fcc_reg = 0;
2163 /* Previous x,y for each fcc reg. */
2164 static rtx prev_args[4][2];
2166 /* Scan prev_args for x,y. */
2167 for (reg = 0; reg < 4; reg++)
2168 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2173 prev_args[reg][0] = x;
2174 prev_args[reg][1] = y;
2175 next_fcc_reg = (next_fcc_reg + 1) & 3;
2177 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2180 cc_reg = gen_reg_rtx (mode);
2181 #endif /* ! experiment */
2182 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2183 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2185 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2187 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2188 gen_rtx_COMPARE (mode, x, y)));
2193 /* This function is used for v9 only.
2194 CODE is the code for an Scc's comparison.
2195 OPERANDS[0] is the target of the Scc insn.
2196 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2197 been generated yet).
2199 This function is needed to turn
2202 (gt (reg:CCX 100 %icc)
2206 (gt:DI (reg:CCX 100 %icc)
2209 IE: The instruction recognizer needs to see the mode of the comparison to
2210 find the right instruction. We could use "gt:DI" right in the
2211 define_expand, but leaving it out allows us to handle DI, SI, etc.
2213 We refer to the global sparc compare operands sparc_compare_op0 and
2214 sparc_compare_op1. */
2217 gen_v9_scc (compare_code, operands)
2218 enum rtx_code compare_code;
2219 register rtx *operands;
2224 && (GET_MODE (sparc_compare_op0) == DImode
2225 || GET_MODE (operands[0]) == DImode))
2228 /* Handle the case where operands[0] == sparc_compare_op0.
2229 We "early clobber" the result. */
2230 if (REGNO (operands[0]) == REGNO (sparc_compare_op0))
2232 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2233 emit_move_insn (op0, sparc_compare_op0);
2236 op0 = sparc_compare_op0;
2237 /* For consistency in the following. */
2238 op1 = sparc_compare_op1;
2240 /* Try to use the movrCC insns. */
2242 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2243 && op1 == const0_rtx
2244 && v9_regcmp_p (compare_code))
2246 /* Special case for op0 != 0. This can be done with one instruction if
2247 operands[0] == sparc_compare_op0. We don't assume they are equal
2250 if (compare_code == NE
2251 && GET_MODE (operands[0]) == DImode
2252 && GET_MODE (op0) == DImode)
2254 emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0));
2255 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2256 gen_rtx_IF_THEN_ELSE (DImode,
2257 gen_rtx_fmt_ee (compare_code, DImode,
2264 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2265 if (GET_MODE (op0) != DImode)
2267 temp = gen_reg_rtx (DImode);
2268 convert_move (temp, op0, 0);
2272 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2273 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2274 gen_rtx_fmt_ee (compare_code, DImode,
2282 operands[1] = gen_compare_reg (compare_code, op0, op1);
2284 switch (GET_MODE (operands[1]))
2294 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2295 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2296 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2297 gen_rtx_fmt_ee (compare_code,
2298 GET_MODE (operands[1]),
2299 operands[1], const0_rtx),
2300 const1_rtx, operands[0])));
2305 /* Emit a conditional jump insn for the v9 architecture using comparison code
2306 CODE and jump target LABEL.
2307 This function exists to take advantage of the v9 brxx insns. */
2310 emit_v9_brxx_insn (code, op0, label)
2314 emit_jump_insn (gen_rtx_SET (VOIDmode,
2316 gen_rtx_IF_THEN_ELSE (VOIDmode,
2317 gen_rtx_fmt_ee (code, GET_MODE (op0),
2319 gen_rtx_LABEL_REF (VOIDmode, label),
2323 /* Generate a DFmode part of a hard TFmode register.
2324 REG is the TFmode hard register, LOW is 1 for the
2325 low 64bit of the register and 0 otherwise.
2328 gen_df_reg (reg, low)
2332 int regno = REGNO (reg);
2334 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2335 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2336 return gen_rtx_REG (DFmode, regno);
2339 /* Return nonzero if a return peephole merging return with
2340 setting of output register is ok. */
2342 leaf_return_peephole_ok ()
2344 return (actual_fsize == 0);
2347 /* Return nonzero if TRIAL can go into the function epilogue's
2348 delay slot. SLOT is the slot we are trying to fill. */
2351 eligible_for_epilogue_delay (trial, slot)
2360 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2363 if (get_attr_length (trial) != 1)
2366 /* If %g0 is live, there are lots of things we can't handle.
2367 Rather than trying to find them all now, let's punt and only
2368 optimize things as necessary. */
2372 /* If there are any call-saved registers, we should scan TRIAL if it
2373 does not reference them. For now just make it easy. */
2377 /* In the case of a true leaf function, anything can go into the delay slot.
2378 A delay slot only exists however if the frame size is zero, otherwise
2379 we will put an insn to adjust the stack after the return. */
2380 if (current_function_uses_only_leaf_regs)
2382 if (leaf_return_peephole_ok ())
2383 return ((get_attr_in_uncond_branch_delay (trial)
2384 == IN_BRANCH_DELAY_TRUE));
2388 /* If only trivial `restore' insns work, nothing can go in the
2390 else if (TARGET_BROKEN_SAVERESTORE)
2393 pat = PATTERN (trial);
2395 /* Otherwise, only operations which can be done in tandem with
2396 a `restore' or `return' insn can go into the delay slot. */
2397 if (GET_CODE (SET_DEST (pat)) != REG
2398 || REGNO (SET_DEST (pat)) >= 32
2399 || REGNO (SET_DEST (pat)) < 24)
2402 /* The set of insns matched here must agree precisely with the set of
2403 patterns paired with a RETURN in sparc.md. */
2405 src = SET_SRC (pat);
2407 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2408 if (arith_operand (src, GET_MODE (src)))
2411 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2413 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2416 /* This matches "*return_di". */
2417 else if (arith_double_operand (src, GET_MODE (src)))
2418 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2420 /* This matches "*return_sf_no_fpu". */
2421 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2422 && register_operand (src, SFmode))
2425 /* If we have return instruction, anything that does not use
2426 local or output registers and can go into a delay slot wins. */
2427 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2428 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2431 /* This matches "*return_addsi". */
2432 else if (GET_CODE (src) == PLUS
2433 && arith_operand (XEXP (src, 0), SImode)
2434 && arith_operand (XEXP (src, 1), SImode)
2435 && (register_operand (XEXP (src, 0), SImode)
2436 || register_operand (XEXP (src, 1), SImode)))
2439 /* This matches "*return_adddi". */
2440 else if (GET_CODE (src) == PLUS
2441 && arith_double_operand (XEXP (src, 0), DImode)
2442 && arith_double_operand (XEXP (src, 1), DImode)
2443 && (register_operand (XEXP (src, 0), DImode)
2444 || register_operand (XEXP (src, 1), DImode)))
2447 /* This can match "*return_losum_[sd]i".
2448 Catch only some cases, so that return_losum* don't have
2450 else if (GET_CODE (src) == LO_SUM
2451 && ! TARGET_CM_MEDMID
2452 && ((register_operand (XEXP (src, 0), SImode)
2453 && immediate_operand (XEXP (src, 1), SImode))
2455 && register_operand (XEXP (src, 0), DImode)
2456 && immediate_operand (XEXP (src, 1), DImode))))
2459 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2460 else if (GET_CODE (src) == ASHIFT
2461 && (register_operand (XEXP (src, 0), SImode)
2462 || register_operand (XEXP (src, 0), DImode))
2463 && XEXP (src, 1) == const1_rtx)
2470 check_return_regs (x)
2473 switch (GET_CODE (x))
2476 return IN_OR_GLOBAL_P (x);
2491 if (check_return_regs (XEXP (x, 1)) == 0)
2496 return check_return_regs (XEXP (x, 0));
2504 /* Return 1 if TRIAL references only in and global registers. */
2506 eligible_for_return_delay (trial)
2509 if (GET_CODE (PATTERN (trial)) != SET)
2512 return check_return_regs (PATTERN (trial));
2516 short_branch (uid1, uid2)
2519 unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2];
2520 if (delta + 1024 < 2048)
2522 /* warning ("long branch, distance %d", delta); */
2526 /* Return non-zero if REG is not used after INSN.
2527 We assume REG is a reload reg, and therefore does
2528 not live past labels or calls or jumps. */
2530 reg_unused_after (reg, insn)
2534 enum rtx_code code, prev_code = UNKNOWN;
2536 while ((insn = NEXT_INSN (insn)))
2538 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2541 code = GET_CODE (insn);
2542 if (GET_CODE (insn) == CODE_LABEL)
2545 if (GET_RTX_CLASS (code) == 'i')
2547 rtx set = single_set (insn);
2548 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2551 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2553 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2561 /* The table we use to reference PIC data. */
2562 static rtx global_offset_table;
2564 /* The function we use to get at it. */
2565 static rtx get_pc_symbol;
2566 static char get_pc_symbol_name[256];
2568 /* Ensure that we are not using patterns that are not OK with PIC. */
2577 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
2578 || (GET_CODE (recog_data.operand[i]) == CONST
2579 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
2580 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
2581 == global_offset_table)
2582 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
2591 /* Return true if X is an address which needs a temporary register when
2592 reloaded while generating PIC code. */
2595 pic_address_needs_scratch (x)
2598 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2599 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2600 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2601 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2602 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2608 /* Legitimize PIC addresses. If the address is already position-independent,
2609 we return ORIG. Newly generated position-independent addresses go into a
2610 reg. This is REG if non zero, otherwise we allocate register(s) as
2614 legitimize_pic_address (orig, mode, reg)
2616 enum machine_mode mode ATTRIBUTE_UNUSED;
2619 if (GET_CODE (orig) == SYMBOL_REF)
2621 rtx pic_ref, address;
2626 if (reload_in_progress || reload_completed)
2629 reg = gen_reg_rtx (Pmode);
2634 /* If not during reload, allocate another temp reg here for loading
2635 in the address, so that these instructions can be optimized
2637 rtx temp_reg = ((reload_in_progress || reload_completed)
2638 ? reg : gen_reg_rtx (Pmode));
2640 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
2641 won't get confused into thinking that these two instructions
2642 are loading in the true address of the symbol. If in the
2643 future a PIC rtx exists, that should be used instead. */
2644 if (Pmode == SImode)
2646 emit_insn (gen_movsi_high_pic (temp_reg, orig));
2647 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
2651 emit_insn (gen_movdi_high_pic (temp_reg, orig));
2652 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
2659 pic_ref = gen_rtx_MEM (Pmode,
2660 gen_rtx_PLUS (Pmode,
2661 pic_offset_table_rtx, address));
2662 current_function_uses_pic_offset_table = 1;
2663 RTX_UNCHANGING_P (pic_ref) = 1;
2664 insn = emit_move_insn (reg, pic_ref);
2665 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2667 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2671 else if (GET_CODE (orig) == CONST)
2675 if (GET_CODE (XEXP (orig, 0)) == PLUS
2676 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2681 if (reload_in_progress || reload_completed)
2684 reg = gen_reg_rtx (Pmode);
2687 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2689 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2690 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2691 base == reg ? 0 : reg);
2696 if (GET_CODE (offset) == CONST_INT)
2698 if (SMALL_INT (offset))
2699 return plus_constant_for_output (base, INTVAL (offset));
2700 else if (! reload_in_progress && ! reload_completed)
2701 offset = force_reg (Pmode, offset);
2703 /* If we reach here, then something is seriously wrong. */
2706 return gen_rtx_PLUS (Pmode, base, offset);
2708 else if (GET_CODE (orig) == LABEL_REF)
2709 /* ??? Why do we do this? */
2710 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
2711 the register is live instead, in case it is eliminated. */
2712 current_function_uses_pic_offset_table = 1;
2717 /* Return the RTX for insns to set the PIC register. */
2725 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
2727 seq = gen_sequence ();
2733 /* Emit special PIC prologues and epilogues. */
2738 /* Labels to get the PC in the prologue of this function. */
2739 int orig_flag_pic = flag_pic;
2742 if (current_function_uses_pic_offset_table == 0)
2748 /* If we havn't emitted the special get_pc helper function, do so now. */
2749 if (get_pc_symbol_name[0] == 0)
2753 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
2756 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
2758 ASM_OUTPUT_ALIGN (asm_out_file, align);
2759 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0);
2760 fputs ("\tretl\n\tadd %o7,%l7,%l7\n", asm_out_file);
2763 /* Initialize every time through, since we can't easily
2764 know this to be permanent. */
2765 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2766 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
2769 emit_insn_after (pic_setup_code (), get_insns ());
2771 /* Insert the code in each nonlocal goto receiver.
2772 If you make changes here or to the nonlocal_goto_receiver
2773 pattern, make sure the unspec_volatile numbers still
2775 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2776 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
2777 && XINT (PATTERN (insn), 1) == 5)
2778 emit_insn_after (pic_setup_code (), insn);
2780 flag_pic = orig_flag_pic;
2782 /* Need to emit this whether or not we obey regdecls,
2783 since setjmp/longjmp can cause life info to screw up.
2784 ??? In the case where we don't obey regdecls, this is not sufficient
2785 since we may not fall out the bottom. */
2786 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2789 /* Return 1 if RTX is a MEM which is known to be aligned to at
2790 least an 8 byte boundary. */
2793 mem_min_alignment (mem, desired)
2797 rtx addr, base, offset;
2799 /* If it's not a MEM we can't accept it. */
2800 if (GET_CODE (mem) != MEM)
2803 addr = XEXP (mem, 0);
2804 base = offset = NULL_RTX;
2805 if (GET_CODE (addr) == PLUS)
2807 if (GET_CODE (XEXP (addr, 0)) == REG)
2809 base = XEXP (addr, 0);
2811 /* What we are saying here is that if the base
2812 REG is aligned properly, the compiler will make
2813 sure any REG based index upon it will be so
2815 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2816 offset = XEXP (addr, 1);
2818 offset = const0_rtx;
2821 else if (GET_CODE (addr) == REG)
2824 offset = const0_rtx;
2827 if (base != NULL_RTX)
2829 int regno = REGNO (base);
2831 if (regno != FRAME_POINTER_REGNUM
2832 && regno != STACK_POINTER_REGNUM)
2834 /* Check if the compiler has recorded some information
2835 about the alignment of the base REG. If reload has
2836 completed, we already matched with proper alignments. */
2837 if (((cfun != 0 && REGNO_POINTER_ALIGN (regno) >= desired)
2838 || reload_completed)
2839 && ((INTVAL (offset) & (desired - 1)) == 0))
2844 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
2848 else if (! TARGET_UNALIGNED_DOUBLES
2849 || CONSTANT_P (addr)
2850 || GET_CODE (addr) == LO_SUM)
2852 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
2853 is true, in which case we can only assume that an access is aligned if
2854 it is to a constant address, or the address involves a LO_SUM. */
2858 /* An obviously unaligned address. */
2863 /* Vectors to keep interesting information about registers where it can easily
2864 be got. We use to use the actual mode value as the bit number, but there
2865 are more than 32 modes now. Instead we use two tables: one indexed by
2866 hard register number, and one indexed by mode. */
2868 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2869 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2870 mapped into one sparc_mode_class mode. */
2872 enum sparc_mode_class {
2873 S_MODE, D_MODE, T_MODE, O_MODE,
2874 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
2878 /* Modes for single-word and smaller quantities. */
2879 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2881 /* Modes for double-word and smaller quantities. */
2882 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2884 /* Modes for quad-word and smaller quantities. */
2885 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2887 /* Modes for 8-word and smaller quantities. */
2888 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
2890 /* Modes for single-float quantities. We must allow any single word or
2891 smaller quantity. This is because the fix/float conversion instructions
2892 take integer inputs/outputs from the float registers. */
2893 #define SF_MODES (S_MODES)
2895 /* Modes for double-float and smaller quantities. */
2896 #define DF_MODES (S_MODES | D_MODES)
2898 /* Modes for double-float only quantities. */
2899 #define DF_MODES_NO_S (D_MODES)
2901 /* Modes for quad-float only quantities. */
2902 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2904 /* Modes for quad-float and smaller quantities. */
2905 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2907 /* Modes for quad-float and double-float quantities. */
2908 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
2910 /* Modes for quad-float pair only quantities. */
2911 #define OF_ONLY_MODES (1 << (int) OF_MODE)
2913 /* Modes for quad-float pairs and smaller quantities. */
2914 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
2916 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
2918 /* Modes for condition codes. */
2919 #define CC_MODES (1 << (int) CC_MODE)
2920 #define CCFP_MODES (1 << (int) CCFP_MODE)
2922 /* Value is 1 if register/mode pair is acceptable on sparc.
2923 The funny mixture of D and T modes is because integer operations
2924 do not specially operate on tetra quantities, so non-quad-aligned
2925 registers can hold quadword quantities (except %o4 and %i4 because
2926 they cross fixed registers). */
2928 /* This points to either the 32 bit or the 64 bit version. */
2929 int *hard_regno_mode_classes;
2931 static int hard_32bit_mode_classes[] = {
2932 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2933 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2934 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2935 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2937 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
2938 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
2939 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
2940 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2942 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2943 and none can hold SFmode/SImode values. */
2944 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
2945 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
2946 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
2947 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
2950 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2956 static int hard_64bit_mode_classes[] = {
2957 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2958 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2959 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2960 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2962 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
2963 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
2964 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
2965 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2967 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2968 and none can hold SFmode/SImode values. */
2969 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
2970 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
2971 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
2972 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
2975 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2981 int sparc_mode_class [NUM_MACHINE_MODES];
2983 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
2990 for (i = 0; i < NUM_MACHINE_MODES; i++)
2992 switch (GET_MODE_CLASS (i))
2995 case MODE_PARTIAL_INT:
2996 case MODE_COMPLEX_INT:
2997 if (GET_MODE_SIZE (i) <= 4)
2998 sparc_mode_class[i] = 1 << (int) S_MODE;
2999 else if (GET_MODE_SIZE (i) == 8)
3000 sparc_mode_class[i] = 1 << (int) D_MODE;
3001 else if (GET_MODE_SIZE (i) == 16)
3002 sparc_mode_class[i] = 1 << (int) T_MODE;
3003 else if (GET_MODE_SIZE (i) == 32)
3004 sparc_mode_class[i] = 1 << (int) O_MODE;
3006 sparc_mode_class[i] = 0;
3009 case MODE_COMPLEX_FLOAT:
3010 if (GET_MODE_SIZE (i) <= 4)
3011 sparc_mode_class[i] = 1 << (int) SF_MODE;
3012 else if (GET_MODE_SIZE (i) == 8)
3013 sparc_mode_class[i] = 1 << (int) DF_MODE;
3014 else if (GET_MODE_SIZE (i) == 16)
3015 sparc_mode_class[i] = 1 << (int) TF_MODE;
3016 else if (GET_MODE_SIZE (i) == 32)
3017 sparc_mode_class[i] = 1 << (int) OF_MODE;
3019 sparc_mode_class[i] = 0;
3023 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3024 we must explicitly check for them here. */
3025 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3026 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3027 else if (i == (int) CCmode || i == (int) CC_NOOVmode
3028 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3029 sparc_mode_class[i] = 1 << (int) CC_MODE;
3031 sparc_mode_class[i] = 0;
3037 hard_regno_mode_classes = hard_64bit_mode_classes;
3039 hard_regno_mode_classes = hard_32bit_mode_classes;
3041 /* Initialize the array used by REGNO_REG_CLASS. */
3042 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3044 if (i < 16 && TARGET_V8PLUS)
3045 sparc_regno_reg_class[i] = I64_REGS;
3047 sparc_regno_reg_class[i] = GENERAL_REGS;
3049 sparc_regno_reg_class[i] = FP_REGS;
3051 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3053 sparc_regno_reg_class[i] = FPCC_REGS;
3055 sparc_regno_reg_class[i] = NO_REGS;
3059 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3060 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3061 v9 int regs as it simplifies the code. */
3064 save_regs (file, low, high, base, offset, n_regs, real_offset)
3074 if (TARGET_ARCH64 && high <= 32)
3076 for (i = low; i < high; i++)
3078 if (regs_ever_live[i] && ! call_used_regs[i])
3080 fprintf (file, "\tstx\t%s, [%s+%d]\n",
3081 reg_names[i], base, offset + 4 * n_regs);
3082 if (dwarf2out_do_frame ())
3083 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3090 for (i = low; i < high; i += 2)
3092 if (regs_ever_live[i] && ! call_used_regs[i])
3094 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3096 fprintf (file, "\tstd\t%s, [%s+%d]\n",
3097 reg_names[i], base, offset + 4 * n_regs);
3098 if (dwarf2out_do_frame ())
3100 char *l = dwarf2out_cfi_label ();
3101 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
3102 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
3108 fprintf (file, "\tst\t%s, [%s+%d]\n",
3109 reg_names[i], base, offset + 4 * n_regs);
3110 if (dwarf2out_do_frame ())
3111 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3117 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3119 fprintf (file, "\tst\t%s, [%s+%d]\n",
3120 reg_names[i+1], base, offset + 4 * n_regs + 4);
3121 if (dwarf2out_do_frame ())
3122 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
3131 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3133 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3134 v9 int regs as it simplifies the code. */
3137 restore_regs (file, low, high, base, offset, n_regs)
3146 if (TARGET_ARCH64 && high <= 32)
3148 for (i = low; i < high; i++)
3150 if (regs_ever_live[i] && ! call_used_regs[i])
3151 fprintf (file, "\tldx\t[%s+%d], %s\n",
3152 base, offset + 4 * n_regs, reg_names[i]),
3158 for (i = low; i < high; i += 2)
3160 if (regs_ever_live[i] && ! call_used_regs[i])
3161 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3162 fprintf (file, "\tldd\t[%s+%d], %s\n",
3163 base, offset + 4 * n_regs, reg_names[i]),
3166 fprintf (file, "\tld\t[%s+%d],%s\n",
3167 base, offset + 4 * n_regs, reg_names[i]),
3169 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3170 fprintf (file, "\tld\t[%s+%d],%s\n",
3171 base, offset + 4 * n_regs + 4, reg_names[i+1]),
3178 /* Compute the frame size required by the function. This function is called
3179 during the reload pass and also by output_function_prologue(). */
3182 compute_frame_size (size, leaf_function)
3187 int outgoing_args_size = (current_function_outgoing_args_size
3188 + REG_PARM_STACK_SPACE (current_function_decl));
3190 if (TARGET_EPILOGUE)
3192 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3193 even to v9 int regs to be consistent with save_regs/restore_regs. */
3197 for (i = 0; i < 8; i++)
3198 if (regs_ever_live[i] && ! call_used_regs[i])
3203 for (i = 0; i < 8; i += 2)
3204 if ((regs_ever_live[i] && ! call_used_regs[i])
3205 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3209 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3210 if ((regs_ever_live[i] && ! call_used_regs[i])
3211 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3215 /* Set up values for use in `function_epilogue'. */
3216 num_gfregs = n_regs;
3218 if (leaf_function && n_regs == 0
3219 && size == 0 && current_function_outgoing_args_size == 0)
3221 actual_fsize = apparent_fsize = 0;
3225 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3226 The stack bias (if any) is taken out to undo its effects. */
3227 apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8;
3228 apparent_fsize += n_regs * 4;
3229 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3232 /* Make sure nothing can clobber our register windows.
3233 If a SAVE must be done, or there is a stack-local variable,
3234 the register window area must be allocated.
3235 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3236 if (leaf_function == 0 || size > 0)
3237 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3239 return SPARC_STACK_ALIGN (actual_fsize);
3242 /* Build a (32 bit) big number in a register. */
3243 /* ??? We may be able to use the set macro here too. */
3246 build_big_number (file, num, reg)
3251 if (num >= 0 || ! TARGET_ARCH64)
3253 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
3254 if ((num & 0x3ff) != 0)
3255 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
3257 else /* num < 0 && TARGET_ARCH64 */
3259 /* Sethi does not sign extend, so we must use a little trickery
3260 to use it for negative numbers. Invert the constant before
3261 loading it in, then use xor immediate to invert the loaded bits
3262 (along with the upper 32 bits) to the desired constant. This
3263 works because the sethi and immediate fields overlap. */
3266 int low = -0x400 + (asize & 0x3FF);
3268 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3269 inv, reg, reg, low, reg);
3273 /* Output any necessary .register pseudo-ops. */
3275 sparc_output_scratch_registers (file)
3278 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3284 /* Check if %g[2367] were used without
3285 .register being printed for them already. */
3286 for (i = 2; i < 8; i++)
3288 if (regs_ever_live [i]
3289 && ! sparc_hard_reg_printed [i])
3291 sparc_hard_reg_printed [i] = 1;
3292 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
3299 /* Output code for the function prologue. */
3302 output_function_prologue (file, size, leaf_function)
3307 sparc_output_scratch_registers (file);
3309 /* Need to use actual_fsize, since we are also allocating
3310 space for our callee (and our own register save area). */
3311 actual_fsize = compute_frame_size (size, leaf_function);
3315 frame_base_name = "%sp";
3316 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3320 frame_base_name = "%fp";
3321 frame_base_offset = SPARC_STACK_BIAS;
3324 /* This is only for the human reader. */
3325 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3327 if (actual_fsize == 0)
3329 else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE)
3331 if (actual_fsize <= 4096)
3332 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3333 else if (actual_fsize <= 8192)
3335 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3336 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3340 build_big_number (file, -actual_fsize, "%g1");
3341 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
3344 else if (! leaf_function && TARGET_BROKEN_SAVERESTORE)
3346 /* We assume the environment will properly handle or otherwise avoid
3347 trouble associated with an interrupt occurring after the `save' or
3348 trap occurring during it. */
3349 fprintf (file, "\tsave\n");
3351 if (actual_fsize <= 4096)
3352 fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize);
3353 else if (actual_fsize <= 8192)
3355 fprintf (file, "\tadd\t%%fp, -4096, %%sp\n");
3356 fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize - 4096);
3360 build_big_number (file, -actual_fsize, "%g1");
3361 fprintf (file, "\tadd\t%%fp, %%g1, %%sp\n");
3364 else /* leaf function */
3366 if (actual_fsize <= 4096)
3367 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3368 else if (actual_fsize <= 8192)
3370 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3371 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3375 build_big_number (file, -actual_fsize, "%g1");
3376 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3380 if (dwarf2out_do_frame () && actual_fsize)
3382 char *label = dwarf2out_cfi_label ();
3384 /* The canonical frame address refers to the top of the frame. */
3385 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3386 : FRAME_POINTER_REGNUM),
3389 if (! leaf_function)
3391 /* Note the register window save. This tells the unwinder that
3392 it needs to restore the window registers from the previous
3393 frame's window save area at 0(cfa). */
3394 dwarf2out_window_save (label);
3396 /* The return address (-8) is now in %i7. */
3397 dwarf2out_return_reg (label, 31);
3401 /* If doing anything with PIC, do it now. */
3403 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3405 /* Call saved registers are saved just above the outgoing argument area. */
3408 int offset, real_offset, n_regs;
3411 real_offset = -apparent_fsize;
3412 offset = -apparent_fsize + frame_base_offset;
3413 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3415 /* ??? This might be optimized a little as %g1 might already have a
3416 value close enough that a single add insn will do. */
3417 /* ??? Although, all of this is probably only a temporary fix
3418 because if %g1 can hold a function result, then
3419 output_function_epilogue will lose (the result will get
3421 build_big_number (file, offset, "%g1");
3422 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3428 base = frame_base_name;
3432 if (TARGET_EPILOGUE && ! leaf_function)
3433 /* ??? Originally saved regs 0-15 here. */
3434 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3435 else if (leaf_function)
3436 /* ??? Originally saved regs 0-31 here. */
3437 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3438 if (TARGET_EPILOGUE)
3439 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3444 if (leaf_function && actual_fsize != 0)
3446 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3447 if (! TARGET_EPILOGUE)
3448 leaf_label = gen_label_rtx ();
3452 /* Output code for the function epilogue. */
3455 output_function_epilogue (file, size, leaf_function)
3457 int size ATTRIBUTE_UNUSED;
3464 emit_label_after (leaf_label, get_last_insn ());
3465 final_scan_insn (get_last_insn (), file, 0, 0, 1);
3468 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3469 else if (profile_block_flag == 2)
3471 FUNCTION_BLOCK_PROFILER_EXIT(file);
3475 else if (current_function_epilogue_delay_list == 0)
3477 /* If code does not drop into the epilogue, we need
3478 do nothing except output pending case vectors. */
3479 rtx insn = get_last_insn ();
3480 if (GET_CODE (insn) == NOTE)
3481 insn = prev_nonnote_insn (insn);
3482 if (insn && GET_CODE (insn) == BARRIER)
3483 goto output_vectors;
3486 /* Restore any call saved registers. */
3492 offset = -apparent_fsize + frame_base_offset;
3493 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3495 build_big_number (file, offset, "%g1");
3496 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3502 base = frame_base_name;
3506 if (TARGET_EPILOGUE && ! leaf_function)
3507 /* ??? Originally saved regs 0-15 here. */
3508 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3509 else if (leaf_function)
3510 /* ??? Originally saved regs 0-31 here. */
3511 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3512 if (TARGET_EPILOGUE)
3513 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
3516 /* Work out how to skip the caller's unimp instruction if required. */
3518 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
3520 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
3522 if (TARGET_EPILOGUE || leaf_label)
3524 int old_target_epilogue = TARGET_EPILOGUE;
3525 target_flags &= ~old_target_epilogue;
3527 if (! leaf_function)
3529 /* If we wound up with things in our delay slot, flush them here. */
3530 if (current_function_epilogue_delay_list)
3532 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
3534 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
3536 epilogue_renumber (&delay, 0);
3537 fputs (SKIP_CALLERS_UNIMP_P
3538 ? "\treturn\t%i7+12\n"
3539 : "\treturn\t%i7+8\n", file);
3540 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), file, 1, 0, 0);
3544 rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode),
3548 if (GET_CODE (delay) != SET)
3551 src = SET_SRC (delay);
3552 if (GET_CODE (src) == ASHIFT)
3554 if (XEXP (src, 1) != const1_rtx)
3556 SET_SRC (delay) = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
3560 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode,
3561 gen_rtvec (2, delay, PATTERN (insn)));
3562 final_scan_insn (insn, file, 1, 0, 1);
3565 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
3566 fputs ("\treturn\t%i7+8\n\tnop\n", file);
3568 fprintf (file, "\t%s\n\trestore\n", ret);
3570 /* All of the following cases are for leaf functions. */
3571 else if (current_function_epilogue_delay_list)
3573 /* eligible_for_epilogue_delay_slot ensures that if this is a
3574 leaf function, then we will only have insn in the delay slot
3575 if the frame size is zero, thus no adjust for the stack is
3577 if (actual_fsize != 0)
3579 fprintf (file, "\t%s\n", ret);
3580 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
3583 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3584 avoid generating confusing assembly language output. */
3585 else if (actual_fsize == 0)
3586 fprintf (file, "\t%s\n\tnop\n", ret);
3587 else if (actual_fsize <= 4096)
3588 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
3589 else if (actual_fsize <= 8192)
3590 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
3591 ret, actual_fsize - 4096);
3592 else if ((actual_fsize & 0x3ff) == 0)
3593 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3596 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3597 actual_fsize, actual_fsize, ret);
3598 target_flags |= old_target_epilogue;
3602 sparc_output_deferred_case_vectors ();
3605 /* Functions for handling argument passing.
3607 For v8 the first six args are normally in registers and the rest are
3608 pushed. Any arg that starts within the first 6 words is at least
3609 partially passed in a register unless its data type forbids.
3611 For v9, the argument registers are laid out as an array of 16 elements
3612 and arguments are added sequentially. The first 6 int args and up to the
3613 first 16 fp args (depending on size) are passed in regs.
3615 Slot Stack Integral Float Float in structure Double Long Double
3616 ---- ----- -------- ----- ------------------ ------ -----------
3617 15 [SP+248] %f31 %f30,%f31 %d30
3618 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3619 13 [SP+232] %f27 %f26,%f27 %d26
3620 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3621 11 [SP+216] %f23 %f22,%f23 %d22
3622 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3623 9 [SP+200] %f19 %f18,%f19 %d18
3624 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3625 7 [SP+184] %f15 %f14,%f15 %d14
3626 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3627 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3628 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3629 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3630 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3631 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3632 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3634 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3636 Integral arguments are always passed as 64 bit quantities appropriately
3639 Passing of floating point values is handled as follows.
3640 If a prototype is in scope:
3641 If the value is in a named argument (i.e. not a stdarg function or a
3642 value not part of the `...') then the value is passed in the appropriate
3644 If the value is part of the `...' and is passed in one of the first 6
3645 slots then the value is passed in the appropriate int reg.
3646 If the value is part of the `...' and is not passed in one of the first 6
3647 slots then the value is passed in memory.
3648 If a prototype is not in scope:
3649 If the value is one of the first 6 arguments the value is passed in the
3650 appropriate integer reg and the appropriate fp reg.
3651 If the value is not one of the first 6 arguments the value is passed in
3652 the appropriate fp reg and in memory.
3655 /* Maximum number of int regs for args. */
3656 #define SPARC_INT_ARG_MAX 6
3657 /* Maximum number of fp regs for args. */
3658 #define SPARC_FP_ARG_MAX 16
3660 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3662 /* Handle the INIT_CUMULATIVE_ARGS macro.
3663 Initialize a variable CUM of type CUMULATIVE_ARGS
3664 for a call to a function whose data type is FNTYPE.
3665 For a library call, FNTYPE is 0. */
3668 init_cumulative_args (cum, fntype, libname, indirect)
3669 CUMULATIVE_ARGS *cum;
3671 rtx libname ATTRIBUTE_UNUSED;
3672 int indirect ATTRIBUTE_UNUSED;
3675 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
3676 cum->libcall_p = fntype == 0;
3679 /* Compute the slot number to pass an argument in.
3680 Returns the slot number or -1 if passing on the stack.
3682 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3683 the preceding args and about the function being called.
3684 MODE is the argument's machine mode.
3685 TYPE is the data type of the argument (as a tree).
3686 This is null for libcalls where that information may
3688 NAMED is nonzero if this argument is a named parameter
3689 (otherwise it is an extra parameter matching an ellipsis).
3690 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3691 *PREGNO records the register number to use if scalar type.
3692 *PPADDING records the amount of padding needed in words. */
3695 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
3696 const CUMULATIVE_ARGS *cum;
3697 enum machine_mode mode;
3704 int regbase = (incoming_p
3705 ? SPARC_INCOMING_INT_ARG_FIRST
3706 : SPARC_OUTGOING_INT_ARG_FIRST);
3707 int slotno = cum->words;
3712 if (type != 0 && TREE_ADDRESSABLE (type))
3715 && type != 0 && mode == BLKmode
3716 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
3722 /* MODE is VOIDmode when generating the actual call.
3726 case QImode : case CQImode :
3727 case HImode : case CHImode :
3728 case SImode : case CSImode :
3729 case DImode : case CDImode :
3730 if (slotno >= SPARC_INT_ARG_MAX)
3732 regno = regbase + slotno;
3735 case SFmode : case SCmode :
3736 case DFmode : case DCmode :
3737 case TFmode : case TCmode :
3740 if (slotno >= SPARC_INT_ARG_MAX)
3742 regno = regbase + slotno;
3746 if ((mode == TFmode || mode == TCmode)
3747 && (slotno & 1) != 0)
3748 slotno++, *ppadding = 1;
3749 if (TARGET_FPU && named)
3751 if (slotno >= SPARC_FP_ARG_MAX)
3753 regno = SPARC_FP_ARG_FIRST + slotno * 2;
3759 if (slotno >= SPARC_INT_ARG_MAX)
3761 regno = regbase + slotno;
3767 /* For sparc64, objects requiring 16 byte alignment get it. */
3770 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
3771 slotno++, *ppadding = 1;
3775 || (type && TREE_CODE (type) == UNION_TYPE))
3777 if (slotno >= SPARC_INT_ARG_MAX)
3779 regno = regbase + slotno;
3784 int intregs_p = 0, fpregs_p = 0;
3785 /* The ABI obviously doesn't specify how packed
3786 structures are passed. These are defined to be passed
3787 in int regs if possible, otherwise memory. */
3790 /* First see what kinds of registers we need. */
3791 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3793 if (TREE_CODE (field) == FIELD_DECL)
3795 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3800 if (DECL_PACKED (field))
3804 if (packed_p || !named)
3805 fpregs_p = 0, intregs_p = 1;
3807 /* If all arg slots are filled, then must pass on stack. */
3808 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
3810 /* If there are only int args and all int arg slots are filled,
3811 then must pass on stack. */
3812 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
3814 /* Note that even if all int arg slots are filled, fp members may
3815 still be passed in regs if such regs are available.
3816 *PREGNO isn't set because there may be more than one, it's up
3817 to the caller to compute them. */
3830 /* Handle recursive register counting for structure field layout. */
3832 struct function_arg_record_value_parms
3835 int slotno, named, regbase;
3836 int nregs, intoffset;
3839 static void function_arg_record_value_3
3840 PARAMS ((int, struct function_arg_record_value_parms *));
3841 static void function_arg_record_value_2
3842 PARAMS ((tree, int, struct function_arg_record_value_parms *));
3843 static void function_arg_record_value_1
3844 PARAMS ((tree, int, struct function_arg_record_value_parms *));
3845 static rtx function_arg_record_value
3846 PARAMS ((tree, enum machine_mode, int, int, int));
3849 function_arg_record_value_1 (type, startbitpos, parms)
3852 struct function_arg_record_value_parms *parms;
3856 /* The ABI obviously doesn't specify how packed structures are
3857 passed. These are defined to be passed in int regs if possible,
3858 otherwise memory. */
3861 /* We need to compute how many registers are needed so we can
3862 allocate the PARALLEL but before we can do that we need to know
3863 whether there are any packed fields. If there are, int regs are
3864 used regardless of whether there are fp values present. */
3865 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3867 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
3874 /* Compute how many registers we need. */
3875 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3877 if (TREE_CODE (field) == FIELD_DECL)
3879 int bitpos = startbitpos;
3880 if (DECL_FIELD_BITPOS (field))
3881 bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3882 /* ??? FIXME: else assume zero offset. */
3884 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
3886 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
3888 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3893 if (parms->intoffset != -1)
3895 int intslots, this_slotno;
3897 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
3899 this_slotno = parms->slotno + parms->intoffset
3902 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3903 intslots = MAX (intslots, 0);
3904 parms->nregs += intslots;
3905 parms->intoffset = -1;
3908 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
3909 If it wasn't true we wouldn't be here. */
3914 if (parms->intoffset == -1)
3915 parms->intoffset = bitpos;
3921 /* Handle recursive structure field register assignment. */
3924 function_arg_record_value_3 (bitpos, parms)
3926 struct function_arg_record_value_parms *parms;
3928 enum machine_mode mode;
3929 int regno, this_slotno, intslots, intoffset;
3932 if (parms->intoffset == -1)
3934 intoffset = parms->intoffset;
3935 parms->intoffset = -1;
3937 intslots = (bitpos - intoffset + BITS_PER_WORD - 1) / BITS_PER_WORD;
3938 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
3940 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3944 /* If this is the trailing part of a word, only load that much into
3945 the register. Otherwise load the whole register. Note that in
3946 the latter case we may pick up unwanted bits. It's not a problem
3947 at the moment but may wish to revisit. */
3949 if (intoffset % BITS_PER_WORD != 0)
3951 mode = mode_for_size (BITS_PER_WORD - intoffset%BITS_PER_WORD,
3957 intoffset /= BITS_PER_UNIT;
3960 regno = parms->regbase + this_slotno;
3961 reg = gen_rtx_REG (mode, regno);
3962 XVECEXP (parms->ret, 0, parms->nregs)
3963 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
3966 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
3970 while (intslots > 0);
3974 function_arg_record_value_2 (type, startbitpos, parms)
3977 struct function_arg_record_value_parms *parms;
3982 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3984 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
3991 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3993 if (TREE_CODE (field) == FIELD_DECL)
3995 int bitpos = startbitpos;
3996 if (DECL_FIELD_BITPOS (field))
3997 bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3998 /* ??? FIXME: else assume zero offset. */
4000 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4002 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
4004 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4009 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
4012 function_arg_record_value_3 (bitpos, parms);
4014 reg = gen_rtx_REG (DECL_MODE (field),
4015 (SPARC_FP_ARG_FIRST + this_slotno * 2
4016 + (DECL_MODE (field) == SFmode
4017 && (bitpos & 32) != 0)));
4018 XVECEXP (parms->ret, 0, parms->nregs)
4019 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4020 GEN_INT (bitpos / BITS_PER_UNIT));
4025 if (parms->intoffset == -1)
4026 parms->intoffset = bitpos;
4033 function_arg_record_value (type, mode, slotno, named, regbase)
4035 enum machine_mode mode;
4036 int slotno, named, regbase;
4038 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4039 struct function_arg_record_value_parms parms;
4042 parms.ret = NULL_RTX;
4043 parms.slotno = slotno;
4044 parms.named = named;
4045 parms.regbase = regbase;
4047 /* Compute how many registers we need. */
4049 parms.intoffset = 0;
4050 function_arg_record_value_1 (type, 0, &parms);
4052 if (parms.intoffset != -1)
4054 int intslots, this_slotno;
4056 intslots = (typesize*BITS_PER_UNIT - parms.intoffset + BITS_PER_WORD - 1)
4058 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
4060 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4061 intslots = MAX (intslots, 0);
4063 parms.nregs += intslots;
4065 nregs = parms.nregs;
4067 /* Allocate the vector and handle some annoying special cases. */
4070 /* ??? Empty structure has no value? Duh? */
4073 /* Though there's nothing really to store, return a word register
4074 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4075 leads to breakage due to the fact that there are zero bytes to
4077 return gen_rtx_REG (mode, regbase);
4081 /* ??? C++ has structures with no fields, and yet a size. Give up
4082 for now and pass everything back in integer registers. */
4083 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4085 if (nregs + slotno > SPARC_INT_ARG_MAX)
4086 nregs = SPARC_INT_ARG_MAX - slotno;
4091 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
4093 /* Fill in the entries. */
4095 parms.intoffset = 0;
4096 function_arg_record_value_2 (type, 0, &parms);
4097 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
4099 if (parms.nregs != nregs)
4105 /* Handle the FUNCTION_ARG macro.
4106 Determine where to put an argument to a function.
4107 Value is zero to push the argument on the stack,
4108 or a hard register in which to store the argument.
4110 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4111 the preceding args and about the function being called.
4112 MODE is the argument's machine mode.
4113 TYPE is the data type of the argument (as a tree).
4114 This is null for libcalls where that information may
4116 NAMED is nonzero if this argument is a named parameter
4117 (otherwise it is an extra parameter matching an ellipsis).
4118 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4121 function_arg (cum, mode, type, named, incoming_p)
4122 const CUMULATIVE_ARGS *cum;
4123 enum machine_mode mode;
4128 int regbase = (incoming_p
4129 ? SPARC_INCOMING_INT_ARG_FIRST
4130 : SPARC_OUTGOING_INT_ARG_FIRST);
4131 int slotno, regno, padding;
4134 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
4142 reg = gen_rtx_REG (mode, regno);
4146 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4147 but also have the slot allocated for them.
4148 If no prototype is in scope fp values in register slots get passed
4149 in two places, either fp regs and int regs or fp regs and memory. */
4150 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4151 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4152 && SPARC_FP_REG_P (regno))
4154 reg = gen_rtx_REG (mode, regno);
4155 if (cum->prototype_p || cum->libcall_p)
4157 /* "* 2" because fp reg numbers are recorded in 4 byte
4160 /* ??? This will cause the value to be passed in the fp reg and
4161 in the stack. When a prototype exists we want to pass the
4162 value in the reg but reserve space on the stack. That's an
4163 optimization, and is deferred [for a bit]. */
4164 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
4165 return gen_rtx_PARALLEL (mode,
4167 gen_rtx_EXPR_LIST (VOIDmode,
4168 NULL_RTX, const0_rtx),
4169 gen_rtx_EXPR_LIST (VOIDmode,
4173 /* ??? It seems that passing back a register even when past
4174 the area declared by REG_PARM_STACK_SPACE will allocate
4175 space appropriately, and will not copy the data onto the
4176 stack, exactly as we desire.
4178 This is due to locate_and_pad_parm being called in
4179 expand_call whenever reg_parm_stack_space > 0, which
4180 while benefical to our example here, would seem to be
4181 in error from what had been intended. Ho hum... -- r~ */
4189 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
4193 /* On incoming, we don't need to know that the value
4194 is passed in %f0 and %i0, and it confuses other parts
4195 causing needless spillage even on the simplest cases. */
4199 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
4200 + (regno - SPARC_FP_ARG_FIRST) / 2);
4202 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4203 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
4205 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4209 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4210 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4211 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4215 else if (type && TREE_CODE (type) == RECORD_TYPE)
4217 /* Structures up to 16 bytes in size are passed in arg slots on the
4218 stack and are promoted to registers where possible. */
4220 if (int_size_in_bytes (type) > 16)
4221 abort (); /* shouldn't get here */
4223 return function_arg_record_value (type, mode, slotno, named, regbase);
4225 else if (type && TREE_CODE (type) == UNION_TYPE)
4227 enum machine_mode mode;
4228 int bytes = int_size_in_bytes (type);
4233 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4234 reg = gen_rtx_REG (mode, regno);
4238 /* Scalar or complex int. */
4239 reg = gen_rtx_REG (mode, regno);
4245 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4246 For an arg passed partly in registers and partly in memory,
4247 this is the number of registers used.
4248 For args passed entirely in registers or entirely in memory, zero.
4250 Any arg that starts in the first 6 regs but won't entirely fit in them
4251 needs partial registers on v8. On v9, structures with integer
4252 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4253 values that begin in the last fp reg [where "last fp reg" varies with the
4254 mode] will be split between that reg and memory. */
4257 function_arg_partial_nregs (cum, mode, type, named)
4258 const CUMULATIVE_ARGS *cum;
4259 enum machine_mode mode;
4263 int slotno, regno, padding;
4265 /* We pass 0 for incoming_p here, it doesn't matter. */
4266 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4273 if ((slotno + (mode == BLKmode
4274 ? ROUND_ADVANCE (int_size_in_bytes (type))
4275 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
4276 > NPARM_REGS (SImode))
4277 return NPARM_REGS (SImode) - slotno;
4282 if (type && AGGREGATE_TYPE_P (type))
4284 int size = int_size_in_bytes (type);
4285 int align = TYPE_ALIGN (type);
4288 slotno += slotno & 1;
4289 if (size > 8 && size <= 16
4290 && slotno == SPARC_INT_ARG_MAX - 1)
4293 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
4294 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4297 if (GET_MODE_ALIGNMENT (mode) == 128)
4299 slotno += slotno & 1;
4300 if (slotno == SPARC_INT_ARG_MAX - 2)
4305 if (slotno == SPARC_INT_ARG_MAX - 1)
4309 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4311 if (GET_MODE_ALIGNMENT (mode) == 128)
4312 slotno += slotno & 1;
4313 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
4321 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
4322 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
4323 quad-precision floats by invisible reference.
4324 v9: Aggregates greater than 16 bytes are passed by reference.
4325 For Pascal, also pass arrays by reference. */
4328 function_arg_pass_by_reference (cum, mode, type, named)
4329 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
4330 enum machine_mode mode;
4332 int named ATTRIBUTE_UNUSED;
4336 return ((type && AGGREGATE_TYPE_P (type))
4337 || mode == TFmode || mode == TCmode);
4341 return ((type && TREE_CODE (type) == ARRAY_TYPE)
4342 /* Consider complex values as aggregates, so care for TCmode. */
4343 || GET_MODE_SIZE (mode) > 16
4344 || (type && AGGREGATE_TYPE_P (type)
4345 && int_size_in_bytes (type) > 16));
4349 /* Handle the FUNCTION_ARG_ADVANCE macro.
4350 Update the data in CUM to advance over an argument
4351 of mode MODE and data type TYPE.
4352 TYPE is null for libcalls where that information may not be available. */
4355 function_arg_advance (cum, mode, type, named)
4356 CUMULATIVE_ARGS *cum;
4357 enum machine_mode mode;
4361 int slotno, regno, padding;
4363 /* We pass 0 for incoming_p here, it doesn't matter. */
4364 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4366 /* If register required leading padding, add it. */
4368 cum->words += padding;
4372 cum->words += (mode != BLKmode
4373 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4374 : ROUND_ADVANCE (int_size_in_bytes (type)));
4378 if (type && AGGREGATE_TYPE_P (type))
4380 int size = int_size_in_bytes (type);
4384 else if (size <= 16)
4386 else /* passed by reference */
4389 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
4393 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4395 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
4399 cum->words += (mode != BLKmode
4400 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4401 : ROUND_ADVANCE (int_size_in_bytes (type)));
4406 /* Handle the FUNCTION_ARG_PADDING macro.
4407 For the 64 bit ABI structs are always stored left shifted in their
4411 function_arg_padding (mode, type)
4412 enum machine_mode mode;
4415 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
4418 /* This is the default definition. */
4419 return (! BYTES_BIG_ENDIAN
4422 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
4423 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
4424 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
4425 ? downward : upward));
4428 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
4429 For v9, function return values are subject to the same rules as arguments,
4430 except that up to 32-bytes may be returned in registers. */
4433 function_value (type, mode, incoming_p)
4435 enum machine_mode mode;
4439 int regbase = (incoming_p
4440 ? SPARC_OUTGOING_INT_ARG_FIRST
4441 : SPARC_INCOMING_INT_ARG_FIRST);
4443 if (TARGET_ARCH64 && type)
4445 if (TREE_CODE (type) == RECORD_TYPE)
4447 /* Structures up to 32 bytes in size are passed in registers,
4448 promoted to fp registers where possible. */
4450 if (int_size_in_bytes (type) > 32)
4451 abort (); /* shouldn't get here */
4453 return function_arg_record_value (type, mode, 0, 1, regbase);
4455 else if (TREE_CODE (type) == UNION_TYPE)
4457 int bytes = int_size_in_bytes (type);
4462 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4467 && GET_MODE_CLASS (mode) == MODE_INT
4468 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
4469 && type && TREE_CODE (type) != UNION_TYPE)
4473 regno = BASE_RETURN_VALUE_REG (mode);
4475 regno = BASE_OUTGOING_VALUE_REG (mode);
4477 return gen_rtx_REG (mode, regno);
4480 /* Do what is necessary for `va_start'. We look at the current function
4481 to determine if stdarg or varargs is used and return the address of
4482 the first unnamed parameter. */
4485 sparc_builtin_saveregs ()
4487 int first_reg = current_function_args_info.words;
4491 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
4492 emit_move_insn (gen_rtx_MEM (word_mode,
4493 gen_rtx_PLUS (Pmode,
4495 GEN_INT (STACK_POINTER_OFFSET
4496 + UNITS_PER_WORD * regno))),
4497 gen_rtx_REG (word_mode,
4498 BASE_INCOMING_ARG_REG (word_mode) + regno));
4500 address = gen_rtx_PLUS (Pmode,
4502 GEN_INT (STACK_POINTER_OFFSET
4503 + UNITS_PER_WORD * first_reg));
4505 if (current_function_check_memory_usage
4506 && first_reg < NPARM_REGS (word_mode))
4507 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4509 GEN_INT (UNITS_PER_WORD
4510 * (NPARM_REGS (word_mode) - first_reg)),
4511 TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW),
4512 TYPE_MODE (integer_type_node));
4517 /* Implement `va_start' for varargs and stdarg. */
4520 sparc_va_start (stdarg_p, valist, nextarg)
4521 int stdarg_p ATTRIBUTE_UNUSED;
4525 nextarg = expand_builtin_saveregs ();
4526 std_expand_builtin_va_start (1, valist, nextarg);
4529 /* Implement `va_arg'. */
4532 sparc_va_arg (valist, type)
4535 HOST_WIDE_INT size, rsize, align;
4540 /* Round up sizeof(type) to a word. */
4541 size = int_size_in_bytes (type);
4542 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4547 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD)
4548 align = 2 * UNITS_PER_WORD;
4550 if (AGGREGATE_TYPE_P (type))
4555 size = rsize = UNITS_PER_WORD;
4563 if (AGGREGATE_TYPE_P (type)
4564 || TYPE_MODE (type) == TFmode
4565 || TYPE_MODE (type) == TCmode)
4568 size = rsize = UNITS_PER_WORD;
4572 /* ??? The old va-sparc.h implementation, for 8 byte objects
4573 copied stuff to a temporary -- I don't see that that
4574 provides any more alignment than the stack slot did. */
4581 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4582 build_int_2 (align - 1, 0)));
4583 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
4584 build_int_2 (-align, -1)));
4587 addr = incr = save_expr (incr);
4588 if (BYTES_BIG_ENDIAN && size < rsize)
4590 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4591 build_int_2 (rsize - size, 0)));
4593 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4594 build_int_2 (rsize, 0)));
4596 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
4597 TREE_SIDE_EFFECTS (incr) = 1;
4598 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
4600 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
4604 addr_rtx = force_reg (Pmode, addr_rtx);
4605 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
4606 MEM_ALIAS_SET (addr_rtx) = get_varargs_alias_set ();
4612 /* Return the string to output a conditional branch to LABEL, which is
4613 the operand number of the label. OP is the conditional expression.
4614 XEXP (OP, 0) is assumed to be a condition code register (integer or
4615 floating point) and its mode specifies what kind of comparison we made.
4617 REVERSED is non-zero if we should reverse the sense of the comparison.
4619 ANNUL is non-zero if we should generate an annulling branch.
4621 NOOP is non-zero if we have to follow this branch by a noop.
4623 INSN, if set, is the insn. */
4626 output_cbranch (op, label, reversed, annul, noop, insn)
4629 int reversed, annul, noop;
4632 static char string[32];
4633 enum rtx_code code = GET_CODE (op);
4634 rtx cc_reg = XEXP (op, 0);
4635 enum machine_mode mode = GET_MODE (cc_reg);
4636 static char v8_labelno[] = "%lX";
4637 static char v9_icc_labelno[] = "%%icc, %lX";
4638 static char v9_xcc_labelno[] = "%%xcc, %lX";
4639 static char v9_fcc_labelno[] = "%%fccX, %lY";
4642 int labeloff, spaces = 8;
4644 /* ??? !v9: FP branches cannot be preceded by another floating point insn.
4645 Because there is currently no concept of pre-delay slots, we can fix
4646 this only by always emitting a nop before a floating point branch. */
4648 if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9)
4649 strcpy (string, "nop\n\t");
4655 /* Reversal of FP compares takes care -- an ordered compare
4656 becomes an unordered compare and vice versa. */
4657 if (mode == CCFPmode || mode == CCFPEmode)
4692 /* ??? We don't have a "less or greater" rtx code. */
4707 code = reverse_condition (code);
4710 /* Start by writing the branch condition. */
4711 if (mode == CCFPmode || mode == CCFPEmode)
4770 if (mode == CC_NOOVmode)
4782 if (mode == CC_NOOVmode)
4803 strcpy (string, branch);
4804 spaces -= strlen (branch);
4806 /* Now add the annulling, the label, and a possible noop. */
4809 strcat (string, ",a");
4816 labelno = v8_labelno;
4822 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
4825 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
4830 if (mode == CCFPmode || mode == CCFPEmode)
4833 labelno = v9_fcc_labelno;
4834 /* Set the char indicating the number of the fcc reg to use. */
4835 labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
4837 else if (mode == CCXmode || mode == CCX_NOOVmode)
4838 labelno = v9_xcc_labelno;
4840 labelno = v9_icc_labelno;
4842 /* Set the char indicating the number of the operand containing the
4844 labelno[labeloff] = label + '0';
4846 strcat (string, "\t");
4848 strcat (string, " ");
4849 strcat (string, labelno);
4852 strcat (string, "\n\tnop");
4857 /* Emit a library call comparison between floating point X and Y.
4858 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
4859 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
4860 values as arguments instead of the TFmode registers themselves,
4861 that's why we cannot call emit_float_lib_cmp. */
4863 sparc_emit_float_lib_cmp (x, y, comparison)
4865 enum rtx_code comparison;
4868 rtx slot0, slot1, result;
4901 if (GET_CODE (x) != MEM)
4903 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
4904 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
4907 if (GET_CODE (y) != MEM)
4909 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
4910 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
4913 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, qpfunc), 1,
4915 XEXP (slot0, 0), Pmode,
4916 XEXP (slot1, 0), Pmode);
4918 /* Immediately move the result of the libcall into a pseudo
4919 register so reload doesn't clobber the value if it needs
4920 the return register for a spill reg. */
4921 result = gen_reg_rtx (DImode);
4922 emit_move_insn (result, hard_libcall_value (DImode));
4924 emit_cmp_insn (result, const0_rtx, comparison,
4925 NULL_RTX, DImode, 0, 0);
4928 /* Return the string to output a conditional branch to LABEL, testing
4929 register REG. LABEL is the operand number of the label; REG is the
4930 operand number of the reg. OP is the conditional expression. The mode
4931 of REG says what kind of comparison we made.
4933 REVERSED is non-zero if we should reverse the sense of the comparison.
4935 ANNUL is non-zero if we should generate an annulling branch.
4937 NOOP is non-zero if we have to follow this branch by a noop. */
4940 output_v9branch (op, reg, label, reversed, annul, noop, insn)
4943 int reversed, annul, noop;
4946 static char string[20];
4947 enum rtx_code code = GET_CODE (op);
4948 enum machine_mode mode = GET_MODE (XEXP (op, 0));
4949 static char labelno[] = "%X, %lX";
4953 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4955 code = reverse_condition (code), reversed = 0;
4957 /* Only 64 bit versions of these instructions exist. */
4961 /* Start by writing the branch condition. */
4966 strcpy (string, "brnz");
4971 strcpy (string, "brz");
4976 strcpy (string, "brgez");
4981 strcpy (string, "brlz");
4986 strcpy (string, "brlez");
4991 strcpy (string, "brgz");
4999 /* Now add the annulling, reg, label, and nop. */
5002 strcat (string, ",a");
5006 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
5009 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
5013 labelno[1] = reg + '0';
5014 labelno[6] = label + '0';
5016 strcat (string, "\t");
5018 strcat (string, " ");
5019 strcat (string, labelno);
5022 strcat (string, "\n\tnop");
5027 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
5028 Such instructions cannot be used in the delay slot of return insn on v9.
5029 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
5033 epilogue_renumber (where, test)
5034 register rtx *where;
5037 register const char *fmt;
5039 register enum rtx_code code;
5044 code = GET_CODE (*where);
5049 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
5051 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
5052 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
5064 fmt = GET_RTX_FORMAT (code);
5066 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5071 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5072 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
5075 else if (fmt[i] == 'e'
5076 && epilogue_renumber (&(XEXP (*where, i)), test))
5082 /* Output assembler code to return from a function. */
5085 output_return (operands)
5088 rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0;
5092 operands[0] = leaf_label;
5095 else if (current_function_uses_only_leaf_regs)
5097 /* No delay slot in a leaf function. */
5101 /* If we didn't allocate a frame pointer for the current function,
5102 the stack pointer might have been adjusted. Output code to
5105 operands[0] = GEN_INT (actual_fsize);
5107 /* Use sub of negated value in first two cases instead of add to
5108 allow actual_fsize == 4096. */
5110 if (actual_fsize <= 4096)
5112 if (SKIP_CALLERS_UNIMP_P)
5113 return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
5115 return "retl\n\tsub\t%%sp, -%0, %%sp";
5117 else if (actual_fsize <= 8192)
5119 operands[0] = GEN_INT (actual_fsize - 4096);
5120 if (SKIP_CALLERS_UNIMP_P)
5121 return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
5123 return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
5125 else if (SKIP_CALLERS_UNIMP_P)
5127 if ((actual_fsize & 0x3ff) != 0)
5128 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
5130 return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
5134 if ((actual_fsize & 0x3ff) != 0)
5135 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
5137 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
5144 epilogue_renumber (&SET_DEST (PATTERN (delay)), 0);
5145 epilogue_renumber (&SET_SRC (PATTERN (delay)), 0);
5147 if (SKIP_CALLERS_UNIMP_P)
5148 return "return\t%%i7+12%#";
5150 return "return\t%%i7+8%#";
5156 if (SKIP_CALLERS_UNIMP_P)
5157 return "jmp\t%%i7+12\n\trestore";
5159 return "ret\n\trestore";
5163 /* Leaf functions and non-leaf functions have different needs. */
5166 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
5169 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
5171 static int *reg_alloc_orders[] = {
5172 reg_leaf_alloc_order,
5173 reg_nonleaf_alloc_order};
5176 order_regs_for_local_alloc ()
5178 static int last_order_nonleaf = 1;
5180 if (regs_ever_live[15] != last_order_nonleaf)
5182 last_order_nonleaf = !last_order_nonleaf;
5183 bcopy ((char *) reg_alloc_orders[last_order_nonleaf],
5184 (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int));
5188 /* Return 1 if REG and MEM are legitimate enough to allow the various
5189 mem<-->reg splits to be run. */
5192 sparc_splitdi_legitimate (reg, mem)
5196 /* Punt if we are here by mistake. */
5197 if (! reload_completed)
5200 /* We must have an offsettable memory reference. */
5201 if (! offsettable_memref_p (mem))
5204 /* If we have legitimate args for ldd/std, we do not want
5205 the split to happen. */
5206 if ((REGNO (reg) % 2) == 0
5207 && mem_min_alignment (mem, 8))
5214 /* Return 1 if x and y are some kind of REG and they refer to
5215 different hard registers. This test is guarenteed to be
5216 run after reload. */
5219 sparc_absnegfloat_split_legitimate (x, y)
5222 if (GET_CODE (x) == SUBREG)
5223 x = alter_subreg (x);
5224 if (GET_CODE (x) != REG)
5226 if (GET_CODE (y) == SUBREG)
5227 y = alter_subreg (y);
5228 if (GET_CODE (y) != REG)
5230 if (REGNO (x) == REGNO (y))
5235 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
5236 This makes them candidates for using ldd and std insns.
5238 Note reg1 and reg2 *must* be hard registers. */
5241 registers_ok_for_ldd_peep (reg1, reg2)
5244 /* We might have been passed a SUBREG. */
5245 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
5248 if (REGNO (reg1) % 2 != 0)
5251 /* Integer ldd is deprecated in SPARC V9 */
5252 if (TARGET_V9 && REGNO (reg1) < 32)
5255 return (REGNO (reg1) == REGNO (reg2) - 1);
5258 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
5261 This can only happen when addr1 and addr2 are consecutive memory
5262 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
5263 64 bit boundary (addr1 % 8 == 0).
5265 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
5266 registers are assumed to *never* be properly aligned and are
5269 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
5270 need only check that the offset for addr1 % 8 == 0. */
5273 addrs_ok_for_ldd_peep (addr1, addr2)
5278 /* Extract a register number and offset (if used) from the first addr. */
5279 if (GET_CODE (addr1) == PLUS)
5281 /* If not a REG, return zero. */
5282 if (GET_CODE (XEXP (addr1, 0)) != REG)
5286 reg1 = REGNO (XEXP (addr1, 0));
5287 /* The offset must be constant! */
5288 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
5290 offset1 = INTVAL (XEXP (addr1, 1));
5293 else if (GET_CODE (addr1) != REG)
5297 reg1 = REGNO (addr1);
5298 /* This was a simple (mem (reg)) expression. Offset is 0. */
5302 /* Make sure the second address is a (mem (plus (reg) (const_int). */
5303 if (GET_CODE (addr2) != PLUS)
5306 if (GET_CODE (XEXP (addr2, 0)) != REG
5307 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
5310 /* Only %fp and %sp are allowed. Additionally both addresses must
5311 use the same register. */
5312 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
5315 if (reg1 != REGNO (XEXP (addr2, 0)))
5318 /* The first offset must be evenly divisible by 8 to ensure the
5319 address is 64 bit aligned. */
5320 if (offset1 % 8 != 0)
5323 /* The offset for the second addr must be 4 more than the first addr. */
5324 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
5327 /* All the tests passed. addr1 and addr2 are valid for ldd and std
5332 /* Return 1 if reg is a pseudo, or is the first register in
5333 a hard register pair. This makes it a candidate for use in
5334 ldd and std insns. */
5337 register_ok_for_ldd (reg)
5340 /* We might have been passed a SUBREG. */
5341 if (GET_CODE (reg) != REG)
5344 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
5345 return (REGNO (reg) % 2 == 0);
5350 /* Print operand X (an rtx) in assembler syntax to file FILE.
5351 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
5352 For `%' followed by punctuation, CODE is the punctuation and X is null. */
5355 print_operand (file, x, code)
5363 /* Output a 'nop' if there's nothing for the delay slot. */
5364 if (dbr_sequence_length () == 0)
5365 fputs ("\n\t nop", file);
5368 /* Output an annul flag if there's nothing for the delay slot and we
5369 are optimizing. This is always used with '(' below. */
5370 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
5371 this is a dbx bug. So, we only do this when optimizing. */
5372 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
5373 Always emit a nop in case the next instruction is a branch. */
5374 if (dbr_sequence_length () == 0
5375 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
5379 /* Output a 'nop' if there's nothing for the delay slot and we are
5380 not optimizing. This is always used with '*' above. */
5381 if (dbr_sequence_length () == 0
5382 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
5383 fputs ("\n\t nop", file);
5386 /* Output the Embedded Medium/Anywhere code model base register. */
5387 fputs (EMBMEDANY_BASE_REG, file);
5390 /* Print out what we are using as the frame pointer. This might
5391 be %fp, or might be %sp+offset. */
5392 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
5393 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
5396 /* Adjust the operand to take into account a RESTORE operation. */
5397 if (GET_CODE (x) == CONST_INT)
5399 else if (GET_CODE (x) != REG)
5400 output_operand_lossage ("Invalid %%Y operand");
5401 else if (REGNO (x) < 8)
5402 fputs (reg_names[REGNO (x)], file);
5403 else if (REGNO (x) >= 24 && REGNO (x) < 32)
5404 fputs (reg_names[REGNO (x)-16], file);
5406 output_operand_lossage ("Invalid %%Y operand");
5409 /* Print out the low order register name of a register pair. */
5410 if (WORDS_BIG_ENDIAN)
5411 fputs (reg_names[REGNO (x)+1], file);
5413 fputs (reg_names[REGNO (x)], file);
5416 /* Print out the high order register name of a register pair. */
5417 if (WORDS_BIG_ENDIAN)
5418 fputs (reg_names[REGNO (x)], file);
5420 fputs (reg_names[REGNO (x)+1], file);
5423 /* Print out the second register name of a register pair or quad.
5424 I.e., R (%o0) => %o1. */
5425 fputs (reg_names[REGNO (x)+1], file);
5428 /* Print out the third register name of a register quad.
5429 I.e., S (%o0) => %o2. */
5430 fputs (reg_names[REGNO (x)+2], file);
5433 /* Print out the fourth register name of a register quad.
5434 I.e., T (%o0) => %o3. */
5435 fputs (reg_names[REGNO (x)+3], file);
5438 /* Print a condition code register. */
5439 if (REGNO (x) == SPARC_ICC_REG)
5441 /* We don't handle CC[X]_NOOVmode because they're not supposed
5443 if (GET_MODE (x) == CCmode)
5444 fputs ("%icc", file);
5445 else if (GET_MODE (x) == CCXmode)
5446 fputs ("%xcc", file);
5451 /* %fccN register */
5452 fputs (reg_names[REGNO (x)], file);
5455 /* Print the operand's address only. */
5456 output_address (XEXP (x, 0));
5459 /* In this case we need a register. Use %g0 if the
5460 operand is const0_rtx. */
5462 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
5464 fputs ("%g0", file);
5471 switch (GET_CODE (x))
5473 case IOR: fputs ("or", file); break;
5474 case AND: fputs ("and", file); break;
5475 case XOR: fputs ("xor", file); break;
5476 default: output_operand_lossage ("Invalid %%A operand");
5481 switch (GET_CODE (x))
5483 case IOR: fputs ("orn", file); break;
5484 case AND: fputs ("andn", file); break;
5485 case XOR: fputs ("xnor", file); break;
5486 default: output_operand_lossage ("Invalid %%B operand");
5490 /* These are used by the conditional move instructions. */
5494 enum rtx_code rc = (code == 'c'
5495 ? reverse_condition (GET_CODE (x))
5499 case NE: fputs ("ne", file); break;
5500 case EQ: fputs ("e", file); break;
5501 case GE: fputs ("ge", file); break;
5502 case GT: fputs ("g", file); break;
5503 case LE: fputs ("le", file); break;
5504 case LT: fputs ("l", file); break;
5505 case GEU: fputs ("geu", file); break;
5506 case GTU: fputs ("gu", file); break;
5507 case LEU: fputs ("leu", file); break;
5508 case LTU: fputs ("lu", file); break;
5509 default: output_operand_lossage (code == 'c'
5510 ? "Invalid %%c operand"
5511 : "Invalid %%C operand");
5516 /* These are used by the movr instruction pattern. */
5520 enum rtx_code rc = (code == 'd'
5521 ? reverse_condition (GET_CODE (x))
5525 case NE: fputs ("ne", file); break;
5526 case EQ: fputs ("e", file); break;
5527 case GE: fputs ("gez", file); break;
5528 case LT: fputs ("lz", file); break;
5529 case LE: fputs ("lez", file); break;
5530 case GT: fputs ("gz", file); break;
5531 default: output_operand_lossage (code == 'd'
5532 ? "Invalid %%d operand"
5533 : "Invalid %%D operand");
5540 /* Print a sign-extended character. */
5541 int i = INTVAL (x) & 0xff;
5544 fprintf (file, "%d", i);
5549 /* Operand must be a MEM; write its address. */
5550 if (GET_CODE (x) != MEM)
5551 output_operand_lossage ("Invalid %%f operand");
5552 output_address (XEXP (x, 0));
5556 /* Do nothing special. */
5560 /* Undocumented flag. */
5561 output_operand_lossage ("invalid operand output code");
5564 if (GET_CODE (x) == REG)
5565 fputs (reg_names[REGNO (x)], file);
5566 else if (GET_CODE (x) == MEM)
5569 /* Poor Sun assembler doesn't understand absolute addressing. */
5570 if (CONSTANT_P (XEXP (x, 0))
5571 && ! TARGET_LIVE_G0)
5572 fputs ("%g0+", file);
5573 output_address (XEXP (x, 0));
5576 else if (GET_CODE (x) == HIGH)
5578 fputs ("%hi(", file);
5579 output_addr_const (file, XEXP (x, 0));
5582 else if (GET_CODE (x) == LO_SUM)
5584 print_operand (file, XEXP (x, 0), 0);
5585 if (TARGET_CM_MEDMID)
5586 fputs ("+%l44(", file);
5588 fputs ("+%lo(", file);
5589 output_addr_const (file, XEXP (x, 1));
5592 else if (GET_CODE (x) == CONST_DOUBLE
5593 && (GET_MODE (x) == VOIDmode
5594 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
5596 if (CONST_DOUBLE_HIGH (x) == 0)
5597 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
5598 else if (CONST_DOUBLE_HIGH (x) == -1
5599 && CONST_DOUBLE_LOW (x) < 0)
5600 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
5602 output_operand_lossage ("long long constant not a valid immediate operand");
5604 else if (GET_CODE (x) == CONST_DOUBLE)
5605 output_operand_lossage ("floating point constant not a valid immediate operand");
5606 else { output_addr_const (file, x); }
5609 /* This function outputs assembler code for VALUE to FILE, where VALUE is
5610 a 64 bit (DImode) value. */
5612 /* ??? If there is a 64 bit counterpart to .word that the assembler
5613 understands, then using that would simply this code greatly. */
5614 /* ??? We only output .xword's for symbols and only then in environments
5615 where the assembler can handle them. */
5618 output_double_int (file, value)
5622 if (GET_CODE (value) == CONST_INT)
5624 /* ??? This has endianness issues. */
5625 #if HOST_BITS_PER_WIDE_INT == 64
5626 HOST_WIDE_INT xword = INTVAL (value);
5627 HOST_WIDE_INT high, low;
5629 high = (xword >> 32) & 0xffffffff;
5630 low = xword & 0xffffffff;
5631 ASM_OUTPUT_INT (file, GEN_INT (high));
5632 ASM_OUTPUT_INT (file, GEN_INT (low));
5634 if (INTVAL (value) < 0)
5635 ASM_OUTPUT_INT (file, constm1_rtx);
5637 ASM_OUTPUT_INT (file, const0_rtx);
5638 ASM_OUTPUT_INT (file, value);
5641 else if (GET_CODE (value) == CONST_DOUBLE)
5643 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value)));
5644 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value)));
5646 else if (GET_CODE (value) == SYMBOL_REF
5647 || GET_CODE (value) == CONST
5648 || GET_CODE (value) == PLUS
5649 || (TARGET_ARCH64 &&
5650 (GET_CODE (value) == LABEL_REF
5651 || GET_CODE (value) == CODE_LABEL
5652 || GET_CODE (value) == MINUS)))
5656 ASM_OUTPUT_INT (file, const0_rtx);
5657 ASM_OUTPUT_INT (file, value);
5661 fprintf (file, "\t%s\t", ASM_LONGLONG);
5662 output_addr_const (file, value);
5663 fprintf (file, "\n");
5670 /* Return the value of a code used in the .proc pseudo-op that says
5671 what kind of result this function returns. For non-C types, we pick
5672 the closest C type. */
5674 #ifndef CHAR_TYPE_SIZE
5675 #define CHAR_TYPE_SIZE BITS_PER_UNIT
5678 #ifndef SHORT_TYPE_SIZE
5679 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
5682 #ifndef INT_TYPE_SIZE
5683 #define INT_TYPE_SIZE BITS_PER_WORD
5686 #ifndef LONG_TYPE_SIZE
5687 #define LONG_TYPE_SIZE BITS_PER_WORD
5690 #ifndef LONG_LONG_TYPE_SIZE
5691 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
5694 #ifndef FLOAT_TYPE_SIZE
5695 #define FLOAT_TYPE_SIZE BITS_PER_WORD
5698 #ifndef DOUBLE_TYPE_SIZE
5699 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5702 #ifndef LONG_DOUBLE_TYPE_SIZE
5703 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5707 sparc_type_code (type)
5710 register unsigned long qualifiers = 0;
5711 register unsigned shift;
5713 /* Only the first 30 bits of the qualifier are valid. We must refrain from
5714 setting more, since some assemblers will give an error for this. Also,
5715 we must be careful to avoid shifts of 32 bits or more to avoid getting
5716 unpredictable results. */
5718 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
5720 switch (TREE_CODE (type))
5726 qualifiers |= (3 << shift);
5731 qualifiers |= (2 << shift);
5735 case REFERENCE_TYPE:
5737 qualifiers |= (1 << shift);
5741 return (qualifiers | 8);
5744 case QUAL_UNION_TYPE:
5745 return (qualifiers | 9);
5748 return (qualifiers | 10);
5751 return (qualifiers | 16);
5754 /* If this is a range type, consider it to be the underlying
5756 if (TREE_TYPE (type) != 0)
5759 /* Carefully distinguish all the standard types of C,
5760 without messing up if the language is not C. We do this by
5761 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
5762 look at both the names and the above fields, but that's redundant.
5763 Any type whose size is between two C types will be considered
5764 to be the wider of the two types. Also, we do not have a
5765 special code to use for "long long", so anything wider than
5766 long is treated the same. Note that we can't distinguish
5767 between "int" and "long" in this code if they are the same
5768 size, but that's fine, since neither can the assembler. */
5770 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
5771 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
5773 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
5774 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
5776 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
5777 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
5780 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
5783 /* If this is a range type, consider it to be the underlying
5785 if (TREE_TYPE (type) != 0)
5788 /* Carefully distinguish all the standard types of C,
5789 without messing up if the language is not C. */
5791 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
5792 return (qualifiers | 6);
5795 return (qualifiers | 7);
5797 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
5798 /* ??? We need to distinguish between double and float complex types,
5799 but I don't know how yet because I can't reach this code from
5800 existing front-ends. */
5801 return (qualifiers | 7); /* Who knows? */
5803 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
5804 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
5805 case FILE_TYPE: /* GNU Pascal FILE type. */
5806 case SET_TYPE: /* GNU Pascal SET type. */
5807 case LANG_TYPE: /* ? */
5811 abort (); /* Not a type! */
5818 /* Nested function support. */
5820 /* Emit RTL insns to initialize the variable parts of a trampoline.
5821 FNADDR is an RTX for the address of the function's pure code.
5822 CXT is an RTX for the static chain value for the function.
5824 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
5825 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
5826 (to store insns). This is a bit excessive. Perhaps a different
5827 mechanism would be better here.
5829 Emit enough FLUSH insns to synchronize the data and instruction caches. */
5832 sparc_initialize_trampoline (tramp, fnaddr, cxt)
5833 rtx tramp, fnaddr, cxt;
5835 /* SPARC 32 bit trampoline:
5838 sethi %hi(static), %g2
5840 or %g2, %lo(static), %g2
5842 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
5843 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
5845 #ifdef TRANSFER_FROM_TRAMPOLINE
5846 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
5847 0, VOIDmode, 1, tramp, Pmode);
5850 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
5851 expand_binop (SImode, ior_optab,
5852 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
5853 size_int (10), 0, 1),
5854 GEN_INT (0x03000000),
5855 NULL_RTX, 1, OPTAB_DIRECT));
5857 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
5858 expand_binop (SImode, ior_optab,
5859 expand_shift (RSHIFT_EXPR, SImode, cxt,
5860 size_int (10), 0, 1),
5861 GEN_INT (0x05000000),
5862 NULL_RTX, 1, OPTAB_DIRECT));
5864 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
5865 expand_binop (SImode, ior_optab,
5866 expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX),
5867 GEN_INT (0x81c06000),
5868 NULL_RTX, 1, OPTAB_DIRECT));
5870 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
5871 expand_binop (SImode, ior_optab,
5872 expand_and (cxt, GEN_INT (0x3ff), NULL_RTX),
5873 GEN_INT (0x8410a000),
5874 NULL_RTX, 1, OPTAB_DIRECT));
5876 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
5877 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
5878 aligned on a 16 byte boundary so one flush clears it all. */
5879 if (sparc_cpu != PROCESSOR_ULTRASPARC)
5880 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
5881 plus_constant (tramp, 8)))));
5884 /* The 64 bit version is simpler because it makes more sense to load the
5885 values as "immediate" data out of the trampoline. It's also easier since
5886 we can read the PC without clobbering a register. */
5889 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
5890 rtx tramp, fnaddr, cxt;
5892 #ifdef TRANSFER_FROM_TRAMPOLINE
5893 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
5894 0, VOIDmode, 1, tramp, Pmode);
5905 emit_move_insn (gen_rtx_MEM (SImode, tramp),
5906 GEN_INT (0x83414000));
5907 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
5908 GEN_INT (0xca586018));
5909 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
5910 GEN_INT (0x81c14000));
5911 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
5912 GEN_INT (0xca586010));
5913 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
5914 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
5915 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
5917 if (sparc_cpu != PROCESSOR_ULTRASPARC)
5918 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
5921 /* Subroutines to support a flat (single) register window calling
5924 /* Single-register window sparc stack frames look like:
5926 Before call After call
5927 +-----------------------+ +-----------------------+
5929 mem | caller's temps. | | caller's temps. |
5931 +-----------------------+ +-----------------------+
5933 | arguments on stack. | | arguments on stack. |
5935 +-----------------------+FP+92->+-----------------------+
5936 | 6 words to save | | 6 words to save |
5937 | arguments passed | | arguments passed |
5938 | in registers, even | | in registers, even |
5939 | if not passed. | | if not passed. |
5940 SP+68->+-----------------------+FP+68->+-----------------------+
5941 | 1 word struct addr | | 1 word struct addr |
5942 +-----------------------+FP+64->+-----------------------+
5944 | 16 word reg save area | | 16 word reg save area |
5946 SP->+-----------------------+ FP->+-----------------------+
5948 | fp/alu reg moves |
5949 FP-16->+-----------------------+
5953 +-----------------------+
5955 | fp register save |
5957 +-----------------------+
5959 | gp register save |
5961 +-----------------------+
5963 | alloca allocations |
5965 +-----------------------+
5967 | arguments on stack |
5969 SP+92->+-----------------------+
5971 | arguments passed |
5972 | in registers, even |
5973 low | if not passed. |
5974 memory SP+68->+-----------------------+
5975 | 1 word struct addr |
5976 SP+64->+-----------------------+
5978 I 16 word reg save area |
5980 SP->+-----------------------+ */
5982 /* Structure to be filled in by sparc_flat_compute_frame_size with register
5983 save masks, and offsets for the current function. */
5985 struct sparc_frame_info
5987 unsigned long total_size; /* # bytes that the entire frame takes up. */
5988 unsigned long var_size; /* # bytes that variables take up. */
5989 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5990 unsigned long extra_size; /* # bytes of extra gunk. */
5991 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5992 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5993 unsigned long gmask; /* Mask of saved gp registers. */
5994 unsigned long fmask; /* Mask of saved fp registers. */
5995 unsigned long reg_offset; /* Offset from new sp to store regs. */
5996 int initialized; /* Nonzero if frame size already calculated. */
5999 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6000 struct sparc_frame_info current_frame_info;
6002 /* Zero structure to initialize current_frame_info. */
6003 struct sparc_frame_info zero_frame_info;
6005 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6007 #define RETURN_ADDR_REGNUM 15
6008 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
6009 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6011 #define MUST_SAVE_REGISTER(regno) \
6012 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6013 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
6014 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6016 /* Return the bytes needed to compute the frame pointer from the current
6020 sparc_flat_compute_frame_size (size)
6021 int size; /* # of var. bytes allocated. */
6024 unsigned long total_size; /* # bytes that the entire frame takes up. */
6025 unsigned long var_size; /* # bytes that variables take up. */
6026 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6027 unsigned long extra_size; /* # extra bytes. */
6028 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6029 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6030 unsigned long gmask; /* Mask of saved gp registers. */
6031 unsigned long fmask; /* Mask of saved fp registers. */
6032 unsigned long reg_offset; /* Offset to register save area. */
6033 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
6035 /* This is the size of the 16 word reg save area, 1 word struct addr
6036 area, and 4 word fp/alu register copy area. */
6037 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
6047 if (!leaf_function_p ())
6049 /* Also include the size needed for the 6 parameter registers. */
6050 args_size = current_function_outgoing_args_size + 24;
6052 total_size = var_size + args_size;
6054 /* Calculate space needed for gp registers. */
6055 for (regno = 1; regno <= 31; regno++)
6057 if (MUST_SAVE_REGISTER (regno))
6059 /* If we need to save two regs in a row, ensure there's room to bump
6060 up the address to align it to a doubleword boundary. */
6061 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
6063 if (gp_reg_size % 8 != 0)
6065 gp_reg_size += 2 * UNITS_PER_WORD;
6066 gmask |= 3 << regno;
6072 gp_reg_size += UNITS_PER_WORD;
6073 gmask |= 1 << regno;
6078 /* Calculate space needed for fp registers. */
6079 for (regno = 32; regno <= 63; regno++)
6081 if (regs_ever_live[regno] && !call_used_regs[regno])
6083 fp_reg_size += UNITS_PER_WORD;
6084 fmask |= 1 << (regno - 32);
6091 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
6092 /* Ensure save area is 8 byte aligned if we need it. */
6094 if (need_aligned_p && n != 0)
6096 total_size += 8 - n;
6097 reg_offset += 8 - n;
6099 total_size += gp_reg_size + fp_reg_size;
6102 /* If we must allocate a stack frame at all, we must also allocate
6103 room for register window spillage, so as to be binary compatible
6104 with libraries and operating systems that do not use -mflat. */
6106 total_size += extra_size;
6110 total_size = SPARC_STACK_ALIGN (total_size);
6112 /* Save other computed information. */
6113 current_frame_info.total_size = total_size;
6114 current_frame_info.var_size = var_size;
6115 current_frame_info.args_size = args_size;
6116 current_frame_info.extra_size = extra_size;
6117 current_frame_info.gp_reg_size = gp_reg_size;
6118 current_frame_info.fp_reg_size = fp_reg_size;
6119 current_frame_info.gmask = gmask;
6120 current_frame_info.fmask = fmask;
6121 current_frame_info.reg_offset = reg_offset;
6122 current_frame_info.initialized = reload_completed;
6124 /* Ok, we're done. */
6128 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
6131 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
6132 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
6133 [BASE_REG+OFFSET] will always be a valid address.
6135 WORD_OP is either "st" for save, "ld" for restore.
6136 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
6139 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
6140 doubleword_op, base_offset)
6142 const char *base_reg;
6143 unsigned int offset;
6144 unsigned long gmask;
6145 unsigned long fmask;
6146 const char *word_op;
6147 const char *doubleword_op;
6148 unsigned long base_offset;
6152 if (gmask == 0 && fmask == 0)
6155 /* Save registers starting from high to low. We've already saved the
6156 previous frame pointer and previous return address for the debugger's
6157 sake. The debugger allows us to not need a nop in the epilog if at least
6158 one register is reloaded in addition to return address. */
6162 for (regno = 1; regno <= 31; regno++)
6164 if ((gmask & (1L << regno)) != 0)
6166 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
6168 /* We can save two registers in a row. If we're not at a
6169 double word boundary, move to one.
6170 sparc_flat_compute_frame_size ensures there's room to do
6172 if (offset % 8 != 0)
6173 offset += UNITS_PER_WORD;
6175 if (word_op[0] == 's')
6177 fprintf (file, "\t%s\t%s, [%s+%d]\n",
6178 doubleword_op, reg_names[regno],
6180 if (dwarf2out_do_frame ())
6182 char *l = dwarf2out_cfi_label ();
6183 dwarf2out_reg_save (l, regno, offset + base_offset);
6185 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
6189 fprintf (file, "\t%s\t[%s+%d], %s\n",
6190 doubleword_op, base_reg, offset,
6193 offset += 2 * UNITS_PER_WORD;
6198 if (word_op[0] == 's')
6200 fprintf (file, "\t%s\t%s, [%s+%d]\n",
6201 word_op, reg_names[regno],
6203 if (dwarf2out_do_frame ())
6204 dwarf2out_reg_save ("", regno, offset + base_offset);
6207 fprintf (file, "\t%s\t[%s+%d], %s\n",
6208 word_op, base_reg, offset, reg_names[regno]);
6210 offset += UNITS_PER_WORD;
6218 for (regno = 32; regno <= 63; regno++)
6220 if ((fmask & (1L << (regno - 32))) != 0)
6222 if (word_op[0] == 's')
6224 fprintf (file, "\t%s\t%s, [%s+%d]\n",
6225 word_op, reg_names[regno],
6227 if (dwarf2out_do_frame ())
6228 dwarf2out_reg_save ("", regno, offset + base_offset);
6231 fprintf (file, "\t%s\t[%s+%d], %s\n",
6232 word_op, base_reg, offset, reg_names[regno]);
6234 offset += UNITS_PER_WORD;
6240 /* Set up the stack and frame (if desired) for the function. */
6243 sparc_flat_output_function_prologue (file, size)
6247 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
6248 unsigned long gmask = current_frame_info.gmask;
6250 sparc_output_scratch_registers (file);
6252 /* This is only for the human reader. */
6253 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
6254 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6256 current_frame_info.var_size,
6257 current_frame_info.gp_reg_size / 4,
6258 current_frame_info.fp_reg_size / 4,
6259 current_function_outgoing_args_size,
6260 current_frame_info.extra_size);
6262 size = SPARC_STACK_ALIGN (size);
6263 size = (! current_frame_info.initialized
6264 ? sparc_flat_compute_frame_size (size)
6265 : current_frame_info.total_size);
6267 /* These cases shouldn't happen. Catch them now. */
6268 if (size == 0 && (gmask || current_frame_info.fmask))
6271 /* Allocate our stack frame by decrementing %sp.
6272 At present, the only algorithm gdb can use to determine if this is a
6273 flat frame is if we always set %i7 if we set %sp. This can be optimized
6274 in the future by putting in some sort of debugging information that says
6275 this is a `flat' function. However, there is still the case of debugging
6276 code without such debugging information (including cases where most fns
6277 have such info, but there is one that doesn't). So, always do this now
6278 so we don't get a lot of code out there that gdb can't handle.
6279 If the frame pointer isn't needn't then that's ok - gdb won't be able to
6280 distinguish us from a non-flat function but there won't (and shouldn't)
6281 be any differences anyway. The return pc is saved (if necessary) right
6282 after %i7 so gdb won't have to look too far to find it. */
6285 unsigned int reg_offset = current_frame_info.reg_offset;
6286 const char *fp_str = reg_names[FRAME_POINTER_REGNUM];
6287 const char *t1_str = "%g1";
6289 /* Things get a little tricky if local variables take up more than ~4096
6290 bytes and outgoing arguments take up more than ~4096 bytes. When that
6291 happens, the register save area can't be accessed from either end of
6292 the frame. Handle this by decrementing %sp to the start of the gp
6293 register save area, save the regs, update %i7, and then set %sp to its
6294 final value. Given that we only have one scratch register to play
6295 with it is the cheapest solution, and it helps gdb out as it won't
6296 slow down recognition of flat functions.
6297 Don't change the order of insns emitted here without checking with
6298 the gdb folk first. */
6300 /* Is the entire register save area offsettable from %sp? */
6301 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
6305 fprintf (file, "\tadd\t%s, %d, %s\n",
6306 sp_str, -size, sp_str);
6307 if (gmask & FRAME_POINTER_MASK)
6309 fprintf (file, "\tst\t%s, [%s+%d]\n",
6310 fp_str, sp_str, reg_offset);
6311 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
6312 sp_str, -size, fp_str, ASM_COMMENT_START);
6318 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6319 size, t1_str, sp_str, t1_str, sp_str);
6320 if (gmask & FRAME_POINTER_MASK)
6322 fprintf (file, "\tst\t%s, [%s+%d]\n",
6323 fp_str, sp_str, reg_offset);
6324 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
6325 sp_str, t1_str, fp_str, ASM_COMMENT_START);
6329 if (dwarf2out_do_frame ())
6331 char *l = dwarf2out_cfi_label ();
6332 if (gmask & FRAME_POINTER_MASK)
6334 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
6335 reg_offset - 4 - size);
6336 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
6339 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
6341 if (gmask & RETURN_ADDR_MASK)
6343 fprintf (file, "\tst\t%s, [%s+%d]\n",
6344 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
6345 if (dwarf2out_do_frame ())
6346 dwarf2out_return_save ("", reg_offset - size);
6349 sparc_flat_save_restore (file, sp_str, reg_offset,
6350 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6351 current_frame_info.fmask,
6352 "st", "std", -size);
6356 /* Subtract %sp in two steps, but make sure there is always a
6357 64 byte register save area, and %sp is properly aligned. */
6358 /* Amount to decrement %sp by, the first time. */
6359 unsigned int size1 = ((size - reg_offset + 64) + 15) & -16;
6360 /* Offset to register save area from %sp. */
6361 unsigned int offset = size1 - (size - reg_offset);
6365 fprintf (file, "\tadd\t%s, %d, %s\n",
6366 sp_str, -size1, sp_str);
6367 if (gmask & FRAME_POINTER_MASK)
6369 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
6370 fp_str, sp_str, offset, sp_str, -size1, fp_str,
6377 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6378 size1, t1_str, sp_str, t1_str, sp_str);
6379 if (gmask & FRAME_POINTER_MASK)
6381 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
6382 fp_str, sp_str, offset, sp_str, t1_str, fp_str,
6387 if (dwarf2out_do_frame ())
6389 char *l = dwarf2out_cfi_label ();
6390 if (gmask & FRAME_POINTER_MASK)
6392 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
6393 offset - 4 - size1);
6394 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
6397 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
6399 if (gmask & RETURN_ADDR_MASK)
6401 fprintf (file, "\tst\t%s, [%s+%d]\n",
6402 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
6403 if (dwarf2out_do_frame ())
6404 /* offset - size1 == reg_offset - size
6405 if reg_offset were updated above like offset. */
6406 dwarf2out_return_save ("", offset - size1);
6409 sparc_flat_save_restore (file, sp_str, offset,
6410 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6411 current_frame_info.fmask,
6412 "st", "std", -size1);
6413 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6414 size - size1, t1_str, sp_str, t1_str, sp_str);
6415 if (dwarf2out_do_frame ())
6416 if (! (gmask & FRAME_POINTER_MASK))
6417 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
6421 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
6424 /* Do any necessary cleanup after a function to restore stack, frame,
6428 sparc_flat_output_function_epilogue (file, size)
6432 rtx epilogue_delay = current_function_epilogue_delay_list;
6433 int noepilogue = FALSE;
6435 /* This is only for the human reader. */
6436 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
6438 /* The epilogue does not depend on any registers, but the stack
6439 registers, so we assume that if we have 1 pending nop, it can be
6440 ignored, and 2 it must be filled (2 nops occur for integer
6441 multiply and divide). */
6443 size = SPARC_STACK_ALIGN (size);
6444 size = (!current_frame_info.initialized
6445 ? sparc_flat_compute_frame_size (size)
6446 : current_frame_info.total_size);
6448 if (size == 0 && epilogue_delay == 0)
6450 rtx insn = get_last_insn ();
6452 /* If the last insn was a BARRIER, we don't have to write any code
6453 because a jump (aka return) was put there. */
6454 if (GET_CODE (insn) == NOTE)
6455 insn = prev_nonnote_insn (insn);
6456 if (insn && GET_CODE (insn) == BARRIER)
6462 unsigned int reg_offset = current_frame_info.reg_offset;
6464 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
6465 const char *fp_str = reg_names[FRAME_POINTER_REGNUM];
6466 const char *t1_str = "%g1";
6468 /* In the reload sequence, we don't need to fill the load delay
6469 slots for most of the loads, also see if we can fill the final
6470 delay slot if not otherwise filled by the reload sequence. */
6473 fprintf (file, "\tset\t%d, %s\n", size, t1_str);
6475 if (frame_pointer_needed)
6478 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
6479 fp_str, t1_str, sp_str, ASM_COMMENT_START);
6481 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
6482 fp_str, size, sp_str, ASM_COMMENT_START);
6485 /* Is the entire register save area offsettable from %sp? */
6486 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
6492 /* Restore %sp in two steps, but make sure there is always a
6493 64 byte register save area, and %sp is properly aligned. */
6494 /* Amount to increment %sp by, the first time. */
6495 size1 = ((reg_offset - 64 - 16) + 15) & -16;
6496 /* Offset to register save area from %sp. */
6497 reg_offset = size1 - reg_offset;
6499 fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n",
6500 size1, t1_str, sp_str, t1_str, sp_str);
6503 /* We must restore the frame pointer and return address reg first
6504 because they are treated specially by the prologue output code. */
6505 if (current_frame_info.gmask & FRAME_POINTER_MASK)
6507 fprintf (file, "\tld\t[%s+%d], %s\n",
6508 sp_str, reg_offset, fp_str);
6511 if (current_frame_info.gmask & RETURN_ADDR_MASK)
6513 fprintf (file, "\tld\t[%s+%d], %s\n",
6514 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
6518 /* Restore any remaining saved registers. */
6519 sparc_flat_save_restore (file, sp_str, reg_offset,
6520 current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6521 current_frame_info.fmask,
6524 /* If we had to increment %sp in two steps, record it so the second
6525 restoration in the epilogue finishes up. */
6530 fprintf (file, "\tset\t%d, %s\n",
6534 if (current_function_returns_struct)
6535 fprintf (file, "\tjmp\t%%o7+12\n");
6537 fprintf (file, "\tretl\n");
6539 /* If the only register saved is the return address, we need a
6540 nop, unless we have an instruction to put into it. Otherwise
6541 we don't since reloading multiple registers doesn't reference
6542 the register being loaded. */
6548 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
6551 else if (size > 4095)
6552 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
6555 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str);
6558 fprintf (file, "\tnop\n");
6561 /* Reset state info for each function. */
6562 current_frame_info = zero_frame_info;
6564 sparc_output_deferred_case_vectors ();
6567 /* Define the number of delay slots needed for the function epilogue.
6569 On the sparc, we need a slot if either no stack has been allocated,
6570 or the only register saved is the return register. */
6573 sparc_flat_epilogue_delay_slots ()
6575 if (!current_frame_info.initialized)
6576 (void) sparc_flat_compute_frame_size (get_frame_size ());
6578 if (current_frame_info.total_size == 0)
6584 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
6585 Any single length instruction which doesn't reference the stack or frame
6589 sparc_flat_eligible_for_epilogue_delay (trial, slot)
6591 int slot ATTRIBUTE_UNUSED;
6593 rtx pat = PATTERN (trial);
6595 if (get_attr_length (trial) != 1)
6598 /* If %g0 is live, there are lots of things we can't handle.
6599 Rather than trying to find them all now, let's punt and only
6600 optimize things as necessary. */
6604 if (! reg_mentioned_p (stack_pointer_rtx, pat)
6605 && ! reg_mentioned_p (frame_pointer_rtx, pat))
6611 /* Adjust the cost of a scheduling dependency. Return the new cost of
6612 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6615 supersparc_adjust_cost (insn, link, dep_insn, cost)
6621 enum attr_type insn_type;
6623 if (! recog_memoized (insn))
6626 insn_type = get_attr_type (insn);
6628 if (REG_NOTE_KIND (link) == 0)
6630 /* Data dependency; DEP_INSN writes a register that INSN reads some
6633 /* if a load, then the dependence must be on the memory address;
6634 add an extra "cycle". Note that the cost could be two cycles
6635 if the reg was written late in an instruction group; we ca not tell
6637 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
6640 /* Get the delay only if the address of the store is the dependence. */
6641 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
6643 rtx pat = PATTERN(insn);
6644 rtx dep_pat = PATTERN (dep_insn);
6646 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6647 return cost; /* This should not happen! */
6649 /* The dependency between the two instructions was on the data that
6650 is being stored. Assume that this implies that the address of the
6651 store is not dependent. */
6652 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6655 return cost + 3; /* An approximation. */
6658 /* A shift instruction cannot receive its data from an instruction
6659 in the same cycle; add a one cycle penalty. */
6660 if (insn_type == TYPE_SHIFT)
6661 return cost + 3; /* Split before cascade into shift. */
6665 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
6666 INSN writes some cycles later. */
6668 /* These are only significant for the fpu unit; writing a fp reg before
6669 the fpu has finished with it stalls the processor. */
6671 /* Reusing an integer register causes no problems. */
6672 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
6680 hypersparc_adjust_cost (insn, link, dep_insn, cost)
6686 enum attr_type insn_type, dep_type;
6687 rtx pat = PATTERN(insn);
6688 rtx dep_pat = PATTERN (dep_insn);
6690 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
6693 insn_type = get_attr_type (insn);
6694 dep_type = get_attr_type (dep_insn);
6696 switch (REG_NOTE_KIND (link))
6699 /* Data dependency; DEP_INSN writes a register that INSN reads some
6706 /* Get the delay iff the address of the store is the dependence. */
6707 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6710 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6717 /* If a load, then the dependence must be on the memory address. If
6718 the addresses aren't equal, then it might be a false dependency */
6719 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
6721 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
6722 || GET_CODE (SET_DEST (dep_pat)) != MEM
6723 || GET_CODE (SET_SRC (pat)) != MEM
6724 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
6725 XEXP (SET_SRC (pat), 0)))
6733 /* Compare to branch latency is 0. There is no benefit from
6734 separating compare and branch. */
6735 if (dep_type == TYPE_COMPARE)
6737 /* Floating point compare to branch latency is less than
6738 compare to conditional move. */
6739 if (dep_type == TYPE_FPCMP)
6748 /* Anti-dependencies only penalize the fpu unit. */
6749 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
6761 ultrasparc_adjust_cost (insn, link, dep_insn, cost)
6767 enum attr_type insn_type, dep_type;
6768 rtx pat = PATTERN(insn);
6769 rtx dep_pat = PATTERN (dep_insn);
6771 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
6774 insn_type = get_attr_type (insn);
6775 dep_type = get_attr_type (dep_insn);
6777 /* Nothing issues in parallel with integer multiplies, so
6778 mark as zero cost since the scheduler can not do anything
6780 if (insn_type == TYPE_IMUL)
6783 #define SLOW_FP(dep_type) \
6784 (dep_type == TYPE_FPSQRTS || dep_type == TYPE_FPSQRTD || \
6785 dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
6787 switch (REG_NOTE_KIND (link))
6790 /* Data dependency; DEP_INSN writes a register that INSN reads some
6793 if (dep_type == TYPE_CMOVE)
6795 /* Instructions that read the result of conditional moves cannot
6796 be in the same group or the following group. */
6802 /* UltraSPARC can dual issue a store and an instruction setting
6803 the value stored, except for divide and square root. */
6805 if (! SLOW_FP (dep_type))
6810 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6813 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6814 /* The dependency between the two instructions is on the data
6815 that is being stored. Assume that the address of the store
6816 is not also dependent. */
6823 /* A load does not return data until at least 11 cycles after
6824 a store to the same location. 3 cycles are accounted for
6825 in the load latency; add the other 8 here. */
6826 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
6828 /* If the addresses are not equal this may be a false
6829 dependency because pointer aliasing could not be
6830 determined. Add only 2 cycles in that case. 2 is
6831 an arbitrary compromise between 8, which would cause
6832 the scheduler to generate worse code elsewhere to
6833 compensate for a dependency which might not really
6835 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
6836 || GET_CODE (SET_SRC (pat)) != MEM
6837 || GET_CODE (SET_DEST (dep_pat)) != MEM
6838 || ! rtx_equal_p (XEXP (SET_SRC (pat), 0),
6839 XEXP (SET_DEST (dep_pat), 0)))
6847 /* Compare to branch latency is 0. There is no benefit from
6848 separating compare and branch. */
6849 if (dep_type == TYPE_COMPARE)
6851 /* Floating point compare to branch latency is less than
6852 compare to conditional move. */
6853 if (dep_type == TYPE_FPCMP)
6858 /* FMOVR class instructions can not issue in the same cycle
6859 or the cycle after an instruction which writes any
6860 integer register. Model this as cost 2 for dependent
6862 if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY
6863 || dep_type == TYPE_BINARY)
6866 /* Otherwise check as for integer conditional moves. */
6869 /* Conditional moves involving integer registers wait until
6870 3 cycles after loads return data. The interlock applies
6871 to all loads, not just dependent loads, but that is hard
6873 if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD)
6883 /* Divide and square root lock destination registers for full latency. */
6884 if (! SLOW_FP (dep_type))
6888 case REG_DEP_OUTPUT:
6889 /* IEU and FPU instruction that have the same destination
6890 register cannot be grouped together. */
6897 /* Other costs not accounted for:
6898 - Single precision floating point loads lock the other half of
6899 the even/odd register pair.
6900 - Several hazards associated with ldd/std are ignored because these
6901 instructions are rarely generated for V9.
6902 - The floating point pipeline can not have both a single and double
6903 precision operation active at the same time. Format conversions
6904 and graphics instructions are given honorary double precision status.
6905 - call and jmpl are always the first instruction in a group. */
6913 sparc_adjust_cost(insn, link, dep, cost)
6921 case PROCESSOR_SUPERSPARC:
6922 cost = supersparc_adjust_cost (insn, link, dep, cost);
6924 case PROCESSOR_HYPERSPARC:
6925 case PROCESSOR_SPARCLITE86X:
6926 cost = hypersparc_adjust_cost (insn, link, dep, cost);
6928 case PROCESSOR_ULTRASPARC:
6929 cost = ultrasparc_adjust_cost (insn, link, dep, cost);
6937 /* This describes the state of the UltraSPARC pipeline during
6938 instruction scheduling. */
6940 #define TMASK(__x) ((unsigned)1 << ((int)(__x)))
6941 #define UMASK(__x) ((unsigned)1 << ((int)(__x)))
6943 enum ultra_code { NONE=0, /* no insn at all */
6944 IEU0, /* shifts and conditional moves */
6945 IEU1, /* condition code setting insns, calls+jumps */
6946 IEUN, /* all other single cycle ieu insns */
6947 LSU, /* loads and stores */
6949 FPM, /* FPU pipeline 1, multiplies and divides */
6950 FPA, /* FPU pipeline 2, all other operations */
6951 SINGLE, /* single issue instructions */
6954 static enum ultra_code ultra_code_from_mask PARAMS ((int));
6955 static void ultra_schedule_insn PARAMS ((rtx *, rtx *, int, enum ultra_code));
6957 static const char *ultra_code_names[NUM_ULTRA_CODES] = {
6958 "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI",
6959 "FPM", "FPA", "SINGLE" };
6961 struct ultrasparc_pipeline_state {
6962 /* The insns in this group. */
6965 /* The code for each insn. */
6966 enum ultra_code codes[4];
6968 /* Which insns in this group have been committed by the
6969 scheduler. This is how we determine how many more
6970 can issue this cycle. */
6973 /* How many insns in this group. */
6976 /* Mask of free slots still in this group. */
6977 char free_slot_mask;
6979 /* The slotter uses the following to determine what other
6980 insn types can still make their way into this group. */
6981 char contents [NUM_ULTRA_CODES];
6985 #define ULTRA_NUM_HIST 8
6986 static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST];
6987 static int ultra_cur_hist;
6988 static int ultra_cycles_elapsed;
6990 #define ultra_pipe (ultra_pipe_hist[ultra_cur_hist])
6992 /* Given TYPE_MASK compute the ultra_code it has. */
6993 static enum ultra_code
6994 ultra_code_from_mask (type_mask)
6997 if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE)))
6999 else if (type_mask & (TMASK (TYPE_COMPARE) |
7001 TMASK (TYPE_UNCOND_BRANCH)))
7003 else if (type_mask & (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
7004 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY)))
7006 else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
7007 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
7008 TMASK (TYPE_FPSTORE)))
7010 else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) |
7011 TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRTS) |
7012 TMASK (TYPE_FPSQRTD)))
7014 else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
7015 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)))
7017 else if (type_mask & TMASK (TYPE_BRANCH))
7023 /* Check INSN (a conditional move) and make sure that it's
7024 results are available at this cycle. Return 1 if the
7025 results are in fact ready. */
7027 ultra_cmove_results_ready_p (insn)
7030 struct ultrasparc_pipeline_state *up;
7033 /* If this got dispatched in the previous
7034 group, the results are not ready. */
7035 entry = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1);
7036 up = &ultra_pipe_hist[entry];
7039 if (up->group[slot] == insn)
7045 /* Walk backwards in pipeline history looking for FPU
7046 operations which use a mode different than FPMODE and
7047 will create a stall if an insn using FPMODE were to be
7048 dispatched this cycle. */
7050 ultra_fpmode_conflict_exists (fpmode)
7051 enum machine_mode fpmode;
7056 hist_ent = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1);
7057 if (ultra_cycles_elapsed < 4)
7058 hist_lim = ultra_cycles_elapsed;
7061 while (hist_lim > 0)
7063 struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent];
7068 rtx insn = up->group[slot];
7069 enum machine_mode this_mode;
7073 || GET_CODE (insn) != INSN
7074 || (pat = PATTERN (insn)) == 0
7075 || GET_CODE (pat) != SET)
7078 this_mode = GET_MODE (SET_DEST (pat));
7079 if ((this_mode != SFmode
7080 && this_mode != DFmode)
7081 || this_mode == fpmode)
7084 /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then
7085 we will get a stall. Loads and stores are independant
7087 if (GET_CODE (SET_SRC (pat)) != ABS
7088 && GET_CODE (SET_SRC (pat)) != NEG
7089 && ((TMASK (get_attr_type (insn)) &
7090 (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) |
7091 TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRTS) |
7092 TMASK (TYPE_FPSQRTD) |
7093 TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0))
7097 hist_ent = (hist_ent - 1) & (ULTRA_NUM_HIST - 1);
7100 /* No conflicts, safe to dispatch. */
7104 /* Find an instruction in LIST which has one of the
7105 type attributes enumerated in TYPE_MASK. START
7106 says where to begin the search.
7108 NOTE: This scheme depends upon the fact that we
7109 have less than 32 distinct type attributes. */
7111 static int ultra_types_avail;
7114 ultra_find_type (type_mask, list, start)
7121 /* Short circuit if no such insn exists in the ready
7123 if ((type_mask & ultra_types_avail) == 0)
7126 for (i = start; i >= 0; i--)
7130 if (recog_memoized (insn) >= 0
7131 && (TMASK(get_attr_type (insn)) & type_mask))
7133 enum machine_mode fpmode = SFmode;
7136 int check_depend = 0;
7137 int check_fpmode_conflict = 0;
7139 if (GET_CODE (insn) == INSN
7140 && (pat = PATTERN(insn)) != 0
7141 && GET_CODE (pat) == SET
7142 && !(type_mask & (TMASK (TYPE_STORE) |
7143 TMASK (TYPE_FPSTORE))))
7146 if (GET_MODE (SET_DEST (pat)) == SFmode
7147 || GET_MODE (SET_DEST (pat)) == DFmode)
7149 fpmode = GET_MODE (SET_DEST (pat));
7150 check_fpmode_conflict = 1;
7157 rtx slot_insn = ultra_pipe.group[slot];
7160 /* Already issued, bad dependency, or FPU
7163 && (slot_pat = PATTERN (slot_insn)) != 0
7164 && ((insn == slot_insn)
7165 || (check_depend == 1
7166 && GET_CODE (slot_insn) == INSN
7167 && GET_CODE (slot_pat) == SET
7168 && ((GET_CODE (SET_DEST (slot_pat)) == REG
7169 && GET_CODE (SET_SRC (pat)) == REG
7170 && REGNO (SET_DEST (slot_pat)) ==
7171 REGNO (SET_SRC (pat)))
7172 || (GET_CODE (SET_DEST (slot_pat)) == SUBREG
7173 && GET_CODE (SET_SRC (pat)) == SUBREG
7174 && REGNO (SUBREG_REG (SET_DEST (slot_pat))) ==
7175 REGNO (SUBREG_REG (SET_SRC (pat)))
7176 && SUBREG_WORD (SET_DEST (slot_pat)) ==
7177 SUBREG_WORD (SET_SRC (pat)))))
7178 || (check_fpmode_conflict == 1
7179 && GET_CODE (slot_insn) == INSN
7180 && GET_CODE (slot_pat) == SET
7181 && (GET_MODE (SET_DEST (slot_pat)) == SFmode
7182 || GET_MODE (SET_DEST (slot_pat)) == DFmode)
7183 && GET_MODE (SET_DEST (slot_pat)) != fpmode)))
7187 /* Check for peculiar result availability and dispatch
7188 interference situations. */
7190 && ultra_cycles_elapsed > 0)
7194 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
7196 rtx link_insn = XEXP (link, 0);
7197 if (GET_CODE (link_insn) == INSN
7198 && recog_memoized (link_insn) >= 0
7199 && (TMASK (get_attr_type (link_insn)) &
7200 (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE)))
7201 && ! ultra_cmove_results_ready_p (link_insn))
7205 if (check_fpmode_conflict
7206 && ultra_fpmode_conflict_exists (fpmode))
7219 ultra_build_types_avail (ready, n_ready)
7223 int i = n_ready - 1;
7225 ultra_types_avail = 0;
7228 rtx insn = ready[i];
7230 if (recog_memoized (insn) >= 0)
7231 ultra_types_avail |= TMASK (get_attr_type (insn));
7237 /* Place insn pointed to my IP into the pipeline.
7238 Make element THIS of READY be that insn if it
7239 is not already. TYPE indicates the pipeline class
7240 this insn falls into. */
7242 ultra_schedule_insn (ip, ready, this, type)
7246 enum ultra_code type;
7249 char mask = ultra_pipe.free_slot_mask;
7252 /* Obtain free slot. */
7253 for (pipe_slot = 0; pipe_slot < 4; pipe_slot++)
7254 if ((mask & (1 << pipe_slot)) != 0)
7259 /* In it goes, and it hasn't been committed yet. */
7260 ultra_pipe.group[pipe_slot] = *ip;
7261 ultra_pipe.codes[pipe_slot] = type;
7262 ultra_pipe.contents[type] = 1;
7264 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
7265 ultra_pipe.num_ieu_insns += 1;
7267 ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot));
7268 ultra_pipe.group_size += 1;
7269 ultra_pipe.commit[pipe_slot] = 0;
7271 /* Update ready list. */
7273 while (ip != &ready[this])
7281 /* Advance to the next pipeline group. */
7283 ultra_flush_pipeline ()
7285 ultra_cur_hist = (ultra_cur_hist + 1) & (ULTRA_NUM_HIST - 1);
7286 ultra_cycles_elapsed += 1;
7287 bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
7288 ultra_pipe.free_slot_mask = 0xf;
7291 /* Init our data structures for this current block. */
7293 ultrasparc_sched_init (dump, sched_verbose)
7294 FILE *dump ATTRIBUTE_UNUSED;
7295 int sched_verbose ATTRIBUTE_UNUSED;
7297 bzero ((char *) ultra_pipe_hist, sizeof ultra_pipe_hist);
7299 ultra_cycles_elapsed = 0;
7300 ultra_pipe.free_slot_mask = 0xf;
7303 /* INSN has been scheduled, update pipeline commit state
7304 and return how many instructions are still to be
7305 scheduled in this group. */
7307 ultrasparc_variable_issue (insn)
7310 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7311 int i, left_to_fire;
7314 for (i = 0; i < 4; i++)
7316 if (up->group[i] == 0)
7319 if (up->group[i] == insn)
7323 else if (! up->commit[i])
7327 return left_to_fire;
7330 /* In actual_hazard_this_instance, we may have yanked some
7331 instructions from the ready list due to conflict cost
7332 adjustments. If so, and such an insn was in our pipeline
7333 group, remove it and update state. */
7335 ultra_rescan_pipeline_state (ready, n_ready)
7339 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7342 for (i = 0; i < 4; i++)
7344 rtx insn = up->group[i];
7350 /* If it has been committed, then it was removed from
7351 the ready list because it was actually scheduled,
7352 and that is not the case we are searching for here. */
7353 if (up->commit[i] != 0)
7356 for (j = n_ready - 1; j >= 0; j--)
7357 if (ready[j] == insn)
7360 /* If we didn't find it, toss it. */
7363 enum ultra_code ucode = up->codes[i];
7366 up->codes[i] = NONE;
7367 up->contents[ucode] = 0;
7369 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
7370 up->num_ieu_insns -= 1;
7372 up->free_slot_mask |= (1 << i);
7373 up->group_size -= 1;
7380 ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
7386 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7393 fprintf (dump, "\n;;\tUltraSPARC Looking at [");
7394 for (n = n_ready - 1; n >= 0; n--)
7396 rtx insn = ready[n];
7397 enum ultra_code ucode;
7399 if (recog_memoized (insn) < 0)
7401 ucode = ultra_code_from_mask (TMASK (get_attr_type (insn)));
7403 fprintf (dump, "%s(%d) ",
7404 ultra_code_names[ucode],
7407 fprintf (dump, "%s(%d)",
7408 ultra_code_names[ucode],
7411 fprintf (dump, "]\n");
7414 this_insn = n_ready - 1;
7416 /* Skip over junk we don't understand. */
7417 while ((this_insn >= 0)
7418 && recog_memoized (ready[this_insn]) < 0)
7421 ultra_build_types_avail (ready, this_insn + 1);
7423 while (this_insn >= 0) {
7424 int old_group_size = up->group_size;
7426 if (up->group_size != 0)
7430 num_committed = (up->commit[0] + up->commit[1] +
7431 up->commit[2] + up->commit[3]);
7432 /* If nothing has been commited from our group, or all of
7433 them have. Clear out the (current cycle's) pipeline
7434 state and start afresh. */
7435 if (num_committed == 0
7436 || num_committed == up->group_size)
7438 ultra_flush_pipeline ();
7444 /* OK, some ready list insns got requeued and thus removed
7445 from the ready list. Account for this fact. */
7446 ultra_rescan_pipeline_state (ready, n_ready);
7448 /* Something "changed", make this look like a newly
7449 formed group so the code at the end of the loop
7450 knows that progress was in fact made. */
7451 if (up->group_size != old_group_size)
7456 if (up->group_size == 0)
7458 /* If the pipeline is (still) empty and we have any single
7459 group insns, get them out now as this is a good time. */
7460 rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_ADDRESS) |
7461 TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) |
7462 TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)),
7466 ultra_schedule_insn (ip, ready, this_insn, SINGLE);
7470 /* If we are not in the process of emptying out the pipe, try to
7471 obtain an instruction which must be the first in it's group. */
7472 ip = ultra_find_type ((TMASK (TYPE_CALL) |
7473 TMASK (TYPE_CALL_NO_DELAY_SLOT) |
7474 TMASK (TYPE_UNCOND_BRANCH)),
7478 ultra_schedule_insn (ip, ready, this_insn, IEU1);
7481 else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) |
7482 TMASK (TYPE_FPDIVD) |
7483 TMASK (TYPE_FPSQRTS) |
7484 TMASK (TYPE_FPSQRTD)),
7485 ready, this_insn)) != 0)
7487 ultra_schedule_insn (ip, ready, this_insn, FPM);
7492 /* Try to fill the integer pipeline. First, look for an IEU0 specific
7493 operation. We can't do more IEU operations if the first 3 slots are
7494 all full or we have dispatched two IEU insns already. */
7495 if ((up->free_slot_mask & 0x7) != 0
7496 && up->num_ieu_insns < 2
7497 && up->contents[IEU0] == 0
7498 && up->contents[IEUN] == 0)
7500 rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn);
7503 ultra_schedule_insn (ip, ready, this_insn, IEU0);
7508 /* If we can, try to find an IEU1 specific or an unnamed
7510 if ((up->free_slot_mask & 0x7) != 0
7511 && up->num_ieu_insns < 2)
7513 rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
7514 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY) |
7515 (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)),
7521 ultra_schedule_insn (ip, ready, this_insn,
7522 (!up->contents[IEU1]
7523 && get_attr_type (insn) == TYPE_COMPARE)
7529 /* If only one IEU insn has been found, try to find another unnamed
7530 IEU operation or an IEU1 specific one. */
7531 if ((up->free_slot_mask & 0x7) != 0
7532 && up->num_ieu_insns < 2)
7535 int tmask = (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
7536 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY));
7538 if (!up->contents[IEU1])
7539 tmask |= TMASK (TYPE_COMPARE);
7540 ip = ultra_find_type (tmask, ready, this_insn);
7545 ultra_schedule_insn (ip, ready, this_insn,
7546 (!up->contents[IEU1]
7547 && get_attr_type (insn) == TYPE_COMPARE)
7553 /* Try for a load or store, but such an insn can only be issued
7554 if it is within' one of the first 3 slots. */
7555 if ((up->free_slot_mask & 0x7) != 0
7556 && up->contents[LSU] == 0)
7558 rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
7559 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
7560 TMASK (TYPE_FPSTORE)), ready, this_insn);
7563 ultra_schedule_insn (ip, ready, this_insn, LSU);
7568 /* Now find FPU operations, first FPM class. But not divisions or
7569 square-roots because those will break the group up. Unlike all
7570 the previous types, these can go in any slot. */
7571 if (up->free_slot_mask != 0
7572 && up->contents[FPM] == 0)
7574 rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn);
7577 ultra_schedule_insn (ip, ready, this_insn, FPM);
7582 /* Continue on with FPA class if we have not filled the group already. */
7583 if (up->free_slot_mask != 0
7584 && up->contents[FPA] == 0)
7586 rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
7587 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)),
7591 ultra_schedule_insn (ip, ready, this_insn, FPA);
7596 /* Finally, maybe stick a branch in here. */
7597 if (up->free_slot_mask != 0
7598 && up->contents[CTI] == 0)
7600 rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn);
7602 /* Try to slip in a branch only if it is one of the
7603 next 2 in the ready list. */
7604 if (ip && ((&ready[this_insn] - ip) < 2))
7606 ultra_schedule_insn (ip, ready, this_insn, CTI);
7612 for (i = 0; i < 4; i++)
7613 if ((up->free_slot_mask & (1 << i)) == 0)
7616 /* See if we made any progress... */
7617 if (old_group_size != up->group_size)
7620 /* Clean out the (current cycle's) pipeline state
7621 and try once more. If we placed no instructions
7622 into the pipeline at all, it means a real hard
7623 conflict exists with some earlier issued instruction
7624 so we must advance to the next cycle to clear it up. */
7625 if (up->group_size == 0)
7627 ultra_flush_pipeline ();
7632 bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
7633 ultra_pipe.free_slot_mask = 0xf;
7641 fprintf (dump, ";;\tUltraSPARC Launched [");
7642 gsize = up->group_size;
7643 for (n = 0; n < 4; n++)
7645 rtx insn = up->group[n];
7652 fprintf (dump, "%s(%d) ",
7653 ultra_code_names[up->codes[n]],
7656 fprintf (dump, "%s(%d)",
7657 ultra_code_names[up->codes[n]],
7660 fprintf (dump, "]\n");
7672 /* Assume V9 processors are capable of at least dual-issue. */
7674 case PROCESSOR_SUPERSPARC:
7676 case PROCESSOR_HYPERSPARC:
7677 case PROCESSOR_SPARCLITE86X:
7679 case PROCESSOR_ULTRASPARC:
7685 set_extends(x, insn)
7688 register rtx pat = PATTERN (insn);
7690 switch (GET_CODE (SET_SRC (pat)))
7692 /* Load and some shift instructions zero extend. */
7695 /* sethi clears the high bits */
7697 /* LO_SUM is used with sethi. sethi cleared the high
7698 bits and the values used with lo_sum are positive */
7700 /* Store flag stores 0 or 1 */
7710 rtx op1 = XEXP (SET_SRC (pat), 1);
7711 if (GET_CODE (op1) == CONST_INT)
7712 return INTVAL (op1) >= 0;
7713 if (GET_CODE (XEXP (SET_SRC (pat), 0)) == REG
7714 && sparc_check_64 (XEXP (SET_SRC (pat), 0), insn) == 1)
7716 if (GET_CODE (op1) == REG
7717 && sparc_check_64 ((op1), insn) == 1)
7722 return GET_MODE (SET_SRC (pat)) == SImode;
7723 /* Positive integers leave the high bits zero. */
7725 return ! (CONST_DOUBLE_LOW (x) & 0x80000000);
7727 return ! (INTVAL (x) & 0x80000000);
7730 return - (GET_MODE (SET_SRC (pat)) == SImode);
7736 /* We _ought_ to have only one kind per function, but... */
7737 static rtx sparc_addr_diff_list;
7738 static rtx sparc_addr_list;
7741 sparc_defer_case_vector (lab, vec, diff)
7745 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7747 sparc_addr_diff_list
7748 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7750 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7754 sparc_output_addr_vec (vec)
7757 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7758 int idx, vlen = XVECLEN (body, 0);
7760 #ifdef ASM_OUTPUT_ADDR_VEC_START
7761 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7764 #ifdef ASM_OUTPUT_CASE_LABEL
7765 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7768 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7771 for (idx = 0; idx < vlen; idx++)
7773 ASM_OUTPUT_ADDR_VEC_ELT
7774 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7777 #ifdef ASM_OUTPUT_ADDR_VEC_END
7778 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7783 sparc_output_addr_diff_vec (vec)
7786 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7787 rtx base = XEXP (XEXP (body, 0), 0);
7788 int idx, vlen = XVECLEN (body, 1);
7790 #ifdef ASM_OUTPUT_ADDR_VEC_START
7791 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7794 #ifdef ASM_OUTPUT_CASE_LABEL
7795 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7798 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7801 for (idx = 0; idx < vlen; idx++)
7803 ASM_OUTPUT_ADDR_DIFF_ELT
7806 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7807 CODE_LABEL_NUMBER (base));
7810 #ifdef ASM_OUTPUT_ADDR_VEC_END
7811 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7816 sparc_output_deferred_case_vectors ()
7821 if (sparc_addr_list == NULL_RTX
7822 && sparc_addr_diff_list == NULL_RTX)
7825 /* Align to cache line in the function's code section. */
7826 function_section (current_function_decl);
7828 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7830 ASM_OUTPUT_ALIGN (asm_out_file, align);
7832 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7833 sparc_output_addr_vec (XEXP (t, 0));
7834 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7835 sparc_output_addr_diff_vec (XEXP (t, 0));
7837 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7840 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7841 unknown. Return 1 if the high bits are zero, -1 if the register is
7844 sparc_check_64 (x, insn)
7847 /* If a register is set only once it is safe to ignore insns this
7848 code does not know how to handle. The loop will either recognize
7849 the single set and return the correct value or fail to recognize
7853 if (GET_CODE (x) == REG
7854 && flag_expensive_optimizations
7855 && REG_N_SETS (REGNO (x)) == 1)
7861 insn = get_last_insn_anywhere ();
7866 while ((insn = PREV_INSN (insn)))
7868 switch (GET_CODE (insn))
7881 rtx pat = PATTERN (insn);
7882 if (GET_CODE (pat) != SET)
7884 if (rtx_equal_p (x, SET_DEST (pat)))
7885 return set_extends (x, insn);
7886 if (reg_overlap_mentioned_p (SET_DEST (pat), x))
7895 sparc_v8plus_shift (operands, insn, opcode)
7900 static char asm_code[60];
7902 if (GET_CODE (operands[3]) == SCRATCH)
7903 operands[3] = operands[0];
7904 if (GET_CODE (operands[1]) == CONST_INT)
7906 output_asm_insn ("mov %1,%3", operands);
7910 output_asm_insn ("sllx %H1,32,%3", operands);
7911 if (sparc_check_64 (operands[1], insn) <= 0)
7912 output_asm_insn ("srl %L1,0,%L1", operands);
7913 output_asm_insn ("or %L1,%3,%3", operands);
7916 strcpy(asm_code, opcode);
7917 if (which_alternative != 2)
7918 return strcat (asm_code, " %0,%2,%L0\n\tsrlx %L0,32,%H0");
7920 return strcat (asm_code, " %3,%2,%3\n\tsrlx %3,32,%H0\n\tmov %3,%L0");
7924 /* Return 1 if DEST and SRC reference only global and in registers. */
7927 sparc_return_peephole_ok (dest, src)
7932 if (current_function_uses_only_leaf_regs)
7934 if (GET_CODE (src) != CONST_INT
7935 && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src)))
7937 return IN_OR_GLOBAL_P (dest);
7940 /* Output assembler code to FILE to increment profiler label # LABELNO
7941 for profiling a function entry.
7943 32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered
7944 during profiling so we need to save/restore it around the call to mcount.
7945 We're guaranteed that a save has just been done, and we use the space
7946 allocated for intreg/fpreg value passing. */
7949 sparc_function_profiler (file, labelno)
7954 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
7956 if (! TARGET_ARCH64)
7957 fputs ("\tst\t%g2,[%fp-4]\n", file);
7959 fputs ("\tsethi\t%hi(", file);
7960 assemble_name (file, buf);
7961 fputs ("),%o0\n", file);
7963 fputs ("\tcall\t", file);
7964 assemble_name (file, MCOUNT_FUNCTION);
7967 fputs ("\t or\t%o0,%lo(", file);
7968 assemble_name (file, buf);
7969 fputs ("),%o0\n", file);
7971 if (! TARGET_ARCH64)
7972 fputs ("\tld\t[%fp-4],%g2\n", file);
7976 /* The following macro shall output assembler code to FILE
7977 to initialize basic-block profiling.
7979 If profile_block_flag == 2
7981 Output code to call the subroutine `__bb_init_trace_func'
7982 and pass two parameters to it. The first parameter is
7983 the address of a block allocated in the object module.
7984 The second parameter is the number of the first basic block
7987 The name of the block is a local symbol made with this statement:
7989 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
7991 Of course, since you are writing the definition of
7992 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
7993 can take a short cut in the definition of this macro and use the
7994 name that you know will result.
7996 The number of the first basic block of the function is
7997 passed to the macro in BLOCK_OR_LABEL.
7999 If described in a virtual assembler language the code to be
8003 parameter2 <- BLOCK_OR_LABEL
8004 call __bb_init_trace_func
8006 else if profile_block_flag != 0
8008 Output code to call the subroutine `__bb_init_func'
8009 and pass one single parameter to it, which is the same
8010 as the first parameter to `__bb_init_trace_func'.
8012 The first word of this parameter is a flag which will be nonzero if
8013 the object module has already been initialized. So test this word
8014 first, and do not call `__bb_init_func' if the flag is nonzero.
8015 Note: When profile_block_flag == 2 the test need not be done
8016 but `__bb_init_trace_func' *must* be called.
8018 BLOCK_OR_LABEL may be used to generate a label number as a
8019 branch destination in case `__bb_init_func' will not be called.
8021 If described in a virtual assembler language the code to be
8033 sparc_function_block_profiler(file, block_or_label)
8038 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0);
8040 if (profile_block_flag == 2)
8042 fputs ("\tsethi\t%hi(", file);
8043 assemble_name (file, LPBX);
8044 fputs ("),%o0\n", file);
8046 fprintf (file, "\tsethi\t%%hi(%d),%%o1\n", block_or_label);
8048 fputs ("\tor\t%o0,%lo(", file);
8049 assemble_name (file, LPBX);
8050 fputs ("),%o0\n", file);
8052 fprintf (file, "\tcall\t%s__bb_init_trace_func\n", user_label_prefix);
8054 fprintf (file, "\t or\t%%o1,%%lo(%d),%%o1\n", block_or_label);
8056 else if (profile_block_flag != 0)
8059 ASM_GENERATE_INTERNAL_LABEL (LPBY, "LPBY", block_or_label);
8061 fputs ("\tsethi\t%hi(", file);
8062 assemble_name (file, LPBX);
8063 fputs ("),%o0\n", file);
8065 fputs ("\tld\t[%lo(", file);
8066 assemble_name (file, LPBX);
8067 fputs (")+%o0],%o1\n", file);
8069 fputs ("\ttst\t%o1\n", file);
8073 fputs ("\tbne,pn\t%icc,", file);
8074 assemble_name (file, LPBY);
8079 fputs ("\tbne\t", file);
8080 assemble_name (file, LPBY);
8084 fputs ("\t or\t%o0,%lo(", file);
8085 assemble_name (file, LPBX);
8086 fputs ("),%o0\n", file);
8088 fprintf (file, "\tcall\t%s__bb_init_func\n\t nop\n", user_label_prefix);
8090 ASM_OUTPUT_INTERNAL_LABEL (file, "LPBY", block_or_label);
8094 /* The following macro shall output assembler code to FILE
8095 to increment a counter associated with basic block number BLOCKNO.
8097 If profile_block_flag == 2
8099 Output code to initialize the global structure `__bb' and
8100 call the function `__bb_trace_func' which will increment the
8103 `__bb' consists of two words. In the first word the number
8104 of the basic block has to be stored. In the second word
8105 the address of a block allocated in the object module
8108 The basic block number is given by BLOCKNO.
8110 The address of the block is given by the label created with
8112 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
8114 by FUNCTION_BLOCK_PROFILER.
8116 Of course, since you are writing the definition of
8117 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
8118 can take a short cut in the definition of this macro and use the
8119 name that you know will result.
8121 If described in a virtual assembler language the code to be
8124 move BLOCKNO -> (__bb)
8125 move LPBX0 -> (__bb+4)
8126 call __bb_trace_func
8128 Note that function `__bb_trace_func' must not change the
8129 machine state, especially the flag register. To grant
8130 this, you must output code to save and restore registers
8131 either in this macro or in the macros MACHINE_STATE_SAVE
8132 and MACHINE_STATE_RESTORE. The last two macros will be
8133 used in the function `__bb_trace_func', so you must make
8134 sure that the function prologue does not change any
8135 register prior to saving it with MACHINE_STATE_SAVE.
8137 else if profile_block_flag != 0
8139 Output code to increment the counter directly.
8140 Basic blocks are numbered separately from zero within each
8141 compiled object module. The count associated with block number
8142 BLOCKNO is at index BLOCKNO in an array of words; the name of
8143 this array is a local symbol made with this statement:
8145 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
8147 Of course, since you are writing the definition of
8148 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
8149 can take a short cut in the definition of this macro and use the
8150 name that you know will result.
8152 If described in a virtual assembler language, the code to be
8155 inc (LPBX2+4*BLOCKNO)
8160 sparc_block_profiler(file, blockno)
8165 int bbreg = TARGET_ARCH64 ? 4 : 2;
8167 if (profile_block_flag == 2)
8169 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0);
8171 fprintf (file, "\tsethi\t%%hi(%s__bb),%%g1\n", user_label_prefix);
8172 fprintf (file, "\tsethi\t%%hi(%d),%%g%d\n", blockno, bbreg);
8173 fprintf (file, "\tor\t%%g1,%%lo(%s__bb),%%g1\n", user_label_prefix);
8174 fprintf (file, "\tor\t%%g%d,%%lo(%d),%%g%d\n", bbreg, blockno, bbreg);
8176 fprintf (file, "\tst\t%%g%d,[%%g1]\n", bbreg);
8178 fputs ("\tsethi\t%hi(", file);
8179 assemble_name (file, LPBX);
8180 fprintf (file, "),%%g%d\n", bbreg);
8182 fputs ("\tor\t%o2,%lo(", file);
8183 assemble_name (file, LPBX);
8184 fprintf (file, "),%%g%d\n", bbreg);
8186 fprintf (file, "\tst\t%%g%d,[%%g1+4]\n", bbreg);
8187 fprintf (file, "\tmov\t%%o7,%%g%d\n", bbreg);
8189 fprintf (file, "\tcall\t%s__bb_trace_func\n\t nop\n", user_label_prefix);
8191 fprintf (file, "\tmov\t%%g%d,%%o7\n", bbreg);
8193 else if (profile_block_flag != 0)
8195 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 2);
8197 fputs ("\tsethi\t%hi(", file);
8198 assemble_name (file, LPBX);
8199 fprintf (file, "+%d),%%g1\n", blockno*4);
8201 fputs ("\tld\t[%g1+%lo(", file);
8202 assemble_name (file, LPBX);
8203 if (TARGET_ARCH64 && USE_AS_OFFSETABLE_LO10)
8204 fprintf (file, ")+%d],%%g%d\n", blockno*4, bbreg);
8206 fprintf (file, "+%d)],%%g%d\n", blockno*4, bbreg);
8208 fprintf (file, "\tadd\t%%g%d,1,%%g%d\n", bbreg, bbreg);
8210 fprintf (file, "\tst\t%%g%d,[%%g1+%%lo(", bbreg);
8211 assemble_name (file, LPBX);
8212 if (TARGET_ARCH64 && USE_AS_OFFSETABLE_LO10)
8213 fprintf (file, ")+%d]\n", blockno*4);
8215 fprintf (file, "+%d)]\n", blockno*4);
8219 /* The following macro shall output assembler code to FILE
8220 to indicate a return from function during basic-block profiling.
8222 If profile_block_flag == 2:
8224 Output assembler code to call function `__bb_trace_ret'.
8226 Note that function `__bb_trace_ret' must not change the
8227 machine state, especially the flag register. To grant
8228 this, you must output code to save and restore registers
8229 either in this macro or in the macros MACHINE_STATE_SAVE_RET
8230 and MACHINE_STATE_RESTORE_RET. The last two macros will be
8231 used in the function `__bb_trace_ret', so you must make
8232 sure that the function prologue does not change any
8233 register prior to saving it with MACHINE_STATE_SAVE_RET.
8235 else if profile_block_flag != 0:
8237 The macro will not be used, so it need not distinguish
8242 sparc_function_block_profiler_exit(file)
8245 if (profile_block_flag == 2)
8246 fprintf (file, "\tcall\t%s__bb_trace_ret\n\t nop\n", user_label_prefix);
8251 /* Mark ARG, which is really a struct ultrasparc_pipline_state *, for
8255 mark_ultrasparc_pipeline_state (arg)
8258 struct ultrasparc_pipeline_state *ups;
8261 ups = (struct ultrasparc_pipeline_state *) arg;
8262 for (i = 0; i < sizeof (ups->group) / sizeof (rtx); ++i)
8263 ggc_mark_rtx (ups->group[i]);
8266 /* Called to register all of our global variables with the garbage
8270 sparc_add_gc_roots ()
8272 ggc_add_rtx_root (&sparc_compare_op0, 1);
8273 ggc_add_rtx_root (&sparc_compare_op1, 1);
8274 ggc_add_rtx_root (&leaf_label, 1);
8275 ggc_add_rtx_root (&global_offset_table, 1);
8276 ggc_add_rtx_root (&get_pc_symbol, 1);
8277 ggc_add_rtx_root (&sparc_addr_diff_list, 1);
8278 ggc_add_rtx_root (&sparc_addr_list, 1);
8279 ggc_add_root (ultra_pipe_hist,
8280 sizeof (ultra_pipe_hist) / sizeof (ultra_pipe_hist[0]),
8281 sizeof (ultra_pipe_hist[0]),
8282 &mark_ultrasparc_pipeline_state);