1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
49 #include "target-def.h"
50 #include "cfglayout.h"
52 /* 1 if the caller has placed an "unimp" insn immediately after the call.
53 This is used in v8 code when calling a function that returns a structure.
54 v9 doesn't have this. Be careful to have this test be the same as that
57 #define SKIP_CALLERS_UNIMP_P \
58 (!TARGET_ARCH64 && current_function_returns_struct \
59 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
60 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
63 /* Global variables for machine-dependent things. */
65 /* Size of frame. Need to know this to emit return insns from leaf procedures.
66 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
67 reload pass. This is important as the value is later used in insn
68 scheduling (to see what can go in a delay slot).
69 APPARENT_FSIZE is the size of the stack less the register save area and less
70 the outgoing argument area. It is used when saving call preserved regs. */
71 static int apparent_fsize;
72 static int actual_fsize;
74 /* Number of live general or floating point registers needed to be
75 saved (as 4-byte quantities). */
76 static int num_gfregs;
78 /* Save the operands last given to a compare for use when we
79 generate a scc or bcc insn. */
80 rtx sparc_compare_op0, sparc_compare_op1;
82 /* Coordinate with the md file wrt special insns created by
83 sparc_nonflat_function_epilogue. */
84 bool sparc_emitting_epilogue;
86 /* Vector to say how input registers are mapped to output registers.
87 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
88 eliminate it. You must use -fomit-frame-pointer to get that. */
89 char leaf_reg_remap[] =
90 { 0, 1, 2, 3, 4, 5, 6, 7,
91 -1, -1, -1, -1, -1, -1, 14, -1,
92 -1, -1, -1, -1, -1, -1, -1, -1,
93 8, 9, 10, 11, 12, 13, -1, 15,
95 32, 33, 34, 35, 36, 37, 38, 39,
96 40, 41, 42, 43, 44, 45, 46, 47,
97 48, 49, 50, 51, 52, 53, 54, 55,
98 56, 57, 58, 59, 60, 61, 62, 63,
99 64, 65, 66, 67, 68, 69, 70, 71,
100 72, 73, 74, 75, 76, 77, 78, 79,
101 80, 81, 82, 83, 84, 85, 86, 87,
102 88, 89, 90, 91, 92, 93, 94, 95,
103 96, 97, 98, 99, 100};
105 /* Vector, indexed by hard register number, which contains 1
106 for a register that is allowable in a candidate for leaf
107 function treatment. */
108 char sparc_leaf_regs[] =
109 { 1, 1, 1, 1, 1, 1, 1, 1,
110 0, 0, 0, 0, 0, 0, 1, 0,
111 0, 0, 0, 0, 0, 0, 0, 0,
112 1, 1, 1, 1, 1, 1, 0, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
120 1, 1, 1, 1, 1, 1, 1, 1,
123 struct machine_function GTY(())
125 /* Some local-dynamic TLS symbol name. */
126 const char *some_ld_name;
129 /* Name of where we pretend to think the frame pointer points.
130 Normally, this is "%fp", but if we are in a leaf procedure,
131 this is "%sp+something". We record "something" separately as it may be
132 too big for reg+constant addressing. */
134 static const char *frame_base_name;
135 static int frame_base_offset;
137 static void sparc_init_modes (void);
138 static int save_regs (FILE *, int, int, const char *, int, int, int);
139 static int restore_regs (FILE *, int, int, const char *, int, int);
140 static void build_big_number (FILE *, int, const char *);
141 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
142 tree, int, int, int *, int *);
144 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
145 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
147 static void sparc_output_addr_vec (rtx);
148 static void sparc_output_addr_diff_vec (rtx);
149 static void sparc_output_deferred_case_vectors (void);
150 static int check_return_regs (rtx);
151 static int epilogue_renumber (rtx *, int);
152 static bool sparc_assemble_integer (rtx, unsigned int, int);
153 static int set_extends (rtx);
154 static void output_restore_regs (FILE *, int);
155 static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT);
156 static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT);
157 static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT);
158 static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT);
159 static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int);
160 static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int);
161 #ifdef OBJECT_FORMAT_ELF
162 static void sparc_elf_asm_named_section (const char *, unsigned int);
164 static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT)
166 static void sparc_aout_select_rtx_section (enum machine_mode, rtx,
167 unsigned HOST_WIDE_INT)
170 static int sparc_adjust_cost (rtx, rtx, rtx, int);
171 static int sparc_issue_rate (void);
172 static void sparc_sched_init (FILE *, int, int);
173 static int sparc_use_dfa_pipeline_interface (void);
174 static int sparc_use_sched_lookahead (void);
176 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
177 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
178 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
179 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
180 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
182 static bool sparc_function_ok_for_sibcall (tree, tree);
183 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
184 HOST_WIDE_INT, tree);
185 static struct machine_function * sparc_init_machine_status (void);
186 static bool sparc_cannot_force_const_mem (rtx);
187 static rtx sparc_tls_get_addr (void);
188 static rtx sparc_tls_got (void);
189 static const char *get_some_local_dynamic_name (void);
190 static int get_some_local_dynamic_name_1 (rtx *, void *);
191 static bool sparc_rtx_costs (rtx, int, int, int *);
193 /* Option handling. */
195 /* Code model option as passed by user. */
196 const char *sparc_cmodel_string;
198 enum cmodel sparc_cmodel;
200 char sparc_hard_reg_printed[8];
202 struct sparc_cpu_select sparc_select[] =
204 /* switch name, tune arch */
205 { (char *)0, "default", 1, 1 },
206 { (char *)0, "-mcpu=", 1, 1 },
207 { (char *)0, "-mtune=", 1, 0 },
211 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
212 enum processor_type sparc_cpu;
214 /* Initialize the GCC target structure. */
216 /* The sparc default is to use .half rather than .short for aligned
217 HI objects. Use .word instead of .long on non-ELF systems. */
218 #undef TARGET_ASM_ALIGNED_HI_OP
219 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
220 #ifndef OBJECT_FORMAT_ELF
221 #undef TARGET_ASM_ALIGNED_SI_OP
222 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
225 #undef TARGET_ASM_UNALIGNED_HI_OP
226 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
227 #undef TARGET_ASM_UNALIGNED_SI_OP
228 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
229 #undef TARGET_ASM_UNALIGNED_DI_OP
230 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
232 /* The target hook has to handle DI-mode values. */
233 #undef TARGET_ASM_INTEGER
234 #define TARGET_ASM_INTEGER sparc_assemble_integer
236 #undef TARGET_ASM_FUNCTION_PROLOGUE
237 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
238 #undef TARGET_ASM_FUNCTION_EPILOGUE
239 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
241 #undef TARGET_SCHED_ADJUST_COST
242 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
243 #undef TARGET_SCHED_ISSUE_RATE
244 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
245 #undef TARGET_SCHED_INIT
246 #define TARGET_SCHED_INIT sparc_sched_init
247 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
248 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
249 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
250 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
252 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
253 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
256 #undef TARGET_HAVE_TLS
257 #define TARGET_HAVE_TLS true
259 #undef TARGET_CANNOT_FORCE_CONST_MEM
260 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
262 #undef TARGET_ASM_OUTPUT_MI_THUNK
263 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
264 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
265 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
267 #undef TARGET_RTX_COSTS
268 #define TARGET_RTX_COSTS sparc_rtx_costs
269 #undef TARGET_ADDRESS_COST
270 #define TARGET_ADDRESS_COST hook_int_rtx_0
272 struct gcc_target targetm = TARGET_INITIALIZER;
274 /* Validate and override various options, and do some machine dependent
278 sparc_override_options (void)
280 static struct code_model {
281 const char *const name;
283 } const cmodels[] = {
285 { "medlow", CM_MEDLOW },
286 { "medmid", CM_MEDMID },
287 { "medany", CM_MEDANY },
288 { "embmedany", CM_EMBMEDANY },
291 const struct code_model *cmodel;
292 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
293 static struct cpu_default {
295 const char *const name;
296 } const cpu_default[] = {
297 /* There must be one entry here for each TARGET_CPU value. */
298 { TARGET_CPU_sparc, "cypress" },
299 { TARGET_CPU_sparclet, "tsc701" },
300 { TARGET_CPU_sparclite, "f930" },
301 { TARGET_CPU_v8, "v8" },
302 { TARGET_CPU_hypersparc, "hypersparc" },
303 { TARGET_CPU_sparclite86x, "sparclite86x" },
304 { TARGET_CPU_supersparc, "supersparc" },
305 { TARGET_CPU_v9, "v9" },
306 { TARGET_CPU_ultrasparc, "ultrasparc" },
307 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
310 const struct cpu_default *def;
311 /* Table of values for -m{cpu,tune}=. */
312 static struct cpu_table {
313 const char *const name;
314 const enum processor_type processor;
317 } const cpu_table[] = {
318 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
319 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
320 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
321 /* TI TMS390Z55 supersparc */
322 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
323 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
324 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
325 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
326 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
327 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
328 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
329 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
331 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
333 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
334 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
335 /* TI ultrasparc I, II, IIi */
336 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
337 /* Although insns using %y are deprecated, it is a clear win on current
339 |MASK_DEPRECATED_V8_INSNS},
340 /* TI ultrasparc III */
341 /* ??? Check if %y issue still holds true in ultra3. */
342 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
345 const struct cpu_table *cpu;
346 const struct sparc_cpu_select *sel;
349 #ifndef SPARC_BI_ARCH
350 /* Check for unsupported architecture size. */
351 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
352 error ("%s is not supported by this configuration",
353 DEFAULT_ARCH32_P ? "-m64" : "-m32");
356 /* We force all 64bit archs to use 128 bit long double */
357 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
359 error ("-mlong-double-64 not allowed with -m64");
360 target_flags |= MASK_LONG_DOUBLE_128;
363 /* Code model selection. */
364 sparc_cmodel = SPARC_DEFAULT_CMODEL;
368 sparc_cmodel = CM_32;
371 if (sparc_cmodel_string != NULL)
375 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
376 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
378 if (cmodel->name == NULL)
379 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
381 sparc_cmodel = cmodel->value;
384 error ("-mcmodel= is not supported on 32 bit systems");
387 fpu = TARGET_FPU; /* save current -mfpu status */
389 /* Set the default CPU. */
390 for (def = &cpu_default[0]; def->name; ++def)
391 if (def->cpu == TARGET_CPU_DEFAULT)
395 sparc_select[0].string = def->name;
397 for (sel = &sparc_select[0]; sel->name; ++sel)
401 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
402 if (! strcmp (sel->string, cpu->name))
405 sparc_cpu = cpu->processor;
409 target_flags &= ~cpu->disable;
410 target_flags |= cpu->enable;
416 error ("bad value (%s) for %s switch", sel->string, sel->name);
420 /* If -mfpu or -mno-fpu was explicitly used, don't override with
421 the processor default. Clear MASK_FPU_SET to avoid confusing
422 the reverse mapping from switch values to names. */
425 target_flags = (target_flags & ~MASK_FPU) | fpu;
426 target_flags &= ~MASK_FPU_SET;
429 /* Don't allow -mvis if FPU is disabled. */
431 target_flags &= ~MASK_VIS;
433 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
435 -m64 also implies v9. */
436 if (TARGET_VIS || TARGET_ARCH64)
438 target_flags |= MASK_V9;
439 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
442 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
443 if (TARGET_V9 && TARGET_ARCH32)
444 target_flags |= MASK_DEPRECATED_V8_INSNS;
446 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
447 if (! TARGET_V9 || TARGET_ARCH64)
448 target_flags &= ~MASK_V8PLUS;
450 /* Don't use stack biasing in 32 bit mode. */
452 target_flags &= ~MASK_STACK_BIAS;
454 /* Supply a default value for align_functions. */
455 if (align_functions == 0
456 && (sparc_cpu == PROCESSOR_ULTRASPARC
457 || sparc_cpu == PROCESSOR_ULTRASPARC3))
458 align_functions = 32;
460 /* Validate PCC_STRUCT_RETURN. */
461 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
462 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
464 /* Only use .uaxword when compiling for a 64-bit target. */
466 targetm.asm_out.unaligned_op.di = NULL;
468 /* Do various machine dependent initializations. */
471 /* Set up function hooks. */
472 init_machine_status = sparc_init_machine_status;
475 /* Miscellaneous utilities. */
477 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
478 or branch on register contents instructions. */
481 v9_regcmp_p (enum rtx_code code)
483 return (code == EQ || code == NE || code == GE || code == LT
484 || code == LE || code == GT);
488 /* Operand constraints. */
490 /* Return nonzero only if OP is a register of mode MODE,
494 reg_or_0_operand (rtx op, enum machine_mode mode)
496 if (register_operand (op, mode))
498 if (op == const0_rtx)
500 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
501 && CONST_DOUBLE_HIGH (op) == 0
502 && CONST_DOUBLE_LOW (op) == 0)
504 if (fp_zero_operand (op, mode))
509 /* Return nonzero only if OP is const1_rtx. */
512 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
514 return op == const1_rtx;
517 /* Nonzero if OP is a floating point value with value 0.0. */
520 fp_zero_operand (rtx op, enum machine_mode mode)
522 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
524 return op == CONST0_RTX (mode);
527 /* Nonzero if OP is a register operand in floating point register. */
530 fp_register_operand (rtx op, enum machine_mode mode)
532 if (! register_operand (op, mode))
534 if (GET_CODE (op) == SUBREG)
535 op = SUBREG_REG (op);
536 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
539 /* Nonzero if OP is a floating point constant which can
540 be loaded into an integer register using a single
541 sethi instruction. */
546 if (GET_CODE (op) == CONST_DOUBLE)
551 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
552 if (REAL_VALUES_EQUAL (r, dconst0) &&
553 ! REAL_VALUE_MINUS_ZERO (r))
555 REAL_VALUE_TO_TARGET_SINGLE (r, i);
556 if (SPARC_SETHI_P (i))
563 /* Nonzero if OP is a floating point constant which can
564 be loaded into an integer register using a single
570 if (GET_CODE (op) == CONST_DOUBLE)
575 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
576 if (REAL_VALUES_EQUAL (r, dconst0) &&
577 ! REAL_VALUE_MINUS_ZERO (r))
579 REAL_VALUE_TO_TARGET_SINGLE (r, i);
580 if (SPARC_SIMM13_P (i))
587 /* Nonzero if OP is a floating point constant which can
588 be loaded into an integer register using a high/losum
589 instruction sequence. */
592 fp_high_losum_p (rtx op)
594 /* The constraints calling this should only be in
595 SFmode move insns, so any constant which cannot
596 be moved using a single insn will do. */
597 if (GET_CODE (op) == CONST_DOUBLE)
602 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
603 if (REAL_VALUES_EQUAL (r, dconst0) &&
604 ! REAL_VALUE_MINUS_ZERO (r))
606 REAL_VALUE_TO_TARGET_SINGLE (r, i);
607 if (! SPARC_SETHI_P (i)
608 && ! SPARC_SIMM13_P (i))
615 /* Nonzero if OP is an integer register. */
618 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
620 return (register_operand (op, SImode)
621 || (TARGET_ARCH64 && register_operand (op, DImode)));
624 /* Nonzero if OP is a floating point condition code register. */
627 fcc_reg_operand (rtx op, enum machine_mode mode)
629 /* This can happen when recog is called from combine. Op may be a MEM.
630 Fail instead of calling abort in this case. */
631 if (GET_CODE (op) != REG)
634 if (mode != VOIDmode && mode != GET_MODE (op))
637 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
640 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
641 if (reg_renumber == 0)
642 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
643 return REGNO_OK_FOR_CCFP_P (REGNO (op));
645 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
649 /* Nonzero if OP is a floating point condition code fcc0 register. */
652 fcc0_reg_operand (rtx op, enum machine_mode mode)
654 /* This can happen when recog is called from combine. Op may be a MEM.
655 Fail instead of calling abort in this case. */
656 if (GET_CODE (op) != REG)
659 if (mode != VOIDmode && mode != GET_MODE (op))
662 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
665 return REGNO (op) == SPARC_FCC_REG;
668 /* Nonzero if OP is an integer or floating point condition code register. */
671 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
673 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
675 if (mode != VOIDmode && mode != GET_MODE (op))
678 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
683 return fcc_reg_operand (op, mode);
686 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
688 restore_operand (rtx op, enum machine_mode mode)
690 return (GET_CODE (op) == REG && GET_MODE (op) == mode
691 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
694 /* Call insn on SPARC can take a PC-relative constant address, or any regular
698 call_operand (rtx op, enum machine_mode mode)
700 if (GET_CODE (op) != MEM)
703 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
707 call_operand_address (rtx op, enum machine_mode mode)
709 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
712 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
713 otherwise return 0. */
716 tls_symbolic_operand (rtx op)
718 if (GET_CODE (op) != SYMBOL_REF)
720 return SYMBOL_REF_TLS_MODEL (op);
724 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
726 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
730 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
732 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
736 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
738 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
742 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
744 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
747 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
748 reference and a constant. */
751 symbolic_operand (register rtx op, enum machine_mode mode)
753 enum machine_mode omode = GET_MODE (op);
755 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
758 switch (GET_CODE (op))
761 return !SYMBOL_REF_TLS_MODEL (op);
768 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
769 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
770 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
771 && GET_CODE (XEXP (op, 1)) == CONST_INT);
778 /* Return truth value of statement that OP is a symbolic memory
779 operand of mode MODE. */
782 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
784 if (GET_CODE (op) == SUBREG)
785 op = SUBREG_REG (op);
786 if (GET_CODE (op) != MEM)
789 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
790 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
791 || GET_CODE (op) == LABEL_REF);
794 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
797 label_ref_operand (rtx op, enum machine_mode mode)
799 if (GET_CODE (op) != LABEL_REF)
801 if (GET_MODE (op) != mode)
806 /* Return 1 if the operand is an argument used in generating pic references
807 in either the medium/low or medium/anywhere code models of sparc64. */
810 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
812 /* Check for (const (minus (symbol_ref:GOT)
813 (const (minus (label) (pc))))). */
814 if (GET_CODE (op) != CONST)
817 if (GET_CODE (op) != MINUS)
819 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
821 /* ??? Ensure symbol is GOT. */
822 if (GET_CODE (XEXP (op, 1)) != CONST)
824 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
829 /* Return 1 if the operand is a data segment reference. This includes
830 the readonly data segment, or in other words anything but the text segment.
831 This is needed in the medium/anywhere code model on v9. These values
832 are accessed with EMBMEDANY_BASE_REG. */
835 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
837 switch (GET_CODE (op))
840 return ! SYMBOL_REF_FUNCTION_P (op);
842 /* Assume canonical format of symbol + constant.
845 return data_segment_operand (XEXP (op, 0), VOIDmode);
851 /* Return 1 if the operand is a text segment reference.
852 This is needed in the medium/anywhere code model on v9. */
855 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
857 switch (GET_CODE (op))
862 return SYMBOL_REF_FUNCTION_P (op);
864 /* Assume canonical format of symbol + constant.
867 return text_segment_operand (XEXP (op, 0), VOIDmode);
873 /* Return 1 if the operand is either a register or a memory operand that is
877 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
879 if (register_operand (op, mode))
882 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
889 splittable_symbolic_memory_operand (rtx op,
890 enum machine_mode mode ATTRIBUTE_UNUSED)
892 if (GET_CODE (op) != MEM)
894 if (! symbolic_operand (XEXP (op, 0), Pmode))
900 splittable_immediate_memory_operand (rtx op,
901 enum machine_mode mode ATTRIBUTE_UNUSED)
903 if (GET_CODE (op) != MEM)
905 if (! immediate_operand (XEXP (op, 0), Pmode))
910 /* Return truth value of whether OP is EQ or NE. */
913 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
915 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
918 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
919 or LTU for non-floating-point. We handle those specially. */
922 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
924 enum rtx_code code = GET_CODE (op);
926 if (GET_RTX_CLASS (code) != '<')
929 if (GET_MODE (XEXP (op, 0)) == CCFPmode
930 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
933 return (code != NE && code != EQ && code != GEU && code != LTU);
936 /* Return 1 if this is a comparison operator. This allows the use of
937 MATCH_OPERATOR to recognize all the branch insns. */
940 noov_compare_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
942 enum rtx_code code = GET_CODE (op);
944 if (GET_RTX_CLASS (code) != '<')
947 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
948 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
949 /* These are the only branches which work with CC_NOOVmode. */
950 return (code == EQ || code == NE || code == GE || code == LT);
954 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
955 MATCH_OPERATOR to recognize all the branch insns. */
958 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
960 enum rtx_code code = GET_CODE (op);
965 if (GET_RTX_CLASS (code) != '<')
968 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
969 /* These are the only branches which work with CCX_NOOVmode. */
970 return (code == EQ || code == NE || code == GE || code == LT);
971 return (GET_MODE (XEXP (op, 0)) == CCXmode);
974 /* Nonzero if OP is a comparison operator suitable for use in v9
975 conditional move or branch on register contents instructions. */
978 v9_regcmp_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
980 enum rtx_code code = GET_CODE (op);
982 if (GET_RTX_CLASS (code) != '<')
985 return v9_regcmp_p (code);
988 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
991 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
993 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
996 /* Return nonzero if OP is an operator of mode MODE which can set
997 the condition codes explicitly. We do not include PLUS and MINUS
998 because these require CC_NOOVmode, which we handle explicitly. */
1001 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1003 if (GET_CODE (op) == AND
1004 || GET_CODE (op) == IOR
1005 || GET_CODE (op) == XOR)
1011 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1012 complement its second operand and set the condition codes explicitly. */
1015 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1017 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1018 and (xor ... (not ...)) to (not (xor ...)). */
1019 return (GET_CODE (op) == AND
1020 || GET_CODE (op) == IOR);
1023 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1024 signed 13 bit immediate field. This is an acceptable SImode operand for
1025 most 3 address instructions. */
1028 arith_operand (rtx op, enum machine_mode mode)
1030 if (register_operand (op, mode))
1032 if (GET_CODE (op) != CONST_INT)
1034 return SMALL_INT32 (op);
1037 /* Return true if OP is a constant 4096 */
1040 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1042 if (GET_CODE (op) != CONST_INT)
1045 return INTVAL (op) == 4096;
1048 /* Return true if OP is suitable as second operand for add/sub */
1051 arith_add_operand (rtx op, enum machine_mode mode)
1053 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1056 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1057 immediate field of OR and XOR instructions. Used for 64-bit
1058 constant formation patterns. */
1060 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1062 return ((GET_CODE (op) == CONST_INT
1063 && SPARC_SIMM13_P (INTVAL (op)))
1064 #if HOST_BITS_PER_WIDE_INT != 64
1065 || (GET_CODE (op) == CONST_DOUBLE
1066 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1067 && (CONST_DOUBLE_HIGH (op) ==
1068 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1069 (HOST_WIDE_INT)-1 : 0)))
1074 /* The same, but only for sethi instructions. */
1076 const64_high_operand (rtx op, enum machine_mode mode)
1078 return ((GET_CODE (op) == CONST_INT
1079 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1080 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1082 || (GET_CODE (op) == CONST_DOUBLE
1083 && CONST_DOUBLE_HIGH (op) == 0
1084 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1085 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1088 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1089 signed 11 bit immediate field. This is an acceptable SImode operand for
1090 the movcc instructions. */
1093 arith11_operand (rtx op, enum machine_mode mode)
1095 return (register_operand (op, mode)
1096 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1099 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1100 signed 10 bit immediate field. This is an acceptable SImode operand for
1101 the movrcc instructions. */
1104 arith10_operand (rtx op, enum machine_mode mode)
1106 return (register_operand (op, mode)
1107 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1110 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1111 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1113 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1114 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1115 for most 3 address instructions. */
1118 arith_double_operand (rtx op, enum machine_mode mode)
1120 return (register_operand (op, mode)
1121 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1123 && GET_CODE (op) == CONST_DOUBLE
1124 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1125 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1127 && GET_CODE (op) == CONST_DOUBLE
1128 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1129 && ((CONST_DOUBLE_HIGH (op) == -1
1130 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1131 || (CONST_DOUBLE_HIGH (op) == 0
1132 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1135 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1138 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1140 return (TARGET_ARCH64 &&
1141 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1142 (GET_CODE (op) == CONST_DOUBLE &&
1143 CONST_DOUBLE_LOW (op) == 4096 &&
1144 CONST_DOUBLE_HIGH (op) == 0)));
1147 /* Return true if OP is suitable as second operand for add/sub in DImode */
1150 arith_double_add_operand (rtx op, enum machine_mode mode)
1152 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1155 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1156 can fit in an 11 bit immediate field. This is an acceptable DImode
1157 operand for the movcc instructions. */
1158 /* ??? Replace with arith11_operand? */
1161 arith11_double_operand (rtx op, enum machine_mode mode)
1163 return (register_operand (op, mode)
1164 || (GET_CODE (op) == CONST_DOUBLE
1165 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1166 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1167 && ((CONST_DOUBLE_HIGH (op) == -1
1168 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1169 || (CONST_DOUBLE_HIGH (op) == 0
1170 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1171 || (GET_CODE (op) == CONST_INT
1172 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1173 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1176 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1177 can fit in an 10 bit immediate field. This is an acceptable DImode
1178 operand for the movrcc instructions. */
1179 /* ??? Replace with arith10_operand? */
1182 arith10_double_operand (rtx op, enum machine_mode mode)
1184 return (register_operand (op, mode)
1185 || (GET_CODE (op) == CONST_DOUBLE
1186 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1187 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1188 && ((CONST_DOUBLE_HIGH (op) == -1
1189 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1190 || (CONST_DOUBLE_HIGH (op) == 0
1191 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1192 || (GET_CODE (op) == CONST_INT
1193 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1194 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1197 /* Return truth value of whether OP is an integer which fits the
1198 range constraining immediate operands in most three-address insns,
1199 which have a 13 bit immediate field. */
1202 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1204 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1208 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1210 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1211 || (GET_CODE (op) == CONST_DOUBLE
1212 && CONST_DOUBLE_HIGH (op) == 0
1213 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1216 /* Recognize operand values for the umul instruction. That instruction sign
1217 extends immediate values just like all other sparc instructions, but
1218 interprets the extended result as an unsigned number. */
1221 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1223 #if HOST_BITS_PER_WIDE_INT > 32
1224 /* All allowed constants will fit a CONST_INT. */
1225 return (GET_CODE (op) == CONST_INT
1226 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1227 || (INTVAL (op) >= 0xFFFFF000
1228 && INTVAL (op) <= 0xFFFFFFFF)));
1230 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1231 || (GET_CODE (op) == CONST_DOUBLE
1232 && CONST_DOUBLE_HIGH (op) == 0
1233 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1238 uns_arith_operand (rtx op, enum machine_mode mode)
1240 return register_operand (op, mode) || uns_small_int (op, mode);
1243 /* Return truth value of statement that OP is a call-clobbered register. */
1245 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1247 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1250 /* Return 1 if OP is a valid operand for the source of a move insn. */
1253 input_operand (rtx op, enum machine_mode mode)
1255 /* If both modes are non-void they must be the same. */
1256 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1259 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */
1260 if (GET_CODE (op) == CONSTANT_P_RTX)
1263 /* Allow any one instruction integer constant, and all CONST_INT
1264 variants when we are working in DImode and !arch64. */
1265 if (GET_MODE_CLASS (mode) == MODE_INT
1266 && ((GET_CODE (op) == CONST_INT
1267 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1268 || SPARC_SIMM13_P (INTVAL (op))
1270 && ! TARGET_ARCH64)))
1272 && GET_CODE (op) == CONST_DOUBLE
1273 && ((CONST_DOUBLE_HIGH (op) == 0
1274 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1276 #if HOST_BITS_PER_WIDE_INT == 64
1277 (CONST_DOUBLE_HIGH (op) == 0
1278 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1280 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1281 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1282 && CONST_DOUBLE_HIGH (op) == 0)
1283 || (CONST_DOUBLE_HIGH (op) == -1
1284 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1289 /* If !arch64 and this is a DImode const, allow it so that
1290 the splits can be generated. */
1293 && GET_CODE (op) == CONST_DOUBLE)
1296 if (register_operand (op, mode))
1299 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1300 && GET_CODE (op) == CONST_DOUBLE)
1303 /* If this is a SUBREG, look inside so that we handle
1304 paradoxical ones. */
1305 if (GET_CODE (op) == SUBREG)
1306 op = SUBREG_REG (op);
1308 /* Check for valid MEM forms. */
1309 if (GET_CODE (op) == MEM)
1311 rtx inside = XEXP (op, 0);
1313 if (GET_CODE (inside) == LO_SUM)
1315 /* We can't allow these because all of the splits
1316 (eventually as they trickle down into DFmode
1317 splits) require offsettable memory references. */
1319 && GET_MODE (op) == TFmode)
1322 return (register_operand (XEXP (inside, 0), Pmode)
1323 && CONSTANT_P (XEXP (inside, 1)));
1325 return memory_address_p (mode, inside);
1332 /* We know it can't be done in one insn when we get here,
1333 the movsi expander guarantees this. */
1335 sparc_emit_set_const32 (rtx op0, rtx op1)
1337 enum machine_mode mode = GET_MODE (op0);
1340 if (GET_CODE (op1) == CONST_INT)
1342 HOST_WIDE_INT value = INTVAL (op1);
1344 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1345 || SPARC_SIMM13_P (value))
1349 /* Full 2-insn decomposition is needed. */
1350 if (reload_in_progress || reload_completed)
1353 temp = gen_reg_rtx (mode);
1355 if (GET_CODE (op1) == CONST_INT)
1357 /* Emit them as real moves instead of a HIGH/LO_SUM,
1358 this way CSE can see everything and reuse intermediate
1359 values if it wants. */
1361 && HOST_BITS_PER_WIDE_INT != 64
1362 && (INTVAL (op1) & 0x80000000) != 0)
1363 emit_insn (gen_rtx_SET
1365 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1368 emit_insn (gen_rtx_SET (VOIDmode, temp,
1369 GEN_INT (INTVAL (op1)
1370 & ~(HOST_WIDE_INT)0x3ff)));
1372 emit_insn (gen_rtx_SET (VOIDmode,
1374 gen_rtx_IOR (mode, temp,
1375 GEN_INT (INTVAL (op1) & 0x3ff))));
1379 /* A symbol, emit in the traditional way. */
1380 emit_insn (gen_rtx_SET (VOIDmode, temp,
1381 gen_rtx_HIGH (mode, op1)));
1382 emit_insn (gen_rtx_SET (VOIDmode,
1383 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1389 /* SPARC-v9 code-model support. */
1391 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp1)
1395 if (temp1 && GET_MODE (temp1) == TImode)
1398 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1401 switch (sparc_cmodel)
1404 /* The range spanned by all instructions in the object is less
1405 than 2^31 bytes (2GB) and the distance from any instruction
1406 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1407 than 2^31 bytes (2GB).
1409 The executable must be in the low 4TB of the virtual address
1412 sethi %hi(symbol), %temp
1413 or %temp, %lo(symbol), %reg */
1414 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1415 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1419 /* The range spanned by all instructions in the object is less
1420 than 2^31 bytes (2GB) and the distance from any instruction
1421 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1422 than 2^31 bytes (2GB).
1424 The executable must be in the low 16TB of the virtual address
1427 sethi %h44(symbol), %temp1
1428 or %temp1, %m44(symbol), %temp2
1429 sllx %temp2, 12, %temp3
1430 or %temp3, %l44(symbol), %reg */
1431 emit_insn (gen_seth44 (op0, op1));
1432 emit_insn (gen_setm44 (op0, op0, op1));
1433 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1434 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1435 emit_insn (gen_setl44 (op0, temp1, op1));
1439 /* The range spanned by all instructions in the object is less
1440 than 2^31 bytes (2GB) and the distance from any instruction
1441 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1442 than 2^31 bytes (2GB).
1444 The executable can be placed anywhere in the virtual address
1447 sethi %hh(symbol), %temp1
1448 sethi %lm(symbol), %temp2
1449 or %temp1, %hm(symbol), %temp3
1450 or %temp2, %lo(symbol), %temp4
1451 sllx %temp3, 32, %temp5
1452 or %temp4, %temp5, %reg */
1454 /* It is possible that one of the registers we got for operands[2]
1455 might coincide with that of operands[0] (which is why we made
1456 it TImode). Pick the other one to use as our scratch. */
1457 if (rtx_equal_p (temp1, op0))
1460 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1465 emit_insn (gen_sethh (op0, op1));
1466 emit_insn (gen_setlm (temp1, op1));
1467 emit_insn (gen_sethm (op0, op0, op1));
1468 emit_insn (gen_rtx_SET (VOIDmode, op0,
1469 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1470 emit_insn (gen_rtx_SET (VOIDmode, op0,
1471 gen_rtx_PLUS (DImode, op0, temp1)));
1472 emit_insn (gen_setlo (op0, op0, op1));
1476 /* Old old old backwards compatibility kruft here.
1477 Essentially it is MEDLOW with a fixed 64-bit
1478 virtual base added to all data segment addresses.
1479 Text-segment stuff is computed like MEDANY, we can't
1480 reuse the code above because the relocation knobs
1483 Data segment: sethi %hi(symbol), %temp1
1484 or %temp1, %lo(symbol), %temp2
1485 add %temp2, EMBMEDANY_BASE_REG, %reg
1487 Text segment: sethi %uhi(symbol), %temp1
1488 sethi %hi(symbol), %temp2
1489 or %temp1, %ulo(symbol), %temp3
1490 or %temp2, %lo(symbol), %temp4
1491 sllx %temp3, 32, %temp5
1492 or %temp4, %temp5, %reg */
1493 if (data_segment_operand (op1, GET_MODE (op1)))
1495 emit_insn (gen_embmedany_sethi (temp1, op1));
1496 emit_insn (gen_embmedany_brsum (op0, temp1));
1497 emit_insn (gen_embmedany_losum (op0, op0, op1));
1501 /* It is possible that one of the registers we got for operands[2]
1502 might coincide with that of operands[0] (which is why we made
1503 it TImode). Pick the other one to use as our scratch. */
1504 if (rtx_equal_p (temp1, op0))
1507 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1512 emit_insn (gen_embmedany_textuhi (op0, op1));
1513 emit_insn (gen_embmedany_texthi (temp1, op1));
1514 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1515 emit_insn (gen_rtx_SET (VOIDmode, op0,
1516 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1517 emit_insn (gen_rtx_SET (VOIDmode, op0,
1518 gen_rtx_PLUS (DImode, op0, temp1)));
1519 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1528 /* These avoid problems when cross compiling. If we do not
1529 go through all this hair then the optimizer will see
1530 invalid REG_EQUAL notes or in some cases none at all. */
1531 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1532 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1533 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1534 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1536 #if HOST_BITS_PER_WIDE_INT == 64
1537 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1538 #define GEN_INT64(__x) GEN_INT (__x)
1540 #define GEN_HIGHINT64(__x) \
1541 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1542 #define GEN_INT64(__x) \
1543 immed_double_const ((__x) & 0xffffffff, \
1544 ((__x) & 0x80000000 ? -1 : 0), DImode)
1547 /* The optimizer is not to assume anything about exactly
1548 which bits are set for a HIGH, they are unspecified.
1549 Unfortunately this leads to many missed optimizations
1550 during CSE. We mask out the non-HIGH bits, and matches
1551 a plain movdi, to alleviate this problem. */
1553 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1555 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1559 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1561 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1565 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1567 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1571 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1573 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1576 /* Worker routines for 64-bit constant formation on arch64.
1577 One of the key things to be doing in these emissions is
1578 to create as many temp REGs as possible. This makes it
1579 possible for half-built constants to be used later when
1580 such values are similar to something required later on.
1581 Without doing this, the optimizer cannot see such
1584 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1585 unsigned HOST_WIDE_INT, int);
1588 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1589 unsigned HOST_WIDE_INT low_bits, int is_neg)
1591 unsigned HOST_WIDE_INT high_bits;
1594 high_bits = (~low_bits) & 0xffffffff;
1596 high_bits = low_bits;
1598 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1601 emit_insn (gen_rtx_SET (VOIDmode, op0,
1602 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1606 /* If we are XOR'ing with -1, then we should emit a one's complement
1607 instead. This way the combiner will notice logical operations
1608 such as ANDN later on and substitute. */
1609 if ((low_bits & 0x3ff) == 0x3ff)
1611 emit_insn (gen_rtx_SET (VOIDmode, op0,
1612 gen_rtx_NOT (DImode, temp)));
1616 emit_insn (gen_rtx_SET (VOIDmode, op0,
1617 gen_safe_XOR64 (temp,
1618 (-(HOST_WIDE_INT)0x400
1619 | (low_bits & 0x3ff)))));
1624 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1625 unsigned HOST_WIDE_INT, int);
1628 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1629 unsigned HOST_WIDE_INT high_bits,
1630 unsigned HOST_WIDE_INT low_immediate,
1635 if ((high_bits & 0xfffffc00) != 0)
1637 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1638 if ((high_bits & ~0xfffffc00) != 0)
1639 emit_insn (gen_rtx_SET (VOIDmode, op0,
1640 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1646 emit_insn (gen_safe_SET64 (temp, high_bits));
1650 /* Now shift it up into place. */
1651 emit_insn (gen_rtx_SET (VOIDmode, op0,
1652 gen_rtx_ASHIFT (DImode, temp2,
1653 GEN_INT (shift_count))));
1655 /* If there is a low immediate part piece, finish up by
1656 putting that in as well. */
1657 if (low_immediate != 0)
1658 emit_insn (gen_rtx_SET (VOIDmode, op0,
1659 gen_safe_OR64 (op0, low_immediate)));
1662 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1663 unsigned HOST_WIDE_INT);
1665 /* Full 64-bit constant decomposition. Even though this is the
1666 'worst' case, we still optimize a few things away. */
1668 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1669 unsigned HOST_WIDE_INT high_bits,
1670 unsigned HOST_WIDE_INT low_bits)
1674 if (reload_in_progress || reload_completed)
1677 sub_temp = gen_reg_rtx (DImode);
1679 if ((high_bits & 0xfffffc00) != 0)
1681 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1682 if ((high_bits & ~0xfffffc00) != 0)
1683 emit_insn (gen_rtx_SET (VOIDmode,
1685 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1691 emit_insn (gen_safe_SET64 (temp, high_bits));
1695 if (!reload_in_progress && !reload_completed)
1697 rtx temp2 = gen_reg_rtx (DImode);
1698 rtx temp3 = gen_reg_rtx (DImode);
1699 rtx temp4 = gen_reg_rtx (DImode);
1701 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1702 gen_rtx_ASHIFT (DImode, sub_temp,
1705 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1706 if ((low_bits & ~0xfffffc00) != 0)
1708 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1709 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1710 emit_insn (gen_rtx_SET (VOIDmode, op0,
1711 gen_rtx_PLUS (DImode, temp4, temp3)));
1715 emit_insn (gen_rtx_SET (VOIDmode, op0,
1716 gen_rtx_PLUS (DImode, temp4, temp2)));
1721 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1722 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1723 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1726 /* We are in the middle of reload, so this is really
1727 painful. However we do still make an attempt to
1728 avoid emitting truly stupid code. */
1729 if (low1 != const0_rtx)
1731 emit_insn (gen_rtx_SET (VOIDmode, op0,
1732 gen_rtx_ASHIFT (DImode, sub_temp,
1733 GEN_INT (to_shift))));
1734 emit_insn (gen_rtx_SET (VOIDmode, op0,
1735 gen_rtx_IOR (DImode, op0, low1)));
1743 if (low2 != const0_rtx)
1745 emit_insn (gen_rtx_SET (VOIDmode, op0,
1746 gen_rtx_ASHIFT (DImode, sub_temp,
1747 GEN_INT (to_shift))));
1748 emit_insn (gen_rtx_SET (VOIDmode, op0,
1749 gen_rtx_IOR (DImode, op0, low2)));
1757 emit_insn (gen_rtx_SET (VOIDmode, op0,
1758 gen_rtx_ASHIFT (DImode, sub_temp,
1759 GEN_INT (to_shift))));
1760 if (low3 != const0_rtx)
1761 emit_insn (gen_rtx_SET (VOIDmode, op0,
1762 gen_rtx_IOR (DImode, op0, low3)));
1767 /* Analyze a 64-bit constant for certain properties. */
1768 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1769 unsigned HOST_WIDE_INT,
1770 int *, int *, int *);
1773 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1774 unsigned HOST_WIDE_INT low_bits,
1775 int *hbsp, int *lbsp, int *abbasp)
1777 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1780 lowest_bit_set = highest_bit_set = -1;
1784 if ((lowest_bit_set == -1)
1785 && ((low_bits >> i) & 1))
1787 if ((highest_bit_set == -1)
1788 && ((high_bits >> (32 - i - 1)) & 1))
1789 highest_bit_set = (64 - i - 1);
1792 && ((highest_bit_set == -1)
1793 || (lowest_bit_set == -1)));
1799 if ((lowest_bit_set == -1)
1800 && ((high_bits >> i) & 1))
1801 lowest_bit_set = i + 32;
1802 if ((highest_bit_set == -1)
1803 && ((low_bits >> (32 - i - 1)) & 1))
1804 highest_bit_set = 32 - i - 1;
1807 && ((highest_bit_set == -1)
1808 || (lowest_bit_set == -1)));
1810 /* If there are no bits set this should have gone out
1811 as one instruction! */
1812 if (lowest_bit_set == -1
1813 || highest_bit_set == -1)
1815 all_bits_between_are_set = 1;
1816 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1820 if ((low_bits & (1 << i)) != 0)
1825 if ((high_bits & (1 << (i - 32))) != 0)
1828 all_bits_between_are_set = 0;
1831 *hbsp = highest_bit_set;
1832 *lbsp = lowest_bit_set;
1833 *abbasp = all_bits_between_are_set;
1836 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1839 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1840 unsigned HOST_WIDE_INT low_bits)
1842 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1845 || high_bits == 0xffffffff)
1848 analyze_64bit_constant (high_bits, low_bits,
1849 &highest_bit_set, &lowest_bit_set,
1850 &all_bits_between_are_set);
1852 if ((highest_bit_set == 63
1853 || lowest_bit_set == 0)
1854 && all_bits_between_are_set != 0)
1857 if ((highest_bit_set - lowest_bit_set) < 21)
1863 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1864 unsigned HOST_WIDE_INT,
1867 static unsigned HOST_WIDE_INT
1868 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1869 unsigned HOST_WIDE_INT low_bits,
1870 int lowest_bit_set, int shift)
1872 HOST_WIDE_INT hi, lo;
1874 if (lowest_bit_set < 32)
1876 lo = (low_bits >> lowest_bit_set) << shift;
1877 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1882 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1889 /* Here we are sure to be arch64 and this is an integer constant
1890 being loaded into a register. Emit the most efficient
1891 insn sequence possible. Detection of all the 1-insn cases
1892 has been done already. */
1894 sparc_emit_set_const64 (rtx op0, rtx op1)
1896 unsigned HOST_WIDE_INT high_bits, low_bits;
1897 int lowest_bit_set, highest_bit_set;
1898 int all_bits_between_are_set;
1901 /* Sanity check that we know what we are working with. */
1902 if (! TARGET_ARCH64)
1905 if (GET_CODE (op0) != SUBREG)
1907 if (GET_CODE (op0) != REG
1908 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1909 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1913 if (reload_in_progress || reload_completed)
1916 temp = gen_reg_rtx (DImode);
1918 if (GET_CODE (op1) != CONST_DOUBLE
1919 && GET_CODE (op1) != CONST_INT)
1921 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1925 if (GET_CODE (op1) == CONST_DOUBLE)
1927 #if HOST_BITS_PER_WIDE_INT == 64
1928 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1929 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1931 high_bits = CONST_DOUBLE_HIGH (op1);
1932 low_bits = CONST_DOUBLE_LOW (op1);
1937 #if HOST_BITS_PER_WIDE_INT == 64
1938 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1939 low_bits = (INTVAL (op1) & 0xffffffff);
1941 high_bits = ((INTVAL (op1) < 0) ?
1944 low_bits = INTVAL (op1);
1948 /* low_bits bits 0 --> 31
1949 high_bits bits 32 --> 63 */
1951 analyze_64bit_constant (high_bits, low_bits,
1952 &highest_bit_set, &lowest_bit_set,
1953 &all_bits_between_are_set);
1955 /* First try for a 2-insn sequence. */
1957 /* These situations are preferred because the optimizer can
1958 * do more things with them:
1960 * sllx %reg, shift, %reg
1962 * srlx %reg, shift, %reg
1963 * 3) mov some_small_const, %reg
1964 * sllx %reg, shift, %reg
1966 if (((highest_bit_set == 63
1967 || lowest_bit_set == 0)
1968 && all_bits_between_are_set != 0)
1969 || ((highest_bit_set - lowest_bit_set) < 12))
1971 HOST_WIDE_INT the_const = -1;
1972 int shift = lowest_bit_set;
1974 if ((highest_bit_set != 63
1975 && lowest_bit_set != 0)
1976 || all_bits_between_are_set == 0)
1979 create_simple_focus_bits (high_bits, low_bits,
1982 else if (lowest_bit_set == 0)
1983 shift = -(63 - highest_bit_set);
1985 if (! SPARC_SIMM13_P (the_const))
1988 emit_insn (gen_safe_SET64 (temp, the_const));
1990 emit_insn (gen_rtx_SET (VOIDmode,
1992 gen_rtx_ASHIFT (DImode,
1996 emit_insn (gen_rtx_SET (VOIDmode,
1998 gen_rtx_LSHIFTRT (DImode,
2000 GEN_INT (-shift))));
2006 /* Now a range of 22 or less bits set somewhere.
2007 * 1) sethi %hi(focus_bits), %reg
2008 * sllx %reg, shift, %reg
2009 * 2) sethi %hi(focus_bits), %reg
2010 * srlx %reg, shift, %reg
2012 if ((highest_bit_set - lowest_bit_set) < 21)
2014 unsigned HOST_WIDE_INT focus_bits =
2015 create_simple_focus_bits (high_bits, low_bits,
2016 lowest_bit_set, 10);
2018 if (! SPARC_SETHI_P (focus_bits))
2021 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2023 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2024 if (lowest_bit_set < 10)
2025 emit_insn (gen_rtx_SET (VOIDmode,
2027 gen_rtx_LSHIFTRT (DImode, temp,
2028 GEN_INT (10 - lowest_bit_set))));
2029 else if (lowest_bit_set > 10)
2030 emit_insn (gen_rtx_SET (VOIDmode,
2032 gen_rtx_ASHIFT (DImode, temp,
2033 GEN_INT (lowest_bit_set - 10))));
2039 /* 1) sethi %hi(low_bits), %reg
2040 * or %reg, %lo(low_bits), %reg
2041 * 2) sethi %hi(~low_bits), %reg
2042 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2045 || high_bits == 0xffffffff)
2047 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2048 (high_bits == 0xffffffff));
2052 /* Now, try 3-insn sequences. */
2054 /* 1) sethi %hi(high_bits), %reg
2055 * or %reg, %lo(high_bits), %reg
2056 * sllx %reg, 32, %reg
2060 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2064 /* We may be able to do something quick
2065 when the constant is negated, so try that. */
2066 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2067 (~low_bits) & 0xfffffc00))
2069 /* NOTE: The trailing bits get XOR'd so we need the
2070 non-negated bits, not the negated ones. */
2071 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2073 if ((((~high_bits) & 0xffffffff) == 0
2074 && ((~low_bits) & 0x80000000) == 0)
2075 || (((~high_bits) & 0xffffffff) == 0xffffffff
2076 && ((~low_bits) & 0x80000000) != 0))
2078 int fast_int = (~low_bits & 0xffffffff);
2080 if ((SPARC_SETHI_P (fast_int)
2081 && (~high_bits & 0xffffffff) == 0)
2082 || SPARC_SIMM13_P (fast_int))
2083 emit_insn (gen_safe_SET64 (temp, fast_int));
2085 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2090 #if HOST_BITS_PER_WIDE_INT == 64
2091 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2092 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2094 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2095 (~high_bits) & 0xffffffff,
2098 sparc_emit_set_const64 (temp, negated_const);
2101 /* If we are XOR'ing with -1, then we should emit a one's complement
2102 instead. This way the combiner will notice logical operations
2103 such as ANDN later on and substitute. */
2104 if (trailing_bits == 0x3ff)
2106 emit_insn (gen_rtx_SET (VOIDmode, op0,
2107 gen_rtx_NOT (DImode, temp)));
2111 emit_insn (gen_rtx_SET (VOIDmode,
2113 gen_safe_XOR64 (temp,
2114 (-0x400 | trailing_bits))));
2119 /* 1) sethi %hi(xxx), %reg
2120 * or %reg, %lo(xxx), %reg
2121 * sllx %reg, yyy, %reg
2123 * ??? This is just a generalized version of the low_bits==0
2124 * thing above, FIXME...
2126 if ((highest_bit_set - lowest_bit_set) < 32)
2128 unsigned HOST_WIDE_INT focus_bits =
2129 create_simple_focus_bits (high_bits, low_bits,
2132 /* We can't get here in this state. */
2133 if (highest_bit_set < 32
2134 || lowest_bit_set >= 32)
2137 /* So what we know is that the set bits straddle the
2138 middle of the 64-bit word. */
2139 sparc_emit_set_const64_quick2 (op0, temp,
2145 /* 1) sethi %hi(high_bits), %reg
2146 * or %reg, %lo(high_bits), %reg
2147 * sllx %reg, 32, %reg
2148 * or %reg, low_bits, %reg
2150 if (SPARC_SIMM13_P(low_bits)
2151 && ((int)low_bits > 0))
2153 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2157 /* The easiest way when all else fails, is full decomposition. */
2159 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2160 high_bits, low_bits, ~high_bits, ~low_bits);
2162 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2165 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2166 return the mode to be used for the comparison. For floating-point,
2167 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2168 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2169 processing is needed. */
2172 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2174 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2200 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2201 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2203 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2204 return CCX_NOOVmode;
2210 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2217 /* X and Y are two things to compare using CODE. Emit the compare insn and
2218 return the rtx for the cc reg in the proper mode. */
2221 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2223 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2226 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2227 fcc regs (cse can't tell they're really call clobbered regs and will
2228 remove a duplicate comparison even if there is an intervening function
2229 call - it will then try to reload the cc reg via an int reg which is why
2230 we need the movcc patterns). It is possible to provide the movcc
2231 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2232 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2233 to tell cse that CCFPE mode registers (even pseudos) are call
2236 /* ??? This is an experiment. Rather than making changes to cse which may
2237 or may not be easy/clean, we do our own cse. This is possible because
2238 we will generate hard registers. Cse knows they're call clobbered (it
2239 doesn't know the same thing about pseudos). If we guess wrong, no big
2240 deal, but if we win, great! */
2242 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2243 #if 1 /* experiment */
2246 /* We cycle through the registers to ensure they're all exercised. */
2247 static int next_fcc_reg = 0;
2248 /* Previous x,y for each fcc reg. */
2249 static rtx prev_args[4][2];
2251 /* Scan prev_args for x,y. */
2252 for (reg = 0; reg < 4; reg++)
2253 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2258 prev_args[reg][0] = x;
2259 prev_args[reg][1] = y;
2260 next_fcc_reg = (next_fcc_reg + 1) & 3;
2262 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2265 cc_reg = gen_reg_rtx (mode);
2266 #endif /* ! experiment */
2267 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2268 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2270 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2272 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2273 gen_rtx_COMPARE (mode, x, y)));
2278 /* This function is used for v9 only.
2279 CODE is the code for an Scc's comparison.
2280 OPERANDS[0] is the target of the Scc insn.
2281 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2282 been generated yet).
2284 This function is needed to turn
2287 (gt (reg:CCX 100 %icc)
2291 (gt:DI (reg:CCX 100 %icc)
2294 IE: The instruction recognizer needs to see the mode of the comparison to
2295 find the right instruction. We could use "gt:DI" right in the
2296 define_expand, but leaving it out allows us to handle DI, SI, etc.
2298 We refer to the global sparc compare operands sparc_compare_op0 and
2299 sparc_compare_op1. */
2302 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2307 && (GET_MODE (sparc_compare_op0) == DImode
2308 || GET_MODE (operands[0]) == DImode))
2311 op0 = sparc_compare_op0;
2312 op1 = sparc_compare_op1;
2314 /* Try to use the movrCC insns. */
2316 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2317 && op1 == const0_rtx
2318 && v9_regcmp_p (compare_code))
2320 /* Special case for op0 != 0. This can be done with one instruction if
2321 operands[0] == sparc_compare_op0. */
2323 if (compare_code == NE
2324 && GET_MODE (operands[0]) == DImode
2325 && rtx_equal_p (op0, operands[0]))
2327 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2328 gen_rtx_IF_THEN_ELSE (DImode,
2329 gen_rtx_fmt_ee (compare_code, DImode,
2336 if (reg_overlap_mentioned_p (operands[0], op0))
2338 /* Handle the case where operands[0] == sparc_compare_op0.
2339 We "early clobber" the result. */
2340 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2341 emit_move_insn (op0, sparc_compare_op0);
2344 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2345 if (GET_MODE (op0) != DImode)
2347 temp = gen_reg_rtx (DImode);
2348 convert_move (temp, op0, 0);
2352 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2353 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2354 gen_rtx_fmt_ee (compare_code, DImode,
2362 operands[1] = gen_compare_reg (compare_code, op0, op1);
2364 switch (GET_MODE (operands[1]))
2374 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2375 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2376 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2377 gen_rtx_fmt_ee (compare_code,
2378 GET_MODE (operands[1]),
2379 operands[1], const0_rtx),
2380 const1_rtx, operands[0])));
2385 /* Emit a conditional jump insn for the v9 architecture using comparison code
2386 CODE and jump target LABEL.
2387 This function exists to take advantage of the v9 brxx insns. */
2390 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2392 emit_jump_insn (gen_rtx_SET (VOIDmode,
2394 gen_rtx_IF_THEN_ELSE (VOIDmode,
2395 gen_rtx_fmt_ee (code, GET_MODE (op0),
2397 gen_rtx_LABEL_REF (VOIDmode, label),
2401 /* Generate a DFmode part of a hard TFmode register.
2402 REG is the TFmode hard register, LOW is 1 for the
2403 low 64bit of the register and 0 otherwise.
2406 gen_df_reg (rtx reg, int low)
2408 int regno = REGNO (reg);
2410 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2411 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2412 return gen_rtx_REG (DFmode, regno);
2415 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2416 Unlike normal calls, TFmode operands are passed by reference. It is
2417 assumed that no more than 3 operands are required. */
2420 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2422 rtx ret_slot = NULL, arg[3], func_sym;
2425 /* We only expect to be called for conversions, unary, and binary ops. */
2426 if (nargs < 2 || nargs > 3)
2429 for (i = 0; i < nargs; ++i)
2431 rtx this_arg = operands[i];
2434 /* TFmode arguments and return values are passed by reference. */
2435 if (GET_MODE (this_arg) == TFmode)
2437 int force_stack_temp;
2439 force_stack_temp = 0;
2440 if (TARGET_BUGGY_QP_LIB && i == 0)
2441 force_stack_temp = 1;
2443 if (GET_CODE (this_arg) == MEM
2444 && ! force_stack_temp)
2445 this_arg = XEXP (this_arg, 0);
2446 else if (CONSTANT_P (this_arg)
2447 && ! force_stack_temp)
2449 this_slot = force_const_mem (TFmode, this_arg);
2450 this_arg = XEXP (this_slot, 0);
2454 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2456 /* Operand 0 is the return value. We'll copy it out later. */
2458 emit_move_insn (this_slot, this_arg);
2460 ret_slot = this_slot;
2462 this_arg = XEXP (this_slot, 0);
2469 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2471 if (GET_MODE (operands[0]) == TFmode)
2474 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2475 arg[0], GET_MODE (arg[0]),
2476 arg[1], GET_MODE (arg[1]));
2478 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2479 arg[0], GET_MODE (arg[0]),
2480 arg[1], GET_MODE (arg[1]),
2481 arg[2], GET_MODE (arg[2]));
2484 emit_move_insn (operands[0], ret_slot);
2493 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2494 GET_MODE (operands[0]), 1,
2495 arg[1], GET_MODE (arg[1]));
2497 if (ret != operands[0])
2498 emit_move_insn (operands[0], ret);
2502 /* Expand soft-float TFmode calls to sparc abi routines. */
2505 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2527 emit_soft_tfmode_libcall (func, 3, operands);
2531 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2544 emit_soft_tfmode_libcall (func, 2, operands);
2548 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2555 switch (GET_MODE (operands[1]))
2568 case FLOAT_TRUNCATE:
2569 switch (GET_MODE (operands[0]))
2583 switch (GET_MODE (operands[1]))
2596 case UNSIGNED_FLOAT:
2597 switch (GET_MODE (operands[1]))
2611 switch (GET_MODE (operands[0]))
2625 switch (GET_MODE (operands[0]))
2642 emit_soft_tfmode_libcall (func, 2, operands);
2645 /* Expand a hard-float tfmode operation. All arguments must be in
2649 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2653 if (GET_RTX_CLASS (code) == '1')
2655 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2656 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2660 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2661 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2662 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2663 operands[1], operands[2]);
2666 if (register_operand (operands[0], VOIDmode))
2669 dest = gen_reg_rtx (GET_MODE (operands[0]));
2671 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2673 if (dest != operands[0])
2674 emit_move_insn (operands[0], dest);
2678 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2680 if (TARGET_HARD_QUAD)
2681 emit_hard_tfmode_operation (code, operands);
2683 emit_soft_tfmode_binop (code, operands);
2687 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2689 if (TARGET_HARD_QUAD)
2690 emit_hard_tfmode_operation (code, operands);
2692 emit_soft_tfmode_unop (code, operands);
2696 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2698 if (TARGET_HARD_QUAD)
2699 emit_hard_tfmode_operation (code, operands);
2701 emit_soft_tfmode_cvt (code, operands);
2704 /* Return nonzero if a return peephole merging return with
2705 setting of output register is ok. */
2707 leaf_return_peephole_ok (void)
2709 return (actual_fsize == 0);
2712 /* Return nonzero if a branch/jump/call instruction will be emitting
2713 nop into its delay slot. */
2716 empty_delay_slot (rtx insn)
2720 /* If no previous instruction (should not happen), return true. */
2721 if (PREV_INSN (insn) == NULL)
2724 seq = NEXT_INSN (PREV_INSN (insn));
2725 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2731 /* Return nonzero if TRIAL can go into the function epilogue's
2732 delay slot. SLOT is the slot we are trying to fill. */
2735 eligible_for_epilogue_delay (rtx trial, int slot)
2742 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2745 if (get_attr_length (trial) != 1)
2748 /* If there are any call-saved registers, we should scan TRIAL if it
2749 does not reference them. For now just make it easy. */
2753 /* If the function uses __builtin_eh_return, the eh_return machinery
2754 occupies the delay slot. */
2755 if (current_function_calls_eh_return)
2758 /* In the case of a true leaf function, anything can go into the delay slot.
2759 A delay slot only exists however if the frame size is zero, otherwise
2760 we will put an insn to adjust the stack after the return. */
2761 if (current_function_uses_only_leaf_regs)
2763 if (leaf_return_peephole_ok ())
2764 return ((get_attr_in_uncond_branch_delay (trial)
2765 == IN_BRANCH_DELAY_TRUE));
2769 pat = PATTERN (trial);
2771 /* Otherwise, only operations which can be done in tandem with
2772 a `restore' or `return' insn can go into the delay slot. */
2773 if (GET_CODE (SET_DEST (pat)) != REG
2774 || REGNO (SET_DEST (pat)) < 24)
2777 /* If this instruction sets up floating point register and we have a return
2778 instruction, it can probably go in. But restore will not work
2780 if (REGNO (SET_DEST (pat)) >= 32)
2782 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2783 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2788 /* The set of insns matched here must agree precisely with the set of
2789 patterns paired with a RETURN in sparc.md. */
2791 src = SET_SRC (pat);
2793 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2794 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2795 && arith_operand (src, GET_MODE (src)))
2798 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2800 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2803 /* This matches "*return_di". */
2804 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2805 && arith_double_operand (src, GET_MODE (src)))
2806 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2808 /* This matches "*return_sf_no_fpu". */
2809 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2810 && register_operand (src, SFmode))
2813 /* If we have return instruction, anything that does not use
2814 local or output registers and can go into a delay slot wins. */
2815 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2816 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2819 /* This matches "*return_addsi". */
2820 else if (GET_CODE (src) == PLUS
2821 && arith_operand (XEXP (src, 0), SImode)
2822 && arith_operand (XEXP (src, 1), SImode)
2823 && (register_operand (XEXP (src, 0), SImode)
2824 || register_operand (XEXP (src, 1), SImode)))
2827 /* This matches "*return_adddi". */
2828 else if (GET_CODE (src) == PLUS
2829 && arith_double_operand (XEXP (src, 0), DImode)
2830 && arith_double_operand (XEXP (src, 1), DImode)
2831 && (register_operand (XEXP (src, 0), DImode)
2832 || register_operand (XEXP (src, 1), DImode)))
2835 /* This can match "*return_losum_[sd]i".
2836 Catch only some cases, so that return_losum* don't have
2838 else if (GET_CODE (src) == LO_SUM
2839 && ! TARGET_CM_MEDMID
2840 && ((register_operand (XEXP (src, 0), SImode)
2841 && immediate_operand (XEXP (src, 1), SImode))
2843 && register_operand (XEXP (src, 0), DImode)
2844 && immediate_operand (XEXP (src, 1), DImode))))
2847 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2848 else if (GET_CODE (src) == ASHIFT
2849 && (register_operand (XEXP (src, 0), SImode)
2850 || register_operand (XEXP (src, 0), DImode))
2851 && XEXP (src, 1) == const1_rtx)
2857 /* Return nonzero if TRIAL can go into the call delay slot. */
2859 tls_call_delay (rtx trial)
2864 call __tls_get_addr, %tgd_call (foo)
2865 add %l7, %o0, %o0, %tgd_add (foo)
2866 while Sun as/ld does not. */
2867 if (TARGET_GNU_TLS || !TARGET_TLS)
2870 pat = PATTERN (trial);
2871 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
2874 unspec = XEXP (SET_DEST (pat), 1);
2875 if (GET_CODE (unspec) != UNSPEC
2876 || (XINT (unspec, 1) != UNSPEC_TLSGD
2877 && XINT (unspec, 1) != UNSPEC_TLSLDM))
2883 /* Return nonzero if TRIAL can go into the sibling call
2887 eligible_for_sibcall_delay (rtx trial)
2891 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2894 if (get_attr_length (trial) != 1)
2897 pat = PATTERN (trial);
2899 if (current_function_uses_only_leaf_regs)
2901 /* If the tail call is done using the call instruction,
2902 we have to restore %o7 in the delay slot. */
2903 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2906 /* %g1 is used to build the function address */
2907 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2913 /* Otherwise, only operations which can be done in tandem with
2914 a `restore' insn can go into the delay slot. */
2915 if (GET_CODE (SET_DEST (pat)) != REG
2916 || REGNO (SET_DEST (pat)) < 24
2917 || REGNO (SET_DEST (pat)) >= 32)
2920 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2922 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2925 src = SET_SRC (pat);
2927 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2928 && arith_operand (src, GET_MODE (src)))
2931 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2933 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2936 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2937 && arith_double_operand (src, GET_MODE (src)))
2938 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2940 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2941 && register_operand (src, SFmode))
2944 else if (GET_CODE (src) == PLUS
2945 && arith_operand (XEXP (src, 0), SImode)
2946 && arith_operand (XEXP (src, 1), SImode)
2947 && (register_operand (XEXP (src, 0), SImode)
2948 || register_operand (XEXP (src, 1), SImode)))
2951 else if (GET_CODE (src) == PLUS
2952 && arith_double_operand (XEXP (src, 0), DImode)
2953 && arith_double_operand (XEXP (src, 1), DImode)
2954 && (register_operand (XEXP (src, 0), DImode)
2955 || register_operand (XEXP (src, 1), DImode)))
2958 else if (GET_CODE (src) == LO_SUM
2959 && ! TARGET_CM_MEDMID
2960 && ((register_operand (XEXP (src, 0), SImode)
2961 && immediate_operand (XEXP (src, 1), SImode))
2963 && register_operand (XEXP (src, 0), DImode)
2964 && immediate_operand (XEXP (src, 1), DImode))))
2967 else if (GET_CODE (src) == ASHIFT
2968 && (register_operand (XEXP (src, 0), SImode)
2969 || register_operand (XEXP (src, 0), DImode))
2970 && XEXP (src, 1) == const1_rtx)
2977 check_return_regs (rtx x)
2979 switch (GET_CODE (x))
2982 return IN_OR_GLOBAL_P (x);
2997 if (check_return_regs (XEXP (x, 1)) == 0)
3002 return check_return_regs (XEXP (x, 0));
3011 short_branch (int uid1, int uid2)
3013 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3015 /* Leave a few words of "slop". */
3016 if (delta >= -1023 && delta <= 1022)
3022 /* Return nonzero if REG is not used after INSN.
3023 We assume REG is a reload reg, and therefore does
3024 not live past labels or calls or jumps. */
3026 reg_unused_after (rtx reg, rtx insn)
3028 enum rtx_code code, prev_code = UNKNOWN;
3030 while ((insn = NEXT_INSN (insn)))
3032 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3035 code = GET_CODE (insn);
3036 if (GET_CODE (insn) == CODE_LABEL)
3039 if (GET_RTX_CLASS (code) == 'i')
3041 rtx set = single_set (insn);
3042 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3045 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3047 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3055 /* Determine if it's legal to put X into the constant pool. This
3056 is not possible if X contains the address of a symbol that is
3057 not constant (TLS) or not known at final link time (PIC). */
3060 sparc_cannot_force_const_mem (rtx x)
3062 switch (GET_CODE (x))
3066 /* Accept all non-symbolic constants. */
3070 /* Labels are OK iff we are non-PIC. */
3071 return flag_pic != 0;
3074 /* 'Naked' TLS symbol references are never OK,
3075 non-TLS symbols are OK iff we are non-PIC. */
3076 if (SYMBOL_REF_TLS_MODEL (x))
3079 return flag_pic != 0;
3082 return sparc_cannot_force_const_mem (XEXP (x, 0));
3085 return sparc_cannot_force_const_mem (XEXP (x, 0))
3086 || sparc_cannot_force_const_mem (XEXP (x, 1));
3094 /* The table we use to reference PIC data. */
3095 static GTY(()) rtx global_offset_table;
3097 /* The function we use to get at it. */
3098 static GTY(()) rtx get_pc_symbol;
3099 static char get_pc_symbol_name[256];
3101 /* Ensure that we are not using patterns that are not OK with PIC. */
3109 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3110 || (GET_CODE (recog_data.operand[i]) == CONST
3111 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3112 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3113 == global_offset_table)
3114 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3123 /* Return true if X is an address which needs a temporary register when
3124 reloaded while generating PIC code. */
3127 pic_address_needs_scratch (rtx x)
3129 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3130 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3131 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3132 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3133 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3139 /* Determine if a given RTX is a valid constant. We already know this
3140 satisfies CONSTANT_P. */
3143 legitimate_constant_p (rtx x)
3147 switch (GET_CODE (x))
3150 /* TLS symbols are not constant. */
3151 if (SYMBOL_REF_TLS_MODEL (x))
3156 inner = XEXP (x, 0);
3158 /* Offsets of TLS symbols are never valid.
3159 Discourage CSE from creating them. */
3160 if (GET_CODE (inner) == PLUS
3161 && tls_symbolic_operand (XEXP (inner, 0)))
3166 if (GET_MODE (x) == VOIDmode)
3169 /* Floating point constants are generally not ok.
3170 The only exception is 0.0 in VIS. */
3172 && (GET_MODE (x) == SFmode
3173 || GET_MODE (x) == DFmode
3174 || GET_MODE (x) == TFmode)
3175 && fp_zero_operand (x, GET_MODE (x)))
3187 /* Determine if a given RTX is a valid constant address. */
3190 constant_address_p (rtx x)
3192 switch (GET_CODE (x))
3200 if (flag_pic && pic_address_needs_scratch (x))
3202 return legitimate_constant_p (x);
3205 return !flag_pic && legitimate_constant_p (x);
3212 /* Nonzero if the constant value X is a legitimate general operand
3213 when generating PIC code. It is given that flag_pic is on and
3214 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3217 legitimate_pic_operand_p (rtx x)
3219 if (pic_address_needs_scratch (x))
3221 if (tls_symbolic_operand (x)
3222 || (GET_CODE (x) == CONST
3223 && GET_CODE (XEXP (x, 0)) == PLUS
3224 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3229 /* Return nonzero if ADDR is a valid memory address.
3230 STRICT specifies whether strict register checking applies. */
3233 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3235 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3237 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3239 else if (GET_CODE (addr) == PLUS)
3241 rs1 = XEXP (addr, 0);
3242 rs2 = XEXP (addr, 1);
3244 /* Canonicalize. REG comes first, if there are no regs,
3245 LO_SUM comes first. */
3247 && GET_CODE (rs1) != SUBREG
3249 || GET_CODE (rs2) == SUBREG
3250 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3252 rs1 = XEXP (addr, 1);
3253 rs2 = XEXP (addr, 0);
3257 && rs1 == pic_offset_table_rtx
3259 && GET_CODE (rs2) != SUBREG
3260 && GET_CODE (rs2) != LO_SUM
3261 && GET_CODE (rs2) != MEM
3262 && !tls_symbolic_operand (rs2)
3263 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3264 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3266 || GET_CODE (rs1) == SUBREG)
3267 && RTX_OK_FOR_OFFSET_P (rs2)))
3272 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3273 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3275 /* We prohibit REG + REG for TFmode when there are no instructions
3276 which accept REG+REG instructions. We do this because REG+REG
3277 is not an offsetable address. If we get the situation in reload
3278 where source and destination of a movtf pattern are both MEMs with
3279 REG+REG address, then only one of them gets converted to an
3280 offsetable address. */
3282 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3283 && TARGET_HARD_QUAD))
3286 /* We prohibit REG + REG on ARCH32 if not optimizing for
3287 DFmode/DImode because then mem_min_alignment is likely to be zero
3288 after reload and the forced split would lack a matching splitter
3290 if (TARGET_ARCH32 && !optimize
3291 && (mode == DFmode || mode == DImode))
3294 else if (USE_AS_OFFSETABLE_LO10
3295 && GET_CODE (rs1) == LO_SUM
3297 && ! TARGET_CM_MEDMID
3298 && RTX_OK_FOR_OLO10_P (rs2))
3302 imm1 = XEXP (rs1, 1);
3303 rs1 = XEXP (rs1, 0);
3304 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3308 else if (GET_CODE (addr) == LO_SUM)
3310 rs1 = XEXP (addr, 0);
3311 imm1 = XEXP (addr, 1);
3313 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3316 /* We can't allow TFmode, because an offset greater than or equal to the
3317 alignment (8) may cause the LO_SUM to overflow if !v9. */
3318 if (mode == TFmode && !TARGET_V9)
3321 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3326 if (GET_CODE (rs1) == SUBREG)
3327 rs1 = SUBREG_REG (rs1);
3333 if (GET_CODE (rs2) == SUBREG)
3334 rs2 = SUBREG_REG (rs2);
3341 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3342 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3347 if ((REGNO (rs1) >= 32
3348 && REGNO (rs1) != FRAME_POINTER_REGNUM
3349 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3351 && (REGNO (rs2) >= 32
3352 && REGNO (rs2) != FRAME_POINTER_REGNUM
3353 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3359 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3361 static GTY(()) rtx sparc_tls_symbol;
3363 sparc_tls_get_addr (void)
3365 if (!sparc_tls_symbol)
3366 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3368 return sparc_tls_symbol;
3372 sparc_tls_got (void)
3377 current_function_uses_pic_offset_table = 1;
3378 return pic_offset_table_rtx;
3381 if (!global_offset_table)
3382 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3383 temp = gen_reg_rtx (Pmode);
3384 emit_move_insn (temp, global_offset_table);
3389 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3390 this (thread-local) address. */
3393 legitimize_tls_address (rtx addr)
3395 rtx temp1, temp2, temp3, ret, o0, got, insn;
3400 if (GET_CODE (addr) == SYMBOL_REF)
3401 switch (SYMBOL_REF_TLS_MODEL (addr))
3403 case TLS_MODEL_GLOBAL_DYNAMIC:
3405 temp1 = gen_reg_rtx (SImode);
3406 temp2 = gen_reg_rtx (SImode);
3407 ret = gen_reg_rtx (Pmode);
3408 o0 = gen_rtx_REG (Pmode, 8);
3409 got = sparc_tls_got ();
3410 emit_insn (gen_tgd_hi22 (temp1, addr));
3411 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3414 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3415 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3420 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3421 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3424 CALL_INSN_FUNCTION_USAGE (insn)
3425 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3426 CALL_INSN_FUNCTION_USAGE (insn));
3427 insn = get_insns ();
3429 emit_libcall_block (insn, ret, o0, addr);
3432 case TLS_MODEL_LOCAL_DYNAMIC:
3434 temp1 = gen_reg_rtx (SImode);
3435 temp2 = gen_reg_rtx (SImode);
3436 temp3 = gen_reg_rtx (Pmode);
3437 ret = gen_reg_rtx (Pmode);
3438 o0 = gen_rtx_REG (Pmode, 8);
3439 got = sparc_tls_got ();
3440 emit_insn (gen_tldm_hi22 (temp1));
3441 emit_insn (gen_tldm_lo10 (temp2, temp1));
3444 emit_insn (gen_tldm_add32 (o0, got, temp2));
3445 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3450 emit_insn (gen_tldm_add64 (o0, got, temp2));
3451 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3454 CALL_INSN_FUNCTION_USAGE (insn)
3455 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3456 CALL_INSN_FUNCTION_USAGE (insn));
3457 insn = get_insns ();
3459 emit_libcall_block (insn, temp3, o0,
3460 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3461 UNSPEC_TLSLD_BASE));
3462 temp1 = gen_reg_rtx (SImode);
3463 temp2 = gen_reg_rtx (SImode);
3464 emit_insn (gen_tldo_hix22 (temp1, addr));
3465 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3467 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3469 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3472 case TLS_MODEL_INITIAL_EXEC:
3473 temp1 = gen_reg_rtx (SImode);
3474 temp2 = gen_reg_rtx (SImode);
3475 temp3 = gen_reg_rtx (Pmode);
3476 got = sparc_tls_got ();
3477 emit_insn (gen_tie_hi22 (temp1, addr));
3478 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3480 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3482 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3485 ret = gen_reg_rtx (Pmode);
3487 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3490 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3494 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3497 case TLS_MODEL_LOCAL_EXEC:
3498 temp1 = gen_reg_rtx (Pmode);
3499 temp2 = gen_reg_rtx (Pmode);
3502 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3503 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3507 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3508 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3510 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3518 abort (); /* for now ... */
3524 /* Legitimize PIC addresses. If the address is already position-independent,
3525 we return ORIG. Newly generated position-independent addresses go into a
3526 reg. This is REG if nonzero, otherwise we allocate register(s) as
3530 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3533 if (GET_CODE (orig) == SYMBOL_REF)
3535 rtx pic_ref, address;
3540 if (reload_in_progress || reload_completed)
3543 reg = gen_reg_rtx (Pmode);
3548 /* If not during reload, allocate another temp reg here for loading
3549 in the address, so that these instructions can be optimized
3551 rtx temp_reg = ((reload_in_progress || reload_completed)
3552 ? reg : gen_reg_rtx (Pmode));
3554 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3555 won't get confused into thinking that these two instructions
3556 are loading in the true address of the symbol. If in the
3557 future a PIC rtx exists, that should be used instead. */
3558 if (Pmode == SImode)
3560 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3561 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3565 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3566 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3573 pic_ref = gen_rtx_MEM (Pmode,
3574 gen_rtx_PLUS (Pmode,
3575 pic_offset_table_rtx, address));
3576 current_function_uses_pic_offset_table = 1;
3577 RTX_UNCHANGING_P (pic_ref) = 1;
3578 insn = emit_move_insn (reg, pic_ref);
3579 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3581 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3585 else if (GET_CODE (orig) == CONST)
3589 if (GET_CODE (XEXP (orig, 0)) == PLUS
3590 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3595 if (reload_in_progress || reload_completed)
3598 reg = gen_reg_rtx (Pmode);
3601 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3603 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3604 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3605 base == reg ? 0 : reg);
3610 if (GET_CODE (offset) == CONST_INT)
3612 if (SMALL_INT (offset))
3613 return plus_constant (base, INTVAL (offset));
3614 else if (! reload_in_progress && ! reload_completed)
3615 offset = force_reg (Pmode, offset);
3617 /* If we reach here, then something is seriously wrong. */
3620 return gen_rtx_PLUS (Pmode, base, offset);
3622 else if (GET_CODE (orig) == LABEL_REF)
3623 /* ??? Why do we do this? */
3624 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3625 the register is live instead, in case it is eliminated. */
3626 current_function_uses_pic_offset_table = 1;
3631 /* Try machine-dependent ways of modifying an illegitimate address X
3632 to be legitimate. If we find one, return the new, valid address.
3634 OLDX is the address as it was before break_out_memory_refs was called.
3635 In some cases it is useful to look at this to decide what needs to be done.
3637 MODE is the mode of the operand pointed to by X. */
3640 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3644 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3645 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3646 force_operand (XEXP (x, 0), NULL_RTX));
3647 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3648 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3649 force_operand (XEXP (x, 1), NULL_RTX));
3650 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3651 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3653 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3654 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3655 force_operand (XEXP (x, 1), NULL_RTX));
3657 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3660 if (tls_symbolic_operand (x))
3661 x = legitimize_tls_address (x);
3663 x = legitimize_pic_address (x, mode, 0);
3664 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3665 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3666 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3667 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3668 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3669 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3670 else if (GET_CODE (x) == SYMBOL_REF
3671 || GET_CODE (x) == CONST
3672 || GET_CODE (x) == LABEL_REF)
3673 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3677 /* Emit special PIC prologues. */
3680 load_pic_register (void)
3682 /* Labels to get the PC in the prologue of this function. */
3683 int orig_flag_pic = flag_pic;
3688 /* If we haven't emitted the special get_pc helper function, do so now. */
3689 if (get_pc_symbol_name[0] == 0)
3693 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3696 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3698 ASM_OUTPUT_ALIGN (asm_out_file, align);
3699 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
3700 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3703 /* Initialize every time through, since we can't easily
3704 know this to be permanent. */
3705 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3706 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3709 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3712 flag_pic = orig_flag_pic;
3714 /* Need to emit this whether or not we obey regdecls,
3715 since setjmp/longjmp can cause life info to screw up.
3716 ??? In the case where we don't obey regdecls, this is not sufficient
3717 since we may not fall out the bottom. */
3718 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3721 /* Return 1 if RTX is a MEM which is known to be aligned to at
3722 least a DESIRED byte boundary. */
3725 mem_min_alignment (rtx mem, int desired)
3727 rtx addr, base, offset;
3729 /* If it's not a MEM we can't accept it. */
3730 if (GET_CODE (mem) != MEM)
3733 addr = XEXP (mem, 0);
3734 base = offset = NULL_RTX;
3735 if (GET_CODE (addr) == PLUS)
3737 if (GET_CODE (XEXP (addr, 0)) == REG)
3739 base = XEXP (addr, 0);
3741 /* What we are saying here is that if the base
3742 REG is aligned properly, the compiler will make
3743 sure any REG based index upon it will be so
3745 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3746 offset = XEXP (addr, 1);
3748 offset = const0_rtx;
3751 else if (GET_CODE (addr) == REG)
3754 offset = const0_rtx;
3757 if (base != NULL_RTX)
3759 int regno = REGNO (base);
3761 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3763 /* Check if the compiler has recorded some information
3764 about the alignment of the base REG. If reload has
3765 completed, we already matched with proper alignments.
3766 If not running global_alloc, reload might give us
3767 unaligned pointer to local stack though. */
3769 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3770 || (optimize && reload_completed))
3771 && (INTVAL (offset) & (desired - 1)) == 0)
3776 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3780 else if (! TARGET_UNALIGNED_DOUBLES
3781 || CONSTANT_P (addr)
3782 || GET_CODE (addr) == LO_SUM)
3784 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3785 is true, in which case we can only assume that an access is aligned if
3786 it is to a constant address, or the address involves a LO_SUM. */
3790 /* An obviously unaligned address. */
3795 /* Vectors to keep interesting information about registers where it can easily
3796 be got. We used to use the actual mode value as the bit number, but there
3797 are more than 32 modes now. Instead we use two tables: one indexed by
3798 hard register number, and one indexed by mode. */
3800 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3801 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3802 mapped into one sparc_mode_class mode. */
3804 enum sparc_mode_class {
3805 S_MODE, D_MODE, T_MODE, O_MODE,
3806 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3810 /* Modes for single-word and smaller quantities. */
3811 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3813 /* Modes for double-word and smaller quantities. */
3814 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3816 /* Modes for quad-word and smaller quantities. */
3817 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3819 /* Modes for 8-word and smaller quantities. */
3820 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3822 /* Modes for single-float quantities. We must allow any single word or
3823 smaller quantity. This is because the fix/float conversion instructions
3824 take integer inputs/outputs from the float registers. */
3825 #define SF_MODES (S_MODES)
3827 /* Modes for double-float and smaller quantities. */
3828 #define DF_MODES (S_MODES | D_MODES)
3830 /* Modes for double-float only quantities. */
3831 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3833 /* Modes for quad-float only quantities. */
3834 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3836 /* Modes for quad-float and smaller quantities. */
3837 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3839 /* Modes for quad-float and double-float quantities. */
3840 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3842 /* Modes for quad-float pair only quantities. */
3843 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3845 /* Modes for quad-float pairs and smaller quantities. */
3846 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3848 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3850 /* Modes for condition codes. */
3851 #define CC_MODES (1 << (int) CC_MODE)
3852 #define CCFP_MODES (1 << (int) CCFP_MODE)
3854 /* Value is 1 if register/mode pair is acceptable on sparc.
3855 The funny mixture of D and T modes is because integer operations
3856 do not specially operate on tetra quantities, so non-quad-aligned
3857 registers can hold quadword quantities (except %o4 and %i4 because
3858 they cross fixed registers). */
3860 /* This points to either the 32 bit or the 64 bit version. */
3861 const int *hard_regno_mode_classes;
3863 static const int hard_32bit_mode_classes[] = {
3864 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3865 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3866 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3867 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3869 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3870 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3871 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3872 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3874 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3875 and none can hold SFmode/SImode values. */
3876 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3877 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3878 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3879 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3882 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3888 static const int hard_64bit_mode_classes[] = {
3889 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3890 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3891 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3892 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3894 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3895 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3896 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3897 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3899 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3900 and none can hold SFmode/SImode values. */
3901 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3902 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3903 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3904 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3907 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3913 int sparc_mode_class [NUM_MACHINE_MODES];
3915 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3918 sparc_init_modes (void)
3922 for (i = 0; i < NUM_MACHINE_MODES; i++)
3924 switch (GET_MODE_CLASS (i))
3927 case MODE_PARTIAL_INT:
3928 case MODE_COMPLEX_INT:
3929 if (GET_MODE_SIZE (i) <= 4)
3930 sparc_mode_class[i] = 1 << (int) S_MODE;
3931 else if (GET_MODE_SIZE (i) == 8)
3932 sparc_mode_class[i] = 1 << (int) D_MODE;
3933 else if (GET_MODE_SIZE (i) == 16)
3934 sparc_mode_class[i] = 1 << (int) T_MODE;
3935 else if (GET_MODE_SIZE (i) == 32)
3936 sparc_mode_class[i] = 1 << (int) O_MODE;
3938 sparc_mode_class[i] = 0;
3941 case MODE_COMPLEX_FLOAT:
3942 if (GET_MODE_SIZE (i) <= 4)
3943 sparc_mode_class[i] = 1 << (int) SF_MODE;
3944 else if (GET_MODE_SIZE (i) == 8)
3945 sparc_mode_class[i] = 1 << (int) DF_MODE;
3946 else if (GET_MODE_SIZE (i) == 16)
3947 sparc_mode_class[i] = 1 << (int) TF_MODE;
3948 else if (GET_MODE_SIZE (i) == 32)
3949 sparc_mode_class[i] = 1 << (int) OF_MODE;
3951 sparc_mode_class[i] = 0;
3955 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3956 we must explicitly check for them here. */
3957 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3958 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3959 else if (i == (int) CCmode || i == (int) CC_NOOVmode
3960 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3961 sparc_mode_class[i] = 1 << (int) CC_MODE;
3963 sparc_mode_class[i] = 0;
3969 hard_regno_mode_classes = hard_64bit_mode_classes;
3971 hard_regno_mode_classes = hard_32bit_mode_classes;
3973 /* Initialize the array used by REGNO_REG_CLASS. */
3974 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3976 if (i < 16 && TARGET_V8PLUS)
3977 sparc_regno_reg_class[i] = I64_REGS;
3978 else if (i < 32 || i == FRAME_POINTER_REGNUM)
3979 sparc_regno_reg_class[i] = GENERAL_REGS;
3981 sparc_regno_reg_class[i] = FP_REGS;
3983 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3985 sparc_regno_reg_class[i] = FPCC_REGS;
3987 sparc_regno_reg_class[i] = NO_REGS;
3991 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3992 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3993 v9 int regs as it simplifies the code. */
3996 save_regs (FILE *file, int low, int high, const char *base,
3997 int offset, int n_regs, int real_offset)
4001 if (TARGET_ARCH64 && high <= 32)
4003 for (i = low; i < high; i++)
4005 if (regs_ever_live[i] && ! call_used_regs[i])
4007 fprintf (file, "\tstx\t%s, [%s+%d]\n",
4008 reg_names[i], base, offset + 4 * n_regs);
4009 if (dwarf2out_do_frame ())
4010 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4017 for (i = low; i < high; i += 2)
4019 if (regs_ever_live[i] && ! call_used_regs[i])
4021 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4023 fprintf (file, "\tstd\t%s, [%s+%d]\n",
4024 reg_names[i], base, offset + 4 * n_regs);
4025 if (dwarf2out_do_frame ())
4027 char *l = dwarf2out_cfi_label ();
4028 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
4029 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
4035 fprintf (file, "\tst\t%s, [%s+%d]\n",
4036 reg_names[i], base, offset + 4 * n_regs);
4037 if (dwarf2out_do_frame ())
4038 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4044 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4046 fprintf (file, "\tst\t%s, [%s+%d]\n",
4047 reg_names[i+1], base, offset + 4 * n_regs + 4);
4048 if (dwarf2out_do_frame ())
4049 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
4058 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
4060 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4061 v9 int regs as it simplifies the code. */
4064 restore_regs (FILE *file, int low, int high, const char *base,
4065 int offset, int n_regs)
4069 if (TARGET_ARCH64 && high <= 32)
4071 for (i = low; i < high; i++)
4073 if (regs_ever_live[i] && ! call_used_regs[i])
4074 fprintf (file, "\tldx\t[%s+%d], %s\n",
4075 base, offset + 4 * n_regs, reg_names[i]),
4081 for (i = low; i < high; i += 2)
4083 if (regs_ever_live[i] && ! call_used_regs[i])
4084 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4085 fprintf (file, "\tldd\t[%s+%d], %s\n",
4086 base, offset + 4 * n_regs, reg_names[i]),
4089 fprintf (file, "\tld\t[%s+%d], %s\n",
4090 base, offset + 4 * n_regs, reg_names[i]),
4092 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4093 fprintf (file, "\tld\t[%s+%d], %s\n",
4094 base, offset + 4 * n_regs + 4, reg_names[i+1]),
4101 /* Compute the frame size required by the function. This function is called
4102 during the reload pass and also by output_function_prologue(). */
4105 compute_frame_size (int size, int leaf_function)
4108 int outgoing_args_size = (current_function_outgoing_args_size
4109 + REG_PARM_STACK_SPACE (current_function_decl));
4111 /* N_REGS is the number of 4-byte regs saved thus far. This applies
4112 even to v9 int regs to be consistent with save_regs/restore_regs. */
4116 for (i = 0; i < 8; i++)
4117 if (regs_ever_live[i] && ! call_used_regs[i])
4122 for (i = 0; i < 8; i += 2)
4123 if ((regs_ever_live[i] && ! call_used_regs[i])
4124 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4128 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4129 if ((regs_ever_live[i] && ! call_used_regs[i])
4130 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4133 /* Set up values for use in `function_epilogue'. */
4134 num_gfregs = n_regs;
4136 if (leaf_function && n_regs == 0
4137 && size == 0 && current_function_outgoing_args_size == 0)
4139 actual_fsize = apparent_fsize = 0;
4143 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4144 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4145 apparent_fsize += n_regs * 4;
4146 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4149 /* Make sure nothing can clobber our register windows.
4150 If a SAVE must be done, or there is a stack-local variable,
4151 the register window area must be allocated.
4152 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4153 if (leaf_function == 0 || size > 0)
4154 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4156 return SPARC_STACK_ALIGN (actual_fsize);
4159 /* Build a (32 bit) big number in a register. */
4160 /* ??? We may be able to use the set macro here too. */
4163 build_big_number (FILE *file, int num, const char *reg)
4165 if (num >= 0 || ! TARGET_ARCH64)
4167 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
4168 if ((num & 0x3ff) != 0)
4169 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
4171 else /* num < 0 && TARGET_ARCH64 */
4173 /* Sethi does not sign extend, so we must use a little trickery
4174 to use it for negative numbers. Invert the constant before
4175 loading it in, then use xor immediate to invert the loaded bits
4176 (along with the upper 32 bits) to the desired constant. This
4177 works because the sethi and immediate fields overlap. */
4180 int low = -0x400 + (asize & 0x3FF);
4182 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
4183 inv, reg, reg, low, reg);
4187 /* Output any necessary .register pseudo-ops. */
4189 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4191 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4197 /* Check if %g[2367] were used without
4198 .register being printed for them already. */
4199 for (i = 2; i < 8; i++)
4201 if (regs_ever_live [i]
4202 && ! sparc_hard_reg_printed [i])
4204 sparc_hard_reg_printed [i] = 1;
4205 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4212 /* This function generates the assembly code for function entry.
4213 FILE is a stdio stream to output the code to.
4214 SIZE is an int: how many units of temporary storage to allocate.
4215 Refer to the array `regs_ever_live' to determine which registers
4216 to save; `regs_ever_live[I]' is nonzero if register number I
4217 is ever used in the function. This macro is responsible for
4218 knowing which registers should not be saved even if used. */
4220 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
4221 of memory. If any fpu reg is used in the function, we allocate
4222 such a block here, at the bottom of the frame, just in case it's needed.
4224 If this function is a leaf procedure, then we may choose not
4225 to do a "save" insn. The decision about whether or not
4226 to do this is made in regclass.c. */
4229 sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size)
4232 sparc_flat_function_prologue (file, size);
4234 sparc_nonflat_function_prologue (file, size,
4235 current_function_uses_only_leaf_regs);
4238 /* Output code for the function prologue. */
4241 sparc_nonflat_function_prologue (FILE *file, HOST_WIDE_INT size,
4244 sparc_output_scratch_registers (file);
4246 /* Need to use actual_fsize, since we are also allocating
4247 space for our callee (and our own register save area). */
4248 actual_fsize = compute_frame_size (size, leaf_function);
4252 frame_base_name = "%sp";
4253 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4257 frame_base_name = "%fp";
4258 frame_base_offset = SPARC_STACK_BIAS;
4261 /* This is only for the human reader. */
4262 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
4264 if (actual_fsize == 0)
4266 else if (! leaf_function)
4268 if (actual_fsize <= 4096)
4269 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
4270 else if (actual_fsize <= 8192)
4272 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
4273 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
4277 build_big_number (file, -actual_fsize, "%g1");
4278 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
4281 else /* leaf function */
4283 if (actual_fsize <= 4096)
4284 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
4285 else if (actual_fsize <= 8192)
4287 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
4288 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
4292 build_big_number (file, -actual_fsize, "%g1");
4293 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
4297 if (dwarf2out_do_frame () && actual_fsize)
4299 char *label = dwarf2out_cfi_label ();
4301 /* The canonical frame address refers to the top of the frame. */
4302 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
4303 : HARD_FRAME_POINTER_REGNUM),
4306 if (! leaf_function)
4308 /* Note the register window save. This tells the unwinder that
4309 it needs to restore the window registers from the previous
4310 frame's window save area at 0(cfa). */
4311 dwarf2out_window_save (label);
4313 /* The return address (-8) is now in %i7. */
4314 dwarf2out_return_reg (label, 31);
4318 /* If doing anything with PIC, do it now. */
4320 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
4322 /* Call saved registers are saved just above the outgoing argument area. */
4325 int offset, real_offset, n_regs;
4328 real_offset = -apparent_fsize;
4329 offset = -apparent_fsize + frame_base_offset;
4330 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4332 /* ??? This might be optimized a little as %g1 might already have a
4333 value close enough that a single add insn will do. */
4334 /* ??? Although, all of this is probably only a temporary fix
4335 because if %g1 can hold a function result, then
4336 output_function_epilogue will lose (the result will get
4338 build_big_number (file, offset, "%g1");
4339 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4345 base = frame_base_name;
4348 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
4349 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
4354 /* Output code to restore any call saved registers. */
4357 output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED)
4362 offset = -apparent_fsize + frame_base_offset;
4363 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4365 build_big_number (file, offset, "%g1");
4366 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4372 base = frame_base_name;
4375 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4376 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4379 /* This function generates the assembly code for function exit,
4380 on machines that need it.
4382 The function epilogue should not depend on the current stack pointer!
4383 It should use the frame pointer only. This is mandatory because
4384 of alloca; we also take advantage of it to omit stack adjustments
4385 before returning. */
4388 sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size)
4391 sparc_flat_function_epilogue (file, size);
4393 sparc_nonflat_function_epilogue (file, size,
4394 current_function_uses_only_leaf_regs);
4397 /* Output code for the function epilogue. */
4400 sparc_nonflat_function_epilogue (FILE *file,
4401 HOST_WIDE_INT size ATTRIBUTE_UNUSED,
4406 if (current_function_epilogue_delay_list == 0)
4408 /* If code does not drop into the epilogue, we need
4409 do nothing except output pending case vectors.
4411 We have to still output a dummy nop for the sake of
4412 sane backtraces. Otherwise, if the last two instructions
4413 of a function were call foo; dslot; this can make the return
4414 PC of foo (ie. address of call instruction plus 8) point to
4415 the first instruction in the next function. */
4416 rtx insn, last_real_insn;
4418 insn = get_last_insn ();
4420 last_real_insn = prev_real_insn (insn);
4422 && GET_CODE (last_real_insn) == INSN
4423 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4424 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4426 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4427 fputs("\tnop\n", file);
4429 if (GET_CODE (insn) == NOTE)
4430 insn = prev_nonnote_insn (insn);
4431 if (insn && GET_CODE (insn) == BARRIER)
4432 goto output_vectors;
4436 output_restore_regs (file, leaf_function);
4438 /* Work out how to skip the caller's unimp instruction if required. */
4440 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4442 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4444 if (! leaf_function)
4446 if (current_function_calls_eh_return)
4448 if (current_function_epilogue_delay_list)
4450 if (SKIP_CALLERS_UNIMP_P)
4453 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4455 /* If we wound up with things in our delay slot, flush them here. */
4456 else if (current_function_epilogue_delay_list)
4458 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4460 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4462 epilogue_renumber (&delay, 0);
4463 fputs (SKIP_CALLERS_UNIMP_P
4464 ? "\treturn\t%i7+12\n"
4465 : "\treturn\t%i7+8\n", file);
4466 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4473 if (GET_CODE (delay) != SET)
4476 src = SET_SRC (delay);
4477 if (GET_CODE (src) == ASHIFT)
4479 if (XEXP (src, 1) != const1_rtx)
4482 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4486 insn = gen_rtx_PARALLEL (VOIDmode,
4487 gen_rtvec (2, delay,
4488 gen_rtx_RETURN (VOIDmode)));
4489 insn = emit_jump_insn (insn);
4491 sparc_emitting_epilogue = true;
4492 final_scan_insn (insn, file, 1, 0, 1);
4493 sparc_emitting_epilogue = false;
4496 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4497 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4499 fprintf (file, "\t%s\n\trestore\n", ret);
4501 /* All of the following cases are for leaf functions. */
4502 else if (current_function_calls_eh_return)
4504 else if (current_function_epilogue_delay_list)
4506 /* eligible_for_epilogue_delay_slot ensures that if this is a
4507 leaf function, then we will only have insn in the delay slot
4508 if the frame size is zero, thus no adjust for the stack is
4510 if (actual_fsize != 0)
4512 fprintf (file, "\t%s\n", ret);
4513 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4516 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4517 avoid generating confusing assembly language output. */
4518 else if (actual_fsize == 0)
4519 fprintf (file, "\t%s\n\tnop\n", ret);
4520 else if (actual_fsize <= 4096)
4521 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
4522 else if (actual_fsize <= 8192)
4523 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4524 ret, actual_fsize - 4096);
4525 else if ((actual_fsize & 0x3ff) == 0)
4526 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4529 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4530 actual_fsize, actual_fsize, ret);
4533 sparc_output_deferred_case_vectors ();
4536 /* Output a sibling call. */
4539 output_sibcall (rtx insn, rtx call_operand)
4541 int leaf_regs = current_function_uses_only_leaf_regs;
4543 int delay_slot = dbr_sequence_length () > 0;
4547 /* Call to restore global regs might clobber
4548 the delay slot. Instead of checking for this
4549 output the delay slot now. */
4552 rtx delay = NEXT_INSN (insn);
4557 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4558 PATTERN (delay) = gen_blockage ();
4559 INSN_CODE (delay) = -1;
4562 output_restore_regs (asm_out_file, leaf_regs);
4565 operands[0] = call_operand;
4569 #ifdef HAVE_AS_RELAX_OPTION
4570 /* If as and ld are relaxing tail call insns into branch always,
4571 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4572 be optimized. With sethi/jmpl as nor ld has no easy way how to
4573 find out if somebody does not branch between the sethi and jmpl. */
4576 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4580 if ((actual_fsize || ! spare_slot) && delay_slot)
4582 rtx delay = NEXT_INSN (insn);
4587 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4588 PATTERN (delay) = gen_blockage ();
4589 INSN_CODE (delay) = -1;
4594 if (actual_fsize <= 4096)
4595 size = actual_fsize;
4596 else if (actual_fsize <= 8192)
4598 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4599 size = actual_fsize - 4096;
4601 else if ((actual_fsize & 0x3ff) == 0)
4602 fprintf (asm_out_file,
4603 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4607 fprintf (asm_out_file,
4608 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4609 actual_fsize, actual_fsize);
4610 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4615 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4616 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4618 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size);
4619 else if (! delay_slot)
4620 fputs ("\t nop\n", asm_out_file);
4625 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size);
4626 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4627 it into branch if possible. */
4628 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4629 output_asm_insn ("call\t%a0, 0", operands);
4630 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4635 output_asm_insn ("call\t%a0, 0", operands);
4638 rtx delay = NEXT_INSN (insn), pat;
4643 pat = PATTERN (delay);
4644 if (GET_CODE (pat) != SET)
4647 operands[0] = SET_DEST (pat);
4648 pat = SET_SRC (pat);
4649 switch (GET_CODE (pat))
4652 operands[1] = XEXP (pat, 0);
4653 operands[2] = XEXP (pat, 1);
4654 output_asm_insn (" restore %r1, %2, %Y0", operands);
4657 operands[1] = XEXP (pat, 0);
4658 operands[2] = XEXP (pat, 1);
4659 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4662 operands[1] = XEXP (pat, 0);
4663 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4667 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4670 PATTERN (delay) = gen_blockage ();
4671 INSN_CODE (delay) = -1;
4674 fputs ("\t restore\n", asm_out_file);
4678 /* Functions for handling argument passing.
4680 For v8 the first six args are normally in registers and the rest are
4681 pushed. Any arg that starts within the first 6 words is at least
4682 partially passed in a register unless its data type forbids.
4684 For v9, the argument registers are laid out as an array of 16 elements
4685 and arguments are added sequentially. The first 6 int args and up to the
4686 first 16 fp args (depending on size) are passed in regs.
4688 Slot Stack Integral Float Float in structure Double Long Double
4689 ---- ----- -------- ----- ------------------ ------ -----------
4690 15 [SP+248] %f31 %f30,%f31 %d30
4691 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4692 13 [SP+232] %f27 %f26,%f27 %d26
4693 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4694 11 [SP+216] %f23 %f22,%f23 %d22
4695 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4696 9 [SP+200] %f19 %f18,%f19 %d18
4697 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4698 7 [SP+184] %f15 %f14,%f15 %d14
4699 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4700 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4701 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4702 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4703 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4704 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4705 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4707 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4709 Integral arguments are always passed as 64 bit quantities appropriately
4712 Passing of floating point values is handled as follows.
4713 If a prototype is in scope:
4714 If the value is in a named argument (i.e. not a stdarg function or a
4715 value not part of the `...') then the value is passed in the appropriate
4717 If the value is part of the `...' and is passed in one of the first 6
4718 slots then the value is passed in the appropriate int reg.
4719 If the value is part of the `...' and is not passed in one of the first 6
4720 slots then the value is passed in memory.
4721 If a prototype is not in scope:
4722 If the value is one of the first 6 arguments the value is passed in the
4723 appropriate integer reg and the appropriate fp reg.
4724 If the value is not one of the first 6 arguments the value is passed in
4725 the appropriate fp reg and in memory.
4728 /* Maximum number of int regs for args. */
4729 #define SPARC_INT_ARG_MAX 6
4730 /* Maximum number of fp regs for args. */
4731 #define SPARC_FP_ARG_MAX 16
4733 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4735 /* Handle the INIT_CUMULATIVE_ARGS macro.
4736 Initialize a variable CUM of type CUMULATIVE_ARGS
4737 for a call to a function whose data type is FNTYPE.
4738 For a library call, FNTYPE is 0. */
4741 init_cumulative_args (struct sparc_args *cum, tree fntype,
4742 rtx libname ATTRIBUTE_UNUSED,
4743 tree fndecl ATTRIBUTE_UNUSED)
4746 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4747 cum->libcall_p = fntype == 0;
4750 /* Compute the slot number to pass an argument in.
4751 Returns the slot number or -1 if passing on the stack.
4753 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4754 the preceding args and about the function being called.
4755 MODE is the argument's machine mode.
4756 TYPE is the data type of the argument (as a tree).
4757 This is null for libcalls where that information may
4759 NAMED is nonzero if this argument is a named parameter
4760 (otherwise it is an extra parameter matching an ellipsis).
4761 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4762 *PREGNO records the register number to use if scalar type.
4763 *PPADDING records the amount of padding needed in words. */
4766 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
4767 tree type, int named, int incoming_p,
4768 int *pregno, int *ppadding)
4770 int regbase = (incoming_p
4771 ? SPARC_INCOMING_INT_ARG_FIRST
4772 : SPARC_OUTGOING_INT_ARG_FIRST);
4773 int slotno = cum->words;
4778 if (type != 0 && TREE_ADDRESSABLE (type))
4781 && type != 0 && mode == BLKmode
4782 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4788 /* MODE is VOIDmode when generating the actual call.
4792 case QImode : case CQImode :
4793 case HImode : case CHImode :
4794 case SImode : case CSImode :
4795 case DImode : case CDImode :
4796 case TImode : case CTImode :
4797 if (slotno >= SPARC_INT_ARG_MAX)
4799 regno = regbase + slotno;
4802 case SFmode : case SCmode :
4803 case DFmode : case DCmode :
4804 case TFmode : case TCmode :
4807 if (slotno >= SPARC_INT_ARG_MAX)
4809 regno = regbase + slotno;
4813 if ((mode == TFmode || mode == TCmode)
4814 && (slotno & 1) != 0)
4815 slotno++, *ppadding = 1;
4816 if (TARGET_FPU && named)
4818 if (slotno >= SPARC_FP_ARG_MAX)
4820 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4826 if (slotno >= SPARC_INT_ARG_MAX)
4828 regno = regbase + slotno;
4834 /* For sparc64, objects requiring 16 byte alignment get it. */
4837 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
4838 slotno++, *ppadding = 1;
4842 || (type && TREE_CODE (type) == UNION_TYPE))
4844 if (slotno >= SPARC_INT_ARG_MAX)
4846 regno = regbase + slotno;
4851 int intregs_p = 0, fpregs_p = 0;
4852 /* The ABI obviously doesn't specify how packed
4853 structures are passed. These are defined to be passed
4854 in int regs if possible, otherwise memory. */
4857 /* First see what kinds of registers we need. */
4858 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4860 if (TREE_CODE (field) == FIELD_DECL)
4862 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4867 if (DECL_PACKED (field))
4871 if (packed_p || !named)
4872 fpregs_p = 0, intregs_p = 1;
4874 /* If all arg slots are filled, then must pass on stack. */
4875 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4877 /* If there are only int args and all int arg slots are filled,
4878 then must pass on stack. */
4879 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4881 /* Note that even if all int arg slots are filled, fp members may
4882 still be passed in regs if such regs are available.
4883 *PREGNO isn't set because there may be more than one, it's up
4884 to the caller to compute them. */
4897 /* Handle recursive register counting for structure field layout. */
4899 struct function_arg_record_value_parms
4901 rtx ret; /* return expression being built. */
4902 int slotno; /* slot number of the argument. */
4903 int named; /* whether the argument is named. */
4904 int regbase; /* regno of the base register. */
4905 int stack; /* 1 if part of the argument is on the stack. */
4906 int intoffset; /* offset of the pending integer field. */
4907 unsigned int nregs; /* number of words passed in registers. */
4910 static void function_arg_record_value_3
4911 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
4912 static void function_arg_record_value_2
4913 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *);
4914 static void function_arg_record_value_1
4915 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *);
4916 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
4918 /* A subroutine of function_arg_record_value. Traverse the structure
4919 recursively and determine how many registers will be required. */
4922 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
4923 struct function_arg_record_value_parms *parms)
4927 /* The ABI obviously doesn't specify how packed structures are
4928 passed. These are defined to be passed in int regs if possible,
4929 otherwise memory. */
4932 /* We need to compute how many registers are needed so we can
4933 allocate the PARALLEL but before we can do that we need to know
4934 whether there are any packed fields. If there are, int regs are
4935 used regardless of whether there are fp values present. */
4936 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4938 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4945 /* Compute how many registers we need. */
4946 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4948 if (TREE_CODE (field) == FIELD_DECL)
4950 HOST_WIDE_INT bitpos = startbitpos;
4952 if (DECL_SIZE (field) != 0
4953 && host_integerp (bit_position (field), 1))
4954 bitpos += int_bit_position (field);
4956 /* ??? FIXME: else assume zero offset. */
4958 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4959 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
4960 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4961 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4962 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4968 if (parms->intoffset != -1)
4970 int intslots, this_slotno;
4972 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
4974 this_slotno = parms->slotno + parms->intoffset
4977 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
4979 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
4980 /* We need to pass this field on the stack. */
4984 parms->nregs += intslots;
4985 parms->intoffset = -1;
4988 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4989 If it wasn't true we wouldn't be here. */
4991 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4996 if (parms->intoffset == -1)
4997 parms->intoffset = bitpos;
5003 /* A subroutine of function_arg_record_value. Assign the bits of the
5004 structure between parms->intoffset and bitpos to integer registers. */
5007 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5008 struct function_arg_record_value_parms *parms)
5010 enum machine_mode mode;
5012 unsigned int startbit, endbit;
5013 int this_slotno, intslots, intoffset;
5016 if (parms->intoffset == -1)
5019 intoffset = parms->intoffset;
5020 parms->intoffset = -1;
5022 startbit = intoffset & -BITS_PER_WORD;
5023 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5024 intslots = (endbit - startbit) / BITS_PER_WORD;
5025 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5027 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5031 /* If this is the trailing part of a word, only load that much into
5032 the register. Otherwise load the whole register. Note that in
5033 the latter case we may pick up unwanted bits. It's not a problem
5034 at the moment but may wish to revisit. */
5036 if (intoffset % BITS_PER_WORD != 0)
5037 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5042 intoffset /= BITS_PER_UNIT;
5045 regno = parms->regbase + this_slotno;
5046 reg = gen_rtx_REG (mode, regno);
5047 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5048 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5051 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5055 while (intslots > 0);
5058 /* A subroutine of function_arg_record_value. Traverse the structure
5059 recursively and assign bits to floating point registers. Track which
5060 bits in between need integer registers; invoke function_arg_record_value_3
5061 to make that happen. */
5064 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5065 struct function_arg_record_value_parms *parms)
5070 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5072 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5079 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5081 if (TREE_CODE (field) == FIELD_DECL)
5083 HOST_WIDE_INT bitpos = startbitpos;
5085 if (DECL_SIZE (field) != 0
5086 && host_integerp (bit_position (field), 1))
5087 bitpos += int_bit_position (field);
5089 /* ??? FIXME: else assume zero offset. */
5091 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5092 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
5093 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
5094 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
5095 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
5101 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5103 enum machine_mode mode = DECL_MODE (field);
5106 function_arg_record_value_3 (bitpos, parms);
5107 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
5108 + ((mode == SFmode || mode == SCmode)
5109 && (bitpos & 32) != 0);
5112 case SCmode: mode = SFmode; break;
5113 case DCmode: mode = DFmode; break;
5114 case TCmode: mode = TFmode; break;
5117 reg = gen_rtx_REG (mode, regno);
5118 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5119 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5120 GEN_INT (bitpos / BITS_PER_UNIT));
5122 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5124 regno += GET_MODE_SIZE (mode) / 4;
5125 reg = gen_rtx_REG (mode, regno);
5126 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5127 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5128 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5135 if (parms->intoffset == -1)
5136 parms->intoffset = bitpos;
5142 /* Used by function_arg and function_value to implement the complex
5143 conventions of the 64-bit ABI for passing and returning structures.
5144 Return an expression valid as a return value for the two macros
5145 FUNCTION_ARG and FUNCTION_VALUE.
5147 TYPE is the data type of the argument (as a tree).
5148 This is null for libcalls where that information may
5150 MODE is the argument's machine mode.
5151 SLOTNO is the index number of the argument's slot in the parameter array.
5152 NAMED is nonzero if this argument is a named parameter
5153 (otherwise it is an extra parameter matching an ellipsis).
5154 REGBASE is the regno of the base register for the parameter array. */
5157 function_arg_record_value (tree type, enum machine_mode mode,
5158 int slotno, int named, int regbase)
5160 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5161 struct function_arg_record_value_parms parms;
5164 parms.ret = NULL_RTX;
5165 parms.slotno = slotno;
5166 parms.named = named;
5167 parms.regbase = regbase;
5170 /* Compute how many registers we need. */
5172 parms.intoffset = 0;
5173 function_arg_record_value_1 (type, 0, &parms);
5175 if (parms.intoffset != -1)
5177 unsigned int startbit, endbit;
5178 int intslots, this_slotno;
5180 startbit = parms.intoffset & -BITS_PER_WORD;
5181 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5182 intslots = (endbit - startbit) / BITS_PER_WORD;
5183 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5185 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5187 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5188 /* We need to pass this field on the stack. */
5192 parms.nregs += intslots;
5194 nregs = parms.nregs;
5196 /* Allocate the vector and handle some annoying special cases. */
5199 /* ??? Empty structure has no value? Duh? */
5202 /* Though there's nothing really to store, return a word register
5203 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5204 leads to breakage due to the fact that there are zero bytes to
5206 return gen_rtx_REG (mode, regbase);
5210 /* ??? C++ has structures with no fields, and yet a size. Give up
5211 for now and pass everything back in integer registers. */
5212 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5214 if (nregs + slotno > SPARC_INT_ARG_MAX)
5215 nregs = SPARC_INT_ARG_MAX - slotno;
5220 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5222 /* If at least one field must be passed on the stack, generate
5223 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5224 also be passed on the stack. We can't do much better because the
5225 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5226 of structures for which the fields passed exclusively in registers
5227 are not at the beginning of the structure. */
5229 XVECEXP (parms.ret, 0, 0)
5230 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5232 /* Fill in the entries. */
5234 parms.intoffset = 0;
5235 function_arg_record_value_2 (type, 0, &parms);
5236 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5238 if (parms.nregs != nregs)
5244 /* Handle the FUNCTION_ARG macro.
5245 Determine where to put an argument to a function.
5246 Value is zero to push the argument on the stack,
5247 or a hard register in which to store the argument.
5249 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5250 the preceding args and about the function being called.
5251 MODE is the argument's machine mode.
5252 TYPE is the data type of the argument (as a tree).
5253 This is null for libcalls where that information may
5255 NAMED is nonzero if this argument is a named parameter
5256 (otherwise it is an extra parameter matching an ellipsis).
5257 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5260 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5261 tree type, int named, int incoming_p)
5263 int regbase = (incoming_p
5264 ? SPARC_INCOMING_INT_ARG_FIRST
5265 : SPARC_OUTGOING_INT_ARG_FIRST);
5266 int slotno, regno, padding;
5269 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5277 reg = gen_rtx_REG (mode, regno);
5281 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5282 but also have the slot allocated for them.
5283 If no prototype is in scope fp values in register slots get passed
5284 in two places, either fp regs and int regs or fp regs and memory. */
5285 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5286 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5287 && SPARC_FP_REG_P (regno))
5289 reg = gen_rtx_REG (mode, regno);
5290 if (cum->prototype_p || cum->libcall_p)
5292 /* "* 2" because fp reg numbers are recorded in 4 byte
5295 /* ??? This will cause the value to be passed in the fp reg and
5296 in the stack. When a prototype exists we want to pass the
5297 value in the reg but reserve space on the stack. That's an
5298 optimization, and is deferred [for a bit]. */
5299 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5300 return gen_rtx_PARALLEL (mode,
5302 gen_rtx_EXPR_LIST (VOIDmode,
5303 NULL_RTX, const0_rtx),
5304 gen_rtx_EXPR_LIST (VOIDmode,
5308 /* ??? It seems that passing back a register even when past
5309 the area declared by REG_PARM_STACK_SPACE will allocate
5310 space appropriately, and will not copy the data onto the
5311 stack, exactly as we desire.
5313 This is due to locate_and_pad_parm being called in
5314 expand_call whenever reg_parm_stack_space > 0, which
5315 while beneficial to our example here, would seem to be
5316 in error from what had been intended. Ho hum... -- r~ */
5324 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5328 /* On incoming, we don't need to know that the value
5329 is passed in %f0 and %i0, and it confuses other parts
5330 causing needless spillage even on the simplest cases. */
5334 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5335 + (regno - SPARC_FP_ARG_FIRST) / 2);
5337 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5338 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5340 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5344 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5345 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5346 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5350 else if (type && TREE_CODE (type) == RECORD_TYPE)
5352 /* Structures up to 16 bytes in size are passed in arg slots on the
5353 stack and are promoted to registers where possible. */
5355 if (int_size_in_bytes (type) > 16)
5356 abort (); /* shouldn't get here */
5358 return function_arg_record_value (type, mode, slotno, named, regbase);
5360 else if (type && TREE_CODE (type) == UNION_TYPE)
5362 enum machine_mode mode;
5363 int bytes = int_size_in_bytes (type);
5368 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5369 reg = gen_rtx_REG (mode, regno);
5373 /* Scalar or complex int. */
5374 reg = gen_rtx_REG (mode, regno);
5380 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5381 For an arg passed partly in registers and partly in memory,
5382 this is the number of registers used.
5383 For args passed entirely in registers or entirely in memory, zero.
5385 Any arg that starts in the first 6 regs but won't entirely fit in them
5386 needs partial registers on v8. On v9, structures with integer
5387 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5388 values that begin in the last fp reg [where "last fp reg" varies with the
5389 mode] will be split between that reg and memory. */
5392 function_arg_partial_nregs (const struct sparc_args *cum,
5393 enum machine_mode mode, tree type, int named)
5395 int slotno, regno, padding;
5397 /* We pass 0 for incoming_p here, it doesn't matter. */
5398 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5405 if ((slotno + (mode == BLKmode
5406 ? ROUND_ADVANCE (int_size_in_bytes (type))
5407 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5408 > NPARM_REGS (SImode))
5409 return NPARM_REGS (SImode) - slotno;
5414 if (type && AGGREGATE_TYPE_P (type))
5416 int size = int_size_in_bytes (type);
5417 int align = TYPE_ALIGN (type);
5420 slotno += slotno & 1;
5421 if (size > 8 && size <= 16
5422 && slotno == SPARC_INT_ARG_MAX - 1)
5425 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5426 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5427 && ! (TARGET_FPU && named)))
5429 if (GET_MODE_ALIGNMENT (mode) == 128)
5431 slotno += slotno & 1;
5432 if (slotno == SPARC_INT_ARG_MAX - 2)
5437 if (slotno == SPARC_INT_ARG_MAX - 1)
5441 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5443 if (GET_MODE_ALIGNMENT (mode) == 128)
5444 slotno += slotno & 1;
5445 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5453 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5454 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5455 quad-precision floats by invisible reference.
5456 v9: Aggregates greater than 16 bytes are passed by reference.
5457 For Pascal, also pass arrays by reference. */
5460 function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
5461 enum machine_mode mode, tree type,
5462 int named ATTRIBUTE_UNUSED)
5466 return ((type && AGGREGATE_TYPE_P (type))
5467 || mode == TFmode || mode == TCmode);
5471 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5472 /* Consider complex values as aggregates, so care for TCmode. */
5473 || GET_MODE_SIZE (mode) > 16
5475 && AGGREGATE_TYPE_P (type)
5476 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5480 /* Handle the FUNCTION_ARG_ADVANCE macro.
5481 Update the data in CUM to advance over an argument
5482 of mode MODE and data type TYPE.
5483 TYPE is null for libcalls where that information may not be available. */
5486 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5487 tree type, int named)
5489 int slotno, regno, padding;
5491 /* We pass 0 for incoming_p here, it doesn't matter. */
5492 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5494 /* If register required leading padding, add it. */
5496 cum->words += padding;
5500 cum->words += (mode != BLKmode
5501 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5502 : ROUND_ADVANCE (int_size_in_bytes (type)));
5506 if (type && AGGREGATE_TYPE_P (type))
5508 int size = int_size_in_bytes (type);
5512 else if (size <= 16)
5514 else /* passed by reference */
5517 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
5521 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5523 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
5527 cum->words += (mode != BLKmode
5528 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5529 : ROUND_ADVANCE (int_size_in_bytes (type)));
5534 /* Handle the FUNCTION_ARG_PADDING macro.
5535 For the 64 bit ABI structs are always stored left shifted in their
5539 function_arg_padding (enum machine_mode mode, tree type)
5541 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5544 /* This is the default definition. */
5545 return (! BYTES_BIG_ENDIAN
5548 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5549 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
5550 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5551 ? downward : upward));
5554 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5555 For v9, function return values are subject to the same rules as arguments,
5556 except that up to 32-bytes may be returned in registers. */
5559 function_value (tree type, enum machine_mode mode, int incoming_p)
5562 int regbase = (incoming_p
5563 ? SPARC_OUTGOING_INT_ARG_FIRST
5564 : SPARC_INCOMING_INT_ARG_FIRST);
5566 if (TARGET_ARCH64 && type)
5568 if (TREE_CODE (type) == RECORD_TYPE)
5570 /* Structures up to 32 bytes in size are passed in registers,
5571 promoted to fp registers where possible. */
5573 if (int_size_in_bytes (type) > 32)
5574 abort (); /* shouldn't get here */
5576 return function_arg_record_value (type, mode, 0, 1, regbase);
5578 else if (AGGREGATE_TYPE_P (type))
5580 /* All other aggregate types are passed in an integer register
5581 in a mode corresponding to the size of the type. */
5582 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5587 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5592 && GET_MODE_CLASS (mode) == MODE_INT
5593 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5594 && type && ! AGGREGATE_TYPE_P (type))
5598 regno = BASE_RETURN_VALUE_REG (mode);
5600 regno = BASE_OUTGOING_VALUE_REG (mode);
5602 return gen_rtx_REG (mode, regno);
5605 /* Do what is necessary for `va_start'. We look at the current function
5606 to determine if stdarg or varargs is used and return the address of
5607 the first unnamed parameter. */
5610 sparc_builtin_saveregs (void)
5612 int first_reg = current_function_args_info.words;
5616 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5617 emit_move_insn (gen_rtx_MEM (word_mode,
5618 gen_rtx_PLUS (Pmode,
5620 GEN_INT (FIRST_PARM_OFFSET (0)
5623 gen_rtx_REG (word_mode,
5624 BASE_INCOMING_ARG_REG (word_mode) + regno));
5626 address = gen_rtx_PLUS (Pmode,
5628 GEN_INT (FIRST_PARM_OFFSET (0)
5629 + UNITS_PER_WORD * first_reg));
5634 /* Implement `va_start' for varargs and stdarg. */
5637 sparc_va_start (tree valist, rtx nextarg)
5639 nextarg = expand_builtin_saveregs ();
5640 std_expand_builtin_va_start (valist, nextarg);
5643 /* Implement `va_arg'. */
5646 sparc_va_arg (tree valist, tree type)
5648 HOST_WIDE_INT size, rsize, align;
5653 /* Round up sizeof(type) to a word. */
5654 size = int_size_in_bytes (type);
5655 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5660 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5661 align = 2 * UNITS_PER_WORD;
5663 if (AGGREGATE_TYPE_P (type))
5665 if ((unsigned HOST_WIDE_INT) size > 16)
5668 size = rsize = UNITS_PER_WORD;
5671 /* SPARC v9 ABI states that structures up to 8 bytes in size are
5672 given one 8 byte slot. */
5674 size = rsize = UNITS_PER_WORD;
5681 if (AGGREGATE_TYPE_P (type)
5682 || TYPE_MODE (type) == TFmode
5683 || TYPE_MODE (type) == TCmode)
5686 size = rsize = UNITS_PER_WORD;
5693 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5694 build_int_2 (align - 1, 0)));
5695 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5696 build_int_2 (-align, -1)));
5699 addr = incr = save_expr (incr);
5700 if (BYTES_BIG_ENDIAN && size < rsize)
5702 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5703 build_int_2 (rsize - size, 0)));
5705 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5706 build_int_2 (rsize, 0)));
5708 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5709 TREE_SIDE_EFFECTS (incr) = 1;
5710 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5712 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5714 /* If the address isn't aligned properly for the type,
5715 we may need to copy to a temporary.
5716 FIXME: This is inefficient. Usually we can do this
5719 && TYPE_ALIGN (type) > BITS_PER_WORD
5722 /* FIXME: We really need to specify that the temporary is live
5723 for the whole function because expand_builtin_va_arg wants
5724 the alias set to be get_varargs_alias_set (), but in this
5725 case the alias set is that for TYPE and if the memory gets
5726 reused it will be reused with alias set TYPE. */
5727 rtx tmp = assign_temp (type, 0, 1, 0);
5730 addr_rtx = force_reg (Pmode, addr_rtx);
5731 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5732 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5733 set_mem_align (addr_rtx, BITS_PER_WORD);
5734 tmp = shallow_copy_rtx (tmp);
5735 PUT_MODE (tmp, BLKmode);
5736 set_mem_alias_set (tmp, 0);
5738 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
5740 if (dest_addr != NULL_RTX)
5741 addr_rtx = dest_addr;
5743 addr_rtx = XCEXP (tmp, 0, MEM);
5748 addr_rtx = force_reg (Pmode, addr_rtx);
5749 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5750 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5756 /* Return the string to output a conditional branch to LABEL, which is
5757 the operand number of the label. OP is the conditional expression.
5758 XEXP (OP, 0) is assumed to be a condition code register (integer or
5759 floating point) and its mode specifies what kind of comparison we made.
5761 REVERSED is nonzero if we should reverse the sense of the comparison.
5763 ANNUL is nonzero if we should generate an annulling branch.
5765 NOOP is nonzero if we have to follow this branch by a noop.
5767 INSN, if set, is the insn. */
5770 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
5773 static char string[50];
5774 enum rtx_code code = GET_CODE (op);
5775 rtx cc_reg = XEXP (op, 0);
5776 enum machine_mode mode = GET_MODE (cc_reg);
5777 const char *labelno, *branch;
5778 int spaces = 8, far;
5781 /* v9 branches are limited to +-1MB. If it is too far away,
5794 fbne,a,pn %fcc2, .LC29
5802 far = get_attr_length (insn) >= 3;
5805 /* Reversal of FP compares takes care -- an ordered compare
5806 becomes an unordered compare and vice versa. */
5807 if (mode == CCFPmode || mode == CCFPEmode)
5808 code = reverse_condition_maybe_unordered (code);
5810 code = reverse_condition (code);
5813 /* Start by writing the branch condition. */
5814 if (mode == CCFPmode || mode == CCFPEmode)
5865 /* ??? !v9: FP branches cannot be preceded by another floating point
5866 insn. Because there is currently no concept of pre-delay slots,
5867 we can fix this only by always emitting a nop before a floating
5872 strcpy (string, "nop\n\t");
5873 strcat (string, branch);
5886 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5898 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5919 strcpy (string, branch);
5921 spaces -= strlen (branch);
5922 p = strchr (string, '\0');
5924 /* Now add the annulling, the label, and a possible noop. */
5939 if (! far && insn && INSN_ADDRESSES_SET_P ())
5941 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5942 - INSN_ADDRESSES (INSN_UID (insn)));
5943 /* Leave some instructions for "slop". */
5944 if (delta < -260000 || delta >= 260000)
5948 if (mode == CCFPmode || mode == CCFPEmode)
5950 static char v9_fcc_labelno[] = "%%fccX, ";
5951 /* Set the char indicating the number of the fcc reg to use. */
5952 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5953 labelno = v9_fcc_labelno;
5956 if (REGNO (cc_reg) == SPARC_FCC_REG)
5962 else if (mode == CCXmode || mode == CCX_NOOVmode)
5964 labelno = "%%xcc, ";
5970 labelno = "%%icc, ";
5975 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5978 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5988 strcpy (p, labelno);
5989 p = strchr (p, '\0');
5992 strcpy (p, ".+12\n\tnop\n\tb\t");
5999 /* Set the char indicating the number of the operand containing the
6004 strcpy (p, "\n\tnop");
6009 /* Emit a library call comparison between floating point X and Y.
6010 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6011 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6012 values as arguments instead of the TFmode registers themselves,
6013 that's why we cannot call emit_float_lib_cmp. */
6015 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6018 rtx slot0, slot1, result, tem, tem2;
6019 enum machine_mode mode;
6024 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6028 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6032 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6036 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6040 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6044 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6055 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6065 if (GET_CODE (x) != MEM)
6067 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6068 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6073 if (GET_CODE (y) != MEM)
6075 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6076 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6081 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6083 XEXP (slot0, 0), Pmode,
6084 XEXP (slot1, 0), Pmode);
6090 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6092 x, TFmode, y, TFmode);
6098 /* Immediately move the result of the libcall into a pseudo
6099 register so reload doesn't clobber the value if it needs
6100 the return register for a spill reg. */
6101 result = gen_reg_rtx (mode);
6102 emit_move_insn (result, hard_libcall_value (mode));
6107 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6111 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6116 emit_cmp_insn (result, const1_rtx,
6117 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6120 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6123 tem = gen_reg_rtx (mode);
6125 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6127 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6128 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6132 tem = gen_reg_rtx (mode);
6134 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6136 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6137 tem2 = gen_reg_rtx (mode);
6139 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6141 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6142 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6148 /* Generate an unsigned DImode to FP conversion. This is the same code
6149 optabs would emit if we didn't have TFmode patterns. */
6152 sparc_emit_floatunsdi (rtx *operands)
6154 rtx neglab, donelab, i0, i1, f0, in, out;
6155 enum machine_mode mode;
6158 in = force_reg (DImode, operands[1]);
6159 mode = GET_MODE (out);
6160 neglab = gen_label_rtx ();
6161 donelab = gen_label_rtx ();
6162 i0 = gen_reg_rtx (DImode);
6163 i1 = gen_reg_rtx (DImode);
6164 f0 = gen_reg_rtx (mode);
6166 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6168 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6169 emit_jump_insn (gen_jump (donelab));
6172 emit_label (neglab);
6174 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6175 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6176 emit_insn (gen_iordi3 (i0, i0, i1));
6177 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6178 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6180 emit_label (donelab);
6183 /* Return the string to output a conditional branch to LABEL, testing
6184 register REG. LABEL is the operand number of the label; REG is the
6185 operand number of the reg. OP is the conditional expression. The mode
6186 of REG says what kind of comparison we made.
6188 REVERSED is nonzero if we should reverse the sense of the comparison.
6190 ANNUL is nonzero if we should generate an annulling branch.
6192 NOOP is nonzero if we have to follow this branch by a noop. */
6195 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6196 int annul, int noop, rtx insn)
6198 static char string[50];
6199 enum rtx_code code = GET_CODE (op);
6200 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6205 /* branch on register are limited to +-128KB. If it is too far away,
6218 brgez,a,pn %o1, .LC29
6224 ba,pt %xcc, .LC29 */
6226 far = get_attr_length (insn) >= 3;
6228 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6230 code = reverse_condition (code);
6232 /* Only 64 bit versions of these instructions exist. */
6236 /* Start by writing the branch condition. */
6241 strcpy (string, "brnz");
6245 strcpy (string, "brz");
6249 strcpy (string, "brgez");
6253 strcpy (string, "brlz");
6257 strcpy (string, "brlez");
6261 strcpy (string, "brgz");
6268 p = strchr (string, '\0');
6270 /* Now add the annulling, reg, label, and nop. */
6277 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6280 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6285 *p = p < string + 8 ? '\t' : ' ';
6293 int veryfar = 1, delta;
6295 if (INSN_ADDRESSES_SET_P ())
6297 delta = (INSN_ADDRESSES (INSN_UID (dest))
6298 - INSN_ADDRESSES (INSN_UID (insn)));
6299 /* Leave some instructions for "slop". */
6300 if (delta >= -260000 && delta < 260000)
6304 strcpy (p, ".+12\n\tnop\n\t");
6315 strcpy (p, "ba,pt\t%%xcc, ");
6325 strcpy (p, "\n\tnop");
6330 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6331 Such instructions cannot be used in the delay slot of return insn on v9.
6332 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6336 epilogue_renumber (register rtx *where, int test)
6338 register const char *fmt;
6340 register enum rtx_code code;
6345 code = GET_CODE (*where);
6350 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6352 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6353 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6361 /* Do not replace the frame pointer with the stack pointer because
6362 it can cause the delayed instruction to load below the stack.
6363 This occurs when instructions like:
6365 (set (reg/i:SI 24 %i0)
6366 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6367 (const_int -20 [0xffffffec])) 0))
6369 are in the return delayed slot. */
6371 if (GET_CODE (XEXP (*where, 0)) == REG
6372 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6373 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6374 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6379 if (SPARC_STACK_BIAS
6380 && GET_CODE (XEXP (*where, 0)) == REG
6381 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6389 fmt = GET_RTX_FORMAT (code);
6391 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6396 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6397 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6400 else if (fmt[i] == 'e'
6401 && epilogue_renumber (&(XEXP (*where, i)), test))
6407 /* Leaf functions and non-leaf functions have different needs. */
6410 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6413 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6415 static const int *const reg_alloc_orders[] = {
6416 reg_leaf_alloc_order,
6417 reg_nonleaf_alloc_order};
6420 order_regs_for_local_alloc (void)
6422 static int last_order_nonleaf = 1;
6424 if (regs_ever_live[15] != last_order_nonleaf)
6426 last_order_nonleaf = !last_order_nonleaf;
6427 memcpy ((char *) reg_alloc_order,
6428 (const char *) reg_alloc_orders[last_order_nonleaf],
6429 FIRST_PSEUDO_REGISTER * sizeof (int));
6433 /* Return 1 if REG and MEM are legitimate enough to allow the various
6434 mem<-->reg splits to be run. */
6437 sparc_splitdi_legitimate (rtx reg, rtx mem)
6439 /* Punt if we are here by mistake. */
6440 if (! reload_completed)
6443 /* We must have an offsettable memory reference. */
6444 if (! offsettable_memref_p (mem))
6447 /* If we have legitimate args for ldd/std, we do not want
6448 the split to happen. */
6449 if ((REGNO (reg) % 2) == 0
6450 && mem_min_alignment (mem, 8))
6457 /* Return 1 if x and y are some kind of REG and they refer to
6458 different hard registers. This test is guaranteed to be
6459 run after reload. */
6462 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6464 if (GET_CODE (x) != REG)
6466 if (GET_CODE (y) != REG)
6468 if (REGNO (x) == REGNO (y))
6473 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6474 This makes them candidates for using ldd and std insns.
6476 Note reg1 and reg2 *must* be hard registers. */
6479 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6481 /* We might have been passed a SUBREG. */
6482 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6485 if (REGNO (reg1) % 2 != 0)
6488 /* Integer ldd is deprecated in SPARC V9 */
6489 if (TARGET_V9 && REGNO (reg1) < 32)
6492 return (REGNO (reg1) == REGNO (reg2) - 1);
6495 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6498 This can only happen when addr1 and addr2, the addresses in mem1
6499 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6500 addr1 must also be aligned on a 64-bit boundary.
6502 Also iff dependent_reg_rtx is not null it should not be used to
6503 compute the address for mem1, i.e. we cannot optimize a sequence
6515 But, note that the transformation from:
6520 is perfectly fine. Thus, the peephole2 patterns always pass us
6521 the destination register of the first load, never the second one.
6523 For stores we don't have a similar problem, so dependent_reg_rtx is
6527 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6533 /* The mems cannot be volatile. */
6534 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6537 /* MEM1 should be aligned on a 64-bit boundary. */
6538 if (MEM_ALIGN (mem1) < 64)
6541 addr1 = XEXP (mem1, 0);
6542 addr2 = XEXP (mem2, 0);
6544 /* Extract a register number and offset (if used) from the first addr. */
6545 if (GET_CODE (addr1) == PLUS)
6547 /* If not a REG, return zero. */
6548 if (GET_CODE (XEXP (addr1, 0)) != REG)
6552 reg1 = REGNO (XEXP (addr1, 0));
6553 /* The offset must be constant! */
6554 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6556 offset1 = INTVAL (XEXP (addr1, 1));
6559 else if (GET_CODE (addr1) != REG)
6563 reg1 = REGNO (addr1);
6564 /* This was a simple (mem (reg)) expression. Offset is 0. */
6568 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6569 if (GET_CODE (addr2) != PLUS)
6572 if (GET_CODE (XEXP (addr2, 0)) != REG
6573 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6576 if (reg1 != REGNO (XEXP (addr2, 0)))
6579 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6582 /* The first offset must be evenly divisible by 8 to ensure the
6583 address is 64 bit aligned. */
6584 if (offset1 % 8 != 0)
6587 /* The offset for the second addr must be 4 more than the first addr. */
6588 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6591 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6596 /* Return 1 if reg is a pseudo, or is the first register in
6597 a hard register pair. This makes it a candidate for use in
6598 ldd and std insns. */
6601 register_ok_for_ldd (rtx reg)
6603 /* We might have been passed a SUBREG. */
6604 if (GET_CODE (reg) != REG)
6607 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6608 return (REGNO (reg) % 2 == 0);
6613 /* Print operand X (an rtx) in assembler syntax to file FILE.
6614 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6615 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6618 print_operand (FILE *file, rtx x, int code)
6623 /* Output a 'nop' if there's nothing for the delay slot. */
6624 if (dbr_sequence_length () == 0)
6625 fputs ("\n\t nop", file);
6628 /* Output an annul flag if there's nothing for the delay slot and we
6629 are optimizing. This is always used with '(' below. */
6630 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6631 this is a dbx bug. So, we only do this when optimizing. */
6632 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6633 Always emit a nop in case the next instruction is a branch. */
6634 if (dbr_sequence_length () == 0
6635 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6639 /* Output a 'nop' if there's nothing for the delay slot and we are
6640 not optimizing. This is always used with '*' above. */
6641 if (dbr_sequence_length () == 0
6642 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6643 fputs ("\n\t nop", file);
6646 /* Output the Embedded Medium/Anywhere code model base register. */
6647 fputs (EMBMEDANY_BASE_REG, file);
6650 /* Print out what we are using as the frame pointer. This might
6651 be %fp, or might be %sp+offset. */
6652 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6653 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
6656 /* Print some local dynamic TLS name. */
6657 assemble_name (file, get_some_local_dynamic_name ());
6660 /* Adjust the operand to take into account a RESTORE operation. */
6661 if (GET_CODE (x) == CONST_INT)
6663 else if (GET_CODE (x) != REG)
6664 output_operand_lossage ("invalid %%Y operand");
6665 else if (REGNO (x) < 8)
6666 fputs (reg_names[REGNO (x)], file);
6667 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6668 fputs (reg_names[REGNO (x)-16], file);
6670 output_operand_lossage ("invalid %%Y operand");
6673 /* Print out the low order register name of a register pair. */
6674 if (WORDS_BIG_ENDIAN)
6675 fputs (reg_names[REGNO (x)+1], file);
6677 fputs (reg_names[REGNO (x)], file);
6680 /* Print out the high order register name of a register pair. */
6681 if (WORDS_BIG_ENDIAN)
6682 fputs (reg_names[REGNO (x)], file);
6684 fputs (reg_names[REGNO (x)+1], file);
6687 /* Print out the second register name of a register pair or quad.
6688 I.e., R (%o0) => %o1. */
6689 fputs (reg_names[REGNO (x)+1], file);
6692 /* Print out the third register name of a register quad.
6693 I.e., S (%o0) => %o2. */
6694 fputs (reg_names[REGNO (x)+2], file);
6697 /* Print out the fourth register name of a register quad.
6698 I.e., T (%o0) => %o3. */
6699 fputs (reg_names[REGNO (x)+3], file);
6702 /* Print a condition code register. */
6703 if (REGNO (x) == SPARC_ICC_REG)
6705 /* We don't handle CC[X]_NOOVmode because they're not supposed
6707 if (GET_MODE (x) == CCmode)
6708 fputs ("%icc", file);
6709 else if (GET_MODE (x) == CCXmode)
6710 fputs ("%xcc", file);
6715 /* %fccN register */
6716 fputs (reg_names[REGNO (x)], file);
6719 /* Print the operand's address only. */
6720 output_address (XEXP (x, 0));
6723 /* In this case we need a register. Use %g0 if the
6724 operand is const0_rtx. */
6726 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
6728 fputs ("%g0", file);
6735 switch (GET_CODE (x))
6737 case IOR: fputs ("or", file); break;
6738 case AND: fputs ("and", file); break;
6739 case XOR: fputs ("xor", file); break;
6740 default: output_operand_lossage ("invalid %%A operand");
6745 switch (GET_CODE (x))
6747 case IOR: fputs ("orn", file); break;
6748 case AND: fputs ("andn", file); break;
6749 case XOR: fputs ("xnor", file); break;
6750 default: output_operand_lossage ("invalid %%B operand");
6754 /* These are used by the conditional move instructions. */
6758 enum rtx_code rc = GET_CODE (x);
6762 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6763 if (mode == CCFPmode || mode == CCFPEmode)
6764 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6766 rc = reverse_condition (GET_CODE (x));
6770 case NE: fputs ("ne", file); break;
6771 case EQ: fputs ("e", file); break;
6772 case GE: fputs ("ge", file); break;
6773 case GT: fputs ("g", file); break;
6774 case LE: fputs ("le", file); break;
6775 case LT: fputs ("l", file); break;
6776 case GEU: fputs ("geu", file); break;
6777 case GTU: fputs ("gu", file); break;
6778 case LEU: fputs ("leu", file); break;
6779 case LTU: fputs ("lu", file); break;
6780 case LTGT: fputs ("lg", file); break;
6781 case UNORDERED: fputs ("u", file); break;
6782 case ORDERED: fputs ("o", file); break;
6783 case UNLT: fputs ("ul", file); break;
6784 case UNLE: fputs ("ule", file); break;
6785 case UNGT: fputs ("ug", file); break;
6786 case UNGE: fputs ("uge", file); break;
6787 case UNEQ: fputs ("ue", file); break;
6788 default: output_operand_lossage (code == 'c'
6789 ? "invalid %%c operand"
6790 : "invalid %%C operand");
6795 /* These are used by the movr instruction pattern. */
6799 enum rtx_code rc = (code == 'd'
6800 ? reverse_condition (GET_CODE (x))
6804 case NE: fputs ("ne", file); break;
6805 case EQ: fputs ("e", file); break;
6806 case GE: fputs ("gez", file); break;
6807 case LT: fputs ("lz", file); break;
6808 case LE: fputs ("lez", file); break;
6809 case GT: fputs ("gz", file); break;
6810 default: output_operand_lossage (code == 'd'
6811 ? "invalid %%d operand"
6812 : "invalid %%D operand");
6819 /* Print a sign-extended character. */
6820 int i = trunc_int_for_mode (INTVAL (x), QImode);
6821 fprintf (file, "%d", i);
6826 /* Operand must be a MEM; write its address. */
6827 if (GET_CODE (x) != MEM)
6828 output_operand_lossage ("invalid %%f operand");
6829 output_address (XEXP (x, 0));
6834 /* Print a sign-extended 32-bit value. */
6836 if (GET_CODE(x) == CONST_INT)
6838 else if (GET_CODE(x) == CONST_DOUBLE)
6839 i = CONST_DOUBLE_LOW (x);
6842 output_operand_lossage ("invalid %%s operand");
6845 i = trunc_int_for_mode (i, SImode);
6846 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
6851 /* Do nothing special. */
6855 /* Undocumented flag. */
6856 output_operand_lossage ("invalid operand output code");
6859 if (GET_CODE (x) == REG)
6860 fputs (reg_names[REGNO (x)], file);
6861 else if (GET_CODE (x) == MEM)
6864 /* Poor Sun assembler doesn't understand absolute addressing. */
6865 if (CONSTANT_P (XEXP (x, 0)))
6866 fputs ("%g0+", file);
6867 output_address (XEXP (x, 0));
6870 else if (GET_CODE (x) == HIGH)
6872 fputs ("%hi(", file);
6873 output_addr_const (file, XEXP (x, 0));
6876 else if (GET_CODE (x) == LO_SUM)
6878 print_operand (file, XEXP (x, 0), 0);
6879 if (TARGET_CM_MEDMID)
6880 fputs ("+%l44(", file);
6882 fputs ("+%lo(", file);
6883 output_addr_const (file, XEXP (x, 1));
6886 else if (GET_CODE (x) == CONST_DOUBLE
6887 && (GET_MODE (x) == VOIDmode
6888 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
6890 if (CONST_DOUBLE_HIGH (x) == 0)
6891 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
6892 else if (CONST_DOUBLE_HIGH (x) == -1
6893 && CONST_DOUBLE_LOW (x) < 0)
6894 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
6896 output_operand_lossage ("long long constant not a valid immediate operand");
6898 else if (GET_CODE (x) == CONST_DOUBLE)
6899 output_operand_lossage ("floating point constant not a valid immediate operand");
6900 else { output_addr_const (file, x); }
6903 /* Target hook for assembling integer objects. The sparc version has
6904 special handling for aligned DI-mode objects. */
6907 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
6909 /* ??? We only output .xword's for symbols and only then in environments
6910 where the assembler can handle them. */
6911 if (aligned_p && size == 8
6912 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
6916 assemble_integer_with_op ("\t.xword\t", x);
6921 assemble_aligned_integer (4, const0_rtx);
6922 assemble_aligned_integer (4, x);
6926 return default_assemble_integer (x, size, aligned_p);
6929 /* Return the value of a code used in the .proc pseudo-op that says
6930 what kind of result this function returns. For non-C types, we pick
6931 the closest C type. */
6933 #ifndef SHORT_TYPE_SIZE
6934 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6937 #ifndef INT_TYPE_SIZE
6938 #define INT_TYPE_SIZE BITS_PER_WORD
6941 #ifndef LONG_TYPE_SIZE
6942 #define LONG_TYPE_SIZE BITS_PER_WORD
6945 #ifndef LONG_LONG_TYPE_SIZE
6946 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6949 #ifndef FLOAT_TYPE_SIZE
6950 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6953 #ifndef DOUBLE_TYPE_SIZE
6954 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6957 #ifndef LONG_DOUBLE_TYPE_SIZE
6958 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6962 sparc_type_code (register tree type)
6964 register unsigned long qualifiers = 0;
6965 register unsigned shift;
6967 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6968 setting more, since some assemblers will give an error for this. Also,
6969 we must be careful to avoid shifts of 32 bits or more to avoid getting
6970 unpredictable results. */
6972 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
6974 switch (TREE_CODE (type))
6980 qualifiers |= (3 << shift);
6985 qualifiers |= (2 << shift);
6989 case REFERENCE_TYPE:
6991 qualifiers |= (1 << shift);
6995 return (qualifiers | 8);
6998 case QUAL_UNION_TYPE:
6999 return (qualifiers | 9);
7002 return (qualifiers | 10);
7005 return (qualifiers | 16);
7008 /* If this is a range type, consider it to be the underlying
7010 if (TREE_TYPE (type) != 0)
7013 /* Carefully distinguish all the standard types of C,
7014 without messing up if the language is not C. We do this by
7015 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
7016 look at both the names and the above fields, but that's redundant.
7017 Any type whose size is between two C types will be considered
7018 to be the wider of the two types. Also, we do not have a
7019 special code to use for "long long", so anything wider than
7020 long is treated the same. Note that we can't distinguish
7021 between "int" and "long" in this code if they are the same
7022 size, but that's fine, since neither can the assembler. */
7024 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7025 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
7027 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7028 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
7030 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7031 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
7034 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
7037 /* If this is a range type, consider it to be the underlying
7039 if (TREE_TYPE (type) != 0)
7042 /* Carefully distinguish all the standard types of C,
7043 without messing up if the language is not C. */
7045 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7046 return (qualifiers | 6);
7049 return (qualifiers | 7);
7051 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7052 /* ??? We need to distinguish between double and float complex types,
7053 but I don't know how yet because I can't reach this code from
7054 existing front-ends. */
7055 return (qualifiers | 7); /* Who knows? */
7057 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7058 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7059 case FILE_TYPE: /* GNU Pascal FILE type. */
7060 case SET_TYPE: /* GNU Pascal SET type. */
7061 case LANG_TYPE: /* ? */
7065 abort (); /* Not a type! */
7072 /* Nested function support. */
7074 /* Emit RTL insns to initialize the variable parts of a trampoline.
7075 FNADDR is an RTX for the address of the function's pure code.
7076 CXT is an RTX for the static chain value for the function.
7078 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7079 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7080 (to store insns). This is a bit excessive. Perhaps a different
7081 mechanism would be better here.
7083 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7086 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7088 /* SPARC 32 bit trampoline:
7091 sethi %hi(static), %g2
7093 or %g2, %lo(static), %g2
7095 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7096 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7098 #ifdef TRANSFER_FROM_TRAMPOLINE
7099 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7100 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7104 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7105 expand_binop (SImode, ior_optab,
7106 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7107 size_int (10), 0, 1),
7108 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7109 NULL_RTX, 1, OPTAB_DIRECT));
7112 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7113 expand_binop (SImode, ior_optab,
7114 expand_shift (RSHIFT_EXPR, SImode, cxt,
7115 size_int (10), 0, 1),
7116 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7117 NULL_RTX, 1, OPTAB_DIRECT));
7120 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7121 expand_binop (SImode, ior_optab,
7122 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7123 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7124 NULL_RTX, 1, OPTAB_DIRECT));
7127 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7128 expand_binop (SImode, ior_optab,
7129 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7130 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7131 NULL_RTX, 1, OPTAB_DIRECT));
7133 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7134 aligned on a 16 byte boundary so one flush clears it all. */
7135 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7136 if (sparc_cpu != PROCESSOR_ULTRASPARC
7137 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7138 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7139 plus_constant (tramp, 8)))));
7142 /* The 64 bit version is simpler because it makes more sense to load the
7143 values as "immediate" data out of the trampoline. It's also easier since
7144 we can read the PC without clobbering a register. */
7147 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7149 #ifdef TRANSFER_FROM_TRAMPOLINE
7150 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7151 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7162 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7163 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7164 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7165 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7166 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7167 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7168 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7169 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7170 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7171 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7172 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7174 if (sparc_cpu != PROCESSOR_ULTRASPARC
7175 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7176 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7179 /* Subroutines to support a flat (single) register window calling
7182 /* Single-register window sparc stack frames look like:
7184 Before call After call
7185 +-----------------------+ +-----------------------+
7187 mem | caller's temps. | | caller's temps. |
7189 +-----------------------+ +-----------------------+
7191 | arguments on stack. | | arguments on stack. |
7193 +-----------------------+FP+92->+-----------------------+
7194 | 6 words to save | | 6 words to save |
7195 | arguments passed | | arguments passed |
7196 | in registers, even | | in registers, even |
7197 | if not passed. | | if not passed. |
7198 SP+68->+-----------------------+FP+68->+-----------------------+
7199 | 1 word struct addr | | 1 word struct addr |
7200 +-----------------------+FP+64->+-----------------------+
7202 | 16 word reg save area | | 16 word reg save area |
7204 SP->+-----------------------+ FP->+-----------------------+
7206 | fp/alu reg moves |
7207 FP-16->+-----------------------+
7211 +-----------------------+
7213 | fp register save |
7215 +-----------------------+
7217 | gp register save |
7219 +-----------------------+
7221 | alloca allocations |
7223 +-----------------------+
7225 | arguments on stack |
7227 SP+92->+-----------------------+
7229 | arguments passed |
7230 | in registers, even |
7231 low | if not passed. |
7232 memory SP+68->+-----------------------+
7233 | 1 word struct addr |
7234 SP+64->+-----------------------+
7236 I 16 word reg save area |
7238 SP->+-----------------------+ */
7240 /* Structure to be filled in by sparc_flat_compute_frame_size with register
7241 save masks, and offsets for the current function. */
7243 struct sparc_frame_info
7245 unsigned long total_size; /* # bytes that the entire frame takes up. */
7246 unsigned long var_size; /* # bytes that variables take up. */
7247 unsigned long args_size; /* # bytes that outgoing arguments take up. */
7248 unsigned long extra_size; /* # bytes of extra gunk. */
7249 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
7250 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
7251 unsigned long gmask; /* Mask of saved gp registers. */
7252 unsigned long fmask; /* Mask of saved fp registers. */
7253 unsigned long reg_offset; /* Offset from new sp to store regs. */
7254 int initialized; /* Nonzero if frame size already calculated. */
7257 /* Current frame information calculated by sparc_flat_compute_frame_size. */
7258 struct sparc_frame_info current_frame_info;
7260 /* Zero structure to initialize current_frame_info. */
7261 struct sparc_frame_info zero_frame_info;
7263 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
7265 #define RETURN_ADDR_REGNUM 15
7266 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
7267 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
7269 #define MUST_SAVE_REGISTER(regno) \
7270 ((regs_ever_live[regno] && !call_used_regs[regno]) \
7271 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
7272 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
7274 /* Return the bytes needed to compute the frame pointer from the current
7278 sparc_flat_compute_frame_size (int size)
7279 /* # of var. bytes allocated. */
7282 unsigned long total_size; /* # bytes that the entire frame takes up. */
7283 unsigned long var_size; /* # bytes that variables take up. */
7284 unsigned long args_size; /* # bytes that outgoing arguments take up. */
7285 unsigned long extra_size; /* # extra bytes. */
7286 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
7287 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
7288 unsigned long gmask; /* Mask of saved gp registers. */
7289 unsigned long fmask; /* Mask of saved fp registers. */
7290 unsigned long reg_offset; /* Offset to register save area. */
7291 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
7293 /* This is the size of the 16 word reg save area, 1 word struct addr
7294 area, and 4 word fp/alu register copy area. */
7295 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
7305 if (!leaf_function_p ())
7307 /* Also include the size needed for the 6 parameter registers. */
7308 args_size = current_function_outgoing_args_size + 24;
7310 total_size = var_size + args_size;
7312 /* Calculate space needed for gp registers. */
7313 for (regno = 1; regno <= 31; regno++)
7315 if (MUST_SAVE_REGISTER (regno))
7317 /* If we need to save two regs in a row, ensure there's room to bump
7318 up the address to align it to a doubleword boundary. */
7319 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
7321 if (gp_reg_size % 8 != 0)
7323 gp_reg_size += 2 * UNITS_PER_WORD;
7324 gmask |= 3 << regno;
7330 gp_reg_size += UNITS_PER_WORD;
7331 gmask |= 1 << regno;
7336 /* Calculate space needed for fp registers. */
7337 for (regno = 32; regno <= 63; regno++)
7339 if (regs_ever_live[regno] && !call_used_regs[regno])
7341 fp_reg_size += UNITS_PER_WORD;
7342 fmask |= 1 << (regno - 32);
7349 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
7350 /* Ensure save area is 8 byte aligned if we need it. */
7352 if (need_aligned_p && n != 0)
7354 total_size += 8 - n;
7355 reg_offset += 8 - n;
7357 total_size += gp_reg_size + fp_reg_size;
7360 /* If we must allocate a stack frame at all, we must also allocate
7361 room for register window spillage, so as to be binary compatible
7362 with libraries and operating systems that do not use -mflat. */
7364 total_size += extra_size;
7368 total_size = SPARC_STACK_ALIGN (total_size);
7370 /* Save other computed information. */
7371 current_frame_info.total_size = total_size;
7372 current_frame_info.var_size = var_size;
7373 current_frame_info.args_size = args_size;
7374 current_frame_info.extra_size = extra_size;
7375 current_frame_info.gp_reg_size = gp_reg_size;
7376 current_frame_info.fp_reg_size = fp_reg_size;
7377 current_frame_info.gmask = gmask;
7378 current_frame_info.fmask = fmask;
7379 current_frame_info.reg_offset = reg_offset;
7380 current_frame_info.initialized = reload_completed;
7382 /* Ok, we're done. */
7386 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7389 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7390 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7391 [BASE_REG+OFFSET] will always be a valid address.
7393 WORD_OP is either "st" for save, "ld" for restore.
7394 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7397 sparc_flat_save_restore (FILE *file, const char *base_reg,
7398 unsigned int offset, long unsigned int gmask,
7399 long unsigned int fmask, const char *word_op,
7400 const char *doubleword_op,
7401 long unsigned int base_offset)
7405 if (gmask == 0 && fmask == 0)
7408 /* Save registers starting from high to low. We've already saved the
7409 previous frame pointer and previous return address for the debugger's
7410 sake. The debugger allows us to not need a nop in the epilog if at least
7411 one register is reloaded in addition to return address. */
7415 for (regno = 1; regno <= 31; regno++)
7417 if ((gmask & (1L << regno)) != 0)
7419 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7421 /* We can save two registers in a row. If we're not at a
7422 double word boundary, move to one.
7423 sparc_flat_compute_frame_size ensures there's room to do
7425 if (offset % 8 != 0)
7426 offset += UNITS_PER_WORD;
7428 if (word_op[0] == 's')
7430 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7431 doubleword_op, reg_names[regno],
7433 if (dwarf2out_do_frame ())
7435 char *l = dwarf2out_cfi_label ();
7436 dwarf2out_reg_save (l, regno, offset + base_offset);
7438 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7442 fprintf (file, "\t%s\t[%s+%d], %s\n",
7443 doubleword_op, base_reg, offset,
7446 offset += 2 * UNITS_PER_WORD;
7451 if (word_op[0] == 's')
7453 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7454 word_op, reg_names[regno],
7456 if (dwarf2out_do_frame ())
7457 dwarf2out_reg_save ("", regno, offset + base_offset);
7460 fprintf (file, "\t%s\t[%s+%d], %s\n",
7461 word_op, base_reg, offset, reg_names[regno]);
7463 offset += UNITS_PER_WORD;
7471 for (regno = 32; regno <= 63; regno++)
7473 if ((fmask & (1L << (regno - 32))) != 0)
7475 if (word_op[0] == 's')
7477 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7478 word_op, reg_names[regno],
7480 if (dwarf2out_do_frame ())
7481 dwarf2out_reg_save ("", regno, offset + base_offset);
7484 fprintf (file, "\t%s\t[%s+%d], %s\n",
7485 word_op, base_reg, offset, reg_names[regno]);
7487 offset += UNITS_PER_WORD;
7493 /* Set up the stack and frame (if desired) for the function. */
7496 sparc_flat_function_prologue (FILE *file, HOST_WIDE_INT size)
7498 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7499 unsigned long gmask = current_frame_info.gmask;
7501 sparc_output_scratch_registers (file);
7503 /* This is only for the human reader. */
7504 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7505 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7507 current_frame_info.var_size,
7508 current_frame_info.gp_reg_size / 4,
7509 current_frame_info.fp_reg_size / 4,
7510 current_function_outgoing_args_size,
7511 current_frame_info.extra_size);
7513 size = SPARC_STACK_ALIGN (size);
7514 size = (! current_frame_info.initialized
7515 ? sparc_flat_compute_frame_size (size)
7516 : current_frame_info.total_size);
7518 /* These cases shouldn't happen. Catch them now. */
7519 if (size == 0 && (gmask || current_frame_info.fmask))
7522 /* Allocate our stack frame by decrementing %sp.
7523 At present, the only algorithm gdb can use to determine if this is a
7524 flat frame is if we always set %i7 if we set %sp. This can be optimized
7525 in the future by putting in some sort of debugging information that says
7526 this is a `flat' function. However, there is still the case of debugging
7527 code without such debugging information (including cases where most fns
7528 have such info, but there is one that doesn't). So, always do this now
7529 so we don't get a lot of code out there that gdb can't handle.
7530 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7531 distinguish us from a non-flat function but there won't (and shouldn't)
7532 be any differences anyway. The return pc is saved (if necessary) right
7533 after %i7 so gdb won't have to look too far to find it. */
7536 unsigned int reg_offset = current_frame_info.reg_offset;
7537 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7538 static const char *const t1_str = "%g1";
7540 /* Things get a little tricky if local variables take up more than ~4096
7541 bytes and outgoing arguments take up more than ~4096 bytes. When that
7542 happens, the register save area can't be accessed from either end of
7543 the frame. Handle this by decrementing %sp to the start of the gp
7544 register save area, save the regs, update %i7, and then set %sp to its
7545 final value. Given that we only have one scratch register to play
7546 with it is the cheapest solution, and it helps gdb out as it won't
7547 slow down recognition of flat functions.
7548 Don't change the order of insns emitted here without checking with
7549 the gdb folk first. */
7551 /* Is the entire register save area offsettable from %sp? */
7552 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7556 fprintf (file, "\tadd\t%s, %d, %s\n",
7557 sp_str, (int) -size, sp_str);
7558 if (gmask & HARD_FRAME_POINTER_MASK)
7560 fprintf (file, "\tst\t%s, [%s+%d]\n",
7561 fp_str, sp_str, reg_offset);
7562 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7563 sp_str, (int) -size, fp_str, ASM_COMMENT_START);
7569 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7570 ", %s\n\tsub\t%s, %s, %s\n",
7571 size, t1_str, sp_str, t1_str, sp_str);
7572 if (gmask & HARD_FRAME_POINTER_MASK)
7574 fprintf (file, "\tst\t%s, [%s+%d]\n",
7575 fp_str, sp_str, reg_offset);
7576 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7577 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7581 if (dwarf2out_do_frame ())
7583 char *l = dwarf2out_cfi_label ();
7584 if (gmask & HARD_FRAME_POINTER_MASK)
7586 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7587 reg_offset - 4 - size);
7588 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7591 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7593 if (gmask & RETURN_ADDR_MASK)
7595 fprintf (file, "\tst\t%s, [%s+%d]\n",
7596 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7597 if (dwarf2out_do_frame ())
7598 dwarf2out_return_save ("", reg_offset - size);
7601 sparc_flat_save_restore (file, sp_str, reg_offset,
7602 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7603 current_frame_info.fmask,
7604 "st", "std", -size);
7608 /* Subtract %sp in two steps, but make sure there is always a
7609 64 byte register save area, and %sp is properly aligned. */
7610 /* Amount to decrement %sp by, the first time. */
7611 unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7612 /* Offset to register save area from %sp. */
7613 unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset);
7617 fprintf (file, "\tadd\t%s, %d, %s\n",
7618 sp_str, (int) -size1, sp_str);
7619 if (gmask & HARD_FRAME_POINTER_MASK)
7621 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7622 fp_str, sp_str, (int) offset, sp_str, (int) -size1,
7623 fp_str, ASM_COMMENT_START);
7629 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7630 ", %s\n\tsub\t%s, %s, %s\n",
7631 size1, t1_str, sp_str, t1_str, sp_str);
7632 if (gmask & HARD_FRAME_POINTER_MASK)
7634 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7635 fp_str, sp_str, (int) offset, sp_str, t1_str,
7636 fp_str, ASM_COMMENT_START);
7640 if (dwarf2out_do_frame ())
7642 char *l = dwarf2out_cfi_label ();
7643 if (gmask & HARD_FRAME_POINTER_MASK)
7645 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7646 offset - 4 - size1);
7647 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7650 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7652 if (gmask & RETURN_ADDR_MASK)
7654 fprintf (file, "\tst\t%s, [%s+%d]\n",
7655 reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset);
7656 if (dwarf2out_do_frame ())
7657 /* offset - size1 == reg_offset - size
7658 if reg_offset were updated above like offset. */
7659 dwarf2out_return_save ("", offset - size1);
7662 sparc_flat_save_restore (file, sp_str, offset,
7663 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7664 current_frame_info.fmask,
7665 "st", "std", -size1);
7666 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7667 ", %s\n\tsub\t%s, %s, %s\n",
7668 size - size1, t1_str, sp_str, t1_str, sp_str);
7669 if (dwarf2out_do_frame ())
7670 if (! (gmask & HARD_FRAME_POINTER_MASK))
7671 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
7675 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
7678 /* Do any necessary cleanup after a function to restore stack, frame,
7682 sparc_flat_function_epilogue (FILE *file, HOST_WIDE_INT size)
7684 rtx epilogue_delay = current_function_epilogue_delay_list;
7685 int noepilogue = FALSE;
7687 /* This is only for the human reader. */
7688 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
7690 /* The epilogue does not depend on any registers, but the stack
7691 registers, so we assume that if we have 1 pending nop, it can be
7692 ignored, and 2 it must be filled (2 nops occur for integer
7693 multiply and divide). */
7695 size = SPARC_STACK_ALIGN (size);
7696 size = (!current_frame_info.initialized
7697 ? sparc_flat_compute_frame_size (size)
7698 : current_frame_info.total_size);
7700 if (size == 0 && epilogue_delay == 0)
7702 rtx insn = get_last_insn ();
7704 /* If the last insn was a BARRIER, we don't have to write any code
7705 because a jump (aka return) was put there. */
7706 if (GET_CODE (insn) == NOTE)
7707 insn = prev_nonnote_insn (insn);
7708 if (insn && GET_CODE (insn) == BARRIER)
7714 unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset;
7715 unsigned HOST_WIDE_INT size1;
7716 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7717 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7718 static const char *const t1_str = "%g1";
7720 /* In the reload sequence, we don't need to fill the load delay
7721 slots for most of the loads, also see if we can fill the final
7722 delay slot if not otherwise filled by the reload sequence. */
7725 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC ", %s\n",
7728 if (frame_pointer_needed)
7731 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7732 fp_str, t1_str, sp_str, ASM_COMMENT_START);
7734 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
7735 fp_str, (int) size, sp_str, ASM_COMMENT_START);
7738 /* Is the entire register save area offsettable from %sp? */
7739 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7745 /* Restore %sp in two steps, but make sure there is always a
7746 64 byte register save area, and %sp is properly aligned. */
7747 /* Amount to increment %sp by, the first time. */
7748 size1 = ((reg_offset - 64 - 16) + 15) & -16;
7749 /* Offset to register save area from %sp. */
7750 reg_offset = size1 - reg_offset;
7752 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7753 ", %s\n\tadd\t%s, %s, %s\n",
7754 size1, t1_str, sp_str, t1_str, sp_str);
7757 /* We must restore the frame pointer and return address reg first
7758 because they are treated specially by the prologue output code. */
7759 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
7761 fprintf (file, "\tld\t[%s+%d], %s\n",
7762 sp_str, (int) reg_offset, fp_str);
7765 if (current_frame_info.gmask & RETURN_ADDR_MASK)
7767 fprintf (file, "\tld\t[%s+%d], %s\n",
7768 sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]);
7772 /* Restore any remaining saved registers. */
7773 sparc_flat_save_restore (file, sp_str, reg_offset,
7774 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7775 current_frame_info.fmask,
7778 /* If we had to increment %sp in two steps, record it so the second
7779 restoration in the epilogue finishes up. */
7784 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC ", %s\n",
7788 if (current_function_returns_struct)
7789 fprintf (file, "\tjmp\t%%o7+12\n");
7791 fprintf (file, "\tretl\n");
7793 /* If the only register saved is the return address, we need a
7794 nop, unless we have an instruction to put into it. Otherwise
7795 we don't since reloading multiple registers doesn't reference
7796 the register being loaded. */
7802 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
7805 else if (size > 4095)
7806 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7809 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str);
7812 fprintf (file, "\tnop\n");
7815 /* Reset state info for each function. */
7816 current_frame_info = zero_frame_info;
7818 sparc_output_deferred_case_vectors ();
7821 /* Define the number of delay slots needed for the function epilogue.
7823 On the sparc, we need a slot if either no stack has been allocated,
7824 or the only register saved is the return register. */
7827 sparc_flat_epilogue_delay_slots (void)
7829 if (!current_frame_info.initialized)
7830 (void) sparc_flat_compute_frame_size (get_frame_size ());
7832 if (current_frame_info.total_size == 0)
7838 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7839 Any single length instruction which doesn't reference the stack or frame
7843 sparc_flat_eligible_for_epilogue_delay (rtx trial, int slot ATTRIBUTE_UNUSED)
7845 rtx pat = PATTERN (trial);
7847 if (get_attr_length (trial) != 1)
7850 if (! reg_mentioned_p (stack_pointer_rtx, pat)
7851 && ! reg_mentioned_p (frame_pointer_rtx, pat))
7857 /* Adjust the cost of a scheduling dependency. Return the new cost of
7858 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7861 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7863 enum attr_type insn_type;
7865 if (! recog_memoized (insn))
7868 insn_type = get_attr_type (insn);
7870 if (REG_NOTE_KIND (link) == 0)
7872 /* Data dependency; DEP_INSN writes a register that INSN reads some
7875 /* if a load, then the dependence must be on the memory address;
7876 add an extra "cycle". Note that the cost could be two cycles
7877 if the reg was written late in an instruction group; we ca not tell
7879 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7882 /* Get the delay only if the address of the store is the dependence. */
7883 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7885 rtx pat = PATTERN(insn);
7886 rtx dep_pat = PATTERN (dep_insn);
7888 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7889 return cost; /* This should not happen! */
7891 /* The dependency between the two instructions was on the data that
7892 is being stored. Assume that this implies that the address of the
7893 store is not dependent. */
7894 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7897 return cost + 3; /* An approximation. */
7900 /* A shift instruction cannot receive its data from an instruction
7901 in the same cycle; add a one cycle penalty. */
7902 if (insn_type == TYPE_SHIFT)
7903 return cost + 3; /* Split before cascade into shift. */
7907 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7908 INSN writes some cycles later. */
7910 /* These are only significant for the fpu unit; writing a fp reg before
7911 the fpu has finished with it stalls the processor. */
7913 /* Reusing an integer register causes no problems. */
7914 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7922 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7924 enum attr_type insn_type, dep_type;
7925 rtx pat = PATTERN(insn);
7926 rtx dep_pat = PATTERN (dep_insn);
7928 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7931 insn_type = get_attr_type (insn);
7932 dep_type = get_attr_type (dep_insn);
7934 switch (REG_NOTE_KIND (link))
7937 /* Data dependency; DEP_INSN writes a register that INSN reads some
7944 /* Get the delay iff the address of the store is the dependence. */
7945 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7948 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7955 /* If a load, then the dependence must be on the memory address. If
7956 the addresses aren't equal, then it might be a false dependency */
7957 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7959 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7960 || GET_CODE (SET_DEST (dep_pat)) != MEM
7961 || GET_CODE (SET_SRC (pat)) != MEM
7962 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7963 XEXP (SET_SRC (pat), 0)))
7971 /* Compare to branch latency is 0. There is no benefit from
7972 separating compare and branch. */
7973 if (dep_type == TYPE_COMPARE)
7975 /* Floating point compare to branch latency is less than
7976 compare to conditional move. */
7977 if (dep_type == TYPE_FPCMP)
7986 /* Anti-dependencies only penalize the fpu unit. */
7987 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7999 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8003 case PROCESSOR_SUPERSPARC:
8004 cost = supersparc_adjust_cost (insn, link, dep, cost);
8006 case PROCESSOR_HYPERSPARC:
8007 case PROCESSOR_SPARCLITE86X:
8008 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8017 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8018 int sched_verbose ATTRIBUTE_UNUSED,
8019 int max_ready ATTRIBUTE_UNUSED)
8024 sparc_use_dfa_pipeline_interface (void)
8026 if ((1 << sparc_cpu) &
8027 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
8028 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8029 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
8030 (1 << PROCESSOR_ULTRASPARC3)))
8036 sparc_use_sched_lookahead (void)
8038 if (sparc_cpu == PROCESSOR_ULTRASPARC
8039 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8041 if ((1 << sparc_cpu) &
8042 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8043 (1 << PROCESSOR_SPARCLITE86X)))
8049 sparc_issue_rate (void)
8056 /* Assume V9 processors are capable of at least dual-issue. */
8058 case PROCESSOR_SUPERSPARC:
8060 case PROCESSOR_HYPERSPARC:
8061 case PROCESSOR_SPARCLITE86X:
8063 case PROCESSOR_ULTRASPARC:
8064 case PROCESSOR_ULTRASPARC3:
8070 set_extends (rtx insn)
8072 register rtx pat = PATTERN (insn);
8074 switch (GET_CODE (SET_SRC (pat)))
8076 /* Load and some shift instructions zero extend. */
8079 /* sethi clears the high bits */
8081 /* LO_SUM is used with sethi. sethi cleared the high
8082 bits and the values used with lo_sum are positive */
8084 /* Store flag stores 0 or 1 */
8094 rtx op0 = XEXP (SET_SRC (pat), 0);
8095 rtx op1 = XEXP (SET_SRC (pat), 1);
8096 if (GET_CODE (op1) == CONST_INT)
8097 return INTVAL (op1) >= 0;
8098 if (GET_CODE (op0) != REG)
8100 if (sparc_check_64 (op0, insn) == 1)
8102 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8107 rtx op0 = XEXP (SET_SRC (pat), 0);
8108 rtx op1 = XEXP (SET_SRC (pat), 1);
8109 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8111 if (GET_CODE (op1) == CONST_INT)
8112 return INTVAL (op1) >= 0;
8113 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8116 return GET_MODE (SET_SRC (pat)) == SImode;
8117 /* Positive integers leave the high bits zero. */
8119 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8121 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8124 return - (GET_MODE (SET_SRC (pat)) == SImode);
8126 return sparc_check_64 (SET_SRC (pat), insn);
8132 /* We _ought_ to have only one kind per function, but... */
8133 static GTY(()) rtx sparc_addr_diff_list;
8134 static GTY(()) rtx sparc_addr_list;
8137 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8139 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8141 sparc_addr_diff_list
8142 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8144 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8148 sparc_output_addr_vec (rtx vec)
8150 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8151 int idx, vlen = XVECLEN (body, 0);
8153 #ifdef ASM_OUTPUT_ADDR_VEC_START
8154 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8157 #ifdef ASM_OUTPUT_CASE_LABEL
8158 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8161 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8164 for (idx = 0; idx < vlen; idx++)
8166 ASM_OUTPUT_ADDR_VEC_ELT
8167 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8170 #ifdef ASM_OUTPUT_ADDR_VEC_END
8171 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8176 sparc_output_addr_diff_vec (rtx vec)
8178 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8179 rtx base = XEXP (XEXP (body, 0), 0);
8180 int idx, vlen = XVECLEN (body, 1);
8182 #ifdef ASM_OUTPUT_ADDR_VEC_START
8183 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8186 #ifdef ASM_OUTPUT_CASE_LABEL
8187 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8190 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8193 for (idx = 0; idx < vlen; idx++)
8195 ASM_OUTPUT_ADDR_DIFF_ELT
8198 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8199 CODE_LABEL_NUMBER (base));
8202 #ifdef ASM_OUTPUT_ADDR_VEC_END
8203 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8208 sparc_output_deferred_case_vectors (void)
8213 if (sparc_addr_list == NULL_RTX
8214 && sparc_addr_diff_list == NULL_RTX)
8217 /* Align to cache line in the function's code section. */
8218 function_section (current_function_decl);
8220 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8222 ASM_OUTPUT_ALIGN (asm_out_file, align);
8224 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8225 sparc_output_addr_vec (XEXP (t, 0));
8226 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8227 sparc_output_addr_diff_vec (XEXP (t, 0));
8229 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8232 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8233 unknown. Return 1 if the high bits are zero, -1 if the register is
8236 sparc_check_64 (rtx x, rtx insn)
8238 /* If a register is set only once it is safe to ignore insns this
8239 code does not know how to handle. The loop will either recognize
8240 the single set and return the correct value or fail to recognize
8245 if (GET_CODE (x) != REG)
8248 if (GET_MODE (x) == DImode)
8249 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8251 if (flag_expensive_optimizations
8252 && REG_N_SETS (REGNO (y)) == 1)
8258 insn = get_last_insn_anywhere ();
8263 while ((insn = PREV_INSN (insn)))
8265 switch (GET_CODE (insn))
8278 rtx pat = PATTERN (insn);
8279 if (GET_CODE (pat) != SET)
8281 if (rtx_equal_p (x, SET_DEST (pat)))
8282 return set_extends (insn);
8283 if (y && rtx_equal_p (y, SET_DEST (pat)))
8284 return set_extends (insn);
8285 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8293 /* Returns assembly code to perform a DImode shift using
8294 a 64-bit global or out register on SPARC-V8+. */
8296 sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8298 static char asm_code[60];
8300 /* The scratch register is only required when the destination
8301 register is not a 64-bit global or out register. */
8302 if (which_alternative != 2)
8303 operands[3] = operands[0];
8305 /* We can only shift by constants <= 63. */
8306 if (GET_CODE (operands[2]) == CONST_INT)
8307 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8309 if (GET_CODE (operands[1]) == CONST_INT)
8311 output_asm_insn ("mov\t%1, %3", operands);
8315 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8316 if (sparc_check_64 (operands[1], insn) <= 0)
8317 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8318 output_asm_insn ("or\t%L1, %3, %3", operands);
8321 strcpy(asm_code, opcode);
8323 if (which_alternative != 2)
8324 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8326 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8329 /* Output rtl to increment the profiler label LABELNO
8330 for profiling a function entry. */
8333 sparc_profile_hook (int labelno)
8338 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8339 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8340 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8342 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8345 #ifdef OBJECT_FORMAT_ELF
8347 sparc_elf_asm_named_section (const char *name, unsigned int flags)
8349 if (flags & SECTION_MERGE)
8351 /* entsize cannot be expressed in this section attributes
8353 default_elf_asm_named_section (name, flags);
8357 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8359 if (!(flags & SECTION_DEBUG))
8360 fputs (",#alloc", asm_out_file);
8361 if (flags & SECTION_WRITE)
8362 fputs (",#write", asm_out_file);
8363 if (flags & SECTION_CODE)
8364 fputs (",#execinstr", asm_out_file);
8366 /* ??? Handle SECTION_BSS. */
8368 fputc ('\n', asm_out_file);
8370 #endif /* OBJECT_FORMAT_ELF */
8372 /* We do not allow sibling calls if -mflat, nor
8373 we do not allow indirect calls to be optimized into sibling calls.
8375 Also, on sparc 32-bit we cannot emit a sibling call when the
8376 current function returns a structure. This is because the "unimp
8377 after call" convention would cause the callee to return to the
8378 wrong place. The generic code already disallows cases where the
8379 function being called returns a structure.
8381 It may seem strange how this last case could occur. Usually there
8382 is code after the call which jumps to epilogue code which dumps the
8383 return value into the struct return area. That ought to invalidate
8384 the sibling call right? Well, in the c++ case we can end up passing
8385 the pointer to the struct return area to a constructor (which returns
8386 void) and then nothing else happens. Such a sibling call would look
8387 valid without the added check here. */
8389 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8393 && (TARGET_ARCH64 || ! current_function_returns_struct));
8396 /* ??? Similar to the standard section selection, but force reloc-y-ness
8397 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8398 pretending PIC always on), but that's what the old code did. */
8401 sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align)
8403 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
8406 /* Use text section for a constant unless we need more alignment than
8410 sparc_aout_select_rtx_section (enum machine_mode mode, rtx x,
8411 unsigned HOST_WIDE_INT align)
8413 if (align <= MAX_TEXT_ALIGN
8414 && ! (flag_pic && (symbolic_operand (x, mode)
8415 || SUNOS4_SHARED_LIBRARIES)))
8416 readonly_data_section ();
8422 sparc_extra_constraint_check (rtx op, int c, int strict)
8427 && (c == 'T' || c == 'U'))
8433 return fp_sethi_p (op);
8436 return fp_mov_p (op);
8439 return fp_high_losum_p (op);
8443 || (GET_CODE (op) == REG
8444 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8445 || reg_renumber[REGNO (op)] >= 0)))
8446 return register_ok_for_ldd (op);
8458 /* Our memory extra constraints have to emulate the
8459 behavior of 'm' and 'o' in order for reload to work
8461 if (GET_CODE (op) == MEM)
8464 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8466 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8471 reload_ok_mem = (reload_in_progress
8472 && GET_CODE (op) == REG
8473 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8474 && reg_renumber [REGNO (op)] < 0);
8477 return reload_ok_mem;
8480 /* ??? This duplicates information provided to the compiler by the
8481 ??? scheduler description. Some day, teach genautomata to output
8482 ??? the latencies and then CSE will just use that. */
8485 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8489 case PLUS: case MINUS: case ABS: case NEG:
8490 case FLOAT: case UNSIGNED_FLOAT:
8491 case FIX: case UNSIGNED_FIX:
8492 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8493 if (FLOAT_MODE_P (GET_MODE (x)))
8497 case PROCESSOR_ULTRASPARC:
8498 case PROCESSOR_ULTRASPARC3:
8499 *total = COSTS_N_INSNS (4);
8502 case PROCESSOR_SUPERSPARC:
8503 *total = COSTS_N_INSNS (3);
8506 case PROCESSOR_CYPRESS:
8507 *total = COSTS_N_INSNS (5);
8510 case PROCESSOR_HYPERSPARC:
8511 case PROCESSOR_SPARCLITE86X:
8513 *total = COSTS_N_INSNS (1);
8518 *total = COSTS_N_INSNS (1);
8524 case PROCESSOR_ULTRASPARC:
8525 if (GET_MODE (x) == SFmode)
8526 *total = COSTS_N_INSNS (13);
8528 *total = COSTS_N_INSNS (23);
8531 case PROCESSOR_ULTRASPARC3:
8532 if (GET_MODE (x) == SFmode)
8533 *total = COSTS_N_INSNS (20);
8535 *total = COSTS_N_INSNS (29);
8538 case PROCESSOR_SUPERSPARC:
8539 *total = COSTS_N_INSNS (12);
8542 case PROCESSOR_CYPRESS:
8543 *total = COSTS_N_INSNS (63);
8546 case PROCESSOR_HYPERSPARC:
8547 case PROCESSOR_SPARCLITE86X:
8548 *total = COSTS_N_INSNS (17);
8552 *total = COSTS_N_INSNS (30);
8557 if (FLOAT_MODE_P (GET_MODE (x)))
8561 case PROCESSOR_ULTRASPARC:
8562 case PROCESSOR_ULTRASPARC3:
8563 *total = COSTS_N_INSNS (1);
8566 case PROCESSOR_SUPERSPARC:
8567 *total = COSTS_N_INSNS (3);
8570 case PROCESSOR_CYPRESS:
8571 *total = COSTS_N_INSNS (5);
8574 case PROCESSOR_HYPERSPARC:
8575 case PROCESSOR_SPARCLITE86X:
8577 *total = COSTS_N_INSNS (1);
8582 /* ??? Maybe mark integer compares as zero cost on
8583 ??? all UltraSPARC processors because the result
8584 ??? can be bypassed to a branch in the same group. */
8586 *total = COSTS_N_INSNS (1);
8590 if (FLOAT_MODE_P (GET_MODE (x)))
8594 case PROCESSOR_ULTRASPARC:
8595 case PROCESSOR_ULTRASPARC3:
8596 *total = COSTS_N_INSNS (4);
8599 case PROCESSOR_SUPERSPARC:
8600 *total = COSTS_N_INSNS (3);
8603 case PROCESSOR_CYPRESS:
8604 *total = COSTS_N_INSNS (7);
8607 case PROCESSOR_HYPERSPARC:
8608 case PROCESSOR_SPARCLITE86X:
8609 *total = COSTS_N_INSNS (1);
8613 *total = COSTS_N_INSNS (5);
8618 /* The latency is actually variable for Ultra-I/II
8619 And if one of the inputs have a known constant
8620 value, we could calculate this precisely.
8622 However, for that to be useful we would need to
8623 add some machine description changes which would
8624 make sure small constants ended up in rs1 of the
8625 multiply instruction. This is because the multiply
8626 latency is determined by the number of clear (or
8627 set if the value is negative) bits starting from
8628 the most significant bit of the first input.
8630 The algorithm for computing num_cycles of a multiply
8634 highest_bit = highest_clear_bit(rs1);
8636 highest_bit = highest_set_bit(rs1);
8639 num_cycles = 4 + ((highest_bit - 3) / 2);
8641 If we did that we would have to also consider register
8642 allocation issues that would result from forcing such
8643 a value into a register.
8645 There are other similar tricks we could play if we
8646 knew, for example, that one input was an array index.
8648 Since we do not play any such tricks currently the
8649 safest thing to do is report the worst case latency. */
8650 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8652 *total = (GET_MODE (x) == DImode
8653 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8657 /* Multiply latency on Ultra-III, fortunately, is constant. */
8658 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8660 *total = COSTS_N_INSNS (6);
8664 if (sparc_cpu == PROCESSOR_HYPERSPARC
8665 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8667 *total = COSTS_N_INSNS (17);
8671 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
8678 if (FLOAT_MODE_P (GET_MODE (x)))
8682 case PROCESSOR_ULTRASPARC:
8683 if (GET_MODE (x) == SFmode)
8684 *total = COSTS_N_INSNS (13);
8686 *total = COSTS_N_INSNS (23);
8689 case PROCESSOR_ULTRASPARC3:
8690 if (GET_MODE (x) == SFmode)
8691 *total = COSTS_N_INSNS (17);
8693 *total = COSTS_N_INSNS (20);
8696 case PROCESSOR_SUPERSPARC:
8697 if (GET_MODE (x) == SFmode)
8698 *total = COSTS_N_INSNS (6);
8700 *total = COSTS_N_INSNS (9);
8703 case PROCESSOR_HYPERSPARC:
8704 case PROCESSOR_SPARCLITE86X:
8705 if (GET_MODE (x) == SFmode)
8706 *total = COSTS_N_INSNS (8);
8708 *total = COSTS_N_INSNS (12);
8712 *total = COSTS_N_INSNS (7);
8717 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8718 *total = (GET_MODE (x) == DImode
8719 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8720 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8721 *total = (GET_MODE (x) == DImode
8722 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8724 *total = COSTS_N_INSNS (25);
8728 /* Conditional moves. */
8731 case PROCESSOR_ULTRASPARC:
8732 *total = COSTS_N_INSNS (2);
8735 case PROCESSOR_ULTRASPARC3:
8736 if (FLOAT_MODE_P (GET_MODE (x)))
8737 *total = COSTS_N_INSNS (3);
8739 *total = COSTS_N_INSNS (2);
8743 *total = COSTS_N_INSNS (1);
8748 /* If outer-code is SIGN/ZERO extension we have to subtract
8749 out COSTS_N_INSNS (1) from whatever we return in determining
8753 case PROCESSOR_ULTRASPARC:
8754 if (outer_code == ZERO_EXTEND)
8755 *total = COSTS_N_INSNS (1);
8757 *total = COSTS_N_INSNS (2);
8760 case PROCESSOR_ULTRASPARC3:
8761 if (outer_code == ZERO_EXTEND)
8763 if (GET_MODE (x) == QImode
8764 || GET_MODE (x) == HImode
8765 || outer_code == SIGN_EXTEND)
8766 *total = COSTS_N_INSNS (2);
8768 *total = COSTS_N_INSNS (1);
8772 /* This handles sign extension (3 cycles)
8773 and everything else (2 cycles). */
8774 *total = COSTS_N_INSNS (2);
8778 case PROCESSOR_SUPERSPARC:
8779 if (FLOAT_MODE_P (GET_MODE (x))
8780 || outer_code == ZERO_EXTEND
8781 || outer_code == SIGN_EXTEND)
8782 *total = COSTS_N_INSNS (0);
8784 *total = COSTS_N_INSNS (1);
8787 case PROCESSOR_TSC701:
8788 if (outer_code == ZERO_EXTEND
8789 || outer_code == SIGN_EXTEND)
8790 *total = COSTS_N_INSNS (2);
8792 *total = COSTS_N_INSNS (3);
8795 case PROCESSOR_CYPRESS:
8796 if (outer_code == ZERO_EXTEND
8797 || outer_code == SIGN_EXTEND)
8798 *total = COSTS_N_INSNS (1);
8800 *total = COSTS_N_INSNS (2);
8803 case PROCESSOR_HYPERSPARC:
8804 case PROCESSOR_SPARCLITE86X:
8806 if (outer_code == ZERO_EXTEND
8807 || outer_code == SIGN_EXTEND)
8808 *total = COSTS_N_INSNS (0);
8810 *total = COSTS_N_INSNS (1);
8815 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8833 if (GET_MODE (x) == DImode
8834 && ((XINT (x, 3) == 0
8835 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8836 || (XINT (x, 3) == -1
8838 && XINT (x, 2) >= -0x1000)))
8849 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8850 Used for C++ multiple inheritance. */
8853 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8854 HOST_WIDE_INT delta,
8855 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8858 rtx this, insn, funexp, delta_rtx, tmp;
8860 reload_completed = 1;
8861 epilogue_completed = 1;
8863 current_function_uses_only_leaf_regs = 1;
8865 emit_note (NOTE_INSN_PROLOGUE_END);
8867 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8868 returns a structure, the structure return pointer is there instead. */
8869 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8870 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
8872 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
8874 /* Add DELTA. When possible use a plain add, otherwise load it into
8875 a register first. */
8876 delta_rtx = GEN_INT (delta);
8877 if (!SPARC_SIMM13_P (delta))
8879 rtx scratch = gen_rtx_REG (Pmode, 1);
8881 sparc_emit_set_const64 (scratch, delta_rtx);
8883 sparc_emit_set_const32 (scratch, delta_rtx);
8884 delta_rtx = scratch;
8887 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
8888 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
8890 /* Generate a tail call to the target function. */
8891 if (! TREE_USED (function))
8893 assemble_external (function);
8894 TREE_USED (function) = 1;
8896 funexp = XEXP (DECL_RTL (function), 0);
8897 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8898 insn = emit_call_insn (gen_sibcall (funexp));
8899 SIBLING_CALL_P (insn) = 1;
8902 /* Run just enough of rest_of_compilation to get the insns emitted.
8903 There's not really enough bulk here to make other passes such as
8904 instruction scheduling worth while. Note that use_thunk calls
8905 assemble_start_function and assemble_end_function. */
8906 insn = get_insns ();
8907 insn_locators_initialize ();
8908 shorten_branches (insn);
8909 final_start_function (insn, file, 1);
8910 final (insn, file, 1, 0);
8911 final_end_function ();
8913 reload_completed = 0;
8914 epilogue_completed = 0;
8918 /* How to allocate a 'struct machine_function'. */
8920 static struct machine_function *
8921 sparc_init_machine_status (void)
8923 return ggc_alloc_cleared (sizeof (struct machine_function));
8926 /* Locate some local-dynamic symbol still in use by this function
8927 so that we can print its name in local-dynamic base patterns. */
8930 get_some_local_dynamic_name (void)
8934 if (cfun->machine->some_ld_name)
8935 return cfun->machine->some_ld_name;
8937 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8939 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8940 return cfun->machine->some_ld_name;
8946 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8951 && GET_CODE (x) == SYMBOL_REF
8952 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8954 cfun->machine->some_ld_name = XSTR (x, 0);
8961 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
8962 We need to emit DTP-relative relocations. */
8965 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
8970 fputs ("\t.word\t%r_tls_dtpoff32(", file);
8973 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
8978 output_addr_const (file, x);
8982 #include "gt-sparc.h"