1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
49 #include "target-def.h"
51 /* 1 if the caller has placed an "unimp" insn immediately after the call.
52 This is used in v8 code when calling a function that returns a structure.
53 v9 doesn't have this. Be careful to have this test be the same as that
56 #define SKIP_CALLERS_UNIMP_P \
57 (!TARGET_ARCH64 && current_function_returns_struct \
58 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
59 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
62 /* Global variables for machine-dependent things. */
64 /* Size of frame. Need to know this to emit return insns from leaf procedures.
65 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
66 reload pass. This is important as the value is later used in insn
67 scheduling (to see what can go in a delay slot).
68 APPARENT_FSIZE is the size of the stack less the register save area and less
69 the outgoing argument area. It is used when saving call preserved regs. */
70 static int apparent_fsize;
71 static int actual_fsize;
73 /* Number of live general or floating point registers needed to be
74 saved (as 4-byte quantities). */
75 static int num_gfregs;
77 /* Save the operands last given to a compare for use when we
78 generate a scc or bcc insn. */
79 rtx sparc_compare_op0, sparc_compare_op1;
81 /* Coordinate with the md file wrt special insns created by
82 sparc_nonflat_function_epilogue. */
83 bool sparc_emitting_epilogue;
85 /* Vector to say how input registers are mapped to output registers.
86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
87 eliminate it. You must use -fomit-frame-pointer to get that. */
88 char leaf_reg_remap[] =
89 { 0, 1, 2, 3, 4, 5, 6, 7,
90 -1, -1, -1, -1, -1, -1, 14, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1,
92 8, 9, 10, 11, 12, 13, -1, 15,
94 32, 33, 34, 35, 36, 37, 38, 39,
95 40, 41, 42, 43, 44, 45, 46, 47,
96 48, 49, 50, 51, 52, 53, 54, 55,
97 56, 57, 58, 59, 60, 61, 62, 63,
98 64, 65, 66, 67, 68, 69, 70, 71,
99 72, 73, 74, 75, 76, 77, 78, 79,
100 80, 81, 82, 83, 84, 85, 86, 87,
101 88, 89, 90, 91, 92, 93, 94, 95,
102 96, 97, 98, 99, 100};
104 /* Vector, indexed by hard register number, which contains 1
105 for a register that is allowable in a candidate for leaf
106 function treatment. */
107 char sparc_leaf_regs[] =
108 { 1, 1, 1, 1, 1, 1, 1, 1,
109 0, 0, 0, 0, 0, 0, 1, 0,
110 0, 0, 0, 0, 0, 0, 0, 0,
111 1, 1, 1, 1, 1, 1, 0, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
122 /* Name of where we pretend to think the frame pointer points.
123 Normally, this is "%fp", but if we are in a leaf procedure,
124 this is "%sp+something". We record "something" separately as it may be
125 too big for reg+constant addressing. */
127 static const char *frame_base_name;
128 static int frame_base_offset;
130 static void sparc_init_modes PARAMS ((void));
131 static int save_regs PARAMS ((FILE *, int, int, const char *,
133 static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int));
134 static void build_big_number PARAMS ((FILE *, int, const char *));
135 static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *,
136 enum machine_mode, tree, int, int,
139 static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
140 static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
142 static void sparc_output_addr_vec PARAMS ((rtx));
143 static void sparc_output_addr_diff_vec PARAMS ((rtx));
144 static void sparc_output_deferred_case_vectors PARAMS ((void));
145 static int check_return_regs PARAMS ((rtx));
146 static int epilogue_renumber PARAMS ((rtx *, int));
147 static bool sparc_assemble_integer PARAMS ((rtx, unsigned int, int));
148 static int set_extends PARAMS ((rtx));
149 static void output_restore_regs PARAMS ((FILE *, int));
150 static void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
151 static void sparc_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
152 static void sparc_flat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
153 static void sparc_flat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
154 static void sparc_nonflat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT,
156 static void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT,
158 #ifdef OBJECT_FORMAT_ELF
159 static void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int));
161 static void sparc_aout_select_section PARAMS ((tree, int,
162 unsigned HOST_WIDE_INT))
164 static void sparc_aout_select_rtx_section PARAMS ((enum machine_mode, rtx,
165 unsigned HOST_WIDE_INT))
168 static int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
169 static int sparc_issue_rate PARAMS ((void));
170 static void sparc_sched_init PARAMS ((FILE *, int, int));
171 static int sparc_use_dfa_pipeline_interface PARAMS ((void));
172 static int sparc_use_sched_lookahead PARAMS ((void));
174 static void emit_soft_tfmode_libcall PARAMS ((const char *, int, rtx *));
175 static void emit_soft_tfmode_binop PARAMS ((enum rtx_code, rtx *));
176 static void emit_soft_tfmode_unop PARAMS ((enum rtx_code, rtx *));
177 static void emit_soft_tfmode_cvt PARAMS ((enum rtx_code, rtx *));
178 static void emit_hard_tfmode_operation PARAMS ((enum rtx_code, rtx *));
180 static bool sparc_function_ok_for_sibcall PARAMS ((tree, tree));
181 static void sparc_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
182 HOST_WIDE_INT, tree));
183 static bool sparc_rtx_costs PARAMS ((rtx, int, int, int *));
185 /* Option handling. */
187 /* Code model option as passed by user. */
188 const char *sparc_cmodel_string;
190 enum cmodel sparc_cmodel;
192 char sparc_hard_reg_printed[8];
194 struct sparc_cpu_select sparc_select[] =
196 /* switch name, tune arch */
197 { (char *)0, "default", 1, 1 },
198 { (char *)0, "-mcpu=", 1, 1 },
199 { (char *)0, "-mtune=", 1, 0 },
203 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
204 enum processor_type sparc_cpu;
206 /* Initialize the GCC target structure. */
208 /* The sparc default is to use .half rather than .short for aligned
209 HI objects. Use .word instead of .long on non-ELF systems. */
210 #undef TARGET_ASM_ALIGNED_HI_OP
211 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
212 #ifndef OBJECT_FORMAT_ELF
213 #undef TARGET_ASM_ALIGNED_SI_OP
214 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
217 #undef TARGET_ASM_UNALIGNED_HI_OP
218 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
219 #undef TARGET_ASM_UNALIGNED_SI_OP
220 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
221 #undef TARGET_ASM_UNALIGNED_DI_OP
222 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
224 /* The target hook has to handle DI-mode values. */
225 #undef TARGET_ASM_INTEGER
226 #define TARGET_ASM_INTEGER sparc_assemble_integer
228 #undef TARGET_ASM_FUNCTION_PROLOGUE
229 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
230 #undef TARGET_ASM_FUNCTION_EPILOGUE
231 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
233 #undef TARGET_SCHED_ADJUST_COST
234 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
235 #undef TARGET_SCHED_ISSUE_RATE
236 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
237 #undef TARGET_SCHED_INIT
238 #define TARGET_SCHED_INIT sparc_sched_init
239 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
240 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
241 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
242 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
244 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
245 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
247 #undef TARGET_ASM_OUTPUT_MI_THUNK
248 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
249 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
250 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
252 #undef TARGET_RTX_COSTS
253 #define TARGET_RTX_COSTS sparc_rtx_costs
254 #undef TARGET_ADDRESS_COST
255 #define TARGET_ADDRESS_COST hook_int_rtx_0
257 struct gcc_target targetm = TARGET_INITIALIZER;
259 /* Validate and override various options, and do some machine dependent
263 sparc_override_options ()
265 static struct code_model {
266 const char *const name;
268 } const cmodels[] = {
270 { "medlow", CM_MEDLOW },
271 { "medmid", CM_MEDMID },
272 { "medany", CM_MEDANY },
273 { "embmedany", CM_EMBMEDANY },
276 const struct code_model *cmodel;
277 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
278 static struct cpu_default {
280 const char *const name;
281 } const cpu_default[] = {
282 /* There must be one entry here for each TARGET_CPU value. */
283 { TARGET_CPU_sparc, "cypress" },
284 { TARGET_CPU_sparclet, "tsc701" },
285 { TARGET_CPU_sparclite, "f930" },
286 { TARGET_CPU_v8, "v8" },
287 { TARGET_CPU_hypersparc, "hypersparc" },
288 { TARGET_CPU_sparclite86x, "sparclite86x" },
289 { TARGET_CPU_supersparc, "supersparc" },
290 { TARGET_CPU_v9, "v9" },
291 { TARGET_CPU_ultrasparc, "ultrasparc" },
292 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
295 const struct cpu_default *def;
296 /* Table of values for -m{cpu,tune}=. */
297 static struct cpu_table {
298 const char *const name;
299 const enum processor_type processor;
302 } const cpu_table[] = {
303 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
304 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
305 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
306 /* TI TMS390Z55 supersparc */
307 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
308 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
309 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
310 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
311 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
312 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
313 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
314 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
316 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
318 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
319 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
320 /* TI ultrasparc I, II, IIi */
321 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
322 /* Although insns using %y are deprecated, it is a clear win on current
324 |MASK_DEPRECATED_V8_INSNS},
325 /* TI ultrasparc III */
326 /* ??? Check if %y issue still holds true in ultra3. */
327 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
330 const struct cpu_table *cpu;
331 const struct sparc_cpu_select *sel;
334 #ifndef SPARC_BI_ARCH
335 /* Check for unsupported architecture size. */
336 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
337 error ("%s is not supported by this configuration",
338 DEFAULT_ARCH32_P ? "-m64" : "-m32");
341 /* We force all 64bit archs to use 128 bit long double */
342 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
344 error ("-mlong-double-64 not allowed with -m64");
345 target_flags |= MASK_LONG_DOUBLE_128;
348 /* Code model selection. */
349 sparc_cmodel = SPARC_DEFAULT_CMODEL;
353 sparc_cmodel = CM_32;
356 if (sparc_cmodel_string != NULL)
360 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
361 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
363 if (cmodel->name == NULL)
364 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
366 sparc_cmodel = cmodel->value;
369 error ("-mcmodel= is not supported on 32 bit systems");
372 fpu = TARGET_FPU; /* save current -mfpu status */
374 /* Set the default CPU. */
375 for (def = &cpu_default[0]; def->name; ++def)
376 if (def->cpu == TARGET_CPU_DEFAULT)
380 sparc_select[0].string = def->name;
382 for (sel = &sparc_select[0]; sel->name; ++sel)
386 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
387 if (! strcmp (sel->string, cpu->name))
390 sparc_cpu = cpu->processor;
394 target_flags &= ~cpu->disable;
395 target_flags |= cpu->enable;
401 error ("bad value (%s) for %s switch", sel->string, sel->name);
405 /* If -mfpu or -mno-fpu was explicitly used, don't override with
406 the processor default. Clear MASK_FPU_SET to avoid confusing
407 the reverse mapping from switch values to names. */
410 target_flags = (target_flags & ~MASK_FPU) | fpu;
411 target_flags &= ~MASK_FPU_SET;
414 /* Don't allow -mvis if FPU is disabled. */
416 target_flags &= ~MASK_VIS;
418 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
420 -m64 also implies v9. */
421 if (TARGET_VIS || TARGET_ARCH64)
423 target_flags |= MASK_V9;
424 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
427 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
428 if (TARGET_V9 && TARGET_ARCH32)
429 target_flags |= MASK_DEPRECATED_V8_INSNS;
431 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
432 if (! TARGET_V9 || TARGET_ARCH64)
433 target_flags &= ~MASK_V8PLUS;
435 /* Don't use stack biasing in 32 bit mode. */
437 target_flags &= ~MASK_STACK_BIAS;
439 /* Supply a default value for align_functions. */
440 if (align_functions == 0
441 && (sparc_cpu == PROCESSOR_ULTRASPARC
442 || sparc_cpu == PROCESSOR_ULTRASPARC3))
443 align_functions = 32;
445 /* Validate PCC_STRUCT_RETURN. */
446 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
447 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
449 /* Only use .uaxword when compiling for a 64-bit target. */
451 targetm.asm_out.unaligned_op.di = NULL;
453 /* Do various machine dependent initializations. */
457 /* Miscellaneous utilities. */
459 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
460 or branch on register contents instructions. */
466 return (code == EQ || code == NE || code == GE || code == LT
467 || code == LE || code == GT);
471 /* Operand constraints. */
473 /* Return nonzero only if OP is a register of mode MODE,
477 reg_or_0_operand (op, mode)
479 enum machine_mode mode;
481 if (register_operand (op, mode))
483 if (op == const0_rtx)
485 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
486 && CONST_DOUBLE_HIGH (op) == 0
487 && CONST_DOUBLE_LOW (op) == 0)
489 if (fp_zero_operand (op, mode))
494 /* Return nonzero only if OP is const1_rtx. */
497 const1_operand (op, mode)
499 enum machine_mode mode ATTRIBUTE_UNUSED;
501 return op == const1_rtx;
504 /* Nonzero if OP is a floating point value with value 0.0. */
507 fp_zero_operand (op, mode)
509 enum machine_mode mode;
511 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
513 return op == CONST0_RTX (mode);
516 /* Nonzero if OP is a register operand in floating point register. */
519 fp_register_operand (op, mode)
521 enum machine_mode mode;
523 if (! register_operand (op, mode))
525 if (GET_CODE (op) == SUBREG)
526 op = SUBREG_REG (op);
527 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
530 /* Nonzero if OP is a floating point constant which can
531 be loaded into an integer register using a single
532 sethi instruction. */
538 if (GET_CODE (op) == CONST_DOUBLE)
543 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
544 if (REAL_VALUES_EQUAL (r, dconst0) &&
545 ! REAL_VALUE_MINUS_ZERO (r))
547 REAL_VALUE_TO_TARGET_SINGLE (r, i);
548 if (SPARC_SETHI_P (i))
555 /* Nonzero if OP is a floating point constant which can
556 be loaded into an integer register using a single
563 if (GET_CODE (op) == CONST_DOUBLE)
568 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
569 if (REAL_VALUES_EQUAL (r, dconst0) &&
570 ! REAL_VALUE_MINUS_ZERO (r))
572 REAL_VALUE_TO_TARGET_SINGLE (r, i);
573 if (SPARC_SIMM13_P (i))
580 /* Nonzero if OP is a floating point constant which can
581 be loaded into an integer register using a high/losum
582 instruction sequence. */
588 /* The constraints calling this should only be in
589 SFmode move insns, so any constant which cannot
590 be moved using a single insn will do. */
591 if (GET_CODE (op) == CONST_DOUBLE)
596 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
597 if (REAL_VALUES_EQUAL (r, dconst0) &&
598 ! REAL_VALUE_MINUS_ZERO (r))
600 REAL_VALUE_TO_TARGET_SINGLE (r, i);
601 if (! SPARC_SETHI_P (i)
602 && ! SPARC_SIMM13_P (i))
609 /* Nonzero if OP is an integer register. */
612 intreg_operand (op, mode)
614 enum machine_mode mode ATTRIBUTE_UNUSED;
616 return (register_operand (op, SImode)
617 || (TARGET_ARCH64 && register_operand (op, DImode)));
620 /* Nonzero if OP is a floating point condition code register. */
623 fcc_reg_operand (op, mode)
625 enum machine_mode mode;
627 /* This can happen when recog is called from combine. Op may be a MEM.
628 Fail instead of calling abort in this case. */
629 if (GET_CODE (op) != REG)
632 if (mode != VOIDmode && mode != GET_MODE (op))
635 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
638 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
639 if (reg_renumber == 0)
640 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
641 return REGNO_OK_FOR_CCFP_P (REGNO (op));
643 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
647 /* Nonzero if OP is a floating point condition code fcc0 register. */
650 fcc0_reg_operand (op, mode)
652 enum machine_mode mode;
654 /* This can happen when recog is called from combine. Op may be a MEM.
655 Fail instead of calling abort in this case. */
656 if (GET_CODE (op) != REG)
659 if (mode != VOIDmode && mode != GET_MODE (op))
662 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
665 return REGNO (op) == SPARC_FCC_REG;
668 /* Nonzero if OP is an integer or floating point condition code register. */
671 icc_or_fcc_reg_operand (op, mode)
673 enum machine_mode mode;
675 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
677 if (mode != VOIDmode && mode != GET_MODE (op))
680 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
685 return fcc_reg_operand (op, mode);
688 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
690 restore_operand (op, mode)
692 enum machine_mode mode;
694 return (GET_CODE (op) == REG && GET_MODE (op) == mode
695 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
698 /* Call insn on SPARC can take a PC-relative constant address, or any regular
702 call_operand (op, mode)
704 enum machine_mode mode;
706 if (GET_CODE (op) != MEM)
709 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
713 call_operand_address (op, mode)
715 enum machine_mode mode;
717 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
720 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
721 reference and a constant. */
724 symbolic_operand (op, mode)
726 enum machine_mode mode;
728 enum machine_mode omode = GET_MODE (op);
730 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
733 switch (GET_CODE (op))
741 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
742 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
743 && GET_CODE (XEXP (op, 1)) == CONST_INT);
750 /* Return truth value of statement that OP is a symbolic memory
751 operand of mode MODE. */
754 symbolic_memory_operand (op, mode)
756 enum machine_mode mode ATTRIBUTE_UNUSED;
758 if (GET_CODE (op) == SUBREG)
759 op = SUBREG_REG (op);
760 if (GET_CODE (op) != MEM)
763 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
764 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
767 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
770 label_ref_operand (op, mode)
772 enum machine_mode mode;
774 if (GET_CODE (op) != LABEL_REF)
776 if (GET_MODE (op) != mode)
781 /* Return 1 if the operand is an argument used in generating pic references
782 in either the medium/low or medium/anywhere code models of sparc64. */
785 sp64_medium_pic_operand (op, mode)
787 enum machine_mode mode ATTRIBUTE_UNUSED;
789 /* Check for (const (minus (symbol_ref:GOT)
790 (const (minus (label) (pc))))). */
791 if (GET_CODE (op) != CONST)
794 if (GET_CODE (op) != MINUS)
796 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
798 /* ??? Ensure symbol is GOT. */
799 if (GET_CODE (XEXP (op, 1)) != CONST)
801 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
806 /* Return 1 if the operand is a data segment reference. This includes
807 the readonly data segment, or in other words anything but the text segment.
808 This is needed in the medium/anywhere code model on v9. These values
809 are accessed with EMBMEDANY_BASE_REG. */
812 data_segment_operand (op, mode)
814 enum machine_mode mode ATTRIBUTE_UNUSED;
816 switch (GET_CODE (op))
819 return ! SYMBOL_REF_FUNCTION_P (op);
821 /* Assume canonical format of symbol + constant.
824 return data_segment_operand (XEXP (op, 0), VOIDmode);
830 /* Return 1 if the operand is a text segment reference.
831 This is needed in the medium/anywhere code model on v9. */
834 text_segment_operand (op, mode)
836 enum machine_mode mode ATTRIBUTE_UNUSED;
838 switch (GET_CODE (op))
843 return SYMBOL_REF_FUNCTION_P (op);
845 /* Assume canonical format of symbol + constant.
848 return text_segment_operand (XEXP (op, 0), VOIDmode);
854 /* Return 1 if the operand is either a register or a memory operand that is
858 reg_or_nonsymb_mem_operand (op, mode)
860 enum machine_mode mode;
862 if (register_operand (op, mode))
865 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
872 splittable_symbolic_memory_operand (op, mode)
874 enum machine_mode mode ATTRIBUTE_UNUSED;
876 if (GET_CODE (op) != MEM)
878 if (! symbolic_operand (XEXP (op, 0), Pmode))
884 splittable_immediate_memory_operand (op, mode)
886 enum machine_mode mode ATTRIBUTE_UNUSED;
888 if (GET_CODE (op) != MEM)
890 if (! immediate_operand (XEXP (op, 0), Pmode))
895 /* Return truth value of whether OP is EQ or NE. */
900 enum machine_mode mode ATTRIBUTE_UNUSED;
902 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
905 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
906 or LTU for non-floating-point. We handle those specially. */
909 normal_comp_operator (op, mode)
911 enum machine_mode mode ATTRIBUTE_UNUSED;
913 enum rtx_code code = GET_CODE (op);
915 if (GET_RTX_CLASS (code) != '<')
918 if (GET_MODE (XEXP (op, 0)) == CCFPmode
919 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
922 return (code != NE && code != EQ && code != GEU && code != LTU);
925 /* Return 1 if this is a comparison operator. This allows the use of
926 MATCH_OPERATOR to recognize all the branch insns. */
929 noov_compare_op (op, mode)
931 enum machine_mode mode ATTRIBUTE_UNUSED;
933 enum rtx_code code = GET_CODE (op);
935 if (GET_RTX_CLASS (code) != '<')
938 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
939 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
940 /* These are the only branches which work with CC_NOOVmode. */
941 return (code == EQ || code == NE || code == GE || code == LT);
945 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
946 MATCH_OPERATOR to recognize all the branch insns. */
949 noov_compare64_op (op, mode)
951 enum machine_mode mode ATTRIBUTE_UNUSED;
953 enum rtx_code code = GET_CODE (op);
958 if (GET_RTX_CLASS (code) != '<')
961 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
962 /* These are the only branches which work with CCX_NOOVmode. */
963 return (code == EQ || code == NE || code == GE || code == LT);
964 return (GET_MODE (XEXP (op, 0)) == CCXmode);
967 /* Nonzero if OP is a comparison operator suitable for use in v9
968 conditional move or branch on register contents instructions. */
971 v9_regcmp_op (op, mode)
973 enum machine_mode mode ATTRIBUTE_UNUSED;
975 enum rtx_code code = GET_CODE (op);
977 if (GET_RTX_CLASS (code) != '<')
980 return v9_regcmp_p (code);
983 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
988 enum machine_mode mode ATTRIBUTE_UNUSED;
990 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
993 /* Return nonzero if OP is an operator of mode MODE which can set
994 the condition codes explicitly. We do not include PLUS and MINUS
995 because these require CC_NOOVmode, which we handle explicitly. */
998 cc_arithop (op, mode)
1000 enum machine_mode mode ATTRIBUTE_UNUSED;
1002 if (GET_CODE (op) == AND
1003 || GET_CODE (op) == IOR
1004 || GET_CODE (op) == XOR)
1010 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1011 complement its second operand and set the condition codes explicitly. */
1014 cc_arithopn (op, mode)
1016 enum machine_mode mode ATTRIBUTE_UNUSED;
1018 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1019 and (xor ... (not ...)) to (not (xor ...)). */
1020 return (GET_CODE (op) == AND
1021 || GET_CODE (op) == IOR);
1024 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1025 signed 13 bit immediate field. This is an acceptable SImode operand for
1026 most 3 address instructions. */
1029 arith_operand (op, mode)
1031 enum machine_mode mode;
1033 if (register_operand (op, mode))
1035 if (GET_CODE (op) != CONST_INT)
1037 return SMALL_INT32 (op);
1040 /* Return true if OP is a constant 4096 */
1043 arith_4096_operand (op, mode)
1045 enum machine_mode mode ATTRIBUTE_UNUSED;
1047 if (GET_CODE (op) != CONST_INT)
1050 return INTVAL (op) == 4096;
1053 /* Return true if OP is suitable as second operand for add/sub */
1056 arith_add_operand (op, mode)
1058 enum machine_mode mode;
1060 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1063 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1064 immediate field of OR and XOR instructions. Used for 64-bit
1065 constant formation patterns. */
1067 const64_operand (op, mode)
1069 enum machine_mode mode ATTRIBUTE_UNUSED;
1071 return ((GET_CODE (op) == CONST_INT
1072 && SPARC_SIMM13_P (INTVAL (op)))
1073 #if HOST_BITS_PER_WIDE_INT != 64
1074 || (GET_CODE (op) == CONST_DOUBLE
1075 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1076 && (CONST_DOUBLE_HIGH (op) ==
1077 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1078 (HOST_WIDE_INT)-1 : 0)))
1083 /* The same, but only for sethi instructions. */
1085 const64_high_operand (op, mode)
1087 enum machine_mode mode;
1089 return ((GET_CODE (op) == CONST_INT
1090 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1091 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1093 || (GET_CODE (op) == CONST_DOUBLE
1094 && CONST_DOUBLE_HIGH (op) == 0
1095 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1096 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1099 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1100 signed 11 bit immediate field. This is an acceptable SImode operand for
1101 the movcc instructions. */
1104 arith11_operand (op, mode)
1106 enum machine_mode mode;
1108 return (register_operand (op, mode)
1109 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1112 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1113 signed 10 bit immediate field. This is an acceptable SImode operand for
1114 the movrcc instructions. */
1117 arith10_operand (op, mode)
1119 enum machine_mode mode;
1121 return (register_operand (op, mode)
1122 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1125 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1126 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1128 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1129 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1130 for most 3 address instructions. */
1133 arith_double_operand (op, mode)
1135 enum machine_mode mode;
1137 return (register_operand (op, mode)
1138 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1140 && GET_CODE (op) == CONST_DOUBLE
1141 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1142 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1144 && GET_CODE (op) == CONST_DOUBLE
1145 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1146 && ((CONST_DOUBLE_HIGH (op) == -1
1147 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1148 || (CONST_DOUBLE_HIGH (op) == 0
1149 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1152 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1155 arith_double_4096_operand (op, mode)
1157 enum machine_mode mode ATTRIBUTE_UNUSED;
1159 return (TARGET_ARCH64 &&
1160 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1161 (GET_CODE (op) == CONST_DOUBLE &&
1162 CONST_DOUBLE_LOW (op) == 4096 &&
1163 CONST_DOUBLE_HIGH (op) == 0)));
1166 /* Return true if OP is suitable as second operand for add/sub in DImode */
1169 arith_double_add_operand (op, mode)
1171 enum machine_mode mode;
1173 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1176 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1177 can fit in an 11 bit immediate field. This is an acceptable DImode
1178 operand for the movcc instructions. */
1179 /* ??? Replace with arith11_operand? */
1182 arith11_double_operand (op, mode)
1184 enum machine_mode mode;
1186 return (register_operand (op, mode)
1187 || (GET_CODE (op) == CONST_DOUBLE
1188 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1189 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1190 && ((CONST_DOUBLE_HIGH (op) == -1
1191 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1192 || (CONST_DOUBLE_HIGH (op) == 0
1193 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1194 || (GET_CODE (op) == CONST_INT
1195 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1196 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1199 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1200 can fit in an 10 bit immediate field. This is an acceptable DImode
1201 operand for the movrcc instructions. */
1202 /* ??? Replace with arith10_operand? */
1205 arith10_double_operand (op, mode)
1207 enum machine_mode mode;
1209 return (register_operand (op, mode)
1210 || (GET_CODE (op) == CONST_DOUBLE
1211 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1212 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1213 && ((CONST_DOUBLE_HIGH (op) == -1
1214 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1215 || (CONST_DOUBLE_HIGH (op) == 0
1216 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1217 || (GET_CODE (op) == CONST_INT
1218 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1219 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1222 /* Return truth value of whether OP is an integer which fits the
1223 range constraining immediate operands in most three-address insns,
1224 which have a 13 bit immediate field. */
1227 small_int (op, mode)
1229 enum machine_mode mode ATTRIBUTE_UNUSED;
1231 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1235 small_int_or_double (op, mode)
1237 enum machine_mode mode ATTRIBUTE_UNUSED;
1239 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1240 || (GET_CODE (op) == CONST_DOUBLE
1241 && CONST_DOUBLE_HIGH (op) == 0
1242 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1245 /* Recognize operand values for the umul instruction. That instruction sign
1246 extends immediate values just like all other sparc instructions, but
1247 interprets the extended result as an unsigned number. */
1250 uns_small_int (op, mode)
1252 enum machine_mode mode ATTRIBUTE_UNUSED;
1254 #if HOST_BITS_PER_WIDE_INT > 32
1255 /* All allowed constants will fit a CONST_INT. */
1256 return (GET_CODE (op) == CONST_INT
1257 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1258 || (INTVAL (op) >= 0xFFFFF000
1259 && INTVAL (op) <= 0xFFFFFFFF)));
1261 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1262 || (GET_CODE (op) == CONST_DOUBLE
1263 && CONST_DOUBLE_HIGH (op) == 0
1264 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1269 uns_arith_operand (op, mode)
1271 enum machine_mode mode;
1273 return register_operand (op, mode) || uns_small_int (op, mode);
1276 /* Return truth value of statement that OP is a call-clobbered register. */
1278 clobbered_register (op, mode)
1280 enum machine_mode mode ATTRIBUTE_UNUSED;
1282 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1285 /* Return 1 if OP is a valid operand for the source of a move insn. */
1288 input_operand (op, mode)
1290 enum machine_mode mode;
1292 /* If both modes are non-void they must be the same. */
1293 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1296 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */
1297 if (GET_CODE (op) == CONSTANT_P_RTX)
1300 /* Allow any one instruction integer constant, and all CONST_INT
1301 variants when we are working in DImode and !arch64. */
1302 if (GET_MODE_CLASS (mode) == MODE_INT
1303 && ((GET_CODE (op) == CONST_INT
1304 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1305 || SPARC_SIMM13_P (INTVAL (op))
1307 && ! TARGET_ARCH64)))
1309 && GET_CODE (op) == CONST_DOUBLE
1310 && ((CONST_DOUBLE_HIGH (op) == 0
1311 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1313 #if HOST_BITS_PER_WIDE_INT == 64
1314 (CONST_DOUBLE_HIGH (op) == 0
1315 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1317 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1318 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1319 && CONST_DOUBLE_HIGH (op) == 0)
1320 || (CONST_DOUBLE_HIGH (op) == -1
1321 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1326 /* If !arch64 and this is a DImode const, allow it so that
1327 the splits can be generated. */
1330 && GET_CODE (op) == CONST_DOUBLE)
1333 if (register_operand (op, mode))
1336 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1337 && GET_CODE (op) == CONST_DOUBLE)
1340 /* If this is a SUBREG, look inside so that we handle
1341 paradoxical ones. */
1342 if (GET_CODE (op) == SUBREG)
1343 op = SUBREG_REG (op);
1345 /* Check for valid MEM forms. */
1346 if (GET_CODE (op) == MEM)
1348 rtx inside = XEXP (op, 0);
1350 if (GET_CODE (inside) == LO_SUM)
1352 /* We can't allow these because all of the splits
1353 (eventually as they trickle down into DFmode
1354 splits) require offsettable memory references. */
1356 && GET_MODE (op) == TFmode)
1359 return (register_operand (XEXP (inside, 0), Pmode)
1360 && CONSTANT_P (XEXP (inside, 1)));
1362 return memory_address_p (mode, inside);
1369 /* We know it can't be done in one insn when we get here,
1370 the movsi expander guarentees this. */
1372 sparc_emit_set_const32 (op0, op1)
1376 enum machine_mode mode = GET_MODE (op0);
1379 if (GET_CODE (op1) == CONST_INT)
1381 HOST_WIDE_INT value = INTVAL (op1);
1383 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1384 || SPARC_SIMM13_P (value))
1388 /* Full 2-insn decomposition is needed. */
1389 if (reload_in_progress || reload_completed)
1392 temp = gen_reg_rtx (mode);
1394 if (GET_CODE (op1) == CONST_INT)
1396 /* Emit them as real moves instead of a HIGH/LO_SUM,
1397 this way CSE can see everything and reuse intermediate
1398 values if it wants. */
1400 && HOST_BITS_PER_WIDE_INT != 64
1401 && (INTVAL (op1) & 0x80000000) != 0)
1402 emit_insn (gen_rtx_SET
1404 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1407 emit_insn (gen_rtx_SET (VOIDmode, temp,
1408 GEN_INT (INTVAL (op1)
1409 & ~(HOST_WIDE_INT)0x3ff)));
1411 emit_insn (gen_rtx_SET (VOIDmode,
1413 gen_rtx_IOR (mode, temp,
1414 GEN_INT (INTVAL (op1) & 0x3ff))));
1418 /* A symbol, emit in the traditional way. */
1419 emit_insn (gen_rtx_SET (VOIDmode, temp,
1420 gen_rtx_HIGH (mode, op1)));
1421 emit_insn (gen_rtx_SET (VOIDmode,
1422 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1428 /* SPARC-v9 code-model support. */
1430 sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1437 if (temp1 && GET_MODE (temp1) == TImode)
1440 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1443 switch (sparc_cmodel)
1446 /* The range spanned by all instructions in the object is less
1447 than 2^31 bytes (2GB) and the distance from any instruction
1448 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1449 than 2^31 bytes (2GB).
1451 The executable must be in the low 4TB of the virtual address
1454 sethi %hi(symbol), %temp
1455 or %temp, %lo(symbol), %reg */
1456 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1457 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1461 /* The range spanned by all instructions in the object is less
1462 than 2^31 bytes (2GB) and the distance from any instruction
1463 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1464 than 2^31 bytes (2GB).
1466 The executable must be in the low 16TB of the virtual address
1469 sethi %h44(symbol), %temp1
1470 or %temp1, %m44(symbol), %temp2
1471 sllx %temp2, 12, %temp3
1472 or %temp3, %l44(symbol), %reg */
1473 emit_insn (gen_seth44 (op0, op1));
1474 emit_insn (gen_setm44 (op0, op0, op1));
1475 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1476 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1477 emit_insn (gen_setl44 (op0, temp1, op1));
1481 /* The range spanned by all instructions in the object is less
1482 than 2^31 bytes (2GB) and the distance from any instruction
1483 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1484 than 2^31 bytes (2GB).
1486 The executable can be placed anywhere in the virtual address
1489 sethi %hh(symbol), %temp1
1490 sethi %lm(symbol), %temp2
1491 or %temp1, %hm(symbol), %temp3
1492 or %temp2, %lo(symbol), %temp4
1493 sllx %temp3, 32, %temp5
1494 or %temp4, %temp5, %reg */
1496 /* It is possible that one of the registers we got for operands[2]
1497 might coincide with that of operands[0] (which is why we made
1498 it TImode). Pick the other one to use as our scratch. */
1499 if (rtx_equal_p (temp1, op0))
1502 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1507 emit_insn (gen_sethh (op0, op1));
1508 emit_insn (gen_setlm (temp1, op1));
1509 emit_insn (gen_sethm (op0, op0, op1));
1510 emit_insn (gen_rtx_SET (VOIDmode, op0,
1511 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1512 emit_insn (gen_rtx_SET (VOIDmode, op0,
1513 gen_rtx_PLUS (DImode, op0, temp1)));
1514 emit_insn (gen_setlo (op0, op0, op1));
1518 /* Old old old backwards compatibility kruft here.
1519 Essentially it is MEDLOW with a fixed 64-bit
1520 virtual base added to all data segment addresses.
1521 Text-segment stuff is computed like MEDANY, we can't
1522 reuse the code above because the relocation knobs
1525 Data segment: sethi %hi(symbol), %temp1
1526 or %temp1, %lo(symbol), %temp2
1527 add %temp2, EMBMEDANY_BASE_REG, %reg
1529 Text segment: sethi %uhi(symbol), %temp1
1530 sethi %hi(symbol), %temp2
1531 or %temp1, %ulo(symbol), %temp3
1532 or %temp2, %lo(symbol), %temp4
1533 sllx %temp3, 32, %temp5
1534 or %temp4, %temp5, %reg */
1535 if (data_segment_operand (op1, GET_MODE (op1)))
1537 emit_insn (gen_embmedany_sethi (temp1, op1));
1538 emit_insn (gen_embmedany_brsum (op0, temp1));
1539 emit_insn (gen_embmedany_losum (op0, op0, op1));
1543 /* It is possible that one of the registers we got for operands[2]
1544 might coincide with that of operands[0] (which is why we made
1545 it TImode). Pick the other one to use as our scratch. */
1546 if (rtx_equal_p (temp1, op0))
1549 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1554 emit_insn (gen_embmedany_textuhi (op0, op1));
1555 emit_insn (gen_embmedany_texthi (temp1, op1));
1556 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1557 emit_insn (gen_rtx_SET (VOIDmode, op0,
1558 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1559 emit_insn (gen_rtx_SET (VOIDmode, op0,
1560 gen_rtx_PLUS (DImode, op0, temp1)));
1561 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1570 /* These avoid problems when cross compiling. If we do not
1571 go through all this hair then the optimizer will see
1572 invalid REG_EQUAL notes or in some cases none at all. */
1573 static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT));
1574 static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT));
1575 static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT));
1576 static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
1578 #if HOST_BITS_PER_WIDE_INT == 64
1579 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1580 #define GEN_INT64(__x) GEN_INT (__x)
1582 #define GEN_HIGHINT64(__x) \
1583 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1584 #define GEN_INT64(__x) \
1585 immed_double_const ((__x) & 0xffffffff, \
1586 ((__x) & 0x80000000 ? -1 : 0), DImode)
1589 /* The optimizer is not to assume anything about exactly
1590 which bits are set for a HIGH, they are unspecified.
1591 Unfortunately this leads to many missed optimizations
1592 during CSE. We mask out the non-HIGH bits, and matches
1593 a plain movdi, to alleviate this problem. */
1595 sparc_emit_set_safe_HIGH64 (dest, val)
1599 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1603 gen_safe_SET64 (dest, val)
1607 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1611 gen_safe_OR64 (src, val)
1615 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1619 gen_safe_XOR64 (src, val)
1623 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1626 /* Worker routines for 64-bit constant formation on arch64.
1627 One of the key things to be doing in these emissions is
1628 to create as many temp REGs as possible. This makes it
1629 possible for half-built constants to be used later when
1630 such values are similar to something required later on.
1631 Without doing this, the optimizer cannot see such
1634 static void sparc_emit_set_const64_quick1
1635 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int));
1638 sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1641 unsigned HOST_WIDE_INT low_bits;
1644 unsigned HOST_WIDE_INT high_bits;
1647 high_bits = (~low_bits) & 0xffffffff;
1649 high_bits = low_bits;
1651 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1654 emit_insn (gen_rtx_SET (VOIDmode, op0,
1655 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1659 /* If we are XOR'ing with -1, then we should emit a one's complement
1660 instead. This way the combiner will notice logical operations
1661 such as ANDN later on and substitute. */
1662 if ((low_bits & 0x3ff) == 0x3ff)
1664 emit_insn (gen_rtx_SET (VOIDmode, op0,
1665 gen_rtx_NOT (DImode, temp)));
1669 emit_insn (gen_rtx_SET (VOIDmode, op0,
1670 gen_safe_XOR64 (temp,
1671 (-(HOST_WIDE_INT)0x400
1672 | (low_bits & 0x3ff)))));
1677 static void sparc_emit_set_const64_quick2
1678 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT,
1679 unsigned HOST_WIDE_INT, int));
1682 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1685 unsigned HOST_WIDE_INT high_bits;
1686 unsigned HOST_WIDE_INT low_immediate;
1691 if ((high_bits & 0xfffffc00) != 0)
1693 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1694 if ((high_bits & ~0xfffffc00) != 0)
1695 emit_insn (gen_rtx_SET (VOIDmode, op0,
1696 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1702 emit_insn (gen_safe_SET64 (temp, high_bits));
1706 /* Now shift it up into place. */
1707 emit_insn (gen_rtx_SET (VOIDmode, op0,
1708 gen_rtx_ASHIFT (DImode, temp2,
1709 GEN_INT (shift_count))));
1711 /* If there is a low immediate part piece, finish up by
1712 putting that in as well. */
1713 if (low_immediate != 0)
1714 emit_insn (gen_rtx_SET (VOIDmode, op0,
1715 gen_safe_OR64 (op0, low_immediate)));
1718 static void sparc_emit_set_const64_longway
1719 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1721 /* Full 64-bit constant decomposition. Even though this is the
1722 'worst' case, we still optimize a few things away. */
1724 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1727 unsigned HOST_WIDE_INT high_bits;
1728 unsigned HOST_WIDE_INT low_bits;
1732 if (reload_in_progress || reload_completed)
1735 sub_temp = gen_reg_rtx (DImode);
1737 if ((high_bits & 0xfffffc00) != 0)
1739 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1740 if ((high_bits & ~0xfffffc00) != 0)
1741 emit_insn (gen_rtx_SET (VOIDmode,
1743 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1749 emit_insn (gen_safe_SET64 (temp, high_bits));
1753 if (!reload_in_progress && !reload_completed)
1755 rtx temp2 = gen_reg_rtx (DImode);
1756 rtx temp3 = gen_reg_rtx (DImode);
1757 rtx temp4 = gen_reg_rtx (DImode);
1759 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1760 gen_rtx_ASHIFT (DImode, sub_temp,
1763 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1764 if ((low_bits & ~0xfffffc00) != 0)
1766 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1767 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1768 emit_insn (gen_rtx_SET (VOIDmode, op0,
1769 gen_rtx_PLUS (DImode, temp4, temp3)));
1773 emit_insn (gen_rtx_SET (VOIDmode, op0,
1774 gen_rtx_PLUS (DImode, temp4, temp2)));
1779 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1780 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1781 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1784 /* We are in the middle of reload, so this is really
1785 painful. However we do still make an attempt to
1786 avoid emitting truly stupid code. */
1787 if (low1 != const0_rtx)
1789 emit_insn (gen_rtx_SET (VOIDmode, op0,
1790 gen_rtx_ASHIFT (DImode, sub_temp,
1791 GEN_INT (to_shift))));
1792 emit_insn (gen_rtx_SET (VOIDmode, op0,
1793 gen_rtx_IOR (DImode, op0, low1)));
1801 if (low2 != const0_rtx)
1803 emit_insn (gen_rtx_SET (VOIDmode, op0,
1804 gen_rtx_ASHIFT (DImode, sub_temp,
1805 GEN_INT (to_shift))));
1806 emit_insn (gen_rtx_SET (VOIDmode, op0,
1807 gen_rtx_IOR (DImode, op0, low2)));
1815 emit_insn (gen_rtx_SET (VOIDmode, op0,
1816 gen_rtx_ASHIFT (DImode, sub_temp,
1817 GEN_INT (to_shift))));
1818 if (low3 != const0_rtx)
1819 emit_insn (gen_rtx_SET (VOIDmode, op0,
1820 gen_rtx_IOR (DImode, op0, low3)));
1825 /* Analyze a 64-bit constant for certain properties. */
1826 static void analyze_64bit_constant
1827 PARAMS ((unsigned HOST_WIDE_INT,
1828 unsigned HOST_WIDE_INT,
1829 int *, int *, int *));
1832 analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
1833 unsigned HOST_WIDE_INT high_bits, low_bits;
1834 int *hbsp, *lbsp, *abbasp;
1836 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1839 lowest_bit_set = highest_bit_set = -1;
1843 if ((lowest_bit_set == -1)
1844 && ((low_bits >> i) & 1))
1846 if ((highest_bit_set == -1)
1847 && ((high_bits >> (32 - i - 1)) & 1))
1848 highest_bit_set = (64 - i - 1);
1851 && ((highest_bit_set == -1)
1852 || (lowest_bit_set == -1)));
1858 if ((lowest_bit_set == -1)
1859 && ((high_bits >> i) & 1))
1860 lowest_bit_set = i + 32;
1861 if ((highest_bit_set == -1)
1862 && ((low_bits >> (32 - i - 1)) & 1))
1863 highest_bit_set = 32 - i - 1;
1866 && ((highest_bit_set == -1)
1867 || (lowest_bit_set == -1)));
1869 /* If there are no bits set this should have gone out
1870 as one instruction! */
1871 if (lowest_bit_set == -1
1872 || highest_bit_set == -1)
1874 all_bits_between_are_set = 1;
1875 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1879 if ((low_bits & (1 << i)) != 0)
1884 if ((high_bits & (1 << (i - 32))) != 0)
1887 all_bits_between_are_set = 0;
1890 *hbsp = highest_bit_set;
1891 *lbsp = lowest_bit_set;
1892 *abbasp = all_bits_between_are_set;
1895 static int const64_is_2insns
1896 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1899 const64_is_2insns (high_bits, low_bits)
1900 unsigned HOST_WIDE_INT high_bits, low_bits;
1902 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1905 || high_bits == 0xffffffff)
1908 analyze_64bit_constant (high_bits, low_bits,
1909 &highest_bit_set, &lowest_bit_set,
1910 &all_bits_between_are_set);
1912 if ((highest_bit_set == 63
1913 || lowest_bit_set == 0)
1914 && all_bits_between_are_set != 0)
1917 if ((highest_bit_set - lowest_bit_set) < 21)
1923 static unsigned HOST_WIDE_INT create_simple_focus_bits
1924 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
1927 static unsigned HOST_WIDE_INT
1928 create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
1929 unsigned HOST_WIDE_INT high_bits, low_bits;
1930 int lowest_bit_set, shift;
1932 HOST_WIDE_INT hi, lo;
1934 if (lowest_bit_set < 32)
1936 lo = (low_bits >> lowest_bit_set) << shift;
1937 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1942 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1949 /* Here we are sure to be arch64 and this is an integer constant
1950 being loaded into a register. Emit the most efficient
1951 insn sequence possible. Detection of all the 1-insn cases
1952 has been done already. */
1954 sparc_emit_set_const64 (op0, op1)
1958 unsigned HOST_WIDE_INT high_bits, low_bits;
1959 int lowest_bit_set, highest_bit_set;
1960 int all_bits_between_are_set;
1963 /* Sanity check that we know what we are working with. */
1964 if (! TARGET_ARCH64)
1967 if (GET_CODE (op0) != SUBREG)
1969 if (GET_CODE (op0) != REG
1970 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1971 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1975 if (reload_in_progress || reload_completed)
1978 temp = gen_reg_rtx (DImode);
1980 if (GET_CODE (op1) != CONST_DOUBLE
1981 && GET_CODE (op1) != CONST_INT)
1983 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1987 if (GET_CODE (op1) == CONST_DOUBLE)
1989 #if HOST_BITS_PER_WIDE_INT == 64
1990 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1991 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1993 high_bits = CONST_DOUBLE_HIGH (op1);
1994 low_bits = CONST_DOUBLE_LOW (op1);
1999 #if HOST_BITS_PER_WIDE_INT == 64
2000 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2001 low_bits = (INTVAL (op1) & 0xffffffff);
2003 high_bits = ((INTVAL (op1) < 0) ?
2006 low_bits = INTVAL (op1);
2010 /* low_bits bits 0 --> 31
2011 high_bits bits 32 --> 63 */
2013 analyze_64bit_constant (high_bits, low_bits,
2014 &highest_bit_set, &lowest_bit_set,
2015 &all_bits_between_are_set);
2017 /* First try for a 2-insn sequence. */
2019 /* These situations are preferred because the optimizer can
2020 * do more things with them:
2022 * sllx %reg, shift, %reg
2024 * srlx %reg, shift, %reg
2025 * 3) mov some_small_const, %reg
2026 * sllx %reg, shift, %reg
2028 if (((highest_bit_set == 63
2029 || lowest_bit_set == 0)
2030 && all_bits_between_are_set != 0)
2031 || ((highest_bit_set - lowest_bit_set) < 12))
2033 HOST_WIDE_INT the_const = -1;
2034 int shift = lowest_bit_set;
2036 if ((highest_bit_set != 63
2037 && lowest_bit_set != 0)
2038 || all_bits_between_are_set == 0)
2041 create_simple_focus_bits (high_bits, low_bits,
2044 else if (lowest_bit_set == 0)
2045 shift = -(63 - highest_bit_set);
2047 if (! SPARC_SIMM13_P (the_const))
2050 emit_insn (gen_safe_SET64 (temp, the_const));
2052 emit_insn (gen_rtx_SET (VOIDmode,
2054 gen_rtx_ASHIFT (DImode,
2058 emit_insn (gen_rtx_SET (VOIDmode,
2060 gen_rtx_LSHIFTRT (DImode,
2062 GEN_INT (-shift))));
2068 /* Now a range of 22 or less bits set somewhere.
2069 * 1) sethi %hi(focus_bits), %reg
2070 * sllx %reg, shift, %reg
2071 * 2) sethi %hi(focus_bits), %reg
2072 * srlx %reg, shift, %reg
2074 if ((highest_bit_set - lowest_bit_set) < 21)
2076 unsigned HOST_WIDE_INT focus_bits =
2077 create_simple_focus_bits (high_bits, low_bits,
2078 lowest_bit_set, 10);
2080 if (! SPARC_SETHI_P (focus_bits))
2083 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2085 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2086 if (lowest_bit_set < 10)
2087 emit_insn (gen_rtx_SET (VOIDmode,
2089 gen_rtx_LSHIFTRT (DImode, temp,
2090 GEN_INT (10 - lowest_bit_set))));
2091 else if (lowest_bit_set > 10)
2092 emit_insn (gen_rtx_SET (VOIDmode,
2094 gen_rtx_ASHIFT (DImode, temp,
2095 GEN_INT (lowest_bit_set - 10))));
2101 /* 1) sethi %hi(low_bits), %reg
2102 * or %reg, %lo(low_bits), %reg
2103 * 2) sethi %hi(~low_bits), %reg
2104 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2107 || high_bits == 0xffffffff)
2109 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2110 (high_bits == 0xffffffff));
2114 /* Now, try 3-insn sequences. */
2116 /* 1) sethi %hi(high_bits), %reg
2117 * or %reg, %lo(high_bits), %reg
2118 * sllx %reg, 32, %reg
2122 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2126 /* We may be able to do something quick
2127 when the constant is negated, so try that. */
2128 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2129 (~low_bits) & 0xfffffc00))
2131 /* NOTE: The trailing bits get XOR'd so we need the
2132 non-negated bits, not the negated ones. */
2133 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2135 if ((((~high_bits) & 0xffffffff) == 0
2136 && ((~low_bits) & 0x80000000) == 0)
2137 || (((~high_bits) & 0xffffffff) == 0xffffffff
2138 && ((~low_bits) & 0x80000000) != 0))
2140 int fast_int = (~low_bits & 0xffffffff);
2142 if ((SPARC_SETHI_P (fast_int)
2143 && (~high_bits & 0xffffffff) == 0)
2144 || SPARC_SIMM13_P (fast_int))
2145 emit_insn (gen_safe_SET64 (temp, fast_int));
2147 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2152 #if HOST_BITS_PER_WIDE_INT == 64
2153 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2154 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2156 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2157 (~high_bits) & 0xffffffff,
2160 sparc_emit_set_const64 (temp, negated_const);
2163 /* If we are XOR'ing with -1, then we should emit a one's complement
2164 instead. This way the combiner will notice logical operations
2165 such as ANDN later on and substitute. */
2166 if (trailing_bits == 0x3ff)
2168 emit_insn (gen_rtx_SET (VOIDmode, op0,
2169 gen_rtx_NOT (DImode, temp)));
2173 emit_insn (gen_rtx_SET (VOIDmode,
2175 gen_safe_XOR64 (temp,
2176 (-0x400 | trailing_bits))));
2181 /* 1) sethi %hi(xxx), %reg
2182 * or %reg, %lo(xxx), %reg
2183 * sllx %reg, yyy, %reg
2185 * ??? This is just a generalized version of the low_bits==0
2186 * thing above, FIXME...
2188 if ((highest_bit_set - lowest_bit_set) < 32)
2190 unsigned HOST_WIDE_INT focus_bits =
2191 create_simple_focus_bits (high_bits, low_bits,
2194 /* We can't get here in this state. */
2195 if (highest_bit_set < 32
2196 || lowest_bit_set >= 32)
2199 /* So what we know is that the set bits straddle the
2200 middle of the 64-bit word. */
2201 sparc_emit_set_const64_quick2 (op0, temp,
2207 /* 1) sethi %hi(high_bits), %reg
2208 * or %reg, %lo(high_bits), %reg
2209 * sllx %reg, 32, %reg
2210 * or %reg, low_bits, %reg
2212 if (SPARC_SIMM13_P(low_bits)
2213 && ((int)low_bits > 0))
2215 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2219 /* The easiest way when all else fails, is full decomposition. */
2221 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2222 high_bits, low_bits, ~high_bits, ~low_bits);
2224 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2227 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2228 return the mode to be used for the comparison. For floating-point,
2229 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2230 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2231 processing is needed. */
2234 select_cc_mode (op, x, y)
2237 rtx y ATTRIBUTE_UNUSED;
2239 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2265 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2266 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2268 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2269 return CCX_NOOVmode;
2275 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2282 /* X and Y are two things to compare using CODE. Emit the compare insn and
2283 return the rtx for the cc reg in the proper mode. */
2286 gen_compare_reg (code, x, y)
2290 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2293 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2294 fcc regs (cse can't tell they're really call clobbered regs and will
2295 remove a duplicate comparison even if there is an intervening function
2296 call - it will then try to reload the cc reg via an int reg which is why
2297 we need the movcc patterns). It is possible to provide the movcc
2298 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2299 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2300 to tell cse that CCFPE mode registers (even pseudos) are call
2303 /* ??? This is an experiment. Rather than making changes to cse which may
2304 or may not be easy/clean, we do our own cse. This is possible because
2305 we will generate hard registers. Cse knows they're call clobbered (it
2306 doesn't know the same thing about pseudos). If we guess wrong, no big
2307 deal, but if we win, great! */
2309 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2310 #if 1 /* experiment */
2313 /* We cycle through the registers to ensure they're all exercised. */
2314 static int next_fcc_reg = 0;
2315 /* Previous x,y for each fcc reg. */
2316 static rtx prev_args[4][2];
2318 /* Scan prev_args for x,y. */
2319 for (reg = 0; reg < 4; reg++)
2320 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2325 prev_args[reg][0] = x;
2326 prev_args[reg][1] = y;
2327 next_fcc_reg = (next_fcc_reg + 1) & 3;
2329 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2332 cc_reg = gen_reg_rtx (mode);
2333 #endif /* ! experiment */
2334 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2335 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2337 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2339 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2340 gen_rtx_COMPARE (mode, x, y)));
2345 /* This function is used for v9 only.
2346 CODE is the code for an Scc's comparison.
2347 OPERANDS[0] is the target of the Scc insn.
2348 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2349 been generated yet).
2351 This function is needed to turn
2354 (gt (reg:CCX 100 %icc)
2358 (gt:DI (reg:CCX 100 %icc)
2361 IE: The instruction recognizer needs to see the mode of the comparison to
2362 find the right instruction. We could use "gt:DI" right in the
2363 define_expand, but leaving it out allows us to handle DI, SI, etc.
2365 We refer to the global sparc compare operands sparc_compare_op0 and
2366 sparc_compare_op1. */
2369 gen_v9_scc (compare_code, operands)
2370 enum rtx_code compare_code;
2371 register rtx *operands;
2376 && (GET_MODE (sparc_compare_op0) == DImode
2377 || GET_MODE (operands[0]) == DImode))
2380 op0 = sparc_compare_op0;
2381 op1 = sparc_compare_op1;
2383 /* Try to use the movrCC insns. */
2385 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2386 && op1 == const0_rtx
2387 && v9_regcmp_p (compare_code))
2389 /* Special case for op0 != 0. This can be done with one instruction if
2390 operands[0] == sparc_compare_op0. */
2392 if (compare_code == NE
2393 && GET_MODE (operands[0]) == DImode
2394 && rtx_equal_p (op0, operands[0]))
2396 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2397 gen_rtx_IF_THEN_ELSE (DImode,
2398 gen_rtx_fmt_ee (compare_code, DImode,
2405 if (reg_overlap_mentioned_p (operands[0], op0))
2407 /* Handle the case where operands[0] == sparc_compare_op0.
2408 We "early clobber" the result. */
2409 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2410 emit_move_insn (op0, sparc_compare_op0);
2413 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2414 if (GET_MODE (op0) != DImode)
2416 temp = gen_reg_rtx (DImode);
2417 convert_move (temp, op0, 0);
2421 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2422 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2423 gen_rtx_fmt_ee (compare_code, DImode,
2431 operands[1] = gen_compare_reg (compare_code, op0, op1);
2433 switch (GET_MODE (operands[1]))
2443 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2444 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2445 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2446 gen_rtx_fmt_ee (compare_code,
2447 GET_MODE (operands[1]),
2448 operands[1], const0_rtx),
2449 const1_rtx, operands[0])));
2454 /* Emit a conditional jump insn for the v9 architecture using comparison code
2455 CODE and jump target LABEL.
2456 This function exists to take advantage of the v9 brxx insns. */
2459 emit_v9_brxx_insn (code, op0, label)
2463 emit_jump_insn (gen_rtx_SET (VOIDmode,
2465 gen_rtx_IF_THEN_ELSE (VOIDmode,
2466 gen_rtx_fmt_ee (code, GET_MODE (op0),
2468 gen_rtx_LABEL_REF (VOIDmode, label),
2472 /* Generate a DFmode part of a hard TFmode register.
2473 REG is the TFmode hard register, LOW is 1 for the
2474 low 64bit of the register and 0 otherwise.
2477 gen_df_reg (reg, low)
2481 int regno = REGNO (reg);
2483 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2484 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2485 return gen_rtx_REG (DFmode, regno);
2488 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2489 Unlike normal calls, TFmode operands are passed by reference. It is
2490 assumed that no more than 3 operands are required. */
2493 emit_soft_tfmode_libcall (func_name, nargs, operands)
2494 const char *func_name;
2498 rtx ret_slot = NULL, arg[3], func_sym;
2501 /* We only expect to be called for conversions, unary, and binary ops. */
2502 if (nargs < 2 || nargs > 3)
2505 for (i = 0; i < nargs; ++i)
2507 rtx this_arg = operands[i];
2510 /* TFmode arguments and return values are passed by reference. */
2511 if (GET_MODE (this_arg) == TFmode)
2513 int force_stack_temp;
2515 force_stack_temp = 0;
2516 if (TARGET_BUGGY_QP_LIB && i == 0)
2517 force_stack_temp = 1;
2519 if (GET_CODE (this_arg) == MEM
2520 && ! force_stack_temp)
2521 this_arg = XEXP (this_arg, 0);
2522 else if (CONSTANT_P (this_arg)
2523 && ! force_stack_temp)
2525 this_slot = force_const_mem (TFmode, this_arg);
2526 this_arg = XEXP (this_slot, 0);
2530 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2532 /* Operand 0 is the return value. We'll copy it out later. */
2534 emit_move_insn (this_slot, this_arg);
2536 ret_slot = this_slot;
2538 this_arg = XEXP (this_slot, 0);
2545 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2547 if (GET_MODE (operands[0]) == TFmode)
2550 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2551 arg[0], GET_MODE (arg[0]),
2552 arg[1], GET_MODE (arg[1]));
2554 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2555 arg[0], GET_MODE (arg[0]),
2556 arg[1], GET_MODE (arg[1]),
2557 arg[2], GET_MODE (arg[2]));
2560 emit_move_insn (operands[0], ret_slot);
2569 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2570 GET_MODE (operands[0]), 1,
2571 arg[1], GET_MODE (arg[1]));
2573 if (ret != operands[0])
2574 emit_move_insn (operands[0], ret);
2578 /* Expand soft-float TFmode calls to sparc abi routines. */
2581 emit_soft_tfmode_binop (code, operands)
2605 emit_soft_tfmode_libcall (func, 3, operands);
2609 emit_soft_tfmode_unop (code, operands)
2624 emit_soft_tfmode_libcall (func, 2, operands);
2628 emit_soft_tfmode_cvt (code, operands)
2637 switch (GET_MODE (operands[1]))
2650 case FLOAT_TRUNCATE:
2651 switch (GET_MODE (operands[0]))
2665 switch (GET_MODE (operands[1]))
2678 case UNSIGNED_FLOAT:
2679 switch (GET_MODE (operands[1]))
2693 switch (GET_MODE (operands[0]))
2707 switch (GET_MODE (operands[0]))
2724 emit_soft_tfmode_libcall (func, 2, operands);
2727 /* Expand a hard-float tfmode operation. All arguments must be in
2731 emit_hard_tfmode_operation (code, operands)
2737 if (GET_RTX_CLASS (code) == '1')
2739 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2740 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2744 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2745 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2746 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2747 operands[1], operands[2]);
2750 if (register_operand (operands[0], VOIDmode))
2753 dest = gen_reg_rtx (GET_MODE (operands[0]));
2755 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2757 if (dest != operands[0])
2758 emit_move_insn (operands[0], dest);
2762 emit_tfmode_binop (code, operands)
2766 if (TARGET_HARD_QUAD)
2767 emit_hard_tfmode_operation (code, operands);
2769 emit_soft_tfmode_binop (code, operands);
2773 emit_tfmode_unop (code, operands)
2777 if (TARGET_HARD_QUAD)
2778 emit_hard_tfmode_operation (code, operands);
2780 emit_soft_tfmode_unop (code, operands);
2784 emit_tfmode_cvt (code, operands)
2788 if (TARGET_HARD_QUAD)
2789 emit_hard_tfmode_operation (code, operands);
2791 emit_soft_tfmode_cvt (code, operands);
2794 /* Return nonzero if a return peephole merging return with
2795 setting of output register is ok. */
2797 leaf_return_peephole_ok ()
2799 return (actual_fsize == 0);
2802 /* Return nonzero if a branch/jump/call instruction will be emitting
2803 nop into its delay slot. */
2806 empty_delay_slot (insn)
2811 /* If no previous instruction (should not happen), return true. */
2812 if (PREV_INSN (insn) == NULL)
2815 seq = NEXT_INSN (PREV_INSN (insn));
2816 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2822 /* Return nonzero if TRIAL can go into the function epilogue's
2823 delay slot. SLOT is the slot we are trying to fill. */
2826 eligible_for_epilogue_delay (trial, slot)
2835 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2838 if (get_attr_length (trial) != 1)
2841 /* If there are any call-saved registers, we should scan TRIAL if it
2842 does not reference them. For now just make it easy. */
2846 /* If the function uses __builtin_eh_return, the eh_return machinery
2847 occupies the delay slot. */
2848 if (current_function_calls_eh_return)
2851 /* In the case of a true leaf function, anything can go into the delay slot.
2852 A delay slot only exists however if the frame size is zero, otherwise
2853 we will put an insn to adjust the stack after the return. */
2854 if (current_function_uses_only_leaf_regs)
2856 if (leaf_return_peephole_ok ())
2857 return ((get_attr_in_uncond_branch_delay (trial)
2858 == IN_BRANCH_DELAY_TRUE));
2862 pat = PATTERN (trial);
2864 /* Otherwise, only operations which can be done in tandem with
2865 a `restore' or `return' insn can go into the delay slot. */
2866 if (GET_CODE (SET_DEST (pat)) != REG
2867 || REGNO (SET_DEST (pat)) < 24)
2870 /* If this instruction sets up floating point register and we have a return
2871 instruction, it can probably go in. But restore will not work
2873 if (REGNO (SET_DEST (pat)) >= 32)
2875 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2876 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2881 /* The set of insns matched here must agree precisely with the set of
2882 patterns paired with a RETURN in sparc.md. */
2884 src = SET_SRC (pat);
2886 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2887 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2888 && arith_operand (src, GET_MODE (src)))
2891 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2893 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2896 /* This matches "*return_di". */
2897 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2898 && arith_double_operand (src, GET_MODE (src)))
2899 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2901 /* This matches "*return_sf_no_fpu". */
2902 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2903 && register_operand (src, SFmode))
2906 /* If we have return instruction, anything that does not use
2907 local or output registers and can go into a delay slot wins. */
2908 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2909 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2912 /* This matches "*return_addsi". */
2913 else if (GET_CODE (src) == PLUS
2914 && arith_operand (XEXP (src, 0), SImode)
2915 && arith_operand (XEXP (src, 1), SImode)
2916 && (register_operand (XEXP (src, 0), SImode)
2917 || register_operand (XEXP (src, 1), SImode)))
2920 /* This matches "*return_adddi". */
2921 else if (GET_CODE (src) == PLUS
2922 && arith_double_operand (XEXP (src, 0), DImode)
2923 && arith_double_operand (XEXP (src, 1), DImode)
2924 && (register_operand (XEXP (src, 0), DImode)
2925 || register_operand (XEXP (src, 1), DImode)))
2928 /* This can match "*return_losum_[sd]i".
2929 Catch only some cases, so that return_losum* don't have
2931 else if (GET_CODE (src) == LO_SUM
2932 && ! TARGET_CM_MEDMID
2933 && ((register_operand (XEXP (src, 0), SImode)
2934 && immediate_operand (XEXP (src, 1), SImode))
2936 && register_operand (XEXP (src, 0), DImode)
2937 && immediate_operand (XEXP (src, 1), DImode))))
2940 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2941 else if (GET_CODE (src) == ASHIFT
2942 && (register_operand (XEXP (src, 0), SImode)
2943 || register_operand (XEXP (src, 0), DImode))
2944 && XEXP (src, 1) == const1_rtx)
2950 /* Return nonzero if TRIAL can go into the sibling call
2954 eligible_for_sibcall_delay (trial)
2959 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2962 if (get_attr_length (trial) != 1)
2965 pat = PATTERN (trial);
2967 if (current_function_uses_only_leaf_regs)
2969 /* If the tail call is done using the call instruction,
2970 we have to restore %o7 in the delay slot. */
2971 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2974 /* %g1 is used to build the function address */
2975 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2981 /* Otherwise, only operations which can be done in tandem with
2982 a `restore' insn can go into the delay slot. */
2983 if (GET_CODE (SET_DEST (pat)) != REG
2984 || REGNO (SET_DEST (pat)) < 24
2985 || REGNO (SET_DEST (pat)) >= 32)
2988 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2990 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2993 src = SET_SRC (pat);
2995 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2996 && arith_operand (src, GET_MODE (src)))
2999 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3001 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3004 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3005 && arith_double_operand (src, GET_MODE (src)))
3006 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3008 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
3009 && register_operand (src, SFmode))
3012 else if (GET_CODE (src) == PLUS
3013 && arith_operand (XEXP (src, 0), SImode)
3014 && arith_operand (XEXP (src, 1), SImode)
3015 && (register_operand (XEXP (src, 0), SImode)
3016 || register_operand (XEXP (src, 1), SImode)))
3019 else if (GET_CODE (src) == PLUS
3020 && arith_double_operand (XEXP (src, 0), DImode)
3021 && arith_double_operand (XEXP (src, 1), DImode)
3022 && (register_operand (XEXP (src, 0), DImode)
3023 || register_operand (XEXP (src, 1), DImode)))
3026 else if (GET_CODE (src) == LO_SUM
3027 && ! TARGET_CM_MEDMID
3028 && ((register_operand (XEXP (src, 0), SImode)
3029 && immediate_operand (XEXP (src, 1), SImode))
3031 && register_operand (XEXP (src, 0), DImode)
3032 && immediate_operand (XEXP (src, 1), DImode))))
3035 else if (GET_CODE (src) == ASHIFT
3036 && (register_operand (XEXP (src, 0), SImode)
3037 || register_operand (XEXP (src, 0), DImode))
3038 && XEXP (src, 1) == const1_rtx)
3045 check_return_regs (x)
3048 switch (GET_CODE (x))
3051 return IN_OR_GLOBAL_P (x);
3066 if (check_return_regs (XEXP (x, 1)) == 0)
3071 return check_return_regs (XEXP (x, 0));
3080 short_branch (uid1, uid2)
3083 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3085 /* Leave a few words of "slop". */
3086 if (delta >= -1023 && delta <= 1022)
3092 /* Return nonzero if REG is not used after INSN.
3093 We assume REG is a reload reg, and therefore does
3094 not live past labels or calls or jumps. */
3096 reg_unused_after (reg, insn)
3100 enum rtx_code code, prev_code = UNKNOWN;
3102 while ((insn = NEXT_INSN (insn)))
3104 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3107 code = GET_CODE (insn);
3108 if (GET_CODE (insn) == CODE_LABEL)
3111 if (GET_RTX_CLASS (code) == 'i')
3113 rtx set = single_set (insn);
3114 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3117 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3119 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3127 /* The table we use to reference PIC data. */
3128 static GTY(()) rtx global_offset_table;
3130 /* The function we use to get at it. */
3131 static GTY(()) rtx get_pc_symbol;
3132 static char get_pc_symbol_name[256];
3134 /* Ensure that we are not using patterns that are not OK with PIC. */
3143 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3144 || (GET_CODE (recog_data.operand[i]) == CONST
3145 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3146 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3147 == global_offset_table)
3148 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3157 /* Return true if X is an address which needs a temporary register when
3158 reloaded while generating PIC code. */
3161 pic_address_needs_scratch (x)
3164 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3165 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3166 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3167 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3168 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3174 /* Legitimize PIC addresses. If the address is already position-independent,
3175 we return ORIG. Newly generated position-independent addresses go into a
3176 reg. This is REG if nonzero, otherwise we allocate register(s) as
3180 legitimize_pic_address (orig, mode, reg)
3182 enum machine_mode mode ATTRIBUTE_UNUSED;
3185 if (GET_CODE (orig) == SYMBOL_REF)
3187 rtx pic_ref, address;
3192 if (reload_in_progress || reload_completed)
3195 reg = gen_reg_rtx (Pmode);
3200 /* If not during reload, allocate another temp reg here for loading
3201 in the address, so that these instructions can be optimized
3203 rtx temp_reg = ((reload_in_progress || reload_completed)
3204 ? reg : gen_reg_rtx (Pmode));
3206 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3207 won't get confused into thinking that these two instructions
3208 are loading in the true address of the symbol. If in the
3209 future a PIC rtx exists, that should be used instead. */
3210 if (Pmode == SImode)
3212 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3213 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3217 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3218 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3225 pic_ref = gen_rtx_MEM (Pmode,
3226 gen_rtx_PLUS (Pmode,
3227 pic_offset_table_rtx, address));
3228 current_function_uses_pic_offset_table = 1;
3229 RTX_UNCHANGING_P (pic_ref) = 1;
3230 insn = emit_move_insn (reg, pic_ref);
3231 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3233 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3237 else if (GET_CODE (orig) == CONST)
3241 if (GET_CODE (XEXP (orig, 0)) == PLUS
3242 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3247 if (reload_in_progress || reload_completed)
3250 reg = gen_reg_rtx (Pmode);
3253 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3255 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3256 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3257 base == reg ? 0 : reg);
3262 if (GET_CODE (offset) == CONST_INT)
3264 if (SMALL_INT (offset))
3265 return plus_constant (base, INTVAL (offset));
3266 else if (! reload_in_progress && ! reload_completed)
3267 offset = force_reg (Pmode, offset);
3269 /* If we reach here, then something is seriously wrong. */
3272 return gen_rtx_PLUS (Pmode, base, offset);
3274 else if (GET_CODE (orig) == LABEL_REF)
3275 /* ??? Why do we do this? */
3276 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3277 the register is live instead, in case it is eliminated. */
3278 current_function_uses_pic_offset_table = 1;
3283 /* Emit special PIC prologues. */
3286 load_pic_register ()
3288 /* Labels to get the PC in the prologue of this function. */
3289 int orig_flag_pic = flag_pic;
3294 /* If we haven't emitted the special get_pc helper function, do so now. */
3295 if (get_pc_symbol_name[0] == 0)
3299 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3302 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3304 ASM_OUTPUT_ALIGN (asm_out_file, align);
3305 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
3306 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3309 /* Initialize every time through, since we can't easily
3310 know this to be permanent. */
3311 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3312 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3315 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3318 flag_pic = orig_flag_pic;
3320 /* Need to emit this whether or not we obey regdecls,
3321 since setjmp/longjmp can cause life info to screw up.
3322 ??? In the case where we don't obey regdecls, this is not sufficient
3323 since we may not fall out the bottom. */
3324 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3327 /* Return 1 if RTX is a MEM which is known to be aligned to at
3328 least a DESIRED byte boundary. */
3331 mem_min_alignment (mem, desired)
3335 rtx addr, base, offset;
3337 /* If it's not a MEM we can't accept it. */
3338 if (GET_CODE (mem) != MEM)
3341 addr = XEXP (mem, 0);
3342 base = offset = NULL_RTX;
3343 if (GET_CODE (addr) == PLUS)
3345 if (GET_CODE (XEXP (addr, 0)) == REG)
3347 base = XEXP (addr, 0);
3349 /* What we are saying here is that if the base
3350 REG is aligned properly, the compiler will make
3351 sure any REG based index upon it will be so
3353 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3354 offset = XEXP (addr, 1);
3356 offset = const0_rtx;
3359 else if (GET_CODE (addr) == REG)
3362 offset = const0_rtx;
3365 if (base != NULL_RTX)
3367 int regno = REGNO (base);
3369 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3371 /* Check if the compiler has recorded some information
3372 about the alignment of the base REG. If reload has
3373 completed, we already matched with proper alignments.
3374 If not running global_alloc, reload might give us
3375 unaligned pointer to local stack though. */
3377 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3378 || (optimize && reload_completed))
3379 && (INTVAL (offset) & (desired - 1)) == 0)
3384 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3388 else if (! TARGET_UNALIGNED_DOUBLES
3389 || CONSTANT_P (addr)
3390 || GET_CODE (addr) == LO_SUM)
3392 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3393 is true, in which case we can only assume that an access is aligned if
3394 it is to a constant address, or the address involves a LO_SUM. */
3398 /* An obviously unaligned address. */
3403 /* Vectors to keep interesting information about registers where it can easily
3404 be got. We use to use the actual mode value as the bit number, but there
3405 are more than 32 modes now. Instead we use two tables: one indexed by
3406 hard register number, and one indexed by mode. */
3408 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3409 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3410 mapped into one sparc_mode_class mode. */
3412 enum sparc_mode_class {
3413 S_MODE, D_MODE, T_MODE, O_MODE,
3414 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3418 /* Modes for single-word and smaller quantities. */
3419 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3421 /* Modes for double-word and smaller quantities. */
3422 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3424 /* Modes for quad-word and smaller quantities. */
3425 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3427 /* Modes for 8-word and smaller quantities. */
3428 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3430 /* Modes for single-float quantities. We must allow any single word or
3431 smaller quantity. This is because the fix/float conversion instructions
3432 take integer inputs/outputs from the float registers. */
3433 #define SF_MODES (S_MODES)
3435 /* Modes for double-float and smaller quantities. */
3436 #define DF_MODES (S_MODES | D_MODES)
3438 /* Modes for double-float only quantities. */
3439 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3441 /* Modes for quad-float only quantities. */
3442 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3444 /* Modes for quad-float and smaller quantities. */
3445 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3447 /* Modes for quad-float and double-float quantities. */
3448 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3450 /* Modes for quad-float pair only quantities. */
3451 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3453 /* Modes for quad-float pairs and smaller quantities. */
3454 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3456 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3458 /* Modes for condition codes. */
3459 #define CC_MODES (1 << (int) CC_MODE)
3460 #define CCFP_MODES (1 << (int) CCFP_MODE)
3462 /* Value is 1 if register/mode pair is acceptable on sparc.
3463 The funny mixture of D and T modes is because integer operations
3464 do not specially operate on tetra quantities, so non-quad-aligned
3465 registers can hold quadword quantities (except %o4 and %i4 because
3466 they cross fixed registers). */
3468 /* This points to either the 32 bit or the 64 bit version. */
3469 const int *hard_regno_mode_classes;
3471 static const int hard_32bit_mode_classes[] = {
3472 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3473 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3474 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3475 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3477 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3478 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3479 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3480 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3482 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3483 and none can hold SFmode/SImode values. */
3484 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3485 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3486 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3487 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3490 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3496 static const int hard_64bit_mode_classes[] = {
3497 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3498 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3499 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3500 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3502 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3503 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3504 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3505 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3507 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3508 and none can hold SFmode/SImode values. */
3509 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3510 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3511 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3512 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3515 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3521 int sparc_mode_class [NUM_MACHINE_MODES];
3523 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3530 for (i = 0; i < NUM_MACHINE_MODES; i++)
3532 switch (GET_MODE_CLASS (i))
3535 case MODE_PARTIAL_INT:
3536 case MODE_COMPLEX_INT:
3537 if (GET_MODE_SIZE (i) <= 4)
3538 sparc_mode_class[i] = 1 << (int) S_MODE;
3539 else if (GET_MODE_SIZE (i) == 8)
3540 sparc_mode_class[i] = 1 << (int) D_MODE;
3541 else if (GET_MODE_SIZE (i) == 16)
3542 sparc_mode_class[i] = 1 << (int) T_MODE;
3543 else if (GET_MODE_SIZE (i) == 32)
3544 sparc_mode_class[i] = 1 << (int) O_MODE;
3546 sparc_mode_class[i] = 0;
3549 case MODE_COMPLEX_FLOAT:
3550 if (GET_MODE_SIZE (i) <= 4)
3551 sparc_mode_class[i] = 1 << (int) SF_MODE;
3552 else if (GET_MODE_SIZE (i) == 8)
3553 sparc_mode_class[i] = 1 << (int) DF_MODE;
3554 else if (GET_MODE_SIZE (i) == 16)
3555 sparc_mode_class[i] = 1 << (int) TF_MODE;
3556 else if (GET_MODE_SIZE (i) == 32)
3557 sparc_mode_class[i] = 1 << (int) OF_MODE;
3559 sparc_mode_class[i] = 0;
3563 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3564 we must explicitly check for them here. */
3565 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3566 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3567 else if (i == (int) CCmode || i == (int) CC_NOOVmode
3568 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3569 sparc_mode_class[i] = 1 << (int) CC_MODE;
3571 sparc_mode_class[i] = 0;
3577 hard_regno_mode_classes = hard_64bit_mode_classes;
3579 hard_regno_mode_classes = hard_32bit_mode_classes;
3581 /* Initialize the array used by REGNO_REG_CLASS. */
3582 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3584 if (i < 16 && TARGET_V8PLUS)
3585 sparc_regno_reg_class[i] = I64_REGS;
3586 else if (i < 32 || i == FRAME_POINTER_REGNUM)
3587 sparc_regno_reg_class[i] = GENERAL_REGS;
3589 sparc_regno_reg_class[i] = FP_REGS;
3591 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3593 sparc_regno_reg_class[i] = FPCC_REGS;
3595 sparc_regno_reg_class[i] = NO_REGS;
3599 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3600 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3601 v9 int regs as it simplifies the code. */
3604 save_regs (file, low, high, base, offset, n_regs, real_offset)
3614 if (TARGET_ARCH64 && high <= 32)
3616 for (i = low; i < high; i++)
3618 if (regs_ever_live[i] && ! call_used_regs[i])
3620 fprintf (file, "\tstx\t%s, [%s+%d]\n",
3621 reg_names[i], base, offset + 4 * n_regs);
3622 if (dwarf2out_do_frame ())
3623 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3630 for (i = low; i < high; i += 2)
3632 if (regs_ever_live[i] && ! call_used_regs[i])
3634 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3636 fprintf (file, "\tstd\t%s, [%s+%d]\n",
3637 reg_names[i], base, offset + 4 * n_regs);
3638 if (dwarf2out_do_frame ())
3640 char *l = dwarf2out_cfi_label ();
3641 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
3642 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
3648 fprintf (file, "\tst\t%s, [%s+%d]\n",
3649 reg_names[i], base, offset + 4 * n_regs);
3650 if (dwarf2out_do_frame ())
3651 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3657 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3659 fprintf (file, "\tst\t%s, [%s+%d]\n",
3660 reg_names[i+1], base, offset + 4 * n_regs + 4);
3661 if (dwarf2out_do_frame ())
3662 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
3671 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3673 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3674 v9 int regs as it simplifies the code. */
3677 restore_regs (file, low, high, base, offset, n_regs)
3686 if (TARGET_ARCH64 && high <= 32)
3688 for (i = low; i < high; i++)
3690 if (regs_ever_live[i] && ! call_used_regs[i])
3691 fprintf (file, "\tldx\t[%s+%d], %s\n",
3692 base, offset + 4 * n_regs, reg_names[i]),
3698 for (i = low; i < high; i += 2)
3700 if (regs_ever_live[i] && ! call_used_regs[i])
3701 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3702 fprintf (file, "\tldd\t[%s+%d], %s\n",
3703 base, offset + 4 * n_regs, reg_names[i]),
3706 fprintf (file, "\tld\t[%s+%d], %s\n",
3707 base, offset + 4 * n_regs, reg_names[i]),
3709 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3710 fprintf (file, "\tld\t[%s+%d], %s\n",
3711 base, offset + 4 * n_regs + 4, reg_names[i+1]),
3718 /* Compute the frame size required by the function. This function is called
3719 during the reload pass and also by output_function_prologue(). */
3722 compute_frame_size (size, leaf_function)
3727 int outgoing_args_size = (current_function_outgoing_args_size
3728 + REG_PARM_STACK_SPACE (current_function_decl));
3730 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3731 even to v9 int regs to be consistent with save_regs/restore_regs. */
3735 for (i = 0; i < 8; i++)
3736 if (regs_ever_live[i] && ! call_used_regs[i])
3741 for (i = 0; i < 8; i += 2)
3742 if ((regs_ever_live[i] && ! call_used_regs[i])
3743 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3747 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3748 if ((regs_ever_live[i] && ! call_used_regs[i])
3749 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3752 /* Set up values for use in `function_epilogue'. */
3753 num_gfregs = n_regs;
3755 if (leaf_function && n_regs == 0
3756 && size == 0 && current_function_outgoing_args_size == 0)
3758 actual_fsize = apparent_fsize = 0;
3762 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3763 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
3764 apparent_fsize += n_regs * 4;
3765 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3768 /* Make sure nothing can clobber our register windows.
3769 If a SAVE must be done, or there is a stack-local variable,
3770 the register window area must be allocated.
3771 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3772 if (leaf_function == 0 || size > 0)
3773 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3775 return SPARC_STACK_ALIGN (actual_fsize);
3778 /* Build a (32 bit) big number in a register. */
3779 /* ??? We may be able to use the set macro here too. */
3782 build_big_number (file, num, reg)
3787 if (num >= 0 || ! TARGET_ARCH64)
3789 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
3790 if ((num & 0x3ff) != 0)
3791 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
3793 else /* num < 0 && TARGET_ARCH64 */
3795 /* Sethi does not sign extend, so we must use a little trickery
3796 to use it for negative numbers. Invert the constant before
3797 loading it in, then use xor immediate to invert the loaded bits
3798 (along with the upper 32 bits) to the desired constant. This
3799 works because the sethi and immediate fields overlap. */
3802 int low = -0x400 + (asize & 0x3FF);
3804 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3805 inv, reg, reg, low, reg);
3809 /* Output any necessary .register pseudo-ops. */
3811 sparc_output_scratch_registers (file)
3812 FILE *file ATTRIBUTE_UNUSED;
3814 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3820 /* Check if %g[2367] were used without
3821 .register being printed for them already. */
3822 for (i = 2; i < 8; i++)
3824 if (regs_ever_live [i]
3825 && ! sparc_hard_reg_printed [i])
3827 sparc_hard_reg_printed [i] = 1;
3828 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
3835 /* This function generates the assembly code for function entry.
3836 FILE is a stdio stream to output the code to.
3837 SIZE is an int: how many units of temporary storage to allocate.
3838 Refer to the array `regs_ever_live' to determine which registers
3839 to save; `regs_ever_live[I]' is nonzero if register number I
3840 is ever used in the function. This macro is responsible for
3841 knowing which registers should not be saved even if used. */
3843 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
3844 of memory. If any fpu reg is used in the function, we allocate
3845 such a block here, at the bottom of the frame, just in case it's needed.
3847 If this function is a leaf procedure, then we may choose not
3848 to do a "save" insn. The decision about whether or not
3849 to do this is made in regclass.c. */
3852 sparc_output_function_prologue (file, size)
3857 sparc_flat_function_prologue (file, size);
3859 sparc_nonflat_function_prologue (file, size,
3860 current_function_uses_only_leaf_regs);
3863 /* Output code for the function prologue. */
3866 sparc_nonflat_function_prologue (file, size, leaf_function)
3871 sparc_output_scratch_registers (file);
3873 /* Need to use actual_fsize, since we are also allocating
3874 space for our callee (and our own register save area). */
3875 actual_fsize = compute_frame_size (size, leaf_function);
3879 frame_base_name = "%sp";
3880 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3884 frame_base_name = "%fp";
3885 frame_base_offset = SPARC_STACK_BIAS;
3888 /* This is only for the human reader. */
3889 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3891 if (actual_fsize == 0)
3893 else if (! leaf_function)
3895 if (actual_fsize <= 4096)
3896 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3897 else if (actual_fsize <= 8192)
3899 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3900 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3904 build_big_number (file, -actual_fsize, "%g1");
3905 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
3908 else /* leaf function */
3910 if (actual_fsize <= 4096)
3911 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3912 else if (actual_fsize <= 8192)
3914 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3915 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3919 build_big_number (file, -actual_fsize, "%g1");
3920 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3924 if (dwarf2out_do_frame () && actual_fsize)
3926 char *label = dwarf2out_cfi_label ();
3928 /* The canonical frame address refers to the top of the frame. */
3929 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3930 : HARD_FRAME_POINTER_REGNUM),
3933 if (! leaf_function)
3935 /* Note the register window save. This tells the unwinder that
3936 it needs to restore the window registers from the previous
3937 frame's window save area at 0(cfa). */
3938 dwarf2out_window_save (label);
3940 /* The return address (-8) is now in %i7. */
3941 dwarf2out_return_reg (label, 31);
3945 /* If doing anything with PIC, do it now. */
3947 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3949 /* Call saved registers are saved just above the outgoing argument area. */
3952 int offset, real_offset, n_regs;
3955 real_offset = -apparent_fsize;
3956 offset = -apparent_fsize + frame_base_offset;
3957 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3959 /* ??? This might be optimized a little as %g1 might already have a
3960 value close enough that a single add insn will do. */
3961 /* ??? Although, all of this is probably only a temporary fix
3962 because if %g1 can hold a function result, then
3963 output_function_epilogue will lose (the result will get
3965 build_big_number (file, offset, "%g1");
3966 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3972 base = frame_base_name;
3975 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3976 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3981 /* Output code to restore any call saved registers. */
3984 output_restore_regs (file, leaf_function)
3986 int leaf_function ATTRIBUTE_UNUSED;
3991 offset = -apparent_fsize + frame_base_offset;
3992 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3994 build_big_number (file, offset, "%g1");
3995 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4001 base = frame_base_name;
4004 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4005 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4008 /* This function generates the assembly code for function exit,
4009 on machines that need it.
4011 The function epilogue should not depend on the current stack pointer!
4012 It should use the frame pointer only. This is mandatory because
4013 of alloca; we also take advantage of it to omit stack adjustments
4014 before returning. */
4017 sparc_output_function_epilogue (file, size)
4022 sparc_flat_function_epilogue (file, size);
4024 sparc_nonflat_function_epilogue (file, size,
4025 current_function_uses_only_leaf_regs);
4028 /* Output code for the function epilogue. */
4031 sparc_nonflat_function_epilogue (file, size, leaf_function)
4033 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
4038 if (current_function_epilogue_delay_list == 0)
4040 /* If code does not drop into the epilogue, we need
4041 do nothing except output pending case vectors.
4043 We have to still output a dummy nop for the sake of
4044 sane backtraces. Otherwise, if the last two instructions
4045 of a function were call foo; dslot; this can make the return
4046 PC of foo (ie. address of call instruction plus 8) point to
4047 the first instruction in the next function. */
4050 fputs("\tnop\n", file);
4052 insn = get_last_insn ();
4053 if (GET_CODE (insn) == NOTE)
4054 insn = prev_nonnote_insn (insn);
4055 if (insn && GET_CODE (insn) == BARRIER)
4056 goto output_vectors;
4060 output_restore_regs (file, leaf_function);
4062 /* Work out how to skip the caller's unimp instruction if required. */
4064 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4066 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4068 if (! leaf_function)
4070 if (current_function_calls_eh_return)
4072 if (current_function_epilogue_delay_list)
4074 if (SKIP_CALLERS_UNIMP_P)
4077 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4079 /* If we wound up with things in our delay slot, flush them here. */
4080 else if (current_function_epilogue_delay_list)
4082 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4084 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4086 epilogue_renumber (&delay, 0);
4087 fputs (SKIP_CALLERS_UNIMP_P
4088 ? "\treturn\t%i7+12\n"
4089 : "\treturn\t%i7+8\n", file);
4090 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4097 if (GET_CODE (delay) != SET)
4100 src = SET_SRC (delay);
4101 if (GET_CODE (src) == ASHIFT)
4103 if (XEXP (src, 1) != const1_rtx)
4106 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4110 insn = gen_rtx_PARALLEL (VOIDmode,
4111 gen_rtvec (2, delay,
4112 gen_rtx_RETURN (VOIDmode)));
4113 insn = emit_jump_insn (insn);
4115 sparc_emitting_epilogue = true;
4116 final_scan_insn (insn, file, 1, 0, 1);
4117 sparc_emitting_epilogue = false;
4120 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4121 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4123 fprintf (file, "\t%s\n\trestore\n", ret);
4125 /* All of the following cases are for leaf functions. */
4126 else if (current_function_calls_eh_return)
4128 else if (current_function_epilogue_delay_list)
4130 /* eligible_for_epilogue_delay_slot ensures that if this is a
4131 leaf function, then we will only have insn in the delay slot
4132 if the frame size is zero, thus no adjust for the stack is
4134 if (actual_fsize != 0)
4136 fprintf (file, "\t%s\n", ret);
4137 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4140 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4141 avoid generating confusing assembly language output. */
4142 else if (actual_fsize == 0)
4143 fprintf (file, "\t%s\n\tnop\n", ret);
4144 else if (actual_fsize <= 4096)
4145 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
4146 else if (actual_fsize <= 8192)
4147 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4148 ret, actual_fsize - 4096);
4149 else if ((actual_fsize & 0x3ff) == 0)
4150 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4153 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4154 actual_fsize, actual_fsize, ret);
4157 sparc_output_deferred_case_vectors ();
4160 /* Output a sibling call. */
4163 output_sibcall (insn, call_operand)
4164 rtx insn, call_operand;
4166 int leaf_regs = current_function_uses_only_leaf_regs;
4168 int delay_slot = dbr_sequence_length () > 0;
4172 /* Call to restore global regs might clobber
4173 the delay slot. Instead of checking for this
4174 output the delay slot now. */
4177 rtx delay = NEXT_INSN (insn);
4182 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4183 PATTERN (delay) = gen_blockage ();
4184 INSN_CODE (delay) = -1;
4187 output_restore_regs (asm_out_file, leaf_regs);
4190 operands[0] = call_operand;
4194 #ifdef HAVE_AS_RELAX_OPTION
4195 /* If as and ld are relaxing tail call insns into branch always,
4196 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4197 be optimized. With sethi/jmpl as nor ld has no easy way how to
4198 find out if somebody does not branch between the sethi and jmpl. */
4201 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4205 if ((actual_fsize || ! spare_slot) && delay_slot)
4207 rtx delay = NEXT_INSN (insn);
4212 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4213 PATTERN (delay) = gen_blockage ();
4214 INSN_CODE (delay) = -1;
4219 if (actual_fsize <= 4096)
4220 size = actual_fsize;
4221 else if (actual_fsize <= 8192)
4223 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4224 size = actual_fsize - 4096;
4226 else if ((actual_fsize & 0x3ff) == 0)
4227 fprintf (asm_out_file,
4228 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4232 fprintf (asm_out_file,
4233 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4234 actual_fsize, actual_fsize);
4235 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4240 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4241 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4243 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size);
4244 else if (! delay_slot)
4245 fputs ("\t nop\n", asm_out_file);
4250 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size);
4251 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4252 it into branch if possible. */
4253 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4254 output_asm_insn ("call\t%a0, 0", operands);
4255 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4260 output_asm_insn ("call\t%a0, 0", operands);
4263 rtx delay = NEXT_INSN (insn), pat;
4268 pat = PATTERN (delay);
4269 if (GET_CODE (pat) != SET)
4272 operands[0] = SET_DEST (pat);
4273 pat = SET_SRC (pat);
4274 switch (GET_CODE (pat))
4277 operands[1] = XEXP (pat, 0);
4278 operands[2] = XEXP (pat, 1);
4279 output_asm_insn (" restore %r1, %2, %Y0", operands);
4282 operands[1] = XEXP (pat, 0);
4283 operands[2] = XEXP (pat, 1);
4284 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4287 operands[1] = XEXP (pat, 0);
4288 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4292 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4295 PATTERN (delay) = gen_blockage ();
4296 INSN_CODE (delay) = -1;
4299 fputs ("\t restore\n", asm_out_file);
4303 /* Functions for handling argument passing.
4305 For v8 the first six args are normally in registers and the rest are
4306 pushed. Any arg that starts within the first 6 words is at least
4307 partially passed in a register unless its data type forbids.
4309 For v9, the argument registers are laid out as an array of 16 elements
4310 and arguments are added sequentially. The first 6 int args and up to the
4311 first 16 fp args (depending on size) are passed in regs.
4313 Slot Stack Integral Float Float in structure Double Long Double
4314 ---- ----- -------- ----- ------------------ ------ -----------
4315 15 [SP+248] %f31 %f30,%f31 %d30
4316 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4317 13 [SP+232] %f27 %f26,%f27 %d26
4318 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4319 11 [SP+216] %f23 %f22,%f23 %d22
4320 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4321 9 [SP+200] %f19 %f18,%f19 %d18
4322 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4323 7 [SP+184] %f15 %f14,%f15 %d14
4324 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4325 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4326 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4327 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4328 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4329 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4330 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4332 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4334 Integral arguments are always passed as 64 bit quantities appropriately
4337 Passing of floating point values is handled as follows.
4338 If a prototype is in scope:
4339 If the value is in a named argument (i.e. not a stdarg function or a
4340 value not part of the `...') then the value is passed in the appropriate
4342 If the value is part of the `...' and is passed in one of the first 6
4343 slots then the value is passed in the appropriate int reg.
4344 If the value is part of the `...' and is not passed in one of the first 6
4345 slots then the value is passed in memory.
4346 If a prototype is not in scope:
4347 If the value is one of the first 6 arguments the value is passed in the
4348 appropriate integer reg and the appropriate fp reg.
4349 If the value is not one of the first 6 arguments the value is passed in
4350 the appropriate fp reg and in memory.
4353 /* Maximum number of int regs for args. */
4354 #define SPARC_INT_ARG_MAX 6
4355 /* Maximum number of fp regs for args. */
4356 #define SPARC_FP_ARG_MAX 16
4358 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4360 /* Handle the INIT_CUMULATIVE_ARGS macro.
4361 Initialize a variable CUM of type CUMULATIVE_ARGS
4362 for a call to a function whose data type is FNTYPE.
4363 For a library call, FNTYPE is 0. */
4366 init_cumulative_args (cum, fntype, libname, fndecl)
4367 CUMULATIVE_ARGS *cum;
4369 rtx libname ATTRIBUTE_UNUSED;
4370 tree fndecl ATTRIBUTE_UNUSED;
4373 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4374 cum->libcall_p = fntype == 0;
4377 /* Compute the slot number to pass an argument in.
4378 Returns the slot number or -1 if passing on the stack.
4380 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4381 the preceding args and about the function being called.
4382 MODE is the argument's machine mode.
4383 TYPE is the data type of the argument (as a tree).
4384 This is null for libcalls where that information may
4386 NAMED is nonzero if this argument is a named parameter
4387 (otherwise it is an extra parameter matching an ellipsis).
4388 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4389 *PREGNO records the register number to use if scalar type.
4390 *PPADDING records the amount of padding needed in words. */
4393 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
4394 const CUMULATIVE_ARGS *cum;
4395 enum machine_mode mode;
4402 int regbase = (incoming_p
4403 ? SPARC_INCOMING_INT_ARG_FIRST
4404 : SPARC_OUTGOING_INT_ARG_FIRST);
4405 int slotno = cum->words;
4410 if (type != 0 && TREE_ADDRESSABLE (type))
4413 && type != 0 && mode == BLKmode
4414 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4420 /* MODE is VOIDmode when generating the actual call.
4424 case QImode : case CQImode :
4425 case HImode : case CHImode :
4426 case SImode : case CSImode :
4427 case DImode : case CDImode :
4428 case TImode : case CTImode :
4429 if (slotno >= SPARC_INT_ARG_MAX)
4431 regno = regbase + slotno;
4434 case SFmode : case SCmode :
4435 case DFmode : case DCmode :
4436 case TFmode : case TCmode :
4439 if (slotno >= SPARC_INT_ARG_MAX)
4441 regno = regbase + slotno;
4445 if ((mode == TFmode || mode == TCmode)
4446 && (slotno & 1) != 0)
4447 slotno++, *ppadding = 1;
4448 if (TARGET_FPU && named)
4450 if (slotno >= SPARC_FP_ARG_MAX)
4452 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4458 if (slotno >= SPARC_INT_ARG_MAX)
4460 regno = regbase + slotno;
4466 /* For sparc64, objects requiring 16 byte alignment get it. */
4469 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
4470 slotno++, *ppadding = 1;
4474 || (type && TREE_CODE (type) == UNION_TYPE))
4476 if (slotno >= SPARC_INT_ARG_MAX)
4478 regno = regbase + slotno;
4483 int intregs_p = 0, fpregs_p = 0;
4484 /* The ABI obviously doesn't specify how packed
4485 structures are passed. These are defined to be passed
4486 in int regs if possible, otherwise memory. */
4489 /* First see what kinds of registers we need. */
4490 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4492 if (TREE_CODE (field) == FIELD_DECL)
4494 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4499 if (DECL_PACKED (field))
4503 if (packed_p || !named)
4504 fpregs_p = 0, intregs_p = 1;
4506 /* If all arg slots are filled, then must pass on stack. */
4507 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4509 /* If there are only int args and all int arg slots are filled,
4510 then must pass on stack. */
4511 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4513 /* Note that even if all int arg slots are filled, fp members may
4514 still be passed in regs if such regs are available.
4515 *PREGNO isn't set because there may be more than one, it's up
4516 to the caller to compute them. */
4529 /* Handle recursive register counting for structure field layout. */
4531 struct function_arg_record_value_parms
4534 int slotno, named, regbase;
4539 static void function_arg_record_value_3
4540 PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *));
4541 static void function_arg_record_value_2
4542 PARAMS ((tree, HOST_WIDE_INT,
4543 struct function_arg_record_value_parms *));
4544 static void function_arg_record_value_1
4545 PARAMS ((tree, HOST_WIDE_INT,
4546 struct function_arg_record_value_parms *));
4547 static rtx function_arg_record_value
4548 PARAMS ((tree, enum machine_mode, int, int, int));
4550 /* A subroutine of function_arg_record_value. Traverse the structure
4551 recusively and determine how many registers will be required. */
4554 function_arg_record_value_1 (type, startbitpos, parms)
4556 HOST_WIDE_INT startbitpos;
4557 struct function_arg_record_value_parms *parms;
4561 /* The ABI obviously doesn't specify how packed structures are
4562 passed. These are defined to be passed in int regs if possible,
4563 otherwise memory. */
4566 /* We need to compute how many registers are needed so we can
4567 allocate the PARALLEL but before we can do that we need to know
4568 whether there are any packed fields. If there are, int regs are
4569 used regardless of whether there are fp values present. */
4570 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4572 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4579 /* Compute how many registers we need. */
4580 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4582 if (TREE_CODE (field) == FIELD_DECL)
4584 HOST_WIDE_INT bitpos = startbitpos;
4586 if (DECL_SIZE (field) != 0
4587 && host_integerp (bit_position (field), 1))
4588 bitpos += int_bit_position (field);
4590 /* ??? FIXME: else assume zero offset. */
4592 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4593 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
4594 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4595 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4596 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4602 if (parms->intoffset != -1)
4604 int intslots, this_slotno;
4606 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
4608 this_slotno = parms->slotno + parms->intoffset
4611 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4612 intslots = MAX (intslots, 0);
4613 parms->nregs += intslots;
4614 parms->intoffset = -1;
4617 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4618 If it wasn't true we wouldn't be here. */
4620 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4625 if (parms->intoffset == -1)
4626 parms->intoffset = bitpos;
4632 /* A subroutine of function_arg_record_value. Assign the bits of the
4633 structure between parms->intoffset and bitpos to integer registers. */
4636 function_arg_record_value_3 (bitpos, parms)
4637 HOST_WIDE_INT bitpos;
4638 struct function_arg_record_value_parms *parms;
4640 enum machine_mode mode;
4642 unsigned int startbit, endbit;
4643 int this_slotno, intslots, intoffset;
4646 if (parms->intoffset == -1)
4649 intoffset = parms->intoffset;
4650 parms->intoffset = -1;
4652 startbit = intoffset & -BITS_PER_WORD;
4653 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4654 intslots = (endbit - startbit) / BITS_PER_WORD;
4655 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
4657 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4661 /* If this is the trailing part of a word, only load that much into
4662 the register. Otherwise load the whole register. Note that in
4663 the latter case we may pick up unwanted bits. It's not a problem
4664 at the moment but may wish to revisit. */
4666 if (intoffset % BITS_PER_WORD != 0)
4667 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4672 intoffset /= BITS_PER_UNIT;
4675 regno = parms->regbase + this_slotno;
4676 reg = gen_rtx_REG (mode, regno);
4677 XVECEXP (parms->ret, 0, parms->nregs)
4678 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4681 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4685 while (intslots > 0);
4688 /* A subroutine of function_arg_record_value. Traverse the structure
4689 recursively and assign bits to floating point registers. Track which
4690 bits in between need integer registers; invoke function_arg_record_value_3
4691 to make that happen. */
4694 function_arg_record_value_2 (type, startbitpos, parms)
4696 HOST_WIDE_INT startbitpos;
4697 struct function_arg_record_value_parms *parms;
4702 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4704 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4711 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4713 if (TREE_CODE (field) == FIELD_DECL)
4715 HOST_WIDE_INT bitpos = startbitpos;
4717 if (DECL_SIZE (field) != 0
4718 && host_integerp (bit_position (field), 1))
4719 bitpos += int_bit_position (field);
4721 /* ??? FIXME: else assume zero offset. */
4723 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4724 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
4725 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4726 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4727 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4733 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
4735 enum machine_mode mode = DECL_MODE (field);
4738 function_arg_record_value_3 (bitpos, parms);
4739 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
4740 + ((mode == SFmode || mode == SCmode)
4741 && (bitpos & 32) != 0);
4744 case SCmode: mode = SFmode; break;
4745 case DCmode: mode = DFmode; break;
4746 case TCmode: mode = TFmode; break;
4749 reg = gen_rtx_REG (mode, regno);
4750 XVECEXP (parms->ret, 0, parms->nregs)
4751 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4752 GEN_INT (bitpos / BITS_PER_UNIT));
4754 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4756 regno += GET_MODE_SIZE (mode) / 4;
4757 reg = gen_rtx_REG (mode, regno);
4758 XVECEXP (parms->ret, 0, parms->nregs)
4759 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4760 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
4767 if (parms->intoffset == -1)
4768 parms->intoffset = bitpos;
4774 /* Used by function_arg and function_value to implement the complex
4775 SPARC64 structure calling conventions. */
4778 function_arg_record_value (type, mode, slotno, named, regbase)
4780 enum machine_mode mode;
4781 int slotno, named, regbase;
4783 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4784 struct function_arg_record_value_parms parms;
4787 parms.ret = NULL_RTX;
4788 parms.slotno = slotno;
4789 parms.named = named;
4790 parms.regbase = regbase;
4792 /* Compute how many registers we need. */
4794 parms.intoffset = 0;
4795 function_arg_record_value_1 (type, 0, &parms);
4797 if (parms.intoffset != -1)
4799 unsigned int startbit, endbit;
4800 int intslots, this_slotno;
4802 startbit = parms.intoffset & -BITS_PER_WORD;
4803 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4804 intslots = (endbit - startbit) / BITS_PER_WORD;
4805 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
4807 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4808 intslots = MAX (intslots, 0);
4810 parms.nregs += intslots;
4812 nregs = parms.nregs;
4814 /* Allocate the vector and handle some annoying special cases. */
4817 /* ??? Empty structure has no value? Duh? */
4820 /* Though there's nothing really to store, return a word register
4821 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4822 leads to breakage due to the fact that there are zero bytes to
4824 return gen_rtx_REG (mode, regbase);
4828 /* ??? C++ has structures with no fields, and yet a size. Give up
4829 for now and pass everything back in integer registers. */
4830 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4832 if (nregs + slotno > SPARC_INT_ARG_MAX)
4833 nregs = SPARC_INT_ARG_MAX - slotno;
4838 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
4840 /* Fill in the entries. */
4842 parms.intoffset = 0;
4843 function_arg_record_value_2 (type, 0, &parms);
4844 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
4846 if (parms.nregs != nregs)
4852 /* Handle the FUNCTION_ARG macro.
4853 Determine where to put an argument to a function.
4854 Value is zero to push the argument on the stack,
4855 or a hard register in which to store the argument.
4857 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4858 the preceding args and about the function being called.
4859 MODE is the argument's machine mode.
4860 TYPE is the data type of the argument (as a tree).
4861 This is null for libcalls where that information may
4863 NAMED is nonzero if this argument is a named parameter
4864 (otherwise it is an extra parameter matching an ellipsis).
4865 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4868 function_arg (cum, mode, type, named, incoming_p)
4869 const CUMULATIVE_ARGS *cum;
4870 enum machine_mode mode;
4875 int regbase = (incoming_p
4876 ? SPARC_INCOMING_INT_ARG_FIRST
4877 : SPARC_OUTGOING_INT_ARG_FIRST);
4878 int slotno, regno, padding;
4881 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
4889 reg = gen_rtx_REG (mode, regno);
4893 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4894 but also have the slot allocated for them.
4895 If no prototype is in scope fp values in register slots get passed
4896 in two places, either fp regs and int regs or fp regs and memory. */
4897 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4898 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4899 && SPARC_FP_REG_P (regno))
4901 reg = gen_rtx_REG (mode, regno);
4902 if (cum->prototype_p || cum->libcall_p)
4904 /* "* 2" because fp reg numbers are recorded in 4 byte
4907 /* ??? This will cause the value to be passed in the fp reg and
4908 in the stack. When a prototype exists we want to pass the
4909 value in the reg but reserve space on the stack. That's an
4910 optimization, and is deferred [for a bit]. */
4911 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
4912 return gen_rtx_PARALLEL (mode,
4914 gen_rtx_EXPR_LIST (VOIDmode,
4915 NULL_RTX, const0_rtx),
4916 gen_rtx_EXPR_LIST (VOIDmode,
4920 /* ??? It seems that passing back a register even when past
4921 the area declared by REG_PARM_STACK_SPACE will allocate
4922 space appropriately, and will not copy the data onto the
4923 stack, exactly as we desire.
4925 This is due to locate_and_pad_parm being called in
4926 expand_call whenever reg_parm_stack_space > 0, which
4927 while benefical to our example here, would seem to be
4928 in error from what had been intended. Ho hum... -- r~ */
4936 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
4940 /* On incoming, we don't need to know that the value
4941 is passed in %f0 and %i0, and it confuses other parts
4942 causing needless spillage even on the simplest cases. */
4946 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
4947 + (regno - SPARC_FP_ARG_FIRST) / 2);
4949 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4950 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
4952 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4956 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4957 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4958 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4962 else if (type && TREE_CODE (type) == RECORD_TYPE)
4964 /* Structures up to 16 bytes in size are passed in arg slots on the
4965 stack and are promoted to registers where possible. */
4967 if (int_size_in_bytes (type) > 16)
4968 abort (); /* shouldn't get here */
4970 return function_arg_record_value (type, mode, slotno, named, regbase);
4972 else if (type && TREE_CODE (type) == UNION_TYPE)
4974 enum machine_mode mode;
4975 int bytes = int_size_in_bytes (type);
4980 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4981 reg = gen_rtx_REG (mode, regno);
4985 /* Scalar or complex int. */
4986 reg = gen_rtx_REG (mode, regno);
4992 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4993 For an arg passed partly in registers and partly in memory,
4994 this is the number of registers used.
4995 For args passed entirely in registers or entirely in memory, zero.
4997 Any arg that starts in the first 6 regs but won't entirely fit in them
4998 needs partial registers on v8. On v9, structures with integer
4999 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5000 values that begin in the last fp reg [where "last fp reg" varies with the
5001 mode] will be split between that reg and memory. */
5004 function_arg_partial_nregs (cum, mode, type, named)
5005 const CUMULATIVE_ARGS *cum;
5006 enum machine_mode mode;
5010 int slotno, regno, padding;
5012 /* We pass 0 for incoming_p here, it doesn't matter. */
5013 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5020 if ((slotno + (mode == BLKmode
5021 ? ROUND_ADVANCE (int_size_in_bytes (type))
5022 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5023 > NPARM_REGS (SImode))
5024 return NPARM_REGS (SImode) - slotno;
5029 if (type && AGGREGATE_TYPE_P (type))
5031 int size = int_size_in_bytes (type);
5032 int align = TYPE_ALIGN (type);
5035 slotno += slotno & 1;
5036 if (size > 8 && size <= 16
5037 && slotno == SPARC_INT_ARG_MAX - 1)
5040 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5041 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5044 if (GET_MODE_ALIGNMENT (mode) == 128)
5046 slotno += slotno & 1;
5047 if (slotno == SPARC_INT_ARG_MAX - 2)
5052 if (slotno == SPARC_INT_ARG_MAX - 1)
5056 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5058 if (GET_MODE_ALIGNMENT (mode) == 128)
5059 slotno += slotno & 1;
5060 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5068 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5069 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5070 quad-precision floats by invisible reference.
5071 v9: Aggregates greater than 16 bytes are passed by reference.
5072 For Pascal, also pass arrays by reference. */
5075 function_arg_pass_by_reference (cum, mode, type, named)
5076 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
5077 enum machine_mode mode;
5079 int named ATTRIBUTE_UNUSED;
5083 return ((type && AGGREGATE_TYPE_P (type))
5084 || mode == TFmode || mode == TCmode);
5088 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5089 /* Consider complex values as aggregates, so care for TCmode. */
5090 || GET_MODE_SIZE (mode) > 16
5092 && AGGREGATE_TYPE_P (type)
5093 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5097 /* Handle the FUNCTION_ARG_ADVANCE macro.
5098 Update the data in CUM to advance over an argument
5099 of mode MODE and data type TYPE.
5100 TYPE is null for libcalls where that information may not be available. */
5103 function_arg_advance (cum, mode, type, named)
5104 CUMULATIVE_ARGS *cum;
5105 enum machine_mode mode;
5109 int slotno, regno, padding;
5111 /* We pass 0 for incoming_p here, it doesn't matter. */
5112 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5114 /* If register required leading padding, add it. */
5116 cum->words += padding;
5120 cum->words += (mode != BLKmode
5121 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5122 : ROUND_ADVANCE (int_size_in_bytes (type)));
5126 if (type && AGGREGATE_TYPE_P (type))
5128 int size = int_size_in_bytes (type);
5132 else if (size <= 16)
5134 else /* passed by reference */
5137 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
5141 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5143 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
5147 cum->words += (mode != BLKmode
5148 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5149 : ROUND_ADVANCE (int_size_in_bytes (type)));
5154 /* Handle the FUNCTION_ARG_PADDING macro.
5155 For the 64 bit ABI structs are always stored left shifted in their
5159 function_arg_padding (mode, type)
5160 enum machine_mode mode;
5163 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5166 /* This is the default definition. */
5167 return (! BYTES_BIG_ENDIAN
5170 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5171 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
5172 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5173 ? downward : upward));
5176 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5177 For v9, function return values are subject to the same rules as arguments,
5178 except that up to 32-bytes may be returned in registers. */
5181 function_value (type, mode, incoming_p)
5183 enum machine_mode mode;
5187 int regbase = (incoming_p
5188 ? SPARC_OUTGOING_INT_ARG_FIRST
5189 : SPARC_INCOMING_INT_ARG_FIRST);
5191 if (TARGET_ARCH64 && type)
5193 if (TREE_CODE (type) == RECORD_TYPE)
5195 /* Structures up to 32 bytes in size are passed in registers,
5196 promoted to fp registers where possible. */
5198 if (int_size_in_bytes (type) > 32)
5199 abort (); /* shouldn't get here */
5201 return function_arg_record_value (type, mode, 0, 1, regbase);
5203 else if (AGGREGATE_TYPE_P (type))
5205 /* All other aggregate types are passed in an integer register
5206 in a mode corresponding to the size of the type. */
5207 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5212 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5217 && GET_MODE_CLASS (mode) == MODE_INT
5218 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5219 && type && ! AGGREGATE_TYPE_P (type))
5223 regno = BASE_RETURN_VALUE_REG (mode);
5225 regno = BASE_OUTGOING_VALUE_REG (mode);
5227 return gen_rtx_REG (mode, regno);
5230 /* Do what is necessary for `va_start'. We look at the current function
5231 to determine if stdarg or varargs is used and return the address of
5232 the first unnamed parameter. */
5235 sparc_builtin_saveregs ()
5237 int first_reg = current_function_args_info.words;
5241 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5242 emit_move_insn (gen_rtx_MEM (word_mode,
5243 gen_rtx_PLUS (Pmode,
5245 GEN_INT (FIRST_PARM_OFFSET (0)
5248 gen_rtx_REG (word_mode,
5249 BASE_INCOMING_ARG_REG (word_mode) + regno));
5251 address = gen_rtx_PLUS (Pmode,
5253 GEN_INT (FIRST_PARM_OFFSET (0)
5254 + UNITS_PER_WORD * first_reg));
5259 /* Implement `va_start' for varargs and stdarg. */
5262 sparc_va_start (valist, nextarg)
5266 nextarg = expand_builtin_saveregs ();
5267 std_expand_builtin_va_start (valist, nextarg);
5270 /* Implement `va_arg'. */
5273 sparc_va_arg (valist, type)
5276 HOST_WIDE_INT size, rsize, align;
5281 /* Round up sizeof(type) to a word. */
5282 size = int_size_in_bytes (type);
5283 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5288 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5289 align = 2 * UNITS_PER_WORD;
5291 if (AGGREGATE_TYPE_P (type))
5293 if ((unsigned HOST_WIDE_INT) size > 16)
5296 size = rsize = UNITS_PER_WORD;
5298 /* SPARC v9 ABI states that structures up to 8 bytes in size are
5299 given one 8 byte slot. */
5301 size = rsize = UNITS_PER_WORD;
5308 if (AGGREGATE_TYPE_P (type)
5309 || TYPE_MODE (type) == TFmode
5310 || TYPE_MODE (type) == TCmode)
5313 size = rsize = UNITS_PER_WORD;
5320 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5321 build_int_2 (align - 1, 0)));
5322 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5323 build_int_2 (-align, -1)));
5326 addr = incr = save_expr (incr);
5327 if (BYTES_BIG_ENDIAN && size < rsize)
5329 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5330 build_int_2 (rsize - size, 0)));
5332 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5333 build_int_2 (rsize, 0)));
5335 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5336 TREE_SIDE_EFFECTS (incr) = 1;
5337 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5339 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5341 /* If the address isn't aligned properly for the type,
5342 we may need to copy to a temporary.
5343 FIXME: This is inefficient. Usually we can do this
5346 && TYPE_ALIGN (type) > BITS_PER_WORD
5349 /* FIXME: We really need to specify that the temporary is live
5350 for the whole function because expand_builtin_va_arg wants
5351 the alias set to be get_varargs_alias_set (), but in this
5352 case the alias set is that for TYPE and if the memory gets
5353 reused it will be reused with alias set TYPE. */
5354 rtx tmp = assign_temp (type, 0, 1, 0);
5357 addr_rtx = force_reg (Pmode, addr_rtx);
5358 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5359 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5360 set_mem_align (addr_rtx, BITS_PER_WORD);
5361 tmp = shallow_copy_rtx (tmp);
5362 PUT_MODE (tmp, BLKmode);
5363 set_mem_alias_set (tmp, 0);
5365 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
5367 if (dest_addr != NULL_RTX)
5368 addr_rtx = dest_addr;
5370 addr_rtx = XCEXP (tmp, 0, MEM);
5375 addr_rtx = force_reg (Pmode, addr_rtx);
5376 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5377 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5383 /* Return the string to output a conditional branch to LABEL, which is
5384 the operand number of the label. OP is the conditional expression.
5385 XEXP (OP, 0) is assumed to be a condition code register (integer or
5386 floating point) and its mode specifies what kind of comparison we made.
5388 REVERSED is nonzero if we should reverse the sense of the comparison.
5390 ANNUL is nonzero if we should generate an annulling branch.
5392 NOOP is nonzero if we have to follow this branch by a noop.
5394 INSN, if set, is the insn. */
5397 output_cbranch (op, dest, label, reversed, annul, noop, insn)
5400 int reversed, annul, noop;
5403 static char string[50];
5404 enum rtx_code code = GET_CODE (op);
5405 rtx cc_reg = XEXP (op, 0);
5406 enum machine_mode mode = GET_MODE (cc_reg);
5407 const char *labelno, *branch;
5408 int spaces = 8, far;
5411 /* v9 branches are limited to +-1MB. If it is too far away,
5424 fbne,a,pn %fcc2, .LC29
5432 far = get_attr_length (insn) >= 3;
5435 /* Reversal of FP compares takes care -- an ordered compare
5436 becomes an unordered compare and vice versa. */
5437 if (mode == CCFPmode || mode == CCFPEmode)
5438 code = reverse_condition_maybe_unordered (code);
5440 code = reverse_condition (code);
5443 /* Start by writing the branch condition. */
5444 if (mode == CCFPmode || mode == CCFPEmode)
5495 /* ??? !v9: FP branches cannot be preceded by another floating point
5496 insn. Because there is currently no concept of pre-delay slots,
5497 we can fix this only by always emitting a nop before a floating
5502 strcpy (string, "nop\n\t");
5503 strcat (string, branch);
5516 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5528 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5549 strcpy (string, branch);
5551 spaces -= strlen (branch);
5552 p = strchr (string, '\0');
5554 /* Now add the annulling, the label, and a possible noop. */
5569 if (! far && insn && INSN_ADDRESSES_SET_P ())
5571 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5572 - INSN_ADDRESSES (INSN_UID (insn)));
5573 /* Leave some instructions for "slop". */
5574 if (delta < -260000 || delta >= 260000)
5578 if (mode == CCFPmode || mode == CCFPEmode)
5580 static char v9_fcc_labelno[] = "%%fccX, ";
5581 /* Set the char indicating the number of the fcc reg to use. */
5582 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5583 labelno = v9_fcc_labelno;
5586 if (REGNO (cc_reg) == SPARC_FCC_REG)
5592 else if (mode == CCXmode || mode == CCX_NOOVmode)
5594 labelno = "%%xcc, ";
5600 labelno = "%%icc, ";
5605 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5608 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5618 strcpy (p, labelno);
5619 p = strchr (p, '\0');
5622 strcpy (p, ".+12\n\tnop\n\tb\t");
5629 /* Set the char indicating the number of the operand containing the
5634 strcpy (p, "\n\tnop");
5639 /* Emit a library call comparison between floating point X and Y.
5640 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5641 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5642 values as arguments instead of the TFmode registers themselves,
5643 that's why we cannot call emit_float_lib_cmp. */
5645 sparc_emit_float_lib_cmp (x, y, comparison)
5647 enum rtx_code comparison;
5650 rtx slot0, slot1, result, tem, tem2;
5651 enum machine_mode mode;
5656 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
5660 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
5664 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
5668 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
5672 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
5676 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
5687 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
5697 if (GET_CODE (x) != MEM)
5699 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5700 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
5705 if (GET_CODE (y) != MEM)
5707 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5708 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
5713 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5715 XEXP (slot0, 0), Pmode,
5716 XEXP (slot1, 0), Pmode);
5722 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5724 x, TFmode, y, TFmode);
5730 /* Immediately move the result of the libcall into a pseudo
5731 register so reload doesn't clobber the value if it needs
5732 the return register for a spill reg. */
5733 result = gen_reg_rtx (mode);
5734 emit_move_insn (result, hard_libcall_value (mode));
5739 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
5743 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
5748 emit_cmp_insn (result, const1_rtx,
5749 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
5752 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
5755 tem = gen_reg_rtx (mode);
5757 emit_insn (gen_andsi3 (tem, result, const1_rtx));
5759 emit_insn (gen_anddi3 (tem, result, const1_rtx));
5760 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
5764 tem = gen_reg_rtx (mode);
5766 emit_insn (gen_addsi3 (tem, result, const1_rtx));
5768 emit_insn (gen_adddi3 (tem, result, const1_rtx));
5769 tem2 = gen_reg_rtx (mode);
5771 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
5773 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
5774 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
5780 /* Generate an unsigned DImode to FP conversion. This is the same code
5781 optabs would emit if we didn't have TFmode patterns. */
5784 sparc_emit_floatunsdi (operands)
5787 rtx neglab, donelab, i0, i1, f0, in, out;
5788 enum machine_mode mode;
5791 in = force_reg (DImode, operands[1]);
5792 mode = GET_MODE (out);
5793 neglab = gen_label_rtx ();
5794 donelab = gen_label_rtx ();
5795 i0 = gen_reg_rtx (DImode);
5796 i1 = gen_reg_rtx (DImode);
5797 f0 = gen_reg_rtx (mode);
5799 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
5801 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
5802 emit_jump_insn (gen_jump (donelab));
5805 emit_label (neglab);
5807 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
5808 emit_insn (gen_anddi3 (i1, in, const1_rtx));
5809 emit_insn (gen_iordi3 (i0, i0, i1));
5810 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
5811 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
5813 emit_label (donelab);
5816 /* Return the string to output a conditional branch to LABEL, testing
5817 register REG. LABEL is the operand number of the label; REG is the
5818 operand number of the reg. OP is the conditional expression. The mode
5819 of REG says what kind of comparison we made.
5821 REVERSED is nonzero if we should reverse the sense of the comparison.
5823 ANNUL is nonzero if we should generate an annulling branch.
5825 NOOP is nonzero if we have to follow this branch by a noop. */
5828 output_v9branch (op, dest, reg, label, reversed, annul, noop, insn)
5831 int reversed, annul, noop;
5834 static char string[50];
5835 enum rtx_code code = GET_CODE (op);
5836 enum machine_mode mode = GET_MODE (XEXP (op, 0));
5841 /* branch on register are limited to +-128KB. If it is too far away,
5854 brgez,a,pn %o1, .LC29
5860 ba,pt %xcc, .LC29 */
5862 far = get_attr_length (insn) >= 3;
5864 /* If not floating-point or if EQ or NE, we can just reverse the code. */
5866 code = reverse_condition (code);
5868 /* Only 64 bit versions of these instructions exist. */
5872 /* Start by writing the branch condition. */
5877 strcpy (string, "brnz");
5881 strcpy (string, "brz");
5885 strcpy (string, "brgez");
5889 strcpy (string, "brlz");
5893 strcpy (string, "brlez");
5897 strcpy (string, "brgz");
5904 p = strchr (string, '\0');
5906 /* Now add the annulling, reg, label, and nop. */
5913 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5916 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5921 *p = p < string + 8 ? '\t' : ' ';
5929 int veryfar = 1, delta;
5931 if (INSN_ADDRESSES_SET_P ())
5933 delta = (INSN_ADDRESSES (INSN_UID (dest))
5934 - INSN_ADDRESSES (INSN_UID (insn)));
5935 /* Leave some instructions for "slop". */
5936 if (delta >= -260000 && delta < 260000)
5940 strcpy (p, ".+12\n\tnop\n\t");
5951 strcpy (p, "ba,pt\t%%xcc, ");
5961 strcpy (p, "\n\tnop");
5966 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
5967 Such instructions cannot be used in the delay slot of return insn on v9.
5968 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
5972 epilogue_renumber (where, test)
5973 register rtx *where;
5976 register const char *fmt;
5978 register enum rtx_code code;
5983 code = GET_CODE (*where);
5988 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
5990 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
5991 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
5999 /* Do not replace the frame pointer with the stack pointer because
6000 it can cause the delayed instruction to load below the stack.
6001 This occurs when instructions like:
6003 (set (reg/i:SI 24 %i0)
6004 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6005 (const_int -20 [0xffffffec])) 0))
6007 are in the return delayed slot. */
6009 if (GET_CODE (XEXP (*where, 0)) == REG
6010 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6011 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6012 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6017 if (SPARC_STACK_BIAS
6018 && GET_CODE (XEXP (*where, 0)) == REG
6019 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6027 fmt = GET_RTX_FORMAT (code);
6029 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6034 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6035 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6038 else if (fmt[i] == 'e'
6039 && epilogue_renumber (&(XEXP (*where, i)), test))
6045 /* Leaf functions and non-leaf functions have different needs. */
6048 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6051 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6053 static const int *const reg_alloc_orders[] = {
6054 reg_leaf_alloc_order,
6055 reg_nonleaf_alloc_order};
6058 order_regs_for_local_alloc ()
6060 static int last_order_nonleaf = 1;
6062 if (regs_ever_live[15] != last_order_nonleaf)
6064 last_order_nonleaf = !last_order_nonleaf;
6065 memcpy ((char *) reg_alloc_order,
6066 (const char *) reg_alloc_orders[last_order_nonleaf],
6067 FIRST_PSEUDO_REGISTER * sizeof (int));
6071 /* Return 1 if REG and MEM are legitimate enough to allow the various
6072 mem<-->reg splits to be run. */
6075 sparc_splitdi_legitimate (reg, mem)
6079 /* Punt if we are here by mistake. */
6080 if (! reload_completed)
6083 /* We must have an offsettable memory reference. */
6084 if (! offsettable_memref_p (mem))
6087 /* If we have legitimate args for ldd/std, we do not want
6088 the split to happen. */
6089 if ((REGNO (reg) % 2) == 0
6090 && mem_min_alignment (mem, 8))
6097 /* Return 1 if x and y are some kind of REG and they refer to
6098 different hard registers. This test is guarenteed to be
6099 run after reload. */
6102 sparc_absnegfloat_split_legitimate (x, y)
6105 if (GET_CODE (x) != REG)
6107 if (GET_CODE (y) != REG)
6109 if (REGNO (x) == REGNO (y))
6114 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6115 This makes them candidates for using ldd and std insns.
6117 Note reg1 and reg2 *must* be hard registers. */
6120 registers_ok_for_ldd_peep (reg1, reg2)
6123 /* We might have been passed a SUBREG. */
6124 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6127 if (REGNO (reg1) % 2 != 0)
6130 /* Integer ldd is deprecated in SPARC V9 */
6131 if (TARGET_V9 && REGNO (reg1) < 32)
6134 return (REGNO (reg1) == REGNO (reg2) - 1);
6137 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6140 This can only happen when addr1 and addr2, the addresses in mem1
6141 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6142 addr1 must also be aligned on a 64-bit boundary.
6144 Also iff dependent_reg_rtx is not null it should not be used to
6145 compute the address for mem1, i.e. we cannot optimize a sequence
6157 But, note that the transformation from:
6162 is perfectly fine. Thus, the peephole2 patterns always pass us
6163 the destination register of the first load, never the second one.
6165 For stores we don't have a similar problem, so dependent_reg_rtx is
6169 mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx)
6170 rtx mem1, mem2, dependent_reg_rtx;
6176 /* The mems cannot be volatile. */
6177 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6180 /* MEM1 should be aligned on a 64-bit boundary. */
6181 if (MEM_ALIGN (mem1) < 64)
6184 addr1 = XEXP (mem1, 0);
6185 addr2 = XEXP (mem2, 0);
6187 /* Extract a register number and offset (if used) from the first addr. */
6188 if (GET_CODE (addr1) == PLUS)
6190 /* If not a REG, return zero. */
6191 if (GET_CODE (XEXP (addr1, 0)) != REG)
6195 reg1 = REGNO (XEXP (addr1, 0));
6196 /* The offset must be constant! */
6197 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6199 offset1 = INTVAL (XEXP (addr1, 1));
6202 else if (GET_CODE (addr1) != REG)
6206 reg1 = REGNO (addr1);
6207 /* This was a simple (mem (reg)) expression. Offset is 0. */
6211 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6212 if (GET_CODE (addr2) != PLUS)
6215 if (GET_CODE (XEXP (addr2, 0)) != REG
6216 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6219 if (reg1 != REGNO (XEXP (addr2, 0)))
6222 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6225 /* The first offset must be evenly divisible by 8 to ensure the
6226 address is 64 bit aligned. */
6227 if (offset1 % 8 != 0)
6230 /* The offset for the second addr must be 4 more than the first addr. */
6231 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6234 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6239 /* Return 1 if reg is a pseudo, or is the first register in
6240 a hard register pair. This makes it a candidate for use in
6241 ldd and std insns. */
6244 register_ok_for_ldd (reg)
6247 /* We might have been passed a SUBREG. */
6248 if (GET_CODE (reg) != REG)
6251 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6252 return (REGNO (reg) % 2 == 0);
6257 /* Print operand X (an rtx) in assembler syntax to file FILE.
6258 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6259 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6262 print_operand (file, x, code)
6270 /* Output a 'nop' if there's nothing for the delay slot. */
6271 if (dbr_sequence_length () == 0)
6272 fputs ("\n\t nop", file);
6275 /* Output an annul flag if there's nothing for the delay slot and we
6276 are optimizing. This is always used with '(' below. */
6277 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6278 this is a dbx bug. So, we only do this when optimizing. */
6279 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6280 Always emit a nop in case the next instruction is a branch. */
6281 if (dbr_sequence_length () == 0
6282 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6286 /* Output a 'nop' if there's nothing for the delay slot and we are
6287 not optimizing. This is always used with '*' above. */
6288 if (dbr_sequence_length () == 0
6289 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6290 fputs ("\n\t nop", file);
6293 /* Output the Embedded Medium/Anywhere code model base register. */
6294 fputs (EMBMEDANY_BASE_REG, file);
6297 /* Print out what we are using as the frame pointer. This might
6298 be %fp, or might be %sp+offset. */
6299 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6300 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
6303 /* Adjust the operand to take into account a RESTORE operation. */
6304 if (GET_CODE (x) == CONST_INT)
6306 else if (GET_CODE (x) != REG)
6307 output_operand_lossage ("invalid %%Y operand");
6308 else if (REGNO (x) < 8)
6309 fputs (reg_names[REGNO (x)], file);
6310 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6311 fputs (reg_names[REGNO (x)-16], file);
6313 output_operand_lossage ("invalid %%Y operand");
6316 /* Print out the low order register name of a register pair. */
6317 if (WORDS_BIG_ENDIAN)
6318 fputs (reg_names[REGNO (x)+1], file);
6320 fputs (reg_names[REGNO (x)], file);
6323 /* Print out the high order register name of a register pair. */
6324 if (WORDS_BIG_ENDIAN)
6325 fputs (reg_names[REGNO (x)], file);
6327 fputs (reg_names[REGNO (x)+1], file);
6330 /* Print out the second register name of a register pair or quad.
6331 I.e., R (%o0) => %o1. */
6332 fputs (reg_names[REGNO (x)+1], file);
6335 /* Print out the third register name of a register quad.
6336 I.e., S (%o0) => %o2. */
6337 fputs (reg_names[REGNO (x)+2], file);
6340 /* Print out the fourth register name of a register quad.
6341 I.e., T (%o0) => %o3. */
6342 fputs (reg_names[REGNO (x)+3], file);
6345 /* Print a condition code register. */
6346 if (REGNO (x) == SPARC_ICC_REG)
6348 /* We don't handle CC[X]_NOOVmode because they're not supposed
6350 if (GET_MODE (x) == CCmode)
6351 fputs ("%icc", file);
6352 else if (GET_MODE (x) == CCXmode)
6353 fputs ("%xcc", file);
6358 /* %fccN register */
6359 fputs (reg_names[REGNO (x)], file);
6362 /* Print the operand's address only. */
6363 output_address (XEXP (x, 0));
6366 /* In this case we need a register. Use %g0 if the
6367 operand is const0_rtx. */
6369 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
6371 fputs ("%g0", file);
6378 switch (GET_CODE (x))
6380 case IOR: fputs ("or", file); break;
6381 case AND: fputs ("and", file); break;
6382 case XOR: fputs ("xor", file); break;
6383 default: output_operand_lossage ("invalid %%A operand");
6388 switch (GET_CODE (x))
6390 case IOR: fputs ("orn", file); break;
6391 case AND: fputs ("andn", file); break;
6392 case XOR: fputs ("xnor", file); break;
6393 default: output_operand_lossage ("invalid %%B operand");
6397 /* These are used by the conditional move instructions. */
6401 enum rtx_code rc = GET_CODE (x);
6405 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6406 if (mode == CCFPmode || mode == CCFPEmode)
6407 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6409 rc = reverse_condition (GET_CODE (x));
6413 case NE: fputs ("ne", file); break;
6414 case EQ: fputs ("e", file); break;
6415 case GE: fputs ("ge", file); break;
6416 case GT: fputs ("g", file); break;
6417 case LE: fputs ("le", file); break;
6418 case LT: fputs ("l", file); break;
6419 case GEU: fputs ("geu", file); break;
6420 case GTU: fputs ("gu", file); break;
6421 case LEU: fputs ("leu", file); break;
6422 case LTU: fputs ("lu", file); break;
6423 case LTGT: fputs ("lg", file); break;
6424 case UNORDERED: fputs ("u", file); break;
6425 case ORDERED: fputs ("o", file); break;
6426 case UNLT: fputs ("ul", file); break;
6427 case UNLE: fputs ("ule", file); break;
6428 case UNGT: fputs ("ug", file); break;
6429 case UNGE: fputs ("uge", file); break;
6430 case UNEQ: fputs ("ue", file); break;
6431 default: output_operand_lossage (code == 'c'
6432 ? "invalid %%c operand"
6433 : "invalid %%C operand");
6438 /* These are used by the movr instruction pattern. */
6442 enum rtx_code rc = (code == 'd'
6443 ? reverse_condition (GET_CODE (x))
6447 case NE: fputs ("ne", file); break;
6448 case EQ: fputs ("e", file); break;
6449 case GE: fputs ("gez", file); break;
6450 case LT: fputs ("lz", file); break;
6451 case LE: fputs ("lez", file); break;
6452 case GT: fputs ("gz", file); break;
6453 default: output_operand_lossage (code == 'd'
6454 ? "invalid %%d operand"
6455 : "invalid %%D operand");
6462 /* Print a sign-extended character. */
6463 int i = trunc_int_for_mode (INTVAL (x), QImode);
6464 fprintf (file, "%d", i);
6469 /* Operand must be a MEM; write its address. */
6470 if (GET_CODE (x) != MEM)
6471 output_operand_lossage ("invalid %%f operand");
6472 output_address (XEXP (x, 0));
6476 /* Do nothing special. */
6480 /* Undocumented flag. */
6481 output_operand_lossage ("invalid operand output code");
6484 if (GET_CODE (x) == REG)
6485 fputs (reg_names[REGNO (x)], file);
6486 else if (GET_CODE (x) == MEM)
6489 /* Poor Sun assembler doesn't understand absolute addressing. */
6490 if (CONSTANT_P (XEXP (x, 0)))
6491 fputs ("%g0+", file);
6492 output_address (XEXP (x, 0));
6495 else if (GET_CODE (x) == HIGH)
6497 fputs ("%hi(", file);
6498 output_addr_const (file, XEXP (x, 0));
6501 else if (GET_CODE (x) == LO_SUM)
6503 print_operand (file, XEXP (x, 0), 0);
6504 if (TARGET_CM_MEDMID)
6505 fputs ("+%l44(", file);
6507 fputs ("+%lo(", file);
6508 output_addr_const (file, XEXP (x, 1));
6511 else if (GET_CODE (x) == CONST_DOUBLE
6512 && (GET_MODE (x) == VOIDmode
6513 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
6515 if (CONST_DOUBLE_HIGH (x) == 0)
6516 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
6517 else if (CONST_DOUBLE_HIGH (x) == -1
6518 && CONST_DOUBLE_LOW (x) < 0)
6519 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
6521 output_operand_lossage ("long long constant not a valid immediate operand");
6523 else if (GET_CODE (x) == CONST_DOUBLE)
6524 output_operand_lossage ("floating point constant not a valid immediate operand");
6525 else { output_addr_const (file, x); }
6528 /* Target hook for assembling integer objects. The sparc version has
6529 special handling for aligned DI-mode objects. */
6532 sparc_assemble_integer (x, size, aligned_p)
6537 /* ??? We only output .xword's for symbols and only then in environments
6538 where the assembler can handle them. */
6539 if (aligned_p && size == 8
6540 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
6544 assemble_integer_with_op ("\t.xword\t", x);
6549 assemble_aligned_integer (4, const0_rtx);
6550 assemble_aligned_integer (4, x);
6554 return default_assemble_integer (x, size, aligned_p);
6557 /* Return the value of a code used in the .proc pseudo-op that says
6558 what kind of result this function returns. For non-C types, we pick
6559 the closest C type. */
6561 #ifndef SHORT_TYPE_SIZE
6562 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6565 #ifndef INT_TYPE_SIZE
6566 #define INT_TYPE_SIZE BITS_PER_WORD
6569 #ifndef LONG_TYPE_SIZE
6570 #define LONG_TYPE_SIZE BITS_PER_WORD
6573 #ifndef LONG_LONG_TYPE_SIZE
6574 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6577 #ifndef FLOAT_TYPE_SIZE
6578 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6581 #ifndef DOUBLE_TYPE_SIZE
6582 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6585 #ifndef LONG_DOUBLE_TYPE_SIZE
6586 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6590 sparc_type_code (type)
6593 register unsigned long qualifiers = 0;
6594 register unsigned shift;
6596 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6597 setting more, since some assemblers will give an error for this. Also,
6598 we must be careful to avoid shifts of 32 bits or more to avoid getting
6599 unpredictable results. */
6601 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
6603 switch (TREE_CODE (type))
6609 qualifiers |= (3 << shift);
6614 qualifiers |= (2 << shift);
6618 case REFERENCE_TYPE:
6620 qualifiers |= (1 << shift);
6624 return (qualifiers | 8);
6627 case QUAL_UNION_TYPE:
6628 return (qualifiers | 9);
6631 return (qualifiers | 10);
6634 return (qualifiers | 16);
6637 /* If this is a range type, consider it to be the underlying
6639 if (TREE_TYPE (type) != 0)
6642 /* Carefully distinguish all the standard types of C,
6643 without messing up if the language is not C. We do this by
6644 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6645 look at both the names and the above fields, but that's redundant.
6646 Any type whose size is between two C types will be considered
6647 to be the wider of the two types. Also, we do not have a
6648 special code to use for "long long", so anything wider than
6649 long is treated the same. Note that we can't distinguish
6650 between "int" and "long" in this code if they are the same
6651 size, but that's fine, since neither can the assembler. */
6653 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
6654 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
6656 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
6657 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
6659 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
6660 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
6663 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
6666 /* If this is a range type, consider it to be the underlying
6668 if (TREE_TYPE (type) != 0)
6671 /* Carefully distinguish all the standard types of C,
6672 without messing up if the language is not C. */
6674 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
6675 return (qualifiers | 6);
6678 return (qualifiers | 7);
6680 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
6681 /* ??? We need to distinguish between double and float complex types,
6682 but I don't know how yet because I can't reach this code from
6683 existing front-ends. */
6684 return (qualifiers | 7); /* Who knows? */
6686 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
6687 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
6688 case FILE_TYPE: /* GNU Pascal FILE type. */
6689 case SET_TYPE: /* GNU Pascal SET type. */
6690 case LANG_TYPE: /* ? */
6694 abort (); /* Not a type! */
6701 /* Nested function support. */
6703 /* Emit RTL insns to initialize the variable parts of a trampoline.
6704 FNADDR is an RTX for the address of the function's pure code.
6705 CXT is an RTX for the static chain value for the function.
6707 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6708 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6709 (to store insns). This is a bit excessive. Perhaps a different
6710 mechanism would be better here.
6712 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6715 sparc_initialize_trampoline (tramp, fnaddr, cxt)
6716 rtx tramp, fnaddr, cxt;
6718 /* SPARC 32 bit trampoline:
6721 sethi %hi(static), %g2
6723 or %g2, %lo(static), %g2
6725 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6726 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6728 #ifdef TRANSFER_FROM_TRAMPOLINE
6729 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6730 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
6734 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
6735 expand_binop (SImode, ior_optab,
6736 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
6737 size_int (10), 0, 1),
6738 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
6739 NULL_RTX, 1, OPTAB_DIRECT));
6742 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6743 expand_binop (SImode, ior_optab,
6744 expand_shift (RSHIFT_EXPR, SImode, cxt,
6745 size_int (10), 0, 1),
6746 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
6747 NULL_RTX, 1, OPTAB_DIRECT));
6750 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6751 expand_binop (SImode, ior_optab,
6752 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
6753 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
6754 NULL_RTX, 1, OPTAB_DIRECT));
6757 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6758 expand_binop (SImode, ior_optab,
6759 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
6760 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
6761 NULL_RTX, 1, OPTAB_DIRECT));
6763 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6764 aligned on a 16 byte boundary so one flush clears it all. */
6765 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
6766 if (sparc_cpu != PROCESSOR_ULTRASPARC
6767 && sparc_cpu != PROCESSOR_ULTRASPARC3)
6768 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
6769 plus_constant (tramp, 8)))));
6772 /* The 64 bit version is simpler because it makes more sense to load the
6773 values as "immediate" data out of the trampoline. It's also easier since
6774 we can read the PC without clobbering a register. */
6777 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
6778 rtx tramp, fnaddr, cxt;
6780 #ifdef TRANSFER_FROM_TRAMPOLINE
6781 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6782 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
6793 emit_move_insn (gen_rtx_MEM (SImode, tramp),
6794 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
6795 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6796 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
6797 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6798 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
6799 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6800 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
6801 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
6802 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
6803 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
6805 if (sparc_cpu != PROCESSOR_ULTRASPARC
6806 && sparc_cpu != PROCESSOR_ULTRASPARC3)
6807 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
6810 /* Subroutines to support a flat (single) register window calling
6813 /* Single-register window sparc stack frames look like:
6815 Before call After call
6816 +-----------------------+ +-----------------------+
6818 mem | caller's temps. | | caller's temps. |
6820 +-----------------------+ +-----------------------+
6822 | arguments on stack. | | arguments on stack. |
6824 +-----------------------+FP+92->+-----------------------+
6825 | 6 words to save | | 6 words to save |
6826 | arguments passed | | arguments passed |
6827 | in registers, even | | in registers, even |
6828 | if not passed. | | if not passed. |
6829 SP+68->+-----------------------+FP+68->+-----------------------+
6830 | 1 word struct addr | | 1 word struct addr |
6831 +-----------------------+FP+64->+-----------------------+
6833 | 16 word reg save area | | 16 word reg save area |
6835 SP->+-----------------------+ FP->+-----------------------+
6837 | fp/alu reg moves |
6838 FP-16->+-----------------------+
6842 +-----------------------+
6844 | fp register save |
6846 +-----------------------+
6848 | gp register save |
6850 +-----------------------+
6852 | alloca allocations |
6854 +-----------------------+
6856 | arguments on stack |
6858 SP+92->+-----------------------+
6860 | arguments passed |
6861 | in registers, even |
6862 low | if not passed. |
6863 memory SP+68->+-----------------------+
6864 | 1 word struct addr |
6865 SP+64->+-----------------------+
6867 I 16 word reg save area |
6869 SP->+-----------------------+ */
6871 /* Structure to be filled in by sparc_flat_compute_frame_size with register
6872 save masks, and offsets for the current function. */
6874 struct sparc_frame_info
6876 unsigned long total_size; /* # bytes that the entire frame takes up. */
6877 unsigned long var_size; /* # bytes that variables take up. */
6878 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6879 unsigned long extra_size; /* # bytes of extra gunk. */
6880 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6881 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6882 unsigned long gmask; /* Mask of saved gp registers. */
6883 unsigned long fmask; /* Mask of saved fp registers. */
6884 unsigned long reg_offset; /* Offset from new sp to store regs. */
6885 int initialized; /* Nonzero if frame size already calculated. */
6888 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6889 struct sparc_frame_info current_frame_info;
6891 /* Zero structure to initialize current_frame_info. */
6892 struct sparc_frame_info zero_frame_info;
6894 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6896 #define RETURN_ADDR_REGNUM 15
6897 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
6898 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6900 #define MUST_SAVE_REGISTER(regno) \
6901 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6902 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
6903 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6905 /* Return the bytes needed to compute the frame pointer from the current
6909 sparc_flat_compute_frame_size (size)
6910 int size; /* # of var. bytes allocated. */
6913 unsigned long total_size; /* # bytes that the entire frame takes up. */
6914 unsigned long var_size; /* # bytes that variables take up. */
6915 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6916 unsigned long extra_size; /* # extra bytes. */
6917 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6918 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6919 unsigned long gmask; /* Mask of saved gp registers. */
6920 unsigned long fmask; /* Mask of saved fp registers. */
6921 unsigned long reg_offset; /* Offset to register save area. */
6922 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
6924 /* This is the size of the 16 word reg save area, 1 word struct addr
6925 area, and 4 word fp/alu register copy area. */
6926 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
6936 if (!leaf_function_p ())
6938 /* Also include the size needed for the 6 parameter registers. */
6939 args_size = current_function_outgoing_args_size + 24;
6941 total_size = var_size + args_size;
6943 /* Calculate space needed for gp registers. */
6944 for (regno = 1; regno <= 31; regno++)
6946 if (MUST_SAVE_REGISTER (regno))
6948 /* If we need to save two regs in a row, ensure there's room to bump
6949 up the address to align it to a doubleword boundary. */
6950 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
6952 if (gp_reg_size % 8 != 0)
6954 gp_reg_size += 2 * UNITS_PER_WORD;
6955 gmask |= 3 << regno;
6961 gp_reg_size += UNITS_PER_WORD;
6962 gmask |= 1 << regno;
6967 /* Calculate space needed for fp registers. */
6968 for (regno = 32; regno <= 63; regno++)
6970 if (regs_ever_live[regno] && !call_used_regs[regno])
6972 fp_reg_size += UNITS_PER_WORD;
6973 fmask |= 1 << (regno - 32);
6980 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
6981 /* Ensure save area is 8 byte aligned if we need it. */
6983 if (need_aligned_p && n != 0)
6985 total_size += 8 - n;
6986 reg_offset += 8 - n;
6988 total_size += gp_reg_size + fp_reg_size;
6991 /* If we must allocate a stack frame at all, we must also allocate
6992 room for register window spillage, so as to be binary compatible
6993 with libraries and operating systems that do not use -mflat. */
6995 total_size += extra_size;
6999 total_size = SPARC_STACK_ALIGN (total_size);
7001 /* Save other computed information. */
7002 current_frame_info.total_size = total_size;
7003 current_frame_info.var_size = var_size;
7004 current_frame_info.args_size = args_size;
7005 current_frame_info.extra_size = extra_size;
7006 current_frame_info.gp_reg_size = gp_reg_size;
7007 current_frame_info.fp_reg_size = fp_reg_size;
7008 current_frame_info.gmask = gmask;
7009 current_frame_info.fmask = fmask;
7010 current_frame_info.reg_offset = reg_offset;
7011 current_frame_info.initialized = reload_completed;
7013 /* Ok, we're done. */
7017 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7020 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7021 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7022 [BASE_REG+OFFSET] will always be a valid address.
7024 WORD_OP is either "st" for save, "ld" for restore.
7025 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7028 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
7029 doubleword_op, base_offset)
7031 const char *base_reg;
7032 unsigned int offset;
7033 unsigned long gmask;
7034 unsigned long fmask;
7035 const char *word_op;
7036 const char *doubleword_op;
7037 unsigned long base_offset;
7041 if (gmask == 0 && fmask == 0)
7044 /* Save registers starting from high to low. We've already saved the
7045 previous frame pointer and previous return address for the debugger's
7046 sake. The debugger allows us to not need a nop in the epilog if at least
7047 one register is reloaded in addition to return address. */
7051 for (regno = 1; regno <= 31; regno++)
7053 if ((gmask & (1L << regno)) != 0)
7055 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7057 /* We can save two registers in a row. If we're not at a
7058 double word boundary, move to one.
7059 sparc_flat_compute_frame_size ensures there's room to do
7061 if (offset % 8 != 0)
7062 offset += UNITS_PER_WORD;
7064 if (word_op[0] == 's')
7066 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7067 doubleword_op, reg_names[regno],
7069 if (dwarf2out_do_frame ())
7071 char *l = dwarf2out_cfi_label ();
7072 dwarf2out_reg_save (l, regno, offset + base_offset);
7074 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7078 fprintf (file, "\t%s\t[%s+%d], %s\n",
7079 doubleword_op, base_reg, offset,
7082 offset += 2 * UNITS_PER_WORD;
7087 if (word_op[0] == 's')
7089 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7090 word_op, reg_names[regno],
7092 if (dwarf2out_do_frame ())
7093 dwarf2out_reg_save ("", regno, offset + base_offset);
7096 fprintf (file, "\t%s\t[%s+%d], %s\n",
7097 word_op, base_reg, offset, reg_names[regno]);
7099 offset += UNITS_PER_WORD;
7107 for (regno = 32; regno <= 63; regno++)
7109 if ((fmask & (1L << (regno - 32))) != 0)
7111 if (word_op[0] == 's')
7113 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7114 word_op, reg_names[regno],
7116 if (dwarf2out_do_frame ())
7117 dwarf2out_reg_save ("", regno, offset + base_offset);
7120 fprintf (file, "\t%s\t[%s+%d], %s\n",
7121 word_op, base_reg, offset, reg_names[regno]);
7123 offset += UNITS_PER_WORD;
7129 /* Set up the stack and frame (if desired) for the function. */
7132 sparc_flat_function_prologue (file, size)
7136 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7137 unsigned long gmask = current_frame_info.gmask;
7139 sparc_output_scratch_registers (file);
7141 /* This is only for the human reader. */
7142 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7143 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7145 current_frame_info.var_size,
7146 current_frame_info.gp_reg_size / 4,
7147 current_frame_info.fp_reg_size / 4,
7148 current_function_outgoing_args_size,
7149 current_frame_info.extra_size);
7151 size = SPARC_STACK_ALIGN (size);
7152 size = (! current_frame_info.initialized
7153 ? sparc_flat_compute_frame_size (size)
7154 : current_frame_info.total_size);
7156 /* These cases shouldn't happen. Catch them now. */
7157 if (size == 0 && (gmask || current_frame_info.fmask))
7160 /* Allocate our stack frame by decrementing %sp.
7161 At present, the only algorithm gdb can use to determine if this is a
7162 flat frame is if we always set %i7 if we set %sp. This can be optimized
7163 in the future by putting in some sort of debugging information that says
7164 this is a `flat' function. However, there is still the case of debugging
7165 code without such debugging information (including cases where most fns
7166 have such info, but there is one that doesn't). So, always do this now
7167 so we don't get a lot of code out there that gdb can't handle.
7168 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7169 distinguish us from a non-flat function but there won't (and shouldn't)
7170 be any differences anyway. The return pc is saved (if necessary) right
7171 after %i7 so gdb won't have to look too far to find it. */
7174 unsigned int reg_offset = current_frame_info.reg_offset;
7175 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7176 static const char *const t1_str = "%g1";
7178 /* Things get a little tricky if local variables take up more than ~4096
7179 bytes and outgoing arguments take up more than ~4096 bytes. When that
7180 happens, the register save area can't be accessed from either end of
7181 the frame. Handle this by decrementing %sp to the start of the gp
7182 register save area, save the regs, update %i7, and then set %sp to its
7183 final value. Given that we only have one scratch register to play
7184 with it is the cheapest solution, and it helps gdb out as it won't
7185 slow down recognition of flat functions.
7186 Don't change the order of insns emitted here without checking with
7187 the gdb folk first. */
7189 /* Is the entire register save area offsettable from %sp? */
7190 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7194 fprintf (file, "\tadd\t%s, %d, %s\n",
7195 sp_str, (int) -size, sp_str);
7196 if (gmask & HARD_FRAME_POINTER_MASK)
7198 fprintf (file, "\tst\t%s, [%s+%d]\n",
7199 fp_str, sp_str, reg_offset);
7200 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7201 sp_str, (int) -size, fp_str, ASM_COMMENT_START);
7207 fprintf (file, "\tset\t");
7208 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7209 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7210 t1_str, sp_str, t1_str, sp_str);
7211 if (gmask & HARD_FRAME_POINTER_MASK)
7213 fprintf (file, "\tst\t%s, [%s+%d]\n",
7214 fp_str, sp_str, reg_offset);
7215 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7216 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7220 if (dwarf2out_do_frame ())
7222 char *l = dwarf2out_cfi_label ();
7223 if (gmask & HARD_FRAME_POINTER_MASK)
7225 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7226 reg_offset - 4 - size);
7227 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7230 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7232 if (gmask & RETURN_ADDR_MASK)
7234 fprintf (file, "\tst\t%s, [%s+%d]\n",
7235 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7236 if (dwarf2out_do_frame ())
7237 dwarf2out_return_save ("", reg_offset - size);
7240 sparc_flat_save_restore (file, sp_str, reg_offset,
7241 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7242 current_frame_info.fmask,
7243 "st", "std", -size);
7247 /* Subtract %sp in two steps, but make sure there is always a
7248 64 byte register save area, and %sp is properly aligned. */
7249 /* Amount to decrement %sp by, the first time. */
7250 unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7251 /* Offset to register save area from %sp. */
7252 unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset);
7256 fprintf (file, "\tadd\t%s, %d, %s\n",
7257 sp_str, (int) -size1, sp_str);
7258 if (gmask & HARD_FRAME_POINTER_MASK)
7260 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7261 fp_str, sp_str, (int) offset, sp_str, (int) -size1,
7262 fp_str, ASM_COMMENT_START);
7268 fprintf (file, "\tset\t");
7269 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1);
7270 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7271 t1_str, sp_str, t1_str, sp_str);
7272 if (gmask & HARD_FRAME_POINTER_MASK)
7274 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7275 fp_str, sp_str, (int) offset, sp_str, t1_str,
7276 fp_str, ASM_COMMENT_START);
7280 if (dwarf2out_do_frame ())
7282 char *l = dwarf2out_cfi_label ();
7283 if (gmask & HARD_FRAME_POINTER_MASK)
7285 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7286 offset - 4 - size1);
7287 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7290 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7292 if (gmask & RETURN_ADDR_MASK)
7294 fprintf (file, "\tst\t%s, [%s+%d]\n",
7295 reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset);
7296 if (dwarf2out_do_frame ())
7297 /* offset - size1 == reg_offset - size
7298 if reg_offset were updated above like offset. */
7299 dwarf2out_return_save ("", offset - size1);
7302 sparc_flat_save_restore (file, sp_str, offset,
7303 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7304 current_frame_info.fmask,
7305 "st", "std", -size1);
7306 fprintf (file, "\tset\t");
7307 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size - size1);
7308 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7309 t1_str, sp_str, t1_str, sp_str);
7310 if (dwarf2out_do_frame ())
7311 if (! (gmask & HARD_FRAME_POINTER_MASK))
7312 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
7316 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
7319 /* Do any necessary cleanup after a function to restore stack, frame,
7323 sparc_flat_function_epilogue (file, size)
7327 rtx epilogue_delay = current_function_epilogue_delay_list;
7328 int noepilogue = FALSE;
7330 /* This is only for the human reader. */
7331 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
7333 /* The epilogue does not depend on any registers, but the stack
7334 registers, so we assume that if we have 1 pending nop, it can be
7335 ignored, and 2 it must be filled (2 nops occur for integer
7336 multiply and divide). */
7338 size = SPARC_STACK_ALIGN (size);
7339 size = (!current_frame_info.initialized
7340 ? sparc_flat_compute_frame_size (size)
7341 : current_frame_info.total_size);
7343 if (size == 0 && epilogue_delay == 0)
7345 rtx insn = get_last_insn ();
7347 /* If the last insn was a BARRIER, we don't have to write any code
7348 because a jump (aka return) was put there. */
7349 if (GET_CODE (insn) == NOTE)
7350 insn = prev_nonnote_insn (insn);
7351 if (insn && GET_CODE (insn) == BARRIER)
7357 unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset;
7358 unsigned HOST_WIDE_INT size1;
7359 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7360 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7361 static const char *const t1_str = "%g1";
7363 /* In the reload sequence, we don't need to fill the load delay
7364 slots for most of the loads, also see if we can fill the final
7365 delay slot if not otherwise filled by the reload sequence. */
7369 fprintf (file, "\tset\t");
7370 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7371 fprintf (file, ", %s\n", t1_str);
7374 if (frame_pointer_needed)
7377 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7378 fp_str, t1_str, sp_str, ASM_COMMENT_START);
7380 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
7381 fp_str, (int) size, sp_str, ASM_COMMENT_START);
7384 /* Is the entire register save area offsettable from %sp? */
7385 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7391 /* Restore %sp in two steps, but make sure there is always a
7392 64 byte register save area, and %sp is properly aligned. */
7393 /* Amount to increment %sp by, the first time. */
7394 size1 = ((reg_offset - 64 - 16) + 15) & -16;
7395 /* Offset to register save area from %sp. */
7396 reg_offset = size1 - reg_offset;
7398 fprintf (file, "\tset\t");
7399 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1);
7400 fprintf (file, ", %s\n\tadd\t%s, %s, %s\n",
7401 t1_str, sp_str, t1_str, sp_str);
7404 /* We must restore the frame pointer and return address reg first
7405 because they are treated specially by the prologue output code. */
7406 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
7408 fprintf (file, "\tld\t[%s+%d], %s\n",
7409 sp_str, (int) reg_offset, fp_str);
7412 if (current_frame_info.gmask & RETURN_ADDR_MASK)
7414 fprintf (file, "\tld\t[%s+%d], %s\n",
7415 sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]);
7419 /* Restore any remaining saved registers. */
7420 sparc_flat_save_restore (file, sp_str, reg_offset,
7421 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7422 current_frame_info.fmask,
7425 /* If we had to increment %sp in two steps, record it so the second
7426 restoration in the epilogue finishes up. */
7432 fprintf (file, "\tset\t");
7433 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7434 fprintf (file, ", %s\n", t1_str);
7438 if (current_function_returns_struct)
7439 fprintf (file, "\tjmp\t%%o7+12\n");
7441 fprintf (file, "\tretl\n");
7443 /* If the only register saved is the return address, we need a
7444 nop, unless we have an instruction to put into it. Otherwise
7445 we don't since reloading multiple registers doesn't reference
7446 the register being loaded. */
7452 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
7455 else if (size > 4095)
7456 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7459 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str);
7462 fprintf (file, "\tnop\n");
7465 /* Reset state info for each function. */
7466 current_frame_info = zero_frame_info;
7468 sparc_output_deferred_case_vectors ();
7471 /* Define the number of delay slots needed for the function epilogue.
7473 On the sparc, we need a slot if either no stack has been allocated,
7474 or the only register saved is the return register. */
7477 sparc_flat_epilogue_delay_slots ()
7479 if (!current_frame_info.initialized)
7480 (void) sparc_flat_compute_frame_size (get_frame_size ());
7482 if (current_frame_info.total_size == 0)
7488 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7489 Any single length instruction which doesn't reference the stack or frame
7493 sparc_flat_eligible_for_epilogue_delay (trial, slot)
7495 int slot ATTRIBUTE_UNUSED;
7497 rtx pat = PATTERN (trial);
7499 if (get_attr_length (trial) != 1)
7502 if (! reg_mentioned_p (stack_pointer_rtx, pat)
7503 && ! reg_mentioned_p (frame_pointer_rtx, pat))
7509 /* Adjust the cost of a scheduling dependency. Return the new cost of
7510 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7513 supersparc_adjust_cost (insn, link, dep_insn, cost)
7519 enum attr_type insn_type;
7521 if (! recog_memoized (insn))
7524 insn_type = get_attr_type (insn);
7526 if (REG_NOTE_KIND (link) == 0)
7528 /* Data dependency; DEP_INSN writes a register that INSN reads some
7531 /* if a load, then the dependence must be on the memory address;
7532 add an extra "cycle". Note that the cost could be two cycles
7533 if the reg was written late in an instruction group; we ca not tell
7535 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7538 /* Get the delay only if the address of the store is the dependence. */
7539 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7541 rtx pat = PATTERN(insn);
7542 rtx dep_pat = PATTERN (dep_insn);
7544 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7545 return cost; /* This should not happen! */
7547 /* The dependency between the two instructions was on the data that
7548 is being stored. Assume that this implies that the address of the
7549 store is not dependent. */
7550 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7553 return cost + 3; /* An approximation. */
7556 /* A shift instruction cannot receive its data from an instruction
7557 in the same cycle; add a one cycle penalty. */
7558 if (insn_type == TYPE_SHIFT)
7559 return cost + 3; /* Split before cascade into shift. */
7563 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7564 INSN writes some cycles later. */
7566 /* These are only significant for the fpu unit; writing a fp reg before
7567 the fpu has finished with it stalls the processor. */
7569 /* Reusing an integer register causes no problems. */
7570 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7578 hypersparc_adjust_cost (insn, link, dep_insn, cost)
7584 enum attr_type insn_type, dep_type;
7585 rtx pat = PATTERN(insn);
7586 rtx dep_pat = PATTERN (dep_insn);
7588 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7591 insn_type = get_attr_type (insn);
7592 dep_type = get_attr_type (dep_insn);
7594 switch (REG_NOTE_KIND (link))
7597 /* Data dependency; DEP_INSN writes a register that INSN reads some
7604 /* Get the delay iff the address of the store is the dependence. */
7605 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7608 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7615 /* If a load, then the dependence must be on the memory address. If
7616 the addresses aren't equal, then it might be a false dependency */
7617 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7619 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7620 || GET_CODE (SET_DEST (dep_pat)) != MEM
7621 || GET_CODE (SET_SRC (pat)) != MEM
7622 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7623 XEXP (SET_SRC (pat), 0)))
7631 /* Compare to branch latency is 0. There is no benefit from
7632 separating compare and branch. */
7633 if (dep_type == TYPE_COMPARE)
7635 /* Floating point compare to branch latency is less than
7636 compare to conditional move. */
7637 if (dep_type == TYPE_FPCMP)
7646 /* Anti-dependencies only penalize the fpu unit. */
7647 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7659 sparc_adjust_cost(insn, link, dep, cost)
7667 case PROCESSOR_SUPERSPARC:
7668 cost = supersparc_adjust_cost (insn, link, dep, cost);
7670 case PROCESSOR_HYPERSPARC:
7671 case PROCESSOR_SPARCLITE86X:
7672 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7681 sparc_sched_init (dump, sched_verbose, max_ready)
7682 FILE *dump ATTRIBUTE_UNUSED;
7683 int sched_verbose ATTRIBUTE_UNUSED;
7684 int max_ready ATTRIBUTE_UNUSED;
7689 sparc_use_dfa_pipeline_interface ()
7691 if ((1 << sparc_cpu) &
7692 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
7693 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7694 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
7695 (1 << PROCESSOR_ULTRASPARC3)))
7701 sparc_use_sched_lookahead ()
7703 if (sparc_cpu == PROCESSOR_ULTRASPARC
7704 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7706 if ((1 << sparc_cpu) &
7707 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7708 (1 << PROCESSOR_SPARCLITE86X)))
7721 /* Assume V9 processors are capable of at least dual-issue. */
7723 case PROCESSOR_SUPERSPARC:
7725 case PROCESSOR_HYPERSPARC:
7726 case PROCESSOR_SPARCLITE86X:
7728 case PROCESSOR_ULTRASPARC:
7729 case PROCESSOR_ULTRASPARC3:
7738 register rtx pat = PATTERN (insn);
7740 switch (GET_CODE (SET_SRC (pat)))
7742 /* Load and some shift instructions zero extend. */
7745 /* sethi clears the high bits */
7747 /* LO_SUM is used with sethi. sethi cleared the high
7748 bits and the values used with lo_sum are positive */
7750 /* Store flag stores 0 or 1 */
7760 rtx op0 = XEXP (SET_SRC (pat), 0);
7761 rtx op1 = XEXP (SET_SRC (pat), 1);
7762 if (GET_CODE (op1) == CONST_INT)
7763 return INTVAL (op1) >= 0;
7764 if (GET_CODE (op0) != REG)
7766 if (sparc_check_64 (op0, insn) == 1)
7768 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7773 rtx op0 = XEXP (SET_SRC (pat), 0);
7774 rtx op1 = XEXP (SET_SRC (pat), 1);
7775 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7777 if (GET_CODE (op1) == CONST_INT)
7778 return INTVAL (op1) >= 0;
7779 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7782 return GET_MODE (SET_SRC (pat)) == SImode;
7783 /* Positive integers leave the high bits zero. */
7785 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7787 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7790 return - (GET_MODE (SET_SRC (pat)) == SImode);
7792 return sparc_check_64 (SET_SRC (pat), insn);
7798 /* We _ought_ to have only one kind per function, but... */
7799 static GTY(()) rtx sparc_addr_diff_list;
7800 static GTY(()) rtx sparc_addr_list;
7803 sparc_defer_case_vector (lab, vec, diff)
7807 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7809 sparc_addr_diff_list
7810 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7812 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7816 sparc_output_addr_vec (vec)
7819 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7820 int idx, vlen = XVECLEN (body, 0);
7822 #ifdef ASM_OUTPUT_ADDR_VEC_START
7823 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7826 #ifdef ASM_OUTPUT_CASE_LABEL
7827 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7830 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7833 for (idx = 0; idx < vlen; idx++)
7835 ASM_OUTPUT_ADDR_VEC_ELT
7836 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7839 #ifdef ASM_OUTPUT_ADDR_VEC_END
7840 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7845 sparc_output_addr_diff_vec (vec)
7848 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7849 rtx base = XEXP (XEXP (body, 0), 0);
7850 int idx, vlen = XVECLEN (body, 1);
7852 #ifdef ASM_OUTPUT_ADDR_VEC_START
7853 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7856 #ifdef ASM_OUTPUT_CASE_LABEL
7857 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7860 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7863 for (idx = 0; idx < vlen; idx++)
7865 ASM_OUTPUT_ADDR_DIFF_ELT
7868 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7869 CODE_LABEL_NUMBER (base));
7872 #ifdef ASM_OUTPUT_ADDR_VEC_END
7873 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7878 sparc_output_deferred_case_vectors ()
7883 if (sparc_addr_list == NULL_RTX
7884 && sparc_addr_diff_list == NULL_RTX)
7887 /* Align to cache line in the function's code section. */
7888 function_section (current_function_decl);
7890 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7892 ASM_OUTPUT_ALIGN (asm_out_file, align);
7894 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7895 sparc_output_addr_vec (XEXP (t, 0));
7896 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7897 sparc_output_addr_diff_vec (XEXP (t, 0));
7899 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7902 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7903 unknown. Return 1 if the high bits are zero, -1 if the register is
7906 sparc_check_64 (x, insn)
7909 /* If a register is set only once it is safe to ignore insns this
7910 code does not know how to handle. The loop will either recognize
7911 the single set and return the correct value or fail to recognize
7916 if (GET_CODE (x) != REG)
7919 if (GET_MODE (x) == DImode)
7920 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
7922 if (flag_expensive_optimizations
7923 && REG_N_SETS (REGNO (y)) == 1)
7929 insn = get_last_insn_anywhere ();
7934 while ((insn = PREV_INSN (insn)))
7936 switch (GET_CODE (insn))
7949 rtx pat = PATTERN (insn);
7950 if (GET_CODE (pat) != SET)
7952 if (rtx_equal_p (x, SET_DEST (pat)))
7953 return set_extends (insn);
7954 if (y && rtx_equal_p (y, SET_DEST (pat)))
7955 return set_extends (insn);
7956 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
7965 sparc_v8plus_shift (operands, insn, opcode)
7970 static char asm_code[60];
7972 if (GET_CODE (operands[3]) == SCRATCH)
7973 operands[3] = operands[0];
7974 if (GET_CODE (operands[1]) == CONST_INT)
7976 output_asm_insn ("mov\t%1, %3", operands);
7980 output_asm_insn ("sllx\t%H1, 32, %3", operands);
7981 if (sparc_check_64 (operands[1], insn) <= 0)
7982 output_asm_insn ("srl\t%L1, 0, %L1", operands);
7983 output_asm_insn ("or\t%L1, %3, %3", operands);
7986 strcpy(asm_code, opcode);
7987 if (which_alternative != 2)
7988 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7990 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7993 /* Output rtl to increment the profiler label LABELNO
7994 for profiling a function entry. */
7997 sparc_profile_hook (labelno)
8003 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8004 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8005 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8007 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8010 #ifdef OBJECT_FORMAT_ELF
8012 sparc_elf_asm_named_section (name, flags)
8016 if (flags & SECTION_MERGE)
8018 /* entsize cannot be expressed in this section attributes
8020 default_elf_asm_named_section (name, flags);
8024 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8026 if (!(flags & SECTION_DEBUG))
8027 fputs (",#alloc", asm_out_file);
8028 if (flags & SECTION_WRITE)
8029 fputs (",#write", asm_out_file);
8030 if (flags & SECTION_CODE)
8031 fputs (",#execinstr", asm_out_file);
8033 /* ??? Handle SECTION_BSS. */
8035 fputc ('\n', asm_out_file);
8037 #endif /* OBJECT_FORMAT_ELF */
8039 /* We do not allow sibling calls if -mflat, nor
8040 we do not allow indirect calls to be optimized into sibling calls.
8042 Also, on sparc 32-bit we cannot emit a sibling call when the
8043 current function returns a structure. This is because the "unimp
8044 after call" convention would cause the callee to return to the
8045 wrong place. The generic code already disallows cases where the
8046 function being called returns a structure.
8048 It may seem strange how this last case could occur. Usually there
8049 is code after the call which jumps to epilogue code which dumps the
8050 return value into the struct return area. That ought to invalidate
8051 the sibling call right? Well, in the c++ case we can end up passing
8052 the pointer to the struct return area to a constructor (which returns
8053 void) and then nothing else happens. Such a sibling call would look
8054 valid without the added check here. */
8056 sparc_function_ok_for_sibcall (decl, exp)
8058 tree exp ATTRIBUTE_UNUSED;
8062 && (TARGET_ARCH64 || ! current_function_returns_struct));
8065 /* ??? Similar to the standard section selection, but force reloc-y-ness
8066 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8067 pretending PIC always on), but that's what the old code did. */
8070 sparc_aout_select_section (t, reloc, align)
8073 unsigned HOST_WIDE_INT align;
8075 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
8078 /* Use text section for a constant unless we need more alignment than
8082 sparc_aout_select_rtx_section (mode, x, align)
8083 enum machine_mode mode;
8085 unsigned HOST_WIDE_INT align;
8087 if (align <= MAX_TEXT_ALIGN
8088 && ! (flag_pic && (symbolic_operand (x, mode)
8089 || SUNOS4_SHARED_LIBRARIES)))
8090 readonly_data_section ();
8096 sparc_extra_constraint_check (op, c, strict)
8104 && (c == 'T' || c == 'U'))
8110 return fp_sethi_p (op);
8113 return fp_mov_p (op);
8116 return fp_high_losum_p (op);
8120 || (GET_CODE (op) == REG
8121 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8122 || reg_renumber[REGNO (op)] >= 0)))
8123 return register_ok_for_ldd (op);
8135 /* Our memory extra constraints have to emulate the
8136 behavior of 'm' and 'o' in order for reload to work
8138 if (GET_CODE (op) == MEM)
8141 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8143 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8148 reload_ok_mem = (reload_in_progress
8149 && GET_CODE (op) == REG
8150 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8151 && reg_renumber [REGNO (op)] < 0);
8154 return reload_ok_mem;
8157 /* ??? This duplicates information provided to the compiler by the
8158 ??? scheduler description. Some day, teach genautomata to output
8159 ??? the latencies and then CSE will just use that. */
8162 sparc_rtx_costs (x, code, outer_code, total)
8164 int code, outer_code, *total;
8168 case PLUS: case MINUS: case ABS: case NEG:
8169 case FLOAT: case UNSIGNED_FLOAT:
8170 case FIX: case UNSIGNED_FIX:
8171 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8172 if (FLOAT_MODE_P (GET_MODE (x)))
8176 case PROCESSOR_ULTRASPARC:
8177 case PROCESSOR_ULTRASPARC3:
8178 *total = COSTS_N_INSNS (4);
8181 case PROCESSOR_SUPERSPARC:
8182 *total = COSTS_N_INSNS (3);
8185 case PROCESSOR_CYPRESS:
8186 *total = COSTS_N_INSNS (5);
8189 case PROCESSOR_HYPERSPARC:
8190 case PROCESSOR_SPARCLITE86X:
8192 *total = COSTS_N_INSNS (1);
8197 *total = COSTS_N_INSNS (1);
8203 case PROCESSOR_ULTRASPARC:
8204 if (GET_MODE (x) == SFmode)
8205 *total = COSTS_N_INSNS (13);
8207 *total = COSTS_N_INSNS (23);
8210 case PROCESSOR_ULTRASPARC3:
8211 if (GET_MODE (x) == SFmode)
8212 *total = COSTS_N_INSNS (20);
8214 *total = COSTS_N_INSNS (29);
8217 case PROCESSOR_SUPERSPARC:
8218 *total = COSTS_N_INSNS (12);
8221 case PROCESSOR_CYPRESS:
8222 *total = COSTS_N_INSNS (63);
8225 case PROCESSOR_HYPERSPARC:
8226 case PROCESSOR_SPARCLITE86X:
8227 *total = COSTS_N_INSNS (17);
8231 *total = COSTS_N_INSNS (30);
8236 if (FLOAT_MODE_P (GET_MODE (x)))
8240 case PROCESSOR_ULTRASPARC:
8241 case PROCESSOR_ULTRASPARC3:
8242 *total = COSTS_N_INSNS (1);
8245 case PROCESSOR_SUPERSPARC:
8246 *total = COSTS_N_INSNS (3);
8249 case PROCESSOR_CYPRESS:
8250 *total = COSTS_N_INSNS (5);
8253 case PROCESSOR_HYPERSPARC:
8254 case PROCESSOR_SPARCLITE86X:
8256 *total = COSTS_N_INSNS (1);
8261 /* ??? Maybe mark integer compares as zero cost on
8262 ??? all UltraSPARC processors because the result
8263 ??? can be bypassed to a branch in the same group. */
8265 *total = COSTS_N_INSNS (1);
8269 if (FLOAT_MODE_P (GET_MODE (x)))
8273 case PROCESSOR_ULTRASPARC:
8274 case PROCESSOR_ULTRASPARC3:
8275 *total = COSTS_N_INSNS (4);
8278 case PROCESSOR_SUPERSPARC:
8279 *total = COSTS_N_INSNS (3);
8282 case PROCESSOR_CYPRESS:
8283 *total = COSTS_N_INSNS (7);
8286 case PROCESSOR_HYPERSPARC:
8287 case PROCESSOR_SPARCLITE86X:
8288 *total = COSTS_N_INSNS (1);
8292 *total = COSTS_N_INSNS (5);
8297 /* The latency is actually variable for Ultra-I/II
8298 And if one of the inputs have a known constant
8299 value, we could calculate this precisely.
8301 However, for that to be useful we would need to
8302 add some machine description changes which would
8303 make sure small constants ended up in rs1 of the
8304 multiply instruction. This is because the multiply
8305 latency is determined by the number of clear (or
8306 set if the value is negative) bits starting from
8307 the most significant bit of the first input.
8309 The algorithm for computing num_cycles of a multiply
8313 highest_bit = highest_clear_bit(rs1);
8315 highest_bit = highest_set_bit(rs1);
8318 num_cycles = 4 + ((highest_bit - 3) / 2);
8320 If we did that we would have to also consider register
8321 allocation issues that would result from forcing such
8322 a value into a register.
8324 There are other similar tricks we could play if we
8325 knew, for example, that one input was an array index.
8327 Since we do not play any such tricks currently the
8328 safest thing to do is report the worst case latency. */
8329 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8331 *total = (GET_MODE (x) == DImode
8332 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8336 /* Multiply latency on Ultra-III, fortunately, is constant. */
8337 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8339 *total = COSTS_N_INSNS (6);
8343 if (sparc_cpu == PROCESSOR_HYPERSPARC
8344 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8346 *total = COSTS_N_INSNS (17);
8350 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
8357 if (FLOAT_MODE_P (GET_MODE (x)))
8361 case PROCESSOR_ULTRASPARC:
8362 if (GET_MODE (x) == SFmode)
8363 *total = COSTS_N_INSNS (13);
8365 *total = COSTS_N_INSNS (23);
8368 case PROCESSOR_ULTRASPARC3:
8369 if (GET_MODE (x) == SFmode)
8370 *total = COSTS_N_INSNS (17);
8372 *total = COSTS_N_INSNS (20);
8375 case PROCESSOR_SUPERSPARC:
8376 if (GET_MODE (x) == SFmode)
8377 *total = COSTS_N_INSNS (6);
8379 *total = COSTS_N_INSNS (9);
8382 case PROCESSOR_HYPERSPARC:
8383 case PROCESSOR_SPARCLITE86X:
8384 if (GET_MODE (x) == SFmode)
8385 *total = COSTS_N_INSNS (8);
8387 *total = COSTS_N_INSNS (12);
8391 *total = COSTS_N_INSNS (7);
8396 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8397 *total = (GET_MODE (x) == DImode
8398 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8399 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8400 *total = (GET_MODE (x) == DImode
8401 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8403 *total = COSTS_N_INSNS (25);
8407 /* Conditional moves. */
8410 case PROCESSOR_ULTRASPARC:
8411 *total = COSTS_N_INSNS (2);
8414 case PROCESSOR_ULTRASPARC3:
8415 if (FLOAT_MODE_P (GET_MODE (x)))
8416 *total = COSTS_N_INSNS (3);
8418 *total = COSTS_N_INSNS (2);
8422 *total = COSTS_N_INSNS (1);
8427 /* If outer-code is SIGN/ZERO extension we have to subtract
8428 out COSTS_N_INSNS (1) from whatever we return in determining
8432 case PROCESSOR_ULTRASPARC:
8433 if (outer_code == ZERO_EXTEND)
8434 *total = COSTS_N_INSNS (1);
8436 *total = COSTS_N_INSNS (2);
8439 case PROCESSOR_ULTRASPARC3:
8440 if (outer_code == ZERO_EXTEND)
8442 if (GET_MODE (x) == QImode
8443 || GET_MODE (x) == HImode
8444 || outer_code == SIGN_EXTEND)
8445 *total = COSTS_N_INSNS (2);
8447 *total = COSTS_N_INSNS (1);
8451 /* This handles sign extension (3 cycles)
8452 and everything else (2 cycles). */
8453 *total = COSTS_N_INSNS (2);
8457 case PROCESSOR_SUPERSPARC:
8458 if (FLOAT_MODE_P (GET_MODE (x))
8459 || outer_code == ZERO_EXTEND
8460 || outer_code == SIGN_EXTEND)
8461 *total = COSTS_N_INSNS (0);
8463 *total = COSTS_N_INSNS (1);
8466 case PROCESSOR_TSC701:
8467 if (outer_code == ZERO_EXTEND
8468 || outer_code == SIGN_EXTEND)
8469 *total = COSTS_N_INSNS (2);
8471 *total = COSTS_N_INSNS (3);
8474 case PROCESSOR_CYPRESS:
8475 if (outer_code == ZERO_EXTEND
8476 || outer_code == SIGN_EXTEND)
8477 *total = COSTS_N_INSNS (1);
8479 *total = COSTS_N_INSNS (2);
8482 case PROCESSOR_HYPERSPARC:
8483 case PROCESSOR_SPARCLITE86X:
8485 if (outer_code == ZERO_EXTEND
8486 || outer_code == SIGN_EXTEND)
8487 *total = COSTS_N_INSNS (0);
8489 *total = COSTS_N_INSNS (1);
8494 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8512 if (GET_MODE (x) == DImode
8513 && ((XINT (x, 3) == 0
8514 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8515 || (XINT (x, 3) == -1
8517 && XINT (x, 2) >= -0x1000)))
8528 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8529 Used for C++ multiple inheritance. */
8532 sparc_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
8534 tree thunk_fndecl ATTRIBUTE_UNUSED;
8535 HOST_WIDE_INT delta;
8536 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
8539 rtx this, insn, funexp, delta_rtx, tmp;
8541 reload_completed = 1;
8543 current_function_uses_only_leaf_regs = 1;
8545 emit_note (NULL, NOTE_INSN_PROLOGUE_END);
8547 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8548 returns a structure, the structure return pointer is there instead. */
8549 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
8550 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
8552 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
8554 /* Add DELTA. When possible use a plain add, otherwise load it into
8555 a register first. */
8556 delta_rtx = GEN_INT (delta);
8557 if (!SPARC_SIMM13_P (delta))
8559 rtx scratch = gen_rtx_REG (Pmode, 1);
8561 sparc_emit_set_const64 (scratch, delta_rtx);
8563 sparc_emit_set_const32 (scratch, delta_rtx);
8564 delta_rtx = scratch;
8567 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
8568 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
8570 /* Generate a tail call to the target function. */
8571 if (! TREE_USED (function))
8573 assemble_external (function);
8574 TREE_USED (function) = 1;
8576 funexp = XEXP (DECL_RTL (function), 0);
8577 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8578 insn = emit_call_insn (gen_sibcall (funexp));
8579 SIBLING_CALL_P (insn) = 1;
8582 /* Run just enough of rest_of_compilation to get the insns emitted.
8583 There's not really enough bulk here to make other passes such as
8584 instruction scheduling worth while. Note that use_thunk calls
8585 assemble_start_function and assemble_end_function. */
8586 insn = get_insns ();
8587 shorten_branches (insn);
8588 final_start_function (insn, file, 1);
8589 final (insn, file, 1, 0);
8590 final_end_function ();
8592 reload_completed = 0;
8596 #include "gt-sparc.h"