1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
50 #include "tree-gimple.h"
54 struct processor_costs cypress_costs = {
55 COSTS_N_INSNS (2), /* int load */
56 COSTS_N_INSNS (2), /* int signed load */
57 COSTS_N_INSNS (2), /* int zeroed load */
58 COSTS_N_INSNS (2), /* float load */
59 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
60 COSTS_N_INSNS (5), /* fadd, fsub */
61 COSTS_N_INSNS (1), /* fcmp */
62 COSTS_N_INSNS (1), /* fmov, fmovr */
63 COSTS_N_INSNS (7), /* fmul */
64 COSTS_N_INSNS (37), /* fdivs */
65 COSTS_N_INSNS (37), /* fdivd */
66 COSTS_N_INSNS (63), /* fsqrts */
67 COSTS_N_INSNS (63), /* fsqrtd */
68 COSTS_N_INSNS (1), /* imul */
69 COSTS_N_INSNS (1), /* imulX */
70 0, /* imul bit factor */
71 COSTS_N_INSNS (1), /* idiv */
72 COSTS_N_INSNS (1), /* idivX */
73 COSTS_N_INSNS (1), /* movcc/movr */
74 0, /* shift penalty */
78 struct processor_costs supersparc_costs = {
79 COSTS_N_INSNS (1), /* int load */
80 COSTS_N_INSNS (1), /* int signed load */
81 COSTS_N_INSNS (1), /* int zeroed load */
82 COSTS_N_INSNS (0), /* float load */
83 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
84 COSTS_N_INSNS (3), /* fadd, fsub */
85 COSTS_N_INSNS (3), /* fcmp */
86 COSTS_N_INSNS (1), /* fmov, fmovr */
87 COSTS_N_INSNS (3), /* fmul */
88 COSTS_N_INSNS (6), /* fdivs */
89 COSTS_N_INSNS (9), /* fdivd */
90 COSTS_N_INSNS (12), /* fsqrts */
91 COSTS_N_INSNS (12), /* fsqrtd */
92 COSTS_N_INSNS (4), /* imul */
93 COSTS_N_INSNS (4), /* imulX */
94 0, /* imul bit factor */
95 COSTS_N_INSNS (4), /* idiv */
96 COSTS_N_INSNS (4), /* idivX */
97 COSTS_N_INSNS (1), /* movcc/movr */
98 1, /* shift penalty */
102 struct processor_costs hypersparc_costs = {
103 COSTS_N_INSNS (1), /* int load */
104 COSTS_N_INSNS (1), /* int signed load */
105 COSTS_N_INSNS (1), /* int zeroed load */
106 COSTS_N_INSNS (1), /* float load */
107 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
108 COSTS_N_INSNS (1), /* fadd, fsub */
109 COSTS_N_INSNS (1), /* fcmp */
110 COSTS_N_INSNS (1), /* fmov, fmovr */
111 COSTS_N_INSNS (1), /* fmul */
112 COSTS_N_INSNS (8), /* fdivs */
113 COSTS_N_INSNS (12), /* fdivd */
114 COSTS_N_INSNS (17), /* fsqrts */
115 COSTS_N_INSNS (17), /* fsqrtd */
116 COSTS_N_INSNS (17), /* imul */
117 COSTS_N_INSNS (17), /* imulX */
118 0, /* imul bit factor */
119 COSTS_N_INSNS (17), /* idiv */
120 COSTS_N_INSNS (17), /* idivX */
121 COSTS_N_INSNS (1), /* movcc/movr */
122 0, /* shift penalty */
126 struct processor_costs sparclet_costs = {
127 COSTS_N_INSNS (3), /* int load */
128 COSTS_N_INSNS (3), /* int signed load */
129 COSTS_N_INSNS (1), /* int zeroed load */
130 COSTS_N_INSNS (1), /* float load */
131 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
132 COSTS_N_INSNS (1), /* fadd, fsub */
133 COSTS_N_INSNS (1), /* fcmp */
134 COSTS_N_INSNS (1), /* fmov, fmovr */
135 COSTS_N_INSNS (1), /* fmul */
136 COSTS_N_INSNS (1), /* fdivs */
137 COSTS_N_INSNS (1), /* fdivd */
138 COSTS_N_INSNS (1), /* fsqrts */
139 COSTS_N_INSNS (1), /* fsqrtd */
140 COSTS_N_INSNS (5), /* imul */
141 COSTS_N_INSNS (5), /* imulX */
142 0, /* imul bit factor */
143 COSTS_N_INSNS (5), /* idiv */
144 COSTS_N_INSNS (5), /* idivX */
145 COSTS_N_INSNS (1), /* movcc/movr */
146 0, /* shift penalty */
150 struct processor_costs ultrasparc_costs = {
151 COSTS_N_INSNS (2), /* int load */
152 COSTS_N_INSNS (3), /* int signed load */
153 COSTS_N_INSNS (2), /* int zeroed load */
154 COSTS_N_INSNS (2), /* float load */
155 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
156 COSTS_N_INSNS (4), /* fadd, fsub */
157 COSTS_N_INSNS (1), /* fcmp */
158 COSTS_N_INSNS (2), /* fmov, fmovr */
159 COSTS_N_INSNS (4), /* fmul */
160 COSTS_N_INSNS (13), /* fdivs */
161 COSTS_N_INSNS (23), /* fdivd */
162 COSTS_N_INSNS (13), /* fsqrts */
163 COSTS_N_INSNS (23), /* fsqrtd */
164 COSTS_N_INSNS (4), /* imul */
165 COSTS_N_INSNS (4), /* imulX */
166 2, /* imul bit factor */
167 COSTS_N_INSNS (37), /* idiv */
168 COSTS_N_INSNS (68), /* idivX */
169 COSTS_N_INSNS (2), /* movcc/movr */
170 2, /* shift penalty */
174 struct processor_costs ultrasparc3_costs = {
175 COSTS_N_INSNS (2), /* int load */
176 COSTS_N_INSNS (3), /* int signed load */
177 COSTS_N_INSNS (3), /* int zeroed load */
178 COSTS_N_INSNS (2), /* float load */
179 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
180 COSTS_N_INSNS (4), /* fadd, fsub */
181 COSTS_N_INSNS (5), /* fcmp */
182 COSTS_N_INSNS (3), /* fmov, fmovr */
183 COSTS_N_INSNS (4), /* fmul */
184 COSTS_N_INSNS (17), /* fdivs */
185 COSTS_N_INSNS (20), /* fdivd */
186 COSTS_N_INSNS (20), /* fsqrts */
187 COSTS_N_INSNS (29), /* fsqrtd */
188 COSTS_N_INSNS (6), /* imul */
189 COSTS_N_INSNS (6), /* imulX */
190 0, /* imul bit factor */
191 COSTS_N_INSNS (40), /* idiv */
192 COSTS_N_INSNS (71), /* idivX */
193 COSTS_N_INSNS (2), /* movcc/movr */
194 0, /* shift penalty */
197 const struct processor_costs *sparc_costs = &cypress_costs;
199 #ifdef HAVE_AS_RELAX_OPTION
200 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
201 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
202 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
203 somebody does not branch between the sethi and jmp. */
204 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
206 #define LEAF_SIBCALL_SLOT_RESERVED_P \
207 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
210 /* Global variables for machine-dependent things. */
212 /* Size of frame. Need to know this to emit return insns from leaf procedures.
213 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
214 reload pass. This is important as the value is later used for scheduling
215 (to see what can go in a delay slot).
216 APPARENT_FSIZE is the size of the stack less the register save area and less
217 the outgoing argument area. It is used when saving call preserved regs. */
218 static HOST_WIDE_INT apparent_fsize;
219 static HOST_WIDE_INT actual_fsize;
221 /* Number of live general or floating point registers needed to be
222 saved (as 4-byte quantities). */
223 static int num_gfregs;
225 /* The alias set for prologue/epilogue register save/restore. */
226 static GTY(()) int sparc_sr_alias_set;
228 /* Save the operands last given to a compare for use when we
229 generate a scc or bcc insn. */
230 rtx sparc_compare_op0, sparc_compare_op1;
232 /* Vector to say how input registers are mapped to output registers.
233 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
234 eliminate it. You must use -fomit-frame-pointer to get that. */
235 char leaf_reg_remap[] =
236 { 0, 1, 2, 3, 4, 5, 6, 7,
237 -1, -1, -1, -1, -1, -1, 14, -1,
238 -1, -1, -1, -1, -1, -1, -1, -1,
239 8, 9, 10, 11, 12, 13, -1, 15,
241 32, 33, 34, 35, 36, 37, 38, 39,
242 40, 41, 42, 43, 44, 45, 46, 47,
243 48, 49, 50, 51, 52, 53, 54, 55,
244 56, 57, 58, 59, 60, 61, 62, 63,
245 64, 65, 66, 67, 68, 69, 70, 71,
246 72, 73, 74, 75, 76, 77, 78, 79,
247 80, 81, 82, 83, 84, 85, 86, 87,
248 88, 89, 90, 91, 92, 93, 94, 95,
249 96, 97, 98, 99, 100};
251 /* Vector, indexed by hard register number, which contains 1
252 for a register that is allowable in a candidate for leaf
253 function treatment. */
254 char sparc_leaf_regs[] =
255 { 1, 1, 1, 1, 1, 1, 1, 1,
256 0, 0, 0, 0, 0, 0, 1, 0,
257 0, 0, 0, 0, 0, 0, 0, 0,
258 1, 1, 1, 1, 1, 1, 0, 1,
259 1, 1, 1, 1, 1, 1, 1, 1,
260 1, 1, 1, 1, 1, 1, 1, 1,
261 1, 1, 1, 1, 1, 1, 1, 1,
262 1, 1, 1, 1, 1, 1, 1, 1,
263 1, 1, 1, 1, 1, 1, 1, 1,
264 1, 1, 1, 1, 1, 1, 1, 1,
265 1, 1, 1, 1, 1, 1, 1, 1,
266 1, 1, 1, 1, 1, 1, 1, 1,
269 struct machine_function GTY(())
271 /* Some local-dynamic TLS symbol name. */
272 const char *some_ld_name;
275 /* Register we pretend to think the frame pointer is allocated to.
276 Normally, this is %fp, but if we are in a leaf procedure, this
277 is %sp+"something". We record "something" separately as it may
278 be too big for reg+constant addressing. */
280 static rtx frame_base_reg;
281 static HOST_WIDE_INT frame_base_offset;
283 static void sparc_init_modes (void);
284 static void scan_record_type (tree, int *, int *, int *);
285 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
286 tree, int, int, int *, int *);
288 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
289 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
291 static void sparc_output_addr_vec (rtx);
292 static void sparc_output_addr_diff_vec (rtx);
293 static void sparc_output_deferred_case_vectors (void);
294 static rtx sparc_builtin_saveregs (void);
295 static int epilogue_renumber (rtx *, int);
296 static bool sparc_assemble_integer (rtx, unsigned int, int);
297 static int set_extends (rtx);
298 static void load_pic_register (void);
299 static int save_or_restore_regs (int, int, rtx, int, int);
300 static void emit_save_regs (void);
301 static void emit_restore_regs (void);
302 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
303 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
304 #ifdef OBJECT_FORMAT_ELF
305 static void sparc_elf_asm_named_section (const char *, unsigned int);
308 static int sparc_adjust_cost (rtx, rtx, rtx, int);
309 static int sparc_issue_rate (void);
310 static void sparc_sched_init (FILE *, int, int);
311 static int sparc_use_sched_lookahead (void);
313 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
314 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
315 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
316 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
317 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
319 static bool sparc_function_ok_for_sibcall (tree, tree);
320 static void sparc_init_libfuncs (void);
321 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
322 HOST_WIDE_INT, tree);
323 static struct machine_function * sparc_init_machine_status (void);
324 static bool sparc_cannot_force_const_mem (rtx);
325 static rtx sparc_tls_get_addr (void);
326 static rtx sparc_tls_got (void);
327 static const char *get_some_local_dynamic_name (void);
328 static int get_some_local_dynamic_name_1 (rtx *, void *);
329 static bool sparc_rtx_costs (rtx, int, int, int *);
330 static bool sparc_promote_prototypes (tree);
331 static rtx sparc_struct_value_rtx (tree, int);
332 static bool sparc_return_in_memory (tree, tree);
333 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
334 static tree sparc_gimplify_va_arg (tree, tree, tree *, tree *);
336 /* Option handling. */
338 /* Code model option as passed by user. */
339 const char *sparc_cmodel_string;
341 enum cmodel sparc_cmodel;
343 char sparc_hard_reg_printed[8];
345 struct sparc_cpu_select sparc_select[] =
347 /* switch name, tune arch */
348 { (char *)0, "default", 1, 1 },
349 { (char *)0, "-mcpu=", 1, 1 },
350 { (char *)0, "-mtune=", 1, 0 },
354 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
355 enum processor_type sparc_cpu;
357 /* Initialize the GCC target structure. */
359 /* The sparc default is to use .half rather than .short for aligned
360 HI objects. Use .word instead of .long on non-ELF systems. */
361 #undef TARGET_ASM_ALIGNED_HI_OP
362 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
363 #ifndef OBJECT_FORMAT_ELF
364 #undef TARGET_ASM_ALIGNED_SI_OP
365 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
368 #undef TARGET_ASM_UNALIGNED_HI_OP
369 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
370 #undef TARGET_ASM_UNALIGNED_SI_OP
371 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
372 #undef TARGET_ASM_UNALIGNED_DI_OP
373 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
375 /* The target hook has to handle DI-mode values. */
376 #undef TARGET_ASM_INTEGER
377 #define TARGET_ASM_INTEGER sparc_assemble_integer
379 #undef TARGET_ASM_FUNCTION_PROLOGUE
380 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
381 #undef TARGET_ASM_FUNCTION_EPILOGUE
382 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
384 #undef TARGET_SCHED_ADJUST_COST
385 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
386 #undef TARGET_SCHED_ISSUE_RATE
387 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
388 #undef TARGET_SCHED_INIT
389 #define TARGET_SCHED_INIT sparc_sched_init
390 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
391 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
392 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
393 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
395 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
396 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
398 #undef TARGET_INIT_LIBFUNCS
399 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
402 #undef TARGET_HAVE_TLS
403 #define TARGET_HAVE_TLS true
405 #undef TARGET_CANNOT_FORCE_CONST_MEM
406 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
408 #undef TARGET_ASM_OUTPUT_MI_THUNK
409 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
410 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
411 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
413 #undef TARGET_RTX_COSTS
414 #define TARGET_RTX_COSTS sparc_rtx_costs
415 #undef TARGET_ADDRESS_COST
416 #define TARGET_ADDRESS_COST hook_int_rtx_0
418 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
419 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
420 test for this value. */
421 #undef TARGET_PROMOTE_FUNCTION_ARGS
422 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
424 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
425 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
426 test for this value. */
427 #undef TARGET_PROMOTE_FUNCTION_RETURN
428 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
430 #undef TARGET_PROMOTE_PROTOTYPES
431 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
433 #undef TARGET_STRUCT_VALUE_RTX
434 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
435 #undef TARGET_RETURN_IN_MEMORY
436 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
437 #undef TARGET_MUST_PASS_IN_STACK
438 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
440 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
441 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
442 #undef TARGET_STRICT_ARGUMENT_NAMING
443 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
445 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
446 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
448 #undef TARGET_LATE_RTL_PROLOGUE_EPILOGUE
449 #define TARGET_LATE_RTL_PROLOGUE_EPILOGUE true
451 struct gcc_target targetm = TARGET_INITIALIZER;
453 /* Validate and override various options, and do some machine dependent
457 sparc_override_options (void)
459 static struct code_model {
460 const char *const name;
462 } const cmodels[] = {
464 { "medlow", CM_MEDLOW },
465 { "medmid", CM_MEDMID },
466 { "medany", CM_MEDANY },
467 { "embmedany", CM_EMBMEDANY },
470 const struct code_model *cmodel;
471 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
472 static struct cpu_default {
474 const char *const name;
475 } const cpu_default[] = {
476 /* There must be one entry here for each TARGET_CPU value. */
477 { TARGET_CPU_sparc, "cypress" },
478 { TARGET_CPU_sparclet, "tsc701" },
479 { TARGET_CPU_sparclite, "f930" },
480 { TARGET_CPU_v8, "v8" },
481 { TARGET_CPU_hypersparc, "hypersparc" },
482 { TARGET_CPU_sparclite86x, "sparclite86x" },
483 { TARGET_CPU_supersparc, "supersparc" },
484 { TARGET_CPU_v9, "v9" },
485 { TARGET_CPU_ultrasparc, "ultrasparc" },
486 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
489 const struct cpu_default *def;
490 /* Table of values for -m{cpu,tune}=. */
491 static struct cpu_table {
492 const char *const name;
493 const enum processor_type processor;
496 } const cpu_table[] = {
497 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
498 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
499 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
500 /* TI TMS390Z55 supersparc */
501 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
502 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
503 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
504 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
505 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
506 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
507 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
508 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
510 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
512 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
513 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
514 /* TI ultrasparc I, II, IIi */
515 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
516 /* Although insns using %y are deprecated, it is a clear win on current
518 |MASK_DEPRECATED_V8_INSNS},
519 /* TI ultrasparc III */
520 /* ??? Check if %y issue still holds true in ultra3. */
521 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
524 const struct cpu_table *cpu;
525 const struct sparc_cpu_select *sel;
528 #ifndef SPARC_BI_ARCH
529 /* Check for unsupported architecture size. */
530 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
531 error ("%s is not supported by this configuration",
532 DEFAULT_ARCH32_P ? "-m64" : "-m32");
535 /* We force all 64bit archs to use 128 bit long double */
536 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
538 error ("-mlong-double-64 not allowed with -m64");
539 target_flags |= MASK_LONG_DOUBLE_128;
542 /* Code model selection. */
543 sparc_cmodel = SPARC_DEFAULT_CMODEL;
547 sparc_cmodel = CM_32;
550 if (sparc_cmodel_string != NULL)
554 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
555 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
557 if (cmodel->name == NULL)
558 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
560 sparc_cmodel = cmodel->value;
563 error ("-mcmodel= is not supported on 32 bit systems");
566 fpu = TARGET_FPU; /* save current -mfpu status */
568 /* Set the default CPU. */
569 for (def = &cpu_default[0]; def->name; ++def)
570 if (def->cpu == TARGET_CPU_DEFAULT)
574 sparc_select[0].string = def->name;
576 for (sel = &sparc_select[0]; sel->name; ++sel)
580 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
581 if (! strcmp (sel->string, cpu->name))
584 sparc_cpu = cpu->processor;
588 target_flags &= ~cpu->disable;
589 target_flags |= cpu->enable;
595 error ("bad value (%s) for %s switch", sel->string, sel->name);
599 /* If -mfpu or -mno-fpu was explicitly used, don't override with
600 the processor default. Clear MASK_FPU_SET to avoid confusing
601 the reverse mapping from switch values to names. */
604 target_flags = (target_flags & ~MASK_FPU) | fpu;
605 target_flags &= ~MASK_FPU_SET;
608 /* Don't allow -mvis if FPU is disabled. */
610 target_flags &= ~MASK_VIS;
612 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
614 -m64 also implies v9. */
615 if (TARGET_VIS || TARGET_ARCH64)
617 target_flags |= MASK_V9;
618 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
621 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
622 if (TARGET_V9 && TARGET_ARCH32)
623 target_flags |= MASK_DEPRECATED_V8_INSNS;
625 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
626 if (! TARGET_V9 || TARGET_ARCH64)
627 target_flags &= ~MASK_V8PLUS;
629 /* Don't use stack biasing in 32 bit mode. */
631 target_flags &= ~MASK_STACK_BIAS;
633 /* Supply a default value for align_functions. */
634 if (align_functions == 0
635 && (sparc_cpu == PROCESSOR_ULTRASPARC
636 || sparc_cpu == PROCESSOR_ULTRASPARC3))
637 align_functions = 32;
639 /* Validate PCC_STRUCT_RETURN. */
640 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
641 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
643 /* Only use .uaxword when compiling for a 64-bit target. */
645 targetm.asm_out.unaligned_op.di = NULL;
647 /* Do various machine dependent initializations. */
650 /* Acquire a unique set number for our register saves and restores. */
651 sparc_sr_alias_set = new_alias_set ();
653 /* Set up function hooks. */
654 init_machine_status = sparc_init_machine_status;
659 case PROCESSOR_CYPRESS:
660 sparc_costs = &cypress_costs;
663 case PROCESSOR_SPARCLITE:
664 case PROCESSOR_SUPERSPARC:
665 sparc_costs = &supersparc_costs;
669 case PROCESSOR_HYPERSPARC:
670 case PROCESSOR_SPARCLITE86X:
671 sparc_costs = &hypersparc_costs;
673 case PROCESSOR_SPARCLET:
674 case PROCESSOR_TSC701:
675 sparc_costs = &sparclet_costs;
678 case PROCESSOR_ULTRASPARC:
679 sparc_costs = &ultrasparc_costs;
681 case PROCESSOR_ULTRASPARC3:
682 sparc_costs = &ultrasparc3_costs;
687 /* Miscellaneous utilities. */
689 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
690 or branch on register contents instructions. */
693 v9_regcmp_p (enum rtx_code code)
695 return (code == EQ || code == NE || code == GE || code == LT
696 || code == LE || code == GT);
700 /* Operand constraints. */
702 /* Return nonzero only if OP is a register of mode MODE,
706 reg_or_0_operand (rtx op, enum machine_mode mode)
708 if (register_operand (op, mode))
710 if (op == const0_rtx)
712 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
713 && CONST_DOUBLE_HIGH (op) == 0
714 && CONST_DOUBLE_LOW (op) == 0)
716 if (fp_zero_operand (op, mode))
721 /* Return nonzero only if OP is const1_rtx. */
724 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
726 return op == const1_rtx;
729 /* Nonzero if OP is a floating point value with value 0.0. */
732 fp_zero_operand (rtx op, enum machine_mode mode)
734 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
736 return op == CONST0_RTX (mode);
739 /* Nonzero if OP is a register operand in floating point register. */
742 fp_register_operand (rtx op, enum machine_mode mode)
744 if (! register_operand (op, mode))
746 if (GET_CODE (op) == SUBREG)
747 op = SUBREG_REG (op);
748 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
751 /* Nonzero if OP is a floating point constant which can
752 be loaded into an integer register using a single
753 sethi instruction. */
758 if (GET_CODE (op) == CONST_DOUBLE)
763 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
764 if (REAL_VALUES_EQUAL (r, dconst0) &&
765 ! REAL_VALUE_MINUS_ZERO (r))
767 REAL_VALUE_TO_TARGET_SINGLE (r, i);
768 if (SPARC_SETHI_P (i))
775 /* Nonzero if OP is a floating point constant which can
776 be loaded into an integer register using a single
782 if (GET_CODE (op) == CONST_DOUBLE)
787 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
788 if (REAL_VALUES_EQUAL (r, dconst0) &&
789 ! REAL_VALUE_MINUS_ZERO (r))
791 REAL_VALUE_TO_TARGET_SINGLE (r, i);
792 if (SPARC_SIMM13_P (i))
799 /* Nonzero if OP is a floating point constant which can
800 be loaded into an integer register using a high/losum
801 instruction sequence. */
804 fp_high_losum_p (rtx op)
806 /* The constraints calling this should only be in
807 SFmode move insns, so any constant which cannot
808 be moved using a single insn will do. */
809 if (GET_CODE (op) == CONST_DOUBLE)
814 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
815 if (REAL_VALUES_EQUAL (r, dconst0) &&
816 ! REAL_VALUE_MINUS_ZERO (r))
818 REAL_VALUE_TO_TARGET_SINGLE (r, i);
819 if (! SPARC_SETHI_P (i)
820 && ! SPARC_SIMM13_P (i))
827 /* Nonzero if OP is an integer register. */
830 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
832 return (register_operand (op, SImode)
833 || (TARGET_ARCH64 && register_operand (op, DImode)));
836 /* Nonzero if OP is a floating point condition code register. */
839 fcc_reg_operand (rtx op, enum machine_mode mode)
841 /* This can happen when recog is called from combine. Op may be a MEM.
842 Fail instead of calling abort in this case. */
843 if (GET_CODE (op) != REG)
846 if (mode != VOIDmode && mode != GET_MODE (op))
849 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
852 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
853 if (reg_renumber == 0)
854 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
855 return REGNO_OK_FOR_CCFP_P (REGNO (op));
857 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
861 /* Nonzero if OP is a floating point condition code fcc0 register. */
864 fcc0_reg_operand (rtx op, enum machine_mode mode)
866 /* This can happen when recog is called from combine. Op may be a MEM.
867 Fail instead of calling abort in this case. */
868 if (GET_CODE (op) != REG)
871 if (mode != VOIDmode && mode != GET_MODE (op))
874 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
877 return REGNO (op) == SPARC_FCC_REG;
880 /* Nonzero if OP is an integer or floating point condition code register. */
883 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
885 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
887 if (mode != VOIDmode && mode != GET_MODE (op))
890 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
895 return fcc_reg_operand (op, mode);
898 /* Call insn on SPARC can take a PC-relative constant address, or any regular
902 call_operand (rtx op, enum machine_mode mode)
904 if (GET_CODE (op) != MEM)
907 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
911 call_operand_address (rtx op, enum machine_mode mode)
913 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
916 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
917 otherwise return 0. */
920 tls_symbolic_operand (rtx op)
922 if (GET_CODE (op) != SYMBOL_REF)
924 return SYMBOL_REF_TLS_MODEL (op);
928 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
930 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
934 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
936 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
940 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
942 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
946 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
948 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
951 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
952 reference and a constant. */
955 symbolic_operand (register rtx op, enum machine_mode mode)
957 enum machine_mode omode = GET_MODE (op);
959 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
962 switch (GET_CODE (op))
965 return !SYMBOL_REF_TLS_MODEL (op);
972 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
973 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
974 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
975 && GET_CODE (XEXP (op, 1)) == CONST_INT);
982 /* Return truth value of statement that OP is a symbolic memory
983 operand of mode MODE. */
986 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
988 if (GET_CODE (op) == SUBREG)
989 op = SUBREG_REG (op);
990 if (GET_CODE (op) != MEM)
993 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
994 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
995 || GET_CODE (op) == LABEL_REF);
998 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
1001 label_ref_operand (rtx op, enum machine_mode mode)
1003 if (GET_CODE (op) != LABEL_REF)
1005 if (GET_MODE (op) != mode)
1010 /* Return 1 if the operand is an argument used in generating pic references
1011 in either the medium/low or medium/anywhere code models of sparc64. */
1014 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1016 /* Check for (const (minus (symbol_ref:GOT)
1017 (const (minus (label) (pc))))). */
1018 if (GET_CODE (op) != CONST)
1021 if (GET_CODE (op) != MINUS)
1023 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
1025 /* ??? Ensure symbol is GOT. */
1026 if (GET_CODE (XEXP (op, 1)) != CONST)
1028 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
1033 /* Return 1 if the operand is a data segment reference. This includes
1034 the readonly data segment, or in other words anything but the text segment.
1035 This is needed in the medium/anywhere code model on v9. These values
1036 are accessed with EMBMEDANY_BASE_REG. */
1039 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1041 switch (GET_CODE (op))
1044 return ! SYMBOL_REF_FUNCTION_P (op);
1046 /* Assume canonical format of symbol + constant.
1049 return data_segment_operand (XEXP (op, 0), VOIDmode);
1055 /* Return 1 if the operand is a text segment reference.
1056 This is needed in the medium/anywhere code model on v9. */
1059 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1061 switch (GET_CODE (op))
1066 return SYMBOL_REF_FUNCTION_P (op);
1068 /* Assume canonical format of symbol + constant.
1071 return text_segment_operand (XEXP (op, 0), VOIDmode);
1077 /* Return 1 if the operand is either a register or a memory operand that is
1081 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
1083 if (register_operand (op, mode))
1086 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
1093 splittable_symbolic_memory_operand (rtx op,
1094 enum machine_mode mode ATTRIBUTE_UNUSED)
1096 if (GET_CODE (op) != MEM)
1098 if (! symbolic_operand (XEXP (op, 0), Pmode))
1104 splittable_immediate_memory_operand (rtx op,
1105 enum machine_mode mode ATTRIBUTE_UNUSED)
1107 if (GET_CODE (op) != MEM)
1109 if (! immediate_operand (XEXP (op, 0), Pmode))
1114 /* Return truth value of whether OP is EQ or NE. */
1117 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1119 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
1122 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
1123 or LTU for non-floating-point. We handle those specially. */
1126 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1130 if (!COMPARISON_P (op))
1133 if (GET_MODE (XEXP (op, 0)) == CCFPmode
1134 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
1137 code = GET_CODE (op);
1138 return (code != NE && code != EQ && code != GEU && code != LTU);
1141 /* Return 1 if this is a comparison operator. This allows the use of
1142 MATCH_OPERATOR to recognize all the branch insns. */
1145 noov_compare_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1149 if (!COMPARISON_P (op))
1152 code = GET_CODE (op);
1153 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
1154 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1155 /* These are the only branches which work with CC_NOOVmode. */
1156 return (code == EQ || code == NE || code == GE || code == LT);
1160 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
1161 MATCH_OPERATOR to recognize all the branch insns. */
1164 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1171 if (!COMPARISON_P (op))
1174 code = GET_CODE (op);
1175 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1176 /* These are the only branches which work with CCX_NOOVmode. */
1177 return (code == EQ || code == NE || code == GE || code == LT);
1178 return (GET_MODE (XEXP (op, 0)) == CCXmode);
1181 /* Nonzero if OP is a comparison operator suitable for use in v9
1182 conditional move or branch on register contents instructions. */
1185 v9_regcmp_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1189 if (!COMPARISON_P (op))
1192 code = GET_CODE (op);
1193 return v9_regcmp_p (code);
1196 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1199 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1201 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1204 /* Return nonzero if OP is an operator of mode MODE which can set
1205 the condition codes explicitly. We do not include PLUS and MINUS
1206 because these require CC_NOOVmode, which we handle explicitly. */
1209 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1211 if (GET_CODE (op) == AND
1212 || GET_CODE (op) == IOR
1213 || GET_CODE (op) == XOR)
1219 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1220 complement its second operand and set the condition codes explicitly. */
1223 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1225 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1226 and (xor ... (not ...)) to (not (xor ...)). */
1227 return (GET_CODE (op) == AND
1228 || GET_CODE (op) == IOR);
1231 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1232 signed 13 bit immediate field. This is an acceptable SImode operand for
1233 most 3 address instructions. */
1236 arith_operand (rtx op, enum machine_mode mode)
1238 if (register_operand (op, mode))
1240 if (GET_CODE (op) != CONST_INT)
1242 return SMALL_INT32 (op);
1245 /* Return true if OP is a constant 4096 */
1248 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1250 if (GET_CODE (op) != CONST_INT)
1253 return INTVAL (op) == 4096;
1256 /* Return true if OP is suitable as second operand for add/sub */
1259 arith_add_operand (rtx op, enum machine_mode mode)
1261 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1264 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1265 immediate field of OR and XOR instructions. Used for 64-bit
1266 constant formation patterns. */
1268 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1270 return ((GET_CODE (op) == CONST_INT
1271 && SPARC_SIMM13_P (INTVAL (op)))
1272 #if HOST_BITS_PER_WIDE_INT != 64
1273 || (GET_CODE (op) == CONST_DOUBLE
1274 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1275 && (CONST_DOUBLE_HIGH (op) ==
1276 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1277 (HOST_WIDE_INT)-1 : 0)))
1282 /* The same, but only for sethi instructions. */
1284 const64_high_operand (rtx op, enum machine_mode mode)
1286 return ((GET_CODE (op) == CONST_INT
1287 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1288 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1290 || (GET_CODE (op) == CONST_DOUBLE
1291 && CONST_DOUBLE_HIGH (op) == 0
1292 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1293 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1296 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1297 signed 11 bit immediate field. This is an acceptable SImode operand for
1298 the movcc instructions. */
1301 arith11_operand (rtx op, enum machine_mode mode)
1303 return (register_operand (op, mode)
1304 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1307 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1308 signed 10 bit immediate field. This is an acceptable SImode operand for
1309 the movrcc instructions. */
1312 arith10_operand (rtx op, enum machine_mode mode)
1314 return (register_operand (op, mode)
1315 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1318 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1319 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1321 ARCH64: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1322 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1323 for most 3 address instructions. */
1326 arith_double_operand (rtx op, enum machine_mode mode)
1328 return (register_operand (op, mode)
1329 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1331 && GET_CODE (op) == CONST_DOUBLE
1332 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1333 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1335 && GET_CODE (op) == CONST_DOUBLE
1336 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1337 && ((CONST_DOUBLE_HIGH (op) == -1
1338 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1339 || (CONST_DOUBLE_HIGH (op) == 0
1340 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1343 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1346 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1348 return (TARGET_ARCH64 &&
1349 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1350 (GET_CODE (op) == CONST_DOUBLE &&
1351 CONST_DOUBLE_LOW (op) == 4096 &&
1352 CONST_DOUBLE_HIGH (op) == 0)));
1355 /* Return true if OP is suitable as second operand for add/sub in DImode */
1358 arith_double_add_operand (rtx op, enum machine_mode mode)
1360 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1363 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1364 can fit in an 11 bit immediate field. This is an acceptable DImode
1365 operand for the movcc instructions. */
1366 /* ??? Replace with arith11_operand? */
1369 arith11_double_operand (rtx op, enum machine_mode mode)
1371 return (register_operand (op, mode)
1372 || (GET_CODE (op) == CONST_DOUBLE
1373 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1374 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1375 && ((CONST_DOUBLE_HIGH (op) == -1
1376 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1377 || (CONST_DOUBLE_HIGH (op) == 0
1378 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1379 || (GET_CODE (op) == CONST_INT
1380 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1381 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1384 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1385 can fit in an 10 bit immediate field. This is an acceptable DImode
1386 operand for the movrcc instructions. */
1387 /* ??? Replace with arith10_operand? */
1390 arith10_double_operand (rtx op, enum machine_mode mode)
1392 return (register_operand (op, mode)
1393 || (GET_CODE (op) == CONST_DOUBLE
1394 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1395 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1396 && ((CONST_DOUBLE_HIGH (op) == -1
1397 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1398 || (CONST_DOUBLE_HIGH (op) == 0
1399 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1400 || (GET_CODE (op) == CONST_INT
1401 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1402 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1405 /* Return truth value of whether OP is an integer which fits the
1406 range constraining immediate operands in most three-address insns,
1407 which have a 13 bit immediate field. */
1410 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1412 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1416 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1418 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1419 || (GET_CODE (op) == CONST_DOUBLE
1420 && CONST_DOUBLE_HIGH (op) == 0
1421 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1424 /* Recognize operand values for the umul instruction. That instruction sign
1425 extends immediate values just like all other sparc instructions, but
1426 interprets the extended result as an unsigned number. */
1429 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1431 #if HOST_BITS_PER_WIDE_INT > 32
1432 /* All allowed constants will fit a CONST_INT. */
1433 return (GET_CODE (op) == CONST_INT
1434 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1435 || (INTVAL (op) >= 0xFFFFF000
1436 && INTVAL (op) <= 0xFFFFFFFF)));
1438 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1439 || (GET_CODE (op) == CONST_DOUBLE
1440 && CONST_DOUBLE_HIGH (op) == 0
1441 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1446 uns_arith_operand (rtx op, enum machine_mode mode)
1448 return register_operand (op, mode) || uns_small_int (op, mode);
1451 /* Return truth value of statement that OP is a call-clobbered register. */
1453 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1455 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1458 /* Return 1 if OP is a valid operand for the source of a move insn. */
1461 input_operand (rtx op, enum machine_mode mode)
1463 /* If both modes are non-void they must be the same. */
1464 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1467 /* Allow any one instruction integer constant, and all CONST_INT
1468 variants when we are working in DImode and !arch64. */
1469 if (GET_MODE_CLASS (mode) == MODE_INT
1470 && ((GET_CODE (op) == CONST_INT
1471 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1472 || SPARC_SIMM13_P (INTVAL (op))
1474 && ! TARGET_ARCH64)))
1476 && GET_CODE (op) == CONST_DOUBLE
1477 && ((CONST_DOUBLE_HIGH (op) == 0
1478 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1480 #if HOST_BITS_PER_WIDE_INT == 64
1481 (CONST_DOUBLE_HIGH (op) == 0
1482 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1484 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1485 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1486 && CONST_DOUBLE_HIGH (op) == 0)
1487 || (CONST_DOUBLE_HIGH (op) == -1
1488 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1493 /* If !arch64 and this is a DImode const, allow it so that
1494 the splits can be generated. */
1497 && GET_CODE (op) == CONST_DOUBLE)
1500 if (register_operand (op, mode))
1503 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1504 && GET_CODE (op) == CONST_DOUBLE)
1507 /* If this is a SUBREG, look inside so that we handle
1508 paradoxical ones. */
1509 if (GET_CODE (op) == SUBREG)
1510 op = SUBREG_REG (op);
1512 /* Check for valid MEM forms. */
1513 if (GET_CODE (op) == MEM)
1515 rtx inside = XEXP (op, 0);
1517 if (GET_CODE (inside) == LO_SUM)
1519 /* We can't allow these because all of the splits
1520 (eventually as they trickle down into DFmode
1521 splits) require offsettable memory references. */
1523 && GET_MODE (op) == TFmode)
1526 return (register_operand (XEXP (inside, 0), Pmode)
1527 && CONSTANT_P (XEXP (inside, 1)));
1529 return memory_address_p (mode, inside);
1535 /* Return 1 if OP is valid for the lhs of a compare insn. */
1538 compare_operand (rtx op, enum machine_mode mode)
1540 if (GET_CODE (op) == ZERO_EXTRACT)
1541 return (register_operand (XEXP (op, 0), mode)
1542 && small_int_or_double (XEXP (op, 1), mode)
1543 && small_int_or_double (XEXP (op, 2), mode)
1544 /* This matches cmp_zero_extract. */
1546 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1547 && INTVAL (XEXP (op, 2)) > 19)
1548 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1549 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 19)))
1550 /* This matches cmp_zero_extract_sp64. */
1553 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1554 && INTVAL (XEXP (op, 2)) > 51)
1555 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1556 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 51)))));
1558 return register_operand (op, mode);
1562 /* We know it can't be done in one insn when we get here,
1563 the movsi expander guarantees this. */
1565 sparc_emit_set_const32 (rtx op0, rtx op1)
1567 enum machine_mode mode = GET_MODE (op0);
1570 if (GET_CODE (op1) == CONST_INT)
1572 HOST_WIDE_INT value = INTVAL (op1);
1574 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1575 || SPARC_SIMM13_P (value))
1579 /* Full 2-insn decomposition is needed. */
1580 if (reload_in_progress || reload_completed)
1583 temp = gen_reg_rtx (mode);
1585 if (GET_CODE (op1) == CONST_INT)
1587 /* Emit them as real moves instead of a HIGH/LO_SUM,
1588 this way CSE can see everything and reuse intermediate
1589 values if it wants. */
1591 && HOST_BITS_PER_WIDE_INT != 64
1592 && (INTVAL (op1) & 0x80000000) != 0)
1593 emit_insn (gen_rtx_SET
1595 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1598 emit_insn (gen_rtx_SET (VOIDmode, temp,
1599 GEN_INT (INTVAL (op1)
1600 & ~(HOST_WIDE_INT)0x3ff)));
1602 emit_insn (gen_rtx_SET (VOIDmode,
1604 gen_rtx_IOR (mode, temp,
1605 GEN_INT (INTVAL (op1) & 0x3ff))));
1609 /* A symbol, emit in the traditional way. */
1610 emit_insn (gen_rtx_SET (VOIDmode, temp,
1611 gen_rtx_HIGH (mode, op1)));
1612 emit_insn (gen_rtx_SET (VOIDmode,
1613 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1619 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1620 If TEMP is non-zero, we are forbidden to use any other scratch
1621 registers. Otherwise, we are allowed to generate them as needed.
1623 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1624 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1626 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1628 rtx temp1, temp2, temp3, temp4, temp5;
1631 if (temp && GET_MODE (temp) == TImode)
1634 temp = gen_rtx_REG (DImode, REGNO (temp));
1637 /* SPARC-V9 code-model support. */
1638 switch (sparc_cmodel)
1641 /* The range spanned by all instructions in the object is less
1642 than 2^31 bytes (2GB) and the distance from any instruction
1643 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1644 than 2^31 bytes (2GB).
1646 The executable must be in the low 4TB of the virtual address
1649 sethi %hi(symbol), %temp1
1650 or %temp1, %lo(symbol), %reg */
1652 temp1 = temp; /* op0 is allowed. */
1654 temp1 = gen_reg_rtx (DImode);
1656 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1657 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1661 /* The range spanned by all instructions in the object is less
1662 than 2^31 bytes (2GB) and the distance from any instruction
1663 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1664 than 2^31 bytes (2GB).
1666 The executable must be in the low 16TB of the virtual address
1669 sethi %h44(symbol), %temp1
1670 or %temp1, %m44(symbol), %temp2
1671 sllx %temp2, 12, %temp3
1672 or %temp3, %l44(symbol), %reg */
1677 temp3 = temp; /* op0 is allowed. */
1681 temp1 = gen_reg_rtx (DImode);
1682 temp2 = gen_reg_rtx (DImode);
1683 temp3 = gen_reg_rtx (DImode);
1686 emit_insn (gen_seth44 (temp1, op1));
1687 emit_insn (gen_setm44 (temp2, temp1, op1));
1688 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1689 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1690 emit_insn (gen_setl44 (op0, temp3, op1));
1694 /* The range spanned by all instructions in the object is less
1695 than 2^31 bytes (2GB) and the distance from any instruction
1696 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1697 than 2^31 bytes (2GB).
1699 The executable can be placed anywhere in the virtual address
1702 sethi %hh(symbol), %temp1
1703 sethi %lm(symbol), %temp2
1704 or %temp1, %hm(symbol), %temp3
1705 sllx %temp3, 32, %temp4
1706 or %temp4, %temp2, %temp5
1707 or %temp5, %lo(symbol), %reg */
1710 /* It is possible that one of the registers we got for operands[2]
1711 might coincide with that of operands[0] (which is why we made
1712 it TImode). Pick the other one to use as our scratch. */
1713 if (rtx_equal_p (temp, op0))
1716 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1721 temp2 = temp; /* op0 is _not_ allowed, see above. */
1728 temp1 = gen_reg_rtx (DImode);
1729 temp2 = gen_reg_rtx (DImode);
1730 temp3 = gen_reg_rtx (DImode);
1731 temp4 = gen_reg_rtx (DImode);
1732 temp5 = gen_reg_rtx (DImode);
1735 emit_insn (gen_sethh (temp1, op1));
1736 emit_insn (gen_setlm (temp2, op1));
1737 emit_insn (gen_sethm (temp3, temp1, op1));
1738 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1739 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1740 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1741 gen_rtx_PLUS (DImode, temp4, temp2)));
1742 emit_insn (gen_setlo (op0, temp5, op1));
1746 /* Old old old backwards compatibility kruft here.
1747 Essentially it is MEDLOW with a fixed 64-bit
1748 virtual base added to all data segment addresses.
1749 Text-segment stuff is computed like MEDANY, we can't
1750 reuse the code above because the relocation knobs
1753 Data segment: sethi %hi(symbol), %temp1
1754 add %temp1, EMBMEDANY_BASE_REG, %temp2
1755 or %temp2, %lo(symbol), %reg */
1756 if (data_segment_operand (op1, GET_MODE (op1)))
1760 temp1 = temp; /* op0 is allowed. */
1765 temp1 = gen_reg_rtx (DImode);
1766 temp2 = gen_reg_rtx (DImode);
1769 emit_insn (gen_embmedany_sethi (temp1, op1));
1770 emit_insn (gen_embmedany_brsum (temp2, temp1));
1771 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1774 /* Text segment: sethi %uhi(symbol), %temp1
1775 sethi %hi(symbol), %temp2
1776 or %temp1, %ulo(symbol), %temp3
1777 sllx %temp3, 32, %temp4
1778 or %temp4, %temp2, %temp5
1779 or %temp5, %lo(symbol), %reg */
1784 /* It is possible that one of the registers we got for operands[2]
1785 might coincide with that of operands[0] (which is why we made
1786 it TImode). Pick the other one to use as our scratch. */
1787 if (rtx_equal_p (temp, op0))
1790 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1795 temp2 = temp; /* op0 is _not_ allowed, see above. */
1802 temp1 = gen_reg_rtx (DImode);
1803 temp2 = gen_reg_rtx (DImode);
1804 temp3 = gen_reg_rtx (DImode);
1805 temp4 = gen_reg_rtx (DImode);
1806 temp5 = gen_reg_rtx (DImode);
1809 emit_insn (gen_embmedany_textuhi (temp1, op1));
1810 emit_insn (gen_embmedany_texthi (temp2, op1));
1811 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1812 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1813 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1814 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1815 gen_rtx_PLUS (DImode, temp4, temp2)));
1816 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1825 /* These avoid problems when cross compiling. If we do not
1826 go through all this hair then the optimizer will see
1827 invalid REG_EQUAL notes or in some cases none at all. */
1828 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1829 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1830 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1831 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1833 #if HOST_BITS_PER_WIDE_INT == 64
1834 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1835 #define GEN_INT64(__x) GEN_INT (__x)
1837 #define GEN_HIGHINT64(__x) \
1838 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1839 #define GEN_INT64(__x) \
1840 immed_double_const ((__x) & 0xffffffff, \
1841 ((__x) & 0x80000000 ? -1 : 0), DImode)
1844 /* The optimizer is not to assume anything about exactly
1845 which bits are set for a HIGH, they are unspecified.
1846 Unfortunately this leads to many missed optimizations
1847 during CSE. We mask out the non-HIGH bits, and matches
1848 a plain movdi, to alleviate this problem. */
1850 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1852 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1856 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1858 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1862 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1864 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1868 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1870 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1873 /* Worker routines for 64-bit constant formation on arch64.
1874 One of the key things to be doing in these emissions is
1875 to create as many temp REGs as possible. This makes it
1876 possible for half-built constants to be used later when
1877 such values are similar to something required later on.
1878 Without doing this, the optimizer cannot see such
1881 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1882 unsigned HOST_WIDE_INT, int);
1885 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1886 unsigned HOST_WIDE_INT low_bits, int is_neg)
1888 unsigned HOST_WIDE_INT high_bits;
1891 high_bits = (~low_bits) & 0xffffffff;
1893 high_bits = low_bits;
1895 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1898 emit_insn (gen_rtx_SET (VOIDmode, op0,
1899 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1903 /* If we are XOR'ing with -1, then we should emit a one's complement
1904 instead. This way the combiner will notice logical operations
1905 such as ANDN later on and substitute. */
1906 if ((low_bits & 0x3ff) == 0x3ff)
1908 emit_insn (gen_rtx_SET (VOIDmode, op0,
1909 gen_rtx_NOT (DImode, temp)));
1913 emit_insn (gen_rtx_SET (VOIDmode, op0,
1914 gen_safe_XOR64 (temp,
1915 (-(HOST_WIDE_INT)0x400
1916 | (low_bits & 0x3ff)))));
1921 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1922 unsigned HOST_WIDE_INT, int);
1925 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1926 unsigned HOST_WIDE_INT high_bits,
1927 unsigned HOST_WIDE_INT low_immediate,
1932 if ((high_bits & 0xfffffc00) != 0)
1934 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1935 if ((high_bits & ~0xfffffc00) != 0)
1936 emit_insn (gen_rtx_SET (VOIDmode, op0,
1937 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1943 emit_insn (gen_safe_SET64 (temp, high_bits));
1947 /* Now shift it up into place. */
1948 emit_insn (gen_rtx_SET (VOIDmode, op0,
1949 gen_rtx_ASHIFT (DImode, temp2,
1950 GEN_INT (shift_count))));
1952 /* If there is a low immediate part piece, finish up by
1953 putting that in as well. */
1954 if (low_immediate != 0)
1955 emit_insn (gen_rtx_SET (VOIDmode, op0,
1956 gen_safe_OR64 (op0, low_immediate)));
1959 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1960 unsigned HOST_WIDE_INT);
1962 /* Full 64-bit constant decomposition. Even though this is the
1963 'worst' case, we still optimize a few things away. */
1965 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1966 unsigned HOST_WIDE_INT high_bits,
1967 unsigned HOST_WIDE_INT low_bits)
1971 if (reload_in_progress || reload_completed)
1974 sub_temp = gen_reg_rtx (DImode);
1976 if ((high_bits & 0xfffffc00) != 0)
1978 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1979 if ((high_bits & ~0xfffffc00) != 0)
1980 emit_insn (gen_rtx_SET (VOIDmode,
1982 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1988 emit_insn (gen_safe_SET64 (temp, high_bits));
1992 if (!reload_in_progress && !reload_completed)
1994 rtx temp2 = gen_reg_rtx (DImode);
1995 rtx temp3 = gen_reg_rtx (DImode);
1996 rtx temp4 = gen_reg_rtx (DImode);
1998 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1999 gen_rtx_ASHIFT (DImode, sub_temp,
2002 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
2003 if ((low_bits & ~0xfffffc00) != 0)
2005 emit_insn (gen_rtx_SET (VOIDmode, temp3,
2006 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
2007 emit_insn (gen_rtx_SET (VOIDmode, op0,
2008 gen_rtx_PLUS (DImode, temp4, temp3)));
2012 emit_insn (gen_rtx_SET (VOIDmode, op0,
2013 gen_rtx_PLUS (DImode, temp4, temp2)));
2018 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
2019 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
2020 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
2023 /* We are in the middle of reload, so this is really
2024 painful. However we do still make an attempt to
2025 avoid emitting truly stupid code. */
2026 if (low1 != const0_rtx)
2028 emit_insn (gen_rtx_SET (VOIDmode, op0,
2029 gen_rtx_ASHIFT (DImode, sub_temp,
2030 GEN_INT (to_shift))));
2031 emit_insn (gen_rtx_SET (VOIDmode, op0,
2032 gen_rtx_IOR (DImode, op0, low1)));
2040 if (low2 != const0_rtx)
2042 emit_insn (gen_rtx_SET (VOIDmode, op0,
2043 gen_rtx_ASHIFT (DImode, sub_temp,
2044 GEN_INT (to_shift))));
2045 emit_insn (gen_rtx_SET (VOIDmode, op0,
2046 gen_rtx_IOR (DImode, op0, low2)));
2054 emit_insn (gen_rtx_SET (VOIDmode, op0,
2055 gen_rtx_ASHIFT (DImode, sub_temp,
2056 GEN_INT (to_shift))));
2057 if (low3 != const0_rtx)
2058 emit_insn (gen_rtx_SET (VOIDmode, op0,
2059 gen_rtx_IOR (DImode, op0, low3)));
2064 /* Analyze a 64-bit constant for certain properties. */
2065 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
2066 unsigned HOST_WIDE_INT,
2067 int *, int *, int *);
2070 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
2071 unsigned HOST_WIDE_INT low_bits,
2072 int *hbsp, int *lbsp, int *abbasp)
2074 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
2077 lowest_bit_set = highest_bit_set = -1;
2081 if ((lowest_bit_set == -1)
2082 && ((low_bits >> i) & 1))
2084 if ((highest_bit_set == -1)
2085 && ((high_bits >> (32 - i - 1)) & 1))
2086 highest_bit_set = (64 - i - 1);
2089 && ((highest_bit_set == -1)
2090 || (lowest_bit_set == -1)));
2096 if ((lowest_bit_set == -1)
2097 && ((high_bits >> i) & 1))
2098 lowest_bit_set = i + 32;
2099 if ((highest_bit_set == -1)
2100 && ((low_bits >> (32 - i - 1)) & 1))
2101 highest_bit_set = 32 - i - 1;
2104 && ((highest_bit_set == -1)
2105 || (lowest_bit_set == -1)));
2107 /* If there are no bits set this should have gone out
2108 as one instruction! */
2109 if (lowest_bit_set == -1
2110 || highest_bit_set == -1)
2112 all_bits_between_are_set = 1;
2113 for (i = lowest_bit_set; i <= highest_bit_set; i++)
2117 if ((low_bits & (1 << i)) != 0)
2122 if ((high_bits & (1 << (i - 32))) != 0)
2125 all_bits_between_are_set = 0;
2128 *hbsp = highest_bit_set;
2129 *lbsp = lowest_bit_set;
2130 *abbasp = all_bits_between_are_set;
2133 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
2136 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
2137 unsigned HOST_WIDE_INT low_bits)
2139 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
2142 || high_bits == 0xffffffff)
2145 analyze_64bit_constant (high_bits, low_bits,
2146 &highest_bit_set, &lowest_bit_set,
2147 &all_bits_between_are_set);
2149 if ((highest_bit_set == 63
2150 || lowest_bit_set == 0)
2151 && all_bits_between_are_set != 0)
2154 if ((highest_bit_set - lowest_bit_set) < 21)
2160 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
2161 unsigned HOST_WIDE_INT,
2164 static unsigned HOST_WIDE_INT
2165 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
2166 unsigned HOST_WIDE_INT low_bits,
2167 int lowest_bit_set, int shift)
2169 HOST_WIDE_INT hi, lo;
2171 if (lowest_bit_set < 32)
2173 lo = (low_bits >> lowest_bit_set) << shift;
2174 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
2179 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
2186 /* Here we are sure to be arch64 and this is an integer constant
2187 being loaded into a register. Emit the most efficient
2188 insn sequence possible. Detection of all the 1-insn cases
2189 has been done already. */
2191 sparc_emit_set_const64 (rtx op0, rtx op1)
2193 unsigned HOST_WIDE_INT high_bits, low_bits;
2194 int lowest_bit_set, highest_bit_set;
2195 int all_bits_between_are_set;
2198 /* Sanity check that we know what we are working with. */
2199 if (! TARGET_ARCH64)
2202 if (GET_CODE (op0) != SUBREG)
2204 if (GET_CODE (op0) != REG
2205 || (REGNO (op0) >= SPARC_FIRST_FP_REG
2206 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
2210 if (reload_in_progress || reload_completed)
2213 if (GET_CODE (op1) != CONST_DOUBLE
2214 && GET_CODE (op1) != CONST_INT)
2216 sparc_emit_set_symbolic_const64 (op0, op1, temp);
2221 temp = gen_reg_rtx (DImode);
2223 if (GET_CODE (op1) == CONST_DOUBLE)
2225 #if HOST_BITS_PER_WIDE_INT == 64
2226 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
2227 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
2229 high_bits = CONST_DOUBLE_HIGH (op1);
2230 low_bits = CONST_DOUBLE_LOW (op1);
2235 #if HOST_BITS_PER_WIDE_INT == 64
2236 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2237 low_bits = (INTVAL (op1) & 0xffffffff);
2239 high_bits = ((INTVAL (op1) < 0) ?
2242 low_bits = INTVAL (op1);
2246 /* low_bits bits 0 --> 31
2247 high_bits bits 32 --> 63 */
2249 analyze_64bit_constant (high_bits, low_bits,
2250 &highest_bit_set, &lowest_bit_set,
2251 &all_bits_between_are_set);
2253 /* First try for a 2-insn sequence. */
2255 /* These situations are preferred because the optimizer can
2256 * do more things with them:
2258 * sllx %reg, shift, %reg
2260 * srlx %reg, shift, %reg
2261 * 3) mov some_small_const, %reg
2262 * sllx %reg, shift, %reg
2264 if (((highest_bit_set == 63
2265 || lowest_bit_set == 0)
2266 && all_bits_between_are_set != 0)
2267 || ((highest_bit_set - lowest_bit_set) < 12))
2269 HOST_WIDE_INT the_const = -1;
2270 int shift = lowest_bit_set;
2272 if ((highest_bit_set != 63
2273 && lowest_bit_set != 0)
2274 || all_bits_between_are_set == 0)
2277 create_simple_focus_bits (high_bits, low_bits,
2280 else if (lowest_bit_set == 0)
2281 shift = -(63 - highest_bit_set);
2283 if (! SPARC_SIMM13_P (the_const))
2286 emit_insn (gen_safe_SET64 (temp, the_const));
2288 emit_insn (gen_rtx_SET (VOIDmode,
2290 gen_rtx_ASHIFT (DImode,
2294 emit_insn (gen_rtx_SET (VOIDmode,
2296 gen_rtx_LSHIFTRT (DImode,
2298 GEN_INT (-shift))));
2304 /* Now a range of 22 or less bits set somewhere.
2305 * 1) sethi %hi(focus_bits), %reg
2306 * sllx %reg, shift, %reg
2307 * 2) sethi %hi(focus_bits), %reg
2308 * srlx %reg, shift, %reg
2310 if ((highest_bit_set - lowest_bit_set) < 21)
2312 unsigned HOST_WIDE_INT focus_bits =
2313 create_simple_focus_bits (high_bits, low_bits,
2314 lowest_bit_set, 10);
2316 if (! SPARC_SETHI_P (focus_bits))
2319 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2321 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2322 if (lowest_bit_set < 10)
2323 emit_insn (gen_rtx_SET (VOIDmode,
2325 gen_rtx_LSHIFTRT (DImode, temp,
2326 GEN_INT (10 - lowest_bit_set))));
2327 else if (lowest_bit_set > 10)
2328 emit_insn (gen_rtx_SET (VOIDmode,
2330 gen_rtx_ASHIFT (DImode, temp,
2331 GEN_INT (lowest_bit_set - 10))));
2337 /* 1) sethi %hi(low_bits), %reg
2338 * or %reg, %lo(low_bits), %reg
2339 * 2) sethi %hi(~low_bits), %reg
2340 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2343 || high_bits == 0xffffffff)
2345 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2346 (high_bits == 0xffffffff));
2350 /* Now, try 3-insn sequences. */
2352 /* 1) sethi %hi(high_bits), %reg
2353 * or %reg, %lo(high_bits), %reg
2354 * sllx %reg, 32, %reg
2358 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2362 /* We may be able to do something quick
2363 when the constant is negated, so try that. */
2364 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2365 (~low_bits) & 0xfffffc00))
2367 /* NOTE: The trailing bits get XOR'd so we need the
2368 non-negated bits, not the negated ones. */
2369 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2371 if ((((~high_bits) & 0xffffffff) == 0
2372 && ((~low_bits) & 0x80000000) == 0)
2373 || (((~high_bits) & 0xffffffff) == 0xffffffff
2374 && ((~low_bits) & 0x80000000) != 0))
2376 int fast_int = (~low_bits & 0xffffffff);
2378 if ((SPARC_SETHI_P (fast_int)
2379 && (~high_bits & 0xffffffff) == 0)
2380 || SPARC_SIMM13_P (fast_int))
2381 emit_insn (gen_safe_SET64 (temp, fast_int));
2383 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2388 #if HOST_BITS_PER_WIDE_INT == 64
2389 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2390 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2392 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2393 (~high_bits) & 0xffffffff,
2396 sparc_emit_set_const64 (temp, negated_const);
2399 /* If we are XOR'ing with -1, then we should emit a one's complement
2400 instead. This way the combiner will notice logical operations
2401 such as ANDN later on and substitute. */
2402 if (trailing_bits == 0x3ff)
2404 emit_insn (gen_rtx_SET (VOIDmode, op0,
2405 gen_rtx_NOT (DImode, temp)));
2409 emit_insn (gen_rtx_SET (VOIDmode,
2411 gen_safe_XOR64 (temp,
2412 (-0x400 | trailing_bits))));
2417 /* 1) sethi %hi(xxx), %reg
2418 * or %reg, %lo(xxx), %reg
2419 * sllx %reg, yyy, %reg
2421 * ??? This is just a generalized version of the low_bits==0
2422 * thing above, FIXME...
2424 if ((highest_bit_set - lowest_bit_set) < 32)
2426 unsigned HOST_WIDE_INT focus_bits =
2427 create_simple_focus_bits (high_bits, low_bits,
2430 /* We can't get here in this state. */
2431 if (highest_bit_set < 32
2432 || lowest_bit_set >= 32)
2435 /* So what we know is that the set bits straddle the
2436 middle of the 64-bit word. */
2437 sparc_emit_set_const64_quick2 (op0, temp,
2443 /* 1) sethi %hi(high_bits), %reg
2444 * or %reg, %lo(high_bits), %reg
2445 * sllx %reg, 32, %reg
2446 * or %reg, low_bits, %reg
2448 if (SPARC_SIMM13_P(low_bits)
2449 && ((int)low_bits > 0))
2451 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2455 /* The easiest way when all else fails, is full decomposition. */
2457 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2458 high_bits, low_bits, ~high_bits, ~low_bits);
2460 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2463 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2464 return the mode to be used for the comparison. For floating-point,
2465 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2466 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2467 processing is needed. */
2470 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2472 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2498 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2499 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2501 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2502 return CCX_NOOVmode;
2508 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2515 /* X and Y are two things to compare using CODE. Emit the compare insn and
2516 return the rtx for the cc reg in the proper mode. */
2519 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2521 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2524 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2525 fcc regs (cse can't tell they're really call clobbered regs and will
2526 remove a duplicate comparison even if there is an intervening function
2527 call - it will then try to reload the cc reg via an int reg which is why
2528 we need the movcc patterns). It is possible to provide the movcc
2529 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2530 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2531 to tell cse that CCFPE mode registers (even pseudos) are call
2534 /* ??? This is an experiment. Rather than making changes to cse which may
2535 or may not be easy/clean, we do our own cse. This is possible because
2536 we will generate hard registers. Cse knows they're call clobbered (it
2537 doesn't know the same thing about pseudos). If we guess wrong, no big
2538 deal, but if we win, great! */
2540 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2541 #if 1 /* experiment */
2544 /* We cycle through the registers to ensure they're all exercised. */
2545 static int next_fcc_reg = 0;
2546 /* Previous x,y for each fcc reg. */
2547 static rtx prev_args[4][2];
2549 /* Scan prev_args for x,y. */
2550 for (reg = 0; reg < 4; reg++)
2551 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2556 prev_args[reg][0] = x;
2557 prev_args[reg][1] = y;
2558 next_fcc_reg = (next_fcc_reg + 1) & 3;
2560 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2563 cc_reg = gen_reg_rtx (mode);
2564 #endif /* ! experiment */
2565 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2566 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2568 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2570 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2571 gen_rtx_COMPARE (mode, x, y)));
2576 /* This function is used for v9 only.
2577 CODE is the code for an Scc's comparison.
2578 OPERANDS[0] is the target of the Scc insn.
2579 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2580 been generated yet).
2582 This function is needed to turn
2585 (gt (reg:CCX 100 %icc)
2589 (gt:DI (reg:CCX 100 %icc)
2592 IE: The instruction recognizer needs to see the mode of the comparison to
2593 find the right instruction. We could use "gt:DI" right in the
2594 define_expand, but leaving it out allows us to handle DI, SI, etc.
2596 We refer to the global sparc compare operands sparc_compare_op0 and
2597 sparc_compare_op1. */
2600 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2605 && (GET_MODE (sparc_compare_op0) == DImode
2606 || GET_MODE (operands[0]) == DImode))
2609 op0 = sparc_compare_op0;
2610 op1 = sparc_compare_op1;
2612 /* Try to use the movrCC insns. */
2614 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2615 && op1 == const0_rtx
2616 && v9_regcmp_p (compare_code))
2618 /* Special case for op0 != 0. This can be done with one instruction if
2619 operands[0] == sparc_compare_op0. */
2621 if (compare_code == NE
2622 && GET_MODE (operands[0]) == DImode
2623 && rtx_equal_p (op0, operands[0]))
2625 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2626 gen_rtx_IF_THEN_ELSE (DImode,
2627 gen_rtx_fmt_ee (compare_code, DImode,
2634 if (reg_overlap_mentioned_p (operands[0], op0))
2636 /* Handle the case where operands[0] == sparc_compare_op0.
2637 We "early clobber" the result. */
2638 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2639 emit_move_insn (op0, sparc_compare_op0);
2642 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2643 if (GET_MODE (op0) != DImode)
2645 temp = gen_reg_rtx (DImode);
2646 convert_move (temp, op0, 0);
2650 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2651 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2652 gen_rtx_fmt_ee (compare_code, DImode,
2660 operands[1] = gen_compare_reg (compare_code, op0, op1);
2662 switch (GET_MODE (operands[1]))
2672 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2673 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2674 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2675 gen_rtx_fmt_ee (compare_code,
2676 GET_MODE (operands[1]),
2677 operands[1], const0_rtx),
2678 const1_rtx, operands[0])));
2683 /* Emit a conditional jump insn for the v9 architecture using comparison code
2684 CODE and jump target LABEL.
2685 This function exists to take advantage of the v9 brxx insns. */
2688 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2690 emit_jump_insn (gen_rtx_SET (VOIDmode,
2692 gen_rtx_IF_THEN_ELSE (VOIDmode,
2693 gen_rtx_fmt_ee (code, GET_MODE (op0),
2695 gen_rtx_LABEL_REF (VOIDmode, label),
2699 /* Generate a DFmode part of a hard TFmode register.
2700 REG is the TFmode hard register, LOW is 1 for the
2701 low 64bit of the register and 0 otherwise.
2704 gen_df_reg (rtx reg, int low)
2706 int regno = REGNO (reg);
2708 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2709 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2710 return gen_rtx_REG (DFmode, regno);
2713 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2714 Unlike normal calls, TFmode operands are passed by reference. It is
2715 assumed that no more than 3 operands are required. */
2718 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2720 rtx ret_slot = NULL, arg[3], func_sym;
2723 /* We only expect to be called for conversions, unary, and binary ops. */
2724 if (nargs < 2 || nargs > 3)
2727 for (i = 0; i < nargs; ++i)
2729 rtx this_arg = operands[i];
2732 /* TFmode arguments and return values are passed by reference. */
2733 if (GET_MODE (this_arg) == TFmode)
2735 int force_stack_temp;
2737 force_stack_temp = 0;
2738 if (TARGET_BUGGY_QP_LIB && i == 0)
2739 force_stack_temp = 1;
2741 if (GET_CODE (this_arg) == MEM
2742 && ! force_stack_temp)
2743 this_arg = XEXP (this_arg, 0);
2744 else if (CONSTANT_P (this_arg)
2745 && ! force_stack_temp)
2747 this_slot = force_const_mem (TFmode, this_arg);
2748 this_arg = XEXP (this_slot, 0);
2752 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2754 /* Operand 0 is the return value. We'll copy it out later. */
2756 emit_move_insn (this_slot, this_arg);
2758 ret_slot = this_slot;
2760 this_arg = XEXP (this_slot, 0);
2767 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2769 if (GET_MODE (operands[0]) == TFmode)
2772 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2773 arg[0], GET_MODE (arg[0]),
2774 arg[1], GET_MODE (arg[1]));
2776 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2777 arg[0], GET_MODE (arg[0]),
2778 arg[1], GET_MODE (arg[1]),
2779 arg[2], GET_MODE (arg[2]));
2782 emit_move_insn (operands[0], ret_slot);
2791 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2792 GET_MODE (operands[0]), 1,
2793 arg[1], GET_MODE (arg[1]));
2795 if (ret != operands[0])
2796 emit_move_insn (operands[0], ret);
2800 /* Expand soft-float TFmode calls to sparc abi routines. */
2803 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2825 emit_soft_tfmode_libcall (func, 3, operands);
2829 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2842 emit_soft_tfmode_libcall (func, 2, operands);
2846 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2853 switch (GET_MODE (operands[1]))
2866 case FLOAT_TRUNCATE:
2867 switch (GET_MODE (operands[0]))
2881 switch (GET_MODE (operands[1]))
2894 case UNSIGNED_FLOAT:
2895 switch (GET_MODE (operands[1]))
2909 switch (GET_MODE (operands[0]))
2923 switch (GET_MODE (operands[0]))
2940 emit_soft_tfmode_libcall (func, 2, operands);
2943 /* Expand a hard-float tfmode operation. All arguments must be in
2947 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2951 if (GET_RTX_CLASS (code) == RTX_UNARY)
2953 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2954 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2958 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2959 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2960 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2961 operands[1], operands[2]);
2964 if (register_operand (operands[0], VOIDmode))
2967 dest = gen_reg_rtx (GET_MODE (operands[0]));
2969 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2971 if (dest != operands[0])
2972 emit_move_insn (operands[0], dest);
2976 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2978 if (TARGET_HARD_QUAD)
2979 emit_hard_tfmode_operation (code, operands);
2981 emit_soft_tfmode_binop (code, operands);
2985 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2987 if (TARGET_HARD_QUAD)
2988 emit_hard_tfmode_operation (code, operands);
2990 emit_soft_tfmode_unop (code, operands);
2994 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2996 if (TARGET_HARD_QUAD)
2997 emit_hard_tfmode_operation (code, operands);
2999 emit_soft_tfmode_cvt (code, operands);
3002 /* Return nonzero if a branch/jump/call instruction will be emitting
3003 nop into its delay slot. */
3006 empty_delay_slot (rtx insn)
3010 /* If no previous instruction (should not happen), return true. */
3011 if (PREV_INSN (insn) == NULL)
3014 seq = NEXT_INSN (PREV_INSN (insn));
3015 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
3021 /* Return nonzero if TRIAL can go into the call delay slot. */
3024 tls_call_delay (rtx trial)
3029 call __tls_get_addr, %tgd_call (foo)
3030 add %l7, %o0, %o0, %tgd_add (foo)
3031 while Sun as/ld does not. */
3032 if (TARGET_GNU_TLS || !TARGET_TLS)
3035 pat = PATTERN (trial);
3036 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
3039 unspec = XEXP (SET_DEST (pat), 1);
3040 if (GET_CODE (unspec) != UNSPEC
3041 || (XINT (unspec, 1) != UNSPEC_TLSGD
3042 && XINT (unspec, 1) != UNSPEC_TLSLDM))
3048 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3049 instruction. RETURN_P is true if the v9 variant 'return' is to be
3050 considered in the test too.
3052 TRIAL must be a SET whose destination is a REG appropriate for the
3053 'restore' instruction or, if RETURN_P is true, for the 'return'
3057 eligible_for_restore_insn (rtx trial, bool return_p)
3059 rtx pat = PATTERN (trial);
3060 rtx src = SET_SRC (pat);
3062 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3063 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3064 && arith_operand (src, GET_MODE (src)))
3067 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3069 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3072 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3073 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3074 && arith_double_operand (src, GET_MODE (src)))
3075 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3077 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3078 else if (! TARGET_FPU && register_operand (src, SFmode))
3081 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3082 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
3085 /* If we have the 'return' instruction, anything that does not use
3086 local or output registers and can go into a delay slot wins. */
3087 else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1)
3088 && (get_attr_in_uncond_branch_delay (trial)
3089 == IN_UNCOND_BRANCH_DELAY_TRUE))
3092 /* The 'restore src1,src2,dest' pattern for SImode. */
3093 else if (GET_CODE (src) == PLUS
3094 && register_operand (XEXP (src, 0), SImode)
3095 && arith_operand (XEXP (src, 1), SImode))
3098 /* The 'restore src1,src2,dest' pattern for DImode. */
3099 else if (GET_CODE (src) == PLUS
3100 && register_operand (XEXP (src, 0), DImode)
3101 && arith_double_operand (XEXP (src, 1), DImode))
3104 /* The 'restore src1,%lo(src2),dest' pattern. */
3105 else if (GET_CODE (src) == LO_SUM
3106 && ! TARGET_CM_MEDMID
3107 && ((register_operand (XEXP (src, 0), SImode)
3108 && immediate_operand (XEXP (src, 1), SImode))
3110 && register_operand (XEXP (src, 0), DImode)
3111 && immediate_operand (XEXP (src, 1), DImode))))
3114 /* The 'restore src,src,dest' pattern. */
3115 else if (GET_CODE (src) == ASHIFT
3116 && (register_operand (XEXP (src, 0), SImode)
3117 || register_operand (XEXP (src, 0), DImode))
3118 && XEXP (src, 1) == const1_rtx)
3124 /* Return nonzero if TRIAL can go into the function return's
3128 eligible_for_return_delay (rtx trial)
3130 int leaf_function_p = current_function_uses_only_leaf_regs;
3133 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3136 if (get_attr_length (trial) != 1)
3139 /* If there are any call-saved registers, we should scan TRIAL if it
3140 does not reference them. For now just make it easy. */
3144 /* If the function uses __builtin_eh_return, the eh_return machinery
3145 occupies the delay slot. */
3146 if (current_function_calls_eh_return)
3149 /* In the case of a true leaf function, anything can go into the slot. */
3150 if (leaf_function_p)
3151 return get_attr_in_uncond_branch_delay (trial)
3152 == IN_UNCOND_BRANCH_DELAY_TRUE;
3154 pat = PATTERN (trial);
3156 /* Otherwise, only operations which can be done in tandem with
3157 a `restore' or `return' insn can go into the delay slot. */
3158 if (GET_CODE (SET_DEST (pat)) != REG
3159 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
3162 /* If this instruction sets up floating point register and we have a return
3163 instruction, it can probably go in. But restore will not work
3165 if (REGNO (SET_DEST (pat)) >= 32)
3167 && ! epilogue_renumber (&pat, 1)
3168 && (get_attr_in_uncond_branch_delay (trial)
3169 == IN_UNCOND_BRANCH_DELAY_TRUE));
3171 return eligible_for_restore_insn (trial, true);
3174 /* Return nonzero if TRIAL can go into the sibling call's
3178 eligible_for_sibcall_delay (rtx trial)
3180 int leaf_function_p = current_function_uses_only_leaf_regs;
3183 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3186 if (get_attr_length (trial) != 1)
3189 pat = PATTERN (trial);
3191 if (leaf_function_p)
3193 /* If the tail call is done using the call instruction,
3194 we have to restore %o7 in the delay slot. */
3195 if (LEAF_SIBCALL_SLOT_RESERVED_P)
3198 /* %g1 is used to build the function address */
3199 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3205 /* Otherwise, only operations which can be done in tandem with
3206 a `restore' insn can go into the delay slot. */
3207 if (GET_CODE (SET_DEST (pat)) != REG
3208 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
3209 || REGNO (SET_DEST (pat)) >= 32)
3212 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3214 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3217 return eligible_for_restore_insn (trial, false);
3221 short_branch (int uid1, int uid2)
3223 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3225 /* Leave a few words of "slop". */
3226 if (delta >= -1023 && delta <= 1022)
3232 /* Return nonzero if REG is not used after INSN.
3233 We assume REG is a reload reg, and therefore does
3234 not live past labels or calls or jumps. */
3236 reg_unused_after (rtx reg, rtx insn)
3238 enum rtx_code code, prev_code = UNKNOWN;
3240 while ((insn = NEXT_INSN (insn)))
3242 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3245 code = GET_CODE (insn);
3246 if (GET_CODE (insn) == CODE_LABEL)
3251 rtx set = single_set (insn);
3252 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3255 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3257 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3265 /* Determine if it's legal to put X into the constant pool. This
3266 is not possible if X contains the address of a symbol that is
3267 not constant (TLS) or not known at final link time (PIC). */
3270 sparc_cannot_force_const_mem (rtx x)
3272 switch (GET_CODE (x))
3276 /* Accept all non-symbolic constants. */
3280 /* Labels are OK iff we are non-PIC. */
3281 return flag_pic != 0;
3284 /* 'Naked' TLS symbol references are never OK,
3285 non-TLS symbols are OK iff we are non-PIC. */
3286 if (SYMBOL_REF_TLS_MODEL (x))
3289 return flag_pic != 0;
3292 return sparc_cannot_force_const_mem (XEXP (x, 0));
3295 return sparc_cannot_force_const_mem (XEXP (x, 0))
3296 || sparc_cannot_force_const_mem (XEXP (x, 1));
3304 /* The table we use to reference PIC data. */
3305 static GTY(()) rtx global_offset_table;
3307 /* The function we use to get at it. */
3308 static GTY(()) rtx add_pc_to_pic_symbol;
3309 static GTY(()) char add_pc_to_pic_symbol_name[256];
3311 /* Ensure that we are not using patterns that are not OK with PIC. */
3319 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3320 || (GET_CODE (recog_data.operand[i]) == CONST
3321 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3322 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3323 == global_offset_table)
3324 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3333 /* Return true if X is an address which needs a temporary register when
3334 reloaded while generating PIC code. */
3337 pic_address_needs_scratch (rtx x)
3339 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3340 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3341 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3342 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3343 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3349 /* Determine if a given RTX is a valid constant. We already know this
3350 satisfies CONSTANT_P. */
3353 legitimate_constant_p (rtx x)
3357 switch (GET_CODE (x))
3360 /* TLS symbols are not constant. */
3361 if (SYMBOL_REF_TLS_MODEL (x))
3366 inner = XEXP (x, 0);
3368 /* Offsets of TLS symbols are never valid.
3369 Discourage CSE from creating them. */
3370 if (GET_CODE (inner) == PLUS
3371 && tls_symbolic_operand (XEXP (inner, 0)))
3376 if (GET_MODE (x) == VOIDmode)
3379 /* Floating point constants are generally not ok.
3380 The only exception is 0.0 in VIS. */
3382 && (GET_MODE (x) == SFmode
3383 || GET_MODE (x) == DFmode
3384 || GET_MODE (x) == TFmode)
3385 && fp_zero_operand (x, GET_MODE (x)))
3397 /* Determine if a given RTX is a valid constant address. */
3400 constant_address_p (rtx x)
3402 switch (GET_CODE (x))
3410 if (flag_pic && pic_address_needs_scratch (x))
3412 return legitimate_constant_p (x);
3415 return !flag_pic && legitimate_constant_p (x);
3422 /* Nonzero if the constant value X is a legitimate general operand
3423 when generating PIC code. It is given that flag_pic is on and
3424 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3427 legitimate_pic_operand_p (rtx x)
3429 if (pic_address_needs_scratch (x))
3431 if (tls_symbolic_operand (x)
3432 || (GET_CODE (x) == CONST
3433 && GET_CODE (XEXP (x, 0)) == PLUS
3434 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3439 /* Return nonzero if ADDR is a valid memory address.
3440 STRICT specifies whether strict register checking applies. */
3443 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3445 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3447 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3449 else if (GET_CODE (addr) == PLUS)
3451 rs1 = XEXP (addr, 0);
3452 rs2 = XEXP (addr, 1);
3454 /* Canonicalize. REG comes first, if there are no regs,
3455 LO_SUM comes first. */
3457 && GET_CODE (rs1) != SUBREG
3459 || GET_CODE (rs2) == SUBREG
3460 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3462 rs1 = XEXP (addr, 1);
3463 rs2 = XEXP (addr, 0);
3467 && rs1 == pic_offset_table_rtx
3469 && GET_CODE (rs2) != SUBREG
3470 && GET_CODE (rs2) != LO_SUM
3471 && GET_CODE (rs2) != MEM
3472 && !tls_symbolic_operand (rs2)
3473 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3474 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3476 || GET_CODE (rs1) == SUBREG)
3477 && RTX_OK_FOR_OFFSET_P (rs2)))
3482 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3483 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3485 /* We prohibit REG + REG for TFmode when there are no instructions
3486 which accept REG+REG instructions. We do this because REG+REG
3487 is not an offsetable address. If we get the situation in reload
3488 where source and destination of a movtf pattern are both MEMs with
3489 REG+REG address, then only one of them gets converted to an
3490 offsetable address. */
3492 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3493 && TARGET_HARD_QUAD))
3496 /* We prohibit REG + REG on ARCH32 if not optimizing for
3497 DFmode/DImode because then mem_min_alignment is likely to be zero
3498 after reload and the forced split would lack a matching splitter
3500 if (TARGET_ARCH32 && !optimize
3501 && (mode == DFmode || mode == DImode))
3504 else if (USE_AS_OFFSETABLE_LO10
3505 && GET_CODE (rs1) == LO_SUM
3507 && ! TARGET_CM_MEDMID
3508 && RTX_OK_FOR_OLO10_P (rs2))
3512 imm1 = XEXP (rs1, 1);
3513 rs1 = XEXP (rs1, 0);
3514 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3518 else if (GET_CODE (addr) == LO_SUM)
3520 rs1 = XEXP (addr, 0);
3521 imm1 = XEXP (addr, 1);
3523 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3526 /* We can't allow TFmode, because an offset greater than or equal to the
3527 alignment (8) may cause the LO_SUM to overflow if !v9. */
3528 if (mode == TFmode && !TARGET_V9)
3531 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3536 if (GET_CODE (rs1) == SUBREG)
3537 rs1 = SUBREG_REG (rs1);
3543 if (GET_CODE (rs2) == SUBREG)
3544 rs2 = SUBREG_REG (rs2);
3551 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3552 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3557 if ((REGNO (rs1) >= 32
3558 && REGNO (rs1) != FRAME_POINTER_REGNUM
3559 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3561 && (REGNO (rs2) >= 32
3562 && REGNO (rs2) != FRAME_POINTER_REGNUM
3563 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3569 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3571 static GTY(()) rtx sparc_tls_symbol;
3573 sparc_tls_get_addr (void)
3575 if (!sparc_tls_symbol)
3576 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3578 return sparc_tls_symbol;
3582 sparc_tls_got (void)
3587 current_function_uses_pic_offset_table = 1;
3588 return pic_offset_table_rtx;
3591 if (!global_offset_table)
3592 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3593 temp = gen_reg_rtx (Pmode);
3594 emit_move_insn (temp, global_offset_table);
3599 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3600 this (thread-local) address. */
3603 legitimize_tls_address (rtx addr)
3605 rtx temp1, temp2, temp3, ret, o0, got, insn;
3610 if (GET_CODE (addr) == SYMBOL_REF)
3611 switch (SYMBOL_REF_TLS_MODEL (addr))
3613 case TLS_MODEL_GLOBAL_DYNAMIC:
3615 temp1 = gen_reg_rtx (SImode);
3616 temp2 = gen_reg_rtx (SImode);
3617 ret = gen_reg_rtx (Pmode);
3618 o0 = gen_rtx_REG (Pmode, 8);
3619 got = sparc_tls_got ();
3620 emit_insn (gen_tgd_hi22 (temp1, addr));
3621 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3624 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3625 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3630 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3631 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3634 CALL_INSN_FUNCTION_USAGE (insn)
3635 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3636 CALL_INSN_FUNCTION_USAGE (insn));
3637 insn = get_insns ();
3639 emit_libcall_block (insn, ret, o0, addr);
3642 case TLS_MODEL_LOCAL_DYNAMIC:
3644 temp1 = gen_reg_rtx (SImode);
3645 temp2 = gen_reg_rtx (SImode);
3646 temp3 = gen_reg_rtx (Pmode);
3647 ret = gen_reg_rtx (Pmode);
3648 o0 = gen_rtx_REG (Pmode, 8);
3649 got = sparc_tls_got ();
3650 emit_insn (gen_tldm_hi22 (temp1));
3651 emit_insn (gen_tldm_lo10 (temp2, temp1));
3654 emit_insn (gen_tldm_add32 (o0, got, temp2));
3655 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3660 emit_insn (gen_tldm_add64 (o0, got, temp2));
3661 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3664 CALL_INSN_FUNCTION_USAGE (insn)
3665 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3666 CALL_INSN_FUNCTION_USAGE (insn));
3667 insn = get_insns ();
3669 emit_libcall_block (insn, temp3, o0,
3670 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3671 UNSPEC_TLSLD_BASE));
3672 temp1 = gen_reg_rtx (SImode);
3673 temp2 = gen_reg_rtx (SImode);
3674 emit_insn (gen_tldo_hix22 (temp1, addr));
3675 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3677 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3679 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3682 case TLS_MODEL_INITIAL_EXEC:
3683 temp1 = gen_reg_rtx (SImode);
3684 temp2 = gen_reg_rtx (SImode);
3685 temp3 = gen_reg_rtx (Pmode);
3686 got = sparc_tls_got ();
3687 emit_insn (gen_tie_hi22 (temp1, addr));
3688 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3690 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3692 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3695 ret = gen_reg_rtx (Pmode);
3697 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3700 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3704 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3707 case TLS_MODEL_LOCAL_EXEC:
3708 temp1 = gen_reg_rtx (Pmode);
3709 temp2 = gen_reg_rtx (Pmode);
3712 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3713 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3717 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3718 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3720 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3728 abort (); /* for now ... */
3734 /* Legitimize PIC addresses. If the address is already position-independent,
3735 we return ORIG. Newly generated position-independent addresses go into a
3736 reg. This is REG if nonzero, otherwise we allocate register(s) as
3740 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3743 if (GET_CODE (orig) == SYMBOL_REF)
3745 rtx pic_ref, address;
3750 if (reload_in_progress || reload_completed)
3753 reg = gen_reg_rtx (Pmode);
3758 /* If not during reload, allocate another temp reg here for loading
3759 in the address, so that these instructions can be optimized
3761 rtx temp_reg = ((reload_in_progress || reload_completed)
3762 ? reg : gen_reg_rtx (Pmode));
3764 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3765 won't get confused into thinking that these two instructions
3766 are loading in the true address of the symbol. If in the
3767 future a PIC rtx exists, that should be used instead. */
3768 if (Pmode == SImode)
3770 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3771 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3775 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3776 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3783 pic_ref = gen_rtx_MEM (Pmode,
3784 gen_rtx_PLUS (Pmode,
3785 pic_offset_table_rtx, address));
3786 current_function_uses_pic_offset_table = 1;
3787 RTX_UNCHANGING_P (pic_ref) = 1;
3788 insn = emit_move_insn (reg, pic_ref);
3789 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3791 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3795 else if (GET_CODE (orig) == CONST)
3799 if (GET_CODE (XEXP (orig, 0)) == PLUS
3800 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3805 if (reload_in_progress || reload_completed)
3808 reg = gen_reg_rtx (Pmode);
3811 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3813 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3814 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3815 base == reg ? 0 : reg);
3820 if (GET_CODE (offset) == CONST_INT)
3822 if (SMALL_INT (offset))
3823 return plus_constant (base, INTVAL (offset));
3824 else if (! reload_in_progress && ! reload_completed)
3825 offset = force_reg (Pmode, offset);
3827 /* If we reach here, then something is seriously wrong. */
3830 return gen_rtx_PLUS (Pmode, base, offset);
3832 else if (GET_CODE (orig) == LABEL_REF)
3833 /* ??? Why do we do this? */
3834 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3835 the register is live instead, in case it is eliminated. */
3836 current_function_uses_pic_offset_table = 1;
3841 /* Try machine-dependent ways of modifying an illegitimate address X
3842 to be legitimate. If we find one, return the new, valid address.
3844 OLDX is the address as it was before break_out_memory_refs was called.
3845 In some cases it is useful to look at this to decide what needs to be done.
3847 MODE is the mode of the operand pointed to by X. */
3850 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3854 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3855 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3856 force_operand (XEXP (x, 0), NULL_RTX));
3857 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3858 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3859 force_operand (XEXP (x, 1), NULL_RTX));
3860 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3861 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3863 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3864 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3865 force_operand (XEXP (x, 1), NULL_RTX));
3867 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3870 if (tls_symbolic_operand (x))
3871 x = legitimize_tls_address (x);
3873 x = legitimize_pic_address (x, mode, 0);
3874 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3875 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3876 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3877 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3878 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3879 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3880 else if (GET_CODE (x) == SYMBOL_REF
3881 || GET_CODE (x) == CONST
3882 || GET_CODE (x) == LABEL_REF)
3883 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3887 /* Emit the special PIC prologue. */
3890 load_pic_register (void)
3892 int orig_flag_pic = flag_pic;
3894 /* If we haven't emitted the special helper function, do so now. */
3895 if (add_pc_to_pic_symbol_name[0] == 0)
3897 const char *pic_name = reg_names[REGNO (pic_offset_table_rtx)];
3900 ASM_GENERATE_INTERNAL_LABEL (add_pc_to_pic_symbol_name, "LADDPC", 0);
3903 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3905 ASM_OUTPUT_ALIGN (asm_out_file, align);
3906 ASM_OUTPUT_LABEL (asm_out_file, add_pc_to_pic_symbol_name);
3907 if (flag_delayed_branch)
3908 fprintf (asm_out_file, "\tjmp %%o7+8\n\t add\t%%o7, %s, %s\n",
3909 pic_name, pic_name);
3911 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp %%o7+8\n\t nop\n",
3912 pic_name, pic_name);
3915 /* Initialize every time through, since we can't easily
3916 know this to be permanent. */
3917 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3918 add_pc_to_pic_symbol = gen_rtx_SYMBOL_REF (Pmode, add_pc_to_pic_symbol_name);
3921 emit_insn (gen_load_pcrel_sym (pic_offset_table_rtx, global_offset_table,
3922 add_pc_to_pic_symbol));
3923 flag_pic = orig_flag_pic;
3925 /* Need to emit this whether or not we obey regdecls,
3926 since setjmp/longjmp can cause life info to screw up.
3927 ??? In the case where we don't obey regdecls, this is not sufficient
3928 since we may not fall out the bottom. */
3929 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3932 /* Return 1 if RTX is a MEM which is known to be aligned to at
3933 least a DESIRED byte boundary. */
3936 mem_min_alignment (rtx mem, int desired)
3938 rtx addr, base, offset;
3940 /* If it's not a MEM we can't accept it. */
3941 if (GET_CODE (mem) != MEM)
3944 addr = XEXP (mem, 0);
3945 base = offset = NULL_RTX;
3946 if (GET_CODE (addr) == PLUS)
3948 if (GET_CODE (XEXP (addr, 0)) == REG)
3950 base = XEXP (addr, 0);
3952 /* What we are saying here is that if the base
3953 REG is aligned properly, the compiler will make
3954 sure any REG based index upon it will be so
3956 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3957 offset = XEXP (addr, 1);
3959 offset = const0_rtx;
3962 else if (GET_CODE (addr) == REG)
3965 offset = const0_rtx;
3968 if (base != NULL_RTX)
3970 int regno = REGNO (base);
3972 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3974 /* Check if the compiler has recorded some information
3975 about the alignment of the base REG. If reload has
3976 completed, we already matched with proper alignments.
3977 If not running global_alloc, reload might give us
3978 unaligned pointer to local stack though. */
3980 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3981 || (optimize && reload_completed))
3982 && (INTVAL (offset) & (desired - 1)) == 0)
3987 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3991 else if (! TARGET_UNALIGNED_DOUBLES
3992 || CONSTANT_P (addr)
3993 || GET_CODE (addr) == LO_SUM)
3995 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3996 is true, in which case we can only assume that an access is aligned if
3997 it is to a constant address, or the address involves a LO_SUM. */
4001 /* An obviously unaligned address. */
4006 /* Vectors to keep interesting information about registers where it can easily
4007 be got. We used to use the actual mode value as the bit number, but there
4008 are more than 32 modes now. Instead we use two tables: one indexed by
4009 hard register number, and one indexed by mode. */
4011 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4012 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
4013 mapped into one sparc_mode_class mode. */
4015 enum sparc_mode_class {
4016 S_MODE, D_MODE, T_MODE, O_MODE,
4017 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
4021 /* Modes for single-word and smaller quantities. */
4022 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4024 /* Modes for double-word and smaller quantities. */
4025 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4027 /* Modes for quad-word and smaller quantities. */
4028 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4030 /* Modes for 8-word and smaller quantities. */
4031 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4033 /* Modes for single-float quantities. We must allow any single word or
4034 smaller quantity. This is because the fix/float conversion instructions
4035 take integer inputs/outputs from the float registers. */
4036 #define SF_MODES (S_MODES)
4038 /* Modes for double-float and smaller quantities. */
4039 #define DF_MODES (S_MODES | D_MODES)
4041 /* Modes for double-float only quantities. */
4042 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4044 /* Modes for quad-float only quantities. */
4045 #define TF_ONLY_MODES (1 << (int) TF_MODE)
4047 /* Modes for quad-float and smaller quantities. */
4048 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
4050 /* Modes for quad-float and double-float quantities. */
4051 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
4053 /* Modes for quad-float pair only quantities. */
4054 #define OF_ONLY_MODES (1 << (int) OF_MODE)
4056 /* Modes for quad-float pairs and smaller quantities. */
4057 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
4059 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
4061 /* Modes for condition codes. */
4062 #define CC_MODES (1 << (int) CC_MODE)
4063 #define CCFP_MODES (1 << (int) CCFP_MODE)
4065 /* Value is 1 if register/mode pair is acceptable on sparc.
4066 The funny mixture of D and T modes is because integer operations
4067 do not specially operate on tetra quantities, so non-quad-aligned
4068 registers can hold quadword quantities (except %o4 and %i4 because
4069 they cross fixed registers). */
4071 /* This points to either the 32 bit or the 64 bit version. */
4072 const int *hard_regno_mode_classes;
4074 static const int hard_32bit_mode_classes[] = {
4075 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4076 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4077 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4078 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4080 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4081 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4082 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4083 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4085 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4086 and none can hold SFmode/SImode values. */
4087 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4088 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4089 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4090 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4093 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4099 static const int hard_64bit_mode_classes[] = {
4100 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4101 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4102 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4103 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4105 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4106 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4107 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4108 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4110 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4111 and none can hold SFmode/SImode values. */
4112 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4113 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4114 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4115 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4118 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4124 int sparc_mode_class [NUM_MACHINE_MODES];
4126 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4129 sparc_init_modes (void)
4133 for (i = 0; i < NUM_MACHINE_MODES; i++)
4135 switch (GET_MODE_CLASS (i))
4138 case MODE_PARTIAL_INT:
4139 case MODE_COMPLEX_INT:
4140 if (GET_MODE_SIZE (i) <= 4)
4141 sparc_mode_class[i] = 1 << (int) S_MODE;
4142 else if (GET_MODE_SIZE (i) == 8)
4143 sparc_mode_class[i] = 1 << (int) D_MODE;
4144 else if (GET_MODE_SIZE (i) == 16)
4145 sparc_mode_class[i] = 1 << (int) T_MODE;
4146 else if (GET_MODE_SIZE (i) == 32)
4147 sparc_mode_class[i] = 1 << (int) O_MODE;
4149 sparc_mode_class[i] = 0;
4152 case MODE_COMPLEX_FLOAT:
4153 if (GET_MODE_SIZE (i) <= 4)
4154 sparc_mode_class[i] = 1 << (int) SF_MODE;
4155 else if (GET_MODE_SIZE (i) == 8)
4156 sparc_mode_class[i] = 1 << (int) DF_MODE;
4157 else if (GET_MODE_SIZE (i) == 16)
4158 sparc_mode_class[i] = 1 << (int) TF_MODE;
4159 else if (GET_MODE_SIZE (i) == 32)
4160 sparc_mode_class[i] = 1 << (int) OF_MODE;
4162 sparc_mode_class[i] = 0;
4165 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4166 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4168 sparc_mode_class[i] = 1 << (int) CC_MODE;
4171 sparc_mode_class[i] = 0;
4177 hard_regno_mode_classes = hard_64bit_mode_classes;
4179 hard_regno_mode_classes = hard_32bit_mode_classes;
4181 /* Initialize the array used by REGNO_REG_CLASS. */
4182 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4184 if (i < 16 && TARGET_V8PLUS)
4185 sparc_regno_reg_class[i] = I64_REGS;
4186 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4187 sparc_regno_reg_class[i] = GENERAL_REGS;
4189 sparc_regno_reg_class[i] = FP_REGS;
4191 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4193 sparc_regno_reg_class[i] = FPCC_REGS;
4195 sparc_regno_reg_class[i] = NO_REGS;
4199 /* Compute the frame size required by the function. This function is called
4200 during the reload pass and also by sparc_expand_prologue. */
4203 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p)
4205 int outgoing_args_size = (current_function_outgoing_args_size
4206 + REG_PARM_STACK_SPACE (current_function_decl));
4207 int n_regs = 0; /* N_REGS is the number of 4-byte regs saved thus far. */
4212 for (i = 0; i < 8; i++)
4213 if (regs_ever_live[i] && ! call_used_regs[i])
4218 for (i = 0; i < 8; i += 2)
4219 if ((regs_ever_live[i] && ! call_used_regs[i])
4220 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4224 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4225 if ((regs_ever_live[i] && ! call_used_regs[i])
4226 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4229 /* Set up values for use in prologue and epilogue. */
4230 num_gfregs = n_regs;
4235 && current_function_outgoing_args_size == 0)
4236 actual_fsize = apparent_fsize = 0;
4239 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4240 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4241 apparent_fsize += n_regs * 4;
4242 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4245 /* Make sure nothing can clobber our register windows.
4246 If a SAVE must be done, or there is a stack-local variable,
4247 the register window area must be allocated.
4248 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4249 if (! leaf_function_p || size > 0)
4250 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4252 return SPARC_STACK_ALIGN (actual_fsize);
4255 /* Output any necessary .register pseudo-ops. */
4258 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4260 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4266 /* Check if %g[2367] were used without
4267 .register being printed for them already. */
4268 for (i = 2; i < 8; i++)
4270 if (regs_ever_live [i]
4271 && ! sparc_hard_reg_printed [i])
4273 sparc_hard_reg_printed [i] = 1;
4274 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4281 /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
4282 as needed. LOW should be double-word aligned for 32-bit registers.
4283 Return the new OFFSET. */
4286 #define SORR_RESTORE 1
4289 save_or_restore_regs (int low, int high, rtx base, int offset, int action)
4294 if (TARGET_ARCH64 && high <= 32)
4296 for (i = low; i < high; i++)
4298 if (regs_ever_live[i] && ! call_used_regs[i])
4300 mem = gen_rtx_MEM (DImode, plus_constant (base, offset));
4301 set_mem_alias_set (mem, sparc_sr_alias_set);
4302 if (action == SORR_SAVE)
4304 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
4305 RTX_FRAME_RELATED_P (insn) = 1;
4307 else /* action == SORR_RESTORE */
4308 emit_move_insn (gen_rtx_REG (DImode, i), mem);
4315 for (i = low; i < high; i += 2)
4317 bool reg0 = regs_ever_live[i] && ! call_used_regs[i];
4318 bool reg1 = regs_ever_live[i+1] && ! call_used_regs[i+1];
4319 enum machine_mode mode;
4324 mode = i < 32 ? DImode : DFmode;
4329 mode = i < 32 ? SImode : SFmode;
4334 mode = i < 32 ? SImode : SFmode;
4341 mem = gen_rtx_MEM (mode, plus_constant (base, offset));
4342 set_mem_alias_set (mem, sparc_sr_alias_set);
4343 if (action == SORR_SAVE)
4345 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4346 RTX_FRAME_RELATED_P (insn) = 1;
4348 else /* action == SORR_RESTORE */
4349 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4351 /* Always preserve double-word alignment. */
4352 offset = (offset + 7) & -8;
4359 /* Emit code to save call-saved registers. */
4362 emit_save_regs (void)
4364 HOST_WIDE_INT offset;
4367 offset = frame_base_offset - apparent_fsize;
4369 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4371 /* ??? This might be optimized a little as %g1 might already have a
4372 value close enough that a single add insn will do. */
4373 /* ??? Although, all of this is probably only a temporary fix
4374 because if %g1 can hold a function result, then
4375 sparc_expand_epilogue will lose (the result will be
4377 base = gen_rtx_REG (Pmode, 1);
4378 emit_move_insn (base, GEN_INT (offset));
4379 emit_insn (gen_rtx_SET (VOIDmode,
4381 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4385 base = frame_base_reg;
4387 offset = save_or_restore_regs (0, 8, base, offset, SORR_SAVE);
4388 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_SAVE);
4391 /* Emit code to restore call-saved registers. */
4394 emit_restore_regs (void)
4396 HOST_WIDE_INT offset;
4399 offset = frame_base_offset - apparent_fsize;
4401 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4403 base = gen_rtx_REG (Pmode, 1);
4404 emit_move_insn (base, GEN_INT (offset));
4405 emit_insn (gen_rtx_SET (VOIDmode,
4407 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4411 base = frame_base_reg;
4413 offset = save_or_restore_regs (0, 8, base, offset, SORR_RESTORE);
4414 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_RESTORE);
4417 /* Emit an increment for the stack pointer. */
4420 emit_stack_pointer_increment (rtx increment)
4423 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, increment));
4425 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, increment));
4428 /* Emit a decrement for the stack pointer. */
4431 emit_stack_pointer_decrement (rtx decrement)
4434 emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, decrement));
4436 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, decrement));
4439 /* Expand the function prologue. The prologue is responsible for reserving
4440 storage for the frame, saving the call-saved registers and loading the
4441 PIC register if needed. */
4444 sparc_expand_prologue (void)
4446 int leaf_function_p = current_function_uses_only_leaf_regs;
4448 /* Need to use actual_fsize, since we are also allocating
4449 space for our callee (and our own register save area). */
4450 actual_fsize = sparc_compute_frame_size (get_frame_size(), leaf_function_p);
4452 if (leaf_function_p)
4454 frame_base_reg = stack_pointer_rtx;
4455 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4459 frame_base_reg = hard_frame_pointer_rtx;
4460 frame_base_offset = SPARC_STACK_BIAS;
4463 if (actual_fsize == 0)
4465 else if (leaf_function_p)
4467 if (actual_fsize <= 4096)
4468 emit_stack_pointer_increment (GEN_INT (- actual_fsize));
4469 else if (actual_fsize <= 8192)
4471 emit_stack_pointer_increment (GEN_INT (-4096));
4472 emit_stack_pointer_increment (GEN_INT (4096 - actual_fsize));
4476 rtx reg = gen_rtx_REG (Pmode, 1);
4477 emit_move_insn (reg, GEN_INT (-actual_fsize));
4478 emit_stack_pointer_increment (reg);
4483 if (actual_fsize <= 4096)
4484 emit_insn (gen_save_register_window (GEN_INT (-actual_fsize)));
4485 else if (actual_fsize <= 8192)
4487 emit_insn (gen_save_register_window (GEN_INT (-4096)));
4488 emit_stack_pointer_increment (GEN_INT (4096 - actual_fsize));
4492 rtx reg = gen_rtx_REG (Pmode, 1);
4493 emit_move_insn (reg, GEN_INT (-actual_fsize));
4494 emit_insn (gen_save_register_window (reg));
4498 /* Call-saved registers are saved just above the outgoing argument area. */
4502 /* Load the PIC register if needed. */
4503 if (flag_pic && current_function_uses_pic_offset_table)
4504 load_pic_register ();
4507 /* This function generates the assembly code for function entry, which boils
4508 down to emitting the necessary .register directives. It also informs the
4509 DWARF-2 back-end on the layout of the frame.
4511 ??? Historical cruft: "On SPARC, move-double insns between fpu and cpu need
4512 an 8-byte block of memory. If any fpu reg is used in the function, we
4513 allocate such a block here, at the bottom of the frame, just in case it's
4514 needed." Could this explain the -8 in emit_restore_regs? */
4517 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4519 int leaf_function_p = current_function_uses_only_leaf_regs;
4521 sparc_output_scratch_registers (file);
4523 if (dwarf2out_do_frame () && actual_fsize)
4525 char *label = dwarf2out_cfi_label ();
4527 /* The canonical frame address refers to the top of the frame. */
4528 dwarf2out_def_cfa (label,
4530 ? STACK_POINTER_REGNUM
4531 : HARD_FRAME_POINTER_REGNUM,
4534 if (! leaf_function_p)
4536 /* Note the register window save. This tells the unwinder that
4537 it needs to restore the window registers from the previous
4538 frame's window save area at 0(cfa). */
4539 dwarf2out_window_save (label);
4541 /* The return address (-8) is now in %i7. */
4542 dwarf2out_return_reg (label, 31);
4547 /* Expand the function epilogue, either normal or part of a sibcall.
4548 We emit all the instructions except the return or the call. */
4551 sparc_expand_epilogue (void)
4553 int leaf_function_p = current_function_uses_only_leaf_regs;
4556 emit_restore_regs ();
4558 if (actual_fsize == 0)
4560 else if (leaf_function_p)
4562 if (actual_fsize <= 4096)
4563 emit_stack_pointer_decrement (GEN_INT (- actual_fsize));
4564 else if (actual_fsize <= 8192)
4566 emit_stack_pointer_decrement (GEN_INT (-4096));
4567 emit_stack_pointer_decrement (GEN_INT (4096 - actual_fsize));
4571 rtx reg = gen_rtx_REG (Pmode, 1);
4572 emit_move_insn (reg, GEN_INT (-actual_fsize));
4573 emit_stack_pointer_decrement (reg);
4578 /* This function generates the assembly code for function exit. */
4581 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4583 /* If code does not drop into the epilogue, we have to still output
4584 a dummy nop for the sake of sane backtraces. Otherwise, if the
4585 last two instructions of a function were "call foo; dslot;" this
4586 can make the return PC of foo (ie. address of call instruction
4587 plus 8) point to the first instruction in the next function. */
4589 rtx insn, last_real_insn;
4591 insn = get_last_insn ();
4593 last_real_insn = prev_real_insn (insn);
4595 && GET_CODE (last_real_insn) == INSN
4596 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4597 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4599 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4600 fputs("\tnop\n", file);
4602 sparc_output_deferred_case_vectors ();
4605 /* Output a 'restore' instruction. */
4608 output_restore (rtx pat)
4614 fputs ("\t restore\n", asm_out_file);
4618 if (GET_CODE (pat) != SET)
4621 operands[0] = SET_DEST (pat);
4622 pat = SET_SRC (pat);
4624 switch (GET_CODE (pat))
4627 operands[1] = XEXP (pat, 0);
4628 operands[2] = XEXP (pat, 1);
4629 output_asm_insn (" restore %r1, %2, %Y0", operands);
4632 operands[1] = XEXP (pat, 0);
4633 operands[2] = XEXP (pat, 1);
4634 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4637 operands[1] = XEXP (pat, 0);
4638 if (XEXP (pat, 1) != const1_rtx)
4640 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4644 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4649 /* Output a return. */
4652 output_return (rtx insn)
4654 int leaf_function_p = current_function_uses_only_leaf_regs;
4655 bool delay_slot_filled_p = dbr_sequence_length () > 0;
4656 /* True if the caller has placed an "unimp" insn immediately after the call.
4657 This insn is used in the 32-bit ABI when calling a function that returns
4658 a non zero-sized structure. The 64-bit ABI doesn't have it. Be careful
4659 to have this test be the same as that used on the call. */
4660 bool sparc_skip_caller_unimp
4662 && current_function_returns_struct
4663 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
4665 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl)));
4667 if (leaf_function_p)
4669 /* This is a leaf function so we don't have to bother restoring the
4670 register window, which frees us from dealing with the convoluted
4671 semantics of restore/return. We simply output the jump to the
4672 return address and the insn in the delay slot, which usually is
4673 the substraction restoring the stack pointer %sp. */
4675 if (current_function_calls_eh_return)
4678 fprintf (asm_out_file, "\tjmp\t%%o7+%d\n", sparc_skip_caller_unimp ? 12 : 8);
4680 if (delay_slot_filled_p)
4682 rtx delay = NEXT_INSN (insn);
4686 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4687 PATTERN (delay) = gen_blockage ();
4688 INSN_CODE (delay) = -1;
4691 fputs ("\t nop\n", asm_out_file);
4695 /* This is a regular function so we have to restore the register window.
4696 We may have a pending insn for the delay slot, which will be either
4697 combined with the 'restore' instruction or put in the delay slot of
4698 the 'return' instruction. */
4700 if (current_function_calls_eh_return)
4702 /* If the function uses __builtin_eh_return, the eh_return
4703 machinery occupies the delay slot. */
4704 if (delay_slot_filled_p || sparc_skip_caller_unimp)
4707 if (! flag_delayed_branch)
4708 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file);
4711 fputs ("\treturn\t%i7+8\n", asm_out_file);
4713 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file);
4715 if (flag_delayed_branch)
4716 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
4718 fputs ("\t nop\n", asm_out_file);
4720 else if (delay_slot_filled_p)
4724 delay = NEXT_INSN (insn);
4728 pat = PATTERN (delay);
4730 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
4732 epilogue_renumber (&pat, 0);
4733 fprintf (asm_out_file, "\treturn\t%%i7+%d\n",
4734 sparc_skip_caller_unimp ? 12 : 8);
4735 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4739 fprintf (asm_out_file, "\tjmp\t%%i7+%d\n",
4740 sparc_skip_caller_unimp ? 12 : 8);
4741 output_restore (pat);
4744 PATTERN (delay) = gen_blockage ();
4745 INSN_CODE (delay) = -1;
4749 /* The delay slot is empty. */
4751 fprintf (asm_out_file, "\treturn\t%%i7+%d\n\t nop\n",
4752 sparc_skip_caller_unimp ? 12 : 8);
4753 else if (flag_delayed_branch)
4754 fprintf (asm_out_file, "\tjmp\t%%i7+%d\n\t restore\n",
4755 sparc_skip_caller_unimp ? 12 : 8);
4757 fprintf (asm_out_file, "\trestore\n\tjmp\t%%o7+%d\n\t nop\n",
4758 sparc_skip_caller_unimp ? 12 : 8);
4765 /* Output a sibling call. */
4768 output_sibcall (rtx insn, rtx call_operand)
4770 int leaf_function_p = current_function_uses_only_leaf_regs;
4771 bool delay_slot_filled_p = dbr_sequence_length () > 0;
4774 if (! flag_delayed_branch)
4777 operands[0] = call_operand;
4779 if (leaf_function_p)
4781 /* This is a leaf function so we don't have to bother restoring the
4782 register window. We simply output the jump to the function and
4783 the insn in the delay slot (if any). */
4785 if (LEAF_SIBCALL_SLOT_RESERVED_P && delay_slot_filled_p)
4788 if (delay_slot_filled_p)
4790 rtx delay = NEXT_INSN (insn);
4794 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4795 output_asm_insn ("jmp\t%%g1 + %%lo(%a0)", operands);
4796 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4798 PATTERN (delay) = gen_blockage ();
4799 INSN_CODE (delay) = -1;
4803 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4804 it into branch if possible. */
4805 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4806 output_asm_insn ("call\t%a0, 0", operands);
4807 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4812 /* This is a regular function so we have to restore the register window.
4813 We may have a pending insn for the delay slot, which will be combined
4814 with the 'restore' instruction. */
4816 output_asm_insn ("call\t%a0, 0", operands);
4818 if (delay_slot_filled_p)
4820 rtx delay = NEXT_INSN (insn);
4824 output_restore (PATTERN (delay));
4826 PATTERN (delay) = gen_blockage ();
4827 INSN_CODE (delay) = -1;
4830 output_restore (NULL_RTX);
4836 /* Functions for handling argument passing.
4838 For 32-bit, the first 6 args are normally in registers and the rest are
4839 pushed. Any arg that starts within the first 6 words is at least
4840 partially passed in a register unless its data type forbids.
4842 For 64-bit, the argument registers are laid out as an array of 16 elements
4843 and arguments are added sequentially. The first 6 int args and up to the
4844 first 16 fp args (depending on size) are passed in regs.
4846 Slot Stack Integral Float Float in structure Double Long Double
4847 ---- ----- -------- ----- ------------------ ------ -----------
4848 15 [SP+248] %f31 %f30,%f31 %d30
4849 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4850 13 [SP+232] %f27 %f26,%f27 %d26
4851 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4852 11 [SP+216] %f23 %f22,%f23 %d22
4853 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4854 9 [SP+200] %f19 %f18,%f19 %d18
4855 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4856 7 [SP+184] %f15 %f14,%f15 %d14
4857 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4858 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4859 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4860 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4861 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4862 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4863 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4865 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4867 Integral arguments are always passed as 64-bit quantities appropriately
4870 Passing of floating point values is handled as follows.
4871 If a prototype is in scope:
4872 If the value is in a named argument (i.e. not a stdarg function or a
4873 value not part of the `...') then the value is passed in the appropriate
4875 If the value is part of the `...' and is passed in one of the first 6
4876 slots then the value is passed in the appropriate int reg.
4877 If the value is part of the `...' and is not passed in one of the first 6
4878 slots then the value is passed in memory.
4879 If a prototype is not in scope:
4880 If the value is one of the first 6 arguments the value is passed in the
4881 appropriate integer reg and the appropriate fp reg.
4882 If the value is not one of the first 6 arguments the value is passed in
4883 the appropriate fp reg and in memory.
4886 Summary of the calling conventions implemented by GCC on SPARC:
4889 size argument return value
4891 small integer <4 int. reg. int. reg.
4892 word 4 int. reg. int. reg.
4893 double word 8 int. reg. int. reg.
4895 _Complex small integer <8 int. reg. int. reg.
4896 _Complex word 8 int. reg. int. reg.
4897 _Complex double word 16 memory int. reg.
4899 vector integer <=8 int. reg. FP reg.
4900 vector integer >8 memory memory
4902 float 4 int. reg. FP reg.
4903 double 8 int. reg. FP reg.
4904 long double 16 memory memory
4906 _Complex float 8 memory FP reg.
4907 _Complex double 16 memory FP reg.
4908 _Complex long double 32 memory FP reg.
4910 vector float <=32 memory FP reg.
4911 vector float >32 memory memory
4913 aggregate any memory memory
4918 size argument return value
4920 small integer <8 int. reg. int. reg.
4921 word 8 int. reg. int. reg.
4922 double word 16 int. reg. int. reg.
4924 _Complex small integer <16 int. reg. int. reg.
4925 _Complex word 16 int. reg. int. reg.
4926 _Complex double word 32 memory int. reg.
4928 vector integer <=16 FP reg. FP reg.
4929 vector integer 16<s<=32 memory FP reg.
4930 vector integer >32 memory memory
4932 float 4 FP reg. FP reg.
4933 double 8 FP reg. FP reg.
4934 long double 16 FP reg. FP reg.
4936 _Complex float 8 FP reg. FP reg.
4937 _Complex double 16 FP reg. FP reg.
4938 _Complex long double 32 memory FP reg.
4940 vector float <=16 FP reg. FP reg.
4941 vector float 16<s<=32 memory FP reg.
4942 vector float >32 memory memory
4944 aggregate <=16 reg. reg.
4945 aggregate 16<s<=32 memory reg.
4946 aggregate >32 memory memory
4950 Note #1: complex floating-point types follow the extended SPARC ABIs as
4951 implemented by the Sun compiler.
4953 Note #2: integral vector types follow the scalar floating-point types
4954 conventions to match what is implemented by the Sun VIS SDK.
4956 Note #3: floating-point vector types follow the complex floating-point
4957 types conventions. */
4960 /* Maximum number of int regs for args. */
4961 #define SPARC_INT_ARG_MAX 6
4962 /* Maximum number of fp regs for args. */
4963 #define SPARC_FP_ARG_MAX 16
4965 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4967 /* Handle the INIT_CUMULATIVE_ARGS macro.
4968 Initialize a variable CUM of type CUMULATIVE_ARGS
4969 for a call to a function whose data type is FNTYPE.
4970 For a library call, FNTYPE is 0. */
4973 init_cumulative_args (struct sparc_args *cum, tree fntype,
4974 rtx libname ATTRIBUTE_UNUSED,
4975 tree fndecl ATTRIBUTE_UNUSED)
4978 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4979 cum->libcall_p = fntype == 0;
4982 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
4983 When a prototype says `char' or `short', really pass an `int'. */
4986 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
4988 return TARGET_ARCH32 ? true : false;
4991 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
4994 sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4996 return TARGET_ARCH64 ? true : false;
4999 /* Scan the record type TYPE and return the following predicates:
5000 - INTREGS_P: the record contains at least one field or sub-field
5001 that is eligible for promotion in integer registers.
5002 - FP_REGS_P: the record contains at least one field or sub-field
5003 that is eligible for promotion in floating-point registers.
5004 - PACKED_P: the record contains at least one field that is packed.
5006 Sub-fields are not taken into account for the PACKED_P predicate. */
5009 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
5013 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5015 if (TREE_CODE (field) == FIELD_DECL)
5017 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5018 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
5019 else if (FLOAT_TYPE_P (TREE_TYPE (field)) && TARGET_FPU)
5024 if (packed_p && DECL_PACKED (field))
5030 /* Compute the slot number to pass an argument in.
5031 Return the slot number or -1 if passing on the stack.
5033 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5034 the preceding args and about the function being called.
5035 MODE is the argument's machine mode.
5036 TYPE is the data type of the argument (as a tree).
5037 This is null for libcalls where that information may
5039 NAMED is nonzero if this argument is a named parameter
5040 (otherwise it is an extra parameter matching an ellipsis).
5041 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5042 *PREGNO records the register number to use if scalar type.
5043 *PPADDING records the amount of padding needed in words. */
5046 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
5047 tree type, int named, int incoming_p,
5048 int *pregno, int *ppadding)
5050 int regbase = (incoming_p
5051 ? SPARC_INCOMING_INT_ARG_FIRST
5052 : SPARC_OUTGOING_INT_ARG_FIRST);
5053 int slotno = cum->words;
5058 if (type && TREE_ADDRESSABLE (type))
5064 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5067 /* For SPARC64, objects requiring 16-byte alignment get it. */
5069 && GET_MODE_ALIGNMENT (mode) >= 2 * BITS_PER_WORD
5070 && (slotno & 1) != 0)
5071 slotno++, *ppadding = 1;
5073 switch (GET_MODE_CLASS (mode))
5076 case MODE_COMPLEX_FLOAT:
5077 case MODE_VECTOR_INT:
5078 case MODE_VECTOR_FLOAT:
5079 if (TARGET_ARCH64 && TARGET_FPU && named)
5081 if (slotno >= SPARC_FP_ARG_MAX)
5083 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5084 /* Arguments filling only one single FP register are
5085 right-justified in the outer double FP register. */
5086 if (GET_MODE_SIZE (mode) <= 4)
5093 case MODE_COMPLEX_INT:
5094 if (slotno >= SPARC_INT_ARG_MAX)
5096 regno = regbase + slotno;
5100 if (mode == VOIDmode)
5101 /* MODE is VOIDmode when generating the actual call. */
5104 if (mode != BLKmode)
5107 /* For SPARC64, objects requiring 16-byte alignment get it. */
5110 && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5111 && (slotno & 1) != 0)
5112 slotno++, *ppadding = 1;
5114 if (TARGET_ARCH32 || (type && TREE_CODE (type) == UNION_TYPE))
5116 if (slotno >= SPARC_INT_ARG_MAX)
5118 regno = regbase + slotno;
5120 else /* TARGET_ARCH64 && type && TREE_CODE (type) == RECORD_TYPE */
5122 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5124 /* First see what kinds of registers we would need. */
5125 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5127 /* The ABI obviously doesn't specify how packed structures
5128 are passed. These are defined to be passed in int regs
5129 if possible, otherwise memory. */
5130 if (packed_p || !named)
5131 fpregs_p = 0, intregs_p = 1;
5133 /* If all arg slots are filled, then must pass on stack. */
5134 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5137 /* If there are only int args and all int arg slots are filled,
5138 then must pass on stack. */
5139 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5142 /* Note that even if all int arg slots are filled, fp members may
5143 still be passed in regs if such regs are available.
5144 *PREGNO isn't set because there may be more than one, it's up
5145 to the caller to compute them. */
5158 /* Handle recursive register counting for structure field layout. */
5160 struct function_arg_record_value_parms
5162 rtx ret; /* return expression being built. */
5163 int slotno; /* slot number of the argument. */
5164 int named; /* whether the argument is named. */
5165 int regbase; /* regno of the base register. */
5166 int stack; /* 1 if part of the argument is on the stack. */
5167 int intoffset; /* offset of the first pending integer field. */
5168 unsigned int nregs; /* number of words passed in registers. */
5171 static void function_arg_record_value_3
5172 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5173 static void function_arg_record_value_2
5174 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5175 static void function_arg_record_value_1
5176 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5177 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
5178 static rtx function_arg_union_value (int, enum machine_mode, int);
5180 /* A subroutine of function_arg_record_value. Traverse the structure
5181 recursively and determine how many registers will be required. */
5184 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
5185 struct function_arg_record_value_parms *parms,
5190 /* We need to compute how many registers are needed so we can
5191 allocate the PARALLEL but before we can do that we need to know
5192 whether there are any packed fields. The ABI obviously doesn't
5193 specify how structures are passed in this case, so they are
5194 defined to be passed in int regs if possible, otherwise memory,
5195 regardless of whether there are fp values present. */
5198 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5200 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5207 /* Compute how many registers we need. */
5208 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5210 if (TREE_CODE (field) == FIELD_DECL)
5212 HOST_WIDE_INT bitpos = startbitpos;
5214 if (DECL_SIZE (field) != 0
5215 && host_integerp (bit_position (field), 1))
5216 bitpos += int_bit_position (field);
5218 /* ??? FIXME: else assume zero offset. */
5220 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5221 function_arg_record_value_1 (TREE_TYPE (field),
5225 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5226 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5231 if (parms->intoffset != -1)
5233 unsigned int startbit, endbit;
5234 int intslots, this_slotno;
5236 startbit = parms->intoffset & -BITS_PER_WORD;
5237 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5239 intslots = (endbit - startbit) / BITS_PER_WORD;
5240 this_slotno = parms->slotno + parms->intoffset
5243 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5245 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5246 /* We need to pass this field on the stack. */
5250 parms->nregs += intslots;
5251 parms->intoffset = -1;
5254 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5255 If it wasn't true we wouldn't be here. */
5257 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5262 if (parms->intoffset == -1)
5263 parms->intoffset = bitpos;
5269 /* A subroutine of function_arg_record_value. Assign the bits of the
5270 structure between parms->intoffset and bitpos to integer registers. */
5273 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5274 struct function_arg_record_value_parms *parms)
5276 enum machine_mode mode;
5278 unsigned int startbit, endbit;
5279 int this_slotno, intslots, intoffset;
5282 if (parms->intoffset == -1)
5285 intoffset = parms->intoffset;
5286 parms->intoffset = -1;
5288 startbit = intoffset & -BITS_PER_WORD;
5289 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5290 intslots = (endbit - startbit) / BITS_PER_WORD;
5291 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5293 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5297 /* If this is the trailing part of a word, only load that much into
5298 the register. Otherwise load the whole register. Note that in
5299 the latter case we may pick up unwanted bits. It's not a problem
5300 at the moment but may wish to revisit. */
5302 if (intoffset % BITS_PER_WORD != 0)
5303 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5308 intoffset /= BITS_PER_UNIT;
5311 regno = parms->regbase + this_slotno;
5312 reg = gen_rtx_REG (mode, regno);
5313 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5314 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5317 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5322 while (intslots > 0);
5325 /* A subroutine of function_arg_record_value. Traverse the structure
5326 recursively and assign bits to floating point registers. Track which
5327 bits in between need integer registers; invoke function_arg_record_value_3
5328 to make that happen. */
5331 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5332 struct function_arg_record_value_parms *parms,
5338 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5340 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5347 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5349 if (TREE_CODE (field) == FIELD_DECL)
5351 HOST_WIDE_INT bitpos = startbitpos;
5353 if (DECL_SIZE (field) != 0
5354 && host_integerp (bit_position (field), 1))
5355 bitpos += int_bit_position (field);
5357 /* ??? FIXME: else assume zero offset. */
5359 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5360 function_arg_record_value_2 (TREE_TYPE (field),
5364 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5365 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5370 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5372 enum machine_mode mode = DECL_MODE (field);
5375 function_arg_record_value_3 (bitpos, parms);
5378 case SCmode: mode = SFmode; break;
5379 case DCmode: mode = DFmode; break;
5380 case TCmode: mode = TFmode; break;
5383 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
5384 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
5386 reg = gen_rtx_REG (mode, regno);
5387 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5388 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5389 GEN_INT (bitpos / BITS_PER_UNIT));
5391 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5393 regno += GET_MODE_SIZE (mode) / 4;
5394 reg = gen_rtx_REG (mode, regno);
5395 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5396 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5397 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5404 if (parms->intoffset == -1)
5405 parms->intoffset = bitpos;
5411 /* Used by function_arg and function_value to implement the complex
5412 conventions of the 64-bit ABI for passing and returning structures.
5413 Return an expression valid as a return value for the two macros
5414 FUNCTION_ARG and FUNCTION_VALUE.
5416 TYPE is the data type of the argument (as a tree).
5417 This is null for libcalls where that information may
5419 MODE is the argument's machine mode.
5420 SLOTNO is the index number of the argument's slot in the parameter array.
5421 NAMED is nonzero if this argument is a named parameter
5422 (otherwise it is an extra parameter matching an ellipsis).
5423 REGBASE is the regno of the base register for the parameter array. */
5426 function_arg_record_value (tree type, enum machine_mode mode,
5427 int slotno, int named, int regbase)
5429 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5430 struct function_arg_record_value_parms parms;
5433 parms.ret = NULL_RTX;
5434 parms.slotno = slotno;
5435 parms.named = named;
5436 parms.regbase = regbase;
5439 /* Compute how many registers we need. */
5441 parms.intoffset = 0;
5442 function_arg_record_value_1 (type, 0, &parms, false);
5444 /* Take into account pending integer fields. */
5445 if (parms.intoffset != -1)
5447 unsigned int startbit, endbit;
5448 int intslots, this_slotno;
5450 startbit = parms.intoffset & -BITS_PER_WORD;
5451 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5452 intslots = (endbit - startbit) / BITS_PER_WORD;
5453 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5455 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5457 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5458 /* We need to pass this field on the stack. */
5462 parms.nregs += intslots;
5464 nregs = parms.nregs;
5466 /* Allocate the vector and handle some annoying special cases. */
5469 /* ??? Empty structure has no value? Duh? */
5472 /* Though there's nothing really to store, return a word register
5473 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5474 leads to breakage due to the fact that there are zero bytes to
5476 return gen_rtx_REG (mode, regbase);
5480 /* ??? C++ has structures with no fields, and yet a size. Give up
5481 for now and pass everything back in integer registers. */
5482 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5484 if (nregs + slotno > SPARC_INT_ARG_MAX)
5485 nregs = SPARC_INT_ARG_MAX - slotno;
5490 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5492 /* If at least one field must be passed on the stack, generate
5493 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5494 also be passed on the stack. We can't do much better because the
5495 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5496 of structures for which the fields passed exclusively in registers
5497 are not at the beginning of the structure. */
5499 XVECEXP (parms.ret, 0, 0)
5500 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5502 /* Fill in the entries. */
5504 parms.intoffset = 0;
5505 function_arg_record_value_2 (type, 0, &parms, false);
5506 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5508 if (parms.nregs != nregs)
5514 /* Used by function_arg and function_value to implement the conventions
5515 of the 64-bit ABI for passing and returning unions.
5516 Return an expression valid as a return value for the two macros
5517 FUNCTION_ARG and FUNCTION_VALUE.
5519 SIZE is the size in bytes of the union.
5520 MODE is the argument's machine mode.
5521 REGNO is the hard register the union will be passed in. */
5524 function_arg_union_value (int size, enum machine_mode mode, int regno)
5526 int nwords = ROUND_ADVANCE (size), i;
5529 /* Unions are passed left-justified. */
5530 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
5532 for (i = 0; i < nwords; i++)
5533 XVECEXP (regs, 0, i)
5534 = gen_rtx_EXPR_LIST (VOIDmode,
5535 gen_rtx_REG (word_mode, regno + i),
5536 GEN_INT (UNITS_PER_WORD * i));
5541 /* Handle the FUNCTION_ARG macro.
5542 Determine where to put an argument to a function.
5543 Value is zero to push the argument on the stack,
5544 or a hard register in which to store the argument.
5546 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5547 the preceding args and about the function being called.
5548 MODE is the argument's machine mode.
5549 TYPE is the data type of the argument (as a tree).
5550 This is null for libcalls where that information may
5552 NAMED is nonzero if this argument is a named parameter
5553 (otherwise it is an extra parameter matching an ellipsis).
5554 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5557 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5558 tree type, int named, int incoming_p)
5560 int regbase = (incoming_p
5561 ? SPARC_INCOMING_INT_ARG_FIRST
5562 : SPARC_OUTGOING_INT_ARG_FIRST);
5563 int slotno, regno, padding;
5566 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5574 reg = gen_rtx_REG (mode, regno);
5578 if (type && TREE_CODE (type) == RECORD_TYPE)
5580 /* Structures up to 16 bytes in size are passed in arg slots on the
5581 stack and are promoted to registers where possible. */
5583 if (int_size_in_bytes (type) > 16)
5584 abort (); /* shouldn't get here */
5586 return function_arg_record_value (type, mode, slotno, named, regbase);
5588 else if (type && TREE_CODE (type) == UNION_TYPE)
5590 HOST_WIDE_INT size = int_size_in_bytes (type);
5593 abort (); /* shouldn't get here */
5595 return function_arg_union_value (size, mode, regno);
5597 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5598 but also have the slot allocated for them.
5599 If no prototype is in scope fp values in register slots get passed
5600 in two places, either fp regs and int regs or fp regs and memory. */
5601 else if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5602 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5603 || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
5604 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
5605 && SPARC_FP_REG_P (regno))
5607 reg = gen_rtx_REG (mode, regno);
5608 if (cum->prototype_p || cum->libcall_p)
5610 /* "* 2" because fp reg numbers are recorded in 4 byte
5613 /* ??? This will cause the value to be passed in the fp reg and
5614 in the stack. When a prototype exists we want to pass the
5615 value in the reg but reserve space on the stack. That's an
5616 optimization, and is deferred [for a bit]. */
5617 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5618 return gen_rtx_PARALLEL (mode,
5620 gen_rtx_EXPR_LIST (VOIDmode,
5621 NULL_RTX, const0_rtx),
5622 gen_rtx_EXPR_LIST (VOIDmode,
5626 /* ??? It seems that passing back a register even when past
5627 the area declared by REG_PARM_STACK_SPACE will allocate
5628 space appropriately, and will not copy the data onto the
5629 stack, exactly as we desire.
5631 This is due to locate_and_pad_parm being called in
5632 expand_call whenever reg_parm_stack_space > 0, which
5633 while beneficial to our example here, would seem to be
5634 in error from what had been intended. Ho hum... -- r~ */
5642 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5646 /* On incoming, we don't need to know that the value
5647 is passed in %f0 and %i0, and it confuses other parts
5648 causing needless spillage even on the simplest cases. */
5652 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5653 + (regno - SPARC_FP_ARG_FIRST) / 2);
5655 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5656 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5658 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5662 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5663 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5664 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5670 /* Scalar or complex int. */
5671 reg = gen_rtx_REG (mode, regno);
5677 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5678 For an arg passed partly in registers and partly in memory,
5679 this is the number of registers used.
5680 For args passed entirely in registers or entirely in memory, zero.
5682 Any arg that starts in the first 6 regs but won't entirely fit in them
5683 needs partial registers on v8. On v9, structures with integer
5684 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5685 values that begin in the last fp reg [where "last fp reg" varies with the
5686 mode] will be split between that reg and memory. */
5689 function_arg_partial_nregs (const struct sparc_args *cum,
5690 enum machine_mode mode, tree type, int named)
5692 int slotno, regno, padding;
5694 /* We pass 0 for incoming_p here, it doesn't matter. */
5695 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5702 if ((slotno + (mode == BLKmode
5703 ? ROUND_ADVANCE (int_size_in_bytes (type))
5704 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5705 > SPARC_INT_ARG_MAX)
5706 return SPARC_INT_ARG_MAX - slotno;
5710 /* We are guaranteed by function_arg_pass_by_reference that the size
5711 of the argument is not greater than 16 bytes, so we only need to
5712 return 1 if the argument is partially passed in registers. */
5714 if (type && AGGREGATE_TYPE_P (type))
5716 int size = int_size_in_bytes (type);
5718 if (size > UNITS_PER_WORD
5719 && slotno == SPARC_INT_ARG_MAX - 1)
5722 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5723 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5724 && ! (TARGET_FPU && named)))
5726 /* The complex types are passed as packed types. */
5727 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5728 && slotno == SPARC_INT_ARG_MAX - 1)
5731 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5733 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5742 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5743 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5744 quad-precision floats by invisible reference.
5745 v9: Aggregates greater than 16 bytes are passed by reference.
5746 For Pascal, also pass arrays by reference. */
5749 function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
5750 enum machine_mode mode, tree type,
5751 int named ATTRIBUTE_UNUSED)
5755 return ((type && AGGREGATE_TYPE_P (type))
5756 /* Extended ABI (as implemented by the Sun compiler) says
5757 that all complex floats are passed in memory. */
5759 /* Enforce the 2-word cap for passing arguments in registers.
5760 This affects CDImode, TFmode, DCmode, TCmode and large
5762 || GET_MODE_SIZE (mode) > 8);
5766 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5768 && AGGREGATE_TYPE_P (type)
5769 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
5770 /* Enforce the 2-word cap for passing arguments in registers.
5771 This affects CTImode, TCmode and large vector modes. */
5772 || GET_MODE_SIZE (mode) > 16);
5776 /* Handle the FUNCTION_ARG_ADVANCE macro.
5777 Update the data in CUM to advance over an argument
5778 of mode MODE and data type TYPE.
5779 TYPE is null for libcalls where that information may not be available. */
5782 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5783 tree type, int named)
5785 int slotno, regno, padding;
5787 /* We pass 0 for incoming_p here, it doesn't matter. */
5788 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5790 /* If register required leading padding, add it. */
5792 cum->words += padding;
5796 cum->words += (mode != BLKmode
5797 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5798 : ROUND_ADVANCE (int_size_in_bytes (type)));
5802 if (type && AGGREGATE_TYPE_P (type))
5804 int size = int_size_in_bytes (type);
5808 else if (size <= 16)
5810 else /* passed by reference */
5815 cum->words += (mode != BLKmode
5816 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5817 : ROUND_ADVANCE (int_size_in_bytes (type)));
5822 /* Handle the FUNCTION_ARG_PADDING macro.
5823 For the 64 bit ABI structs are always stored left shifted in their
5827 function_arg_padding (enum machine_mode mode, tree type)
5829 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5832 /* Fall back to the default. */
5833 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5836 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
5837 Specify whether to return the return value in memory. */
5840 sparc_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
5843 /* Original SPARC 32-bit ABI says that quad-precision floats
5844 and all structures are returned in memory. Extended ABI
5845 (as implemented by the Sun compiler) says that all complex
5846 floats are returned in registers (8 FP registers at most
5847 for '_Complex long double'). Return all complex integers
5848 in registers (4 at most for '_Complex long long'). */
5849 return (TYPE_MODE (type) == BLKmode
5850 || TYPE_MODE (type) == TFmode
5851 /* Integral vector types follow the scalar FP types conventions. */
5852 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_INT
5853 && GET_MODE_SIZE (TYPE_MODE (type)) > 8)
5854 /* FP vector types follow the complex FP types conventions. */
5855 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_FLOAT
5856 && GET_MODE_SIZE (TYPE_MODE (type)) > 32));
5858 /* Original SPARC 64-bit ABI says that structures and unions
5859 smaller than 32 bytes are returned in registers. Extended
5860 ABI (as implemented by the Sun compiler) says that all complex
5861 floats are returned in registers (8 FP registers at most
5862 for '_Complex long double'). Return all complex integers
5863 in registers (4 at most for '_Complex TItype'). */
5864 return ((TYPE_MODE (type) == BLKmode
5865 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32)
5866 || GET_MODE_SIZE (TYPE_MODE (type)) > 32);
5869 /* Handle the TARGET_STRUCT_VALUE target hook.
5870 Return where to find the structure return value address. */
5873 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED, int incoming)
5880 return gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx,
5881 STRUCT_VALUE_OFFSET));
5883 return gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx,
5884 STRUCT_VALUE_OFFSET));
5888 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5889 For v9, function return values are subject to the same rules as arguments,
5890 except that up to 32 bytes may be returned in registers. */
5893 function_value (tree type, enum machine_mode mode, int incoming_p)
5895 /* Beware that the two values are swapped here wrt function_arg. */
5896 int regbase = (incoming_p
5897 ? SPARC_OUTGOING_INT_ARG_FIRST
5898 : SPARC_INCOMING_INT_ARG_FIRST);
5901 if (TARGET_ARCH64 && type)
5903 if (TREE_CODE (type) == RECORD_TYPE)
5905 /* Structures up to 32 bytes in size are passed in registers,
5906 promoted to fp registers where possible. */
5908 if (int_size_in_bytes (type) > 32)
5909 abort (); /* shouldn't get here */
5911 return function_arg_record_value (type, mode, 0, 1, regbase);
5913 else if (TREE_CODE (type) == UNION_TYPE)
5915 HOST_WIDE_INT size = int_size_in_bytes (type);
5918 abort (); /* shouldn't get here */
5920 return function_arg_union_value (size, mode, regbase);
5922 else if (AGGREGATE_TYPE_P (type))
5924 /* All other aggregate types are passed in an integer register
5925 in a mode corresponding to the size of the type. */
5926 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5929 abort (); /* shouldn't get here */
5931 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5933 /* ??? We probably should have made the same ABI change in
5934 3.4.0 as the one we made for unions. The latter was
5935 required by the SCD though, while the former is not
5936 specified, so we favored compatibility and efficiency.
5938 Now we're stuck for aggregates larger than 16 bytes,
5939 because OImode vanished in the meantime. Let's not
5940 try to be unduly clever, and simply follow the ABI
5941 for unions in that case. */
5942 if (mode == BLKmode)
5943 return function_arg_union_value (bytes, mode, regbase);
5945 else if (GET_MODE_CLASS (mode) == MODE_INT
5946 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5950 if (TARGET_FPU && (FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)))
5951 regno = SPARC_FP_ARG_FIRST;
5955 return gen_rtx_REG (mode, regno);
5958 /* Do what is necessary for `va_start'. We look at the current function
5959 to determine if stdarg or varargs is used and return the address of
5960 the first unnamed parameter. */
5963 sparc_builtin_saveregs (void)
5965 int first_reg = current_function_args_info.words;
5969 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
5970 emit_move_insn (gen_rtx_MEM (word_mode,
5971 gen_rtx_PLUS (Pmode,
5973 GEN_INT (FIRST_PARM_OFFSET (0)
5976 gen_rtx_REG (word_mode,
5977 SPARC_INCOMING_INT_ARG_FIRST + regno));
5979 address = gen_rtx_PLUS (Pmode,
5981 GEN_INT (FIRST_PARM_OFFSET (0)
5982 + UNITS_PER_WORD * first_reg));
5987 /* Implement `va_start' for stdarg. */
5990 sparc_va_start (tree valist, rtx nextarg)
5992 nextarg = expand_builtin_saveregs ();
5993 std_expand_builtin_va_start (valist, nextarg);
5996 /* Implement `va_arg' for stdarg. */
5999 sparc_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6001 HOST_WIDE_INT size, rsize, align;
6004 tree ptrtype = build_pointer_type (type);
6006 if (function_arg_pass_by_reference (0, TYPE_MODE (type), type, 0))
6009 size = rsize = UNITS_PER_WORD;
6015 size = int_size_in_bytes (type);
6016 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6021 /* For SPARC64, objects requiring 16-byte alignment get it. */
6022 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
6023 align = 2 * UNITS_PER_WORD;
6025 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6026 are given whole slots as needed. */
6027 if (AGGREGATE_TYPE_P (type))
6030 size = rsize = UNITS_PER_WORD;
6040 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
6041 ssize_int (align - 1)));
6042 incr = fold (build2 (BIT_AND_EXPR, ptr_type_node, incr,
6043 ssize_int (-align)));
6046 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
6049 if (BYTES_BIG_ENDIAN && size < rsize)
6050 addr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
6051 ssize_int (rsize - size)));
6055 addr = fold_convert (build_pointer_type (ptrtype), addr);
6056 addr = build_fold_indirect_ref (addr);
6058 /* If the address isn't aligned properly for the type,
6059 we may need to copy to a temporary.
6060 FIXME: This is inefficient. Usually we can do this
6063 && TYPE_ALIGN (type) > BITS_PER_WORD)
6065 tree tmp = create_tmp_var (type, "va_arg_tmp");
6066 tree dest_addr = build_fold_addr_expr (tmp);
6068 tree copy = build_function_call_expr
6069 (implicit_built_in_decls[BUILT_IN_MEMCPY],
6070 tree_cons (NULL_TREE, dest_addr,
6071 tree_cons (NULL_TREE, addr,
6072 tree_cons (NULL_TREE, size_int (rsize),
6075 gimplify_and_add (copy, pre_p);
6079 addr = fold_convert (ptrtype, addr);
6081 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr, ssize_int (rsize)));
6082 incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr);
6083 gimplify_and_add (incr, post_p);
6085 return build_fold_indirect_ref (addr);
6088 /* Return the string to output a conditional branch to LABEL, which is
6089 the operand number of the label. OP is the conditional expression.
6090 XEXP (OP, 0) is assumed to be a condition code register (integer or
6091 floating point) and its mode specifies what kind of comparison we made.
6093 REVERSED is nonzero if we should reverse the sense of the comparison.
6095 ANNUL is nonzero if we should generate an annulling branch.
6097 NOOP is nonzero if we have to follow this branch by a noop.
6099 INSN, if set, is the insn. */
6102 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
6105 static char string[64];
6106 enum rtx_code code = GET_CODE (op);
6107 rtx cc_reg = XEXP (op, 0);
6108 enum machine_mode mode = GET_MODE (cc_reg);
6109 const char *labelno, *branch;
6110 int spaces = 8, far;
6113 /* v9 branches are limited to +-1MB. If it is too far away,
6126 fbne,a,pn %fcc2, .LC29
6134 far = TARGET_V9 && (get_attr_length (insn) >= 3);
6137 /* Reversal of FP compares takes care -- an ordered compare
6138 becomes an unordered compare and vice versa. */
6139 if (mode == CCFPmode || mode == CCFPEmode)
6140 code = reverse_condition_maybe_unordered (code);
6142 code = reverse_condition (code);
6145 /* Start by writing the branch condition. */
6146 if (mode == CCFPmode || mode == CCFPEmode)
6197 /* ??? !v9: FP branches cannot be preceded by another floating point
6198 insn. Because there is currently no concept of pre-delay slots,
6199 we can fix this only by always emitting a nop before a floating
6204 strcpy (string, "nop\n\t");
6205 strcat (string, branch);
6218 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6230 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6251 strcpy (string, branch);
6253 spaces -= strlen (branch);
6254 p = strchr (string, '\0');
6256 /* Now add the annulling, the label, and a possible noop. */
6269 if (! far && insn && INSN_ADDRESSES_SET_P ())
6271 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6272 - INSN_ADDRESSES (INSN_UID (insn)));
6273 /* Leave some instructions for "slop". */
6274 if (delta < -260000 || delta >= 260000)
6278 if (mode == CCFPmode || mode == CCFPEmode)
6280 static char v9_fcc_labelno[] = "%%fccX, ";
6281 /* Set the char indicating the number of the fcc reg to use. */
6282 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6283 labelno = v9_fcc_labelno;
6286 if (REGNO (cc_reg) == SPARC_FCC_REG)
6292 else if (mode == CCXmode || mode == CCX_NOOVmode)
6294 labelno = "%%xcc, ";
6300 labelno = "%%icc, ";
6305 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6308 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6321 strcpy (p, labelno);
6322 p = strchr (p, '\0');
6325 strcpy (p, ".+12\n\t nop\n\tb\t");
6332 /* Set the char indicating the number of the operand containing the
6337 strcpy (p, "\n\t nop");
6342 /* Emit a library call comparison between floating point X and Y.
6343 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6344 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6345 values as arguments instead of the TFmode registers themselves,
6346 that's why we cannot call emit_float_lib_cmp. */
6348 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6351 rtx slot0, slot1, result, tem, tem2;
6352 enum machine_mode mode;
6357 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6361 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6365 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6369 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6373 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6377 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6388 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6398 if (GET_CODE (x) != MEM)
6400 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6401 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6406 if (GET_CODE (y) != MEM)
6408 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6409 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6414 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6416 XEXP (slot0, 0), Pmode,
6417 XEXP (slot1, 0), Pmode);
6423 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6425 x, TFmode, y, TFmode);
6431 /* Immediately move the result of the libcall into a pseudo
6432 register so reload doesn't clobber the value if it needs
6433 the return register for a spill reg. */
6434 result = gen_reg_rtx (mode);
6435 emit_move_insn (result, hard_libcall_value (mode));
6440 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6444 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6449 emit_cmp_insn (result, const1_rtx,
6450 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6453 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6456 tem = gen_reg_rtx (mode);
6458 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6460 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6461 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6465 tem = gen_reg_rtx (mode);
6467 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6469 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6470 tem2 = gen_reg_rtx (mode);
6472 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6474 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6475 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6481 /* Generate an unsigned DImode to FP conversion. This is the same code
6482 optabs would emit if we didn't have TFmode patterns. */
6485 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
6487 rtx neglab, donelab, i0, i1, f0, in, out;
6490 in = force_reg (DImode, operands[1]);
6491 neglab = gen_label_rtx ();
6492 donelab = gen_label_rtx ();
6493 i0 = gen_reg_rtx (DImode);
6494 i1 = gen_reg_rtx (DImode);
6495 f0 = gen_reg_rtx (mode);
6497 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6499 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6500 emit_jump_insn (gen_jump (donelab));
6503 emit_label (neglab);
6505 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6506 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6507 emit_insn (gen_iordi3 (i0, i0, i1));
6508 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6509 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6511 emit_label (donelab);
6514 /* Generate an FP to unsigned DImode conversion. This is the same code
6515 optabs would emit if we didn't have TFmode patterns. */
6518 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
6520 rtx neglab, donelab, i0, i1, f0, in, out, limit;
6523 in = force_reg (mode, operands[1]);
6524 neglab = gen_label_rtx ();
6525 donelab = gen_label_rtx ();
6526 i0 = gen_reg_rtx (DImode);
6527 i1 = gen_reg_rtx (DImode);
6528 limit = gen_reg_rtx (mode);
6529 f0 = gen_reg_rtx (mode);
6531 emit_move_insn (limit,
6532 CONST_DOUBLE_FROM_REAL_VALUE (
6533 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
6534 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
6536 emit_insn (gen_rtx_SET (VOIDmode,
6538 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
6539 emit_jump_insn (gen_jump (donelab));
6542 emit_label (neglab);
6544 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
6545 emit_insn (gen_rtx_SET (VOIDmode,
6547 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6548 emit_insn (gen_movdi (i1, const1_rtx));
6549 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6550 emit_insn (gen_xordi3 (out, i0, i1));
6552 emit_label (donelab);
6555 /* Return the string to output a conditional branch to LABEL, testing
6556 register REG. LABEL is the operand number of the label; REG is the
6557 operand number of the reg. OP is the conditional expression. The mode
6558 of REG says what kind of comparison we made.
6560 REVERSED is nonzero if we should reverse the sense of the comparison.
6562 ANNUL is nonzero if we should generate an annulling branch.
6564 NOOP is nonzero if we have to follow this branch by a noop. */
6567 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6568 int annul, int noop, rtx insn)
6570 static char string[64];
6571 enum rtx_code code = GET_CODE (op);
6572 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6577 /* branch on register are limited to +-128KB. If it is too far away,
6590 brgez,a,pn %o1, .LC29
6596 ba,pt %xcc, .LC29 */
6598 far = get_attr_length (insn) >= 3;
6600 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6602 code = reverse_condition (code);
6604 /* Only 64 bit versions of these instructions exist. */
6608 /* Start by writing the branch condition. */
6613 strcpy (string, "brnz");
6617 strcpy (string, "brz");
6621 strcpy (string, "brgez");
6625 strcpy (string, "brlz");
6629 strcpy (string, "brlez");
6633 strcpy (string, "brgz");
6640 p = strchr (string, '\0');
6642 /* Now add the annulling, reg, label, and nop. */
6649 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6652 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6657 *p = p < string + 8 ? '\t' : ' ';
6665 int veryfar = 1, delta;
6667 if (INSN_ADDRESSES_SET_P ())
6669 delta = (INSN_ADDRESSES (INSN_UID (dest))
6670 - INSN_ADDRESSES (INSN_UID (insn)));
6671 /* Leave some instructions for "slop". */
6672 if (delta >= -260000 && delta < 260000)
6676 strcpy (p, ".+12\n\t nop\n\t");
6687 strcpy (p, "ba,pt\t%%xcc, ");
6697 strcpy (p, "\n\t nop");
6702 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6703 Such instructions cannot be used in the delay slot of return insn on v9.
6704 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6708 epilogue_renumber (register rtx *where, int test)
6710 register const char *fmt;
6712 register enum rtx_code code;
6717 code = GET_CODE (*where);
6722 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6724 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6725 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6733 /* Do not replace the frame pointer with the stack pointer because
6734 it can cause the delayed instruction to load below the stack.
6735 This occurs when instructions like:
6737 (set (reg/i:SI 24 %i0)
6738 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6739 (const_int -20 [0xffffffec])) 0))
6741 are in the return delayed slot. */
6743 if (GET_CODE (XEXP (*where, 0)) == REG
6744 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6745 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6746 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6751 if (SPARC_STACK_BIAS
6752 && GET_CODE (XEXP (*where, 0)) == REG
6753 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6761 fmt = GET_RTX_FORMAT (code);
6763 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6768 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6769 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6772 else if (fmt[i] == 'e'
6773 && epilogue_renumber (&(XEXP (*where, i)), test))
6779 /* Leaf functions and non-leaf functions have different needs. */
6782 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6785 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6787 static const int *const reg_alloc_orders[] = {
6788 reg_leaf_alloc_order,
6789 reg_nonleaf_alloc_order};
6792 order_regs_for_local_alloc (void)
6794 static int last_order_nonleaf = 1;
6796 if (regs_ever_live[15] != last_order_nonleaf)
6798 last_order_nonleaf = !last_order_nonleaf;
6799 memcpy ((char *) reg_alloc_order,
6800 (const char *) reg_alloc_orders[last_order_nonleaf],
6801 FIRST_PSEUDO_REGISTER * sizeof (int));
6805 /* Return 1 if REG and MEM are legitimate enough to allow the various
6806 mem<-->reg splits to be run. */
6809 sparc_splitdi_legitimate (rtx reg, rtx mem)
6811 /* Punt if we are here by mistake. */
6812 if (! reload_completed)
6815 /* We must have an offsettable memory reference. */
6816 if (! offsettable_memref_p (mem))
6819 /* If we have legitimate args for ldd/std, we do not want
6820 the split to happen. */
6821 if ((REGNO (reg) % 2) == 0
6822 && mem_min_alignment (mem, 8))
6829 /* Return 1 if x and y are some kind of REG and they refer to
6830 different hard registers. This test is guaranteed to be
6831 run after reload. */
6834 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6836 if (GET_CODE (x) != REG)
6838 if (GET_CODE (y) != REG)
6840 if (REGNO (x) == REGNO (y))
6845 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6846 This makes them candidates for using ldd and std insns.
6848 Note reg1 and reg2 *must* be hard registers. */
6851 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6853 /* We might have been passed a SUBREG. */
6854 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6857 if (REGNO (reg1) % 2 != 0)
6860 /* Integer ldd is deprecated in SPARC V9 */
6861 if (TARGET_V9 && REGNO (reg1) < 32)
6864 return (REGNO (reg1) == REGNO (reg2) - 1);
6867 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6870 This can only happen when addr1 and addr2, the addresses in mem1
6871 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6872 addr1 must also be aligned on a 64-bit boundary.
6874 Also iff dependent_reg_rtx is not null it should not be used to
6875 compute the address for mem1, i.e. we cannot optimize a sequence
6887 But, note that the transformation from:
6892 is perfectly fine. Thus, the peephole2 patterns always pass us
6893 the destination register of the first load, never the second one.
6895 For stores we don't have a similar problem, so dependent_reg_rtx is
6899 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6903 HOST_WIDE_INT offset1;
6905 /* The mems cannot be volatile. */
6906 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6909 /* MEM1 should be aligned on a 64-bit boundary. */
6910 if (MEM_ALIGN (mem1) < 64)
6913 addr1 = XEXP (mem1, 0);
6914 addr2 = XEXP (mem2, 0);
6916 /* Extract a register number and offset (if used) from the first addr. */
6917 if (GET_CODE (addr1) == PLUS)
6919 /* If not a REG, return zero. */
6920 if (GET_CODE (XEXP (addr1, 0)) != REG)
6924 reg1 = REGNO (XEXP (addr1, 0));
6925 /* The offset must be constant! */
6926 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6928 offset1 = INTVAL (XEXP (addr1, 1));
6931 else if (GET_CODE (addr1) != REG)
6935 reg1 = REGNO (addr1);
6936 /* This was a simple (mem (reg)) expression. Offset is 0. */
6940 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6941 if (GET_CODE (addr2) != PLUS)
6944 if (GET_CODE (XEXP (addr2, 0)) != REG
6945 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6948 if (reg1 != REGNO (XEXP (addr2, 0)))
6951 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6954 /* The first offset must be evenly divisible by 8 to ensure the
6955 address is 64 bit aligned. */
6956 if (offset1 % 8 != 0)
6959 /* The offset for the second addr must be 4 more than the first addr. */
6960 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6963 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6968 /* Return 1 if reg is a pseudo, or is the first register in
6969 a hard register pair. This makes it a candidate for use in
6970 ldd and std insns. */
6973 register_ok_for_ldd (rtx reg)
6975 /* We might have been passed a SUBREG. */
6976 if (GET_CODE (reg) != REG)
6979 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6980 return (REGNO (reg) % 2 == 0);
6985 /* Print operand X (an rtx) in assembler syntax to file FILE.
6986 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6987 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6990 print_operand (FILE *file, rtx x, int code)
6995 /* Output a 'nop' if there's nothing for the delay slot. */
6996 if (dbr_sequence_length () == 0)
6997 fputs ("\n\t nop", file);
7000 /* Output an annul flag if there's nothing for the delay slot and we
7001 are optimizing. This is always used with '(' below. */
7002 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7003 this is a dbx bug. So, we only do this when optimizing. */
7004 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7005 Always emit a nop in case the next instruction is a branch. */
7006 if (dbr_sequence_length () == 0
7007 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
7011 /* Output a 'nop' if there's nothing for the delay slot and we are
7012 not optimizing. This is always used with '*' above. */
7013 if (dbr_sequence_length () == 0
7014 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
7015 fputs ("\n\t nop", file);
7018 /* Output the Embedded Medium/Anywhere code model base register. */
7019 fputs (EMBMEDANY_BASE_REG, file);
7022 /* Print out what we are using as the frame pointer. This might
7023 be %fp, or might be %sp+offset. */
7024 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
7025 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC,
7026 reg_names[REGNO (frame_base_reg)], frame_base_offset);
7029 /* Print some local dynamic TLS name. */
7030 assemble_name (file, get_some_local_dynamic_name ());
7033 /* Adjust the operand to take into account a RESTORE operation. */
7034 if (GET_CODE (x) == CONST_INT)
7036 else if (GET_CODE (x) != REG)
7037 output_operand_lossage ("invalid %%Y operand");
7038 else if (REGNO (x) < 8)
7039 fputs (reg_names[REGNO (x)], file);
7040 else if (REGNO (x) >= 24 && REGNO (x) < 32)
7041 fputs (reg_names[REGNO (x)-16], file);
7043 output_operand_lossage ("invalid %%Y operand");
7046 /* Print out the low order register name of a register pair. */
7047 if (WORDS_BIG_ENDIAN)
7048 fputs (reg_names[REGNO (x)+1], file);
7050 fputs (reg_names[REGNO (x)], file);
7053 /* Print out the high order register name of a register pair. */
7054 if (WORDS_BIG_ENDIAN)
7055 fputs (reg_names[REGNO (x)], file);
7057 fputs (reg_names[REGNO (x)+1], file);
7060 /* Print out the second register name of a register pair or quad.
7061 I.e., R (%o0) => %o1. */
7062 fputs (reg_names[REGNO (x)+1], file);
7065 /* Print out the third register name of a register quad.
7066 I.e., S (%o0) => %o2. */
7067 fputs (reg_names[REGNO (x)+2], file);
7070 /* Print out the fourth register name of a register quad.
7071 I.e., T (%o0) => %o3. */
7072 fputs (reg_names[REGNO (x)+3], file);
7075 /* Print a condition code register. */
7076 if (REGNO (x) == SPARC_ICC_REG)
7078 /* We don't handle CC[X]_NOOVmode because they're not supposed
7080 if (GET_MODE (x) == CCmode)
7081 fputs ("%icc", file);
7082 else if (GET_MODE (x) == CCXmode)
7083 fputs ("%xcc", file);
7088 /* %fccN register */
7089 fputs (reg_names[REGNO (x)], file);
7092 /* Print the operand's address only. */
7093 output_address (XEXP (x, 0));
7096 /* In this case we need a register. Use %g0 if the
7097 operand is const0_rtx. */
7099 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
7101 fputs ("%g0", file);
7108 switch (GET_CODE (x))
7110 case IOR: fputs ("or", file); break;
7111 case AND: fputs ("and", file); break;
7112 case XOR: fputs ("xor", file); break;
7113 default: output_operand_lossage ("invalid %%A operand");
7118 switch (GET_CODE (x))
7120 case IOR: fputs ("orn", file); break;
7121 case AND: fputs ("andn", file); break;
7122 case XOR: fputs ("xnor", file); break;
7123 default: output_operand_lossage ("invalid %%B operand");
7127 /* These are used by the conditional move instructions. */
7131 enum rtx_code rc = GET_CODE (x);
7135 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7136 if (mode == CCFPmode || mode == CCFPEmode)
7137 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7139 rc = reverse_condition (GET_CODE (x));
7143 case NE: fputs ("ne", file); break;
7144 case EQ: fputs ("e", file); break;
7145 case GE: fputs ("ge", file); break;
7146 case GT: fputs ("g", file); break;
7147 case LE: fputs ("le", file); break;
7148 case LT: fputs ("l", file); break;
7149 case GEU: fputs ("geu", file); break;
7150 case GTU: fputs ("gu", file); break;
7151 case LEU: fputs ("leu", file); break;
7152 case LTU: fputs ("lu", file); break;
7153 case LTGT: fputs ("lg", file); break;
7154 case UNORDERED: fputs ("u", file); break;
7155 case ORDERED: fputs ("o", file); break;
7156 case UNLT: fputs ("ul", file); break;
7157 case UNLE: fputs ("ule", file); break;
7158 case UNGT: fputs ("ug", file); break;
7159 case UNGE: fputs ("uge", file); break;
7160 case UNEQ: fputs ("ue", file); break;
7161 default: output_operand_lossage (code == 'c'
7162 ? "invalid %%c operand"
7163 : "invalid %%C operand");
7168 /* These are used by the movr instruction pattern. */
7172 enum rtx_code rc = (code == 'd'
7173 ? reverse_condition (GET_CODE (x))
7177 case NE: fputs ("ne", file); break;
7178 case EQ: fputs ("e", file); break;
7179 case GE: fputs ("gez", file); break;
7180 case LT: fputs ("lz", file); break;
7181 case LE: fputs ("lez", file); break;
7182 case GT: fputs ("gz", file); break;
7183 default: output_operand_lossage (code == 'd'
7184 ? "invalid %%d operand"
7185 : "invalid %%D operand");
7192 /* Print a sign-extended character. */
7193 int i = trunc_int_for_mode (INTVAL (x), QImode);
7194 fprintf (file, "%d", i);
7199 /* Operand must be a MEM; write its address. */
7200 if (GET_CODE (x) != MEM)
7201 output_operand_lossage ("invalid %%f operand");
7202 output_address (XEXP (x, 0));
7207 /* Print a sign-extended 32-bit value. */
7209 if (GET_CODE(x) == CONST_INT)
7211 else if (GET_CODE(x) == CONST_DOUBLE)
7212 i = CONST_DOUBLE_LOW (x);
7215 output_operand_lossage ("invalid %%s operand");
7218 i = trunc_int_for_mode (i, SImode);
7219 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7224 /* Do nothing special. */
7228 /* Undocumented flag. */
7229 output_operand_lossage ("invalid operand output code");
7232 if (GET_CODE (x) == REG)
7233 fputs (reg_names[REGNO (x)], file);
7234 else if (GET_CODE (x) == MEM)
7237 /* Poor Sun assembler doesn't understand absolute addressing. */
7238 if (CONSTANT_P (XEXP (x, 0)))
7239 fputs ("%g0+", file);
7240 output_address (XEXP (x, 0));
7243 else if (GET_CODE (x) == HIGH)
7245 fputs ("%hi(", file);
7246 output_addr_const (file, XEXP (x, 0));
7249 else if (GET_CODE (x) == LO_SUM)
7251 print_operand (file, XEXP (x, 0), 0);
7252 if (TARGET_CM_MEDMID)
7253 fputs ("+%l44(", file);
7255 fputs ("+%lo(", file);
7256 output_addr_const (file, XEXP (x, 1));
7259 else if (GET_CODE (x) == CONST_DOUBLE
7260 && (GET_MODE (x) == VOIDmode
7261 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
7263 if (CONST_DOUBLE_HIGH (x) == 0)
7264 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
7265 else if (CONST_DOUBLE_HIGH (x) == -1
7266 && CONST_DOUBLE_LOW (x) < 0)
7267 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
7269 output_operand_lossage ("long long constant not a valid immediate operand");
7271 else if (GET_CODE (x) == CONST_DOUBLE)
7272 output_operand_lossage ("floating point constant not a valid immediate operand");
7273 else { output_addr_const (file, x); }
7276 /* Target hook for assembling integer objects. The sparc version has
7277 special handling for aligned DI-mode objects. */
7280 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7282 /* ??? We only output .xword's for symbols and only then in environments
7283 where the assembler can handle them. */
7284 if (aligned_p && size == 8
7285 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7289 assemble_integer_with_op ("\t.xword\t", x);
7294 assemble_aligned_integer (4, const0_rtx);
7295 assemble_aligned_integer (4, x);
7299 return default_assemble_integer (x, size, aligned_p);
7302 /* Return the value of a code used in the .proc pseudo-op that says
7303 what kind of result this function returns. For non-C types, we pick
7304 the closest C type. */
7306 #ifndef SHORT_TYPE_SIZE
7307 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7310 #ifndef INT_TYPE_SIZE
7311 #define INT_TYPE_SIZE BITS_PER_WORD
7314 #ifndef LONG_TYPE_SIZE
7315 #define LONG_TYPE_SIZE BITS_PER_WORD
7318 #ifndef LONG_LONG_TYPE_SIZE
7319 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7322 #ifndef FLOAT_TYPE_SIZE
7323 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7326 #ifndef DOUBLE_TYPE_SIZE
7327 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7330 #ifndef LONG_DOUBLE_TYPE_SIZE
7331 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7335 sparc_type_code (register tree type)
7337 register unsigned long qualifiers = 0;
7338 register unsigned shift;
7340 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7341 setting more, since some assemblers will give an error for this. Also,
7342 we must be careful to avoid shifts of 32 bits or more to avoid getting
7343 unpredictable results. */
7345 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7347 switch (TREE_CODE (type))
7353 qualifiers |= (3 << shift);
7358 qualifiers |= (2 << shift);
7362 case REFERENCE_TYPE:
7364 qualifiers |= (1 << shift);
7368 return (qualifiers | 8);
7371 case QUAL_UNION_TYPE:
7372 return (qualifiers | 9);
7375 return (qualifiers | 10);
7378 return (qualifiers | 16);
7381 /* If this is a range type, consider it to be the underlying
7383 if (TREE_TYPE (type) != 0)
7386 /* Carefully distinguish all the standard types of C,
7387 without messing up if the language is not C. We do this by
7388 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
7389 look at both the names and the above fields, but that's redundant.
7390 Any type whose size is between two C types will be considered
7391 to be the wider of the two types. Also, we do not have a
7392 special code to use for "long long", so anything wider than
7393 long is treated the same. Note that we can't distinguish
7394 between "int" and "long" in this code if they are the same
7395 size, but that's fine, since neither can the assembler. */
7397 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7398 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
7400 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7401 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
7403 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7404 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
7407 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
7410 /* If this is a range type, consider it to be the underlying
7412 if (TREE_TYPE (type) != 0)
7415 /* Carefully distinguish all the standard types of C,
7416 without messing up if the language is not C. */
7418 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7419 return (qualifiers | 6);
7422 return (qualifiers | 7);
7424 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7425 /* ??? We need to distinguish between double and float complex types,
7426 but I don't know how yet because I can't reach this code from
7427 existing front-ends. */
7428 return (qualifiers | 7); /* Who knows? */
7431 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7432 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7433 case FILE_TYPE: /* GNU Pascal FILE type. */
7434 case SET_TYPE: /* GNU Pascal SET type. */
7435 case LANG_TYPE: /* ? */
7439 abort (); /* Not a type! */
7446 /* Nested function support. */
7448 /* Emit RTL insns to initialize the variable parts of a trampoline.
7449 FNADDR is an RTX for the address of the function's pure code.
7450 CXT is an RTX for the static chain value for the function.
7452 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7453 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7454 (to store insns). This is a bit excessive. Perhaps a different
7455 mechanism would be better here.
7457 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7460 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7462 /* SPARC 32-bit trampoline:
7465 sethi %hi(static), %g2
7467 or %g2, %lo(static), %g2
7469 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7470 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7474 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7475 expand_binop (SImode, ior_optab,
7476 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7477 size_int (10), 0, 1),
7478 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7479 NULL_RTX, 1, OPTAB_DIRECT));
7482 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7483 expand_binop (SImode, ior_optab,
7484 expand_shift (RSHIFT_EXPR, SImode, cxt,
7485 size_int (10), 0, 1),
7486 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7487 NULL_RTX, 1, OPTAB_DIRECT));
7490 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7491 expand_binop (SImode, ior_optab,
7492 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7493 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7494 NULL_RTX, 1, OPTAB_DIRECT));
7497 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7498 expand_binop (SImode, ior_optab,
7499 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7500 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7501 NULL_RTX, 1, OPTAB_DIRECT));
7503 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7504 aligned on a 16 byte boundary so one flush clears it all. */
7505 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7506 if (sparc_cpu != PROCESSOR_ULTRASPARC
7507 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7508 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7509 plus_constant (tramp, 8)))));
7511 /* Call __enable_execute_stack after writing onto the stack to make sure
7512 the stack address is accessible. */
7513 #ifdef TRANSFER_FROM_TRAMPOLINE
7514 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7515 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7520 /* The 64-bit version is simpler because it makes more sense to load the
7521 values as "immediate" data out of the trampoline. It's also easier since
7522 we can read the PC without clobbering a register. */
7525 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7527 /* SPARC 64-bit trampoline:
7536 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7537 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7538 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7539 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7540 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7541 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7542 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7543 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7544 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7545 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7546 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7548 if (sparc_cpu != PROCESSOR_ULTRASPARC
7549 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7550 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7552 /* Call __enable_execute_stack after writing onto the stack to make sure
7553 the stack address is accessible. */
7554 #ifdef TRANSFER_FROM_TRAMPOLINE
7555 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7556 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7560 /* Adjust the cost of a scheduling dependency. Return the new cost of
7561 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7564 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7566 enum attr_type insn_type;
7568 if (! recog_memoized (insn))
7571 insn_type = get_attr_type (insn);
7573 if (REG_NOTE_KIND (link) == 0)
7575 /* Data dependency; DEP_INSN writes a register that INSN reads some
7578 /* if a load, then the dependence must be on the memory address;
7579 add an extra "cycle". Note that the cost could be two cycles
7580 if the reg was written late in an instruction group; we ca not tell
7582 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7585 /* Get the delay only if the address of the store is the dependence. */
7586 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7588 rtx pat = PATTERN(insn);
7589 rtx dep_pat = PATTERN (dep_insn);
7591 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7592 return cost; /* This should not happen! */
7594 /* The dependency between the two instructions was on the data that
7595 is being stored. Assume that this implies that the address of the
7596 store is not dependent. */
7597 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7600 return cost + 3; /* An approximation. */
7603 /* A shift instruction cannot receive its data from an instruction
7604 in the same cycle; add a one cycle penalty. */
7605 if (insn_type == TYPE_SHIFT)
7606 return cost + 3; /* Split before cascade into shift. */
7610 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7611 INSN writes some cycles later. */
7613 /* These are only significant for the fpu unit; writing a fp reg before
7614 the fpu has finished with it stalls the processor. */
7616 /* Reusing an integer register causes no problems. */
7617 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7625 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7627 enum attr_type insn_type, dep_type;
7628 rtx pat = PATTERN(insn);
7629 rtx dep_pat = PATTERN (dep_insn);
7631 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7634 insn_type = get_attr_type (insn);
7635 dep_type = get_attr_type (dep_insn);
7637 switch (REG_NOTE_KIND (link))
7640 /* Data dependency; DEP_INSN writes a register that INSN reads some
7647 /* Get the delay iff the address of the store is the dependence. */
7648 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7651 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7658 /* If a load, then the dependence must be on the memory address. If
7659 the addresses aren't equal, then it might be a false dependency */
7660 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7662 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7663 || GET_CODE (SET_DEST (dep_pat)) != MEM
7664 || GET_CODE (SET_SRC (pat)) != MEM
7665 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7666 XEXP (SET_SRC (pat), 0)))
7674 /* Compare to branch latency is 0. There is no benefit from
7675 separating compare and branch. */
7676 if (dep_type == TYPE_COMPARE)
7678 /* Floating point compare to branch latency is less than
7679 compare to conditional move. */
7680 if (dep_type == TYPE_FPCMP)
7689 /* Anti-dependencies only penalize the fpu unit. */
7690 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7702 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
7706 case PROCESSOR_SUPERSPARC:
7707 cost = supersparc_adjust_cost (insn, link, dep, cost);
7709 case PROCESSOR_HYPERSPARC:
7710 case PROCESSOR_SPARCLITE86X:
7711 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7720 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7721 int sched_verbose ATTRIBUTE_UNUSED,
7722 int max_ready ATTRIBUTE_UNUSED)
7727 sparc_use_sched_lookahead (void)
7729 if (sparc_cpu == PROCESSOR_ULTRASPARC
7730 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7732 if ((1 << sparc_cpu) &
7733 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7734 (1 << PROCESSOR_SPARCLITE86X)))
7740 sparc_issue_rate (void)
7747 /* Assume V9 processors are capable of at least dual-issue. */
7749 case PROCESSOR_SUPERSPARC:
7751 case PROCESSOR_HYPERSPARC:
7752 case PROCESSOR_SPARCLITE86X:
7754 case PROCESSOR_ULTRASPARC:
7755 case PROCESSOR_ULTRASPARC3:
7761 set_extends (rtx insn)
7763 register rtx pat = PATTERN (insn);
7765 switch (GET_CODE (SET_SRC (pat)))
7767 /* Load and some shift instructions zero extend. */
7770 /* sethi clears the high bits */
7772 /* LO_SUM is used with sethi. sethi cleared the high
7773 bits and the values used with lo_sum are positive */
7775 /* Store flag stores 0 or 1 */
7785 rtx op0 = XEXP (SET_SRC (pat), 0);
7786 rtx op1 = XEXP (SET_SRC (pat), 1);
7787 if (GET_CODE (op1) == CONST_INT)
7788 return INTVAL (op1) >= 0;
7789 if (GET_CODE (op0) != REG)
7791 if (sparc_check_64 (op0, insn) == 1)
7793 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7798 rtx op0 = XEXP (SET_SRC (pat), 0);
7799 rtx op1 = XEXP (SET_SRC (pat), 1);
7800 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7802 if (GET_CODE (op1) == CONST_INT)
7803 return INTVAL (op1) >= 0;
7804 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7807 return GET_MODE (SET_SRC (pat)) == SImode;
7808 /* Positive integers leave the high bits zero. */
7810 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7812 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7815 return - (GET_MODE (SET_SRC (pat)) == SImode);
7817 return sparc_check_64 (SET_SRC (pat), insn);
7823 /* We _ought_ to have only one kind per function, but... */
7824 static GTY(()) rtx sparc_addr_diff_list;
7825 static GTY(()) rtx sparc_addr_list;
7828 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
7830 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7832 sparc_addr_diff_list
7833 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7835 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7839 sparc_output_addr_vec (rtx vec)
7841 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7842 int idx, vlen = XVECLEN (body, 0);
7844 #ifdef ASM_OUTPUT_ADDR_VEC_START
7845 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7848 #ifdef ASM_OUTPUT_CASE_LABEL
7849 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7852 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7855 for (idx = 0; idx < vlen; idx++)
7857 ASM_OUTPUT_ADDR_VEC_ELT
7858 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7861 #ifdef ASM_OUTPUT_ADDR_VEC_END
7862 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7867 sparc_output_addr_diff_vec (rtx vec)
7869 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7870 rtx base = XEXP (XEXP (body, 0), 0);
7871 int idx, vlen = XVECLEN (body, 1);
7873 #ifdef ASM_OUTPUT_ADDR_VEC_START
7874 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7877 #ifdef ASM_OUTPUT_CASE_LABEL
7878 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7881 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7884 for (idx = 0; idx < vlen; idx++)
7886 ASM_OUTPUT_ADDR_DIFF_ELT
7889 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7890 CODE_LABEL_NUMBER (base));
7893 #ifdef ASM_OUTPUT_ADDR_VEC_END
7894 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7899 sparc_output_deferred_case_vectors (void)
7904 if (sparc_addr_list == NULL_RTX
7905 && sparc_addr_diff_list == NULL_RTX)
7908 /* Align to cache line in the function's code section. */
7909 function_section (current_function_decl);
7911 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7913 ASM_OUTPUT_ALIGN (asm_out_file, align);
7915 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7916 sparc_output_addr_vec (XEXP (t, 0));
7917 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7918 sparc_output_addr_diff_vec (XEXP (t, 0));
7920 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7923 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7924 unknown. Return 1 if the high bits are zero, -1 if the register is
7927 sparc_check_64 (rtx x, rtx insn)
7929 /* If a register is set only once it is safe to ignore insns this
7930 code does not know how to handle. The loop will either recognize
7931 the single set and return the correct value or fail to recognize
7936 if (GET_CODE (x) != REG)
7939 if (GET_MODE (x) == DImode)
7940 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
7942 if (flag_expensive_optimizations
7943 && REG_N_SETS (REGNO (y)) == 1)
7949 insn = get_last_insn_anywhere ();
7954 while ((insn = PREV_INSN (insn)))
7956 switch (GET_CODE (insn))
7969 rtx pat = PATTERN (insn);
7970 if (GET_CODE (pat) != SET)
7972 if (rtx_equal_p (x, SET_DEST (pat)))
7973 return set_extends (insn);
7974 if (y && rtx_equal_p (y, SET_DEST (pat)))
7975 return set_extends (insn);
7976 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
7984 /* Returns assembly code to perform a DImode shift using
7985 a 64-bit global or out register on SPARC-V8+. */
7987 output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
7989 static char asm_code[60];
7991 /* The scratch register is only required when the destination
7992 register is not a 64-bit global or out register. */
7993 if (which_alternative != 2)
7994 operands[3] = operands[0];
7996 /* We can only shift by constants <= 63. */
7997 if (GET_CODE (operands[2]) == CONST_INT)
7998 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8000 if (GET_CODE (operands[1]) == CONST_INT)
8002 output_asm_insn ("mov\t%1, %3", operands);
8006 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8007 if (sparc_check_64 (operands[1], insn) <= 0)
8008 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8009 output_asm_insn ("or\t%L1, %3, %3", operands);
8012 strcpy(asm_code, opcode);
8014 if (which_alternative != 2)
8015 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8017 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8020 /* Output rtl to increment the profiler label LABELNO
8021 for profiling a function entry. */
8024 sparc_profile_hook (int labelno)
8029 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8030 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8031 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8033 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8036 #ifdef OBJECT_FORMAT_ELF
8038 sparc_elf_asm_named_section (const char *name, unsigned int flags)
8040 if (flags & SECTION_MERGE)
8042 /* entsize cannot be expressed in this section attributes
8044 default_elf_asm_named_section (name, flags);
8048 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8050 if (!(flags & SECTION_DEBUG))
8051 fputs (",#alloc", asm_out_file);
8052 if (flags & SECTION_WRITE)
8053 fputs (",#write", asm_out_file);
8054 if (flags & SECTION_TLS)
8055 fputs (",#tls", asm_out_file);
8056 if (flags & SECTION_CODE)
8057 fputs (",#execinstr", asm_out_file);
8059 /* ??? Handle SECTION_BSS. */
8061 fputc ('\n', asm_out_file);
8063 #endif /* OBJECT_FORMAT_ELF */
8065 /* We do not allow indirect calls to be optimized into sibling calls.
8067 We cannot use sibling calls when delayed branches are disabled
8068 because they will likely require the call delay slot to be filled.
8070 Also, on SPARC 32-bit we cannot emit a sibling call when the
8071 current function returns a structure. This is because the "unimp
8072 after call" convention would cause the callee to return to the
8073 wrong place. The generic code already disallows cases where the
8074 function being called returns a structure.
8076 It may seem strange how this last case could occur. Usually there
8077 is code after the call which jumps to epilogue code which dumps the
8078 return value into the struct return area. That ought to invalidate
8079 the sibling call right? Well, in the C++ case we can end up passing
8080 the pointer to the struct return area to a constructor (which returns
8081 void) and then nothing else happens. Such a sibling call would look
8082 valid without the added check here. */
8084 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8087 && flag_delayed_branch
8088 && (TARGET_ARCH64 || ! current_function_returns_struct));
8091 /* libfunc renaming. */
8092 #include "config/gofast.h"
8095 sparc_init_libfuncs (void)
8099 /* Use the subroutines that Sun's library provides for integer
8100 multiply and divide. The `*' prevents an underscore from
8101 being prepended by the compiler. .umul is a little faster
8103 set_optab_libfunc (smul_optab, SImode, "*.umul");
8104 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8105 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8106 set_optab_libfunc (smod_optab, SImode, "*.rem");
8107 set_optab_libfunc (umod_optab, SImode, "*.urem");
8109 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8110 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8111 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8112 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8113 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8114 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8116 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8117 is because with soft-float, the SFmode and DFmode sqrt
8118 instructions will be absent, and the compiler will notice and
8119 try to use the TFmode sqrt instruction for calls to the
8120 builtin function sqrt, but this fails. */
8122 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8124 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8125 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8126 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8127 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8128 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8129 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8131 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8132 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8133 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8134 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8136 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8137 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8138 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8140 if (DITF_CONVERSION_LIBFUNCS)
8142 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
8143 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
8144 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
8147 if (SUN_CONVERSION_LIBFUNCS)
8149 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8150 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8151 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8152 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8157 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8158 do not exist in the library. Make sure the compiler does not
8159 emit calls to them by accident. (It should always use the
8160 hardware instructions.) */
8161 set_optab_libfunc (smul_optab, SImode, 0);
8162 set_optab_libfunc (sdiv_optab, SImode, 0);
8163 set_optab_libfunc (udiv_optab, SImode, 0);
8164 set_optab_libfunc (smod_optab, SImode, 0);
8165 set_optab_libfunc (umod_optab, SImode, 0);
8167 if (SUN_INTEGER_MULTIPLY_64)
8169 set_optab_libfunc (smul_optab, DImode, "__mul64");
8170 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8171 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8172 set_optab_libfunc (smod_optab, DImode, "__rem64");
8173 set_optab_libfunc (umod_optab, DImode, "__urem64");
8176 if (SUN_CONVERSION_LIBFUNCS)
8178 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8179 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8180 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8181 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8185 gofast_maybe_init_libfuncs ();
8189 sparc_extra_constraint_check (rtx op, int c, int strict)
8194 && (c == 'T' || c == 'U'))
8200 return fp_sethi_p (op);
8203 return fp_mov_p (op);
8206 return fp_high_losum_p (op);
8210 || (GET_CODE (op) == REG
8211 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8212 || reg_renumber[REGNO (op)] >= 0)))
8213 return register_ok_for_ldd (op);
8225 /* Our memory extra constraints have to emulate the
8226 behavior of 'm' and 'o' in order for reload to work
8228 if (GET_CODE (op) == MEM)
8231 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8233 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8238 reload_ok_mem = (reload_in_progress
8239 && GET_CODE (op) == REG
8240 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8241 && reg_renumber [REGNO (op)] < 0);
8244 return reload_ok_mem;
8247 /* ??? This duplicates information provided to the compiler by the
8248 ??? scheduler description. Some day, teach genautomata to output
8249 ??? the latencies and then CSE will just use that. */
8252 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8254 enum machine_mode mode = GET_MODE (x);
8255 bool float_mode_p = FLOAT_MODE_P (mode);
8260 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8278 if (GET_MODE (x) == DImode
8279 && ((XINT (x, 3) == 0
8280 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8281 || (XINT (x, 3) == -1
8283 && XINT (x, 2) >= -0x1000)))
8290 /* If outer-code was a sign or zero extension, a cost
8291 of COSTS_N_INSNS (1) was already added in. This is
8292 why we are subtracting it back out. */
8293 if (outer_code == ZERO_EXTEND)
8295 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
8297 else if (outer_code == SIGN_EXTEND)
8299 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
8301 else if (float_mode_p)
8303 *total = sparc_costs->float_load;
8307 *total = sparc_costs->int_load;
8315 *total = sparc_costs->float_plusminus;
8317 *total = COSTS_N_INSNS (1);
8322 *total = sparc_costs->float_mul;
8328 if (sparc_costs->int_mul_bit_factor)
8332 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8334 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
8335 for (nbits = 0; value != 0; value &= value - 1)
8338 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
8339 && GET_MODE (XEXP (x, 1)) == DImode)
8341 rtx x1 = XEXP (x, 1);
8342 unsigned HOST_WIDE_INT value1 = XINT (x1, 2);
8343 unsigned HOST_WIDE_INT value2 = XINT (x1, 3);
8345 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
8347 for (; value2 != 0; value2 &= value2 - 1)
8355 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
8356 bit_cost = COSTS_N_INSNS (bit_cost);
8360 *total = sparc_costs->int_mulX + bit_cost;
8362 *total = sparc_costs->int_mul + bit_cost;
8369 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
8379 *total = sparc_costs->float_div_df;
8381 *total = sparc_costs->float_div_sf;
8386 *total = sparc_costs->int_divX;
8388 *total = sparc_costs->int_div;
8395 *total = COSTS_N_INSNS (1);
8402 case UNSIGNED_FLOAT:
8406 case FLOAT_TRUNCATE:
8407 *total = sparc_costs->float_move;
8412 *total = sparc_costs->float_sqrt_df;
8414 *total = sparc_costs->float_sqrt_sf;
8419 *total = sparc_costs->float_cmp;
8421 *total = COSTS_N_INSNS (1);
8426 *total = sparc_costs->float_cmove;
8428 *total = sparc_costs->int_cmove;
8436 /* Emit the sequence of insns SEQ while preserving the register REG. */
8439 emit_and_preserve (rtx seq, rtx reg)
8441 rtx slot = gen_rtx_MEM (word_mode,
8442 plus_constant (stack_pointer_rtx, SPARC_STACK_BIAS));
8444 emit_stack_pointer_decrement (GEN_INT (UNITS_PER_WORD));
8445 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
8447 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
8448 emit_stack_pointer_increment (GEN_INT (UNITS_PER_WORD));
8451 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8452 Used for C++ multiple inheritance. */
8455 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8456 HOST_WIDE_INT delta,
8457 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8460 rtx this, insn, funexp, delta_rtx;
8461 unsigned int int_arg_first;
8463 reload_completed = 1;
8464 epilogue_completed = 1;
8466 reset_block_changes ();
8468 emit_note (NOTE_INSN_PROLOGUE_END);
8470 if (flag_delayed_branch)
8472 /* We will emit a regular sibcall below, so we need to instruct
8473 output_sibcall that we are in a leaf function. */
8474 current_function_uses_only_leaf_regs = 1;
8476 /* This will cause final.c to invoke leaf_renumber_regs so we
8477 must behave as if we were in a not-yet-leafified function. */
8478 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
8482 /* We will emit the sibcall manually below, so we will need to
8483 manually spill non-leaf registers. */
8484 current_function_uses_only_leaf_regs = 0;
8486 /* We really are in a leaf function. */
8487 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
8490 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8491 returns a structure, the structure return pointer is there instead. */
8492 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8493 this = gen_rtx_REG (Pmode, int_arg_first + 1);
8495 this = gen_rtx_REG (Pmode, int_arg_first);
8497 /* Add DELTA. When possible use a plain add, otherwise load it into
8498 a register first. */
8499 delta_rtx = GEN_INT (delta);
8500 if (!SPARC_SIMM13_P (delta))
8502 rtx scratch = gen_rtx_REG (Pmode, 1);
8504 if (input_operand (delta_rtx, GET_MODE (scratch)))
8505 emit_insn (gen_rtx_SET (VOIDmode, scratch, delta_rtx));
8509 sparc_emit_set_const64 (scratch, delta_rtx);
8511 sparc_emit_set_const32 (scratch, delta_rtx);
8514 delta_rtx = scratch;
8517 emit_insn (gen_rtx_SET (VOIDmode,
8519 gen_rtx_PLUS (Pmode, this, delta_rtx)));
8521 /* Generate a tail call to the target function. */
8522 if (! TREE_USED (function))
8524 assemble_external (function);
8525 TREE_USED (function) = 1;
8527 funexp = XEXP (DECL_RTL (function), 0);
8529 if (flag_delayed_branch)
8531 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8532 insn = emit_call_insn (gen_sibcall (funexp));
8533 SIBLING_CALL_P (insn) = 1;
8537 /* The hoops we have to jump through in order to generate a sibcall
8538 without using delay slots... */
8539 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
8543 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
8545 load_pic_register (); /* clobbers %o7 */
8546 scratch = legitimize_pic_address (funexp, Pmode, scratch);
8549 emit_and_preserve (seq, spill_reg);
8551 else if (TARGET_ARCH32)
8553 emit_insn (gen_rtx_SET (VOIDmode,
8555 gen_rtx_HIGH (SImode, funexp)));
8556 emit_insn (gen_rtx_SET (VOIDmode,
8558 gen_rtx_LO_SUM (SImode, scratch, funexp)));
8560 else /* TARGET_ARCH64 */
8562 switch (sparc_cmodel)
8566 /* The destination can serve as a temporary. */
8567 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
8572 /* The destination cannot serve as a temporary. */
8573 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
8575 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
8578 emit_and_preserve (seq, spill_reg);
8586 emit_jump_insn (gen_indirect_jump (scratch));
8591 /* Run just enough of rest_of_compilation to get the insns emitted.
8592 There's not really enough bulk here to make other passes such as
8593 instruction scheduling worth while. Note that use_thunk calls
8594 assemble_start_function and assemble_end_function. */
8595 insn = get_insns ();
8596 insn_locators_initialize ();
8597 shorten_branches (insn);
8598 final_start_function (insn, file, 1);
8599 final (insn, file, 1, 0);
8600 final_end_function ();
8602 reload_completed = 0;
8603 epilogue_completed = 0;
8607 /* How to allocate a 'struct machine_function'. */
8609 static struct machine_function *
8610 sparc_init_machine_status (void)
8612 return ggc_alloc_cleared (sizeof (struct machine_function));
8615 /* Locate some local-dynamic symbol still in use by this function
8616 so that we can print its name in local-dynamic base patterns. */
8619 get_some_local_dynamic_name (void)
8623 if (cfun->machine->some_ld_name)
8624 return cfun->machine->some_ld_name;
8626 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8628 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8629 return cfun->machine->some_ld_name;
8635 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8640 && GET_CODE (x) == SYMBOL_REF
8641 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8643 cfun->machine->some_ld_name = XSTR (x, 0);
8650 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
8651 We need to emit DTP-relative relocations. */
8654 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
8659 fputs ("\t.word\t%r_tls_dtpoff32(", file);
8662 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
8667 output_addr_const (file, x);
8671 #include "gt-sparc.h"