1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
47 #include "target-def.h"
49 /* 1 if the caller has placed an "unimp" insn immediately after the call.
50 This is used in v8 code when calling a function that returns a structure.
51 v9 doesn't have this. Be careful to have this test be the same as that
54 #define SKIP_CALLERS_UNIMP_P \
55 (!TARGET_ARCH64 && current_function_returns_struct \
56 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
57 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
60 /* Global variables for machine-dependent things. */
62 /* Size of frame. Need to know this to emit return insns from leaf procedures.
63 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
64 reload pass. This is important as the value is later used in insn
65 scheduling (to see what can go in a delay slot).
66 APPARENT_FSIZE is the size of the stack less the register save area and less
67 the outgoing argument area. It is used when saving call preserved regs. */
68 static int apparent_fsize;
69 static int actual_fsize;
71 /* Number of live general or floating point registers needed to be
72 saved (as 4-byte quantities). */
73 static int num_gfregs;
75 /* Save the operands last given to a compare for use when we
76 generate a scc or bcc insn. */
77 rtx sparc_compare_op0, sparc_compare_op1;
79 /* Coordinate with the md file wrt special insns created by
80 sparc_nonflat_function_epilogue. */
81 bool sparc_emitting_epilogue;
83 /* Vector to say how input registers are mapped to output registers.
84 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
85 eliminate it. You must use -fomit-frame-pointer to get that. */
86 char leaf_reg_remap[] =
87 { 0, 1, 2, 3, 4, 5, 6, 7,
88 -1, -1, -1, -1, -1, -1, 14, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1,
90 8, 9, 10, 11, 12, 13, -1, 15,
92 32, 33, 34, 35, 36, 37, 38, 39,
93 40, 41, 42, 43, 44, 45, 46, 47,
94 48, 49, 50, 51, 52, 53, 54, 55,
95 56, 57, 58, 59, 60, 61, 62, 63,
96 64, 65, 66, 67, 68, 69, 70, 71,
97 72, 73, 74, 75, 76, 77, 78, 79,
98 80, 81, 82, 83, 84, 85, 86, 87,
99 88, 89, 90, 91, 92, 93, 94, 95,
100 96, 97, 98, 99, 100};
102 /* Vector, indexed by hard register number, which contains 1
103 for a register that is allowable in a candidate for leaf
104 function treatment. */
105 char sparc_leaf_regs[] =
106 { 1, 1, 1, 1, 1, 1, 1, 1,
107 0, 0, 0, 0, 0, 0, 1, 0,
108 0, 0, 0, 0, 0, 0, 0, 0,
109 1, 1, 1, 1, 1, 1, 0, 1,
110 1, 1, 1, 1, 1, 1, 1, 1,
111 1, 1, 1, 1, 1, 1, 1, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
120 /* Name of where we pretend to think the frame pointer points.
121 Normally, this is "%fp", but if we are in a leaf procedure,
122 this is "%sp+something". We record "something" separately as it may be
123 too big for reg+constant addressing. */
125 static const char *frame_base_name;
126 static int frame_base_offset;
128 static void sparc_init_modes PARAMS ((void));
129 static int save_regs PARAMS ((FILE *, int, int, const char *,
131 static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int));
132 static void build_big_number PARAMS ((FILE *, int, const char *));
133 static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *,
134 enum machine_mode, tree, int, int,
137 static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
138 static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
140 static void sparc_output_addr_vec PARAMS ((rtx));
141 static void sparc_output_addr_diff_vec PARAMS ((rtx));
142 static void sparc_output_deferred_case_vectors PARAMS ((void));
143 static void sparc_add_gc_roots PARAMS ((void));
144 static int check_return_regs PARAMS ((rtx));
145 static int epilogue_renumber PARAMS ((rtx *, int));
146 static bool sparc_assemble_integer PARAMS ((rtx, unsigned int, int));
147 static int set_extends PARAMS ((rtx));
148 static void output_restore_regs PARAMS ((FILE *, int));
149 static void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
150 static void sparc_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
151 static void sparc_flat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
152 static void sparc_flat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
153 static void sparc_nonflat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT,
155 static void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT,
157 #ifdef OBJECT_FORMAT_ELF
158 static void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int));
161 static int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
162 static int sparc_issue_rate PARAMS ((void));
163 static void sparc_sched_init PARAMS ((FILE *, int, int));
164 static int sparc_use_dfa_pipeline_interface PARAMS ((void));
165 static int sparc_use_sched_lookahead PARAMS ((void));
167 static void emit_soft_tfmode_libcall PARAMS ((const char *, int, rtx *));
168 static void emit_soft_tfmode_binop PARAMS ((enum rtx_code, rtx *));
169 static void emit_soft_tfmode_unop PARAMS ((enum rtx_code, rtx *));
170 static void emit_soft_tfmode_cvt PARAMS ((enum rtx_code, rtx *));
171 static void emit_hard_tfmode_operation PARAMS ((enum rtx_code, rtx *));
173 /* Option handling. */
175 /* Code model option as passed by user. */
176 const char *sparc_cmodel_string;
178 enum cmodel sparc_cmodel;
180 char sparc_hard_reg_printed[8];
182 struct sparc_cpu_select sparc_select[] =
184 /* switch name, tune arch */
185 { (char *)0, "default", 1, 1 },
186 { (char *)0, "-mcpu=", 1, 1 },
187 { (char *)0, "-mtune=", 1, 0 },
191 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
192 enum processor_type sparc_cpu;
194 /* Initialize the GCC target structure. */
196 /* The sparc default is to use .half rather than .short for aligned
197 HI objects. Use .word instead of .long on non-ELF systems. */
198 #undef TARGET_ASM_ALIGNED_HI_OP
199 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
200 #ifndef OBJECT_FORMAT_ELF
201 #undef TARGET_ASM_ALIGNED_SI_OP
202 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
205 #undef TARGET_ASM_UNALIGNED_HI_OP
206 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
207 #undef TARGET_ASM_UNALIGNED_SI_OP
208 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
209 #undef TARGET_ASM_UNALIGNED_DI_OP
210 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
212 /* The target hook has to handle DI-mode values. */
213 #undef TARGET_ASM_INTEGER
214 #define TARGET_ASM_INTEGER sparc_assemble_integer
216 #undef TARGET_ASM_FUNCTION_PROLOGUE
217 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
218 #undef TARGET_ASM_FUNCTION_EPILOGUE
219 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
221 #undef TARGET_SCHED_ADJUST_COST
222 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
223 #undef TARGET_SCHED_ISSUE_RATE
224 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
225 #undef TARGET_SCHED_INIT
226 #define TARGET_SCHED_INIT sparc_sched_init
227 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
228 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
229 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
230 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
232 struct gcc_target targetm = TARGET_INITIALIZER;
234 /* Validate and override various options, and do some machine dependent
238 sparc_override_options ()
240 static struct code_model {
241 const char *const name;
243 } const cmodels[] = {
245 { "medlow", CM_MEDLOW },
246 { "medmid", CM_MEDMID },
247 { "medany", CM_MEDANY },
248 { "embmedany", CM_EMBMEDANY },
251 const struct code_model *cmodel;
252 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
253 static struct cpu_default {
255 const char *const name;
256 } const cpu_default[] = {
257 /* There must be one entry here for each TARGET_CPU value. */
258 { TARGET_CPU_sparc, "cypress" },
259 { TARGET_CPU_sparclet, "tsc701" },
260 { TARGET_CPU_sparclite, "f930" },
261 { TARGET_CPU_v8, "v8" },
262 { TARGET_CPU_hypersparc, "hypersparc" },
263 { TARGET_CPU_sparclite86x, "sparclite86x" },
264 { TARGET_CPU_supersparc, "supersparc" },
265 { TARGET_CPU_v9, "v9" },
266 { TARGET_CPU_ultrasparc, "ultrasparc" },
267 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
270 const struct cpu_default *def;
271 /* Table of values for -m{cpu,tune}=. */
272 static struct cpu_table {
273 const char *const name;
274 const enum processor_type processor;
277 } const cpu_table[] = {
278 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
279 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
280 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
281 /* TI TMS390Z55 supersparc */
282 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
283 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
284 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
285 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
286 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
287 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
288 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
289 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
291 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
293 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
294 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
295 /* TI ultrasparc I, II, IIi */
296 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
297 /* Although insns using %y are deprecated, it is a clear win on current
299 |MASK_DEPRECATED_V8_INSNS},
300 /* TI ultrasparc III */
301 /* ??? Check if %y issue still holds true in ultra3. */
302 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
305 const struct cpu_table *cpu;
306 const struct sparc_cpu_select *sel;
309 #ifndef SPARC_BI_ARCH
310 /* Check for unsupported architecture size. */
311 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
312 error ("%s is not supported by this configuration",
313 DEFAULT_ARCH32_P ? "-m64" : "-m32");
316 /* We force all 64bit archs to use 128 bit long double */
317 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
319 error ("-mlong-double-64 not allowed with -m64");
320 target_flags |= MASK_LONG_DOUBLE_128;
323 /* Code model selection. */
324 sparc_cmodel = SPARC_DEFAULT_CMODEL;
328 sparc_cmodel = CM_32;
331 if (sparc_cmodel_string != NULL)
335 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
336 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
338 if (cmodel->name == NULL)
339 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
341 sparc_cmodel = cmodel->value;
344 error ("-mcmodel= is not supported on 32 bit systems");
347 fpu = TARGET_FPU; /* save current -mfpu status */
349 /* Set the default CPU. */
350 for (def = &cpu_default[0]; def->name; ++def)
351 if (def->cpu == TARGET_CPU_DEFAULT)
355 sparc_select[0].string = def->name;
357 for (sel = &sparc_select[0]; sel->name; ++sel)
361 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
362 if (! strcmp (sel->string, cpu->name))
365 sparc_cpu = cpu->processor;
369 target_flags &= ~cpu->disable;
370 target_flags |= cpu->enable;
376 error ("bad value (%s) for %s switch", sel->string, sel->name);
380 /* If -mfpu or -mno-fpu was explicitly used, don't override with
381 the processor default. Clear MASK_FPU_SET to avoid confusing
382 the reverse mapping from switch values to names. */
385 target_flags = (target_flags & ~MASK_FPU) | fpu;
386 target_flags &= ~MASK_FPU_SET;
389 /* Don't allow -mvis if FPU is disabled. */
391 target_flags &= ~MASK_VIS;
393 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
395 -m64 also implies v9. */
396 if (TARGET_VIS || TARGET_ARCH64)
398 target_flags |= MASK_V9;
399 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
402 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
403 if (TARGET_V9 && TARGET_ARCH32)
404 target_flags |= MASK_DEPRECATED_V8_INSNS;
406 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
407 if (! TARGET_V9 || TARGET_ARCH64)
408 target_flags &= ~MASK_V8PLUS;
410 /* Don't use stack biasing in 32 bit mode. */
412 target_flags &= ~MASK_STACK_BIAS;
414 /* Supply a default value for align_functions. */
415 if (align_functions == 0
416 && (sparc_cpu == PROCESSOR_ULTRASPARC
417 || sparc_cpu == PROCESSOR_ULTRASPARC3))
418 align_functions = 32;
420 /* Validate PCC_STRUCT_RETURN. */
421 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
422 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
424 /* Only use .uaxword when compiling for a 64-bit target. */
426 targetm.asm_out.unaligned_op.di = NULL;
428 /* Do various machine dependent initializations. */
431 /* Register global variables with the garbage collector. */
432 sparc_add_gc_roots ();
435 /* Miscellaneous utilities. */
437 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
438 or branch on register contents instructions. */
444 return (code == EQ || code == NE || code == GE || code == LT
445 || code == LE || code == GT);
449 /* Operand constraints. */
451 /* Return non-zero only if OP is a register of mode MODE,
455 reg_or_0_operand (op, mode)
457 enum machine_mode mode;
459 if (register_operand (op, mode))
461 if (op == const0_rtx)
463 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
464 && CONST_DOUBLE_HIGH (op) == 0
465 && CONST_DOUBLE_LOW (op) == 0)
467 if (fp_zero_operand (op, mode))
472 /* Return non-zero only if OP is const1_rtx. */
475 const1_operand (op, mode)
477 enum machine_mode mode ATTRIBUTE_UNUSED;
479 return op == const1_rtx;
482 /* Nonzero if OP is a floating point value with value 0.0. */
485 fp_zero_operand (op, mode)
487 enum machine_mode mode;
489 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
491 return op == CONST0_RTX (mode);
494 /* Nonzero if OP is a register operand in floating point register. */
497 fp_register_operand (op, mode)
499 enum machine_mode mode;
501 if (! register_operand (op, mode))
503 if (GET_CODE (op) == SUBREG)
504 op = SUBREG_REG (op);
505 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
508 /* Nonzero if OP is a floating point constant which can
509 be loaded into an integer register using a single
510 sethi instruction. */
516 if (GET_CODE (op) == CONST_DOUBLE)
521 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
522 if (REAL_VALUES_EQUAL (r, dconst0) &&
523 ! REAL_VALUE_MINUS_ZERO (r))
525 REAL_VALUE_TO_TARGET_SINGLE (r, i);
526 if (SPARC_SETHI_P (i))
533 /* Nonzero if OP is a floating point constant which can
534 be loaded into an integer register using a single
541 if (GET_CODE (op) == CONST_DOUBLE)
546 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
547 if (REAL_VALUES_EQUAL (r, dconst0) &&
548 ! REAL_VALUE_MINUS_ZERO (r))
550 REAL_VALUE_TO_TARGET_SINGLE (r, i);
551 if (SPARC_SIMM13_P (i))
558 /* Nonzero if OP is a floating point constant which can
559 be loaded into an integer register using a high/losum
560 instruction sequence. */
566 /* The constraints calling this should only be in
567 SFmode move insns, so any constant which cannot
568 be moved using a single insn will do. */
569 if (GET_CODE (op) == CONST_DOUBLE)
574 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
575 if (REAL_VALUES_EQUAL (r, dconst0) &&
576 ! REAL_VALUE_MINUS_ZERO (r))
578 REAL_VALUE_TO_TARGET_SINGLE (r, i);
579 if (! SPARC_SETHI_P (i)
580 && ! SPARC_SIMM13_P (i))
587 /* Nonzero if OP is an integer register. */
590 intreg_operand (op, mode)
592 enum machine_mode mode ATTRIBUTE_UNUSED;
594 return (register_operand (op, SImode)
595 || (TARGET_ARCH64 && register_operand (op, DImode)));
598 /* Nonzero if OP is a floating point condition code register. */
601 fcc_reg_operand (op, mode)
603 enum machine_mode mode;
605 /* This can happen when recog is called from combine. Op may be a MEM.
606 Fail instead of calling abort in this case. */
607 if (GET_CODE (op) != REG)
610 if (mode != VOIDmode && mode != GET_MODE (op))
613 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
616 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
617 if (reg_renumber == 0)
618 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
619 return REGNO_OK_FOR_CCFP_P (REGNO (op));
621 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
625 /* Nonzero if OP is a floating point condition code fcc0 register. */
628 fcc0_reg_operand (op, mode)
630 enum machine_mode mode;
632 /* This can happen when recog is called from combine. Op may be a MEM.
633 Fail instead of calling abort in this case. */
634 if (GET_CODE (op) != REG)
637 if (mode != VOIDmode && mode != GET_MODE (op))
640 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
643 return REGNO (op) == SPARC_FCC_REG;
646 /* Nonzero if OP is an integer or floating point condition code register. */
649 icc_or_fcc_reg_operand (op, mode)
651 enum machine_mode mode;
653 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
655 if (mode != VOIDmode && mode != GET_MODE (op))
658 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
663 return fcc_reg_operand (op, mode);
666 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
668 restore_operand (op, mode)
670 enum machine_mode mode;
672 return (GET_CODE (op) == REG && GET_MODE (op) == mode
673 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
676 /* Call insn on SPARC can take a PC-relative constant address, or any regular
680 call_operand (op, mode)
682 enum machine_mode mode;
684 if (GET_CODE (op) != MEM)
687 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
691 call_operand_address (op, mode)
693 enum machine_mode mode;
695 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
698 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
699 reference and a constant. */
702 symbolic_operand (op, mode)
704 enum machine_mode mode;
706 enum machine_mode omode = GET_MODE (op);
708 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
711 switch (GET_CODE (op))
719 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
720 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
721 && GET_CODE (XEXP (op, 1)) == CONST_INT);
728 /* Return truth value of statement that OP is a symbolic memory
729 operand of mode MODE. */
732 symbolic_memory_operand (op, mode)
734 enum machine_mode mode ATTRIBUTE_UNUSED;
736 if (GET_CODE (op) == SUBREG)
737 op = SUBREG_REG (op);
738 if (GET_CODE (op) != MEM)
741 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
742 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
745 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
748 label_ref_operand (op, mode)
750 enum machine_mode mode;
752 if (GET_CODE (op) != LABEL_REF)
754 if (GET_MODE (op) != mode)
759 /* Return 1 if the operand is an argument used in generating pic references
760 in either the medium/low or medium/anywhere code models of sparc64. */
763 sp64_medium_pic_operand (op, mode)
765 enum machine_mode mode ATTRIBUTE_UNUSED;
767 /* Check for (const (minus (symbol_ref:GOT)
768 (const (minus (label) (pc))))). */
769 if (GET_CODE (op) != CONST)
772 if (GET_CODE (op) != MINUS)
774 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
776 /* ??? Ensure symbol is GOT. */
777 if (GET_CODE (XEXP (op, 1)) != CONST)
779 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
784 /* Return 1 if the operand is a data segment reference. This includes
785 the readonly data segment, or in other words anything but the text segment.
786 This is needed in the medium/anywhere code model on v9. These values
787 are accessed with EMBMEDANY_BASE_REG. */
790 data_segment_operand (op, mode)
792 enum machine_mode mode ATTRIBUTE_UNUSED;
794 switch (GET_CODE (op))
797 return ! SYMBOL_REF_FLAG (op);
799 /* Assume canonical format of symbol + constant.
802 return data_segment_operand (XEXP (op, 0), VOIDmode);
808 /* Return 1 if the operand is a text segment reference.
809 This is needed in the medium/anywhere code model on v9. */
812 text_segment_operand (op, mode)
814 enum machine_mode mode ATTRIBUTE_UNUSED;
816 switch (GET_CODE (op))
821 return SYMBOL_REF_FLAG (op);
823 /* Assume canonical format of symbol + constant.
826 return text_segment_operand (XEXP (op, 0), VOIDmode);
832 /* Return 1 if the operand is either a register or a memory operand that is
836 reg_or_nonsymb_mem_operand (op, mode)
838 enum machine_mode mode;
840 if (register_operand (op, mode))
843 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
850 splittable_symbolic_memory_operand (op, mode)
852 enum machine_mode mode ATTRIBUTE_UNUSED;
854 if (GET_CODE (op) != MEM)
856 if (! symbolic_operand (XEXP (op, 0), Pmode))
862 splittable_immediate_memory_operand (op, mode)
864 enum machine_mode mode ATTRIBUTE_UNUSED;
866 if (GET_CODE (op) != MEM)
868 if (! immediate_operand (XEXP (op, 0), Pmode))
873 /* Return truth value of whether OP is EQ or NE. */
878 enum machine_mode mode ATTRIBUTE_UNUSED;
880 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
883 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
884 or LTU for non-floating-point. We handle those specially. */
887 normal_comp_operator (op, mode)
889 enum machine_mode mode ATTRIBUTE_UNUSED;
891 enum rtx_code code = GET_CODE (op);
893 if (GET_RTX_CLASS (code) != '<')
896 if (GET_MODE (XEXP (op, 0)) == CCFPmode
897 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
900 return (code != NE && code != EQ && code != GEU && code != LTU);
903 /* Return 1 if this is a comparison operator. This allows the use of
904 MATCH_OPERATOR to recognize all the branch insns. */
907 noov_compare_op (op, mode)
909 enum machine_mode mode ATTRIBUTE_UNUSED;
911 enum rtx_code code = GET_CODE (op);
913 if (GET_RTX_CLASS (code) != '<')
916 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
917 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
918 /* These are the only branches which work with CC_NOOVmode. */
919 return (code == EQ || code == NE || code == GE || code == LT);
923 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
924 MATCH_OPERATOR to recognize all the branch insns. */
927 noov_compare64_op (op, mode)
929 enum machine_mode mode ATTRIBUTE_UNUSED;
931 enum rtx_code code = GET_CODE (op);
936 if (GET_RTX_CLASS (code) != '<')
939 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
940 /* These are the only branches which work with CCX_NOOVmode. */
941 return (code == EQ || code == NE || code == GE || code == LT);
942 return (GET_MODE (XEXP (op, 0)) == CCXmode);
945 /* Nonzero if OP is a comparison operator suitable for use in v9
946 conditional move or branch on register contents instructions. */
949 v9_regcmp_op (op, mode)
951 enum machine_mode mode ATTRIBUTE_UNUSED;
953 enum rtx_code code = GET_CODE (op);
955 if (GET_RTX_CLASS (code) != '<')
958 return v9_regcmp_p (code);
961 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
966 enum machine_mode mode ATTRIBUTE_UNUSED;
968 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
971 /* Return nonzero if OP is an operator of mode MODE which can set
972 the condition codes explicitly. We do not include PLUS and MINUS
973 because these require CC_NOOVmode, which we handle explicitly. */
976 cc_arithop (op, mode)
978 enum machine_mode mode ATTRIBUTE_UNUSED;
980 if (GET_CODE (op) == AND
981 || GET_CODE (op) == IOR
982 || GET_CODE (op) == XOR)
988 /* Return nonzero if OP is an operator of mode MODE which can bitwise
989 complement its second operand and set the condition codes explicitly. */
992 cc_arithopn (op, mode)
994 enum machine_mode mode ATTRIBUTE_UNUSED;
996 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
997 and (xor ... (not ...)) to (not (xor ...)). */
998 return (GET_CODE (op) == AND
999 || GET_CODE (op) == IOR);
1002 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1003 signed 13 bit immediate field. This is an acceptable SImode operand for
1004 most 3 address instructions. */
1007 arith_operand (op, mode)
1009 enum machine_mode mode;
1011 if (register_operand (op, mode))
1013 if (GET_CODE (op) != CONST_INT)
1015 return SMALL_INT32 (op);
1018 /* Return true if OP is a constant 4096 */
1021 arith_4096_operand (op, mode)
1023 enum machine_mode mode ATTRIBUTE_UNUSED;
1025 if (GET_CODE (op) != CONST_INT)
1028 return INTVAL (op) == 4096;
1031 /* Return true if OP is suitable as second operand for add/sub */
1034 arith_add_operand (op, mode)
1036 enum machine_mode mode;
1038 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1041 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1042 immediate field of OR and XOR instructions. Used for 64-bit
1043 constant formation patterns. */
1045 const64_operand (op, mode)
1047 enum machine_mode mode ATTRIBUTE_UNUSED;
1049 return ((GET_CODE (op) == CONST_INT
1050 && SPARC_SIMM13_P (INTVAL (op)))
1051 #if HOST_BITS_PER_WIDE_INT != 64
1052 || (GET_CODE (op) == CONST_DOUBLE
1053 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1054 && (CONST_DOUBLE_HIGH (op) ==
1055 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1056 (HOST_WIDE_INT)-1 : 0)))
1061 /* The same, but only for sethi instructions. */
1063 const64_high_operand (op, mode)
1065 enum machine_mode mode;
1067 return ((GET_CODE (op) == CONST_INT
1068 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1069 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1071 || (GET_CODE (op) == CONST_DOUBLE
1072 && CONST_DOUBLE_HIGH (op) == 0
1073 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1074 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1077 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1078 signed 11 bit immediate field. This is an acceptable SImode operand for
1079 the movcc instructions. */
1082 arith11_operand (op, mode)
1084 enum machine_mode mode;
1086 return (register_operand (op, mode)
1087 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1090 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1091 signed 10 bit immediate field. This is an acceptable SImode operand for
1092 the movrcc instructions. */
1095 arith10_operand (op, mode)
1097 enum machine_mode mode;
1099 return (register_operand (op, mode)
1100 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1103 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1104 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1106 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1107 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1108 for most 3 address instructions. */
1111 arith_double_operand (op, mode)
1113 enum machine_mode mode;
1115 return (register_operand (op, mode)
1116 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1118 && GET_CODE (op) == CONST_DOUBLE
1119 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1120 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1122 && GET_CODE (op) == CONST_DOUBLE
1123 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1124 && ((CONST_DOUBLE_HIGH (op) == -1
1125 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1126 || (CONST_DOUBLE_HIGH (op) == 0
1127 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1130 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1133 arith_double_4096_operand (op, mode)
1135 enum machine_mode mode ATTRIBUTE_UNUSED;
1137 return (TARGET_ARCH64 &&
1138 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1139 (GET_CODE (op) == CONST_DOUBLE &&
1140 CONST_DOUBLE_LOW (op) == 4096 &&
1141 CONST_DOUBLE_HIGH (op) == 0)));
1144 /* Return true if OP is suitable as second operand for add/sub in DImode */
1147 arith_double_add_operand (op, mode)
1149 enum machine_mode mode;
1151 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1154 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1155 can fit in an 11 bit immediate field. This is an acceptable DImode
1156 operand for the movcc instructions. */
1157 /* ??? Replace with arith11_operand? */
1160 arith11_double_operand (op, mode)
1162 enum machine_mode mode;
1164 return (register_operand (op, mode)
1165 || (GET_CODE (op) == CONST_DOUBLE
1166 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1167 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1168 && ((CONST_DOUBLE_HIGH (op) == -1
1169 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1170 || (CONST_DOUBLE_HIGH (op) == 0
1171 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1172 || (GET_CODE (op) == CONST_INT
1173 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1174 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1177 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1178 can fit in an 10 bit immediate field. This is an acceptable DImode
1179 operand for the movrcc instructions. */
1180 /* ??? Replace with arith10_operand? */
1183 arith10_double_operand (op, mode)
1185 enum machine_mode mode;
1187 return (register_operand (op, mode)
1188 || (GET_CODE (op) == CONST_DOUBLE
1189 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1190 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1191 && ((CONST_DOUBLE_HIGH (op) == -1
1192 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1193 || (CONST_DOUBLE_HIGH (op) == 0
1194 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1195 || (GET_CODE (op) == CONST_INT
1196 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1197 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1200 /* Return truth value of whether OP is an integer which fits the
1201 range constraining immediate operands in most three-address insns,
1202 which have a 13 bit immediate field. */
1205 small_int (op, mode)
1207 enum machine_mode mode ATTRIBUTE_UNUSED;
1209 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1213 small_int_or_double (op, mode)
1215 enum machine_mode mode ATTRIBUTE_UNUSED;
1217 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1218 || (GET_CODE (op) == CONST_DOUBLE
1219 && CONST_DOUBLE_HIGH (op) == 0
1220 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1223 /* Recognize operand values for the umul instruction. That instruction sign
1224 extends immediate values just like all other sparc instructions, but
1225 interprets the extended result as an unsigned number. */
1228 uns_small_int (op, mode)
1230 enum machine_mode mode ATTRIBUTE_UNUSED;
1232 #if HOST_BITS_PER_WIDE_INT > 32
1233 /* All allowed constants will fit a CONST_INT. */
1234 return (GET_CODE (op) == CONST_INT
1235 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1236 || (INTVAL (op) >= 0xFFFFF000
1237 && INTVAL (op) <= 0xFFFFFFFF)));
1239 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1240 || (GET_CODE (op) == CONST_DOUBLE
1241 && CONST_DOUBLE_HIGH (op) == 0
1242 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1247 uns_arith_operand (op, mode)
1249 enum machine_mode mode;
1251 return register_operand (op, mode) || uns_small_int (op, mode);
1254 /* Return truth value of statement that OP is a call-clobbered register. */
1256 clobbered_register (op, mode)
1258 enum machine_mode mode ATTRIBUTE_UNUSED;
1260 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1263 /* Return 1 if OP is a valid operand for the source of a move insn. */
1266 input_operand (op, mode)
1268 enum machine_mode mode;
1270 /* If both modes are non-void they must be the same. */
1271 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1274 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1275 if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX)
1278 /* Allow any one instruction integer constant, and all CONST_INT
1279 variants when we are working in DImode and !arch64. */
1280 if (GET_MODE_CLASS (mode) == MODE_INT
1281 && ((GET_CODE (op) == CONST_INT
1282 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1283 || SPARC_SIMM13_P (INTVAL (op))
1285 && ! TARGET_ARCH64)))
1287 && GET_CODE (op) == CONST_DOUBLE
1288 && ((CONST_DOUBLE_HIGH (op) == 0
1289 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1291 #if HOST_BITS_PER_WIDE_INT == 64
1292 (CONST_DOUBLE_HIGH (op) == 0
1293 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1295 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1296 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1297 && CONST_DOUBLE_HIGH (op) == 0)
1298 || (CONST_DOUBLE_HIGH (op) == -1
1299 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1304 /* If !arch64 and this is a DImode const, allow it so that
1305 the splits can be generated. */
1308 && GET_CODE (op) == CONST_DOUBLE)
1311 if (register_operand (op, mode))
1314 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1315 && GET_CODE (op) == CONST_DOUBLE)
1318 /* If this is a SUBREG, look inside so that we handle
1319 paradoxical ones. */
1320 if (GET_CODE (op) == SUBREG)
1321 op = SUBREG_REG (op);
1323 /* Check for valid MEM forms. */
1324 if (GET_CODE (op) == MEM)
1326 rtx inside = XEXP (op, 0);
1328 if (GET_CODE (inside) == LO_SUM)
1330 /* We can't allow these because all of the splits
1331 (eventually as they trickle down into DFmode
1332 splits) require offsettable memory references. */
1334 && GET_MODE (op) == TFmode)
1337 return (register_operand (XEXP (inside, 0), Pmode)
1338 && CONSTANT_P (XEXP (inside, 1)));
1340 return memory_address_p (mode, inside);
1347 /* We know it can't be done in one insn when we get here,
1348 the movsi expander guarentees this. */
1350 sparc_emit_set_const32 (op0, op1)
1354 enum machine_mode mode = GET_MODE (op0);
1357 if (GET_CODE (op1) == CONST_INT)
1359 HOST_WIDE_INT value = INTVAL (op1);
1361 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1362 || SPARC_SIMM13_P (value))
1366 /* Full 2-insn decomposition is needed. */
1367 if (reload_in_progress || reload_completed)
1370 temp = gen_reg_rtx (mode);
1372 if (GET_CODE (op1) == CONST_INT)
1374 /* Emit them as real moves instead of a HIGH/LO_SUM,
1375 this way CSE can see everything and reuse intermediate
1376 values if it wants. */
1378 && HOST_BITS_PER_WIDE_INT != 64
1379 && (INTVAL (op1) & 0x80000000) != 0)
1380 emit_insn (gen_rtx_SET
1382 gen_rtx_CONST_DOUBLE (VOIDmode,
1383 INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1386 emit_insn (gen_rtx_SET (VOIDmode, temp,
1387 GEN_INT (INTVAL (op1)
1388 & ~(HOST_WIDE_INT)0x3ff)));
1390 emit_insn (gen_rtx_SET (VOIDmode,
1392 gen_rtx_IOR (mode, temp,
1393 GEN_INT (INTVAL (op1) & 0x3ff))));
1397 /* A symbol, emit in the traditional way. */
1398 emit_insn (gen_rtx_SET (VOIDmode, temp,
1399 gen_rtx_HIGH (mode, op1)));
1400 emit_insn (gen_rtx_SET (VOIDmode,
1401 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1407 /* Sparc-v9 code-model support. */
1409 sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1416 if (temp1 && GET_MODE (temp1) == TImode)
1419 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1422 switch (sparc_cmodel)
1425 /* The range spanned by all instructions in the object is less
1426 than 2^31 bytes (2GB) and the distance from any instruction
1427 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1428 than 2^31 bytes (2GB).
1430 The executable must be in the low 4TB of the virtual address
1433 sethi %hi(symbol), %temp
1434 or %temp, %lo(symbol), %reg */
1435 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1436 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1440 /* The range spanned by all instructions in the object is less
1441 than 2^31 bytes (2GB) and the distance from any instruction
1442 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1443 than 2^31 bytes (2GB).
1445 The executable must be in the low 16TB of the virtual address
1448 sethi %h44(symbol), %temp1
1449 or %temp1, %m44(symbol), %temp2
1450 sllx %temp2, 12, %temp3
1451 or %temp3, %l44(symbol), %reg */
1452 emit_insn (gen_seth44 (op0, op1));
1453 emit_insn (gen_setm44 (op0, op0, op1));
1454 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1455 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1456 emit_insn (gen_setl44 (op0, temp1, op1));
1460 /* The range spanned by all instructions in the object is less
1461 than 2^31 bytes (2GB) and the distance from any instruction
1462 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1463 than 2^31 bytes (2GB).
1465 The executable can be placed anywhere in the virtual address
1468 sethi %hh(symbol), %temp1
1469 sethi %lm(symbol), %temp2
1470 or %temp1, %hm(symbol), %temp3
1471 or %temp2, %lo(symbol), %temp4
1472 sllx %temp3, 32, %temp5
1473 or %temp4, %temp5, %reg */
1475 /* It is possible that one of the registers we got for operands[2]
1476 might coincide with that of operands[0] (which is why we made
1477 it TImode). Pick the other one to use as our scratch. */
1478 if (rtx_equal_p (temp1, op0))
1481 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1486 emit_insn (gen_sethh (op0, op1));
1487 emit_insn (gen_setlm (temp1, op1));
1488 emit_insn (gen_sethm (op0, op0, op1));
1489 emit_insn (gen_rtx_SET (VOIDmode, op0,
1490 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1491 emit_insn (gen_rtx_SET (VOIDmode, op0,
1492 gen_rtx_PLUS (DImode, op0, temp1)));
1493 emit_insn (gen_setlo (op0, op0, op1));
1497 /* Old old old backwards compatibility kruft here.
1498 Essentially it is MEDLOW with a fixed 64-bit
1499 virtual base added to all data segment addresses.
1500 Text-segment stuff is computed like MEDANY, we can't
1501 reuse the code above because the relocation knobs
1504 Data segment: sethi %hi(symbol), %temp1
1505 or %temp1, %lo(symbol), %temp2
1506 add %temp2, EMBMEDANY_BASE_REG, %reg
1508 Text segment: sethi %uhi(symbol), %temp1
1509 sethi %hi(symbol), %temp2
1510 or %temp1, %ulo(symbol), %temp3
1511 or %temp2, %lo(symbol), %temp4
1512 sllx %temp3, 32, %temp5
1513 or %temp4, %temp5, %reg */
1514 if (data_segment_operand (op1, GET_MODE (op1)))
1516 emit_insn (gen_embmedany_sethi (temp1, op1));
1517 emit_insn (gen_embmedany_brsum (op0, temp1));
1518 emit_insn (gen_embmedany_losum (op0, op0, op1));
1522 /* It is possible that one of the registers we got for operands[2]
1523 might coincide with that of operands[0] (which is why we made
1524 it TImode). Pick the other one to use as our scratch. */
1525 if (rtx_equal_p (temp1, op0))
1528 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1533 emit_insn (gen_embmedany_textuhi (op0, op1));
1534 emit_insn (gen_embmedany_texthi (temp1, op1));
1535 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1536 emit_insn (gen_rtx_SET (VOIDmode, op0,
1537 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1538 emit_insn (gen_rtx_SET (VOIDmode, op0,
1539 gen_rtx_PLUS (DImode, op0, temp1)));
1540 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1549 /* These avoid problems when cross compiling. If we do not
1550 go through all this hair then the optimizer will see
1551 invalid REG_EQUAL notes or in some cases none at all. */
1552 static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT));
1553 static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT));
1554 static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT));
1555 static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
1557 #if HOST_BITS_PER_WIDE_INT == 64
1558 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1559 #define GEN_INT64(__x) GEN_INT (__x)
1561 #define GEN_HIGHINT64(__x) \
1562 gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & ~(HOST_WIDE_INT)0x3ff, 0)
1563 #define GEN_INT64(__x) \
1564 gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & 0xffffffff, \
1565 ((__x) & 0x80000000 \
1569 /* The optimizer is not to assume anything about exactly
1570 which bits are set for a HIGH, they are unspecified.
1571 Unfortunately this leads to many missed optimizations
1572 during CSE. We mask out the non-HIGH bits, and matches
1573 a plain movdi, to alleviate this problem. */
1575 sparc_emit_set_safe_HIGH64 (dest, val)
1579 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1583 gen_safe_SET64 (dest, val)
1587 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1591 gen_safe_OR64 (src, val)
1595 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1599 gen_safe_XOR64 (src, val)
1603 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1606 /* Worker routines for 64-bit constant formation on arch64.
1607 One of the key things to be doing in these emissions is
1608 to create as many temp REGs as possible. This makes it
1609 possible for half-built constants to be used later when
1610 such values are similar to something required later on.
1611 Without doing this, the optimizer cannot see such
1614 static void sparc_emit_set_const64_quick1
1615 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int));
1618 sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1621 unsigned HOST_WIDE_INT low_bits;
1624 unsigned HOST_WIDE_INT high_bits;
1627 high_bits = (~low_bits) & 0xffffffff;
1629 high_bits = low_bits;
1631 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1634 emit_insn (gen_rtx_SET (VOIDmode, op0,
1635 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1639 /* If we are XOR'ing with -1, then we should emit a one's complement
1640 instead. This way the combiner will notice logical operations
1641 such as ANDN later on and substitute. */
1642 if ((low_bits & 0x3ff) == 0x3ff)
1644 emit_insn (gen_rtx_SET (VOIDmode, op0,
1645 gen_rtx_NOT (DImode, temp)));
1649 emit_insn (gen_rtx_SET (VOIDmode, op0,
1650 gen_safe_XOR64 (temp,
1651 (-(HOST_WIDE_INT)0x400
1652 | (low_bits & 0x3ff)))));
1657 static void sparc_emit_set_const64_quick2
1658 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT,
1659 unsigned HOST_WIDE_INT, int));
1662 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1665 unsigned HOST_WIDE_INT high_bits;
1666 unsigned HOST_WIDE_INT low_immediate;
1671 if ((high_bits & 0xfffffc00) != 0)
1673 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1674 if ((high_bits & ~0xfffffc00) != 0)
1675 emit_insn (gen_rtx_SET (VOIDmode, op0,
1676 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1682 emit_insn (gen_safe_SET64 (temp, high_bits));
1686 /* Now shift it up into place. */
1687 emit_insn (gen_rtx_SET (VOIDmode, op0,
1688 gen_rtx_ASHIFT (DImode, temp2,
1689 GEN_INT (shift_count))));
1691 /* If there is a low immediate part piece, finish up by
1692 putting that in as well. */
1693 if (low_immediate != 0)
1694 emit_insn (gen_rtx_SET (VOIDmode, op0,
1695 gen_safe_OR64 (op0, low_immediate)));
1698 static void sparc_emit_set_const64_longway
1699 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1701 /* Full 64-bit constant decomposition. Even though this is the
1702 'worst' case, we still optimize a few things away. */
1704 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1707 unsigned HOST_WIDE_INT high_bits;
1708 unsigned HOST_WIDE_INT low_bits;
1712 if (reload_in_progress || reload_completed)
1715 sub_temp = gen_reg_rtx (DImode);
1717 if ((high_bits & 0xfffffc00) != 0)
1719 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1720 if ((high_bits & ~0xfffffc00) != 0)
1721 emit_insn (gen_rtx_SET (VOIDmode,
1723 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1729 emit_insn (gen_safe_SET64 (temp, high_bits));
1733 if (!reload_in_progress && !reload_completed)
1735 rtx temp2 = gen_reg_rtx (DImode);
1736 rtx temp3 = gen_reg_rtx (DImode);
1737 rtx temp4 = gen_reg_rtx (DImode);
1739 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1740 gen_rtx_ASHIFT (DImode, sub_temp,
1743 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1744 if ((low_bits & ~0xfffffc00) != 0)
1746 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1747 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1748 emit_insn (gen_rtx_SET (VOIDmode, op0,
1749 gen_rtx_PLUS (DImode, temp4, temp3)));
1753 emit_insn (gen_rtx_SET (VOIDmode, op0,
1754 gen_rtx_PLUS (DImode, temp4, temp2)));
1759 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1760 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1761 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1764 /* We are in the middle of reload, so this is really
1765 painful. However we do still make an attempt to
1766 avoid emitting truly stupid code. */
1767 if (low1 != const0_rtx)
1769 emit_insn (gen_rtx_SET (VOIDmode, op0,
1770 gen_rtx_ASHIFT (DImode, sub_temp,
1771 GEN_INT (to_shift))));
1772 emit_insn (gen_rtx_SET (VOIDmode, op0,
1773 gen_rtx_IOR (DImode, op0, low1)));
1781 if (low2 != const0_rtx)
1783 emit_insn (gen_rtx_SET (VOIDmode, op0,
1784 gen_rtx_ASHIFT (DImode, sub_temp,
1785 GEN_INT (to_shift))));
1786 emit_insn (gen_rtx_SET (VOIDmode, op0,
1787 gen_rtx_IOR (DImode, op0, low2)));
1795 emit_insn (gen_rtx_SET (VOIDmode, op0,
1796 gen_rtx_ASHIFT (DImode, sub_temp,
1797 GEN_INT (to_shift))));
1798 if (low3 != const0_rtx)
1799 emit_insn (gen_rtx_SET (VOIDmode, op0,
1800 gen_rtx_IOR (DImode, op0, low3)));
1805 /* Analyze a 64-bit constant for certain properties. */
1806 static void analyze_64bit_constant
1807 PARAMS ((unsigned HOST_WIDE_INT,
1808 unsigned HOST_WIDE_INT,
1809 int *, int *, int *));
1812 analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
1813 unsigned HOST_WIDE_INT high_bits, low_bits;
1814 int *hbsp, *lbsp, *abbasp;
1816 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1819 lowest_bit_set = highest_bit_set = -1;
1823 if ((lowest_bit_set == -1)
1824 && ((low_bits >> i) & 1))
1826 if ((highest_bit_set == -1)
1827 && ((high_bits >> (32 - i - 1)) & 1))
1828 highest_bit_set = (64 - i - 1);
1831 && ((highest_bit_set == -1)
1832 || (lowest_bit_set == -1)));
1838 if ((lowest_bit_set == -1)
1839 && ((high_bits >> i) & 1))
1840 lowest_bit_set = i + 32;
1841 if ((highest_bit_set == -1)
1842 && ((low_bits >> (32 - i - 1)) & 1))
1843 highest_bit_set = 32 - i - 1;
1846 && ((highest_bit_set == -1)
1847 || (lowest_bit_set == -1)));
1849 /* If there are no bits set this should have gone out
1850 as one instruction! */
1851 if (lowest_bit_set == -1
1852 || highest_bit_set == -1)
1854 all_bits_between_are_set = 1;
1855 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1859 if ((low_bits & (1 << i)) != 0)
1864 if ((high_bits & (1 << (i - 32))) != 0)
1867 all_bits_between_are_set = 0;
1870 *hbsp = highest_bit_set;
1871 *lbsp = lowest_bit_set;
1872 *abbasp = all_bits_between_are_set;
1875 static int const64_is_2insns
1876 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1879 const64_is_2insns (high_bits, low_bits)
1880 unsigned HOST_WIDE_INT high_bits, low_bits;
1882 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1885 || high_bits == 0xffffffff)
1888 analyze_64bit_constant (high_bits, low_bits,
1889 &highest_bit_set, &lowest_bit_set,
1890 &all_bits_between_are_set);
1892 if ((highest_bit_set == 63
1893 || lowest_bit_set == 0)
1894 && all_bits_between_are_set != 0)
1897 if ((highest_bit_set - lowest_bit_set) < 21)
1903 static unsigned HOST_WIDE_INT create_simple_focus_bits
1904 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
1907 static unsigned HOST_WIDE_INT
1908 create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
1909 unsigned HOST_WIDE_INT high_bits, low_bits;
1910 int lowest_bit_set, shift;
1912 HOST_WIDE_INT hi, lo;
1914 if (lowest_bit_set < 32)
1916 lo = (low_bits >> lowest_bit_set) << shift;
1917 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1922 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1929 /* Here we are sure to be arch64 and this is an integer constant
1930 being loaded into a register. Emit the most efficient
1931 insn sequence possible. Detection of all the 1-insn cases
1932 has been done already. */
1934 sparc_emit_set_const64 (op0, op1)
1938 unsigned HOST_WIDE_INT high_bits, low_bits;
1939 int lowest_bit_set, highest_bit_set;
1940 int all_bits_between_are_set;
1943 /* Sanity check that we know what we are working with. */
1944 if (! TARGET_ARCH64)
1947 if (GET_CODE (op0) != SUBREG)
1949 if (GET_CODE (op0) != REG
1950 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1951 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1955 if (reload_in_progress || reload_completed)
1958 temp = gen_reg_rtx (DImode);
1960 if (GET_CODE (op1) != CONST_DOUBLE
1961 && GET_CODE (op1) != CONST_INT)
1963 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1967 if (GET_CODE (op1) == CONST_DOUBLE)
1969 #if HOST_BITS_PER_WIDE_INT == 64
1970 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1971 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1973 high_bits = CONST_DOUBLE_HIGH (op1);
1974 low_bits = CONST_DOUBLE_LOW (op1);
1979 #if HOST_BITS_PER_WIDE_INT == 64
1980 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1981 low_bits = (INTVAL (op1) & 0xffffffff);
1983 high_bits = ((INTVAL (op1) < 0) ?
1986 low_bits = INTVAL (op1);
1990 /* low_bits bits 0 --> 31
1991 high_bits bits 32 --> 63 */
1993 analyze_64bit_constant (high_bits, low_bits,
1994 &highest_bit_set, &lowest_bit_set,
1995 &all_bits_between_are_set);
1997 /* First try for a 2-insn sequence. */
1999 /* These situations are preferred because the optimizer can
2000 * do more things with them:
2002 * sllx %reg, shift, %reg
2004 * srlx %reg, shift, %reg
2005 * 3) mov some_small_const, %reg
2006 * sllx %reg, shift, %reg
2008 if (((highest_bit_set == 63
2009 || lowest_bit_set == 0)
2010 && all_bits_between_are_set != 0)
2011 || ((highest_bit_set - lowest_bit_set) < 12))
2013 HOST_WIDE_INT the_const = -1;
2014 int shift = lowest_bit_set;
2016 if ((highest_bit_set != 63
2017 && lowest_bit_set != 0)
2018 || all_bits_between_are_set == 0)
2021 create_simple_focus_bits (high_bits, low_bits,
2024 else if (lowest_bit_set == 0)
2025 shift = -(63 - highest_bit_set);
2027 if (! SPARC_SIMM13_P (the_const))
2030 emit_insn (gen_safe_SET64 (temp, the_const));
2032 emit_insn (gen_rtx_SET (VOIDmode,
2034 gen_rtx_ASHIFT (DImode,
2038 emit_insn (gen_rtx_SET (VOIDmode,
2040 gen_rtx_LSHIFTRT (DImode,
2042 GEN_INT (-shift))));
2048 /* Now a range of 22 or less bits set somewhere.
2049 * 1) sethi %hi(focus_bits), %reg
2050 * sllx %reg, shift, %reg
2051 * 2) sethi %hi(focus_bits), %reg
2052 * srlx %reg, shift, %reg
2054 if ((highest_bit_set - lowest_bit_set) < 21)
2056 unsigned HOST_WIDE_INT focus_bits =
2057 create_simple_focus_bits (high_bits, low_bits,
2058 lowest_bit_set, 10);
2060 if (! SPARC_SETHI_P (focus_bits))
2063 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2065 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2066 if (lowest_bit_set < 10)
2067 emit_insn (gen_rtx_SET (VOIDmode,
2069 gen_rtx_LSHIFTRT (DImode, temp,
2070 GEN_INT (10 - lowest_bit_set))));
2071 else if (lowest_bit_set > 10)
2072 emit_insn (gen_rtx_SET (VOIDmode,
2074 gen_rtx_ASHIFT (DImode, temp,
2075 GEN_INT (lowest_bit_set - 10))));
2081 /* 1) sethi %hi(low_bits), %reg
2082 * or %reg, %lo(low_bits), %reg
2083 * 2) sethi %hi(~low_bits), %reg
2084 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2087 || high_bits == 0xffffffff)
2089 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2090 (high_bits == 0xffffffff));
2094 /* Now, try 3-insn sequences. */
2096 /* 1) sethi %hi(high_bits), %reg
2097 * or %reg, %lo(high_bits), %reg
2098 * sllx %reg, 32, %reg
2102 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2106 /* We may be able to do something quick
2107 when the constant is negated, so try that. */
2108 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2109 (~low_bits) & 0xfffffc00))
2111 /* NOTE: The trailing bits get XOR'd so we need the
2112 non-negated bits, not the negated ones. */
2113 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2115 if ((((~high_bits) & 0xffffffff) == 0
2116 && ((~low_bits) & 0x80000000) == 0)
2117 || (((~high_bits) & 0xffffffff) == 0xffffffff
2118 && ((~low_bits) & 0x80000000) != 0))
2120 int fast_int = (~low_bits & 0xffffffff);
2122 if ((SPARC_SETHI_P (fast_int)
2123 && (~high_bits & 0xffffffff) == 0)
2124 || SPARC_SIMM13_P (fast_int))
2125 emit_insn (gen_safe_SET64 (temp, fast_int));
2127 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2132 #if HOST_BITS_PER_WIDE_INT == 64
2133 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2134 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2136 negated_const = gen_rtx_CONST_DOUBLE (DImode,
2137 (~low_bits) & 0xfffffc00,
2138 (~high_bits) & 0xffffffff);
2140 sparc_emit_set_const64 (temp, negated_const);
2143 /* If we are XOR'ing with -1, then we should emit a one's complement
2144 instead. This way the combiner will notice logical operations
2145 such as ANDN later on and substitute. */
2146 if (trailing_bits == 0x3ff)
2148 emit_insn (gen_rtx_SET (VOIDmode, op0,
2149 gen_rtx_NOT (DImode, temp)));
2153 emit_insn (gen_rtx_SET (VOIDmode,
2155 gen_safe_XOR64 (temp,
2156 (-0x400 | trailing_bits))));
2161 /* 1) sethi %hi(xxx), %reg
2162 * or %reg, %lo(xxx), %reg
2163 * sllx %reg, yyy, %reg
2165 * ??? This is just a generalized version of the low_bits==0
2166 * thing above, FIXME...
2168 if ((highest_bit_set - lowest_bit_set) < 32)
2170 unsigned HOST_WIDE_INT focus_bits =
2171 create_simple_focus_bits (high_bits, low_bits,
2174 /* We can't get here in this state. */
2175 if (highest_bit_set < 32
2176 || lowest_bit_set >= 32)
2179 /* So what we know is that the set bits straddle the
2180 middle of the 64-bit word. */
2181 sparc_emit_set_const64_quick2 (op0, temp,
2187 /* 1) sethi %hi(high_bits), %reg
2188 * or %reg, %lo(high_bits), %reg
2189 * sllx %reg, 32, %reg
2190 * or %reg, low_bits, %reg
2192 if (SPARC_SIMM13_P(low_bits)
2193 && ((int)low_bits > 0))
2195 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2199 /* The easiest way when all else fails, is full decomposition. */
2201 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2202 high_bits, low_bits, ~high_bits, ~low_bits);
2204 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2207 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2208 return the mode to be used for the comparison. For floating-point,
2209 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2210 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2211 processing is needed. */
2214 select_cc_mode (op, x, y)
2217 rtx y ATTRIBUTE_UNUSED;
2219 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2245 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2246 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2248 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2249 return CCX_NOOVmode;
2255 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2262 /* X and Y are two things to compare using CODE. Emit the compare insn and
2263 return the rtx for the cc reg in the proper mode. */
2266 gen_compare_reg (code, x, y)
2270 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2273 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2274 fcc regs (cse can't tell they're really call clobbered regs and will
2275 remove a duplicate comparison even if there is an intervening function
2276 call - it will then try to reload the cc reg via an int reg which is why
2277 we need the movcc patterns). It is possible to provide the movcc
2278 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2279 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2280 to tell cse that CCFPE mode registers (even pseudos) are call
2283 /* ??? This is an experiment. Rather than making changes to cse which may
2284 or may not be easy/clean, we do our own cse. This is possible because
2285 we will generate hard registers. Cse knows they're call clobbered (it
2286 doesn't know the same thing about pseudos). If we guess wrong, no big
2287 deal, but if we win, great! */
2289 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2290 #if 1 /* experiment */
2293 /* We cycle through the registers to ensure they're all exercised. */
2294 static int next_fcc_reg = 0;
2295 /* Previous x,y for each fcc reg. */
2296 static rtx prev_args[4][2];
2298 /* Scan prev_args for x,y. */
2299 for (reg = 0; reg < 4; reg++)
2300 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2305 prev_args[reg][0] = x;
2306 prev_args[reg][1] = y;
2307 next_fcc_reg = (next_fcc_reg + 1) & 3;
2309 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2312 cc_reg = gen_reg_rtx (mode);
2313 #endif /* ! experiment */
2314 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2315 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2317 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2319 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2320 gen_rtx_COMPARE (mode, x, y)));
2325 /* This function is used for v9 only.
2326 CODE is the code for an Scc's comparison.
2327 OPERANDS[0] is the target of the Scc insn.
2328 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2329 been generated yet).
2331 This function is needed to turn
2334 (gt (reg:CCX 100 %icc)
2338 (gt:DI (reg:CCX 100 %icc)
2341 IE: The instruction recognizer needs to see the mode of the comparison to
2342 find the right instruction. We could use "gt:DI" right in the
2343 define_expand, but leaving it out allows us to handle DI, SI, etc.
2345 We refer to the global sparc compare operands sparc_compare_op0 and
2346 sparc_compare_op1. */
2349 gen_v9_scc (compare_code, operands)
2350 enum rtx_code compare_code;
2351 register rtx *operands;
2356 && (GET_MODE (sparc_compare_op0) == DImode
2357 || GET_MODE (operands[0]) == DImode))
2360 op0 = sparc_compare_op0;
2361 op1 = sparc_compare_op1;
2363 /* Try to use the movrCC insns. */
2365 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2366 && op1 == const0_rtx
2367 && v9_regcmp_p (compare_code))
2369 /* Special case for op0 != 0. This can be done with one instruction if
2370 operands[0] == sparc_compare_op0. */
2372 if (compare_code == NE
2373 && GET_MODE (operands[0]) == DImode
2374 && rtx_equal_p (op0, operands[0]))
2376 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2377 gen_rtx_IF_THEN_ELSE (DImode,
2378 gen_rtx_fmt_ee (compare_code, DImode,
2385 if (reg_overlap_mentioned_p (operands[0], op0))
2387 /* Handle the case where operands[0] == sparc_compare_op0.
2388 We "early clobber" the result. */
2389 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2390 emit_move_insn (op0, sparc_compare_op0);
2393 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2394 if (GET_MODE (op0) != DImode)
2396 temp = gen_reg_rtx (DImode);
2397 convert_move (temp, op0, 0);
2401 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2402 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2403 gen_rtx_fmt_ee (compare_code, DImode,
2411 operands[1] = gen_compare_reg (compare_code, op0, op1);
2413 switch (GET_MODE (operands[1]))
2423 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2424 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2425 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2426 gen_rtx_fmt_ee (compare_code,
2427 GET_MODE (operands[1]),
2428 operands[1], const0_rtx),
2429 const1_rtx, operands[0])));
2434 /* Emit a conditional jump insn for the v9 architecture using comparison code
2435 CODE and jump target LABEL.
2436 This function exists to take advantage of the v9 brxx insns. */
2439 emit_v9_brxx_insn (code, op0, label)
2443 emit_jump_insn (gen_rtx_SET (VOIDmode,
2445 gen_rtx_IF_THEN_ELSE (VOIDmode,
2446 gen_rtx_fmt_ee (code, GET_MODE (op0),
2448 gen_rtx_LABEL_REF (VOIDmode, label),
2452 /* Generate a DFmode part of a hard TFmode register.
2453 REG is the TFmode hard register, LOW is 1 for the
2454 low 64bit of the register and 0 otherwise.
2457 gen_df_reg (reg, low)
2461 int regno = REGNO (reg);
2463 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2464 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2465 return gen_rtx_REG (DFmode, regno);
2468 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2469 Unlike normal calls, TFmode operands are passed by reference. It is
2470 assumed that no more than 3 operands are required. */
2473 emit_soft_tfmode_libcall (func_name, nargs, operands)
2474 const char *func_name;
2478 rtx ret_slot = NULL, arg[3], func_sym;
2481 /* We only expect to be called for conversions, unary, and binary ops. */
2482 if (nargs < 2 || nargs > 3)
2485 for (i = 0; i < nargs; ++i)
2487 rtx this_arg = operands[i];
2490 /* TFmode arguments and return values are passed by reference. */
2491 if (GET_MODE (this_arg) == TFmode)
2493 if (GET_CODE (this_arg) == MEM)
2494 this_arg = XEXP (this_arg, 0);
2495 else if (CONSTANT_P (this_arg))
2497 this_slot = force_const_mem (TFmode, this_arg);
2498 this_arg = XEXP (this_slot, 0);
2502 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2504 /* Operand 0 is the return value. We'll copy it out later. */
2506 emit_move_insn (this_slot, this_arg);
2508 ret_slot = this_slot;
2510 this_arg = XEXP (this_slot, 0);
2517 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2519 if (GET_MODE (operands[0]) == TFmode)
2522 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2523 arg[0], GET_MODE (arg[0]),
2524 arg[1], GET_MODE (arg[1]));
2526 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2527 arg[0], GET_MODE (arg[0]),
2528 arg[1], GET_MODE (arg[1]),
2529 arg[2], GET_MODE (arg[2]));
2532 emit_move_insn (operands[0], ret_slot);
2541 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2542 GET_MODE (operands[0]), 1,
2543 arg[1], GET_MODE (arg[1]));
2545 if (ret != operands[0])
2546 emit_move_insn (operands[0], ret);
2550 /* Expand soft-float TFmode calls to sparc abi routines. */
2553 emit_soft_tfmode_binop (code, operands)
2577 emit_soft_tfmode_libcall (func, 3, operands);
2581 emit_soft_tfmode_unop (code, operands)
2596 emit_soft_tfmode_libcall (func, 2, operands);
2600 emit_soft_tfmode_cvt (code, operands)
2609 switch (GET_MODE (operands[1]))
2622 case FLOAT_TRUNCATE:
2623 switch (GET_MODE (operands[0]))
2637 switch (GET_MODE (operands[1]))
2650 case UNSIGNED_FLOAT:
2651 switch (GET_MODE (operands[1]))
2665 switch (GET_MODE (operands[0]))
2679 switch (GET_MODE (operands[0]))
2696 emit_soft_tfmode_libcall (func, 2, operands);
2699 /* Expand a hard-float tfmode operation. All arguments must be in
2703 emit_hard_tfmode_operation (code, operands)
2709 if (GET_RTX_CLASS (code) == '1')
2711 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2712 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2716 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2717 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2718 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2719 operands[1], operands[2]);
2722 if (register_operand (operands[0], VOIDmode))
2725 dest = gen_reg_rtx (GET_MODE (operands[0]));
2727 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2729 if (dest != operands[0])
2730 emit_move_insn (operands[0], dest);
2734 emit_tfmode_binop (code, operands)
2738 if (TARGET_HARD_QUAD)
2739 emit_hard_tfmode_operation (code, operands);
2741 emit_soft_tfmode_binop (code, operands);
2745 emit_tfmode_unop (code, operands)
2749 if (TARGET_HARD_QUAD)
2750 emit_hard_tfmode_operation (code, operands);
2752 emit_soft_tfmode_unop (code, operands);
2756 emit_tfmode_cvt (code, operands)
2760 if (TARGET_HARD_QUAD)
2761 emit_hard_tfmode_operation (code, operands);
2763 emit_soft_tfmode_cvt (code, operands);
2766 /* Return nonzero if a return peephole merging return with
2767 setting of output register is ok. */
2769 leaf_return_peephole_ok ()
2771 return (actual_fsize == 0);
2774 /* Return nonzero if a branch/jump/call instruction will be emitting
2775 nop into its delay slot. */
2778 empty_delay_slot (insn)
2783 /* If no previous instruction (should not happen), return true. */
2784 if (PREV_INSN (insn) == NULL)
2787 seq = NEXT_INSN (PREV_INSN (insn));
2788 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2794 /* Return nonzero if TRIAL can go into the function epilogue's
2795 delay slot. SLOT is the slot we are trying to fill. */
2798 eligible_for_epilogue_delay (trial, slot)
2807 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2810 if (get_attr_length (trial) != 1)
2813 /* If there are any call-saved registers, we should scan TRIAL if it
2814 does not reference them. For now just make it easy. */
2818 /* If the function uses __builtin_eh_return, the eh_return machinery
2819 occupies the delay slot. */
2820 if (current_function_calls_eh_return)
2823 /* In the case of a true leaf function, anything can go into the delay slot.
2824 A delay slot only exists however if the frame size is zero, otherwise
2825 we will put an insn to adjust the stack after the return. */
2826 if (current_function_uses_only_leaf_regs)
2828 if (leaf_return_peephole_ok ())
2829 return ((get_attr_in_uncond_branch_delay (trial)
2830 == IN_BRANCH_DELAY_TRUE));
2834 pat = PATTERN (trial);
2836 /* Otherwise, only operations which can be done in tandem with
2837 a `restore' or `return' insn can go into the delay slot. */
2838 if (GET_CODE (SET_DEST (pat)) != REG
2839 || REGNO (SET_DEST (pat)) < 24)
2842 /* If this instruction sets up floating point register and we have a return
2843 instruction, it can probably go in. But restore will not work
2845 if (REGNO (SET_DEST (pat)) >= 32)
2847 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2848 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2853 /* The set of insns matched here must agree precisely with the set of
2854 patterns paired with a RETURN in sparc.md. */
2856 src = SET_SRC (pat);
2858 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2859 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2860 && arith_operand (src, GET_MODE (src)))
2863 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2865 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2868 /* This matches "*return_di". */
2869 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2870 && arith_double_operand (src, GET_MODE (src)))
2871 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2873 /* This matches "*return_sf_no_fpu". */
2874 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2875 && register_operand (src, SFmode))
2878 /* If we have return instruction, anything that does not use
2879 local or output registers and can go into a delay slot wins. */
2880 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2881 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2884 /* This matches "*return_addsi". */
2885 else if (GET_CODE (src) == PLUS
2886 && arith_operand (XEXP (src, 0), SImode)
2887 && arith_operand (XEXP (src, 1), SImode)
2888 && (register_operand (XEXP (src, 0), SImode)
2889 || register_operand (XEXP (src, 1), SImode)))
2892 /* This matches "*return_adddi". */
2893 else if (GET_CODE (src) == PLUS
2894 && arith_double_operand (XEXP (src, 0), DImode)
2895 && arith_double_operand (XEXP (src, 1), DImode)
2896 && (register_operand (XEXP (src, 0), DImode)
2897 || register_operand (XEXP (src, 1), DImode)))
2900 /* This can match "*return_losum_[sd]i".
2901 Catch only some cases, so that return_losum* don't have
2903 else if (GET_CODE (src) == LO_SUM
2904 && ! TARGET_CM_MEDMID
2905 && ((register_operand (XEXP (src, 0), SImode)
2906 && immediate_operand (XEXP (src, 1), SImode))
2908 && register_operand (XEXP (src, 0), DImode)
2909 && immediate_operand (XEXP (src, 1), DImode))))
2912 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2913 else if (GET_CODE (src) == ASHIFT
2914 && (register_operand (XEXP (src, 0), SImode)
2915 || register_operand (XEXP (src, 0), DImode))
2916 && XEXP (src, 1) == const1_rtx)
2922 /* Return nonzero if TRIAL can go into the sibling call
2926 eligible_for_sibcall_delay (trial)
2931 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2934 if (get_attr_length (trial) != 1)
2937 pat = PATTERN (trial);
2939 if (current_function_uses_only_leaf_regs)
2941 /* If the tail call is done using the call instruction,
2942 we have to restore %o7 in the delay slot. */
2943 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2946 /* %g1 is used to build the function address */
2947 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2953 /* Otherwise, only operations which can be done in tandem with
2954 a `restore' insn can go into the delay slot. */
2955 if (GET_CODE (SET_DEST (pat)) != REG
2956 || REGNO (SET_DEST (pat)) < 24
2957 || REGNO (SET_DEST (pat)) >= 32)
2960 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2962 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2965 src = SET_SRC (pat);
2967 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2968 && arith_operand (src, GET_MODE (src)))
2971 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2973 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2976 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2977 && arith_double_operand (src, GET_MODE (src)))
2978 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2980 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2981 && register_operand (src, SFmode))
2984 else if (GET_CODE (src) == PLUS
2985 && arith_operand (XEXP (src, 0), SImode)
2986 && arith_operand (XEXP (src, 1), SImode)
2987 && (register_operand (XEXP (src, 0), SImode)
2988 || register_operand (XEXP (src, 1), SImode)))
2991 else if (GET_CODE (src) == PLUS
2992 && arith_double_operand (XEXP (src, 0), DImode)
2993 && arith_double_operand (XEXP (src, 1), DImode)
2994 && (register_operand (XEXP (src, 0), DImode)
2995 || register_operand (XEXP (src, 1), DImode)))
2998 else if (GET_CODE (src) == LO_SUM
2999 && ! TARGET_CM_MEDMID
3000 && ((register_operand (XEXP (src, 0), SImode)
3001 && immediate_operand (XEXP (src, 1), SImode))
3003 && register_operand (XEXP (src, 0), DImode)
3004 && immediate_operand (XEXP (src, 1), DImode))))
3007 else if (GET_CODE (src) == ASHIFT
3008 && (register_operand (XEXP (src, 0), SImode)
3009 || register_operand (XEXP (src, 0), DImode))
3010 && XEXP (src, 1) == const1_rtx)
3017 check_return_regs (x)
3020 switch (GET_CODE (x))
3023 return IN_OR_GLOBAL_P (x);
3038 if (check_return_regs (XEXP (x, 1)) == 0)
3043 return check_return_regs (XEXP (x, 0));
3051 /* Return 1 if TRIAL references only in and global registers. */
3053 eligible_for_return_delay (trial)
3056 if (GET_CODE (PATTERN (trial)) != SET)
3059 return check_return_regs (PATTERN (trial));
3063 short_branch (uid1, uid2)
3066 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3068 /* Leave a few words of "slop". */
3069 if (delta >= -1023 && delta <= 1022)
3075 /* Return non-zero if REG is not used after INSN.
3076 We assume REG is a reload reg, and therefore does
3077 not live past labels or calls or jumps. */
3079 reg_unused_after (reg, insn)
3083 enum rtx_code code, prev_code = UNKNOWN;
3085 while ((insn = NEXT_INSN (insn)))
3087 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3090 code = GET_CODE (insn);
3091 if (GET_CODE (insn) == CODE_LABEL)
3094 if (GET_RTX_CLASS (code) == 'i')
3096 rtx set = single_set (insn);
3097 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3100 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3102 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3110 /* The table we use to reference PIC data. */
3111 static rtx global_offset_table;
3113 /* The function we use to get at it. */
3114 static rtx get_pc_symbol;
3115 static char get_pc_symbol_name[256];
3117 /* Ensure that we are not using patterns that are not OK with PIC. */
3126 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3127 || (GET_CODE (recog_data.operand[i]) == CONST
3128 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3129 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3130 == global_offset_table)
3131 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3140 /* Return true if X is an address which needs a temporary register when
3141 reloaded while generating PIC code. */
3144 pic_address_needs_scratch (x)
3147 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3148 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3149 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3150 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3151 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3157 /* Legitimize PIC addresses. If the address is already position-independent,
3158 we return ORIG. Newly generated position-independent addresses go into a
3159 reg. This is REG if non zero, otherwise we allocate register(s) as
3163 legitimize_pic_address (orig, mode, reg)
3165 enum machine_mode mode ATTRIBUTE_UNUSED;
3168 if (GET_CODE (orig) == SYMBOL_REF)
3170 rtx pic_ref, address;
3175 if (reload_in_progress || reload_completed)
3178 reg = gen_reg_rtx (Pmode);
3183 /* If not during reload, allocate another temp reg here for loading
3184 in the address, so that these instructions can be optimized
3186 rtx temp_reg = ((reload_in_progress || reload_completed)
3187 ? reg : gen_reg_rtx (Pmode));
3189 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3190 won't get confused into thinking that these two instructions
3191 are loading in the true address of the symbol. If in the
3192 future a PIC rtx exists, that should be used instead. */
3193 if (Pmode == SImode)
3195 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3196 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3200 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3201 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3208 pic_ref = gen_rtx_MEM (Pmode,
3209 gen_rtx_PLUS (Pmode,
3210 pic_offset_table_rtx, address));
3211 current_function_uses_pic_offset_table = 1;
3212 RTX_UNCHANGING_P (pic_ref) = 1;
3213 insn = emit_move_insn (reg, pic_ref);
3214 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3216 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3220 else if (GET_CODE (orig) == CONST)
3224 if (GET_CODE (XEXP (orig, 0)) == PLUS
3225 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3230 if (reload_in_progress || reload_completed)
3233 reg = gen_reg_rtx (Pmode);
3236 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3238 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3239 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3240 base == reg ? 0 : reg);
3245 if (GET_CODE (offset) == CONST_INT)
3247 if (SMALL_INT (offset))
3248 return plus_constant (base, INTVAL (offset));
3249 else if (! reload_in_progress && ! reload_completed)
3250 offset = force_reg (Pmode, offset);
3252 /* If we reach here, then something is seriously wrong. */
3255 return gen_rtx_PLUS (Pmode, base, offset);
3257 else if (GET_CODE (orig) == LABEL_REF)
3258 /* ??? Why do we do this? */
3259 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3260 the register is live instead, in case it is eliminated. */
3261 current_function_uses_pic_offset_table = 1;
3266 /* Emit special PIC prologues. */
3269 load_pic_register ()
3271 /* Labels to get the PC in the prologue of this function. */
3272 int orig_flag_pic = flag_pic;
3277 /* If we haven't emitted the special get_pc helper function, do so now. */
3278 if (get_pc_symbol_name[0] == 0)
3282 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3285 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3287 ASM_OUTPUT_ALIGN (asm_out_file, align);
3288 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0);
3289 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3292 /* Initialize every time through, since we can't easily
3293 know this to be permanent. */
3294 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3295 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3298 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3301 flag_pic = orig_flag_pic;
3303 /* Need to emit this whether or not we obey regdecls,
3304 since setjmp/longjmp can cause life info to screw up.
3305 ??? In the case where we don't obey regdecls, this is not sufficient
3306 since we may not fall out the bottom. */
3307 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3310 /* Return 1 if RTX is a MEM which is known to be aligned to at
3311 least a DESIRED byte boundary. */
3314 mem_min_alignment (mem, desired)
3318 rtx addr, base, offset;
3320 /* If it's not a MEM we can't accept it. */
3321 if (GET_CODE (mem) != MEM)
3324 addr = XEXP (mem, 0);
3325 base = offset = NULL_RTX;
3326 if (GET_CODE (addr) == PLUS)
3328 if (GET_CODE (XEXP (addr, 0)) == REG)
3330 base = XEXP (addr, 0);
3332 /* What we are saying here is that if the base
3333 REG is aligned properly, the compiler will make
3334 sure any REG based index upon it will be so
3336 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3337 offset = XEXP (addr, 1);
3339 offset = const0_rtx;
3342 else if (GET_CODE (addr) == REG)
3345 offset = const0_rtx;
3348 if (base != NULL_RTX)
3350 int regno = REGNO (base);
3352 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3354 /* Check if the compiler has recorded some information
3355 about the alignment of the base REG. If reload has
3356 completed, we already matched with proper alignments.
3357 If not running global_alloc, reload might give us
3358 unaligned pointer to local stack though. */
3360 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3361 || (optimize && reload_completed))
3362 && (INTVAL (offset) & (desired - 1)) == 0)
3367 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3371 else if (! TARGET_UNALIGNED_DOUBLES
3372 || CONSTANT_P (addr)
3373 || GET_CODE (addr) == LO_SUM)
3375 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3376 is true, in which case we can only assume that an access is aligned if
3377 it is to a constant address, or the address involves a LO_SUM. */
3381 /* An obviously unaligned address. */
3386 /* Vectors to keep interesting information about registers where it can easily
3387 be got. We use to use the actual mode value as the bit number, but there
3388 are more than 32 modes now. Instead we use two tables: one indexed by
3389 hard register number, and one indexed by mode. */
3391 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3392 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3393 mapped into one sparc_mode_class mode. */
3395 enum sparc_mode_class {
3396 S_MODE, D_MODE, T_MODE, O_MODE,
3397 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3401 /* Modes for single-word and smaller quantities. */
3402 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3404 /* Modes for double-word and smaller quantities. */
3405 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3407 /* Modes for quad-word and smaller quantities. */
3408 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3410 /* Modes for 8-word and smaller quantities. */
3411 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3413 /* Modes for single-float quantities. We must allow any single word or
3414 smaller quantity. This is because the fix/float conversion instructions
3415 take integer inputs/outputs from the float registers. */
3416 #define SF_MODES (S_MODES)
3418 /* Modes for double-float and smaller quantities. */
3419 #define DF_MODES (S_MODES | D_MODES)
3421 /* Modes for double-float only quantities. */
3422 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3424 /* Modes for quad-float only quantities. */
3425 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3427 /* Modes for quad-float and smaller quantities. */
3428 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3430 /* Modes for quad-float and double-float quantities. */
3431 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3433 /* Modes for quad-float pair only quantities. */
3434 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3436 /* Modes for quad-float pairs and smaller quantities. */
3437 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3439 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3441 /* Modes for condition codes. */
3442 #define CC_MODES (1 << (int) CC_MODE)
3443 #define CCFP_MODES (1 << (int) CCFP_MODE)
3445 /* Value is 1 if register/mode pair is acceptable on sparc.
3446 The funny mixture of D and T modes is because integer operations
3447 do not specially operate on tetra quantities, so non-quad-aligned
3448 registers can hold quadword quantities (except %o4 and %i4 because
3449 they cross fixed registers). */
3451 /* This points to either the 32 bit or the 64 bit version. */
3452 const int *hard_regno_mode_classes;
3454 static const int hard_32bit_mode_classes[] = {
3455 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3456 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3457 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3458 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3460 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3461 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3462 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3463 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3465 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3466 and none can hold SFmode/SImode values. */
3467 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3468 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3469 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3470 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3473 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3479 static const int hard_64bit_mode_classes[] = {
3480 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3481 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3482 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3483 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3485 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3486 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3487 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3488 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3490 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3491 and none can hold SFmode/SImode values. */
3492 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3493 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3494 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3495 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3498 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3504 int sparc_mode_class [NUM_MACHINE_MODES];
3506 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3513 for (i = 0; i < NUM_MACHINE_MODES; i++)
3515 switch (GET_MODE_CLASS (i))
3518 case MODE_PARTIAL_INT:
3519 case MODE_COMPLEX_INT:
3520 if (GET_MODE_SIZE (i) <= 4)
3521 sparc_mode_class[i] = 1 << (int) S_MODE;
3522 else if (GET_MODE_SIZE (i) == 8)
3523 sparc_mode_class[i] = 1 << (int) D_MODE;
3524 else if (GET_MODE_SIZE (i) == 16)
3525 sparc_mode_class[i] = 1 << (int) T_MODE;
3526 else if (GET_MODE_SIZE (i) == 32)
3527 sparc_mode_class[i] = 1 << (int) O_MODE;
3529 sparc_mode_class[i] = 0;
3532 case MODE_COMPLEX_FLOAT:
3533 if (GET_MODE_SIZE (i) <= 4)
3534 sparc_mode_class[i] = 1 << (int) SF_MODE;
3535 else if (GET_MODE_SIZE (i) == 8)
3536 sparc_mode_class[i] = 1 << (int) DF_MODE;
3537 else if (GET_MODE_SIZE (i) == 16)
3538 sparc_mode_class[i] = 1 << (int) TF_MODE;
3539 else if (GET_MODE_SIZE (i) == 32)
3540 sparc_mode_class[i] = 1 << (int) OF_MODE;
3542 sparc_mode_class[i] = 0;
3546 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3547 we must explicitly check for them here. */
3548 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3549 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3550 else if (i == (int) CCmode || i == (int) CC_NOOVmode
3551 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3552 sparc_mode_class[i] = 1 << (int) CC_MODE;
3554 sparc_mode_class[i] = 0;
3560 hard_regno_mode_classes = hard_64bit_mode_classes;
3562 hard_regno_mode_classes = hard_32bit_mode_classes;
3564 /* Initialize the array used by REGNO_REG_CLASS. */
3565 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3567 if (i < 16 && TARGET_V8PLUS)
3568 sparc_regno_reg_class[i] = I64_REGS;
3569 else if (i < 32 || i == FRAME_POINTER_REGNUM)
3570 sparc_regno_reg_class[i] = GENERAL_REGS;
3572 sparc_regno_reg_class[i] = FP_REGS;
3574 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3576 sparc_regno_reg_class[i] = FPCC_REGS;
3578 sparc_regno_reg_class[i] = NO_REGS;
3582 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3583 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3584 v9 int regs as it simplifies the code. */
3587 save_regs (file, low, high, base, offset, n_regs, real_offset)
3597 if (TARGET_ARCH64 && high <= 32)
3599 for (i = low; i < high; i++)
3601 if (regs_ever_live[i] && ! call_used_regs[i])
3603 fprintf (file, "\tstx\t%s, [%s+%d]\n",
3604 reg_names[i], base, offset + 4 * n_regs);
3605 if (dwarf2out_do_frame ())
3606 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3613 for (i = low; i < high; i += 2)
3615 if (regs_ever_live[i] && ! call_used_regs[i])
3617 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3619 fprintf (file, "\tstd\t%s, [%s+%d]\n",
3620 reg_names[i], base, offset + 4 * n_regs);
3621 if (dwarf2out_do_frame ())
3623 char *l = dwarf2out_cfi_label ();
3624 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
3625 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
3631 fprintf (file, "\tst\t%s, [%s+%d]\n",
3632 reg_names[i], base, offset + 4 * n_regs);
3633 if (dwarf2out_do_frame ())
3634 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3640 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3642 fprintf (file, "\tst\t%s, [%s+%d]\n",
3643 reg_names[i+1], base, offset + 4 * n_regs + 4);
3644 if (dwarf2out_do_frame ())
3645 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
3654 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3656 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3657 v9 int regs as it simplifies the code. */
3660 restore_regs (file, low, high, base, offset, n_regs)
3669 if (TARGET_ARCH64 && high <= 32)
3671 for (i = low; i < high; i++)
3673 if (regs_ever_live[i] && ! call_used_regs[i])
3674 fprintf (file, "\tldx\t[%s+%d], %s\n",
3675 base, offset + 4 * n_regs, reg_names[i]),
3681 for (i = low; i < high; i += 2)
3683 if (regs_ever_live[i] && ! call_used_regs[i])
3684 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3685 fprintf (file, "\tldd\t[%s+%d], %s\n",
3686 base, offset + 4 * n_regs, reg_names[i]),
3689 fprintf (file, "\tld\t[%s+%d], %s\n",
3690 base, offset + 4 * n_regs, reg_names[i]),
3692 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3693 fprintf (file, "\tld\t[%s+%d], %s\n",
3694 base, offset + 4 * n_regs + 4, reg_names[i+1]),
3701 /* Compute the frame size required by the function. This function is called
3702 during the reload pass and also by output_function_prologue(). */
3705 compute_frame_size (size, leaf_function)
3710 int outgoing_args_size = (current_function_outgoing_args_size
3711 + REG_PARM_STACK_SPACE (current_function_decl));
3713 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3714 even to v9 int regs to be consistent with save_regs/restore_regs. */
3718 for (i = 0; i < 8; i++)
3719 if (regs_ever_live[i] && ! call_used_regs[i])
3724 for (i = 0; i < 8; i += 2)
3725 if ((regs_ever_live[i] && ! call_used_regs[i])
3726 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3730 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3731 if ((regs_ever_live[i] && ! call_used_regs[i])
3732 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3735 /* Set up values for use in `function_epilogue'. */
3736 num_gfregs = n_regs;
3738 if (leaf_function && n_regs == 0
3739 && size == 0 && current_function_outgoing_args_size == 0)
3741 actual_fsize = apparent_fsize = 0;
3745 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3746 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
3747 apparent_fsize += n_regs * 4;
3748 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3751 /* Make sure nothing can clobber our register windows.
3752 If a SAVE must be done, or there is a stack-local variable,
3753 the register window area must be allocated.
3754 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3755 if (leaf_function == 0 || size > 0)
3756 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3758 return SPARC_STACK_ALIGN (actual_fsize);
3761 /* Build a (32 bit) big number in a register. */
3762 /* ??? We may be able to use the set macro here too. */
3765 build_big_number (file, num, reg)
3770 if (num >= 0 || ! TARGET_ARCH64)
3772 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
3773 if ((num & 0x3ff) != 0)
3774 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
3776 else /* num < 0 && TARGET_ARCH64 */
3778 /* Sethi does not sign extend, so we must use a little trickery
3779 to use it for negative numbers. Invert the constant before
3780 loading it in, then use xor immediate to invert the loaded bits
3781 (along with the upper 32 bits) to the desired constant. This
3782 works because the sethi and immediate fields overlap. */
3785 int low = -0x400 + (asize & 0x3FF);
3787 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3788 inv, reg, reg, low, reg);
3792 /* Output any necessary .register pseudo-ops. */
3794 sparc_output_scratch_registers (file)
3795 FILE *file ATTRIBUTE_UNUSED;
3797 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3803 /* Check if %g[2367] were used without
3804 .register being printed for them already. */
3805 for (i = 2; i < 8; i++)
3807 if (regs_ever_live [i]
3808 && ! sparc_hard_reg_printed [i])
3810 sparc_hard_reg_printed [i] = 1;
3811 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
3818 /* This function generates the assembly code for function entry.
3819 FILE is a stdio stream to output the code to.
3820 SIZE is an int: how many units of temporary storage to allocate.
3821 Refer to the array `regs_ever_live' to determine which registers
3822 to save; `regs_ever_live[I]' is nonzero if register number I
3823 is ever used in the function. This macro is responsible for
3824 knowing which registers should not be saved even if used. */
3826 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
3827 of memory. If any fpu reg is used in the function, we allocate
3828 such a block here, at the bottom of the frame, just in case it's needed.
3830 If this function is a leaf procedure, then we may choose not
3831 to do a "save" insn. The decision about whether or not
3832 to do this is made in regclass.c. */
3835 sparc_output_function_prologue (file, size)
3840 sparc_flat_function_prologue (file, size);
3842 sparc_nonflat_function_prologue (file, size,
3843 current_function_uses_only_leaf_regs);
3846 /* Output code for the function prologue. */
3849 sparc_nonflat_function_prologue (file, size, leaf_function)
3854 sparc_output_scratch_registers (file);
3856 /* Need to use actual_fsize, since we are also allocating
3857 space for our callee (and our own register save area). */
3858 actual_fsize = compute_frame_size (size, leaf_function);
3862 frame_base_name = "%sp";
3863 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3867 frame_base_name = "%fp";
3868 frame_base_offset = SPARC_STACK_BIAS;
3871 /* This is only for the human reader. */
3872 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3874 if (actual_fsize == 0)
3876 else if (! leaf_function)
3878 if (actual_fsize <= 4096)
3879 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3880 else if (actual_fsize <= 8192)
3882 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3883 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3887 build_big_number (file, -actual_fsize, "%g1");
3888 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
3891 else /* leaf function */
3893 if (actual_fsize <= 4096)
3894 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3895 else if (actual_fsize <= 8192)
3897 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3898 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3902 build_big_number (file, -actual_fsize, "%g1");
3903 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3907 if (dwarf2out_do_frame () && actual_fsize)
3909 char *label = dwarf2out_cfi_label ();
3911 /* The canonical frame address refers to the top of the frame. */
3912 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3913 : HARD_FRAME_POINTER_REGNUM),
3916 if (! leaf_function)
3918 /* Note the register window save. This tells the unwinder that
3919 it needs to restore the window registers from the previous
3920 frame's window save area at 0(cfa). */
3921 dwarf2out_window_save (label);
3923 /* The return address (-8) is now in %i7. */
3924 dwarf2out_return_reg (label, 31);
3928 /* If doing anything with PIC, do it now. */
3930 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3932 /* Call saved registers are saved just above the outgoing argument area. */
3935 int offset, real_offset, n_regs;
3938 real_offset = -apparent_fsize;
3939 offset = -apparent_fsize + frame_base_offset;
3940 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3942 /* ??? This might be optimized a little as %g1 might already have a
3943 value close enough that a single add insn will do. */
3944 /* ??? Although, all of this is probably only a temporary fix
3945 because if %g1 can hold a function result, then
3946 output_function_epilogue will lose (the result will get
3948 build_big_number (file, offset, "%g1");
3949 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3955 base = frame_base_name;
3958 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3959 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3964 /* Output code to restore any call saved registers. */
3967 output_restore_regs (file, leaf_function)
3969 int leaf_function ATTRIBUTE_UNUSED;
3974 offset = -apparent_fsize + frame_base_offset;
3975 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3977 build_big_number (file, offset, "%g1");
3978 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3984 base = frame_base_name;
3987 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3988 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
3991 /* This function generates the assembly code for function exit,
3992 on machines that need it.
3994 The function epilogue should not depend on the current stack pointer!
3995 It should use the frame pointer only. This is mandatory because
3996 of alloca; we also take advantage of it to omit stack adjustments
3997 before returning. */
4000 sparc_output_function_epilogue (file, size)
4005 sparc_flat_function_epilogue (file, size);
4007 sparc_nonflat_function_epilogue (file, size,
4008 current_function_uses_only_leaf_regs);
4011 /* Output code for the function epilogue. */
4014 sparc_nonflat_function_epilogue (file, size, leaf_function)
4016 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
4021 if (current_function_epilogue_delay_list == 0)
4023 /* If code does not drop into the epilogue, we need
4024 do nothing except output pending case vectors.
4026 We have to still output a dummy nop for the sake of
4027 sane backtraces. Otherwise, if the last two instructions
4028 of a function were call foo; dslot; this can make the return
4029 PC of foo (ie. address of call instruction plus 8) point to
4030 the first instruction in the next function. */
4033 fputs("\tnop\n", file);
4035 insn = get_last_insn ();
4036 if (GET_CODE (insn) == NOTE)
4037 insn = prev_nonnote_insn (insn);
4038 if (insn && GET_CODE (insn) == BARRIER)
4039 goto output_vectors;
4043 output_restore_regs (file, leaf_function);
4045 /* Work out how to skip the caller's unimp instruction if required. */
4047 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4049 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4051 if (! leaf_function)
4053 if (current_function_calls_eh_return)
4055 if (current_function_epilogue_delay_list)
4057 if (SKIP_CALLERS_UNIMP_P)
4060 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4062 /* If we wound up with things in our delay slot, flush them here. */
4063 else if (current_function_epilogue_delay_list)
4065 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4067 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4069 epilogue_renumber (&delay, 0);
4070 fputs (SKIP_CALLERS_UNIMP_P
4071 ? "\treturn\t%i7+12\n"
4072 : "\treturn\t%i7+8\n", file);
4073 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4080 if (GET_CODE (delay) != SET)
4083 src = SET_SRC (delay);
4084 if (GET_CODE (src) == ASHIFT)
4086 if (XEXP (src, 1) != const1_rtx)
4089 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4093 insn = gen_rtx_PARALLEL (VOIDmode,
4094 gen_rtvec (2, delay,
4095 gen_rtx_RETURN (VOIDmode)));
4096 insn = emit_jump_insn (insn);
4098 sparc_emitting_epilogue = true;
4099 final_scan_insn (insn, file, 1, 0, 1);
4100 sparc_emitting_epilogue = false;
4103 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4104 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4106 fprintf (file, "\t%s\n\trestore\n", ret);
4108 /* All of the following cases are for leaf functions. */
4109 else if (current_function_calls_eh_return)
4111 else if (current_function_epilogue_delay_list)
4113 /* eligible_for_epilogue_delay_slot ensures that if this is a
4114 leaf function, then we will only have insn in the delay slot
4115 if the frame size is zero, thus no adjust for the stack is
4117 if (actual_fsize != 0)
4119 fprintf (file, "\t%s\n", ret);
4120 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4123 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4124 avoid generating confusing assembly language output. */
4125 else if (actual_fsize == 0)
4126 fprintf (file, "\t%s\n\tnop\n", ret);
4127 else if (actual_fsize <= 4096)
4128 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
4129 else if (actual_fsize <= 8192)
4130 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4131 ret, actual_fsize - 4096);
4132 else if ((actual_fsize & 0x3ff) == 0)
4133 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4136 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4137 actual_fsize, actual_fsize, ret);
4140 sparc_output_deferred_case_vectors ();
4143 /* Output a sibling call. */
4146 output_sibcall (insn, call_operand)
4147 rtx insn, call_operand;
4149 int leaf_regs = current_function_uses_only_leaf_regs;
4151 int delay_slot = dbr_sequence_length () > 0;
4155 /* Call to restore global regs might clobber
4156 the delay slot. Instead of checking for this
4157 output the delay slot now. */
4160 rtx delay = NEXT_INSN (insn);
4165 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4166 PATTERN (delay) = gen_blockage ();
4167 INSN_CODE (delay) = -1;
4170 output_restore_regs (asm_out_file, leaf_regs);
4173 operands[0] = call_operand;
4177 #ifdef HAVE_AS_RELAX_OPTION
4178 /* If as and ld are relaxing tail call insns into branch always,
4179 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4180 be optimized. With sethi/jmpl as nor ld has no easy way how to
4181 find out if somebody does not branch between the sethi and jmpl. */
4184 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4188 if ((actual_fsize || ! spare_slot) && delay_slot)
4190 rtx delay = NEXT_INSN (insn);
4195 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4196 PATTERN (delay) = gen_blockage ();
4197 INSN_CODE (delay) = -1;
4202 if (actual_fsize <= 4096)
4203 size = actual_fsize;
4204 else if (actual_fsize <= 8192)
4206 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4207 size = actual_fsize - 4096;
4209 else if ((actual_fsize & 0x3ff) == 0)
4210 fprintf (asm_out_file,
4211 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4215 fprintf (asm_out_file,
4216 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4217 actual_fsize, actual_fsize);
4218 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4223 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4224 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4226 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size);
4227 else if (! delay_slot)
4228 fputs ("\t nop\n", asm_out_file);
4233 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size);
4234 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4235 it into branch if possible. */
4236 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4237 output_asm_insn ("call\t%a0, 0", operands);
4238 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4243 output_asm_insn ("call\t%a0, 0", operands);
4246 rtx delay = NEXT_INSN (insn), pat;
4251 pat = PATTERN (delay);
4252 if (GET_CODE (pat) != SET)
4255 operands[0] = SET_DEST (pat);
4256 pat = SET_SRC (pat);
4257 switch (GET_CODE (pat))
4260 operands[1] = XEXP (pat, 0);
4261 operands[2] = XEXP (pat, 1);
4262 output_asm_insn (" restore %r1, %2, %Y0", operands);
4265 operands[1] = XEXP (pat, 0);
4266 operands[2] = XEXP (pat, 1);
4267 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4270 operands[1] = XEXP (pat, 0);
4271 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4275 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4278 PATTERN (delay) = gen_blockage ();
4279 INSN_CODE (delay) = -1;
4282 fputs ("\t restore\n", asm_out_file);
4286 /* Functions for handling argument passing.
4288 For v8 the first six args are normally in registers and the rest are
4289 pushed. Any arg that starts within the first 6 words is at least
4290 partially passed in a register unless its data type forbids.
4292 For v9, the argument registers are laid out as an array of 16 elements
4293 and arguments are added sequentially. The first 6 int args and up to the
4294 first 16 fp args (depending on size) are passed in regs.
4296 Slot Stack Integral Float Float in structure Double Long Double
4297 ---- ----- -------- ----- ------------------ ------ -----------
4298 15 [SP+248] %f31 %f30,%f31 %d30
4299 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4300 13 [SP+232] %f27 %f26,%f27 %d26
4301 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4302 11 [SP+216] %f23 %f22,%f23 %d22
4303 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4304 9 [SP+200] %f19 %f18,%f19 %d18
4305 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4306 7 [SP+184] %f15 %f14,%f15 %d14
4307 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4308 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4309 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4310 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4311 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4312 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4313 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4315 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4317 Integral arguments are always passed as 64 bit quantities appropriately
4320 Passing of floating point values is handled as follows.
4321 If a prototype is in scope:
4322 If the value is in a named argument (i.e. not a stdarg function or a
4323 value not part of the `...') then the value is passed in the appropriate
4325 If the value is part of the `...' and is passed in one of the first 6
4326 slots then the value is passed in the appropriate int reg.
4327 If the value is part of the `...' and is not passed in one of the first 6
4328 slots then the value is passed in memory.
4329 If a prototype is not in scope:
4330 If the value is one of the first 6 arguments the value is passed in the
4331 appropriate integer reg and the appropriate fp reg.
4332 If the value is not one of the first 6 arguments the value is passed in
4333 the appropriate fp reg and in memory.
4336 /* Maximum number of int regs for args. */
4337 #define SPARC_INT_ARG_MAX 6
4338 /* Maximum number of fp regs for args. */
4339 #define SPARC_FP_ARG_MAX 16
4341 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4343 /* Handle the INIT_CUMULATIVE_ARGS macro.
4344 Initialize a variable CUM of type CUMULATIVE_ARGS
4345 for a call to a function whose data type is FNTYPE.
4346 For a library call, FNTYPE is 0. */
4349 init_cumulative_args (cum, fntype, libname, indirect)
4350 CUMULATIVE_ARGS *cum;
4352 rtx libname ATTRIBUTE_UNUSED;
4353 int indirect ATTRIBUTE_UNUSED;
4356 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4357 cum->libcall_p = fntype == 0;
4360 /* Compute the slot number to pass an argument in.
4361 Returns the slot number or -1 if passing on the stack.
4363 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4364 the preceding args and about the function being called.
4365 MODE is the argument's machine mode.
4366 TYPE is the data type of the argument (as a tree).
4367 This is null for libcalls where that information may
4369 NAMED is nonzero if this argument is a named parameter
4370 (otherwise it is an extra parameter matching an ellipsis).
4371 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4372 *PREGNO records the register number to use if scalar type.
4373 *PPADDING records the amount of padding needed in words. */
4376 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
4377 const CUMULATIVE_ARGS *cum;
4378 enum machine_mode mode;
4385 int regbase = (incoming_p
4386 ? SPARC_INCOMING_INT_ARG_FIRST
4387 : SPARC_OUTGOING_INT_ARG_FIRST);
4388 int slotno = cum->words;
4393 if (type != 0 && TREE_ADDRESSABLE (type))
4396 && type != 0 && mode == BLKmode
4397 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4403 /* MODE is VOIDmode when generating the actual call.
4407 case QImode : case CQImode :
4408 case HImode : case CHImode :
4409 case SImode : case CSImode :
4410 case DImode : case CDImode :
4411 case TImode : case CTImode :
4412 if (slotno >= SPARC_INT_ARG_MAX)
4414 regno = regbase + slotno;
4417 case SFmode : case SCmode :
4418 case DFmode : case DCmode :
4419 case TFmode : case TCmode :
4422 if (slotno >= SPARC_INT_ARG_MAX)
4424 regno = regbase + slotno;
4428 if ((mode == TFmode || mode == TCmode)
4429 && (slotno & 1) != 0)
4430 slotno++, *ppadding = 1;
4431 if (TARGET_FPU && named)
4433 if (slotno >= SPARC_FP_ARG_MAX)
4435 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4441 if (slotno >= SPARC_INT_ARG_MAX)
4443 regno = regbase + slotno;
4449 /* For sparc64, objects requiring 16 byte alignment get it. */
4452 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
4453 slotno++, *ppadding = 1;
4457 || (type && TREE_CODE (type) == UNION_TYPE))
4459 if (slotno >= SPARC_INT_ARG_MAX)
4461 regno = regbase + slotno;
4466 int intregs_p = 0, fpregs_p = 0;
4467 /* The ABI obviously doesn't specify how packed
4468 structures are passed. These are defined to be passed
4469 in int regs if possible, otherwise memory. */
4472 /* First see what kinds of registers we need. */
4473 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4475 if (TREE_CODE (field) == FIELD_DECL)
4477 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4482 if (DECL_PACKED (field))
4486 if (packed_p || !named)
4487 fpregs_p = 0, intregs_p = 1;
4489 /* If all arg slots are filled, then must pass on stack. */
4490 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4492 /* If there are only int args and all int arg slots are filled,
4493 then must pass on stack. */
4494 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4496 /* Note that even if all int arg slots are filled, fp members may
4497 still be passed in regs if such regs are available.
4498 *PREGNO isn't set because there may be more than one, it's up
4499 to the caller to compute them. */
4512 /* Handle recursive register counting for structure field layout. */
4514 struct function_arg_record_value_parms
4517 int slotno, named, regbase;
4522 static void function_arg_record_value_3
4523 PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *));
4524 static void function_arg_record_value_2
4525 PARAMS ((tree, HOST_WIDE_INT,
4526 struct function_arg_record_value_parms *));
4527 static void function_arg_record_value_1
4528 PARAMS ((tree, HOST_WIDE_INT,
4529 struct function_arg_record_value_parms *));
4530 static rtx function_arg_record_value
4531 PARAMS ((tree, enum machine_mode, int, int, int));
4533 /* A subroutine of function_arg_record_value. Traverse the structure
4534 recusively and determine how many registers will be required. */
4537 function_arg_record_value_1 (type, startbitpos, parms)
4539 HOST_WIDE_INT startbitpos;
4540 struct function_arg_record_value_parms *parms;
4544 /* The ABI obviously doesn't specify how packed structures are
4545 passed. These are defined to be passed in int regs if possible,
4546 otherwise memory. */
4549 /* We need to compute how many registers are needed so we can
4550 allocate the PARALLEL but before we can do that we need to know
4551 whether there are any packed fields. If there are, int regs are
4552 used regardless of whether there are fp values present. */
4553 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4555 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4562 /* Compute how many registers we need. */
4563 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4565 if (TREE_CODE (field) == FIELD_DECL)
4567 HOST_WIDE_INT bitpos = startbitpos;
4569 if (DECL_SIZE (field) != 0
4570 && host_integerp (bit_position (field), 1))
4571 bitpos += int_bit_position (field);
4573 /* ??? FIXME: else assume zero offset. */
4575 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4576 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
4577 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4578 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4579 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4585 if (parms->intoffset != -1)
4587 int intslots, this_slotno;
4589 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
4591 this_slotno = parms->slotno + parms->intoffset
4594 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4595 intslots = MAX (intslots, 0);
4596 parms->nregs += intslots;
4597 parms->intoffset = -1;
4600 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4601 If it wasn't true we wouldn't be here. */
4603 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4608 if (parms->intoffset == -1)
4609 parms->intoffset = bitpos;
4615 /* A subroutine of function_arg_record_value. Assign the bits of the
4616 structure between parms->intoffset and bitpos to integer registers. */
4619 function_arg_record_value_3 (bitpos, parms)
4620 HOST_WIDE_INT bitpos;
4621 struct function_arg_record_value_parms *parms;
4623 enum machine_mode mode;
4625 unsigned int startbit, endbit;
4626 int this_slotno, intslots, intoffset;
4629 if (parms->intoffset == -1)
4632 intoffset = parms->intoffset;
4633 parms->intoffset = -1;
4635 startbit = intoffset & -BITS_PER_WORD;
4636 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4637 intslots = (endbit - startbit) / BITS_PER_WORD;
4638 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
4640 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4644 /* If this is the trailing part of a word, only load that much into
4645 the register. Otherwise load the whole register. Note that in
4646 the latter case we may pick up unwanted bits. It's not a problem
4647 at the moment but may wish to revisit. */
4649 if (intoffset % BITS_PER_WORD != 0)
4650 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4655 intoffset /= BITS_PER_UNIT;
4658 regno = parms->regbase + this_slotno;
4659 reg = gen_rtx_REG (mode, regno);
4660 XVECEXP (parms->ret, 0, parms->nregs)
4661 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4664 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4668 while (intslots > 0);
4671 /* A subroutine of function_arg_record_value. Traverse the structure
4672 recursively and assign bits to floating point registers. Track which
4673 bits in between need integer registers; invoke function_arg_record_value_3
4674 to make that happen. */
4677 function_arg_record_value_2 (type, startbitpos, parms)
4679 HOST_WIDE_INT startbitpos;
4680 struct function_arg_record_value_parms *parms;
4685 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4687 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4694 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4696 if (TREE_CODE (field) == FIELD_DECL)
4698 HOST_WIDE_INT bitpos = startbitpos;
4700 if (DECL_SIZE (field) != 0
4701 && host_integerp (bit_position (field), 1))
4702 bitpos += int_bit_position (field);
4704 /* ??? FIXME: else assume zero offset. */
4706 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4707 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
4708 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4709 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4710 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4716 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
4718 enum machine_mode mode = DECL_MODE (field);
4721 function_arg_record_value_3 (bitpos, parms);
4722 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
4723 + ((mode == SFmode || mode == SCmode)
4724 && (bitpos & 32) != 0);
4727 case SCmode: mode = SFmode; break;
4728 case DCmode: mode = DFmode; break;
4729 case TCmode: mode = TFmode; break;
4732 reg = gen_rtx_REG (mode, regno);
4733 XVECEXP (parms->ret, 0, parms->nregs)
4734 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4735 GEN_INT (bitpos / BITS_PER_UNIT));
4737 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4739 regno += GET_MODE_SIZE (mode) / 4;
4740 reg = gen_rtx_REG (mode, regno);
4741 XVECEXP (parms->ret, 0, parms->nregs)
4742 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4743 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
4750 if (parms->intoffset == -1)
4751 parms->intoffset = bitpos;
4757 /* Used by function_arg and function_value to implement the complex
4758 Sparc64 structure calling conventions. */
4761 function_arg_record_value (type, mode, slotno, named, regbase)
4763 enum machine_mode mode;
4764 int slotno, named, regbase;
4766 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4767 struct function_arg_record_value_parms parms;
4770 parms.ret = NULL_RTX;
4771 parms.slotno = slotno;
4772 parms.named = named;
4773 parms.regbase = regbase;
4775 /* Compute how many registers we need. */
4777 parms.intoffset = 0;
4778 function_arg_record_value_1 (type, 0, &parms);
4780 if (parms.intoffset != -1)
4782 unsigned int startbit, endbit;
4783 int intslots, this_slotno;
4785 startbit = parms.intoffset & -BITS_PER_WORD;
4786 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4787 intslots = (endbit - startbit) / BITS_PER_WORD;
4788 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
4790 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4791 intslots = MAX (intslots, 0);
4793 parms.nregs += intslots;
4795 nregs = parms.nregs;
4797 /* Allocate the vector and handle some annoying special cases. */
4800 /* ??? Empty structure has no value? Duh? */
4803 /* Though there's nothing really to store, return a word register
4804 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4805 leads to breakage due to the fact that there are zero bytes to
4807 return gen_rtx_REG (mode, regbase);
4811 /* ??? C++ has structures with no fields, and yet a size. Give up
4812 for now and pass everything back in integer registers. */
4813 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4815 if (nregs + slotno > SPARC_INT_ARG_MAX)
4816 nregs = SPARC_INT_ARG_MAX - slotno;
4821 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
4823 /* Fill in the entries. */
4825 parms.intoffset = 0;
4826 function_arg_record_value_2 (type, 0, &parms);
4827 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
4829 if (parms.nregs != nregs)
4835 /* Handle the FUNCTION_ARG macro.
4836 Determine where to put an argument to a function.
4837 Value is zero to push the argument on the stack,
4838 or a hard register in which to store the argument.
4840 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4841 the preceding args and about the function being called.
4842 MODE is the argument's machine mode.
4843 TYPE is the data type of the argument (as a tree).
4844 This is null for libcalls where that information may
4846 NAMED is nonzero if this argument is a named parameter
4847 (otherwise it is an extra parameter matching an ellipsis).
4848 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4851 function_arg (cum, mode, type, named, incoming_p)
4852 const CUMULATIVE_ARGS *cum;
4853 enum machine_mode mode;
4858 int regbase = (incoming_p
4859 ? SPARC_INCOMING_INT_ARG_FIRST
4860 : SPARC_OUTGOING_INT_ARG_FIRST);
4861 int slotno, regno, padding;
4864 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
4872 reg = gen_rtx_REG (mode, regno);
4876 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4877 but also have the slot allocated for them.
4878 If no prototype is in scope fp values in register slots get passed
4879 in two places, either fp regs and int regs or fp regs and memory. */
4880 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4881 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4882 && SPARC_FP_REG_P (regno))
4884 reg = gen_rtx_REG (mode, regno);
4885 if (cum->prototype_p || cum->libcall_p)
4887 /* "* 2" because fp reg numbers are recorded in 4 byte
4890 /* ??? This will cause the value to be passed in the fp reg and
4891 in the stack. When a prototype exists we want to pass the
4892 value in the reg but reserve space on the stack. That's an
4893 optimization, and is deferred [for a bit]. */
4894 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
4895 return gen_rtx_PARALLEL (mode,
4897 gen_rtx_EXPR_LIST (VOIDmode,
4898 NULL_RTX, const0_rtx),
4899 gen_rtx_EXPR_LIST (VOIDmode,
4903 /* ??? It seems that passing back a register even when past
4904 the area declared by REG_PARM_STACK_SPACE will allocate
4905 space appropriately, and will not copy the data onto the
4906 stack, exactly as we desire.
4908 This is due to locate_and_pad_parm being called in
4909 expand_call whenever reg_parm_stack_space > 0, which
4910 while benefical to our example here, would seem to be
4911 in error from what had been intended. Ho hum... -- r~ */
4919 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
4923 /* On incoming, we don't need to know that the value
4924 is passed in %f0 and %i0, and it confuses other parts
4925 causing needless spillage even on the simplest cases. */
4929 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
4930 + (regno - SPARC_FP_ARG_FIRST) / 2);
4932 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4933 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
4935 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4939 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4940 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4941 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4945 else if (type && TREE_CODE (type) == RECORD_TYPE)
4947 /* Structures up to 16 bytes in size are passed in arg slots on the
4948 stack and are promoted to registers where possible. */
4950 if (int_size_in_bytes (type) > 16)
4951 abort (); /* shouldn't get here */
4953 return function_arg_record_value (type, mode, slotno, named, regbase);
4955 else if (type && TREE_CODE (type) == UNION_TYPE)
4957 enum machine_mode mode;
4958 int bytes = int_size_in_bytes (type);
4963 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4964 reg = gen_rtx_REG (mode, regno);
4968 /* Scalar or complex int. */
4969 reg = gen_rtx_REG (mode, regno);
4975 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4976 For an arg passed partly in registers and partly in memory,
4977 this is the number of registers used.
4978 For args passed entirely in registers or entirely in memory, zero.
4980 Any arg that starts in the first 6 regs but won't entirely fit in them
4981 needs partial registers on v8. On v9, structures with integer
4982 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4983 values that begin in the last fp reg [where "last fp reg" varies with the
4984 mode] will be split between that reg and memory. */
4987 function_arg_partial_nregs (cum, mode, type, named)
4988 const CUMULATIVE_ARGS *cum;
4989 enum machine_mode mode;
4993 int slotno, regno, padding;
4995 /* We pass 0 for incoming_p here, it doesn't matter. */
4996 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5003 if ((slotno + (mode == BLKmode
5004 ? ROUND_ADVANCE (int_size_in_bytes (type))
5005 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5006 > NPARM_REGS (SImode))
5007 return NPARM_REGS (SImode) - slotno;
5012 if (type && AGGREGATE_TYPE_P (type))
5014 int size = int_size_in_bytes (type);
5015 int align = TYPE_ALIGN (type);
5018 slotno += slotno & 1;
5019 if (size > 8 && size <= 16
5020 && slotno == SPARC_INT_ARG_MAX - 1)
5023 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5024 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5027 if (GET_MODE_ALIGNMENT (mode) == 128)
5029 slotno += slotno & 1;
5030 if (slotno == SPARC_INT_ARG_MAX - 2)
5035 if (slotno == SPARC_INT_ARG_MAX - 1)
5039 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5041 if (GET_MODE_ALIGNMENT (mode) == 128)
5042 slotno += slotno & 1;
5043 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5051 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5052 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5053 quad-precision floats by invisible reference.
5054 v9: Aggregates greater than 16 bytes are passed by reference.
5055 For Pascal, also pass arrays by reference. */
5058 function_arg_pass_by_reference (cum, mode, type, named)
5059 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
5060 enum machine_mode mode;
5062 int named ATTRIBUTE_UNUSED;
5066 return ((type && AGGREGATE_TYPE_P (type))
5067 || mode == TFmode || mode == TCmode);
5071 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5072 /* Consider complex values as aggregates, so care for TCmode. */
5073 || GET_MODE_SIZE (mode) > 16
5075 && AGGREGATE_TYPE_P (type)
5076 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5080 /* Handle the FUNCTION_ARG_ADVANCE macro.
5081 Update the data in CUM to advance over an argument
5082 of mode MODE and data type TYPE.
5083 TYPE is null for libcalls where that information may not be available. */
5086 function_arg_advance (cum, mode, type, named)
5087 CUMULATIVE_ARGS *cum;
5088 enum machine_mode mode;
5092 int slotno, regno, padding;
5094 /* We pass 0 for incoming_p here, it doesn't matter. */
5095 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5097 /* If register required leading padding, add it. */
5099 cum->words += padding;
5103 cum->words += (mode != BLKmode
5104 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5105 : ROUND_ADVANCE (int_size_in_bytes (type)));
5109 if (type && AGGREGATE_TYPE_P (type))
5111 int size = int_size_in_bytes (type);
5115 else if (size <= 16)
5117 else /* passed by reference */
5120 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
5124 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5126 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
5130 cum->words += (mode != BLKmode
5131 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5132 : ROUND_ADVANCE (int_size_in_bytes (type)));
5137 /* Handle the FUNCTION_ARG_PADDING macro.
5138 For the 64 bit ABI structs are always stored left shifted in their
5142 function_arg_padding (mode, type)
5143 enum machine_mode mode;
5146 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5149 /* This is the default definition. */
5150 return (! BYTES_BIG_ENDIAN
5153 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5154 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
5155 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5156 ? downward : upward));
5159 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5160 For v9, function return values are subject to the same rules as arguments,
5161 except that up to 32-bytes may be returned in registers. */
5164 function_value (type, mode, incoming_p)
5166 enum machine_mode mode;
5170 int regbase = (incoming_p
5171 ? SPARC_OUTGOING_INT_ARG_FIRST
5172 : SPARC_INCOMING_INT_ARG_FIRST);
5174 if (TARGET_ARCH64 && type)
5176 if (TREE_CODE (type) == RECORD_TYPE)
5178 /* Structures up to 32 bytes in size are passed in registers,
5179 promoted to fp registers where possible. */
5181 if (int_size_in_bytes (type) > 32)
5182 abort (); /* shouldn't get here */
5184 return function_arg_record_value (type, mode, 0, 1, regbase);
5186 else if (AGGREGATE_TYPE_P (type))
5188 /* All other aggregate types are passed in an integer register
5189 in a mode corresponding to the size of the type. */
5190 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5195 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5200 && GET_MODE_CLASS (mode) == MODE_INT
5201 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5202 && type && ! AGGREGATE_TYPE_P (type))
5206 regno = BASE_RETURN_VALUE_REG (mode);
5208 regno = BASE_OUTGOING_VALUE_REG (mode);
5210 return gen_rtx_REG (mode, regno);
5213 /* Do what is necessary for `va_start'. We look at the current function
5214 to determine if stdarg or varargs is used and return the address of
5215 the first unnamed parameter. */
5218 sparc_builtin_saveregs ()
5220 int first_reg = current_function_args_info.words;
5224 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5225 emit_move_insn (gen_rtx_MEM (word_mode,
5226 gen_rtx_PLUS (Pmode,
5228 GEN_INT (FIRST_PARM_OFFSET (0)
5231 gen_rtx_REG (word_mode,
5232 BASE_INCOMING_ARG_REG (word_mode) + regno));
5234 address = gen_rtx_PLUS (Pmode,
5236 GEN_INT (FIRST_PARM_OFFSET (0)
5237 + UNITS_PER_WORD * first_reg));
5242 /* Implement `va_start' for varargs and stdarg. */
5245 sparc_va_start (stdarg_p, valist, nextarg)
5246 int stdarg_p ATTRIBUTE_UNUSED;
5250 nextarg = expand_builtin_saveregs ();
5251 std_expand_builtin_va_start (1, valist, nextarg);
5254 /* Implement `va_arg'. */
5257 sparc_va_arg (valist, type)
5260 HOST_WIDE_INT size, rsize, align;
5265 /* Round up sizeof(type) to a word. */
5266 size = int_size_in_bytes (type);
5267 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5272 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5273 align = 2 * UNITS_PER_WORD;
5275 if (AGGREGATE_TYPE_P (type))
5277 if ((unsigned HOST_WIDE_INT) size > 16)
5280 size = rsize = UNITS_PER_WORD;
5282 /* SPARC v9 ABI states that structures up to 8 bytes in size are
5283 given one 8 byte slot. */
5285 size = rsize = UNITS_PER_WORD;
5292 if (AGGREGATE_TYPE_P (type)
5293 || TYPE_MODE (type) == TFmode
5294 || TYPE_MODE (type) == TCmode)
5297 size = rsize = UNITS_PER_WORD;
5304 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5305 build_int_2 (align - 1, 0)));
5306 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5307 build_int_2 (-align, -1)));
5310 addr = incr = save_expr (incr);
5311 if (BYTES_BIG_ENDIAN && size < rsize)
5313 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5314 build_int_2 (rsize - size, 0)));
5316 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5317 build_int_2 (rsize, 0)));
5319 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5320 TREE_SIDE_EFFECTS (incr) = 1;
5321 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5323 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5325 /* If the address isn't aligned properly for the type,
5326 we may need to copy to a temporary.
5327 FIXME: This is inefficient. Usually we can do this
5330 && TYPE_ALIGN (type) > BITS_PER_WORD
5333 /* FIXME: We really need to specify that the temporary is live
5334 for the whole function because expand_builtin_va_arg wants
5335 the alias set to be get_varargs_alias_set (), but in this
5336 case the alias set is that for TYPE and if the memory gets
5337 reused it will be reused with alias set TYPE. */
5338 rtx tmp = assign_temp (type, 0, 1, 0);
5341 addr_rtx = force_reg (Pmode, addr_rtx);
5342 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5343 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5344 set_mem_align (addr_rtx, BITS_PER_WORD);
5345 tmp = shallow_copy_rtx (tmp);
5346 PUT_MODE (tmp, BLKmode);
5347 set_mem_alias_set (tmp, 0);
5349 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize));
5350 if (dest_addr != NULL_RTX)
5351 addr_rtx = dest_addr;
5353 addr_rtx = XCEXP (tmp, 0, MEM);
5358 addr_rtx = force_reg (Pmode, addr_rtx);
5359 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5360 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5366 /* Return the string to output a conditional branch to LABEL, which is
5367 the operand number of the label. OP is the conditional expression.
5368 XEXP (OP, 0) is assumed to be a condition code register (integer or
5369 floating point) and its mode specifies what kind of comparison we made.
5371 REVERSED is non-zero if we should reverse the sense of the comparison.
5373 ANNUL is non-zero if we should generate an annulling branch.
5375 NOOP is non-zero if we have to follow this branch by a noop.
5377 INSN, if set, is the insn. */
5380 output_cbranch (op, dest, label, reversed, annul, noop, insn)
5383 int reversed, annul, noop;
5386 static char string[50];
5387 enum rtx_code code = GET_CODE (op);
5388 rtx cc_reg = XEXP (op, 0);
5389 enum machine_mode mode = GET_MODE (cc_reg);
5390 const char *labelno, *branch;
5391 int spaces = 8, far;
5394 /* v9 branches are limited to +-1MB. If it is too far away,
5407 fbne,a,pn %fcc2, .LC29
5415 far = get_attr_length (insn) >= 3;
5418 /* Reversal of FP compares takes care -- an ordered compare
5419 becomes an unordered compare and vice versa. */
5420 if (mode == CCFPmode || mode == CCFPEmode)
5421 code = reverse_condition_maybe_unordered (code);
5423 code = reverse_condition (code);
5426 /* Start by writing the branch condition. */
5427 if (mode == CCFPmode || mode == CCFPEmode)
5478 /* ??? !v9: FP branches cannot be preceded by another floating point
5479 insn. Because there is currently no concept of pre-delay slots,
5480 we can fix this only by always emitting a nop before a floating
5485 strcpy (string, "nop\n\t");
5486 strcat (string, branch);
5499 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5511 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5532 strcpy (string, branch);
5534 spaces -= strlen (branch);
5535 p = strchr (string, '\0');
5537 /* Now add the annulling, the label, and a possible noop. */
5552 if (! far && insn && INSN_ADDRESSES_SET_P ())
5554 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5555 - INSN_ADDRESSES (INSN_UID (insn)));
5556 /* Leave some instructions for "slop". */
5557 if (delta < -260000 || delta >= 260000)
5561 if (mode == CCFPmode || mode == CCFPEmode)
5563 static char v9_fcc_labelno[] = "%%fccX, ";
5564 /* Set the char indicating the number of the fcc reg to use. */
5565 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5566 labelno = v9_fcc_labelno;
5569 if (REGNO (cc_reg) == SPARC_FCC_REG)
5575 else if (mode == CCXmode || mode == CCX_NOOVmode)
5577 labelno = "%%xcc, ";
5583 labelno = "%%icc, ";
5588 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5591 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5601 strcpy (p, labelno);
5602 p = strchr (p, '\0');
5605 strcpy (p, ".+12\n\tnop\n\tb\t");
5612 /* Set the char indicating the number of the operand containing the
5617 strcpy (p, "\n\tnop");
5622 /* Emit a library call comparison between floating point X and Y.
5623 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5624 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5625 values as arguments instead of the TFmode registers themselves,
5626 that's why we cannot call emit_float_lib_cmp. */
5628 sparc_emit_float_lib_cmp (x, y, comparison)
5630 enum rtx_code comparison;
5633 rtx slot0, slot1, result, tem, tem2;
5634 enum machine_mode mode;
5639 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
5643 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
5647 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
5651 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
5655 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
5659 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
5670 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
5680 if (GET_CODE (x) != MEM)
5682 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5683 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
5688 if (GET_CODE (y) != MEM)
5690 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5691 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
5696 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5698 XEXP (slot0, 0), Pmode,
5699 XEXP (slot1, 0), Pmode);
5705 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5707 x, TFmode, y, TFmode);
5713 /* Immediately move the result of the libcall into a pseudo
5714 register so reload doesn't clobber the value if it needs
5715 the return register for a spill reg. */
5716 result = gen_reg_rtx (mode);
5717 emit_move_insn (result, hard_libcall_value (mode));
5722 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
5726 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
5731 emit_cmp_insn (result, const1_rtx,
5732 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
5735 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
5738 tem = gen_reg_rtx (mode);
5740 emit_insn (gen_andsi3 (tem, result, const1_rtx));
5742 emit_insn (gen_anddi3 (tem, result, const1_rtx));
5743 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
5747 tem = gen_reg_rtx (mode);
5749 emit_insn (gen_addsi3 (tem, result, const1_rtx));
5751 emit_insn (gen_adddi3 (tem, result, const1_rtx));
5752 tem2 = gen_reg_rtx (mode);
5754 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
5756 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
5757 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
5763 /* Generate an unsigned DImode to FP conversion. This is the same code
5764 optabs would emit if we didn't have TFmode patterns. */
5767 sparc_emit_floatunsdi (operands)
5770 rtx neglab, donelab, i0, i1, f0, in, out;
5771 enum machine_mode mode;
5774 in = force_reg (DImode, operands[1]);
5775 mode = GET_MODE (out);
5776 neglab = gen_label_rtx ();
5777 donelab = gen_label_rtx ();
5778 i0 = gen_reg_rtx (DImode);
5779 i1 = gen_reg_rtx (DImode);
5780 f0 = gen_reg_rtx (mode);
5782 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
5784 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
5785 emit_jump_insn (gen_jump (donelab));
5788 emit_label (neglab);
5790 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
5791 emit_insn (gen_anddi3 (i1, in, const1_rtx));
5792 emit_insn (gen_iordi3 (i0, i0, i1));
5793 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
5794 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
5796 emit_label (donelab);
5799 /* Return the string to output a conditional branch to LABEL, testing
5800 register REG. LABEL is the operand number of the label; REG is the
5801 operand number of the reg. OP is the conditional expression. The mode
5802 of REG says what kind of comparison we made.
5804 REVERSED is non-zero if we should reverse the sense of the comparison.
5806 ANNUL is non-zero if we should generate an annulling branch.
5808 NOOP is non-zero if we have to follow this branch by a noop. */
5811 output_v9branch (op, dest, reg, label, reversed, annul, noop, insn)
5814 int reversed, annul, noop;
5817 static char string[50];
5818 enum rtx_code code = GET_CODE (op);
5819 enum machine_mode mode = GET_MODE (XEXP (op, 0));
5824 /* branch on register are limited to +-128KB. If it is too far away,
5837 brgez,a,pn %o1, .LC29
5843 ba,pt %xcc, .LC29 */
5845 far = get_attr_length (insn) >= 3;
5847 /* If not floating-point or if EQ or NE, we can just reverse the code. */
5849 code = reverse_condition (code);
5851 /* Only 64 bit versions of these instructions exist. */
5855 /* Start by writing the branch condition. */
5860 strcpy (string, "brnz");
5864 strcpy (string, "brz");
5868 strcpy (string, "brgez");
5872 strcpy (string, "brlz");
5876 strcpy (string, "brlez");
5880 strcpy (string, "brgz");
5887 p = strchr (string, '\0');
5889 /* Now add the annulling, reg, label, and nop. */
5896 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5899 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5904 *p = p < string + 8 ? '\t' : ' ';
5912 int veryfar = 1, delta;
5914 if (INSN_ADDRESSES_SET_P ())
5916 delta = (INSN_ADDRESSES (INSN_UID (dest))
5917 - INSN_ADDRESSES (INSN_UID (insn)));
5918 /* Leave some instructions for "slop". */
5919 if (delta >= -260000 && delta < 260000)
5923 strcpy (p, ".+12\n\tnop\n\t");
5934 strcpy (p, "ba,pt\t%%xcc, ");
5944 strcpy (p, "\n\tnop");
5949 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
5950 Such instructions cannot be used in the delay slot of return insn on v9.
5951 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
5955 epilogue_renumber (where, test)
5956 register rtx *where;
5959 register const char *fmt;
5961 register enum rtx_code code;
5966 code = GET_CODE (*where);
5971 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
5973 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
5974 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
5982 /* Do not replace the frame pointer with the stack pointer because
5983 it can cause the delayed instruction to load below the stack.
5984 This occurs when instructions like:
5986 (set (reg/i:SI 24 %i0)
5987 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
5988 (const_int -20 [0xffffffec])) 0))
5990 are in the return delayed slot. */
5992 if (GET_CODE (XEXP (*where, 0)) == REG
5993 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
5994 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
5995 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6000 if (SPARC_STACK_BIAS
6001 && GET_CODE (XEXP (*where, 0)) == REG
6002 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6010 fmt = GET_RTX_FORMAT (code);
6012 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6017 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6018 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6021 else if (fmt[i] == 'e'
6022 && epilogue_renumber (&(XEXP (*where, i)), test))
6028 /* Leaf functions and non-leaf functions have different needs. */
6031 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6034 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6036 static const int *const reg_alloc_orders[] = {
6037 reg_leaf_alloc_order,
6038 reg_nonleaf_alloc_order};
6041 order_regs_for_local_alloc ()
6043 static int last_order_nonleaf = 1;
6045 if (regs_ever_live[15] != last_order_nonleaf)
6047 last_order_nonleaf = !last_order_nonleaf;
6048 memcpy ((char *) reg_alloc_order,
6049 (const char *) reg_alloc_orders[last_order_nonleaf],
6050 FIRST_PSEUDO_REGISTER * sizeof (int));
6054 /* Return 1 if REG and MEM are legitimate enough to allow the various
6055 mem<-->reg splits to be run. */
6058 sparc_splitdi_legitimate (reg, mem)
6062 /* Punt if we are here by mistake. */
6063 if (! reload_completed)
6066 /* We must have an offsettable memory reference. */
6067 if (! offsettable_memref_p (mem))
6070 /* If we have legitimate args for ldd/std, we do not want
6071 the split to happen. */
6072 if ((REGNO (reg) % 2) == 0
6073 && mem_min_alignment (mem, 8))
6080 /* Return 1 if x and y are some kind of REG and they refer to
6081 different hard registers. This test is guarenteed to be
6082 run after reload. */
6085 sparc_absnegfloat_split_legitimate (x, y)
6088 if (GET_CODE (x) != REG)
6090 if (GET_CODE (y) != REG)
6092 if (REGNO (x) == REGNO (y))
6097 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6098 This makes them candidates for using ldd and std insns.
6100 Note reg1 and reg2 *must* be hard registers. */
6103 registers_ok_for_ldd_peep (reg1, reg2)
6106 /* We might have been passed a SUBREG. */
6107 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6110 if (REGNO (reg1) % 2 != 0)
6113 /* Integer ldd is deprecated in SPARC V9 */
6114 if (TARGET_V9 && REGNO (reg1) < 32)
6117 return (REGNO (reg1) == REGNO (reg2) - 1);
6120 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6123 This can only happen when addr1 and addr2, the addresses in mem1
6124 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6125 addr1 must also be aligned on a 64-bit boundary.
6127 Also iff dependent_reg_rtx is not null it should not be used to
6128 compute the address for mem1, i.e. we cannot optimize a sequence
6140 But, note that the transformation from:
6145 is perfectly fine. Thus, the peephole2 patterns always pass us
6146 the destination register of the first load, never the second one.
6148 For stores we don't have a similar problem, so dependent_reg_rtx is
6152 mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx)
6153 rtx mem1, mem2, dependent_reg_rtx;
6159 /* The mems cannot be volatile. */
6160 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6163 /* MEM1 should be aligned on a 64-bit boundary. */
6164 if (MEM_ALIGN (mem1) < 64)
6167 addr1 = XEXP (mem1, 0);
6168 addr2 = XEXP (mem2, 0);
6170 /* Extract a register number and offset (if used) from the first addr. */
6171 if (GET_CODE (addr1) == PLUS)
6173 /* If not a REG, return zero. */
6174 if (GET_CODE (XEXP (addr1, 0)) != REG)
6178 reg1 = REGNO (XEXP (addr1, 0));
6179 /* The offset must be constant! */
6180 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6182 offset1 = INTVAL (XEXP (addr1, 1));
6185 else if (GET_CODE (addr1) != REG)
6189 reg1 = REGNO (addr1);
6190 /* This was a simple (mem (reg)) expression. Offset is 0. */
6194 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6195 if (GET_CODE (addr2) != PLUS)
6198 if (GET_CODE (XEXP (addr2, 0)) != REG
6199 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6202 if (reg1 != REGNO (XEXP (addr2, 0)))
6205 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6208 /* The first offset must be evenly divisible by 8 to ensure the
6209 address is 64 bit aligned. */
6210 if (offset1 % 8 != 0)
6213 /* The offset for the second addr must be 4 more than the first addr. */
6214 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6217 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6222 /* Return 1 if reg is a pseudo, or is the first register in
6223 a hard register pair. This makes it a candidate for use in
6224 ldd and std insns. */
6227 register_ok_for_ldd (reg)
6230 /* We might have been passed a SUBREG. */
6231 if (GET_CODE (reg) != REG)
6234 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6235 return (REGNO (reg) % 2 == 0);
6240 /* Print operand X (an rtx) in assembler syntax to file FILE.
6241 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6242 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6245 print_operand (file, x, code)
6253 /* Output a 'nop' if there's nothing for the delay slot. */
6254 if (dbr_sequence_length () == 0)
6255 fputs ("\n\t nop", file);
6258 /* Output an annul flag if there's nothing for the delay slot and we
6259 are optimizing. This is always used with '(' below. */
6260 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6261 this is a dbx bug. So, we only do this when optimizing. */
6262 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6263 Always emit a nop in case the next instruction is a branch. */
6264 if (dbr_sequence_length () == 0
6265 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6269 /* Output a 'nop' if there's nothing for the delay slot and we are
6270 not optimizing. This is always used with '*' above. */
6271 if (dbr_sequence_length () == 0
6272 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6273 fputs ("\n\t nop", file);
6276 /* Output the Embedded Medium/Anywhere code model base register. */
6277 fputs (EMBMEDANY_BASE_REG, file);
6280 /* Print out what we are using as the frame pointer. This might
6281 be %fp, or might be %sp+offset. */
6282 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6283 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
6286 /* Adjust the operand to take into account a RESTORE operation. */
6287 if (GET_CODE (x) == CONST_INT)
6289 else if (GET_CODE (x) != REG)
6290 output_operand_lossage ("invalid %%Y operand");
6291 else if (REGNO (x) < 8)
6292 fputs (reg_names[REGNO (x)], file);
6293 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6294 fputs (reg_names[REGNO (x)-16], file);
6296 output_operand_lossage ("invalid %%Y operand");
6299 /* Print out the low order register name of a register pair. */
6300 if (WORDS_BIG_ENDIAN)
6301 fputs (reg_names[REGNO (x)+1], file);
6303 fputs (reg_names[REGNO (x)], file);
6306 /* Print out the high order register name of a register pair. */
6307 if (WORDS_BIG_ENDIAN)
6308 fputs (reg_names[REGNO (x)], file);
6310 fputs (reg_names[REGNO (x)+1], file);
6313 /* Print out the second register name of a register pair or quad.
6314 I.e., R (%o0) => %o1. */
6315 fputs (reg_names[REGNO (x)+1], file);
6318 /* Print out the third register name of a register quad.
6319 I.e., S (%o0) => %o2. */
6320 fputs (reg_names[REGNO (x)+2], file);
6323 /* Print out the fourth register name of a register quad.
6324 I.e., T (%o0) => %o3. */
6325 fputs (reg_names[REGNO (x)+3], file);
6328 /* Print a condition code register. */
6329 if (REGNO (x) == SPARC_ICC_REG)
6331 /* We don't handle CC[X]_NOOVmode because they're not supposed
6333 if (GET_MODE (x) == CCmode)
6334 fputs ("%icc", file);
6335 else if (GET_MODE (x) == CCXmode)
6336 fputs ("%xcc", file);
6341 /* %fccN register */
6342 fputs (reg_names[REGNO (x)], file);
6345 /* Print the operand's address only. */
6346 output_address (XEXP (x, 0));
6349 /* In this case we need a register. Use %g0 if the
6350 operand is const0_rtx. */
6352 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
6354 fputs ("%g0", file);
6361 switch (GET_CODE (x))
6363 case IOR: fputs ("or", file); break;
6364 case AND: fputs ("and", file); break;
6365 case XOR: fputs ("xor", file); break;
6366 default: output_operand_lossage ("invalid %%A operand");
6371 switch (GET_CODE (x))
6373 case IOR: fputs ("orn", file); break;
6374 case AND: fputs ("andn", file); break;
6375 case XOR: fputs ("xnor", file); break;
6376 default: output_operand_lossage ("invalid %%B operand");
6380 /* These are used by the conditional move instructions. */
6384 enum rtx_code rc = GET_CODE (x);
6388 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6389 if (mode == CCFPmode || mode == CCFPEmode)
6390 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6392 rc = reverse_condition (GET_CODE (x));
6396 case NE: fputs ("ne", file); break;
6397 case EQ: fputs ("e", file); break;
6398 case GE: fputs ("ge", file); break;
6399 case GT: fputs ("g", file); break;
6400 case LE: fputs ("le", file); break;
6401 case LT: fputs ("l", file); break;
6402 case GEU: fputs ("geu", file); break;
6403 case GTU: fputs ("gu", file); break;
6404 case LEU: fputs ("leu", file); break;
6405 case LTU: fputs ("lu", file); break;
6406 case LTGT: fputs ("lg", file); break;
6407 case UNORDERED: fputs ("u", file); break;
6408 case ORDERED: fputs ("o", file); break;
6409 case UNLT: fputs ("ul", file); break;
6410 case UNLE: fputs ("ule", file); break;
6411 case UNGT: fputs ("ug", file); break;
6412 case UNGE: fputs ("uge", file); break;
6413 case UNEQ: fputs ("ue", file); break;
6414 default: output_operand_lossage (code == 'c'
6415 ? "invalid %%c operand"
6416 : "invalid %%C operand");
6421 /* These are used by the movr instruction pattern. */
6425 enum rtx_code rc = (code == 'd'
6426 ? reverse_condition (GET_CODE (x))
6430 case NE: fputs ("ne", file); break;
6431 case EQ: fputs ("e", file); break;
6432 case GE: fputs ("gez", file); break;
6433 case LT: fputs ("lz", file); break;
6434 case LE: fputs ("lez", file); break;
6435 case GT: fputs ("gz", file); break;
6436 default: output_operand_lossage (code == 'd'
6437 ? "invalid %%d operand"
6438 : "invalid %%D operand");
6445 /* Print a sign-extended character. */
6446 int i = trunc_int_for_mode (INTVAL (x), QImode);
6447 fprintf (file, "%d", i);
6452 /* Operand must be a MEM; write its address. */
6453 if (GET_CODE (x) != MEM)
6454 output_operand_lossage ("invalid %%f operand");
6455 output_address (XEXP (x, 0));
6459 /* Do nothing special. */
6463 /* Undocumented flag. */
6464 output_operand_lossage ("invalid operand output code");
6467 if (GET_CODE (x) == REG)
6468 fputs (reg_names[REGNO (x)], file);
6469 else if (GET_CODE (x) == MEM)
6472 /* Poor Sun assembler doesn't understand absolute addressing. */
6473 if (CONSTANT_P (XEXP (x, 0)))
6474 fputs ("%g0+", file);
6475 output_address (XEXP (x, 0));
6478 else if (GET_CODE (x) == HIGH)
6480 fputs ("%hi(", file);
6481 output_addr_const (file, XEXP (x, 0));
6484 else if (GET_CODE (x) == LO_SUM)
6486 print_operand (file, XEXP (x, 0), 0);
6487 if (TARGET_CM_MEDMID)
6488 fputs ("+%l44(", file);
6490 fputs ("+%lo(", file);
6491 output_addr_const (file, XEXP (x, 1));
6494 else if (GET_CODE (x) == CONST_DOUBLE
6495 && (GET_MODE (x) == VOIDmode
6496 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
6498 if (CONST_DOUBLE_HIGH (x) == 0)
6499 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
6500 else if (CONST_DOUBLE_HIGH (x) == -1
6501 && CONST_DOUBLE_LOW (x) < 0)
6502 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
6504 output_operand_lossage ("long long constant not a valid immediate operand");
6506 else if (GET_CODE (x) == CONST_DOUBLE)
6507 output_operand_lossage ("floating point constant not a valid immediate operand");
6508 else { output_addr_const (file, x); }
6511 /* Target hook for assembling integer objects. The sparc version has
6512 special handling for aligned DI-mode objects. */
6515 sparc_assemble_integer (x, size, aligned_p)
6520 /* ??? We only output .xword's for symbols and only then in environments
6521 where the assembler can handle them. */
6522 if (aligned_p && size == 8
6523 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
6527 assemble_integer_with_op ("\t.xword\t", x);
6532 assemble_aligned_integer (4, const0_rtx);
6533 assemble_aligned_integer (4, x);
6537 return default_assemble_integer (x, size, aligned_p);
6540 /* Return the value of a code used in the .proc pseudo-op that says
6541 what kind of result this function returns. For non-C types, we pick
6542 the closest C type. */
6544 #ifndef SHORT_TYPE_SIZE
6545 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6548 #ifndef INT_TYPE_SIZE
6549 #define INT_TYPE_SIZE BITS_PER_WORD
6552 #ifndef LONG_TYPE_SIZE
6553 #define LONG_TYPE_SIZE BITS_PER_WORD
6556 #ifndef LONG_LONG_TYPE_SIZE
6557 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6560 #ifndef FLOAT_TYPE_SIZE
6561 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6564 #ifndef DOUBLE_TYPE_SIZE
6565 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6568 #ifndef LONG_DOUBLE_TYPE_SIZE
6569 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6573 sparc_type_code (type)
6576 register unsigned long qualifiers = 0;
6577 register unsigned shift;
6579 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6580 setting more, since some assemblers will give an error for this. Also,
6581 we must be careful to avoid shifts of 32 bits or more to avoid getting
6582 unpredictable results. */
6584 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
6586 switch (TREE_CODE (type))
6592 qualifiers |= (3 << shift);
6597 qualifiers |= (2 << shift);
6601 case REFERENCE_TYPE:
6603 qualifiers |= (1 << shift);
6607 return (qualifiers | 8);
6610 case QUAL_UNION_TYPE:
6611 return (qualifiers | 9);
6614 return (qualifiers | 10);
6617 return (qualifiers | 16);
6620 /* If this is a range type, consider it to be the underlying
6622 if (TREE_TYPE (type) != 0)
6625 /* Carefully distinguish all the standard types of C,
6626 without messing up if the language is not C. We do this by
6627 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6628 look at both the names and the above fields, but that's redundant.
6629 Any type whose size is between two C types will be considered
6630 to be the wider of the two types. Also, we do not have a
6631 special code to use for "long long", so anything wider than
6632 long is treated the same. Note that we can't distinguish
6633 between "int" and "long" in this code if they are the same
6634 size, but that's fine, since neither can the assembler. */
6636 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
6637 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
6639 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
6640 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
6642 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
6643 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
6646 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
6649 /* If this is a range type, consider it to be the underlying
6651 if (TREE_TYPE (type) != 0)
6654 /* Carefully distinguish all the standard types of C,
6655 without messing up if the language is not C. */
6657 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
6658 return (qualifiers | 6);
6661 return (qualifiers | 7);
6663 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
6664 /* ??? We need to distinguish between double and float complex types,
6665 but I don't know how yet because I can't reach this code from
6666 existing front-ends. */
6667 return (qualifiers | 7); /* Who knows? */
6669 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
6670 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
6671 case FILE_TYPE: /* GNU Pascal FILE type. */
6672 case SET_TYPE: /* GNU Pascal SET type. */
6673 case LANG_TYPE: /* ? */
6677 abort (); /* Not a type! */
6684 /* Nested function support. */
6686 /* Emit RTL insns to initialize the variable parts of a trampoline.
6687 FNADDR is an RTX for the address of the function's pure code.
6688 CXT is an RTX for the static chain value for the function.
6690 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6691 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6692 (to store insns). This is a bit excessive. Perhaps a different
6693 mechanism would be better here.
6695 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6698 sparc_initialize_trampoline (tramp, fnaddr, cxt)
6699 rtx tramp, fnaddr, cxt;
6701 /* SPARC 32 bit trampoline:
6704 sethi %hi(static), %g2
6706 or %g2, %lo(static), %g2
6708 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6709 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6711 #ifdef TRANSFER_FROM_TRAMPOLINE
6712 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6713 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
6717 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
6718 expand_binop (SImode, ior_optab,
6719 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
6720 size_int (10), 0, 1),
6721 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
6722 NULL_RTX, 1, OPTAB_DIRECT));
6725 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6726 expand_binop (SImode, ior_optab,
6727 expand_shift (RSHIFT_EXPR, SImode, cxt,
6728 size_int (10), 0, 1),
6729 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
6730 NULL_RTX, 1, OPTAB_DIRECT));
6733 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6734 expand_binop (SImode, ior_optab,
6735 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
6736 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
6737 NULL_RTX, 1, OPTAB_DIRECT));
6740 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6741 expand_binop (SImode, ior_optab,
6742 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
6743 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
6744 NULL_RTX, 1, OPTAB_DIRECT));
6746 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6747 aligned on a 16 byte boundary so one flush clears it all. */
6748 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
6749 if (sparc_cpu != PROCESSOR_ULTRASPARC
6750 && sparc_cpu != PROCESSOR_ULTRASPARC3)
6751 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
6752 plus_constant (tramp, 8)))));
6755 /* The 64 bit version is simpler because it makes more sense to load the
6756 values as "immediate" data out of the trampoline. It's also easier since
6757 we can read the PC without clobbering a register. */
6760 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
6761 rtx tramp, fnaddr, cxt;
6763 #ifdef TRANSFER_FROM_TRAMPOLINE
6764 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6765 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
6776 emit_move_insn (gen_rtx_MEM (SImode, tramp),
6777 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
6778 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6779 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
6780 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6781 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
6782 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6783 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
6784 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
6785 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
6786 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
6788 if (sparc_cpu != PROCESSOR_ULTRASPARC
6789 && sparc_cpu != PROCESSOR_ULTRASPARC3)
6790 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
6793 /* Subroutines to support a flat (single) register window calling
6796 /* Single-register window sparc stack frames look like:
6798 Before call After call
6799 +-----------------------+ +-----------------------+
6801 mem | caller's temps. | | caller's temps. |
6803 +-----------------------+ +-----------------------+
6805 | arguments on stack. | | arguments on stack. |
6807 +-----------------------+FP+92->+-----------------------+
6808 | 6 words to save | | 6 words to save |
6809 | arguments passed | | arguments passed |
6810 | in registers, even | | in registers, even |
6811 | if not passed. | | if not passed. |
6812 SP+68->+-----------------------+FP+68->+-----------------------+
6813 | 1 word struct addr | | 1 word struct addr |
6814 +-----------------------+FP+64->+-----------------------+
6816 | 16 word reg save area | | 16 word reg save area |
6818 SP->+-----------------------+ FP->+-----------------------+
6820 | fp/alu reg moves |
6821 FP-16->+-----------------------+
6825 +-----------------------+
6827 | fp register save |
6829 +-----------------------+
6831 | gp register save |
6833 +-----------------------+
6835 | alloca allocations |
6837 +-----------------------+
6839 | arguments on stack |
6841 SP+92->+-----------------------+
6843 | arguments passed |
6844 | in registers, even |
6845 low | if not passed. |
6846 memory SP+68->+-----------------------+
6847 | 1 word struct addr |
6848 SP+64->+-----------------------+
6850 I 16 word reg save area |
6852 SP->+-----------------------+ */
6854 /* Structure to be filled in by sparc_flat_compute_frame_size with register
6855 save masks, and offsets for the current function. */
6857 struct sparc_frame_info
6859 unsigned long total_size; /* # bytes that the entire frame takes up. */
6860 unsigned long var_size; /* # bytes that variables take up. */
6861 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6862 unsigned long extra_size; /* # bytes of extra gunk. */
6863 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6864 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6865 unsigned long gmask; /* Mask of saved gp registers. */
6866 unsigned long fmask; /* Mask of saved fp registers. */
6867 unsigned long reg_offset; /* Offset from new sp to store regs. */
6868 int initialized; /* Nonzero if frame size already calculated. */
6871 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6872 struct sparc_frame_info current_frame_info;
6874 /* Zero structure to initialize current_frame_info. */
6875 struct sparc_frame_info zero_frame_info;
6877 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6879 #define RETURN_ADDR_REGNUM 15
6880 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
6881 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6883 #define MUST_SAVE_REGISTER(regno) \
6884 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6885 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
6886 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6888 /* Return the bytes needed to compute the frame pointer from the current
6892 sparc_flat_compute_frame_size (size)
6893 int size; /* # of var. bytes allocated. */
6896 unsigned long total_size; /* # bytes that the entire frame takes up. */
6897 unsigned long var_size; /* # bytes that variables take up. */
6898 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6899 unsigned long extra_size; /* # extra bytes. */
6900 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6901 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6902 unsigned long gmask; /* Mask of saved gp registers. */
6903 unsigned long fmask; /* Mask of saved fp registers. */
6904 unsigned long reg_offset; /* Offset to register save area. */
6905 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
6907 /* This is the size of the 16 word reg save area, 1 word struct addr
6908 area, and 4 word fp/alu register copy area. */
6909 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
6919 if (!leaf_function_p ())
6921 /* Also include the size needed for the 6 parameter registers. */
6922 args_size = current_function_outgoing_args_size + 24;
6924 total_size = var_size + args_size;
6926 /* Calculate space needed for gp registers. */
6927 for (regno = 1; regno <= 31; regno++)
6929 if (MUST_SAVE_REGISTER (regno))
6931 /* If we need to save two regs in a row, ensure there's room to bump
6932 up the address to align it to a doubleword boundary. */
6933 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
6935 if (gp_reg_size % 8 != 0)
6937 gp_reg_size += 2 * UNITS_PER_WORD;
6938 gmask |= 3 << regno;
6944 gp_reg_size += UNITS_PER_WORD;
6945 gmask |= 1 << regno;
6950 /* Calculate space needed for fp registers. */
6951 for (regno = 32; regno <= 63; regno++)
6953 if (regs_ever_live[regno] && !call_used_regs[regno])
6955 fp_reg_size += UNITS_PER_WORD;
6956 fmask |= 1 << (regno - 32);
6963 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
6964 /* Ensure save area is 8 byte aligned if we need it. */
6966 if (need_aligned_p && n != 0)
6968 total_size += 8 - n;
6969 reg_offset += 8 - n;
6971 total_size += gp_reg_size + fp_reg_size;
6974 /* If we must allocate a stack frame at all, we must also allocate
6975 room for register window spillage, so as to be binary compatible
6976 with libraries and operating systems that do not use -mflat. */
6978 total_size += extra_size;
6982 total_size = SPARC_STACK_ALIGN (total_size);
6984 /* Save other computed information. */
6985 current_frame_info.total_size = total_size;
6986 current_frame_info.var_size = var_size;
6987 current_frame_info.args_size = args_size;
6988 current_frame_info.extra_size = extra_size;
6989 current_frame_info.gp_reg_size = gp_reg_size;
6990 current_frame_info.fp_reg_size = fp_reg_size;
6991 current_frame_info.gmask = gmask;
6992 current_frame_info.fmask = fmask;
6993 current_frame_info.reg_offset = reg_offset;
6994 current_frame_info.initialized = reload_completed;
6996 /* Ok, we're done. */
7000 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7003 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7004 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7005 [BASE_REG+OFFSET] will always be a valid address.
7007 WORD_OP is either "st" for save, "ld" for restore.
7008 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7011 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
7012 doubleword_op, base_offset)
7014 const char *base_reg;
7015 unsigned int offset;
7016 unsigned long gmask;
7017 unsigned long fmask;
7018 const char *word_op;
7019 const char *doubleword_op;
7020 unsigned long base_offset;
7024 if (gmask == 0 && fmask == 0)
7027 /* Save registers starting from high to low. We've already saved the
7028 previous frame pointer and previous return address for the debugger's
7029 sake. The debugger allows us to not need a nop in the epilog if at least
7030 one register is reloaded in addition to return address. */
7034 for (regno = 1; regno <= 31; regno++)
7036 if ((gmask & (1L << regno)) != 0)
7038 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7040 /* We can save two registers in a row. If we're not at a
7041 double word boundary, move to one.
7042 sparc_flat_compute_frame_size ensures there's room to do
7044 if (offset % 8 != 0)
7045 offset += UNITS_PER_WORD;
7047 if (word_op[0] == 's')
7049 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7050 doubleword_op, reg_names[regno],
7052 if (dwarf2out_do_frame ())
7054 char *l = dwarf2out_cfi_label ();
7055 dwarf2out_reg_save (l, regno, offset + base_offset);
7057 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7061 fprintf (file, "\t%s\t[%s+%d], %s\n",
7062 doubleword_op, base_reg, offset,
7065 offset += 2 * UNITS_PER_WORD;
7070 if (word_op[0] == 's')
7072 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7073 word_op, reg_names[regno],
7075 if (dwarf2out_do_frame ())
7076 dwarf2out_reg_save ("", regno, offset + base_offset);
7079 fprintf (file, "\t%s\t[%s+%d], %s\n",
7080 word_op, base_reg, offset, reg_names[regno]);
7082 offset += UNITS_PER_WORD;
7090 for (regno = 32; regno <= 63; regno++)
7092 if ((fmask & (1L << (regno - 32))) != 0)
7094 if (word_op[0] == 's')
7096 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7097 word_op, reg_names[regno],
7099 if (dwarf2out_do_frame ())
7100 dwarf2out_reg_save ("", regno, offset + base_offset);
7103 fprintf (file, "\t%s\t[%s+%d], %s\n",
7104 word_op, base_reg, offset, reg_names[regno]);
7106 offset += UNITS_PER_WORD;
7112 /* Set up the stack and frame (if desired) for the function. */
7115 sparc_flat_function_prologue (file, size)
7119 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7120 unsigned long gmask = current_frame_info.gmask;
7122 sparc_output_scratch_registers (file);
7124 /* This is only for the human reader. */
7125 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7126 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7128 current_frame_info.var_size,
7129 current_frame_info.gp_reg_size / 4,
7130 current_frame_info.fp_reg_size / 4,
7131 current_function_outgoing_args_size,
7132 current_frame_info.extra_size);
7134 size = SPARC_STACK_ALIGN (size);
7135 size = (! current_frame_info.initialized
7136 ? sparc_flat_compute_frame_size (size)
7137 : current_frame_info.total_size);
7139 /* These cases shouldn't happen. Catch them now. */
7140 if (size == 0 && (gmask || current_frame_info.fmask))
7143 /* Allocate our stack frame by decrementing %sp.
7144 At present, the only algorithm gdb can use to determine if this is a
7145 flat frame is if we always set %i7 if we set %sp. This can be optimized
7146 in the future by putting in some sort of debugging information that says
7147 this is a `flat' function. However, there is still the case of debugging
7148 code without such debugging information (including cases where most fns
7149 have such info, but there is one that doesn't). So, always do this now
7150 so we don't get a lot of code out there that gdb can't handle.
7151 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7152 distinguish us from a non-flat function but there won't (and shouldn't)
7153 be any differences anyway. The return pc is saved (if necessary) right
7154 after %i7 so gdb won't have to look too far to find it. */
7157 unsigned int reg_offset = current_frame_info.reg_offset;
7158 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7159 static const char *const t1_str = "%g1";
7161 /* Things get a little tricky if local variables take up more than ~4096
7162 bytes and outgoing arguments take up more than ~4096 bytes. When that
7163 happens, the register save area can't be accessed from either end of
7164 the frame. Handle this by decrementing %sp to the start of the gp
7165 register save area, save the regs, update %i7, and then set %sp to its
7166 final value. Given that we only have one scratch register to play
7167 with it is the cheapest solution, and it helps gdb out as it won't
7168 slow down recognition of flat functions.
7169 Don't change the order of insns emitted here without checking with
7170 the gdb folk first. */
7172 /* Is the entire register save area offsettable from %sp? */
7173 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7177 fprintf (file, "\tadd\t%s, %d, %s\n",
7178 sp_str, (int) -size, sp_str);
7179 if (gmask & HARD_FRAME_POINTER_MASK)
7181 fprintf (file, "\tst\t%s, [%s+%d]\n",
7182 fp_str, sp_str, reg_offset);
7183 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7184 sp_str, (int) -size, fp_str, ASM_COMMENT_START);
7190 fprintf (file, "\tset\t");
7191 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7192 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7193 t1_str, sp_str, t1_str, sp_str);
7194 if (gmask & HARD_FRAME_POINTER_MASK)
7196 fprintf (file, "\tst\t%s, [%s+%d]\n",
7197 fp_str, sp_str, reg_offset);
7198 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7199 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7203 if (dwarf2out_do_frame ())
7205 char *l = dwarf2out_cfi_label ();
7206 if (gmask & HARD_FRAME_POINTER_MASK)
7208 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7209 reg_offset - 4 - size);
7210 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7213 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7215 if (gmask & RETURN_ADDR_MASK)
7217 fprintf (file, "\tst\t%s, [%s+%d]\n",
7218 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7219 if (dwarf2out_do_frame ())
7220 dwarf2out_return_save ("", reg_offset - size);
7223 sparc_flat_save_restore (file, sp_str, reg_offset,
7224 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7225 current_frame_info.fmask,
7226 "st", "std", -size);
7230 /* Subtract %sp in two steps, but make sure there is always a
7231 64 byte register save area, and %sp is properly aligned. */
7232 /* Amount to decrement %sp by, the first time. */
7233 unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7234 /* Offset to register save area from %sp. */
7235 unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset);
7239 fprintf (file, "\tadd\t%s, %d, %s\n",
7240 sp_str, (int) -size1, sp_str);
7241 if (gmask & HARD_FRAME_POINTER_MASK)
7243 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7244 fp_str, sp_str, (int) offset, sp_str, (int) -size1,
7245 fp_str, ASM_COMMENT_START);
7251 fprintf (file, "\tset\t");
7252 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1);
7253 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7254 t1_str, sp_str, t1_str, sp_str);
7255 if (gmask & HARD_FRAME_POINTER_MASK)
7257 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7258 fp_str, sp_str, (int) offset, sp_str, t1_str,
7259 fp_str, ASM_COMMENT_START);
7263 if (dwarf2out_do_frame ())
7265 char *l = dwarf2out_cfi_label ();
7266 if (gmask & HARD_FRAME_POINTER_MASK)
7268 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7269 offset - 4 - size1);
7270 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7273 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7275 if (gmask & RETURN_ADDR_MASK)
7277 fprintf (file, "\tst\t%s, [%s+%d]\n",
7278 reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset);
7279 if (dwarf2out_do_frame ())
7280 /* offset - size1 == reg_offset - size
7281 if reg_offset were updated above like offset. */
7282 dwarf2out_return_save ("", offset - size1);
7285 sparc_flat_save_restore (file, sp_str, offset,
7286 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7287 current_frame_info.fmask,
7288 "st", "std", -size1);
7289 fprintf (file, "\tset\t");
7290 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size - size1);
7291 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7292 t1_str, sp_str, t1_str, sp_str);
7293 if (dwarf2out_do_frame ())
7294 if (! (gmask & HARD_FRAME_POINTER_MASK))
7295 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
7299 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
7302 /* Do any necessary cleanup after a function to restore stack, frame,
7306 sparc_flat_function_epilogue (file, size)
7310 rtx epilogue_delay = current_function_epilogue_delay_list;
7311 int noepilogue = FALSE;
7313 /* This is only for the human reader. */
7314 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
7316 /* The epilogue does not depend on any registers, but the stack
7317 registers, so we assume that if we have 1 pending nop, it can be
7318 ignored, and 2 it must be filled (2 nops occur for integer
7319 multiply and divide). */
7321 size = SPARC_STACK_ALIGN (size);
7322 size = (!current_frame_info.initialized
7323 ? sparc_flat_compute_frame_size (size)
7324 : current_frame_info.total_size);
7326 if (size == 0 && epilogue_delay == 0)
7328 rtx insn = get_last_insn ();
7330 /* If the last insn was a BARRIER, we don't have to write any code
7331 because a jump (aka return) was put there. */
7332 if (GET_CODE (insn) == NOTE)
7333 insn = prev_nonnote_insn (insn);
7334 if (insn && GET_CODE (insn) == BARRIER)
7340 unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset;
7341 unsigned HOST_WIDE_INT size1;
7342 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7343 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7344 static const char *const t1_str = "%g1";
7346 /* In the reload sequence, we don't need to fill the load delay
7347 slots for most of the loads, also see if we can fill the final
7348 delay slot if not otherwise filled by the reload sequence. */
7352 fprintf (file, "\tset\t");
7353 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7354 fprintf (file, ", %s\n", t1_str);
7357 if (frame_pointer_needed)
7360 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7361 fp_str, t1_str, sp_str, ASM_COMMENT_START);
7363 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
7364 fp_str, (int) size, sp_str, ASM_COMMENT_START);
7367 /* Is the entire register save area offsettable from %sp? */
7368 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7374 /* Restore %sp in two steps, but make sure there is always a
7375 64 byte register save area, and %sp is properly aligned. */
7376 /* Amount to increment %sp by, the first time. */
7377 size1 = ((reg_offset - 64 - 16) + 15) & -16;
7378 /* Offset to register save area from %sp. */
7379 reg_offset = size1 - reg_offset;
7381 fprintf (file, "\tset\t");
7382 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1);
7383 fprintf (file, ", %s\n\tadd\t%s, %s, %s\n",
7384 t1_str, sp_str, t1_str, sp_str);
7387 /* We must restore the frame pointer and return address reg first
7388 because they are treated specially by the prologue output code. */
7389 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
7391 fprintf (file, "\tld\t[%s+%d], %s\n",
7392 sp_str, (int) reg_offset, fp_str);
7395 if (current_frame_info.gmask & RETURN_ADDR_MASK)
7397 fprintf (file, "\tld\t[%s+%d], %s\n",
7398 sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]);
7402 /* Restore any remaining saved registers. */
7403 sparc_flat_save_restore (file, sp_str, reg_offset,
7404 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7405 current_frame_info.fmask,
7408 /* If we had to increment %sp in two steps, record it so the second
7409 restoration in the epilogue finishes up. */
7415 fprintf (file, "\tset\t");
7416 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7417 fprintf (file, ", %s\n", t1_str);
7421 if (current_function_returns_struct)
7422 fprintf (file, "\tjmp\t%%o7+12\n");
7424 fprintf (file, "\tretl\n");
7426 /* If the only register saved is the return address, we need a
7427 nop, unless we have an instruction to put into it. Otherwise
7428 we don't since reloading multiple registers doesn't reference
7429 the register being loaded. */
7435 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
7438 else if (size > 4095)
7439 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7442 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str);
7445 fprintf (file, "\tnop\n");
7448 /* Reset state info for each function. */
7449 current_frame_info = zero_frame_info;
7451 sparc_output_deferred_case_vectors ();
7454 /* Define the number of delay slots needed for the function epilogue.
7456 On the sparc, we need a slot if either no stack has been allocated,
7457 or the only register saved is the return register. */
7460 sparc_flat_epilogue_delay_slots ()
7462 if (!current_frame_info.initialized)
7463 (void) sparc_flat_compute_frame_size (get_frame_size ());
7465 if (current_frame_info.total_size == 0)
7471 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7472 Any single length instruction which doesn't reference the stack or frame
7476 sparc_flat_eligible_for_epilogue_delay (trial, slot)
7478 int slot ATTRIBUTE_UNUSED;
7480 rtx pat = PATTERN (trial);
7482 if (get_attr_length (trial) != 1)
7485 if (! reg_mentioned_p (stack_pointer_rtx, pat)
7486 && ! reg_mentioned_p (frame_pointer_rtx, pat))
7492 /* Adjust the cost of a scheduling dependency. Return the new cost of
7493 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7496 supersparc_adjust_cost (insn, link, dep_insn, cost)
7502 enum attr_type insn_type;
7504 if (! recog_memoized (insn))
7507 insn_type = get_attr_type (insn);
7509 if (REG_NOTE_KIND (link) == 0)
7511 /* Data dependency; DEP_INSN writes a register that INSN reads some
7514 /* if a load, then the dependence must be on the memory address;
7515 add an extra "cycle". Note that the cost could be two cycles
7516 if the reg was written late in an instruction group; we ca not tell
7518 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7521 /* Get the delay only if the address of the store is the dependence. */
7522 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7524 rtx pat = PATTERN(insn);
7525 rtx dep_pat = PATTERN (dep_insn);
7527 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7528 return cost; /* This should not happen! */
7530 /* The dependency between the two instructions was on the data that
7531 is being stored. Assume that this implies that the address of the
7532 store is not dependent. */
7533 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7536 return cost + 3; /* An approximation. */
7539 /* A shift instruction cannot receive its data from an instruction
7540 in the same cycle; add a one cycle penalty. */
7541 if (insn_type == TYPE_SHIFT)
7542 return cost + 3; /* Split before cascade into shift. */
7546 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7547 INSN writes some cycles later. */
7549 /* These are only significant for the fpu unit; writing a fp reg before
7550 the fpu has finished with it stalls the processor. */
7552 /* Reusing an integer register causes no problems. */
7553 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7561 hypersparc_adjust_cost (insn, link, dep_insn, cost)
7567 enum attr_type insn_type, dep_type;
7568 rtx pat = PATTERN(insn);
7569 rtx dep_pat = PATTERN (dep_insn);
7571 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7574 insn_type = get_attr_type (insn);
7575 dep_type = get_attr_type (dep_insn);
7577 switch (REG_NOTE_KIND (link))
7580 /* Data dependency; DEP_INSN writes a register that INSN reads some
7587 /* Get the delay iff the address of the store is the dependence. */
7588 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7591 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7598 /* If a load, then the dependence must be on the memory address. If
7599 the addresses aren't equal, then it might be a false dependency */
7600 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7602 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7603 || GET_CODE (SET_DEST (dep_pat)) != MEM
7604 || GET_CODE (SET_SRC (pat)) != MEM
7605 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7606 XEXP (SET_SRC (pat), 0)))
7614 /* Compare to branch latency is 0. There is no benefit from
7615 separating compare and branch. */
7616 if (dep_type == TYPE_COMPARE)
7618 /* Floating point compare to branch latency is less than
7619 compare to conditional move. */
7620 if (dep_type == TYPE_FPCMP)
7629 /* Anti-dependencies only penalize the fpu unit. */
7630 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7642 sparc_adjust_cost(insn, link, dep, cost)
7650 case PROCESSOR_SUPERSPARC:
7651 cost = supersparc_adjust_cost (insn, link, dep, cost);
7653 case PROCESSOR_HYPERSPARC:
7654 case PROCESSOR_SPARCLITE86X:
7655 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7664 sparc_sched_init (dump, sched_verbose, max_ready)
7665 FILE *dump ATTRIBUTE_UNUSED;
7666 int sched_verbose ATTRIBUTE_UNUSED;
7667 int max_ready ATTRIBUTE_UNUSED;
7672 sparc_use_dfa_pipeline_interface ()
7674 if ((1 << sparc_cpu) &
7675 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
7676 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7677 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
7678 (1 << PROCESSOR_ULTRASPARC3)))
7684 sparc_use_sched_lookahead ()
7686 if (sparc_cpu == PROCESSOR_ULTRASPARC
7687 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7689 if ((1 << sparc_cpu) &
7690 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7691 (1 << PROCESSOR_SPARCLITE86X)))
7704 /* Assume V9 processors are capable of at least dual-issue. */
7706 case PROCESSOR_SUPERSPARC:
7708 case PROCESSOR_HYPERSPARC:
7709 case PROCESSOR_SPARCLITE86X:
7711 case PROCESSOR_ULTRASPARC:
7712 case PROCESSOR_ULTRASPARC3:
7721 register rtx pat = PATTERN (insn);
7723 switch (GET_CODE (SET_SRC (pat)))
7725 /* Load and some shift instructions zero extend. */
7728 /* sethi clears the high bits */
7730 /* LO_SUM is used with sethi. sethi cleared the high
7731 bits and the values used with lo_sum are positive */
7733 /* Store flag stores 0 or 1 */
7743 rtx op0 = XEXP (SET_SRC (pat), 0);
7744 rtx op1 = XEXP (SET_SRC (pat), 1);
7745 if (GET_CODE (op1) == CONST_INT)
7746 return INTVAL (op1) >= 0;
7747 if (GET_CODE (op0) != REG)
7749 if (sparc_check_64 (op0, insn) == 1)
7751 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7756 rtx op0 = XEXP (SET_SRC (pat), 0);
7757 rtx op1 = XEXP (SET_SRC (pat), 1);
7758 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7760 if (GET_CODE (op1) == CONST_INT)
7761 return INTVAL (op1) >= 0;
7762 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7766 return GET_MODE (SET_SRC (pat)) == SImode;
7767 /* Positive integers leave the high bits zero. */
7769 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7771 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7774 return - (GET_MODE (SET_SRC (pat)) == SImode);
7776 return sparc_check_64 (SET_SRC (pat), insn);
7782 /* We _ought_ to have only one kind per function, but... */
7783 static rtx sparc_addr_diff_list;
7784 static rtx sparc_addr_list;
7787 sparc_defer_case_vector (lab, vec, diff)
7791 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7793 sparc_addr_diff_list
7794 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7796 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7800 sparc_output_addr_vec (vec)
7803 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7804 int idx, vlen = XVECLEN (body, 0);
7806 #ifdef ASM_OUTPUT_ADDR_VEC_START
7807 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7810 #ifdef ASM_OUTPUT_CASE_LABEL
7811 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7814 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7817 for (idx = 0; idx < vlen; idx++)
7819 ASM_OUTPUT_ADDR_VEC_ELT
7820 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7823 #ifdef ASM_OUTPUT_ADDR_VEC_END
7824 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7829 sparc_output_addr_diff_vec (vec)
7832 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7833 rtx base = XEXP (XEXP (body, 0), 0);
7834 int idx, vlen = XVECLEN (body, 1);
7836 #ifdef ASM_OUTPUT_ADDR_VEC_START
7837 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7840 #ifdef ASM_OUTPUT_CASE_LABEL
7841 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7844 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7847 for (idx = 0; idx < vlen; idx++)
7849 ASM_OUTPUT_ADDR_DIFF_ELT
7852 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7853 CODE_LABEL_NUMBER (base));
7856 #ifdef ASM_OUTPUT_ADDR_VEC_END
7857 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7862 sparc_output_deferred_case_vectors ()
7867 if (sparc_addr_list == NULL_RTX
7868 && sparc_addr_diff_list == NULL_RTX)
7871 /* Align to cache line in the function's code section. */
7872 function_section (current_function_decl);
7874 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7876 ASM_OUTPUT_ALIGN (asm_out_file, align);
7878 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7879 sparc_output_addr_vec (XEXP (t, 0));
7880 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7881 sparc_output_addr_diff_vec (XEXP (t, 0));
7883 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7886 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7887 unknown. Return 1 if the high bits are zero, -1 if the register is
7890 sparc_check_64 (x, insn)
7893 /* If a register is set only once it is safe to ignore insns this
7894 code does not know how to handle. The loop will either recognize
7895 the single set and return the correct value or fail to recognize
7900 if (GET_CODE (x) != REG)
7903 if (GET_MODE (x) == DImode)
7904 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
7906 if (flag_expensive_optimizations
7907 && REG_N_SETS (REGNO (y)) == 1)
7913 insn = get_last_insn_anywhere ();
7918 while ((insn = PREV_INSN (insn)))
7920 switch (GET_CODE (insn))
7933 rtx pat = PATTERN (insn);
7934 if (GET_CODE (pat) != SET)
7936 if (rtx_equal_p (x, SET_DEST (pat)))
7937 return set_extends (insn);
7938 if (y && rtx_equal_p (y, SET_DEST (pat)))
7939 return set_extends (insn);
7940 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
7949 sparc_v8plus_shift (operands, insn, opcode)
7954 static char asm_code[60];
7956 if (GET_CODE (operands[3]) == SCRATCH)
7957 operands[3] = operands[0];
7958 if (GET_CODE (operands[1]) == CONST_INT)
7960 output_asm_insn ("mov\t%1, %3", operands);
7964 output_asm_insn ("sllx\t%H1, 32, %3", operands);
7965 if (sparc_check_64 (operands[1], insn) <= 0)
7966 output_asm_insn ("srl\t%L1, 0, %L1", operands);
7967 output_asm_insn ("or\t%L1, %3, %3", operands);
7970 strcpy(asm_code, opcode);
7971 if (which_alternative != 2)
7972 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7974 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7977 /* Output rtl to increment the profiler label LABELNO
7978 for profiling a function entry. */
7981 sparc_profile_hook (labelno)
7987 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
7988 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
7989 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
7991 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
7994 /* Called to register all of our global variables with the garbage
7998 sparc_add_gc_roots ()
8000 ggc_add_rtx_root (&sparc_compare_op0, 1);
8001 ggc_add_rtx_root (&sparc_compare_op1, 1);
8002 ggc_add_rtx_root (&global_offset_table, 1);
8003 ggc_add_rtx_root (&get_pc_symbol, 1);
8004 ggc_add_rtx_root (&sparc_addr_diff_list, 1);
8005 ggc_add_rtx_root (&sparc_addr_list, 1);
8008 #ifdef OBJECT_FORMAT_ELF
8010 sparc_elf_asm_named_section (name, flags)
8014 if (flags & SECTION_MERGE)
8016 /* entsize cannot be expressed in this section attributes
8018 default_elf_asm_named_section (name, flags);
8022 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8024 if (!(flags & SECTION_DEBUG))
8025 fputs (",#alloc", asm_out_file);
8026 if (flags & SECTION_WRITE)
8027 fputs (",#write", asm_out_file);
8028 if (flags & SECTION_CODE)
8029 fputs (",#execinstr", asm_out_file);
8031 /* ??? Handle SECTION_BSS. */
8033 fputc ('\n', asm_out_file);
8035 #endif /* OBJECT_FORMAT_ELF */
8038 sparc_extra_constraint_check (op, c, strict)
8046 && (c == 'T' || c == 'U'))
8052 return fp_sethi_p (op);
8055 return fp_mov_p (op);
8058 return fp_high_losum_p (op);
8062 || (GET_CODE (op) == REG
8063 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8064 || reg_renumber[REGNO (op)] >= 0)))
8065 return register_ok_for_ldd (op);
8077 /* Our memory extra constraints have to emulate the
8078 behavior of 'm' and 'o' in order for reload to work
8080 if (GET_CODE (op) == MEM)
8083 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8085 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8090 reload_ok_mem = (reload_in_progress
8091 && GET_CODE (op) == REG
8092 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8093 && reg_renumber [REGNO (op)] < 0);
8096 return reload_ok_mem;
8099 /* ??? This duplicates information provided to the compiler by the
8100 ??? scheduler description. Some day, teach genautomata to output
8101 ??? the latencies and then CSE will just use that. */
8104 sparc_rtx_costs (x, code, outer_code)
8106 enum rtx_code code, outer_code;
8110 case PLUS: case MINUS: case ABS: case NEG:
8111 case FLOAT: case UNSIGNED_FLOAT:
8112 case FIX: case UNSIGNED_FIX:
8113 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8114 if (FLOAT_MODE_P (GET_MODE (x)))
8118 case PROCESSOR_ULTRASPARC:
8119 case PROCESSOR_ULTRASPARC3:
8120 return COSTS_N_INSNS (4);
8122 case PROCESSOR_SUPERSPARC:
8123 return COSTS_N_INSNS (3);
8125 case PROCESSOR_CYPRESS:
8126 return COSTS_N_INSNS (5);
8128 case PROCESSOR_HYPERSPARC:
8129 case PROCESSOR_SPARCLITE86X:
8131 return COSTS_N_INSNS (1);
8135 return COSTS_N_INSNS (1);
8140 case PROCESSOR_ULTRASPARC:
8141 if (GET_MODE (x) == SFmode)
8142 return COSTS_N_INSNS (13);
8144 return COSTS_N_INSNS (23);
8146 case PROCESSOR_ULTRASPARC3:
8147 if (GET_MODE (x) == SFmode)
8148 return COSTS_N_INSNS (20);
8150 return COSTS_N_INSNS (29);
8152 case PROCESSOR_SUPERSPARC:
8153 return COSTS_N_INSNS (12);
8155 case PROCESSOR_CYPRESS:
8156 return COSTS_N_INSNS (63);
8158 case PROCESSOR_HYPERSPARC:
8159 case PROCESSOR_SPARCLITE86X:
8160 return COSTS_N_INSNS (17);
8163 return COSTS_N_INSNS (30);
8167 if (FLOAT_MODE_P (GET_MODE (x)))
8171 case PROCESSOR_ULTRASPARC:
8172 case PROCESSOR_ULTRASPARC3:
8173 return COSTS_N_INSNS (1);
8175 case PROCESSOR_SUPERSPARC:
8176 return COSTS_N_INSNS (3);
8178 case PROCESSOR_CYPRESS:
8179 return COSTS_N_INSNS (5);
8181 case PROCESSOR_HYPERSPARC:
8182 case PROCESSOR_SPARCLITE86X:
8184 return COSTS_N_INSNS (1);
8188 /* ??? Maybe mark integer compares as zero cost on
8189 ??? all UltraSPARC processors because the result
8190 ??? can be bypassed to a branch in the same group. */
8192 return COSTS_N_INSNS (1);
8195 if (FLOAT_MODE_P (GET_MODE (x)))
8199 case PROCESSOR_ULTRASPARC:
8200 case PROCESSOR_ULTRASPARC3:
8201 return COSTS_N_INSNS (4);
8203 case PROCESSOR_SUPERSPARC:
8204 return COSTS_N_INSNS (3);
8206 case PROCESSOR_CYPRESS:
8207 return COSTS_N_INSNS (7);
8209 case PROCESSOR_HYPERSPARC:
8210 case PROCESSOR_SPARCLITE86X:
8211 return COSTS_N_INSNS (1);
8214 return COSTS_N_INSNS (5);
8218 /* The latency is actually variable for Ultra-I/II
8219 And if one of the inputs have a known constant
8220 value, we could calculate this precisely.
8222 However, for that to be useful we would need to
8223 add some machine description changes which would
8224 make sure small constants ended up in rs1 of the
8225 multiply instruction. This is because the multiply
8226 latency is determined by the number of clear (or
8227 set if the value is negative) bits starting from
8228 the most significant bit of the first input.
8230 The algorithm for computing num_cycles of a multiply
8234 highest_bit = highest_clear_bit(rs1);
8236 highest_bit = highest_set_bit(rs1);
8239 num_cycles = 4 + ((highest_bit - 3) / 2);
8241 If we did that we would have to also consider register
8242 allocation issues that would result from forcing such
8243 a value into a register.
8245 There are other similar tricks we could play if we
8246 knew, for example, that one input was an array index.
8248 Since we do not play any such tricks currently the
8249 safest thing to do is report the worst case latency. */
8250 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8251 return (GET_MODE (x) == DImode ?
8252 COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8254 /* Multiply latency on Ultra-III, fortunately, is constant. */
8255 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8256 return COSTS_N_INSNS (6);
8258 if (sparc_cpu == PROCESSOR_HYPERSPARC
8259 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8260 return COSTS_N_INSNS (17);
8262 return (TARGET_HARD_MUL
8264 : COSTS_N_INSNS (25));
8270 if (FLOAT_MODE_P (GET_MODE (x)))
8274 case PROCESSOR_ULTRASPARC:
8275 if (GET_MODE (x) == SFmode)
8276 return COSTS_N_INSNS (13);
8278 return COSTS_N_INSNS (23);
8280 case PROCESSOR_ULTRASPARC3:
8281 if (GET_MODE (x) == SFmode)
8282 return COSTS_N_INSNS (17);
8284 return COSTS_N_INSNS (20);
8286 case PROCESSOR_SUPERSPARC:
8287 if (GET_MODE (x) == SFmode)
8288 return COSTS_N_INSNS (6);
8290 return COSTS_N_INSNS (9);
8292 case PROCESSOR_HYPERSPARC:
8293 case PROCESSOR_SPARCLITE86X:
8294 if (GET_MODE (x) == SFmode)
8295 return COSTS_N_INSNS (8);
8297 return COSTS_N_INSNS (12);
8300 return COSTS_N_INSNS (7);
8304 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8305 return (GET_MODE (x) == DImode ?
8306 COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8307 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8308 return (GET_MODE (x) == DImode ?
8309 COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8310 return COSTS_N_INSNS (25);
8313 /* Conditional moves. */
8316 case PROCESSOR_ULTRASPARC:
8317 return COSTS_N_INSNS (2);
8319 case PROCESSOR_ULTRASPARC3:
8320 if (FLOAT_MODE_P (GET_MODE (x)))
8321 return COSTS_N_INSNS (3);
8323 return COSTS_N_INSNS (2);
8326 return COSTS_N_INSNS (1);
8330 /* If outer-code is SIGN/ZERO extension we have to subtract
8331 out COSTS_N_INSNS (1) from whatever we return in determining
8335 case PROCESSOR_ULTRASPARC:
8336 if (outer_code == ZERO_EXTEND)
8337 return COSTS_N_INSNS (1);
8339 return COSTS_N_INSNS (2);
8341 case PROCESSOR_ULTRASPARC3:
8342 if (outer_code == ZERO_EXTEND)
8344 if (GET_MODE (x) == QImode
8345 || GET_MODE (x) == HImode
8346 || outer_code == SIGN_EXTEND)
8347 return COSTS_N_INSNS (2);
8349 return COSTS_N_INSNS (1);
8353 /* This handles sign extension (3 cycles)
8354 and everything else (2 cycles). */
8355 return COSTS_N_INSNS (2);
8358 case PROCESSOR_SUPERSPARC:
8359 if (FLOAT_MODE_P (GET_MODE (x))
8360 || outer_code == ZERO_EXTEND
8361 || outer_code == SIGN_EXTEND)
8362 return COSTS_N_INSNS (0);
8364 return COSTS_N_INSNS (1);
8366 case PROCESSOR_TSC701:
8367 if (outer_code == ZERO_EXTEND
8368 || outer_code == SIGN_EXTEND)
8369 return COSTS_N_INSNS (2);
8371 return COSTS_N_INSNS (3);
8373 case PROCESSOR_CYPRESS:
8374 if (outer_code == ZERO_EXTEND
8375 || outer_code == SIGN_EXTEND)
8376 return COSTS_N_INSNS (1);
8378 return COSTS_N_INSNS (2);
8380 case PROCESSOR_HYPERSPARC:
8381 case PROCESSOR_SPARCLITE86X:
8383 if (outer_code == ZERO_EXTEND
8384 || outer_code == SIGN_EXTEND)
8385 return COSTS_N_INSNS (0);
8387 return COSTS_N_INSNS (1);
8391 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8404 if (GET_MODE (x) == DImode)
8405 if ((XINT (x, 3) == 0
8406 && (unsigned) XINT (x, 2) < 0x1000)
8407 || (XINT (x, 3) == -1
8409 && XINT (x, 2) >= -0x1000))