1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
47 #include "target-def.h"
49 /* 1 if the caller has placed an "unimp" insn immediately after the call.
50 This is used in v8 code when calling a function that returns a structure.
51 v9 doesn't have this. Be careful to have this test be the same as that
54 #define SKIP_CALLERS_UNIMP_P \
55 (!TARGET_ARCH64 && current_function_returns_struct \
56 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
57 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
60 /* Global variables for machine-dependent things. */
62 /* Size of frame. Need to know this to emit return insns from leaf procedures.
63 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
64 reload pass. This is important as the value is later used in insn
65 scheduling (to see what can go in a delay slot).
66 APPARENT_FSIZE is the size of the stack less the register save area and less
67 the outgoing argument area. It is used when saving call preserved regs. */
68 static int apparent_fsize;
69 static int actual_fsize;
71 /* Number of live general or floating point registers needed to be
72 saved (as 4-byte quantities). */
73 static int num_gfregs;
75 /* Save the operands last given to a compare for use when we
76 generate a scc or bcc insn. */
77 rtx sparc_compare_op0, sparc_compare_op1;
79 /* Coordinate with the md file wrt special insns created by
80 sparc_nonflat_function_epilogue. */
81 bool sparc_emitting_epilogue;
83 /* Vector to say how input registers are mapped to output registers.
84 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
85 eliminate it. You must use -fomit-frame-pointer to get that. */
86 char leaf_reg_remap[] =
87 { 0, 1, 2, 3, 4, 5, 6, 7,
88 -1, -1, -1, -1, -1, -1, 14, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1,
90 8, 9, 10, 11, 12, 13, -1, 15,
92 32, 33, 34, 35, 36, 37, 38, 39,
93 40, 41, 42, 43, 44, 45, 46, 47,
94 48, 49, 50, 51, 52, 53, 54, 55,
95 56, 57, 58, 59, 60, 61, 62, 63,
96 64, 65, 66, 67, 68, 69, 70, 71,
97 72, 73, 74, 75, 76, 77, 78, 79,
98 80, 81, 82, 83, 84, 85, 86, 87,
99 88, 89, 90, 91, 92, 93, 94, 95,
100 96, 97, 98, 99, 100};
102 /* Vector, indexed by hard register number, which contains 1
103 for a register that is allowable in a candidate for leaf
104 function treatment. */
105 char sparc_leaf_regs[] =
106 { 1, 1, 1, 1, 1, 1, 1, 1,
107 0, 0, 0, 0, 0, 0, 1, 0,
108 0, 0, 0, 0, 0, 0, 0, 0,
109 1, 1, 1, 1, 1, 1, 0, 1,
110 1, 1, 1, 1, 1, 1, 1, 1,
111 1, 1, 1, 1, 1, 1, 1, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
120 /* Name of where we pretend to think the frame pointer points.
121 Normally, this is "%fp", but if we are in a leaf procedure,
122 this is "%sp+something". We record "something" separately as it may be
123 too big for reg+constant addressing. */
125 static const char *frame_base_name;
126 static int frame_base_offset;
128 static void sparc_init_modes PARAMS ((void));
129 static int save_regs PARAMS ((FILE *, int, int, const char *,
131 static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int));
132 static void build_big_number PARAMS ((FILE *, int, const char *));
133 static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *,
134 enum machine_mode, tree, int, int,
137 static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
138 static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
140 static void sparc_output_addr_vec PARAMS ((rtx));
141 static void sparc_output_addr_diff_vec PARAMS ((rtx));
142 static void sparc_output_deferred_case_vectors PARAMS ((void));
143 static void sparc_add_gc_roots PARAMS ((void));
144 static int check_return_regs PARAMS ((rtx));
145 static int epilogue_renumber PARAMS ((rtx *, int));
146 static bool sparc_assemble_integer PARAMS ((rtx, unsigned int, int));
147 static int set_extends PARAMS ((rtx));
148 static void output_restore_regs PARAMS ((FILE *, int));
149 static void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
150 static void sparc_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
151 static void sparc_flat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
152 static void sparc_flat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
153 static void sparc_nonflat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT,
155 static void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT,
157 #ifdef OBJECT_FORMAT_ELF
158 static void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int));
161 static int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
162 static int sparc_issue_rate PARAMS ((void));
163 static void sparc_sched_init PARAMS ((FILE *, int, int));
164 static int sparc_use_dfa_pipeline_interface PARAMS ((void));
165 static int sparc_use_sched_lookahead PARAMS ((void));
167 static void emit_soft_tfmode_libcall PARAMS ((const char *, int, rtx *));
168 static void emit_soft_tfmode_binop PARAMS ((enum rtx_code, rtx *));
169 static void emit_soft_tfmode_unop PARAMS ((enum rtx_code, rtx *));
170 static void emit_soft_tfmode_cvt PARAMS ((enum rtx_code, rtx *));
171 static void emit_hard_tfmode_operation PARAMS ((enum rtx_code, rtx *));
173 /* Option handling. */
175 /* Code model option as passed by user. */
176 const char *sparc_cmodel_string;
178 enum cmodel sparc_cmodel;
180 char sparc_hard_reg_printed[8];
182 struct sparc_cpu_select sparc_select[] =
184 /* switch name, tune arch */
185 { (char *)0, "default", 1, 1 },
186 { (char *)0, "-mcpu=", 1, 1 },
187 { (char *)0, "-mtune=", 1, 0 },
191 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
192 enum processor_type sparc_cpu;
194 /* Initialize the GCC target structure. */
196 /* The sparc default is to use .half rather than .short for aligned
197 HI objects. Use .word instead of .long on non-ELF systems. */
198 #undef TARGET_ASM_ALIGNED_HI_OP
199 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
200 #ifndef OBJECT_FORMAT_ELF
201 #undef TARGET_ASM_ALIGNED_SI_OP
202 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
205 #undef TARGET_ASM_UNALIGNED_HI_OP
206 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
207 #undef TARGET_ASM_UNALIGNED_SI_OP
208 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
209 #undef TARGET_ASM_UNALIGNED_DI_OP
210 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
212 /* The target hook has to handle DI-mode values. */
213 #undef TARGET_ASM_INTEGER
214 #define TARGET_ASM_INTEGER sparc_assemble_integer
216 #undef TARGET_ASM_FUNCTION_PROLOGUE
217 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
218 #undef TARGET_ASM_FUNCTION_EPILOGUE
219 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
221 #undef TARGET_SCHED_ADJUST_COST
222 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
223 #undef TARGET_SCHED_ISSUE_RATE
224 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
225 #undef TARGET_SCHED_INIT
226 #define TARGET_SCHED_INIT sparc_sched_init
227 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
228 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
229 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
230 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
232 struct gcc_target targetm = TARGET_INITIALIZER;
234 /* Validate and override various options, and do some machine dependent
238 sparc_override_options ()
240 static struct code_model {
241 const char *const name;
243 } const cmodels[] = {
245 { "medlow", CM_MEDLOW },
246 { "medmid", CM_MEDMID },
247 { "medany", CM_MEDANY },
248 { "embmedany", CM_EMBMEDANY },
251 const struct code_model *cmodel;
252 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
253 static struct cpu_default {
255 const char *const name;
256 } const cpu_default[] = {
257 /* There must be one entry here for each TARGET_CPU value. */
258 { TARGET_CPU_sparc, "cypress" },
259 { TARGET_CPU_sparclet, "tsc701" },
260 { TARGET_CPU_sparclite, "f930" },
261 { TARGET_CPU_v8, "v8" },
262 { TARGET_CPU_hypersparc, "hypersparc" },
263 { TARGET_CPU_sparclite86x, "sparclite86x" },
264 { TARGET_CPU_supersparc, "supersparc" },
265 { TARGET_CPU_v9, "v9" },
266 { TARGET_CPU_ultrasparc, "ultrasparc" },
267 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
270 const struct cpu_default *def;
271 /* Table of values for -m{cpu,tune}=. */
272 static struct cpu_table {
273 const char *const name;
274 const enum processor_type processor;
277 } const cpu_table[] = {
278 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
279 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
280 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
281 /* TI TMS390Z55 supersparc */
282 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
283 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
284 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
285 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
286 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
287 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
288 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
289 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
291 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
293 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
294 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
295 /* TI ultrasparc I, II, IIi */
296 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
297 /* Although insns using %y are deprecated, it is a clear win on current
299 |MASK_DEPRECATED_V8_INSNS},
300 /* TI ultrasparc III */
301 /* ??? Check if %y issue still holds true in ultra3. */
302 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
305 const struct cpu_table *cpu;
306 const struct sparc_cpu_select *sel;
309 #ifndef SPARC_BI_ARCH
310 /* Check for unsupported architecture size. */
311 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
312 error ("%s is not supported by this configuration",
313 DEFAULT_ARCH32_P ? "-m64" : "-m32");
316 /* We force all 64bit archs to use 128 bit long double */
317 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
319 error ("-mlong-double-64 not allowed with -m64");
320 target_flags |= MASK_LONG_DOUBLE_128;
323 /* Code model selection. */
324 sparc_cmodel = SPARC_DEFAULT_CMODEL;
328 sparc_cmodel = CM_32;
331 if (sparc_cmodel_string != NULL)
335 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
336 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
338 if (cmodel->name == NULL)
339 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
341 sparc_cmodel = cmodel->value;
344 error ("-mcmodel= is not supported on 32 bit systems");
347 fpu = TARGET_FPU; /* save current -mfpu status */
349 /* Set the default CPU. */
350 for (def = &cpu_default[0]; def->name; ++def)
351 if (def->cpu == TARGET_CPU_DEFAULT)
355 sparc_select[0].string = def->name;
357 for (sel = &sparc_select[0]; sel->name; ++sel)
361 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
362 if (! strcmp (sel->string, cpu->name))
365 sparc_cpu = cpu->processor;
369 target_flags &= ~cpu->disable;
370 target_flags |= cpu->enable;
376 error ("bad value (%s) for %s switch", sel->string, sel->name);
380 /* If -mfpu or -mno-fpu was explicitly used, don't override with
381 the processor default. Clear MASK_FPU_SET to avoid confusing
382 the reverse mapping from switch values to names. */
385 target_flags = (target_flags & ~MASK_FPU) | fpu;
386 target_flags &= ~MASK_FPU_SET;
389 /* Don't allow -mvis if FPU is disabled. */
391 target_flags &= ~MASK_VIS;
393 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
395 -m64 also implies v9. */
396 if (TARGET_VIS || TARGET_ARCH64)
398 target_flags |= MASK_V9;
399 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
402 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
403 if (TARGET_V9 && TARGET_ARCH32)
404 target_flags |= MASK_DEPRECATED_V8_INSNS;
406 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
407 if (! TARGET_V9 || TARGET_ARCH64)
408 target_flags &= ~MASK_V8PLUS;
410 /* Don't use stack biasing in 32 bit mode. */
412 target_flags &= ~MASK_STACK_BIAS;
414 /* Supply a default value for align_functions. */
415 if (align_functions == 0
416 && (sparc_cpu == PROCESSOR_ULTRASPARC
417 || sparc_cpu == PROCESSOR_ULTRASPARC3))
418 align_functions = 32;
420 /* Validate PCC_STRUCT_RETURN. */
421 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
422 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
424 /* Only use .uaxword when compiling for a 64-bit target. */
426 targetm.asm_out.unaligned_op.di = NULL;
428 /* Do various machine dependent initializations. */
431 /* Register global variables with the garbage collector. */
432 sparc_add_gc_roots ();
435 /* Miscellaneous utilities. */
437 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
438 or branch on register contents instructions. */
444 return (code == EQ || code == NE || code == GE || code == LT
445 || code == LE || code == GT);
449 /* Operand constraints. */
451 /* Return non-zero only if OP is a register of mode MODE,
455 reg_or_0_operand (op, mode)
457 enum machine_mode mode;
459 if (register_operand (op, mode))
461 if (op == const0_rtx)
463 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
464 && CONST_DOUBLE_HIGH (op) == 0
465 && CONST_DOUBLE_LOW (op) == 0)
467 if (fp_zero_operand (op, mode))
472 /* Return non-zero only if OP is const1_rtx. */
475 const1_operand (op, mode)
477 enum machine_mode mode ATTRIBUTE_UNUSED;
479 return op == const1_rtx;
482 /* Nonzero if OP is a floating point value with value 0.0. */
485 fp_zero_operand (op, mode)
487 enum machine_mode mode;
489 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
491 return op == CONST0_RTX (mode);
494 /* Nonzero if OP is a register operand in floating point register. */
497 fp_register_operand (op, mode)
499 enum machine_mode mode;
501 if (! register_operand (op, mode))
503 if (GET_CODE (op) == SUBREG)
504 op = SUBREG_REG (op);
505 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
508 /* Nonzero if OP is a floating point constant which can
509 be loaded into an integer register using a single
510 sethi instruction. */
516 if (GET_CODE (op) == CONST_DOUBLE)
521 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
522 if (REAL_VALUES_EQUAL (r, dconst0) &&
523 ! REAL_VALUE_MINUS_ZERO (r))
525 REAL_VALUE_TO_TARGET_SINGLE (r, i);
526 if (SPARC_SETHI_P (i))
533 /* Nonzero if OP is a floating point constant which can
534 be loaded into an integer register using a single
541 if (GET_CODE (op) == CONST_DOUBLE)
546 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
547 if (REAL_VALUES_EQUAL (r, dconst0) &&
548 ! REAL_VALUE_MINUS_ZERO (r))
550 REAL_VALUE_TO_TARGET_SINGLE (r, i);
551 if (SPARC_SIMM13_P (i))
558 /* Nonzero if OP is a floating point constant which can
559 be loaded into an integer register using a high/losum
560 instruction sequence. */
566 /* The constraints calling this should only be in
567 SFmode move insns, so any constant which cannot
568 be moved using a single insn will do. */
569 if (GET_CODE (op) == CONST_DOUBLE)
574 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
575 if (REAL_VALUES_EQUAL (r, dconst0) &&
576 ! REAL_VALUE_MINUS_ZERO (r))
578 REAL_VALUE_TO_TARGET_SINGLE (r, i);
579 if (! SPARC_SETHI_P (i)
580 && ! SPARC_SIMM13_P (i))
587 /* Nonzero if OP is an integer register. */
590 intreg_operand (op, mode)
592 enum machine_mode mode ATTRIBUTE_UNUSED;
594 return (register_operand (op, SImode)
595 || (TARGET_ARCH64 && register_operand (op, DImode)));
598 /* Nonzero if OP is a floating point condition code register. */
601 fcc_reg_operand (op, mode)
603 enum machine_mode mode;
605 /* This can happen when recog is called from combine. Op may be a MEM.
606 Fail instead of calling abort in this case. */
607 if (GET_CODE (op) != REG)
610 if (mode != VOIDmode && mode != GET_MODE (op))
613 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
616 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
617 if (reg_renumber == 0)
618 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
619 return REGNO_OK_FOR_CCFP_P (REGNO (op));
621 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
625 /* Nonzero if OP is a floating point condition code fcc0 register. */
628 fcc0_reg_operand (op, mode)
630 enum machine_mode mode;
632 /* This can happen when recog is called from combine. Op may be a MEM.
633 Fail instead of calling abort in this case. */
634 if (GET_CODE (op) != REG)
637 if (mode != VOIDmode && mode != GET_MODE (op))
640 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
643 return REGNO (op) == SPARC_FCC_REG;
646 /* Nonzero if OP is an integer or floating point condition code register. */
649 icc_or_fcc_reg_operand (op, mode)
651 enum machine_mode mode;
653 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
655 if (mode != VOIDmode && mode != GET_MODE (op))
658 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
663 return fcc_reg_operand (op, mode);
666 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
668 restore_operand (op, mode)
670 enum machine_mode mode;
672 return (GET_CODE (op) == REG && GET_MODE (op) == mode
673 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
676 /* Call insn on SPARC can take a PC-relative constant address, or any regular
680 call_operand (op, mode)
682 enum machine_mode mode;
684 if (GET_CODE (op) != MEM)
687 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
691 call_operand_address (op, mode)
693 enum machine_mode mode;
695 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
698 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
699 reference and a constant. */
702 symbolic_operand (op, mode)
704 enum machine_mode mode;
706 enum machine_mode omode = GET_MODE (op);
708 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
711 switch (GET_CODE (op))
719 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
720 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
721 && GET_CODE (XEXP (op, 1)) == CONST_INT);
728 /* Return truth value of statement that OP is a symbolic memory
729 operand of mode MODE. */
732 symbolic_memory_operand (op, mode)
734 enum machine_mode mode ATTRIBUTE_UNUSED;
736 if (GET_CODE (op) == SUBREG)
737 op = SUBREG_REG (op);
738 if (GET_CODE (op) != MEM)
741 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
742 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
745 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
748 label_ref_operand (op, mode)
750 enum machine_mode mode;
752 if (GET_CODE (op) != LABEL_REF)
754 if (GET_MODE (op) != mode)
759 /* Return 1 if the operand is an argument used in generating pic references
760 in either the medium/low or medium/anywhere code models of sparc64. */
763 sp64_medium_pic_operand (op, mode)
765 enum machine_mode mode ATTRIBUTE_UNUSED;
767 /* Check for (const (minus (symbol_ref:GOT)
768 (const (minus (label) (pc))))). */
769 if (GET_CODE (op) != CONST)
772 if (GET_CODE (op) != MINUS)
774 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
776 /* ??? Ensure symbol is GOT. */
777 if (GET_CODE (XEXP (op, 1)) != CONST)
779 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
784 /* Return 1 if the operand is a data segment reference. This includes
785 the readonly data segment, or in other words anything but the text segment.
786 This is needed in the medium/anywhere code model on v9. These values
787 are accessed with EMBMEDANY_BASE_REG. */
790 data_segment_operand (op, mode)
792 enum machine_mode mode ATTRIBUTE_UNUSED;
794 switch (GET_CODE (op))
797 return ! SYMBOL_REF_FLAG (op);
799 /* Assume canonical format of symbol + constant.
802 return data_segment_operand (XEXP (op, 0), VOIDmode);
808 /* Return 1 if the operand is a text segment reference.
809 This is needed in the medium/anywhere code model on v9. */
812 text_segment_operand (op, mode)
814 enum machine_mode mode ATTRIBUTE_UNUSED;
816 switch (GET_CODE (op))
821 return SYMBOL_REF_FLAG (op);
823 /* Assume canonical format of symbol + constant.
826 return text_segment_operand (XEXP (op, 0), VOIDmode);
832 /* Return 1 if the operand is either a register or a memory operand that is
836 reg_or_nonsymb_mem_operand (op, mode)
838 enum machine_mode mode;
840 if (register_operand (op, mode))
843 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
850 splittable_symbolic_memory_operand (op, mode)
852 enum machine_mode mode ATTRIBUTE_UNUSED;
854 if (GET_CODE (op) != MEM)
856 if (! symbolic_operand (XEXP (op, 0), Pmode))
862 splittable_immediate_memory_operand (op, mode)
864 enum machine_mode mode ATTRIBUTE_UNUSED;
866 if (GET_CODE (op) != MEM)
868 if (! immediate_operand (XEXP (op, 0), Pmode))
873 /* Return truth value of whether OP is EQ or NE. */
878 enum machine_mode mode ATTRIBUTE_UNUSED;
880 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
883 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
884 or LTU for non-floating-point. We handle those specially. */
887 normal_comp_operator (op, mode)
889 enum machine_mode mode ATTRIBUTE_UNUSED;
891 enum rtx_code code = GET_CODE (op);
893 if (GET_RTX_CLASS (code) != '<')
896 if (GET_MODE (XEXP (op, 0)) == CCFPmode
897 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
900 return (code != NE && code != EQ && code != GEU && code != LTU);
903 /* Return 1 if this is a comparison operator. This allows the use of
904 MATCH_OPERATOR to recognize all the branch insns. */
907 noov_compare_op (op, mode)
909 enum machine_mode mode ATTRIBUTE_UNUSED;
911 enum rtx_code code = GET_CODE (op);
913 if (GET_RTX_CLASS (code) != '<')
916 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
917 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
918 /* These are the only branches which work with CC_NOOVmode. */
919 return (code == EQ || code == NE || code == GE || code == LT);
923 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
924 MATCH_OPERATOR to recognize all the branch insns. */
927 noov_compare64_op (op, mode)
929 enum machine_mode mode ATTRIBUTE_UNUSED;
931 enum rtx_code code = GET_CODE (op);
936 if (GET_RTX_CLASS (code) != '<')
939 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
940 /* These are the only branches which work with CCX_NOOVmode. */
941 return (code == EQ || code == NE || code == GE || code == LT);
942 return (GET_MODE (XEXP (op, 0)) == CCXmode);
945 /* Nonzero if OP is a comparison operator suitable for use in v9
946 conditional move or branch on register contents instructions. */
949 v9_regcmp_op (op, mode)
951 enum machine_mode mode ATTRIBUTE_UNUSED;
953 enum rtx_code code = GET_CODE (op);
955 if (GET_RTX_CLASS (code) != '<')
958 return v9_regcmp_p (code);
961 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
966 enum machine_mode mode ATTRIBUTE_UNUSED;
968 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
971 /* Return nonzero if OP is an operator of mode MODE which can set
972 the condition codes explicitly. We do not include PLUS and MINUS
973 because these require CC_NOOVmode, which we handle explicitly. */
976 cc_arithop (op, mode)
978 enum machine_mode mode ATTRIBUTE_UNUSED;
980 if (GET_CODE (op) == AND
981 || GET_CODE (op) == IOR
982 || GET_CODE (op) == XOR)
988 /* Return nonzero if OP is an operator of mode MODE which can bitwise
989 complement its second operand and set the condition codes explicitly. */
992 cc_arithopn (op, mode)
994 enum machine_mode mode ATTRIBUTE_UNUSED;
996 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
997 and (xor ... (not ...)) to (not (xor ...)). */
998 return (GET_CODE (op) == AND
999 || GET_CODE (op) == IOR);
1002 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1003 signed 13 bit immediate field. This is an acceptable SImode operand for
1004 most 3 address instructions. */
1007 arith_operand (op, mode)
1009 enum machine_mode mode;
1011 if (register_operand (op, mode))
1013 if (GET_CODE (op) != CONST_INT)
1015 return SMALL_INT32 (op);
1018 /* Return true if OP is a constant 4096 */
1021 arith_4096_operand (op, mode)
1023 enum machine_mode mode ATTRIBUTE_UNUSED;
1025 if (GET_CODE (op) != CONST_INT)
1028 return INTVAL (op) == 4096;
1031 /* Return true if OP is suitable as second operand for add/sub */
1034 arith_add_operand (op, mode)
1036 enum machine_mode mode;
1038 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1041 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1042 immediate field of OR and XOR instructions. Used for 64-bit
1043 constant formation patterns. */
1045 const64_operand (op, mode)
1047 enum machine_mode mode ATTRIBUTE_UNUSED;
1049 return ((GET_CODE (op) == CONST_INT
1050 && SPARC_SIMM13_P (INTVAL (op)))
1051 #if HOST_BITS_PER_WIDE_INT != 64
1052 || (GET_CODE (op) == CONST_DOUBLE
1053 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1054 && (CONST_DOUBLE_HIGH (op) ==
1055 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1056 (HOST_WIDE_INT)-1 : 0)))
1061 /* The same, but only for sethi instructions. */
1063 const64_high_operand (op, mode)
1065 enum machine_mode mode;
1067 return ((GET_CODE (op) == CONST_INT
1068 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1069 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1071 || (GET_CODE (op) == CONST_DOUBLE
1072 && CONST_DOUBLE_HIGH (op) == 0
1073 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1074 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1077 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1078 signed 11 bit immediate field. This is an acceptable SImode operand for
1079 the movcc instructions. */
1082 arith11_operand (op, mode)
1084 enum machine_mode mode;
1086 return (register_operand (op, mode)
1087 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1090 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1091 signed 10 bit immediate field. This is an acceptable SImode operand for
1092 the movrcc instructions. */
1095 arith10_operand (op, mode)
1097 enum machine_mode mode;
1099 return (register_operand (op, mode)
1100 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1103 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1104 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1106 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1107 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1108 for most 3 address instructions. */
1111 arith_double_operand (op, mode)
1113 enum machine_mode mode;
1115 return (register_operand (op, mode)
1116 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1118 && GET_CODE (op) == CONST_DOUBLE
1119 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1120 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1122 && GET_CODE (op) == CONST_DOUBLE
1123 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1124 && ((CONST_DOUBLE_HIGH (op) == -1
1125 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1126 || (CONST_DOUBLE_HIGH (op) == 0
1127 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1130 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1133 arith_double_4096_operand (op, mode)
1135 enum machine_mode mode ATTRIBUTE_UNUSED;
1137 return (TARGET_ARCH64 &&
1138 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1139 (GET_CODE (op) == CONST_DOUBLE &&
1140 CONST_DOUBLE_LOW (op) == 4096 &&
1141 CONST_DOUBLE_HIGH (op) == 0)));
1144 /* Return true if OP is suitable as second operand for add/sub in DImode */
1147 arith_double_add_operand (op, mode)
1149 enum machine_mode mode;
1151 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1154 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1155 can fit in an 11 bit immediate field. This is an acceptable DImode
1156 operand for the movcc instructions. */
1157 /* ??? Replace with arith11_operand? */
1160 arith11_double_operand (op, mode)
1162 enum machine_mode mode;
1164 return (register_operand (op, mode)
1165 || (GET_CODE (op) == CONST_DOUBLE
1166 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1167 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1168 && ((CONST_DOUBLE_HIGH (op) == -1
1169 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1170 || (CONST_DOUBLE_HIGH (op) == 0
1171 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1172 || (GET_CODE (op) == CONST_INT
1173 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1174 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1177 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1178 can fit in an 10 bit immediate field. This is an acceptable DImode
1179 operand for the movrcc instructions. */
1180 /* ??? Replace with arith10_operand? */
1183 arith10_double_operand (op, mode)
1185 enum machine_mode mode;
1187 return (register_operand (op, mode)
1188 || (GET_CODE (op) == CONST_DOUBLE
1189 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1190 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1191 && ((CONST_DOUBLE_HIGH (op) == -1
1192 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1193 || (CONST_DOUBLE_HIGH (op) == 0
1194 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1195 || (GET_CODE (op) == CONST_INT
1196 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1197 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1200 /* Return truth value of whether OP is an integer which fits the
1201 range constraining immediate operands in most three-address insns,
1202 which have a 13 bit immediate field. */
1205 small_int (op, mode)
1207 enum machine_mode mode ATTRIBUTE_UNUSED;
1209 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1213 small_int_or_double (op, mode)
1215 enum machine_mode mode ATTRIBUTE_UNUSED;
1217 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1218 || (GET_CODE (op) == CONST_DOUBLE
1219 && CONST_DOUBLE_HIGH (op) == 0
1220 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1223 /* Recognize operand values for the umul instruction. That instruction sign
1224 extends immediate values just like all other sparc instructions, but
1225 interprets the extended result as an unsigned number. */
1228 uns_small_int (op, mode)
1230 enum machine_mode mode ATTRIBUTE_UNUSED;
1232 #if HOST_BITS_PER_WIDE_INT > 32
1233 /* All allowed constants will fit a CONST_INT. */
1234 return (GET_CODE (op) == CONST_INT
1235 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1236 || (INTVAL (op) >= 0xFFFFF000
1237 && INTVAL (op) <= 0xFFFFFFFF)));
1239 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1240 || (GET_CODE (op) == CONST_DOUBLE
1241 && CONST_DOUBLE_HIGH (op) == 0
1242 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1247 uns_arith_operand (op, mode)
1249 enum machine_mode mode;
1251 return register_operand (op, mode) || uns_small_int (op, mode);
1254 /* Return truth value of statement that OP is a call-clobbered register. */
1256 clobbered_register (op, mode)
1258 enum machine_mode mode ATTRIBUTE_UNUSED;
1260 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1263 /* Return 1 if OP is a valid operand for the source of a move insn. */
1266 input_operand (op, mode)
1268 enum machine_mode mode;
1270 /* If both modes are non-void they must be the same. */
1271 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1274 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1275 if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX)
1278 /* Allow any one instruction integer constant, and all CONST_INT
1279 variants when we are working in DImode and !arch64. */
1280 if (GET_MODE_CLASS (mode) == MODE_INT
1281 && ((GET_CODE (op) == CONST_INT
1282 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1283 || SPARC_SIMM13_P (INTVAL (op))
1285 && ! TARGET_ARCH64)))
1287 && GET_CODE (op) == CONST_DOUBLE
1288 && ((CONST_DOUBLE_HIGH (op) == 0
1289 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1291 #if HOST_BITS_PER_WIDE_INT == 64
1292 (CONST_DOUBLE_HIGH (op) == 0
1293 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1295 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1296 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1297 && CONST_DOUBLE_HIGH (op) == 0)
1298 || (CONST_DOUBLE_HIGH (op) == -1
1299 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1304 /* If !arch64 and this is a DImode const, allow it so that
1305 the splits can be generated. */
1308 && GET_CODE (op) == CONST_DOUBLE)
1311 if (register_operand (op, mode))
1314 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1315 && GET_CODE (op) == CONST_DOUBLE)
1318 /* If this is a SUBREG, look inside so that we handle
1319 paradoxical ones. */
1320 if (GET_CODE (op) == SUBREG)
1321 op = SUBREG_REG (op);
1323 /* Check for valid MEM forms. */
1324 if (GET_CODE (op) == MEM)
1326 rtx inside = XEXP (op, 0);
1328 if (GET_CODE (inside) == LO_SUM)
1330 /* We can't allow these because all of the splits
1331 (eventually as they trickle down into DFmode
1332 splits) require offsettable memory references. */
1334 && GET_MODE (op) == TFmode)
1337 return (register_operand (XEXP (inside, 0), Pmode)
1338 && CONSTANT_P (XEXP (inside, 1)));
1340 return memory_address_p (mode, inside);
1347 /* We know it can't be done in one insn when we get here,
1348 the movsi expander guarentees this. */
1350 sparc_emit_set_const32 (op0, op1)
1354 enum machine_mode mode = GET_MODE (op0);
1357 if (GET_CODE (op1) == CONST_INT)
1359 HOST_WIDE_INT value = INTVAL (op1);
1361 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1362 || SPARC_SIMM13_P (value))
1366 /* Full 2-insn decomposition is needed. */
1367 if (reload_in_progress || reload_completed)
1370 temp = gen_reg_rtx (mode);
1372 if (GET_CODE (op1) == CONST_INT)
1374 /* Emit them as real moves instead of a HIGH/LO_SUM,
1375 this way CSE can see everything and reuse intermediate
1376 values if it wants. */
1378 && HOST_BITS_PER_WIDE_INT != 64
1379 && (INTVAL (op1) & 0x80000000) != 0)
1380 emit_insn (gen_rtx_SET
1382 gen_rtx_CONST_DOUBLE (VOIDmode,
1383 INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1386 emit_insn (gen_rtx_SET (VOIDmode, temp,
1387 GEN_INT (INTVAL (op1)
1388 & ~(HOST_WIDE_INT)0x3ff)));
1390 emit_insn (gen_rtx_SET (VOIDmode,
1392 gen_rtx_IOR (mode, temp,
1393 GEN_INT (INTVAL (op1) & 0x3ff))));
1397 /* A symbol, emit in the traditional way. */
1398 emit_insn (gen_rtx_SET (VOIDmode, temp,
1399 gen_rtx_HIGH (mode, op1)));
1400 emit_insn (gen_rtx_SET (VOIDmode,
1401 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1407 /* Sparc-v9 code-model support. */
1409 sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1416 if (temp1 && GET_MODE (temp1) == TImode)
1419 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1422 switch (sparc_cmodel)
1425 /* The range spanned by all instructions in the object is less
1426 than 2^31 bytes (2GB) and the distance from any instruction
1427 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1428 than 2^31 bytes (2GB).
1430 The executable must be in the low 4TB of the virtual address
1433 sethi %hi(symbol), %temp
1434 or %temp, %lo(symbol), %reg */
1435 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1436 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1440 /* The range spanned by all instructions in the object is less
1441 than 2^31 bytes (2GB) and the distance from any instruction
1442 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1443 than 2^31 bytes (2GB).
1445 The executable must be in the low 16TB of the virtual address
1448 sethi %h44(symbol), %temp1
1449 or %temp1, %m44(symbol), %temp2
1450 sllx %temp2, 12, %temp3
1451 or %temp3, %l44(symbol), %reg */
1452 emit_insn (gen_seth44 (op0, op1));
1453 emit_insn (gen_setm44 (op0, op0, op1));
1454 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1455 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1456 emit_insn (gen_setl44 (op0, temp1, op1));
1460 /* The range spanned by all instructions in the object is less
1461 than 2^31 bytes (2GB) and the distance from any instruction
1462 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1463 than 2^31 bytes (2GB).
1465 The executable can be placed anywhere in the virtual address
1468 sethi %hh(symbol), %temp1
1469 sethi %lm(symbol), %temp2
1470 or %temp1, %hm(symbol), %temp3
1471 or %temp2, %lo(symbol), %temp4
1472 sllx %temp3, 32, %temp5
1473 or %temp4, %temp5, %reg */
1475 /* It is possible that one of the registers we got for operands[2]
1476 might coincide with that of operands[0] (which is why we made
1477 it TImode). Pick the other one to use as our scratch. */
1478 if (rtx_equal_p (temp1, op0))
1481 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1486 emit_insn (gen_sethh (op0, op1));
1487 emit_insn (gen_setlm (temp1, op1));
1488 emit_insn (gen_sethm (op0, op0, op1));
1489 emit_insn (gen_rtx_SET (VOIDmode, op0,
1490 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1491 emit_insn (gen_rtx_SET (VOIDmode, op0,
1492 gen_rtx_PLUS (DImode, op0, temp1)));
1493 emit_insn (gen_setlo (op0, op0, op1));
1497 /* Old old old backwards compatibility kruft here.
1498 Essentially it is MEDLOW with a fixed 64-bit
1499 virtual base added to all data segment addresses.
1500 Text-segment stuff is computed like MEDANY, we can't
1501 reuse the code above because the relocation knobs
1504 Data segment: sethi %hi(symbol), %temp1
1505 or %temp1, %lo(symbol), %temp2
1506 add %temp2, EMBMEDANY_BASE_REG, %reg
1508 Text segment: sethi %uhi(symbol), %temp1
1509 sethi %hi(symbol), %temp2
1510 or %temp1, %ulo(symbol), %temp3
1511 or %temp2, %lo(symbol), %temp4
1512 sllx %temp3, 32, %temp5
1513 or %temp4, %temp5, %reg */
1514 if (data_segment_operand (op1, GET_MODE (op1)))
1516 emit_insn (gen_embmedany_sethi (temp1, op1));
1517 emit_insn (gen_embmedany_brsum (op0, temp1));
1518 emit_insn (gen_embmedany_losum (op0, op0, op1));
1522 /* It is possible that one of the registers we got for operands[2]
1523 might coincide with that of operands[0] (which is why we made
1524 it TImode). Pick the other one to use as our scratch. */
1525 if (rtx_equal_p (temp1, op0))
1528 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1533 emit_insn (gen_embmedany_textuhi (op0, op1));
1534 emit_insn (gen_embmedany_texthi (temp1, op1));
1535 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1536 emit_insn (gen_rtx_SET (VOIDmode, op0,
1537 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1538 emit_insn (gen_rtx_SET (VOIDmode, op0,
1539 gen_rtx_PLUS (DImode, op0, temp1)));
1540 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1549 /* These avoid problems when cross compiling. If we do not
1550 go through all this hair then the optimizer will see
1551 invalid REG_EQUAL notes or in some cases none at all. */
1552 static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT));
1553 static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT));
1554 static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT));
1555 static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
1557 #if HOST_BITS_PER_WIDE_INT == 64
1558 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1559 #define GEN_INT64(__x) GEN_INT (__x)
1561 #define GEN_HIGHINT64(__x) \
1562 gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & ~(HOST_WIDE_INT)0x3ff, 0)
1563 #define GEN_INT64(__x) \
1564 gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & 0xffffffff, \
1565 ((__x) & 0x80000000 \
1569 /* The optimizer is not to assume anything about exactly
1570 which bits are set for a HIGH, they are unspecified.
1571 Unfortunately this leads to many missed optimizations
1572 during CSE. We mask out the non-HIGH bits, and matches
1573 a plain movdi, to alleviate this problem. */
1575 sparc_emit_set_safe_HIGH64 (dest, val)
1579 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1583 gen_safe_SET64 (dest, val)
1587 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1591 gen_safe_OR64 (src, val)
1595 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1599 gen_safe_XOR64 (src, val)
1603 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1606 /* Worker routines for 64-bit constant formation on arch64.
1607 One of the key things to be doing in these emissions is
1608 to create as many temp REGs as possible. This makes it
1609 possible for half-built constants to be used later when
1610 such values are similar to something required later on.
1611 Without doing this, the optimizer cannot see such
1614 static void sparc_emit_set_const64_quick1
1615 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int));
1618 sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1621 unsigned HOST_WIDE_INT low_bits;
1624 unsigned HOST_WIDE_INT high_bits;
1627 high_bits = (~low_bits) & 0xffffffff;
1629 high_bits = low_bits;
1631 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1634 emit_insn (gen_rtx_SET (VOIDmode, op0,
1635 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1639 /* If we are XOR'ing with -1, then we should emit a one's complement
1640 instead. This way the combiner will notice logical operations
1641 such as ANDN later on and substitute. */
1642 if ((low_bits & 0x3ff) == 0x3ff)
1644 emit_insn (gen_rtx_SET (VOIDmode, op0,
1645 gen_rtx_NOT (DImode, temp)));
1649 emit_insn (gen_rtx_SET (VOIDmode, op0,
1650 gen_safe_XOR64 (temp,
1651 (-(HOST_WIDE_INT)0x400
1652 | (low_bits & 0x3ff)))));
1657 static void sparc_emit_set_const64_quick2
1658 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT,
1659 unsigned HOST_WIDE_INT, int));
1662 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1665 unsigned HOST_WIDE_INT high_bits;
1666 unsigned HOST_WIDE_INT low_immediate;
1671 if ((high_bits & 0xfffffc00) != 0)
1673 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1674 if ((high_bits & ~0xfffffc00) != 0)
1675 emit_insn (gen_rtx_SET (VOIDmode, op0,
1676 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1682 emit_insn (gen_safe_SET64 (temp, high_bits));
1686 /* Now shift it up into place. */
1687 emit_insn (gen_rtx_SET (VOIDmode, op0,
1688 gen_rtx_ASHIFT (DImode, temp2,
1689 GEN_INT (shift_count))));
1691 /* If there is a low immediate part piece, finish up by
1692 putting that in as well. */
1693 if (low_immediate != 0)
1694 emit_insn (gen_rtx_SET (VOIDmode, op0,
1695 gen_safe_OR64 (op0, low_immediate)));
1698 static void sparc_emit_set_const64_longway
1699 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1701 /* Full 64-bit constant decomposition. Even though this is the
1702 'worst' case, we still optimize a few things away. */
1704 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1707 unsigned HOST_WIDE_INT high_bits;
1708 unsigned HOST_WIDE_INT low_bits;
1712 if (reload_in_progress || reload_completed)
1715 sub_temp = gen_reg_rtx (DImode);
1717 if ((high_bits & 0xfffffc00) != 0)
1719 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1720 if ((high_bits & ~0xfffffc00) != 0)
1721 emit_insn (gen_rtx_SET (VOIDmode,
1723 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1729 emit_insn (gen_safe_SET64 (temp, high_bits));
1733 if (!reload_in_progress && !reload_completed)
1735 rtx temp2 = gen_reg_rtx (DImode);
1736 rtx temp3 = gen_reg_rtx (DImode);
1737 rtx temp4 = gen_reg_rtx (DImode);
1739 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1740 gen_rtx_ASHIFT (DImode, sub_temp,
1743 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1744 if ((low_bits & ~0xfffffc00) != 0)
1746 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1747 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1748 emit_insn (gen_rtx_SET (VOIDmode, op0,
1749 gen_rtx_PLUS (DImode, temp4, temp3)));
1753 emit_insn (gen_rtx_SET (VOIDmode, op0,
1754 gen_rtx_PLUS (DImode, temp4, temp2)));
1759 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1760 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1761 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1764 /* We are in the middle of reload, so this is really
1765 painful. However we do still make an attempt to
1766 avoid emitting truly stupid code. */
1767 if (low1 != const0_rtx)
1769 emit_insn (gen_rtx_SET (VOIDmode, op0,
1770 gen_rtx_ASHIFT (DImode, sub_temp,
1771 GEN_INT (to_shift))));
1772 emit_insn (gen_rtx_SET (VOIDmode, op0,
1773 gen_rtx_IOR (DImode, op0, low1)));
1781 if (low2 != const0_rtx)
1783 emit_insn (gen_rtx_SET (VOIDmode, op0,
1784 gen_rtx_ASHIFT (DImode, sub_temp,
1785 GEN_INT (to_shift))));
1786 emit_insn (gen_rtx_SET (VOIDmode, op0,
1787 gen_rtx_IOR (DImode, op0, low2)));
1795 emit_insn (gen_rtx_SET (VOIDmode, op0,
1796 gen_rtx_ASHIFT (DImode, sub_temp,
1797 GEN_INT (to_shift))));
1798 if (low3 != const0_rtx)
1799 emit_insn (gen_rtx_SET (VOIDmode, op0,
1800 gen_rtx_IOR (DImode, op0, low3)));
1805 /* Analyze a 64-bit constant for certain properties. */
1806 static void analyze_64bit_constant
1807 PARAMS ((unsigned HOST_WIDE_INT,
1808 unsigned HOST_WIDE_INT,
1809 int *, int *, int *));
1812 analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
1813 unsigned HOST_WIDE_INT high_bits, low_bits;
1814 int *hbsp, *lbsp, *abbasp;
1816 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1819 lowest_bit_set = highest_bit_set = -1;
1823 if ((lowest_bit_set == -1)
1824 && ((low_bits >> i) & 1))
1826 if ((highest_bit_set == -1)
1827 && ((high_bits >> (32 - i - 1)) & 1))
1828 highest_bit_set = (64 - i - 1);
1831 && ((highest_bit_set == -1)
1832 || (lowest_bit_set == -1)));
1838 if ((lowest_bit_set == -1)
1839 && ((high_bits >> i) & 1))
1840 lowest_bit_set = i + 32;
1841 if ((highest_bit_set == -1)
1842 && ((low_bits >> (32 - i - 1)) & 1))
1843 highest_bit_set = 32 - i - 1;
1846 && ((highest_bit_set == -1)
1847 || (lowest_bit_set == -1)));
1849 /* If there are no bits set this should have gone out
1850 as one instruction! */
1851 if (lowest_bit_set == -1
1852 || highest_bit_set == -1)
1854 all_bits_between_are_set = 1;
1855 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1859 if ((low_bits & (1 << i)) != 0)
1864 if ((high_bits & (1 << (i - 32))) != 0)
1867 all_bits_between_are_set = 0;
1870 *hbsp = highest_bit_set;
1871 *lbsp = lowest_bit_set;
1872 *abbasp = all_bits_between_are_set;
1875 static int const64_is_2insns
1876 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1879 const64_is_2insns (high_bits, low_bits)
1880 unsigned HOST_WIDE_INT high_bits, low_bits;
1882 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1885 || high_bits == 0xffffffff)
1888 analyze_64bit_constant (high_bits, low_bits,
1889 &highest_bit_set, &lowest_bit_set,
1890 &all_bits_between_are_set);
1892 if ((highest_bit_set == 63
1893 || lowest_bit_set == 0)
1894 && all_bits_between_are_set != 0)
1897 if ((highest_bit_set - lowest_bit_set) < 21)
1903 static unsigned HOST_WIDE_INT create_simple_focus_bits
1904 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
1907 static unsigned HOST_WIDE_INT
1908 create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
1909 unsigned HOST_WIDE_INT high_bits, low_bits;
1910 int lowest_bit_set, shift;
1912 HOST_WIDE_INT hi, lo;
1914 if (lowest_bit_set < 32)
1916 lo = (low_bits >> lowest_bit_set) << shift;
1917 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1922 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1929 /* Here we are sure to be arch64 and this is an integer constant
1930 being loaded into a register. Emit the most efficient
1931 insn sequence possible. Detection of all the 1-insn cases
1932 has been done already. */
1934 sparc_emit_set_const64 (op0, op1)
1938 unsigned HOST_WIDE_INT high_bits, low_bits;
1939 int lowest_bit_set, highest_bit_set;
1940 int all_bits_between_are_set;
1943 /* Sanity check that we know what we are working with. */
1944 if (! TARGET_ARCH64)
1947 if (GET_CODE (op0) != SUBREG)
1949 if (GET_CODE (op0) != REG
1950 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1951 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1955 if (reload_in_progress || reload_completed)
1958 temp = gen_reg_rtx (DImode);
1960 if (GET_CODE (op1) != CONST_DOUBLE
1961 && GET_CODE (op1) != CONST_INT)
1963 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1967 if (GET_CODE (op1) == CONST_DOUBLE)
1969 #if HOST_BITS_PER_WIDE_INT == 64
1970 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1971 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1973 high_bits = CONST_DOUBLE_HIGH (op1);
1974 low_bits = CONST_DOUBLE_LOW (op1);
1979 #if HOST_BITS_PER_WIDE_INT == 64
1980 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1981 low_bits = (INTVAL (op1) & 0xffffffff);
1983 high_bits = ((INTVAL (op1) < 0) ?
1986 low_bits = INTVAL (op1);
1990 /* low_bits bits 0 --> 31
1991 high_bits bits 32 --> 63 */
1993 analyze_64bit_constant (high_bits, low_bits,
1994 &highest_bit_set, &lowest_bit_set,
1995 &all_bits_between_are_set);
1997 /* First try for a 2-insn sequence. */
1999 /* These situations are preferred because the optimizer can
2000 * do more things with them:
2002 * sllx %reg, shift, %reg
2004 * srlx %reg, shift, %reg
2005 * 3) mov some_small_const, %reg
2006 * sllx %reg, shift, %reg
2008 if (((highest_bit_set == 63
2009 || lowest_bit_set == 0)
2010 && all_bits_between_are_set != 0)
2011 || ((highest_bit_set - lowest_bit_set) < 12))
2013 HOST_WIDE_INT the_const = -1;
2014 int shift = lowest_bit_set;
2016 if ((highest_bit_set != 63
2017 && lowest_bit_set != 0)
2018 || all_bits_between_are_set == 0)
2021 create_simple_focus_bits (high_bits, low_bits,
2024 else if (lowest_bit_set == 0)
2025 shift = -(63 - highest_bit_set);
2027 if (! SPARC_SIMM13_P (the_const))
2030 emit_insn (gen_safe_SET64 (temp, the_const));
2032 emit_insn (gen_rtx_SET (VOIDmode,
2034 gen_rtx_ASHIFT (DImode,
2038 emit_insn (gen_rtx_SET (VOIDmode,
2040 gen_rtx_LSHIFTRT (DImode,
2042 GEN_INT (-shift))));
2048 /* Now a range of 22 or less bits set somewhere.
2049 * 1) sethi %hi(focus_bits), %reg
2050 * sllx %reg, shift, %reg
2051 * 2) sethi %hi(focus_bits), %reg
2052 * srlx %reg, shift, %reg
2054 if ((highest_bit_set - lowest_bit_set) < 21)
2056 unsigned HOST_WIDE_INT focus_bits =
2057 create_simple_focus_bits (high_bits, low_bits,
2058 lowest_bit_set, 10);
2060 if (! SPARC_SETHI_P (focus_bits))
2063 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2065 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2066 if (lowest_bit_set < 10)
2067 emit_insn (gen_rtx_SET (VOIDmode,
2069 gen_rtx_LSHIFTRT (DImode, temp,
2070 GEN_INT (10 - lowest_bit_set))));
2071 else if (lowest_bit_set > 10)
2072 emit_insn (gen_rtx_SET (VOIDmode,
2074 gen_rtx_ASHIFT (DImode, temp,
2075 GEN_INT (lowest_bit_set - 10))));
2081 /* 1) sethi %hi(low_bits), %reg
2082 * or %reg, %lo(low_bits), %reg
2083 * 2) sethi %hi(~low_bits), %reg
2084 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2087 || high_bits == 0xffffffff)
2089 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2090 (high_bits == 0xffffffff));
2094 /* Now, try 3-insn sequences. */
2096 /* 1) sethi %hi(high_bits), %reg
2097 * or %reg, %lo(high_bits), %reg
2098 * sllx %reg, 32, %reg
2102 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2106 /* We may be able to do something quick
2107 when the constant is negated, so try that. */
2108 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2109 (~low_bits) & 0xfffffc00))
2111 /* NOTE: The trailing bits get XOR'd so we need the
2112 non-negated bits, not the negated ones. */
2113 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2115 if ((((~high_bits) & 0xffffffff) == 0
2116 && ((~low_bits) & 0x80000000) == 0)
2117 || (((~high_bits) & 0xffffffff) == 0xffffffff
2118 && ((~low_bits) & 0x80000000) != 0))
2120 int fast_int = (~low_bits & 0xffffffff);
2122 if ((SPARC_SETHI_P (fast_int)
2123 && (~high_bits & 0xffffffff) == 0)
2124 || SPARC_SIMM13_P (fast_int))
2125 emit_insn (gen_safe_SET64 (temp, fast_int));
2127 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2132 #if HOST_BITS_PER_WIDE_INT == 64
2133 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2134 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2136 negated_const = gen_rtx_CONST_DOUBLE (DImode,
2137 (~low_bits) & 0xfffffc00,
2138 (~high_bits) & 0xffffffff);
2140 sparc_emit_set_const64 (temp, negated_const);
2143 /* If we are XOR'ing with -1, then we should emit a one's complement
2144 instead. This way the combiner will notice logical operations
2145 such as ANDN later on and substitute. */
2146 if (trailing_bits == 0x3ff)
2148 emit_insn (gen_rtx_SET (VOIDmode, op0,
2149 gen_rtx_NOT (DImode, temp)));
2153 emit_insn (gen_rtx_SET (VOIDmode,
2155 gen_safe_XOR64 (temp,
2156 (-0x400 | trailing_bits))));
2161 /* 1) sethi %hi(xxx), %reg
2162 * or %reg, %lo(xxx), %reg
2163 * sllx %reg, yyy, %reg
2165 * ??? This is just a generalized version of the low_bits==0
2166 * thing above, FIXME...
2168 if ((highest_bit_set - lowest_bit_set) < 32)
2170 unsigned HOST_WIDE_INT focus_bits =
2171 create_simple_focus_bits (high_bits, low_bits,
2174 /* We can't get here in this state. */
2175 if (highest_bit_set < 32
2176 || lowest_bit_set >= 32)
2179 /* So what we know is that the set bits straddle the
2180 middle of the 64-bit word. */
2181 sparc_emit_set_const64_quick2 (op0, temp,
2187 /* 1) sethi %hi(high_bits), %reg
2188 * or %reg, %lo(high_bits), %reg
2189 * sllx %reg, 32, %reg
2190 * or %reg, low_bits, %reg
2192 if (SPARC_SIMM13_P(low_bits)
2193 && ((int)low_bits > 0))
2195 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2199 /* The easiest way when all else fails, is full decomposition. */
2201 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2202 high_bits, low_bits, ~high_bits, ~low_bits);
2204 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2207 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2208 return the mode to be used for the comparison. For floating-point,
2209 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2210 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2211 processing is needed. */
2214 select_cc_mode (op, x, y)
2217 rtx y ATTRIBUTE_UNUSED;
2219 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2245 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2246 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2248 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2249 return CCX_NOOVmode;
2255 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2262 /* X and Y are two things to compare using CODE. Emit the compare insn and
2263 return the rtx for the cc reg in the proper mode. */
2266 gen_compare_reg (code, x, y)
2270 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2273 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2274 fcc regs (cse can't tell they're really call clobbered regs and will
2275 remove a duplicate comparison even if there is an intervening function
2276 call - it will then try to reload the cc reg via an int reg which is why
2277 we need the movcc patterns). It is possible to provide the movcc
2278 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2279 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2280 to tell cse that CCFPE mode registers (even pseudos) are call
2283 /* ??? This is an experiment. Rather than making changes to cse which may
2284 or may not be easy/clean, we do our own cse. This is possible because
2285 we will generate hard registers. Cse knows they're call clobbered (it
2286 doesn't know the same thing about pseudos). If we guess wrong, no big
2287 deal, but if we win, great! */
2289 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2290 #if 1 /* experiment */
2293 /* We cycle through the registers to ensure they're all exercised. */
2294 static int next_fcc_reg = 0;
2295 /* Previous x,y for each fcc reg. */
2296 static rtx prev_args[4][2];
2298 /* Scan prev_args for x,y. */
2299 for (reg = 0; reg < 4; reg++)
2300 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2305 prev_args[reg][0] = x;
2306 prev_args[reg][1] = y;
2307 next_fcc_reg = (next_fcc_reg + 1) & 3;
2309 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2312 cc_reg = gen_reg_rtx (mode);
2313 #endif /* ! experiment */
2314 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2315 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2317 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2319 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2320 gen_rtx_COMPARE (mode, x, y)));
2325 /* This function is used for v9 only.
2326 CODE is the code for an Scc's comparison.
2327 OPERANDS[0] is the target of the Scc insn.
2328 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2329 been generated yet).
2331 This function is needed to turn
2334 (gt (reg:CCX 100 %icc)
2338 (gt:DI (reg:CCX 100 %icc)
2341 IE: The instruction recognizer needs to see the mode of the comparison to
2342 find the right instruction. We could use "gt:DI" right in the
2343 define_expand, but leaving it out allows us to handle DI, SI, etc.
2345 We refer to the global sparc compare operands sparc_compare_op0 and
2346 sparc_compare_op1. */
2349 gen_v9_scc (compare_code, operands)
2350 enum rtx_code compare_code;
2351 register rtx *operands;
2356 && (GET_MODE (sparc_compare_op0) == DImode
2357 || GET_MODE (operands[0]) == DImode))
2360 op0 = sparc_compare_op0;
2361 op1 = sparc_compare_op1;
2363 /* Try to use the movrCC insns. */
2365 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2366 && op1 == const0_rtx
2367 && v9_regcmp_p (compare_code))
2369 /* Special case for op0 != 0. This can be done with one instruction if
2370 operands[0] == sparc_compare_op0. */
2372 if (compare_code == NE
2373 && GET_MODE (operands[0]) == DImode
2374 && rtx_equal_p (op0, operands[0]))
2376 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2377 gen_rtx_IF_THEN_ELSE (DImode,
2378 gen_rtx_fmt_ee (compare_code, DImode,
2385 if (reg_overlap_mentioned_p (operands[0], op0))
2387 /* Handle the case where operands[0] == sparc_compare_op0.
2388 We "early clobber" the result. */
2389 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2390 emit_move_insn (op0, sparc_compare_op0);
2393 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2394 if (GET_MODE (op0) != DImode)
2396 temp = gen_reg_rtx (DImode);
2397 convert_move (temp, op0, 0);
2401 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2402 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2403 gen_rtx_fmt_ee (compare_code, DImode,
2411 operands[1] = gen_compare_reg (compare_code, op0, op1);
2413 switch (GET_MODE (operands[1]))
2423 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2424 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2425 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2426 gen_rtx_fmt_ee (compare_code,
2427 GET_MODE (operands[1]),
2428 operands[1], const0_rtx),
2429 const1_rtx, operands[0])));
2434 /* Emit a conditional jump insn for the v9 architecture using comparison code
2435 CODE and jump target LABEL.
2436 This function exists to take advantage of the v9 brxx insns. */
2439 emit_v9_brxx_insn (code, op0, label)
2443 emit_jump_insn (gen_rtx_SET (VOIDmode,
2445 gen_rtx_IF_THEN_ELSE (VOIDmode,
2446 gen_rtx_fmt_ee (code, GET_MODE (op0),
2448 gen_rtx_LABEL_REF (VOIDmode, label),
2452 /* Generate a DFmode part of a hard TFmode register.
2453 REG is the TFmode hard register, LOW is 1 for the
2454 low 64bit of the register and 0 otherwise.
2457 gen_df_reg (reg, low)
2461 int regno = REGNO (reg);
2463 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2464 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2465 return gen_rtx_REG (DFmode, regno);
2468 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2469 Unlike normal calls, TFmode operands are passed by reference. It is
2470 assumed that no more than 3 operands are required. */
2473 emit_soft_tfmode_libcall (func_name, nargs, operands)
2474 const char *func_name;
2478 rtx ret_slot = NULL, arg[3], func_sym;
2481 /* We only expect to be called for conversions, unary, and binary ops. */
2482 if (nargs < 2 || nargs > 3)
2485 for (i = 0; i < nargs; ++i)
2487 rtx this_arg = operands[i];
2490 /* TFmode arguments and return values are passed by reference. */
2491 if (GET_MODE (this_arg) == TFmode)
2493 if (GET_CODE (this_arg) == MEM)
2495 this_arg = XEXP (this_arg, 0);
2497 /* Make sure the output is not in the same place
2498 as one of our inputs. */
2501 for (j = 1; j < nargs; j++)
2502 if (rtx_equal_p (operands[0], operands[j]))
2507 ret_slot = assign_stack_temp (TFmode,
2508 GET_MODE_SIZE (TFmode), 0);
2509 this_arg = XEXP (ret_slot, 0);
2513 else if (CONSTANT_P (this_arg))
2515 this_slot = force_const_mem (TFmode, this_arg);
2516 this_arg = XEXP (this_slot, 0);
2520 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2522 /* Operand 0 is the return value. We'll copy it out later. */
2524 emit_move_insn (this_slot, this_arg);
2526 ret_slot = this_slot;
2528 this_arg = XEXP (this_slot, 0);
2535 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2537 if (GET_MODE (operands[0]) == TFmode)
2540 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2541 arg[0], GET_MODE (arg[0]),
2542 arg[1], GET_MODE (arg[1]));
2544 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2545 arg[0], GET_MODE (arg[0]),
2546 arg[1], GET_MODE (arg[1]),
2547 arg[2], GET_MODE (arg[2]));
2550 emit_move_insn (operands[0], ret_slot);
2559 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2560 GET_MODE (operands[0]), 1,
2561 arg[1], GET_MODE (arg[1]));
2563 if (ret != operands[0])
2564 emit_move_insn (operands[0], ret);
2568 /* Expand soft-float TFmode calls to sparc abi routines. */
2571 emit_soft_tfmode_binop (code, operands)
2595 emit_soft_tfmode_libcall (func, 3, operands);
2599 emit_soft_tfmode_unop (code, operands)
2614 emit_soft_tfmode_libcall (func, 2, operands);
2618 emit_soft_tfmode_cvt (code, operands)
2627 switch (GET_MODE (operands[1]))
2640 case FLOAT_TRUNCATE:
2641 switch (GET_MODE (operands[0]))
2655 switch (GET_MODE (operands[1]))
2668 case UNSIGNED_FLOAT:
2669 switch (GET_MODE (operands[1]))
2683 switch (GET_MODE (operands[0]))
2697 switch (GET_MODE (operands[0]))
2714 emit_soft_tfmode_libcall (func, 2, operands);
2717 /* Expand a hard-float tfmode operation. All arguments must be in
2721 emit_hard_tfmode_operation (code, operands)
2727 if (GET_RTX_CLASS (code) == '1')
2729 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2730 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2734 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2735 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2736 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2737 operands[1], operands[2]);
2740 if (register_operand (operands[0], VOIDmode))
2743 dest = gen_reg_rtx (GET_MODE (operands[0]));
2745 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2747 if (dest != operands[0])
2748 emit_move_insn (operands[0], dest);
2752 emit_tfmode_binop (code, operands)
2756 if (TARGET_HARD_QUAD)
2757 emit_hard_tfmode_operation (code, operands);
2759 emit_soft_tfmode_binop (code, operands);
2763 emit_tfmode_unop (code, operands)
2767 if (TARGET_HARD_QUAD)
2768 emit_hard_tfmode_operation (code, operands);
2770 emit_soft_tfmode_unop (code, operands);
2774 emit_tfmode_cvt (code, operands)
2778 if (TARGET_HARD_QUAD)
2779 emit_hard_tfmode_operation (code, operands);
2781 emit_soft_tfmode_cvt (code, operands);
2784 /* Return nonzero if a return peephole merging return with
2785 setting of output register is ok. */
2787 leaf_return_peephole_ok ()
2789 return (actual_fsize == 0);
2792 /* Return nonzero if a branch/jump/call instruction will be emitting
2793 nop into its delay slot. */
2796 empty_delay_slot (insn)
2801 /* If no previous instruction (should not happen), return true. */
2802 if (PREV_INSN (insn) == NULL)
2805 seq = NEXT_INSN (PREV_INSN (insn));
2806 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2812 /* Return nonzero if TRIAL can go into the function epilogue's
2813 delay slot. SLOT is the slot we are trying to fill. */
2816 eligible_for_epilogue_delay (trial, slot)
2825 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2828 if (get_attr_length (trial) != 1)
2831 /* If there are any call-saved registers, we should scan TRIAL if it
2832 does not reference them. For now just make it easy. */
2836 /* If the function uses __builtin_eh_return, the eh_return machinery
2837 occupies the delay slot. */
2838 if (current_function_calls_eh_return)
2841 /* In the case of a true leaf function, anything can go into the delay slot.
2842 A delay slot only exists however if the frame size is zero, otherwise
2843 we will put an insn to adjust the stack after the return. */
2844 if (current_function_uses_only_leaf_regs)
2846 if (leaf_return_peephole_ok ())
2847 return ((get_attr_in_uncond_branch_delay (trial)
2848 == IN_BRANCH_DELAY_TRUE));
2852 pat = PATTERN (trial);
2854 /* Otherwise, only operations which can be done in tandem with
2855 a `restore' or `return' insn can go into the delay slot. */
2856 if (GET_CODE (SET_DEST (pat)) != REG
2857 || REGNO (SET_DEST (pat)) < 24)
2860 /* If this instruction sets up floating point register and we have a return
2861 instruction, it can probably go in. But restore will not work
2863 if (REGNO (SET_DEST (pat)) >= 32)
2865 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2866 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2871 /* The set of insns matched here must agree precisely with the set of
2872 patterns paired with a RETURN in sparc.md. */
2874 src = SET_SRC (pat);
2876 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2877 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2878 && arith_operand (src, GET_MODE (src)))
2881 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2883 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2886 /* This matches "*return_di". */
2887 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2888 && arith_double_operand (src, GET_MODE (src)))
2889 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2891 /* This matches "*return_sf_no_fpu". */
2892 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2893 && register_operand (src, SFmode))
2896 /* If we have return instruction, anything that does not use
2897 local or output registers and can go into a delay slot wins. */
2898 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2899 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2902 /* This matches "*return_addsi". */
2903 else if (GET_CODE (src) == PLUS
2904 && arith_operand (XEXP (src, 0), SImode)
2905 && arith_operand (XEXP (src, 1), SImode)
2906 && (register_operand (XEXP (src, 0), SImode)
2907 || register_operand (XEXP (src, 1), SImode)))
2910 /* This matches "*return_adddi". */
2911 else if (GET_CODE (src) == PLUS
2912 && arith_double_operand (XEXP (src, 0), DImode)
2913 && arith_double_operand (XEXP (src, 1), DImode)
2914 && (register_operand (XEXP (src, 0), DImode)
2915 || register_operand (XEXP (src, 1), DImode)))
2918 /* This can match "*return_losum_[sd]i".
2919 Catch only some cases, so that return_losum* don't have
2921 else if (GET_CODE (src) == LO_SUM
2922 && ! TARGET_CM_MEDMID
2923 && ((register_operand (XEXP (src, 0), SImode)
2924 && immediate_operand (XEXP (src, 1), SImode))
2926 && register_operand (XEXP (src, 0), DImode)
2927 && immediate_operand (XEXP (src, 1), DImode))))
2930 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2931 else if (GET_CODE (src) == ASHIFT
2932 && (register_operand (XEXP (src, 0), SImode)
2933 || register_operand (XEXP (src, 0), DImode))
2934 && XEXP (src, 1) == const1_rtx)
2940 /* Return nonzero if TRIAL can go into the sibling call
2944 eligible_for_sibcall_delay (trial)
2949 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2952 if (get_attr_length (trial) != 1)
2955 pat = PATTERN (trial);
2957 if (current_function_uses_only_leaf_regs)
2959 /* If the tail call is done using the call instruction,
2960 we have to restore %o7 in the delay slot. */
2961 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2964 /* %g1 is used to build the function address */
2965 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2971 /* Otherwise, only operations which can be done in tandem with
2972 a `restore' insn can go into the delay slot. */
2973 if (GET_CODE (SET_DEST (pat)) != REG
2974 || REGNO (SET_DEST (pat)) < 24
2975 || REGNO (SET_DEST (pat)) >= 32)
2978 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2980 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2983 src = SET_SRC (pat);
2985 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2986 && arith_operand (src, GET_MODE (src)))
2989 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2991 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2994 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2995 && arith_double_operand (src, GET_MODE (src)))
2996 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2998 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2999 && register_operand (src, SFmode))
3002 else if (GET_CODE (src) == PLUS
3003 && arith_operand (XEXP (src, 0), SImode)
3004 && arith_operand (XEXP (src, 1), SImode)
3005 && (register_operand (XEXP (src, 0), SImode)
3006 || register_operand (XEXP (src, 1), SImode)))
3009 else if (GET_CODE (src) == PLUS
3010 && arith_double_operand (XEXP (src, 0), DImode)
3011 && arith_double_operand (XEXP (src, 1), DImode)
3012 && (register_operand (XEXP (src, 0), DImode)
3013 || register_operand (XEXP (src, 1), DImode)))
3016 else if (GET_CODE (src) == LO_SUM
3017 && ! TARGET_CM_MEDMID
3018 && ((register_operand (XEXP (src, 0), SImode)
3019 && immediate_operand (XEXP (src, 1), SImode))
3021 && register_operand (XEXP (src, 0), DImode)
3022 && immediate_operand (XEXP (src, 1), DImode))))
3025 else if (GET_CODE (src) == ASHIFT
3026 && (register_operand (XEXP (src, 0), SImode)
3027 || register_operand (XEXP (src, 0), DImode))
3028 && XEXP (src, 1) == const1_rtx)
3035 check_return_regs (x)
3038 switch (GET_CODE (x))
3041 return IN_OR_GLOBAL_P (x);
3056 if (check_return_regs (XEXP (x, 1)) == 0)
3061 return check_return_regs (XEXP (x, 0));
3069 /* Return 1 if TRIAL references only in and global registers. */
3071 eligible_for_return_delay (trial)
3074 if (GET_CODE (PATTERN (trial)) != SET)
3077 return check_return_regs (PATTERN (trial));
3081 short_branch (uid1, uid2)
3084 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3086 /* Leave a few words of "slop". */
3087 if (delta >= -1023 && delta <= 1022)
3093 /* Return non-zero if REG is not used after INSN.
3094 We assume REG is a reload reg, and therefore does
3095 not live past labels or calls or jumps. */
3097 reg_unused_after (reg, insn)
3101 enum rtx_code code, prev_code = UNKNOWN;
3103 while ((insn = NEXT_INSN (insn)))
3105 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3108 code = GET_CODE (insn);
3109 if (GET_CODE (insn) == CODE_LABEL)
3112 if (GET_RTX_CLASS (code) == 'i')
3114 rtx set = single_set (insn);
3115 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3118 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3120 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3128 /* The table we use to reference PIC data. */
3129 static rtx global_offset_table;
3131 /* The function we use to get at it. */
3132 static rtx get_pc_symbol;
3133 static char get_pc_symbol_name[256];
3135 /* Ensure that we are not using patterns that are not OK with PIC. */
3144 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3145 || (GET_CODE (recog_data.operand[i]) == CONST
3146 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3147 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3148 == global_offset_table)
3149 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3158 /* Return true if X is an address which needs a temporary register when
3159 reloaded while generating PIC code. */
3162 pic_address_needs_scratch (x)
3165 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3166 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3167 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3168 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3169 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3175 /* Legitimize PIC addresses. If the address is already position-independent,
3176 we return ORIG. Newly generated position-independent addresses go into a
3177 reg. This is REG if non zero, otherwise we allocate register(s) as
3181 legitimize_pic_address (orig, mode, reg)
3183 enum machine_mode mode ATTRIBUTE_UNUSED;
3186 if (GET_CODE (orig) == SYMBOL_REF)
3188 rtx pic_ref, address;
3193 if (reload_in_progress || reload_completed)
3196 reg = gen_reg_rtx (Pmode);
3201 /* If not during reload, allocate another temp reg here for loading
3202 in the address, so that these instructions can be optimized
3204 rtx temp_reg = ((reload_in_progress || reload_completed)
3205 ? reg : gen_reg_rtx (Pmode));
3207 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3208 won't get confused into thinking that these two instructions
3209 are loading in the true address of the symbol. If in the
3210 future a PIC rtx exists, that should be used instead. */
3211 if (Pmode == SImode)
3213 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3214 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3218 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3219 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3226 pic_ref = gen_rtx_MEM (Pmode,
3227 gen_rtx_PLUS (Pmode,
3228 pic_offset_table_rtx, address));
3229 current_function_uses_pic_offset_table = 1;
3230 RTX_UNCHANGING_P (pic_ref) = 1;
3231 insn = emit_move_insn (reg, pic_ref);
3232 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3234 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3238 else if (GET_CODE (orig) == CONST)
3242 if (GET_CODE (XEXP (orig, 0)) == PLUS
3243 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3248 if (reload_in_progress || reload_completed)
3251 reg = gen_reg_rtx (Pmode);
3254 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3256 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3257 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3258 base == reg ? 0 : reg);
3263 if (GET_CODE (offset) == CONST_INT)
3265 if (SMALL_INT (offset))
3266 return plus_constant (base, INTVAL (offset));
3267 else if (! reload_in_progress && ! reload_completed)
3268 offset = force_reg (Pmode, offset);
3270 /* If we reach here, then something is seriously wrong. */
3273 return gen_rtx_PLUS (Pmode, base, offset);
3275 else if (GET_CODE (orig) == LABEL_REF)
3276 /* ??? Why do we do this? */
3277 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3278 the register is live instead, in case it is eliminated. */
3279 current_function_uses_pic_offset_table = 1;
3284 /* Emit special PIC prologues. */
3287 load_pic_register ()
3289 /* Labels to get the PC in the prologue of this function. */
3290 int orig_flag_pic = flag_pic;
3295 /* If we haven't emitted the special get_pc helper function, do so now. */
3296 if (get_pc_symbol_name[0] == 0)
3300 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3303 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3305 ASM_OUTPUT_ALIGN (asm_out_file, align);
3306 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0);
3307 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3310 /* Initialize every time through, since we can't easily
3311 know this to be permanent. */
3312 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3313 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3316 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3319 flag_pic = orig_flag_pic;
3321 /* Need to emit this whether or not we obey regdecls,
3322 since setjmp/longjmp can cause life info to screw up.
3323 ??? In the case where we don't obey regdecls, this is not sufficient
3324 since we may not fall out the bottom. */
3325 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3328 /* Return 1 if RTX is a MEM which is known to be aligned to at
3329 least a DESIRED byte boundary. */
3332 mem_min_alignment (mem, desired)
3336 rtx addr, base, offset;
3338 /* If it's not a MEM we can't accept it. */
3339 if (GET_CODE (mem) != MEM)
3342 addr = XEXP (mem, 0);
3343 base = offset = NULL_RTX;
3344 if (GET_CODE (addr) == PLUS)
3346 if (GET_CODE (XEXP (addr, 0)) == REG)
3348 base = XEXP (addr, 0);
3350 /* What we are saying here is that if the base
3351 REG is aligned properly, the compiler will make
3352 sure any REG based index upon it will be so
3354 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3355 offset = XEXP (addr, 1);
3357 offset = const0_rtx;
3360 else if (GET_CODE (addr) == REG)
3363 offset = const0_rtx;
3366 if (base != NULL_RTX)
3368 int regno = REGNO (base);
3370 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3372 /* Check if the compiler has recorded some information
3373 about the alignment of the base REG. If reload has
3374 completed, we already matched with proper alignments.
3375 If not running global_alloc, reload might give us
3376 unaligned pointer to local stack though. */
3378 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3379 || (optimize && reload_completed))
3380 && (INTVAL (offset) & (desired - 1)) == 0)
3385 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3389 else if (! TARGET_UNALIGNED_DOUBLES
3390 || CONSTANT_P (addr)
3391 || GET_CODE (addr) == LO_SUM)
3393 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3394 is true, in which case we can only assume that an access is aligned if
3395 it is to a constant address, or the address involves a LO_SUM. */
3399 /* An obviously unaligned address. */
3404 /* Vectors to keep interesting information about registers where it can easily
3405 be got. We use to use the actual mode value as the bit number, but there
3406 are more than 32 modes now. Instead we use two tables: one indexed by
3407 hard register number, and one indexed by mode. */
3409 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3410 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3411 mapped into one sparc_mode_class mode. */
3413 enum sparc_mode_class {
3414 S_MODE, D_MODE, T_MODE, O_MODE,
3415 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3419 /* Modes for single-word and smaller quantities. */
3420 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3422 /* Modes for double-word and smaller quantities. */
3423 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3425 /* Modes for quad-word and smaller quantities. */
3426 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3428 /* Modes for 8-word and smaller quantities. */
3429 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3431 /* Modes for single-float quantities. We must allow any single word or
3432 smaller quantity. This is because the fix/float conversion instructions
3433 take integer inputs/outputs from the float registers. */
3434 #define SF_MODES (S_MODES)
3436 /* Modes for double-float and smaller quantities. */
3437 #define DF_MODES (S_MODES | D_MODES)
3439 /* Modes for double-float only quantities. */
3440 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3442 /* Modes for quad-float only quantities. */
3443 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3445 /* Modes for quad-float and smaller quantities. */
3446 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3448 /* Modes for quad-float and double-float quantities. */
3449 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3451 /* Modes for quad-float pair only quantities. */
3452 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3454 /* Modes for quad-float pairs and smaller quantities. */
3455 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3457 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3459 /* Modes for condition codes. */
3460 #define CC_MODES (1 << (int) CC_MODE)
3461 #define CCFP_MODES (1 << (int) CCFP_MODE)
3463 /* Value is 1 if register/mode pair is acceptable on sparc.
3464 The funny mixture of D and T modes is because integer operations
3465 do not specially operate on tetra quantities, so non-quad-aligned
3466 registers can hold quadword quantities (except %o4 and %i4 because
3467 they cross fixed registers). */
3469 /* This points to either the 32 bit or the 64 bit version. */
3470 const int *hard_regno_mode_classes;
3472 static const int hard_32bit_mode_classes[] = {
3473 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3474 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3475 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3476 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3478 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3479 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3480 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3481 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3483 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3484 and none can hold SFmode/SImode values. */
3485 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3486 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3487 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3488 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3491 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3497 static const int hard_64bit_mode_classes[] = {
3498 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3499 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3500 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3501 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3503 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3504 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3505 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3506 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3508 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3509 and none can hold SFmode/SImode values. */
3510 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3511 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3512 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3513 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3516 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3522 int sparc_mode_class [NUM_MACHINE_MODES];
3524 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3531 for (i = 0; i < NUM_MACHINE_MODES; i++)
3533 switch (GET_MODE_CLASS (i))
3536 case MODE_PARTIAL_INT:
3537 case MODE_COMPLEX_INT:
3538 if (GET_MODE_SIZE (i) <= 4)
3539 sparc_mode_class[i] = 1 << (int) S_MODE;
3540 else if (GET_MODE_SIZE (i) == 8)
3541 sparc_mode_class[i] = 1 << (int) D_MODE;
3542 else if (GET_MODE_SIZE (i) == 16)
3543 sparc_mode_class[i] = 1 << (int) T_MODE;
3544 else if (GET_MODE_SIZE (i) == 32)
3545 sparc_mode_class[i] = 1 << (int) O_MODE;
3547 sparc_mode_class[i] = 0;
3550 case MODE_COMPLEX_FLOAT:
3551 if (GET_MODE_SIZE (i) <= 4)
3552 sparc_mode_class[i] = 1 << (int) SF_MODE;
3553 else if (GET_MODE_SIZE (i) == 8)
3554 sparc_mode_class[i] = 1 << (int) DF_MODE;
3555 else if (GET_MODE_SIZE (i) == 16)
3556 sparc_mode_class[i] = 1 << (int) TF_MODE;
3557 else if (GET_MODE_SIZE (i) == 32)
3558 sparc_mode_class[i] = 1 << (int) OF_MODE;
3560 sparc_mode_class[i] = 0;
3564 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3565 we must explicitly check for them here. */
3566 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3567 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3568 else if (i == (int) CCmode || i == (int) CC_NOOVmode
3569 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3570 sparc_mode_class[i] = 1 << (int) CC_MODE;
3572 sparc_mode_class[i] = 0;
3578 hard_regno_mode_classes = hard_64bit_mode_classes;
3580 hard_regno_mode_classes = hard_32bit_mode_classes;
3582 /* Initialize the array used by REGNO_REG_CLASS. */
3583 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3585 if (i < 16 && TARGET_V8PLUS)
3586 sparc_regno_reg_class[i] = I64_REGS;
3587 else if (i < 32 || i == FRAME_POINTER_REGNUM)
3588 sparc_regno_reg_class[i] = GENERAL_REGS;
3590 sparc_regno_reg_class[i] = FP_REGS;
3592 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3594 sparc_regno_reg_class[i] = FPCC_REGS;
3596 sparc_regno_reg_class[i] = NO_REGS;
3600 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3601 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3602 v9 int regs as it simplifies the code. */
3605 save_regs (file, low, high, base, offset, n_regs, real_offset)
3615 if (TARGET_ARCH64 && high <= 32)
3617 for (i = low; i < high; i++)
3619 if (regs_ever_live[i] && ! call_used_regs[i])
3621 fprintf (file, "\tstx\t%s, [%s+%d]\n",
3622 reg_names[i], base, offset + 4 * n_regs);
3623 if (dwarf2out_do_frame ())
3624 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3631 for (i = low; i < high; i += 2)
3633 if (regs_ever_live[i] && ! call_used_regs[i])
3635 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3637 fprintf (file, "\tstd\t%s, [%s+%d]\n",
3638 reg_names[i], base, offset + 4 * n_regs);
3639 if (dwarf2out_do_frame ())
3641 char *l = dwarf2out_cfi_label ();
3642 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
3643 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
3649 fprintf (file, "\tst\t%s, [%s+%d]\n",
3650 reg_names[i], base, offset + 4 * n_regs);
3651 if (dwarf2out_do_frame ())
3652 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3658 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3660 fprintf (file, "\tst\t%s, [%s+%d]\n",
3661 reg_names[i+1], base, offset + 4 * n_regs + 4);
3662 if (dwarf2out_do_frame ())
3663 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
3672 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3674 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3675 v9 int regs as it simplifies the code. */
3678 restore_regs (file, low, high, base, offset, n_regs)
3687 if (TARGET_ARCH64 && high <= 32)
3689 for (i = low; i < high; i++)
3691 if (regs_ever_live[i] && ! call_used_regs[i])
3692 fprintf (file, "\tldx\t[%s+%d], %s\n",
3693 base, offset + 4 * n_regs, reg_names[i]),
3699 for (i = low; i < high; i += 2)
3701 if (regs_ever_live[i] && ! call_used_regs[i])
3702 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3703 fprintf (file, "\tldd\t[%s+%d], %s\n",
3704 base, offset + 4 * n_regs, reg_names[i]),
3707 fprintf (file, "\tld\t[%s+%d], %s\n",
3708 base, offset + 4 * n_regs, reg_names[i]),
3710 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3711 fprintf (file, "\tld\t[%s+%d], %s\n",
3712 base, offset + 4 * n_regs + 4, reg_names[i+1]),
3719 /* Compute the frame size required by the function. This function is called
3720 during the reload pass and also by output_function_prologue(). */
3723 compute_frame_size (size, leaf_function)
3728 int outgoing_args_size = (current_function_outgoing_args_size
3729 + REG_PARM_STACK_SPACE (current_function_decl));
3731 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3732 even to v9 int regs to be consistent with save_regs/restore_regs. */
3736 for (i = 0; i < 8; i++)
3737 if (regs_ever_live[i] && ! call_used_regs[i])
3742 for (i = 0; i < 8; i += 2)
3743 if ((regs_ever_live[i] && ! call_used_regs[i])
3744 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3748 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3749 if ((regs_ever_live[i] && ! call_used_regs[i])
3750 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3753 /* Set up values for use in `function_epilogue'. */
3754 num_gfregs = n_regs;
3756 if (leaf_function && n_regs == 0
3757 && size == 0 && current_function_outgoing_args_size == 0)
3759 actual_fsize = apparent_fsize = 0;
3763 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3764 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
3765 apparent_fsize += n_regs * 4;
3766 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3769 /* Make sure nothing can clobber our register windows.
3770 If a SAVE must be done, or there is a stack-local variable,
3771 the register window area must be allocated.
3772 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3773 if (leaf_function == 0 || size > 0)
3774 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3776 return SPARC_STACK_ALIGN (actual_fsize);
3779 /* Build a (32 bit) big number in a register. */
3780 /* ??? We may be able to use the set macro here too. */
3783 build_big_number (file, num, reg)
3788 if (num >= 0 || ! TARGET_ARCH64)
3790 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
3791 if ((num & 0x3ff) != 0)
3792 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
3794 else /* num < 0 && TARGET_ARCH64 */
3796 /* Sethi does not sign extend, so we must use a little trickery
3797 to use it for negative numbers. Invert the constant before
3798 loading it in, then use xor immediate to invert the loaded bits
3799 (along with the upper 32 bits) to the desired constant. This
3800 works because the sethi and immediate fields overlap. */
3803 int low = -0x400 + (asize & 0x3FF);
3805 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3806 inv, reg, reg, low, reg);
3810 /* Output any necessary .register pseudo-ops. */
3812 sparc_output_scratch_registers (file)
3813 FILE *file ATTRIBUTE_UNUSED;
3815 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3821 /* Check if %g[2367] were used without
3822 .register being printed for them already. */
3823 for (i = 2; i < 8; i++)
3825 if (regs_ever_live [i]
3826 && ! sparc_hard_reg_printed [i])
3828 sparc_hard_reg_printed [i] = 1;
3829 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
3836 /* This function generates the assembly code for function entry.
3837 FILE is a stdio stream to output the code to.
3838 SIZE is an int: how many units of temporary storage to allocate.
3839 Refer to the array `regs_ever_live' to determine which registers
3840 to save; `regs_ever_live[I]' is nonzero if register number I
3841 is ever used in the function. This macro is responsible for
3842 knowing which registers should not be saved even if used. */
3844 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
3845 of memory. If any fpu reg is used in the function, we allocate
3846 such a block here, at the bottom of the frame, just in case it's needed.
3848 If this function is a leaf procedure, then we may choose not
3849 to do a "save" insn. The decision about whether or not
3850 to do this is made in regclass.c. */
3853 sparc_output_function_prologue (file, size)
3858 sparc_flat_function_prologue (file, size);
3860 sparc_nonflat_function_prologue (file, size,
3861 current_function_uses_only_leaf_regs);
3864 /* Output code for the function prologue. */
3867 sparc_nonflat_function_prologue (file, size, leaf_function)
3872 sparc_output_scratch_registers (file);
3874 /* Need to use actual_fsize, since we are also allocating
3875 space for our callee (and our own register save area). */
3876 actual_fsize = compute_frame_size (size, leaf_function);
3880 frame_base_name = "%sp";
3881 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3885 frame_base_name = "%fp";
3886 frame_base_offset = SPARC_STACK_BIAS;
3889 /* This is only for the human reader. */
3890 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3892 if (actual_fsize == 0)
3894 else if (! leaf_function)
3896 if (actual_fsize <= 4096)
3897 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3898 else if (actual_fsize <= 8192)
3900 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3901 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3905 build_big_number (file, -actual_fsize, "%g1");
3906 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
3909 else /* leaf function */
3911 if (actual_fsize <= 4096)
3912 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3913 else if (actual_fsize <= 8192)
3915 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3916 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3920 build_big_number (file, -actual_fsize, "%g1");
3921 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3925 if (dwarf2out_do_frame () && actual_fsize)
3927 char *label = dwarf2out_cfi_label ();
3929 /* The canonical frame address refers to the top of the frame. */
3930 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3931 : HARD_FRAME_POINTER_REGNUM),
3934 if (! leaf_function)
3936 /* Note the register window save. This tells the unwinder that
3937 it needs to restore the window registers from the previous
3938 frame's window save area at 0(cfa). */
3939 dwarf2out_window_save (label);
3941 /* The return address (-8) is now in %i7. */
3942 dwarf2out_return_reg (label, 31);
3946 /* If doing anything with PIC, do it now. */
3948 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3950 /* Call saved registers are saved just above the outgoing argument area. */
3953 int offset, real_offset, n_regs;
3956 real_offset = -apparent_fsize;
3957 offset = -apparent_fsize + frame_base_offset;
3958 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3960 /* ??? This might be optimized a little as %g1 might already have a
3961 value close enough that a single add insn will do. */
3962 /* ??? Although, all of this is probably only a temporary fix
3963 because if %g1 can hold a function result, then
3964 output_function_epilogue will lose (the result will get
3966 build_big_number (file, offset, "%g1");
3967 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3973 base = frame_base_name;
3976 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3977 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3982 /* Output code to restore any call saved registers. */
3985 output_restore_regs (file, leaf_function)
3987 int leaf_function ATTRIBUTE_UNUSED;
3992 offset = -apparent_fsize + frame_base_offset;
3993 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3995 build_big_number (file, offset, "%g1");
3996 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4002 base = frame_base_name;
4005 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4006 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4009 /* This function generates the assembly code for function exit,
4010 on machines that need it.
4012 The function epilogue should not depend on the current stack pointer!
4013 It should use the frame pointer only. This is mandatory because
4014 of alloca; we also take advantage of it to omit stack adjustments
4015 before returning. */
4018 sparc_output_function_epilogue (file, size)
4023 sparc_flat_function_epilogue (file, size);
4025 sparc_nonflat_function_epilogue (file, size,
4026 current_function_uses_only_leaf_regs);
4029 /* Output code for the function epilogue. */
4032 sparc_nonflat_function_epilogue (file, size, leaf_function)
4034 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
4039 if (current_function_epilogue_delay_list == 0)
4041 /* If code does not drop into the epilogue, we need
4042 do nothing except output pending case vectors.
4044 We have to still output a dummy nop for the sake of
4045 sane backtraces. Otherwise, if the last two instructions
4046 of a function were call foo; dslot; this can make the return
4047 PC of foo (ie. address of call instruction plus 8) point to
4048 the first instruction in the next function. */
4051 fputs("\tnop\n", file);
4053 insn = get_last_insn ();
4054 if (GET_CODE (insn) == NOTE)
4055 insn = prev_nonnote_insn (insn);
4056 if (insn && GET_CODE (insn) == BARRIER)
4057 goto output_vectors;
4061 output_restore_regs (file, leaf_function);
4063 /* Work out how to skip the caller's unimp instruction if required. */
4065 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4067 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4069 if (! leaf_function)
4071 if (current_function_calls_eh_return)
4073 if (current_function_epilogue_delay_list)
4075 if (SKIP_CALLERS_UNIMP_P)
4078 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4080 /* If we wound up with things in our delay slot, flush them here. */
4081 else if (current_function_epilogue_delay_list)
4083 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4085 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4087 epilogue_renumber (&delay, 0);
4088 fputs (SKIP_CALLERS_UNIMP_P
4089 ? "\treturn\t%i7+12\n"
4090 : "\treturn\t%i7+8\n", file);
4091 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4098 if (GET_CODE (delay) != SET)
4101 src = SET_SRC (delay);
4102 if (GET_CODE (src) == ASHIFT)
4104 if (XEXP (src, 1) != const1_rtx)
4107 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4111 insn = gen_rtx_PARALLEL (VOIDmode,
4112 gen_rtvec (2, delay,
4113 gen_rtx_RETURN (VOIDmode)));
4114 insn = emit_jump_insn (insn);
4116 sparc_emitting_epilogue = true;
4117 final_scan_insn (insn, file, 1, 0, 1);
4118 sparc_emitting_epilogue = false;
4121 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4122 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4124 fprintf (file, "\t%s\n\trestore\n", ret);
4126 /* All of the following cases are for leaf functions. */
4127 else if (current_function_calls_eh_return)
4129 else if (current_function_epilogue_delay_list)
4131 /* eligible_for_epilogue_delay_slot ensures that if this is a
4132 leaf function, then we will only have insn in the delay slot
4133 if the frame size is zero, thus no adjust for the stack is
4135 if (actual_fsize != 0)
4137 fprintf (file, "\t%s\n", ret);
4138 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4141 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4142 avoid generating confusing assembly language output. */
4143 else if (actual_fsize == 0)
4144 fprintf (file, "\t%s\n\tnop\n", ret);
4145 else if (actual_fsize <= 4096)
4146 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
4147 else if (actual_fsize <= 8192)
4148 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4149 ret, actual_fsize - 4096);
4150 else if ((actual_fsize & 0x3ff) == 0)
4151 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4154 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4155 actual_fsize, actual_fsize, ret);
4158 sparc_output_deferred_case_vectors ();
4161 /* Output a sibling call. */
4164 output_sibcall (insn, call_operand)
4165 rtx insn, call_operand;
4167 int leaf_regs = current_function_uses_only_leaf_regs;
4169 int delay_slot = dbr_sequence_length () > 0;
4173 /* Call to restore global regs might clobber
4174 the delay slot. Instead of checking for this
4175 output the delay slot now. */
4178 rtx delay = NEXT_INSN (insn);
4183 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4184 PATTERN (delay) = gen_blockage ();
4185 INSN_CODE (delay) = -1;
4188 output_restore_regs (asm_out_file, leaf_regs);
4191 operands[0] = call_operand;
4195 #ifdef HAVE_AS_RELAX_OPTION
4196 /* If as and ld are relaxing tail call insns into branch always,
4197 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4198 be optimized. With sethi/jmpl as nor ld has no easy way how to
4199 find out if somebody does not branch between the sethi and jmpl. */
4202 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4206 if ((actual_fsize || ! spare_slot) && delay_slot)
4208 rtx delay = NEXT_INSN (insn);
4213 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4214 PATTERN (delay) = gen_blockage ();
4215 INSN_CODE (delay) = -1;
4220 if (actual_fsize <= 4096)
4221 size = actual_fsize;
4222 else if (actual_fsize <= 8192)
4224 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4225 size = actual_fsize - 4096;
4227 else if ((actual_fsize & 0x3ff) == 0)
4228 fprintf (asm_out_file,
4229 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4233 fprintf (asm_out_file,
4234 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4235 actual_fsize, actual_fsize);
4236 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4241 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4242 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4244 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size);
4245 else if (! delay_slot)
4246 fputs ("\t nop\n", asm_out_file);
4251 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size);
4252 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4253 it into branch if possible. */
4254 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4255 output_asm_insn ("call\t%a0, 0", operands);
4256 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4261 output_asm_insn ("call\t%a0, 0", operands);
4264 rtx delay = NEXT_INSN (insn), pat;
4269 pat = PATTERN (delay);
4270 if (GET_CODE (pat) != SET)
4273 operands[0] = SET_DEST (pat);
4274 pat = SET_SRC (pat);
4275 switch (GET_CODE (pat))
4278 operands[1] = XEXP (pat, 0);
4279 operands[2] = XEXP (pat, 1);
4280 output_asm_insn (" restore %r1, %2, %Y0", operands);
4283 operands[1] = XEXP (pat, 0);
4284 operands[2] = XEXP (pat, 1);
4285 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4288 operands[1] = XEXP (pat, 0);
4289 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4293 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4296 PATTERN (delay) = gen_blockage ();
4297 INSN_CODE (delay) = -1;
4300 fputs ("\t restore\n", asm_out_file);
4304 /* Functions for handling argument passing.
4306 For v8 the first six args are normally in registers and the rest are
4307 pushed. Any arg that starts within the first 6 words is at least
4308 partially passed in a register unless its data type forbids.
4310 For v9, the argument registers are laid out as an array of 16 elements
4311 and arguments are added sequentially. The first 6 int args and up to the
4312 first 16 fp args (depending on size) are passed in regs.
4314 Slot Stack Integral Float Float in structure Double Long Double
4315 ---- ----- -------- ----- ------------------ ------ -----------
4316 15 [SP+248] %f31 %f30,%f31 %d30
4317 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4318 13 [SP+232] %f27 %f26,%f27 %d26
4319 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4320 11 [SP+216] %f23 %f22,%f23 %d22
4321 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4322 9 [SP+200] %f19 %f18,%f19 %d18
4323 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4324 7 [SP+184] %f15 %f14,%f15 %d14
4325 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4326 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4327 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4328 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4329 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4330 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4331 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4333 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4335 Integral arguments are always passed as 64 bit quantities appropriately
4338 Passing of floating point values is handled as follows.
4339 If a prototype is in scope:
4340 If the value is in a named argument (i.e. not a stdarg function or a
4341 value not part of the `...') then the value is passed in the appropriate
4343 If the value is part of the `...' and is passed in one of the first 6
4344 slots then the value is passed in the appropriate int reg.
4345 If the value is part of the `...' and is not passed in one of the first 6
4346 slots then the value is passed in memory.
4347 If a prototype is not in scope:
4348 If the value is one of the first 6 arguments the value is passed in the
4349 appropriate integer reg and the appropriate fp reg.
4350 If the value is not one of the first 6 arguments the value is passed in
4351 the appropriate fp reg and in memory.
4354 /* Maximum number of int regs for args. */
4355 #define SPARC_INT_ARG_MAX 6
4356 /* Maximum number of fp regs for args. */
4357 #define SPARC_FP_ARG_MAX 16
4359 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4361 /* Handle the INIT_CUMULATIVE_ARGS macro.
4362 Initialize a variable CUM of type CUMULATIVE_ARGS
4363 for a call to a function whose data type is FNTYPE.
4364 For a library call, FNTYPE is 0. */
4367 init_cumulative_args (cum, fntype, libname, indirect)
4368 CUMULATIVE_ARGS *cum;
4370 rtx libname ATTRIBUTE_UNUSED;
4371 int indirect ATTRIBUTE_UNUSED;
4374 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4375 cum->libcall_p = fntype == 0;
4378 /* Compute the slot number to pass an argument in.
4379 Returns the slot number or -1 if passing on the stack.
4381 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4382 the preceding args and about the function being called.
4383 MODE is the argument's machine mode.
4384 TYPE is the data type of the argument (as a tree).
4385 This is null for libcalls where that information may
4387 NAMED is nonzero if this argument is a named parameter
4388 (otherwise it is an extra parameter matching an ellipsis).
4389 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4390 *PREGNO records the register number to use if scalar type.
4391 *PPADDING records the amount of padding needed in words. */
4394 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
4395 const CUMULATIVE_ARGS *cum;
4396 enum machine_mode mode;
4403 int regbase = (incoming_p
4404 ? SPARC_INCOMING_INT_ARG_FIRST
4405 : SPARC_OUTGOING_INT_ARG_FIRST);
4406 int slotno = cum->words;
4411 if (type != 0 && TREE_ADDRESSABLE (type))
4414 && type != 0 && mode == BLKmode
4415 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4421 /* MODE is VOIDmode when generating the actual call.
4425 case QImode : case CQImode :
4426 case HImode : case CHImode :
4427 case SImode : case CSImode :
4428 case DImode : case CDImode :
4429 case TImode : case CTImode :
4430 if (slotno >= SPARC_INT_ARG_MAX)
4432 regno = regbase + slotno;
4435 case SFmode : case SCmode :
4436 case DFmode : case DCmode :
4437 case TFmode : case TCmode :
4440 if (slotno >= SPARC_INT_ARG_MAX)
4442 regno = regbase + slotno;
4446 if ((mode == TFmode || mode == TCmode)
4447 && (slotno & 1) != 0)
4448 slotno++, *ppadding = 1;
4449 if (TARGET_FPU && named)
4451 if (slotno >= SPARC_FP_ARG_MAX)
4453 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4459 if (slotno >= SPARC_INT_ARG_MAX)
4461 regno = regbase + slotno;
4467 /* For sparc64, objects requiring 16 byte alignment get it. */
4470 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
4471 slotno++, *ppadding = 1;
4475 || (type && TREE_CODE (type) == UNION_TYPE))
4477 if (slotno >= SPARC_INT_ARG_MAX)
4479 regno = regbase + slotno;
4484 int intregs_p = 0, fpregs_p = 0;
4485 /* The ABI obviously doesn't specify how packed
4486 structures are passed. These are defined to be passed
4487 in int regs if possible, otherwise memory. */
4490 /* First see what kinds of registers we need. */
4491 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4493 if (TREE_CODE (field) == FIELD_DECL)
4495 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4500 if (DECL_PACKED (field))
4504 if (packed_p || !named)
4505 fpregs_p = 0, intregs_p = 1;
4507 /* If all arg slots are filled, then must pass on stack. */
4508 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4510 /* If there are only int args and all int arg slots are filled,
4511 then must pass on stack. */
4512 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4514 /* Note that even if all int arg slots are filled, fp members may
4515 still be passed in regs if such regs are available.
4516 *PREGNO isn't set because there may be more than one, it's up
4517 to the caller to compute them. */
4530 /* Handle recursive register counting for structure field layout. */
4532 struct function_arg_record_value_parms
4535 int slotno, named, regbase;
4540 static void function_arg_record_value_3
4541 PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *));
4542 static void function_arg_record_value_2
4543 PARAMS ((tree, HOST_WIDE_INT,
4544 struct function_arg_record_value_parms *));
4545 static void function_arg_record_value_1
4546 PARAMS ((tree, HOST_WIDE_INT,
4547 struct function_arg_record_value_parms *));
4548 static rtx function_arg_record_value
4549 PARAMS ((tree, enum machine_mode, int, int, int));
4551 /* A subroutine of function_arg_record_value. Traverse the structure
4552 recusively and determine how many registers will be required. */
4555 function_arg_record_value_1 (type, startbitpos, parms)
4557 HOST_WIDE_INT startbitpos;
4558 struct function_arg_record_value_parms *parms;
4562 /* The ABI obviously doesn't specify how packed structures are
4563 passed. These are defined to be passed in int regs if possible,
4564 otherwise memory. */
4567 /* We need to compute how many registers are needed so we can
4568 allocate the PARALLEL but before we can do that we need to know
4569 whether there are any packed fields. If there are, int regs are
4570 used regardless of whether there are fp values present. */
4571 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4573 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4580 /* Compute how many registers we need. */
4581 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4583 if (TREE_CODE (field) == FIELD_DECL)
4585 HOST_WIDE_INT bitpos = startbitpos;
4587 if (DECL_SIZE (field) != 0
4588 && host_integerp (bit_position (field), 1))
4589 bitpos += int_bit_position (field);
4591 /* ??? FIXME: else assume zero offset. */
4593 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4594 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
4595 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4596 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4597 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4603 if (parms->intoffset != -1)
4605 int intslots, this_slotno;
4607 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
4609 this_slotno = parms->slotno + parms->intoffset
4612 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4613 intslots = MAX (intslots, 0);
4614 parms->nregs += intslots;
4615 parms->intoffset = -1;
4618 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4619 If it wasn't true we wouldn't be here. */
4621 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4626 if (parms->intoffset == -1)
4627 parms->intoffset = bitpos;
4633 /* A subroutine of function_arg_record_value. Assign the bits of the
4634 structure between parms->intoffset and bitpos to integer registers. */
4637 function_arg_record_value_3 (bitpos, parms)
4638 HOST_WIDE_INT bitpos;
4639 struct function_arg_record_value_parms *parms;
4641 enum machine_mode mode;
4643 unsigned int startbit, endbit;
4644 int this_slotno, intslots, intoffset;
4647 if (parms->intoffset == -1)
4650 intoffset = parms->intoffset;
4651 parms->intoffset = -1;
4653 startbit = intoffset & -BITS_PER_WORD;
4654 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4655 intslots = (endbit - startbit) / BITS_PER_WORD;
4656 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
4658 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4662 /* If this is the trailing part of a word, only load that much into
4663 the register. Otherwise load the whole register. Note that in
4664 the latter case we may pick up unwanted bits. It's not a problem
4665 at the moment but may wish to revisit. */
4667 if (intoffset % BITS_PER_WORD != 0)
4668 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4673 intoffset /= BITS_PER_UNIT;
4676 regno = parms->regbase + this_slotno;
4677 reg = gen_rtx_REG (mode, regno);
4678 XVECEXP (parms->ret, 0, parms->nregs)
4679 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4682 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4686 while (intslots > 0);
4689 /* A subroutine of function_arg_record_value. Traverse the structure
4690 recursively and assign bits to floating point registers. Track which
4691 bits in between need integer registers; invoke function_arg_record_value_3
4692 to make that happen. */
4695 function_arg_record_value_2 (type, startbitpos, parms)
4697 HOST_WIDE_INT startbitpos;
4698 struct function_arg_record_value_parms *parms;
4703 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4705 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4712 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4714 if (TREE_CODE (field) == FIELD_DECL)
4716 HOST_WIDE_INT bitpos = startbitpos;
4718 if (DECL_SIZE (field) != 0
4719 && host_integerp (bit_position (field), 1))
4720 bitpos += int_bit_position (field);
4722 /* ??? FIXME: else assume zero offset. */
4724 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4725 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
4726 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4727 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4728 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4734 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
4736 enum machine_mode mode = DECL_MODE (field);
4739 function_arg_record_value_3 (bitpos, parms);
4740 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
4741 + ((mode == SFmode || mode == SCmode)
4742 && (bitpos & 32) != 0);
4745 case SCmode: mode = SFmode; break;
4746 case DCmode: mode = DFmode; break;
4747 case TCmode: mode = TFmode; break;
4750 reg = gen_rtx_REG (mode, regno);
4751 XVECEXP (parms->ret, 0, parms->nregs)
4752 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4753 GEN_INT (bitpos / BITS_PER_UNIT));
4755 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4757 regno += GET_MODE_SIZE (mode) / 4;
4758 reg = gen_rtx_REG (mode, regno);
4759 XVECEXP (parms->ret, 0, parms->nregs)
4760 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4761 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
4768 if (parms->intoffset == -1)
4769 parms->intoffset = bitpos;
4775 /* Used by function_arg and function_value to implement the complex
4776 Sparc64 structure calling conventions. */
4779 function_arg_record_value (type, mode, slotno, named, regbase)
4781 enum machine_mode mode;
4782 int slotno, named, regbase;
4784 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4785 struct function_arg_record_value_parms parms;
4788 parms.ret = NULL_RTX;
4789 parms.slotno = slotno;
4790 parms.named = named;
4791 parms.regbase = regbase;
4793 /* Compute how many registers we need. */
4795 parms.intoffset = 0;
4796 function_arg_record_value_1 (type, 0, &parms);
4798 if (parms.intoffset != -1)
4800 unsigned int startbit, endbit;
4801 int intslots, this_slotno;
4803 startbit = parms.intoffset & -BITS_PER_WORD;
4804 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4805 intslots = (endbit - startbit) / BITS_PER_WORD;
4806 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
4808 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4809 intslots = MAX (intslots, 0);
4811 parms.nregs += intslots;
4813 nregs = parms.nregs;
4815 /* Allocate the vector and handle some annoying special cases. */
4818 /* ??? Empty structure has no value? Duh? */
4821 /* Though there's nothing really to store, return a word register
4822 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4823 leads to breakage due to the fact that there are zero bytes to
4825 return gen_rtx_REG (mode, regbase);
4829 /* ??? C++ has structures with no fields, and yet a size. Give up
4830 for now and pass everything back in integer registers. */
4831 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4833 if (nregs + slotno > SPARC_INT_ARG_MAX)
4834 nregs = SPARC_INT_ARG_MAX - slotno;
4839 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
4841 /* Fill in the entries. */
4843 parms.intoffset = 0;
4844 function_arg_record_value_2 (type, 0, &parms);
4845 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
4847 if (parms.nregs != nregs)
4853 /* Handle the FUNCTION_ARG macro.
4854 Determine where to put an argument to a function.
4855 Value is zero to push the argument on the stack,
4856 or a hard register in which to store the argument.
4858 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4859 the preceding args and about the function being called.
4860 MODE is the argument's machine mode.
4861 TYPE is the data type of the argument (as a tree).
4862 This is null for libcalls where that information may
4864 NAMED is nonzero if this argument is a named parameter
4865 (otherwise it is an extra parameter matching an ellipsis).
4866 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4869 function_arg (cum, mode, type, named, incoming_p)
4870 const CUMULATIVE_ARGS *cum;
4871 enum machine_mode mode;
4876 int regbase = (incoming_p
4877 ? SPARC_INCOMING_INT_ARG_FIRST
4878 : SPARC_OUTGOING_INT_ARG_FIRST);
4879 int slotno, regno, padding;
4882 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
4890 reg = gen_rtx_REG (mode, regno);
4894 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4895 but also have the slot allocated for them.
4896 If no prototype is in scope fp values in register slots get passed
4897 in two places, either fp regs and int regs or fp regs and memory. */
4898 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4899 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4900 && SPARC_FP_REG_P (regno))
4902 reg = gen_rtx_REG (mode, regno);
4903 if (cum->prototype_p || cum->libcall_p)
4905 /* "* 2" because fp reg numbers are recorded in 4 byte
4908 /* ??? This will cause the value to be passed in the fp reg and
4909 in the stack. When a prototype exists we want to pass the
4910 value in the reg but reserve space on the stack. That's an
4911 optimization, and is deferred [for a bit]. */
4912 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
4913 return gen_rtx_PARALLEL (mode,
4915 gen_rtx_EXPR_LIST (VOIDmode,
4916 NULL_RTX, const0_rtx),
4917 gen_rtx_EXPR_LIST (VOIDmode,
4921 /* ??? It seems that passing back a register even when past
4922 the area declared by REG_PARM_STACK_SPACE will allocate
4923 space appropriately, and will not copy the data onto the
4924 stack, exactly as we desire.
4926 This is due to locate_and_pad_parm being called in
4927 expand_call whenever reg_parm_stack_space > 0, which
4928 while benefical to our example here, would seem to be
4929 in error from what had been intended. Ho hum... -- r~ */
4937 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
4941 /* On incoming, we don't need to know that the value
4942 is passed in %f0 and %i0, and it confuses other parts
4943 causing needless spillage even on the simplest cases. */
4947 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
4948 + (regno - SPARC_FP_ARG_FIRST) / 2);
4950 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4951 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
4953 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4957 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4958 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4959 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4963 else if (type && TREE_CODE (type) == RECORD_TYPE)
4965 /* Structures up to 16 bytes in size are passed in arg slots on the
4966 stack and are promoted to registers where possible. */
4968 if (int_size_in_bytes (type) > 16)
4969 abort (); /* shouldn't get here */
4971 return function_arg_record_value (type, mode, slotno, named, regbase);
4973 else if (type && TREE_CODE (type) == UNION_TYPE)
4975 enum machine_mode mode;
4976 int bytes = int_size_in_bytes (type);
4981 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4982 reg = gen_rtx_REG (mode, regno);
4986 /* Scalar or complex int. */
4987 reg = gen_rtx_REG (mode, regno);
4993 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4994 For an arg passed partly in registers and partly in memory,
4995 this is the number of registers used.
4996 For args passed entirely in registers or entirely in memory, zero.
4998 Any arg that starts in the first 6 regs but won't entirely fit in them
4999 needs partial registers on v8. On v9, structures with integer
5000 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5001 values that begin in the last fp reg [where "last fp reg" varies with the
5002 mode] will be split between that reg and memory. */
5005 function_arg_partial_nregs (cum, mode, type, named)
5006 const CUMULATIVE_ARGS *cum;
5007 enum machine_mode mode;
5011 int slotno, regno, padding;
5013 /* We pass 0 for incoming_p here, it doesn't matter. */
5014 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5021 if ((slotno + (mode == BLKmode
5022 ? ROUND_ADVANCE (int_size_in_bytes (type))
5023 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5024 > NPARM_REGS (SImode))
5025 return NPARM_REGS (SImode) - slotno;
5030 if (type && AGGREGATE_TYPE_P (type))
5032 int size = int_size_in_bytes (type);
5033 int align = TYPE_ALIGN (type);
5036 slotno += slotno & 1;
5037 if (size > 8 && size <= 16
5038 && slotno == SPARC_INT_ARG_MAX - 1)
5041 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5042 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5045 if (GET_MODE_ALIGNMENT (mode) == 128)
5047 slotno += slotno & 1;
5048 if (slotno == SPARC_INT_ARG_MAX - 2)
5053 if (slotno == SPARC_INT_ARG_MAX - 1)
5057 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5059 if (GET_MODE_ALIGNMENT (mode) == 128)
5060 slotno += slotno & 1;
5061 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5069 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5070 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5071 quad-precision floats by invisible reference.
5072 v9: Aggregates greater than 16 bytes are passed by reference.
5073 For Pascal, also pass arrays by reference. */
5076 function_arg_pass_by_reference (cum, mode, type, named)
5077 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
5078 enum machine_mode mode;
5080 int named ATTRIBUTE_UNUSED;
5084 return ((type && AGGREGATE_TYPE_P (type))
5085 || mode == TFmode || mode == TCmode);
5089 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5090 /* Consider complex values as aggregates, so care for TCmode. */
5091 || GET_MODE_SIZE (mode) > 16
5093 && AGGREGATE_TYPE_P (type)
5094 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5098 /* Handle the FUNCTION_ARG_ADVANCE macro.
5099 Update the data in CUM to advance over an argument
5100 of mode MODE and data type TYPE.
5101 TYPE is null for libcalls where that information may not be available. */
5104 function_arg_advance (cum, mode, type, named)
5105 CUMULATIVE_ARGS *cum;
5106 enum machine_mode mode;
5110 int slotno, regno, padding;
5112 /* We pass 0 for incoming_p here, it doesn't matter. */
5113 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5115 /* If register required leading padding, add it. */
5117 cum->words += padding;
5121 cum->words += (mode != BLKmode
5122 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5123 : ROUND_ADVANCE (int_size_in_bytes (type)));
5127 if (type && AGGREGATE_TYPE_P (type))
5129 int size = int_size_in_bytes (type);
5133 else if (size <= 16)
5135 else /* passed by reference */
5138 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
5142 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5144 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
5148 cum->words += (mode != BLKmode
5149 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5150 : ROUND_ADVANCE (int_size_in_bytes (type)));
5155 /* Handle the FUNCTION_ARG_PADDING macro.
5156 For the 64 bit ABI structs are always stored left shifted in their
5160 function_arg_padding (mode, type)
5161 enum machine_mode mode;
5164 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5167 /* This is the default definition. */
5168 return (! BYTES_BIG_ENDIAN
5171 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5172 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
5173 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5174 ? downward : upward));
5177 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5178 For v9, function return values are subject to the same rules as arguments,
5179 except that up to 32-bytes may be returned in registers. */
5182 function_value (type, mode, incoming_p)
5184 enum machine_mode mode;
5188 int regbase = (incoming_p
5189 ? SPARC_OUTGOING_INT_ARG_FIRST
5190 : SPARC_INCOMING_INT_ARG_FIRST);
5192 if (TARGET_ARCH64 && type)
5194 if (TREE_CODE (type) == RECORD_TYPE)
5196 /* Structures up to 32 bytes in size are passed in registers,
5197 promoted to fp registers where possible. */
5199 if (int_size_in_bytes (type) > 32)
5200 abort (); /* shouldn't get here */
5202 return function_arg_record_value (type, mode, 0, 1, regbase);
5204 else if (AGGREGATE_TYPE_P (type))
5206 /* All other aggregate types are passed in an integer register
5207 in a mode corresponding to the size of the type. */
5208 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5213 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5218 && GET_MODE_CLASS (mode) == MODE_INT
5219 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5220 && type && ! AGGREGATE_TYPE_P (type))
5224 regno = BASE_RETURN_VALUE_REG (mode);
5226 regno = BASE_OUTGOING_VALUE_REG (mode);
5228 return gen_rtx_REG (mode, regno);
5231 /* Do what is necessary for `va_start'. We look at the current function
5232 to determine if stdarg or varargs is used and return the address of
5233 the first unnamed parameter. */
5236 sparc_builtin_saveregs ()
5238 int first_reg = current_function_args_info.words;
5242 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5243 emit_move_insn (gen_rtx_MEM (word_mode,
5244 gen_rtx_PLUS (Pmode,
5246 GEN_INT (FIRST_PARM_OFFSET (0)
5249 gen_rtx_REG (word_mode,
5250 BASE_INCOMING_ARG_REG (word_mode) + regno));
5252 address = gen_rtx_PLUS (Pmode,
5254 GEN_INT (FIRST_PARM_OFFSET (0)
5255 + UNITS_PER_WORD * first_reg));
5260 /* Implement `va_start' for varargs and stdarg. */
5263 sparc_va_start (stdarg_p, valist, nextarg)
5264 int stdarg_p ATTRIBUTE_UNUSED;
5268 nextarg = expand_builtin_saveregs ();
5269 std_expand_builtin_va_start (1, valist, nextarg);
5272 /* Implement `va_arg'. */
5275 sparc_va_arg (valist, type)
5278 HOST_WIDE_INT size, rsize, align;
5283 /* Round up sizeof(type) to a word. */
5284 size = int_size_in_bytes (type);
5285 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5290 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5291 align = 2 * UNITS_PER_WORD;
5293 if (AGGREGATE_TYPE_P (type))
5295 if ((unsigned HOST_WIDE_INT) size > 16)
5298 size = rsize = UNITS_PER_WORD;
5300 /* SPARC v9 ABI states that structures up to 8 bytes in size are
5301 given one 8 byte slot. */
5303 size = rsize = UNITS_PER_WORD;
5310 if (AGGREGATE_TYPE_P (type)
5311 || TYPE_MODE (type) == TFmode
5312 || TYPE_MODE (type) == TCmode)
5315 size = rsize = UNITS_PER_WORD;
5322 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5323 build_int_2 (align - 1, 0)));
5324 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5325 build_int_2 (-align, -1)));
5328 addr = incr = save_expr (incr);
5329 if (BYTES_BIG_ENDIAN && size < rsize)
5331 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5332 build_int_2 (rsize - size, 0)));
5334 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5335 build_int_2 (rsize, 0)));
5337 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5338 TREE_SIDE_EFFECTS (incr) = 1;
5339 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5341 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5343 /* If the address isn't aligned properly for the type,
5344 we may need to copy to a temporary.
5345 FIXME: This is inefficient. Usually we can do this
5348 && TYPE_ALIGN (type) > BITS_PER_WORD
5351 /* FIXME: We really need to specify that the temporary is live
5352 for the whole function because expand_builtin_va_arg wants
5353 the alias set to be get_varargs_alias_set (), but in this
5354 case the alias set is that for TYPE and if the memory gets
5355 reused it will be reused with alias set TYPE. */
5356 rtx tmp = assign_temp (type, 0, 1, 0);
5359 addr_rtx = force_reg (Pmode, addr_rtx);
5360 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5361 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5362 set_mem_align (addr_rtx, BITS_PER_WORD);
5363 tmp = shallow_copy_rtx (tmp);
5364 PUT_MODE (tmp, BLKmode);
5365 set_mem_alias_set (tmp, 0);
5367 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize));
5368 if (dest_addr != NULL_RTX)
5369 addr_rtx = dest_addr;
5371 addr_rtx = XCEXP (tmp, 0, MEM);
5376 addr_rtx = force_reg (Pmode, addr_rtx);
5377 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5378 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5384 /* Return the string to output a conditional branch to LABEL, which is
5385 the operand number of the label. OP is the conditional expression.
5386 XEXP (OP, 0) is assumed to be a condition code register (integer or
5387 floating point) and its mode specifies what kind of comparison we made.
5389 REVERSED is non-zero if we should reverse the sense of the comparison.
5391 ANNUL is non-zero if we should generate an annulling branch.
5393 NOOP is non-zero if we have to follow this branch by a noop.
5395 INSN, if set, is the insn. */
5398 output_cbranch (op, dest, label, reversed, annul, noop, insn)
5401 int reversed, annul, noop;
5404 static char string[50];
5405 enum rtx_code code = GET_CODE (op);
5406 rtx cc_reg = XEXP (op, 0);
5407 enum machine_mode mode = GET_MODE (cc_reg);
5408 const char *labelno, *branch;
5409 int spaces = 8, far;
5412 /* v9 branches are limited to +-1MB. If it is too far away,
5425 fbne,a,pn %fcc2, .LC29
5433 far = get_attr_length (insn) >= 3;
5436 /* Reversal of FP compares takes care -- an ordered compare
5437 becomes an unordered compare and vice versa. */
5438 if (mode == CCFPmode || mode == CCFPEmode)
5439 code = reverse_condition_maybe_unordered (code);
5441 code = reverse_condition (code);
5444 /* Start by writing the branch condition. */
5445 if (mode == CCFPmode || mode == CCFPEmode)
5496 /* ??? !v9: FP branches cannot be preceded by another floating point
5497 insn. Because there is currently no concept of pre-delay slots,
5498 we can fix this only by always emitting a nop before a floating
5503 strcpy (string, "nop\n\t");
5504 strcat (string, branch);
5517 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5529 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5550 strcpy (string, branch);
5552 spaces -= strlen (branch);
5553 p = strchr (string, '\0');
5555 /* Now add the annulling, the label, and a possible noop. */
5570 if (! far && insn && INSN_ADDRESSES_SET_P ())
5572 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5573 - INSN_ADDRESSES (INSN_UID (insn)));
5574 /* Leave some instructions for "slop". */
5575 if (delta < -260000 || delta >= 260000)
5579 if (mode == CCFPmode || mode == CCFPEmode)
5581 static char v9_fcc_labelno[] = "%%fccX, ";
5582 /* Set the char indicating the number of the fcc reg to use. */
5583 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5584 labelno = v9_fcc_labelno;
5587 if (REGNO (cc_reg) == SPARC_FCC_REG)
5593 else if (mode == CCXmode || mode == CCX_NOOVmode)
5595 labelno = "%%xcc, ";
5601 labelno = "%%icc, ";
5606 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5609 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5619 strcpy (p, labelno);
5620 p = strchr (p, '\0');
5623 strcpy (p, ".+12\n\tnop\n\tb\t");
5630 /* Set the char indicating the number of the operand containing the
5635 strcpy (p, "\n\tnop");
5640 /* Emit a library call comparison between floating point X and Y.
5641 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5642 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5643 values as arguments instead of the TFmode registers themselves,
5644 that's why we cannot call emit_float_lib_cmp. */
5646 sparc_emit_float_lib_cmp (x, y, comparison)
5648 enum rtx_code comparison;
5651 rtx slot0, slot1, result, tem, tem2;
5652 enum machine_mode mode;
5657 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
5661 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
5665 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
5669 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
5673 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
5677 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
5688 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
5698 if (GET_CODE (x) != MEM)
5700 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5701 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
5706 if (GET_CODE (y) != MEM)
5708 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5709 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
5714 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5716 XEXP (slot0, 0), Pmode,
5717 XEXP (slot1, 0), Pmode);
5723 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5725 x, TFmode, y, TFmode);
5731 /* Immediately move the result of the libcall into a pseudo
5732 register so reload doesn't clobber the value if it needs
5733 the return register for a spill reg. */
5734 result = gen_reg_rtx (mode);
5735 emit_move_insn (result, hard_libcall_value (mode));
5740 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
5744 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
5749 emit_cmp_insn (result, const1_rtx,
5750 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
5753 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
5756 tem = gen_reg_rtx (mode);
5758 emit_insn (gen_andsi3 (tem, result, const1_rtx));
5760 emit_insn (gen_anddi3 (tem, result, const1_rtx));
5761 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
5765 tem = gen_reg_rtx (mode);
5767 emit_insn (gen_addsi3 (tem, result, const1_rtx));
5769 emit_insn (gen_adddi3 (tem, result, const1_rtx));
5770 tem2 = gen_reg_rtx (mode);
5772 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
5774 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
5775 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
5781 /* Generate an unsigned DImode to FP conversion. This is the same code
5782 optabs would emit if we didn't have TFmode patterns. */
5785 sparc_emit_floatunsdi (operands)
5788 rtx neglab, donelab, i0, i1, f0, in, out;
5789 enum machine_mode mode;
5792 in = force_reg (DImode, operands[1]);
5793 mode = GET_MODE (out);
5794 neglab = gen_label_rtx ();
5795 donelab = gen_label_rtx ();
5796 i0 = gen_reg_rtx (DImode);
5797 i1 = gen_reg_rtx (DImode);
5798 f0 = gen_reg_rtx (mode);
5800 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
5802 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
5803 emit_jump_insn (gen_jump (donelab));
5806 emit_label (neglab);
5808 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
5809 emit_insn (gen_anddi3 (i1, in, const1_rtx));
5810 emit_insn (gen_iordi3 (i0, i0, i1));
5811 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
5812 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
5814 emit_label (donelab);
5817 /* Return the string to output a conditional branch to LABEL, testing
5818 register REG. LABEL is the operand number of the label; REG is the
5819 operand number of the reg. OP is the conditional expression. The mode
5820 of REG says what kind of comparison we made.
5822 REVERSED is non-zero if we should reverse the sense of the comparison.
5824 ANNUL is non-zero if we should generate an annulling branch.
5826 NOOP is non-zero if we have to follow this branch by a noop. */
5829 output_v9branch (op, dest, reg, label, reversed, annul, noop, insn)
5832 int reversed, annul, noop;
5835 static char string[50];
5836 enum rtx_code code = GET_CODE (op);
5837 enum machine_mode mode = GET_MODE (XEXP (op, 0));
5842 /* branch on register are limited to +-128KB. If it is too far away,
5855 brgez,a,pn %o1, .LC29
5861 ba,pt %xcc, .LC29 */
5863 far = get_attr_length (insn) >= 3;
5865 /* If not floating-point or if EQ or NE, we can just reverse the code. */
5867 code = reverse_condition (code);
5869 /* Only 64 bit versions of these instructions exist. */
5873 /* Start by writing the branch condition. */
5878 strcpy (string, "brnz");
5882 strcpy (string, "brz");
5886 strcpy (string, "brgez");
5890 strcpy (string, "brlz");
5894 strcpy (string, "brlez");
5898 strcpy (string, "brgz");
5905 p = strchr (string, '\0');
5907 /* Now add the annulling, reg, label, and nop. */
5914 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5917 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5922 *p = p < string + 8 ? '\t' : ' ';
5930 int veryfar = 1, delta;
5932 if (INSN_ADDRESSES_SET_P ())
5934 delta = (INSN_ADDRESSES (INSN_UID (dest))
5935 - INSN_ADDRESSES (INSN_UID (insn)));
5936 /* Leave some instructions for "slop". */
5937 if (delta >= -260000 && delta < 260000)
5941 strcpy (p, ".+12\n\tnop\n\t");
5952 strcpy (p, "ba,pt\t%%xcc, ");
5962 strcpy (p, "\n\tnop");
5967 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
5968 Such instructions cannot be used in the delay slot of return insn on v9.
5969 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
5973 epilogue_renumber (where, test)
5974 register rtx *where;
5977 register const char *fmt;
5979 register enum rtx_code code;
5984 code = GET_CODE (*where);
5989 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
5991 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
5992 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6000 /* Do not replace the frame pointer with the stack pointer because
6001 it can cause the delayed instruction to load below the stack.
6002 This occurs when instructions like:
6004 (set (reg/i:SI 24 %i0)
6005 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6006 (const_int -20 [0xffffffec])) 0))
6008 are in the return delayed slot. */
6010 if (GET_CODE (XEXP (*where, 0)) == REG
6011 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6012 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6013 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6018 if (SPARC_STACK_BIAS
6019 && GET_CODE (XEXP (*where, 0)) == REG
6020 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6028 fmt = GET_RTX_FORMAT (code);
6030 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6035 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6036 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6039 else if (fmt[i] == 'e'
6040 && epilogue_renumber (&(XEXP (*where, i)), test))
6046 /* Leaf functions and non-leaf functions have different needs. */
6049 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6052 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6054 static const int *const reg_alloc_orders[] = {
6055 reg_leaf_alloc_order,
6056 reg_nonleaf_alloc_order};
6059 order_regs_for_local_alloc ()
6061 static int last_order_nonleaf = 1;
6063 if (regs_ever_live[15] != last_order_nonleaf)
6065 last_order_nonleaf = !last_order_nonleaf;
6066 memcpy ((char *) reg_alloc_order,
6067 (const char *) reg_alloc_orders[last_order_nonleaf],
6068 FIRST_PSEUDO_REGISTER * sizeof (int));
6072 /* Return 1 if REG and MEM are legitimate enough to allow the various
6073 mem<-->reg splits to be run. */
6076 sparc_splitdi_legitimate (reg, mem)
6080 /* Punt if we are here by mistake. */
6081 if (! reload_completed)
6084 /* We must have an offsettable memory reference. */
6085 if (! offsettable_memref_p (mem))
6088 /* If we have legitimate args for ldd/std, we do not want
6089 the split to happen. */
6090 if ((REGNO (reg) % 2) == 0
6091 && mem_min_alignment (mem, 8))
6098 /* Return 1 if x and y are some kind of REG and they refer to
6099 different hard registers. This test is guarenteed to be
6100 run after reload. */
6103 sparc_absnegfloat_split_legitimate (x, y)
6106 if (GET_CODE (x) != REG)
6108 if (GET_CODE (y) != REG)
6110 if (REGNO (x) == REGNO (y))
6115 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6116 This makes them candidates for using ldd and std insns.
6118 Note reg1 and reg2 *must* be hard registers. */
6121 registers_ok_for_ldd_peep (reg1, reg2)
6124 /* We might have been passed a SUBREG. */
6125 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6128 if (REGNO (reg1) % 2 != 0)
6131 /* Integer ldd is deprecated in SPARC V9 */
6132 if (TARGET_V9 && REGNO (reg1) < 32)
6135 return (REGNO (reg1) == REGNO (reg2) - 1);
6138 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6141 This can only happen when addr1 and addr2, the addresses in mem1
6142 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6143 addr1 must also be aligned on a 64-bit boundary.
6145 Also iff dependent_reg_rtx is not null it should not be used to
6146 compute the address for mem1, i.e. we cannot optimize a sequence
6158 But, note that the transformation from:
6163 is perfectly fine. Thus, the peephole2 patterns always pass us
6164 the destination register of the first load, never the second one.
6166 For stores we don't have a similar problem, so dependent_reg_rtx is
6170 mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx)
6171 rtx mem1, mem2, dependent_reg_rtx;
6177 /* The mems cannot be volatile. */
6178 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6181 /* MEM1 should be aligned on a 64-bit boundary. */
6182 if (MEM_ALIGN (mem1) < 64)
6185 addr1 = XEXP (mem1, 0);
6186 addr2 = XEXP (mem2, 0);
6188 /* Extract a register number and offset (if used) from the first addr. */
6189 if (GET_CODE (addr1) == PLUS)
6191 /* If not a REG, return zero. */
6192 if (GET_CODE (XEXP (addr1, 0)) != REG)
6196 reg1 = REGNO (XEXP (addr1, 0));
6197 /* The offset must be constant! */
6198 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6200 offset1 = INTVAL (XEXP (addr1, 1));
6203 else if (GET_CODE (addr1) != REG)
6207 reg1 = REGNO (addr1);
6208 /* This was a simple (mem (reg)) expression. Offset is 0. */
6212 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6213 if (GET_CODE (addr2) != PLUS)
6216 if (GET_CODE (XEXP (addr2, 0)) != REG
6217 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6220 if (reg1 != REGNO (XEXP (addr2, 0)))
6223 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6226 /* The first offset must be evenly divisible by 8 to ensure the
6227 address is 64 bit aligned. */
6228 if (offset1 % 8 != 0)
6231 /* The offset for the second addr must be 4 more than the first addr. */
6232 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6235 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6240 /* Return 1 if reg is a pseudo, or is the first register in
6241 a hard register pair. This makes it a candidate for use in
6242 ldd and std insns. */
6245 register_ok_for_ldd (reg)
6248 /* We might have been passed a SUBREG. */
6249 if (GET_CODE (reg) != REG)
6252 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6253 return (REGNO (reg) % 2 == 0);
6258 /* Print operand X (an rtx) in assembler syntax to file FILE.
6259 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6260 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6263 print_operand (file, x, code)
6271 /* Output a 'nop' if there's nothing for the delay slot. */
6272 if (dbr_sequence_length () == 0)
6273 fputs ("\n\t nop", file);
6276 /* Output an annul flag if there's nothing for the delay slot and we
6277 are optimizing. This is always used with '(' below. */
6278 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6279 this is a dbx bug. So, we only do this when optimizing. */
6280 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6281 Always emit a nop in case the next instruction is a branch. */
6282 if (dbr_sequence_length () == 0
6283 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6287 /* Output a 'nop' if there's nothing for the delay slot and we are
6288 not optimizing. This is always used with '*' above. */
6289 if (dbr_sequence_length () == 0
6290 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6291 fputs ("\n\t nop", file);
6294 /* Output the Embedded Medium/Anywhere code model base register. */
6295 fputs (EMBMEDANY_BASE_REG, file);
6298 /* Print out what we are using as the frame pointer. This might
6299 be %fp, or might be %sp+offset. */
6300 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6301 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
6304 /* Adjust the operand to take into account a RESTORE operation. */
6305 if (GET_CODE (x) == CONST_INT)
6307 else if (GET_CODE (x) != REG)
6308 output_operand_lossage ("invalid %%Y operand");
6309 else if (REGNO (x) < 8)
6310 fputs (reg_names[REGNO (x)], file);
6311 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6312 fputs (reg_names[REGNO (x)-16], file);
6314 output_operand_lossage ("invalid %%Y operand");
6317 /* Print out the low order register name of a register pair. */
6318 if (WORDS_BIG_ENDIAN)
6319 fputs (reg_names[REGNO (x)+1], file);
6321 fputs (reg_names[REGNO (x)], file);
6324 /* Print out the high order register name of a register pair. */
6325 if (WORDS_BIG_ENDIAN)
6326 fputs (reg_names[REGNO (x)], file);
6328 fputs (reg_names[REGNO (x)+1], file);
6331 /* Print out the second register name of a register pair or quad.
6332 I.e., R (%o0) => %o1. */
6333 fputs (reg_names[REGNO (x)+1], file);
6336 /* Print out the third register name of a register quad.
6337 I.e., S (%o0) => %o2. */
6338 fputs (reg_names[REGNO (x)+2], file);
6341 /* Print out the fourth register name of a register quad.
6342 I.e., T (%o0) => %o3. */
6343 fputs (reg_names[REGNO (x)+3], file);
6346 /* Print a condition code register. */
6347 if (REGNO (x) == SPARC_ICC_REG)
6349 /* We don't handle CC[X]_NOOVmode because they're not supposed
6351 if (GET_MODE (x) == CCmode)
6352 fputs ("%icc", file);
6353 else if (GET_MODE (x) == CCXmode)
6354 fputs ("%xcc", file);
6359 /* %fccN register */
6360 fputs (reg_names[REGNO (x)], file);
6363 /* Print the operand's address only. */
6364 output_address (XEXP (x, 0));
6367 /* In this case we need a register. Use %g0 if the
6368 operand is const0_rtx. */
6370 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
6372 fputs ("%g0", file);
6379 switch (GET_CODE (x))
6381 case IOR: fputs ("or", file); break;
6382 case AND: fputs ("and", file); break;
6383 case XOR: fputs ("xor", file); break;
6384 default: output_operand_lossage ("invalid %%A operand");
6389 switch (GET_CODE (x))
6391 case IOR: fputs ("orn", file); break;
6392 case AND: fputs ("andn", file); break;
6393 case XOR: fputs ("xnor", file); break;
6394 default: output_operand_lossage ("invalid %%B operand");
6398 /* These are used by the conditional move instructions. */
6402 enum rtx_code rc = GET_CODE (x);
6406 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6407 if (mode == CCFPmode || mode == CCFPEmode)
6408 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6410 rc = reverse_condition (GET_CODE (x));
6414 case NE: fputs ("ne", file); break;
6415 case EQ: fputs ("e", file); break;
6416 case GE: fputs ("ge", file); break;
6417 case GT: fputs ("g", file); break;
6418 case LE: fputs ("le", file); break;
6419 case LT: fputs ("l", file); break;
6420 case GEU: fputs ("geu", file); break;
6421 case GTU: fputs ("gu", file); break;
6422 case LEU: fputs ("leu", file); break;
6423 case LTU: fputs ("lu", file); break;
6424 case LTGT: fputs ("lg", file); break;
6425 case UNORDERED: fputs ("u", file); break;
6426 case ORDERED: fputs ("o", file); break;
6427 case UNLT: fputs ("ul", file); break;
6428 case UNLE: fputs ("ule", file); break;
6429 case UNGT: fputs ("ug", file); break;
6430 case UNGE: fputs ("uge", file); break;
6431 case UNEQ: fputs ("ue", file); break;
6432 default: output_operand_lossage (code == 'c'
6433 ? "invalid %%c operand"
6434 : "invalid %%C operand");
6439 /* These are used by the movr instruction pattern. */
6443 enum rtx_code rc = (code == 'd'
6444 ? reverse_condition (GET_CODE (x))
6448 case NE: fputs ("ne", file); break;
6449 case EQ: fputs ("e", file); break;
6450 case GE: fputs ("gez", file); break;
6451 case LT: fputs ("lz", file); break;
6452 case LE: fputs ("lez", file); break;
6453 case GT: fputs ("gz", file); break;
6454 default: output_operand_lossage (code == 'd'
6455 ? "invalid %%d operand"
6456 : "invalid %%D operand");
6463 /* Print a sign-extended character. */
6464 int i = trunc_int_for_mode (INTVAL (x), QImode);
6465 fprintf (file, "%d", i);
6470 /* Operand must be a MEM; write its address. */
6471 if (GET_CODE (x) != MEM)
6472 output_operand_lossage ("invalid %%f operand");
6473 output_address (XEXP (x, 0));
6477 /* Do nothing special. */
6481 /* Undocumented flag. */
6482 output_operand_lossage ("invalid operand output code");
6485 if (GET_CODE (x) == REG)
6486 fputs (reg_names[REGNO (x)], file);
6487 else if (GET_CODE (x) == MEM)
6490 /* Poor Sun assembler doesn't understand absolute addressing. */
6491 if (CONSTANT_P (XEXP (x, 0)))
6492 fputs ("%g0+", file);
6493 output_address (XEXP (x, 0));
6496 else if (GET_CODE (x) == HIGH)
6498 fputs ("%hi(", file);
6499 output_addr_const (file, XEXP (x, 0));
6502 else if (GET_CODE (x) == LO_SUM)
6504 print_operand (file, XEXP (x, 0), 0);
6505 if (TARGET_CM_MEDMID)
6506 fputs ("+%l44(", file);
6508 fputs ("+%lo(", file);
6509 output_addr_const (file, XEXP (x, 1));
6512 else if (GET_CODE (x) == CONST_DOUBLE
6513 && (GET_MODE (x) == VOIDmode
6514 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
6516 if (CONST_DOUBLE_HIGH (x) == 0)
6517 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
6518 else if (CONST_DOUBLE_HIGH (x) == -1
6519 && CONST_DOUBLE_LOW (x) < 0)
6520 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
6522 output_operand_lossage ("long long constant not a valid immediate operand");
6524 else if (GET_CODE (x) == CONST_DOUBLE)
6525 output_operand_lossage ("floating point constant not a valid immediate operand");
6526 else { output_addr_const (file, x); }
6529 /* Target hook for assembling integer objects. The sparc version has
6530 special handling for aligned DI-mode objects. */
6533 sparc_assemble_integer (x, size, aligned_p)
6538 /* ??? We only output .xword's for symbols and only then in environments
6539 where the assembler can handle them. */
6540 if (aligned_p && size == 8
6541 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
6545 assemble_integer_with_op ("\t.xword\t", x);
6550 assemble_aligned_integer (4, const0_rtx);
6551 assemble_aligned_integer (4, x);
6555 return default_assemble_integer (x, size, aligned_p);
6558 /* Return the value of a code used in the .proc pseudo-op that says
6559 what kind of result this function returns. For non-C types, we pick
6560 the closest C type. */
6562 #ifndef SHORT_TYPE_SIZE
6563 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6566 #ifndef INT_TYPE_SIZE
6567 #define INT_TYPE_SIZE BITS_PER_WORD
6570 #ifndef LONG_TYPE_SIZE
6571 #define LONG_TYPE_SIZE BITS_PER_WORD
6574 #ifndef LONG_LONG_TYPE_SIZE
6575 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6578 #ifndef FLOAT_TYPE_SIZE
6579 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6582 #ifndef DOUBLE_TYPE_SIZE
6583 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6586 #ifndef LONG_DOUBLE_TYPE_SIZE
6587 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6591 sparc_type_code (type)
6594 register unsigned long qualifiers = 0;
6595 register unsigned shift;
6597 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6598 setting more, since some assemblers will give an error for this. Also,
6599 we must be careful to avoid shifts of 32 bits or more to avoid getting
6600 unpredictable results. */
6602 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
6604 switch (TREE_CODE (type))
6610 qualifiers |= (3 << shift);
6615 qualifiers |= (2 << shift);
6619 case REFERENCE_TYPE:
6621 qualifiers |= (1 << shift);
6625 return (qualifiers | 8);
6628 case QUAL_UNION_TYPE:
6629 return (qualifiers | 9);
6632 return (qualifiers | 10);
6635 return (qualifiers | 16);
6638 /* If this is a range type, consider it to be the underlying
6640 if (TREE_TYPE (type) != 0)
6643 /* Carefully distinguish all the standard types of C,
6644 without messing up if the language is not C. We do this by
6645 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6646 look at both the names and the above fields, but that's redundant.
6647 Any type whose size is between two C types will be considered
6648 to be the wider of the two types. Also, we do not have a
6649 special code to use for "long long", so anything wider than
6650 long is treated the same. Note that we can't distinguish
6651 between "int" and "long" in this code if they are the same
6652 size, but that's fine, since neither can the assembler. */
6654 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
6655 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
6657 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
6658 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
6660 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
6661 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
6664 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
6667 /* If this is a range type, consider it to be the underlying
6669 if (TREE_TYPE (type) != 0)
6672 /* Carefully distinguish all the standard types of C,
6673 without messing up if the language is not C. */
6675 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
6676 return (qualifiers | 6);
6679 return (qualifiers | 7);
6681 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
6682 /* ??? We need to distinguish between double and float complex types,
6683 but I don't know how yet because I can't reach this code from
6684 existing front-ends. */
6685 return (qualifiers | 7); /* Who knows? */
6687 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
6688 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
6689 case FILE_TYPE: /* GNU Pascal FILE type. */
6690 case SET_TYPE: /* GNU Pascal SET type. */
6691 case LANG_TYPE: /* ? */
6695 abort (); /* Not a type! */
6702 /* Nested function support. */
6704 /* Emit RTL insns to initialize the variable parts of a trampoline.
6705 FNADDR is an RTX for the address of the function's pure code.
6706 CXT is an RTX for the static chain value for the function.
6708 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6709 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6710 (to store insns). This is a bit excessive. Perhaps a different
6711 mechanism would be better here.
6713 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6716 sparc_initialize_trampoline (tramp, fnaddr, cxt)
6717 rtx tramp, fnaddr, cxt;
6719 /* SPARC 32 bit trampoline:
6722 sethi %hi(static), %g2
6724 or %g2, %lo(static), %g2
6726 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6727 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6729 #ifdef TRANSFER_FROM_TRAMPOLINE
6730 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6731 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
6735 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
6736 expand_binop (SImode, ior_optab,
6737 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
6738 size_int (10), 0, 1),
6739 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
6740 NULL_RTX, 1, OPTAB_DIRECT));
6743 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6744 expand_binop (SImode, ior_optab,
6745 expand_shift (RSHIFT_EXPR, SImode, cxt,
6746 size_int (10), 0, 1),
6747 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
6748 NULL_RTX, 1, OPTAB_DIRECT));
6751 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6752 expand_binop (SImode, ior_optab,
6753 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
6754 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
6755 NULL_RTX, 1, OPTAB_DIRECT));
6758 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6759 expand_binop (SImode, ior_optab,
6760 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
6761 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
6762 NULL_RTX, 1, OPTAB_DIRECT));
6764 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6765 aligned on a 16 byte boundary so one flush clears it all. */
6766 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
6767 if (sparc_cpu != PROCESSOR_ULTRASPARC
6768 && sparc_cpu != PROCESSOR_ULTRASPARC3)
6769 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
6770 plus_constant (tramp, 8)))));
6773 /* The 64 bit version is simpler because it makes more sense to load the
6774 values as "immediate" data out of the trampoline. It's also easier since
6775 we can read the PC without clobbering a register. */
6778 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
6779 rtx tramp, fnaddr, cxt;
6781 #ifdef TRANSFER_FROM_TRAMPOLINE
6782 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6783 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
6794 emit_move_insn (gen_rtx_MEM (SImode, tramp),
6795 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
6796 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6797 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
6798 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6799 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
6800 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6801 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
6802 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
6803 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
6804 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
6806 if (sparc_cpu != PROCESSOR_ULTRASPARC
6807 && sparc_cpu != PROCESSOR_ULTRASPARC3)
6808 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
6811 /* Subroutines to support a flat (single) register window calling
6814 /* Single-register window sparc stack frames look like:
6816 Before call After call
6817 +-----------------------+ +-----------------------+
6819 mem | caller's temps. | | caller's temps. |
6821 +-----------------------+ +-----------------------+
6823 | arguments on stack. | | arguments on stack. |
6825 +-----------------------+FP+92->+-----------------------+
6826 | 6 words to save | | 6 words to save |
6827 | arguments passed | | arguments passed |
6828 | in registers, even | | in registers, even |
6829 | if not passed. | | if not passed. |
6830 SP+68->+-----------------------+FP+68->+-----------------------+
6831 | 1 word struct addr | | 1 word struct addr |
6832 +-----------------------+FP+64->+-----------------------+
6834 | 16 word reg save area | | 16 word reg save area |
6836 SP->+-----------------------+ FP->+-----------------------+
6838 | fp/alu reg moves |
6839 FP-16->+-----------------------+
6843 +-----------------------+
6845 | fp register save |
6847 +-----------------------+
6849 | gp register save |
6851 +-----------------------+
6853 | alloca allocations |
6855 +-----------------------+
6857 | arguments on stack |
6859 SP+92->+-----------------------+
6861 | arguments passed |
6862 | in registers, even |
6863 low | if not passed. |
6864 memory SP+68->+-----------------------+
6865 | 1 word struct addr |
6866 SP+64->+-----------------------+
6868 I 16 word reg save area |
6870 SP->+-----------------------+ */
6872 /* Structure to be filled in by sparc_flat_compute_frame_size with register
6873 save masks, and offsets for the current function. */
6875 struct sparc_frame_info
6877 unsigned long total_size; /* # bytes that the entire frame takes up. */
6878 unsigned long var_size; /* # bytes that variables take up. */
6879 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6880 unsigned long extra_size; /* # bytes of extra gunk. */
6881 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6882 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6883 unsigned long gmask; /* Mask of saved gp registers. */
6884 unsigned long fmask; /* Mask of saved fp registers. */
6885 unsigned long reg_offset; /* Offset from new sp to store regs. */
6886 int initialized; /* Nonzero if frame size already calculated. */
6889 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6890 struct sparc_frame_info current_frame_info;
6892 /* Zero structure to initialize current_frame_info. */
6893 struct sparc_frame_info zero_frame_info;
6895 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6897 #define RETURN_ADDR_REGNUM 15
6898 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
6899 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6901 #define MUST_SAVE_REGISTER(regno) \
6902 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6903 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
6904 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6906 /* Return the bytes needed to compute the frame pointer from the current
6910 sparc_flat_compute_frame_size (size)
6911 int size; /* # of var. bytes allocated. */
6914 unsigned long total_size; /* # bytes that the entire frame takes up. */
6915 unsigned long var_size; /* # bytes that variables take up. */
6916 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6917 unsigned long extra_size; /* # extra bytes. */
6918 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6919 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6920 unsigned long gmask; /* Mask of saved gp registers. */
6921 unsigned long fmask; /* Mask of saved fp registers. */
6922 unsigned long reg_offset; /* Offset to register save area. */
6923 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
6925 /* This is the size of the 16 word reg save area, 1 word struct addr
6926 area, and 4 word fp/alu register copy area. */
6927 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
6937 if (!leaf_function_p ())
6939 /* Also include the size needed for the 6 parameter registers. */
6940 args_size = current_function_outgoing_args_size + 24;
6942 total_size = var_size + args_size;
6944 /* Calculate space needed for gp registers. */
6945 for (regno = 1; regno <= 31; regno++)
6947 if (MUST_SAVE_REGISTER (regno))
6949 /* If we need to save two regs in a row, ensure there's room to bump
6950 up the address to align it to a doubleword boundary. */
6951 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
6953 if (gp_reg_size % 8 != 0)
6955 gp_reg_size += 2 * UNITS_PER_WORD;
6956 gmask |= 3 << regno;
6962 gp_reg_size += UNITS_PER_WORD;
6963 gmask |= 1 << regno;
6968 /* Calculate space needed for fp registers. */
6969 for (regno = 32; regno <= 63; regno++)
6971 if (regs_ever_live[regno] && !call_used_regs[regno])
6973 fp_reg_size += UNITS_PER_WORD;
6974 fmask |= 1 << (regno - 32);
6981 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
6982 /* Ensure save area is 8 byte aligned if we need it. */
6984 if (need_aligned_p && n != 0)
6986 total_size += 8 - n;
6987 reg_offset += 8 - n;
6989 total_size += gp_reg_size + fp_reg_size;
6992 /* If we must allocate a stack frame at all, we must also allocate
6993 room for register window spillage, so as to be binary compatible
6994 with libraries and operating systems that do not use -mflat. */
6996 total_size += extra_size;
7000 total_size = SPARC_STACK_ALIGN (total_size);
7002 /* Save other computed information. */
7003 current_frame_info.total_size = total_size;
7004 current_frame_info.var_size = var_size;
7005 current_frame_info.args_size = args_size;
7006 current_frame_info.extra_size = extra_size;
7007 current_frame_info.gp_reg_size = gp_reg_size;
7008 current_frame_info.fp_reg_size = fp_reg_size;
7009 current_frame_info.gmask = gmask;
7010 current_frame_info.fmask = fmask;
7011 current_frame_info.reg_offset = reg_offset;
7012 current_frame_info.initialized = reload_completed;
7014 /* Ok, we're done. */
7018 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7021 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7022 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7023 [BASE_REG+OFFSET] will always be a valid address.
7025 WORD_OP is either "st" for save, "ld" for restore.
7026 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7029 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
7030 doubleword_op, base_offset)
7032 const char *base_reg;
7033 unsigned int offset;
7034 unsigned long gmask;
7035 unsigned long fmask;
7036 const char *word_op;
7037 const char *doubleword_op;
7038 unsigned long base_offset;
7042 if (gmask == 0 && fmask == 0)
7045 /* Save registers starting from high to low. We've already saved the
7046 previous frame pointer and previous return address for the debugger's
7047 sake. The debugger allows us to not need a nop in the epilog if at least
7048 one register is reloaded in addition to return address. */
7052 for (regno = 1; regno <= 31; regno++)
7054 if ((gmask & (1L << regno)) != 0)
7056 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7058 /* We can save two registers in a row. If we're not at a
7059 double word boundary, move to one.
7060 sparc_flat_compute_frame_size ensures there's room to do
7062 if (offset % 8 != 0)
7063 offset += UNITS_PER_WORD;
7065 if (word_op[0] == 's')
7067 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7068 doubleword_op, reg_names[regno],
7070 if (dwarf2out_do_frame ())
7072 char *l = dwarf2out_cfi_label ();
7073 dwarf2out_reg_save (l, regno, offset + base_offset);
7075 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7079 fprintf (file, "\t%s\t[%s+%d], %s\n",
7080 doubleword_op, base_reg, offset,
7083 offset += 2 * UNITS_PER_WORD;
7088 if (word_op[0] == 's')
7090 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7091 word_op, reg_names[regno],
7093 if (dwarf2out_do_frame ())
7094 dwarf2out_reg_save ("", regno, offset + base_offset);
7097 fprintf (file, "\t%s\t[%s+%d], %s\n",
7098 word_op, base_reg, offset, reg_names[regno]);
7100 offset += UNITS_PER_WORD;
7108 for (regno = 32; regno <= 63; regno++)
7110 if ((fmask & (1L << (regno - 32))) != 0)
7112 if (word_op[0] == 's')
7114 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7115 word_op, reg_names[regno],
7117 if (dwarf2out_do_frame ())
7118 dwarf2out_reg_save ("", regno, offset + base_offset);
7121 fprintf (file, "\t%s\t[%s+%d], %s\n",
7122 word_op, base_reg, offset, reg_names[regno]);
7124 offset += UNITS_PER_WORD;
7130 /* Set up the stack and frame (if desired) for the function. */
7133 sparc_flat_function_prologue (file, size)
7137 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7138 unsigned long gmask = current_frame_info.gmask;
7140 sparc_output_scratch_registers (file);
7142 /* This is only for the human reader. */
7143 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7144 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7146 current_frame_info.var_size,
7147 current_frame_info.gp_reg_size / 4,
7148 current_frame_info.fp_reg_size / 4,
7149 current_function_outgoing_args_size,
7150 current_frame_info.extra_size);
7152 size = SPARC_STACK_ALIGN (size);
7153 size = (! current_frame_info.initialized
7154 ? sparc_flat_compute_frame_size (size)
7155 : current_frame_info.total_size);
7157 /* These cases shouldn't happen. Catch them now. */
7158 if (size == 0 && (gmask || current_frame_info.fmask))
7161 /* Allocate our stack frame by decrementing %sp.
7162 At present, the only algorithm gdb can use to determine if this is a
7163 flat frame is if we always set %i7 if we set %sp. This can be optimized
7164 in the future by putting in some sort of debugging information that says
7165 this is a `flat' function. However, there is still the case of debugging
7166 code without such debugging information (including cases where most fns
7167 have such info, but there is one that doesn't). So, always do this now
7168 so we don't get a lot of code out there that gdb can't handle.
7169 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7170 distinguish us from a non-flat function but there won't (and shouldn't)
7171 be any differences anyway. The return pc is saved (if necessary) right
7172 after %i7 so gdb won't have to look too far to find it. */
7175 unsigned int reg_offset = current_frame_info.reg_offset;
7176 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7177 static const char *const t1_str = "%g1";
7179 /* Things get a little tricky if local variables take up more than ~4096
7180 bytes and outgoing arguments take up more than ~4096 bytes. When that
7181 happens, the register save area can't be accessed from either end of
7182 the frame. Handle this by decrementing %sp to the start of the gp
7183 register save area, save the regs, update %i7, and then set %sp to its
7184 final value. Given that we only have one scratch register to play
7185 with it is the cheapest solution, and it helps gdb out as it won't
7186 slow down recognition of flat functions.
7187 Don't change the order of insns emitted here without checking with
7188 the gdb folk first. */
7190 /* Is the entire register save area offsettable from %sp? */
7191 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7195 fprintf (file, "\tadd\t%s, %d, %s\n",
7196 sp_str, (int) -size, sp_str);
7197 if (gmask & HARD_FRAME_POINTER_MASK)
7199 fprintf (file, "\tst\t%s, [%s+%d]\n",
7200 fp_str, sp_str, reg_offset);
7201 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7202 sp_str, (int) -size, fp_str, ASM_COMMENT_START);
7208 fprintf (file, "\tset\t");
7209 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7210 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7211 t1_str, sp_str, t1_str, sp_str);
7212 if (gmask & HARD_FRAME_POINTER_MASK)
7214 fprintf (file, "\tst\t%s, [%s+%d]\n",
7215 fp_str, sp_str, reg_offset);
7216 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7217 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7221 if (dwarf2out_do_frame ())
7223 char *l = dwarf2out_cfi_label ();
7224 if (gmask & HARD_FRAME_POINTER_MASK)
7226 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7227 reg_offset - 4 - size);
7228 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7231 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7233 if (gmask & RETURN_ADDR_MASK)
7235 fprintf (file, "\tst\t%s, [%s+%d]\n",
7236 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7237 if (dwarf2out_do_frame ())
7238 dwarf2out_return_save ("", reg_offset - size);
7241 sparc_flat_save_restore (file, sp_str, reg_offset,
7242 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7243 current_frame_info.fmask,
7244 "st", "std", -size);
7248 /* Subtract %sp in two steps, but make sure there is always a
7249 64 byte register save area, and %sp is properly aligned. */
7250 /* Amount to decrement %sp by, the first time. */
7251 unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7252 /* Offset to register save area from %sp. */
7253 unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset);
7257 fprintf (file, "\tadd\t%s, %d, %s\n",
7258 sp_str, (int) -size1, sp_str);
7259 if (gmask & HARD_FRAME_POINTER_MASK)
7261 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7262 fp_str, sp_str, (int) offset, sp_str, (int) -size1,
7263 fp_str, ASM_COMMENT_START);
7269 fprintf (file, "\tset\t");
7270 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1);
7271 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7272 t1_str, sp_str, t1_str, sp_str);
7273 if (gmask & HARD_FRAME_POINTER_MASK)
7275 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7276 fp_str, sp_str, (int) offset, sp_str, t1_str,
7277 fp_str, ASM_COMMENT_START);
7281 if (dwarf2out_do_frame ())
7283 char *l = dwarf2out_cfi_label ();
7284 if (gmask & HARD_FRAME_POINTER_MASK)
7286 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7287 offset - 4 - size1);
7288 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7291 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7293 if (gmask & RETURN_ADDR_MASK)
7295 fprintf (file, "\tst\t%s, [%s+%d]\n",
7296 reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset);
7297 if (dwarf2out_do_frame ())
7298 /* offset - size1 == reg_offset - size
7299 if reg_offset were updated above like offset. */
7300 dwarf2out_return_save ("", offset - size1);
7303 sparc_flat_save_restore (file, sp_str, offset,
7304 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7305 current_frame_info.fmask,
7306 "st", "std", -size1);
7307 fprintf (file, "\tset\t");
7308 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size - size1);
7309 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7310 t1_str, sp_str, t1_str, sp_str);
7311 if (dwarf2out_do_frame ())
7312 if (! (gmask & HARD_FRAME_POINTER_MASK))
7313 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
7317 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
7320 /* Do any necessary cleanup after a function to restore stack, frame,
7324 sparc_flat_function_epilogue (file, size)
7328 rtx epilogue_delay = current_function_epilogue_delay_list;
7329 int noepilogue = FALSE;
7331 /* This is only for the human reader. */
7332 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
7334 /* The epilogue does not depend on any registers, but the stack
7335 registers, so we assume that if we have 1 pending nop, it can be
7336 ignored, and 2 it must be filled (2 nops occur for integer
7337 multiply and divide). */
7339 size = SPARC_STACK_ALIGN (size);
7340 size = (!current_frame_info.initialized
7341 ? sparc_flat_compute_frame_size (size)
7342 : current_frame_info.total_size);
7344 if (size == 0 && epilogue_delay == 0)
7346 rtx insn = get_last_insn ();
7348 /* If the last insn was a BARRIER, we don't have to write any code
7349 because a jump (aka return) was put there. */
7350 if (GET_CODE (insn) == NOTE)
7351 insn = prev_nonnote_insn (insn);
7352 if (insn && GET_CODE (insn) == BARRIER)
7358 unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset;
7359 unsigned HOST_WIDE_INT size1;
7360 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7361 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7362 static const char *const t1_str = "%g1";
7364 /* In the reload sequence, we don't need to fill the load delay
7365 slots for most of the loads, also see if we can fill the final
7366 delay slot if not otherwise filled by the reload sequence. */
7370 fprintf (file, "\tset\t");
7371 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7372 fprintf (file, ", %s\n", t1_str);
7375 if (frame_pointer_needed)
7378 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7379 fp_str, t1_str, sp_str, ASM_COMMENT_START);
7381 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
7382 fp_str, (int) size, sp_str, ASM_COMMENT_START);
7385 /* Is the entire register save area offsettable from %sp? */
7386 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7392 /* Restore %sp in two steps, but make sure there is always a
7393 64 byte register save area, and %sp is properly aligned. */
7394 /* Amount to increment %sp by, the first time. */
7395 size1 = ((reg_offset - 64 - 16) + 15) & -16;
7396 /* Offset to register save area from %sp. */
7397 reg_offset = size1 - reg_offset;
7399 fprintf (file, "\tset\t");
7400 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1);
7401 fprintf (file, ", %s\n\tadd\t%s, %s, %s\n",
7402 t1_str, sp_str, t1_str, sp_str);
7405 /* We must restore the frame pointer and return address reg first
7406 because they are treated specially by the prologue output code. */
7407 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
7409 fprintf (file, "\tld\t[%s+%d], %s\n",
7410 sp_str, (int) reg_offset, fp_str);
7413 if (current_frame_info.gmask & RETURN_ADDR_MASK)
7415 fprintf (file, "\tld\t[%s+%d], %s\n",
7416 sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]);
7420 /* Restore any remaining saved registers. */
7421 sparc_flat_save_restore (file, sp_str, reg_offset,
7422 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7423 current_frame_info.fmask,
7426 /* If we had to increment %sp in two steps, record it so the second
7427 restoration in the epilogue finishes up. */
7433 fprintf (file, "\tset\t");
7434 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7435 fprintf (file, ", %s\n", t1_str);
7439 if (current_function_returns_struct)
7440 fprintf (file, "\tjmp\t%%o7+12\n");
7442 fprintf (file, "\tretl\n");
7444 /* If the only register saved is the return address, we need a
7445 nop, unless we have an instruction to put into it. Otherwise
7446 we don't since reloading multiple registers doesn't reference
7447 the register being loaded. */
7453 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
7456 else if (size > 4095)
7457 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7460 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str);
7463 fprintf (file, "\tnop\n");
7466 /* Reset state info for each function. */
7467 current_frame_info = zero_frame_info;
7469 sparc_output_deferred_case_vectors ();
7472 /* Define the number of delay slots needed for the function epilogue.
7474 On the sparc, we need a slot if either no stack has been allocated,
7475 or the only register saved is the return register. */
7478 sparc_flat_epilogue_delay_slots ()
7480 if (!current_frame_info.initialized)
7481 (void) sparc_flat_compute_frame_size (get_frame_size ());
7483 if (current_frame_info.total_size == 0)
7489 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7490 Any single length instruction which doesn't reference the stack or frame
7494 sparc_flat_eligible_for_epilogue_delay (trial, slot)
7496 int slot ATTRIBUTE_UNUSED;
7498 rtx pat = PATTERN (trial);
7500 if (get_attr_length (trial) != 1)
7503 if (! reg_mentioned_p (stack_pointer_rtx, pat)
7504 && ! reg_mentioned_p (frame_pointer_rtx, pat))
7510 /* Adjust the cost of a scheduling dependency. Return the new cost of
7511 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7514 supersparc_adjust_cost (insn, link, dep_insn, cost)
7520 enum attr_type insn_type;
7522 if (! recog_memoized (insn))
7525 insn_type = get_attr_type (insn);
7527 if (REG_NOTE_KIND (link) == 0)
7529 /* Data dependency; DEP_INSN writes a register that INSN reads some
7532 /* if a load, then the dependence must be on the memory address;
7533 add an extra "cycle". Note that the cost could be two cycles
7534 if the reg was written late in an instruction group; we ca not tell
7536 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7539 /* Get the delay only if the address of the store is the dependence. */
7540 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7542 rtx pat = PATTERN(insn);
7543 rtx dep_pat = PATTERN (dep_insn);
7545 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7546 return cost; /* This should not happen! */
7548 /* The dependency between the two instructions was on the data that
7549 is being stored. Assume that this implies that the address of the
7550 store is not dependent. */
7551 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7554 return cost + 3; /* An approximation. */
7557 /* A shift instruction cannot receive its data from an instruction
7558 in the same cycle; add a one cycle penalty. */
7559 if (insn_type == TYPE_SHIFT)
7560 return cost + 3; /* Split before cascade into shift. */
7564 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7565 INSN writes some cycles later. */
7567 /* These are only significant for the fpu unit; writing a fp reg before
7568 the fpu has finished with it stalls the processor. */
7570 /* Reusing an integer register causes no problems. */
7571 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7579 hypersparc_adjust_cost (insn, link, dep_insn, cost)
7585 enum attr_type insn_type, dep_type;
7586 rtx pat = PATTERN(insn);
7587 rtx dep_pat = PATTERN (dep_insn);
7589 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7592 insn_type = get_attr_type (insn);
7593 dep_type = get_attr_type (dep_insn);
7595 switch (REG_NOTE_KIND (link))
7598 /* Data dependency; DEP_INSN writes a register that INSN reads some
7605 /* Get the delay iff the address of the store is the dependence. */
7606 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7609 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7616 /* If a load, then the dependence must be on the memory address. If
7617 the addresses aren't equal, then it might be a false dependency */
7618 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7620 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7621 || GET_CODE (SET_DEST (dep_pat)) != MEM
7622 || GET_CODE (SET_SRC (pat)) != MEM
7623 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7624 XEXP (SET_SRC (pat), 0)))
7632 /* Compare to branch latency is 0. There is no benefit from
7633 separating compare and branch. */
7634 if (dep_type == TYPE_COMPARE)
7636 /* Floating point compare to branch latency is less than
7637 compare to conditional move. */
7638 if (dep_type == TYPE_FPCMP)
7647 /* Anti-dependencies only penalize the fpu unit. */
7648 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7660 sparc_adjust_cost(insn, link, dep, cost)
7668 case PROCESSOR_SUPERSPARC:
7669 cost = supersparc_adjust_cost (insn, link, dep, cost);
7671 case PROCESSOR_HYPERSPARC:
7672 case PROCESSOR_SPARCLITE86X:
7673 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7682 sparc_sched_init (dump, sched_verbose, max_ready)
7683 FILE *dump ATTRIBUTE_UNUSED;
7684 int sched_verbose ATTRIBUTE_UNUSED;
7685 int max_ready ATTRIBUTE_UNUSED;
7690 sparc_use_dfa_pipeline_interface ()
7692 if ((1 << sparc_cpu) &
7693 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
7694 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7695 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
7696 (1 << PROCESSOR_ULTRASPARC3)))
7702 sparc_use_sched_lookahead ()
7704 if (sparc_cpu == PROCESSOR_ULTRASPARC
7705 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7707 if ((1 << sparc_cpu) &
7708 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7709 (1 << PROCESSOR_SPARCLITE86X)))
7722 /* Assume V9 processors are capable of at least dual-issue. */
7724 case PROCESSOR_SUPERSPARC:
7726 case PROCESSOR_HYPERSPARC:
7727 case PROCESSOR_SPARCLITE86X:
7729 case PROCESSOR_ULTRASPARC:
7730 case PROCESSOR_ULTRASPARC3:
7739 register rtx pat = PATTERN (insn);
7741 switch (GET_CODE (SET_SRC (pat)))
7743 /* Load and some shift instructions zero extend. */
7746 /* sethi clears the high bits */
7748 /* LO_SUM is used with sethi. sethi cleared the high
7749 bits and the values used with lo_sum are positive */
7751 /* Store flag stores 0 or 1 */
7761 rtx op0 = XEXP (SET_SRC (pat), 0);
7762 rtx op1 = XEXP (SET_SRC (pat), 1);
7763 if (GET_CODE (op1) == CONST_INT)
7764 return INTVAL (op1) >= 0;
7765 if (GET_CODE (op0) != REG)
7767 if (sparc_check_64 (op0, insn) == 1)
7769 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7774 rtx op0 = XEXP (SET_SRC (pat), 0);
7775 rtx op1 = XEXP (SET_SRC (pat), 1);
7776 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7778 if (GET_CODE (op1) == CONST_INT)
7779 return INTVAL (op1) >= 0;
7780 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7784 return GET_MODE (SET_SRC (pat)) == SImode;
7785 /* Positive integers leave the high bits zero. */
7787 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7789 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7792 return - (GET_MODE (SET_SRC (pat)) == SImode);
7794 return sparc_check_64 (SET_SRC (pat), insn);
7800 /* We _ought_ to have only one kind per function, but... */
7801 static rtx sparc_addr_diff_list;
7802 static rtx sparc_addr_list;
7805 sparc_defer_case_vector (lab, vec, diff)
7809 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7811 sparc_addr_diff_list
7812 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7814 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7818 sparc_output_addr_vec (vec)
7821 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7822 int idx, vlen = XVECLEN (body, 0);
7824 #ifdef ASM_OUTPUT_ADDR_VEC_START
7825 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7828 #ifdef ASM_OUTPUT_CASE_LABEL
7829 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7832 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7835 for (idx = 0; idx < vlen; idx++)
7837 ASM_OUTPUT_ADDR_VEC_ELT
7838 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7841 #ifdef ASM_OUTPUT_ADDR_VEC_END
7842 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7847 sparc_output_addr_diff_vec (vec)
7850 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7851 rtx base = XEXP (XEXP (body, 0), 0);
7852 int idx, vlen = XVECLEN (body, 1);
7854 #ifdef ASM_OUTPUT_ADDR_VEC_START
7855 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7858 #ifdef ASM_OUTPUT_CASE_LABEL
7859 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7862 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7865 for (idx = 0; idx < vlen; idx++)
7867 ASM_OUTPUT_ADDR_DIFF_ELT
7870 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7871 CODE_LABEL_NUMBER (base));
7874 #ifdef ASM_OUTPUT_ADDR_VEC_END
7875 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7880 sparc_output_deferred_case_vectors ()
7885 if (sparc_addr_list == NULL_RTX
7886 && sparc_addr_diff_list == NULL_RTX)
7889 /* Align to cache line in the function's code section. */
7890 function_section (current_function_decl);
7892 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7894 ASM_OUTPUT_ALIGN (asm_out_file, align);
7896 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7897 sparc_output_addr_vec (XEXP (t, 0));
7898 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7899 sparc_output_addr_diff_vec (XEXP (t, 0));
7901 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7904 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7905 unknown. Return 1 if the high bits are zero, -1 if the register is
7908 sparc_check_64 (x, insn)
7911 /* If a register is set only once it is safe to ignore insns this
7912 code does not know how to handle. The loop will either recognize
7913 the single set and return the correct value or fail to recognize
7918 if (GET_CODE (x) != REG)
7921 if (GET_MODE (x) == DImode)
7922 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
7924 if (flag_expensive_optimizations
7925 && REG_N_SETS (REGNO (y)) == 1)
7931 insn = get_last_insn_anywhere ();
7936 while ((insn = PREV_INSN (insn)))
7938 switch (GET_CODE (insn))
7951 rtx pat = PATTERN (insn);
7952 if (GET_CODE (pat) != SET)
7954 if (rtx_equal_p (x, SET_DEST (pat)))
7955 return set_extends (insn);
7956 if (y && rtx_equal_p (y, SET_DEST (pat)))
7957 return set_extends (insn);
7958 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
7967 sparc_v8plus_shift (operands, insn, opcode)
7972 static char asm_code[60];
7974 if (GET_CODE (operands[3]) == SCRATCH)
7975 operands[3] = operands[0];
7976 if (GET_CODE (operands[1]) == CONST_INT)
7978 output_asm_insn ("mov\t%1, %3", operands);
7982 output_asm_insn ("sllx\t%H1, 32, %3", operands);
7983 if (sparc_check_64 (operands[1], insn) <= 0)
7984 output_asm_insn ("srl\t%L1, 0, %L1", operands);
7985 output_asm_insn ("or\t%L1, %3, %3", operands);
7988 strcpy(asm_code, opcode);
7989 if (which_alternative != 2)
7990 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7992 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7995 /* Output rtl to increment the profiler label LABELNO
7996 for profiling a function entry. */
7999 sparc_profile_hook (labelno)
8005 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8006 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8007 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8009 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8012 /* Called to register all of our global variables with the garbage
8016 sparc_add_gc_roots ()
8018 ggc_add_rtx_root (&sparc_compare_op0, 1);
8019 ggc_add_rtx_root (&sparc_compare_op1, 1);
8020 ggc_add_rtx_root (&global_offset_table, 1);
8021 ggc_add_rtx_root (&get_pc_symbol, 1);
8022 ggc_add_rtx_root (&sparc_addr_diff_list, 1);
8023 ggc_add_rtx_root (&sparc_addr_list, 1);
8026 #ifdef OBJECT_FORMAT_ELF
8028 sparc_elf_asm_named_section (name, flags)
8032 if (flags & SECTION_MERGE)
8034 /* entsize cannot be expressed in this section attributes
8036 default_elf_asm_named_section (name, flags);
8040 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8042 if (!(flags & SECTION_DEBUG))
8043 fputs (",#alloc", asm_out_file);
8044 if (flags & SECTION_WRITE)
8045 fputs (",#write", asm_out_file);
8046 if (flags & SECTION_CODE)
8047 fputs (",#execinstr", asm_out_file);
8049 /* ??? Handle SECTION_BSS. */
8051 fputc ('\n', asm_out_file);
8053 #endif /* OBJECT_FORMAT_ELF */
8056 sparc_extra_constraint_check (op, c, strict)
8064 && (c == 'T' || c == 'U'))
8070 return fp_sethi_p (op);
8073 return fp_mov_p (op);
8076 return fp_high_losum_p (op);
8080 || (GET_CODE (op) == REG
8081 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8082 || reg_renumber[REGNO (op)] >= 0)))
8083 return register_ok_for_ldd (op);
8095 /* Our memory extra constraints have to emulate the
8096 behavior of 'm' and 'o' in order for reload to work
8098 if (GET_CODE (op) == MEM)
8101 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8103 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8108 reload_ok_mem = (reload_in_progress
8109 && GET_CODE (op) == REG
8110 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8111 && reg_renumber [REGNO (op)] < 0);
8114 return reload_ok_mem;
8117 /* ??? This duplicates information provided to the compiler by the
8118 ??? scheduler description. Some day, teach genautomata to output
8119 ??? the latencies and then CSE will just use that. */
8122 sparc_rtx_costs (x, code, outer_code)
8124 enum rtx_code code, outer_code;
8128 case PLUS: case MINUS: case ABS: case NEG:
8129 case FLOAT: case UNSIGNED_FLOAT:
8130 case FIX: case UNSIGNED_FIX:
8131 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8132 if (FLOAT_MODE_P (GET_MODE (x)))
8136 case PROCESSOR_ULTRASPARC:
8137 case PROCESSOR_ULTRASPARC3:
8138 return COSTS_N_INSNS (4);
8140 case PROCESSOR_SUPERSPARC:
8141 return COSTS_N_INSNS (3);
8143 case PROCESSOR_CYPRESS:
8144 return COSTS_N_INSNS (5);
8146 case PROCESSOR_HYPERSPARC:
8147 case PROCESSOR_SPARCLITE86X:
8149 return COSTS_N_INSNS (1);
8153 return COSTS_N_INSNS (1);
8158 case PROCESSOR_ULTRASPARC:
8159 if (GET_MODE (x) == SFmode)
8160 return COSTS_N_INSNS (13);
8162 return COSTS_N_INSNS (23);
8164 case PROCESSOR_ULTRASPARC3:
8165 if (GET_MODE (x) == SFmode)
8166 return COSTS_N_INSNS (20);
8168 return COSTS_N_INSNS (29);
8170 case PROCESSOR_SUPERSPARC:
8171 return COSTS_N_INSNS (12);
8173 case PROCESSOR_CYPRESS:
8174 return COSTS_N_INSNS (63);
8176 case PROCESSOR_HYPERSPARC:
8177 case PROCESSOR_SPARCLITE86X:
8178 return COSTS_N_INSNS (17);
8181 return COSTS_N_INSNS (30);
8185 if (FLOAT_MODE_P (GET_MODE (x)))
8189 case PROCESSOR_ULTRASPARC:
8190 case PROCESSOR_ULTRASPARC3:
8191 return COSTS_N_INSNS (1);
8193 case PROCESSOR_SUPERSPARC:
8194 return COSTS_N_INSNS (3);
8196 case PROCESSOR_CYPRESS:
8197 return COSTS_N_INSNS (5);
8199 case PROCESSOR_HYPERSPARC:
8200 case PROCESSOR_SPARCLITE86X:
8202 return COSTS_N_INSNS (1);
8206 /* ??? Maybe mark integer compares as zero cost on
8207 ??? all UltraSPARC processors because the result
8208 ??? can be bypassed to a branch in the same group. */
8210 return COSTS_N_INSNS (1);
8213 if (FLOAT_MODE_P (GET_MODE (x)))
8217 case PROCESSOR_ULTRASPARC:
8218 case PROCESSOR_ULTRASPARC3:
8219 return COSTS_N_INSNS (4);
8221 case PROCESSOR_SUPERSPARC:
8222 return COSTS_N_INSNS (3);
8224 case PROCESSOR_CYPRESS:
8225 return COSTS_N_INSNS (7);
8227 case PROCESSOR_HYPERSPARC:
8228 case PROCESSOR_SPARCLITE86X:
8229 return COSTS_N_INSNS (1);
8232 return COSTS_N_INSNS (5);
8236 /* The latency is actually variable for Ultra-I/II
8237 And if one of the inputs have a known constant
8238 value, we could calculate this precisely.
8240 However, for that to be useful we would need to
8241 add some machine description changes which would
8242 make sure small constants ended up in rs1 of the
8243 multiply instruction. This is because the multiply
8244 latency is determined by the number of clear (or
8245 set if the value is negative) bits starting from
8246 the most significant bit of the first input.
8248 The algorithm for computing num_cycles of a multiply
8252 highest_bit = highest_clear_bit(rs1);
8254 highest_bit = highest_set_bit(rs1);
8257 num_cycles = 4 + ((highest_bit - 3) / 2);
8259 If we did that we would have to also consider register
8260 allocation issues that would result from forcing such
8261 a value into a register.
8263 There are other similar tricks we could play if we
8264 knew, for example, that one input was an array index.
8266 Since we do not play any such tricks currently the
8267 safest thing to do is report the worst case latency. */
8268 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8269 return (GET_MODE (x) == DImode ?
8270 COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8272 /* Multiply latency on Ultra-III, fortunately, is constant. */
8273 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8274 return COSTS_N_INSNS (6);
8276 if (sparc_cpu == PROCESSOR_HYPERSPARC
8277 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8278 return COSTS_N_INSNS (17);
8280 return (TARGET_HARD_MUL
8282 : COSTS_N_INSNS (25));
8288 if (FLOAT_MODE_P (GET_MODE (x)))
8292 case PROCESSOR_ULTRASPARC:
8293 if (GET_MODE (x) == SFmode)
8294 return COSTS_N_INSNS (13);
8296 return COSTS_N_INSNS (23);
8298 case PROCESSOR_ULTRASPARC3:
8299 if (GET_MODE (x) == SFmode)
8300 return COSTS_N_INSNS (17);
8302 return COSTS_N_INSNS (20);
8304 case PROCESSOR_SUPERSPARC:
8305 if (GET_MODE (x) == SFmode)
8306 return COSTS_N_INSNS (6);
8308 return COSTS_N_INSNS (9);
8310 case PROCESSOR_HYPERSPARC:
8311 case PROCESSOR_SPARCLITE86X:
8312 if (GET_MODE (x) == SFmode)
8313 return COSTS_N_INSNS (8);
8315 return COSTS_N_INSNS (12);
8318 return COSTS_N_INSNS (7);
8322 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8323 return (GET_MODE (x) == DImode ?
8324 COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8325 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8326 return (GET_MODE (x) == DImode ?
8327 COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8328 return COSTS_N_INSNS (25);
8331 /* Conditional moves. */
8334 case PROCESSOR_ULTRASPARC:
8335 return COSTS_N_INSNS (2);
8337 case PROCESSOR_ULTRASPARC3:
8338 if (FLOAT_MODE_P (GET_MODE (x)))
8339 return COSTS_N_INSNS (3);
8341 return COSTS_N_INSNS (2);
8344 return COSTS_N_INSNS (1);
8348 /* If outer-code is SIGN/ZERO extension we have to subtract
8349 out COSTS_N_INSNS (1) from whatever we return in determining
8353 case PROCESSOR_ULTRASPARC:
8354 if (outer_code == ZERO_EXTEND)
8355 return COSTS_N_INSNS (1);
8357 return COSTS_N_INSNS (2);
8359 case PROCESSOR_ULTRASPARC3:
8360 if (outer_code == ZERO_EXTEND)
8362 if (GET_MODE (x) == QImode
8363 || GET_MODE (x) == HImode
8364 || outer_code == SIGN_EXTEND)
8365 return COSTS_N_INSNS (2);
8367 return COSTS_N_INSNS (1);
8371 /* This handles sign extension (3 cycles)
8372 and everything else (2 cycles). */
8373 return COSTS_N_INSNS (2);
8376 case PROCESSOR_SUPERSPARC:
8377 if (FLOAT_MODE_P (GET_MODE (x))
8378 || outer_code == ZERO_EXTEND
8379 || outer_code == SIGN_EXTEND)
8380 return COSTS_N_INSNS (0);
8382 return COSTS_N_INSNS (1);
8384 case PROCESSOR_TSC701:
8385 if (outer_code == ZERO_EXTEND
8386 || outer_code == SIGN_EXTEND)
8387 return COSTS_N_INSNS (2);
8389 return COSTS_N_INSNS (3);
8391 case PROCESSOR_CYPRESS:
8392 if (outer_code == ZERO_EXTEND
8393 || outer_code == SIGN_EXTEND)
8394 return COSTS_N_INSNS (1);
8396 return COSTS_N_INSNS (2);
8398 case PROCESSOR_HYPERSPARC:
8399 case PROCESSOR_SPARCLITE86X:
8401 if (outer_code == ZERO_EXTEND
8402 || outer_code == SIGN_EXTEND)
8403 return COSTS_N_INSNS (0);
8405 return COSTS_N_INSNS (1);
8409 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8422 if (GET_MODE (x) == DImode)
8423 if ((XINT (x, 3) == 0
8424 && (unsigned) XINT (x, 2) < 0x1000)
8425 || (XINT (x, 3) == -1
8427 && XINT (x, 2) >= -0x1000))