1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
50 #include "tree-gimple.h"
52 /* Global variables for machine-dependent things. */
54 /* Size of frame. Need to know this to emit return insns from leaf procedures.
55 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
56 reload pass. This is important as the value is later used in insn
57 scheduling (to see what can go in a delay slot).
58 APPARENT_FSIZE is the size of the stack less the register save area and less
59 the outgoing argument area. It is used when saving call preserved regs. */
60 static HOST_WIDE_INT apparent_fsize;
61 static HOST_WIDE_INT actual_fsize;
63 /* Number of live general or floating point registers needed to be
64 saved (as 4-byte quantities). */
65 static int num_gfregs;
67 /* Save the operands last given to a compare for use when we
68 generate a scc or bcc insn. */
69 rtx sparc_compare_op0, sparc_compare_op1;
71 /* Coordinate with the md file wrt special insns created by
72 sparc_function_epilogue. */
73 bool sparc_emitting_epilogue;
74 bool sparc_skip_caller_unimp;
76 /* Vector to say how input registers are mapped to output registers.
77 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
78 eliminate it. You must use -fomit-frame-pointer to get that. */
79 char leaf_reg_remap[] =
80 { 0, 1, 2, 3, 4, 5, 6, 7,
81 -1, -1, -1, -1, -1, -1, 14, -1,
82 -1, -1, -1, -1, -1, -1, -1, -1,
83 8, 9, 10, 11, 12, 13, -1, 15,
85 32, 33, 34, 35, 36, 37, 38, 39,
86 40, 41, 42, 43, 44, 45, 46, 47,
87 48, 49, 50, 51, 52, 53, 54, 55,
88 56, 57, 58, 59, 60, 61, 62, 63,
89 64, 65, 66, 67, 68, 69, 70, 71,
90 72, 73, 74, 75, 76, 77, 78, 79,
91 80, 81, 82, 83, 84, 85, 86, 87,
92 88, 89, 90, 91, 92, 93, 94, 95,
95 /* Vector, indexed by hard register number, which contains 1
96 for a register that is allowable in a candidate for leaf
97 function treatment. */
98 char sparc_leaf_regs[] =
99 { 1, 1, 1, 1, 1, 1, 1, 1,
100 0, 0, 0, 0, 0, 0, 1, 0,
101 0, 0, 0, 0, 0, 0, 0, 0,
102 1, 1, 1, 1, 1, 1, 0, 1,
103 1, 1, 1, 1, 1, 1, 1, 1,
104 1, 1, 1, 1, 1, 1, 1, 1,
105 1, 1, 1, 1, 1, 1, 1, 1,
106 1, 1, 1, 1, 1, 1, 1, 1,
107 1, 1, 1, 1, 1, 1, 1, 1,
108 1, 1, 1, 1, 1, 1, 1, 1,
109 1, 1, 1, 1, 1, 1, 1, 1,
110 1, 1, 1, 1, 1, 1, 1, 1,
113 struct machine_function GTY(())
115 /* Some local-dynamic TLS symbol name. */
116 const char *some_ld_name;
119 /* Name of where we pretend to think the frame pointer points.
120 Normally, this is "%fp", but if we are in a leaf procedure,
121 this is "%sp+something". We record "something" separately as it may be
122 too big for reg+constant addressing. */
124 static const char *frame_base_name;
125 static HOST_WIDE_INT frame_base_offset;
127 static void sparc_init_modes (void);
128 static int save_regs (FILE *, int, int, const char *, int, int, HOST_WIDE_INT);
129 static int restore_regs (FILE *, int, int, const char *, int, int);
130 static void build_big_number (FILE *, HOST_WIDE_INT, const char *);
131 static void scan_record_type (tree, int *, int *, int *);
132 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
133 tree, int, int, int *, int *);
135 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
136 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
138 static void sparc_output_addr_vec (rtx);
139 static void sparc_output_addr_diff_vec (rtx);
140 static void sparc_output_deferred_case_vectors (void);
141 static int check_return_regs (rtx);
142 static rtx sparc_builtin_saveregs (void);
143 static int epilogue_renumber (rtx *, int);
144 static bool sparc_assemble_integer (rtx, unsigned int, int);
145 static int set_extends (rtx);
146 static void output_restore_regs (FILE *, int);
147 static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT);
148 static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT);
149 static void sparc_function_epilogue (FILE *, HOST_WIDE_INT, int);
150 static void sparc_function_prologue (FILE *, HOST_WIDE_INT, int);
151 #ifdef OBJECT_FORMAT_ELF
152 static void sparc_elf_asm_named_section (const char *, unsigned int);
155 static int sparc_adjust_cost (rtx, rtx, rtx, int);
156 static int sparc_issue_rate (void);
157 static void sparc_sched_init (FILE *, int, int);
158 static int sparc_use_dfa_pipeline_interface (void);
159 static int sparc_use_sched_lookahead (void);
161 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
162 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
163 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
164 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
165 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
167 static bool sparc_function_ok_for_sibcall (tree, tree);
168 static void sparc_init_libfuncs (void);
169 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
170 HOST_WIDE_INT, tree);
171 static struct machine_function * sparc_init_machine_status (void);
172 static bool sparc_cannot_force_const_mem (rtx);
173 static rtx sparc_tls_get_addr (void);
174 static rtx sparc_tls_got (void);
175 static const char *get_some_local_dynamic_name (void);
176 static int get_some_local_dynamic_name_1 (rtx *, void *);
177 static bool sparc_rtx_costs (rtx, int, int, int *);
178 static bool sparc_promote_prototypes (tree);
179 static rtx sparc_struct_value_rtx (tree, int);
180 static bool sparc_return_in_memory (tree, tree);
181 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
182 static tree sparc_gimplify_va_arg (tree, tree, tree *, tree *);
184 /* Option handling. */
186 /* Code model option as passed by user. */
187 const char *sparc_cmodel_string;
189 enum cmodel sparc_cmodel;
191 char sparc_hard_reg_printed[8];
193 struct sparc_cpu_select sparc_select[] =
195 /* switch name, tune arch */
196 { (char *)0, "default", 1, 1 },
197 { (char *)0, "-mcpu=", 1, 1 },
198 { (char *)0, "-mtune=", 1, 0 },
202 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
203 enum processor_type sparc_cpu;
205 /* Initialize the GCC target structure. */
207 /* The sparc default is to use .half rather than .short for aligned
208 HI objects. Use .word instead of .long on non-ELF systems. */
209 #undef TARGET_ASM_ALIGNED_HI_OP
210 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
211 #ifndef OBJECT_FORMAT_ELF
212 #undef TARGET_ASM_ALIGNED_SI_OP
213 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
216 #undef TARGET_ASM_UNALIGNED_HI_OP
217 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
218 #undef TARGET_ASM_UNALIGNED_SI_OP
219 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
220 #undef TARGET_ASM_UNALIGNED_DI_OP
221 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
223 /* The target hook has to handle DI-mode values. */
224 #undef TARGET_ASM_INTEGER
225 #define TARGET_ASM_INTEGER sparc_assemble_integer
227 #undef TARGET_ASM_FUNCTION_PROLOGUE
228 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
229 #undef TARGET_ASM_FUNCTION_EPILOGUE
230 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
232 #undef TARGET_SCHED_ADJUST_COST
233 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
234 #undef TARGET_SCHED_ISSUE_RATE
235 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
236 #undef TARGET_SCHED_INIT
237 #define TARGET_SCHED_INIT sparc_sched_init
238 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
239 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
240 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
241 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
243 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
244 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
246 #undef TARGET_INIT_LIBFUNCS
247 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
250 #undef TARGET_HAVE_TLS
251 #define TARGET_HAVE_TLS true
253 #undef TARGET_CANNOT_FORCE_CONST_MEM
254 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
256 #undef TARGET_ASM_OUTPUT_MI_THUNK
257 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
258 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
259 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
261 #undef TARGET_RTX_COSTS
262 #define TARGET_RTX_COSTS sparc_rtx_costs
263 #undef TARGET_ADDRESS_COST
264 #define TARGET_ADDRESS_COST hook_int_rtx_0
266 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
267 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
268 test for this value. */
269 #undef TARGET_PROMOTE_FUNCTION_ARGS
270 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
272 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
273 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
274 test for this value. */
275 #undef TARGET_PROMOTE_FUNCTION_RETURN
276 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
278 #undef TARGET_PROMOTE_PROTOTYPES
279 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
281 #undef TARGET_STRUCT_VALUE_RTX
282 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
283 #undef TARGET_RETURN_IN_MEMORY
284 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
286 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
287 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
288 #undef TARGET_STRICT_ARGUMENT_NAMING
289 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
291 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
292 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
294 struct gcc_target targetm = TARGET_INITIALIZER;
296 /* Validate and override various options, and do some machine dependent
300 sparc_override_options (void)
302 static struct code_model {
303 const char *const name;
305 } const cmodels[] = {
307 { "medlow", CM_MEDLOW },
308 { "medmid", CM_MEDMID },
309 { "medany", CM_MEDANY },
310 { "embmedany", CM_EMBMEDANY },
313 const struct code_model *cmodel;
314 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
315 static struct cpu_default {
317 const char *const name;
318 } const cpu_default[] = {
319 /* There must be one entry here for each TARGET_CPU value. */
320 { TARGET_CPU_sparc, "cypress" },
321 { TARGET_CPU_sparclet, "tsc701" },
322 { TARGET_CPU_sparclite, "f930" },
323 { TARGET_CPU_v8, "v8" },
324 { TARGET_CPU_hypersparc, "hypersparc" },
325 { TARGET_CPU_sparclite86x, "sparclite86x" },
326 { TARGET_CPU_supersparc, "supersparc" },
327 { TARGET_CPU_v9, "v9" },
328 { TARGET_CPU_ultrasparc, "ultrasparc" },
329 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
332 const struct cpu_default *def;
333 /* Table of values for -m{cpu,tune}=. */
334 static struct cpu_table {
335 const char *const name;
336 const enum processor_type processor;
339 } const cpu_table[] = {
340 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
341 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
342 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
343 /* TI TMS390Z55 supersparc */
344 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
345 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
346 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
347 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
348 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
349 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
350 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
351 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
353 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
355 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
356 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
357 /* TI ultrasparc I, II, IIi */
358 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
359 /* Although insns using %y are deprecated, it is a clear win on current
361 |MASK_DEPRECATED_V8_INSNS},
362 /* TI ultrasparc III */
363 /* ??? Check if %y issue still holds true in ultra3. */
364 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
367 const struct cpu_table *cpu;
368 const struct sparc_cpu_select *sel;
371 #ifndef SPARC_BI_ARCH
372 /* Check for unsupported architecture size. */
373 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
374 error ("%s is not supported by this configuration",
375 DEFAULT_ARCH32_P ? "-m64" : "-m32");
378 /* We force all 64bit archs to use 128 bit long double */
379 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
381 error ("-mlong-double-64 not allowed with -m64");
382 target_flags |= MASK_LONG_DOUBLE_128;
385 /* Code model selection. */
386 sparc_cmodel = SPARC_DEFAULT_CMODEL;
390 sparc_cmodel = CM_32;
393 if (sparc_cmodel_string != NULL)
397 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
398 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
400 if (cmodel->name == NULL)
401 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
403 sparc_cmodel = cmodel->value;
406 error ("-mcmodel= is not supported on 32 bit systems");
409 fpu = TARGET_FPU; /* save current -mfpu status */
411 /* Set the default CPU. */
412 for (def = &cpu_default[0]; def->name; ++def)
413 if (def->cpu == TARGET_CPU_DEFAULT)
417 sparc_select[0].string = def->name;
419 for (sel = &sparc_select[0]; sel->name; ++sel)
423 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
424 if (! strcmp (sel->string, cpu->name))
427 sparc_cpu = cpu->processor;
431 target_flags &= ~cpu->disable;
432 target_flags |= cpu->enable;
438 error ("bad value (%s) for %s switch", sel->string, sel->name);
442 /* If -mfpu or -mno-fpu was explicitly used, don't override with
443 the processor default. Clear MASK_FPU_SET to avoid confusing
444 the reverse mapping from switch values to names. */
447 target_flags = (target_flags & ~MASK_FPU) | fpu;
448 target_flags &= ~MASK_FPU_SET;
451 /* Don't allow -mvis if FPU is disabled. */
453 target_flags &= ~MASK_VIS;
455 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
457 -m64 also implies v9. */
458 if (TARGET_VIS || TARGET_ARCH64)
460 target_flags |= MASK_V9;
461 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
464 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
465 if (TARGET_V9 && TARGET_ARCH32)
466 target_flags |= MASK_DEPRECATED_V8_INSNS;
468 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
469 if (! TARGET_V9 || TARGET_ARCH64)
470 target_flags &= ~MASK_V8PLUS;
472 /* Don't use stack biasing in 32 bit mode. */
474 target_flags &= ~MASK_STACK_BIAS;
476 /* Supply a default value for align_functions. */
477 if (align_functions == 0
478 && (sparc_cpu == PROCESSOR_ULTRASPARC
479 || sparc_cpu == PROCESSOR_ULTRASPARC3))
480 align_functions = 32;
482 /* Validate PCC_STRUCT_RETURN. */
483 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
484 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
486 /* Only use .uaxword when compiling for a 64-bit target. */
488 targetm.asm_out.unaligned_op.di = NULL;
490 /* Do various machine dependent initializations. */
493 /* Set up function hooks. */
494 init_machine_status = sparc_init_machine_status;
497 /* Miscellaneous utilities. */
499 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
500 or branch on register contents instructions. */
503 v9_regcmp_p (enum rtx_code code)
505 return (code == EQ || code == NE || code == GE || code == LT
506 || code == LE || code == GT);
510 /* Operand constraints. */
512 /* Return nonzero only if OP is a register of mode MODE,
516 reg_or_0_operand (rtx op, enum machine_mode mode)
518 if (register_operand (op, mode))
520 if (op == const0_rtx)
522 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
523 && CONST_DOUBLE_HIGH (op) == 0
524 && CONST_DOUBLE_LOW (op) == 0)
526 if (fp_zero_operand (op, mode))
531 /* Return nonzero only if OP is const1_rtx. */
534 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
536 return op == const1_rtx;
539 /* Nonzero if OP is a floating point value with value 0.0. */
542 fp_zero_operand (rtx op, enum machine_mode mode)
544 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
546 return op == CONST0_RTX (mode);
549 /* Nonzero if OP is a register operand in floating point register. */
552 fp_register_operand (rtx op, enum machine_mode mode)
554 if (! register_operand (op, mode))
556 if (GET_CODE (op) == SUBREG)
557 op = SUBREG_REG (op);
558 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
561 /* Nonzero if OP is a floating point constant which can
562 be loaded into an integer register using a single
563 sethi instruction. */
568 if (GET_CODE (op) == CONST_DOUBLE)
573 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
574 if (REAL_VALUES_EQUAL (r, dconst0) &&
575 ! REAL_VALUE_MINUS_ZERO (r))
577 REAL_VALUE_TO_TARGET_SINGLE (r, i);
578 if (SPARC_SETHI_P (i))
585 /* Nonzero if OP is a floating point constant which can
586 be loaded into an integer register using a single
592 if (GET_CODE (op) == CONST_DOUBLE)
597 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
598 if (REAL_VALUES_EQUAL (r, dconst0) &&
599 ! REAL_VALUE_MINUS_ZERO (r))
601 REAL_VALUE_TO_TARGET_SINGLE (r, i);
602 if (SPARC_SIMM13_P (i))
609 /* Nonzero if OP is a floating point constant which can
610 be loaded into an integer register using a high/losum
611 instruction sequence. */
614 fp_high_losum_p (rtx op)
616 /* The constraints calling this should only be in
617 SFmode move insns, so any constant which cannot
618 be moved using a single insn will do. */
619 if (GET_CODE (op) == CONST_DOUBLE)
624 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
625 if (REAL_VALUES_EQUAL (r, dconst0) &&
626 ! REAL_VALUE_MINUS_ZERO (r))
628 REAL_VALUE_TO_TARGET_SINGLE (r, i);
629 if (! SPARC_SETHI_P (i)
630 && ! SPARC_SIMM13_P (i))
637 /* Nonzero if OP is an integer register. */
640 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
642 return (register_operand (op, SImode)
643 || (TARGET_ARCH64 && register_operand (op, DImode)));
646 /* Nonzero if OP is a floating point condition code register. */
649 fcc_reg_operand (rtx op, enum machine_mode mode)
651 /* This can happen when recog is called from combine. Op may be a MEM.
652 Fail instead of calling abort in this case. */
653 if (GET_CODE (op) != REG)
656 if (mode != VOIDmode && mode != GET_MODE (op))
659 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
662 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
663 if (reg_renumber == 0)
664 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
665 return REGNO_OK_FOR_CCFP_P (REGNO (op));
667 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
671 /* Nonzero if OP is a floating point condition code fcc0 register. */
674 fcc0_reg_operand (rtx op, enum machine_mode mode)
676 /* This can happen when recog is called from combine. Op may be a MEM.
677 Fail instead of calling abort in this case. */
678 if (GET_CODE (op) != REG)
681 if (mode != VOIDmode && mode != GET_MODE (op))
684 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
687 return REGNO (op) == SPARC_FCC_REG;
690 /* Nonzero if OP is an integer or floating point condition code register. */
693 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
695 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
697 if (mode != VOIDmode && mode != GET_MODE (op))
700 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
705 return fcc_reg_operand (op, mode);
708 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
710 restore_operand (rtx op, enum machine_mode mode)
712 return (GET_CODE (op) == REG && GET_MODE (op) == mode
713 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
716 /* Call insn on SPARC can take a PC-relative constant address, or any regular
720 call_operand (rtx op, enum machine_mode mode)
722 if (GET_CODE (op) != MEM)
725 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
729 call_operand_address (rtx op, enum machine_mode mode)
731 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
734 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
735 otherwise return 0. */
738 tls_symbolic_operand (rtx op)
740 if (GET_CODE (op) != SYMBOL_REF)
742 return SYMBOL_REF_TLS_MODEL (op);
746 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
748 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
752 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
754 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
758 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
760 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
764 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
766 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
769 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
770 reference and a constant. */
773 symbolic_operand (register rtx op, enum machine_mode mode)
775 enum machine_mode omode = GET_MODE (op);
777 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
780 switch (GET_CODE (op))
783 return !SYMBOL_REF_TLS_MODEL (op);
790 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
791 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
792 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
793 && GET_CODE (XEXP (op, 1)) == CONST_INT);
800 /* Return truth value of statement that OP is a symbolic memory
801 operand of mode MODE. */
804 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
806 if (GET_CODE (op) == SUBREG)
807 op = SUBREG_REG (op);
808 if (GET_CODE (op) != MEM)
811 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
812 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
813 || GET_CODE (op) == LABEL_REF);
816 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
819 label_ref_operand (rtx op, enum machine_mode mode)
821 if (GET_CODE (op) != LABEL_REF)
823 if (GET_MODE (op) != mode)
828 /* Return 1 if the operand is an argument used in generating pic references
829 in either the medium/low or medium/anywhere code models of sparc64. */
832 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
834 /* Check for (const (minus (symbol_ref:GOT)
835 (const (minus (label) (pc))))). */
836 if (GET_CODE (op) != CONST)
839 if (GET_CODE (op) != MINUS)
841 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
843 /* ??? Ensure symbol is GOT. */
844 if (GET_CODE (XEXP (op, 1)) != CONST)
846 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
851 /* Return 1 if the operand is a data segment reference. This includes
852 the readonly data segment, or in other words anything but the text segment.
853 This is needed in the medium/anywhere code model on v9. These values
854 are accessed with EMBMEDANY_BASE_REG. */
857 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
859 switch (GET_CODE (op))
862 return ! SYMBOL_REF_FUNCTION_P (op);
864 /* Assume canonical format of symbol + constant.
867 return data_segment_operand (XEXP (op, 0), VOIDmode);
873 /* Return 1 if the operand is a text segment reference.
874 This is needed in the medium/anywhere code model on v9. */
877 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
879 switch (GET_CODE (op))
884 return SYMBOL_REF_FUNCTION_P (op);
886 /* Assume canonical format of symbol + constant.
889 return text_segment_operand (XEXP (op, 0), VOIDmode);
895 /* Return 1 if the operand is either a register or a memory operand that is
899 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
901 if (register_operand (op, mode))
904 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
911 splittable_symbolic_memory_operand (rtx op,
912 enum machine_mode mode ATTRIBUTE_UNUSED)
914 if (GET_CODE (op) != MEM)
916 if (! symbolic_operand (XEXP (op, 0), Pmode))
922 splittable_immediate_memory_operand (rtx op,
923 enum machine_mode mode ATTRIBUTE_UNUSED)
925 if (GET_CODE (op) != MEM)
927 if (! immediate_operand (XEXP (op, 0), Pmode))
932 /* Return truth value of whether OP is EQ or NE. */
935 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
937 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
940 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
941 or LTU for non-floating-point. We handle those specially. */
944 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
948 if (!COMPARISON_P (op))
951 if (GET_MODE (XEXP (op, 0)) == CCFPmode
952 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
955 code = GET_CODE (op);
956 return (code != NE && code != EQ && code != GEU && code != LTU);
959 /* Return 1 if this is a comparison operator. This allows the use of
960 MATCH_OPERATOR to recognize all the branch insns. */
963 noov_compare_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
967 if (!COMPARISON_P (op))
970 code = GET_CODE (op);
971 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
972 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
973 /* These are the only branches which work with CC_NOOVmode. */
974 return (code == EQ || code == NE || code == GE || code == LT);
978 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
979 MATCH_OPERATOR to recognize all the branch insns. */
982 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
989 if (!COMPARISON_P (op))
992 code = GET_CODE (op);
993 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
994 /* These are the only branches which work with CCX_NOOVmode. */
995 return (code == EQ || code == NE || code == GE || code == LT);
996 return (GET_MODE (XEXP (op, 0)) == CCXmode);
999 /* Nonzero if OP is a comparison operator suitable for use in v9
1000 conditional move or branch on register contents instructions. */
1003 v9_regcmp_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1007 if (!COMPARISON_P (op))
1010 code = GET_CODE (op);
1011 return v9_regcmp_p (code);
1014 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1017 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1019 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1022 /* Return nonzero if OP is an operator of mode MODE which can set
1023 the condition codes explicitly. We do not include PLUS and MINUS
1024 because these require CC_NOOVmode, which we handle explicitly. */
1027 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1029 if (GET_CODE (op) == AND
1030 || GET_CODE (op) == IOR
1031 || GET_CODE (op) == XOR)
1037 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1038 complement its second operand and set the condition codes explicitly. */
1041 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1043 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1044 and (xor ... (not ...)) to (not (xor ...)). */
1045 return (GET_CODE (op) == AND
1046 || GET_CODE (op) == IOR);
1049 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1050 signed 13 bit immediate field. This is an acceptable SImode operand for
1051 most 3 address instructions. */
1054 arith_operand (rtx op, enum machine_mode mode)
1056 if (register_operand (op, mode))
1058 if (GET_CODE (op) != CONST_INT)
1060 return SMALL_INT32 (op);
1063 /* Return true if OP is a constant 4096 */
1066 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1068 if (GET_CODE (op) != CONST_INT)
1071 return INTVAL (op) == 4096;
1074 /* Return true if OP is suitable as second operand for add/sub */
1077 arith_add_operand (rtx op, enum machine_mode mode)
1079 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1082 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1083 immediate field of OR and XOR instructions. Used for 64-bit
1084 constant formation patterns. */
1086 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1088 return ((GET_CODE (op) == CONST_INT
1089 && SPARC_SIMM13_P (INTVAL (op)))
1090 #if HOST_BITS_PER_WIDE_INT != 64
1091 || (GET_CODE (op) == CONST_DOUBLE
1092 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1093 && (CONST_DOUBLE_HIGH (op) ==
1094 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1095 (HOST_WIDE_INT)-1 : 0)))
1100 /* The same, but only for sethi instructions. */
1102 const64_high_operand (rtx op, enum machine_mode mode)
1104 return ((GET_CODE (op) == CONST_INT
1105 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1106 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1108 || (GET_CODE (op) == CONST_DOUBLE
1109 && CONST_DOUBLE_HIGH (op) == 0
1110 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1111 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1114 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1115 signed 11 bit immediate field. This is an acceptable SImode operand for
1116 the movcc instructions. */
1119 arith11_operand (rtx op, enum machine_mode mode)
1121 return (register_operand (op, mode)
1122 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1125 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1126 signed 10 bit immediate field. This is an acceptable SImode operand for
1127 the movrcc instructions. */
1130 arith10_operand (rtx op, enum machine_mode mode)
1132 return (register_operand (op, mode)
1133 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1136 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1137 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1139 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1140 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1141 for most 3 address instructions. */
1144 arith_double_operand (rtx op, enum machine_mode mode)
1146 return (register_operand (op, mode)
1147 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1149 && GET_CODE (op) == CONST_DOUBLE
1150 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1151 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1153 && GET_CODE (op) == CONST_DOUBLE
1154 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1155 && ((CONST_DOUBLE_HIGH (op) == -1
1156 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1157 || (CONST_DOUBLE_HIGH (op) == 0
1158 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1161 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1164 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1166 return (TARGET_ARCH64 &&
1167 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1168 (GET_CODE (op) == CONST_DOUBLE &&
1169 CONST_DOUBLE_LOW (op) == 4096 &&
1170 CONST_DOUBLE_HIGH (op) == 0)));
1173 /* Return true if OP is suitable as second operand for add/sub in DImode */
1176 arith_double_add_operand (rtx op, enum machine_mode mode)
1178 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1181 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1182 can fit in an 11 bit immediate field. This is an acceptable DImode
1183 operand for the movcc instructions. */
1184 /* ??? Replace with arith11_operand? */
1187 arith11_double_operand (rtx op, enum machine_mode mode)
1189 return (register_operand (op, mode)
1190 || (GET_CODE (op) == CONST_DOUBLE
1191 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1192 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1193 && ((CONST_DOUBLE_HIGH (op) == -1
1194 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1195 || (CONST_DOUBLE_HIGH (op) == 0
1196 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1197 || (GET_CODE (op) == CONST_INT
1198 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1199 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1202 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1203 can fit in an 10 bit immediate field. This is an acceptable DImode
1204 operand for the movrcc instructions. */
1205 /* ??? Replace with arith10_operand? */
1208 arith10_double_operand (rtx op, enum machine_mode mode)
1210 return (register_operand (op, mode)
1211 || (GET_CODE (op) == CONST_DOUBLE
1212 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1213 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1214 && ((CONST_DOUBLE_HIGH (op) == -1
1215 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1216 || (CONST_DOUBLE_HIGH (op) == 0
1217 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1218 || (GET_CODE (op) == CONST_INT
1219 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1220 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1223 /* Return truth value of whether OP is an integer which fits the
1224 range constraining immediate operands in most three-address insns,
1225 which have a 13 bit immediate field. */
1228 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1230 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1234 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1236 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1237 || (GET_CODE (op) == CONST_DOUBLE
1238 && CONST_DOUBLE_HIGH (op) == 0
1239 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1242 /* Recognize operand values for the umul instruction. That instruction sign
1243 extends immediate values just like all other sparc instructions, but
1244 interprets the extended result as an unsigned number. */
1247 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1249 #if HOST_BITS_PER_WIDE_INT > 32
1250 /* All allowed constants will fit a CONST_INT. */
1251 return (GET_CODE (op) == CONST_INT
1252 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1253 || (INTVAL (op) >= 0xFFFFF000
1254 && INTVAL (op) <= 0xFFFFFFFF)));
1256 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1257 || (GET_CODE (op) == CONST_DOUBLE
1258 && CONST_DOUBLE_HIGH (op) == 0
1259 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1264 uns_arith_operand (rtx op, enum machine_mode mode)
1266 return register_operand (op, mode) || uns_small_int (op, mode);
1269 /* Return truth value of statement that OP is a call-clobbered register. */
1271 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1273 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1276 /* Return 1 if OP is a valid operand for the source of a move insn. */
1279 input_operand (rtx op, enum machine_mode mode)
1281 /* If both modes are non-void they must be the same. */
1282 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1285 /* Allow any one instruction integer constant, and all CONST_INT
1286 variants when we are working in DImode and !arch64. */
1287 if (GET_MODE_CLASS (mode) == MODE_INT
1288 && ((GET_CODE (op) == CONST_INT
1289 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1290 || SPARC_SIMM13_P (INTVAL (op))
1292 && ! TARGET_ARCH64)))
1294 && GET_CODE (op) == CONST_DOUBLE
1295 && ((CONST_DOUBLE_HIGH (op) == 0
1296 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1298 #if HOST_BITS_PER_WIDE_INT == 64
1299 (CONST_DOUBLE_HIGH (op) == 0
1300 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1302 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1303 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1304 && CONST_DOUBLE_HIGH (op) == 0)
1305 || (CONST_DOUBLE_HIGH (op) == -1
1306 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1311 /* If !arch64 and this is a DImode const, allow it so that
1312 the splits can be generated. */
1315 && GET_CODE (op) == CONST_DOUBLE)
1318 if (register_operand (op, mode))
1321 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1322 && GET_CODE (op) == CONST_DOUBLE)
1325 /* If this is a SUBREG, look inside so that we handle
1326 paradoxical ones. */
1327 if (GET_CODE (op) == SUBREG)
1328 op = SUBREG_REG (op);
1330 /* Check for valid MEM forms. */
1331 if (GET_CODE (op) == MEM)
1333 rtx inside = XEXP (op, 0);
1335 if (GET_CODE (inside) == LO_SUM)
1337 /* We can't allow these because all of the splits
1338 (eventually as they trickle down into DFmode
1339 splits) require offsettable memory references. */
1341 && GET_MODE (op) == TFmode)
1344 return (register_operand (XEXP (inside, 0), Pmode)
1345 && CONSTANT_P (XEXP (inside, 1)));
1347 return memory_address_p (mode, inside);
1353 /* Return 1 if OP is valid for the lhs of a compare insn. */
1356 compare_operand (rtx op, enum machine_mode mode)
1358 if (GET_CODE (op) == ZERO_EXTRACT)
1359 return (register_operand (XEXP (op, 0), mode)
1360 && small_int_or_double (XEXP (op, 1), mode)
1361 && small_int_or_double (XEXP (op, 2), mode)
1362 /* This matches cmp_zero_extract. */
1364 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1365 && INTVAL (XEXP (op, 2)) > 19)
1366 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1367 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 19)))
1368 /* This matches cmp_zero_extract_sp64. */
1371 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1372 && INTVAL (XEXP (op, 2)) > 51)
1373 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1374 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 51)))));
1376 return register_operand (op, mode);
1380 /* We know it can't be done in one insn when we get here,
1381 the movsi expander guarantees this. */
1383 sparc_emit_set_const32 (rtx op0, rtx op1)
1385 enum machine_mode mode = GET_MODE (op0);
1388 if (GET_CODE (op1) == CONST_INT)
1390 HOST_WIDE_INT value = INTVAL (op1);
1392 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1393 || SPARC_SIMM13_P (value))
1397 /* Full 2-insn decomposition is needed. */
1398 if (reload_in_progress || reload_completed)
1401 temp = gen_reg_rtx (mode);
1403 if (GET_CODE (op1) == CONST_INT)
1405 /* Emit them as real moves instead of a HIGH/LO_SUM,
1406 this way CSE can see everything and reuse intermediate
1407 values if it wants. */
1409 && HOST_BITS_PER_WIDE_INT != 64
1410 && (INTVAL (op1) & 0x80000000) != 0)
1411 emit_insn (gen_rtx_SET
1413 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1416 emit_insn (gen_rtx_SET (VOIDmode, temp,
1417 GEN_INT (INTVAL (op1)
1418 & ~(HOST_WIDE_INT)0x3ff)));
1420 emit_insn (gen_rtx_SET (VOIDmode,
1422 gen_rtx_IOR (mode, temp,
1423 GEN_INT (INTVAL (op1) & 0x3ff))));
1427 /* A symbol, emit in the traditional way. */
1428 emit_insn (gen_rtx_SET (VOIDmode, temp,
1429 gen_rtx_HIGH (mode, op1)));
1430 emit_insn (gen_rtx_SET (VOIDmode,
1431 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1437 /* SPARC-v9 code-model support. */
1439 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp1)
1443 if (temp1 && GET_MODE (temp1) == TImode)
1446 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1449 switch (sparc_cmodel)
1452 /* The range spanned by all instructions in the object is less
1453 than 2^31 bytes (2GB) and the distance from any instruction
1454 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1455 than 2^31 bytes (2GB).
1457 The executable must be in the low 4TB of the virtual address
1460 sethi %hi(symbol), %temp
1461 or %temp, %lo(symbol), %reg */
1462 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1463 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1467 /* The range spanned by all instructions in the object is less
1468 than 2^31 bytes (2GB) and the distance from any instruction
1469 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1470 than 2^31 bytes (2GB).
1472 The executable must be in the low 16TB of the virtual address
1475 sethi %h44(symbol), %temp1
1476 or %temp1, %m44(symbol), %temp2
1477 sllx %temp2, 12, %temp3
1478 or %temp3, %l44(symbol), %reg */
1479 emit_insn (gen_seth44 (op0, op1));
1480 emit_insn (gen_setm44 (op0, op0, op1));
1481 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1482 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1483 emit_insn (gen_setl44 (op0, temp1, op1));
1487 /* The range spanned by all instructions in the object is less
1488 than 2^31 bytes (2GB) and the distance from any instruction
1489 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1490 than 2^31 bytes (2GB).
1492 The executable can be placed anywhere in the virtual address
1495 sethi %hh(symbol), %temp1
1496 sethi %lm(symbol), %temp2
1497 or %temp1, %hm(symbol), %temp3
1498 or %temp2, %lo(symbol), %temp4
1499 sllx %temp3, 32, %temp5
1500 or %temp4, %temp5, %reg */
1502 /* It is possible that one of the registers we got for operands[2]
1503 might coincide with that of operands[0] (which is why we made
1504 it TImode). Pick the other one to use as our scratch. */
1505 if (rtx_equal_p (temp1, op0))
1508 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1513 emit_insn (gen_sethh (op0, op1));
1514 emit_insn (gen_setlm (temp1, op1));
1515 emit_insn (gen_sethm (op0, op0, op1));
1516 emit_insn (gen_rtx_SET (VOIDmode, op0,
1517 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1518 emit_insn (gen_rtx_SET (VOIDmode, op0,
1519 gen_rtx_PLUS (DImode, op0, temp1)));
1520 emit_insn (gen_setlo (op0, op0, op1));
1524 /* Old old old backwards compatibility kruft here.
1525 Essentially it is MEDLOW with a fixed 64-bit
1526 virtual base added to all data segment addresses.
1527 Text-segment stuff is computed like MEDANY, we can't
1528 reuse the code above because the relocation knobs
1531 Data segment: sethi %hi(symbol), %temp1
1532 or %temp1, %lo(symbol), %temp2
1533 add %temp2, EMBMEDANY_BASE_REG, %reg
1535 Text segment: sethi %uhi(symbol), %temp1
1536 sethi %hi(symbol), %temp2
1537 or %temp1, %ulo(symbol), %temp3
1538 or %temp2, %lo(symbol), %temp4
1539 sllx %temp3, 32, %temp5
1540 or %temp4, %temp5, %reg */
1541 if (data_segment_operand (op1, GET_MODE (op1)))
1543 emit_insn (gen_embmedany_sethi (temp1, op1));
1544 emit_insn (gen_embmedany_brsum (op0, temp1));
1545 emit_insn (gen_embmedany_losum (op0, op0, op1));
1549 /* It is possible that one of the registers we got for operands[2]
1550 might coincide with that of operands[0] (which is why we made
1551 it TImode). Pick the other one to use as our scratch. */
1552 if (rtx_equal_p (temp1, op0))
1555 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1560 emit_insn (gen_embmedany_textuhi (op0, op1));
1561 emit_insn (gen_embmedany_texthi (temp1, op1));
1562 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1563 emit_insn (gen_rtx_SET (VOIDmode, op0,
1564 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1565 emit_insn (gen_rtx_SET (VOIDmode, op0,
1566 gen_rtx_PLUS (DImode, op0, temp1)));
1567 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1576 /* These avoid problems when cross compiling. If we do not
1577 go through all this hair then the optimizer will see
1578 invalid REG_EQUAL notes or in some cases none at all. */
1579 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1580 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1581 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1582 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1584 #if HOST_BITS_PER_WIDE_INT == 64
1585 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1586 #define GEN_INT64(__x) GEN_INT (__x)
1588 #define GEN_HIGHINT64(__x) \
1589 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1590 #define GEN_INT64(__x) \
1591 immed_double_const ((__x) & 0xffffffff, \
1592 ((__x) & 0x80000000 ? -1 : 0), DImode)
1595 /* The optimizer is not to assume anything about exactly
1596 which bits are set for a HIGH, they are unspecified.
1597 Unfortunately this leads to many missed optimizations
1598 during CSE. We mask out the non-HIGH bits, and matches
1599 a plain movdi, to alleviate this problem. */
1601 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1603 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1607 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1609 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1613 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1615 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1619 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1621 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1624 /* Worker routines for 64-bit constant formation on arch64.
1625 One of the key things to be doing in these emissions is
1626 to create as many temp REGs as possible. This makes it
1627 possible for half-built constants to be used later when
1628 such values are similar to something required later on.
1629 Without doing this, the optimizer cannot see such
1632 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1633 unsigned HOST_WIDE_INT, int);
1636 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1637 unsigned HOST_WIDE_INT low_bits, int is_neg)
1639 unsigned HOST_WIDE_INT high_bits;
1642 high_bits = (~low_bits) & 0xffffffff;
1644 high_bits = low_bits;
1646 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1649 emit_insn (gen_rtx_SET (VOIDmode, op0,
1650 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1654 /* If we are XOR'ing with -1, then we should emit a one's complement
1655 instead. This way the combiner will notice logical operations
1656 such as ANDN later on and substitute. */
1657 if ((low_bits & 0x3ff) == 0x3ff)
1659 emit_insn (gen_rtx_SET (VOIDmode, op0,
1660 gen_rtx_NOT (DImode, temp)));
1664 emit_insn (gen_rtx_SET (VOIDmode, op0,
1665 gen_safe_XOR64 (temp,
1666 (-(HOST_WIDE_INT)0x400
1667 | (low_bits & 0x3ff)))));
1672 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1673 unsigned HOST_WIDE_INT, int);
1676 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1677 unsigned HOST_WIDE_INT high_bits,
1678 unsigned HOST_WIDE_INT low_immediate,
1683 if ((high_bits & 0xfffffc00) != 0)
1685 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1686 if ((high_bits & ~0xfffffc00) != 0)
1687 emit_insn (gen_rtx_SET (VOIDmode, op0,
1688 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1694 emit_insn (gen_safe_SET64 (temp, high_bits));
1698 /* Now shift it up into place. */
1699 emit_insn (gen_rtx_SET (VOIDmode, op0,
1700 gen_rtx_ASHIFT (DImode, temp2,
1701 GEN_INT (shift_count))));
1703 /* If there is a low immediate part piece, finish up by
1704 putting that in as well. */
1705 if (low_immediate != 0)
1706 emit_insn (gen_rtx_SET (VOIDmode, op0,
1707 gen_safe_OR64 (op0, low_immediate)));
1710 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1711 unsigned HOST_WIDE_INT);
1713 /* Full 64-bit constant decomposition. Even though this is the
1714 'worst' case, we still optimize a few things away. */
1716 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1717 unsigned HOST_WIDE_INT high_bits,
1718 unsigned HOST_WIDE_INT low_bits)
1722 if (reload_in_progress || reload_completed)
1725 sub_temp = gen_reg_rtx (DImode);
1727 if ((high_bits & 0xfffffc00) != 0)
1729 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1730 if ((high_bits & ~0xfffffc00) != 0)
1731 emit_insn (gen_rtx_SET (VOIDmode,
1733 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1739 emit_insn (gen_safe_SET64 (temp, high_bits));
1743 if (!reload_in_progress && !reload_completed)
1745 rtx temp2 = gen_reg_rtx (DImode);
1746 rtx temp3 = gen_reg_rtx (DImode);
1747 rtx temp4 = gen_reg_rtx (DImode);
1749 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1750 gen_rtx_ASHIFT (DImode, sub_temp,
1753 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1754 if ((low_bits & ~0xfffffc00) != 0)
1756 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1757 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1758 emit_insn (gen_rtx_SET (VOIDmode, op0,
1759 gen_rtx_PLUS (DImode, temp4, temp3)));
1763 emit_insn (gen_rtx_SET (VOIDmode, op0,
1764 gen_rtx_PLUS (DImode, temp4, temp2)));
1769 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1770 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1771 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1774 /* We are in the middle of reload, so this is really
1775 painful. However we do still make an attempt to
1776 avoid emitting truly stupid code. */
1777 if (low1 != const0_rtx)
1779 emit_insn (gen_rtx_SET (VOIDmode, op0,
1780 gen_rtx_ASHIFT (DImode, sub_temp,
1781 GEN_INT (to_shift))));
1782 emit_insn (gen_rtx_SET (VOIDmode, op0,
1783 gen_rtx_IOR (DImode, op0, low1)));
1791 if (low2 != const0_rtx)
1793 emit_insn (gen_rtx_SET (VOIDmode, op0,
1794 gen_rtx_ASHIFT (DImode, sub_temp,
1795 GEN_INT (to_shift))));
1796 emit_insn (gen_rtx_SET (VOIDmode, op0,
1797 gen_rtx_IOR (DImode, op0, low2)));
1805 emit_insn (gen_rtx_SET (VOIDmode, op0,
1806 gen_rtx_ASHIFT (DImode, sub_temp,
1807 GEN_INT (to_shift))));
1808 if (low3 != const0_rtx)
1809 emit_insn (gen_rtx_SET (VOIDmode, op0,
1810 gen_rtx_IOR (DImode, op0, low3)));
1815 /* Analyze a 64-bit constant for certain properties. */
1816 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1817 unsigned HOST_WIDE_INT,
1818 int *, int *, int *);
1821 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1822 unsigned HOST_WIDE_INT low_bits,
1823 int *hbsp, int *lbsp, int *abbasp)
1825 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1828 lowest_bit_set = highest_bit_set = -1;
1832 if ((lowest_bit_set == -1)
1833 && ((low_bits >> i) & 1))
1835 if ((highest_bit_set == -1)
1836 && ((high_bits >> (32 - i - 1)) & 1))
1837 highest_bit_set = (64 - i - 1);
1840 && ((highest_bit_set == -1)
1841 || (lowest_bit_set == -1)));
1847 if ((lowest_bit_set == -1)
1848 && ((high_bits >> i) & 1))
1849 lowest_bit_set = i + 32;
1850 if ((highest_bit_set == -1)
1851 && ((low_bits >> (32 - i - 1)) & 1))
1852 highest_bit_set = 32 - i - 1;
1855 && ((highest_bit_set == -1)
1856 || (lowest_bit_set == -1)));
1858 /* If there are no bits set this should have gone out
1859 as one instruction! */
1860 if (lowest_bit_set == -1
1861 || highest_bit_set == -1)
1863 all_bits_between_are_set = 1;
1864 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1868 if ((low_bits & (1 << i)) != 0)
1873 if ((high_bits & (1 << (i - 32))) != 0)
1876 all_bits_between_are_set = 0;
1879 *hbsp = highest_bit_set;
1880 *lbsp = lowest_bit_set;
1881 *abbasp = all_bits_between_are_set;
1884 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1887 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1888 unsigned HOST_WIDE_INT low_bits)
1890 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1893 || high_bits == 0xffffffff)
1896 analyze_64bit_constant (high_bits, low_bits,
1897 &highest_bit_set, &lowest_bit_set,
1898 &all_bits_between_are_set);
1900 if ((highest_bit_set == 63
1901 || lowest_bit_set == 0)
1902 && all_bits_between_are_set != 0)
1905 if ((highest_bit_set - lowest_bit_set) < 21)
1911 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1912 unsigned HOST_WIDE_INT,
1915 static unsigned HOST_WIDE_INT
1916 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1917 unsigned HOST_WIDE_INT low_bits,
1918 int lowest_bit_set, int shift)
1920 HOST_WIDE_INT hi, lo;
1922 if (lowest_bit_set < 32)
1924 lo = (low_bits >> lowest_bit_set) << shift;
1925 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1930 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1937 /* Here we are sure to be arch64 and this is an integer constant
1938 being loaded into a register. Emit the most efficient
1939 insn sequence possible. Detection of all the 1-insn cases
1940 has been done already. */
1942 sparc_emit_set_const64 (rtx op0, rtx op1)
1944 unsigned HOST_WIDE_INT high_bits, low_bits;
1945 int lowest_bit_set, highest_bit_set;
1946 int all_bits_between_are_set;
1949 /* Sanity check that we know what we are working with. */
1950 if (! TARGET_ARCH64)
1953 if (GET_CODE (op0) != SUBREG)
1955 if (GET_CODE (op0) != REG
1956 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1957 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1961 if (reload_in_progress || reload_completed)
1964 temp = gen_reg_rtx (DImode);
1966 if (GET_CODE (op1) != CONST_DOUBLE
1967 && GET_CODE (op1) != CONST_INT)
1969 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1973 if (GET_CODE (op1) == CONST_DOUBLE)
1975 #if HOST_BITS_PER_WIDE_INT == 64
1976 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1977 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1979 high_bits = CONST_DOUBLE_HIGH (op1);
1980 low_bits = CONST_DOUBLE_LOW (op1);
1985 #if HOST_BITS_PER_WIDE_INT == 64
1986 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1987 low_bits = (INTVAL (op1) & 0xffffffff);
1989 high_bits = ((INTVAL (op1) < 0) ?
1992 low_bits = INTVAL (op1);
1996 /* low_bits bits 0 --> 31
1997 high_bits bits 32 --> 63 */
1999 analyze_64bit_constant (high_bits, low_bits,
2000 &highest_bit_set, &lowest_bit_set,
2001 &all_bits_between_are_set);
2003 /* First try for a 2-insn sequence. */
2005 /* These situations are preferred because the optimizer can
2006 * do more things with them:
2008 * sllx %reg, shift, %reg
2010 * srlx %reg, shift, %reg
2011 * 3) mov some_small_const, %reg
2012 * sllx %reg, shift, %reg
2014 if (((highest_bit_set == 63
2015 || lowest_bit_set == 0)
2016 && all_bits_between_are_set != 0)
2017 || ((highest_bit_set - lowest_bit_set) < 12))
2019 HOST_WIDE_INT the_const = -1;
2020 int shift = lowest_bit_set;
2022 if ((highest_bit_set != 63
2023 && lowest_bit_set != 0)
2024 || all_bits_between_are_set == 0)
2027 create_simple_focus_bits (high_bits, low_bits,
2030 else if (lowest_bit_set == 0)
2031 shift = -(63 - highest_bit_set);
2033 if (! SPARC_SIMM13_P (the_const))
2036 emit_insn (gen_safe_SET64 (temp, the_const));
2038 emit_insn (gen_rtx_SET (VOIDmode,
2040 gen_rtx_ASHIFT (DImode,
2044 emit_insn (gen_rtx_SET (VOIDmode,
2046 gen_rtx_LSHIFTRT (DImode,
2048 GEN_INT (-shift))));
2054 /* Now a range of 22 or less bits set somewhere.
2055 * 1) sethi %hi(focus_bits), %reg
2056 * sllx %reg, shift, %reg
2057 * 2) sethi %hi(focus_bits), %reg
2058 * srlx %reg, shift, %reg
2060 if ((highest_bit_set - lowest_bit_set) < 21)
2062 unsigned HOST_WIDE_INT focus_bits =
2063 create_simple_focus_bits (high_bits, low_bits,
2064 lowest_bit_set, 10);
2066 if (! SPARC_SETHI_P (focus_bits))
2069 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2071 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2072 if (lowest_bit_set < 10)
2073 emit_insn (gen_rtx_SET (VOIDmode,
2075 gen_rtx_LSHIFTRT (DImode, temp,
2076 GEN_INT (10 - lowest_bit_set))));
2077 else if (lowest_bit_set > 10)
2078 emit_insn (gen_rtx_SET (VOIDmode,
2080 gen_rtx_ASHIFT (DImode, temp,
2081 GEN_INT (lowest_bit_set - 10))));
2087 /* 1) sethi %hi(low_bits), %reg
2088 * or %reg, %lo(low_bits), %reg
2089 * 2) sethi %hi(~low_bits), %reg
2090 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2093 || high_bits == 0xffffffff)
2095 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2096 (high_bits == 0xffffffff));
2100 /* Now, try 3-insn sequences. */
2102 /* 1) sethi %hi(high_bits), %reg
2103 * or %reg, %lo(high_bits), %reg
2104 * sllx %reg, 32, %reg
2108 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2112 /* We may be able to do something quick
2113 when the constant is negated, so try that. */
2114 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2115 (~low_bits) & 0xfffffc00))
2117 /* NOTE: The trailing bits get XOR'd so we need the
2118 non-negated bits, not the negated ones. */
2119 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2121 if ((((~high_bits) & 0xffffffff) == 0
2122 && ((~low_bits) & 0x80000000) == 0)
2123 || (((~high_bits) & 0xffffffff) == 0xffffffff
2124 && ((~low_bits) & 0x80000000) != 0))
2126 int fast_int = (~low_bits & 0xffffffff);
2128 if ((SPARC_SETHI_P (fast_int)
2129 && (~high_bits & 0xffffffff) == 0)
2130 || SPARC_SIMM13_P (fast_int))
2131 emit_insn (gen_safe_SET64 (temp, fast_int));
2133 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2138 #if HOST_BITS_PER_WIDE_INT == 64
2139 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2140 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2142 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2143 (~high_bits) & 0xffffffff,
2146 sparc_emit_set_const64 (temp, negated_const);
2149 /* If we are XOR'ing with -1, then we should emit a one's complement
2150 instead. This way the combiner will notice logical operations
2151 such as ANDN later on and substitute. */
2152 if (trailing_bits == 0x3ff)
2154 emit_insn (gen_rtx_SET (VOIDmode, op0,
2155 gen_rtx_NOT (DImode, temp)));
2159 emit_insn (gen_rtx_SET (VOIDmode,
2161 gen_safe_XOR64 (temp,
2162 (-0x400 | trailing_bits))));
2167 /* 1) sethi %hi(xxx), %reg
2168 * or %reg, %lo(xxx), %reg
2169 * sllx %reg, yyy, %reg
2171 * ??? This is just a generalized version of the low_bits==0
2172 * thing above, FIXME...
2174 if ((highest_bit_set - lowest_bit_set) < 32)
2176 unsigned HOST_WIDE_INT focus_bits =
2177 create_simple_focus_bits (high_bits, low_bits,
2180 /* We can't get here in this state. */
2181 if (highest_bit_set < 32
2182 || lowest_bit_set >= 32)
2185 /* So what we know is that the set bits straddle the
2186 middle of the 64-bit word. */
2187 sparc_emit_set_const64_quick2 (op0, temp,
2193 /* 1) sethi %hi(high_bits), %reg
2194 * or %reg, %lo(high_bits), %reg
2195 * sllx %reg, 32, %reg
2196 * or %reg, low_bits, %reg
2198 if (SPARC_SIMM13_P(low_bits)
2199 && ((int)low_bits > 0))
2201 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2205 /* The easiest way when all else fails, is full decomposition. */
2207 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2208 high_bits, low_bits, ~high_bits, ~low_bits);
2210 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2213 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2214 return the mode to be used for the comparison. For floating-point,
2215 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2216 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2217 processing is needed. */
2220 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2222 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2248 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2249 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2251 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2252 return CCX_NOOVmode;
2258 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2265 /* X and Y are two things to compare using CODE. Emit the compare insn and
2266 return the rtx for the cc reg in the proper mode. */
2269 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2271 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2274 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2275 fcc regs (cse can't tell they're really call clobbered regs and will
2276 remove a duplicate comparison even if there is an intervening function
2277 call - it will then try to reload the cc reg via an int reg which is why
2278 we need the movcc patterns). It is possible to provide the movcc
2279 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2280 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2281 to tell cse that CCFPE mode registers (even pseudos) are call
2284 /* ??? This is an experiment. Rather than making changes to cse which may
2285 or may not be easy/clean, we do our own cse. This is possible because
2286 we will generate hard registers. Cse knows they're call clobbered (it
2287 doesn't know the same thing about pseudos). If we guess wrong, no big
2288 deal, but if we win, great! */
2290 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2291 #if 1 /* experiment */
2294 /* We cycle through the registers to ensure they're all exercised. */
2295 static int next_fcc_reg = 0;
2296 /* Previous x,y for each fcc reg. */
2297 static rtx prev_args[4][2];
2299 /* Scan prev_args for x,y. */
2300 for (reg = 0; reg < 4; reg++)
2301 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2306 prev_args[reg][0] = x;
2307 prev_args[reg][1] = y;
2308 next_fcc_reg = (next_fcc_reg + 1) & 3;
2310 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2313 cc_reg = gen_reg_rtx (mode);
2314 #endif /* ! experiment */
2315 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2316 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2318 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2320 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2321 gen_rtx_COMPARE (mode, x, y)));
2326 /* This function is used for v9 only.
2327 CODE is the code for an Scc's comparison.
2328 OPERANDS[0] is the target of the Scc insn.
2329 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2330 been generated yet).
2332 This function is needed to turn
2335 (gt (reg:CCX 100 %icc)
2339 (gt:DI (reg:CCX 100 %icc)
2342 IE: The instruction recognizer needs to see the mode of the comparison to
2343 find the right instruction. We could use "gt:DI" right in the
2344 define_expand, but leaving it out allows us to handle DI, SI, etc.
2346 We refer to the global sparc compare operands sparc_compare_op0 and
2347 sparc_compare_op1. */
2350 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2355 && (GET_MODE (sparc_compare_op0) == DImode
2356 || GET_MODE (operands[0]) == DImode))
2359 op0 = sparc_compare_op0;
2360 op1 = sparc_compare_op1;
2362 /* Try to use the movrCC insns. */
2364 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2365 && op1 == const0_rtx
2366 && v9_regcmp_p (compare_code))
2368 /* Special case for op0 != 0. This can be done with one instruction if
2369 operands[0] == sparc_compare_op0. */
2371 if (compare_code == NE
2372 && GET_MODE (operands[0]) == DImode
2373 && rtx_equal_p (op0, operands[0]))
2375 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2376 gen_rtx_IF_THEN_ELSE (DImode,
2377 gen_rtx_fmt_ee (compare_code, DImode,
2384 if (reg_overlap_mentioned_p (operands[0], op0))
2386 /* Handle the case where operands[0] == sparc_compare_op0.
2387 We "early clobber" the result. */
2388 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2389 emit_move_insn (op0, sparc_compare_op0);
2392 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2393 if (GET_MODE (op0) != DImode)
2395 temp = gen_reg_rtx (DImode);
2396 convert_move (temp, op0, 0);
2400 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2401 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2402 gen_rtx_fmt_ee (compare_code, DImode,
2410 operands[1] = gen_compare_reg (compare_code, op0, op1);
2412 switch (GET_MODE (operands[1]))
2422 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2423 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2424 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2425 gen_rtx_fmt_ee (compare_code,
2426 GET_MODE (operands[1]),
2427 operands[1], const0_rtx),
2428 const1_rtx, operands[0])));
2433 /* Emit a conditional jump insn for the v9 architecture using comparison code
2434 CODE and jump target LABEL.
2435 This function exists to take advantage of the v9 brxx insns. */
2438 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2440 emit_jump_insn (gen_rtx_SET (VOIDmode,
2442 gen_rtx_IF_THEN_ELSE (VOIDmode,
2443 gen_rtx_fmt_ee (code, GET_MODE (op0),
2445 gen_rtx_LABEL_REF (VOIDmode, label),
2449 /* Generate a DFmode part of a hard TFmode register.
2450 REG is the TFmode hard register, LOW is 1 for the
2451 low 64bit of the register and 0 otherwise.
2454 gen_df_reg (rtx reg, int low)
2456 int regno = REGNO (reg);
2458 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2459 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2460 return gen_rtx_REG (DFmode, regno);
2463 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2464 Unlike normal calls, TFmode operands are passed by reference. It is
2465 assumed that no more than 3 operands are required. */
2468 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2470 rtx ret_slot = NULL, arg[3], func_sym;
2473 /* We only expect to be called for conversions, unary, and binary ops. */
2474 if (nargs < 2 || nargs > 3)
2477 for (i = 0; i < nargs; ++i)
2479 rtx this_arg = operands[i];
2482 /* TFmode arguments and return values are passed by reference. */
2483 if (GET_MODE (this_arg) == TFmode)
2485 int force_stack_temp;
2487 force_stack_temp = 0;
2488 if (TARGET_BUGGY_QP_LIB && i == 0)
2489 force_stack_temp = 1;
2491 if (GET_CODE (this_arg) == MEM
2492 && ! force_stack_temp)
2493 this_arg = XEXP (this_arg, 0);
2494 else if (CONSTANT_P (this_arg)
2495 && ! force_stack_temp)
2497 this_slot = force_const_mem (TFmode, this_arg);
2498 this_arg = XEXP (this_slot, 0);
2502 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2504 /* Operand 0 is the return value. We'll copy it out later. */
2506 emit_move_insn (this_slot, this_arg);
2508 ret_slot = this_slot;
2510 this_arg = XEXP (this_slot, 0);
2517 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2519 if (GET_MODE (operands[0]) == TFmode)
2522 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2523 arg[0], GET_MODE (arg[0]),
2524 arg[1], GET_MODE (arg[1]));
2526 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2527 arg[0], GET_MODE (arg[0]),
2528 arg[1], GET_MODE (arg[1]),
2529 arg[2], GET_MODE (arg[2]));
2532 emit_move_insn (operands[0], ret_slot);
2541 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2542 GET_MODE (operands[0]), 1,
2543 arg[1], GET_MODE (arg[1]));
2545 if (ret != operands[0])
2546 emit_move_insn (operands[0], ret);
2550 /* Expand soft-float TFmode calls to sparc abi routines. */
2553 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2575 emit_soft_tfmode_libcall (func, 3, operands);
2579 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2592 emit_soft_tfmode_libcall (func, 2, operands);
2596 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2603 switch (GET_MODE (operands[1]))
2616 case FLOAT_TRUNCATE:
2617 switch (GET_MODE (operands[0]))
2631 switch (GET_MODE (operands[1]))
2644 case UNSIGNED_FLOAT:
2645 switch (GET_MODE (operands[1]))
2659 switch (GET_MODE (operands[0]))
2673 switch (GET_MODE (operands[0]))
2690 emit_soft_tfmode_libcall (func, 2, operands);
2693 /* Expand a hard-float tfmode operation. All arguments must be in
2697 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2701 if (GET_RTX_CLASS (code) == RTX_UNARY)
2703 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2704 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2708 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2709 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2710 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2711 operands[1], operands[2]);
2714 if (register_operand (operands[0], VOIDmode))
2717 dest = gen_reg_rtx (GET_MODE (operands[0]));
2719 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2721 if (dest != operands[0])
2722 emit_move_insn (operands[0], dest);
2726 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2728 if (TARGET_HARD_QUAD)
2729 emit_hard_tfmode_operation (code, operands);
2731 emit_soft_tfmode_binop (code, operands);
2735 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2737 if (TARGET_HARD_QUAD)
2738 emit_hard_tfmode_operation (code, operands);
2740 emit_soft_tfmode_unop (code, operands);
2744 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2746 if (TARGET_HARD_QUAD)
2747 emit_hard_tfmode_operation (code, operands);
2749 emit_soft_tfmode_cvt (code, operands);
2752 /* Return nonzero if a return peephole merging return with
2753 setting of output register is ok. */
2755 leaf_return_peephole_ok (void)
2757 return (actual_fsize == 0);
2760 /* Return nonzero if a branch/jump/call instruction will be emitting
2761 nop into its delay slot. */
2764 empty_delay_slot (rtx insn)
2768 /* If no previous instruction (should not happen), return true. */
2769 if (PREV_INSN (insn) == NULL)
2772 seq = NEXT_INSN (PREV_INSN (insn));
2773 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2779 /* Return nonzero if TRIAL can go into the function epilogue's
2780 delay slot. SLOT is the slot we are trying to fill. */
2783 eligible_for_epilogue_delay (rtx trial, int slot)
2790 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2793 if (get_attr_length (trial) != 1)
2796 /* If there are any call-saved registers, we should scan TRIAL if it
2797 does not reference them. For now just make it easy. */
2801 /* If the function uses __builtin_eh_return, the eh_return machinery
2802 occupies the delay slot. */
2803 if (current_function_calls_eh_return)
2806 /* In the case of a true leaf function, anything can go into the delay slot.
2807 A delay slot only exists however if the frame size is zero, otherwise
2808 we will put an insn to adjust the stack after the return. */
2809 if (current_function_uses_only_leaf_regs)
2811 if (leaf_return_peephole_ok ())
2812 return ((get_attr_in_uncond_branch_delay (trial)
2813 == IN_BRANCH_DELAY_TRUE));
2817 pat = PATTERN (trial);
2819 /* Otherwise, only operations which can be done in tandem with
2820 a `restore' or `return' insn can go into the delay slot. */
2821 if (GET_CODE (SET_DEST (pat)) != REG
2822 || REGNO (SET_DEST (pat)) < 24)
2825 /* If this instruction sets up floating point register and we have a return
2826 instruction, it can probably go in. But restore will not work
2828 if (REGNO (SET_DEST (pat)) >= 32)
2830 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2831 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2836 /* The set of insns matched here must agree precisely with the set of
2837 patterns paired with a RETURN in sparc.md. */
2839 src = SET_SRC (pat);
2841 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2842 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2843 && arith_operand (src, GET_MODE (src)))
2846 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2848 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2851 /* This matches "*return_di". */
2852 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2853 && arith_double_operand (src, GET_MODE (src)))
2854 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2856 /* This matches "*return_sf_no_fpu". */
2857 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2858 && register_operand (src, SFmode))
2861 /* If we have return instruction, anything that does not use
2862 local or output registers and can go into a delay slot wins. */
2863 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2864 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2867 /* This matches "*return_addsi". */
2868 else if (GET_CODE (src) == PLUS
2869 && arith_operand (XEXP (src, 0), SImode)
2870 && arith_operand (XEXP (src, 1), SImode)
2871 && (register_operand (XEXP (src, 0), SImode)
2872 || register_operand (XEXP (src, 1), SImode)))
2875 /* This matches "*return_adddi". */
2876 else if (GET_CODE (src) == PLUS
2877 && arith_double_operand (XEXP (src, 0), DImode)
2878 && arith_double_operand (XEXP (src, 1), DImode)
2879 && (register_operand (XEXP (src, 0), DImode)
2880 || register_operand (XEXP (src, 1), DImode)))
2883 /* This can match "*return_losum_[sd]i".
2884 Catch only some cases, so that return_losum* don't have
2886 else if (GET_CODE (src) == LO_SUM
2887 && ! TARGET_CM_MEDMID
2888 && ((register_operand (XEXP (src, 0), SImode)
2889 && immediate_operand (XEXP (src, 1), SImode))
2891 && register_operand (XEXP (src, 0), DImode)
2892 && immediate_operand (XEXP (src, 1), DImode))))
2895 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2896 else if (GET_CODE (src) == ASHIFT
2897 && (register_operand (XEXP (src, 0), SImode)
2898 || register_operand (XEXP (src, 0), DImode))
2899 && XEXP (src, 1) == const1_rtx)
2905 /* Return nonzero if TRIAL can go into the call delay slot. */
2907 tls_call_delay (rtx trial)
2912 call __tls_get_addr, %tgd_call (foo)
2913 add %l7, %o0, %o0, %tgd_add (foo)
2914 while Sun as/ld does not. */
2915 if (TARGET_GNU_TLS || !TARGET_TLS)
2918 pat = PATTERN (trial);
2919 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
2922 unspec = XEXP (SET_DEST (pat), 1);
2923 if (GET_CODE (unspec) != UNSPEC
2924 || (XINT (unspec, 1) != UNSPEC_TLSGD
2925 && XINT (unspec, 1) != UNSPEC_TLSLDM))
2931 /* Return nonzero if TRIAL can go into the sibling call
2935 eligible_for_sibcall_delay (rtx trial)
2939 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2942 if (get_attr_length (trial) != 1)
2945 pat = PATTERN (trial);
2947 if (current_function_uses_only_leaf_regs)
2949 /* If the tail call is done using the call instruction,
2950 we have to restore %o7 in the delay slot. */
2951 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2954 /* %g1 is used to build the function address */
2955 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2961 /* Otherwise, only operations which can be done in tandem with
2962 a `restore' insn can go into the delay slot. */
2963 if (GET_CODE (SET_DEST (pat)) != REG
2964 || REGNO (SET_DEST (pat)) < 24
2965 || REGNO (SET_DEST (pat)) >= 32)
2968 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2970 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2973 src = SET_SRC (pat);
2975 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2976 && arith_operand (src, GET_MODE (src)))
2979 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2981 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2984 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2985 && arith_double_operand (src, GET_MODE (src)))
2986 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2988 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2989 && register_operand (src, SFmode))
2992 else if (GET_CODE (src) == PLUS
2993 && arith_operand (XEXP (src, 0), SImode)
2994 && arith_operand (XEXP (src, 1), SImode)
2995 && (register_operand (XEXP (src, 0), SImode)
2996 || register_operand (XEXP (src, 1), SImode)))
2999 else if (GET_CODE (src) == PLUS
3000 && arith_double_operand (XEXP (src, 0), DImode)
3001 && arith_double_operand (XEXP (src, 1), DImode)
3002 && (register_operand (XEXP (src, 0), DImode)
3003 || register_operand (XEXP (src, 1), DImode)))
3006 else if (GET_CODE (src) == LO_SUM
3007 && ! TARGET_CM_MEDMID
3008 && ((register_operand (XEXP (src, 0), SImode)
3009 && immediate_operand (XEXP (src, 1), SImode))
3011 && register_operand (XEXP (src, 0), DImode)
3012 && immediate_operand (XEXP (src, 1), DImode))))
3015 else if (GET_CODE (src) == ASHIFT
3016 && (register_operand (XEXP (src, 0), SImode)
3017 || register_operand (XEXP (src, 0), DImode))
3018 && XEXP (src, 1) == const1_rtx)
3025 check_return_regs (rtx x)
3027 switch (GET_CODE (x))
3030 return IN_OR_GLOBAL_P (x);
3045 if (check_return_regs (XEXP (x, 1)) == 0)
3050 return check_return_regs (XEXP (x, 0));
3059 short_branch (int uid1, int uid2)
3061 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3063 /* Leave a few words of "slop". */
3064 if (delta >= -1023 && delta <= 1022)
3070 /* Return nonzero if REG is not used after INSN.
3071 We assume REG is a reload reg, and therefore does
3072 not live past labels or calls or jumps. */
3074 reg_unused_after (rtx reg, rtx insn)
3076 enum rtx_code code, prev_code = UNKNOWN;
3078 while ((insn = NEXT_INSN (insn)))
3080 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3083 code = GET_CODE (insn);
3084 if (GET_CODE (insn) == CODE_LABEL)
3089 rtx set = single_set (insn);
3090 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3093 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3095 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3103 /* Determine if it's legal to put X into the constant pool. This
3104 is not possible if X contains the address of a symbol that is
3105 not constant (TLS) or not known at final link time (PIC). */
3108 sparc_cannot_force_const_mem (rtx x)
3110 switch (GET_CODE (x))
3114 /* Accept all non-symbolic constants. */
3118 /* Labels are OK iff we are non-PIC. */
3119 return flag_pic != 0;
3122 /* 'Naked' TLS symbol references are never OK,
3123 non-TLS symbols are OK iff we are non-PIC. */
3124 if (SYMBOL_REF_TLS_MODEL (x))
3127 return flag_pic != 0;
3130 return sparc_cannot_force_const_mem (XEXP (x, 0));
3133 return sparc_cannot_force_const_mem (XEXP (x, 0))
3134 || sparc_cannot_force_const_mem (XEXP (x, 1));
3142 /* The table we use to reference PIC data. */
3143 static GTY(()) rtx global_offset_table;
3145 /* The function we use to get at it. */
3146 static GTY(()) rtx get_pc_symbol;
3147 static GTY(()) char get_pc_symbol_name[256];
3149 /* Ensure that we are not using patterns that are not OK with PIC. */
3157 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3158 || (GET_CODE (recog_data.operand[i]) == CONST
3159 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3160 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3161 == global_offset_table)
3162 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3171 /* Return true if X is an address which needs a temporary register when
3172 reloaded while generating PIC code. */
3175 pic_address_needs_scratch (rtx x)
3177 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3178 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3179 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3180 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3181 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3187 /* Determine if a given RTX is a valid constant. We already know this
3188 satisfies CONSTANT_P. */
3191 legitimate_constant_p (rtx x)
3195 switch (GET_CODE (x))
3198 /* TLS symbols are not constant. */
3199 if (SYMBOL_REF_TLS_MODEL (x))
3204 inner = XEXP (x, 0);
3206 /* Offsets of TLS symbols are never valid.
3207 Discourage CSE from creating them. */
3208 if (GET_CODE (inner) == PLUS
3209 && tls_symbolic_operand (XEXP (inner, 0)))
3214 if (GET_MODE (x) == VOIDmode)
3217 /* Floating point constants are generally not ok.
3218 The only exception is 0.0 in VIS. */
3220 && (GET_MODE (x) == SFmode
3221 || GET_MODE (x) == DFmode
3222 || GET_MODE (x) == TFmode)
3223 && fp_zero_operand (x, GET_MODE (x)))
3235 /* Determine if a given RTX is a valid constant address. */
3238 constant_address_p (rtx x)
3240 switch (GET_CODE (x))
3248 if (flag_pic && pic_address_needs_scratch (x))
3250 return legitimate_constant_p (x);
3253 return !flag_pic && legitimate_constant_p (x);
3260 /* Nonzero if the constant value X is a legitimate general operand
3261 when generating PIC code. It is given that flag_pic is on and
3262 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3265 legitimate_pic_operand_p (rtx x)
3267 if (pic_address_needs_scratch (x))
3269 if (tls_symbolic_operand (x)
3270 || (GET_CODE (x) == CONST
3271 && GET_CODE (XEXP (x, 0)) == PLUS
3272 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3277 /* Return nonzero if ADDR is a valid memory address.
3278 STRICT specifies whether strict register checking applies. */
3281 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3283 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3285 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3287 else if (GET_CODE (addr) == PLUS)
3289 rs1 = XEXP (addr, 0);
3290 rs2 = XEXP (addr, 1);
3292 /* Canonicalize. REG comes first, if there are no regs,
3293 LO_SUM comes first. */
3295 && GET_CODE (rs1) != SUBREG
3297 || GET_CODE (rs2) == SUBREG
3298 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3300 rs1 = XEXP (addr, 1);
3301 rs2 = XEXP (addr, 0);
3305 && rs1 == pic_offset_table_rtx
3307 && GET_CODE (rs2) != SUBREG
3308 && GET_CODE (rs2) != LO_SUM
3309 && GET_CODE (rs2) != MEM
3310 && !tls_symbolic_operand (rs2)
3311 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3312 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3314 || GET_CODE (rs1) == SUBREG)
3315 && RTX_OK_FOR_OFFSET_P (rs2)))
3320 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3321 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3323 /* We prohibit REG + REG for TFmode when there are no instructions
3324 which accept REG+REG instructions. We do this because REG+REG
3325 is not an offsetable address. If we get the situation in reload
3326 where source and destination of a movtf pattern are both MEMs with
3327 REG+REG address, then only one of them gets converted to an
3328 offsetable address. */
3330 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3331 && TARGET_HARD_QUAD))
3334 /* We prohibit REG + REG on ARCH32 if not optimizing for
3335 DFmode/DImode because then mem_min_alignment is likely to be zero
3336 after reload and the forced split would lack a matching splitter
3338 if (TARGET_ARCH32 && !optimize
3339 && (mode == DFmode || mode == DImode))
3342 else if (USE_AS_OFFSETABLE_LO10
3343 && GET_CODE (rs1) == LO_SUM
3345 && ! TARGET_CM_MEDMID
3346 && RTX_OK_FOR_OLO10_P (rs2))
3350 imm1 = XEXP (rs1, 1);
3351 rs1 = XEXP (rs1, 0);
3352 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3356 else if (GET_CODE (addr) == LO_SUM)
3358 rs1 = XEXP (addr, 0);
3359 imm1 = XEXP (addr, 1);
3361 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3364 /* We can't allow TFmode, because an offset greater than or equal to the
3365 alignment (8) may cause the LO_SUM to overflow if !v9. */
3366 if (mode == TFmode && !TARGET_V9)
3369 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3374 if (GET_CODE (rs1) == SUBREG)
3375 rs1 = SUBREG_REG (rs1);
3381 if (GET_CODE (rs2) == SUBREG)
3382 rs2 = SUBREG_REG (rs2);
3389 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3390 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3395 if ((REGNO (rs1) >= 32
3396 && REGNO (rs1) != FRAME_POINTER_REGNUM
3397 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3399 && (REGNO (rs2) >= 32
3400 && REGNO (rs2) != FRAME_POINTER_REGNUM
3401 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3407 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3409 static GTY(()) rtx sparc_tls_symbol;
3411 sparc_tls_get_addr (void)
3413 if (!sparc_tls_symbol)
3414 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3416 return sparc_tls_symbol;
3420 sparc_tls_got (void)
3425 current_function_uses_pic_offset_table = 1;
3426 return pic_offset_table_rtx;
3429 if (!global_offset_table)
3430 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3431 temp = gen_reg_rtx (Pmode);
3432 emit_move_insn (temp, global_offset_table);
3437 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3438 this (thread-local) address. */
3441 legitimize_tls_address (rtx addr)
3443 rtx temp1, temp2, temp3, ret, o0, got, insn;
3448 if (GET_CODE (addr) == SYMBOL_REF)
3449 switch (SYMBOL_REF_TLS_MODEL (addr))
3451 case TLS_MODEL_GLOBAL_DYNAMIC:
3453 temp1 = gen_reg_rtx (SImode);
3454 temp2 = gen_reg_rtx (SImode);
3455 ret = gen_reg_rtx (Pmode);
3456 o0 = gen_rtx_REG (Pmode, 8);
3457 got = sparc_tls_got ();
3458 emit_insn (gen_tgd_hi22 (temp1, addr));
3459 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3462 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3463 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3468 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3469 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3472 CALL_INSN_FUNCTION_USAGE (insn)
3473 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3474 CALL_INSN_FUNCTION_USAGE (insn));
3475 insn = get_insns ();
3477 emit_libcall_block (insn, ret, o0, addr);
3480 case TLS_MODEL_LOCAL_DYNAMIC:
3482 temp1 = gen_reg_rtx (SImode);
3483 temp2 = gen_reg_rtx (SImode);
3484 temp3 = gen_reg_rtx (Pmode);
3485 ret = gen_reg_rtx (Pmode);
3486 o0 = gen_rtx_REG (Pmode, 8);
3487 got = sparc_tls_got ();
3488 emit_insn (gen_tldm_hi22 (temp1));
3489 emit_insn (gen_tldm_lo10 (temp2, temp1));
3492 emit_insn (gen_tldm_add32 (o0, got, temp2));
3493 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3498 emit_insn (gen_tldm_add64 (o0, got, temp2));
3499 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3502 CALL_INSN_FUNCTION_USAGE (insn)
3503 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3504 CALL_INSN_FUNCTION_USAGE (insn));
3505 insn = get_insns ();
3507 emit_libcall_block (insn, temp3, o0,
3508 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3509 UNSPEC_TLSLD_BASE));
3510 temp1 = gen_reg_rtx (SImode);
3511 temp2 = gen_reg_rtx (SImode);
3512 emit_insn (gen_tldo_hix22 (temp1, addr));
3513 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3515 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3517 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3520 case TLS_MODEL_INITIAL_EXEC:
3521 temp1 = gen_reg_rtx (SImode);
3522 temp2 = gen_reg_rtx (SImode);
3523 temp3 = gen_reg_rtx (Pmode);
3524 got = sparc_tls_got ();
3525 emit_insn (gen_tie_hi22 (temp1, addr));
3526 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3528 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3530 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3533 ret = gen_reg_rtx (Pmode);
3535 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3538 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3542 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3545 case TLS_MODEL_LOCAL_EXEC:
3546 temp1 = gen_reg_rtx (Pmode);
3547 temp2 = gen_reg_rtx (Pmode);
3550 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3551 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3555 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3556 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3558 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3566 abort (); /* for now ... */
3572 /* Legitimize PIC addresses. If the address is already position-independent,
3573 we return ORIG. Newly generated position-independent addresses go into a
3574 reg. This is REG if nonzero, otherwise we allocate register(s) as
3578 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3581 if (GET_CODE (orig) == SYMBOL_REF)
3583 rtx pic_ref, address;
3588 if (reload_in_progress || reload_completed)
3591 reg = gen_reg_rtx (Pmode);
3596 /* If not during reload, allocate another temp reg here for loading
3597 in the address, so that these instructions can be optimized
3599 rtx temp_reg = ((reload_in_progress || reload_completed)
3600 ? reg : gen_reg_rtx (Pmode));
3602 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3603 won't get confused into thinking that these two instructions
3604 are loading in the true address of the symbol. If in the
3605 future a PIC rtx exists, that should be used instead. */
3606 if (Pmode == SImode)
3608 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3609 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3613 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3614 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3621 pic_ref = gen_rtx_MEM (Pmode,
3622 gen_rtx_PLUS (Pmode,
3623 pic_offset_table_rtx, address));
3624 current_function_uses_pic_offset_table = 1;
3625 RTX_UNCHANGING_P (pic_ref) = 1;
3626 insn = emit_move_insn (reg, pic_ref);
3627 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3629 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3633 else if (GET_CODE (orig) == CONST)
3637 if (GET_CODE (XEXP (orig, 0)) == PLUS
3638 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3643 if (reload_in_progress || reload_completed)
3646 reg = gen_reg_rtx (Pmode);
3649 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3651 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3652 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3653 base == reg ? 0 : reg);
3658 if (GET_CODE (offset) == CONST_INT)
3660 if (SMALL_INT (offset))
3661 return plus_constant (base, INTVAL (offset));
3662 else if (! reload_in_progress && ! reload_completed)
3663 offset = force_reg (Pmode, offset);
3665 /* If we reach here, then something is seriously wrong. */
3668 return gen_rtx_PLUS (Pmode, base, offset);
3670 else if (GET_CODE (orig) == LABEL_REF)
3671 /* ??? Why do we do this? */
3672 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3673 the register is live instead, in case it is eliminated. */
3674 current_function_uses_pic_offset_table = 1;
3679 /* Try machine-dependent ways of modifying an illegitimate address X
3680 to be legitimate. If we find one, return the new, valid address.
3682 OLDX is the address as it was before break_out_memory_refs was called.
3683 In some cases it is useful to look at this to decide what needs to be done.
3685 MODE is the mode of the operand pointed to by X. */
3688 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3692 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3693 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3694 force_operand (XEXP (x, 0), NULL_RTX));
3695 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3696 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3697 force_operand (XEXP (x, 1), NULL_RTX));
3698 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3699 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3701 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3702 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3703 force_operand (XEXP (x, 1), NULL_RTX));
3705 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3708 if (tls_symbolic_operand (x))
3709 x = legitimize_tls_address (x);
3711 x = legitimize_pic_address (x, mode, 0);
3712 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3713 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3714 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3715 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3716 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3717 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3718 else if (GET_CODE (x) == SYMBOL_REF
3719 || GET_CODE (x) == CONST
3720 || GET_CODE (x) == LABEL_REF)
3721 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3725 /* Emit special PIC prologues. */
3728 load_pic_register (void)
3730 /* Labels to get the PC in the prologue of this function. */
3731 int orig_flag_pic = flag_pic;
3736 /* If we haven't emitted the special get_pc helper function, do so now. */
3737 if (get_pc_symbol_name[0] == 0)
3741 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3744 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3746 ASM_OUTPUT_ALIGN (asm_out_file, align);
3747 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
3748 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3751 /* Initialize every time through, since we can't easily
3752 know this to be permanent. */
3753 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3754 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3757 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3760 flag_pic = orig_flag_pic;
3762 /* Need to emit this whether or not we obey regdecls,
3763 since setjmp/longjmp can cause life info to screw up.
3764 ??? In the case where we don't obey regdecls, this is not sufficient
3765 since we may not fall out the bottom. */
3766 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3769 /* Return 1 if RTX is a MEM which is known to be aligned to at
3770 least a DESIRED byte boundary. */
3773 mem_min_alignment (rtx mem, int desired)
3775 rtx addr, base, offset;
3777 /* If it's not a MEM we can't accept it. */
3778 if (GET_CODE (mem) != MEM)
3781 addr = XEXP (mem, 0);
3782 base = offset = NULL_RTX;
3783 if (GET_CODE (addr) == PLUS)
3785 if (GET_CODE (XEXP (addr, 0)) == REG)
3787 base = XEXP (addr, 0);
3789 /* What we are saying here is that if the base
3790 REG is aligned properly, the compiler will make
3791 sure any REG based index upon it will be so
3793 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3794 offset = XEXP (addr, 1);
3796 offset = const0_rtx;
3799 else if (GET_CODE (addr) == REG)
3802 offset = const0_rtx;
3805 if (base != NULL_RTX)
3807 int regno = REGNO (base);
3809 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3811 /* Check if the compiler has recorded some information
3812 about the alignment of the base REG. If reload has
3813 completed, we already matched with proper alignments.
3814 If not running global_alloc, reload might give us
3815 unaligned pointer to local stack though. */
3817 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3818 || (optimize && reload_completed))
3819 && (INTVAL (offset) & (desired - 1)) == 0)
3824 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3828 else if (! TARGET_UNALIGNED_DOUBLES
3829 || CONSTANT_P (addr)
3830 || GET_CODE (addr) == LO_SUM)
3832 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3833 is true, in which case we can only assume that an access is aligned if
3834 it is to a constant address, or the address involves a LO_SUM. */
3838 /* An obviously unaligned address. */
3843 /* Vectors to keep interesting information about registers where it can easily
3844 be got. We used to use the actual mode value as the bit number, but there
3845 are more than 32 modes now. Instead we use two tables: one indexed by
3846 hard register number, and one indexed by mode. */
3848 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3849 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3850 mapped into one sparc_mode_class mode. */
3852 enum sparc_mode_class {
3853 S_MODE, D_MODE, T_MODE, O_MODE,
3854 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3858 /* Modes for single-word and smaller quantities. */
3859 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3861 /* Modes for double-word and smaller quantities. */
3862 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3864 /* Modes for quad-word and smaller quantities. */
3865 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3867 /* Modes for 8-word and smaller quantities. */
3868 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3870 /* Modes for single-float quantities. We must allow any single word or
3871 smaller quantity. This is because the fix/float conversion instructions
3872 take integer inputs/outputs from the float registers. */
3873 #define SF_MODES (S_MODES)
3875 /* Modes for double-float and smaller quantities. */
3876 #define DF_MODES (S_MODES | D_MODES)
3878 /* Modes for double-float only quantities. */
3879 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3881 /* Modes for quad-float only quantities. */
3882 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3884 /* Modes for quad-float and smaller quantities. */
3885 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3887 /* Modes for quad-float and double-float quantities. */
3888 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3890 /* Modes for quad-float pair only quantities. */
3891 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3893 /* Modes for quad-float pairs and smaller quantities. */
3894 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3896 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3898 /* Modes for condition codes. */
3899 #define CC_MODES (1 << (int) CC_MODE)
3900 #define CCFP_MODES (1 << (int) CCFP_MODE)
3902 /* Value is 1 if register/mode pair is acceptable on sparc.
3903 The funny mixture of D and T modes is because integer operations
3904 do not specially operate on tetra quantities, so non-quad-aligned
3905 registers can hold quadword quantities (except %o4 and %i4 because
3906 they cross fixed registers). */
3908 /* This points to either the 32 bit or the 64 bit version. */
3909 const int *hard_regno_mode_classes;
3911 static const int hard_32bit_mode_classes[] = {
3912 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3913 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3914 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3915 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3917 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3918 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3919 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3920 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3922 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3923 and none can hold SFmode/SImode values. */
3924 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3925 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3926 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3927 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3930 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3936 static const int hard_64bit_mode_classes[] = {
3937 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3938 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3939 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3940 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3942 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3943 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3944 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3945 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3947 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3948 and none can hold SFmode/SImode values. */
3949 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3950 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3951 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3952 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3955 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3961 int sparc_mode_class [NUM_MACHINE_MODES];
3963 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3966 sparc_init_modes (void)
3970 for (i = 0; i < NUM_MACHINE_MODES; i++)
3972 switch (GET_MODE_CLASS (i))
3975 case MODE_PARTIAL_INT:
3976 case MODE_COMPLEX_INT:
3977 if (GET_MODE_SIZE (i) <= 4)
3978 sparc_mode_class[i] = 1 << (int) S_MODE;
3979 else if (GET_MODE_SIZE (i) == 8)
3980 sparc_mode_class[i] = 1 << (int) D_MODE;
3981 else if (GET_MODE_SIZE (i) == 16)
3982 sparc_mode_class[i] = 1 << (int) T_MODE;
3983 else if (GET_MODE_SIZE (i) == 32)
3984 sparc_mode_class[i] = 1 << (int) O_MODE;
3986 sparc_mode_class[i] = 0;
3989 case MODE_COMPLEX_FLOAT:
3990 if (GET_MODE_SIZE (i) <= 4)
3991 sparc_mode_class[i] = 1 << (int) SF_MODE;
3992 else if (GET_MODE_SIZE (i) == 8)
3993 sparc_mode_class[i] = 1 << (int) DF_MODE;
3994 else if (GET_MODE_SIZE (i) == 16)
3995 sparc_mode_class[i] = 1 << (int) TF_MODE;
3996 else if (GET_MODE_SIZE (i) == 32)
3997 sparc_mode_class[i] = 1 << (int) OF_MODE;
3999 sparc_mode_class[i] = 0;
4002 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4003 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4005 sparc_mode_class[i] = 1 << (int) CC_MODE;
4008 sparc_mode_class[i] = 0;
4014 hard_regno_mode_classes = hard_64bit_mode_classes;
4016 hard_regno_mode_classes = hard_32bit_mode_classes;
4018 /* Initialize the array used by REGNO_REG_CLASS. */
4019 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4021 if (i < 16 && TARGET_V8PLUS)
4022 sparc_regno_reg_class[i] = I64_REGS;
4023 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4024 sparc_regno_reg_class[i] = GENERAL_REGS;
4026 sparc_regno_reg_class[i] = FP_REGS;
4028 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4030 sparc_regno_reg_class[i] = FPCC_REGS;
4032 sparc_regno_reg_class[i] = NO_REGS;
4036 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
4037 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4038 v9 int regs as it simplifies the code. */
4041 save_regs (FILE *file, int low, int high, const char *base,
4042 int offset, int n_regs, HOST_WIDE_INT real_offset)
4046 if (TARGET_ARCH64 && high <= 32)
4048 for (i = low; i < high; i++)
4050 if (regs_ever_live[i] && ! call_used_regs[i])
4052 fprintf (file, "\tstx\t%s, [%s+%d]\n",
4053 reg_names[i], base, offset + 4 * n_regs);
4054 if (dwarf2out_do_frame ())
4055 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4062 for (i = low; i < high; i += 2)
4064 if (regs_ever_live[i] && ! call_used_regs[i])
4066 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4068 fprintf (file, "\tstd\t%s, [%s+%d]\n",
4069 reg_names[i], base, offset + 4 * n_regs);
4070 if (dwarf2out_do_frame ())
4072 char *l = dwarf2out_cfi_label ();
4073 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
4074 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
4080 fprintf (file, "\tst\t%s, [%s+%d]\n",
4081 reg_names[i], base, offset + 4 * n_regs);
4082 if (dwarf2out_do_frame ())
4083 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4089 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4091 fprintf (file, "\tst\t%s, [%s+%d]\n",
4092 reg_names[i+1], base, offset + 4 * n_regs + 4);
4093 if (dwarf2out_do_frame ())
4094 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
4103 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
4105 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4106 v9 int regs as it simplifies the code. */
4109 restore_regs (FILE *file, int low, int high, const char *base,
4110 int offset, int n_regs)
4114 if (TARGET_ARCH64 && high <= 32)
4116 for (i = low; i < high; i++)
4118 if (regs_ever_live[i] && ! call_used_regs[i])
4119 fprintf (file, "\tldx\t[%s+%d], %s\n",
4120 base, offset + 4 * n_regs, reg_names[i]),
4126 for (i = low; i < high; i += 2)
4128 if (regs_ever_live[i] && ! call_used_regs[i])
4129 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4130 fprintf (file, "\tldd\t[%s+%d], %s\n",
4131 base, offset + 4 * n_regs, reg_names[i]),
4134 fprintf (file, "\tld\t[%s+%d], %s\n",
4135 base, offset + 4 * n_regs, reg_names[i]),
4137 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4138 fprintf (file, "\tld\t[%s+%d], %s\n",
4139 base, offset + 4 * n_regs + 4, reg_names[i+1]),
4146 /* Compute the frame size required by the function. This function is called
4147 during the reload pass and also by output_function_prologue(). */
4150 compute_frame_size (HOST_WIDE_INT size, int leaf_function)
4153 int outgoing_args_size = (current_function_outgoing_args_size
4154 + REG_PARM_STACK_SPACE (current_function_decl));
4156 /* N_REGS is the number of 4-byte regs saved thus far. This applies
4157 even to v9 int regs to be consistent with save_regs/restore_regs. */
4161 for (i = 0; i < 8; i++)
4162 if (regs_ever_live[i] && ! call_used_regs[i])
4167 for (i = 0; i < 8; i += 2)
4168 if ((regs_ever_live[i] && ! call_used_regs[i])
4169 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4173 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4174 if ((regs_ever_live[i] && ! call_used_regs[i])
4175 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4178 /* Set up values for use in `function_epilogue'. */
4179 num_gfregs = n_regs;
4181 if (leaf_function && n_regs == 0
4182 && size == 0 && current_function_outgoing_args_size == 0)
4184 actual_fsize = apparent_fsize = 0;
4188 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4189 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4190 apparent_fsize += n_regs * 4;
4191 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4194 /* Make sure nothing can clobber our register windows.
4195 If a SAVE must be done, or there is a stack-local variable,
4196 the register window area must be allocated.
4197 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4198 if (leaf_function == 0 || size > 0)
4199 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4201 return SPARC_STACK_ALIGN (actual_fsize);
4204 /* Build big number NUM in register REG and output the result to FILE.
4205 REG is guaranteed to be the only clobbered register. The function
4206 will very likely emit several instructions, so it must not be called
4207 from within a delay slot. */
4210 build_big_number (FILE *file, HOST_WIDE_INT num, const char *reg)
4212 #if HOST_BITS_PER_WIDE_INT == 64
4213 HOST_WIDE_INT high_bits = (num >> 32) & 0xffffffff;
4221 /* We don't use the 'set' macro because it appears to be broken
4222 in the Solaris 7 assembler. */
4223 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4225 if ((num & 0x3ff) != 0)
4226 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4229 #if HOST_BITS_PER_WIDE_INT == 64
4230 else if (high_bits == 0xffffffff) /* && TARGET_ARCH64 */
4232 else /* num < 0 && TARGET_ARCH64 */
4235 /* Sethi does not sign extend, so we must use a little trickery
4236 to use it for negative numbers. Invert the constant before
4237 loading it in, then use xor immediate to invert the loaded bits
4238 (along with the upper 32 bits) to the desired constant. This
4239 works because the sethi and immediate fields overlap. */
4240 HOST_WIDE_INT inv = ~num;
4241 HOST_WIDE_INT low = -0x400 + (num & 0x3ff);
4243 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4245 fprintf (file, "\txor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4248 #if HOST_BITS_PER_WIDE_INT == 64
4249 else /* TARGET_ARCH64 */
4251 /* We don't use the 'setx' macro because if requires a scratch register.
4252 This is the translation of sparc_emit_set_const64_longway into asm.
4253 Hopefully we will soon have prologue/epilogue emitted as RTL. */
4254 HOST_WIDE_INT low1 = (num >> (32 - 12)) & 0xfff;
4255 HOST_WIDE_INT low2 = (num >> (32 - 12 - 12)) & 0xfff;
4256 HOST_WIDE_INT low3 = (num >> (32 - 12 - 12 - 8)) & 0x0ff;
4259 /* We don't use the 'set' macro because it appears to be broken
4260 in the Solaris 7 assembler. */
4261 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4263 if ((high_bits & 0x3ff) != 0)
4264 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4265 reg, high_bits, reg);
4269 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4270 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4280 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4281 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4289 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4291 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4297 /* Output any necessary .register pseudo-ops. */
4299 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4301 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4307 /* Check if %g[2367] were used without
4308 .register being printed for them already. */
4309 for (i = 2; i < 8; i++)
4311 if (regs_ever_live [i]
4312 && ! sparc_hard_reg_printed [i])
4314 sparc_hard_reg_printed [i] = 1;
4315 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4322 /* This function generates the assembly code for function entry.
4323 FILE is a stdio stream to output the code to.
4324 SIZE is an int: how many units of temporary storage to allocate.
4325 Refer to the array `regs_ever_live' to determine which registers
4326 to save; `regs_ever_live[I]' is nonzero if register number I
4327 is ever used in the function. This macro is responsible for
4328 knowing which registers should not be saved even if used. */
4330 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
4331 of memory. If any fpu reg is used in the function, we allocate
4332 such a block here, at the bottom of the frame, just in case it's needed.
4334 If this function is a leaf procedure, then we may choose not
4335 to do a "save" insn. The decision about whether or not
4336 to do this is made in regclass.c. */
4339 sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size)
4341 sparc_function_prologue (file, size,
4342 current_function_uses_only_leaf_regs);
4345 /* Output code for the function prologue. */
4348 sparc_function_prologue (FILE *file, HOST_WIDE_INT size, int leaf_function)
4350 sparc_output_scratch_registers (file);
4352 /* Need to use actual_fsize, since we are also allocating
4353 space for our callee (and our own register save area). */
4354 actual_fsize = compute_frame_size (size, leaf_function);
4358 frame_base_name = "%sp";
4359 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4363 frame_base_name = "%fp";
4364 frame_base_offset = SPARC_STACK_BIAS;
4367 /* This is only for the human reader. */
4368 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
4370 if (actual_fsize == 0)
4372 else if (! leaf_function)
4374 if (actual_fsize <= 4096)
4375 fprintf (file, "\tsave\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4377 else if (actual_fsize <= 8192)
4379 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
4380 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4381 actual_fsize - 4096);
4385 build_big_number (file, -actual_fsize, "%g1");
4386 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
4389 else /* leaf function */
4391 if (actual_fsize <= 4096)
4392 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4394 else if (actual_fsize <= 8192)
4396 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
4397 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4398 actual_fsize - 4096);
4402 build_big_number (file, -actual_fsize, "%g1");
4403 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
4407 if (dwarf2out_do_frame () && actual_fsize)
4409 char *label = dwarf2out_cfi_label ();
4411 /* The canonical frame address refers to the top of the frame. */
4412 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
4413 : HARD_FRAME_POINTER_REGNUM),
4416 if (! leaf_function)
4418 /* Note the register window save. This tells the unwinder that
4419 it needs to restore the window registers from the previous
4420 frame's window save area at 0(cfa). */
4421 dwarf2out_window_save (label);
4423 /* The return address (-8) is now in %i7. */
4424 dwarf2out_return_reg (label, 31);
4428 /* If doing anything with PIC, do it now. */
4430 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
4432 /* Call saved registers are saved just above the outgoing argument area. */
4435 HOST_WIDE_INT offset, real_offset;
4439 real_offset = -apparent_fsize;
4440 offset = -apparent_fsize + frame_base_offset;
4441 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4443 /* ??? This might be optimized a little as %g1 might already have a
4444 value close enough that a single add insn will do. */
4445 /* ??? Although, all of this is probably only a temporary fix
4446 because if %g1 can hold a function result, then
4447 output_function_epilogue will lose (the result will get
4449 build_big_number (file, offset, "%g1");
4450 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4456 base = frame_base_name;
4459 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
4460 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
4465 /* Output code to restore any call saved registers. */
4468 output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED)
4470 HOST_WIDE_INT offset;
4474 offset = -apparent_fsize + frame_base_offset;
4475 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4477 build_big_number (file, offset, "%g1");
4478 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4484 base = frame_base_name;
4487 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4488 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4491 /* This function generates the assembly code for function exit,
4492 on machines that need it.
4494 The function epilogue should not depend on the current stack pointer!
4495 It should use the frame pointer only. This is mandatory because
4496 of alloca; we also take advantage of it to omit stack adjustments
4497 before returning. */
4500 sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size)
4502 sparc_function_epilogue (file, size,
4503 current_function_uses_only_leaf_regs);
4506 /* Output code for the function epilogue. */
4509 sparc_function_epilogue (FILE *file,
4510 HOST_WIDE_INT size ATTRIBUTE_UNUSED,
4515 /* True if the caller has placed an "unimp" insn immediately after the call.
4516 This insn is used in the 32-bit ABI when calling a function that returns
4517 a non zero-sized structure. The 64-bit ABI doesn't have it. Be careful
4518 to have this test be the same as that used on the call. */
4519 sparc_skip_caller_unimp
4521 && current_function_returns_struct
4522 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
4524 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl)));
4526 if (current_function_epilogue_delay_list == 0)
4528 /* If code does not drop into the epilogue, we need
4529 do nothing except output pending case vectors.
4531 We have to still output a dummy nop for the sake of
4532 sane backtraces. Otherwise, if the last two instructions
4533 of a function were call foo; dslot; this can make the return
4534 PC of foo (ie. address of call instruction plus 8) point to
4535 the first instruction in the next function. */
4536 rtx insn, last_real_insn;
4538 insn = get_last_insn ();
4540 last_real_insn = prev_real_insn (insn);
4542 && GET_CODE (last_real_insn) == INSN
4543 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4544 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4546 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4547 fputs("\tnop\n", file);
4549 if (GET_CODE (insn) == NOTE)
4550 insn = prev_nonnote_insn (insn);
4551 if (insn && GET_CODE (insn) == BARRIER)
4552 goto output_vectors;
4556 output_restore_regs (file, leaf_function);
4558 /* Work out how to skip the caller's unimp instruction if required. */
4560 ret = (sparc_skip_caller_unimp ? "jmp\t%o7+12" : "retl");
4562 ret = (sparc_skip_caller_unimp ? "jmp\t%i7+12" : "ret");
4564 if (! leaf_function)
4566 if (current_function_calls_eh_return)
4568 if (current_function_epilogue_delay_list)
4570 if (sparc_skip_caller_unimp)
4573 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4575 /* If we wound up with things in our delay slot, flush them here. */
4576 else if (current_function_epilogue_delay_list)
4578 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4580 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4582 epilogue_renumber (&delay, 0);
4583 fputs (sparc_skip_caller_unimp
4584 ? "\treturn\t%i7+12\n"
4585 : "\treturn\t%i7+8\n", file);
4586 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4587 file, 1, 0, 0, NULL);
4593 if (GET_CODE (delay) != SET)
4596 src = SET_SRC (delay);
4597 if (GET_CODE (src) == ASHIFT)
4599 if (XEXP (src, 1) != const1_rtx)
4602 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4606 insn = gen_rtx_PARALLEL (VOIDmode,
4607 gen_rtvec (2, delay,
4608 gen_rtx_RETURN (VOIDmode)));
4609 insn = emit_jump_insn (insn);
4611 sparc_emitting_epilogue = true;
4612 final_scan_insn (insn, file, 1, 0, 1, NULL);
4613 sparc_emitting_epilogue = false;
4616 else if (TARGET_V9 && ! sparc_skip_caller_unimp)
4617 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4619 fprintf (file, "\t%s\n\trestore\n", ret);
4621 /* All of the following cases are for leaf functions. */
4622 else if (current_function_calls_eh_return)
4624 else if (current_function_epilogue_delay_list)
4626 /* eligible_for_epilogue_delay_slot ensures that if this is a
4627 leaf function, then we will only have insn in the delay slot
4628 if the frame size is zero, thus no adjust for the stack is
4630 if (actual_fsize != 0)
4632 fprintf (file, "\t%s\n", ret);
4633 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4634 file, 1, 0, 1, NULL);
4636 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4637 avoid generating confusing assembly language output. */
4638 else if (actual_fsize == 0)
4639 fprintf (file, "\t%s\n\tnop\n", ret);
4640 else if (actual_fsize <= 4096)
4641 fprintf (file, "\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4643 else if (actual_fsize <= 8192)
4644 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4645 ret, actual_fsize - 4096);
4648 build_big_number (file, actual_fsize, "%g1");
4649 fprintf (file, "\t%s\n\tadd\t%%sp, %%g1, %%sp\n", ret);
4653 sparc_output_deferred_case_vectors ();
4656 /* Output a sibling call. */
4659 output_sibcall (rtx insn, rtx call_operand)
4661 int leaf_regs = current_function_uses_only_leaf_regs;
4663 int delay_slot = dbr_sequence_length () > 0;
4667 /* Call to restore global regs might clobber
4668 the delay slot. Instead of checking for this
4669 output the delay slot now. */
4672 rtx delay = NEXT_INSN (insn);
4677 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4678 PATTERN (delay) = gen_blockage ();
4679 INSN_CODE (delay) = -1;
4682 output_restore_regs (asm_out_file, leaf_regs);
4685 operands[0] = call_operand;
4689 #ifdef HAVE_AS_RELAX_OPTION
4690 /* If as and ld are relaxing tail call insns into branch always,
4691 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4692 be optimized. With sethi/jmpl as nor ld has no easy way how to
4693 find out if somebody does not branch between the sethi and jmpl. */
4696 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4698 HOST_WIDE_INT size = 0;
4700 if ((actual_fsize || ! spare_slot) && delay_slot)
4702 rtx delay = NEXT_INSN (insn);
4707 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4708 PATTERN (delay) = gen_blockage ();
4709 INSN_CODE (delay) = -1;
4714 if (actual_fsize <= 4096)
4715 size = actual_fsize;
4716 else if (actual_fsize <= 8192)
4718 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4719 size = actual_fsize - 4096;
4723 build_big_number (asm_out_file, actual_fsize, "%g1");
4724 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4729 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4730 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4732 fprintf (asm_out_file, "\t sub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size);
4733 else if (! delay_slot)
4734 fputs ("\t nop\n", asm_out_file);
4739 fprintf (asm_out_file, "\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size);
4740 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4741 it into branch if possible. */
4742 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4743 output_asm_insn ("call\t%a0, 0", operands);
4744 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4749 output_asm_insn ("call\t%a0, 0", operands);
4752 rtx delay = NEXT_INSN (insn), pat;
4757 pat = PATTERN (delay);
4758 if (GET_CODE (pat) != SET)
4761 operands[0] = SET_DEST (pat);
4762 pat = SET_SRC (pat);
4763 switch (GET_CODE (pat))
4766 operands[1] = XEXP (pat, 0);
4767 operands[2] = XEXP (pat, 1);
4768 output_asm_insn (" restore %r1, %2, %Y0", operands);
4771 operands[1] = XEXP (pat, 0);
4772 operands[2] = XEXP (pat, 1);
4773 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4776 operands[1] = XEXP (pat, 0);
4777 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4781 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4784 PATTERN (delay) = gen_blockage ();
4785 INSN_CODE (delay) = -1;
4788 fputs ("\t restore\n", asm_out_file);
4792 /* Functions for handling argument passing.
4794 For 32-bit, the first 6 args are normally in registers and the rest are
4795 pushed. Any arg that starts within the first 6 words is at least
4796 partially passed in a register unless its data type forbids.
4798 For 64-bit, the argument registers are laid out as an array of 16 elements
4799 and arguments are added sequentially. The first 6 int args and up to the
4800 first 16 fp args (depending on size) are passed in regs.
4802 Slot Stack Integral Float Float in structure Double Long Double
4803 ---- ----- -------- ----- ------------------ ------ -----------
4804 15 [SP+248] %f31 %f30,%f31 %d30
4805 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4806 13 [SP+232] %f27 %f26,%f27 %d26
4807 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4808 11 [SP+216] %f23 %f22,%f23 %d22
4809 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4810 9 [SP+200] %f19 %f18,%f19 %d18
4811 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4812 7 [SP+184] %f15 %f14,%f15 %d14
4813 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4814 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4815 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4816 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4817 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4818 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4819 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4821 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4823 Integral arguments are always passed as 64-bit quantities appropriately
4826 Passing of floating point values is handled as follows.
4827 If a prototype is in scope:
4828 If the value is in a named argument (i.e. not a stdarg function or a
4829 value not part of the `...') then the value is passed in the appropriate
4831 If the value is part of the `...' and is passed in one of the first 6
4832 slots then the value is passed in the appropriate int reg.
4833 If the value is part of the `...' and is not passed in one of the first 6
4834 slots then the value is passed in memory.
4835 If a prototype is not in scope:
4836 If the value is one of the first 6 arguments the value is passed in the
4837 appropriate integer reg and the appropriate fp reg.
4838 If the value is not one of the first 6 arguments the value is passed in
4839 the appropriate fp reg and in memory.
4842 Summary of the calling conventions implemented by GCC on SPARC:
4845 size argument return value
4847 small integer <4 int. reg. int. reg.
4848 word 4 int. reg. int. reg.
4849 double word 8 int. reg. int. reg.
4851 _Complex small integer <8 int. reg. int. reg.
4852 _Complex word 8 int. reg. int. reg.
4853 _Complex double word 16 memory int. reg.
4855 vector integer <=8 int. reg. FP reg.
4856 vector integer >8 memory memory
4858 float 4 int. reg. FP reg.
4859 double 8 int. reg. FP reg.
4860 long double 16 memory memory
4862 _Complex float 8 memory FP reg.
4863 _Complex double 16 memory FP reg.
4864 _Complex long double 32 memory FP reg.
4866 vector float <=32 memory FP reg.
4867 vector float >32 memory memory
4869 aggregate any memory memory
4874 size argument return value
4876 small integer <8 int. reg. int. reg.
4877 word 8 int. reg. int. reg.
4878 double word 16 int. reg. int. reg.
4880 _Complex small integer <16 int. reg. int. reg.
4881 _Complex word 16 int. reg. int. reg.
4882 _Complex double word 32 memory int. reg.
4884 vector integer <=16 FP reg. FP reg.
4885 vector integer 16<s<=32 memory FP reg.
4886 vector integer >32 memory memory
4888 float 4 FP reg. FP reg.
4889 double 8 FP reg. FP reg.
4890 long double 16 FP reg. FP reg.
4892 _Complex float 8 FP reg. FP reg.
4893 _Complex double 16 FP reg. FP reg.
4894 _Complex long double 32 memory FP reg.
4896 vector float <=16 FP reg. FP reg.
4897 vector float 16<s<=32 memory FP reg.
4898 vector float >32 memory memory
4900 aggregate <=16 reg. reg.
4901 aggregate 16<s<=32 memory reg.
4902 aggregate >32 memory memory
4906 Note #1: complex floating-point types follow the extended SPARC ABIs as
4907 implemented by the Sun compiler.
4909 Note #2: integral vector types follow the scalar floating-point types
4910 conventions to match what is implemented by the Sun VIS SDK.
4912 Note #3: floating-point vector types follow the complex floating-point
4913 types conventions. */
4916 /* Maximum number of int regs for args. */
4917 #define SPARC_INT_ARG_MAX 6
4918 /* Maximum number of fp regs for args. */
4919 #define SPARC_FP_ARG_MAX 16
4921 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4923 /* Handle the INIT_CUMULATIVE_ARGS macro.
4924 Initialize a variable CUM of type CUMULATIVE_ARGS
4925 for a call to a function whose data type is FNTYPE.
4926 For a library call, FNTYPE is 0. */
4929 init_cumulative_args (struct sparc_args *cum, tree fntype,
4930 rtx libname ATTRIBUTE_UNUSED,
4931 tree fndecl ATTRIBUTE_UNUSED)
4934 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4935 cum->libcall_p = fntype == 0;
4938 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
4939 When a prototype says `char' or `short', really pass an `int'. */
4942 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
4944 return TARGET_ARCH32 ? true : false;
4947 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
4950 sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4952 return TARGET_ARCH64 ? true : false;
4955 /* Scan the record type TYPE and return the following predicates:
4956 - INTREGS_P: the record contains at least one field or sub-field
4957 that is eligible for promotion in integer registers.
4958 - FP_REGS_P: the record contains at least one field or sub-field
4959 that is eligible for promotion in floating-point registers.
4960 - PACKED_P: the record contains at least one field that is packed.
4962 Sub-fields are not taken into account for the PACKED_P predicate. */
4965 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
4969 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4971 if (TREE_CODE (field) == FIELD_DECL)
4973 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4974 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
4975 else if (FLOAT_TYPE_P (TREE_TYPE (field)) && TARGET_FPU)
4980 if (packed_p && DECL_PACKED (field))
4986 /* Compute the slot number to pass an argument in.
4987 Return the slot number or -1 if passing on the stack.
4989 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4990 the preceding args and about the function being called.
4991 MODE is the argument's machine mode.
4992 TYPE is the data type of the argument (as a tree).
4993 This is null for libcalls where that information may
4995 NAMED is nonzero if this argument is a named parameter
4996 (otherwise it is an extra parameter matching an ellipsis).
4997 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4998 *PREGNO records the register number to use if scalar type.
4999 *PPADDING records the amount of padding needed in words. */
5002 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
5003 tree type, int named, int incoming_p,
5004 int *pregno, int *ppadding)
5006 int regbase = (incoming_p
5007 ? SPARC_INCOMING_INT_ARG_FIRST
5008 : SPARC_OUTGOING_INT_ARG_FIRST);
5009 int slotno = cum->words;
5014 if (type && TREE_ADDRESSABLE (type))
5020 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5023 /* For SPARC64, objects requiring 16-byte alignment get it. */
5025 && GET_MODE_ALIGNMENT (mode) >= 2 * BITS_PER_WORD
5026 && (slotno & 1) != 0)
5027 slotno++, *ppadding = 1;
5029 switch (GET_MODE_CLASS (mode))
5032 case MODE_COMPLEX_FLOAT:
5033 case MODE_VECTOR_INT:
5034 case MODE_VECTOR_FLOAT:
5035 if (TARGET_ARCH64 && TARGET_FPU && named)
5037 if (slotno >= SPARC_FP_ARG_MAX)
5039 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5040 /* Arguments filling only one single FP register are
5041 right-justified in the outer double FP register. */
5042 if (GET_MODE_SIZE (mode) <= 4)
5049 case MODE_COMPLEX_INT:
5050 if (slotno >= SPARC_INT_ARG_MAX)
5052 regno = regbase + slotno;
5056 if (mode == VOIDmode)
5057 /* MODE is VOIDmode when generating the actual call. */
5060 if (mode != BLKmode)
5063 /* For SPARC64, objects requiring 16-byte alignment get it. */
5066 && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5067 && (slotno & 1) != 0)
5068 slotno++, *ppadding = 1;
5070 if (TARGET_ARCH32 || (type && TREE_CODE (type) == UNION_TYPE))
5072 if (slotno >= SPARC_INT_ARG_MAX)
5074 regno = regbase + slotno;
5076 else /* TARGET_ARCH64 && type && TREE_CODE (type) == RECORD_TYPE */
5078 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5080 /* First see what kinds of registers we would need. */
5081 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5083 /* The ABI obviously doesn't specify how packed structures
5084 are passed. These are defined to be passed in int regs
5085 if possible, otherwise memory. */
5086 if (packed_p || !named)
5087 fpregs_p = 0, intregs_p = 1;
5089 /* If all arg slots are filled, then must pass on stack. */
5090 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5093 /* If there are only int args and all int arg slots are filled,
5094 then must pass on stack. */
5095 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5098 /* Note that even if all int arg slots are filled, fp members may
5099 still be passed in regs if such regs are available.
5100 *PREGNO isn't set because there may be more than one, it's up
5101 to the caller to compute them. */
5114 /* Handle recursive register counting for structure field layout. */
5116 struct function_arg_record_value_parms
5118 rtx ret; /* return expression being built. */
5119 int slotno; /* slot number of the argument. */
5120 int named; /* whether the argument is named. */
5121 int regbase; /* regno of the base register. */
5122 int stack; /* 1 if part of the argument is on the stack. */
5123 int intoffset; /* offset of the first pending integer field. */
5124 unsigned int nregs; /* number of words passed in registers. */
5127 static void function_arg_record_value_3
5128 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5129 static void function_arg_record_value_2
5130 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5131 static void function_arg_record_value_1
5132 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5133 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
5134 static rtx function_arg_union_value (int, enum machine_mode, int);
5136 /* A subroutine of function_arg_record_value. Traverse the structure
5137 recursively and determine how many registers will be required. */
5140 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
5141 struct function_arg_record_value_parms *parms,
5146 /* We need to compute how many registers are needed so we can
5147 allocate the PARALLEL but before we can do that we need to know
5148 whether there are any packed fields. The ABI obviously doesn't
5149 specify how structures are passed in this case, so they are
5150 defined to be passed in int regs if possible, otherwise memory,
5151 regardless of whether there are fp values present. */
5154 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5156 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5163 /* Compute how many registers we need. */
5164 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5166 if (TREE_CODE (field) == FIELD_DECL)
5168 HOST_WIDE_INT bitpos = startbitpos;
5170 if (DECL_SIZE (field) != 0
5171 && host_integerp (bit_position (field), 1))
5172 bitpos += int_bit_position (field);
5174 /* ??? FIXME: else assume zero offset. */
5176 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5177 function_arg_record_value_1 (TREE_TYPE (field),
5181 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5182 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5187 if (parms->intoffset != -1)
5189 unsigned int startbit, endbit;
5190 int intslots, this_slotno;
5192 startbit = parms->intoffset & -BITS_PER_WORD;
5193 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5195 intslots = (endbit - startbit) / BITS_PER_WORD;
5196 this_slotno = parms->slotno + parms->intoffset
5199 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5201 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5202 /* We need to pass this field on the stack. */
5206 parms->nregs += intslots;
5207 parms->intoffset = -1;
5210 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5211 If it wasn't true we wouldn't be here. */
5213 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5218 if (parms->intoffset == -1)
5219 parms->intoffset = bitpos;
5225 /* A subroutine of function_arg_record_value. Assign the bits of the
5226 structure between parms->intoffset and bitpos to integer registers. */
5229 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5230 struct function_arg_record_value_parms *parms)
5232 enum machine_mode mode;
5234 unsigned int startbit, endbit;
5235 int this_slotno, intslots, intoffset;
5238 if (parms->intoffset == -1)
5241 intoffset = parms->intoffset;
5242 parms->intoffset = -1;
5244 startbit = intoffset & -BITS_PER_WORD;
5245 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5246 intslots = (endbit - startbit) / BITS_PER_WORD;
5247 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5249 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5253 /* If this is the trailing part of a word, only load that much into
5254 the register. Otherwise load the whole register. Note that in
5255 the latter case we may pick up unwanted bits. It's not a problem
5256 at the moment but may wish to revisit. */
5258 if (intoffset % BITS_PER_WORD != 0)
5259 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5264 intoffset /= BITS_PER_UNIT;
5267 regno = parms->regbase + this_slotno;
5268 reg = gen_rtx_REG (mode, regno);
5269 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5270 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5273 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5278 while (intslots > 0);
5281 /* A subroutine of function_arg_record_value. Traverse the structure
5282 recursively and assign bits to floating point registers. Track which
5283 bits in between need integer registers; invoke function_arg_record_value_3
5284 to make that happen. */
5287 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5288 struct function_arg_record_value_parms *parms,
5294 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5296 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5303 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5305 if (TREE_CODE (field) == FIELD_DECL)
5307 HOST_WIDE_INT bitpos = startbitpos;
5309 if (DECL_SIZE (field) != 0
5310 && host_integerp (bit_position (field), 1))
5311 bitpos += int_bit_position (field);
5313 /* ??? FIXME: else assume zero offset. */
5315 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5316 function_arg_record_value_2 (TREE_TYPE (field),
5320 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5321 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5326 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5328 enum machine_mode mode = DECL_MODE (field);
5331 function_arg_record_value_3 (bitpos, parms);
5334 case SCmode: mode = SFmode; break;
5335 case DCmode: mode = DFmode; break;
5336 case TCmode: mode = TFmode; break;
5339 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
5340 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
5342 reg = gen_rtx_REG (mode, regno);
5343 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5344 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5345 GEN_INT (bitpos / BITS_PER_UNIT));
5347 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5349 regno += GET_MODE_SIZE (mode) / 4;
5350 reg = gen_rtx_REG (mode, regno);
5351 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5352 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5353 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5360 if (parms->intoffset == -1)
5361 parms->intoffset = bitpos;
5367 /* Used by function_arg and function_value to implement the complex
5368 conventions of the 64-bit ABI for passing and returning structures.
5369 Return an expression valid as a return value for the two macros
5370 FUNCTION_ARG and FUNCTION_VALUE.
5372 TYPE is the data type of the argument (as a tree).
5373 This is null for libcalls where that information may
5375 MODE is the argument's machine mode.
5376 SLOTNO is the index number of the argument's slot in the parameter array.
5377 NAMED is nonzero if this argument is a named parameter
5378 (otherwise it is an extra parameter matching an ellipsis).
5379 REGBASE is the regno of the base register for the parameter array. */
5382 function_arg_record_value (tree type, enum machine_mode mode,
5383 int slotno, int named, int regbase)
5385 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5386 struct function_arg_record_value_parms parms;
5389 parms.ret = NULL_RTX;
5390 parms.slotno = slotno;
5391 parms.named = named;
5392 parms.regbase = regbase;
5395 /* Compute how many registers we need. */
5397 parms.intoffset = 0;
5398 function_arg_record_value_1 (type, 0, &parms, false);
5400 /* Take into account pending integer fields. */
5401 if (parms.intoffset != -1)
5403 unsigned int startbit, endbit;
5404 int intslots, this_slotno;
5406 startbit = parms.intoffset & -BITS_PER_WORD;
5407 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5408 intslots = (endbit - startbit) / BITS_PER_WORD;
5409 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5411 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5413 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5414 /* We need to pass this field on the stack. */
5418 parms.nregs += intslots;
5420 nregs = parms.nregs;
5422 /* Allocate the vector and handle some annoying special cases. */
5425 /* ??? Empty structure has no value? Duh? */
5428 /* Though there's nothing really to store, return a word register
5429 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5430 leads to breakage due to the fact that there are zero bytes to
5432 return gen_rtx_REG (mode, regbase);
5436 /* ??? C++ has structures with no fields, and yet a size. Give up
5437 for now and pass everything back in integer registers. */
5438 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5440 if (nregs + slotno > SPARC_INT_ARG_MAX)
5441 nregs = SPARC_INT_ARG_MAX - slotno;
5446 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5448 /* If at least one field must be passed on the stack, generate
5449 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5450 also be passed on the stack. We can't do much better because the
5451 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5452 of structures for which the fields passed exclusively in registers
5453 are not at the beginning of the structure. */
5455 XVECEXP (parms.ret, 0, 0)
5456 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5458 /* Fill in the entries. */
5460 parms.intoffset = 0;
5461 function_arg_record_value_2 (type, 0, &parms, false);
5462 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5464 if (parms.nregs != nregs)
5470 /* Used by function_arg and function_value to implement the conventions
5471 of the 64-bit ABI for passing and returning unions.
5472 Return an expression valid as a return value for the two macros
5473 FUNCTION_ARG and FUNCTION_VALUE.
5475 SIZE is the size in bytes of the union.
5476 MODE is the argument's machine mode.
5477 REGNO is the hard register the union will be passed in. */
5480 function_arg_union_value (int size, enum machine_mode mode, int regno)
5482 int nwords = ROUND_ADVANCE (size), i;
5485 /* Unions are passed left-justified. */
5486 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
5488 for (i = 0; i < nwords; i++)
5489 XVECEXP (regs, 0, i)
5490 = gen_rtx_EXPR_LIST (VOIDmode,
5491 gen_rtx_REG (word_mode, regno + i),
5492 GEN_INT (UNITS_PER_WORD * i));
5497 /* Handle the FUNCTION_ARG macro.
5498 Determine where to put an argument to a function.
5499 Value is zero to push the argument on the stack,
5500 or a hard register in which to store the argument.
5502 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5503 the preceding args and about the function being called.
5504 MODE is the argument's machine mode.
5505 TYPE is the data type of the argument (as a tree).
5506 This is null for libcalls where that information may
5508 NAMED is nonzero if this argument is a named parameter
5509 (otherwise it is an extra parameter matching an ellipsis).
5510 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5513 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5514 tree type, int named, int incoming_p)
5516 int regbase = (incoming_p
5517 ? SPARC_INCOMING_INT_ARG_FIRST
5518 : SPARC_OUTGOING_INT_ARG_FIRST);
5519 int slotno, regno, padding;
5522 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5530 reg = gen_rtx_REG (mode, regno);
5534 if (type && TREE_CODE (type) == RECORD_TYPE)
5536 /* Structures up to 16 bytes in size are passed in arg slots on the
5537 stack and are promoted to registers where possible. */
5539 if (int_size_in_bytes (type) > 16)
5540 abort (); /* shouldn't get here */
5542 return function_arg_record_value (type, mode, slotno, named, regbase);
5544 else if (type && TREE_CODE (type) == UNION_TYPE)
5546 HOST_WIDE_INT size = int_size_in_bytes (type);
5549 abort (); /* shouldn't get here */
5551 return function_arg_union_value (size, mode, regno);
5553 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5554 but also have the slot allocated for them.
5555 If no prototype is in scope fp values in register slots get passed
5556 in two places, either fp regs and int regs or fp regs and memory. */
5557 else if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5558 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5559 || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
5560 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
5561 && SPARC_FP_REG_P (regno))
5563 reg = gen_rtx_REG (mode, regno);
5564 if (cum->prototype_p || cum->libcall_p)
5566 /* "* 2" because fp reg numbers are recorded in 4 byte
5569 /* ??? This will cause the value to be passed in the fp reg and
5570 in the stack. When a prototype exists we want to pass the
5571 value in the reg but reserve space on the stack. That's an
5572 optimization, and is deferred [for a bit]. */
5573 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5574 return gen_rtx_PARALLEL (mode,
5576 gen_rtx_EXPR_LIST (VOIDmode,
5577 NULL_RTX, const0_rtx),
5578 gen_rtx_EXPR_LIST (VOIDmode,
5582 /* ??? It seems that passing back a register even when past
5583 the area declared by REG_PARM_STACK_SPACE will allocate
5584 space appropriately, and will not copy the data onto the
5585 stack, exactly as we desire.
5587 This is due to locate_and_pad_parm being called in
5588 expand_call whenever reg_parm_stack_space > 0, which
5589 while beneficial to our example here, would seem to be
5590 in error from what had been intended. Ho hum... -- r~ */
5598 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5602 /* On incoming, we don't need to know that the value
5603 is passed in %f0 and %i0, and it confuses other parts
5604 causing needless spillage even on the simplest cases. */
5608 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5609 + (regno - SPARC_FP_ARG_FIRST) / 2);
5611 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5612 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5614 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5618 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5619 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5620 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5626 /* Scalar or complex int. */
5627 reg = gen_rtx_REG (mode, regno);
5633 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5634 For an arg passed partly in registers and partly in memory,
5635 this is the number of registers used.
5636 For args passed entirely in registers or entirely in memory, zero.
5638 Any arg that starts in the first 6 regs but won't entirely fit in them
5639 needs partial registers on v8. On v9, structures with integer
5640 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5641 values that begin in the last fp reg [where "last fp reg" varies with the
5642 mode] will be split between that reg and memory. */
5645 function_arg_partial_nregs (const struct sparc_args *cum,
5646 enum machine_mode mode, tree type, int named)
5648 int slotno, regno, padding;
5650 /* We pass 0 for incoming_p here, it doesn't matter. */
5651 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5658 if ((slotno + (mode == BLKmode
5659 ? ROUND_ADVANCE (int_size_in_bytes (type))
5660 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5661 > SPARC_INT_ARG_MAX)
5662 return SPARC_INT_ARG_MAX - slotno;
5666 /* We are guaranteed by function_arg_pass_by_reference that the size
5667 of the argument is not greater than 16 bytes, so we only need to
5668 return 1 if the argument is partially passed in registers. */
5670 if (type && AGGREGATE_TYPE_P (type))
5672 int size = int_size_in_bytes (type);
5674 if (size > UNITS_PER_WORD
5675 && slotno == SPARC_INT_ARG_MAX - 1)
5678 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5679 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5680 && ! (TARGET_FPU && named)))
5682 /* The complex types are passed as packed types. */
5683 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5684 && slotno == SPARC_INT_ARG_MAX - 1)
5687 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5689 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5698 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5699 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5700 quad-precision floats by invisible reference.
5701 v9: Aggregates greater than 16 bytes are passed by reference.
5702 For Pascal, also pass arrays by reference. */
5705 function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
5706 enum machine_mode mode, tree type,
5707 int named ATTRIBUTE_UNUSED)
5711 return ((type && AGGREGATE_TYPE_P (type))
5712 /* Extended ABI (as implemented by the Sun compiler) says
5713 that all complex floats are passed in memory. */
5715 /* Enforce the 2-word cap for passing arguments in registers.
5716 This affects CDImode, TFmode, DCmode, TCmode and large
5718 || GET_MODE_SIZE (mode) > 8);
5722 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5724 && AGGREGATE_TYPE_P (type)
5725 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
5726 /* Enforce the 2-word cap for passing arguments in registers.
5727 This affects CTImode, TCmode and large vector modes. */
5728 || GET_MODE_SIZE (mode) > 16);
5732 /* Handle the FUNCTION_ARG_ADVANCE macro.
5733 Update the data in CUM to advance over an argument
5734 of mode MODE and data type TYPE.
5735 TYPE is null for libcalls where that information may not be available. */
5738 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5739 tree type, int named)
5741 int slotno, regno, padding;
5743 /* We pass 0 for incoming_p here, it doesn't matter. */
5744 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5746 /* If register required leading padding, add it. */
5748 cum->words += padding;
5752 cum->words += (mode != BLKmode
5753 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5754 : ROUND_ADVANCE (int_size_in_bytes (type)));
5758 if (type && AGGREGATE_TYPE_P (type))
5760 int size = int_size_in_bytes (type);
5764 else if (size <= 16)
5766 else /* passed by reference */
5771 cum->words += (mode != BLKmode
5772 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5773 : ROUND_ADVANCE (int_size_in_bytes (type)));
5778 /* Handle the FUNCTION_ARG_PADDING macro.
5779 For the 64 bit ABI structs are always stored left shifted in their
5783 function_arg_padding (enum machine_mode mode, tree type)
5785 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5788 /* Fall back to the default. */
5789 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5792 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
5793 Specify whether to return the return value in memory. */
5796 sparc_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
5799 /* Original SPARC 32-bit ABI says that quad-precision floats
5800 and all structures are returned in memory. Extended ABI
5801 (as implemented by the Sun compiler) says that all complex
5802 floats are returned in registers (8 FP registers at most
5803 for '_Complex long double'). Return all complex integers
5804 in registers (4 at most for '_Complex long long'). */
5805 return (TYPE_MODE (type) == BLKmode
5806 || TYPE_MODE (type) == TFmode
5807 /* Integral vector types follow the scalar FP types conventions. */
5808 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_INT
5809 && GET_MODE_SIZE (TYPE_MODE (type)) > 8)
5810 /* FP vector types follow the complex FP types conventions. */
5811 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_FLOAT
5812 && GET_MODE_SIZE (TYPE_MODE (type)) > 32));
5814 /* Original SPARC 64-bit ABI says that structures and unions
5815 smaller than 32 bytes are returned in registers. Extended
5816 ABI (as implemented by the Sun compiler) says that all complex
5817 floats are returned in registers (8 FP registers at most
5818 for '_Complex long double'). Return all complex integers
5819 in registers (4 at most for '_Complex TItype'). */
5820 return ((TYPE_MODE (type) == BLKmode
5821 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32)
5822 || GET_MODE_SIZE (TYPE_MODE (type)) > 32);
5825 /* Handle the TARGET_STRUCT_VALUE target hook.
5826 Return where to find the structure return value address. */
5829 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED, int incoming)
5836 return gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx,
5837 STRUCT_VALUE_OFFSET));
5839 return gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx,
5840 STRUCT_VALUE_OFFSET));
5844 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5845 For v9, function return values are subject to the same rules as arguments,
5846 except that up to 32 bytes may be returned in registers. */
5849 function_value (tree type, enum machine_mode mode, int incoming_p)
5851 /* Beware that the two values are swapped here wrt function_arg. */
5852 int regbase = (incoming_p
5853 ? SPARC_OUTGOING_INT_ARG_FIRST
5854 : SPARC_INCOMING_INT_ARG_FIRST);
5857 if (TARGET_ARCH64 && type)
5859 if (TREE_CODE (type) == RECORD_TYPE)
5861 /* Structures up to 32 bytes in size are passed in registers,
5862 promoted to fp registers where possible. */
5864 if (int_size_in_bytes (type) > 32)
5865 abort (); /* shouldn't get here */
5867 return function_arg_record_value (type, mode, 0, 1, regbase);
5869 else if (TREE_CODE (type) == UNION_TYPE)
5871 HOST_WIDE_INT size = int_size_in_bytes (type);
5874 abort (); /* shouldn't get here */
5876 return function_arg_union_value (size, mode, regbase);
5878 else if (AGGREGATE_TYPE_P (type))
5880 /* All other aggregate types are passed in an integer register
5881 in a mode corresponding to the size of the type. */
5882 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5885 abort (); /* shouldn't get here */
5887 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5889 else if (GET_MODE_CLASS (mode) == MODE_INT
5890 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5894 if (TARGET_FPU && (FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)))
5895 regno = SPARC_FP_ARG_FIRST;
5899 return gen_rtx_REG (mode, regno);
5902 /* Do what is necessary for `va_start'. We look at the current function
5903 to determine if stdarg or varargs is used and return the address of
5904 the first unnamed parameter. */
5907 sparc_builtin_saveregs (void)
5909 int first_reg = current_function_args_info.words;
5913 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
5914 emit_move_insn (gen_rtx_MEM (word_mode,
5915 gen_rtx_PLUS (Pmode,
5917 GEN_INT (FIRST_PARM_OFFSET (0)
5920 gen_rtx_REG (word_mode,
5921 SPARC_INCOMING_INT_ARG_FIRST + regno));
5923 address = gen_rtx_PLUS (Pmode,
5925 GEN_INT (FIRST_PARM_OFFSET (0)
5926 + UNITS_PER_WORD * first_reg));
5931 /* Implement `va_start' for stdarg. */
5934 sparc_va_start (tree valist, rtx nextarg)
5936 nextarg = expand_builtin_saveregs ();
5937 std_expand_builtin_va_start (valist, nextarg);
5940 /* Implement `va_arg' for stdarg. */
5943 sparc_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5945 HOST_WIDE_INT size, rsize, align;
5948 tree ptrtype = build_pointer_type (type);
5950 if (function_arg_pass_by_reference (0, TYPE_MODE (type), type, 0))
5953 size = rsize = UNITS_PER_WORD;
5959 size = int_size_in_bytes (type);
5960 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5965 /* For SPARC64, objects requiring 16-byte alignment get it. */
5966 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5967 align = 2 * UNITS_PER_WORD;
5969 /* SPARC-V9 ABI states that structures up to 16 bytes in size
5970 are given whole slots as needed. */
5971 if (AGGREGATE_TYPE_P (type))
5974 size = rsize = UNITS_PER_WORD;
5984 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
5985 ssize_int (align - 1)));
5986 incr = fold (build2 (BIT_AND_EXPR, ptr_type_node, incr,
5987 ssize_int (-align)));
5990 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
5993 if (BYTES_BIG_ENDIAN && size < rsize)
5994 addr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
5995 ssize_int (rsize - size)));
5999 addr = fold_convert (build_pointer_type (ptrtype), addr);
6000 addr = build_fold_indirect_ref (addr);
6002 /* If the address isn't aligned properly for the type,
6003 we may need to copy to a temporary.
6004 FIXME: This is inefficient. Usually we can do this
6007 && TYPE_ALIGN (type) > BITS_PER_WORD)
6009 tree tmp = create_tmp_var (type, "va_arg_tmp");
6010 tree dest_addr = build_fold_addr_expr (tmp);
6012 tree copy = build_function_call_expr
6013 (implicit_built_in_decls[BUILT_IN_MEMCPY],
6014 tree_cons (NULL_TREE, dest_addr,
6015 tree_cons (NULL_TREE, addr,
6016 tree_cons (NULL_TREE, size_int (rsize),
6019 gimplify_and_add (copy, pre_p);
6023 addr = fold_convert (ptrtype, addr);
6025 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr, ssize_int (rsize)));
6026 incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr);
6027 gimplify_and_add (incr, post_p);
6029 return build_fold_indirect_ref (addr);
6032 /* Return the string to output a conditional branch to LABEL, which is
6033 the operand number of the label. OP is the conditional expression.
6034 XEXP (OP, 0) is assumed to be a condition code register (integer or
6035 floating point) and its mode specifies what kind of comparison we made.
6037 REVERSED is nonzero if we should reverse the sense of the comparison.
6039 ANNUL is nonzero if we should generate an annulling branch.
6041 NOOP is nonzero if we have to follow this branch by a noop.
6043 INSN, if set, is the insn. */
6046 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
6049 static char string[50];
6050 enum rtx_code code = GET_CODE (op);
6051 rtx cc_reg = XEXP (op, 0);
6052 enum machine_mode mode = GET_MODE (cc_reg);
6053 const char *labelno, *branch;
6054 int spaces = 8, far;
6057 /* v9 branches are limited to +-1MB. If it is too far away,
6070 fbne,a,pn %fcc2, .LC29
6078 far = get_attr_length (insn) >= 3;
6081 /* Reversal of FP compares takes care -- an ordered compare
6082 becomes an unordered compare and vice versa. */
6083 if (mode == CCFPmode || mode == CCFPEmode)
6084 code = reverse_condition_maybe_unordered (code);
6086 code = reverse_condition (code);
6089 /* Start by writing the branch condition. */
6090 if (mode == CCFPmode || mode == CCFPEmode)
6141 /* ??? !v9: FP branches cannot be preceded by another floating point
6142 insn. Because there is currently no concept of pre-delay slots,
6143 we can fix this only by always emitting a nop before a floating
6148 strcpy (string, "nop\n\t");
6149 strcat (string, branch);
6162 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6174 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6195 strcpy (string, branch);
6197 spaces -= strlen (branch);
6198 p = strchr (string, '\0');
6200 /* Now add the annulling, the label, and a possible noop. */
6215 if (! far && insn && INSN_ADDRESSES_SET_P ())
6217 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6218 - INSN_ADDRESSES (INSN_UID (insn)));
6219 /* Leave some instructions for "slop". */
6220 if (delta < -260000 || delta >= 260000)
6224 if (mode == CCFPmode || mode == CCFPEmode)
6226 static char v9_fcc_labelno[] = "%%fccX, ";
6227 /* Set the char indicating the number of the fcc reg to use. */
6228 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6229 labelno = v9_fcc_labelno;
6232 if (REGNO (cc_reg) == SPARC_FCC_REG)
6238 else if (mode == CCXmode || mode == CCX_NOOVmode)
6240 labelno = "%%xcc, ";
6246 labelno = "%%icc, ";
6251 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6254 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6264 strcpy (p, labelno);
6265 p = strchr (p, '\0');
6268 strcpy (p, ".+12\n\tnop\n\tb\t");
6275 /* Set the char indicating the number of the operand containing the
6280 strcpy (p, "\n\tnop");
6285 /* Emit a library call comparison between floating point X and Y.
6286 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6287 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6288 values as arguments instead of the TFmode registers themselves,
6289 that's why we cannot call emit_float_lib_cmp. */
6291 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6294 rtx slot0, slot1, result, tem, tem2;
6295 enum machine_mode mode;
6300 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6304 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6308 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6312 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6316 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6320 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6331 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6341 if (GET_CODE (x) != MEM)
6343 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6344 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6349 if (GET_CODE (y) != MEM)
6351 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6352 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6357 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6359 XEXP (slot0, 0), Pmode,
6360 XEXP (slot1, 0), Pmode);
6366 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6368 x, TFmode, y, TFmode);
6374 /* Immediately move the result of the libcall into a pseudo
6375 register so reload doesn't clobber the value if it needs
6376 the return register for a spill reg. */
6377 result = gen_reg_rtx (mode);
6378 emit_move_insn (result, hard_libcall_value (mode));
6383 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6387 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6392 emit_cmp_insn (result, const1_rtx,
6393 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6396 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6399 tem = gen_reg_rtx (mode);
6401 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6403 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6404 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6408 tem = gen_reg_rtx (mode);
6410 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6412 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6413 tem2 = gen_reg_rtx (mode);
6415 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6417 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6418 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6424 /* Generate an unsigned DImode to FP conversion. This is the same code
6425 optabs would emit if we didn't have TFmode patterns. */
6428 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
6430 rtx neglab, donelab, i0, i1, f0, in, out;
6433 in = force_reg (DImode, operands[1]);
6434 neglab = gen_label_rtx ();
6435 donelab = gen_label_rtx ();
6436 i0 = gen_reg_rtx (DImode);
6437 i1 = gen_reg_rtx (DImode);
6438 f0 = gen_reg_rtx (mode);
6440 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6442 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6443 emit_jump_insn (gen_jump (donelab));
6446 emit_label (neglab);
6448 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6449 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6450 emit_insn (gen_iordi3 (i0, i0, i1));
6451 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6452 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6454 emit_label (donelab);
6457 /* Generate an FP to unsigned DImode conversion. This is the same code
6458 optabs would emit if we didn't have TFmode patterns. */
6461 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
6463 rtx neglab, donelab, i0, i1, f0, in, out, limit;
6466 in = force_reg (mode, operands[1]);
6467 neglab = gen_label_rtx ();
6468 donelab = gen_label_rtx ();
6469 i0 = gen_reg_rtx (DImode);
6470 i1 = gen_reg_rtx (DImode);
6471 limit = gen_reg_rtx (mode);
6472 f0 = gen_reg_rtx (mode);
6474 emit_move_insn (limit,
6475 CONST_DOUBLE_FROM_REAL_VALUE (
6476 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
6477 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
6479 emit_insn (gen_rtx_SET (VOIDmode,
6481 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
6482 emit_jump_insn (gen_jump (donelab));
6485 emit_label (neglab);
6487 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
6488 emit_insn (gen_rtx_SET (VOIDmode,
6490 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6491 emit_insn (gen_movdi (i1, const1_rtx));
6492 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6493 emit_insn (gen_xordi3 (out, i0, i1));
6495 emit_label (donelab);
6498 /* Return the string to output a conditional branch to LABEL, testing
6499 register REG. LABEL is the operand number of the label; REG is the
6500 operand number of the reg. OP is the conditional expression. The mode
6501 of REG says what kind of comparison we made.
6503 REVERSED is nonzero if we should reverse the sense of the comparison.
6505 ANNUL is nonzero if we should generate an annulling branch.
6507 NOOP is nonzero if we have to follow this branch by a noop. */
6510 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6511 int annul, int noop, rtx insn)
6513 static char string[50];
6514 enum rtx_code code = GET_CODE (op);
6515 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6520 /* branch on register are limited to +-128KB. If it is too far away,
6533 brgez,a,pn %o1, .LC29
6539 ba,pt %xcc, .LC29 */
6541 far = get_attr_length (insn) >= 3;
6543 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6545 code = reverse_condition (code);
6547 /* Only 64 bit versions of these instructions exist. */
6551 /* Start by writing the branch condition. */
6556 strcpy (string, "brnz");
6560 strcpy (string, "brz");
6564 strcpy (string, "brgez");
6568 strcpy (string, "brlz");
6572 strcpy (string, "brlez");
6576 strcpy (string, "brgz");
6583 p = strchr (string, '\0');
6585 /* Now add the annulling, reg, label, and nop. */
6592 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6595 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6600 *p = p < string + 8 ? '\t' : ' ';
6608 int veryfar = 1, delta;
6610 if (INSN_ADDRESSES_SET_P ())
6612 delta = (INSN_ADDRESSES (INSN_UID (dest))
6613 - INSN_ADDRESSES (INSN_UID (insn)));
6614 /* Leave some instructions for "slop". */
6615 if (delta >= -260000 && delta < 260000)
6619 strcpy (p, ".+12\n\tnop\n\t");
6630 strcpy (p, "ba,pt\t%%xcc, ");
6640 strcpy (p, "\n\tnop");
6645 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6646 Such instructions cannot be used in the delay slot of return insn on v9.
6647 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6651 epilogue_renumber (register rtx *where, int test)
6653 register const char *fmt;
6655 register enum rtx_code code;
6660 code = GET_CODE (*where);
6665 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6667 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6668 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6676 /* Do not replace the frame pointer with the stack pointer because
6677 it can cause the delayed instruction to load below the stack.
6678 This occurs when instructions like:
6680 (set (reg/i:SI 24 %i0)
6681 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6682 (const_int -20 [0xffffffec])) 0))
6684 are in the return delayed slot. */
6686 if (GET_CODE (XEXP (*where, 0)) == REG
6687 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6688 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6689 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6694 if (SPARC_STACK_BIAS
6695 && GET_CODE (XEXP (*where, 0)) == REG
6696 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6704 fmt = GET_RTX_FORMAT (code);
6706 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6711 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6712 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6715 else if (fmt[i] == 'e'
6716 && epilogue_renumber (&(XEXP (*where, i)), test))
6722 /* Leaf functions and non-leaf functions have different needs. */
6725 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6728 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6730 static const int *const reg_alloc_orders[] = {
6731 reg_leaf_alloc_order,
6732 reg_nonleaf_alloc_order};
6735 order_regs_for_local_alloc (void)
6737 static int last_order_nonleaf = 1;
6739 if (regs_ever_live[15] != last_order_nonleaf)
6741 last_order_nonleaf = !last_order_nonleaf;
6742 memcpy ((char *) reg_alloc_order,
6743 (const char *) reg_alloc_orders[last_order_nonleaf],
6744 FIRST_PSEUDO_REGISTER * sizeof (int));
6748 /* Return 1 if REG and MEM are legitimate enough to allow the various
6749 mem<-->reg splits to be run. */
6752 sparc_splitdi_legitimate (rtx reg, rtx mem)
6754 /* Punt if we are here by mistake. */
6755 if (! reload_completed)
6758 /* We must have an offsettable memory reference. */
6759 if (! offsettable_memref_p (mem))
6762 /* If we have legitimate args for ldd/std, we do not want
6763 the split to happen. */
6764 if ((REGNO (reg) % 2) == 0
6765 && mem_min_alignment (mem, 8))
6772 /* Return 1 if x and y are some kind of REG and they refer to
6773 different hard registers. This test is guaranteed to be
6774 run after reload. */
6777 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6779 if (GET_CODE (x) != REG)
6781 if (GET_CODE (y) != REG)
6783 if (REGNO (x) == REGNO (y))
6788 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6789 This makes them candidates for using ldd and std insns.
6791 Note reg1 and reg2 *must* be hard registers. */
6794 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6796 /* We might have been passed a SUBREG. */
6797 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6800 if (REGNO (reg1) % 2 != 0)
6803 /* Integer ldd is deprecated in SPARC V9 */
6804 if (TARGET_V9 && REGNO (reg1) < 32)
6807 return (REGNO (reg1) == REGNO (reg2) - 1);
6810 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6813 This can only happen when addr1 and addr2, the addresses in mem1
6814 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6815 addr1 must also be aligned on a 64-bit boundary.
6817 Also iff dependent_reg_rtx is not null it should not be used to
6818 compute the address for mem1, i.e. we cannot optimize a sequence
6830 But, note that the transformation from:
6835 is perfectly fine. Thus, the peephole2 patterns always pass us
6836 the destination register of the first load, never the second one.
6838 For stores we don't have a similar problem, so dependent_reg_rtx is
6842 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6846 HOST_WIDE_INT offset1;
6848 /* The mems cannot be volatile. */
6849 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6852 /* MEM1 should be aligned on a 64-bit boundary. */
6853 if (MEM_ALIGN (mem1) < 64)
6856 addr1 = XEXP (mem1, 0);
6857 addr2 = XEXP (mem2, 0);
6859 /* Extract a register number and offset (if used) from the first addr. */
6860 if (GET_CODE (addr1) == PLUS)
6862 /* If not a REG, return zero. */
6863 if (GET_CODE (XEXP (addr1, 0)) != REG)
6867 reg1 = REGNO (XEXP (addr1, 0));
6868 /* The offset must be constant! */
6869 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6871 offset1 = INTVAL (XEXP (addr1, 1));
6874 else if (GET_CODE (addr1) != REG)
6878 reg1 = REGNO (addr1);
6879 /* This was a simple (mem (reg)) expression. Offset is 0. */
6883 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6884 if (GET_CODE (addr2) != PLUS)
6887 if (GET_CODE (XEXP (addr2, 0)) != REG
6888 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6891 if (reg1 != REGNO (XEXP (addr2, 0)))
6894 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6897 /* The first offset must be evenly divisible by 8 to ensure the
6898 address is 64 bit aligned. */
6899 if (offset1 % 8 != 0)
6902 /* The offset for the second addr must be 4 more than the first addr. */
6903 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6906 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6911 /* Return 1 if reg is a pseudo, or is the first register in
6912 a hard register pair. This makes it a candidate for use in
6913 ldd and std insns. */
6916 register_ok_for_ldd (rtx reg)
6918 /* We might have been passed a SUBREG. */
6919 if (GET_CODE (reg) != REG)
6922 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6923 return (REGNO (reg) % 2 == 0);
6928 /* Print operand X (an rtx) in assembler syntax to file FILE.
6929 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6930 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6933 print_operand (FILE *file, rtx x, int code)
6938 /* Output a 'nop' if there's nothing for the delay slot. */
6939 if (dbr_sequence_length () == 0)
6940 fputs ("\n\t nop", file);
6943 /* Output an annul flag if there's nothing for the delay slot and we
6944 are optimizing. This is always used with '(' below. */
6945 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6946 this is a dbx bug. So, we only do this when optimizing. */
6947 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6948 Always emit a nop in case the next instruction is a branch. */
6949 if (dbr_sequence_length () == 0
6950 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6954 /* Output a 'nop' if there's nothing for the delay slot and we are
6955 not optimizing. This is always used with '*' above. */
6956 if (dbr_sequence_length () == 0
6957 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6958 fputs ("\n\t nop", file);
6961 /* Output the Embedded Medium/Anywhere code model base register. */
6962 fputs (EMBMEDANY_BASE_REG, file);
6965 /* Print out what we are using as the frame pointer. This might
6966 be %fp, or might be %sp+offset. */
6967 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6968 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC, frame_base_name, frame_base_offset);
6971 /* Print some local dynamic TLS name. */
6972 assemble_name (file, get_some_local_dynamic_name ());
6975 /* Adjust the operand to take into account a RESTORE operation. */
6976 if (GET_CODE (x) == CONST_INT)
6978 else if (GET_CODE (x) != REG)
6979 output_operand_lossage ("invalid %%Y operand");
6980 else if (REGNO (x) < 8)
6981 fputs (reg_names[REGNO (x)], file);
6982 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6983 fputs (reg_names[REGNO (x)-16], file);
6985 output_operand_lossage ("invalid %%Y operand");
6988 /* Print out the low order register name of a register pair. */
6989 if (WORDS_BIG_ENDIAN)
6990 fputs (reg_names[REGNO (x)+1], file);
6992 fputs (reg_names[REGNO (x)], file);
6995 /* Print out the high order register name of a register pair. */
6996 if (WORDS_BIG_ENDIAN)
6997 fputs (reg_names[REGNO (x)], file);
6999 fputs (reg_names[REGNO (x)+1], file);
7002 /* Print out the second register name of a register pair or quad.
7003 I.e., R (%o0) => %o1. */
7004 fputs (reg_names[REGNO (x)+1], file);
7007 /* Print out the third register name of a register quad.
7008 I.e., S (%o0) => %o2. */
7009 fputs (reg_names[REGNO (x)+2], file);
7012 /* Print out the fourth register name of a register quad.
7013 I.e., T (%o0) => %o3. */
7014 fputs (reg_names[REGNO (x)+3], file);
7017 /* Print a condition code register. */
7018 if (REGNO (x) == SPARC_ICC_REG)
7020 /* We don't handle CC[X]_NOOVmode because they're not supposed
7022 if (GET_MODE (x) == CCmode)
7023 fputs ("%icc", file);
7024 else if (GET_MODE (x) == CCXmode)
7025 fputs ("%xcc", file);
7030 /* %fccN register */
7031 fputs (reg_names[REGNO (x)], file);
7034 /* Print the operand's address only. */
7035 output_address (XEXP (x, 0));
7038 /* In this case we need a register. Use %g0 if the
7039 operand is const0_rtx. */
7041 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
7043 fputs ("%g0", file);
7050 switch (GET_CODE (x))
7052 case IOR: fputs ("or", file); break;
7053 case AND: fputs ("and", file); break;
7054 case XOR: fputs ("xor", file); break;
7055 default: output_operand_lossage ("invalid %%A operand");
7060 switch (GET_CODE (x))
7062 case IOR: fputs ("orn", file); break;
7063 case AND: fputs ("andn", file); break;
7064 case XOR: fputs ("xnor", file); break;
7065 default: output_operand_lossage ("invalid %%B operand");
7069 /* These are used by the conditional move instructions. */
7073 enum rtx_code rc = GET_CODE (x);
7077 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7078 if (mode == CCFPmode || mode == CCFPEmode)
7079 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7081 rc = reverse_condition (GET_CODE (x));
7085 case NE: fputs ("ne", file); break;
7086 case EQ: fputs ("e", file); break;
7087 case GE: fputs ("ge", file); break;
7088 case GT: fputs ("g", file); break;
7089 case LE: fputs ("le", file); break;
7090 case LT: fputs ("l", file); break;
7091 case GEU: fputs ("geu", file); break;
7092 case GTU: fputs ("gu", file); break;
7093 case LEU: fputs ("leu", file); break;
7094 case LTU: fputs ("lu", file); break;
7095 case LTGT: fputs ("lg", file); break;
7096 case UNORDERED: fputs ("u", file); break;
7097 case ORDERED: fputs ("o", file); break;
7098 case UNLT: fputs ("ul", file); break;
7099 case UNLE: fputs ("ule", file); break;
7100 case UNGT: fputs ("ug", file); break;
7101 case UNGE: fputs ("uge", file); break;
7102 case UNEQ: fputs ("ue", file); break;
7103 default: output_operand_lossage (code == 'c'
7104 ? "invalid %%c operand"
7105 : "invalid %%C operand");
7110 /* These are used by the movr instruction pattern. */
7114 enum rtx_code rc = (code == 'd'
7115 ? reverse_condition (GET_CODE (x))
7119 case NE: fputs ("ne", file); break;
7120 case EQ: fputs ("e", file); break;
7121 case GE: fputs ("gez", file); break;
7122 case LT: fputs ("lz", file); break;
7123 case LE: fputs ("lez", file); break;
7124 case GT: fputs ("gz", file); break;
7125 default: output_operand_lossage (code == 'd'
7126 ? "invalid %%d operand"
7127 : "invalid %%D operand");
7134 /* Print a sign-extended character. */
7135 int i = trunc_int_for_mode (INTVAL (x), QImode);
7136 fprintf (file, "%d", i);
7141 /* Operand must be a MEM; write its address. */
7142 if (GET_CODE (x) != MEM)
7143 output_operand_lossage ("invalid %%f operand");
7144 output_address (XEXP (x, 0));
7149 /* Print a sign-extended 32-bit value. */
7151 if (GET_CODE(x) == CONST_INT)
7153 else if (GET_CODE(x) == CONST_DOUBLE)
7154 i = CONST_DOUBLE_LOW (x);
7157 output_operand_lossage ("invalid %%s operand");
7160 i = trunc_int_for_mode (i, SImode);
7161 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7166 /* Do nothing special. */
7170 /* Undocumented flag. */
7171 output_operand_lossage ("invalid operand output code");
7174 if (GET_CODE (x) == REG)
7175 fputs (reg_names[REGNO (x)], file);
7176 else if (GET_CODE (x) == MEM)
7179 /* Poor Sun assembler doesn't understand absolute addressing. */
7180 if (CONSTANT_P (XEXP (x, 0)))
7181 fputs ("%g0+", file);
7182 output_address (XEXP (x, 0));
7185 else if (GET_CODE (x) == HIGH)
7187 fputs ("%hi(", file);
7188 output_addr_const (file, XEXP (x, 0));
7191 else if (GET_CODE (x) == LO_SUM)
7193 print_operand (file, XEXP (x, 0), 0);
7194 if (TARGET_CM_MEDMID)
7195 fputs ("+%l44(", file);
7197 fputs ("+%lo(", file);
7198 output_addr_const (file, XEXP (x, 1));
7201 else if (GET_CODE (x) == CONST_DOUBLE
7202 && (GET_MODE (x) == VOIDmode
7203 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
7205 if (CONST_DOUBLE_HIGH (x) == 0)
7206 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
7207 else if (CONST_DOUBLE_HIGH (x) == -1
7208 && CONST_DOUBLE_LOW (x) < 0)
7209 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
7211 output_operand_lossage ("long long constant not a valid immediate operand");
7213 else if (GET_CODE (x) == CONST_DOUBLE)
7214 output_operand_lossage ("floating point constant not a valid immediate operand");
7215 else { output_addr_const (file, x); }
7218 /* Target hook for assembling integer objects. The sparc version has
7219 special handling for aligned DI-mode objects. */
7222 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7224 /* ??? We only output .xword's for symbols and only then in environments
7225 where the assembler can handle them. */
7226 if (aligned_p && size == 8
7227 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7231 assemble_integer_with_op ("\t.xword\t", x);
7236 assemble_aligned_integer (4, const0_rtx);
7237 assemble_aligned_integer (4, x);
7241 return default_assemble_integer (x, size, aligned_p);
7244 /* Return the value of a code used in the .proc pseudo-op that says
7245 what kind of result this function returns. For non-C types, we pick
7246 the closest C type. */
7248 #ifndef SHORT_TYPE_SIZE
7249 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7252 #ifndef INT_TYPE_SIZE
7253 #define INT_TYPE_SIZE BITS_PER_WORD
7256 #ifndef LONG_TYPE_SIZE
7257 #define LONG_TYPE_SIZE BITS_PER_WORD
7260 #ifndef LONG_LONG_TYPE_SIZE
7261 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7264 #ifndef FLOAT_TYPE_SIZE
7265 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7268 #ifndef DOUBLE_TYPE_SIZE
7269 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7272 #ifndef LONG_DOUBLE_TYPE_SIZE
7273 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7277 sparc_type_code (register tree type)
7279 register unsigned long qualifiers = 0;
7280 register unsigned shift;
7282 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7283 setting more, since some assemblers will give an error for this. Also,
7284 we must be careful to avoid shifts of 32 bits or more to avoid getting
7285 unpredictable results. */
7287 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7289 switch (TREE_CODE (type))
7295 qualifiers |= (3 << shift);
7300 qualifiers |= (2 << shift);
7304 case REFERENCE_TYPE:
7306 qualifiers |= (1 << shift);
7310 return (qualifiers | 8);
7313 case QUAL_UNION_TYPE:
7314 return (qualifiers | 9);
7317 return (qualifiers | 10);
7320 return (qualifiers | 16);
7323 /* If this is a range type, consider it to be the underlying
7325 if (TREE_TYPE (type) != 0)
7328 /* Carefully distinguish all the standard types of C,
7329 without messing up if the language is not C. We do this by
7330 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
7331 look at both the names and the above fields, but that's redundant.
7332 Any type whose size is between two C types will be considered
7333 to be the wider of the two types. Also, we do not have a
7334 special code to use for "long long", so anything wider than
7335 long is treated the same. Note that we can't distinguish
7336 between "int" and "long" in this code if they are the same
7337 size, but that's fine, since neither can the assembler. */
7339 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7340 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
7342 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7343 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
7345 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7346 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
7349 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
7352 /* If this is a range type, consider it to be the underlying
7354 if (TREE_TYPE (type) != 0)
7357 /* Carefully distinguish all the standard types of C,
7358 without messing up if the language is not C. */
7360 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7361 return (qualifiers | 6);
7364 return (qualifiers | 7);
7366 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7367 /* ??? We need to distinguish between double and float complex types,
7368 but I don't know how yet because I can't reach this code from
7369 existing front-ends. */
7370 return (qualifiers | 7); /* Who knows? */
7373 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7374 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7375 case FILE_TYPE: /* GNU Pascal FILE type. */
7376 case SET_TYPE: /* GNU Pascal SET type. */
7377 case LANG_TYPE: /* ? */
7381 abort (); /* Not a type! */
7388 /* Nested function support. */
7390 /* Emit RTL insns to initialize the variable parts of a trampoline.
7391 FNADDR is an RTX for the address of the function's pure code.
7392 CXT is an RTX for the static chain value for the function.
7394 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7395 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7396 (to store insns). This is a bit excessive. Perhaps a different
7397 mechanism would be better here.
7399 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7402 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7404 /* SPARC 32-bit trampoline:
7407 sethi %hi(static), %g2
7409 or %g2, %lo(static), %g2
7411 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7412 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7416 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7417 expand_binop (SImode, ior_optab,
7418 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7419 size_int (10), 0, 1),
7420 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7421 NULL_RTX, 1, OPTAB_DIRECT));
7424 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7425 expand_binop (SImode, ior_optab,
7426 expand_shift (RSHIFT_EXPR, SImode, cxt,
7427 size_int (10), 0, 1),
7428 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7429 NULL_RTX, 1, OPTAB_DIRECT));
7432 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7433 expand_binop (SImode, ior_optab,
7434 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7435 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7436 NULL_RTX, 1, OPTAB_DIRECT));
7439 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7440 expand_binop (SImode, ior_optab,
7441 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7442 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7443 NULL_RTX, 1, OPTAB_DIRECT));
7445 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7446 aligned on a 16 byte boundary so one flush clears it all. */
7447 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7448 if (sparc_cpu != PROCESSOR_ULTRASPARC
7449 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7450 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7451 plus_constant (tramp, 8)))));
7453 /* Call __enable_execute_stack after writing onto the stack to make sure
7454 the stack address is accessible. */
7455 #ifdef TRANSFER_FROM_TRAMPOLINE
7456 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7457 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7462 /* The 64-bit version is simpler because it makes more sense to load the
7463 values as "immediate" data out of the trampoline. It's also easier since
7464 we can read the PC without clobbering a register. */
7467 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7469 /* SPARC 64-bit trampoline:
7478 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7479 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7480 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7481 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7482 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7483 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7484 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7485 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7486 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7487 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7488 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7490 if (sparc_cpu != PROCESSOR_ULTRASPARC
7491 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7492 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7494 /* Call __enable_execute_stack after writing onto the stack to make sure
7495 the stack address is accessible. */
7496 #ifdef TRANSFER_FROM_TRAMPOLINE
7497 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7498 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7502 /* Adjust the cost of a scheduling dependency. Return the new cost of
7503 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7506 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7508 enum attr_type insn_type;
7510 if (! recog_memoized (insn))
7513 insn_type = get_attr_type (insn);
7515 if (REG_NOTE_KIND (link) == 0)
7517 /* Data dependency; DEP_INSN writes a register that INSN reads some
7520 /* if a load, then the dependence must be on the memory address;
7521 add an extra "cycle". Note that the cost could be two cycles
7522 if the reg was written late in an instruction group; we ca not tell
7524 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7527 /* Get the delay only if the address of the store is the dependence. */
7528 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7530 rtx pat = PATTERN(insn);
7531 rtx dep_pat = PATTERN (dep_insn);
7533 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7534 return cost; /* This should not happen! */
7536 /* The dependency between the two instructions was on the data that
7537 is being stored. Assume that this implies that the address of the
7538 store is not dependent. */
7539 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7542 return cost + 3; /* An approximation. */
7545 /* A shift instruction cannot receive its data from an instruction
7546 in the same cycle; add a one cycle penalty. */
7547 if (insn_type == TYPE_SHIFT)
7548 return cost + 3; /* Split before cascade into shift. */
7552 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7553 INSN writes some cycles later. */
7555 /* These are only significant for the fpu unit; writing a fp reg before
7556 the fpu has finished with it stalls the processor. */
7558 /* Reusing an integer register causes no problems. */
7559 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7567 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7569 enum attr_type insn_type, dep_type;
7570 rtx pat = PATTERN(insn);
7571 rtx dep_pat = PATTERN (dep_insn);
7573 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7576 insn_type = get_attr_type (insn);
7577 dep_type = get_attr_type (dep_insn);
7579 switch (REG_NOTE_KIND (link))
7582 /* Data dependency; DEP_INSN writes a register that INSN reads some
7589 /* Get the delay iff the address of the store is the dependence. */
7590 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7593 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7600 /* If a load, then the dependence must be on the memory address. If
7601 the addresses aren't equal, then it might be a false dependency */
7602 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7604 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7605 || GET_CODE (SET_DEST (dep_pat)) != MEM
7606 || GET_CODE (SET_SRC (pat)) != MEM
7607 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7608 XEXP (SET_SRC (pat), 0)))
7616 /* Compare to branch latency is 0. There is no benefit from
7617 separating compare and branch. */
7618 if (dep_type == TYPE_COMPARE)
7620 /* Floating point compare to branch latency is less than
7621 compare to conditional move. */
7622 if (dep_type == TYPE_FPCMP)
7631 /* Anti-dependencies only penalize the fpu unit. */
7632 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7644 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
7648 case PROCESSOR_SUPERSPARC:
7649 cost = supersparc_adjust_cost (insn, link, dep, cost);
7651 case PROCESSOR_HYPERSPARC:
7652 case PROCESSOR_SPARCLITE86X:
7653 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7662 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7663 int sched_verbose ATTRIBUTE_UNUSED,
7664 int max_ready ATTRIBUTE_UNUSED)
7669 sparc_use_dfa_pipeline_interface (void)
7671 if ((1 << sparc_cpu) &
7672 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
7673 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7674 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
7675 (1 << PROCESSOR_ULTRASPARC3)))
7681 sparc_use_sched_lookahead (void)
7683 if (sparc_cpu == PROCESSOR_ULTRASPARC
7684 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7686 if ((1 << sparc_cpu) &
7687 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7688 (1 << PROCESSOR_SPARCLITE86X)))
7694 sparc_issue_rate (void)
7701 /* Assume V9 processors are capable of at least dual-issue. */
7703 case PROCESSOR_SUPERSPARC:
7705 case PROCESSOR_HYPERSPARC:
7706 case PROCESSOR_SPARCLITE86X:
7708 case PROCESSOR_ULTRASPARC:
7709 case PROCESSOR_ULTRASPARC3:
7715 set_extends (rtx insn)
7717 register rtx pat = PATTERN (insn);
7719 switch (GET_CODE (SET_SRC (pat)))
7721 /* Load and some shift instructions zero extend. */
7724 /* sethi clears the high bits */
7726 /* LO_SUM is used with sethi. sethi cleared the high
7727 bits and the values used with lo_sum are positive */
7729 /* Store flag stores 0 or 1 */
7739 rtx op0 = XEXP (SET_SRC (pat), 0);
7740 rtx op1 = XEXP (SET_SRC (pat), 1);
7741 if (GET_CODE (op1) == CONST_INT)
7742 return INTVAL (op1) >= 0;
7743 if (GET_CODE (op0) != REG)
7745 if (sparc_check_64 (op0, insn) == 1)
7747 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7752 rtx op0 = XEXP (SET_SRC (pat), 0);
7753 rtx op1 = XEXP (SET_SRC (pat), 1);
7754 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7756 if (GET_CODE (op1) == CONST_INT)
7757 return INTVAL (op1) >= 0;
7758 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7761 return GET_MODE (SET_SRC (pat)) == SImode;
7762 /* Positive integers leave the high bits zero. */
7764 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7766 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7769 return - (GET_MODE (SET_SRC (pat)) == SImode);
7771 return sparc_check_64 (SET_SRC (pat), insn);
7777 /* We _ought_ to have only one kind per function, but... */
7778 static GTY(()) rtx sparc_addr_diff_list;
7779 static GTY(()) rtx sparc_addr_list;
7782 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
7784 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7786 sparc_addr_diff_list
7787 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7789 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7793 sparc_output_addr_vec (rtx vec)
7795 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7796 int idx, vlen = XVECLEN (body, 0);
7798 #ifdef ASM_OUTPUT_ADDR_VEC_START
7799 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7802 #ifdef ASM_OUTPUT_CASE_LABEL
7803 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7806 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7809 for (idx = 0; idx < vlen; idx++)
7811 ASM_OUTPUT_ADDR_VEC_ELT
7812 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7815 #ifdef ASM_OUTPUT_ADDR_VEC_END
7816 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7821 sparc_output_addr_diff_vec (rtx vec)
7823 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7824 rtx base = XEXP (XEXP (body, 0), 0);
7825 int idx, vlen = XVECLEN (body, 1);
7827 #ifdef ASM_OUTPUT_ADDR_VEC_START
7828 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7831 #ifdef ASM_OUTPUT_CASE_LABEL
7832 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7835 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7838 for (idx = 0; idx < vlen; idx++)
7840 ASM_OUTPUT_ADDR_DIFF_ELT
7843 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7844 CODE_LABEL_NUMBER (base));
7847 #ifdef ASM_OUTPUT_ADDR_VEC_END
7848 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7853 sparc_output_deferred_case_vectors (void)
7858 if (sparc_addr_list == NULL_RTX
7859 && sparc_addr_diff_list == NULL_RTX)
7862 /* Align to cache line in the function's code section. */
7863 function_section (current_function_decl);
7865 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7867 ASM_OUTPUT_ALIGN (asm_out_file, align);
7869 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7870 sparc_output_addr_vec (XEXP (t, 0));
7871 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7872 sparc_output_addr_diff_vec (XEXP (t, 0));
7874 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7877 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7878 unknown. Return 1 if the high bits are zero, -1 if the register is
7881 sparc_check_64 (rtx x, rtx insn)
7883 /* If a register is set only once it is safe to ignore insns this
7884 code does not know how to handle. The loop will either recognize
7885 the single set and return the correct value or fail to recognize
7890 if (GET_CODE (x) != REG)
7893 if (GET_MODE (x) == DImode)
7894 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
7896 if (flag_expensive_optimizations
7897 && REG_N_SETS (REGNO (y)) == 1)
7903 insn = get_last_insn_anywhere ();
7908 while ((insn = PREV_INSN (insn)))
7910 switch (GET_CODE (insn))
7923 rtx pat = PATTERN (insn);
7924 if (GET_CODE (pat) != SET)
7926 if (rtx_equal_p (x, SET_DEST (pat)))
7927 return set_extends (insn);
7928 if (y && rtx_equal_p (y, SET_DEST (pat)))
7929 return set_extends (insn);
7930 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
7938 /* Returns assembly code to perform a DImode shift using
7939 a 64-bit global or out register on SPARC-V8+. */
7941 sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
7943 static char asm_code[60];
7945 /* The scratch register is only required when the destination
7946 register is not a 64-bit global or out register. */
7947 if (which_alternative != 2)
7948 operands[3] = operands[0];
7950 /* We can only shift by constants <= 63. */
7951 if (GET_CODE (operands[2]) == CONST_INT)
7952 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7954 if (GET_CODE (operands[1]) == CONST_INT)
7956 output_asm_insn ("mov\t%1, %3", operands);
7960 output_asm_insn ("sllx\t%H1, 32, %3", operands);
7961 if (sparc_check_64 (operands[1], insn) <= 0)
7962 output_asm_insn ("srl\t%L1, 0, %L1", operands);
7963 output_asm_insn ("or\t%L1, %3, %3", operands);
7966 strcpy(asm_code, opcode);
7968 if (which_alternative != 2)
7969 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7971 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7974 /* Output rtl to increment the profiler label LABELNO
7975 for profiling a function entry. */
7978 sparc_profile_hook (int labelno)
7983 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
7984 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
7985 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
7987 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
7990 #ifdef OBJECT_FORMAT_ELF
7992 sparc_elf_asm_named_section (const char *name, unsigned int flags)
7994 if (flags & SECTION_MERGE)
7996 /* entsize cannot be expressed in this section attributes
7998 default_elf_asm_named_section (name, flags);
8002 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8004 if (!(flags & SECTION_DEBUG))
8005 fputs (",#alloc", asm_out_file);
8006 if (flags & SECTION_WRITE)
8007 fputs (",#write", asm_out_file);
8008 if (flags & SECTION_TLS)
8009 fputs (",#tls", asm_out_file);
8010 if (flags & SECTION_CODE)
8011 fputs (",#execinstr", asm_out_file);
8013 /* ??? Handle SECTION_BSS. */
8015 fputc ('\n', asm_out_file);
8017 #endif /* OBJECT_FORMAT_ELF */
8019 /* We do not allow indirect calls to be optimized into sibling calls.
8021 Also, on SPARC 32-bit we cannot emit a sibling call when the
8022 current function returns a structure. This is because the "unimp
8023 after call" convention would cause the callee to return to the
8024 wrong place. The generic code already disallows cases where the
8025 function being called returns a structure.
8027 It may seem strange how this last case could occur. Usually there
8028 is code after the call which jumps to epilogue code which dumps the
8029 return value into the struct return area. That ought to invalidate
8030 the sibling call right? Well, in the c++ case we can end up passing
8031 the pointer to the struct return area to a constructor (which returns
8032 void) and then nothing else happens. Such a sibling call would look
8033 valid without the added check here. */
8035 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8037 return (decl && (TARGET_ARCH64 || ! current_function_returns_struct));
8040 /* libfunc renaming. */
8041 #include "config/gofast.h"
8044 sparc_init_libfuncs (void)
8048 /* Use the subroutines that Sun's library provides for integer
8049 multiply and divide. The `*' prevents an underscore from
8050 being prepended by the compiler. .umul is a little faster
8052 set_optab_libfunc (smul_optab, SImode, "*.umul");
8053 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8054 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8055 set_optab_libfunc (smod_optab, SImode, "*.rem");
8056 set_optab_libfunc (umod_optab, SImode, "*.urem");
8058 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8059 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8060 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8061 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8062 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8063 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8065 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8066 is because with soft-float, the SFmode and DFmode sqrt
8067 instructions will be absent, and the compiler will notice and
8068 try to use the TFmode sqrt instruction for calls to the
8069 builtin function sqrt, but this fails. */
8071 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8073 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8074 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8075 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8076 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8077 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8078 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8080 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8081 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8082 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8083 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8085 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8086 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8087 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8089 if (DITF_CONVERSION_LIBFUNCS)
8091 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
8092 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
8093 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
8096 if (SUN_CONVERSION_LIBFUNCS)
8098 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8099 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8100 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8101 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8106 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8107 do not exist in the library. Make sure the compiler does not
8108 emit calls to them by accident. (It should always use the
8109 hardware instructions.) */
8110 set_optab_libfunc (smul_optab, SImode, 0);
8111 set_optab_libfunc (sdiv_optab, SImode, 0);
8112 set_optab_libfunc (udiv_optab, SImode, 0);
8113 set_optab_libfunc (smod_optab, SImode, 0);
8114 set_optab_libfunc (umod_optab, SImode, 0);
8116 if (SUN_INTEGER_MULTIPLY_64)
8118 set_optab_libfunc (smul_optab, DImode, "__mul64");
8119 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8120 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8121 set_optab_libfunc (smod_optab, DImode, "__rem64");
8122 set_optab_libfunc (umod_optab, DImode, "__urem64");
8125 if (SUN_CONVERSION_LIBFUNCS)
8127 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8128 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8129 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8130 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8134 gofast_maybe_init_libfuncs ();
8138 sparc_extra_constraint_check (rtx op, int c, int strict)
8143 && (c == 'T' || c == 'U'))
8149 return fp_sethi_p (op);
8152 return fp_mov_p (op);
8155 return fp_high_losum_p (op);
8159 || (GET_CODE (op) == REG
8160 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8161 || reg_renumber[REGNO (op)] >= 0)))
8162 return register_ok_for_ldd (op);
8174 /* Our memory extra constraints have to emulate the
8175 behavior of 'm' and 'o' in order for reload to work
8177 if (GET_CODE (op) == MEM)
8180 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8182 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8187 reload_ok_mem = (reload_in_progress
8188 && GET_CODE (op) == REG
8189 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8190 && reg_renumber [REGNO (op)] < 0);
8193 return reload_ok_mem;
8196 /* ??? This duplicates information provided to the compiler by the
8197 ??? scheduler description. Some day, teach genautomata to output
8198 ??? the latencies and then CSE will just use that. */
8201 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8205 case PLUS: case MINUS: case ABS: case NEG:
8206 case FLOAT: case UNSIGNED_FLOAT:
8207 case FIX: case UNSIGNED_FIX:
8208 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8209 if (FLOAT_MODE_P (GET_MODE (x)))
8213 case PROCESSOR_ULTRASPARC:
8214 case PROCESSOR_ULTRASPARC3:
8215 *total = COSTS_N_INSNS (4);
8218 case PROCESSOR_SUPERSPARC:
8219 *total = COSTS_N_INSNS (3);
8222 case PROCESSOR_CYPRESS:
8223 *total = COSTS_N_INSNS (5);
8226 case PROCESSOR_HYPERSPARC:
8227 case PROCESSOR_SPARCLITE86X:
8229 *total = COSTS_N_INSNS (1);
8234 *total = COSTS_N_INSNS (1);
8240 case PROCESSOR_ULTRASPARC:
8241 if (GET_MODE (x) == SFmode)
8242 *total = COSTS_N_INSNS (13);
8244 *total = COSTS_N_INSNS (23);
8247 case PROCESSOR_ULTRASPARC3:
8248 if (GET_MODE (x) == SFmode)
8249 *total = COSTS_N_INSNS (20);
8251 *total = COSTS_N_INSNS (29);
8254 case PROCESSOR_SUPERSPARC:
8255 *total = COSTS_N_INSNS (12);
8258 case PROCESSOR_CYPRESS:
8259 *total = COSTS_N_INSNS (63);
8262 case PROCESSOR_HYPERSPARC:
8263 case PROCESSOR_SPARCLITE86X:
8264 *total = COSTS_N_INSNS (17);
8268 *total = COSTS_N_INSNS (30);
8273 if (FLOAT_MODE_P (GET_MODE (x)))
8277 case PROCESSOR_ULTRASPARC:
8278 case PROCESSOR_ULTRASPARC3:
8279 *total = COSTS_N_INSNS (1);
8282 case PROCESSOR_SUPERSPARC:
8283 *total = COSTS_N_INSNS (3);
8286 case PROCESSOR_CYPRESS:
8287 *total = COSTS_N_INSNS (5);
8290 case PROCESSOR_HYPERSPARC:
8291 case PROCESSOR_SPARCLITE86X:
8293 *total = COSTS_N_INSNS (1);
8298 /* ??? Maybe mark integer compares as zero cost on
8299 ??? all UltraSPARC processors because the result
8300 ??? can be bypassed to a branch in the same group. */
8302 *total = COSTS_N_INSNS (1);
8306 if (FLOAT_MODE_P (GET_MODE (x)))
8310 case PROCESSOR_ULTRASPARC:
8311 case PROCESSOR_ULTRASPARC3:
8312 *total = COSTS_N_INSNS (4);
8315 case PROCESSOR_SUPERSPARC:
8316 *total = COSTS_N_INSNS (3);
8319 case PROCESSOR_CYPRESS:
8320 *total = COSTS_N_INSNS (7);
8323 case PROCESSOR_HYPERSPARC:
8324 case PROCESSOR_SPARCLITE86X:
8325 *total = COSTS_N_INSNS (1);
8329 *total = COSTS_N_INSNS (5);
8334 /* The latency is actually variable for Ultra-I/II
8335 And if one of the inputs have a known constant
8336 value, we could calculate this precisely.
8338 However, for that to be useful we would need to
8339 add some machine description changes which would
8340 make sure small constants ended up in rs1 of the
8341 multiply instruction. This is because the multiply
8342 latency is determined by the number of clear (or
8343 set if the value is negative) bits starting from
8344 the most significant bit of the first input.
8346 The algorithm for computing num_cycles of a multiply
8350 highest_bit = highest_clear_bit(rs1);
8352 highest_bit = highest_set_bit(rs1);
8355 num_cycles = 4 + ((highest_bit - 3) / 2);
8357 If we did that we would have to also consider register
8358 allocation issues that would result from forcing such
8359 a value into a register.
8361 There are other similar tricks we could play if we
8362 knew, for example, that one input was an array index.
8364 Since we do not play any such tricks currently the
8365 safest thing to do is report the worst case latency. */
8366 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8368 *total = (GET_MODE (x) == DImode
8369 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8373 /* Multiply latency on Ultra-III, fortunately, is constant. */
8374 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8376 *total = COSTS_N_INSNS (6);
8380 if (sparc_cpu == PROCESSOR_HYPERSPARC
8381 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8383 *total = COSTS_N_INSNS (17);
8387 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
8394 if (FLOAT_MODE_P (GET_MODE (x)))
8398 case PROCESSOR_ULTRASPARC:
8399 if (GET_MODE (x) == SFmode)
8400 *total = COSTS_N_INSNS (13);
8402 *total = COSTS_N_INSNS (23);
8405 case PROCESSOR_ULTRASPARC3:
8406 if (GET_MODE (x) == SFmode)
8407 *total = COSTS_N_INSNS (17);
8409 *total = COSTS_N_INSNS (20);
8412 case PROCESSOR_SUPERSPARC:
8413 if (GET_MODE (x) == SFmode)
8414 *total = COSTS_N_INSNS (6);
8416 *total = COSTS_N_INSNS (9);
8419 case PROCESSOR_HYPERSPARC:
8420 case PROCESSOR_SPARCLITE86X:
8421 if (GET_MODE (x) == SFmode)
8422 *total = COSTS_N_INSNS (8);
8424 *total = COSTS_N_INSNS (12);
8428 *total = COSTS_N_INSNS (7);
8433 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8434 *total = (GET_MODE (x) == DImode
8435 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8436 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8437 *total = (GET_MODE (x) == DImode
8438 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8440 *total = COSTS_N_INSNS (25);
8444 /* Conditional moves. */
8447 case PROCESSOR_ULTRASPARC:
8448 *total = COSTS_N_INSNS (2);
8451 case PROCESSOR_ULTRASPARC3:
8452 if (FLOAT_MODE_P (GET_MODE (x)))
8453 *total = COSTS_N_INSNS (3);
8455 *total = COSTS_N_INSNS (2);
8459 *total = COSTS_N_INSNS (1);
8464 /* If outer-code is SIGN/ZERO extension we have to subtract
8465 out COSTS_N_INSNS (1) from whatever we return in determining
8469 case PROCESSOR_ULTRASPARC:
8470 if (outer_code == ZERO_EXTEND)
8471 *total = COSTS_N_INSNS (1);
8473 *total = COSTS_N_INSNS (2);
8476 case PROCESSOR_ULTRASPARC3:
8477 if (outer_code == ZERO_EXTEND)
8479 if (GET_MODE (x) == QImode
8480 || GET_MODE (x) == HImode
8481 || outer_code == SIGN_EXTEND)
8482 *total = COSTS_N_INSNS (2);
8484 *total = COSTS_N_INSNS (1);
8488 /* This handles sign extension (3 cycles)
8489 and everything else (2 cycles). */
8490 *total = COSTS_N_INSNS (2);
8494 case PROCESSOR_SUPERSPARC:
8495 if (FLOAT_MODE_P (GET_MODE (x))
8496 || outer_code == ZERO_EXTEND
8497 || outer_code == SIGN_EXTEND)
8498 *total = COSTS_N_INSNS (0);
8500 *total = COSTS_N_INSNS (1);
8503 case PROCESSOR_TSC701:
8504 if (outer_code == ZERO_EXTEND
8505 || outer_code == SIGN_EXTEND)
8506 *total = COSTS_N_INSNS (2);
8508 *total = COSTS_N_INSNS (3);
8511 case PROCESSOR_CYPRESS:
8512 if (outer_code == ZERO_EXTEND
8513 || outer_code == SIGN_EXTEND)
8514 *total = COSTS_N_INSNS (1);
8516 *total = COSTS_N_INSNS (2);
8519 case PROCESSOR_HYPERSPARC:
8520 case PROCESSOR_SPARCLITE86X:
8522 if (outer_code == ZERO_EXTEND
8523 || outer_code == SIGN_EXTEND)
8524 *total = COSTS_N_INSNS (0);
8526 *total = COSTS_N_INSNS (1);
8531 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8549 if (GET_MODE (x) == DImode
8550 && ((XINT (x, 3) == 0
8551 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8552 || (XINT (x, 3) == -1
8554 && XINT (x, 2) >= -0x1000)))
8565 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8566 Used for C++ multiple inheritance. */
8569 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8570 HOST_WIDE_INT delta,
8571 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8574 rtx this, insn, funexp, delta_rtx, tmp;
8576 reload_completed = 1;
8577 epilogue_completed = 1;
8579 current_function_uses_only_leaf_regs = 1;
8581 emit_note (NOTE_INSN_PROLOGUE_END);
8583 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8584 returns a structure, the structure return pointer is there instead. */
8585 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8586 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
8588 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
8590 /* Add DELTA. When possible use a plain add, otherwise load it into
8591 a register first. */
8592 delta_rtx = GEN_INT (delta);
8593 if (!SPARC_SIMM13_P (delta))
8595 rtx scratch = gen_rtx_REG (Pmode, 1);
8597 if (input_operand (delta_rtx, GET_MODE (scratch)))
8598 emit_insn (gen_rtx_SET (VOIDmode, scratch, delta_rtx));
8602 sparc_emit_set_const64 (scratch, delta_rtx);
8604 sparc_emit_set_const32 (scratch, delta_rtx);
8607 delta_rtx = scratch;
8610 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
8611 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
8613 /* Generate a tail call to the target function. */
8614 if (! TREE_USED (function))
8616 assemble_external (function);
8617 TREE_USED (function) = 1;
8619 funexp = XEXP (DECL_RTL (function), 0);
8620 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8621 insn = emit_call_insn (gen_sibcall (funexp));
8622 SIBLING_CALL_P (insn) = 1;
8625 /* Run just enough of rest_of_compilation to get the insns emitted.
8626 There's not really enough bulk here to make other passes such as
8627 instruction scheduling worth while. Note that use_thunk calls
8628 assemble_start_function and assemble_end_function. */
8629 insn = get_insns ();
8630 insn_locators_initialize ();
8631 shorten_branches (insn);
8632 final_start_function (insn, file, 1);
8633 final (insn, file, 1, 0);
8634 final_end_function ();
8636 reload_completed = 0;
8637 epilogue_completed = 0;
8641 /* How to allocate a 'struct machine_function'. */
8643 static struct machine_function *
8644 sparc_init_machine_status (void)
8646 return ggc_alloc_cleared (sizeof (struct machine_function));
8649 /* Locate some local-dynamic symbol still in use by this function
8650 so that we can print its name in local-dynamic base patterns. */
8653 get_some_local_dynamic_name (void)
8657 if (cfun->machine->some_ld_name)
8658 return cfun->machine->some_ld_name;
8660 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8662 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8663 return cfun->machine->some_ld_name;
8669 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8674 && GET_CODE (x) == SYMBOL_REF
8675 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8677 cfun->machine->some_ld_name = XSTR (x, 0);
8684 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
8685 We need to emit DTP-relative relocations. */
8688 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
8693 fputs ("\t.word\t%r_tls_dtpoff32(", file);
8696 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
8701 output_addr_const (file, x);
8705 #include "gt-sparc.h"