1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-flags.h"
36 #include "insn-attr.h"
45 /* 1 if the caller has placed an "unimp" insn immediately after the call.
46 This is used in v8 code when calling a function that returns a structure.
47 v9 doesn't have this. Be careful to have this test be the same as that
50 #define SKIP_CALLERS_UNIMP_P \
51 (!TARGET_ARCH64 && current_function_returns_struct \
52 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
53 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
56 /* Global variables for machine-dependent things. */
58 /* Size of frame. Need to know this to emit return insns from leaf procedures.
59 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
60 reload pass. This is important as the value is later used in insn
61 scheduling (to see what can go in a delay slot).
62 APPARENT_FSIZE is the size of the stack less the register save area and less
63 the outgoing argument area. It is used when saving call preserved regs. */
64 static int apparent_fsize;
65 static int actual_fsize;
67 /* Number of live general or floating point registers needed to be saved
68 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
69 static int num_gfregs;
71 /* Save the operands last given to a compare for use when we
72 generate a scc or bcc insn. */
74 rtx sparc_compare_op0, sparc_compare_op1;
76 /* We may need an epilogue if we spill too many registers.
77 If this is non-zero, then we branch here for the epilogue. */
78 static rtx leaf_label;
82 /* Vector to say how input registers are mapped to output
83 registers. FRAME_POINTER_REGNUM cannot be remapped by
84 this function to eliminate it. You must use -fomit-frame-pointer
86 char leaf_reg_remap[] =
87 { 0, 1, 2, 3, 4, 5, 6, 7,
88 -1, -1, -1, -1, -1, -1, 14, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1,
90 8, 9, 10, 11, 12, 13, -1, 15,
92 32, 33, 34, 35, 36, 37, 38, 39,
93 40, 41, 42, 43, 44, 45, 46, 47,
94 48, 49, 50, 51, 52, 53, 54, 55,
95 56, 57, 58, 59, 60, 61, 62, 63,
96 64, 65, 66, 67, 68, 69, 70, 71,
97 72, 73, 74, 75, 76, 77, 78, 79,
98 80, 81, 82, 83, 84, 85, 86, 87,
99 88, 89, 90, 91, 92, 93, 94, 95,
100 96, 97, 98, 99, 100};
102 /* Vector, indexed by hard register number, which contains 1
103 for a register that is allowable in a candidate for leaf
104 function treatment. */
105 char sparc_leaf_regs[] =
106 { 1, 1, 1, 1, 1, 1, 1, 1,
107 0, 0, 0, 0, 0, 0, 1, 0,
108 0, 0, 0, 0, 0, 0, 0, 0,
109 1, 1, 1, 1, 1, 1, 0, 1,
110 1, 1, 1, 1, 1, 1, 1, 1,
111 1, 1, 1, 1, 1, 1, 1, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
122 /* Name of where we pretend to think the frame pointer points.
123 Normally, this is "%fp", but if we are in a leaf procedure,
124 this is "%sp+something". We record "something" separately as it may be
125 too big for reg+constant addressing. */
127 static const char *frame_base_name;
128 static int frame_base_offset;
130 static void sparc_init_modes PARAMS ((void));
131 static int save_regs PARAMS ((FILE *, int, int, const char *,
133 static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int));
134 static void build_big_number PARAMS ((FILE *, int, const char *));
135 static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *,
136 enum machine_mode, tree, int, int,
139 static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
140 static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
141 static int ultrasparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
143 static void sparc_output_addr_vec PARAMS ((rtx));
144 static void sparc_output_addr_diff_vec PARAMS ((rtx));
145 static void sparc_output_deferred_case_vectors PARAMS ((void));
146 static void sparc_add_gc_roots PARAMS ((void));
147 static void mark_ultrasparc_pipeline_state PARAMS ((void *));
148 static int check_return_regs PARAMS ((rtx));
149 static int epilogue_renumber PARAMS ((rtx *, int));
150 static int ultra_cmove_results_ready_p PARAMS ((rtx));
151 static int ultra_fpmode_conflict_exists PARAMS ((enum machine_mode));
152 static rtx *ultra_find_type PARAMS ((int, rtx *, int));
153 static void ultra_build_types_avail PARAMS ((rtx *, int));
154 static void ultra_flush_pipeline PARAMS ((void));
155 static void ultra_rescan_pipeline_state PARAMS ((rtx *, int));
156 static int set_extends PARAMS ((rtx));
157 static void output_restore_regs PARAMS ((FILE *, int));
159 /* Option handling. */
161 /* Code model option as passed by user. */
162 const char *sparc_cmodel_string;
164 enum cmodel sparc_cmodel;
166 char sparc_hard_reg_printed[8];
168 struct sparc_cpu_select sparc_select[] =
170 /* switch name, tune arch */
171 { (char *)0, "default", 1, 1 },
172 { (char *)0, "-mcpu=", 1, 1 },
173 { (char *)0, "-mtune=", 1, 0 },
177 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
178 enum processor_type sparc_cpu;
180 /* Validate and override various options, and do some machine dependent
184 sparc_override_options ()
186 static struct code_model {
191 { "medlow", CM_MEDLOW },
192 { "medmid", CM_MEDMID },
193 { "medany", CM_MEDANY },
194 { "embmedany", CM_EMBMEDANY },
197 struct code_model *cmodel;
198 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
199 static struct cpu_default {
203 /* There must be one entry here for each TARGET_CPU value. */
204 { TARGET_CPU_sparc, "cypress" },
205 { TARGET_CPU_sparclet, "tsc701" },
206 { TARGET_CPU_sparclite, "f930" },
207 { TARGET_CPU_v8, "v8" },
208 { TARGET_CPU_hypersparc, "hypersparc" },
209 { TARGET_CPU_sparclite86x, "sparclite86x" },
210 { TARGET_CPU_supersparc, "supersparc" },
211 { TARGET_CPU_v9, "v9" },
212 { TARGET_CPU_ultrasparc, "ultrasparc" },
215 struct cpu_default *def;
216 /* Table of values for -m{cpu,tune}=. */
217 static struct cpu_table {
219 enum processor_type processor;
223 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
224 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
225 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
226 /* TI TMS390Z55 supersparc */
227 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
228 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
229 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
230 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
231 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
232 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
233 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
234 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
236 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
238 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
239 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
240 /* TI ultrasparc I, II, IIi */
241 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
242 /* Although insns using %y are deprecated, it is a clear win on current
244 |MASK_DEPRECATED_V8_INSNS},
247 struct cpu_table *cpu;
248 struct sparc_cpu_select *sel;
251 #ifndef SPARC_BI_ARCH
252 /* Check for unsupported architecture size. */
253 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
254 error ("%s is not supported by this configuration",
255 DEFAULT_ARCH32_P ? "-m64" : "-m32");
258 /* We force all 64bit archs to use 128 bit long double */
259 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
261 error ("-mlong-double-64 not allowed with -m64");
262 target_flags |= MASK_LONG_DOUBLE_128;
265 /* Code model selection. */
266 sparc_cmodel = SPARC_DEFAULT_CMODEL;
270 sparc_cmodel = CM_32;
273 if (sparc_cmodel_string != NULL)
277 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
278 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
280 if (cmodel->name == NULL)
281 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
283 sparc_cmodel = cmodel->value;
286 error ("-mcmodel= is not supported on 32 bit systems");
289 fpu = TARGET_FPU; /* save current -mfpu status */
291 /* Set the default CPU. */
292 for (def = &cpu_default[0]; def->name; ++def)
293 if (def->cpu == TARGET_CPU_DEFAULT)
297 sparc_select[0].string = def->name;
299 for (sel = &sparc_select[0]; sel->name; ++sel)
303 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
304 if (! strcmp (sel->string, cpu->name))
307 sparc_cpu = cpu->processor;
311 target_flags &= ~cpu->disable;
312 target_flags |= cpu->enable;
318 error ("bad value (%s) for %s switch", sel->string, sel->name);
322 /* If -mfpu or -mno-fpu was explicitly used, don't override with
323 the processor default. Clear MASK_FPU_SET to avoid confusing
324 the reverse mapping from switch values to names. */
327 target_flags = (target_flags & ~MASK_FPU) | fpu;
328 target_flags &= ~MASK_FPU_SET;
331 /* Don't allow -mvis if FPU is disabled. */
333 target_flags &= ~MASK_VIS;
335 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
337 -m64 also implies v9. */
338 if (TARGET_VIS || TARGET_ARCH64)
339 target_flags |= MASK_V9;
341 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
342 if (TARGET_V9 && TARGET_ARCH32)
343 target_flags |= MASK_DEPRECATED_V8_INSNS;
345 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
346 if (! TARGET_V9 || TARGET_ARCH64)
347 target_flags &= ~MASK_V8PLUS;
349 /* Don't use stack biasing in 32 bit mode. */
351 target_flags &= ~MASK_STACK_BIAS;
353 /* Supply a default value for align_functions. */
354 if (align_functions == 0 && sparc_cpu == PROCESSOR_ULTRASPARC)
355 align_functions = 32;
357 /* Validate PCC_STRUCT_RETURN. */
358 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
359 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
361 /* Do various machine dependent initializations. */
364 if ((profile_flag || profile_block_flag)
365 && sparc_cmodel != CM_32 && sparc_cmodel != CM_MEDLOW)
367 error ("profiling does not support code models other than medlow");
370 /* Register global variables with the garbage collector. */
371 sparc_add_gc_roots ();
374 /* Miscellaneous utilities. */
376 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
377 or branch on register contents instructions. */
383 return (code == EQ || code == NE || code == GE || code == LT
384 || code == LE || code == GT);
388 /* Operand constraints. */
390 /* Return non-zero only if OP is a register of mode MODE,
394 reg_or_0_operand (op, mode)
396 enum machine_mode mode;
398 if (register_operand (op, mode))
400 if (op == const0_rtx)
402 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
403 && CONST_DOUBLE_HIGH (op) == 0
404 && CONST_DOUBLE_LOW (op) == 0)
406 if (fp_zero_operand (op, mode))
411 /* Nonzero if OP is a floating point value with value 0.0. */
414 fp_zero_operand (op, mode)
416 enum machine_mode mode;
418 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
420 return op == CONST0_RTX (mode);
423 /* Nonzero if OP is a floating point constant which can
424 be loaded into an integer register using a single
425 sethi instruction. */
431 if (GET_CODE (op) == CONST_DOUBLE)
436 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
437 if (REAL_VALUES_EQUAL (r, dconst0) &&
438 ! REAL_VALUE_MINUS_ZERO (r))
440 REAL_VALUE_TO_TARGET_SINGLE (r, i);
441 if (SPARC_SETHI_P (i))
448 /* Nonzero if OP is a floating point constant which can
449 be loaded into an integer register using a single
456 if (GET_CODE (op) == CONST_DOUBLE)
461 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
462 if (REAL_VALUES_EQUAL (r, dconst0) &&
463 ! REAL_VALUE_MINUS_ZERO (r))
465 REAL_VALUE_TO_TARGET_SINGLE (r, i);
466 if (SPARC_SIMM13_P (i))
473 /* Nonzero if OP is a floating point constant which can
474 be loaded into an integer register using a high/losum
475 instruction sequence. */
481 /* The constraints calling this should only be in
482 SFmode move insns, so any constant which cannot
483 be moved using a single insn will do. */
484 if (GET_CODE (op) == CONST_DOUBLE)
489 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
490 if (REAL_VALUES_EQUAL (r, dconst0) &&
491 ! REAL_VALUE_MINUS_ZERO (r))
493 REAL_VALUE_TO_TARGET_SINGLE (r, i);
494 if (! SPARC_SETHI_P (i)
495 && ! SPARC_SIMM13_P (i))
502 /* Nonzero if OP is an integer register. */
505 intreg_operand (op, mode)
507 enum machine_mode mode ATTRIBUTE_UNUSED;
509 return (register_operand (op, SImode)
510 || (TARGET_ARCH64 && register_operand (op, DImode)));
513 /* Nonzero if OP is a floating point condition code register. */
516 fcc_reg_operand (op, mode)
518 enum machine_mode mode;
520 /* This can happen when recog is called from combine. Op may be a MEM.
521 Fail instead of calling abort in this case. */
522 if (GET_CODE (op) != REG)
525 if (mode != VOIDmode && mode != GET_MODE (op))
528 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
531 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
532 if (reg_renumber == 0)
533 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
534 return REGNO_OK_FOR_CCFP_P (REGNO (op));
536 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
540 /* Nonzero if OP is an integer or floating point condition code register. */
543 icc_or_fcc_reg_operand (op, mode)
545 enum machine_mode mode;
547 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
549 if (mode != VOIDmode && mode != GET_MODE (op))
552 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
557 return fcc_reg_operand (op, mode);
560 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
562 restore_operand (op, mode)
564 enum machine_mode mode;
566 return (GET_CODE (op) == REG && GET_MODE (op) == mode
567 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
570 /* Call insn on SPARC can take a PC-relative constant address, or any regular
574 call_operand (op, mode)
576 enum machine_mode mode;
578 if (GET_CODE (op) != MEM)
581 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
585 call_operand_address (op, mode)
587 enum machine_mode mode;
589 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
592 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
593 reference and a constant. */
596 symbolic_operand (op, mode)
598 enum machine_mode mode;
600 enum machine_mode omode = GET_MODE (op);
602 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
605 switch (GET_CODE (op))
613 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
614 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
615 && GET_CODE (XEXP (op, 1)) == CONST_INT);
622 /* Return truth value of statement that OP is a symbolic memory
623 operand of mode MODE. */
626 symbolic_memory_operand (op, mode)
628 enum machine_mode mode ATTRIBUTE_UNUSED;
630 if (GET_CODE (op) == SUBREG)
631 op = SUBREG_REG (op);
632 if (GET_CODE (op) != MEM)
635 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
636 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
639 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
642 label_ref_operand (op, mode)
644 enum machine_mode mode;
646 if (GET_CODE (op) != LABEL_REF)
648 if (GET_MODE (op) != mode)
653 /* Return 1 if the operand is an argument used in generating pic references
654 in either the medium/low or medium/anywhere code models of sparc64. */
657 sp64_medium_pic_operand (op, mode)
659 enum machine_mode mode ATTRIBUTE_UNUSED;
661 /* Check for (const (minus (symbol_ref:GOT)
662 (const (minus (label) (pc))))). */
663 if (GET_CODE (op) != CONST)
666 if (GET_CODE (op) != MINUS)
668 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
670 /* ??? Ensure symbol is GOT. */
671 if (GET_CODE (XEXP (op, 1)) != CONST)
673 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
678 /* Return 1 if the operand is a data segment reference. This includes
679 the readonly data segment, or in other words anything but the text segment.
680 This is needed in the medium/anywhere code model on v9. These values
681 are accessed with EMBMEDANY_BASE_REG. */
684 data_segment_operand (op, mode)
686 enum machine_mode mode ATTRIBUTE_UNUSED;
688 switch (GET_CODE (op))
691 return ! SYMBOL_REF_FLAG (op);
693 /* Assume canonical format of symbol + constant.
696 return data_segment_operand (XEXP (op, 0), VOIDmode);
702 /* Return 1 if the operand is a text segment reference.
703 This is needed in the medium/anywhere code model on v9. */
706 text_segment_operand (op, mode)
708 enum machine_mode mode ATTRIBUTE_UNUSED;
710 switch (GET_CODE (op))
715 return SYMBOL_REF_FLAG (op);
717 /* Assume canonical format of symbol + constant.
720 return text_segment_operand (XEXP (op, 0), VOIDmode);
726 /* Return 1 if the operand is either a register or a memory operand that is
730 reg_or_nonsymb_mem_operand (op, mode)
732 enum machine_mode mode;
734 if (register_operand (op, mode))
737 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
744 splittable_symbolic_memory_operand (op, mode)
746 enum machine_mode mode ATTRIBUTE_UNUSED;
748 if (GET_CODE (op) != MEM)
750 if (! symbolic_operand (XEXP (op, 0), Pmode))
756 splittable_immediate_memory_operand (op, mode)
758 enum machine_mode mode ATTRIBUTE_UNUSED;
760 if (GET_CODE (op) != MEM)
762 if (! immediate_operand (XEXP (op, 0), Pmode))
767 /* Return truth value of whether OP is EQ or NE. */
772 enum machine_mode mode ATTRIBUTE_UNUSED;
774 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
777 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
778 or LTU for non-floating-point. We handle those specially. */
781 normal_comp_operator (op, mode)
783 enum machine_mode mode ATTRIBUTE_UNUSED;
785 enum rtx_code code = GET_CODE (op);
787 if (GET_RTX_CLASS (code) != '<')
790 if (GET_MODE (XEXP (op, 0)) == CCFPmode
791 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
794 return (code != NE && code != EQ && code != GEU && code != LTU);
797 /* Return 1 if this is a comparison operator. This allows the use of
798 MATCH_OPERATOR to recognize all the branch insns. */
801 noov_compare_op (op, mode)
803 enum machine_mode mode ATTRIBUTE_UNUSED;
805 enum rtx_code code = GET_CODE (op);
807 if (GET_RTX_CLASS (code) != '<')
810 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
811 /* These are the only branches which work with CC_NOOVmode. */
812 return (code == EQ || code == NE || code == GE || code == LT);
816 /* Nonzero if OP is a comparison operator suitable for use in v9
817 conditional move or branch on register contents instructions. */
820 v9_regcmp_op (op, mode)
822 enum machine_mode mode ATTRIBUTE_UNUSED;
824 enum rtx_code code = GET_CODE (op);
826 if (GET_RTX_CLASS (code) != '<')
829 return v9_regcmp_p (code);
832 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
837 enum machine_mode mode ATTRIBUTE_UNUSED;
839 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
842 /* Return nonzero if OP is an operator of mode MODE which can set
843 the condition codes explicitly. We do not include PLUS and MINUS
844 because these require CC_NOOVmode, which we handle explicitly. */
847 cc_arithop (op, mode)
849 enum machine_mode mode ATTRIBUTE_UNUSED;
851 if (GET_CODE (op) == AND
852 || GET_CODE (op) == IOR
853 || GET_CODE (op) == XOR)
859 /* Return nonzero if OP is an operator of mode MODE which can bitwise
860 complement its second operand and set the condition codes explicitly. */
863 cc_arithopn (op, mode)
865 enum machine_mode mode ATTRIBUTE_UNUSED;
867 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
868 and (xor ... (not ...)) to (not (xor ...)). */
869 return (GET_CODE (op) == AND
870 || GET_CODE (op) == IOR);
873 /* Return true if OP is a register, or is a CONST_INT that can fit in a
874 signed 13 bit immediate field. This is an acceptable SImode operand for
875 most 3 address instructions. */
878 arith_operand (op, mode)
880 enum machine_mode mode;
883 if (register_operand (op, mode))
885 if (GET_CODE (op) != CONST_INT)
887 val = INTVAL (op) & 0xffffffff;
888 return SPARC_SIMM13_P (val);
891 /* Return true if OP is a constant 4096 */
894 arith_4096_operand (op, mode)
896 enum machine_mode mode ATTRIBUTE_UNUSED;
899 if (GET_CODE (op) != CONST_INT)
901 val = INTVAL (op) & 0xffffffff;
905 /* Return true if OP is suitable as second operand for add/sub */
908 arith_add_operand (op, mode)
910 enum machine_mode mode;
912 return arith_operand (op, mode) || arith_4096_operand (op, mode);
915 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
916 immediate field of OR and XOR instructions. Used for 64-bit
917 constant formation patterns. */
919 const64_operand (op, mode)
921 enum machine_mode mode ATTRIBUTE_UNUSED;
923 return ((GET_CODE (op) == CONST_INT
924 && SPARC_SIMM13_P (INTVAL (op)))
925 #if HOST_BITS_PER_WIDE_INT != 64
926 || (GET_CODE (op) == CONST_DOUBLE
927 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
928 && (CONST_DOUBLE_HIGH (op) ==
929 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
930 (HOST_WIDE_INT)0xffffffff : 0)))
935 /* The same, but only for sethi instructions. */
937 const64_high_operand (op, mode)
939 enum machine_mode mode ATTRIBUTE_UNUSED;
941 return ((GET_CODE (op) == CONST_INT
942 && (INTVAL (op) & 0xfffffc00) != 0
943 && SPARC_SETHI_P (INTVAL (op))
944 #if HOST_BITS_PER_WIDE_INT != 64
945 /* Must be positive on non-64bit host else the
946 optimizer is fooled into thinking that sethi
947 sign extends, even though it does not. */
951 || (GET_CODE (op) == CONST_DOUBLE
952 && CONST_DOUBLE_HIGH (op) == 0
953 && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
954 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
957 /* Return true if OP is a register, or is a CONST_INT that can fit in a
958 signed 11 bit immediate field. This is an acceptable SImode operand for
959 the movcc instructions. */
962 arith11_operand (op, mode)
964 enum machine_mode mode;
966 return (register_operand (op, mode)
967 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
970 /* Return true if OP is a register, or is a CONST_INT that can fit in a
971 signed 10 bit immediate field. This is an acceptable SImode operand for
972 the movrcc instructions. */
975 arith10_operand (op, mode)
977 enum machine_mode mode;
979 return (register_operand (op, mode)
980 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
983 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
984 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
986 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
987 can fit in a 13 bit immediate field. This is an acceptable DImode operand
988 for most 3 address instructions. */
991 arith_double_operand (op, mode)
993 enum machine_mode mode;
995 return (register_operand (op, mode)
996 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
998 && GET_CODE (op) == CONST_DOUBLE
999 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1000 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1002 && GET_CODE (op) == CONST_DOUBLE
1003 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1004 && ((CONST_DOUBLE_HIGH (op) == -1
1005 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1006 || (CONST_DOUBLE_HIGH (op) == 0
1007 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1010 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1013 arith_double_4096_operand (op, mode)
1015 enum machine_mode mode ATTRIBUTE_UNUSED;
1017 return (TARGET_ARCH64 &&
1018 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1019 (GET_CODE (op) == CONST_DOUBLE &&
1020 CONST_DOUBLE_LOW (op) == 4096 &&
1021 CONST_DOUBLE_HIGH (op) == 0)));
1024 /* Return true if OP is suitable as second operand for add/sub in DImode */
1027 arith_double_add_operand (op, mode)
1029 enum machine_mode mode;
1031 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1034 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1035 can fit in an 11 bit immediate field. This is an acceptable DImode
1036 operand for the movcc instructions. */
1037 /* ??? Replace with arith11_operand? */
1040 arith11_double_operand (op, mode)
1042 enum machine_mode mode;
1044 return (register_operand (op, mode)
1045 || (GET_CODE (op) == CONST_DOUBLE
1046 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1047 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1048 && ((CONST_DOUBLE_HIGH (op) == -1
1049 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1050 || (CONST_DOUBLE_HIGH (op) == 0
1051 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1052 || (GET_CODE (op) == CONST_INT
1053 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1054 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1057 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1058 can fit in an 10 bit immediate field. This is an acceptable DImode
1059 operand for the movrcc instructions. */
1060 /* ??? Replace with arith10_operand? */
1063 arith10_double_operand (op, mode)
1065 enum machine_mode mode;
1067 return (register_operand (op, mode)
1068 || (GET_CODE (op) == CONST_DOUBLE
1069 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1070 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1071 && ((CONST_DOUBLE_HIGH (op) == -1
1072 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1073 || (CONST_DOUBLE_HIGH (op) == 0
1074 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1075 || (GET_CODE (op) == CONST_INT
1076 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1077 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1080 /* Return truth value of whether OP is a integer which fits the
1081 range constraining immediate operands in most three-address insns,
1082 which have a 13 bit immediate field. */
1085 small_int (op, mode)
1087 enum machine_mode mode ATTRIBUTE_UNUSED;
1089 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1093 small_int_or_double (op, mode)
1095 enum machine_mode mode ATTRIBUTE_UNUSED;
1097 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1098 || (GET_CODE (op) == CONST_DOUBLE
1099 && CONST_DOUBLE_HIGH (op) == 0
1100 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1103 /* Recognize operand values for the umul instruction. That instruction sign
1104 extends immediate values just like all other sparc instructions, but
1105 interprets the extended result as an unsigned number. */
1108 uns_small_int (op, mode)
1110 enum machine_mode mode ATTRIBUTE_UNUSED;
1112 #if HOST_BITS_PER_WIDE_INT > 32
1113 /* All allowed constants will fit a CONST_INT. */
1114 return (GET_CODE (op) == CONST_INT
1115 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1116 || (INTVAL (op) >= 0xFFFFF000
1117 && INTVAL (op) < 0x100000000)));
1119 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1120 || (GET_CODE (op) == CONST_DOUBLE
1121 && CONST_DOUBLE_HIGH (op) == 0
1122 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1127 uns_arith_operand (op, mode)
1129 enum machine_mode mode;
1131 return register_operand (op, mode) || uns_small_int (op, mode);
1134 /* Return truth value of statement that OP is a call-clobbered register. */
1136 clobbered_register (op, mode)
1138 enum machine_mode mode ATTRIBUTE_UNUSED;
1140 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1143 /* Return 1 if OP is a valid operand for the source of a move insn. */
1146 input_operand (op, mode)
1148 enum machine_mode mode;
1150 /* If both modes are non-void they must be the same. */
1151 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1154 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1155 if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX)
1158 /* Allow any one instruction integer constant, and all CONST_INT
1159 variants when we are working in DImode and !arch64. */
1160 if (GET_MODE_CLASS (mode) == MODE_INT
1161 && ((GET_CODE (op) == CONST_INT
1162 && ((SPARC_SETHI_P (INTVAL (op))
1164 || (INTVAL (op) >= 0)
1168 || SPARC_SIMM13_P (INTVAL (op))
1170 && ! TARGET_ARCH64)))
1172 && GET_CODE (op) == CONST_DOUBLE
1173 && ((CONST_DOUBLE_HIGH (op) == 0
1174 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1176 #if HOST_BITS_PER_WIDE_INT == 64
1177 (CONST_DOUBLE_HIGH (op) == 0
1178 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1180 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1181 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1182 && CONST_DOUBLE_HIGH (op) == 0)
1183 || (CONST_DOUBLE_HIGH (op) == -1
1184 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1189 /* If !arch64 and this is a DImode const, allow it so that
1190 the splits can be generated. */
1193 && GET_CODE (op) == CONST_DOUBLE)
1196 if (register_operand (op, mode))
1199 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1200 && GET_CODE (op) == CONST_DOUBLE)
1203 /* If this is a SUBREG, look inside so that we handle
1204 paradoxical ones. */
1205 if (GET_CODE (op) == SUBREG)
1206 op = SUBREG_REG (op);
1208 /* Check for valid MEM forms. */
1209 if (GET_CODE (op) == MEM)
1211 rtx inside = XEXP (op, 0);
1213 if (GET_CODE (inside) == LO_SUM)
1215 /* We can't allow these because all of the splits
1216 (eventually as they trickle down into DFmode
1217 splits) require offsettable memory references. */
1219 && GET_MODE (op) == TFmode)
1222 return (register_operand (XEXP (inside, 0), Pmode)
1223 && CONSTANT_P (XEXP (inside, 1)));
1225 return memory_address_p (mode, inside);
1232 /* We know it can't be done in one insn when we get here,
1233 the movsi expander guarentees this. */
1235 sparc_emit_set_const32 (op0, op1)
1239 enum machine_mode mode = GET_MODE (op0);
1242 if (GET_CODE (op1) == CONST_INT)
1244 HOST_WIDE_INT value = INTVAL (op1);
1246 if (SPARC_SETHI_P (value)
1247 || SPARC_SIMM13_P (value))
1251 /* Full 2-insn decomposition is needed. */
1252 if (reload_in_progress || reload_completed)
1255 temp = gen_reg_rtx (mode);
1257 if (GET_CODE (op1) == CONST_INT)
1259 /* Emit them as real moves instead of a HIGH/LO_SUM,
1260 this way CSE can see everything and reuse intermediate
1261 values if it wants. */
1263 && HOST_BITS_PER_WIDE_INT != 64
1264 && (INTVAL (op1) & 0x80000000) != 0)
1266 emit_insn (gen_rtx_SET (VOIDmode,
1268 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx,
1269 INTVAL (op1) & 0xfffffc00, 0)));
1273 emit_insn (gen_rtx_SET (VOIDmode,
1275 GEN_INT (INTVAL (op1) & 0xfffffc00)));
1277 emit_insn (gen_rtx_SET (VOIDmode,
1281 GEN_INT (INTVAL (op1) & 0x3ff))));
1285 /* A symbol, emit in the traditional way. */
1286 emit_insn (gen_rtx_SET (VOIDmode,
1290 emit_insn (gen_rtx_SET (VOIDmode,
1292 gen_rtx_LO_SUM (mode,
1300 /* Sparc-v9 code-model support. */
1302 sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1307 switch (sparc_cmodel)
1310 /* The range spanned by all instructions in the object is less
1311 than 2^31 bytes (2GB) and the distance from any instruction
1312 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1313 than 2^31 bytes (2GB).
1315 The executable must be in the low 4TB of the virtual address
1318 sethi %hi(symbol), %temp
1319 or %temp, %lo(symbol), %reg */
1320 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1321 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1325 /* The range spanned by all instructions in the object is less
1326 than 2^31 bytes (2GB) and the distance from any instruction
1327 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1328 than 2^31 bytes (2GB).
1330 The executable must be in the low 16TB of the virtual address
1333 sethi %h44(symbol), %temp1
1334 or %temp1, %m44(symbol), %temp2
1335 sllx %temp2, 12, %temp3
1336 or %temp3, %l44(symbol), %reg */
1337 emit_insn (gen_seth44 (op0, op1));
1338 emit_insn (gen_setm44 (op0, op0, op1));
1339 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1340 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1341 emit_insn (gen_setl44 (op0, temp1, op1));
1345 /* The range spanned by all instructions in the object is less
1346 than 2^31 bytes (2GB) and the distance from any instruction
1347 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1348 than 2^31 bytes (2GB).
1350 The executable can be placed anywhere in the virtual address
1353 sethi %hh(symbol), %temp1
1354 sethi %lm(symbol), %temp2
1355 or %temp1, %hm(symbol), %temp3
1356 or %temp2, %lo(symbol), %temp4
1357 sllx %temp3, 32, %temp5
1358 or %temp4, %temp5, %reg */
1360 /* Getting this right wrt. reloading is really tricky.
1361 We _MUST_ have a separate temporary at this point,
1362 if we don't barf immediately instead of generating
1367 emit_insn (gen_sethh (op0, op1));
1368 emit_insn (gen_setlm (temp1, op1));
1369 emit_insn (gen_sethm (op0, op0, op1));
1370 emit_insn (gen_rtx_SET (VOIDmode, op0,
1371 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1372 emit_insn (gen_rtx_SET (VOIDmode, op0,
1373 gen_rtx_PLUS (DImode, op0, temp1)));
1374 emit_insn (gen_setlo (op0, op0, op1));
1378 /* Old old old backwards compatibility kruft here.
1379 Essentially it is MEDLOW with a fixed 64-bit
1380 virtual base added to all data segment addresses.
1381 Text-segment stuff is computed like MEDANY, we can't
1382 reuse the code above because the relocation knobs
1385 Data segment: sethi %hi(symbol), %temp1
1386 or %temp1, %lo(symbol), %temp2
1387 add %temp2, EMBMEDANY_BASE_REG, %reg
1389 Text segment: sethi %uhi(symbol), %temp1
1390 sethi %hi(symbol), %temp2
1391 or %temp1, %ulo(symbol), %temp3
1392 or %temp2, %lo(symbol), %temp4
1393 sllx %temp3, 32, %temp5
1394 or %temp4, %temp5, %reg */
1395 if (data_segment_operand (op1, GET_MODE (op1)))
1397 emit_insn (gen_embmedany_sethi (temp1, op1));
1398 emit_insn (gen_embmedany_brsum (op0, temp1));
1399 emit_insn (gen_embmedany_losum (op0, op0, op1));
1403 /* Getting this right wrt. reloading is really tricky.
1404 We _MUST_ have a separate temporary at this point,
1405 so we barf immediately instead of generating
1410 emit_insn (gen_embmedany_textuhi (op0, op1));
1411 emit_insn (gen_embmedany_texthi (temp1, op1));
1412 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1413 emit_insn (gen_rtx_SET (VOIDmode, op0,
1414 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1415 emit_insn (gen_rtx_SET (VOIDmode, op0,
1416 gen_rtx_PLUS (DImode, op0, temp1)));
1417 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1426 /* These avoid problems when cross compiling. If we do not
1427 go through all this hair then the optimizer will see
1428 invalid REG_EQUAL notes or in some cases none at all. */
1429 static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT));
1430 static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT));
1431 static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT));
1432 static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
1434 #if HOST_BITS_PER_WIDE_INT == 64
1435 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
1436 #define GEN_INT64(__x) GEN_INT (__x)
1438 #define GEN_HIGHINT64(__x) \
1439 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1440 (__x) & 0xfffffc00, 0)
1441 #define GEN_INT64(__x) \
1442 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1443 (__x) & 0xffffffff, \
1444 ((__x) & 0x80000000 \
1448 /* The optimizer is not to assume anything about exactly
1449 which bits are set for a HIGH, they are unspecified.
1450 Unfortunately this leads to many missed optimizations
1451 during CSE. We mask out the non-HIGH bits, and matches
1452 a plain movdi, to alleviate this problem. */
1454 sparc_emit_set_safe_HIGH64 (dest, val)
1458 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1462 gen_safe_SET64 (dest, val)
1466 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1470 gen_safe_OR64 (src, val)
1474 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1478 gen_safe_XOR64 (src, val)
1482 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1485 /* Worker routines for 64-bit constant formation on arch64.
1486 One of the key things to be doing in these emissions is
1487 to create as many temp REGs as possible. This makes it
1488 possible for half-built constants to be used later when
1489 such values are similar to something required later on.
1490 Without doing this, the optimizer cannot see such
1493 static void sparc_emit_set_const64_quick1
1494 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int));
1497 sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1500 unsigned HOST_WIDE_INT low_bits;
1503 unsigned HOST_WIDE_INT high_bits;
1506 high_bits = (~low_bits) & 0xffffffff;
1508 high_bits = low_bits;
1510 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1513 emit_insn (gen_rtx_SET (VOIDmode, op0,
1514 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1518 /* If we are XOR'ing with -1, then we should emit a one's complement
1519 instead. This way the combiner will notice logical operations
1520 such as ANDN later on and substitute. */
1521 if ((low_bits & 0x3ff) == 0x3ff)
1523 emit_insn (gen_rtx_SET (VOIDmode, op0,
1524 gen_rtx_NOT (DImode, temp)));
1528 emit_insn (gen_rtx_SET (VOIDmode, op0,
1529 gen_safe_XOR64 (temp,
1530 (-0x400 | (low_bits & 0x3ff)))));
1535 static void sparc_emit_set_const64_quick2
1536 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT,
1537 unsigned HOST_WIDE_INT, int));
1540 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1543 unsigned HOST_WIDE_INT high_bits;
1544 unsigned HOST_WIDE_INT low_immediate;
1549 if ((high_bits & 0xfffffc00) != 0)
1551 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1552 if ((high_bits & ~0xfffffc00) != 0)
1553 emit_insn (gen_rtx_SET (VOIDmode, op0,
1554 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1560 emit_insn (gen_safe_SET64 (temp, high_bits));
1564 /* Now shift it up into place. */
1565 emit_insn (gen_rtx_SET (VOIDmode, op0,
1566 gen_rtx_ASHIFT (DImode, temp2,
1567 GEN_INT (shift_count))));
1569 /* If there is a low immediate part piece, finish up by
1570 putting that in as well. */
1571 if (low_immediate != 0)
1572 emit_insn (gen_rtx_SET (VOIDmode, op0,
1573 gen_safe_OR64 (op0, low_immediate)));
1576 static void sparc_emit_set_const64_longway
1577 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1579 /* Full 64-bit constant decomposition. Even though this is the
1580 'worst' case, we still optimize a few things away. */
1582 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1585 unsigned HOST_WIDE_INT high_bits;
1586 unsigned HOST_WIDE_INT low_bits;
1590 if (reload_in_progress || reload_completed)
1593 sub_temp = gen_reg_rtx (DImode);
1595 if ((high_bits & 0xfffffc00) != 0)
1597 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1598 if ((high_bits & ~0xfffffc00) != 0)
1599 emit_insn (gen_rtx_SET (VOIDmode,
1601 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1607 emit_insn (gen_safe_SET64 (temp, high_bits));
1611 if (!reload_in_progress && !reload_completed)
1613 rtx temp2 = gen_reg_rtx (DImode);
1614 rtx temp3 = gen_reg_rtx (DImode);
1615 rtx temp4 = gen_reg_rtx (DImode);
1617 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1618 gen_rtx_ASHIFT (DImode, sub_temp,
1621 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1622 if ((low_bits & ~0xfffffc00) != 0)
1624 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1625 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1626 emit_insn (gen_rtx_SET (VOIDmode, op0,
1627 gen_rtx_PLUS (DImode, temp4, temp3)));
1631 emit_insn (gen_rtx_SET (VOIDmode, op0,
1632 gen_rtx_PLUS (DImode, temp4, temp2)));
1637 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1638 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1639 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1642 /* We are in the middle of reload, so this is really
1643 painful. However we do still make an attempt to
1644 avoid emitting truly stupid code. */
1645 if (low1 != const0_rtx)
1647 emit_insn (gen_rtx_SET (VOIDmode, op0,
1648 gen_rtx_ASHIFT (DImode, sub_temp,
1649 GEN_INT (to_shift))));
1650 emit_insn (gen_rtx_SET (VOIDmode, op0,
1651 gen_rtx_IOR (DImode, op0, low1)));
1659 if (low2 != const0_rtx)
1661 emit_insn (gen_rtx_SET (VOIDmode, op0,
1662 gen_rtx_ASHIFT (DImode, sub_temp,
1663 GEN_INT (to_shift))));
1664 emit_insn (gen_rtx_SET (VOIDmode, op0,
1665 gen_rtx_IOR (DImode, op0, low2)));
1673 emit_insn (gen_rtx_SET (VOIDmode, op0,
1674 gen_rtx_ASHIFT (DImode, sub_temp,
1675 GEN_INT (to_shift))));
1676 if (low3 != const0_rtx)
1677 emit_insn (gen_rtx_SET (VOIDmode, op0,
1678 gen_rtx_IOR (DImode, op0, low3)));
1683 /* Analyze a 64-bit constant for certain properties. */
1684 static void analyze_64bit_constant
1685 PARAMS ((unsigned HOST_WIDE_INT,
1686 unsigned HOST_WIDE_INT,
1687 int *, int *, int *));
1690 analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
1691 unsigned HOST_WIDE_INT high_bits, low_bits;
1692 int *hbsp, *lbsp, *abbasp;
1694 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1697 lowest_bit_set = highest_bit_set = -1;
1701 if ((lowest_bit_set == -1)
1702 && ((low_bits >> i) & 1))
1704 if ((highest_bit_set == -1)
1705 && ((high_bits >> (32 - i - 1)) & 1))
1706 highest_bit_set = (64 - i - 1);
1709 && ((highest_bit_set == -1)
1710 || (lowest_bit_set == -1)));
1716 if ((lowest_bit_set == -1)
1717 && ((high_bits >> i) & 1))
1718 lowest_bit_set = i + 32;
1719 if ((highest_bit_set == -1)
1720 && ((low_bits >> (32 - i - 1)) & 1))
1721 highest_bit_set = 32 - i - 1;
1724 && ((highest_bit_set == -1)
1725 || (lowest_bit_set == -1)));
1727 /* If there are no bits set this should have gone out
1728 as one instruction! */
1729 if (lowest_bit_set == -1
1730 || highest_bit_set == -1)
1732 all_bits_between_are_set = 1;
1733 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1737 if ((low_bits & (1 << i)) != 0)
1742 if ((high_bits & (1 << (i - 32))) != 0)
1745 all_bits_between_are_set = 0;
1748 *hbsp = highest_bit_set;
1749 *lbsp = lowest_bit_set;
1750 *abbasp = all_bits_between_are_set;
1753 static int const64_is_2insns
1754 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1757 const64_is_2insns (high_bits, low_bits)
1758 unsigned HOST_WIDE_INT high_bits, low_bits;
1760 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1763 || high_bits == 0xffffffff)
1766 analyze_64bit_constant (high_bits, low_bits,
1767 &highest_bit_set, &lowest_bit_set,
1768 &all_bits_between_are_set);
1770 if ((highest_bit_set == 63
1771 || lowest_bit_set == 0)
1772 && all_bits_between_are_set != 0)
1775 if ((highest_bit_set - lowest_bit_set) < 21)
1781 static unsigned HOST_WIDE_INT create_simple_focus_bits
1782 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
1785 static unsigned HOST_WIDE_INT
1786 create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
1787 unsigned HOST_WIDE_INT high_bits, low_bits;
1788 int lowest_bit_set, shift;
1790 HOST_WIDE_INT hi, lo;
1792 if (lowest_bit_set < 32)
1794 lo = (low_bits >> lowest_bit_set) << shift;
1795 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1800 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1807 /* Here we are sure to be arch64 and this is an integer constant
1808 being loaded into a register. Emit the most efficient
1809 insn sequence possible. Detection of all the 1-insn cases
1810 has been done already. */
1812 sparc_emit_set_const64 (op0, op1)
1816 unsigned HOST_WIDE_INT high_bits, low_bits;
1817 int lowest_bit_set, highest_bit_set;
1818 int all_bits_between_are_set;
1821 /* Sanity check that we know what we are working with. */
1822 if (! TARGET_ARCH64)
1825 if (GET_CODE (op0) != SUBREG)
1827 if (GET_CODE (op0) != REG
1828 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1829 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1833 if (reload_in_progress || reload_completed)
1836 temp = gen_reg_rtx (DImode);
1838 if (GET_CODE (op1) != CONST_DOUBLE
1839 && GET_CODE (op1) != CONST_INT)
1841 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1845 if (GET_CODE (op1) == CONST_DOUBLE)
1847 #if HOST_BITS_PER_WIDE_INT == 64
1848 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1849 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1851 high_bits = CONST_DOUBLE_HIGH (op1);
1852 low_bits = CONST_DOUBLE_LOW (op1);
1857 #if HOST_BITS_PER_WIDE_INT == 64
1858 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1859 low_bits = (INTVAL (op1) & 0xffffffff);
1861 high_bits = ((INTVAL (op1) < 0) ?
1864 low_bits = INTVAL (op1);
1868 /* low_bits bits 0 --> 31
1869 high_bits bits 32 --> 63 */
1871 analyze_64bit_constant (high_bits, low_bits,
1872 &highest_bit_set, &lowest_bit_set,
1873 &all_bits_between_are_set);
1875 /* First try for a 2-insn sequence. */
1877 /* These situations are preferred because the optimizer can
1878 * do more things with them:
1880 * sllx %reg, shift, %reg
1882 * srlx %reg, shift, %reg
1883 * 3) mov some_small_const, %reg
1884 * sllx %reg, shift, %reg
1886 if (((highest_bit_set == 63
1887 || lowest_bit_set == 0)
1888 && all_bits_between_are_set != 0)
1889 || ((highest_bit_set - lowest_bit_set) < 12))
1891 HOST_WIDE_INT the_const = -1;
1892 int shift = lowest_bit_set;
1894 if ((highest_bit_set != 63
1895 && lowest_bit_set != 0)
1896 || all_bits_between_are_set == 0)
1899 create_simple_focus_bits (high_bits, low_bits,
1902 else if (lowest_bit_set == 0)
1903 shift = -(63 - highest_bit_set);
1905 if (! SPARC_SIMM13_P (the_const))
1908 emit_insn (gen_safe_SET64 (temp, the_const));
1910 emit_insn (gen_rtx_SET (VOIDmode,
1912 gen_rtx_ASHIFT (DImode,
1916 emit_insn (gen_rtx_SET (VOIDmode,
1918 gen_rtx_LSHIFTRT (DImode,
1920 GEN_INT (-shift))));
1926 /* Now a range of 22 or less bits set somewhere.
1927 * 1) sethi %hi(focus_bits), %reg
1928 * sllx %reg, shift, %reg
1929 * 2) sethi %hi(focus_bits), %reg
1930 * srlx %reg, shift, %reg
1932 if ((highest_bit_set - lowest_bit_set) < 21)
1934 unsigned HOST_WIDE_INT focus_bits =
1935 create_simple_focus_bits (high_bits, low_bits,
1936 lowest_bit_set, 10);
1938 if (! SPARC_SETHI_P (focus_bits))
1941 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
1943 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1944 if (lowest_bit_set < 10)
1945 emit_insn (gen_rtx_SET (VOIDmode,
1947 gen_rtx_LSHIFTRT (DImode, temp,
1948 GEN_INT (10 - lowest_bit_set))));
1949 else if (lowest_bit_set > 10)
1950 emit_insn (gen_rtx_SET (VOIDmode,
1952 gen_rtx_ASHIFT (DImode, temp,
1953 GEN_INT (lowest_bit_set - 10))));
1959 /* 1) sethi %hi(low_bits), %reg
1960 * or %reg, %lo(low_bits), %reg
1961 * 2) sethi %hi(~low_bits), %reg
1962 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1965 || high_bits == 0xffffffff)
1967 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1968 (high_bits == 0xffffffff));
1972 /* Now, try 3-insn sequences. */
1974 /* 1) sethi %hi(high_bits), %reg
1975 * or %reg, %lo(high_bits), %reg
1976 * sllx %reg, 32, %reg
1980 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
1984 /* We may be able to do something quick
1985 when the constant is negated, so try that. */
1986 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1987 (~low_bits) & 0xfffffc00))
1989 /* NOTE: The trailing bits get XOR'd so we need the
1990 non-negated bits, not the negated ones. */
1991 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
1993 if ((((~high_bits) & 0xffffffff) == 0
1994 && ((~low_bits) & 0x80000000) == 0)
1995 || (((~high_bits) & 0xffffffff) == 0xffffffff
1996 && ((~low_bits) & 0x80000000) != 0))
1998 int fast_int = (~low_bits & 0xffffffff);
2000 if ((SPARC_SETHI_P (fast_int)
2001 && (~high_bits & 0xffffffff) == 0)
2002 || SPARC_SIMM13_P (fast_int))
2003 emit_insn (gen_safe_SET64 (temp, fast_int));
2005 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2010 #if HOST_BITS_PER_WIDE_INT == 64
2011 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2012 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2014 negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx,
2015 (~low_bits) & 0xfffffc00,
2016 (~high_bits) & 0xffffffff);
2018 sparc_emit_set_const64 (temp, negated_const);
2021 /* If we are XOR'ing with -1, then we should emit a one's complement
2022 instead. This way the combiner will notice logical operations
2023 such as ANDN later on and substitute. */
2024 if (trailing_bits == 0x3ff)
2026 emit_insn (gen_rtx_SET (VOIDmode, op0,
2027 gen_rtx_NOT (DImode, temp)));
2031 emit_insn (gen_rtx_SET (VOIDmode,
2033 gen_safe_XOR64 (temp,
2034 (-0x400 | trailing_bits))));
2039 /* 1) sethi %hi(xxx), %reg
2040 * or %reg, %lo(xxx), %reg
2041 * sllx %reg, yyy, %reg
2043 * ??? This is just a generalized version of the low_bits==0
2044 * thing above, FIXME...
2046 if ((highest_bit_set - lowest_bit_set) < 32)
2048 unsigned HOST_WIDE_INT focus_bits =
2049 create_simple_focus_bits (high_bits, low_bits,
2052 /* We can't get here in this state. */
2053 if (highest_bit_set < 32
2054 || lowest_bit_set >= 32)
2057 /* So what we know is that the set bits straddle the
2058 middle of the 64-bit word. */
2059 sparc_emit_set_const64_quick2 (op0, temp,
2065 /* 1) sethi %hi(high_bits), %reg
2066 * or %reg, %lo(high_bits), %reg
2067 * sllx %reg, 32, %reg
2068 * or %reg, low_bits, %reg
2070 if (SPARC_SIMM13_P(low_bits)
2071 && ((int)low_bits > 0))
2073 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2077 /* The easiest way when all else fails, is full decomposition. */
2079 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2080 high_bits, low_bits, ~high_bits, ~low_bits);
2082 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2085 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2086 return the mode to be used for the comparison. For floating-point,
2087 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2088 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2089 processing is needed. */
2092 select_cc_mode (op, x, y)
2095 rtx y ATTRIBUTE_UNUSED;
2097 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2123 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2124 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2126 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2127 return CCX_NOOVmode;
2133 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2140 /* X and Y are two things to compare using CODE. Emit the compare insn and
2141 return the rtx for the cc reg in the proper mode. */
2144 gen_compare_reg (code, x, y)
2148 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2151 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2152 fcc regs (cse can't tell they're really call clobbered regs and will
2153 remove a duplicate comparison even if there is an intervening function
2154 call - it will then try to reload the cc reg via an int reg which is why
2155 we need the movcc patterns). It is possible to provide the movcc
2156 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2157 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2158 to tell cse that CCFPE mode registers (even pseudos) are call
2161 /* ??? This is an experiment. Rather than making changes to cse which may
2162 or may not be easy/clean, we do our own cse. This is possible because
2163 we will generate hard registers. Cse knows they're call clobbered (it
2164 doesn't know the same thing about pseudos). If we guess wrong, no big
2165 deal, but if we win, great! */
2167 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2168 #if 1 /* experiment */
2171 /* We cycle through the registers to ensure they're all exercised. */
2172 static int next_fcc_reg = 0;
2173 /* Previous x,y for each fcc reg. */
2174 static rtx prev_args[4][2];
2176 /* Scan prev_args for x,y. */
2177 for (reg = 0; reg < 4; reg++)
2178 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2183 prev_args[reg][0] = x;
2184 prev_args[reg][1] = y;
2185 next_fcc_reg = (next_fcc_reg + 1) & 3;
2187 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2190 cc_reg = gen_reg_rtx (mode);
2191 #endif /* ! experiment */
2192 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2193 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2195 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2197 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2198 gen_rtx_COMPARE (mode, x, y)));
2203 /* This function is used for v9 only.
2204 CODE is the code for an Scc's comparison.
2205 OPERANDS[0] is the target of the Scc insn.
2206 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2207 been generated yet).
2209 This function is needed to turn
2212 (gt (reg:CCX 100 %icc)
2216 (gt:DI (reg:CCX 100 %icc)
2219 IE: The instruction recognizer needs to see the mode of the comparison to
2220 find the right instruction. We could use "gt:DI" right in the
2221 define_expand, but leaving it out allows us to handle DI, SI, etc.
2223 We refer to the global sparc compare operands sparc_compare_op0 and
2224 sparc_compare_op1. */
2227 gen_v9_scc (compare_code, operands)
2228 enum rtx_code compare_code;
2229 register rtx *operands;
2234 && (GET_MODE (sparc_compare_op0) == DImode
2235 || GET_MODE (operands[0]) == DImode))
2238 /* Handle the case where operands[0] == sparc_compare_op0.
2239 We "early clobber" the result. */
2240 if (REGNO (operands[0]) == REGNO (sparc_compare_op0))
2242 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2243 emit_move_insn (op0, sparc_compare_op0);
2246 op0 = sparc_compare_op0;
2247 /* For consistency in the following. */
2248 op1 = sparc_compare_op1;
2250 /* Try to use the movrCC insns. */
2252 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2253 && op1 == const0_rtx
2254 && v9_regcmp_p (compare_code))
2256 /* Special case for op0 != 0. This can be done with one instruction if
2257 operands[0] == sparc_compare_op0. We don't assume they are equal
2260 if (compare_code == NE
2261 && GET_MODE (operands[0]) == DImode
2262 && GET_MODE (op0) == DImode)
2264 emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0));
2265 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2266 gen_rtx_IF_THEN_ELSE (DImode,
2267 gen_rtx_fmt_ee (compare_code, DImode,
2274 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2275 if (GET_MODE (op0) != DImode)
2277 temp = gen_reg_rtx (DImode);
2278 convert_move (temp, op0, 0);
2282 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2283 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2284 gen_rtx_fmt_ee (compare_code, DImode,
2292 operands[1] = gen_compare_reg (compare_code, op0, op1);
2294 switch (GET_MODE (operands[1]))
2304 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2305 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2306 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2307 gen_rtx_fmt_ee (compare_code,
2308 GET_MODE (operands[1]),
2309 operands[1], const0_rtx),
2310 const1_rtx, operands[0])));
2315 /* Emit a conditional jump insn for the v9 architecture using comparison code
2316 CODE and jump target LABEL.
2317 This function exists to take advantage of the v9 brxx insns. */
2320 emit_v9_brxx_insn (code, op0, label)
2324 emit_jump_insn (gen_rtx_SET (VOIDmode,
2326 gen_rtx_IF_THEN_ELSE (VOIDmode,
2327 gen_rtx_fmt_ee (code, GET_MODE (op0),
2329 gen_rtx_LABEL_REF (VOIDmode, label),
2333 /* Generate a DFmode part of a hard TFmode register.
2334 REG is the TFmode hard register, LOW is 1 for the
2335 low 64bit of the register and 0 otherwise.
2338 gen_df_reg (reg, low)
2342 int regno = REGNO (reg);
2344 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2345 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2346 return gen_rtx_REG (DFmode, regno);
2349 /* Return nonzero if a return peephole merging return with
2350 setting of output register is ok. */
2352 leaf_return_peephole_ok ()
2354 return (actual_fsize == 0);
2357 /* Return nonzero if TRIAL can go into the function epilogue's
2358 delay slot. SLOT is the slot we are trying to fill. */
2361 eligible_for_epilogue_delay (trial, slot)
2370 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2373 if (get_attr_length (trial) != 1)
2376 /* If there are any call-saved registers, we should scan TRIAL if it
2377 does not reference them. For now just make it easy. */
2381 /* In the case of a true leaf function, anything can go into the delay slot.
2382 A delay slot only exists however if the frame size is zero, otherwise
2383 we will put an insn to adjust the stack after the return. */
2384 if (current_function_uses_only_leaf_regs)
2386 if (leaf_return_peephole_ok ())
2387 return ((get_attr_in_uncond_branch_delay (trial)
2388 == IN_BRANCH_DELAY_TRUE));
2392 pat = PATTERN (trial);
2394 /* Otherwise, only operations which can be done in tandem with
2395 a `restore' or `return' insn can go into the delay slot. */
2396 if (GET_CODE (SET_DEST (pat)) != REG
2397 || REGNO (SET_DEST (pat)) < 24)
2400 /* If this instruction sets up floating point register and we have a return
2401 instruction, it can probably go in. But restore will not work
2403 if (REGNO (SET_DEST (pat)) >= 32)
2405 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2406 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2411 /* The set of insns matched here must agree precisely with the set of
2412 patterns paired with a RETURN in sparc.md. */
2414 src = SET_SRC (pat);
2416 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2417 if (arith_operand (src, GET_MODE (src)))
2420 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2422 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2425 /* This matches "*return_di". */
2426 else if (arith_double_operand (src, GET_MODE (src)))
2427 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2429 /* This matches "*return_sf_no_fpu". */
2430 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2431 && register_operand (src, SFmode))
2434 /* If we have return instruction, anything that does not use
2435 local or output registers and can go into a delay slot wins. */
2436 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2437 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2440 /* This matches "*return_addsi". */
2441 else if (GET_CODE (src) == PLUS
2442 && arith_operand (XEXP (src, 0), SImode)
2443 && arith_operand (XEXP (src, 1), SImode)
2444 && (register_operand (XEXP (src, 0), SImode)
2445 || register_operand (XEXP (src, 1), SImode)))
2448 /* This matches "*return_adddi". */
2449 else if (GET_CODE (src) == PLUS
2450 && arith_double_operand (XEXP (src, 0), DImode)
2451 && arith_double_operand (XEXP (src, 1), DImode)
2452 && (register_operand (XEXP (src, 0), DImode)
2453 || register_operand (XEXP (src, 1), DImode)))
2456 /* This can match "*return_losum_[sd]i".
2457 Catch only some cases, so that return_losum* don't have
2459 else if (GET_CODE (src) == LO_SUM
2460 && ! TARGET_CM_MEDMID
2461 && ((register_operand (XEXP (src, 0), SImode)
2462 && immediate_operand (XEXP (src, 1), SImode))
2464 && register_operand (XEXP (src, 0), DImode)
2465 && immediate_operand (XEXP (src, 1), DImode))))
2468 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2469 else if (GET_CODE (src) == ASHIFT
2470 && (register_operand (XEXP (src, 0), SImode)
2471 || register_operand (XEXP (src, 0), DImode))
2472 && XEXP (src, 1) == const1_rtx)
2478 /* Return nonzero if TRIAL can go into the sibling call
2482 eligible_for_sibcall_delay (trial)
2487 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2490 if (get_attr_length (trial) != 1 || profile_block_flag == 2)
2493 pat = PATTERN (trial);
2495 if (current_function_uses_only_leaf_regs)
2497 /* If the tail call is done using the call instruction,
2498 we have to restore %o7 in the delay slot. */
2499 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2502 /* %g1 is used to build the function address */
2503 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2509 /* Otherwise, only operations which can be done in tandem with
2510 a `restore' insn can go into the delay slot. */
2511 if (GET_CODE (SET_DEST (pat)) != REG
2512 || REGNO (SET_DEST (pat)) < 24
2513 || REGNO (SET_DEST (pat)) >= 32)
2516 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2518 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2521 src = SET_SRC (pat);
2523 if (arith_operand (src, GET_MODE (src)))
2526 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2528 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2531 else if (arith_double_operand (src, GET_MODE (src)))
2532 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2534 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2535 && register_operand (src, SFmode))
2538 else if (GET_CODE (src) == PLUS
2539 && arith_operand (XEXP (src, 0), SImode)
2540 && arith_operand (XEXP (src, 1), SImode)
2541 && (register_operand (XEXP (src, 0), SImode)
2542 || register_operand (XEXP (src, 1), SImode)))
2545 else if (GET_CODE (src) == PLUS
2546 && arith_double_operand (XEXP (src, 0), DImode)
2547 && arith_double_operand (XEXP (src, 1), DImode)
2548 && (register_operand (XEXP (src, 0), DImode)
2549 || register_operand (XEXP (src, 1), DImode)))
2552 else if (GET_CODE (src) == LO_SUM
2553 && ! TARGET_CM_MEDMID
2554 && ((register_operand (XEXP (src, 0), SImode)
2555 && immediate_operand (XEXP (src, 1), SImode))
2557 && register_operand (XEXP (src, 0), DImode)
2558 && immediate_operand (XEXP (src, 1), DImode))))
2561 else if (GET_CODE (src) == ASHIFT
2562 && (register_operand (XEXP (src, 0), SImode)
2563 || register_operand (XEXP (src, 0), DImode))
2564 && XEXP (src, 1) == const1_rtx)
2571 check_return_regs (x)
2574 switch (GET_CODE (x))
2577 return IN_OR_GLOBAL_P (x);
2592 if (check_return_regs (XEXP (x, 1)) == 0)
2597 return check_return_regs (XEXP (x, 0));
2605 /* Return 1 if TRIAL references only in and global registers. */
2607 eligible_for_return_delay (trial)
2610 if (GET_CODE (PATTERN (trial)) != SET)
2613 return check_return_regs (PATTERN (trial));
2617 short_branch (uid1, uid2)
2620 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
2622 /* Leave a few words of "slop". */
2623 if (delta >= -1023 && delta <= 1022)
2629 /* Return non-zero if REG is not used after INSN.
2630 We assume REG is a reload reg, and therefore does
2631 not live past labels or calls or jumps. */
2633 reg_unused_after (reg, insn)
2637 enum rtx_code code, prev_code = UNKNOWN;
2639 while ((insn = NEXT_INSN (insn)))
2641 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2644 code = GET_CODE (insn);
2645 if (GET_CODE (insn) == CODE_LABEL)
2648 if (GET_RTX_CLASS (code) == 'i')
2650 rtx set = single_set (insn);
2651 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2654 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2656 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2664 /* The table we use to reference PIC data. */
2665 static rtx global_offset_table;
2667 /* The function we use to get at it. */
2668 static rtx get_pc_symbol;
2669 static char get_pc_symbol_name[256];
2671 /* Ensure that we are not using patterns that are not OK with PIC. */
2680 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
2681 || (GET_CODE (recog_data.operand[i]) == CONST
2682 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
2683 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
2684 == global_offset_table)
2685 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
2694 /* Return true if X is an address which needs a temporary register when
2695 reloaded while generating PIC code. */
2698 pic_address_needs_scratch (x)
2701 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2702 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2703 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2704 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2705 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2711 /* Legitimize PIC addresses. If the address is already position-independent,
2712 we return ORIG. Newly generated position-independent addresses go into a
2713 reg. This is REG if non zero, otherwise we allocate register(s) as
2717 legitimize_pic_address (orig, mode, reg)
2719 enum machine_mode mode ATTRIBUTE_UNUSED;
2722 if (GET_CODE (orig) == SYMBOL_REF)
2724 rtx pic_ref, address;
2729 if (reload_in_progress || reload_completed)
2732 reg = gen_reg_rtx (Pmode);
2737 /* If not during reload, allocate another temp reg here for loading
2738 in the address, so that these instructions can be optimized
2740 rtx temp_reg = ((reload_in_progress || reload_completed)
2741 ? reg : gen_reg_rtx (Pmode));
2743 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
2744 won't get confused into thinking that these two instructions
2745 are loading in the true address of the symbol. If in the
2746 future a PIC rtx exists, that should be used instead. */
2747 if (Pmode == SImode)
2749 emit_insn (gen_movsi_high_pic (temp_reg, orig));
2750 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
2754 emit_insn (gen_movdi_high_pic (temp_reg, orig));
2755 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
2762 pic_ref = gen_rtx_MEM (Pmode,
2763 gen_rtx_PLUS (Pmode,
2764 pic_offset_table_rtx, address));
2765 current_function_uses_pic_offset_table = 1;
2766 RTX_UNCHANGING_P (pic_ref) = 1;
2767 insn = emit_move_insn (reg, pic_ref);
2768 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2770 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2774 else if (GET_CODE (orig) == CONST)
2778 if (GET_CODE (XEXP (orig, 0)) == PLUS
2779 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2784 if (reload_in_progress || reload_completed)
2787 reg = gen_reg_rtx (Pmode);
2790 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2792 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2793 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2794 base == reg ? 0 : reg);
2799 if (GET_CODE (offset) == CONST_INT)
2801 if (SMALL_INT (offset))
2802 return plus_constant_for_output (base, INTVAL (offset));
2803 else if (! reload_in_progress && ! reload_completed)
2804 offset = force_reg (Pmode, offset);
2806 /* If we reach here, then something is seriously wrong. */
2809 return gen_rtx_PLUS (Pmode, base, offset);
2811 else if (GET_CODE (orig) == LABEL_REF)
2812 /* ??? Why do we do this? */
2813 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
2814 the register is live instead, in case it is eliminated. */
2815 current_function_uses_pic_offset_table = 1;
2820 /* Emit special PIC prologues. */
2823 load_pic_register ()
2825 /* Labels to get the PC in the prologue of this function. */
2826 int orig_flag_pic = flag_pic;
2831 /* If we havn't emitted the special get_pc helper function, do so now. */
2832 if (get_pc_symbol_name[0] == 0)
2836 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
2839 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
2841 ASM_OUTPUT_ALIGN (asm_out_file, align);
2842 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0);
2843 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
2846 /* Initialize every time through, since we can't easily
2847 know this to be permanent. */
2848 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2849 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
2852 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
2855 flag_pic = orig_flag_pic;
2857 /* Need to emit this whether or not we obey regdecls,
2858 since setjmp/longjmp can cause life info to screw up.
2859 ??? In the case where we don't obey regdecls, this is not sufficient
2860 since we may not fall out the bottom. */
2861 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2864 /* Return 1 if RTX is a MEM which is known to be aligned to at
2865 least an 8 byte boundary. */
2868 mem_min_alignment (mem, desired)
2872 rtx addr, base, offset;
2874 /* If it's not a MEM we can't accept it. */
2875 if (GET_CODE (mem) != MEM)
2878 addr = XEXP (mem, 0);
2879 base = offset = NULL_RTX;
2880 if (GET_CODE (addr) == PLUS)
2882 if (GET_CODE (XEXP (addr, 0)) == REG)
2884 base = XEXP (addr, 0);
2886 /* What we are saying here is that if the base
2887 REG is aligned properly, the compiler will make
2888 sure any REG based index upon it will be so
2890 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2891 offset = XEXP (addr, 1);
2893 offset = const0_rtx;
2896 else if (GET_CODE (addr) == REG)
2899 offset = const0_rtx;
2902 if (base != NULL_RTX)
2904 int regno = REGNO (base);
2906 if (regno != FRAME_POINTER_REGNUM
2907 && regno != STACK_POINTER_REGNUM)
2909 /* Check if the compiler has recorded some information
2910 about the alignment of the base REG. If reload has
2911 completed, we already matched with proper alignments.
2912 If not running global_alloc, reload might give us
2913 unaligned pointer to local stack though. */
2915 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
2916 || (optimize && reload_completed))
2917 && (INTVAL (offset) & (desired - 1)) == 0)
2922 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
2926 else if (! TARGET_UNALIGNED_DOUBLES
2927 || CONSTANT_P (addr)
2928 || GET_CODE (addr) == LO_SUM)
2930 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
2931 is true, in which case we can only assume that an access is aligned if
2932 it is to a constant address, or the address involves a LO_SUM. */
2936 /* An obviously unaligned address. */
2941 /* Vectors to keep interesting information about registers where it can easily
2942 be got. We use to use the actual mode value as the bit number, but there
2943 are more than 32 modes now. Instead we use two tables: one indexed by
2944 hard register number, and one indexed by mode. */
2946 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2947 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2948 mapped into one sparc_mode_class mode. */
2950 enum sparc_mode_class {
2951 S_MODE, D_MODE, T_MODE, O_MODE,
2952 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
2956 /* Modes for single-word and smaller quantities. */
2957 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2959 /* Modes for double-word and smaller quantities. */
2960 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2962 /* Modes for quad-word and smaller quantities. */
2963 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2965 /* Modes for 8-word and smaller quantities. */
2966 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
2968 /* Modes for single-float quantities. We must allow any single word or
2969 smaller quantity. This is because the fix/float conversion instructions
2970 take integer inputs/outputs from the float registers. */
2971 #define SF_MODES (S_MODES)
2973 /* Modes for double-float and smaller quantities. */
2974 #define DF_MODES (S_MODES | D_MODES)
2976 /* Modes for double-float only quantities. */
2977 #define DF_MODES_NO_S (D_MODES)
2979 /* Modes for quad-float only quantities. */
2980 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2982 /* Modes for quad-float and smaller quantities. */
2983 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2985 /* Modes for quad-float and double-float quantities. */
2986 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
2988 /* Modes for quad-float pair only quantities. */
2989 #define OF_ONLY_MODES (1 << (int) OF_MODE)
2991 /* Modes for quad-float pairs and smaller quantities. */
2992 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
2994 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
2996 /* Modes for condition codes. */
2997 #define CC_MODES (1 << (int) CC_MODE)
2998 #define CCFP_MODES (1 << (int) CCFP_MODE)
3000 /* Value is 1 if register/mode pair is acceptable on sparc.
3001 The funny mixture of D and T modes is because integer operations
3002 do not specially operate on tetra quantities, so non-quad-aligned
3003 registers can hold quadword quantities (except %o4 and %i4 because
3004 they cross fixed registers). */
3006 /* This points to either the 32 bit or the 64 bit version. */
3007 int *hard_regno_mode_classes;
3009 static int hard_32bit_mode_classes[] = {
3010 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3011 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3012 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3013 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3015 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3016 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3017 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3018 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3020 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3021 and none can hold SFmode/SImode values. */
3022 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3023 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3024 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3025 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3028 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3034 static int hard_64bit_mode_classes[] = {
3035 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3036 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3037 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3038 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3040 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3041 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3042 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3043 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3045 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3046 and none can hold SFmode/SImode values. */
3047 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3048 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3049 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3050 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3053 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3059 int sparc_mode_class [NUM_MACHINE_MODES];
3061 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3068 for (i = 0; i < NUM_MACHINE_MODES; i++)
3070 switch (GET_MODE_CLASS (i))
3073 case MODE_PARTIAL_INT:
3074 case MODE_COMPLEX_INT:
3075 if (GET_MODE_SIZE (i) <= 4)
3076 sparc_mode_class[i] = 1 << (int) S_MODE;
3077 else if (GET_MODE_SIZE (i) == 8)
3078 sparc_mode_class[i] = 1 << (int) D_MODE;
3079 else if (GET_MODE_SIZE (i) == 16)
3080 sparc_mode_class[i] = 1 << (int) T_MODE;
3081 else if (GET_MODE_SIZE (i) == 32)
3082 sparc_mode_class[i] = 1 << (int) O_MODE;
3084 sparc_mode_class[i] = 0;
3087 case MODE_COMPLEX_FLOAT:
3088 if (GET_MODE_SIZE (i) <= 4)
3089 sparc_mode_class[i] = 1 << (int) SF_MODE;
3090 else if (GET_MODE_SIZE (i) == 8)
3091 sparc_mode_class[i] = 1 << (int) DF_MODE;
3092 else if (GET_MODE_SIZE (i) == 16)
3093 sparc_mode_class[i] = 1 << (int) TF_MODE;
3094 else if (GET_MODE_SIZE (i) == 32)
3095 sparc_mode_class[i] = 1 << (int) OF_MODE;
3097 sparc_mode_class[i] = 0;
3101 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3102 we must explicitly check for them here. */
3103 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3104 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3105 else if (i == (int) CCmode || i == (int) CC_NOOVmode
3106 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3107 sparc_mode_class[i] = 1 << (int) CC_MODE;
3109 sparc_mode_class[i] = 0;
3115 hard_regno_mode_classes = hard_64bit_mode_classes;
3117 hard_regno_mode_classes = hard_32bit_mode_classes;
3119 /* Initialize the array used by REGNO_REG_CLASS. */
3120 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3122 if (i < 16 && TARGET_V8PLUS)
3123 sparc_regno_reg_class[i] = I64_REGS;
3125 sparc_regno_reg_class[i] = GENERAL_REGS;
3127 sparc_regno_reg_class[i] = FP_REGS;
3129 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3131 sparc_regno_reg_class[i] = FPCC_REGS;
3133 sparc_regno_reg_class[i] = NO_REGS;
3137 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3138 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3139 v9 int regs as it simplifies the code. */
3142 save_regs (file, low, high, base, offset, n_regs, real_offset)
3152 if (TARGET_ARCH64 && high <= 32)
3154 for (i = low; i < high; i++)
3156 if (regs_ever_live[i] && ! call_used_regs[i])
3158 fprintf (file, "\tstx\t%s, [%s+%d]\n",
3159 reg_names[i], base, offset + 4 * n_regs);
3160 if (dwarf2out_do_frame ())
3161 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3168 for (i = low; i < high; i += 2)
3170 if (regs_ever_live[i] && ! call_used_regs[i])
3172 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3174 fprintf (file, "\tstd\t%s, [%s+%d]\n",
3175 reg_names[i], base, offset + 4 * n_regs);
3176 if (dwarf2out_do_frame ())
3178 char *l = dwarf2out_cfi_label ();
3179 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
3180 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
3186 fprintf (file, "\tst\t%s, [%s+%d]\n",
3187 reg_names[i], base, offset + 4 * n_regs);
3188 if (dwarf2out_do_frame ())
3189 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3195 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3197 fprintf (file, "\tst\t%s, [%s+%d]\n",
3198 reg_names[i+1], base, offset + 4 * n_regs + 4);
3199 if (dwarf2out_do_frame ())
3200 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
3209 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3211 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3212 v9 int regs as it simplifies the code. */
3215 restore_regs (file, low, high, base, offset, n_regs)
3224 if (TARGET_ARCH64 && high <= 32)
3226 for (i = low; i < high; i++)
3228 if (regs_ever_live[i] && ! call_used_regs[i])
3229 fprintf (file, "\tldx\t[%s+%d], %s\n",
3230 base, offset + 4 * n_regs, reg_names[i]),
3236 for (i = low; i < high; i += 2)
3238 if (regs_ever_live[i] && ! call_used_regs[i])
3239 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3240 fprintf (file, "\tldd\t[%s+%d], %s\n",
3241 base, offset + 4 * n_regs, reg_names[i]),
3244 fprintf (file, "\tld\t[%s+%d], %s\n",
3245 base, offset + 4 * n_regs, reg_names[i]),
3247 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3248 fprintf (file, "\tld\t[%s+%d], %s\n",
3249 base, offset + 4 * n_regs + 4, reg_names[i+1]),
3256 /* Compute the frame size required by the function. This function is called
3257 during the reload pass and also by output_function_prologue(). */
3260 compute_frame_size (size, leaf_function)
3265 int outgoing_args_size = (current_function_outgoing_args_size
3266 + REG_PARM_STACK_SPACE (current_function_decl));
3268 if (TARGET_EPILOGUE)
3270 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3271 even to v9 int regs to be consistent with save_regs/restore_regs. */
3275 for (i = 0; i < 8; i++)
3276 if (regs_ever_live[i] && ! call_used_regs[i])
3281 for (i = 0; i < 8; i += 2)
3282 if ((regs_ever_live[i] && ! call_used_regs[i])
3283 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3287 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3288 if ((regs_ever_live[i] && ! call_used_regs[i])
3289 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3293 /* Set up values for use in `function_epilogue'. */
3294 num_gfregs = n_regs;
3296 if (leaf_function && n_regs == 0
3297 && size == 0 && current_function_outgoing_args_size == 0)
3299 actual_fsize = apparent_fsize = 0;
3303 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3304 The stack bias (if any) is taken out to undo its effects. */
3305 apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8;
3306 apparent_fsize += n_regs * 4;
3307 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3310 /* Make sure nothing can clobber our register windows.
3311 If a SAVE must be done, or there is a stack-local variable,
3312 the register window area must be allocated.
3313 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3314 if (leaf_function == 0 || size > 0)
3315 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3317 return SPARC_STACK_ALIGN (actual_fsize);
3320 /* Build a (32 bit) big number in a register. */
3321 /* ??? We may be able to use the set macro here too. */
3324 build_big_number (file, num, reg)
3329 if (num >= 0 || ! TARGET_ARCH64)
3331 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
3332 if ((num & 0x3ff) != 0)
3333 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
3335 else /* num < 0 && TARGET_ARCH64 */
3337 /* Sethi does not sign extend, so we must use a little trickery
3338 to use it for negative numbers. Invert the constant before
3339 loading it in, then use xor immediate to invert the loaded bits
3340 (along with the upper 32 bits) to the desired constant. This
3341 works because the sethi and immediate fields overlap. */
3344 int low = -0x400 + (asize & 0x3FF);
3346 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3347 inv, reg, reg, low, reg);
3351 /* Output any necessary .register pseudo-ops. */
3353 sparc_output_scratch_registers (file)
3354 FILE *file ATTRIBUTE_UNUSED;
3356 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3362 /* Check if %g[2367] were used without
3363 .register being printed for them already. */
3364 for (i = 2; i < 8; i++)
3366 if (regs_ever_live [i]
3367 && ! sparc_hard_reg_printed [i])
3369 sparc_hard_reg_printed [i] = 1;
3370 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
3377 /* Output code for the function prologue. */
3380 output_function_prologue (file, size, leaf_function)
3385 sparc_output_scratch_registers (file);
3387 /* Need to use actual_fsize, since we are also allocating
3388 space for our callee (and our own register save area). */
3389 actual_fsize = compute_frame_size (size, leaf_function);
3393 frame_base_name = "%sp";
3394 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3398 frame_base_name = "%fp";
3399 frame_base_offset = SPARC_STACK_BIAS;
3402 /* This is only for the human reader. */
3403 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3405 if (actual_fsize == 0)
3407 else if (! leaf_function)
3409 if (actual_fsize <= 4096)
3410 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3411 else if (actual_fsize <= 8192)
3413 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3414 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3418 build_big_number (file, -actual_fsize, "%g1");
3419 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
3422 else /* leaf function */
3424 if (actual_fsize <= 4096)
3425 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3426 else if (actual_fsize <= 8192)
3428 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3429 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3433 build_big_number (file, -actual_fsize, "%g1");
3434 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3438 if (dwarf2out_do_frame () && actual_fsize)
3440 char *label = dwarf2out_cfi_label ();
3442 /* The canonical frame address refers to the top of the frame. */
3443 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3444 : FRAME_POINTER_REGNUM),
3447 if (! leaf_function)
3449 /* Note the register window save. This tells the unwinder that
3450 it needs to restore the window registers from the previous
3451 frame's window save area at 0(cfa). */
3452 dwarf2out_window_save (label);
3454 /* The return address (-8) is now in %i7. */
3455 dwarf2out_return_reg (label, 31);
3459 /* If doing anything with PIC, do it now. */
3461 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3463 /* Call saved registers are saved just above the outgoing argument area. */
3466 int offset, real_offset, n_regs;
3469 real_offset = -apparent_fsize;
3470 offset = -apparent_fsize + frame_base_offset;
3471 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3473 /* ??? This might be optimized a little as %g1 might already have a
3474 value close enough that a single add insn will do. */
3475 /* ??? Although, all of this is probably only a temporary fix
3476 because if %g1 can hold a function result, then
3477 output_function_epilogue will lose (the result will get
3479 build_big_number (file, offset, "%g1");
3480 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3486 base = frame_base_name;
3490 if (TARGET_EPILOGUE && ! leaf_function)
3491 /* ??? Originally saved regs 0-15 here. */
3492 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3493 else if (leaf_function)
3494 /* ??? Originally saved regs 0-31 here. */
3495 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3496 if (TARGET_EPILOGUE)
3497 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3502 if (leaf_function && actual_fsize != 0)
3504 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3505 if (! TARGET_EPILOGUE)
3506 leaf_label = gen_label_rtx ();
3510 /* Output code to restore any call saved registers. */
3513 output_restore_regs (file, leaf_function)
3520 offset = -apparent_fsize + frame_base_offset;
3521 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3523 build_big_number (file, offset, "%g1");
3524 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3530 base = frame_base_name;
3534 if (TARGET_EPILOGUE && ! leaf_function)
3535 /* ??? Originally saved regs 0-15 here. */
3536 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3537 else if (leaf_function)
3538 /* ??? Originally saved regs 0-31 here. */
3539 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3540 if (TARGET_EPILOGUE)
3541 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
3544 /* Output code for the function epilogue. */
3547 output_function_epilogue (file, size, leaf_function)
3549 int size ATTRIBUTE_UNUSED;
3556 emit_label_after (leaf_label, get_last_insn ());
3557 final_scan_insn (get_last_insn (), file, 0, 0, 1);
3560 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3561 else if (profile_block_flag == 2)
3563 FUNCTION_BLOCK_PROFILER_EXIT(file);
3567 else if (current_function_epilogue_delay_list == 0)
3569 /* If code does not drop into the epilogue, we need
3570 do nothing except output pending case vectors. */
3571 rtx insn = get_last_insn ();
3572 if (GET_CODE (insn) == NOTE)
3573 insn = prev_nonnote_insn (insn);
3574 if (insn && GET_CODE (insn) == BARRIER)
3575 goto output_vectors;
3579 output_restore_regs (file, leaf_function);
3581 /* Work out how to skip the caller's unimp instruction if required. */
3583 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
3585 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
3587 if (TARGET_EPILOGUE || leaf_label)
3589 int old_target_epilogue = TARGET_EPILOGUE;
3590 target_flags &= ~old_target_epilogue;
3592 if (! leaf_function)
3594 /* If we wound up with things in our delay slot, flush them here. */
3595 if (current_function_epilogue_delay_list)
3597 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
3599 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
3601 epilogue_renumber (&delay, 0);
3602 fputs (SKIP_CALLERS_UNIMP_P
3603 ? "\treturn\t%i7+12\n"
3604 : "\treturn\t%i7+8\n", file);
3605 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), file, 1, 0, 0);
3609 rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode),
3613 if (GET_CODE (delay) != SET)
3616 src = SET_SRC (delay);
3617 if (GET_CODE (src) == ASHIFT)
3619 if (XEXP (src, 1) != const1_rtx)
3621 SET_SRC (delay) = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
3625 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode,
3626 gen_rtvec (2, delay, PATTERN (insn)));
3627 final_scan_insn (insn, file, 1, 0, 1);
3630 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
3631 fputs ("\treturn\t%i7+8\n\tnop\n", file);
3633 fprintf (file, "\t%s\n\trestore\n", ret);
3635 /* All of the following cases are for leaf functions. */
3636 else if (current_function_epilogue_delay_list)
3638 /* eligible_for_epilogue_delay_slot ensures that if this is a
3639 leaf function, then we will only have insn in the delay slot
3640 if the frame size is zero, thus no adjust for the stack is
3642 if (actual_fsize != 0)
3644 fprintf (file, "\t%s\n", ret);
3645 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
3648 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3649 avoid generating confusing assembly language output. */
3650 else if (actual_fsize == 0)
3651 fprintf (file, "\t%s\n\tnop\n", ret);
3652 else if (actual_fsize <= 4096)
3653 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
3654 else if (actual_fsize <= 8192)
3655 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
3656 ret, actual_fsize - 4096);
3657 else if ((actual_fsize & 0x3ff) == 0)
3658 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3661 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3662 actual_fsize, actual_fsize, ret);
3663 target_flags |= old_target_epilogue;
3667 sparc_output_deferred_case_vectors ();
3670 /* Output a sibling call. */
3673 output_sibcall (insn, call_operand)
3674 rtx insn, call_operand;
3676 int leaf_regs = current_function_uses_only_leaf_regs;
3678 int delay_slot = dbr_sequence_length () > 0;
3682 /* Call to restore global regs might clobber
3683 the delay slot. Instead of checking for this
3684 output the delay slot now. */
3687 rtx delay = NEXT_INSN (insn);
3692 final_scan_insn (delay, asm_out_file, 1, 0, 1);
3693 PATTERN (delay) = gen_blockage ();
3694 INSN_CODE (delay) = -1;
3697 output_restore_regs (asm_out_file, leaf_regs);
3700 operands[0] = call_operand;
3704 #ifdef HAVE_AS_RELAX_OPTION
3705 /* If as and ld are relaxing tail call insns into branch always,
3706 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
3707 be optimized. With sethi/jmpl as nor ld has no easy way how to
3708 find out if somebody does not branch between the sethi and jmpl. */
3711 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
3715 if ((actual_fsize || ! spare_slot) && delay_slot)
3717 rtx delay = NEXT_INSN (insn);
3722 final_scan_insn (delay, asm_out_file, 1, 0, 1);
3723 PATTERN (delay) = gen_blockage ();
3724 INSN_CODE (delay) = -1;
3729 if (actual_fsize <= 4096)
3730 size = actual_fsize;
3731 else if (actual_fsize <= 8192)
3733 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
3734 size = actual_fsize - 4096;
3736 else if ((actual_fsize & 0x3ff) == 0)
3737 fprintf (asm_out_file,
3738 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
3742 fprintf (asm_out_file,
3743 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
3744 actual_fsize, actual_fsize);
3745 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
3750 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
3751 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
3753 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size);
3754 else if (! delay_slot)
3755 fputs ("\t nop\n", asm_out_file);
3760 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size);
3761 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
3762 it into branch if possible. */
3763 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
3764 output_asm_insn ("call\t%a0, 0", operands);
3765 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
3770 output_asm_insn ("call\t%a0, 0", operands);
3773 rtx delay = NEXT_INSN (insn), pat;
3778 pat = PATTERN (delay);
3779 if (GET_CODE (pat) != SET)
3782 operands[0] = SET_DEST (pat);
3783 pat = SET_SRC (pat);
3784 switch (GET_CODE (pat))
3787 operands[1] = XEXP (pat, 0);
3788 operands[2] = XEXP (pat, 1);
3789 output_asm_insn (" restore %r1, %2, %Y0", operands);
3792 operands[1] = XEXP (pat, 0);
3793 operands[2] = XEXP (pat, 1);
3794 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
3797 operands[1] = XEXP (pat, 0);
3798 output_asm_insn (" restore %r1, %r1, %Y0", operands);
3802 output_asm_insn (" restore %%g0, %1, %Y0", operands);
3805 PATTERN (delay) = gen_blockage ();
3806 INSN_CODE (delay) = -1;
3809 fputs ("\t restore\n", asm_out_file);
3813 /* Functions for handling argument passing.
3815 For v8 the first six args are normally in registers and the rest are
3816 pushed. Any arg that starts within the first 6 words is at least
3817 partially passed in a register unless its data type forbids.
3819 For v9, the argument registers are laid out as an array of 16 elements
3820 and arguments are added sequentially. The first 6 int args and up to the
3821 first 16 fp args (depending on size) are passed in regs.
3823 Slot Stack Integral Float Float in structure Double Long Double
3824 ---- ----- -------- ----- ------------------ ------ -----------
3825 15 [SP+248] %f31 %f30,%f31 %d30
3826 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3827 13 [SP+232] %f27 %f26,%f27 %d26
3828 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3829 11 [SP+216] %f23 %f22,%f23 %d22
3830 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3831 9 [SP+200] %f19 %f18,%f19 %d18
3832 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3833 7 [SP+184] %f15 %f14,%f15 %d14
3834 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3835 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3836 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3837 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3838 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3839 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3840 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3842 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3844 Integral arguments are always passed as 64 bit quantities appropriately
3847 Passing of floating point values is handled as follows.
3848 If a prototype is in scope:
3849 If the value is in a named argument (i.e. not a stdarg function or a
3850 value not part of the `...') then the value is passed in the appropriate
3852 If the value is part of the `...' and is passed in one of the first 6
3853 slots then the value is passed in the appropriate int reg.
3854 If the value is part of the `...' and is not passed in one of the first 6
3855 slots then the value is passed in memory.
3856 If a prototype is not in scope:
3857 If the value is one of the first 6 arguments the value is passed in the
3858 appropriate integer reg and the appropriate fp reg.
3859 If the value is not one of the first 6 arguments the value is passed in
3860 the appropriate fp reg and in memory.
3863 /* Maximum number of int regs for args. */
3864 #define SPARC_INT_ARG_MAX 6
3865 /* Maximum number of fp regs for args. */
3866 #define SPARC_FP_ARG_MAX 16
3868 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3870 /* Handle the INIT_CUMULATIVE_ARGS macro.
3871 Initialize a variable CUM of type CUMULATIVE_ARGS
3872 for a call to a function whose data type is FNTYPE.
3873 For a library call, FNTYPE is 0. */
3876 init_cumulative_args (cum, fntype, libname, indirect)
3877 CUMULATIVE_ARGS *cum;
3879 rtx libname ATTRIBUTE_UNUSED;
3880 int indirect ATTRIBUTE_UNUSED;
3883 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
3884 cum->libcall_p = fntype == 0;
3887 /* Compute the slot number to pass an argument in.
3888 Returns the slot number or -1 if passing on the stack.
3890 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3891 the preceding args and about the function being called.
3892 MODE is the argument's machine mode.
3893 TYPE is the data type of the argument (as a tree).
3894 This is null for libcalls where that information may
3896 NAMED is nonzero if this argument is a named parameter
3897 (otherwise it is an extra parameter matching an ellipsis).
3898 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3899 *PREGNO records the register number to use if scalar type.
3900 *PPADDING records the amount of padding needed in words. */
3903 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
3904 const CUMULATIVE_ARGS *cum;
3905 enum machine_mode mode;
3912 int regbase = (incoming_p
3913 ? SPARC_INCOMING_INT_ARG_FIRST
3914 : SPARC_OUTGOING_INT_ARG_FIRST);
3915 int slotno = cum->words;
3920 if (type != 0 && TREE_ADDRESSABLE (type))
3923 && type != 0 && mode == BLKmode
3924 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
3930 /* MODE is VOIDmode when generating the actual call.
3934 case QImode : case CQImode :
3935 case HImode : case CHImode :
3936 case SImode : case CSImode :
3937 case DImode : case CDImode :
3938 case TImode : case CTImode :
3939 if (slotno >= SPARC_INT_ARG_MAX)
3941 regno = regbase + slotno;
3944 case SFmode : case SCmode :
3945 case DFmode : case DCmode :
3946 case TFmode : case TCmode :
3949 if (slotno >= SPARC_INT_ARG_MAX)
3951 regno = regbase + slotno;
3955 if ((mode == TFmode || mode == TCmode)
3956 && (slotno & 1) != 0)
3957 slotno++, *ppadding = 1;
3958 if (TARGET_FPU && named)
3960 if (slotno >= SPARC_FP_ARG_MAX)
3962 regno = SPARC_FP_ARG_FIRST + slotno * 2;
3968 if (slotno >= SPARC_INT_ARG_MAX)
3970 regno = regbase + slotno;
3976 /* For sparc64, objects requiring 16 byte alignment get it. */
3979 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
3980 slotno++, *ppadding = 1;
3984 || (type && TREE_CODE (type) == UNION_TYPE))
3986 if (slotno >= SPARC_INT_ARG_MAX)
3988 regno = regbase + slotno;
3993 int intregs_p = 0, fpregs_p = 0;
3994 /* The ABI obviously doesn't specify how packed
3995 structures are passed. These are defined to be passed
3996 in int regs if possible, otherwise memory. */
3999 /* First see what kinds of registers we need. */
4000 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4002 if (TREE_CODE (field) == FIELD_DECL)
4004 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4009 if (DECL_PACKED (field))
4013 if (packed_p || !named)
4014 fpregs_p = 0, intregs_p = 1;
4016 /* If all arg slots are filled, then must pass on stack. */
4017 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4019 /* If there are only int args and all int arg slots are filled,
4020 then must pass on stack. */
4021 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4023 /* Note that even if all int arg slots are filled, fp members may
4024 still be passed in regs if such regs are available.
4025 *PREGNO isn't set because there may be more than one, it's up
4026 to the caller to compute them. */
4039 /* Handle recursive register counting for structure field layout. */
4041 struct function_arg_record_value_parms
4044 int slotno, named, regbase;
4049 static void function_arg_record_value_3
4050 PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *));
4051 static void function_arg_record_value_2
4052 PARAMS ((tree, HOST_WIDE_INT,
4053 struct function_arg_record_value_parms *));
4054 static void function_arg_record_value_1
4055 PARAMS ((tree, HOST_WIDE_INT,
4056 struct function_arg_record_value_parms *));
4057 static rtx function_arg_record_value
4058 PARAMS ((tree, enum machine_mode, int, int, int));
4060 /* A subroutine of function_arg_record_value. Traverse the structure
4061 recusively and determine how many registers will be required. */
4064 function_arg_record_value_1 (type, startbitpos, parms)
4066 HOST_WIDE_INT startbitpos;
4067 struct function_arg_record_value_parms *parms;
4071 /* The ABI obviously doesn't specify how packed structures are
4072 passed. These are defined to be passed in int regs if possible,
4073 otherwise memory. */
4076 /* We need to compute how many registers are needed so we can
4077 allocate the PARALLEL but before we can do that we need to know
4078 whether there are any packed fields. If there are, int regs are
4079 used regardless of whether there are fp values present. */
4080 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4082 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4089 /* Compute how many registers we need. */
4090 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4092 if (TREE_CODE (field) == FIELD_DECL)
4094 HOST_WIDE_INT bitpos = startbitpos;
4096 if (DECL_SIZE (field) != 0
4097 && host_integerp (bit_position (field), 1))
4098 bitpos += int_bit_position (field);
4100 /* ??? FIXME: else assume zero offset. */
4102 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4103 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
4104 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4109 if (parms->intoffset != -1)
4111 int intslots, this_slotno;
4113 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
4115 this_slotno = parms->slotno + parms->intoffset
4118 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4119 intslots = MAX (intslots, 0);
4120 parms->nregs += intslots;
4121 parms->intoffset = -1;
4124 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4125 If it wasn't true we wouldn't be here. */
4130 if (parms->intoffset == -1)
4131 parms->intoffset = bitpos;
4137 /* A subroutine of function_arg_record_value. Assign the bits of the
4138 structure between parms->intoffset and bitpos to integer registers. */
4141 function_arg_record_value_3 (bitpos, parms)
4142 HOST_WIDE_INT bitpos;
4143 struct function_arg_record_value_parms *parms;
4145 enum machine_mode mode;
4147 unsigned int startbit, endbit;
4148 int this_slotno, intslots, intoffset;
4151 if (parms->intoffset == -1)
4154 intoffset = parms->intoffset;
4155 parms->intoffset = -1;
4157 startbit = intoffset & -BITS_PER_WORD;
4158 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4159 intslots = (endbit - startbit) / BITS_PER_WORD;
4160 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
4162 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4166 /* If this is the trailing part of a word, only load that much into
4167 the register. Otherwise load the whole register. Note that in
4168 the latter case we may pick up unwanted bits. It's not a problem
4169 at the moment but may wish to revisit. */
4171 if (intoffset % BITS_PER_WORD != 0)
4172 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4177 intoffset /= BITS_PER_UNIT;
4180 regno = parms->regbase + this_slotno;
4181 reg = gen_rtx_REG (mode, regno);
4182 XVECEXP (parms->ret, 0, parms->nregs)
4183 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4186 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4190 while (intslots > 0);
4193 /* A subroutine of function_arg_record_value. Traverse the structure
4194 recursively and assign bits to floating point registers. Track which
4195 bits in between need integer registers; invoke function_arg_record_value_3
4196 to make that happen. */
4199 function_arg_record_value_2 (type, startbitpos, parms)
4201 HOST_WIDE_INT startbitpos;
4202 struct function_arg_record_value_parms *parms;
4207 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4209 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4216 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4218 if (TREE_CODE (field) == FIELD_DECL)
4220 HOST_WIDE_INT bitpos = startbitpos;
4222 if (DECL_SIZE (field) != 0
4223 && host_integerp (bit_position (field), 1))
4224 bitpos += int_bit_position (field);
4226 /* ??? FIXME: else assume zero offset. */
4228 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4229 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
4230 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4235 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
4238 function_arg_record_value_3 (bitpos, parms);
4240 reg = gen_rtx_REG (DECL_MODE (field),
4241 (SPARC_FP_ARG_FIRST + this_slotno * 2
4242 + (DECL_MODE (field) == SFmode
4243 && (bitpos & 32) != 0)));
4244 XVECEXP (parms->ret, 0, parms->nregs)
4245 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4246 GEN_INT (bitpos / BITS_PER_UNIT));
4251 if (parms->intoffset == -1)
4252 parms->intoffset = bitpos;
4258 /* Used by function_arg and function_value to implement the complex
4259 Sparc64 structure calling conventions. */
4262 function_arg_record_value (type, mode, slotno, named, regbase)
4264 enum machine_mode mode;
4265 int slotno, named, regbase;
4267 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4268 struct function_arg_record_value_parms parms;
4271 parms.ret = NULL_RTX;
4272 parms.slotno = slotno;
4273 parms.named = named;
4274 parms.regbase = regbase;
4276 /* Compute how many registers we need. */
4278 parms.intoffset = 0;
4279 function_arg_record_value_1 (type, 0, &parms);
4281 if (parms.intoffset != -1)
4283 unsigned int startbit, endbit;
4284 int intslots, this_slotno;
4286 startbit = parms.intoffset & -BITS_PER_WORD;
4287 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4288 intslots = (endbit - startbit) / BITS_PER_WORD;
4289 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
4291 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4292 intslots = MAX (intslots, 0);
4294 parms.nregs += intslots;
4296 nregs = parms.nregs;
4298 /* Allocate the vector and handle some annoying special cases. */
4301 /* ??? Empty structure has no value? Duh? */
4304 /* Though there's nothing really to store, return a word register
4305 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4306 leads to breakage due to the fact that there are zero bytes to
4308 return gen_rtx_REG (mode, regbase);
4312 /* ??? C++ has structures with no fields, and yet a size. Give up
4313 for now and pass everything back in integer registers. */
4314 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4316 if (nregs + slotno > SPARC_INT_ARG_MAX)
4317 nregs = SPARC_INT_ARG_MAX - slotno;
4322 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
4324 /* Fill in the entries. */
4326 parms.intoffset = 0;
4327 function_arg_record_value_2 (type, 0, &parms);
4328 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
4330 if (parms.nregs != nregs)
4336 /* Handle the FUNCTION_ARG macro.
4337 Determine where to put an argument to a function.
4338 Value is zero to push the argument on the stack,
4339 or a hard register in which to store the argument.
4341 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4342 the preceding args and about the function being called.
4343 MODE is the argument's machine mode.
4344 TYPE is the data type of the argument (as a tree).
4345 This is null for libcalls where that information may
4347 NAMED is nonzero if this argument is a named parameter
4348 (otherwise it is an extra parameter matching an ellipsis).
4349 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4352 function_arg (cum, mode, type, named, incoming_p)
4353 const CUMULATIVE_ARGS *cum;
4354 enum machine_mode mode;
4359 int regbase = (incoming_p
4360 ? SPARC_INCOMING_INT_ARG_FIRST
4361 : SPARC_OUTGOING_INT_ARG_FIRST);
4362 int slotno, regno, padding;
4365 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
4373 reg = gen_rtx_REG (mode, regno);
4377 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4378 but also have the slot allocated for them.
4379 If no prototype is in scope fp values in register slots get passed
4380 in two places, either fp regs and int regs or fp regs and memory. */
4381 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4382 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4383 && SPARC_FP_REG_P (regno))
4385 reg = gen_rtx_REG (mode, regno);
4386 if (cum->prototype_p || cum->libcall_p)
4388 /* "* 2" because fp reg numbers are recorded in 4 byte
4391 /* ??? This will cause the value to be passed in the fp reg and
4392 in the stack. When a prototype exists we want to pass the
4393 value in the reg but reserve space on the stack. That's an
4394 optimization, and is deferred [for a bit]. */
4395 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
4396 return gen_rtx_PARALLEL (mode,
4398 gen_rtx_EXPR_LIST (VOIDmode,
4399 NULL_RTX, const0_rtx),
4400 gen_rtx_EXPR_LIST (VOIDmode,
4404 /* ??? It seems that passing back a register even when past
4405 the area declared by REG_PARM_STACK_SPACE will allocate
4406 space appropriately, and will not copy the data onto the
4407 stack, exactly as we desire.
4409 This is due to locate_and_pad_parm being called in
4410 expand_call whenever reg_parm_stack_space > 0, which
4411 while benefical to our example here, would seem to be
4412 in error from what had been intended. Ho hum... -- r~ */
4420 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
4424 /* On incoming, we don't need to know that the value
4425 is passed in %f0 and %i0, and it confuses other parts
4426 causing needless spillage even on the simplest cases. */
4430 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
4431 + (regno - SPARC_FP_ARG_FIRST) / 2);
4433 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4434 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
4436 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4440 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4441 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4442 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4446 else if (type && TREE_CODE (type) == RECORD_TYPE)
4448 /* Structures up to 16 bytes in size are passed in arg slots on the
4449 stack and are promoted to registers where possible. */
4451 if (int_size_in_bytes (type) > 16)
4452 abort (); /* shouldn't get here */
4454 return function_arg_record_value (type, mode, slotno, named, regbase);
4456 else if (type && TREE_CODE (type) == UNION_TYPE)
4458 enum machine_mode mode;
4459 int bytes = int_size_in_bytes (type);
4464 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4465 reg = gen_rtx_REG (mode, regno);
4469 /* Scalar or complex int. */
4470 reg = gen_rtx_REG (mode, regno);
4476 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4477 For an arg passed partly in registers and partly in memory,
4478 this is the number of registers used.
4479 For args passed entirely in registers or entirely in memory, zero.
4481 Any arg that starts in the first 6 regs but won't entirely fit in them
4482 needs partial registers on v8. On v9, structures with integer
4483 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4484 values that begin in the last fp reg [where "last fp reg" varies with the
4485 mode] will be split between that reg and memory. */
4488 function_arg_partial_nregs (cum, mode, type, named)
4489 const CUMULATIVE_ARGS *cum;
4490 enum machine_mode mode;
4494 int slotno, regno, padding;
4496 /* We pass 0 for incoming_p here, it doesn't matter. */
4497 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4504 if ((slotno + (mode == BLKmode
4505 ? ROUND_ADVANCE (int_size_in_bytes (type))
4506 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
4507 > NPARM_REGS (SImode))
4508 return NPARM_REGS (SImode) - slotno;
4513 if (type && AGGREGATE_TYPE_P (type))
4515 int size = int_size_in_bytes (type);
4516 int align = TYPE_ALIGN (type);
4519 slotno += slotno & 1;
4520 if (size > 8 && size <= 16
4521 && slotno == SPARC_INT_ARG_MAX - 1)
4524 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
4525 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4528 if (GET_MODE_ALIGNMENT (mode) == 128)
4530 slotno += slotno & 1;
4531 if (slotno == SPARC_INT_ARG_MAX - 2)
4536 if (slotno == SPARC_INT_ARG_MAX - 1)
4540 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4542 if (GET_MODE_ALIGNMENT (mode) == 128)
4543 slotno += slotno & 1;
4544 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
4552 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
4553 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
4554 quad-precision floats by invisible reference.
4555 v9: Aggregates greater than 16 bytes are passed by reference.
4556 For Pascal, also pass arrays by reference. */
4559 function_arg_pass_by_reference (cum, mode, type, named)
4560 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
4561 enum machine_mode mode;
4563 int named ATTRIBUTE_UNUSED;
4567 return ((type && AGGREGATE_TYPE_P (type))
4568 || mode == TFmode || mode == TCmode);
4572 return ((type && TREE_CODE (type) == ARRAY_TYPE)
4573 /* Consider complex values as aggregates, so care for TCmode. */
4574 || GET_MODE_SIZE (mode) > 16
4575 || (type && AGGREGATE_TYPE_P (type)
4576 && int_size_in_bytes (type) > 16));
4580 /* Handle the FUNCTION_ARG_ADVANCE macro.
4581 Update the data in CUM to advance over an argument
4582 of mode MODE and data type TYPE.
4583 TYPE is null for libcalls where that information may not be available. */
4586 function_arg_advance (cum, mode, type, named)
4587 CUMULATIVE_ARGS *cum;
4588 enum machine_mode mode;
4592 int slotno, regno, padding;
4594 /* We pass 0 for incoming_p here, it doesn't matter. */
4595 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4597 /* If register required leading padding, add it. */
4599 cum->words += padding;
4603 cum->words += (mode != BLKmode
4604 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4605 : ROUND_ADVANCE (int_size_in_bytes (type)));
4609 if (type && AGGREGATE_TYPE_P (type))
4611 int size = int_size_in_bytes (type);
4615 else if (size <= 16)
4617 else /* passed by reference */
4620 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
4624 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4626 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
4630 cum->words += (mode != BLKmode
4631 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4632 : ROUND_ADVANCE (int_size_in_bytes (type)));
4637 /* Handle the FUNCTION_ARG_PADDING macro.
4638 For the 64 bit ABI structs are always stored left shifted in their
4642 function_arg_padding (mode, type)
4643 enum machine_mode mode;
4646 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
4649 /* This is the default definition. */
4650 return (! BYTES_BIG_ENDIAN
4653 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
4654 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
4655 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
4656 ? downward : upward));
4659 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
4660 For v9, function return values are subject to the same rules as arguments,
4661 except that up to 32-bytes may be returned in registers. */
4664 function_value (type, mode, incoming_p)
4666 enum machine_mode mode;
4670 int regbase = (incoming_p
4671 ? SPARC_OUTGOING_INT_ARG_FIRST
4672 : SPARC_INCOMING_INT_ARG_FIRST);
4674 if (TARGET_ARCH64 && type)
4676 if (TREE_CODE (type) == RECORD_TYPE)
4678 /* Structures up to 32 bytes in size are passed in registers,
4679 promoted to fp registers where possible. */
4681 if (int_size_in_bytes (type) > 32)
4682 abort (); /* shouldn't get here */
4684 return function_arg_record_value (type, mode, 0, 1, regbase);
4686 else if (AGGREGATE_TYPE_P (type))
4688 /* All other aggregate types are passed in an integer register
4689 in a mode corresponding to the size of the type. */
4690 HOST_WIDE_INT bytes = int_size_in_bytes (type);
4695 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4700 && GET_MODE_CLASS (mode) == MODE_INT
4701 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
4702 && type && ! AGGREGATE_TYPE_P (type))
4706 regno = BASE_RETURN_VALUE_REG (mode);
4708 regno = BASE_OUTGOING_VALUE_REG (mode);
4710 return gen_rtx_REG (mode, regno);
4713 /* Do what is necessary for `va_start'. We look at the current function
4714 to determine if stdarg or varargs is used and return the address of
4715 the first unnamed parameter. */
4718 sparc_builtin_saveregs ()
4720 int first_reg = current_function_args_info.words;
4724 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
4725 emit_move_insn (gen_rtx_MEM (word_mode,
4726 gen_rtx_PLUS (Pmode,
4728 GEN_INT (STACK_POINTER_OFFSET
4729 + UNITS_PER_WORD * regno))),
4730 gen_rtx_REG (word_mode,
4731 BASE_INCOMING_ARG_REG (word_mode) + regno));
4733 address = gen_rtx_PLUS (Pmode,
4735 GEN_INT (STACK_POINTER_OFFSET
4736 + UNITS_PER_WORD * first_reg));
4738 if (current_function_check_memory_usage
4739 && first_reg < NPARM_REGS (word_mode))
4740 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4742 GEN_INT (UNITS_PER_WORD
4743 * (NPARM_REGS (word_mode) - first_reg)),
4744 TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW),
4745 TYPE_MODE (integer_type_node));
4750 /* Implement `va_start' for varargs and stdarg. */
4753 sparc_va_start (stdarg_p, valist, nextarg)
4754 int stdarg_p ATTRIBUTE_UNUSED;
4758 nextarg = expand_builtin_saveregs ();
4759 std_expand_builtin_va_start (1, valist, nextarg);
4762 /* Implement `va_arg'. */
4765 sparc_va_arg (valist, type)
4768 HOST_WIDE_INT size, rsize, align;
4773 /* Round up sizeof(type) to a word. */
4774 size = int_size_in_bytes (type);
4775 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4780 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
4781 align = 2 * UNITS_PER_WORD;
4783 if (AGGREGATE_TYPE_P (type))
4788 size = rsize = UNITS_PER_WORD;
4796 if (AGGREGATE_TYPE_P (type)
4797 || TYPE_MODE (type) == TFmode
4798 || TYPE_MODE (type) == TCmode)
4801 size = rsize = UNITS_PER_WORD;
4808 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4809 build_int_2 (align - 1, 0)));
4810 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
4811 build_int_2 (-align, -1)));
4814 addr = incr = save_expr (incr);
4815 if (BYTES_BIG_ENDIAN && size < rsize)
4817 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4818 build_int_2 (rsize - size, 0)));
4820 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4821 build_int_2 (rsize, 0)));
4823 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
4824 TREE_SIDE_EFFECTS (incr) = 1;
4825 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
4827 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
4829 /* If the address isn't aligned properly for the type,
4830 we may need to copy to a temporary.
4831 FIXME: This is inefficient. Usually we can do this
4834 && TYPE_ALIGN (type) > BITS_PER_WORD
4837 /* FIXME: We really need to specify that the temporary is live
4838 for the whole function because expand_builtin_va_arg wants
4839 the alias set to be get_varargs_alias_set (), but in this
4840 case the alias set is that for TYPE and if the memory gets
4841 reused it will be reused with alias set TYPE. */
4842 rtx tmp = assign_temp (type, 0, 1, 0);
4845 addr_rtx = force_reg (Pmode, addr_rtx);
4846 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
4847 MEM_ALIAS_SET (addr_rtx) = get_varargs_alias_set ();
4848 tmp = shallow_copy_rtx (tmp);
4849 PUT_MODE (tmp, BLKmode);
4850 MEM_ALIAS_SET (tmp) = 0;
4852 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
4854 if (dest_addr != NULL_RTX)
4855 addr_rtx = dest_addr;
4857 addr_rtx = XCEXP (tmp, 0, MEM);
4862 addr_rtx = force_reg (Pmode, addr_rtx);
4863 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
4864 MEM_ALIAS_SET (addr_rtx) = get_varargs_alias_set ();
4870 /* Return the string to output a conditional branch to LABEL, which is
4871 the operand number of the label. OP is the conditional expression.
4872 XEXP (OP, 0) is assumed to be a condition code register (integer or
4873 floating point) and its mode specifies what kind of comparison we made.
4875 REVERSED is non-zero if we should reverse the sense of the comparison.
4877 ANNUL is non-zero if we should generate an annulling branch.
4879 NOOP is non-zero if we have to follow this branch by a noop.
4881 INSN, if set, is the insn. */
4884 output_cbranch (op, label, reversed, annul, noop, insn)
4887 int reversed, annul, noop;
4890 static char string[32];
4891 enum rtx_code code = GET_CODE (op);
4892 rtx cc_reg = XEXP (op, 0);
4893 enum machine_mode mode = GET_MODE (cc_reg);
4894 static char v8_labelno[] = "%lX";
4895 static char v9_icc_labelno[] = "%%icc, %lX";
4896 static char v9_xcc_labelno[] = "%%xcc, %lX";
4897 static char v9_fcc_labelno[] = "%%fccX, %lY";
4900 int labeloff, spaces = 8;
4904 /* Reversal of FP compares takes care -- an ordered compare
4905 becomes an unordered compare and vice versa. */
4906 if (mode == CCFPmode || mode == CCFPEmode)
4907 code = reverse_condition_maybe_unordered (code);
4909 code = reverse_condition (code);
4912 /* Start by writing the branch condition. */
4913 if (mode == CCFPmode || mode == CCFPEmode)
4964 /* ??? !v9: FP branches cannot be preceded by another floating point
4965 insn. Because there is currently no concept of pre-delay slots,
4966 we can fix this only by always emitting a nop before a floating
4971 strcpy (string, "nop\n\t");
4972 strcat (string, branch);
4985 if (mode == CC_NOOVmode)
4997 if (mode == CC_NOOVmode)
5018 strcpy (string, branch);
5020 spaces -= strlen (branch);
5022 /* Now add the annulling, the label, and a possible noop. */
5025 strcat (string, ",a");
5032 labelno = v8_labelno;
5038 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
5041 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
5046 if (mode == CCFPmode || mode == CCFPEmode)
5049 labelno = v9_fcc_labelno;
5050 /* Set the char indicating the number of the fcc reg to use. */
5051 labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5053 else if (mode == CCXmode || mode == CCX_NOOVmode)
5054 labelno = v9_xcc_labelno;
5056 labelno = v9_icc_labelno;
5058 /* Set the char indicating the number of the operand containing the
5060 labelno[labeloff] = label + '0';
5062 strcat (string, "\t");
5064 strcat (string, " ");
5065 strcat (string, labelno);
5068 strcat (string, "\n\tnop");
5073 /* Emit a library call comparison between floating point X and Y.
5074 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5075 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5076 values as arguments instead of the TFmode registers themselves,
5077 that's why we cannot call emit_float_lib_cmp. */
5079 sparc_emit_float_lib_cmp (x, y, comparison)
5081 enum rtx_code comparison;
5084 rtx slot0, slot1, result, tem, tem2;
5085 enum machine_mode mode;
5090 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
5094 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
5098 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
5102 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
5106 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
5110 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
5121 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
5131 if (GET_CODE (x) != MEM)
5133 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5134 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
5139 if (GET_CODE (y) != MEM)
5141 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5142 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
5147 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), 1,
5149 XEXP (slot0, 0), Pmode,
5150 XEXP (slot1, 0), Pmode);
5156 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), 1,
5158 x, TFmode, y, TFmode);
5164 /* Immediately move the result of the libcall into a pseudo
5165 register so reload doesn't clobber the value if it needs
5166 the return register for a spill reg. */
5167 result = gen_reg_rtx (mode);
5168 emit_move_insn (result, hard_libcall_value (mode));
5173 emit_cmp_insn (result, const0_rtx, NE,
5174 NULL_RTX, mode, 0, 0);
5178 emit_cmp_insn (result, GEN_INT(3),
5179 (comparison == UNORDERED) ? EQ : NE,
5180 NULL_RTX, mode, 0, 0);
5184 emit_cmp_insn (result, const1_rtx,
5185 (comparison == UNGT) ? GT : NE,
5186 NULL_RTX, mode, 0, 0);
5189 emit_cmp_insn (result, const2_rtx, NE,
5190 NULL_RTX, mode, 0, 0);
5193 tem = gen_reg_rtx (mode);
5195 emit_insn (gen_andsi3 (tem, result, const1_rtx));
5197 emit_insn (gen_anddi3 (tem, result, const1_rtx));
5198 emit_cmp_insn (tem, const0_rtx, NE,
5199 NULL_RTX, mode, 0, 0);
5203 tem = gen_reg_rtx (mode);
5205 emit_insn (gen_addsi3 (tem, result, const1_rtx));
5207 emit_insn (gen_adddi3 (tem, result, const1_rtx));
5208 tem2 = gen_reg_rtx (mode);
5210 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
5212 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
5213 emit_cmp_insn (tem2, const0_rtx,
5214 (comparison == UNEQ) ? EQ : NE,
5215 NULL_RTX, mode, 0, 0);
5220 /* Return the string to output a conditional branch to LABEL, testing
5221 register REG. LABEL is the operand number of the label; REG is the
5222 operand number of the reg. OP is the conditional expression. The mode
5223 of REG says what kind of comparison we made.
5225 REVERSED is non-zero if we should reverse the sense of the comparison.
5227 ANNUL is non-zero if we should generate an annulling branch.
5229 NOOP is non-zero if we have to follow this branch by a noop. */
5232 output_v9branch (op, reg, label, reversed, annul, noop, insn)
5235 int reversed, annul, noop;
5238 static char string[20];
5239 enum rtx_code code = GET_CODE (op);
5240 enum machine_mode mode = GET_MODE (XEXP (op, 0));
5241 static char labelno[] = "%X, %lX";
5245 /* If not floating-point or if EQ or NE, we can just reverse the code. */
5247 code = reverse_condition (code), reversed = 0;
5249 /* Only 64 bit versions of these instructions exist. */
5253 /* Start by writing the branch condition. */
5258 strcpy (string, "brnz");
5263 strcpy (string, "brz");
5268 strcpy (string, "brgez");
5273 strcpy (string, "brlz");
5278 strcpy (string, "brlez");
5283 strcpy (string, "brgz");
5291 /* Now add the annulling, reg, label, and nop. */
5294 strcat (string, ",a");
5298 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
5301 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
5305 labelno[1] = reg + '0';
5306 labelno[6] = label + '0';
5308 strcat (string, "\t");
5310 strcat (string, " ");
5311 strcat (string, labelno);
5314 strcat (string, "\n\tnop");
5319 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
5320 Such instructions cannot be used in the delay slot of return insn on v9.
5321 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
5325 epilogue_renumber (where, test)
5326 register rtx *where;
5329 register const char *fmt;
5331 register enum rtx_code code;
5336 code = GET_CODE (*where);
5341 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
5343 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
5344 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
5356 fmt = GET_RTX_FORMAT (code);
5358 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5363 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5364 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
5367 else if (fmt[i] == 'e'
5368 && epilogue_renumber (&(XEXP (*where, i)), test))
5374 /* Output assembler code to return from a function. */
5377 output_return (operands)
5380 rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0;
5384 operands[0] = leaf_label;
5387 else if (current_function_uses_only_leaf_regs)
5389 /* No delay slot in a leaf function. */
5393 /* If we didn't allocate a frame pointer for the current function,
5394 the stack pointer might have been adjusted. Output code to
5397 operands[0] = GEN_INT (actual_fsize);
5399 /* Use sub of negated value in first two cases instead of add to
5400 allow actual_fsize == 4096. */
5402 if (actual_fsize <= 4096)
5404 if (SKIP_CALLERS_UNIMP_P)
5405 return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
5407 return "retl\n\tsub\t%%sp, -%0, %%sp";
5409 else if (actual_fsize <= 8192)
5411 operands[0] = GEN_INT (actual_fsize - 4096);
5412 if (SKIP_CALLERS_UNIMP_P)
5413 return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
5415 return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
5417 else if (SKIP_CALLERS_UNIMP_P)
5419 if ((actual_fsize & 0x3ff) != 0)
5420 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
5422 return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
5426 if ((actual_fsize & 0x3ff) != 0)
5427 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tretl\n\tadd\t%%sp, %%g1, %%sp";
5429 return "sethi\t%%hi(%a0), %%g1\n\tretl\n\tadd\t%%sp, %%g1, %%sp";
5436 epilogue_renumber (&SET_DEST (PATTERN (delay)), 0);
5437 epilogue_renumber (&SET_SRC (PATTERN (delay)), 0);
5439 if (SKIP_CALLERS_UNIMP_P)
5440 return "return\t%%i7+12%#";
5442 return "return\t%%i7+8%#";
5448 if (SKIP_CALLERS_UNIMP_P)
5449 return "jmp\t%%i7+12\n\trestore";
5451 return "ret\n\trestore";
5455 /* Leaf functions and non-leaf functions have different needs. */
5458 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
5461 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
5463 static int *reg_alloc_orders[] = {
5464 reg_leaf_alloc_order,
5465 reg_nonleaf_alloc_order};
5468 order_regs_for_local_alloc ()
5470 static int last_order_nonleaf = 1;
5472 if (regs_ever_live[15] != last_order_nonleaf)
5474 last_order_nonleaf = !last_order_nonleaf;
5475 memcpy ((char *) reg_alloc_order,
5476 (char *) reg_alloc_orders[last_order_nonleaf],
5477 FIRST_PSEUDO_REGISTER * sizeof (int));
5481 /* Return 1 if REG and MEM are legitimate enough to allow the various
5482 mem<-->reg splits to be run. */
5485 sparc_splitdi_legitimate (reg, mem)
5489 /* Punt if we are here by mistake. */
5490 if (! reload_completed)
5493 /* We must have an offsettable memory reference. */
5494 if (! offsettable_memref_p (mem))
5497 /* If we have legitimate args for ldd/std, we do not want
5498 the split to happen. */
5499 if ((REGNO (reg) % 2) == 0
5500 && mem_min_alignment (mem, 8))
5507 /* Return 1 if x and y are some kind of REG and they refer to
5508 different hard registers. This test is guarenteed to be
5509 run after reload. */
5512 sparc_absnegfloat_split_legitimate (x, y)
5515 if (GET_CODE (x) == SUBREG)
5516 x = alter_subreg (x);
5517 if (GET_CODE (x) != REG)
5519 if (GET_CODE (y) == SUBREG)
5520 y = alter_subreg (y);
5521 if (GET_CODE (y) != REG)
5523 if (REGNO (x) == REGNO (y))
5528 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
5529 This makes them candidates for using ldd and std insns.
5531 Note reg1 and reg2 *must* be hard registers. */
5534 registers_ok_for_ldd_peep (reg1, reg2)
5537 /* We might have been passed a SUBREG. */
5538 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
5541 if (REGNO (reg1) % 2 != 0)
5544 /* Integer ldd is deprecated in SPARC V9 */
5545 if (TARGET_V9 && REGNO (reg1) < 32)
5548 return (REGNO (reg1) == REGNO (reg2) - 1);
5551 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
5554 This can only happen when addr1 and addr2 are consecutive memory
5555 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
5556 64 bit boundary (addr1 % 8 == 0).
5558 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
5559 registers are assumed to *never* be properly aligned and are
5562 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
5563 need only check that the offset for addr1 % 8 == 0. */
5566 addrs_ok_for_ldd_peep (addr1, addr2)
5571 /* Extract a register number and offset (if used) from the first addr. */
5572 if (GET_CODE (addr1) == PLUS)
5574 /* If not a REG, return zero. */
5575 if (GET_CODE (XEXP (addr1, 0)) != REG)
5579 reg1 = REGNO (XEXP (addr1, 0));
5580 /* The offset must be constant! */
5581 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
5583 offset1 = INTVAL (XEXP (addr1, 1));
5586 else if (GET_CODE (addr1) != REG)
5590 reg1 = REGNO (addr1);
5591 /* This was a simple (mem (reg)) expression. Offset is 0. */
5595 /* Make sure the second address is a (mem (plus (reg) (const_int). */
5596 if (GET_CODE (addr2) != PLUS)
5599 if (GET_CODE (XEXP (addr2, 0)) != REG
5600 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
5603 /* Only %fp and %sp are allowed. Additionally both addresses must
5604 use the same register. */
5605 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
5608 if (reg1 != REGNO (XEXP (addr2, 0)))
5611 /* The first offset must be evenly divisible by 8 to ensure the
5612 address is 64 bit aligned. */
5613 if (offset1 % 8 != 0)
5616 /* The offset for the second addr must be 4 more than the first addr. */
5617 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
5620 /* All the tests passed. addr1 and addr2 are valid for ldd and std
5625 /* Return 1 if reg is a pseudo, or is the first register in
5626 a hard register pair. This makes it a candidate for use in
5627 ldd and std insns. */
5630 register_ok_for_ldd (reg)
5633 /* We might have been passed a SUBREG. */
5634 if (GET_CODE (reg) != REG)
5637 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
5638 return (REGNO (reg) % 2 == 0);
5643 /* Print operand X (an rtx) in assembler syntax to file FILE.
5644 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
5645 For `%' followed by punctuation, CODE is the punctuation and X is null. */
5648 print_operand (file, x, code)
5656 /* Output a 'nop' if there's nothing for the delay slot. */
5657 if (dbr_sequence_length () == 0)
5658 fputs ("\n\t nop", file);
5661 /* Output an annul flag if there's nothing for the delay slot and we
5662 are optimizing. This is always used with '(' below. */
5663 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
5664 this is a dbx bug. So, we only do this when optimizing. */
5665 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
5666 Always emit a nop in case the next instruction is a branch. */
5667 if (dbr_sequence_length () == 0
5668 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
5672 /* Output a 'nop' if there's nothing for the delay slot and we are
5673 not optimizing. This is always used with '*' above. */
5674 if (dbr_sequence_length () == 0
5675 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
5676 fputs ("\n\t nop", file);
5679 /* Output the Embedded Medium/Anywhere code model base register. */
5680 fputs (EMBMEDANY_BASE_REG, file);
5683 /* Print out what we are using as the frame pointer. This might
5684 be %fp, or might be %sp+offset. */
5685 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
5686 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
5689 /* Adjust the operand to take into account a RESTORE operation. */
5690 if (GET_CODE (x) == CONST_INT)
5692 else if (GET_CODE (x) != REG)
5693 output_operand_lossage ("Invalid %%Y operand");
5694 else if (REGNO (x) < 8)
5695 fputs (reg_names[REGNO (x)], file);
5696 else if (REGNO (x) >= 24 && REGNO (x) < 32)
5697 fputs (reg_names[REGNO (x)-16], file);
5699 output_operand_lossage ("Invalid %%Y operand");
5702 /* Print out the low order register name of a register pair. */
5703 if (WORDS_BIG_ENDIAN)
5704 fputs (reg_names[REGNO (x)+1], file);
5706 fputs (reg_names[REGNO (x)], file);
5709 /* Print out the high order register name of a register pair. */
5710 if (WORDS_BIG_ENDIAN)
5711 fputs (reg_names[REGNO (x)], file);
5713 fputs (reg_names[REGNO (x)+1], file);
5716 /* Print out the second register name of a register pair or quad.
5717 I.e., R (%o0) => %o1. */
5718 fputs (reg_names[REGNO (x)+1], file);
5721 /* Print out the third register name of a register quad.
5722 I.e., S (%o0) => %o2. */
5723 fputs (reg_names[REGNO (x)+2], file);
5726 /* Print out the fourth register name of a register quad.
5727 I.e., T (%o0) => %o3. */
5728 fputs (reg_names[REGNO (x)+3], file);
5731 /* Print a condition code register. */
5732 if (REGNO (x) == SPARC_ICC_REG)
5734 /* We don't handle CC[X]_NOOVmode because they're not supposed
5736 if (GET_MODE (x) == CCmode)
5737 fputs ("%icc", file);
5738 else if (GET_MODE (x) == CCXmode)
5739 fputs ("%xcc", file);
5744 /* %fccN register */
5745 fputs (reg_names[REGNO (x)], file);
5748 /* Print the operand's address only. */
5749 output_address (XEXP (x, 0));
5752 /* In this case we need a register. Use %g0 if the
5753 operand is const0_rtx. */
5755 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
5757 fputs ("%g0", file);
5764 switch (GET_CODE (x))
5766 case IOR: fputs ("or", file); break;
5767 case AND: fputs ("and", file); break;
5768 case XOR: fputs ("xor", file); break;
5769 default: output_operand_lossage ("Invalid %%A operand");
5774 switch (GET_CODE (x))
5776 case IOR: fputs ("orn", file); break;
5777 case AND: fputs ("andn", file); break;
5778 case XOR: fputs ("xnor", file); break;
5779 default: output_operand_lossage ("Invalid %%B operand");
5783 /* These are used by the conditional move instructions. */
5787 enum rtx_code rc = GET_CODE (x);
5791 enum machine_mode mode = GET_MODE (XEXP (x, 0));
5792 if (mode == CCFPmode || mode == CCFPEmode)
5793 rc = reverse_condition_maybe_unordered (GET_CODE (x));
5795 rc = reverse_condition (GET_CODE (x));
5799 case NE: fputs ("ne", file); break;
5800 case EQ: fputs ("e", file); break;
5801 case GE: fputs ("ge", file); break;
5802 case GT: fputs ("g", file); break;
5803 case LE: fputs ("le", file); break;
5804 case LT: fputs ("l", file); break;
5805 case GEU: fputs ("geu", file); break;
5806 case GTU: fputs ("gu", file); break;
5807 case LEU: fputs ("leu", file); break;
5808 case LTU: fputs ("lu", file); break;
5809 case LTGT: fputs ("lg", file); break;
5810 case UNORDERED: fputs ("u", file); break;
5811 case ORDERED: fputs ("o", file); break;
5812 case UNLT: fputs ("ul", file); break;
5813 case UNLE: fputs ("ule", file); break;
5814 case UNGT: fputs ("ug", file); break;
5815 case UNGE: fputs ("uge", file); break;
5816 case UNEQ: fputs ("ue", file); break;
5817 default: output_operand_lossage (code == 'c'
5818 ? "Invalid %%c operand"
5819 : "Invalid %%C operand");
5824 /* These are used by the movr instruction pattern. */
5828 enum rtx_code rc = (code == 'd'
5829 ? reverse_condition (GET_CODE (x))
5833 case NE: fputs ("ne", file); break;
5834 case EQ: fputs ("e", file); break;
5835 case GE: fputs ("gez", file); break;
5836 case LT: fputs ("lz", file); break;
5837 case LE: fputs ("lez", file); break;
5838 case GT: fputs ("gz", file); break;
5839 default: output_operand_lossage (code == 'd'
5840 ? "Invalid %%d operand"
5841 : "Invalid %%D operand");
5848 /* Print a sign-extended character. */
5849 int i = INTVAL (x) & 0xff;
5852 fprintf (file, "%d", i);
5857 /* Operand must be a MEM; write its address. */
5858 if (GET_CODE (x) != MEM)
5859 output_operand_lossage ("Invalid %%f operand");
5860 output_address (XEXP (x, 0));
5864 /* Do nothing special. */
5868 /* Undocumented flag. */
5869 output_operand_lossage ("invalid operand output code");
5872 if (GET_CODE (x) == REG)
5873 fputs (reg_names[REGNO (x)], file);
5874 else if (GET_CODE (x) == MEM)
5877 /* Poor Sun assembler doesn't understand absolute addressing. */
5878 if (CONSTANT_P (XEXP (x, 0)))
5879 fputs ("%g0+", file);
5880 output_address (XEXP (x, 0));
5883 else if (GET_CODE (x) == HIGH)
5885 fputs ("%hi(", file);
5886 output_addr_const (file, XEXP (x, 0));
5889 else if (GET_CODE (x) == LO_SUM)
5891 print_operand (file, XEXP (x, 0), 0);
5892 if (TARGET_CM_MEDMID)
5893 fputs ("+%l44(", file);
5895 fputs ("+%lo(", file);
5896 output_addr_const (file, XEXP (x, 1));
5899 else if (GET_CODE (x) == CONST_DOUBLE
5900 && (GET_MODE (x) == VOIDmode
5901 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
5903 if (CONST_DOUBLE_HIGH (x) == 0)
5904 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
5905 else if (CONST_DOUBLE_HIGH (x) == -1
5906 && CONST_DOUBLE_LOW (x) < 0)
5907 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
5909 output_operand_lossage ("long long constant not a valid immediate operand");
5911 else if (GET_CODE (x) == CONST_DOUBLE)
5912 output_operand_lossage ("floating point constant not a valid immediate operand");
5913 else { output_addr_const (file, x); }
5916 /* This function outputs assembler code for VALUE to FILE, where VALUE is
5917 a 64 bit (DImode) value. */
5919 /* ??? If there is a 64 bit counterpart to .word that the assembler
5920 understands, then using that would simply this code greatly. */
5921 /* ??? We only output .xword's for symbols and only then in environments
5922 where the assembler can handle them. */
5925 output_double_int (file, value)
5929 if (GET_CODE (value) == CONST_INT)
5931 /* ??? This has endianness issues. */
5932 #if HOST_BITS_PER_WIDE_INT == 64
5933 HOST_WIDE_INT xword = INTVAL (value);
5934 HOST_WIDE_INT high, low;
5936 high = (xword >> 32) & 0xffffffff;
5937 low = xword & 0xffffffff;
5938 ASM_OUTPUT_INT (file, GEN_INT (high));
5939 ASM_OUTPUT_INT (file, GEN_INT (low));
5941 if (INTVAL (value) < 0)
5942 ASM_OUTPUT_INT (file, constm1_rtx);
5944 ASM_OUTPUT_INT (file, const0_rtx);
5945 ASM_OUTPUT_INT (file, value);
5948 else if (GET_CODE (value) == CONST_DOUBLE)
5950 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value)));
5951 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value)));
5953 else if (GET_CODE (value) == SYMBOL_REF
5954 || GET_CODE (value) == CONST
5955 || GET_CODE (value) == PLUS
5956 || (TARGET_ARCH64 &&
5957 (GET_CODE (value) == LABEL_REF
5958 || GET_CODE (value) == CODE_LABEL
5959 || GET_CODE (value) == MINUS)))
5963 ASM_OUTPUT_INT (file, const0_rtx);
5964 ASM_OUTPUT_INT (file, value);
5968 fprintf (file, "\t%s\t", ASM_LONGLONG);
5969 output_addr_const (file, value);
5970 fprintf (file, "\n");
5977 /* Return the value of a code used in the .proc pseudo-op that says
5978 what kind of result this function returns. For non-C types, we pick
5979 the closest C type. */
5981 #ifndef CHAR_TYPE_SIZE
5982 #define CHAR_TYPE_SIZE BITS_PER_UNIT
5985 #ifndef SHORT_TYPE_SIZE
5986 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
5989 #ifndef INT_TYPE_SIZE
5990 #define INT_TYPE_SIZE BITS_PER_WORD
5993 #ifndef LONG_TYPE_SIZE
5994 #define LONG_TYPE_SIZE BITS_PER_WORD
5997 #ifndef LONG_LONG_TYPE_SIZE
5998 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6001 #ifndef FLOAT_TYPE_SIZE
6002 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6005 #ifndef DOUBLE_TYPE_SIZE
6006 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6009 #ifndef LONG_DOUBLE_TYPE_SIZE
6010 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6014 sparc_type_code (type)
6017 register unsigned long qualifiers = 0;
6018 register unsigned shift;
6020 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6021 setting more, since some assemblers will give an error for this. Also,
6022 we must be careful to avoid shifts of 32 bits or more to avoid getting
6023 unpredictable results. */
6025 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
6027 switch (TREE_CODE (type))
6033 qualifiers |= (3 << shift);
6038 qualifiers |= (2 << shift);
6042 case REFERENCE_TYPE:
6044 qualifiers |= (1 << shift);
6048 return (qualifiers | 8);
6051 case QUAL_UNION_TYPE:
6052 return (qualifiers | 9);
6055 return (qualifiers | 10);
6058 return (qualifiers | 16);
6061 /* If this is a range type, consider it to be the underlying
6063 if (TREE_TYPE (type) != 0)
6066 /* Carefully distinguish all the standard types of C,
6067 without messing up if the language is not C. We do this by
6068 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6069 look at both the names and the above fields, but that's redundant.
6070 Any type whose size is between two C types will be considered
6071 to be the wider of the two types. Also, we do not have a
6072 special code to use for "long long", so anything wider than
6073 long is treated the same. Note that we can't distinguish
6074 between "int" and "long" in this code if they are the same
6075 size, but that's fine, since neither can the assembler. */
6077 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
6078 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
6080 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
6081 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
6083 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
6084 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
6087 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
6090 /* If this is a range type, consider it to be the underlying
6092 if (TREE_TYPE (type) != 0)
6095 /* Carefully distinguish all the standard types of C,
6096 without messing up if the language is not C. */
6098 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
6099 return (qualifiers | 6);
6102 return (qualifiers | 7);
6104 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
6105 /* ??? We need to distinguish between double and float complex types,
6106 but I don't know how yet because I can't reach this code from
6107 existing front-ends. */
6108 return (qualifiers | 7); /* Who knows? */
6110 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
6111 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
6112 case FILE_TYPE: /* GNU Pascal FILE type. */
6113 case SET_TYPE: /* GNU Pascal SET type. */
6114 case LANG_TYPE: /* ? */
6118 abort (); /* Not a type! */
6125 /* Nested function support. */
6127 /* Emit RTL insns to initialize the variable parts of a trampoline.
6128 FNADDR is an RTX for the address of the function's pure code.
6129 CXT is an RTX for the static chain value for the function.
6131 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6132 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6133 (to store insns). This is a bit excessive. Perhaps a different
6134 mechanism would be better here.
6136 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6139 sparc_initialize_trampoline (tramp, fnaddr, cxt)
6140 rtx tramp, fnaddr, cxt;
6142 /* SPARC 32 bit trampoline:
6145 sethi %hi(static), %g2
6147 or %g2, %lo(static), %g2
6149 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6150 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6152 #ifdef TRANSFER_FROM_TRAMPOLINE
6153 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6154 0, VOIDmode, 1, tramp, Pmode);
6157 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
6158 expand_binop (SImode, ior_optab,
6159 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
6160 size_int (10), 0, 1),
6161 GEN_INT (0x03000000),
6162 NULL_RTX, 1, OPTAB_DIRECT));
6164 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6165 expand_binop (SImode, ior_optab,
6166 expand_shift (RSHIFT_EXPR, SImode, cxt,
6167 size_int (10), 0, 1),
6168 GEN_INT (0x05000000),
6169 NULL_RTX, 1, OPTAB_DIRECT));
6171 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6172 expand_binop (SImode, ior_optab,
6173 expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX),
6174 GEN_INT (0x81c06000),
6175 NULL_RTX, 1, OPTAB_DIRECT));
6177 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6178 expand_binop (SImode, ior_optab,
6179 expand_and (cxt, GEN_INT (0x3ff), NULL_RTX),
6180 GEN_INT (0x8410a000),
6181 NULL_RTX, 1, OPTAB_DIRECT));
6183 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
6184 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6185 aligned on a 16 byte boundary so one flush clears it all. */
6186 if (sparc_cpu != PROCESSOR_ULTRASPARC)
6187 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
6188 plus_constant (tramp, 8)))));
6191 /* The 64 bit version is simpler because it makes more sense to load the
6192 values as "immediate" data out of the trampoline. It's also easier since
6193 we can read the PC without clobbering a register. */
6196 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
6197 rtx tramp, fnaddr, cxt;
6199 #ifdef TRANSFER_FROM_TRAMPOLINE
6200 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6201 0, VOIDmode, 1, tramp, Pmode);
6212 emit_move_insn (gen_rtx_MEM (SImode, tramp),
6213 GEN_INT (0x83414000));
6214 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6215 GEN_INT (0xca586018));
6216 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6217 GEN_INT (0x81c14000));
6218 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6219 GEN_INT (0xca586010));
6220 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
6221 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
6222 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
6224 if (sparc_cpu != PROCESSOR_ULTRASPARC)
6225 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
6228 /* Subroutines to support a flat (single) register window calling
6231 /* Single-register window sparc stack frames look like:
6233 Before call After call
6234 +-----------------------+ +-----------------------+
6236 mem | caller's temps. | | caller's temps. |
6238 +-----------------------+ +-----------------------+
6240 | arguments on stack. | | arguments on stack. |
6242 +-----------------------+FP+92->+-----------------------+
6243 | 6 words to save | | 6 words to save |
6244 | arguments passed | | arguments passed |
6245 | in registers, even | | in registers, even |
6246 | if not passed. | | if not passed. |
6247 SP+68->+-----------------------+FP+68->+-----------------------+
6248 | 1 word struct addr | | 1 word struct addr |
6249 +-----------------------+FP+64->+-----------------------+
6251 | 16 word reg save area | | 16 word reg save area |
6253 SP->+-----------------------+ FP->+-----------------------+
6255 | fp/alu reg moves |
6256 FP-16->+-----------------------+
6260 +-----------------------+
6262 | fp register save |
6264 +-----------------------+
6266 | gp register save |
6268 +-----------------------+
6270 | alloca allocations |
6272 +-----------------------+
6274 | arguments on stack |
6276 SP+92->+-----------------------+
6278 | arguments passed |
6279 | in registers, even |
6280 low | if not passed. |
6281 memory SP+68->+-----------------------+
6282 | 1 word struct addr |
6283 SP+64->+-----------------------+
6285 I 16 word reg save area |
6287 SP->+-----------------------+ */
6289 /* Structure to be filled in by sparc_flat_compute_frame_size with register
6290 save masks, and offsets for the current function. */
6292 struct sparc_frame_info
6294 unsigned long total_size; /* # bytes that the entire frame takes up. */
6295 unsigned long var_size; /* # bytes that variables take up. */
6296 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6297 unsigned long extra_size; /* # bytes of extra gunk. */
6298 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6299 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6300 unsigned long gmask; /* Mask of saved gp registers. */
6301 unsigned long fmask; /* Mask of saved fp registers. */
6302 unsigned long reg_offset; /* Offset from new sp to store regs. */
6303 int initialized; /* Nonzero if frame size already calculated. */
6306 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6307 struct sparc_frame_info current_frame_info;
6309 /* Zero structure to initialize current_frame_info. */
6310 struct sparc_frame_info zero_frame_info;
6312 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6314 #define RETURN_ADDR_REGNUM 15
6315 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
6316 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6318 #define MUST_SAVE_REGISTER(regno) \
6319 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6320 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
6321 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6323 /* Return the bytes needed to compute the frame pointer from the current
6327 sparc_flat_compute_frame_size (size)
6328 int size; /* # of var. bytes allocated. */
6331 unsigned long total_size; /* # bytes that the entire frame takes up. */
6332 unsigned long var_size; /* # bytes that variables take up. */
6333 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6334 unsigned long extra_size; /* # extra bytes. */
6335 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6336 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6337 unsigned long gmask; /* Mask of saved gp registers. */
6338 unsigned long fmask; /* Mask of saved fp registers. */
6339 unsigned long reg_offset; /* Offset to register save area. */
6340 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
6342 /* This is the size of the 16 word reg save area, 1 word struct addr
6343 area, and 4 word fp/alu register copy area. */
6344 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
6354 if (!leaf_function_p ())
6356 /* Also include the size needed for the 6 parameter registers. */
6357 args_size = current_function_outgoing_args_size + 24;
6359 total_size = var_size + args_size;
6361 /* Calculate space needed for gp registers. */
6362 for (regno = 1; regno <= 31; regno++)
6364 if (MUST_SAVE_REGISTER (regno))
6366 /* If we need to save two regs in a row, ensure there's room to bump
6367 up the address to align it to a doubleword boundary. */
6368 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
6370 if (gp_reg_size % 8 != 0)
6372 gp_reg_size += 2 * UNITS_PER_WORD;
6373 gmask |= 3 << regno;
6379 gp_reg_size += UNITS_PER_WORD;
6380 gmask |= 1 << regno;
6385 /* Calculate space needed for fp registers. */
6386 for (regno = 32; regno <= 63; regno++)
6388 if (regs_ever_live[regno] && !call_used_regs[regno])
6390 fp_reg_size += UNITS_PER_WORD;
6391 fmask |= 1 << (regno - 32);
6398 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
6399 /* Ensure save area is 8 byte aligned if we need it. */
6401 if (need_aligned_p && n != 0)
6403 total_size += 8 - n;
6404 reg_offset += 8 - n;
6406 total_size += gp_reg_size + fp_reg_size;
6409 /* If we must allocate a stack frame at all, we must also allocate
6410 room for register window spillage, so as to be binary compatible
6411 with libraries and operating systems that do not use -mflat. */
6413 total_size += extra_size;
6417 total_size = SPARC_STACK_ALIGN (total_size);
6419 /* Save other computed information. */
6420 current_frame_info.total_size = total_size;
6421 current_frame_info.var_size = var_size;
6422 current_frame_info.args_size = args_size;
6423 current_frame_info.extra_size = extra_size;
6424 current_frame_info.gp_reg_size = gp_reg_size;
6425 current_frame_info.fp_reg_size = fp_reg_size;
6426 current_frame_info.gmask = gmask;
6427 current_frame_info.fmask = fmask;
6428 current_frame_info.reg_offset = reg_offset;
6429 current_frame_info.initialized = reload_completed;
6431 /* Ok, we're done. */
6435 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
6438 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
6439 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
6440 [BASE_REG+OFFSET] will always be a valid address.
6442 WORD_OP is either "st" for save, "ld" for restore.
6443 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
6446 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
6447 doubleword_op, base_offset)
6449 const char *base_reg;
6450 unsigned int offset;
6451 unsigned long gmask;
6452 unsigned long fmask;
6453 const char *word_op;
6454 const char *doubleword_op;
6455 unsigned long base_offset;
6459 if (gmask == 0 && fmask == 0)
6462 /* Save registers starting from high to low. We've already saved the
6463 previous frame pointer and previous return address for the debugger's
6464 sake. The debugger allows us to not need a nop in the epilog if at least
6465 one register is reloaded in addition to return address. */
6469 for (regno = 1; regno <= 31; regno++)
6471 if ((gmask & (1L << regno)) != 0)
6473 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
6475 /* We can save two registers in a row. If we're not at a
6476 double word boundary, move to one.
6477 sparc_flat_compute_frame_size ensures there's room to do
6479 if (offset % 8 != 0)
6480 offset += UNITS_PER_WORD;
6482 if (word_op[0] == 's')
6484 fprintf (file, "\t%s\t%s, [%s+%d]\n",
6485 doubleword_op, reg_names[regno],
6487 if (dwarf2out_do_frame ())
6489 char *l = dwarf2out_cfi_label ();
6490 dwarf2out_reg_save (l, regno, offset + base_offset);
6492 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
6496 fprintf (file, "\t%s\t[%s+%d], %s\n",
6497 doubleword_op, base_reg, offset,
6500 offset += 2 * UNITS_PER_WORD;
6505 if (word_op[0] == 's')
6507 fprintf (file, "\t%s\t%s, [%s+%d]\n",
6508 word_op, reg_names[regno],
6510 if (dwarf2out_do_frame ())
6511 dwarf2out_reg_save ("", regno, offset + base_offset);
6514 fprintf (file, "\t%s\t[%s+%d], %s\n",
6515 word_op, base_reg, offset, reg_names[regno]);
6517 offset += UNITS_PER_WORD;
6525 for (regno = 32; regno <= 63; regno++)
6527 if ((fmask & (1L << (regno - 32))) != 0)
6529 if (word_op[0] == 's')
6531 fprintf (file, "\t%s\t%s, [%s+%d]\n",
6532 word_op, reg_names[regno],
6534 if (dwarf2out_do_frame ())
6535 dwarf2out_reg_save ("", regno, offset + base_offset);
6538 fprintf (file, "\t%s\t[%s+%d], %s\n",
6539 word_op, base_reg, offset, reg_names[regno]);
6541 offset += UNITS_PER_WORD;
6547 /* Set up the stack and frame (if desired) for the function. */
6550 sparc_flat_output_function_prologue (file, size)
6554 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
6555 unsigned long gmask = current_frame_info.gmask;
6557 sparc_output_scratch_registers (file);
6559 /* This is only for the human reader. */
6560 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
6561 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6563 current_frame_info.var_size,
6564 current_frame_info.gp_reg_size / 4,
6565 current_frame_info.fp_reg_size / 4,
6566 current_function_outgoing_args_size,
6567 current_frame_info.extra_size);
6569 size = SPARC_STACK_ALIGN (size);
6570 size = (! current_frame_info.initialized
6571 ? sparc_flat_compute_frame_size (size)
6572 : current_frame_info.total_size);
6574 /* These cases shouldn't happen. Catch them now. */
6575 if (size == 0 && (gmask || current_frame_info.fmask))
6578 /* Allocate our stack frame by decrementing %sp.
6579 At present, the only algorithm gdb can use to determine if this is a
6580 flat frame is if we always set %i7 if we set %sp. This can be optimized
6581 in the future by putting in some sort of debugging information that says
6582 this is a `flat' function. However, there is still the case of debugging
6583 code without such debugging information (including cases where most fns
6584 have such info, but there is one that doesn't). So, always do this now
6585 so we don't get a lot of code out there that gdb can't handle.
6586 If the frame pointer isn't needn't then that's ok - gdb won't be able to
6587 distinguish us from a non-flat function but there won't (and shouldn't)
6588 be any differences anyway. The return pc is saved (if necessary) right
6589 after %i7 so gdb won't have to look too far to find it. */
6592 unsigned int reg_offset = current_frame_info.reg_offset;
6593 const char *fp_str = reg_names[FRAME_POINTER_REGNUM];
6594 const char *t1_str = "%g1";
6596 /* Things get a little tricky if local variables take up more than ~4096
6597 bytes and outgoing arguments take up more than ~4096 bytes. When that
6598 happens, the register save area can't be accessed from either end of
6599 the frame. Handle this by decrementing %sp to the start of the gp
6600 register save area, save the regs, update %i7, and then set %sp to its
6601 final value. Given that we only have one scratch register to play
6602 with it is the cheapest solution, and it helps gdb out as it won't
6603 slow down recognition of flat functions.
6604 Don't change the order of insns emitted here without checking with
6605 the gdb folk first. */
6607 /* Is the entire register save area offsettable from %sp? */
6608 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
6612 fprintf (file, "\tadd\t%s, %d, %s\n",
6613 sp_str, -size, sp_str);
6614 if (gmask & FRAME_POINTER_MASK)
6616 fprintf (file, "\tst\t%s, [%s+%d]\n",
6617 fp_str, sp_str, reg_offset);
6618 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
6619 sp_str, -size, fp_str, ASM_COMMENT_START);
6625 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6626 size, t1_str, sp_str, t1_str, sp_str);
6627 if (gmask & FRAME_POINTER_MASK)
6629 fprintf (file, "\tst\t%s, [%s+%d]\n",
6630 fp_str, sp_str, reg_offset);
6631 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
6632 sp_str, t1_str, fp_str, ASM_COMMENT_START);
6636 if (dwarf2out_do_frame ())
6638 char *l = dwarf2out_cfi_label ();
6639 if (gmask & FRAME_POINTER_MASK)
6641 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
6642 reg_offset - 4 - size);
6643 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
6646 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
6648 if (gmask & RETURN_ADDR_MASK)
6650 fprintf (file, "\tst\t%s, [%s+%d]\n",
6651 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
6652 if (dwarf2out_do_frame ())
6653 dwarf2out_return_save ("", reg_offset - size);
6656 sparc_flat_save_restore (file, sp_str, reg_offset,
6657 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6658 current_frame_info.fmask,
6659 "st", "std", -size);
6663 /* Subtract %sp in two steps, but make sure there is always a
6664 64 byte register save area, and %sp is properly aligned. */
6665 /* Amount to decrement %sp by, the first time. */
6666 unsigned int size1 = ((size - reg_offset + 64) + 15) & -16;
6667 /* Offset to register save area from %sp. */
6668 unsigned int offset = size1 - (size - reg_offset);
6672 fprintf (file, "\tadd\t%s, %d, %s\n",
6673 sp_str, -size1, sp_str);
6674 if (gmask & FRAME_POINTER_MASK)
6676 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
6677 fp_str, sp_str, offset, sp_str, -size1, fp_str,
6684 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6685 size1, t1_str, sp_str, t1_str, sp_str);
6686 if (gmask & FRAME_POINTER_MASK)
6688 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
6689 fp_str, sp_str, offset, sp_str, t1_str, fp_str,
6694 if (dwarf2out_do_frame ())
6696 char *l = dwarf2out_cfi_label ();
6697 if (gmask & FRAME_POINTER_MASK)
6699 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
6700 offset - 4 - size1);
6701 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
6704 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
6706 if (gmask & RETURN_ADDR_MASK)
6708 fprintf (file, "\tst\t%s, [%s+%d]\n",
6709 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
6710 if (dwarf2out_do_frame ())
6711 /* offset - size1 == reg_offset - size
6712 if reg_offset were updated above like offset. */
6713 dwarf2out_return_save ("", offset - size1);
6716 sparc_flat_save_restore (file, sp_str, offset,
6717 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6718 current_frame_info.fmask,
6719 "st", "std", -size1);
6720 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6721 size - size1, t1_str, sp_str, t1_str, sp_str);
6722 if (dwarf2out_do_frame ())
6723 if (! (gmask & FRAME_POINTER_MASK))
6724 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
6728 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
6731 /* Do any necessary cleanup after a function to restore stack, frame,
6735 sparc_flat_output_function_epilogue (file, size)
6739 rtx epilogue_delay = current_function_epilogue_delay_list;
6740 int noepilogue = FALSE;
6742 /* This is only for the human reader. */
6743 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
6745 /* The epilogue does not depend on any registers, but the stack
6746 registers, so we assume that if we have 1 pending nop, it can be
6747 ignored, and 2 it must be filled (2 nops occur for integer
6748 multiply and divide). */
6750 size = SPARC_STACK_ALIGN (size);
6751 size = (!current_frame_info.initialized
6752 ? sparc_flat_compute_frame_size (size)
6753 : current_frame_info.total_size);
6755 if (size == 0 && epilogue_delay == 0)
6757 rtx insn = get_last_insn ();
6759 /* If the last insn was a BARRIER, we don't have to write any code
6760 because a jump (aka return) was put there. */
6761 if (GET_CODE (insn) == NOTE)
6762 insn = prev_nonnote_insn (insn);
6763 if (insn && GET_CODE (insn) == BARRIER)
6769 unsigned int reg_offset = current_frame_info.reg_offset;
6771 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
6772 const char *fp_str = reg_names[FRAME_POINTER_REGNUM];
6773 const char *t1_str = "%g1";
6775 /* In the reload sequence, we don't need to fill the load delay
6776 slots for most of the loads, also see if we can fill the final
6777 delay slot if not otherwise filled by the reload sequence. */
6780 fprintf (file, "\tset\t%d, %s\n", size, t1_str);
6782 if (frame_pointer_needed)
6785 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
6786 fp_str, t1_str, sp_str, ASM_COMMENT_START);
6788 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
6789 fp_str, size, sp_str, ASM_COMMENT_START);
6792 /* Is the entire register save area offsettable from %sp? */
6793 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
6799 /* Restore %sp in two steps, but make sure there is always a
6800 64 byte register save area, and %sp is properly aligned. */
6801 /* Amount to increment %sp by, the first time. */
6802 size1 = ((reg_offset - 64 - 16) + 15) & -16;
6803 /* Offset to register save area from %sp. */
6804 reg_offset = size1 - reg_offset;
6806 fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n",
6807 size1, t1_str, sp_str, t1_str, sp_str);
6810 /* We must restore the frame pointer and return address reg first
6811 because they are treated specially by the prologue output code. */
6812 if (current_frame_info.gmask & FRAME_POINTER_MASK)
6814 fprintf (file, "\tld\t[%s+%d], %s\n",
6815 sp_str, reg_offset, fp_str);
6818 if (current_frame_info.gmask & RETURN_ADDR_MASK)
6820 fprintf (file, "\tld\t[%s+%d], %s\n",
6821 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
6825 /* Restore any remaining saved registers. */
6826 sparc_flat_save_restore (file, sp_str, reg_offset,
6827 current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6828 current_frame_info.fmask,
6831 /* If we had to increment %sp in two steps, record it so the second
6832 restoration in the epilogue finishes up. */
6837 fprintf (file, "\tset\t%d, %s\n",
6841 if (current_function_returns_struct)
6842 fprintf (file, "\tjmp\t%%o7+12\n");
6844 fprintf (file, "\tretl\n");
6846 /* If the only register saved is the return address, we need a
6847 nop, unless we have an instruction to put into it. Otherwise
6848 we don't since reloading multiple registers doesn't reference
6849 the register being loaded. */
6855 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
6858 else if (size > 4095)
6859 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
6862 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str);
6865 fprintf (file, "\tnop\n");
6868 /* Reset state info for each function. */
6869 current_frame_info = zero_frame_info;
6871 sparc_output_deferred_case_vectors ();
6874 /* Define the number of delay slots needed for the function epilogue.
6876 On the sparc, we need a slot if either no stack has been allocated,
6877 or the only register saved is the return register. */
6880 sparc_flat_epilogue_delay_slots ()
6882 if (!current_frame_info.initialized)
6883 (void) sparc_flat_compute_frame_size (get_frame_size ());
6885 if (current_frame_info.total_size == 0)
6891 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
6892 Any single length instruction which doesn't reference the stack or frame
6896 sparc_flat_eligible_for_epilogue_delay (trial, slot)
6898 int slot ATTRIBUTE_UNUSED;
6900 rtx pat = PATTERN (trial);
6902 if (get_attr_length (trial) != 1)
6905 if (! reg_mentioned_p (stack_pointer_rtx, pat)
6906 && ! reg_mentioned_p (frame_pointer_rtx, pat))
6912 /* Adjust the cost of a scheduling dependency. Return the new cost of
6913 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6916 supersparc_adjust_cost (insn, link, dep_insn, cost)
6922 enum attr_type insn_type;
6924 if (! recog_memoized (insn))
6927 insn_type = get_attr_type (insn);
6929 if (REG_NOTE_KIND (link) == 0)
6931 /* Data dependency; DEP_INSN writes a register that INSN reads some
6934 /* if a load, then the dependence must be on the memory address;
6935 add an extra "cycle". Note that the cost could be two cycles
6936 if the reg was written late in an instruction group; we ca not tell
6938 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
6941 /* Get the delay only if the address of the store is the dependence. */
6942 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
6944 rtx pat = PATTERN(insn);
6945 rtx dep_pat = PATTERN (dep_insn);
6947 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6948 return cost; /* This should not happen! */
6950 /* The dependency between the two instructions was on the data that
6951 is being stored. Assume that this implies that the address of the
6952 store is not dependent. */
6953 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6956 return cost + 3; /* An approximation. */
6959 /* A shift instruction cannot receive its data from an instruction
6960 in the same cycle; add a one cycle penalty. */
6961 if (insn_type == TYPE_SHIFT)
6962 return cost + 3; /* Split before cascade into shift. */
6966 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
6967 INSN writes some cycles later. */
6969 /* These are only significant for the fpu unit; writing a fp reg before
6970 the fpu has finished with it stalls the processor. */
6972 /* Reusing an integer register causes no problems. */
6973 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
6981 hypersparc_adjust_cost (insn, link, dep_insn, cost)
6987 enum attr_type insn_type, dep_type;
6988 rtx pat = PATTERN(insn);
6989 rtx dep_pat = PATTERN (dep_insn);
6991 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
6994 insn_type = get_attr_type (insn);
6995 dep_type = get_attr_type (dep_insn);
6997 switch (REG_NOTE_KIND (link))
7000 /* Data dependency; DEP_INSN writes a register that INSN reads some
7007 /* Get the delay iff the address of the store is the dependence. */
7008 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7011 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7018 /* If a load, then the dependence must be on the memory address. If
7019 the addresses aren't equal, then it might be a false dependency */
7020 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7022 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7023 || GET_CODE (SET_DEST (dep_pat)) != MEM
7024 || GET_CODE (SET_SRC (pat)) != MEM
7025 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7026 XEXP (SET_SRC (pat), 0)))
7034 /* Compare to branch latency is 0. There is no benefit from
7035 separating compare and branch. */
7036 if (dep_type == TYPE_COMPARE)
7038 /* Floating point compare to branch latency is less than
7039 compare to conditional move. */
7040 if (dep_type == TYPE_FPCMP)
7049 /* Anti-dependencies only penalize the fpu unit. */
7050 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7062 ultrasparc_adjust_cost (insn, link, dep_insn, cost)
7068 enum attr_type insn_type, dep_type;
7069 rtx pat = PATTERN(insn);
7070 rtx dep_pat = PATTERN (dep_insn);
7072 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7075 insn_type = get_attr_type (insn);
7076 dep_type = get_attr_type (dep_insn);
7078 /* Nothing issues in parallel with integer multiplies, so
7079 mark as zero cost since the scheduler can not do anything
7081 if (insn_type == TYPE_IMUL)
7084 #define SLOW_FP(dep_type) \
7085 (dep_type == TYPE_FPSQRTS || dep_type == TYPE_FPSQRTD || \
7086 dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
7088 switch (REG_NOTE_KIND (link))
7091 /* Data dependency; DEP_INSN writes a register that INSN reads some
7094 if (dep_type == TYPE_CMOVE)
7096 /* Instructions that read the result of conditional moves cannot
7097 be in the same group or the following group. */
7103 /* UltraSPARC can dual issue a store and an instruction setting
7104 the value stored, except for divide and square root. */
7106 if (! SLOW_FP (dep_type))
7111 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7114 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7115 /* The dependency between the two instructions is on the data
7116 that is being stored. Assume that the address of the store
7117 is not also dependent. */
7124 /* A load does not return data until at least 11 cycles after
7125 a store to the same location. 3 cycles are accounted for
7126 in the load latency; add the other 8 here. */
7127 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7129 /* If the addresses are not equal this may be a false
7130 dependency because pointer aliasing could not be
7131 determined. Add only 2 cycles in that case. 2 is
7132 an arbitrary compromise between 8, which would cause
7133 the scheduler to generate worse code elsewhere to
7134 compensate for a dependency which might not really
7136 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7137 || GET_CODE (SET_SRC (pat)) != MEM
7138 || GET_CODE (SET_DEST (dep_pat)) != MEM
7139 || ! rtx_equal_p (XEXP (SET_SRC (pat), 0),
7140 XEXP (SET_DEST (dep_pat), 0)))
7148 /* Compare to branch latency is 0. There is no benefit from
7149 separating compare and branch. */
7150 if (dep_type == TYPE_COMPARE)
7152 /* Floating point compare to branch latency is less than
7153 compare to conditional move. */
7154 if (dep_type == TYPE_FPCMP)
7159 /* FMOVR class instructions can not issue in the same cycle
7160 or the cycle after an instruction which writes any
7161 integer register. Model this as cost 2 for dependent
7163 if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY
7164 || dep_type == TYPE_BINARY)
7167 /* Otherwise check as for integer conditional moves. */
7170 /* Conditional moves involving integer registers wait until
7171 3 cycles after loads return data. The interlock applies
7172 to all loads, not just dependent loads, but that is hard
7174 if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD)
7184 /* Divide and square root lock destination registers for full latency. */
7185 if (! SLOW_FP (dep_type))
7189 case REG_DEP_OUTPUT:
7190 /* IEU and FPU instruction that have the same destination
7191 register cannot be grouped together. */
7198 /* Other costs not accounted for:
7199 - Single precision floating point loads lock the other half of
7200 the even/odd register pair.
7201 - Several hazards associated with ldd/std are ignored because these
7202 instructions are rarely generated for V9.
7203 - The floating point pipeline can not have both a single and double
7204 precision operation active at the same time. Format conversions
7205 and graphics instructions are given honorary double precision status.
7206 - call and jmpl are always the first instruction in a group. */
7214 sparc_adjust_cost(insn, link, dep, cost)
7222 case PROCESSOR_SUPERSPARC:
7223 cost = supersparc_adjust_cost (insn, link, dep, cost);
7225 case PROCESSOR_HYPERSPARC:
7226 case PROCESSOR_SPARCLITE86X:
7227 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7229 case PROCESSOR_ULTRASPARC:
7230 cost = ultrasparc_adjust_cost (insn, link, dep, cost);
7238 /* This describes the state of the UltraSPARC pipeline during
7239 instruction scheduling. */
7241 #define TMASK(__x) ((unsigned)1 << ((int)(__x)))
7242 #define UMASK(__x) ((unsigned)1 << ((int)(__x)))
7244 enum ultra_code { NONE=0, /* no insn at all */
7245 IEU0, /* shifts and conditional moves */
7246 IEU1, /* condition code setting insns, calls+jumps */
7247 IEUN, /* all other single cycle ieu insns */
7248 LSU, /* loads and stores */
7250 FPM, /* FPU pipeline 1, multiplies and divides */
7251 FPA, /* FPU pipeline 2, all other operations */
7252 SINGLE, /* single issue instructions */
7255 static enum ultra_code ultra_code_from_mask PARAMS ((int));
7256 static void ultra_schedule_insn PARAMS ((rtx *, rtx *, int, enum ultra_code));
7258 static const char *ultra_code_names[NUM_ULTRA_CODES] = {
7259 "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI",
7260 "FPM", "FPA", "SINGLE" };
7262 struct ultrasparc_pipeline_state {
7263 /* The insns in this group. */
7266 /* The code for each insn. */
7267 enum ultra_code codes[4];
7269 /* Which insns in this group have been committed by the
7270 scheduler. This is how we determine how many more
7271 can issue this cycle. */
7274 /* How many insns in this group. */
7277 /* Mask of free slots still in this group. */
7278 char free_slot_mask;
7280 /* The slotter uses the following to determine what other
7281 insn types can still make their way into this group. */
7282 char contents [NUM_ULTRA_CODES];
7286 #define ULTRA_NUM_HIST 8
7287 static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST];
7288 static int ultra_cur_hist;
7289 static int ultra_cycles_elapsed;
7291 #define ultra_pipe (ultra_pipe_hist[ultra_cur_hist])
7293 /* Given TYPE_MASK compute the ultra_code it has. */
7294 static enum ultra_code
7295 ultra_code_from_mask (type_mask)
7298 if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE)))
7300 else if (type_mask & (TMASK (TYPE_COMPARE) |
7302 TMASK (TYPE_SIBCALL) |
7303 TMASK (TYPE_UNCOND_BRANCH)))
7305 else if (type_mask & (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
7306 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY)))
7308 else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
7309 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
7310 TMASK (TYPE_FPSTORE)))
7312 else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) |
7313 TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRTS) |
7314 TMASK (TYPE_FPSQRTD)))
7316 else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
7317 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)))
7319 else if (type_mask & TMASK (TYPE_BRANCH))
7325 /* Check INSN (a conditional move) and make sure that it's
7326 results are available at this cycle. Return 1 if the
7327 results are in fact ready. */
7329 ultra_cmove_results_ready_p (insn)
7332 struct ultrasparc_pipeline_state *up;
7335 /* If this got dispatched in the previous
7336 group, the results are not ready. */
7337 entry = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1);
7338 up = &ultra_pipe_hist[entry];
7341 if (up->group[slot] == insn)
7347 /* Walk backwards in pipeline history looking for FPU
7348 operations which use a mode different than FPMODE and
7349 will create a stall if an insn using FPMODE were to be
7350 dispatched this cycle. */
7352 ultra_fpmode_conflict_exists (fpmode)
7353 enum machine_mode fpmode;
7358 hist_ent = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1);
7359 if (ultra_cycles_elapsed < 4)
7360 hist_lim = ultra_cycles_elapsed;
7363 while (hist_lim > 0)
7365 struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent];
7370 rtx insn = up->group[slot];
7371 enum machine_mode this_mode;
7375 || GET_CODE (insn) != INSN
7376 || (pat = PATTERN (insn)) == 0
7377 || GET_CODE (pat) != SET)
7380 this_mode = GET_MODE (SET_DEST (pat));
7381 if ((this_mode != SFmode
7382 && this_mode != DFmode)
7383 || this_mode == fpmode)
7386 /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then
7387 we will get a stall. Loads and stores are independant
7389 if (GET_CODE (SET_SRC (pat)) != ABS
7390 && GET_CODE (SET_SRC (pat)) != NEG
7391 && ((TMASK (get_attr_type (insn)) &
7392 (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) |
7393 TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRTS) |
7394 TMASK (TYPE_FPSQRTD) |
7395 TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0))
7399 hist_ent = (hist_ent - 1) & (ULTRA_NUM_HIST - 1);
7402 /* No conflicts, safe to dispatch. */
7406 /* Find an instruction in LIST which has one of the
7407 type attributes enumerated in TYPE_MASK. START
7408 says where to begin the search.
7410 NOTE: This scheme depends upon the fact that we
7411 have less than 32 distinct type attributes. */
7413 static int ultra_types_avail;
7416 ultra_find_type (type_mask, list, start)
7423 /* Short circuit if no such insn exists in the ready
7425 if ((type_mask & ultra_types_avail) == 0)
7428 for (i = start; i >= 0; i--)
7432 if (recog_memoized (insn) >= 0
7433 && (TMASK(get_attr_type (insn)) & type_mask))
7435 enum machine_mode fpmode = SFmode;
7438 int check_depend = 0;
7439 int check_fpmode_conflict = 0;
7441 if (GET_CODE (insn) == INSN
7442 && (pat = PATTERN(insn)) != 0
7443 && GET_CODE (pat) == SET
7444 && !(type_mask & (TMASK (TYPE_STORE) |
7445 TMASK (TYPE_FPSTORE))))
7448 if (GET_MODE (SET_DEST (pat)) == SFmode
7449 || GET_MODE (SET_DEST (pat)) == DFmode)
7451 fpmode = GET_MODE (SET_DEST (pat));
7452 check_fpmode_conflict = 1;
7459 rtx slot_insn = ultra_pipe.group[slot];
7462 /* Already issued, bad dependency, or FPU
7465 && (slot_pat = PATTERN (slot_insn)) != 0
7466 && ((insn == slot_insn)
7467 || (check_depend == 1
7468 && GET_CODE (slot_insn) == INSN
7469 && GET_CODE (slot_pat) == SET
7470 && ((GET_CODE (SET_DEST (slot_pat)) == REG
7471 && GET_CODE (SET_SRC (pat)) == REG
7472 && REGNO (SET_DEST (slot_pat)) ==
7473 REGNO (SET_SRC (pat)))
7474 || (GET_CODE (SET_DEST (slot_pat)) == SUBREG
7475 && GET_CODE (SET_SRC (pat)) == SUBREG
7476 && REGNO (SUBREG_REG (SET_DEST (slot_pat))) ==
7477 REGNO (SUBREG_REG (SET_SRC (pat)))
7478 && SUBREG_WORD (SET_DEST (slot_pat)) ==
7479 SUBREG_WORD (SET_SRC (pat)))))
7480 || (check_fpmode_conflict == 1
7481 && GET_CODE (slot_insn) == INSN
7482 && GET_CODE (slot_pat) == SET
7483 && (GET_MODE (SET_DEST (slot_pat)) == SFmode
7484 || GET_MODE (SET_DEST (slot_pat)) == DFmode)
7485 && GET_MODE (SET_DEST (slot_pat)) != fpmode)))
7489 /* Check for peculiar result availability and dispatch
7490 interference situations. */
7492 && ultra_cycles_elapsed > 0)
7496 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
7498 rtx link_insn = XEXP (link, 0);
7499 if (GET_CODE (link_insn) == INSN
7500 && recog_memoized (link_insn) >= 0
7501 && (TMASK (get_attr_type (link_insn)) &
7502 (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE)))
7503 && ! ultra_cmove_results_ready_p (link_insn))
7507 if (check_fpmode_conflict
7508 && ultra_fpmode_conflict_exists (fpmode))
7521 ultra_build_types_avail (ready, n_ready)
7525 int i = n_ready - 1;
7527 ultra_types_avail = 0;
7530 rtx insn = ready[i];
7532 if (recog_memoized (insn) >= 0)
7533 ultra_types_avail |= TMASK (get_attr_type (insn));
7539 /* Place insn pointed to my IP into the pipeline.
7540 Make element THIS of READY be that insn if it
7541 is not already. TYPE indicates the pipeline class
7542 this insn falls into. */
7544 ultra_schedule_insn (ip, ready, this, type)
7548 enum ultra_code type;
7551 char mask = ultra_pipe.free_slot_mask;
7554 /* Obtain free slot. */
7555 for (pipe_slot = 0; pipe_slot < 4; pipe_slot++)
7556 if ((mask & (1 << pipe_slot)) != 0)
7561 /* In it goes, and it hasn't been committed yet. */
7562 ultra_pipe.group[pipe_slot] = *ip;
7563 ultra_pipe.codes[pipe_slot] = type;
7564 ultra_pipe.contents[type] = 1;
7566 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
7567 ultra_pipe.num_ieu_insns += 1;
7569 ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot));
7570 ultra_pipe.group_size += 1;
7571 ultra_pipe.commit[pipe_slot] = 0;
7573 /* Update ready list. */
7575 while (ip != &ready[this])
7583 /* Advance to the next pipeline group. */
7585 ultra_flush_pipeline ()
7587 ultra_cur_hist = (ultra_cur_hist + 1) & (ULTRA_NUM_HIST - 1);
7588 ultra_cycles_elapsed += 1;
7589 memset ((char *) &ultra_pipe, 0, sizeof ultra_pipe);
7590 ultra_pipe.free_slot_mask = 0xf;
7593 /* Init our data structures for this current block. */
7595 ultrasparc_sched_init (dump, sched_verbose)
7596 FILE *dump ATTRIBUTE_UNUSED;
7597 int sched_verbose ATTRIBUTE_UNUSED;
7599 memset ((char *) ultra_pipe_hist, 0, sizeof ultra_pipe_hist);
7601 ultra_cycles_elapsed = 0;
7602 ultra_pipe.free_slot_mask = 0xf;
7605 /* INSN has been scheduled, update pipeline commit state
7606 and return how many instructions are still to be
7607 scheduled in this group. */
7609 ultrasparc_variable_issue (insn)
7612 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7613 int i, left_to_fire;
7616 for (i = 0; i < 4; i++)
7618 if (up->group[i] == 0)
7621 if (up->group[i] == insn)
7625 else if (! up->commit[i])
7629 return left_to_fire;
7632 /* In actual_hazard_this_instance, we may have yanked some
7633 instructions from the ready list due to conflict cost
7634 adjustments. If so, and such an insn was in our pipeline
7635 group, remove it and update state. */
7637 ultra_rescan_pipeline_state (ready, n_ready)
7641 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7644 for (i = 0; i < 4; i++)
7646 rtx insn = up->group[i];
7652 /* If it has been committed, then it was removed from
7653 the ready list because it was actually scheduled,
7654 and that is not the case we are searching for here. */
7655 if (up->commit[i] != 0)
7658 for (j = n_ready - 1; j >= 0; j--)
7659 if (ready[j] == insn)
7662 /* If we didn't find it, toss it. */
7665 enum ultra_code ucode = up->codes[i];
7668 up->codes[i] = NONE;
7669 up->contents[ucode] = 0;
7671 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
7672 up->num_ieu_insns -= 1;
7674 up->free_slot_mask |= (1 << i);
7675 up->group_size -= 1;
7682 ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
7688 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7695 fprintf (dump, "\n;;\tUltraSPARC Looking at [");
7696 for (n = n_ready - 1; n >= 0; n--)
7698 rtx insn = ready[n];
7699 enum ultra_code ucode;
7701 if (recog_memoized (insn) < 0)
7703 ucode = ultra_code_from_mask (TMASK (get_attr_type (insn)));
7705 fprintf (dump, "%s(%d) ",
7706 ultra_code_names[ucode],
7709 fprintf (dump, "%s(%d)",
7710 ultra_code_names[ucode],
7713 fprintf (dump, "]\n");
7716 this_insn = n_ready - 1;
7718 /* Skip over junk we don't understand. */
7719 while ((this_insn >= 0)
7720 && recog_memoized (ready[this_insn]) < 0)
7723 ultra_build_types_avail (ready, this_insn + 1);
7725 while (this_insn >= 0) {
7726 int old_group_size = up->group_size;
7728 if (up->group_size != 0)
7732 num_committed = (up->commit[0] + up->commit[1] +
7733 up->commit[2] + up->commit[3]);
7734 /* If nothing has been commited from our group, or all of
7735 them have. Clear out the (current cycle's) pipeline
7736 state and start afresh. */
7737 if (num_committed == 0
7738 || num_committed == up->group_size)
7740 ultra_flush_pipeline ();
7746 /* OK, some ready list insns got requeued and thus removed
7747 from the ready list. Account for this fact. */
7748 ultra_rescan_pipeline_state (ready, n_ready);
7750 /* Something "changed", make this look like a newly
7751 formed group so the code at the end of the loop
7752 knows that progress was in fact made. */
7753 if (up->group_size != old_group_size)
7758 if (up->group_size == 0)
7760 /* If the pipeline is (still) empty and we have any single
7761 group insns, get them out now as this is a good time. */
7762 rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_ADDRESS) |
7763 TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) |
7764 TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)),
7768 ultra_schedule_insn (ip, ready, this_insn, SINGLE);
7772 /* If we are not in the process of emptying out the pipe, try to
7773 obtain an instruction which must be the first in it's group. */
7774 ip = ultra_find_type ((TMASK (TYPE_CALL) |
7775 TMASK (TYPE_SIBCALL) |
7776 TMASK (TYPE_CALL_NO_DELAY_SLOT) |
7777 TMASK (TYPE_UNCOND_BRANCH)),
7781 ultra_schedule_insn (ip, ready, this_insn, IEU1);
7784 else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) |
7785 TMASK (TYPE_FPDIVD) |
7786 TMASK (TYPE_FPSQRTS) |
7787 TMASK (TYPE_FPSQRTD)),
7788 ready, this_insn)) != 0)
7790 ultra_schedule_insn (ip, ready, this_insn, FPM);
7795 /* Try to fill the integer pipeline. First, look for an IEU0 specific
7796 operation. We can't do more IEU operations if the first 3 slots are
7797 all full or we have dispatched two IEU insns already. */
7798 if ((up->free_slot_mask & 0x7) != 0
7799 && up->num_ieu_insns < 2
7800 && up->contents[IEU0] == 0
7801 && up->contents[IEUN] == 0)
7803 rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn);
7806 ultra_schedule_insn (ip, ready, this_insn, IEU0);
7811 /* If we can, try to find an IEU1 specific or an unnamed
7813 if ((up->free_slot_mask & 0x7) != 0
7814 && up->num_ieu_insns < 2)
7816 rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
7817 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY) |
7818 (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)),
7824 ultra_schedule_insn (ip, ready, this_insn,
7825 (!up->contents[IEU1]
7826 && get_attr_type (insn) == TYPE_COMPARE)
7832 /* If only one IEU insn has been found, try to find another unnamed
7833 IEU operation or an IEU1 specific one. */
7834 if ((up->free_slot_mask & 0x7) != 0
7835 && up->num_ieu_insns < 2)
7838 int tmask = (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
7839 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY));
7841 if (!up->contents[IEU1])
7842 tmask |= TMASK (TYPE_COMPARE);
7843 ip = ultra_find_type (tmask, ready, this_insn);
7848 ultra_schedule_insn (ip, ready, this_insn,
7849 (!up->contents[IEU1]
7850 && get_attr_type (insn) == TYPE_COMPARE)
7856 /* Try for a load or store, but such an insn can only be issued
7857 if it is within' one of the first 3 slots. */
7858 if ((up->free_slot_mask & 0x7) != 0
7859 && up->contents[LSU] == 0)
7861 rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
7862 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
7863 TMASK (TYPE_FPSTORE)), ready, this_insn);
7866 ultra_schedule_insn (ip, ready, this_insn, LSU);
7871 /* Now find FPU operations, first FPM class. But not divisions or
7872 square-roots because those will break the group up. Unlike all
7873 the previous types, these can go in any slot. */
7874 if (up->free_slot_mask != 0
7875 && up->contents[FPM] == 0)
7877 rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn);
7880 ultra_schedule_insn (ip, ready, this_insn, FPM);
7885 /* Continue on with FPA class if we have not filled the group already. */
7886 if (up->free_slot_mask != 0
7887 && up->contents[FPA] == 0)
7889 rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
7890 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)),
7894 ultra_schedule_insn (ip, ready, this_insn, FPA);
7899 /* Finally, maybe stick a branch in here. */
7900 if (up->free_slot_mask != 0
7901 && up->contents[CTI] == 0)
7903 rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn);
7905 /* Try to slip in a branch only if it is one of the
7906 next 2 in the ready list. */
7907 if (ip && ((&ready[this_insn] - ip) < 2))
7909 ultra_schedule_insn (ip, ready, this_insn, CTI);
7915 for (i = 0; i < 4; i++)
7916 if ((up->free_slot_mask & (1 << i)) == 0)
7919 /* See if we made any progress... */
7920 if (old_group_size != up->group_size)
7923 /* Clean out the (current cycle's) pipeline state
7924 and try once more. If we placed no instructions
7925 into the pipeline at all, it means a real hard
7926 conflict exists with some earlier issued instruction
7927 so we must advance to the next cycle to clear it up. */
7928 if (up->group_size == 0)
7930 ultra_flush_pipeline ();
7935 memset ((char *) &ultra_pipe, 0, sizeof ultra_pipe);
7936 ultra_pipe.free_slot_mask = 0xf;
7944 fprintf (dump, ";;\tUltraSPARC Launched [");
7945 gsize = up->group_size;
7946 for (n = 0; n < 4; n++)
7948 rtx insn = up->group[n];
7955 fprintf (dump, "%s(%d) ",
7956 ultra_code_names[up->codes[n]],
7959 fprintf (dump, "%s(%d)",
7960 ultra_code_names[up->codes[n]],
7963 fprintf (dump, "]\n");
7975 /* Assume V9 processors are capable of at least dual-issue. */
7977 case PROCESSOR_SUPERSPARC:
7979 case PROCESSOR_HYPERSPARC:
7980 case PROCESSOR_SPARCLITE86X:
7982 case PROCESSOR_ULTRASPARC:
7991 register rtx pat = PATTERN (insn);
7993 switch (GET_CODE (SET_SRC (pat)))
7995 /* Load and some shift instructions zero extend. */
7998 /* sethi clears the high bits */
8000 /* LO_SUM is used with sethi. sethi cleared the high
8001 bits and the values used with lo_sum are positive */
8003 /* Store flag stores 0 or 1 */
8013 rtx op0 = XEXP (SET_SRC (pat), 0);
8014 rtx op1 = XEXP (SET_SRC (pat), 1);
8015 if (GET_CODE (op1) == CONST_INT)
8016 return INTVAL (op1) >= 0;
8017 if (GET_CODE (op0) != REG)
8019 if (sparc_check_64 (op0, insn) == 1)
8021 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8026 rtx op0 = XEXP (SET_SRC (pat), 0);
8027 rtx op1 = XEXP (SET_SRC (pat), 1);
8028 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8030 if (GET_CODE (op1) == CONST_INT)
8031 return INTVAL (op1) >= 0;
8032 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8036 return GET_MODE (SET_SRC (pat)) == SImode;
8037 /* Positive integers leave the high bits zero. */
8039 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8041 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8044 return - (GET_MODE (SET_SRC (pat)) == SImode);
8046 return sparc_check_64 (SET_SRC (pat), insn);
8052 /* We _ought_ to have only one kind per function, but... */
8053 static rtx sparc_addr_diff_list;
8054 static rtx sparc_addr_list;
8057 sparc_defer_case_vector (lab, vec, diff)
8061 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8063 sparc_addr_diff_list
8064 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8066 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8070 sparc_output_addr_vec (vec)
8073 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8074 int idx, vlen = XVECLEN (body, 0);
8076 #ifdef ASM_OUTPUT_ADDR_VEC_START
8077 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8080 #ifdef ASM_OUTPUT_CASE_LABEL
8081 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8084 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8087 for (idx = 0; idx < vlen; idx++)
8089 ASM_OUTPUT_ADDR_VEC_ELT
8090 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8093 #ifdef ASM_OUTPUT_ADDR_VEC_END
8094 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8099 sparc_output_addr_diff_vec (vec)
8102 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8103 rtx base = XEXP (XEXP (body, 0), 0);
8104 int idx, vlen = XVECLEN (body, 1);
8106 #ifdef ASM_OUTPUT_ADDR_VEC_START
8107 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8110 #ifdef ASM_OUTPUT_CASE_LABEL
8111 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8114 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8117 for (idx = 0; idx < vlen; idx++)
8119 ASM_OUTPUT_ADDR_DIFF_ELT
8122 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8123 CODE_LABEL_NUMBER (base));
8126 #ifdef ASM_OUTPUT_ADDR_VEC_END
8127 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8132 sparc_output_deferred_case_vectors ()
8137 if (sparc_addr_list == NULL_RTX
8138 && sparc_addr_diff_list == NULL_RTX)
8141 /* Align to cache line in the function's code section. */
8142 function_section (current_function_decl);
8144 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8146 ASM_OUTPUT_ALIGN (asm_out_file, align);
8148 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8149 sparc_output_addr_vec (XEXP (t, 0));
8150 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8151 sparc_output_addr_diff_vec (XEXP (t, 0));
8153 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8156 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8157 unknown. Return 1 if the high bits are zero, -1 if the register is
8160 sparc_check_64 (x, insn)
8163 /* If a register is set only once it is safe to ignore insns this
8164 code does not know how to handle. The loop will either recognize
8165 the single set and return the correct value or fail to recognize
8170 if (GET_CODE (x) != REG)
8173 if (GET_MODE (x) == DImode)
8174 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8176 if (flag_expensive_optimizations
8177 && REG_N_SETS (REGNO (y)) == 1)
8183 insn = get_last_insn_anywhere ();
8188 while ((insn = PREV_INSN (insn)))
8190 switch (GET_CODE (insn))
8203 rtx pat = PATTERN (insn);
8204 if (GET_CODE (pat) != SET)
8206 if (rtx_equal_p (x, SET_DEST (pat)))
8207 return set_extends (insn);
8208 if (y && rtx_equal_p (y, SET_DEST (pat)))
8209 return set_extends (insn);
8210 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8219 sparc_v8plus_shift (operands, insn, opcode)
8224 static char asm_code[60];
8226 if (GET_CODE (operands[3]) == SCRATCH)
8227 operands[3] = operands[0];
8228 if (GET_CODE (operands[1]) == CONST_INT)
8230 output_asm_insn ("mov\t%1, %3", operands);
8234 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8235 if (sparc_check_64 (operands[1], insn) <= 0)
8236 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8237 output_asm_insn ("or\t%L1, %3, %3", operands);
8240 strcpy(asm_code, opcode);
8241 if (which_alternative != 2)
8242 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8244 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8248 /* Return 1 if DEST and SRC reference only global and in registers. */
8251 sparc_return_peephole_ok (dest, src)
8256 if (current_function_uses_only_leaf_regs)
8258 if (GET_CODE (src) != CONST_INT
8259 && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src)))
8261 return IN_OR_GLOBAL_P (dest);
8264 /* Output assembler code to FILE to increment profiler label # LABELNO
8265 for profiling a function entry.
8267 32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered
8268 during profiling so we need to save/restore it around the call to mcount.
8269 We're guaranteed that a save has just been done, and we use the space
8270 allocated for intreg/fpreg value passing. */
8273 sparc_function_profiler (file, labelno)
8278 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8280 if (! TARGET_ARCH64)
8281 fputs ("\tst\t%g2, [%fp-4]\n", file);
8283 fputs ("\tsethi\t%hi(", file);
8284 assemble_name (file, buf);
8285 fputs ("), %o0\n", file);
8287 fputs ("\tcall\t", file);
8288 assemble_name (file, MCOUNT_FUNCTION);
8291 fputs ("\t or\t%o0, %lo(", file);
8292 assemble_name (file, buf);
8293 fputs ("), %o0\n", file);
8295 if (! TARGET_ARCH64)
8296 fputs ("\tld\t[%fp-4], %g2\n", file);
8300 /* The following macro shall output assembler code to FILE
8301 to initialize basic-block profiling.
8303 If profile_block_flag == 2
8305 Output code to call the subroutine `__bb_init_trace_func'
8306 and pass two parameters to it. The first parameter is
8307 the address of a block allocated in the object module.
8308 The second parameter is the number of the first basic block
8311 The name of the block is a local symbol made with this statement:
8313 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
8315 Of course, since you are writing the definition of
8316 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
8317 can take a short cut in the definition of this macro and use the
8318 name that you know will result.
8320 The number of the first basic block of the function is
8321 passed to the macro in BLOCK_OR_LABEL.
8323 If described in a virtual assembler language the code to be
8327 parameter2 <- BLOCK_OR_LABEL
8328 call __bb_init_trace_func
8330 else if profile_block_flag != 0
8332 Output code to call the subroutine `__bb_init_func'
8333 and pass one single parameter to it, which is the same
8334 as the first parameter to `__bb_init_trace_func'.
8336 The first word of this parameter is a flag which will be nonzero if
8337 the object module has already been initialized. So test this word
8338 first, and do not call `__bb_init_func' if the flag is nonzero.
8339 Note: When profile_block_flag == 2 the test need not be done
8340 but `__bb_init_trace_func' *must* be called.
8342 BLOCK_OR_LABEL may be used to generate a label number as a
8343 branch destination in case `__bb_init_func' will not be called.
8345 If described in a virtual assembler language the code to be
8357 sparc_function_block_profiler(file, block_or_label)
8362 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0);
8364 if (profile_block_flag == 2)
8366 fputs ("\tsethi\t%hi(", file);
8367 assemble_name (file, LPBX);
8368 fputs ("), %o0\n", file);
8370 fprintf (file, "\tsethi\t%%hi(%d), %%o1\n", block_or_label);
8372 fputs ("\tor\t%o0, %lo(", file);
8373 assemble_name (file, LPBX);
8374 fputs ("), %o0\n", file);
8376 fprintf (file, "\tcall\t%s__bb_init_trace_func\n", user_label_prefix);
8378 fprintf (file, "\t or\t%%o1, %%lo(%d), %%o1\n", block_or_label);
8380 else if (profile_block_flag != 0)
8383 ASM_GENERATE_INTERNAL_LABEL (LPBY, "LPBY", block_or_label);
8385 fputs ("\tsethi\t%hi(", file);
8386 assemble_name (file, LPBX);
8387 fputs ("), %o0\n", file);
8389 fputs ("\tld\t[%lo(", file);
8390 assemble_name (file, LPBX);
8391 fputs (")+%o0], %o1\n", file);
8393 fputs ("\ttst\t%o1\n", file);
8397 fputs ("\tbne,pn\t%icc,", file);
8398 assemble_name (file, LPBY);
8403 fputs ("\tbne\t", file);
8404 assemble_name (file, LPBY);
8408 fputs ("\t or\t%o0, %lo(", file);
8409 assemble_name (file, LPBX);
8410 fputs ("), %o0\n", file);
8412 fprintf (file, "\tcall\t%s__bb_init_func\n\t nop\n", user_label_prefix);
8414 ASM_OUTPUT_INTERNAL_LABEL (file, "LPBY", block_or_label);
8418 /* The following macro shall output assembler code to FILE
8419 to increment a counter associated with basic block number BLOCKNO.
8421 If profile_block_flag == 2
8423 Output code to initialize the global structure `__bb' and
8424 call the function `__bb_trace_func' which will increment the
8427 `__bb' consists of two words. In the first word the number
8428 of the basic block has to be stored. In the second word
8429 the address of a block allocated in the object module
8432 The basic block number is given by BLOCKNO.
8434 The address of the block is given by the label created with
8436 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
8438 by FUNCTION_BLOCK_PROFILER.
8440 Of course, since you are writing the definition of
8441 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
8442 can take a short cut in the definition of this macro and use the
8443 name that you know will result.
8445 If described in a virtual assembler language the code to be
8448 move BLOCKNO -> (__bb)
8449 move LPBX0 -> (__bb+4)
8450 call __bb_trace_func
8452 Note that function `__bb_trace_func' must not change the
8453 machine state, especially the flag register. To grant
8454 this, you must output code to save and restore registers
8455 either in this macro or in the macros MACHINE_STATE_SAVE
8456 and MACHINE_STATE_RESTORE. The last two macros will be
8457 used in the function `__bb_trace_func', so you must make
8458 sure that the function prologue does not change any
8459 register prior to saving it with MACHINE_STATE_SAVE.
8461 else if profile_block_flag != 0
8463 Output code to increment the counter directly.
8464 Basic blocks are numbered separately from zero within each
8465 compiled object module. The count associated with block number
8466 BLOCKNO is at index BLOCKNO in an array of words; the name of
8467 this array is a local symbol made with this statement:
8469 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
8471 Of course, since you are writing the definition of
8472 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
8473 can take a short cut in the definition of this macro and use the
8474 name that you know will result.
8476 If described in a virtual assembler language, the code to be
8479 inc (LPBX2+4*BLOCKNO)
8484 sparc_block_profiler(file, blockno)
8489 int bbreg = TARGET_ARCH64 ? 4 : 2;
8491 if (profile_block_flag == 2)
8493 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0);
8495 fprintf (file, "\tsethi\t%%hi(%s__bb), %%g1\n", user_label_prefix);
8496 fprintf (file, "\tsethi\t%%hi(%d), %%g%d\n", blockno, bbreg);
8497 fprintf (file, "\tor\t%%g1, %%lo(%s__bb), %%g1\n", user_label_prefix);
8498 fprintf (file, "\tor\t%%g%d, %%lo(%d), %%g%d\n", bbreg, blockno, bbreg);
8500 fprintf (file, "\tst\t%%g%d, [%%g1]\n", bbreg);
8502 fputs ("\tsethi\t%hi(", file);
8503 assemble_name (file, LPBX);
8504 fprintf (file, "), %%g%d\n", bbreg);
8506 fputs ("\tor\t%o2, %lo(", file);
8507 assemble_name (file, LPBX);
8508 fprintf (file, "), %%g%d\n", bbreg);
8510 fprintf (file, "\tst\t%%g%d, [%%g1 + 4]\n", bbreg);
8511 fprintf (file, "\tmov\t%%o7, %%g%d\n", bbreg);
8513 fprintf (file, "\tcall\t%s__bb_trace_func\n\t nop\n", user_label_prefix);
8515 fprintf (file, "\tmov\t%%g%d, %%o7\n", bbreg);
8517 else if (profile_block_flag != 0)
8519 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 2);
8521 fputs ("\tsethi\t%hi(", file);
8522 assemble_name (file, LPBX);
8523 fprintf (file, "+%d), %%g1\n", blockno*4);
8525 fputs ("\tld\t[%g1+%lo(", file);
8526 assemble_name (file, LPBX);
8527 if (TARGET_ARCH64 && USE_AS_OFFSETABLE_LO10)
8528 fprintf (file, ")+%d], %%g%d\n", blockno*4, bbreg);
8530 fprintf (file, "+%d)], %%g%d\n", blockno*4, bbreg);
8532 fprintf (file, "\tadd\t%%g%d, 1, %%g%d\n", bbreg, bbreg);
8534 fprintf (file, "\tst\t%%g%d, [%%g1+%%lo(", bbreg);
8535 assemble_name (file, LPBX);
8536 if (TARGET_ARCH64 && USE_AS_OFFSETABLE_LO10)
8537 fprintf (file, ")+%d]\n", blockno*4);
8539 fprintf (file, "+%d)]\n", blockno*4);
8543 /* The following macro shall output assembler code to FILE
8544 to indicate a return from function during basic-block profiling.
8546 If profile_block_flag == 2:
8548 Output assembler code to call function `__bb_trace_ret'.
8550 Note that function `__bb_trace_ret' must not change the
8551 machine state, especially the flag register. To grant
8552 this, you must output code to save and restore registers
8553 either in this macro or in the macros MACHINE_STATE_SAVE_RET
8554 and MACHINE_STATE_RESTORE_RET. The last two macros will be
8555 used in the function `__bb_trace_ret', so you must make
8556 sure that the function prologue does not change any
8557 register prior to saving it with MACHINE_STATE_SAVE_RET.
8559 else if profile_block_flag != 0:
8561 The macro will not be used, so it need not distinguish
8566 sparc_function_block_profiler_exit(file)
8569 if (profile_block_flag == 2)
8570 fprintf (file, "\tcall\t%s__bb_trace_ret\n\t nop\n", user_label_prefix);
8575 /* Mark ARG, which is really a struct ultrasparc_pipline_state *, for
8579 mark_ultrasparc_pipeline_state (arg)
8582 struct ultrasparc_pipeline_state *ups;
8585 ups = (struct ultrasparc_pipeline_state *) arg;
8586 for (i = 0; i < sizeof (ups->group) / sizeof (rtx); ++i)
8587 ggc_mark_rtx (ups->group[i]);
8590 /* Called to register all of our global variables with the garbage
8594 sparc_add_gc_roots ()
8596 ggc_add_rtx_root (&sparc_compare_op0, 1);
8597 ggc_add_rtx_root (&sparc_compare_op1, 1);
8598 ggc_add_rtx_root (&leaf_label, 1);
8599 ggc_add_rtx_root (&global_offset_table, 1);
8600 ggc_add_rtx_root (&get_pc_symbol, 1);
8601 ggc_add_rtx_root (&sparc_addr_diff_list, 1);
8602 ggc_add_rtx_root (&sparc_addr_list, 1);
8603 ggc_add_root (ultra_pipe_hist, ARRAY_SIZE (ultra_pipe_hist),
8604 sizeof (ultra_pipe_hist[0]), &mark_ultrasparc_pipeline_state);