1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
51 /* 1 if the caller has placed an "unimp" insn immediately after the call.
52 This is used in v8 code when calling a function that returns a structure.
53 v9 doesn't have this. Be careful to have this test be the same as that
56 #define SKIP_CALLERS_UNIMP_P \
57 (!TARGET_ARCH64 && current_function_returns_struct \
58 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
59 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
62 /* Global variables for machine-dependent things. */
64 /* Size of frame. Need to know this to emit return insns from leaf procedures.
65 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
66 reload pass. This is important as the value is later used in insn
67 scheduling (to see what can go in a delay slot).
68 APPARENT_FSIZE is the size of the stack less the register save area and less
69 the outgoing argument area. It is used when saving call preserved regs. */
70 static HOST_WIDE_INT apparent_fsize;
71 static HOST_WIDE_INT actual_fsize;
73 /* Number of live general or floating point registers needed to be
74 saved (as 4-byte quantities). */
75 static int num_gfregs;
77 /* Save the operands last given to a compare for use when we
78 generate a scc or bcc insn. */
79 rtx sparc_compare_op0, sparc_compare_op1;
81 /* Coordinate with the md file wrt special insns created by
82 sparc_nonflat_function_epilogue. */
83 bool sparc_emitting_epilogue;
85 /* Vector to say how input registers are mapped to output registers.
86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
87 eliminate it. You must use -fomit-frame-pointer to get that. */
88 char leaf_reg_remap[] =
89 { 0, 1, 2, 3, 4, 5, 6, 7,
90 -1, -1, -1, -1, -1, -1, 14, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1,
92 8, 9, 10, 11, 12, 13, -1, 15,
94 32, 33, 34, 35, 36, 37, 38, 39,
95 40, 41, 42, 43, 44, 45, 46, 47,
96 48, 49, 50, 51, 52, 53, 54, 55,
97 56, 57, 58, 59, 60, 61, 62, 63,
98 64, 65, 66, 67, 68, 69, 70, 71,
99 72, 73, 74, 75, 76, 77, 78, 79,
100 80, 81, 82, 83, 84, 85, 86, 87,
101 88, 89, 90, 91, 92, 93, 94, 95,
102 96, 97, 98, 99, 100};
104 /* Vector, indexed by hard register number, which contains 1
105 for a register that is allowable in a candidate for leaf
106 function treatment. */
107 char sparc_leaf_regs[] =
108 { 1, 1, 1, 1, 1, 1, 1, 1,
109 0, 0, 0, 0, 0, 0, 1, 0,
110 0, 0, 0, 0, 0, 0, 0, 0,
111 1, 1, 1, 1, 1, 1, 0, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
122 struct machine_function GTY(())
124 /* Some local-dynamic TLS symbol name. */
125 const char *some_ld_name;
128 /* Name of where we pretend to think the frame pointer points.
129 Normally, this is "%fp", but if we are in a leaf procedure,
130 this is "%sp+something". We record "something" separately as it may be
131 too big for reg+constant addressing. */
133 static const char *frame_base_name;
134 static HOST_WIDE_INT frame_base_offset;
136 static void sparc_init_modes (void);
137 static int save_regs (FILE *, int, int, const char *, int, int, HOST_WIDE_INT);
138 static int restore_regs (FILE *, int, int, const char *, int, int);
139 static void build_big_number (FILE *, HOST_WIDE_INT, const char *);
140 static void scan_record_type (tree, int *, int *, int *);
141 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
142 tree, int, int, int *, int *);
144 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
145 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
147 static void sparc_output_addr_vec (rtx);
148 static void sparc_output_addr_diff_vec (rtx);
149 static void sparc_output_deferred_case_vectors (void);
150 static int check_return_regs (rtx);
151 static rtx sparc_builtin_saveregs (void);
152 static int epilogue_renumber (rtx *, int);
153 static bool sparc_assemble_integer (rtx, unsigned int, int);
154 static int set_extends (rtx);
155 static void output_restore_regs (FILE *, int);
156 static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT);
157 static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT);
158 static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT);
159 static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT);
160 static void sparc_flat_save_restore (FILE *, const char *, int,
161 unsigned long, unsigned long,
162 const char *, const char *,
164 static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int);
165 static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int);
166 #ifdef OBJECT_FORMAT_ELF
167 static void sparc_elf_asm_named_section (const char *, unsigned int);
169 static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT)
171 static void sparc_aout_select_rtx_section (enum machine_mode, rtx,
172 unsigned HOST_WIDE_INT)
175 static int sparc_adjust_cost (rtx, rtx, rtx, int);
176 static int sparc_issue_rate (void);
177 static void sparc_sched_init (FILE *, int, int);
178 static int sparc_use_dfa_pipeline_interface (void);
179 static int sparc_use_sched_lookahead (void);
181 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
182 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
183 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
184 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
185 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
187 static bool sparc_function_ok_for_sibcall (tree, tree);
188 static void sparc_init_libfuncs (void);
189 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
190 HOST_WIDE_INT, tree);
191 static struct machine_function * sparc_init_machine_status (void);
192 static bool sparc_cannot_force_const_mem (rtx);
193 static rtx sparc_tls_get_addr (void);
194 static rtx sparc_tls_got (void);
195 static const char *get_some_local_dynamic_name (void);
196 static int get_some_local_dynamic_name_1 (rtx *, void *);
197 static bool sparc_rtx_costs (rtx, int, int, int *);
198 static bool sparc_promote_prototypes (tree);
199 static rtx sparc_struct_value_rtx (tree, int);
200 static bool sparc_return_in_memory (tree, tree);
201 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
203 /* Option handling. */
205 /* Code model option as passed by user. */
206 const char *sparc_cmodel_string;
208 enum cmodel sparc_cmodel;
210 char sparc_hard_reg_printed[8];
212 struct sparc_cpu_select sparc_select[] =
214 /* switch name, tune arch */
215 { (char *)0, "default", 1, 1 },
216 { (char *)0, "-mcpu=", 1, 1 },
217 { (char *)0, "-mtune=", 1, 0 },
221 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
222 enum processor_type sparc_cpu;
224 /* Initialize the GCC target structure. */
226 /* The sparc default is to use .half rather than .short for aligned
227 HI objects. Use .word instead of .long on non-ELF systems. */
228 #undef TARGET_ASM_ALIGNED_HI_OP
229 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
230 #ifndef OBJECT_FORMAT_ELF
231 #undef TARGET_ASM_ALIGNED_SI_OP
232 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
235 #undef TARGET_ASM_UNALIGNED_HI_OP
236 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
237 #undef TARGET_ASM_UNALIGNED_SI_OP
238 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
239 #undef TARGET_ASM_UNALIGNED_DI_OP
240 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
242 /* The target hook has to handle DI-mode values. */
243 #undef TARGET_ASM_INTEGER
244 #define TARGET_ASM_INTEGER sparc_assemble_integer
246 #undef TARGET_ASM_FUNCTION_PROLOGUE
247 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
248 #undef TARGET_ASM_FUNCTION_EPILOGUE
249 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
251 #undef TARGET_SCHED_ADJUST_COST
252 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
253 #undef TARGET_SCHED_ISSUE_RATE
254 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
255 #undef TARGET_SCHED_INIT
256 #define TARGET_SCHED_INIT sparc_sched_init
257 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
258 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
259 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
260 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
262 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
263 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
265 #undef TARGET_INIT_LIBFUNCS
266 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
269 #undef TARGET_HAVE_TLS
270 #define TARGET_HAVE_TLS true
272 #undef TARGET_CANNOT_FORCE_CONST_MEM
273 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
275 #undef TARGET_ASM_OUTPUT_MI_THUNK
276 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
277 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
278 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
280 #undef TARGET_RTX_COSTS
281 #define TARGET_RTX_COSTS sparc_rtx_costs
282 #undef TARGET_ADDRESS_COST
283 #define TARGET_ADDRESS_COST hook_int_rtx_0
285 /* Return TRUE if the promotion described by PROMOTE_MODE should also be done
286 for outgoing function arguments.
287 This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
288 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
290 #undef TARGET_PROMOTE_FUNCTION_ARGS
291 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
293 /* Return TRUE if the promotion described by PROMOTE_MODE should also be done
294 for the return value of functions. If this macro is defined, FUNCTION_VALUE
295 must perform the same promotions done by PROMOTE_MODE.
296 This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
297 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
299 #undef TARGET_PROMOTE_FUNCTION_RETURN
300 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
302 #undef TARGET_PROMOTE_PROTOTYPES
303 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
305 #undef TARGET_STRUCT_VALUE_RTX
306 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
307 #undef TARGET_RETURN_IN_MEMORY
308 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
310 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
311 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
312 #undef TARGET_STRICT_ARGUMENT_NAMING
313 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
315 struct gcc_target targetm = TARGET_INITIALIZER;
317 /* Validate and override various options, and do some machine dependent
321 sparc_override_options (void)
323 static struct code_model {
324 const char *const name;
326 } const cmodels[] = {
328 { "medlow", CM_MEDLOW },
329 { "medmid", CM_MEDMID },
330 { "medany", CM_MEDANY },
331 { "embmedany", CM_EMBMEDANY },
334 const struct code_model *cmodel;
335 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
336 static struct cpu_default {
338 const char *const name;
339 } const cpu_default[] = {
340 /* There must be one entry here for each TARGET_CPU value. */
341 { TARGET_CPU_sparc, "cypress" },
342 { TARGET_CPU_sparclet, "tsc701" },
343 { TARGET_CPU_sparclite, "f930" },
344 { TARGET_CPU_v8, "v8" },
345 { TARGET_CPU_hypersparc, "hypersparc" },
346 { TARGET_CPU_sparclite86x, "sparclite86x" },
347 { TARGET_CPU_supersparc, "supersparc" },
348 { TARGET_CPU_v9, "v9" },
349 { TARGET_CPU_ultrasparc, "ultrasparc" },
350 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
353 const struct cpu_default *def;
354 /* Table of values for -m{cpu,tune}=. */
355 static struct cpu_table {
356 const char *const name;
357 const enum processor_type processor;
360 } const cpu_table[] = {
361 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
362 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
363 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
364 /* TI TMS390Z55 supersparc */
365 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
366 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
367 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
368 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
369 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
370 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
371 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
372 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
374 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
376 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
377 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
378 /* TI ultrasparc I, II, IIi */
379 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
380 /* Although insns using %y are deprecated, it is a clear win on current
382 |MASK_DEPRECATED_V8_INSNS},
383 /* TI ultrasparc III */
384 /* ??? Check if %y issue still holds true in ultra3. */
385 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
388 const struct cpu_table *cpu;
389 const struct sparc_cpu_select *sel;
392 #ifndef SPARC_BI_ARCH
393 /* Check for unsupported architecture size. */
394 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
395 error ("%s is not supported by this configuration",
396 DEFAULT_ARCH32_P ? "-m64" : "-m32");
399 /* We force all 64bit archs to use 128 bit long double */
400 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
402 error ("-mlong-double-64 not allowed with -m64");
403 target_flags |= MASK_LONG_DOUBLE_128;
406 /* Code model selection. */
407 sparc_cmodel = SPARC_DEFAULT_CMODEL;
411 sparc_cmodel = CM_32;
414 if (sparc_cmodel_string != NULL)
418 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
419 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
421 if (cmodel->name == NULL)
422 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
424 sparc_cmodel = cmodel->value;
427 error ("-mcmodel= is not supported on 32 bit systems");
430 fpu = TARGET_FPU; /* save current -mfpu status */
432 /* Set the default CPU. */
433 for (def = &cpu_default[0]; def->name; ++def)
434 if (def->cpu == TARGET_CPU_DEFAULT)
438 sparc_select[0].string = def->name;
440 for (sel = &sparc_select[0]; sel->name; ++sel)
444 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
445 if (! strcmp (sel->string, cpu->name))
448 sparc_cpu = cpu->processor;
452 target_flags &= ~cpu->disable;
453 target_flags |= cpu->enable;
459 error ("bad value (%s) for %s switch", sel->string, sel->name);
463 /* If -mfpu or -mno-fpu was explicitly used, don't override with
464 the processor default. Clear MASK_FPU_SET to avoid confusing
465 the reverse mapping from switch values to names. */
468 target_flags = (target_flags & ~MASK_FPU) | fpu;
469 target_flags &= ~MASK_FPU_SET;
472 /* Don't allow -mvis if FPU is disabled. */
474 target_flags &= ~MASK_VIS;
476 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
478 -m64 also implies v9. */
479 if (TARGET_VIS || TARGET_ARCH64)
481 target_flags |= MASK_V9;
482 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
485 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
486 if (TARGET_V9 && TARGET_ARCH32)
487 target_flags |= MASK_DEPRECATED_V8_INSNS;
489 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
490 if (! TARGET_V9 || TARGET_ARCH64)
491 target_flags &= ~MASK_V8PLUS;
493 /* Don't use stack biasing in 32 bit mode. */
495 target_flags &= ~MASK_STACK_BIAS;
497 /* Supply a default value for align_functions. */
498 if (align_functions == 0
499 && (sparc_cpu == PROCESSOR_ULTRASPARC
500 || sparc_cpu == PROCESSOR_ULTRASPARC3))
501 align_functions = 32;
503 /* Validate PCC_STRUCT_RETURN. */
504 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
505 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
507 /* Only use .uaxword when compiling for a 64-bit target. */
509 targetm.asm_out.unaligned_op.di = NULL;
511 /* Do various machine dependent initializations. */
514 /* Set up function hooks. */
515 init_machine_status = sparc_init_machine_status;
518 /* Miscellaneous utilities. */
520 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
521 or branch on register contents instructions. */
524 v9_regcmp_p (enum rtx_code code)
526 return (code == EQ || code == NE || code == GE || code == LT
527 || code == LE || code == GT);
531 /* Operand constraints. */
533 /* Return nonzero only if OP is a register of mode MODE,
537 reg_or_0_operand (rtx op, enum machine_mode mode)
539 if (register_operand (op, mode))
541 if (op == const0_rtx)
543 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
544 && CONST_DOUBLE_HIGH (op) == 0
545 && CONST_DOUBLE_LOW (op) == 0)
547 if (fp_zero_operand (op, mode))
552 /* Return nonzero only if OP is const1_rtx. */
555 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
557 return op == const1_rtx;
560 /* Nonzero if OP is a floating point value with value 0.0. */
563 fp_zero_operand (rtx op, enum machine_mode mode)
565 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
567 return op == CONST0_RTX (mode);
570 /* Nonzero if OP is a register operand in floating point register. */
573 fp_register_operand (rtx op, enum machine_mode mode)
575 if (! register_operand (op, mode))
577 if (GET_CODE (op) == SUBREG)
578 op = SUBREG_REG (op);
579 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
582 /* Nonzero if OP is a floating point constant which can
583 be loaded into an integer register using a single
584 sethi instruction. */
589 if (GET_CODE (op) == CONST_DOUBLE)
594 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
595 if (REAL_VALUES_EQUAL (r, dconst0) &&
596 ! REAL_VALUE_MINUS_ZERO (r))
598 REAL_VALUE_TO_TARGET_SINGLE (r, i);
599 if (SPARC_SETHI_P (i))
606 /* Nonzero if OP is a floating point constant which can
607 be loaded into an integer register using a single
613 if (GET_CODE (op) == CONST_DOUBLE)
618 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
619 if (REAL_VALUES_EQUAL (r, dconst0) &&
620 ! REAL_VALUE_MINUS_ZERO (r))
622 REAL_VALUE_TO_TARGET_SINGLE (r, i);
623 if (SPARC_SIMM13_P (i))
630 /* Nonzero if OP is a floating point constant which can
631 be loaded into an integer register using a high/losum
632 instruction sequence. */
635 fp_high_losum_p (rtx op)
637 /* The constraints calling this should only be in
638 SFmode move insns, so any constant which cannot
639 be moved using a single insn will do. */
640 if (GET_CODE (op) == CONST_DOUBLE)
645 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
646 if (REAL_VALUES_EQUAL (r, dconst0) &&
647 ! REAL_VALUE_MINUS_ZERO (r))
649 REAL_VALUE_TO_TARGET_SINGLE (r, i);
650 if (! SPARC_SETHI_P (i)
651 && ! SPARC_SIMM13_P (i))
658 /* Nonzero if OP is an integer register. */
661 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
663 return (register_operand (op, SImode)
664 || (TARGET_ARCH64 && register_operand (op, DImode)));
667 /* Nonzero if OP is a floating point condition code register. */
670 fcc_reg_operand (rtx op, enum machine_mode mode)
672 /* This can happen when recog is called from combine. Op may be a MEM.
673 Fail instead of calling abort in this case. */
674 if (GET_CODE (op) != REG)
677 if (mode != VOIDmode && mode != GET_MODE (op))
680 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
683 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
684 if (reg_renumber == 0)
685 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
686 return REGNO_OK_FOR_CCFP_P (REGNO (op));
688 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
692 /* Nonzero if OP is a floating point condition code fcc0 register. */
695 fcc0_reg_operand (rtx op, enum machine_mode mode)
697 /* This can happen when recog is called from combine. Op may be a MEM.
698 Fail instead of calling abort in this case. */
699 if (GET_CODE (op) != REG)
702 if (mode != VOIDmode && mode != GET_MODE (op))
705 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
708 return REGNO (op) == SPARC_FCC_REG;
711 /* Nonzero if OP is an integer or floating point condition code register. */
714 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
716 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
718 if (mode != VOIDmode && mode != GET_MODE (op))
721 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
726 return fcc_reg_operand (op, mode);
729 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
731 restore_operand (rtx op, enum machine_mode mode)
733 return (GET_CODE (op) == REG && GET_MODE (op) == mode
734 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
737 /* Call insn on SPARC can take a PC-relative constant address, or any regular
741 call_operand (rtx op, enum machine_mode mode)
743 if (GET_CODE (op) != MEM)
746 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
750 call_operand_address (rtx op, enum machine_mode mode)
752 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
755 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
756 otherwise return 0. */
759 tls_symbolic_operand (rtx op)
761 if (GET_CODE (op) != SYMBOL_REF)
763 return SYMBOL_REF_TLS_MODEL (op);
767 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
769 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
773 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
775 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
779 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
781 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
785 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
787 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
790 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
791 reference and a constant. */
794 symbolic_operand (register rtx op, enum machine_mode mode)
796 enum machine_mode omode = GET_MODE (op);
798 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
801 switch (GET_CODE (op))
804 return !SYMBOL_REF_TLS_MODEL (op);
811 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
812 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
813 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
814 && GET_CODE (XEXP (op, 1)) == CONST_INT);
821 /* Return truth value of statement that OP is a symbolic memory
822 operand of mode MODE. */
825 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
827 if (GET_CODE (op) == SUBREG)
828 op = SUBREG_REG (op);
829 if (GET_CODE (op) != MEM)
832 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
833 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
834 || GET_CODE (op) == LABEL_REF);
837 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
840 label_ref_operand (rtx op, enum machine_mode mode)
842 if (GET_CODE (op) != LABEL_REF)
844 if (GET_MODE (op) != mode)
849 /* Return 1 if the operand is an argument used in generating pic references
850 in either the medium/low or medium/anywhere code models of sparc64. */
853 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
855 /* Check for (const (minus (symbol_ref:GOT)
856 (const (minus (label) (pc))))). */
857 if (GET_CODE (op) != CONST)
860 if (GET_CODE (op) != MINUS)
862 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
864 /* ??? Ensure symbol is GOT. */
865 if (GET_CODE (XEXP (op, 1)) != CONST)
867 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
872 /* Return 1 if the operand is a data segment reference. This includes
873 the readonly data segment, or in other words anything but the text segment.
874 This is needed in the medium/anywhere code model on v9. These values
875 are accessed with EMBMEDANY_BASE_REG. */
878 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
880 switch (GET_CODE (op))
883 return ! SYMBOL_REF_FUNCTION_P (op);
885 /* Assume canonical format of symbol + constant.
888 return data_segment_operand (XEXP (op, 0), VOIDmode);
894 /* Return 1 if the operand is a text segment reference.
895 This is needed in the medium/anywhere code model on v9. */
898 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
900 switch (GET_CODE (op))
905 return SYMBOL_REF_FUNCTION_P (op);
907 /* Assume canonical format of symbol + constant.
910 return text_segment_operand (XEXP (op, 0), VOIDmode);
916 /* Return 1 if the operand is either a register or a memory operand that is
920 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
922 if (register_operand (op, mode))
925 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
932 splittable_symbolic_memory_operand (rtx op,
933 enum machine_mode mode ATTRIBUTE_UNUSED)
935 if (GET_CODE (op) != MEM)
937 if (! symbolic_operand (XEXP (op, 0), Pmode))
943 splittable_immediate_memory_operand (rtx op,
944 enum machine_mode mode ATTRIBUTE_UNUSED)
946 if (GET_CODE (op) != MEM)
948 if (! immediate_operand (XEXP (op, 0), Pmode))
953 /* Return truth value of whether OP is EQ or NE. */
956 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
958 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
961 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
962 or LTU for non-floating-point. We handle those specially. */
965 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
967 enum rtx_code code = GET_CODE (op);
969 if (GET_RTX_CLASS (code) != '<')
972 if (GET_MODE (XEXP (op, 0)) == CCFPmode
973 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
976 return (code != NE && code != EQ && code != GEU && code != LTU);
979 /* Return 1 if this is a comparison operator. This allows the use of
980 MATCH_OPERATOR to recognize all the branch insns. */
983 noov_compare_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
985 enum rtx_code code = GET_CODE (op);
987 if (GET_RTX_CLASS (code) != '<')
990 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
991 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
992 /* These are the only branches which work with CC_NOOVmode. */
993 return (code == EQ || code == NE || code == GE || code == LT);
997 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
998 MATCH_OPERATOR to recognize all the branch insns. */
1001 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1003 enum rtx_code code = GET_CODE (op);
1008 if (GET_RTX_CLASS (code) != '<')
1011 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1012 /* These are the only branches which work with CCX_NOOVmode. */
1013 return (code == EQ || code == NE || code == GE || code == LT);
1014 return (GET_MODE (XEXP (op, 0)) == CCXmode);
1017 /* Nonzero if OP is a comparison operator suitable for use in v9
1018 conditional move or branch on register contents instructions. */
1021 v9_regcmp_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1023 enum rtx_code code = GET_CODE (op);
1025 if (GET_RTX_CLASS (code) != '<')
1028 return v9_regcmp_p (code);
1031 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1034 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1036 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1039 /* Return nonzero if OP is an operator of mode MODE which can set
1040 the condition codes explicitly. We do not include PLUS and MINUS
1041 because these require CC_NOOVmode, which we handle explicitly. */
1044 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1046 if (GET_CODE (op) == AND
1047 || GET_CODE (op) == IOR
1048 || GET_CODE (op) == XOR)
1054 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1055 complement its second operand and set the condition codes explicitly. */
1058 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1060 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1061 and (xor ... (not ...)) to (not (xor ...)). */
1062 return (GET_CODE (op) == AND
1063 || GET_CODE (op) == IOR);
1066 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1067 signed 13 bit immediate field. This is an acceptable SImode operand for
1068 most 3 address instructions. */
1071 arith_operand (rtx op, enum machine_mode mode)
1073 if (register_operand (op, mode))
1075 if (GET_CODE (op) != CONST_INT)
1077 return SMALL_INT32 (op);
1080 /* Return true if OP is a constant 4096 */
1083 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1085 if (GET_CODE (op) != CONST_INT)
1088 return INTVAL (op) == 4096;
1091 /* Return true if OP is suitable as second operand for add/sub */
1094 arith_add_operand (rtx op, enum machine_mode mode)
1096 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1099 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1100 immediate field of OR and XOR instructions. Used for 64-bit
1101 constant formation patterns. */
1103 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1105 return ((GET_CODE (op) == CONST_INT
1106 && SPARC_SIMM13_P (INTVAL (op)))
1107 #if HOST_BITS_PER_WIDE_INT != 64
1108 || (GET_CODE (op) == CONST_DOUBLE
1109 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1110 && (CONST_DOUBLE_HIGH (op) ==
1111 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1112 (HOST_WIDE_INT)-1 : 0)))
1117 /* The same, but only for sethi instructions. */
1119 const64_high_operand (rtx op, enum machine_mode mode)
1121 return ((GET_CODE (op) == CONST_INT
1122 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1123 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1125 || (GET_CODE (op) == CONST_DOUBLE
1126 && CONST_DOUBLE_HIGH (op) == 0
1127 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1128 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1131 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1132 signed 11 bit immediate field. This is an acceptable SImode operand for
1133 the movcc instructions. */
1136 arith11_operand (rtx op, enum machine_mode mode)
1138 return (register_operand (op, mode)
1139 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1142 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1143 signed 10 bit immediate field. This is an acceptable SImode operand for
1144 the movrcc instructions. */
1147 arith10_operand (rtx op, enum machine_mode mode)
1149 return (register_operand (op, mode)
1150 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1153 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1154 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1156 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1157 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1158 for most 3 address instructions. */
1161 arith_double_operand (rtx op, enum machine_mode mode)
1163 return (register_operand (op, mode)
1164 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1166 && GET_CODE (op) == CONST_DOUBLE
1167 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1168 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1170 && GET_CODE (op) == CONST_DOUBLE
1171 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1172 && ((CONST_DOUBLE_HIGH (op) == -1
1173 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1174 || (CONST_DOUBLE_HIGH (op) == 0
1175 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1178 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1181 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1183 return (TARGET_ARCH64 &&
1184 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1185 (GET_CODE (op) == CONST_DOUBLE &&
1186 CONST_DOUBLE_LOW (op) == 4096 &&
1187 CONST_DOUBLE_HIGH (op) == 0)));
1190 /* Return true if OP is suitable as second operand for add/sub in DImode */
1193 arith_double_add_operand (rtx op, enum machine_mode mode)
1195 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1198 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1199 can fit in an 11 bit immediate field. This is an acceptable DImode
1200 operand for the movcc instructions. */
1201 /* ??? Replace with arith11_operand? */
1204 arith11_double_operand (rtx op, enum machine_mode mode)
1206 return (register_operand (op, mode)
1207 || (GET_CODE (op) == CONST_DOUBLE
1208 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1209 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1210 && ((CONST_DOUBLE_HIGH (op) == -1
1211 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1212 || (CONST_DOUBLE_HIGH (op) == 0
1213 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1214 || (GET_CODE (op) == CONST_INT
1215 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1216 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1219 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1220 can fit in an 10 bit immediate field. This is an acceptable DImode
1221 operand for the movrcc instructions. */
1222 /* ??? Replace with arith10_operand? */
1225 arith10_double_operand (rtx op, enum machine_mode mode)
1227 return (register_operand (op, mode)
1228 || (GET_CODE (op) == CONST_DOUBLE
1229 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1230 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1231 && ((CONST_DOUBLE_HIGH (op) == -1
1232 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1233 || (CONST_DOUBLE_HIGH (op) == 0
1234 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1235 || (GET_CODE (op) == CONST_INT
1236 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1237 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1240 /* Return truth value of whether OP is an integer which fits the
1241 range constraining immediate operands in most three-address insns,
1242 which have a 13 bit immediate field. */
1245 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1247 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1251 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1253 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1254 || (GET_CODE (op) == CONST_DOUBLE
1255 && CONST_DOUBLE_HIGH (op) == 0
1256 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1259 /* Recognize operand values for the umul instruction. That instruction sign
1260 extends immediate values just like all other sparc instructions, but
1261 interprets the extended result as an unsigned number. */
1264 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1266 #if HOST_BITS_PER_WIDE_INT > 32
1267 /* All allowed constants will fit a CONST_INT. */
1268 return (GET_CODE (op) == CONST_INT
1269 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1270 || (INTVAL (op) >= 0xFFFFF000
1271 && INTVAL (op) <= 0xFFFFFFFF)));
1273 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1274 || (GET_CODE (op) == CONST_DOUBLE
1275 && CONST_DOUBLE_HIGH (op) == 0
1276 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1281 uns_arith_operand (rtx op, enum machine_mode mode)
1283 return register_operand (op, mode) || uns_small_int (op, mode);
1286 /* Return truth value of statement that OP is a call-clobbered register. */
1288 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1290 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1293 /* Return 1 if OP is a valid operand for the source of a move insn. */
1296 input_operand (rtx op, enum machine_mode mode)
1298 /* If both modes are non-void they must be the same. */
1299 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1302 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */
1303 if (GET_CODE (op) == CONSTANT_P_RTX)
1306 /* Allow any one instruction integer constant, and all CONST_INT
1307 variants when we are working in DImode and !arch64. */
1308 if (GET_MODE_CLASS (mode) == MODE_INT
1309 && ((GET_CODE (op) == CONST_INT
1310 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1311 || SPARC_SIMM13_P (INTVAL (op))
1313 && ! TARGET_ARCH64)))
1315 && GET_CODE (op) == CONST_DOUBLE
1316 && ((CONST_DOUBLE_HIGH (op) == 0
1317 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1319 #if HOST_BITS_PER_WIDE_INT == 64
1320 (CONST_DOUBLE_HIGH (op) == 0
1321 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1323 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1324 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1325 && CONST_DOUBLE_HIGH (op) == 0)
1326 || (CONST_DOUBLE_HIGH (op) == -1
1327 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1332 /* If !arch64 and this is a DImode const, allow it so that
1333 the splits can be generated. */
1336 && GET_CODE (op) == CONST_DOUBLE)
1339 if (register_operand (op, mode))
1342 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1343 && GET_CODE (op) == CONST_DOUBLE)
1346 /* If this is a SUBREG, look inside so that we handle
1347 paradoxical ones. */
1348 if (GET_CODE (op) == SUBREG)
1349 op = SUBREG_REG (op);
1351 /* Check for valid MEM forms. */
1352 if (GET_CODE (op) == MEM)
1354 rtx inside = XEXP (op, 0);
1356 if (GET_CODE (inside) == LO_SUM)
1358 /* We can't allow these because all of the splits
1359 (eventually as they trickle down into DFmode
1360 splits) require offsettable memory references. */
1362 && GET_MODE (op) == TFmode)
1365 return (register_operand (XEXP (inside, 0), Pmode)
1366 && CONSTANT_P (XEXP (inside, 1)));
1368 return memory_address_p (mode, inside);
1375 /* We know it can't be done in one insn when we get here,
1376 the movsi expander guarantees this. */
1378 sparc_emit_set_const32 (rtx op0, rtx op1)
1380 enum machine_mode mode = GET_MODE (op0);
1383 if (GET_CODE (op1) == CONST_INT)
1385 HOST_WIDE_INT value = INTVAL (op1);
1387 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1388 || SPARC_SIMM13_P (value))
1392 /* Full 2-insn decomposition is needed. */
1393 if (reload_in_progress || reload_completed)
1396 temp = gen_reg_rtx (mode);
1398 if (GET_CODE (op1) == CONST_INT)
1400 /* Emit them as real moves instead of a HIGH/LO_SUM,
1401 this way CSE can see everything and reuse intermediate
1402 values if it wants. */
1404 && HOST_BITS_PER_WIDE_INT != 64
1405 && (INTVAL (op1) & 0x80000000) != 0)
1406 emit_insn (gen_rtx_SET
1408 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1411 emit_insn (gen_rtx_SET (VOIDmode, temp,
1412 GEN_INT (INTVAL (op1)
1413 & ~(HOST_WIDE_INT)0x3ff)));
1415 emit_insn (gen_rtx_SET (VOIDmode,
1417 gen_rtx_IOR (mode, temp,
1418 GEN_INT (INTVAL (op1) & 0x3ff))));
1422 /* A symbol, emit in the traditional way. */
1423 emit_insn (gen_rtx_SET (VOIDmode, temp,
1424 gen_rtx_HIGH (mode, op1)));
1425 emit_insn (gen_rtx_SET (VOIDmode,
1426 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1432 /* SPARC-v9 code-model support. */
1434 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp1)
1438 if (temp1 && GET_MODE (temp1) == TImode)
1441 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1444 switch (sparc_cmodel)
1447 /* The range spanned by all instructions in the object is less
1448 than 2^31 bytes (2GB) and the distance from any instruction
1449 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1450 than 2^31 bytes (2GB).
1452 The executable must be in the low 4TB of the virtual address
1455 sethi %hi(symbol), %temp
1456 or %temp, %lo(symbol), %reg */
1457 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1458 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1462 /* The range spanned by all instructions in the object is less
1463 than 2^31 bytes (2GB) and the distance from any instruction
1464 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1465 than 2^31 bytes (2GB).
1467 The executable must be in the low 16TB of the virtual address
1470 sethi %h44(symbol), %temp1
1471 or %temp1, %m44(symbol), %temp2
1472 sllx %temp2, 12, %temp3
1473 or %temp3, %l44(symbol), %reg */
1474 emit_insn (gen_seth44 (op0, op1));
1475 emit_insn (gen_setm44 (op0, op0, op1));
1476 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1477 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1478 emit_insn (gen_setl44 (op0, temp1, op1));
1482 /* The range spanned by all instructions in the object is less
1483 than 2^31 bytes (2GB) and the distance from any instruction
1484 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1485 than 2^31 bytes (2GB).
1487 The executable can be placed anywhere in the virtual address
1490 sethi %hh(symbol), %temp1
1491 sethi %lm(symbol), %temp2
1492 or %temp1, %hm(symbol), %temp3
1493 or %temp2, %lo(symbol), %temp4
1494 sllx %temp3, 32, %temp5
1495 or %temp4, %temp5, %reg */
1497 /* It is possible that one of the registers we got for operands[2]
1498 might coincide with that of operands[0] (which is why we made
1499 it TImode). Pick the other one to use as our scratch. */
1500 if (rtx_equal_p (temp1, op0))
1503 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1508 emit_insn (gen_sethh (op0, op1));
1509 emit_insn (gen_setlm (temp1, op1));
1510 emit_insn (gen_sethm (op0, op0, op1));
1511 emit_insn (gen_rtx_SET (VOIDmode, op0,
1512 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1513 emit_insn (gen_rtx_SET (VOIDmode, op0,
1514 gen_rtx_PLUS (DImode, op0, temp1)));
1515 emit_insn (gen_setlo (op0, op0, op1));
1519 /* Old old old backwards compatibility kruft here.
1520 Essentially it is MEDLOW with a fixed 64-bit
1521 virtual base added to all data segment addresses.
1522 Text-segment stuff is computed like MEDANY, we can't
1523 reuse the code above because the relocation knobs
1526 Data segment: sethi %hi(symbol), %temp1
1527 or %temp1, %lo(symbol), %temp2
1528 add %temp2, EMBMEDANY_BASE_REG, %reg
1530 Text segment: sethi %uhi(symbol), %temp1
1531 sethi %hi(symbol), %temp2
1532 or %temp1, %ulo(symbol), %temp3
1533 or %temp2, %lo(symbol), %temp4
1534 sllx %temp3, 32, %temp5
1535 or %temp4, %temp5, %reg */
1536 if (data_segment_operand (op1, GET_MODE (op1)))
1538 emit_insn (gen_embmedany_sethi (temp1, op1));
1539 emit_insn (gen_embmedany_brsum (op0, temp1));
1540 emit_insn (gen_embmedany_losum (op0, op0, op1));
1544 /* It is possible that one of the registers we got for operands[2]
1545 might coincide with that of operands[0] (which is why we made
1546 it TImode). Pick the other one to use as our scratch. */
1547 if (rtx_equal_p (temp1, op0))
1550 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1555 emit_insn (gen_embmedany_textuhi (op0, op1));
1556 emit_insn (gen_embmedany_texthi (temp1, op1));
1557 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1558 emit_insn (gen_rtx_SET (VOIDmode, op0,
1559 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1560 emit_insn (gen_rtx_SET (VOIDmode, op0,
1561 gen_rtx_PLUS (DImode, op0, temp1)));
1562 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1571 /* These avoid problems when cross compiling. If we do not
1572 go through all this hair then the optimizer will see
1573 invalid REG_EQUAL notes or in some cases none at all. */
1574 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1575 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1576 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1577 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1579 #if HOST_BITS_PER_WIDE_INT == 64
1580 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1581 #define GEN_INT64(__x) GEN_INT (__x)
1583 #define GEN_HIGHINT64(__x) \
1584 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1585 #define GEN_INT64(__x) \
1586 immed_double_const ((__x) & 0xffffffff, \
1587 ((__x) & 0x80000000 ? -1 : 0), DImode)
1590 /* The optimizer is not to assume anything about exactly
1591 which bits are set for a HIGH, they are unspecified.
1592 Unfortunately this leads to many missed optimizations
1593 during CSE. We mask out the non-HIGH bits, and matches
1594 a plain movdi, to alleviate this problem. */
1596 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1598 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1602 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1604 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1608 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1610 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1614 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1616 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1619 /* Worker routines for 64-bit constant formation on arch64.
1620 One of the key things to be doing in these emissions is
1621 to create as many temp REGs as possible. This makes it
1622 possible for half-built constants to be used later when
1623 such values are similar to something required later on.
1624 Without doing this, the optimizer cannot see such
1627 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1628 unsigned HOST_WIDE_INT, int);
1631 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1632 unsigned HOST_WIDE_INT low_bits, int is_neg)
1634 unsigned HOST_WIDE_INT high_bits;
1637 high_bits = (~low_bits) & 0xffffffff;
1639 high_bits = low_bits;
1641 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1644 emit_insn (gen_rtx_SET (VOIDmode, op0,
1645 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1649 /* If we are XOR'ing with -1, then we should emit a one's complement
1650 instead. This way the combiner will notice logical operations
1651 such as ANDN later on and substitute. */
1652 if ((low_bits & 0x3ff) == 0x3ff)
1654 emit_insn (gen_rtx_SET (VOIDmode, op0,
1655 gen_rtx_NOT (DImode, temp)));
1659 emit_insn (gen_rtx_SET (VOIDmode, op0,
1660 gen_safe_XOR64 (temp,
1661 (-(HOST_WIDE_INT)0x400
1662 | (low_bits & 0x3ff)))));
1667 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1668 unsigned HOST_WIDE_INT, int);
1671 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1672 unsigned HOST_WIDE_INT high_bits,
1673 unsigned HOST_WIDE_INT low_immediate,
1678 if ((high_bits & 0xfffffc00) != 0)
1680 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1681 if ((high_bits & ~0xfffffc00) != 0)
1682 emit_insn (gen_rtx_SET (VOIDmode, op0,
1683 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1689 emit_insn (gen_safe_SET64 (temp, high_bits));
1693 /* Now shift it up into place. */
1694 emit_insn (gen_rtx_SET (VOIDmode, op0,
1695 gen_rtx_ASHIFT (DImode, temp2,
1696 GEN_INT (shift_count))));
1698 /* If there is a low immediate part piece, finish up by
1699 putting that in as well. */
1700 if (low_immediate != 0)
1701 emit_insn (gen_rtx_SET (VOIDmode, op0,
1702 gen_safe_OR64 (op0, low_immediate)));
1705 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1706 unsigned HOST_WIDE_INT);
1708 /* Full 64-bit constant decomposition. Even though this is the
1709 'worst' case, we still optimize a few things away. */
1711 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1712 unsigned HOST_WIDE_INT high_bits,
1713 unsigned HOST_WIDE_INT low_bits)
1717 if (reload_in_progress || reload_completed)
1720 sub_temp = gen_reg_rtx (DImode);
1722 if ((high_bits & 0xfffffc00) != 0)
1724 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1725 if ((high_bits & ~0xfffffc00) != 0)
1726 emit_insn (gen_rtx_SET (VOIDmode,
1728 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1734 emit_insn (gen_safe_SET64 (temp, high_bits));
1738 if (!reload_in_progress && !reload_completed)
1740 rtx temp2 = gen_reg_rtx (DImode);
1741 rtx temp3 = gen_reg_rtx (DImode);
1742 rtx temp4 = gen_reg_rtx (DImode);
1744 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1745 gen_rtx_ASHIFT (DImode, sub_temp,
1748 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1749 if ((low_bits & ~0xfffffc00) != 0)
1751 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1752 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1753 emit_insn (gen_rtx_SET (VOIDmode, op0,
1754 gen_rtx_PLUS (DImode, temp4, temp3)));
1758 emit_insn (gen_rtx_SET (VOIDmode, op0,
1759 gen_rtx_PLUS (DImode, temp4, temp2)));
1764 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1765 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1766 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1769 /* We are in the middle of reload, so this is really
1770 painful. However we do still make an attempt to
1771 avoid emitting truly stupid code. */
1772 if (low1 != const0_rtx)
1774 emit_insn (gen_rtx_SET (VOIDmode, op0,
1775 gen_rtx_ASHIFT (DImode, sub_temp,
1776 GEN_INT (to_shift))));
1777 emit_insn (gen_rtx_SET (VOIDmode, op0,
1778 gen_rtx_IOR (DImode, op0, low1)));
1786 if (low2 != const0_rtx)
1788 emit_insn (gen_rtx_SET (VOIDmode, op0,
1789 gen_rtx_ASHIFT (DImode, sub_temp,
1790 GEN_INT (to_shift))));
1791 emit_insn (gen_rtx_SET (VOIDmode, op0,
1792 gen_rtx_IOR (DImode, op0, low2)));
1800 emit_insn (gen_rtx_SET (VOIDmode, op0,
1801 gen_rtx_ASHIFT (DImode, sub_temp,
1802 GEN_INT (to_shift))));
1803 if (low3 != const0_rtx)
1804 emit_insn (gen_rtx_SET (VOIDmode, op0,
1805 gen_rtx_IOR (DImode, op0, low3)));
1810 /* Analyze a 64-bit constant for certain properties. */
1811 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1812 unsigned HOST_WIDE_INT,
1813 int *, int *, int *);
1816 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1817 unsigned HOST_WIDE_INT low_bits,
1818 int *hbsp, int *lbsp, int *abbasp)
1820 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1823 lowest_bit_set = highest_bit_set = -1;
1827 if ((lowest_bit_set == -1)
1828 && ((low_bits >> i) & 1))
1830 if ((highest_bit_set == -1)
1831 && ((high_bits >> (32 - i - 1)) & 1))
1832 highest_bit_set = (64 - i - 1);
1835 && ((highest_bit_set == -1)
1836 || (lowest_bit_set == -1)));
1842 if ((lowest_bit_set == -1)
1843 && ((high_bits >> i) & 1))
1844 lowest_bit_set = i + 32;
1845 if ((highest_bit_set == -1)
1846 && ((low_bits >> (32 - i - 1)) & 1))
1847 highest_bit_set = 32 - i - 1;
1850 && ((highest_bit_set == -1)
1851 || (lowest_bit_set == -1)));
1853 /* If there are no bits set this should have gone out
1854 as one instruction! */
1855 if (lowest_bit_set == -1
1856 || highest_bit_set == -1)
1858 all_bits_between_are_set = 1;
1859 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1863 if ((low_bits & (1 << i)) != 0)
1868 if ((high_bits & (1 << (i - 32))) != 0)
1871 all_bits_between_are_set = 0;
1874 *hbsp = highest_bit_set;
1875 *lbsp = lowest_bit_set;
1876 *abbasp = all_bits_between_are_set;
1879 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1882 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1883 unsigned HOST_WIDE_INT low_bits)
1885 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1888 || high_bits == 0xffffffff)
1891 analyze_64bit_constant (high_bits, low_bits,
1892 &highest_bit_set, &lowest_bit_set,
1893 &all_bits_between_are_set);
1895 if ((highest_bit_set == 63
1896 || lowest_bit_set == 0)
1897 && all_bits_between_are_set != 0)
1900 if ((highest_bit_set - lowest_bit_set) < 21)
1906 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1907 unsigned HOST_WIDE_INT,
1910 static unsigned HOST_WIDE_INT
1911 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1912 unsigned HOST_WIDE_INT low_bits,
1913 int lowest_bit_set, int shift)
1915 HOST_WIDE_INT hi, lo;
1917 if (lowest_bit_set < 32)
1919 lo = (low_bits >> lowest_bit_set) << shift;
1920 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1925 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1932 /* Here we are sure to be arch64 and this is an integer constant
1933 being loaded into a register. Emit the most efficient
1934 insn sequence possible. Detection of all the 1-insn cases
1935 has been done already. */
1937 sparc_emit_set_const64 (rtx op0, rtx op1)
1939 unsigned HOST_WIDE_INT high_bits, low_bits;
1940 int lowest_bit_set, highest_bit_set;
1941 int all_bits_between_are_set;
1944 /* Sanity check that we know what we are working with. */
1945 if (! TARGET_ARCH64)
1948 if (GET_CODE (op0) != SUBREG)
1950 if (GET_CODE (op0) != REG
1951 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1952 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1956 if (reload_in_progress || reload_completed)
1959 temp = gen_reg_rtx (DImode);
1961 if (GET_CODE (op1) != CONST_DOUBLE
1962 && GET_CODE (op1) != CONST_INT)
1964 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1968 if (GET_CODE (op1) == CONST_DOUBLE)
1970 #if HOST_BITS_PER_WIDE_INT == 64
1971 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1972 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1974 high_bits = CONST_DOUBLE_HIGH (op1);
1975 low_bits = CONST_DOUBLE_LOW (op1);
1980 #if HOST_BITS_PER_WIDE_INT == 64
1981 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1982 low_bits = (INTVAL (op1) & 0xffffffff);
1984 high_bits = ((INTVAL (op1) < 0) ?
1987 low_bits = INTVAL (op1);
1991 /* low_bits bits 0 --> 31
1992 high_bits bits 32 --> 63 */
1994 analyze_64bit_constant (high_bits, low_bits,
1995 &highest_bit_set, &lowest_bit_set,
1996 &all_bits_between_are_set);
1998 /* First try for a 2-insn sequence. */
2000 /* These situations are preferred because the optimizer can
2001 * do more things with them:
2003 * sllx %reg, shift, %reg
2005 * srlx %reg, shift, %reg
2006 * 3) mov some_small_const, %reg
2007 * sllx %reg, shift, %reg
2009 if (((highest_bit_set == 63
2010 || lowest_bit_set == 0)
2011 && all_bits_between_are_set != 0)
2012 || ((highest_bit_set - lowest_bit_set) < 12))
2014 HOST_WIDE_INT the_const = -1;
2015 int shift = lowest_bit_set;
2017 if ((highest_bit_set != 63
2018 && lowest_bit_set != 0)
2019 || all_bits_between_are_set == 0)
2022 create_simple_focus_bits (high_bits, low_bits,
2025 else if (lowest_bit_set == 0)
2026 shift = -(63 - highest_bit_set);
2028 if (! SPARC_SIMM13_P (the_const))
2031 emit_insn (gen_safe_SET64 (temp, the_const));
2033 emit_insn (gen_rtx_SET (VOIDmode,
2035 gen_rtx_ASHIFT (DImode,
2039 emit_insn (gen_rtx_SET (VOIDmode,
2041 gen_rtx_LSHIFTRT (DImode,
2043 GEN_INT (-shift))));
2049 /* Now a range of 22 or less bits set somewhere.
2050 * 1) sethi %hi(focus_bits), %reg
2051 * sllx %reg, shift, %reg
2052 * 2) sethi %hi(focus_bits), %reg
2053 * srlx %reg, shift, %reg
2055 if ((highest_bit_set - lowest_bit_set) < 21)
2057 unsigned HOST_WIDE_INT focus_bits =
2058 create_simple_focus_bits (high_bits, low_bits,
2059 lowest_bit_set, 10);
2061 if (! SPARC_SETHI_P (focus_bits))
2064 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2066 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2067 if (lowest_bit_set < 10)
2068 emit_insn (gen_rtx_SET (VOIDmode,
2070 gen_rtx_LSHIFTRT (DImode, temp,
2071 GEN_INT (10 - lowest_bit_set))));
2072 else if (lowest_bit_set > 10)
2073 emit_insn (gen_rtx_SET (VOIDmode,
2075 gen_rtx_ASHIFT (DImode, temp,
2076 GEN_INT (lowest_bit_set - 10))));
2082 /* 1) sethi %hi(low_bits), %reg
2083 * or %reg, %lo(low_bits), %reg
2084 * 2) sethi %hi(~low_bits), %reg
2085 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2088 || high_bits == 0xffffffff)
2090 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2091 (high_bits == 0xffffffff));
2095 /* Now, try 3-insn sequences. */
2097 /* 1) sethi %hi(high_bits), %reg
2098 * or %reg, %lo(high_bits), %reg
2099 * sllx %reg, 32, %reg
2103 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2107 /* We may be able to do something quick
2108 when the constant is negated, so try that. */
2109 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2110 (~low_bits) & 0xfffffc00))
2112 /* NOTE: The trailing bits get XOR'd so we need the
2113 non-negated bits, not the negated ones. */
2114 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2116 if ((((~high_bits) & 0xffffffff) == 0
2117 && ((~low_bits) & 0x80000000) == 0)
2118 || (((~high_bits) & 0xffffffff) == 0xffffffff
2119 && ((~low_bits) & 0x80000000) != 0))
2121 int fast_int = (~low_bits & 0xffffffff);
2123 if ((SPARC_SETHI_P (fast_int)
2124 && (~high_bits & 0xffffffff) == 0)
2125 || SPARC_SIMM13_P (fast_int))
2126 emit_insn (gen_safe_SET64 (temp, fast_int));
2128 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2133 #if HOST_BITS_PER_WIDE_INT == 64
2134 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2135 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2137 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2138 (~high_bits) & 0xffffffff,
2141 sparc_emit_set_const64 (temp, negated_const);
2144 /* If we are XOR'ing with -1, then we should emit a one's complement
2145 instead. This way the combiner will notice logical operations
2146 such as ANDN later on and substitute. */
2147 if (trailing_bits == 0x3ff)
2149 emit_insn (gen_rtx_SET (VOIDmode, op0,
2150 gen_rtx_NOT (DImode, temp)));
2154 emit_insn (gen_rtx_SET (VOIDmode,
2156 gen_safe_XOR64 (temp,
2157 (-0x400 | trailing_bits))));
2162 /* 1) sethi %hi(xxx), %reg
2163 * or %reg, %lo(xxx), %reg
2164 * sllx %reg, yyy, %reg
2166 * ??? This is just a generalized version of the low_bits==0
2167 * thing above, FIXME...
2169 if ((highest_bit_set - lowest_bit_set) < 32)
2171 unsigned HOST_WIDE_INT focus_bits =
2172 create_simple_focus_bits (high_bits, low_bits,
2175 /* We can't get here in this state. */
2176 if (highest_bit_set < 32
2177 || lowest_bit_set >= 32)
2180 /* So what we know is that the set bits straddle the
2181 middle of the 64-bit word. */
2182 sparc_emit_set_const64_quick2 (op0, temp,
2188 /* 1) sethi %hi(high_bits), %reg
2189 * or %reg, %lo(high_bits), %reg
2190 * sllx %reg, 32, %reg
2191 * or %reg, low_bits, %reg
2193 if (SPARC_SIMM13_P(low_bits)
2194 && ((int)low_bits > 0))
2196 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2200 /* The easiest way when all else fails, is full decomposition. */
2202 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2203 high_bits, low_bits, ~high_bits, ~low_bits);
2205 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2208 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2209 return the mode to be used for the comparison. For floating-point,
2210 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2211 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2212 processing is needed. */
2215 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2217 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2243 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2244 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2246 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2247 return CCX_NOOVmode;
2253 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2260 /* X and Y are two things to compare using CODE. Emit the compare insn and
2261 return the rtx for the cc reg in the proper mode. */
2264 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2266 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2269 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2270 fcc regs (cse can't tell they're really call clobbered regs and will
2271 remove a duplicate comparison even if there is an intervening function
2272 call - it will then try to reload the cc reg via an int reg which is why
2273 we need the movcc patterns). It is possible to provide the movcc
2274 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2275 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2276 to tell cse that CCFPE mode registers (even pseudos) are call
2279 /* ??? This is an experiment. Rather than making changes to cse which may
2280 or may not be easy/clean, we do our own cse. This is possible because
2281 we will generate hard registers. Cse knows they're call clobbered (it
2282 doesn't know the same thing about pseudos). If we guess wrong, no big
2283 deal, but if we win, great! */
2285 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2286 #if 1 /* experiment */
2289 /* We cycle through the registers to ensure they're all exercised. */
2290 static int next_fcc_reg = 0;
2291 /* Previous x,y for each fcc reg. */
2292 static rtx prev_args[4][2];
2294 /* Scan prev_args for x,y. */
2295 for (reg = 0; reg < 4; reg++)
2296 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2301 prev_args[reg][0] = x;
2302 prev_args[reg][1] = y;
2303 next_fcc_reg = (next_fcc_reg + 1) & 3;
2305 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2308 cc_reg = gen_reg_rtx (mode);
2309 #endif /* ! experiment */
2310 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2311 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2313 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2315 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2316 gen_rtx_COMPARE (mode, x, y)));
2321 /* This function is used for v9 only.
2322 CODE is the code for an Scc's comparison.
2323 OPERANDS[0] is the target of the Scc insn.
2324 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2325 been generated yet).
2327 This function is needed to turn
2330 (gt (reg:CCX 100 %icc)
2334 (gt:DI (reg:CCX 100 %icc)
2337 IE: The instruction recognizer needs to see the mode of the comparison to
2338 find the right instruction. We could use "gt:DI" right in the
2339 define_expand, but leaving it out allows us to handle DI, SI, etc.
2341 We refer to the global sparc compare operands sparc_compare_op0 and
2342 sparc_compare_op1. */
2345 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2350 && (GET_MODE (sparc_compare_op0) == DImode
2351 || GET_MODE (operands[0]) == DImode))
2354 op0 = sparc_compare_op0;
2355 op1 = sparc_compare_op1;
2357 /* Try to use the movrCC insns. */
2359 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2360 && op1 == const0_rtx
2361 && v9_regcmp_p (compare_code))
2363 /* Special case for op0 != 0. This can be done with one instruction if
2364 operands[0] == sparc_compare_op0. */
2366 if (compare_code == NE
2367 && GET_MODE (operands[0]) == DImode
2368 && rtx_equal_p (op0, operands[0]))
2370 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2371 gen_rtx_IF_THEN_ELSE (DImode,
2372 gen_rtx_fmt_ee (compare_code, DImode,
2379 if (reg_overlap_mentioned_p (operands[0], op0))
2381 /* Handle the case where operands[0] == sparc_compare_op0.
2382 We "early clobber" the result. */
2383 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2384 emit_move_insn (op0, sparc_compare_op0);
2387 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2388 if (GET_MODE (op0) != DImode)
2390 temp = gen_reg_rtx (DImode);
2391 convert_move (temp, op0, 0);
2395 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2396 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2397 gen_rtx_fmt_ee (compare_code, DImode,
2405 operands[1] = gen_compare_reg (compare_code, op0, op1);
2407 switch (GET_MODE (operands[1]))
2417 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2418 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2419 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2420 gen_rtx_fmt_ee (compare_code,
2421 GET_MODE (operands[1]),
2422 operands[1], const0_rtx),
2423 const1_rtx, operands[0])));
2428 /* Emit a conditional jump insn for the v9 architecture using comparison code
2429 CODE and jump target LABEL.
2430 This function exists to take advantage of the v9 brxx insns. */
2433 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2435 emit_jump_insn (gen_rtx_SET (VOIDmode,
2437 gen_rtx_IF_THEN_ELSE (VOIDmode,
2438 gen_rtx_fmt_ee (code, GET_MODE (op0),
2440 gen_rtx_LABEL_REF (VOIDmode, label),
2444 /* Generate a DFmode part of a hard TFmode register.
2445 REG is the TFmode hard register, LOW is 1 for the
2446 low 64bit of the register and 0 otherwise.
2449 gen_df_reg (rtx reg, int low)
2451 int regno = REGNO (reg);
2453 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2454 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2455 return gen_rtx_REG (DFmode, regno);
2458 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2459 Unlike normal calls, TFmode operands are passed by reference. It is
2460 assumed that no more than 3 operands are required. */
2463 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2465 rtx ret_slot = NULL, arg[3], func_sym;
2468 /* We only expect to be called for conversions, unary, and binary ops. */
2469 if (nargs < 2 || nargs > 3)
2472 for (i = 0; i < nargs; ++i)
2474 rtx this_arg = operands[i];
2477 /* TFmode arguments and return values are passed by reference. */
2478 if (GET_MODE (this_arg) == TFmode)
2480 int force_stack_temp;
2482 force_stack_temp = 0;
2483 if (TARGET_BUGGY_QP_LIB && i == 0)
2484 force_stack_temp = 1;
2486 if (GET_CODE (this_arg) == MEM
2487 && ! force_stack_temp)
2488 this_arg = XEXP (this_arg, 0);
2489 else if (CONSTANT_P (this_arg)
2490 && ! force_stack_temp)
2492 this_slot = force_const_mem (TFmode, this_arg);
2493 this_arg = XEXP (this_slot, 0);
2497 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2499 /* Operand 0 is the return value. We'll copy it out later. */
2501 emit_move_insn (this_slot, this_arg);
2503 ret_slot = this_slot;
2505 this_arg = XEXP (this_slot, 0);
2512 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2514 if (GET_MODE (operands[0]) == TFmode)
2517 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2518 arg[0], GET_MODE (arg[0]),
2519 arg[1], GET_MODE (arg[1]));
2521 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2522 arg[0], GET_MODE (arg[0]),
2523 arg[1], GET_MODE (arg[1]),
2524 arg[2], GET_MODE (arg[2]));
2527 emit_move_insn (operands[0], ret_slot);
2536 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2537 GET_MODE (operands[0]), 1,
2538 arg[1], GET_MODE (arg[1]));
2540 if (ret != operands[0])
2541 emit_move_insn (operands[0], ret);
2545 /* Expand soft-float TFmode calls to sparc abi routines. */
2548 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2570 emit_soft_tfmode_libcall (func, 3, operands);
2574 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2587 emit_soft_tfmode_libcall (func, 2, operands);
2591 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2598 switch (GET_MODE (operands[1]))
2611 case FLOAT_TRUNCATE:
2612 switch (GET_MODE (operands[0]))
2626 switch (GET_MODE (operands[1]))
2639 case UNSIGNED_FLOAT:
2640 switch (GET_MODE (operands[1]))
2654 switch (GET_MODE (operands[0]))
2668 switch (GET_MODE (operands[0]))
2685 emit_soft_tfmode_libcall (func, 2, operands);
2688 /* Expand a hard-float tfmode operation. All arguments must be in
2692 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2696 if (GET_RTX_CLASS (code) == '1')
2698 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2699 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2703 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2704 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2705 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2706 operands[1], operands[2]);
2709 if (register_operand (operands[0], VOIDmode))
2712 dest = gen_reg_rtx (GET_MODE (operands[0]));
2714 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2716 if (dest != operands[0])
2717 emit_move_insn (operands[0], dest);
2721 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2723 if (TARGET_HARD_QUAD)
2724 emit_hard_tfmode_operation (code, operands);
2726 emit_soft_tfmode_binop (code, operands);
2730 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2732 if (TARGET_HARD_QUAD)
2733 emit_hard_tfmode_operation (code, operands);
2735 emit_soft_tfmode_unop (code, operands);
2739 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2741 if (TARGET_HARD_QUAD)
2742 emit_hard_tfmode_operation (code, operands);
2744 emit_soft_tfmode_cvt (code, operands);
2747 /* Return nonzero if a return peephole merging return with
2748 setting of output register is ok. */
2750 leaf_return_peephole_ok (void)
2752 return (actual_fsize == 0);
2755 /* Return nonzero if a branch/jump/call instruction will be emitting
2756 nop into its delay slot. */
2759 empty_delay_slot (rtx insn)
2763 /* If no previous instruction (should not happen), return true. */
2764 if (PREV_INSN (insn) == NULL)
2767 seq = NEXT_INSN (PREV_INSN (insn));
2768 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2774 /* Return nonzero if TRIAL can go into the function epilogue's
2775 delay slot. SLOT is the slot we are trying to fill. */
2778 eligible_for_epilogue_delay (rtx trial, int slot)
2785 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2788 if (get_attr_length (trial) != 1)
2791 /* If there are any call-saved registers, we should scan TRIAL if it
2792 does not reference them. For now just make it easy. */
2796 /* If the function uses __builtin_eh_return, the eh_return machinery
2797 occupies the delay slot. */
2798 if (current_function_calls_eh_return)
2801 /* In the case of a true leaf function, anything can go into the delay slot.
2802 A delay slot only exists however if the frame size is zero, otherwise
2803 we will put an insn to adjust the stack after the return. */
2804 if (current_function_uses_only_leaf_regs)
2806 if (leaf_return_peephole_ok ())
2807 return ((get_attr_in_uncond_branch_delay (trial)
2808 == IN_BRANCH_DELAY_TRUE));
2812 pat = PATTERN (trial);
2814 /* Otherwise, only operations which can be done in tandem with
2815 a `restore' or `return' insn can go into the delay slot. */
2816 if (GET_CODE (SET_DEST (pat)) != REG
2817 || REGNO (SET_DEST (pat)) < 24)
2820 /* If this instruction sets up floating point register and we have a return
2821 instruction, it can probably go in. But restore will not work
2823 if (REGNO (SET_DEST (pat)) >= 32)
2825 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2826 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2831 /* The set of insns matched here must agree precisely with the set of
2832 patterns paired with a RETURN in sparc.md. */
2834 src = SET_SRC (pat);
2836 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2837 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2838 && arith_operand (src, GET_MODE (src)))
2841 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2843 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2846 /* This matches "*return_di". */
2847 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2848 && arith_double_operand (src, GET_MODE (src)))
2849 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2851 /* This matches "*return_sf_no_fpu". */
2852 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2853 && register_operand (src, SFmode))
2856 /* If we have return instruction, anything that does not use
2857 local or output registers and can go into a delay slot wins. */
2858 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2859 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2862 /* This matches "*return_addsi". */
2863 else if (GET_CODE (src) == PLUS
2864 && arith_operand (XEXP (src, 0), SImode)
2865 && arith_operand (XEXP (src, 1), SImode)
2866 && (register_operand (XEXP (src, 0), SImode)
2867 || register_operand (XEXP (src, 1), SImode)))
2870 /* This matches "*return_adddi". */
2871 else if (GET_CODE (src) == PLUS
2872 && arith_double_operand (XEXP (src, 0), DImode)
2873 && arith_double_operand (XEXP (src, 1), DImode)
2874 && (register_operand (XEXP (src, 0), DImode)
2875 || register_operand (XEXP (src, 1), DImode)))
2878 /* This can match "*return_losum_[sd]i".
2879 Catch only some cases, so that return_losum* don't have
2881 else if (GET_CODE (src) == LO_SUM
2882 && ! TARGET_CM_MEDMID
2883 && ((register_operand (XEXP (src, 0), SImode)
2884 && immediate_operand (XEXP (src, 1), SImode))
2886 && register_operand (XEXP (src, 0), DImode)
2887 && immediate_operand (XEXP (src, 1), DImode))))
2890 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2891 else if (GET_CODE (src) == ASHIFT
2892 && (register_operand (XEXP (src, 0), SImode)
2893 || register_operand (XEXP (src, 0), DImode))
2894 && XEXP (src, 1) == const1_rtx)
2900 /* Return nonzero if TRIAL can go into the call delay slot. */
2902 tls_call_delay (rtx trial)
2907 call __tls_get_addr, %tgd_call (foo)
2908 add %l7, %o0, %o0, %tgd_add (foo)
2909 while Sun as/ld does not. */
2910 if (TARGET_GNU_TLS || !TARGET_TLS)
2913 pat = PATTERN (trial);
2914 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
2917 unspec = XEXP (SET_DEST (pat), 1);
2918 if (GET_CODE (unspec) != UNSPEC
2919 || (XINT (unspec, 1) != UNSPEC_TLSGD
2920 && XINT (unspec, 1) != UNSPEC_TLSLDM))
2926 /* Return nonzero if TRIAL can go into the sibling call
2930 eligible_for_sibcall_delay (rtx trial)
2934 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2937 if (get_attr_length (trial) != 1)
2940 pat = PATTERN (trial);
2942 if (current_function_uses_only_leaf_regs)
2944 /* If the tail call is done using the call instruction,
2945 we have to restore %o7 in the delay slot. */
2946 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2949 /* %g1 is used to build the function address */
2950 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2956 /* Otherwise, only operations which can be done in tandem with
2957 a `restore' insn can go into the delay slot. */
2958 if (GET_CODE (SET_DEST (pat)) != REG
2959 || REGNO (SET_DEST (pat)) < 24
2960 || REGNO (SET_DEST (pat)) >= 32)
2963 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2965 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2968 src = SET_SRC (pat);
2970 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2971 && arith_operand (src, GET_MODE (src)))
2974 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2976 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2979 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2980 && arith_double_operand (src, GET_MODE (src)))
2981 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2983 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2984 && register_operand (src, SFmode))
2987 else if (GET_CODE (src) == PLUS
2988 && arith_operand (XEXP (src, 0), SImode)
2989 && arith_operand (XEXP (src, 1), SImode)
2990 && (register_operand (XEXP (src, 0), SImode)
2991 || register_operand (XEXP (src, 1), SImode)))
2994 else if (GET_CODE (src) == PLUS
2995 && arith_double_operand (XEXP (src, 0), DImode)
2996 && arith_double_operand (XEXP (src, 1), DImode)
2997 && (register_operand (XEXP (src, 0), DImode)
2998 || register_operand (XEXP (src, 1), DImode)))
3001 else if (GET_CODE (src) == LO_SUM
3002 && ! TARGET_CM_MEDMID
3003 && ((register_operand (XEXP (src, 0), SImode)
3004 && immediate_operand (XEXP (src, 1), SImode))
3006 && register_operand (XEXP (src, 0), DImode)
3007 && immediate_operand (XEXP (src, 1), DImode))))
3010 else if (GET_CODE (src) == ASHIFT
3011 && (register_operand (XEXP (src, 0), SImode)
3012 || register_operand (XEXP (src, 0), DImode))
3013 && XEXP (src, 1) == const1_rtx)
3020 check_return_regs (rtx x)
3022 switch (GET_CODE (x))
3025 return IN_OR_GLOBAL_P (x);
3040 if (check_return_regs (XEXP (x, 1)) == 0)
3045 return check_return_regs (XEXP (x, 0));
3054 short_branch (int uid1, int uid2)
3056 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3058 /* Leave a few words of "slop". */
3059 if (delta >= -1023 && delta <= 1022)
3065 /* Return nonzero if REG is not used after INSN.
3066 We assume REG is a reload reg, and therefore does
3067 not live past labels or calls or jumps. */
3069 reg_unused_after (rtx reg, rtx insn)
3071 enum rtx_code code, prev_code = UNKNOWN;
3073 while ((insn = NEXT_INSN (insn)))
3075 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3078 code = GET_CODE (insn);
3079 if (GET_CODE (insn) == CODE_LABEL)
3082 if (GET_RTX_CLASS (code) == 'i')
3084 rtx set = single_set (insn);
3085 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3088 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3090 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3098 /* Determine if it's legal to put X into the constant pool. This
3099 is not possible if X contains the address of a symbol that is
3100 not constant (TLS) or not known at final link time (PIC). */
3103 sparc_cannot_force_const_mem (rtx x)
3105 switch (GET_CODE (x))
3109 /* Accept all non-symbolic constants. */
3113 /* Labels are OK iff we are non-PIC. */
3114 return flag_pic != 0;
3117 /* 'Naked' TLS symbol references are never OK,
3118 non-TLS symbols are OK iff we are non-PIC. */
3119 if (SYMBOL_REF_TLS_MODEL (x))
3122 return flag_pic != 0;
3125 return sparc_cannot_force_const_mem (XEXP (x, 0));
3128 return sparc_cannot_force_const_mem (XEXP (x, 0))
3129 || sparc_cannot_force_const_mem (XEXP (x, 1));
3137 /* The table we use to reference PIC data. */
3138 static GTY(()) rtx global_offset_table;
3140 /* The function we use to get at it. */
3141 static GTY(()) rtx get_pc_symbol;
3142 static char get_pc_symbol_name[256];
3144 /* Ensure that we are not using patterns that are not OK with PIC. */
3152 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3153 || (GET_CODE (recog_data.operand[i]) == CONST
3154 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3155 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3156 == global_offset_table)
3157 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3166 /* Return true if X is an address which needs a temporary register when
3167 reloaded while generating PIC code. */
3170 pic_address_needs_scratch (rtx x)
3172 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3173 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3174 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3175 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3176 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3182 /* Determine if a given RTX is a valid constant. We already know this
3183 satisfies CONSTANT_P. */
3186 legitimate_constant_p (rtx x)
3190 switch (GET_CODE (x))
3193 /* TLS symbols are not constant. */
3194 if (SYMBOL_REF_TLS_MODEL (x))
3199 inner = XEXP (x, 0);
3201 /* Offsets of TLS symbols are never valid.
3202 Discourage CSE from creating them. */
3203 if (GET_CODE (inner) == PLUS
3204 && tls_symbolic_operand (XEXP (inner, 0)))
3209 if (GET_MODE (x) == VOIDmode)
3212 /* Floating point constants are generally not ok.
3213 The only exception is 0.0 in VIS. */
3215 && (GET_MODE (x) == SFmode
3216 || GET_MODE (x) == DFmode
3217 || GET_MODE (x) == TFmode)
3218 && fp_zero_operand (x, GET_MODE (x)))
3230 /* Determine if a given RTX is a valid constant address. */
3233 constant_address_p (rtx x)
3235 switch (GET_CODE (x))
3243 if (flag_pic && pic_address_needs_scratch (x))
3245 return legitimate_constant_p (x);
3248 return !flag_pic && legitimate_constant_p (x);
3255 /* Nonzero if the constant value X is a legitimate general operand
3256 when generating PIC code. It is given that flag_pic is on and
3257 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3260 legitimate_pic_operand_p (rtx x)
3262 if (pic_address_needs_scratch (x))
3264 if (tls_symbolic_operand (x)
3265 || (GET_CODE (x) == CONST
3266 && GET_CODE (XEXP (x, 0)) == PLUS
3267 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3272 /* Return nonzero if ADDR is a valid memory address.
3273 STRICT specifies whether strict register checking applies. */
3276 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3278 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3280 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3282 else if (GET_CODE (addr) == PLUS)
3284 rs1 = XEXP (addr, 0);
3285 rs2 = XEXP (addr, 1);
3287 /* Canonicalize. REG comes first, if there are no regs,
3288 LO_SUM comes first. */
3290 && GET_CODE (rs1) != SUBREG
3292 || GET_CODE (rs2) == SUBREG
3293 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3295 rs1 = XEXP (addr, 1);
3296 rs2 = XEXP (addr, 0);
3300 && rs1 == pic_offset_table_rtx
3302 && GET_CODE (rs2) != SUBREG
3303 && GET_CODE (rs2) != LO_SUM
3304 && GET_CODE (rs2) != MEM
3305 && !tls_symbolic_operand (rs2)
3306 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3307 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3309 || GET_CODE (rs1) == SUBREG)
3310 && RTX_OK_FOR_OFFSET_P (rs2)))
3315 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3316 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3318 /* We prohibit REG + REG for TFmode when there are no instructions
3319 which accept REG+REG instructions. We do this because REG+REG
3320 is not an offsetable address. If we get the situation in reload
3321 where source and destination of a movtf pattern are both MEMs with
3322 REG+REG address, then only one of them gets converted to an
3323 offsetable address. */
3325 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3326 && TARGET_HARD_QUAD))
3329 /* We prohibit REG + REG on ARCH32 if not optimizing for
3330 DFmode/DImode because then mem_min_alignment is likely to be zero
3331 after reload and the forced split would lack a matching splitter
3333 if (TARGET_ARCH32 && !optimize
3334 && (mode == DFmode || mode == DImode))
3337 else if (USE_AS_OFFSETABLE_LO10
3338 && GET_CODE (rs1) == LO_SUM
3340 && ! TARGET_CM_MEDMID
3341 && RTX_OK_FOR_OLO10_P (rs2))
3345 imm1 = XEXP (rs1, 1);
3346 rs1 = XEXP (rs1, 0);
3347 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3351 else if (GET_CODE (addr) == LO_SUM)
3353 rs1 = XEXP (addr, 0);
3354 imm1 = XEXP (addr, 1);
3356 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3359 /* We can't allow TFmode, because an offset greater than or equal to the
3360 alignment (8) may cause the LO_SUM to overflow if !v9. */
3361 if (mode == TFmode && !TARGET_V9)
3364 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3369 if (GET_CODE (rs1) == SUBREG)
3370 rs1 = SUBREG_REG (rs1);
3376 if (GET_CODE (rs2) == SUBREG)
3377 rs2 = SUBREG_REG (rs2);
3384 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3385 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3390 if ((REGNO (rs1) >= 32
3391 && REGNO (rs1) != FRAME_POINTER_REGNUM
3392 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3394 && (REGNO (rs2) >= 32
3395 && REGNO (rs2) != FRAME_POINTER_REGNUM
3396 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3402 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3404 static GTY(()) rtx sparc_tls_symbol;
3406 sparc_tls_get_addr (void)
3408 if (!sparc_tls_symbol)
3409 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3411 return sparc_tls_symbol;
3415 sparc_tls_got (void)
3420 current_function_uses_pic_offset_table = 1;
3421 return pic_offset_table_rtx;
3424 if (!global_offset_table)
3425 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3426 temp = gen_reg_rtx (Pmode);
3427 emit_move_insn (temp, global_offset_table);
3432 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3433 this (thread-local) address. */
3436 legitimize_tls_address (rtx addr)
3438 rtx temp1, temp2, temp3, ret, o0, got, insn;
3443 if (GET_CODE (addr) == SYMBOL_REF)
3444 switch (SYMBOL_REF_TLS_MODEL (addr))
3446 case TLS_MODEL_GLOBAL_DYNAMIC:
3448 temp1 = gen_reg_rtx (SImode);
3449 temp2 = gen_reg_rtx (SImode);
3450 ret = gen_reg_rtx (Pmode);
3451 o0 = gen_rtx_REG (Pmode, 8);
3452 got = sparc_tls_got ();
3453 emit_insn (gen_tgd_hi22 (temp1, addr));
3454 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3457 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3458 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3463 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3464 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3467 CALL_INSN_FUNCTION_USAGE (insn)
3468 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3469 CALL_INSN_FUNCTION_USAGE (insn));
3470 insn = get_insns ();
3472 emit_libcall_block (insn, ret, o0, addr);
3475 case TLS_MODEL_LOCAL_DYNAMIC:
3477 temp1 = gen_reg_rtx (SImode);
3478 temp2 = gen_reg_rtx (SImode);
3479 temp3 = gen_reg_rtx (Pmode);
3480 ret = gen_reg_rtx (Pmode);
3481 o0 = gen_rtx_REG (Pmode, 8);
3482 got = sparc_tls_got ();
3483 emit_insn (gen_tldm_hi22 (temp1));
3484 emit_insn (gen_tldm_lo10 (temp2, temp1));
3487 emit_insn (gen_tldm_add32 (o0, got, temp2));
3488 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3493 emit_insn (gen_tldm_add64 (o0, got, temp2));
3494 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3497 CALL_INSN_FUNCTION_USAGE (insn)
3498 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3499 CALL_INSN_FUNCTION_USAGE (insn));
3500 insn = get_insns ();
3502 emit_libcall_block (insn, temp3, o0,
3503 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3504 UNSPEC_TLSLD_BASE));
3505 temp1 = gen_reg_rtx (SImode);
3506 temp2 = gen_reg_rtx (SImode);
3507 emit_insn (gen_tldo_hix22 (temp1, addr));
3508 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3510 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3512 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3515 case TLS_MODEL_INITIAL_EXEC:
3516 temp1 = gen_reg_rtx (SImode);
3517 temp2 = gen_reg_rtx (SImode);
3518 temp3 = gen_reg_rtx (Pmode);
3519 got = sparc_tls_got ();
3520 emit_insn (gen_tie_hi22 (temp1, addr));
3521 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3523 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3525 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3528 ret = gen_reg_rtx (Pmode);
3530 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3533 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3537 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3540 case TLS_MODEL_LOCAL_EXEC:
3541 temp1 = gen_reg_rtx (Pmode);
3542 temp2 = gen_reg_rtx (Pmode);
3545 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3546 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3550 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3551 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3553 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3561 abort (); /* for now ... */
3567 /* Legitimize PIC addresses. If the address is already position-independent,
3568 we return ORIG. Newly generated position-independent addresses go into a
3569 reg. This is REG if nonzero, otherwise we allocate register(s) as
3573 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3576 if (GET_CODE (orig) == SYMBOL_REF)
3578 rtx pic_ref, address;
3583 if (reload_in_progress || reload_completed)
3586 reg = gen_reg_rtx (Pmode);
3591 /* If not during reload, allocate another temp reg here for loading
3592 in the address, so that these instructions can be optimized
3594 rtx temp_reg = ((reload_in_progress || reload_completed)
3595 ? reg : gen_reg_rtx (Pmode));
3597 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3598 won't get confused into thinking that these two instructions
3599 are loading in the true address of the symbol. If in the
3600 future a PIC rtx exists, that should be used instead. */
3601 if (Pmode == SImode)
3603 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3604 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3608 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3609 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3616 pic_ref = gen_rtx_MEM (Pmode,
3617 gen_rtx_PLUS (Pmode,
3618 pic_offset_table_rtx, address));
3619 current_function_uses_pic_offset_table = 1;
3620 RTX_UNCHANGING_P (pic_ref) = 1;
3621 insn = emit_move_insn (reg, pic_ref);
3622 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3624 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3628 else if (GET_CODE (orig) == CONST)
3632 if (GET_CODE (XEXP (orig, 0)) == PLUS
3633 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3638 if (reload_in_progress || reload_completed)
3641 reg = gen_reg_rtx (Pmode);
3644 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3646 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3647 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3648 base == reg ? 0 : reg);
3653 if (GET_CODE (offset) == CONST_INT)
3655 if (SMALL_INT (offset))
3656 return plus_constant (base, INTVAL (offset));
3657 else if (! reload_in_progress && ! reload_completed)
3658 offset = force_reg (Pmode, offset);
3660 /* If we reach here, then something is seriously wrong. */
3663 return gen_rtx_PLUS (Pmode, base, offset);
3665 else if (GET_CODE (orig) == LABEL_REF)
3666 /* ??? Why do we do this? */
3667 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3668 the register is live instead, in case it is eliminated. */
3669 current_function_uses_pic_offset_table = 1;
3674 /* Try machine-dependent ways of modifying an illegitimate address X
3675 to be legitimate. If we find one, return the new, valid address.
3677 OLDX is the address as it was before break_out_memory_refs was called.
3678 In some cases it is useful to look at this to decide what needs to be done.
3680 MODE is the mode of the operand pointed to by X. */
3683 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3687 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3688 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3689 force_operand (XEXP (x, 0), NULL_RTX));
3690 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3691 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3692 force_operand (XEXP (x, 1), NULL_RTX));
3693 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3694 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3696 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3697 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3698 force_operand (XEXP (x, 1), NULL_RTX));
3700 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3703 if (tls_symbolic_operand (x))
3704 x = legitimize_tls_address (x);
3706 x = legitimize_pic_address (x, mode, 0);
3707 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3708 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3709 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3710 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3711 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3712 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3713 else if (GET_CODE (x) == SYMBOL_REF
3714 || GET_CODE (x) == CONST
3715 || GET_CODE (x) == LABEL_REF)
3716 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3720 /* Emit special PIC prologues. */
3723 load_pic_register (void)
3725 /* Labels to get the PC in the prologue of this function. */
3726 int orig_flag_pic = flag_pic;
3731 /* If we haven't emitted the special get_pc helper function, do so now. */
3732 if (get_pc_symbol_name[0] == 0)
3736 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3739 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3741 ASM_OUTPUT_ALIGN (asm_out_file, align);
3742 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
3743 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3746 /* Initialize every time through, since we can't easily
3747 know this to be permanent. */
3748 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3749 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3752 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3755 flag_pic = orig_flag_pic;
3757 /* Need to emit this whether or not we obey regdecls,
3758 since setjmp/longjmp can cause life info to screw up.
3759 ??? In the case where we don't obey regdecls, this is not sufficient
3760 since we may not fall out the bottom. */
3761 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3764 /* Return 1 if RTX is a MEM which is known to be aligned to at
3765 least a DESIRED byte boundary. */
3768 mem_min_alignment (rtx mem, int desired)
3770 rtx addr, base, offset;
3772 /* If it's not a MEM we can't accept it. */
3773 if (GET_CODE (mem) != MEM)
3776 addr = XEXP (mem, 0);
3777 base = offset = NULL_RTX;
3778 if (GET_CODE (addr) == PLUS)
3780 if (GET_CODE (XEXP (addr, 0)) == REG)
3782 base = XEXP (addr, 0);
3784 /* What we are saying here is that if the base
3785 REG is aligned properly, the compiler will make
3786 sure any REG based index upon it will be so
3788 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3789 offset = XEXP (addr, 1);
3791 offset = const0_rtx;
3794 else if (GET_CODE (addr) == REG)
3797 offset = const0_rtx;
3800 if (base != NULL_RTX)
3802 int regno = REGNO (base);
3804 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3806 /* Check if the compiler has recorded some information
3807 about the alignment of the base REG. If reload has
3808 completed, we already matched with proper alignments.
3809 If not running global_alloc, reload might give us
3810 unaligned pointer to local stack though. */
3812 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3813 || (optimize && reload_completed))
3814 && (INTVAL (offset) & (desired - 1)) == 0)
3819 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3823 else if (! TARGET_UNALIGNED_DOUBLES
3824 || CONSTANT_P (addr)
3825 || GET_CODE (addr) == LO_SUM)
3827 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3828 is true, in which case we can only assume that an access is aligned if
3829 it is to a constant address, or the address involves a LO_SUM. */
3833 /* An obviously unaligned address. */
3838 /* Vectors to keep interesting information about registers where it can easily
3839 be got. We used to use the actual mode value as the bit number, but there
3840 are more than 32 modes now. Instead we use two tables: one indexed by
3841 hard register number, and one indexed by mode. */
3843 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3844 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3845 mapped into one sparc_mode_class mode. */
3847 enum sparc_mode_class {
3848 S_MODE, D_MODE, T_MODE, O_MODE,
3849 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3853 /* Modes for single-word and smaller quantities. */
3854 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3856 /* Modes for double-word and smaller quantities. */
3857 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3859 /* Modes for quad-word and smaller quantities. */
3860 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3862 /* Modes for 8-word and smaller quantities. */
3863 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3865 /* Modes for single-float quantities. We must allow any single word or
3866 smaller quantity. This is because the fix/float conversion instructions
3867 take integer inputs/outputs from the float registers. */
3868 #define SF_MODES (S_MODES)
3870 /* Modes for double-float and smaller quantities. */
3871 #define DF_MODES (S_MODES | D_MODES)
3873 /* Modes for double-float only quantities. */
3874 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3876 /* Modes for quad-float only quantities. */
3877 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3879 /* Modes for quad-float and smaller quantities. */
3880 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3882 /* Modes for quad-float and double-float quantities. */
3883 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3885 /* Modes for quad-float pair only quantities. */
3886 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3888 /* Modes for quad-float pairs and smaller quantities. */
3889 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3891 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3893 /* Modes for condition codes. */
3894 #define CC_MODES (1 << (int) CC_MODE)
3895 #define CCFP_MODES (1 << (int) CCFP_MODE)
3897 /* Value is 1 if register/mode pair is acceptable on sparc.
3898 The funny mixture of D and T modes is because integer operations
3899 do not specially operate on tetra quantities, so non-quad-aligned
3900 registers can hold quadword quantities (except %o4 and %i4 because
3901 they cross fixed registers). */
3903 /* This points to either the 32 bit or the 64 bit version. */
3904 const int *hard_regno_mode_classes;
3906 static const int hard_32bit_mode_classes[] = {
3907 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3908 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3909 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3910 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3912 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3913 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3914 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3915 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3917 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3918 and none can hold SFmode/SImode values. */
3919 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3920 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3921 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3922 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3925 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3931 static const int hard_64bit_mode_classes[] = {
3932 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3933 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3934 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3935 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3937 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3938 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3939 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3940 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3942 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3943 and none can hold SFmode/SImode values. */
3944 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3945 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3946 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3947 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3950 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3956 int sparc_mode_class [NUM_MACHINE_MODES];
3958 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3961 sparc_init_modes (void)
3965 for (i = 0; i < NUM_MACHINE_MODES; i++)
3967 switch (GET_MODE_CLASS (i))
3970 case MODE_PARTIAL_INT:
3971 case MODE_COMPLEX_INT:
3972 if (GET_MODE_SIZE (i) <= 4)
3973 sparc_mode_class[i] = 1 << (int) S_MODE;
3974 else if (GET_MODE_SIZE (i) == 8)
3975 sparc_mode_class[i] = 1 << (int) D_MODE;
3976 else if (GET_MODE_SIZE (i) == 16)
3977 sparc_mode_class[i] = 1 << (int) T_MODE;
3978 else if (GET_MODE_SIZE (i) == 32)
3979 sparc_mode_class[i] = 1 << (int) O_MODE;
3981 sparc_mode_class[i] = 0;
3984 case MODE_COMPLEX_FLOAT:
3985 if (GET_MODE_SIZE (i) <= 4)
3986 sparc_mode_class[i] = 1 << (int) SF_MODE;
3987 else if (GET_MODE_SIZE (i) == 8)
3988 sparc_mode_class[i] = 1 << (int) DF_MODE;
3989 else if (GET_MODE_SIZE (i) == 16)
3990 sparc_mode_class[i] = 1 << (int) TF_MODE;
3991 else if (GET_MODE_SIZE (i) == 32)
3992 sparc_mode_class[i] = 1 << (int) OF_MODE;
3994 sparc_mode_class[i] = 0;
3997 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3998 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4000 sparc_mode_class[i] = 1 << (int) CC_MODE;
4003 sparc_mode_class[i] = 0;
4009 hard_regno_mode_classes = hard_64bit_mode_classes;
4011 hard_regno_mode_classes = hard_32bit_mode_classes;
4013 /* Initialize the array used by REGNO_REG_CLASS. */
4014 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4016 if (i < 16 && TARGET_V8PLUS)
4017 sparc_regno_reg_class[i] = I64_REGS;
4018 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4019 sparc_regno_reg_class[i] = GENERAL_REGS;
4021 sparc_regno_reg_class[i] = FP_REGS;
4023 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4025 sparc_regno_reg_class[i] = FPCC_REGS;
4027 sparc_regno_reg_class[i] = NO_REGS;
4031 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
4032 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4033 v9 int regs as it simplifies the code. */
4036 save_regs (FILE *file, int low, int high, const char *base,
4037 int offset, int n_regs, HOST_WIDE_INT real_offset)
4041 if (TARGET_ARCH64 && high <= 32)
4043 for (i = low; i < high; i++)
4045 if (regs_ever_live[i] && ! call_used_regs[i])
4047 fprintf (file, "\tstx\t%s, [%s+%d]\n",
4048 reg_names[i], base, offset + 4 * n_regs);
4049 if (dwarf2out_do_frame ())
4050 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4057 for (i = low; i < high; i += 2)
4059 if (regs_ever_live[i] && ! call_used_regs[i])
4061 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4063 fprintf (file, "\tstd\t%s, [%s+%d]\n",
4064 reg_names[i], base, offset + 4 * n_regs);
4065 if (dwarf2out_do_frame ())
4067 char *l = dwarf2out_cfi_label ();
4068 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
4069 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
4075 fprintf (file, "\tst\t%s, [%s+%d]\n",
4076 reg_names[i], base, offset + 4 * n_regs);
4077 if (dwarf2out_do_frame ())
4078 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4084 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4086 fprintf (file, "\tst\t%s, [%s+%d]\n",
4087 reg_names[i+1], base, offset + 4 * n_regs + 4);
4088 if (dwarf2out_do_frame ())
4089 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
4098 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
4100 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4101 v9 int regs as it simplifies the code. */
4104 restore_regs (FILE *file, int low, int high, const char *base,
4105 int offset, int n_regs)
4109 if (TARGET_ARCH64 && high <= 32)
4111 for (i = low; i < high; i++)
4113 if (regs_ever_live[i] && ! call_used_regs[i])
4114 fprintf (file, "\tldx\t[%s+%d], %s\n",
4115 base, offset + 4 * n_regs, reg_names[i]),
4121 for (i = low; i < high; i += 2)
4123 if (regs_ever_live[i] && ! call_used_regs[i])
4124 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4125 fprintf (file, "\tldd\t[%s+%d], %s\n",
4126 base, offset + 4 * n_regs, reg_names[i]),
4129 fprintf (file, "\tld\t[%s+%d], %s\n",
4130 base, offset + 4 * n_regs, reg_names[i]),
4132 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4133 fprintf (file, "\tld\t[%s+%d], %s\n",
4134 base, offset + 4 * n_regs + 4, reg_names[i+1]),
4141 /* Compute the frame size required by the function. This function is called
4142 during the reload pass and also by output_function_prologue(). */
4145 compute_frame_size (HOST_WIDE_INT size, int leaf_function)
4148 int outgoing_args_size = (current_function_outgoing_args_size
4149 + REG_PARM_STACK_SPACE (current_function_decl));
4151 /* N_REGS is the number of 4-byte regs saved thus far. This applies
4152 even to v9 int regs to be consistent with save_regs/restore_regs. */
4156 for (i = 0; i < 8; i++)
4157 if (regs_ever_live[i] && ! call_used_regs[i])
4162 for (i = 0; i < 8; i += 2)
4163 if ((regs_ever_live[i] && ! call_used_regs[i])
4164 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4168 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4169 if ((regs_ever_live[i] && ! call_used_regs[i])
4170 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4173 /* Set up values for use in `function_epilogue'. */
4174 num_gfregs = n_regs;
4176 if (leaf_function && n_regs == 0
4177 && size == 0 && current_function_outgoing_args_size == 0)
4179 actual_fsize = apparent_fsize = 0;
4183 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4184 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4185 apparent_fsize += n_regs * 4;
4186 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4189 /* Make sure nothing can clobber our register windows.
4190 If a SAVE must be done, or there is a stack-local variable,
4191 the register window area must be allocated.
4192 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4193 if (leaf_function == 0 || size > 0)
4194 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4196 return SPARC_STACK_ALIGN (actual_fsize);
4199 /* Build big number NUM in register REG and output the result to FILE.
4200 REG is guaranteed to be the only clobbered register. The function
4201 will very likely emit several instructions, so it must not be called
4202 from within a delay slot. */
4205 build_big_number (FILE *file, HOST_WIDE_INT num, const char *reg)
4207 #if HOST_BITS_PER_WIDE_INT == 64
4208 HOST_WIDE_INT high_bits = (num >> 32) & 0xffffffff;
4216 /* We don't use the 'set' macro because it appears to be broken
4217 in the Solaris 7 assembler. */
4218 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4220 if ((num & 0x3ff) != 0)
4221 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4224 #if HOST_BITS_PER_WIDE_INT == 64
4225 else if (high_bits == 0xffffffff) /* && TARGET_ARCH64 */
4227 else /* num < 0 && TARGET_ARCH64 */
4230 /* Sethi does not sign extend, so we must use a little trickery
4231 to use it for negative numbers. Invert the constant before
4232 loading it in, then use xor immediate to invert the loaded bits
4233 (along with the upper 32 bits) to the desired constant. This
4234 works because the sethi and immediate fields overlap. */
4235 HOST_WIDE_INT inv = ~num;
4236 HOST_WIDE_INT low = -0x400 + (num & 0x3ff);
4238 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4240 fprintf (file, "\txor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4243 #if HOST_BITS_PER_WIDE_INT == 64
4244 else /* TARGET_ARCH64 */
4246 /* We don't use the 'setx' macro because if requires a scratch register.
4247 This is the translation of sparc_emit_set_const64_longway into asm.
4248 Hopefully we will soon have prologue/epilogue emitted as RTL. */
4249 HOST_WIDE_INT low1 = (num >> (32 - 12)) & 0xfff;
4250 HOST_WIDE_INT low2 = (num >> (32 - 12 - 12)) & 0xfff;
4251 HOST_WIDE_INT low3 = (num >> (32 - 12 - 12 - 8)) & 0x0ff;
4254 /* We don't use the 'set' macro because it appears to be broken
4255 in the Solaris 7 assembler. */
4256 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4258 if ((high_bits & 0x3ff) != 0)
4259 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4260 reg, high_bits, reg);
4264 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4265 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4275 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4276 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4284 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4286 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4292 /* Output any necessary .register pseudo-ops. */
4294 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4296 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4302 /* Check if %g[2367] were used without
4303 .register being printed for them already. */
4304 for (i = 2; i < 8; i++)
4306 if (regs_ever_live [i]
4307 && ! sparc_hard_reg_printed [i])
4309 sparc_hard_reg_printed [i] = 1;
4310 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4317 /* This function generates the assembly code for function entry.
4318 FILE is a stdio stream to output the code to.
4319 SIZE is an int: how many units of temporary storage to allocate.
4320 Refer to the array `regs_ever_live' to determine which registers
4321 to save; `regs_ever_live[I]' is nonzero if register number I
4322 is ever used in the function. This macro is responsible for
4323 knowing which registers should not be saved even if used. */
4325 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
4326 of memory. If any fpu reg is used in the function, we allocate
4327 such a block here, at the bottom of the frame, just in case it's needed.
4329 If this function is a leaf procedure, then we may choose not
4330 to do a "save" insn. The decision about whether or not
4331 to do this is made in regclass.c. */
4334 sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size)
4337 sparc_flat_function_prologue (file, size);
4339 sparc_nonflat_function_prologue (file, size,
4340 current_function_uses_only_leaf_regs);
4343 /* Output code for the function prologue. */
4346 sparc_nonflat_function_prologue (FILE *file, HOST_WIDE_INT size,
4349 sparc_output_scratch_registers (file);
4351 /* Need to use actual_fsize, since we are also allocating
4352 space for our callee (and our own register save area). */
4353 actual_fsize = compute_frame_size (size, leaf_function);
4357 frame_base_name = "%sp";
4358 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4362 frame_base_name = "%fp";
4363 frame_base_offset = SPARC_STACK_BIAS;
4366 /* This is only for the human reader. */
4367 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
4369 if (actual_fsize == 0)
4371 else if (! leaf_function)
4373 if (actual_fsize <= 4096)
4374 fprintf (file, "\tsave\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4376 else if (actual_fsize <= 8192)
4378 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
4379 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4380 actual_fsize - 4096);
4384 build_big_number (file, -actual_fsize, "%g1");
4385 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
4388 else /* leaf function */
4390 if (actual_fsize <= 4096)
4391 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4393 else if (actual_fsize <= 8192)
4395 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
4396 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4397 actual_fsize - 4096);
4401 build_big_number (file, -actual_fsize, "%g1");
4402 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
4406 if (dwarf2out_do_frame () && actual_fsize)
4408 char *label = dwarf2out_cfi_label ();
4410 /* The canonical frame address refers to the top of the frame. */
4411 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
4412 : HARD_FRAME_POINTER_REGNUM),
4415 if (! leaf_function)
4417 /* Note the register window save. This tells the unwinder that
4418 it needs to restore the window registers from the previous
4419 frame's window save area at 0(cfa). */
4420 dwarf2out_window_save (label);
4422 /* The return address (-8) is now in %i7. */
4423 dwarf2out_return_reg (label, 31);
4427 /* If doing anything with PIC, do it now. */
4429 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
4431 /* Call saved registers are saved just above the outgoing argument area. */
4434 HOST_WIDE_INT offset, real_offset;
4438 real_offset = -apparent_fsize;
4439 offset = -apparent_fsize + frame_base_offset;
4440 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4442 /* ??? This might be optimized a little as %g1 might already have a
4443 value close enough that a single add insn will do. */
4444 /* ??? Although, all of this is probably only a temporary fix
4445 because if %g1 can hold a function result, then
4446 output_function_epilogue will lose (the result will get
4448 build_big_number (file, offset, "%g1");
4449 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4455 base = frame_base_name;
4458 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
4459 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
4464 /* Output code to restore any call saved registers. */
4467 output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED)
4469 HOST_WIDE_INT offset;
4473 offset = -apparent_fsize + frame_base_offset;
4474 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4476 build_big_number (file, offset, "%g1");
4477 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4483 base = frame_base_name;
4486 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4487 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4490 /* This function generates the assembly code for function exit,
4491 on machines that need it.
4493 The function epilogue should not depend on the current stack pointer!
4494 It should use the frame pointer only. This is mandatory because
4495 of alloca; we also take advantage of it to omit stack adjustments
4496 before returning. */
4499 sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size)
4502 sparc_flat_function_epilogue (file, size);
4504 sparc_nonflat_function_epilogue (file, size,
4505 current_function_uses_only_leaf_regs);
4508 /* Output code for the function epilogue. */
4511 sparc_nonflat_function_epilogue (FILE *file,
4512 HOST_WIDE_INT size ATTRIBUTE_UNUSED,
4517 if (current_function_epilogue_delay_list == 0)
4519 /* If code does not drop into the epilogue, we need
4520 do nothing except output pending case vectors.
4522 We have to still output a dummy nop for the sake of
4523 sane backtraces. Otherwise, if the last two instructions
4524 of a function were call foo; dslot; this can make the return
4525 PC of foo (ie. address of call instruction plus 8) point to
4526 the first instruction in the next function. */
4527 rtx insn, last_real_insn;
4529 insn = get_last_insn ();
4531 last_real_insn = prev_real_insn (insn);
4533 && GET_CODE (last_real_insn) == INSN
4534 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4535 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4537 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4538 fputs("\tnop\n", file);
4540 if (GET_CODE (insn) == NOTE)
4541 insn = prev_nonnote_insn (insn);
4542 if (insn && GET_CODE (insn) == BARRIER)
4543 goto output_vectors;
4547 output_restore_regs (file, leaf_function);
4549 /* Work out how to skip the caller's unimp instruction if required. */
4551 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4553 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4555 if (! leaf_function)
4557 if (current_function_calls_eh_return)
4559 if (current_function_epilogue_delay_list)
4561 if (SKIP_CALLERS_UNIMP_P)
4564 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4566 /* If we wound up with things in our delay slot, flush them here. */
4567 else if (current_function_epilogue_delay_list)
4569 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4571 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4573 epilogue_renumber (&delay, 0);
4574 fputs (SKIP_CALLERS_UNIMP_P
4575 ? "\treturn\t%i7+12\n"
4576 : "\treturn\t%i7+8\n", file);
4577 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4578 file, 1, 0, 0, NULL);
4584 if (GET_CODE (delay) != SET)
4587 src = SET_SRC (delay);
4588 if (GET_CODE (src) == ASHIFT)
4590 if (XEXP (src, 1) != const1_rtx)
4593 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4597 insn = gen_rtx_PARALLEL (VOIDmode,
4598 gen_rtvec (2, delay,
4599 gen_rtx_RETURN (VOIDmode)));
4600 insn = emit_jump_insn (insn);
4602 sparc_emitting_epilogue = true;
4603 final_scan_insn (insn, file, 1, 0, 1, NULL);
4604 sparc_emitting_epilogue = false;
4607 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4608 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4610 fprintf (file, "\t%s\n\trestore\n", ret);
4612 /* All of the following cases are for leaf functions. */
4613 else if (current_function_calls_eh_return)
4615 else if (current_function_epilogue_delay_list)
4617 /* eligible_for_epilogue_delay_slot ensures that if this is a
4618 leaf function, then we will only have insn in the delay slot
4619 if the frame size is zero, thus no adjust for the stack is
4621 if (actual_fsize != 0)
4623 fprintf (file, "\t%s\n", ret);
4624 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4625 file, 1, 0, 1, NULL);
4627 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4628 avoid generating confusing assembly language output. */
4629 else if (actual_fsize == 0)
4630 fprintf (file, "\t%s\n\tnop\n", ret);
4631 else if (actual_fsize <= 4096)
4632 fprintf (file, "\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4634 else if (actual_fsize <= 8192)
4635 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4636 ret, actual_fsize - 4096);
4639 build_big_number (file, actual_fsize, "%g1");
4640 fprintf (file, "\t%s\n\tadd\t%%sp, %%g1, %%sp\n", ret);
4644 sparc_output_deferred_case_vectors ();
4647 /* Output a sibling call. */
4650 output_sibcall (rtx insn, rtx call_operand)
4652 int leaf_regs = current_function_uses_only_leaf_regs;
4654 int delay_slot = dbr_sequence_length () > 0;
4658 /* Call to restore global regs might clobber
4659 the delay slot. Instead of checking for this
4660 output the delay slot now. */
4663 rtx delay = NEXT_INSN (insn);
4668 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4669 PATTERN (delay) = gen_blockage ();
4670 INSN_CODE (delay) = -1;
4673 output_restore_regs (asm_out_file, leaf_regs);
4676 operands[0] = call_operand;
4680 #ifdef HAVE_AS_RELAX_OPTION
4681 /* If as and ld are relaxing tail call insns into branch always,
4682 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4683 be optimized. With sethi/jmpl as nor ld has no easy way how to
4684 find out if somebody does not branch between the sethi and jmpl. */
4687 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4689 HOST_WIDE_INT size = 0;
4691 if ((actual_fsize || ! spare_slot) && delay_slot)
4693 rtx delay = NEXT_INSN (insn);
4698 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4699 PATTERN (delay) = gen_blockage ();
4700 INSN_CODE (delay) = -1;
4705 if (actual_fsize <= 4096)
4706 size = actual_fsize;
4707 else if (actual_fsize <= 8192)
4709 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4710 size = actual_fsize - 4096;
4714 build_big_number (asm_out_file, actual_fsize, "%g1");
4715 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4720 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4721 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4723 fprintf (asm_out_file, "\t sub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size);
4724 else if (! delay_slot)
4725 fputs ("\t nop\n", asm_out_file);
4730 fprintf (asm_out_file, "\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size);
4731 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4732 it into branch if possible. */
4733 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4734 output_asm_insn ("call\t%a0, 0", operands);
4735 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4740 output_asm_insn ("call\t%a0, 0", operands);
4743 rtx delay = NEXT_INSN (insn), pat;
4748 pat = PATTERN (delay);
4749 if (GET_CODE (pat) != SET)
4752 operands[0] = SET_DEST (pat);
4753 pat = SET_SRC (pat);
4754 switch (GET_CODE (pat))
4757 operands[1] = XEXP (pat, 0);
4758 operands[2] = XEXP (pat, 1);
4759 output_asm_insn (" restore %r1, %2, %Y0", operands);
4762 operands[1] = XEXP (pat, 0);
4763 operands[2] = XEXP (pat, 1);
4764 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4767 operands[1] = XEXP (pat, 0);
4768 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4772 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4775 PATTERN (delay) = gen_blockage ();
4776 INSN_CODE (delay) = -1;
4779 fputs ("\t restore\n", asm_out_file);
4783 /* Functions for handling argument passing.
4785 For v8 the first six args are normally in registers and the rest are
4786 pushed. Any arg that starts within the first 6 words is at least
4787 partially passed in a register unless its data type forbids.
4789 For v9, the argument registers are laid out as an array of 16 elements
4790 and arguments are added sequentially. The first 6 int args and up to the
4791 first 16 fp args (depending on size) are passed in regs.
4793 Slot Stack Integral Float Float in structure Double Long Double
4794 ---- ----- -------- ----- ------------------ ------ -----------
4795 15 [SP+248] %f31 %f30,%f31 %d30
4796 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4797 13 [SP+232] %f27 %f26,%f27 %d26
4798 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4799 11 [SP+216] %f23 %f22,%f23 %d22
4800 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4801 9 [SP+200] %f19 %f18,%f19 %d18
4802 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4803 7 [SP+184] %f15 %f14,%f15 %d14
4804 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4805 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4806 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4807 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4808 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4809 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4810 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4812 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4814 Integral arguments are always passed as 64 bit quantities appropriately
4817 Passing of floating point values is handled as follows.
4818 If a prototype is in scope:
4819 If the value is in a named argument (i.e. not a stdarg function or a
4820 value not part of the `...') then the value is passed in the appropriate
4822 If the value is part of the `...' and is passed in one of the first 6
4823 slots then the value is passed in the appropriate int reg.
4824 If the value is part of the `...' and is not passed in one of the first 6
4825 slots then the value is passed in memory.
4826 If a prototype is not in scope:
4827 If the value is one of the first 6 arguments the value is passed in the
4828 appropriate integer reg and the appropriate fp reg.
4829 If the value is not one of the first 6 arguments the value is passed in
4830 the appropriate fp reg and in memory.
4833 /* Maximum number of int regs for args. */
4834 #define SPARC_INT_ARG_MAX 6
4835 /* Maximum number of fp regs for args. */
4836 #define SPARC_FP_ARG_MAX 16
4838 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4840 /* Handle the INIT_CUMULATIVE_ARGS macro.
4841 Initialize a variable CUM of type CUMULATIVE_ARGS
4842 for a call to a function whose data type is FNTYPE.
4843 For a library call, FNTYPE is 0. */
4846 init_cumulative_args (struct sparc_args *cum, tree fntype,
4847 rtx libname ATTRIBUTE_UNUSED,
4848 tree fndecl ATTRIBUTE_UNUSED)
4851 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4852 cum->libcall_p = fntype == 0;
4855 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
4856 When a prototype says `char' or `short', really pass an `int'. */
4859 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
4861 return TARGET_ARCH32 ? true : false;
4864 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
4867 sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4869 /* For the V9 we want NAMED to mean what it says it means. */
4870 return TARGET_V9 ? true : false;
4873 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
4874 Specify whether to return the return value in memory. */
4877 sparc_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4879 /* SPARC ABI says that quad-precision floats and all structures are
4881 For V9: unions <= 32 bytes in size are returned in int regs,
4882 structures up to 32 bytes are returned in int and fp regs. */
4883 return (TARGET_ARCH32
4884 ? (TYPE_MODE (type) == BLKmode
4885 || TYPE_MODE (type) == TFmode)
4886 : (TYPE_MODE (type) == BLKmode
4887 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32));
4890 /* Handle the TARGET_STRUCT_VALUE target hook.
4891 Return where to find the structure return value address. */
4894 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED, int incoming)
4901 return gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx,
4902 STRUCT_VALUE_OFFSET));
4904 return gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx,
4905 STRUCT_VALUE_OFFSET));
4909 /* Scan the record type TYPE and return the following predicates:
4910 - INTREGS_P: the record contains at least one field or sub-field
4911 that is eligible for promotion in integer registers.
4912 - FP_REGS_P: the record contains at least one field or sub-field
4913 that is eligible for promotion in floating-point registers.
4914 - PACKED_P: the record contains at least one field that is packed.
4916 Sub-fields are not taken into account for the PACKED_P predicate. */
4919 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
4923 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4925 if (TREE_CODE (field) == FIELD_DECL)
4927 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4928 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
4929 else if (FLOAT_TYPE_P (TREE_TYPE (field)) && TARGET_FPU)
4934 if (packed_p && DECL_PACKED (field))
4940 /* Compute the slot number to pass an argument in.
4941 Return the slot number or -1 if passing on the stack.
4943 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4944 the preceding args and about the function being called.
4945 MODE is the argument's machine mode.
4946 TYPE is the data type of the argument (as a tree).
4947 This is null for libcalls where that information may
4949 NAMED is nonzero if this argument is a named parameter
4950 (otherwise it is an extra parameter matching an ellipsis).
4951 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4952 *PREGNO records the register number to use if scalar type.
4953 *PPADDING records the amount of padding needed in words. */
4956 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
4957 tree type, int named, int incoming_p,
4958 int *pregno, int *ppadding)
4960 int regbase = (incoming_p
4961 ? SPARC_INCOMING_INT_ARG_FIRST
4962 : SPARC_OUTGOING_INT_ARG_FIRST);
4963 int slotno = cum->words;
4968 if (type != 0 && TREE_ADDRESSABLE (type))
4971 && type != 0 && mode == BLKmode
4972 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4978 /* MODE is VOIDmode when generating the actual call.
4982 case QImode : case CQImode :
4983 case HImode : case CHImode :
4984 case SImode : case CSImode :
4985 case DImode : case CDImode :
4986 case TImode : case CTImode :
4987 if (slotno >= SPARC_INT_ARG_MAX)
4989 regno = regbase + slotno;
4992 case SFmode : case SCmode :
4993 case DFmode : case DCmode :
4994 case TFmode : case TCmode :
4997 if (slotno >= SPARC_INT_ARG_MAX)
4999 regno = regbase + slotno;
5003 if ((mode == TFmode || mode == TCmode)
5004 && (slotno & 1) != 0)
5005 slotno++, *ppadding = 1;
5006 if (TARGET_FPU && named)
5008 if (slotno >= SPARC_FP_ARG_MAX)
5010 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5016 if (slotno >= SPARC_INT_ARG_MAX)
5018 regno = regbase + slotno;
5024 /* For sparc64, objects requiring 16 byte alignment get it. */
5027 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
5028 slotno++, *ppadding = 1;
5032 || (type && TREE_CODE (type) == UNION_TYPE))
5034 if (slotno >= SPARC_INT_ARG_MAX)
5036 regno = regbase + slotno;
5040 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5042 /* First see what kinds of registers we would need. */
5043 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5045 /* The ABI obviously doesn't specify how packed structures
5046 are passed. These are defined to be passed in int regs
5047 if possible, otherwise memory. */
5048 if (packed_p || !named)
5049 fpregs_p = 0, intregs_p = 1;
5051 /* If all arg slots are filled, then must pass on stack. */
5052 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5054 /* If there are only int args and all int arg slots are filled,
5055 then must pass on stack. */
5056 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5058 /* Note that even if all int arg slots are filled, fp members may
5059 still be passed in regs if such regs are available.
5060 *PREGNO isn't set because there may be more than one, it's up
5061 to the caller to compute them. */
5074 /* Handle recursive register counting for structure field layout. */
5076 struct function_arg_record_value_parms
5078 rtx ret; /* return expression being built. */
5079 int slotno; /* slot number of the argument. */
5080 int named; /* whether the argument is named. */
5081 int regbase; /* regno of the base register. */
5082 int stack; /* 1 if part of the argument is on the stack. */
5083 int intoffset; /* offset of the first pending integer field. */
5084 unsigned int nregs; /* number of words passed in registers. */
5087 static void function_arg_record_value_3
5088 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5089 static void function_arg_record_value_2
5090 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5091 static void function_arg_record_value_1
5092 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5093 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
5094 static rtx function_arg_union_value (int, int);
5096 /* A subroutine of function_arg_record_value. Traverse the structure
5097 recursively and determine how many registers will be required. */
5100 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
5101 struct function_arg_record_value_parms *parms,
5106 /* We need to compute how many registers are needed so we can
5107 allocate the PARALLEL but before we can do that we need to know
5108 whether there are any packed fields. The ABI obviously doesn't
5109 specify how structures are passed in this case, so they are
5110 defined to be passed in int regs if possible, otherwise memory,
5111 regardless of whether there are fp values present. */
5114 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5116 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5123 /* Compute how many registers we need. */
5124 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5126 if (TREE_CODE (field) == FIELD_DECL)
5128 HOST_WIDE_INT bitpos = startbitpos;
5130 if (DECL_SIZE (field) != 0
5131 && host_integerp (bit_position (field), 1))
5132 bitpos += int_bit_position (field);
5134 /* ??? FIXME: else assume zero offset. */
5136 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5137 function_arg_record_value_1 (TREE_TYPE (field),
5141 else if (FLOAT_TYPE_P (TREE_TYPE (field))
5146 if (parms->intoffset != -1)
5148 unsigned int startbit, endbit;
5149 int intslots, this_slotno;
5151 startbit = parms->intoffset & -BITS_PER_WORD;
5152 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5154 intslots = (endbit - startbit) / BITS_PER_WORD;
5155 this_slotno = parms->slotno + parms->intoffset
5158 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5160 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5161 /* We need to pass this field on the stack. */
5165 parms->nregs += intslots;
5166 parms->intoffset = -1;
5169 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5170 If it wasn't true we wouldn't be here. */
5172 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5177 if (parms->intoffset == -1)
5178 parms->intoffset = bitpos;
5184 /* A subroutine of function_arg_record_value. Assign the bits of the
5185 structure between parms->intoffset and bitpos to integer registers. */
5188 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5189 struct function_arg_record_value_parms *parms)
5191 enum machine_mode mode;
5193 unsigned int startbit, endbit;
5194 int this_slotno, intslots, intoffset;
5197 if (parms->intoffset == -1)
5200 intoffset = parms->intoffset;
5201 parms->intoffset = -1;
5203 startbit = intoffset & -BITS_PER_WORD;
5204 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5205 intslots = (endbit - startbit) / BITS_PER_WORD;
5206 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5208 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5212 /* If this is the trailing part of a word, only load that much into
5213 the register. Otherwise load the whole register. Note that in
5214 the latter case we may pick up unwanted bits. It's not a problem
5215 at the moment but may wish to revisit. */
5217 if (intoffset % BITS_PER_WORD != 0)
5218 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5223 intoffset /= BITS_PER_UNIT;
5226 regno = parms->regbase + this_slotno;
5227 reg = gen_rtx_REG (mode, regno);
5228 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5229 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5232 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5237 while (intslots > 0);
5240 /* A subroutine of function_arg_record_value. Traverse the structure
5241 recursively and assign bits to floating point registers. Track which
5242 bits in between need integer registers; invoke function_arg_record_value_3
5243 to make that happen. */
5246 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5247 struct function_arg_record_value_parms *parms,
5253 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5255 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5262 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5264 if (TREE_CODE (field) == FIELD_DECL)
5266 HOST_WIDE_INT bitpos = startbitpos;
5268 if (DECL_SIZE (field) != 0
5269 && host_integerp (bit_position (field), 1))
5270 bitpos += int_bit_position (field);
5272 /* ??? FIXME: else assume zero offset. */
5274 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5275 function_arg_record_value_2 (TREE_TYPE (field),
5279 else if (FLOAT_TYPE_P (TREE_TYPE (field))
5284 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5286 enum machine_mode mode = DECL_MODE (field);
5289 function_arg_record_value_3 (bitpos, parms);
5290 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
5291 + ((mode == SFmode || mode == SCmode)
5292 && (bitpos & 32) != 0);
5295 case SCmode: mode = SFmode; break;
5296 case DCmode: mode = DFmode; break;
5297 case TCmode: mode = TFmode; break;
5300 reg = gen_rtx_REG (mode, regno);
5301 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5302 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5303 GEN_INT (bitpos / BITS_PER_UNIT));
5305 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5307 regno += GET_MODE_SIZE (mode) / 4;
5308 reg = gen_rtx_REG (mode, regno);
5309 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5310 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5311 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5318 if (parms->intoffset == -1)
5319 parms->intoffset = bitpos;
5325 /* Used by function_arg and function_value to implement the complex
5326 conventions of the 64-bit ABI for passing and returning structures.
5327 Return an expression valid as a return value for the two macros
5328 FUNCTION_ARG and FUNCTION_VALUE.
5330 TYPE is the data type of the argument (as a tree).
5331 This is null for libcalls where that information may
5333 MODE is the argument's machine mode.
5334 SLOTNO is the index number of the argument's slot in the parameter array.
5335 NAMED is nonzero if this argument is a named parameter
5336 (otherwise it is an extra parameter matching an ellipsis).
5337 REGBASE is the regno of the base register for the parameter array. */
5340 function_arg_record_value (tree type, enum machine_mode mode,
5341 int slotno, int named, int regbase)
5343 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5344 struct function_arg_record_value_parms parms;
5347 parms.ret = NULL_RTX;
5348 parms.slotno = slotno;
5349 parms.named = named;
5350 parms.regbase = regbase;
5353 /* Compute how many registers we need. */
5355 parms.intoffset = 0;
5356 function_arg_record_value_1 (type, 0, &parms, false);
5358 /* Take into account pending integer fields. */
5359 if (parms.intoffset != -1)
5361 unsigned int startbit, endbit;
5362 int intslots, this_slotno;
5364 startbit = parms.intoffset & -BITS_PER_WORD;
5365 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5366 intslots = (endbit - startbit) / BITS_PER_WORD;
5367 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5369 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5371 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5372 /* We need to pass this field on the stack. */
5376 parms.nregs += intslots;
5378 nregs = parms.nregs;
5380 /* Allocate the vector and handle some annoying special cases. */
5383 /* ??? Empty structure has no value? Duh? */
5386 /* Though there's nothing really to store, return a word register
5387 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5388 leads to breakage due to the fact that there are zero bytes to
5390 return gen_rtx_REG (mode, regbase);
5394 /* ??? C++ has structures with no fields, and yet a size. Give up
5395 for now and pass everything back in integer registers. */
5396 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5398 if (nregs + slotno > SPARC_INT_ARG_MAX)
5399 nregs = SPARC_INT_ARG_MAX - slotno;
5404 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5406 /* If at least one field must be passed on the stack, generate
5407 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5408 also be passed on the stack. We can't do much better because the
5409 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5410 of structures for which the fields passed exclusively in registers
5411 are not at the beginning of the structure. */
5413 XVECEXP (parms.ret, 0, 0)
5414 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5416 /* Fill in the entries. */
5418 parms.intoffset = 0;
5419 function_arg_record_value_2 (type, 0, &parms, false);
5420 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5422 if (parms.nregs != nregs)
5428 /* Used by function_arg and function_value to implement the conventions
5429 of the 64-bit ABI for passing and returning unions.
5430 Return an expression valid as a return value for the two macros
5431 FUNCTION_ARG and FUNCTION_VALUE.
5433 SIZE is the size in bytes of the union.
5434 REGNO is the hard register the union will be passed in. */
5437 function_arg_union_value (int size, int regno)
5439 enum machine_mode mode;
5442 if (size <= UNITS_PER_WORD)
5445 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5447 reg = gen_rtx_REG (mode, regno);
5449 /* Unions are passed left-justified. */
5450 return gen_rtx_PARALLEL (mode,
5451 gen_rtvec (1, gen_rtx_EXPR_LIST (VOIDmode,
5456 /* Handle the FUNCTION_ARG macro.
5457 Determine where to put an argument to a function.
5458 Value is zero to push the argument on the stack,
5459 or a hard register in which to store the argument.
5461 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5462 the preceding args and about the function being called.
5463 MODE is the argument's machine mode.
5464 TYPE is the data type of the argument (as a tree).
5465 This is null for libcalls where that information may
5467 NAMED is nonzero if this argument is a named parameter
5468 (otherwise it is an extra parameter matching an ellipsis).
5469 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5472 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5473 tree type, int named, int incoming_p)
5475 int regbase = (incoming_p
5476 ? SPARC_INCOMING_INT_ARG_FIRST
5477 : SPARC_OUTGOING_INT_ARG_FIRST);
5478 int slotno, regno, padding;
5481 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5489 reg = gen_rtx_REG (mode, regno);
5493 if (type && TREE_CODE (type) == RECORD_TYPE)
5495 /* Structures up to 16 bytes in size are passed in arg slots on the
5496 stack and are promoted to registers where possible. */
5498 if (int_size_in_bytes (type) > 16)
5499 abort (); /* shouldn't get here */
5501 return function_arg_record_value (type, mode, slotno, named, regbase);
5503 else if (type && TREE_CODE (type) == UNION_TYPE)
5505 HOST_WIDE_INT size = int_size_in_bytes (type);
5508 abort (); /* shouldn't get here */
5510 return function_arg_union_value (size, regno);
5512 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5513 but also have the slot allocated for them.
5514 If no prototype is in scope fp values in register slots get passed
5515 in two places, either fp regs and int regs or fp regs and memory. */
5516 else if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5517 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5518 && SPARC_FP_REG_P (regno))
5520 reg = gen_rtx_REG (mode, regno);
5521 if (cum->prototype_p || cum->libcall_p)
5523 /* "* 2" because fp reg numbers are recorded in 4 byte
5526 /* ??? This will cause the value to be passed in the fp reg and
5527 in the stack. When a prototype exists we want to pass the
5528 value in the reg but reserve space on the stack. That's an
5529 optimization, and is deferred [for a bit]. */
5530 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5531 return gen_rtx_PARALLEL (mode,
5533 gen_rtx_EXPR_LIST (VOIDmode,
5534 NULL_RTX, const0_rtx),
5535 gen_rtx_EXPR_LIST (VOIDmode,
5539 /* ??? It seems that passing back a register even when past
5540 the area declared by REG_PARM_STACK_SPACE will allocate
5541 space appropriately, and will not copy the data onto the
5542 stack, exactly as we desire.
5544 This is due to locate_and_pad_parm being called in
5545 expand_call whenever reg_parm_stack_space > 0, which
5546 while beneficial to our example here, would seem to be
5547 in error from what had been intended. Ho hum... -- r~ */
5555 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5559 /* On incoming, we don't need to know that the value
5560 is passed in %f0 and %i0, and it confuses other parts
5561 causing needless spillage even on the simplest cases. */
5565 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5566 + (regno - SPARC_FP_ARG_FIRST) / 2);
5568 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5569 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5571 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5575 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5576 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5577 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5583 /* Scalar or complex int. */
5584 reg = gen_rtx_REG (mode, regno);
5590 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5591 For an arg passed partly in registers and partly in memory,
5592 this is the number of registers used.
5593 For args passed entirely in registers or entirely in memory, zero.
5595 Any arg that starts in the first 6 regs but won't entirely fit in them
5596 needs partial registers on v8. On v9, structures with integer
5597 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5598 values that begin in the last fp reg [where "last fp reg" varies with the
5599 mode] will be split between that reg and memory. */
5602 function_arg_partial_nregs (const struct sparc_args *cum,
5603 enum machine_mode mode, tree type, int named)
5605 int slotno, regno, padding;
5607 /* We pass 0 for incoming_p here, it doesn't matter. */
5608 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5615 if ((slotno + (mode == BLKmode
5616 ? ROUND_ADVANCE (int_size_in_bytes (type))
5617 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5618 > NPARM_REGS (SImode))
5619 return NPARM_REGS (SImode) - slotno;
5624 if (type && AGGREGATE_TYPE_P (type))
5626 int size = int_size_in_bytes (type);
5627 int align = TYPE_ALIGN (type);
5630 slotno += slotno & 1;
5631 if (size > 8 && size <= 16
5632 && slotno == SPARC_INT_ARG_MAX - 1)
5635 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5636 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5637 && ! (TARGET_FPU && named)))
5639 /* The complex types are passed as packed types. */
5640 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
5643 if (GET_MODE_ALIGNMENT (mode) == 128)
5645 slotno += slotno & 1;
5647 /* ??? The mode needs 3 slots? */
5648 if (slotno == SPARC_INT_ARG_MAX - 2)
5653 if (slotno == SPARC_INT_ARG_MAX - 1)
5657 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5659 if (GET_MODE_ALIGNMENT (mode) == 128)
5660 slotno += slotno & 1;
5661 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5669 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5670 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5671 quad-precision floats by invisible reference.
5672 v9: Aggregates greater than 16 bytes are passed by reference.
5673 For Pascal, also pass arrays by reference. */
5676 function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
5677 enum machine_mode mode, tree type,
5678 int named ATTRIBUTE_UNUSED)
5682 return ((type && AGGREGATE_TYPE_P (type))
5690 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5691 /* Consider complex values as aggregates, so care
5692 for CTImode and TCmode. */
5693 || GET_MODE_SIZE (mode) > 16
5695 && AGGREGATE_TYPE_P (type)
5696 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5700 /* Handle the FUNCTION_ARG_ADVANCE macro.
5701 Update the data in CUM to advance over an argument
5702 of mode MODE and data type TYPE.
5703 TYPE is null for libcalls where that information may not be available. */
5706 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5707 tree type, int named)
5709 int slotno, regno, padding;
5711 /* We pass 0 for incoming_p here, it doesn't matter. */
5712 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5714 /* If register required leading padding, add it. */
5716 cum->words += padding;
5720 cum->words += (mode != BLKmode
5721 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5722 : ROUND_ADVANCE (int_size_in_bytes (type)));
5726 if (type && AGGREGATE_TYPE_P (type))
5728 int size = int_size_in_bytes (type);
5732 else if (size <= 16)
5734 else /* passed by reference */
5739 cum->words += (mode != BLKmode
5740 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5741 : ROUND_ADVANCE (int_size_in_bytes (type)));
5746 /* Handle the FUNCTION_ARG_PADDING macro.
5747 For the 64 bit ABI structs are always stored left shifted in their
5751 function_arg_padding (enum machine_mode mode, tree type)
5753 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5756 /* Fall back to the default. */
5757 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5760 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5761 For v9, function return values are subject to the same rules as arguments,
5762 except that up to 32-bytes may be returned in registers. */
5765 function_value (tree type, enum machine_mode mode, int incoming_p)
5769 if (TARGET_ARCH64 && type)
5771 int regbase = (incoming_p
5772 ? SPARC_OUTGOING_INT_ARG_FIRST
5773 : SPARC_INCOMING_INT_ARG_FIRST);
5775 if (TREE_CODE (type) == RECORD_TYPE)
5777 /* Structures up to 32 bytes in size are passed in registers,
5778 promoted to fp registers where possible. */
5780 if (int_size_in_bytes (type) > 32)
5781 abort (); /* shouldn't get here */
5783 return function_arg_record_value (type, mode, 0, 1, regbase);
5785 else if (TREE_CODE (type) == UNION_TYPE)
5787 HOST_WIDE_INT size = int_size_in_bytes (type);
5790 abort (); /* shouldn't get here */
5792 return function_arg_union_value (size, regbase);
5794 else if (AGGREGATE_TYPE_P (type))
5796 /* All other aggregate types are passed in an integer register
5797 in a mode corresponding to the size of the type. */
5798 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5803 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5805 else if (GET_MODE_CLASS (mode) == MODE_INT
5806 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5811 regno = BASE_RETURN_VALUE_REG (mode);
5813 regno = BASE_OUTGOING_VALUE_REG (mode);
5815 return gen_rtx_REG (mode, regno);
5818 /* Do what is necessary for `va_start'. We look at the current function
5819 to determine if stdarg or varargs is used and return the address of
5820 the first unnamed parameter. */
5823 sparc_builtin_saveregs (void)
5825 int first_reg = current_function_args_info.words;
5829 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5830 emit_move_insn (gen_rtx_MEM (word_mode,
5831 gen_rtx_PLUS (Pmode,
5833 GEN_INT (FIRST_PARM_OFFSET (0)
5836 gen_rtx_REG (word_mode,
5837 BASE_INCOMING_ARG_REG (word_mode) + regno));
5839 address = gen_rtx_PLUS (Pmode,
5841 GEN_INT (FIRST_PARM_OFFSET (0)
5842 + UNITS_PER_WORD * first_reg));
5847 /* Implement `va_start' for varargs and stdarg. */
5850 sparc_va_start (tree valist, rtx nextarg)
5852 nextarg = expand_builtin_saveregs ();
5853 std_expand_builtin_va_start (valist, nextarg);
5856 /* Implement `va_arg'. */
5859 sparc_va_arg (tree valist, tree type)
5861 HOST_WIDE_INT size, rsize, align;
5866 /* Round up sizeof(type) to a word. */
5867 size = int_size_in_bytes (type);
5868 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5873 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5874 align = 2 * UNITS_PER_WORD;
5876 /* Consider complex values as aggregates, so care
5877 for CTImode and TCmode. */
5878 if ((unsigned HOST_WIDE_INT) size > 16)
5881 size = rsize = UNITS_PER_WORD;
5884 else if (AGGREGATE_TYPE_P (type))
5886 /* SPARC-V9 ABI states that structures up to 16 bytes in size
5887 are given whole slots as needed. */
5889 size = rsize = UNITS_PER_WORD;
5896 if (AGGREGATE_TYPE_P (type)
5897 || TYPE_MODE (type) == TFmode
5898 || TYPE_MODE (type) == SCmode
5899 || TYPE_MODE (type) == DCmode
5900 || TYPE_MODE (type) == TCmode)
5903 size = rsize = UNITS_PER_WORD;
5910 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5911 build_int_2 (align - 1, 0)));
5912 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5913 build_int_2 (-align, -1)));
5916 addr = incr = save_expr (incr);
5917 if (BYTES_BIG_ENDIAN && size < rsize)
5919 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5920 build_int_2 (rsize - size, 0)));
5922 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5923 build_int_2 (rsize, 0)));
5925 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5926 TREE_SIDE_EFFECTS (incr) = 1;
5927 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5929 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5931 /* If the address isn't aligned properly for the type,
5932 we may need to copy to a temporary.
5933 FIXME: This is inefficient. Usually we can do this
5936 && TYPE_ALIGN (type) > BITS_PER_WORD
5939 /* FIXME: We really need to specify that the temporary is live
5940 for the whole function because expand_builtin_va_arg wants
5941 the alias set to be get_varargs_alias_set (), but in this
5942 case the alias set is that for TYPE and if the memory gets
5943 reused it will be reused with alias set TYPE. */
5944 rtx tmp = assign_temp (type, 0, 1, 0);
5947 addr_rtx = force_reg (Pmode, addr_rtx);
5948 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5949 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5950 set_mem_align (addr_rtx, BITS_PER_WORD);
5951 tmp = shallow_copy_rtx (tmp);
5952 PUT_MODE (tmp, BLKmode);
5953 set_mem_alias_set (tmp, 0);
5955 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
5957 if (dest_addr != NULL_RTX)
5958 addr_rtx = dest_addr;
5960 addr_rtx = XCEXP (tmp, 0, MEM);
5965 addr_rtx = force_reg (Pmode, addr_rtx);
5966 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5967 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5973 /* Return the string to output a conditional branch to LABEL, which is
5974 the operand number of the label. OP is the conditional expression.
5975 XEXP (OP, 0) is assumed to be a condition code register (integer or
5976 floating point) and its mode specifies what kind of comparison we made.
5978 REVERSED is nonzero if we should reverse the sense of the comparison.
5980 ANNUL is nonzero if we should generate an annulling branch.
5982 NOOP is nonzero if we have to follow this branch by a noop.
5984 INSN, if set, is the insn. */
5987 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
5990 static char string[50];
5991 enum rtx_code code = GET_CODE (op);
5992 rtx cc_reg = XEXP (op, 0);
5993 enum machine_mode mode = GET_MODE (cc_reg);
5994 const char *labelno, *branch;
5995 int spaces = 8, far;
5998 /* v9 branches are limited to +-1MB. If it is too far away,
6011 fbne,a,pn %fcc2, .LC29
6019 far = get_attr_length (insn) >= 3;
6022 /* Reversal of FP compares takes care -- an ordered compare
6023 becomes an unordered compare and vice versa. */
6024 if (mode == CCFPmode || mode == CCFPEmode)
6025 code = reverse_condition_maybe_unordered (code);
6027 code = reverse_condition (code);
6030 /* Start by writing the branch condition. */
6031 if (mode == CCFPmode || mode == CCFPEmode)
6082 /* ??? !v9: FP branches cannot be preceded by another floating point
6083 insn. Because there is currently no concept of pre-delay slots,
6084 we can fix this only by always emitting a nop before a floating
6089 strcpy (string, "nop\n\t");
6090 strcat (string, branch);
6103 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6115 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6136 strcpy (string, branch);
6138 spaces -= strlen (branch);
6139 p = strchr (string, '\0');
6141 /* Now add the annulling, the label, and a possible noop. */
6156 if (! far && insn && INSN_ADDRESSES_SET_P ())
6158 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6159 - INSN_ADDRESSES (INSN_UID (insn)));
6160 /* Leave some instructions for "slop". */
6161 if (delta < -260000 || delta >= 260000)
6165 if (mode == CCFPmode || mode == CCFPEmode)
6167 static char v9_fcc_labelno[] = "%%fccX, ";
6168 /* Set the char indicating the number of the fcc reg to use. */
6169 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6170 labelno = v9_fcc_labelno;
6173 if (REGNO (cc_reg) == SPARC_FCC_REG)
6179 else if (mode == CCXmode || mode == CCX_NOOVmode)
6181 labelno = "%%xcc, ";
6187 labelno = "%%icc, ";
6192 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6195 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6205 strcpy (p, labelno);
6206 p = strchr (p, '\0');
6209 strcpy (p, ".+12\n\tnop\n\tb\t");
6216 /* Set the char indicating the number of the operand containing the
6221 strcpy (p, "\n\tnop");
6226 /* Emit a library call comparison between floating point X and Y.
6227 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6228 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6229 values as arguments instead of the TFmode registers themselves,
6230 that's why we cannot call emit_float_lib_cmp. */
6232 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6235 rtx slot0, slot1, result, tem, tem2;
6236 enum machine_mode mode;
6241 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6245 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6249 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6253 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6257 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6261 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6272 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6282 if (GET_CODE (x) != MEM)
6284 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6285 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6290 if (GET_CODE (y) != MEM)
6292 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6293 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6298 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6300 XEXP (slot0, 0), Pmode,
6301 XEXP (slot1, 0), Pmode);
6307 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6309 x, TFmode, y, TFmode);
6315 /* Immediately move the result of the libcall into a pseudo
6316 register so reload doesn't clobber the value if it needs
6317 the return register for a spill reg. */
6318 result = gen_reg_rtx (mode);
6319 emit_move_insn (result, hard_libcall_value (mode));
6324 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6328 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6333 emit_cmp_insn (result, const1_rtx,
6334 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6337 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6340 tem = gen_reg_rtx (mode);
6342 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6344 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6345 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6349 tem = gen_reg_rtx (mode);
6351 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6353 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6354 tem2 = gen_reg_rtx (mode);
6356 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6358 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6359 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6365 /* Generate an unsigned DImode to FP conversion. This is the same code
6366 optabs would emit if we didn't have TFmode patterns. */
6369 sparc_emit_floatunsdi (rtx *operands)
6371 rtx neglab, donelab, i0, i1, f0, in, out;
6372 enum machine_mode mode;
6375 in = force_reg (DImode, operands[1]);
6376 mode = GET_MODE (out);
6377 neglab = gen_label_rtx ();
6378 donelab = gen_label_rtx ();
6379 i0 = gen_reg_rtx (DImode);
6380 i1 = gen_reg_rtx (DImode);
6381 f0 = gen_reg_rtx (mode);
6383 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6385 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6386 emit_jump_insn (gen_jump (donelab));
6389 emit_label (neglab);
6391 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6392 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6393 emit_insn (gen_iordi3 (i0, i0, i1));
6394 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6395 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6397 emit_label (donelab);
6400 /* Return the string to output a conditional branch to LABEL, testing
6401 register REG. LABEL is the operand number of the label; REG is the
6402 operand number of the reg. OP is the conditional expression. The mode
6403 of REG says what kind of comparison we made.
6405 REVERSED is nonzero if we should reverse the sense of the comparison.
6407 ANNUL is nonzero if we should generate an annulling branch.
6409 NOOP is nonzero if we have to follow this branch by a noop. */
6412 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6413 int annul, int noop, rtx insn)
6415 static char string[50];
6416 enum rtx_code code = GET_CODE (op);
6417 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6422 /* branch on register are limited to +-128KB. If it is too far away,
6435 brgez,a,pn %o1, .LC29
6441 ba,pt %xcc, .LC29 */
6443 far = get_attr_length (insn) >= 3;
6445 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6447 code = reverse_condition (code);
6449 /* Only 64 bit versions of these instructions exist. */
6453 /* Start by writing the branch condition. */
6458 strcpy (string, "brnz");
6462 strcpy (string, "brz");
6466 strcpy (string, "brgez");
6470 strcpy (string, "brlz");
6474 strcpy (string, "brlez");
6478 strcpy (string, "brgz");
6485 p = strchr (string, '\0');
6487 /* Now add the annulling, reg, label, and nop. */
6494 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6497 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6502 *p = p < string + 8 ? '\t' : ' ';
6510 int veryfar = 1, delta;
6512 if (INSN_ADDRESSES_SET_P ())
6514 delta = (INSN_ADDRESSES (INSN_UID (dest))
6515 - INSN_ADDRESSES (INSN_UID (insn)));
6516 /* Leave some instructions for "slop". */
6517 if (delta >= -260000 && delta < 260000)
6521 strcpy (p, ".+12\n\tnop\n\t");
6532 strcpy (p, "ba,pt\t%%xcc, ");
6542 strcpy (p, "\n\tnop");
6547 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6548 Such instructions cannot be used in the delay slot of return insn on v9.
6549 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6553 epilogue_renumber (register rtx *where, int test)
6555 register const char *fmt;
6557 register enum rtx_code code;
6562 code = GET_CODE (*where);
6567 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6569 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6570 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6578 /* Do not replace the frame pointer with the stack pointer because
6579 it can cause the delayed instruction to load below the stack.
6580 This occurs when instructions like:
6582 (set (reg/i:SI 24 %i0)
6583 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6584 (const_int -20 [0xffffffec])) 0))
6586 are in the return delayed slot. */
6588 if (GET_CODE (XEXP (*where, 0)) == REG
6589 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6590 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6591 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6596 if (SPARC_STACK_BIAS
6597 && GET_CODE (XEXP (*where, 0)) == REG
6598 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6606 fmt = GET_RTX_FORMAT (code);
6608 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6613 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6614 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6617 else if (fmt[i] == 'e'
6618 && epilogue_renumber (&(XEXP (*where, i)), test))
6624 /* Leaf functions and non-leaf functions have different needs. */
6627 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6630 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6632 static const int *const reg_alloc_orders[] = {
6633 reg_leaf_alloc_order,
6634 reg_nonleaf_alloc_order};
6637 order_regs_for_local_alloc (void)
6639 static int last_order_nonleaf = 1;
6641 if (regs_ever_live[15] != last_order_nonleaf)
6643 last_order_nonleaf = !last_order_nonleaf;
6644 memcpy ((char *) reg_alloc_order,
6645 (const char *) reg_alloc_orders[last_order_nonleaf],
6646 FIRST_PSEUDO_REGISTER * sizeof (int));
6650 /* Return 1 if REG and MEM are legitimate enough to allow the various
6651 mem<-->reg splits to be run. */
6654 sparc_splitdi_legitimate (rtx reg, rtx mem)
6656 /* Punt if we are here by mistake. */
6657 if (! reload_completed)
6660 /* We must have an offsettable memory reference. */
6661 if (! offsettable_memref_p (mem))
6664 /* If we have legitimate args for ldd/std, we do not want
6665 the split to happen. */
6666 if ((REGNO (reg) % 2) == 0
6667 && mem_min_alignment (mem, 8))
6674 /* Return 1 if x and y are some kind of REG and they refer to
6675 different hard registers. This test is guaranteed to be
6676 run after reload. */
6679 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6681 if (GET_CODE (x) != REG)
6683 if (GET_CODE (y) != REG)
6685 if (REGNO (x) == REGNO (y))
6690 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6691 This makes them candidates for using ldd and std insns.
6693 Note reg1 and reg2 *must* be hard registers. */
6696 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6698 /* We might have been passed a SUBREG. */
6699 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6702 if (REGNO (reg1) % 2 != 0)
6705 /* Integer ldd is deprecated in SPARC V9 */
6706 if (TARGET_V9 && REGNO (reg1) < 32)
6709 return (REGNO (reg1) == REGNO (reg2) - 1);
6712 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6715 This can only happen when addr1 and addr2, the addresses in mem1
6716 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6717 addr1 must also be aligned on a 64-bit boundary.
6719 Also iff dependent_reg_rtx is not null it should not be used to
6720 compute the address for mem1, i.e. we cannot optimize a sequence
6732 But, note that the transformation from:
6737 is perfectly fine. Thus, the peephole2 patterns always pass us
6738 the destination register of the first load, never the second one.
6740 For stores we don't have a similar problem, so dependent_reg_rtx is
6744 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6748 HOST_WIDE_INT offset1;
6750 /* The mems cannot be volatile. */
6751 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6754 /* MEM1 should be aligned on a 64-bit boundary. */
6755 if (MEM_ALIGN (mem1) < 64)
6758 addr1 = XEXP (mem1, 0);
6759 addr2 = XEXP (mem2, 0);
6761 /* Extract a register number and offset (if used) from the first addr. */
6762 if (GET_CODE (addr1) == PLUS)
6764 /* If not a REG, return zero. */
6765 if (GET_CODE (XEXP (addr1, 0)) != REG)
6769 reg1 = REGNO (XEXP (addr1, 0));
6770 /* The offset must be constant! */
6771 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6773 offset1 = INTVAL (XEXP (addr1, 1));
6776 else if (GET_CODE (addr1) != REG)
6780 reg1 = REGNO (addr1);
6781 /* This was a simple (mem (reg)) expression. Offset is 0. */
6785 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6786 if (GET_CODE (addr2) != PLUS)
6789 if (GET_CODE (XEXP (addr2, 0)) != REG
6790 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6793 if (reg1 != REGNO (XEXP (addr2, 0)))
6796 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6799 /* The first offset must be evenly divisible by 8 to ensure the
6800 address is 64 bit aligned. */
6801 if (offset1 % 8 != 0)
6804 /* The offset for the second addr must be 4 more than the first addr. */
6805 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6808 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6813 /* Return 1 if reg is a pseudo, or is the first register in
6814 a hard register pair. This makes it a candidate for use in
6815 ldd and std insns. */
6818 register_ok_for_ldd (rtx reg)
6820 /* We might have been passed a SUBREG. */
6821 if (GET_CODE (reg) != REG)
6824 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6825 return (REGNO (reg) % 2 == 0);
6830 /* Print operand X (an rtx) in assembler syntax to file FILE.
6831 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6832 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6835 print_operand (FILE *file, rtx x, int code)
6840 /* Output a 'nop' if there's nothing for the delay slot. */
6841 if (dbr_sequence_length () == 0)
6842 fputs ("\n\t nop", file);
6845 /* Output an annul flag if there's nothing for the delay slot and we
6846 are optimizing. This is always used with '(' below. */
6847 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6848 this is a dbx bug. So, we only do this when optimizing. */
6849 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6850 Always emit a nop in case the next instruction is a branch. */
6851 if (dbr_sequence_length () == 0
6852 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6856 /* Output a 'nop' if there's nothing for the delay slot and we are
6857 not optimizing. This is always used with '*' above. */
6858 if (dbr_sequence_length () == 0
6859 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6860 fputs ("\n\t nop", file);
6863 /* Output the Embedded Medium/Anywhere code model base register. */
6864 fputs (EMBMEDANY_BASE_REG, file);
6867 /* Print out what we are using as the frame pointer. This might
6868 be %fp, or might be %sp+offset. */
6869 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6870 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC, frame_base_name, frame_base_offset);
6873 /* Print some local dynamic TLS name. */
6874 assemble_name (file, get_some_local_dynamic_name ());
6877 /* Adjust the operand to take into account a RESTORE operation. */
6878 if (GET_CODE (x) == CONST_INT)
6880 else if (GET_CODE (x) != REG)
6881 output_operand_lossage ("invalid %%Y operand");
6882 else if (REGNO (x) < 8)
6883 fputs (reg_names[REGNO (x)], file);
6884 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6885 fputs (reg_names[REGNO (x)-16], file);
6887 output_operand_lossage ("invalid %%Y operand");
6890 /* Print out the low order register name of a register pair. */
6891 if (WORDS_BIG_ENDIAN)
6892 fputs (reg_names[REGNO (x)+1], file);
6894 fputs (reg_names[REGNO (x)], file);
6897 /* Print out the high order register name of a register pair. */
6898 if (WORDS_BIG_ENDIAN)
6899 fputs (reg_names[REGNO (x)], file);
6901 fputs (reg_names[REGNO (x)+1], file);
6904 /* Print out the second register name of a register pair or quad.
6905 I.e., R (%o0) => %o1. */
6906 fputs (reg_names[REGNO (x)+1], file);
6909 /* Print out the third register name of a register quad.
6910 I.e., S (%o0) => %o2. */
6911 fputs (reg_names[REGNO (x)+2], file);
6914 /* Print out the fourth register name of a register quad.
6915 I.e., T (%o0) => %o3. */
6916 fputs (reg_names[REGNO (x)+3], file);
6919 /* Print a condition code register. */
6920 if (REGNO (x) == SPARC_ICC_REG)
6922 /* We don't handle CC[X]_NOOVmode because they're not supposed
6924 if (GET_MODE (x) == CCmode)
6925 fputs ("%icc", file);
6926 else if (GET_MODE (x) == CCXmode)
6927 fputs ("%xcc", file);
6932 /* %fccN register */
6933 fputs (reg_names[REGNO (x)], file);
6936 /* Print the operand's address only. */
6937 output_address (XEXP (x, 0));
6940 /* In this case we need a register. Use %g0 if the
6941 operand is const0_rtx. */
6943 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
6945 fputs ("%g0", file);
6952 switch (GET_CODE (x))
6954 case IOR: fputs ("or", file); break;
6955 case AND: fputs ("and", file); break;
6956 case XOR: fputs ("xor", file); break;
6957 default: output_operand_lossage ("invalid %%A operand");
6962 switch (GET_CODE (x))
6964 case IOR: fputs ("orn", file); break;
6965 case AND: fputs ("andn", file); break;
6966 case XOR: fputs ("xnor", file); break;
6967 default: output_operand_lossage ("invalid %%B operand");
6971 /* These are used by the conditional move instructions. */
6975 enum rtx_code rc = GET_CODE (x);
6979 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6980 if (mode == CCFPmode || mode == CCFPEmode)
6981 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6983 rc = reverse_condition (GET_CODE (x));
6987 case NE: fputs ("ne", file); break;
6988 case EQ: fputs ("e", file); break;
6989 case GE: fputs ("ge", file); break;
6990 case GT: fputs ("g", file); break;
6991 case LE: fputs ("le", file); break;
6992 case LT: fputs ("l", file); break;
6993 case GEU: fputs ("geu", file); break;
6994 case GTU: fputs ("gu", file); break;
6995 case LEU: fputs ("leu", file); break;
6996 case LTU: fputs ("lu", file); break;
6997 case LTGT: fputs ("lg", file); break;
6998 case UNORDERED: fputs ("u", file); break;
6999 case ORDERED: fputs ("o", file); break;
7000 case UNLT: fputs ("ul", file); break;
7001 case UNLE: fputs ("ule", file); break;
7002 case UNGT: fputs ("ug", file); break;
7003 case UNGE: fputs ("uge", file); break;
7004 case UNEQ: fputs ("ue", file); break;
7005 default: output_operand_lossage (code == 'c'
7006 ? "invalid %%c operand"
7007 : "invalid %%C operand");
7012 /* These are used by the movr instruction pattern. */
7016 enum rtx_code rc = (code == 'd'
7017 ? reverse_condition (GET_CODE (x))
7021 case NE: fputs ("ne", file); break;
7022 case EQ: fputs ("e", file); break;
7023 case GE: fputs ("gez", file); break;
7024 case LT: fputs ("lz", file); break;
7025 case LE: fputs ("lez", file); break;
7026 case GT: fputs ("gz", file); break;
7027 default: output_operand_lossage (code == 'd'
7028 ? "invalid %%d operand"
7029 : "invalid %%D operand");
7036 /* Print a sign-extended character. */
7037 int i = trunc_int_for_mode (INTVAL (x), QImode);
7038 fprintf (file, "%d", i);
7043 /* Operand must be a MEM; write its address. */
7044 if (GET_CODE (x) != MEM)
7045 output_operand_lossage ("invalid %%f operand");
7046 output_address (XEXP (x, 0));
7051 /* Print a sign-extended 32-bit value. */
7053 if (GET_CODE(x) == CONST_INT)
7055 else if (GET_CODE(x) == CONST_DOUBLE)
7056 i = CONST_DOUBLE_LOW (x);
7059 output_operand_lossage ("invalid %%s operand");
7062 i = trunc_int_for_mode (i, SImode);
7063 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7068 /* Do nothing special. */
7072 /* Undocumented flag. */
7073 output_operand_lossage ("invalid operand output code");
7076 if (GET_CODE (x) == REG)
7077 fputs (reg_names[REGNO (x)], file);
7078 else if (GET_CODE (x) == MEM)
7081 /* Poor Sun assembler doesn't understand absolute addressing. */
7082 if (CONSTANT_P (XEXP (x, 0)))
7083 fputs ("%g0+", file);
7084 output_address (XEXP (x, 0));
7087 else if (GET_CODE (x) == HIGH)
7089 fputs ("%hi(", file);
7090 output_addr_const (file, XEXP (x, 0));
7093 else if (GET_CODE (x) == LO_SUM)
7095 print_operand (file, XEXP (x, 0), 0);
7096 if (TARGET_CM_MEDMID)
7097 fputs ("+%l44(", file);
7099 fputs ("+%lo(", file);
7100 output_addr_const (file, XEXP (x, 1));
7103 else if (GET_CODE (x) == CONST_DOUBLE
7104 && (GET_MODE (x) == VOIDmode
7105 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
7107 if (CONST_DOUBLE_HIGH (x) == 0)
7108 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
7109 else if (CONST_DOUBLE_HIGH (x) == -1
7110 && CONST_DOUBLE_LOW (x) < 0)
7111 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
7113 output_operand_lossage ("long long constant not a valid immediate operand");
7115 else if (GET_CODE (x) == CONST_DOUBLE)
7116 output_operand_lossage ("floating point constant not a valid immediate operand");
7117 else { output_addr_const (file, x); }
7120 /* Target hook for assembling integer objects. The sparc version has
7121 special handling for aligned DI-mode objects. */
7124 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7126 /* ??? We only output .xword's for symbols and only then in environments
7127 where the assembler can handle them. */
7128 if (aligned_p && size == 8
7129 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7133 assemble_integer_with_op ("\t.xword\t", x);
7138 assemble_aligned_integer (4, const0_rtx);
7139 assemble_aligned_integer (4, x);
7143 return default_assemble_integer (x, size, aligned_p);
7146 /* Return the value of a code used in the .proc pseudo-op that says
7147 what kind of result this function returns. For non-C types, we pick
7148 the closest C type. */
7150 #ifndef SHORT_TYPE_SIZE
7151 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7154 #ifndef INT_TYPE_SIZE
7155 #define INT_TYPE_SIZE BITS_PER_WORD
7158 #ifndef LONG_TYPE_SIZE
7159 #define LONG_TYPE_SIZE BITS_PER_WORD
7162 #ifndef LONG_LONG_TYPE_SIZE
7163 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7166 #ifndef FLOAT_TYPE_SIZE
7167 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7170 #ifndef DOUBLE_TYPE_SIZE
7171 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7174 #ifndef LONG_DOUBLE_TYPE_SIZE
7175 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7179 sparc_type_code (register tree type)
7181 register unsigned long qualifiers = 0;
7182 register unsigned shift;
7184 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7185 setting more, since some assemblers will give an error for this. Also,
7186 we must be careful to avoid shifts of 32 bits or more to avoid getting
7187 unpredictable results. */
7189 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7191 switch (TREE_CODE (type))
7197 qualifiers |= (3 << shift);
7202 qualifiers |= (2 << shift);
7206 case REFERENCE_TYPE:
7208 qualifiers |= (1 << shift);
7212 return (qualifiers | 8);
7215 case QUAL_UNION_TYPE:
7216 return (qualifiers | 9);
7219 return (qualifiers | 10);
7222 return (qualifiers | 16);
7225 /* If this is a range type, consider it to be the underlying
7227 if (TREE_TYPE (type) != 0)
7230 /* Carefully distinguish all the standard types of C,
7231 without messing up if the language is not C. We do this by
7232 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
7233 look at both the names and the above fields, but that's redundant.
7234 Any type whose size is between two C types will be considered
7235 to be the wider of the two types. Also, we do not have a
7236 special code to use for "long long", so anything wider than
7237 long is treated the same. Note that we can't distinguish
7238 between "int" and "long" in this code if they are the same
7239 size, but that's fine, since neither can the assembler. */
7241 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7242 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
7244 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7245 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
7247 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7248 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
7251 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
7254 /* If this is a range type, consider it to be the underlying
7256 if (TREE_TYPE (type) != 0)
7259 /* Carefully distinguish all the standard types of C,
7260 without messing up if the language is not C. */
7262 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7263 return (qualifiers | 6);
7266 return (qualifiers | 7);
7268 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7269 /* ??? We need to distinguish between double and float complex types,
7270 but I don't know how yet because I can't reach this code from
7271 existing front-ends. */
7272 return (qualifiers | 7); /* Who knows? */
7274 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7275 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7276 case FILE_TYPE: /* GNU Pascal FILE type. */
7277 case SET_TYPE: /* GNU Pascal SET type. */
7278 case LANG_TYPE: /* ? */
7282 abort (); /* Not a type! */
7289 /* Nested function support. */
7291 /* Emit RTL insns to initialize the variable parts of a trampoline.
7292 FNADDR is an RTX for the address of the function's pure code.
7293 CXT is an RTX for the static chain value for the function.
7295 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7296 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7297 (to store insns). This is a bit excessive. Perhaps a different
7298 mechanism would be better here.
7300 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7303 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7305 /* SPARC 32-bit trampoline:
7308 sethi %hi(static), %g2
7310 or %g2, %lo(static), %g2
7312 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7313 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7317 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7318 expand_binop (SImode, ior_optab,
7319 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7320 size_int (10), 0, 1),
7321 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7322 NULL_RTX, 1, OPTAB_DIRECT));
7325 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7326 expand_binop (SImode, ior_optab,
7327 expand_shift (RSHIFT_EXPR, SImode, cxt,
7328 size_int (10), 0, 1),
7329 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7330 NULL_RTX, 1, OPTAB_DIRECT));
7333 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7334 expand_binop (SImode, ior_optab,
7335 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7336 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7337 NULL_RTX, 1, OPTAB_DIRECT));
7340 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7341 expand_binop (SImode, ior_optab,
7342 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7343 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7344 NULL_RTX, 1, OPTAB_DIRECT));
7346 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7347 aligned on a 16 byte boundary so one flush clears it all. */
7348 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7349 if (sparc_cpu != PROCESSOR_ULTRASPARC
7350 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7351 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7352 plus_constant (tramp, 8)))));
7354 /* Call __enable_execute_stack after writing onto the stack to make sure
7355 the stack address is accessible. */
7356 #ifdef TRANSFER_FROM_TRAMPOLINE
7357 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7358 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7363 /* The 64-bit version is simpler because it makes more sense to load the
7364 values as "immediate" data out of the trampoline. It's also easier since
7365 we can read the PC without clobbering a register. */
7368 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7370 /* SPARC 64-bit trampoline:
7379 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7380 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7381 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7382 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7383 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7384 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7385 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7386 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7387 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7388 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7389 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7391 if (sparc_cpu != PROCESSOR_ULTRASPARC
7392 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7393 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7395 /* Call __enable_execute_stack after writing onto the stack to make sure
7396 the stack address is accessible. */
7397 #ifdef TRANSFER_FROM_TRAMPOLINE
7398 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7399 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7403 /* Subroutines to support a flat (single) register window calling
7406 /* Single-register window sparc stack frames look like:
7408 Before call After call
7409 +-----------------------+ +-----------------------+
7411 mem | caller's temps. | | caller's temps. |
7413 +-----------------------+ +-----------------------+
7415 | arguments on stack. | | arguments on stack. |
7417 +-----------------------+FP+92->+-----------------------+
7418 | 6 words to save | | 6 words to save |
7419 | arguments passed | | arguments passed |
7420 | in registers, even | | in registers, even |
7421 | if not passed. | | if not passed. |
7422 SP+68->+-----------------------+FP+68->+-----------------------+
7423 | 1 word struct addr | | 1 word struct addr |
7424 +-----------------------+FP+64->+-----------------------+
7426 | 16 word reg save area | | 16 word reg save area |
7428 SP->+-----------------------+ FP->+-----------------------+
7430 | fp/alu reg moves |
7431 FP-16->+-----------------------+
7435 +-----------------------+
7437 | fp register save |
7439 +-----------------------+
7441 | gp register save |
7443 +-----------------------+
7445 | alloca allocations |
7447 +-----------------------+
7449 | arguments on stack |
7451 SP+92->+-----------------------+
7453 | arguments passed |
7454 | in registers, even |
7455 low | if not passed. |
7456 memory SP+68->+-----------------------+
7457 | 1 word struct addr |
7458 SP+64->+-----------------------+
7460 I 16 word reg save area |
7462 SP->+-----------------------+ */
7464 /* Structure to be filled in by sparc_flat_compute_frame_size with register
7465 save masks, and offsets for the current function. */
7467 struct sparc_frame_info
7469 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */
7470 HOST_WIDE_INT var_size; /* # bytes that variables take up. */
7471 int args_size; /* # bytes that outgoing arguments take up. */
7472 int extra_size; /* # bytes of extra gunk. */
7473 int gp_reg_size; /* # bytes needed to store gp regs. */
7474 int fp_reg_size; /* # bytes needed to store fp regs. */
7475 unsigned long gmask; /* Mask of saved gp registers. */
7476 unsigned long fmask; /* Mask of saved fp registers. */
7477 int reg_offset; /* Offset from new sp to store regs. */
7478 int initialized; /* Nonzero if frame size already calculated. */
7481 /* Current frame information calculated by sparc_flat_compute_frame_size. */
7482 struct sparc_frame_info current_frame_info;
7484 /* Zero structure to initialize current_frame_info. */
7485 struct sparc_frame_info zero_frame_info;
7487 #define RETURN_ADDR_REGNUM 15
7488 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
7489 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
7491 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
7494 sparc_flat_must_save_register_p (int regno)
7496 /* General case: call-saved registers live at some point. */
7497 if (!call_used_regs[regno] && regs_ever_live[regno])
7500 /* Frame pointer register (%i7) if needed. */
7501 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
7504 /* PIC register (%l7) if needed. */
7505 if (regno == (int) PIC_OFFSET_TABLE_REGNUM
7506 && flag_pic && current_function_uses_pic_offset_table)
7509 /* Return address register (%o7) if needed. */
7510 if (regno == RETURN_ADDR_REGNUM
7511 && (regs_ever_live[RETURN_ADDR_REGNUM]
7512 /* When the PIC offset table is used, the PIC register
7513 is set by using a bare call that clobbers %o7. */
7514 || (flag_pic && current_function_uses_pic_offset_table)))
7520 /* Return the bytes needed to compute the frame pointer from the current
7524 sparc_flat_compute_frame_size (HOST_WIDE_INT size)
7525 /* # of var. bytes allocated. */
7528 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */
7529 HOST_WIDE_INT var_size; /* # bytes that variables take up. */
7530 int args_size; /* # bytes that outgoing arguments take up. */
7531 int extra_size; /* # extra bytes. */
7532 int gp_reg_size; /* # bytes needed to store gp regs. */
7533 int fp_reg_size; /* # bytes needed to store fp regs. */
7534 unsigned long gmask; /* Mask of saved gp registers. */
7535 unsigned long fmask; /* Mask of saved fp registers. */
7536 int reg_offset; /* Offset to register save area. */
7537 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
7539 /* This is the size of the 16 word reg save area, 1 word struct addr
7540 area, and 4 word fp/alu register copy area. */
7541 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
7551 if (!leaf_function_p ())
7553 /* Also include the size needed for the 6 parameter registers. */
7554 args_size = current_function_outgoing_args_size + 24;
7556 total_size = var_size + args_size;
7558 /* Calculate space needed for gp registers. */
7559 for (regno = 1; regno <= 31; regno++)
7561 if (sparc_flat_must_save_register_p (regno))
7563 /* If we need to save two regs in a row, ensure there's room to bump
7564 up the address to align it to a doubleword boundary. */
7565 if ((regno & 0x1) == 0 && sparc_flat_must_save_register_p (regno+1))
7567 if (gp_reg_size % 8 != 0)
7569 gp_reg_size += 2 * UNITS_PER_WORD;
7570 gmask |= 3 << regno;
7576 gp_reg_size += UNITS_PER_WORD;
7577 gmask |= 1 << regno;
7582 /* Calculate space needed for fp registers. */
7583 for (regno = 32; regno <= 63; regno++)
7585 if (regs_ever_live[regno] && !call_used_regs[regno])
7587 fp_reg_size += UNITS_PER_WORD;
7588 fmask |= 1 << (regno - 32);
7595 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
7596 /* Ensure save area is 8 byte aligned if we need it. */
7598 if (need_aligned_p && n != 0)
7600 total_size += 8 - n;
7601 reg_offset += 8 - n;
7603 total_size += gp_reg_size + fp_reg_size;
7606 /* If we must allocate a stack frame at all, we must also allocate
7607 room for register window spillage, so as to be binary compatible
7608 with libraries and operating systems that do not use -mflat. */
7610 total_size += extra_size;
7614 total_size = SPARC_STACK_ALIGN (total_size);
7616 /* Save other computed information. */
7617 current_frame_info.total_size = total_size;
7618 current_frame_info.var_size = var_size;
7619 current_frame_info.args_size = args_size;
7620 current_frame_info.extra_size = extra_size;
7621 current_frame_info.gp_reg_size = gp_reg_size;
7622 current_frame_info.fp_reg_size = fp_reg_size;
7623 current_frame_info.gmask = gmask;
7624 current_frame_info.fmask = fmask;
7625 current_frame_info.reg_offset = reg_offset;
7626 current_frame_info.initialized = reload_completed;
7628 /* Ok, we're done. */
7632 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7635 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7636 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7637 [BASE_REG+OFFSET] will always be a valid address.
7639 WORD_OP is either "st" for save, "ld" for restore.
7640 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7643 sparc_flat_save_restore (FILE *file, const char *base_reg, int offset,
7644 unsigned long gmask, unsigned long fmask,
7645 const char *word_op, const char *doubleword_op,
7646 HOST_WIDE_INT base_offset)
7650 if (gmask == 0 && fmask == 0)
7653 /* Save registers starting from high to low. We've already saved the
7654 previous frame pointer and previous return address for the debugger's
7655 sake. The debugger allows us to not need a nop in the epilog if at least
7656 one register is reloaded in addition to return address. */
7660 for (regno = 1; regno <= 31; regno++)
7662 if ((gmask & (1L << regno)) != 0)
7664 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7666 /* We can save two registers in a row. If we're not at a
7667 double word boundary, move to one.
7668 sparc_flat_compute_frame_size ensures there's room to do
7670 if (offset % 8 != 0)
7671 offset += UNITS_PER_WORD;
7673 if (word_op[0] == 's')
7675 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7676 doubleword_op, reg_names[regno],
7678 if (dwarf2out_do_frame ())
7680 char *l = dwarf2out_cfi_label ();
7681 dwarf2out_reg_save (l, regno, offset + base_offset);
7683 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7687 fprintf (file, "\t%s\t[%s+%d], %s\n",
7688 doubleword_op, base_reg, offset,
7691 offset += 2 * UNITS_PER_WORD;
7696 if (word_op[0] == 's')
7698 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7699 word_op, reg_names[regno],
7701 if (dwarf2out_do_frame ())
7702 dwarf2out_reg_save ("", regno, offset + base_offset);
7705 fprintf (file, "\t%s\t[%s+%d], %s\n",
7706 word_op, base_reg, offset, reg_names[regno]);
7708 offset += UNITS_PER_WORD;
7716 for (regno = 32; regno <= 63; regno++)
7718 if ((fmask & (1L << (regno - 32))) != 0)
7720 if (word_op[0] == 's')
7722 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7723 word_op, reg_names[regno],
7725 if (dwarf2out_do_frame ())
7726 dwarf2out_reg_save ("", regno, offset + base_offset);
7729 fprintf (file, "\t%s\t[%s+%d], %s\n",
7730 word_op, base_reg, offset, reg_names[regno]);
7732 offset += UNITS_PER_WORD;
7738 /* Set up the stack and frame (if desired) for the function. */
7741 sparc_flat_function_prologue (FILE *file, HOST_WIDE_INT size)
7743 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7744 unsigned long gmask = current_frame_info.gmask;
7746 sparc_output_scratch_registers (file);
7748 /* This is only for the human reader. */
7749 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7750 fprintf (file, "\t%s# vars= "HOST_WIDE_INT_PRINT_DEC", "
7751 "regs= %d/%d, args= %d, extra= %d\n",
7753 current_frame_info.var_size,
7754 current_frame_info.gp_reg_size / 4,
7755 current_frame_info.fp_reg_size / 4,
7756 current_function_outgoing_args_size,
7757 current_frame_info.extra_size);
7759 size = SPARC_STACK_ALIGN (size);
7760 size = (! current_frame_info.initialized
7761 ? sparc_flat_compute_frame_size (size)
7762 : current_frame_info.total_size);
7764 /* These cases shouldn't happen. Catch them now. */
7765 if (size == 0 && (gmask || current_frame_info.fmask))
7768 /* Allocate our stack frame by decrementing %sp.
7769 At present, the only algorithm gdb can use to determine if this is a
7770 flat frame is if we always set %i7 if we set %sp. This can be optimized
7771 in the future by putting in some sort of debugging information that says
7772 this is a `flat' function. However, there is still the case of debugging
7773 code without such debugging information (including cases where most fns
7774 have such info, but there is one that doesn't). So, always do this now
7775 so we don't get a lot of code out there that gdb can't handle.
7776 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7777 distinguish us from a non-flat function but there won't (and shouldn't)
7778 be any differences anyway. The return pc is saved (if necessary) right
7779 after %i7 so gdb won't have to look too far to find it. */
7782 int reg_offset = current_frame_info.reg_offset;
7783 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7784 static const char *const t1_str = "%g1";
7786 /* Things get a little tricky if local variables take up more than ~4096
7787 bytes and outgoing arguments take up more than ~4096 bytes. When that
7788 happens, the register save area can't be accessed from either end of
7789 the frame. Handle this by decrementing %sp to the start of the gp
7790 register save area, save the regs, update %i7, and then set %sp to its
7791 final value. Given that we only have one scratch register to play
7792 with it is the cheapest solution, and it helps gdb out as it won't
7793 slow down recognition of flat functions.
7794 Don't change the order of insns emitted here without checking with
7795 the gdb folk first. */
7797 /* Is the entire register save area offsettable from %sp? */
7798 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
7802 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
7803 sp_str, size, sp_str);
7804 if (gmask & HARD_FRAME_POINTER_MASK)
7806 fprintf (file, "\tst\t%s, [%s+%d]\n",
7807 fp_str, sp_str, reg_offset);
7808 fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
7809 "\t%s# set up frame pointer\n",
7810 sp_str, size, fp_str, ASM_COMMENT_START);
7816 build_big_number (file, size, t1_str);
7817 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7818 if (gmask & HARD_FRAME_POINTER_MASK)
7820 fprintf (file, "\tst\t%s, [%s+%d]\n",
7821 fp_str, sp_str, reg_offset);
7822 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7823 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7827 if (dwarf2out_do_frame ())
7829 char *l = dwarf2out_cfi_label ();
7830 if (gmask & HARD_FRAME_POINTER_MASK)
7832 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7833 reg_offset - 4 - size);
7834 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7837 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7839 if (gmask & RETURN_ADDR_MASK)
7841 fprintf (file, "\tst\t%s, [%s+%d]\n",
7842 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7843 if (dwarf2out_do_frame ())
7844 dwarf2out_return_save ("", reg_offset - size);
7847 sparc_flat_save_restore (file, sp_str, reg_offset,
7848 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7849 current_frame_info.fmask,
7850 "st", "std", -size);
7854 /* Subtract %sp in two steps, but make sure there is always a
7855 64-byte register save area, and %sp is properly aligned. */
7857 /* Amount to decrement %sp by, the first time. */
7858 HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7860 /* Amount to decrement %sp by, the second time. */
7861 HOST_WIDE_INT size2 = size - size1;
7863 /* Offset to register save area from %sp after first decrement. */
7864 int offset = (int)(size1 - (size - reg_offset));
7868 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
7869 sp_str, size1, sp_str);
7870 if (gmask & HARD_FRAME_POINTER_MASK)
7872 fprintf (file, "\tst\t%s, [%s+%d]\n"
7873 "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
7874 "\t%s# set up frame pointer\n",
7875 fp_str, sp_str, offset, sp_str, size1,
7876 fp_str, ASM_COMMENT_START);
7882 build_big_number (file, size1, t1_str);
7883 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7884 if (gmask & HARD_FRAME_POINTER_MASK)
7886 fprintf (file, "\tst\t%s, [%s+%d]\n"
7887 "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7888 fp_str, sp_str, offset, sp_str, t1_str,
7889 fp_str, ASM_COMMENT_START);
7893 if (dwarf2out_do_frame ())
7895 char *l = dwarf2out_cfi_label ();
7896 if (gmask & HARD_FRAME_POINTER_MASK)
7898 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7899 offset - 4 - size1);
7900 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7903 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7905 if (gmask & RETURN_ADDR_MASK)
7907 fprintf (file, "\tst\t%s, [%s+%d]\n",
7908 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
7909 if (dwarf2out_do_frame ())
7910 /* offset - size1 == reg_offset - size
7911 if reg_offset were updated above like offset. */
7912 dwarf2out_return_save ("", offset - size1);
7915 sparc_flat_save_restore (file, sp_str, offset,
7916 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7917 current_frame_info.fmask,
7918 "st", "std", -size1);
7920 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
7921 sp_str, size2, sp_str);
7924 build_big_number (file, size2, t1_str);
7925 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7927 if (dwarf2out_do_frame ())
7928 if (! (gmask & HARD_FRAME_POINTER_MASK))
7929 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
7933 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
7936 /* Do any necessary cleanup after a function to restore stack, frame,
7940 sparc_flat_function_epilogue (FILE *file, HOST_WIDE_INT size)
7942 rtx epilogue_delay = current_function_epilogue_delay_list;
7943 int noepilogue = FALSE;
7945 /* This is only for the human reader. */
7946 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
7948 /* The epilogue does not depend on any registers, but the stack
7949 registers, so we assume that if we have 1 pending nop, it can be
7950 ignored, and 2 it must be filled (2 nops occur for integer
7951 multiply and divide). */
7953 size = SPARC_STACK_ALIGN (size);
7954 size = (!current_frame_info.initialized
7955 ? sparc_flat_compute_frame_size (size)
7956 : current_frame_info.total_size);
7958 if (size == 0 && epilogue_delay == 0)
7960 rtx insn = get_last_insn ();
7962 /* If the last insn was a BARRIER, we don't have to write any code
7963 because a jump (aka return) was put there. */
7964 if (GET_CODE (insn) == NOTE)
7965 insn = prev_nonnote_insn (insn);
7966 if (insn && GET_CODE (insn) == BARRIER)
7972 int reg_offset = current_frame_info.reg_offset;
7974 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7975 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7976 static const char *const t1_str = "%g1";
7978 /* In the reload sequence, we don't need to fill the load delay
7979 slots for most of the loads, also see if we can fill the final
7980 delay slot if not otherwise filled by the reload sequence. */
7983 build_big_number (file, size, t1_str);
7985 if (frame_pointer_needed)
7988 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7989 fp_str, t1_str, sp_str, ASM_COMMENT_START);
7991 fprintf (file,"\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
7992 "\t\t%s# sp not trusted here\n",
7993 fp_str, size, sp_str, ASM_COMMENT_START);
7996 /* Is the entire register save area offsettable from %sp? */
7997 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
8003 /* Restore %sp in two steps, but make sure there is always a
8004 64-byte register save area, and %sp is properly aligned. */
8006 /* Amount to increment %sp by, the first time. */
8007 reg_offset1 = ((reg_offset - 64 - 16) + 15) & -16;
8009 /* Offset to register save area from %sp. */
8010 reg_offset = reg_offset1 - reg_offset;
8012 if (reg_offset1 > 4096)
8014 build_big_number (file, reg_offset1, t1_str);
8015 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
8018 fprintf (file, "\tsub\t%s, -%d, %s\n", sp_str, reg_offset1, sp_str);
8021 /* We must restore the frame pointer and return address reg first
8022 because they are treated specially by the prologue output code. */
8023 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
8025 fprintf (file, "\tld\t[%s+%d], %s\n",
8026 sp_str, reg_offset, fp_str);
8029 if (current_frame_info.gmask & RETURN_ADDR_MASK)
8031 fprintf (file, "\tld\t[%s+%d], %s\n",
8032 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
8036 /* Restore any remaining saved registers. */
8037 sparc_flat_save_restore (file, sp_str, reg_offset,
8038 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
8039 current_frame_info.fmask,
8042 /* If we had to increment %sp in two steps, record it so the second
8043 restoration in the epilogue finishes up. */
8044 if (reg_offset1 > 0)
8046 size -= reg_offset1;
8048 build_big_number (file, size, t1_str);
8051 if (current_function_returns_struct)
8052 fprintf (file, "\tjmp\t%%o7+12\n");
8054 fprintf (file, "\tretl\n");
8056 /* If the only register saved is the return address, we need a
8057 nop, unless we have an instruction to put into it. Otherwise
8058 we don't since reloading multiple registers doesn't reference
8059 the register being loaded. */
8065 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1, NULL);
8068 else if (size > 4096)
8069 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
8072 fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
8073 sp_str, size, sp_str);
8076 fprintf (file, "\tnop\n");
8079 /* Reset state info for each function. */
8080 current_frame_info = zero_frame_info;
8082 sparc_output_deferred_case_vectors ();
8085 /* Define the number of delay slots needed for the function epilogue.
8087 On the sparc, we need a slot if either no stack has been allocated,
8088 or the only register saved is the return register. */
8091 sparc_flat_epilogue_delay_slots (void)
8093 if (!current_frame_info.initialized)
8094 (void) sparc_flat_compute_frame_size (get_frame_size ());
8096 if (current_frame_info.total_size == 0)
8102 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
8103 Any single length instruction which doesn't reference the stack or frame
8107 sparc_flat_eligible_for_epilogue_delay (rtx trial, int slot ATTRIBUTE_UNUSED)
8109 rtx pat = PATTERN (trial);
8111 if (get_attr_length (trial) != 1)
8114 if (! reg_mentioned_p (stack_pointer_rtx, pat)
8115 && ! reg_mentioned_p (frame_pointer_rtx, pat))
8121 /* Adjust the cost of a scheduling dependency. Return the new cost of
8122 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8125 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8127 enum attr_type insn_type;
8129 if (! recog_memoized (insn))
8132 insn_type = get_attr_type (insn);
8134 if (REG_NOTE_KIND (link) == 0)
8136 /* Data dependency; DEP_INSN writes a register that INSN reads some
8139 /* if a load, then the dependence must be on the memory address;
8140 add an extra "cycle". Note that the cost could be two cycles
8141 if the reg was written late in an instruction group; we ca not tell
8143 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
8146 /* Get the delay only if the address of the store is the dependence. */
8147 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
8149 rtx pat = PATTERN(insn);
8150 rtx dep_pat = PATTERN (dep_insn);
8152 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8153 return cost; /* This should not happen! */
8155 /* The dependency between the two instructions was on the data that
8156 is being stored. Assume that this implies that the address of the
8157 store is not dependent. */
8158 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8161 return cost + 3; /* An approximation. */
8164 /* A shift instruction cannot receive its data from an instruction
8165 in the same cycle; add a one cycle penalty. */
8166 if (insn_type == TYPE_SHIFT)
8167 return cost + 3; /* Split before cascade into shift. */
8171 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8172 INSN writes some cycles later. */
8174 /* These are only significant for the fpu unit; writing a fp reg before
8175 the fpu has finished with it stalls the processor. */
8177 /* Reusing an integer register causes no problems. */
8178 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8186 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8188 enum attr_type insn_type, dep_type;
8189 rtx pat = PATTERN(insn);
8190 rtx dep_pat = PATTERN (dep_insn);
8192 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
8195 insn_type = get_attr_type (insn);
8196 dep_type = get_attr_type (dep_insn);
8198 switch (REG_NOTE_KIND (link))
8201 /* Data dependency; DEP_INSN writes a register that INSN reads some
8208 /* Get the delay iff the address of the store is the dependence. */
8209 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8212 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8219 /* If a load, then the dependence must be on the memory address. If
8220 the addresses aren't equal, then it might be a false dependency */
8221 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
8223 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
8224 || GET_CODE (SET_DEST (dep_pat)) != MEM
8225 || GET_CODE (SET_SRC (pat)) != MEM
8226 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
8227 XEXP (SET_SRC (pat), 0)))
8235 /* Compare to branch latency is 0. There is no benefit from
8236 separating compare and branch. */
8237 if (dep_type == TYPE_COMPARE)
8239 /* Floating point compare to branch latency is less than
8240 compare to conditional move. */
8241 if (dep_type == TYPE_FPCMP)
8250 /* Anti-dependencies only penalize the fpu unit. */
8251 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8263 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8267 case PROCESSOR_SUPERSPARC:
8268 cost = supersparc_adjust_cost (insn, link, dep, cost);
8270 case PROCESSOR_HYPERSPARC:
8271 case PROCESSOR_SPARCLITE86X:
8272 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8281 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8282 int sched_verbose ATTRIBUTE_UNUSED,
8283 int max_ready ATTRIBUTE_UNUSED)
8288 sparc_use_dfa_pipeline_interface (void)
8290 if ((1 << sparc_cpu) &
8291 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
8292 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8293 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
8294 (1 << PROCESSOR_ULTRASPARC3)))
8300 sparc_use_sched_lookahead (void)
8302 if (sparc_cpu == PROCESSOR_ULTRASPARC
8303 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8305 if ((1 << sparc_cpu) &
8306 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8307 (1 << PROCESSOR_SPARCLITE86X)))
8313 sparc_issue_rate (void)
8320 /* Assume V9 processors are capable of at least dual-issue. */
8322 case PROCESSOR_SUPERSPARC:
8324 case PROCESSOR_HYPERSPARC:
8325 case PROCESSOR_SPARCLITE86X:
8327 case PROCESSOR_ULTRASPARC:
8328 case PROCESSOR_ULTRASPARC3:
8334 set_extends (rtx insn)
8336 register rtx pat = PATTERN (insn);
8338 switch (GET_CODE (SET_SRC (pat)))
8340 /* Load and some shift instructions zero extend. */
8343 /* sethi clears the high bits */
8345 /* LO_SUM is used with sethi. sethi cleared the high
8346 bits and the values used with lo_sum are positive */
8348 /* Store flag stores 0 or 1 */
8358 rtx op0 = XEXP (SET_SRC (pat), 0);
8359 rtx op1 = XEXP (SET_SRC (pat), 1);
8360 if (GET_CODE (op1) == CONST_INT)
8361 return INTVAL (op1) >= 0;
8362 if (GET_CODE (op0) != REG)
8364 if (sparc_check_64 (op0, insn) == 1)
8366 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8371 rtx op0 = XEXP (SET_SRC (pat), 0);
8372 rtx op1 = XEXP (SET_SRC (pat), 1);
8373 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8375 if (GET_CODE (op1) == CONST_INT)
8376 return INTVAL (op1) >= 0;
8377 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8380 return GET_MODE (SET_SRC (pat)) == SImode;
8381 /* Positive integers leave the high bits zero. */
8383 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8385 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8388 return - (GET_MODE (SET_SRC (pat)) == SImode);
8390 return sparc_check_64 (SET_SRC (pat), insn);
8396 /* We _ought_ to have only one kind per function, but... */
8397 static GTY(()) rtx sparc_addr_diff_list;
8398 static GTY(()) rtx sparc_addr_list;
8401 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8403 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8405 sparc_addr_diff_list
8406 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8408 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8412 sparc_output_addr_vec (rtx vec)
8414 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8415 int idx, vlen = XVECLEN (body, 0);
8417 #ifdef ASM_OUTPUT_ADDR_VEC_START
8418 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8421 #ifdef ASM_OUTPUT_CASE_LABEL
8422 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8425 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8428 for (idx = 0; idx < vlen; idx++)
8430 ASM_OUTPUT_ADDR_VEC_ELT
8431 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8434 #ifdef ASM_OUTPUT_ADDR_VEC_END
8435 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8440 sparc_output_addr_diff_vec (rtx vec)
8442 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8443 rtx base = XEXP (XEXP (body, 0), 0);
8444 int idx, vlen = XVECLEN (body, 1);
8446 #ifdef ASM_OUTPUT_ADDR_VEC_START
8447 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8450 #ifdef ASM_OUTPUT_CASE_LABEL
8451 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8454 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8457 for (idx = 0; idx < vlen; idx++)
8459 ASM_OUTPUT_ADDR_DIFF_ELT
8462 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8463 CODE_LABEL_NUMBER (base));
8466 #ifdef ASM_OUTPUT_ADDR_VEC_END
8467 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8472 sparc_output_deferred_case_vectors (void)
8477 if (sparc_addr_list == NULL_RTX
8478 && sparc_addr_diff_list == NULL_RTX)
8481 /* Align to cache line in the function's code section. */
8482 function_section (current_function_decl);
8484 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8486 ASM_OUTPUT_ALIGN (asm_out_file, align);
8488 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8489 sparc_output_addr_vec (XEXP (t, 0));
8490 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8491 sparc_output_addr_diff_vec (XEXP (t, 0));
8493 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8496 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8497 unknown. Return 1 if the high bits are zero, -1 if the register is
8500 sparc_check_64 (rtx x, rtx insn)
8502 /* If a register is set only once it is safe to ignore insns this
8503 code does not know how to handle. The loop will either recognize
8504 the single set and return the correct value or fail to recognize
8509 if (GET_CODE (x) != REG)
8512 if (GET_MODE (x) == DImode)
8513 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8515 if (flag_expensive_optimizations
8516 && REG_N_SETS (REGNO (y)) == 1)
8522 insn = get_last_insn_anywhere ();
8527 while ((insn = PREV_INSN (insn)))
8529 switch (GET_CODE (insn))
8542 rtx pat = PATTERN (insn);
8543 if (GET_CODE (pat) != SET)
8545 if (rtx_equal_p (x, SET_DEST (pat)))
8546 return set_extends (insn);
8547 if (y && rtx_equal_p (y, SET_DEST (pat)))
8548 return set_extends (insn);
8549 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8557 /* Returns assembly code to perform a DImode shift using
8558 a 64-bit global or out register on SPARC-V8+. */
8560 sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8562 static char asm_code[60];
8564 /* The scratch register is only required when the destination
8565 register is not a 64-bit global or out register. */
8566 if (which_alternative != 2)
8567 operands[3] = operands[0];
8569 /* We can only shift by constants <= 63. */
8570 if (GET_CODE (operands[2]) == CONST_INT)
8571 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8573 if (GET_CODE (operands[1]) == CONST_INT)
8575 output_asm_insn ("mov\t%1, %3", operands);
8579 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8580 if (sparc_check_64 (operands[1], insn) <= 0)
8581 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8582 output_asm_insn ("or\t%L1, %3, %3", operands);
8585 strcpy(asm_code, opcode);
8587 if (which_alternative != 2)
8588 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8590 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8593 /* Output rtl to increment the profiler label LABELNO
8594 for profiling a function entry. */
8597 sparc_profile_hook (int labelno)
8602 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8603 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8604 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8606 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8609 #ifdef OBJECT_FORMAT_ELF
8611 sparc_elf_asm_named_section (const char *name, unsigned int flags)
8613 if (flags & SECTION_MERGE)
8615 /* entsize cannot be expressed in this section attributes
8617 default_elf_asm_named_section (name, flags);
8621 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8623 if (!(flags & SECTION_DEBUG))
8624 fputs (",#alloc", asm_out_file);
8625 if (flags & SECTION_WRITE)
8626 fputs (",#write", asm_out_file);
8627 if (flags & SECTION_TLS)
8628 fputs (",#tls", asm_out_file);
8629 if (flags & SECTION_CODE)
8630 fputs (",#execinstr", asm_out_file);
8632 /* ??? Handle SECTION_BSS. */
8634 fputc ('\n', asm_out_file);
8636 #endif /* OBJECT_FORMAT_ELF */
8638 /* We do not allow sibling calls if -mflat, nor
8639 we do not allow indirect calls to be optimized into sibling calls.
8641 Also, on sparc 32-bit we cannot emit a sibling call when the
8642 current function returns a structure. This is because the "unimp
8643 after call" convention would cause the callee to return to the
8644 wrong place. The generic code already disallows cases where the
8645 function being called returns a structure.
8647 It may seem strange how this last case could occur. Usually there
8648 is code after the call which jumps to epilogue code which dumps the
8649 return value into the struct return area. That ought to invalidate
8650 the sibling call right? Well, in the c++ case we can end up passing
8651 the pointer to the struct return area to a constructor (which returns
8652 void) and then nothing else happens. Such a sibling call would look
8653 valid without the added check here. */
8655 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8659 && (TARGET_ARCH64 || ! current_function_returns_struct));
8662 /* libfunc renaming. */
8663 #include "config/gofast.h"
8666 sparc_init_libfuncs (void)
8670 /* Use the subroutines that Sun's library provides for integer
8671 multiply and divide. The `*' prevents an underscore from
8672 being prepended by the compiler. .umul is a little faster
8674 set_optab_libfunc (smul_optab, SImode, "*.umul");
8675 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8676 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8677 set_optab_libfunc (smod_optab, SImode, "*.rem");
8678 set_optab_libfunc (umod_optab, SImode, "*.urem");
8680 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8681 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8682 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8683 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8684 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8685 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8687 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8688 is because with soft-float, the SFmode and DFmode sqrt
8689 instructions will be absent, and the compiler will notice and
8690 try to use the TFmode sqrt instruction for calls to the
8691 builtin function sqrt, but this fails. */
8693 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8695 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8696 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8697 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8698 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8699 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8700 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8702 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8703 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8704 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8705 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8707 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8708 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8709 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8711 if (SUN_CONVERSION_LIBFUNCS)
8713 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8714 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8715 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8716 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8721 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8722 do not exist in the library. Make sure the compiler does not
8723 emit calls to them by accident. (It should always use the
8724 hardware instructions.) */
8725 set_optab_libfunc (smul_optab, SImode, 0);
8726 set_optab_libfunc (sdiv_optab, SImode, 0);
8727 set_optab_libfunc (udiv_optab, SImode, 0);
8728 set_optab_libfunc (smod_optab, SImode, 0);
8729 set_optab_libfunc (umod_optab, SImode, 0);
8731 if (SUN_INTEGER_MULTIPLY_64)
8733 set_optab_libfunc (smul_optab, DImode, "__mul64");
8734 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8735 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8736 set_optab_libfunc (smod_optab, DImode, "__rem64");
8737 set_optab_libfunc (umod_optab, DImode, "__urem64");
8740 if (SUN_CONVERSION_LIBFUNCS)
8742 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8743 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8744 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8745 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8749 gofast_maybe_init_libfuncs ();
8752 /* ??? Similar to the standard section selection, but force reloc-y-ness
8753 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8754 pretending PIC always on), but that's what the old code did. */
8757 sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align)
8759 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
8762 /* Use text section for a constant unless we need more alignment than
8766 sparc_aout_select_rtx_section (enum machine_mode mode, rtx x,
8767 unsigned HOST_WIDE_INT align)
8769 if (align <= MAX_TEXT_ALIGN
8770 && ! (flag_pic && (symbolic_operand (x, mode)
8771 || SUNOS4_SHARED_LIBRARIES)))
8772 readonly_data_section ();
8778 sparc_extra_constraint_check (rtx op, int c, int strict)
8783 && (c == 'T' || c == 'U'))
8789 return fp_sethi_p (op);
8792 return fp_mov_p (op);
8795 return fp_high_losum_p (op);
8799 || (GET_CODE (op) == REG
8800 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8801 || reg_renumber[REGNO (op)] >= 0)))
8802 return register_ok_for_ldd (op);
8814 /* Our memory extra constraints have to emulate the
8815 behavior of 'm' and 'o' in order for reload to work
8817 if (GET_CODE (op) == MEM)
8820 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8822 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8827 reload_ok_mem = (reload_in_progress
8828 && GET_CODE (op) == REG
8829 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8830 && reg_renumber [REGNO (op)] < 0);
8833 return reload_ok_mem;
8836 /* ??? This duplicates information provided to the compiler by the
8837 ??? scheduler description. Some day, teach genautomata to output
8838 ??? the latencies and then CSE will just use that. */
8841 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8845 case PLUS: case MINUS: case ABS: case NEG:
8846 case FLOAT: case UNSIGNED_FLOAT:
8847 case FIX: case UNSIGNED_FIX:
8848 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8849 if (FLOAT_MODE_P (GET_MODE (x)))
8853 case PROCESSOR_ULTRASPARC:
8854 case PROCESSOR_ULTRASPARC3:
8855 *total = COSTS_N_INSNS (4);
8858 case PROCESSOR_SUPERSPARC:
8859 *total = COSTS_N_INSNS (3);
8862 case PROCESSOR_CYPRESS:
8863 *total = COSTS_N_INSNS (5);
8866 case PROCESSOR_HYPERSPARC:
8867 case PROCESSOR_SPARCLITE86X:
8869 *total = COSTS_N_INSNS (1);
8874 *total = COSTS_N_INSNS (1);
8880 case PROCESSOR_ULTRASPARC:
8881 if (GET_MODE (x) == SFmode)
8882 *total = COSTS_N_INSNS (13);
8884 *total = COSTS_N_INSNS (23);
8887 case PROCESSOR_ULTRASPARC3:
8888 if (GET_MODE (x) == SFmode)
8889 *total = COSTS_N_INSNS (20);
8891 *total = COSTS_N_INSNS (29);
8894 case PROCESSOR_SUPERSPARC:
8895 *total = COSTS_N_INSNS (12);
8898 case PROCESSOR_CYPRESS:
8899 *total = COSTS_N_INSNS (63);
8902 case PROCESSOR_HYPERSPARC:
8903 case PROCESSOR_SPARCLITE86X:
8904 *total = COSTS_N_INSNS (17);
8908 *total = COSTS_N_INSNS (30);
8913 if (FLOAT_MODE_P (GET_MODE (x)))
8917 case PROCESSOR_ULTRASPARC:
8918 case PROCESSOR_ULTRASPARC3:
8919 *total = COSTS_N_INSNS (1);
8922 case PROCESSOR_SUPERSPARC:
8923 *total = COSTS_N_INSNS (3);
8926 case PROCESSOR_CYPRESS:
8927 *total = COSTS_N_INSNS (5);
8930 case PROCESSOR_HYPERSPARC:
8931 case PROCESSOR_SPARCLITE86X:
8933 *total = COSTS_N_INSNS (1);
8938 /* ??? Maybe mark integer compares as zero cost on
8939 ??? all UltraSPARC processors because the result
8940 ??? can be bypassed to a branch in the same group. */
8942 *total = COSTS_N_INSNS (1);
8946 if (FLOAT_MODE_P (GET_MODE (x)))
8950 case PROCESSOR_ULTRASPARC:
8951 case PROCESSOR_ULTRASPARC3:
8952 *total = COSTS_N_INSNS (4);
8955 case PROCESSOR_SUPERSPARC:
8956 *total = COSTS_N_INSNS (3);
8959 case PROCESSOR_CYPRESS:
8960 *total = COSTS_N_INSNS (7);
8963 case PROCESSOR_HYPERSPARC:
8964 case PROCESSOR_SPARCLITE86X:
8965 *total = COSTS_N_INSNS (1);
8969 *total = COSTS_N_INSNS (5);
8974 /* The latency is actually variable for Ultra-I/II
8975 And if one of the inputs have a known constant
8976 value, we could calculate this precisely.
8978 However, for that to be useful we would need to
8979 add some machine description changes which would
8980 make sure small constants ended up in rs1 of the
8981 multiply instruction. This is because the multiply
8982 latency is determined by the number of clear (or
8983 set if the value is negative) bits starting from
8984 the most significant bit of the first input.
8986 The algorithm for computing num_cycles of a multiply
8990 highest_bit = highest_clear_bit(rs1);
8992 highest_bit = highest_set_bit(rs1);
8995 num_cycles = 4 + ((highest_bit - 3) / 2);
8997 If we did that we would have to also consider register
8998 allocation issues that would result from forcing such
8999 a value into a register.
9001 There are other similar tricks we could play if we
9002 knew, for example, that one input was an array index.
9004 Since we do not play any such tricks currently the
9005 safest thing to do is report the worst case latency. */
9006 if (sparc_cpu == PROCESSOR_ULTRASPARC)
9008 *total = (GET_MODE (x) == DImode
9009 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
9013 /* Multiply latency on Ultra-III, fortunately, is constant. */
9014 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
9016 *total = COSTS_N_INSNS (6);
9020 if (sparc_cpu == PROCESSOR_HYPERSPARC
9021 || sparc_cpu == PROCESSOR_SPARCLITE86X)
9023 *total = COSTS_N_INSNS (17);
9027 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
9034 if (FLOAT_MODE_P (GET_MODE (x)))
9038 case PROCESSOR_ULTRASPARC:
9039 if (GET_MODE (x) == SFmode)
9040 *total = COSTS_N_INSNS (13);
9042 *total = COSTS_N_INSNS (23);
9045 case PROCESSOR_ULTRASPARC3:
9046 if (GET_MODE (x) == SFmode)
9047 *total = COSTS_N_INSNS (17);
9049 *total = COSTS_N_INSNS (20);
9052 case PROCESSOR_SUPERSPARC:
9053 if (GET_MODE (x) == SFmode)
9054 *total = COSTS_N_INSNS (6);
9056 *total = COSTS_N_INSNS (9);
9059 case PROCESSOR_HYPERSPARC:
9060 case PROCESSOR_SPARCLITE86X:
9061 if (GET_MODE (x) == SFmode)
9062 *total = COSTS_N_INSNS (8);
9064 *total = COSTS_N_INSNS (12);
9068 *total = COSTS_N_INSNS (7);
9073 if (sparc_cpu == PROCESSOR_ULTRASPARC)
9074 *total = (GET_MODE (x) == DImode
9075 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
9076 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
9077 *total = (GET_MODE (x) == DImode
9078 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
9080 *total = COSTS_N_INSNS (25);
9084 /* Conditional moves. */
9087 case PROCESSOR_ULTRASPARC:
9088 *total = COSTS_N_INSNS (2);
9091 case PROCESSOR_ULTRASPARC3:
9092 if (FLOAT_MODE_P (GET_MODE (x)))
9093 *total = COSTS_N_INSNS (3);
9095 *total = COSTS_N_INSNS (2);
9099 *total = COSTS_N_INSNS (1);
9104 /* If outer-code is SIGN/ZERO extension we have to subtract
9105 out COSTS_N_INSNS (1) from whatever we return in determining
9109 case PROCESSOR_ULTRASPARC:
9110 if (outer_code == ZERO_EXTEND)
9111 *total = COSTS_N_INSNS (1);
9113 *total = COSTS_N_INSNS (2);
9116 case PROCESSOR_ULTRASPARC3:
9117 if (outer_code == ZERO_EXTEND)
9119 if (GET_MODE (x) == QImode
9120 || GET_MODE (x) == HImode
9121 || outer_code == SIGN_EXTEND)
9122 *total = COSTS_N_INSNS (2);
9124 *total = COSTS_N_INSNS (1);
9128 /* This handles sign extension (3 cycles)
9129 and everything else (2 cycles). */
9130 *total = COSTS_N_INSNS (2);
9134 case PROCESSOR_SUPERSPARC:
9135 if (FLOAT_MODE_P (GET_MODE (x))
9136 || outer_code == ZERO_EXTEND
9137 || outer_code == SIGN_EXTEND)
9138 *total = COSTS_N_INSNS (0);
9140 *total = COSTS_N_INSNS (1);
9143 case PROCESSOR_TSC701:
9144 if (outer_code == ZERO_EXTEND
9145 || outer_code == SIGN_EXTEND)
9146 *total = COSTS_N_INSNS (2);
9148 *total = COSTS_N_INSNS (3);
9151 case PROCESSOR_CYPRESS:
9152 if (outer_code == ZERO_EXTEND
9153 || outer_code == SIGN_EXTEND)
9154 *total = COSTS_N_INSNS (1);
9156 *total = COSTS_N_INSNS (2);
9159 case PROCESSOR_HYPERSPARC:
9160 case PROCESSOR_SPARCLITE86X:
9162 if (outer_code == ZERO_EXTEND
9163 || outer_code == SIGN_EXTEND)
9164 *total = COSTS_N_INSNS (0);
9166 *total = COSTS_N_INSNS (1);
9171 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
9189 if (GET_MODE (x) == DImode
9190 && ((XINT (x, 3) == 0
9191 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
9192 || (XINT (x, 3) == -1
9194 && XINT (x, 2) >= -0x1000)))
9205 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
9206 Used for C++ multiple inheritance. */
9209 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
9210 HOST_WIDE_INT delta,
9211 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
9214 rtx this, insn, funexp, delta_rtx, tmp;
9216 reload_completed = 1;
9217 epilogue_completed = 1;
9219 current_function_uses_only_leaf_regs = 1;
9221 emit_note (NOTE_INSN_PROLOGUE_END);
9223 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
9224 returns a structure, the structure return pointer is there instead. */
9225 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9226 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
9228 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
9230 /* Add DELTA. When possible use a plain add, otherwise load it into
9231 a register first. */
9232 delta_rtx = GEN_INT (delta);
9233 if (!SPARC_SIMM13_P (delta))
9235 rtx scratch = gen_rtx_REG (Pmode, 1);
9237 if (input_operand (delta_rtx, GET_MODE (scratch)))
9238 emit_insn (gen_rtx_SET (VOIDmode, scratch, delta_rtx));
9242 sparc_emit_set_const64 (scratch, delta_rtx);
9244 sparc_emit_set_const32 (scratch, delta_rtx);
9247 delta_rtx = scratch;
9250 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
9251 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
9253 /* Generate a tail call to the target function. */
9254 if (! TREE_USED (function))
9256 assemble_external (function);
9257 TREE_USED (function) = 1;
9259 funexp = XEXP (DECL_RTL (function), 0);
9260 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
9261 insn = emit_call_insn (gen_sibcall (funexp));
9262 SIBLING_CALL_P (insn) = 1;
9265 /* Run just enough of rest_of_compilation to get the insns emitted.
9266 There's not really enough bulk here to make other passes such as
9267 instruction scheduling worth while. Note that use_thunk calls
9268 assemble_start_function and assemble_end_function. */
9269 insn = get_insns ();
9270 insn_locators_initialize ();
9271 shorten_branches (insn);
9272 final_start_function (insn, file, 1);
9273 final (insn, file, 1, 0);
9274 final_end_function ();
9276 reload_completed = 0;
9277 epilogue_completed = 0;
9281 /* How to allocate a 'struct machine_function'. */
9283 static struct machine_function *
9284 sparc_init_machine_status (void)
9286 return ggc_alloc_cleared (sizeof (struct machine_function));
9289 /* Locate some local-dynamic symbol still in use by this function
9290 so that we can print its name in local-dynamic base patterns. */
9293 get_some_local_dynamic_name (void)
9297 if (cfun->machine->some_ld_name)
9298 return cfun->machine->some_ld_name;
9300 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9302 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
9303 return cfun->machine->some_ld_name;
9309 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9314 && GET_CODE (x) == SYMBOL_REF
9315 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9317 cfun->machine->some_ld_name = XSTR (x, 0);
9324 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
9325 We need to emit DTP-relative relocations. */
9328 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
9333 fputs ("\t.word\t%r_tls_dtpoff32(", file);
9336 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
9341 output_addr_const (file, x);
9345 #include "gt-sparc.h"