1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
49 #include "target-def.h"
50 #include "cfglayout.h"
52 /* 1 if the caller has placed an "unimp" insn immediately after the call.
53 This is used in v8 code when calling a function that returns a structure.
54 v9 doesn't have this. Be careful to have this test be the same as that
57 #define SKIP_CALLERS_UNIMP_P \
58 (!TARGET_ARCH64 && current_function_returns_struct \
59 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
60 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
63 /* Global variables for machine-dependent things. */
65 /* Size of frame. Need to know this to emit return insns from leaf procedures.
66 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
67 reload pass. This is important as the value is later used in insn
68 scheduling (to see what can go in a delay slot).
69 APPARENT_FSIZE is the size of the stack less the register save area and less
70 the outgoing argument area. It is used when saving call preserved regs. */
71 static int apparent_fsize;
72 static int actual_fsize;
74 /* Number of live general or floating point registers needed to be
75 saved (as 4-byte quantities). */
76 static int num_gfregs;
78 /* Save the operands last given to a compare for use when we
79 generate a scc or bcc insn. */
80 rtx sparc_compare_op0, sparc_compare_op1;
82 /* Coordinate with the md file wrt special insns created by
83 sparc_nonflat_function_epilogue. */
84 bool sparc_emitting_epilogue;
86 /* Vector to say how input registers are mapped to output registers.
87 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
88 eliminate it. You must use -fomit-frame-pointer to get that. */
89 char leaf_reg_remap[] =
90 { 0, 1, 2, 3, 4, 5, 6, 7,
91 -1, -1, -1, -1, -1, -1, 14, -1,
92 -1, -1, -1, -1, -1, -1, -1, -1,
93 8, 9, 10, 11, 12, 13, -1, 15,
95 32, 33, 34, 35, 36, 37, 38, 39,
96 40, 41, 42, 43, 44, 45, 46, 47,
97 48, 49, 50, 51, 52, 53, 54, 55,
98 56, 57, 58, 59, 60, 61, 62, 63,
99 64, 65, 66, 67, 68, 69, 70, 71,
100 72, 73, 74, 75, 76, 77, 78, 79,
101 80, 81, 82, 83, 84, 85, 86, 87,
102 88, 89, 90, 91, 92, 93, 94, 95,
103 96, 97, 98, 99, 100};
105 /* Vector, indexed by hard register number, which contains 1
106 for a register that is allowable in a candidate for leaf
107 function treatment. */
108 char sparc_leaf_regs[] =
109 { 1, 1, 1, 1, 1, 1, 1, 1,
110 0, 0, 0, 0, 0, 0, 1, 0,
111 0, 0, 0, 0, 0, 0, 0, 0,
112 1, 1, 1, 1, 1, 1, 0, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
120 1, 1, 1, 1, 1, 1, 1, 1,
123 /* Name of where we pretend to think the frame pointer points.
124 Normally, this is "%fp", but if we are in a leaf procedure,
125 this is "%sp+something". We record "something" separately as it may be
126 too big for reg+constant addressing. */
128 static const char *frame_base_name;
129 static int frame_base_offset;
131 static void sparc_init_modes (void);
132 static int save_regs (FILE *, int, int, const char *, int, int, int);
133 static int restore_regs (FILE *, int, int, const char *, int, int);
134 static void build_big_number (FILE *, int, const char *);
135 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
136 tree, int, int, int *, int *);
138 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
139 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
141 static void sparc_output_addr_vec (rtx);
142 static void sparc_output_addr_diff_vec (rtx);
143 static void sparc_output_deferred_case_vectors (void);
144 static int check_return_regs (rtx);
145 static int epilogue_renumber (rtx *, int);
146 static bool sparc_assemble_integer (rtx, unsigned int, int);
147 static int set_extends (rtx);
148 static void output_restore_regs (FILE *, int);
149 static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT);
150 static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT);
151 static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT);
152 static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT);
153 static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int);
154 static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int);
155 #ifdef OBJECT_FORMAT_ELF
156 static void sparc_elf_asm_named_section (const char *, unsigned int);
158 static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT)
160 static void sparc_aout_select_rtx_section (enum machine_mode, rtx,
161 unsigned HOST_WIDE_INT)
164 static int sparc_adjust_cost (rtx, rtx, rtx, int);
165 static int sparc_issue_rate (void);
166 static void sparc_sched_init (FILE *, int, int);
167 static int sparc_use_dfa_pipeline_interface (void);
168 static int sparc_use_sched_lookahead (void);
170 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
171 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
172 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
173 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
174 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
176 static bool sparc_function_ok_for_sibcall (tree, tree);
177 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
178 HOST_WIDE_INT, tree);
179 static bool sparc_rtx_costs (rtx, int, int, int *);
181 /* Option handling. */
183 /* Code model option as passed by user. */
184 const char *sparc_cmodel_string;
186 enum cmodel sparc_cmodel;
188 char sparc_hard_reg_printed[8];
190 struct sparc_cpu_select sparc_select[] =
192 /* switch name, tune arch */
193 { (char *)0, "default", 1, 1 },
194 { (char *)0, "-mcpu=", 1, 1 },
195 { (char *)0, "-mtune=", 1, 0 },
199 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
200 enum processor_type sparc_cpu;
202 /* Initialize the GCC target structure. */
204 /* The sparc default is to use .half rather than .short for aligned
205 HI objects. Use .word instead of .long on non-ELF systems. */
206 #undef TARGET_ASM_ALIGNED_HI_OP
207 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
208 #ifndef OBJECT_FORMAT_ELF
209 #undef TARGET_ASM_ALIGNED_SI_OP
210 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
213 #undef TARGET_ASM_UNALIGNED_HI_OP
214 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
215 #undef TARGET_ASM_UNALIGNED_SI_OP
216 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
217 #undef TARGET_ASM_UNALIGNED_DI_OP
218 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
220 /* The target hook has to handle DI-mode values. */
221 #undef TARGET_ASM_INTEGER
222 #define TARGET_ASM_INTEGER sparc_assemble_integer
224 #undef TARGET_ASM_FUNCTION_PROLOGUE
225 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
226 #undef TARGET_ASM_FUNCTION_EPILOGUE
227 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
229 #undef TARGET_SCHED_ADJUST_COST
230 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
231 #undef TARGET_SCHED_ISSUE_RATE
232 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
233 #undef TARGET_SCHED_INIT
234 #define TARGET_SCHED_INIT sparc_sched_init
235 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
236 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
237 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
238 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
240 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
241 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
243 #undef TARGET_ASM_OUTPUT_MI_THUNK
244 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
245 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
246 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
248 #undef TARGET_RTX_COSTS
249 #define TARGET_RTX_COSTS sparc_rtx_costs
250 #undef TARGET_ADDRESS_COST
251 #define TARGET_ADDRESS_COST hook_int_rtx_0
253 struct gcc_target targetm = TARGET_INITIALIZER;
255 /* Validate and override various options, and do some machine dependent
259 sparc_override_options ()
261 static struct code_model {
262 const char *const name;
264 } const cmodels[] = {
266 { "medlow", CM_MEDLOW },
267 { "medmid", CM_MEDMID },
268 { "medany", CM_MEDANY },
269 { "embmedany", CM_EMBMEDANY },
272 const struct code_model *cmodel;
273 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
274 static struct cpu_default {
276 const char *const name;
277 } const cpu_default[] = {
278 /* There must be one entry here for each TARGET_CPU value. */
279 { TARGET_CPU_sparc, "cypress" },
280 { TARGET_CPU_sparclet, "tsc701" },
281 { TARGET_CPU_sparclite, "f930" },
282 { TARGET_CPU_v8, "v8" },
283 { TARGET_CPU_hypersparc, "hypersparc" },
284 { TARGET_CPU_sparclite86x, "sparclite86x" },
285 { TARGET_CPU_supersparc, "supersparc" },
286 { TARGET_CPU_v9, "v9" },
287 { TARGET_CPU_ultrasparc, "ultrasparc" },
288 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
291 const struct cpu_default *def;
292 /* Table of values for -m{cpu,tune}=. */
293 static struct cpu_table {
294 const char *const name;
295 const enum processor_type processor;
298 } const cpu_table[] = {
299 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
300 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
301 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
302 /* TI TMS390Z55 supersparc */
303 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
304 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
305 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
306 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
307 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
308 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
309 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
310 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
312 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
314 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
315 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
316 /* TI ultrasparc I, II, IIi */
317 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
318 /* Although insns using %y are deprecated, it is a clear win on current
320 |MASK_DEPRECATED_V8_INSNS},
321 /* TI ultrasparc III */
322 /* ??? Check if %y issue still holds true in ultra3. */
323 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
326 const struct cpu_table *cpu;
327 const struct sparc_cpu_select *sel;
330 #ifndef SPARC_BI_ARCH
331 /* Check for unsupported architecture size. */
332 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
333 error ("%s is not supported by this configuration",
334 DEFAULT_ARCH32_P ? "-m64" : "-m32");
337 /* We force all 64bit archs to use 128 bit long double */
338 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
340 error ("-mlong-double-64 not allowed with -m64");
341 target_flags |= MASK_LONG_DOUBLE_128;
344 /* Code model selection. */
345 sparc_cmodel = SPARC_DEFAULT_CMODEL;
349 sparc_cmodel = CM_32;
352 if (sparc_cmodel_string != NULL)
356 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
357 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
359 if (cmodel->name == NULL)
360 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
362 sparc_cmodel = cmodel->value;
365 error ("-mcmodel= is not supported on 32 bit systems");
368 fpu = TARGET_FPU; /* save current -mfpu status */
370 /* Set the default CPU. */
371 for (def = &cpu_default[0]; def->name; ++def)
372 if (def->cpu == TARGET_CPU_DEFAULT)
376 sparc_select[0].string = def->name;
378 for (sel = &sparc_select[0]; sel->name; ++sel)
382 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
383 if (! strcmp (sel->string, cpu->name))
386 sparc_cpu = cpu->processor;
390 target_flags &= ~cpu->disable;
391 target_flags |= cpu->enable;
397 error ("bad value (%s) for %s switch", sel->string, sel->name);
401 /* If -mfpu or -mno-fpu was explicitly used, don't override with
402 the processor default. Clear MASK_FPU_SET to avoid confusing
403 the reverse mapping from switch values to names. */
406 target_flags = (target_flags & ~MASK_FPU) | fpu;
407 target_flags &= ~MASK_FPU_SET;
410 /* Don't allow -mvis if FPU is disabled. */
412 target_flags &= ~MASK_VIS;
414 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
416 -m64 also implies v9. */
417 if (TARGET_VIS || TARGET_ARCH64)
419 target_flags |= MASK_V9;
420 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
423 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
424 if (TARGET_V9 && TARGET_ARCH32)
425 target_flags |= MASK_DEPRECATED_V8_INSNS;
427 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
428 if (! TARGET_V9 || TARGET_ARCH64)
429 target_flags &= ~MASK_V8PLUS;
431 /* Don't use stack biasing in 32 bit mode. */
433 target_flags &= ~MASK_STACK_BIAS;
435 /* Supply a default value for align_functions. */
436 if (align_functions == 0
437 && (sparc_cpu == PROCESSOR_ULTRASPARC
438 || sparc_cpu == PROCESSOR_ULTRASPARC3))
439 align_functions = 32;
441 /* Validate PCC_STRUCT_RETURN. */
442 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
443 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
445 /* Only use .uaxword when compiling for a 64-bit target. */
447 targetm.asm_out.unaligned_op.di = NULL;
449 /* Do various machine dependent initializations. */
453 /* Miscellaneous utilities. */
455 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
456 or branch on register contents instructions. */
462 return (code == EQ || code == NE || code == GE || code == LT
463 || code == LE || code == GT);
467 /* Operand constraints. */
469 /* Return nonzero only if OP is a register of mode MODE,
473 reg_or_0_operand (op, mode)
475 enum machine_mode mode;
477 if (register_operand (op, mode))
479 if (op == const0_rtx)
481 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
482 && CONST_DOUBLE_HIGH (op) == 0
483 && CONST_DOUBLE_LOW (op) == 0)
485 if (fp_zero_operand (op, mode))
490 /* Return nonzero only if OP is const1_rtx. */
493 const1_operand (op, mode)
495 enum machine_mode mode ATTRIBUTE_UNUSED;
497 return op == const1_rtx;
500 /* Nonzero if OP is a floating point value with value 0.0. */
503 fp_zero_operand (op, mode)
505 enum machine_mode mode;
507 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
509 return op == CONST0_RTX (mode);
512 /* Nonzero if OP is a register operand in floating point register. */
515 fp_register_operand (op, mode)
517 enum machine_mode mode;
519 if (! register_operand (op, mode))
521 if (GET_CODE (op) == SUBREG)
522 op = SUBREG_REG (op);
523 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
526 /* Nonzero if OP is a floating point constant which can
527 be loaded into an integer register using a single
528 sethi instruction. */
534 if (GET_CODE (op) == CONST_DOUBLE)
539 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
540 if (REAL_VALUES_EQUAL (r, dconst0) &&
541 ! REAL_VALUE_MINUS_ZERO (r))
543 REAL_VALUE_TO_TARGET_SINGLE (r, i);
544 if (SPARC_SETHI_P (i))
551 /* Nonzero if OP is a floating point constant which can
552 be loaded into an integer register using a single
559 if (GET_CODE (op) == CONST_DOUBLE)
564 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
565 if (REAL_VALUES_EQUAL (r, dconst0) &&
566 ! REAL_VALUE_MINUS_ZERO (r))
568 REAL_VALUE_TO_TARGET_SINGLE (r, i);
569 if (SPARC_SIMM13_P (i))
576 /* Nonzero if OP is a floating point constant which can
577 be loaded into an integer register using a high/losum
578 instruction sequence. */
584 /* The constraints calling this should only be in
585 SFmode move insns, so any constant which cannot
586 be moved using a single insn will do. */
587 if (GET_CODE (op) == CONST_DOUBLE)
592 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
593 if (REAL_VALUES_EQUAL (r, dconst0) &&
594 ! REAL_VALUE_MINUS_ZERO (r))
596 REAL_VALUE_TO_TARGET_SINGLE (r, i);
597 if (! SPARC_SETHI_P (i)
598 && ! SPARC_SIMM13_P (i))
605 /* Nonzero if OP is an integer register. */
608 intreg_operand (op, mode)
610 enum machine_mode mode ATTRIBUTE_UNUSED;
612 return (register_operand (op, SImode)
613 || (TARGET_ARCH64 && register_operand (op, DImode)));
616 /* Nonzero if OP is a floating point condition code register. */
619 fcc_reg_operand (op, mode)
621 enum machine_mode mode;
623 /* This can happen when recog is called from combine. Op may be a MEM.
624 Fail instead of calling abort in this case. */
625 if (GET_CODE (op) != REG)
628 if (mode != VOIDmode && mode != GET_MODE (op))
631 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
634 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
635 if (reg_renumber == 0)
636 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
637 return REGNO_OK_FOR_CCFP_P (REGNO (op));
639 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
643 /* Nonzero if OP is a floating point condition code fcc0 register. */
646 fcc0_reg_operand (op, mode)
648 enum machine_mode mode;
650 /* This can happen when recog is called from combine. Op may be a MEM.
651 Fail instead of calling abort in this case. */
652 if (GET_CODE (op) != REG)
655 if (mode != VOIDmode && mode != GET_MODE (op))
658 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
661 return REGNO (op) == SPARC_FCC_REG;
664 /* Nonzero if OP is an integer or floating point condition code register. */
667 icc_or_fcc_reg_operand (op, mode)
669 enum machine_mode mode;
671 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
673 if (mode != VOIDmode && mode != GET_MODE (op))
676 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
681 return fcc_reg_operand (op, mode);
684 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
686 restore_operand (op, mode)
688 enum machine_mode mode;
690 return (GET_CODE (op) == REG && GET_MODE (op) == mode
691 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
694 /* Call insn on SPARC can take a PC-relative constant address, or any regular
698 call_operand (op, mode)
700 enum machine_mode mode;
702 if (GET_CODE (op) != MEM)
705 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
709 call_operand_address (op, mode)
711 enum machine_mode mode;
713 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
716 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
717 reference and a constant. */
720 symbolic_operand (op, mode)
722 enum machine_mode mode;
724 enum machine_mode omode = GET_MODE (op);
726 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
729 switch (GET_CODE (op))
737 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
738 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
739 && GET_CODE (XEXP (op, 1)) == CONST_INT);
746 /* Return truth value of statement that OP is a symbolic memory
747 operand of mode MODE. */
750 symbolic_memory_operand (op, mode)
752 enum machine_mode mode ATTRIBUTE_UNUSED;
754 if (GET_CODE (op) == SUBREG)
755 op = SUBREG_REG (op);
756 if (GET_CODE (op) != MEM)
759 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
760 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
763 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
766 label_ref_operand (op, mode)
768 enum machine_mode mode;
770 if (GET_CODE (op) != LABEL_REF)
772 if (GET_MODE (op) != mode)
777 /* Return 1 if the operand is an argument used in generating pic references
778 in either the medium/low or medium/anywhere code models of sparc64. */
781 sp64_medium_pic_operand (op, mode)
783 enum machine_mode mode ATTRIBUTE_UNUSED;
785 /* Check for (const (minus (symbol_ref:GOT)
786 (const (minus (label) (pc))))). */
787 if (GET_CODE (op) != CONST)
790 if (GET_CODE (op) != MINUS)
792 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
794 /* ??? Ensure symbol is GOT. */
795 if (GET_CODE (XEXP (op, 1)) != CONST)
797 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
802 /* Return 1 if the operand is a data segment reference. This includes
803 the readonly data segment, or in other words anything but the text segment.
804 This is needed in the medium/anywhere code model on v9. These values
805 are accessed with EMBMEDANY_BASE_REG. */
808 data_segment_operand (op, mode)
810 enum machine_mode mode ATTRIBUTE_UNUSED;
812 switch (GET_CODE (op))
815 return ! SYMBOL_REF_FUNCTION_P (op);
817 /* Assume canonical format of symbol + constant.
820 return data_segment_operand (XEXP (op, 0), VOIDmode);
826 /* Return 1 if the operand is a text segment reference.
827 This is needed in the medium/anywhere code model on v9. */
830 text_segment_operand (op, mode)
832 enum machine_mode mode ATTRIBUTE_UNUSED;
834 switch (GET_CODE (op))
839 return SYMBOL_REF_FUNCTION_P (op);
841 /* Assume canonical format of symbol + constant.
844 return text_segment_operand (XEXP (op, 0), VOIDmode);
850 /* Return 1 if the operand is either a register or a memory operand that is
854 reg_or_nonsymb_mem_operand (op, mode)
856 enum machine_mode mode;
858 if (register_operand (op, mode))
861 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
868 splittable_symbolic_memory_operand (op, mode)
870 enum machine_mode mode ATTRIBUTE_UNUSED;
872 if (GET_CODE (op) != MEM)
874 if (! symbolic_operand (XEXP (op, 0), Pmode))
880 splittable_immediate_memory_operand (op, mode)
882 enum machine_mode mode ATTRIBUTE_UNUSED;
884 if (GET_CODE (op) != MEM)
886 if (! immediate_operand (XEXP (op, 0), Pmode))
891 /* Return truth value of whether OP is EQ or NE. */
896 enum machine_mode mode ATTRIBUTE_UNUSED;
898 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
901 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
902 or LTU for non-floating-point. We handle those specially. */
905 normal_comp_operator (op, mode)
907 enum machine_mode mode ATTRIBUTE_UNUSED;
909 enum rtx_code code = GET_CODE (op);
911 if (GET_RTX_CLASS (code) != '<')
914 if (GET_MODE (XEXP (op, 0)) == CCFPmode
915 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
918 return (code != NE && code != EQ && code != GEU && code != LTU);
921 /* Return 1 if this is a comparison operator. This allows the use of
922 MATCH_OPERATOR to recognize all the branch insns. */
925 noov_compare_op (op, mode)
927 enum machine_mode mode ATTRIBUTE_UNUSED;
929 enum rtx_code code = GET_CODE (op);
931 if (GET_RTX_CLASS (code) != '<')
934 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
935 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
936 /* These are the only branches which work with CC_NOOVmode. */
937 return (code == EQ || code == NE || code == GE || code == LT);
941 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
942 MATCH_OPERATOR to recognize all the branch insns. */
945 noov_compare64_op (op, mode)
947 enum machine_mode mode ATTRIBUTE_UNUSED;
949 enum rtx_code code = GET_CODE (op);
954 if (GET_RTX_CLASS (code) != '<')
957 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
958 /* These are the only branches which work with CCX_NOOVmode. */
959 return (code == EQ || code == NE || code == GE || code == LT);
960 return (GET_MODE (XEXP (op, 0)) == CCXmode);
963 /* Nonzero if OP is a comparison operator suitable for use in v9
964 conditional move or branch on register contents instructions. */
967 v9_regcmp_op (op, mode)
969 enum machine_mode mode ATTRIBUTE_UNUSED;
971 enum rtx_code code = GET_CODE (op);
973 if (GET_RTX_CLASS (code) != '<')
976 return v9_regcmp_p (code);
979 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
984 enum machine_mode mode ATTRIBUTE_UNUSED;
986 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
989 /* Return nonzero if OP is an operator of mode MODE which can set
990 the condition codes explicitly. We do not include PLUS and MINUS
991 because these require CC_NOOVmode, which we handle explicitly. */
994 cc_arithop (op, mode)
996 enum machine_mode mode ATTRIBUTE_UNUSED;
998 if (GET_CODE (op) == AND
999 || GET_CODE (op) == IOR
1000 || GET_CODE (op) == XOR)
1006 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1007 complement its second operand and set the condition codes explicitly. */
1010 cc_arithopn (op, mode)
1012 enum machine_mode mode ATTRIBUTE_UNUSED;
1014 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1015 and (xor ... (not ...)) to (not (xor ...)). */
1016 return (GET_CODE (op) == AND
1017 || GET_CODE (op) == IOR);
1020 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1021 signed 13 bit immediate field. This is an acceptable SImode operand for
1022 most 3 address instructions. */
1025 arith_operand (op, mode)
1027 enum machine_mode mode;
1029 if (register_operand (op, mode))
1031 if (GET_CODE (op) != CONST_INT)
1033 return SMALL_INT32 (op);
1036 /* Return true if OP is a constant 4096 */
1039 arith_4096_operand (op, mode)
1041 enum machine_mode mode ATTRIBUTE_UNUSED;
1043 if (GET_CODE (op) != CONST_INT)
1046 return INTVAL (op) == 4096;
1049 /* Return true if OP is suitable as second operand for add/sub */
1052 arith_add_operand (op, mode)
1054 enum machine_mode mode;
1056 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1059 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1060 immediate field of OR and XOR instructions. Used for 64-bit
1061 constant formation patterns. */
1063 const64_operand (op, mode)
1065 enum machine_mode mode ATTRIBUTE_UNUSED;
1067 return ((GET_CODE (op) == CONST_INT
1068 && SPARC_SIMM13_P (INTVAL (op)))
1069 #if HOST_BITS_PER_WIDE_INT != 64
1070 || (GET_CODE (op) == CONST_DOUBLE
1071 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1072 && (CONST_DOUBLE_HIGH (op) ==
1073 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1074 (HOST_WIDE_INT)-1 : 0)))
1079 /* The same, but only for sethi instructions. */
1081 const64_high_operand (op, mode)
1083 enum machine_mode mode;
1085 return ((GET_CODE (op) == CONST_INT
1086 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1087 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1089 || (GET_CODE (op) == CONST_DOUBLE
1090 && CONST_DOUBLE_HIGH (op) == 0
1091 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1092 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1095 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1096 signed 11 bit immediate field. This is an acceptable SImode operand for
1097 the movcc instructions. */
1100 arith11_operand (op, mode)
1102 enum machine_mode mode;
1104 return (register_operand (op, mode)
1105 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1108 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1109 signed 10 bit immediate field. This is an acceptable SImode operand for
1110 the movrcc instructions. */
1113 arith10_operand (op, mode)
1115 enum machine_mode mode;
1117 return (register_operand (op, mode)
1118 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1121 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1122 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1124 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1125 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1126 for most 3 address instructions. */
1129 arith_double_operand (op, mode)
1131 enum machine_mode mode;
1133 return (register_operand (op, mode)
1134 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1136 && GET_CODE (op) == CONST_DOUBLE
1137 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1138 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1140 && GET_CODE (op) == CONST_DOUBLE
1141 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1142 && ((CONST_DOUBLE_HIGH (op) == -1
1143 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1144 || (CONST_DOUBLE_HIGH (op) == 0
1145 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1148 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1151 arith_double_4096_operand (op, mode)
1153 enum machine_mode mode ATTRIBUTE_UNUSED;
1155 return (TARGET_ARCH64 &&
1156 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1157 (GET_CODE (op) == CONST_DOUBLE &&
1158 CONST_DOUBLE_LOW (op) == 4096 &&
1159 CONST_DOUBLE_HIGH (op) == 0)));
1162 /* Return true if OP is suitable as second operand for add/sub in DImode */
1165 arith_double_add_operand (op, mode)
1167 enum machine_mode mode;
1169 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1172 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1173 can fit in an 11 bit immediate field. This is an acceptable DImode
1174 operand for the movcc instructions. */
1175 /* ??? Replace with arith11_operand? */
1178 arith11_double_operand (op, mode)
1180 enum machine_mode mode;
1182 return (register_operand (op, mode)
1183 || (GET_CODE (op) == CONST_DOUBLE
1184 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1185 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1186 && ((CONST_DOUBLE_HIGH (op) == -1
1187 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1188 || (CONST_DOUBLE_HIGH (op) == 0
1189 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1190 || (GET_CODE (op) == CONST_INT
1191 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1192 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1195 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1196 can fit in an 10 bit immediate field. This is an acceptable DImode
1197 operand for the movrcc instructions. */
1198 /* ??? Replace with arith10_operand? */
1201 arith10_double_operand (op, mode)
1203 enum machine_mode mode;
1205 return (register_operand (op, mode)
1206 || (GET_CODE (op) == CONST_DOUBLE
1207 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1208 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1209 && ((CONST_DOUBLE_HIGH (op) == -1
1210 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1211 || (CONST_DOUBLE_HIGH (op) == 0
1212 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1213 || (GET_CODE (op) == CONST_INT
1214 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1215 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1218 /* Return truth value of whether OP is an integer which fits the
1219 range constraining immediate operands in most three-address insns,
1220 which have a 13 bit immediate field. */
1223 small_int (op, mode)
1225 enum machine_mode mode ATTRIBUTE_UNUSED;
1227 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1231 small_int_or_double (op, mode)
1233 enum machine_mode mode ATTRIBUTE_UNUSED;
1235 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1236 || (GET_CODE (op) == CONST_DOUBLE
1237 && CONST_DOUBLE_HIGH (op) == 0
1238 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1241 /* Recognize operand values for the umul instruction. That instruction sign
1242 extends immediate values just like all other sparc instructions, but
1243 interprets the extended result as an unsigned number. */
1246 uns_small_int (op, mode)
1248 enum machine_mode mode ATTRIBUTE_UNUSED;
1250 #if HOST_BITS_PER_WIDE_INT > 32
1251 /* All allowed constants will fit a CONST_INT. */
1252 return (GET_CODE (op) == CONST_INT
1253 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1254 || (INTVAL (op) >= 0xFFFFF000
1255 && INTVAL (op) <= 0xFFFFFFFF)));
1257 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1258 || (GET_CODE (op) == CONST_DOUBLE
1259 && CONST_DOUBLE_HIGH (op) == 0
1260 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1265 uns_arith_operand (op, mode)
1267 enum machine_mode mode;
1269 return register_operand (op, mode) || uns_small_int (op, mode);
1272 /* Return truth value of statement that OP is a call-clobbered register. */
1274 clobbered_register (op, mode)
1276 enum machine_mode mode ATTRIBUTE_UNUSED;
1278 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1281 /* Return 1 if OP is a valid operand for the source of a move insn. */
1284 input_operand (op, mode)
1286 enum machine_mode mode;
1288 /* If both modes are non-void they must be the same. */
1289 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1292 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */
1293 if (GET_CODE (op) == CONSTANT_P_RTX)
1296 /* Allow any one instruction integer constant, and all CONST_INT
1297 variants when we are working in DImode and !arch64. */
1298 if (GET_MODE_CLASS (mode) == MODE_INT
1299 && ((GET_CODE (op) == CONST_INT
1300 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1301 || SPARC_SIMM13_P (INTVAL (op))
1303 && ! TARGET_ARCH64)))
1305 && GET_CODE (op) == CONST_DOUBLE
1306 && ((CONST_DOUBLE_HIGH (op) == 0
1307 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1309 #if HOST_BITS_PER_WIDE_INT == 64
1310 (CONST_DOUBLE_HIGH (op) == 0
1311 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1313 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1314 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1315 && CONST_DOUBLE_HIGH (op) == 0)
1316 || (CONST_DOUBLE_HIGH (op) == -1
1317 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1322 /* If !arch64 and this is a DImode const, allow it so that
1323 the splits can be generated. */
1326 && GET_CODE (op) == CONST_DOUBLE)
1329 if (register_operand (op, mode))
1332 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1333 && GET_CODE (op) == CONST_DOUBLE)
1336 /* If this is a SUBREG, look inside so that we handle
1337 paradoxical ones. */
1338 if (GET_CODE (op) == SUBREG)
1339 op = SUBREG_REG (op);
1341 /* Check for valid MEM forms. */
1342 if (GET_CODE (op) == MEM)
1344 rtx inside = XEXP (op, 0);
1346 if (GET_CODE (inside) == LO_SUM)
1348 /* We can't allow these because all of the splits
1349 (eventually as they trickle down into DFmode
1350 splits) require offsettable memory references. */
1352 && GET_MODE (op) == TFmode)
1355 return (register_operand (XEXP (inside, 0), Pmode)
1356 && CONSTANT_P (XEXP (inside, 1)));
1358 return memory_address_p (mode, inside);
1365 /* We know it can't be done in one insn when we get here,
1366 the movsi expander guarantees this. */
1368 sparc_emit_set_const32 (op0, op1)
1372 enum machine_mode mode = GET_MODE (op0);
1375 if (GET_CODE (op1) == CONST_INT)
1377 HOST_WIDE_INT value = INTVAL (op1);
1379 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1380 || SPARC_SIMM13_P (value))
1384 /* Full 2-insn decomposition is needed. */
1385 if (reload_in_progress || reload_completed)
1388 temp = gen_reg_rtx (mode);
1390 if (GET_CODE (op1) == CONST_INT)
1392 /* Emit them as real moves instead of a HIGH/LO_SUM,
1393 this way CSE can see everything and reuse intermediate
1394 values if it wants. */
1396 && HOST_BITS_PER_WIDE_INT != 64
1397 && (INTVAL (op1) & 0x80000000) != 0)
1398 emit_insn (gen_rtx_SET
1400 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1403 emit_insn (gen_rtx_SET (VOIDmode, temp,
1404 GEN_INT (INTVAL (op1)
1405 & ~(HOST_WIDE_INT)0x3ff)));
1407 emit_insn (gen_rtx_SET (VOIDmode,
1409 gen_rtx_IOR (mode, temp,
1410 GEN_INT (INTVAL (op1) & 0x3ff))));
1414 /* A symbol, emit in the traditional way. */
1415 emit_insn (gen_rtx_SET (VOIDmode, temp,
1416 gen_rtx_HIGH (mode, op1)));
1417 emit_insn (gen_rtx_SET (VOIDmode,
1418 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1424 /* SPARC-v9 code-model support. */
1426 sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1433 if (temp1 && GET_MODE (temp1) == TImode)
1436 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1439 switch (sparc_cmodel)
1442 /* The range spanned by all instructions in the object is less
1443 than 2^31 bytes (2GB) and the distance from any instruction
1444 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1445 than 2^31 bytes (2GB).
1447 The executable must be in the low 4TB of the virtual address
1450 sethi %hi(symbol), %temp
1451 or %temp, %lo(symbol), %reg */
1452 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1453 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1457 /* The range spanned by all instructions in the object is less
1458 than 2^31 bytes (2GB) and the distance from any instruction
1459 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1460 than 2^31 bytes (2GB).
1462 The executable must be in the low 16TB of the virtual address
1465 sethi %h44(symbol), %temp1
1466 or %temp1, %m44(symbol), %temp2
1467 sllx %temp2, 12, %temp3
1468 or %temp3, %l44(symbol), %reg */
1469 emit_insn (gen_seth44 (op0, op1));
1470 emit_insn (gen_setm44 (op0, op0, op1));
1471 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1472 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1473 emit_insn (gen_setl44 (op0, temp1, op1));
1477 /* The range spanned by all instructions in the object is less
1478 than 2^31 bytes (2GB) and the distance from any instruction
1479 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1480 than 2^31 bytes (2GB).
1482 The executable can be placed anywhere in the virtual address
1485 sethi %hh(symbol), %temp1
1486 sethi %lm(symbol), %temp2
1487 or %temp1, %hm(symbol), %temp3
1488 or %temp2, %lo(symbol), %temp4
1489 sllx %temp3, 32, %temp5
1490 or %temp4, %temp5, %reg */
1492 /* It is possible that one of the registers we got for operands[2]
1493 might coincide with that of operands[0] (which is why we made
1494 it TImode). Pick the other one to use as our scratch. */
1495 if (rtx_equal_p (temp1, op0))
1498 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1503 emit_insn (gen_sethh (op0, op1));
1504 emit_insn (gen_setlm (temp1, op1));
1505 emit_insn (gen_sethm (op0, op0, op1));
1506 emit_insn (gen_rtx_SET (VOIDmode, op0,
1507 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1508 emit_insn (gen_rtx_SET (VOIDmode, op0,
1509 gen_rtx_PLUS (DImode, op0, temp1)));
1510 emit_insn (gen_setlo (op0, op0, op1));
1514 /* Old old old backwards compatibility kruft here.
1515 Essentially it is MEDLOW with a fixed 64-bit
1516 virtual base added to all data segment addresses.
1517 Text-segment stuff is computed like MEDANY, we can't
1518 reuse the code above because the relocation knobs
1521 Data segment: sethi %hi(symbol), %temp1
1522 or %temp1, %lo(symbol), %temp2
1523 add %temp2, EMBMEDANY_BASE_REG, %reg
1525 Text segment: sethi %uhi(symbol), %temp1
1526 sethi %hi(symbol), %temp2
1527 or %temp1, %ulo(symbol), %temp3
1528 or %temp2, %lo(symbol), %temp4
1529 sllx %temp3, 32, %temp5
1530 or %temp4, %temp5, %reg */
1531 if (data_segment_operand (op1, GET_MODE (op1)))
1533 emit_insn (gen_embmedany_sethi (temp1, op1));
1534 emit_insn (gen_embmedany_brsum (op0, temp1));
1535 emit_insn (gen_embmedany_losum (op0, op0, op1));
1539 /* It is possible that one of the registers we got for operands[2]
1540 might coincide with that of operands[0] (which is why we made
1541 it TImode). Pick the other one to use as our scratch. */
1542 if (rtx_equal_p (temp1, op0))
1545 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1550 emit_insn (gen_embmedany_textuhi (op0, op1));
1551 emit_insn (gen_embmedany_texthi (temp1, op1));
1552 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1553 emit_insn (gen_rtx_SET (VOIDmode, op0,
1554 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1555 emit_insn (gen_rtx_SET (VOIDmode, op0,
1556 gen_rtx_PLUS (DImode, op0, temp1)));
1557 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1566 /* These avoid problems when cross compiling. If we do not
1567 go through all this hair then the optimizer will see
1568 invalid REG_EQUAL notes or in some cases none at all. */
1569 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1570 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1571 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1572 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1574 #if HOST_BITS_PER_WIDE_INT == 64
1575 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1576 #define GEN_INT64(__x) GEN_INT (__x)
1578 #define GEN_HIGHINT64(__x) \
1579 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1580 #define GEN_INT64(__x) \
1581 immed_double_const ((__x) & 0xffffffff, \
1582 ((__x) & 0x80000000 ? -1 : 0), DImode)
1585 /* The optimizer is not to assume anything about exactly
1586 which bits are set for a HIGH, they are unspecified.
1587 Unfortunately this leads to many missed optimizations
1588 during CSE. We mask out the non-HIGH bits, and matches
1589 a plain movdi, to alleviate this problem. */
1591 sparc_emit_set_safe_HIGH64 (dest, val)
1595 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1599 gen_safe_SET64 (dest, val)
1603 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1607 gen_safe_OR64 (src, val)
1611 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1615 gen_safe_XOR64 (src, val)
1619 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1622 /* Worker routines for 64-bit constant formation on arch64.
1623 One of the key things to be doing in these emissions is
1624 to create as many temp REGs as possible. This makes it
1625 possible for half-built constants to be used later when
1626 such values are similar to something required later on.
1627 Without doing this, the optimizer cannot see such
1630 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1631 unsigned HOST_WIDE_INT, int);
1634 sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1637 unsigned HOST_WIDE_INT low_bits;
1640 unsigned HOST_WIDE_INT high_bits;
1643 high_bits = (~low_bits) & 0xffffffff;
1645 high_bits = low_bits;
1647 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1650 emit_insn (gen_rtx_SET (VOIDmode, op0,
1651 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1655 /* If we are XOR'ing with -1, then we should emit a one's complement
1656 instead. This way the combiner will notice logical operations
1657 such as ANDN later on and substitute. */
1658 if ((low_bits & 0x3ff) == 0x3ff)
1660 emit_insn (gen_rtx_SET (VOIDmode, op0,
1661 gen_rtx_NOT (DImode, temp)));
1665 emit_insn (gen_rtx_SET (VOIDmode, op0,
1666 gen_safe_XOR64 (temp,
1667 (-(HOST_WIDE_INT)0x400
1668 | (low_bits & 0x3ff)))));
1673 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1674 unsigned HOST_WIDE_INT, int);
1677 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1680 unsigned HOST_WIDE_INT high_bits;
1681 unsigned HOST_WIDE_INT low_immediate;
1686 if ((high_bits & 0xfffffc00) != 0)
1688 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1689 if ((high_bits & ~0xfffffc00) != 0)
1690 emit_insn (gen_rtx_SET (VOIDmode, op0,
1691 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1697 emit_insn (gen_safe_SET64 (temp, high_bits));
1701 /* Now shift it up into place. */
1702 emit_insn (gen_rtx_SET (VOIDmode, op0,
1703 gen_rtx_ASHIFT (DImode, temp2,
1704 GEN_INT (shift_count))));
1706 /* If there is a low immediate part piece, finish up by
1707 putting that in as well. */
1708 if (low_immediate != 0)
1709 emit_insn (gen_rtx_SET (VOIDmode, op0,
1710 gen_safe_OR64 (op0, low_immediate)));
1713 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1714 unsigned HOST_WIDE_INT);
1716 /* Full 64-bit constant decomposition. Even though this is the
1717 'worst' case, we still optimize a few things away. */
1719 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1722 unsigned HOST_WIDE_INT high_bits;
1723 unsigned HOST_WIDE_INT low_bits;
1727 if (reload_in_progress || reload_completed)
1730 sub_temp = gen_reg_rtx (DImode);
1732 if ((high_bits & 0xfffffc00) != 0)
1734 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1735 if ((high_bits & ~0xfffffc00) != 0)
1736 emit_insn (gen_rtx_SET (VOIDmode,
1738 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1744 emit_insn (gen_safe_SET64 (temp, high_bits));
1748 if (!reload_in_progress && !reload_completed)
1750 rtx temp2 = gen_reg_rtx (DImode);
1751 rtx temp3 = gen_reg_rtx (DImode);
1752 rtx temp4 = gen_reg_rtx (DImode);
1754 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1755 gen_rtx_ASHIFT (DImode, sub_temp,
1758 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1759 if ((low_bits & ~0xfffffc00) != 0)
1761 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1762 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1763 emit_insn (gen_rtx_SET (VOIDmode, op0,
1764 gen_rtx_PLUS (DImode, temp4, temp3)));
1768 emit_insn (gen_rtx_SET (VOIDmode, op0,
1769 gen_rtx_PLUS (DImode, temp4, temp2)));
1774 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1775 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1776 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1779 /* We are in the middle of reload, so this is really
1780 painful. However we do still make an attempt to
1781 avoid emitting truly stupid code. */
1782 if (low1 != const0_rtx)
1784 emit_insn (gen_rtx_SET (VOIDmode, op0,
1785 gen_rtx_ASHIFT (DImode, sub_temp,
1786 GEN_INT (to_shift))));
1787 emit_insn (gen_rtx_SET (VOIDmode, op0,
1788 gen_rtx_IOR (DImode, op0, low1)));
1796 if (low2 != const0_rtx)
1798 emit_insn (gen_rtx_SET (VOIDmode, op0,
1799 gen_rtx_ASHIFT (DImode, sub_temp,
1800 GEN_INT (to_shift))));
1801 emit_insn (gen_rtx_SET (VOIDmode, op0,
1802 gen_rtx_IOR (DImode, op0, low2)));
1810 emit_insn (gen_rtx_SET (VOIDmode, op0,
1811 gen_rtx_ASHIFT (DImode, sub_temp,
1812 GEN_INT (to_shift))));
1813 if (low3 != const0_rtx)
1814 emit_insn (gen_rtx_SET (VOIDmode, op0,
1815 gen_rtx_IOR (DImode, op0, low3)));
1820 /* Analyze a 64-bit constant for certain properties. */
1821 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1822 unsigned HOST_WIDE_INT,
1823 int *, int *, int *);
1826 analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
1827 unsigned HOST_WIDE_INT high_bits, low_bits;
1828 int *hbsp, *lbsp, *abbasp;
1830 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1833 lowest_bit_set = highest_bit_set = -1;
1837 if ((lowest_bit_set == -1)
1838 && ((low_bits >> i) & 1))
1840 if ((highest_bit_set == -1)
1841 && ((high_bits >> (32 - i - 1)) & 1))
1842 highest_bit_set = (64 - i - 1);
1845 && ((highest_bit_set == -1)
1846 || (lowest_bit_set == -1)));
1852 if ((lowest_bit_set == -1)
1853 && ((high_bits >> i) & 1))
1854 lowest_bit_set = i + 32;
1855 if ((highest_bit_set == -1)
1856 && ((low_bits >> (32 - i - 1)) & 1))
1857 highest_bit_set = 32 - i - 1;
1860 && ((highest_bit_set == -1)
1861 || (lowest_bit_set == -1)));
1863 /* If there are no bits set this should have gone out
1864 as one instruction! */
1865 if (lowest_bit_set == -1
1866 || highest_bit_set == -1)
1868 all_bits_between_are_set = 1;
1869 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1873 if ((low_bits & (1 << i)) != 0)
1878 if ((high_bits & (1 << (i - 32))) != 0)
1881 all_bits_between_are_set = 0;
1884 *hbsp = highest_bit_set;
1885 *lbsp = lowest_bit_set;
1886 *abbasp = all_bits_between_are_set;
1889 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1892 const64_is_2insns (high_bits, low_bits)
1893 unsigned HOST_WIDE_INT high_bits, low_bits;
1895 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1898 || high_bits == 0xffffffff)
1901 analyze_64bit_constant (high_bits, low_bits,
1902 &highest_bit_set, &lowest_bit_set,
1903 &all_bits_between_are_set);
1905 if ((highest_bit_set == 63
1906 || lowest_bit_set == 0)
1907 && all_bits_between_are_set != 0)
1910 if ((highest_bit_set - lowest_bit_set) < 21)
1916 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1917 unsigned HOST_WIDE_INT,
1920 static unsigned HOST_WIDE_INT
1921 create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
1922 unsigned HOST_WIDE_INT high_bits, low_bits;
1923 int lowest_bit_set, shift;
1925 HOST_WIDE_INT hi, lo;
1927 if (lowest_bit_set < 32)
1929 lo = (low_bits >> lowest_bit_set) << shift;
1930 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1935 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1942 /* Here we are sure to be arch64 and this is an integer constant
1943 being loaded into a register. Emit the most efficient
1944 insn sequence possible. Detection of all the 1-insn cases
1945 has been done already. */
1947 sparc_emit_set_const64 (op0, op1)
1951 unsigned HOST_WIDE_INT high_bits, low_bits;
1952 int lowest_bit_set, highest_bit_set;
1953 int all_bits_between_are_set;
1956 /* Sanity check that we know what we are working with. */
1957 if (! TARGET_ARCH64)
1960 if (GET_CODE (op0) != SUBREG)
1962 if (GET_CODE (op0) != REG
1963 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1964 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1968 if (reload_in_progress || reload_completed)
1971 temp = gen_reg_rtx (DImode);
1973 if (GET_CODE (op1) != CONST_DOUBLE
1974 && GET_CODE (op1) != CONST_INT)
1976 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1980 if (GET_CODE (op1) == CONST_DOUBLE)
1982 #if HOST_BITS_PER_WIDE_INT == 64
1983 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1984 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1986 high_bits = CONST_DOUBLE_HIGH (op1);
1987 low_bits = CONST_DOUBLE_LOW (op1);
1992 #if HOST_BITS_PER_WIDE_INT == 64
1993 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1994 low_bits = (INTVAL (op1) & 0xffffffff);
1996 high_bits = ((INTVAL (op1) < 0) ?
1999 low_bits = INTVAL (op1);
2003 /* low_bits bits 0 --> 31
2004 high_bits bits 32 --> 63 */
2006 analyze_64bit_constant (high_bits, low_bits,
2007 &highest_bit_set, &lowest_bit_set,
2008 &all_bits_between_are_set);
2010 /* First try for a 2-insn sequence. */
2012 /* These situations are preferred because the optimizer can
2013 * do more things with them:
2015 * sllx %reg, shift, %reg
2017 * srlx %reg, shift, %reg
2018 * 3) mov some_small_const, %reg
2019 * sllx %reg, shift, %reg
2021 if (((highest_bit_set == 63
2022 || lowest_bit_set == 0)
2023 && all_bits_between_are_set != 0)
2024 || ((highest_bit_set - lowest_bit_set) < 12))
2026 HOST_WIDE_INT the_const = -1;
2027 int shift = lowest_bit_set;
2029 if ((highest_bit_set != 63
2030 && lowest_bit_set != 0)
2031 || all_bits_between_are_set == 0)
2034 create_simple_focus_bits (high_bits, low_bits,
2037 else if (lowest_bit_set == 0)
2038 shift = -(63 - highest_bit_set);
2040 if (! SPARC_SIMM13_P (the_const))
2043 emit_insn (gen_safe_SET64 (temp, the_const));
2045 emit_insn (gen_rtx_SET (VOIDmode,
2047 gen_rtx_ASHIFT (DImode,
2051 emit_insn (gen_rtx_SET (VOIDmode,
2053 gen_rtx_LSHIFTRT (DImode,
2055 GEN_INT (-shift))));
2061 /* Now a range of 22 or less bits set somewhere.
2062 * 1) sethi %hi(focus_bits), %reg
2063 * sllx %reg, shift, %reg
2064 * 2) sethi %hi(focus_bits), %reg
2065 * srlx %reg, shift, %reg
2067 if ((highest_bit_set - lowest_bit_set) < 21)
2069 unsigned HOST_WIDE_INT focus_bits =
2070 create_simple_focus_bits (high_bits, low_bits,
2071 lowest_bit_set, 10);
2073 if (! SPARC_SETHI_P (focus_bits))
2076 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2078 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2079 if (lowest_bit_set < 10)
2080 emit_insn (gen_rtx_SET (VOIDmode,
2082 gen_rtx_LSHIFTRT (DImode, temp,
2083 GEN_INT (10 - lowest_bit_set))));
2084 else if (lowest_bit_set > 10)
2085 emit_insn (gen_rtx_SET (VOIDmode,
2087 gen_rtx_ASHIFT (DImode, temp,
2088 GEN_INT (lowest_bit_set - 10))));
2094 /* 1) sethi %hi(low_bits), %reg
2095 * or %reg, %lo(low_bits), %reg
2096 * 2) sethi %hi(~low_bits), %reg
2097 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2100 || high_bits == 0xffffffff)
2102 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2103 (high_bits == 0xffffffff));
2107 /* Now, try 3-insn sequences. */
2109 /* 1) sethi %hi(high_bits), %reg
2110 * or %reg, %lo(high_bits), %reg
2111 * sllx %reg, 32, %reg
2115 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2119 /* We may be able to do something quick
2120 when the constant is negated, so try that. */
2121 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2122 (~low_bits) & 0xfffffc00))
2124 /* NOTE: The trailing bits get XOR'd so we need the
2125 non-negated bits, not the negated ones. */
2126 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2128 if ((((~high_bits) & 0xffffffff) == 0
2129 && ((~low_bits) & 0x80000000) == 0)
2130 || (((~high_bits) & 0xffffffff) == 0xffffffff
2131 && ((~low_bits) & 0x80000000) != 0))
2133 int fast_int = (~low_bits & 0xffffffff);
2135 if ((SPARC_SETHI_P (fast_int)
2136 && (~high_bits & 0xffffffff) == 0)
2137 || SPARC_SIMM13_P (fast_int))
2138 emit_insn (gen_safe_SET64 (temp, fast_int));
2140 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2145 #if HOST_BITS_PER_WIDE_INT == 64
2146 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2147 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2149 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2150 (~high_bits) & 0xffffffff,
2153 sparc_emit_set_const64 (temp, negated_const);
2156 /* If we are XOR'ing with -1, then we should emit a one's complement
2157 instead. This way the combiner will notice logical operations
2158 such as ANDN later on and substitute. */
2159 if (trailing_bits == 0x3ff)
2161 emit_insn (gen_rtx_SET (VOIDmode, op0,
2162 gen_rtx_NOT (DImode, temp)));
2166 emit_insn (gen_rtx_SET (VOIDmode,
2168 gen_safe_XOR64 (temp,
2169 (-0x400 | trailing_bits))));
2174 /* 1) sethi %hi(xxx), %reg
2175 * or %reg, %lo(xxx), %reg
2176 * sllx %reg, yyy, %reg
2178 * ??? This is just a generalized version of the low_bits==0
2179 * thing above, FIXME...
2181 if ((highest_bit_set - lowest_bit_set) < 32)
2183 unsigned HOST_WIDE_INT focus_bits =
2184 create_simple_focus_bits (high_bits, low_bits,
2187 /* We can't get here in this state. */
2188 if (highest_bit_set < 32
2189 || lowest_bit_set >= 32)
2192 /* So what we know is that the set bits straddle the
2193 middle of the 64-bit word. */
2194 sparc_emit_set_const64_quick2 (op0, temp,
2200 /* 1) sethi %hi(high_bits), %reg
2201 * or %reg, %lo(high_bits), %reg
2202 * sllx %reg, 32, %reg
2203 * or %reg, low_bits, %reg
2205 if (SPARC_SIMM13_P(low_bits)
2206 && ((int)low_bits > 0))
2208 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2212 /* The easiest way when all else fails, is full decomposition. */
2214 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2215 high_bits, low_bits, ~high_bits, ~low_bits);
2217 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2220 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2221 return the mode to be used for the comparison. For floating-point,
2222 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2223 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2224 processing is needed. */
2227 select_cc_mode (op, x, y)
2230 rtx y ATTRIBUTE_UNUSED;
2232 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2258 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2259 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2261 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2262 return CCX_NOOVmode;
2268 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2275 /* X and Y are two things to compare using CODE. Emit the compare insn and
2276 return the rtx for the cc reg in the proper mode. */
2279 gen_compare_reg (code, x, y)
2283 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2286 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2287 fcc regs (cse can't tell they're really call clobbered regs and will
2288 remove a duplicate comparison even if there is an intervening function
2289 call - it will then try to reload the cc reg via an int reg which is why
2290 we need the movcc patterns). It is possible to provide the movcc
2291 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2292 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2293 to tell cse that CCFPE mode registers (even pseudos) are call
2296 /* ??? This is an experiment. Rather than making changes to cse which may
2297 or may not be easy/clean, we do our own cse. This is possible because
2298 we will generate hard registers. Cse knows they're call clobbered (it
2299 doesn't know the same thing about pseudos). If we guess wrong, no big
2300 deal, but if we win, great! */
2302 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2303 #if 1 /* experiment */
2306 /* We cycle through the registers to ensure they're all exercised. */
2307 static int next_fcc_reg = 0;
2308 /* Previous x,y for each fcc reg. */
2309 static rtx prev_args[4][2];
2311 /* Scan prev_args for x,y. */
2312 for (reg = 0; reg < 4; reg++)
2313 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2318 prev_args[reg][0] = x;
2319 prev_args[reg][1] = y;
2320 next_fcc_reg = (next_fcc_reg + 1) & 3;
2322 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2325 cc_reg = gen_reg_rtx (mode);
2326 #endif /* ! experiment */
2327 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2328 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2330 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2332 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2333 gen_rtx_COMPARE (mode, x, y)));
2338 /* This function is used for v9 only.
2339 CODE is the code for an Scc's comparison.
2340 OPERANDS[0] is the target of the Scc insn.
2341 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2342 been generated yet).
2344 This function is needed to turn
2347 (gt (reg:CCX 100 %icc)
2351 (gt:DI (reg:CCX 100 %icc)
2354 IE: The instruction recognizer needs to see the mode of the comparison to
2355 find the right instruction. We could use "gt:DI" right in the
2356 define_expand, but leaving it out allows us to handle DI, SI, etc.
2358 We refer to the global sparc compare operands sparc_compare_op0 and
2359 sparc_compare_op1. */
2362 gen_v9_scc (compare_code, operands)
2363 enum rtx_code compare_code;
2364 register rtx *operands;
2369 && (GET_MODE (sparc_compare_op0) == DImode
2370 || GET_MODE (operands[0]) == DImode))
2373 op0 = sparc_compare_op0;
2374 op1 = sparc_compare_op1;
2376 /* Try to use the movrCC insns. */
2378 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2379 && op1 == const0_rtx
2380 && v9_regcmp_p (compare_code))
2382 /* Special case for op0 != 0. This can be done with one instruction if
2383 operands[0] == sparc_compare_op0. */
2385 if (compare_code == NE
2386 && GET_MODE (operands[0]) == DImode
2387 && rtx_equal_p (op0, operands[0]))
2389 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2390 gen_rtx_IF_THEN_ELSE (DImode,
2391 gen_rtx_fmt_ee (compare_code, DImode,
2398 if (reg_overlap_mentioned_p (operands[0], op0))
2400 /* Handle the case where operands[0] == sparc_compare_op0.
2401 We "early clobber" the result. */
2402 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2403 emit_move_insn (op0, sparc_compare_op0);
2406 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2407 if (GET_MODE (op0) != DImode)
2409 temp = gen_reg_rtx (DImode);
2410 convert_move (temp, op0, 0);
2414 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2415 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2416 gen_rtx_fmt_ee (compare_code, DImode,
2424 operands[1] = gen_compare_reg (compare_code, op0, op1);
2426 switch (GET_MODE (operands[1]))
2436 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2437 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2438 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2439 gen_rtx_fmt_ee (compare_code,
2440 GET_MODE (operands[1]),
2441 operands[1], const0_rtx),
2442 const1_rtx, operands[0])));
2447 /* Emit a conditional jump insn for the v9 architecture using comparison code
2448 CODE and jump target LABEL.
2449 This function exists to take advantage of the v9 brxx insns. */
2452 emit_v9_brxx_insn (code, op0, label)
2456 emit_jump_insn (gen_rtx_SET (VOIDmode,
2458 gen_rtx_IF_THEN_ELSE (VOIDmode,
2459 gen_rtx_fmt_ee (code, GET_MODE (op0),
2461 gen_rtx_LABEL_REF (VOIDmode, label),
2465 /* Generate a DFmode part of a hard TFmode register.
2466 REG is the TFmode hard register, LOW is 1 for the
2467 low 64bit of the register and 0 otherwise.
2470 gen_df_reg (reg, low)
2474 int regno = REGNO (reg);
2476 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2477 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2478 return gen_rtx_REG (DFmode, regno);
2481 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2482 Unlike normal calls, TFmode operands are passed by reference. It is
2483 assumed that no more than 3 operands are required. */
2486 emit_soft_tfmode_libcall (func_name, nargs, operands)
2487 const char *func_name;
2491 rtx ret_slot = NULL, arg[3], func_sym;
2494 /* We only expect to be called for conversions, unary, and binary ops. */
2495 if (nargs < 2 || nargs > 3)
2498 for (i = 0; i < nargs; ++i)
2500 rtx this_arg = operands[i];
2503 /* TFmode arguments and return values are passed by reference. */
2504 if (GET_MODE (this_arg) == TFmode)
2506 int force_stack_temp;
2508 force_stack_temp = 0;
2509 if (TARGET_BUGGY_QP_LIB && i == 0)
2510 force_stack_temp = 1;
2512 if (GET_CODE (this_arg) == MEM
2513 && ! force_stack_temp)
2514 this_arg = XEXP (this_arg, 0);
2515 else if (CONSTANT_P (this_arg)
2516 && ! force_stack_temp)
2518 this_slot = force_const_mem (TFmode, this_arg);
2519 this_arg = XEXP (this_slot, 0);
2523 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2525 /* Operand 0 is the return value. We'll copy it out later. */
2527 emit_move_insn (this_slot, this_arg);
2529 ret_slot = this_slot;
2531 this_arg = XEXP (this_slot, 0);
2538 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2540 if (GET_MODE (operands[0]) == TFmode)
2543 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2544 arg[0], GET_MODE (arg[0]),
2545 arg[1], GET_MODE (arg[1]));
2547 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2548 arg[0], GET_MODE (arg[0]),
2549 arg[1], GET_MODE (arg[1]),
2550 arg[2], GET_MODE (arg[2]));
2553 emit_move_insn (operands[0], ret_slot);
2562 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2563 GET_MODE (operands[0]), 1,
2564 arg[1], GET_MODE (arg[1]));
2566 if (ret != operands[0])
2567 emit_move_insn (operands[0], ret);
2571 /* Expand soft-float TFmode calls to sparc abi routines. */
2574 emit_soft_tfmode_binop (code, operands)
2598 emit_soft_tfmode_libcall (func, 3, operands);
2602 emit_soft_tfmode_unop (code, operands)
2617 emit_soft_tfmode_libcall (func, 2, operands);
2621 emit_soft_tfmode_cvt (code, operands)
2630 switch (GET_MODE (operands[1]))
2643 case FLOAT_TRUNCATE:
2644 switch (GET_MODE (operands[0]))
2658 switch (GET_MODE (operands[1]))
2671 case UNSIGNED_FLOAT:
2672 switch (GET_MODE (operands[1]))
2686 switch (GET_MODE (operands[0]))
2700 switch (GET_MODE (operands[0]))
2717 emit_soft_tfmode_libcall (func, 2, operands);
2720 /* Expand a hard-float tfmode operation. All arguments must be in
2724 emit_hard_tfmode_operation (code, operands)
2730 if (GET_RTX_CLASS (code) == '1')
2732 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2733 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2737 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2738 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2739 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2740 operands[1], operands[2]);
2743 if (register_operand (operands[0], VOIDmode))
2746 dest = gen_reg_rtx (GET_MODE (operands[0]));
2748 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2750 if (dest != operands[0])
2751 emit_move_insn (operands[0], dest);
2755 emit_tfmode_binop (code, operands)
2759 if (TARGET_HARD_QUAD)
2760 emit_hard_tfmode_operation (code, operands);
2762 emit_soft_tfmode_binop (code, operands);
2766 emit_tfmode_unop (code, operands)
2770 if (TARGET_HARD_QUAD)
2771 emit_hard_tfmode_operation (code, operands);
2773 emit_soft_tfmode_unop (code, operands);
2777 emit_tfmode_cvt (code, operands)
2781 if (TARGET_HARD_QUAD)
2782 emit_hard_tfmode_operation (code, operands);
2784 emit_soft_tfmode_cvt (code, operands);
2787 /* Return nonzero if a return peephole merging return with
2788 setting of output register is ok. */
2790 leaf_return_peephole_ok ()
2792 return (actual_fsize == 0);
2795 /* Return nonzero if a branch/jump/call instruction will be emitting
2796 nop into its delay slot. */
2799 empty_delay_slot (insn)
2804 /* If no previous instruction (should not happen), return true. */
2805 if (PREV_INSN (insn) == NULL)
2808 seq = NEXT_INSN (PREV_INSN (insn));
2809 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2815 /* Return nonzero if TRIAL can go into the function epilogue's
2816 delay slot. SLOT is the slot we are trying to fill. */
2819 eligible_for_epilogue_delay (trial, slot)
2828 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2831 if (get_attr_length (trial) != 1)
2834 /* If there are any call-saved registers, we should scan TRIAL if it
2835 does not reference them. For now just make it easy. */
2839 /* If the function uses __builtin_eh_return, the eh_return machinery
2840 occupies the delay slot. */
2841 if (current_function_calls_eh_return)
2844 /* In the case of a true leaf function, anything can go into the delay slot.
2845 A delay slot only exists however if the frame size is zero, otherwise
2846 we will put an insn to adjust the stack after the return. */
2847 if (current_function_uses_only_leaf_regs)
2849 if (leaf_return_peephole_ok ())
2850 return ((get_attr_in_uncond_branch_delay (trial)
2851 == IN_BRANCH_DELAY_TRUE));
2855 pat = PATTERN (trial);
2857 /* Otherwise, only operations which can be done in tandem with
2858 a `restore' or `return' insn can go into the delay slot. */
2859 if (GET_CODE (SET_DEST (pat)) != REG
2860 || REGNO (SET_DEST (pat)) < 24)
2863 /* If this instruction sets up floating point register and we have a return
2864 instruction, it can probably go in. But restore will not work
2866 if (REGNO (SET_DEST (pat)) >= 32)
2868 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2869 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2874 /* The set of insns matched here must agree precisely with the set of
2875 patterns paired with a RETURN in sparc.md. */
2877 src = SET_SRC (pat);
2879 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2880 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2881 && arith_operand (src, GET_MODE (src)))
2884 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2886 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2889 /* This matches "*return_di". */
2890 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2891 && arith_double_operand (src, GET_MODE (src)))
2892 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2894 /* This matches "*return_sf_no_fpu". */
2895 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2896 && register_operand (src, SFmode))
2899 /* If we have return instruction, anything that does not use
2900 local or output registers and can go into a delay slot wins. */
2901 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2902 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2905 /* This matches "*return_addsi". */
2906 else if (GET_CODE (src) == PLUS
2907 && arith_operand (XEXP (src, 0), SImode)
2908 && arith_operand (XEXP (src, 1), SImode)
2909 && (register_operand (XEXP (src, 0), SImode)
2910 || register_operand (XEXP (src, 1), SImode)))
2913 /* This matches "*return_adddi". */
2914 else if (GET_CODE (src) == PLUS
2915 && arith_double_operand (XEXP (src, 0), DImode)
2916 && arith_double_operand (XEXP (src, 1), DImode)
2917 && (register_operand (XEXP (src, 0), DImode)
2918 || register_operand (XEXP (src, 1), DImode)))
2921 /* This can match "*return_losum_[sd]i".
2922 Catch only some cases, so that return_losum* don't have
2924 else if (GET_CODE (src) == LO_SUM
2925 && ! TARGET_CM_MEDMID
2926 && ((register_operand (XEXP (src, 0), SImode)
2927 && immediate_operand (XEXP (src, 1), SImode))
2929 && register_operand (XEXP (src, 0), DImode)
2930 && immediate_operand (XEXP (src, 1), DImode))))
2933 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2934 else if (GET_CODE (src) == ASHIFT
2935 && (register_operand (XEXP (src, 0), SImode)
2936 || register_operand (XEXP (src, 0), DImode))
2937 && XEXP (src, 1) == const1_rtx)
2943 /* Return nonzero if TRIAL can go into the sibling call
2947 eligible_for_sibcall_delay (trial)
2952 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2955 if (get_attr_length (trial) != 1)
2958 pat = PATTERN (trial);
2960 if (current_function_uses_only_leaf_regs)
2962 /* If the tail call is done using the call instruction,
2963 we have to restore %o7 in the delay slot. */
2964 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2967 /* %g1 is used to build the function address */
2968 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2974 /* Otherwise, only operations which can be done in tandem with
2975 a `restore' insn can go into the delay slot. */
2976 if (GET_CODE (SET_DEST (pat)) != REG
2977 || REGNO (SET_DEST (pat)) < 24
2978 || REGNO (SET_DEST (pat)) >= 32)
2981 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2983 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2986 src = SET_SRC (pat);
2988 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2989 && arith_operand (src, GET_MODE (src)))
2992 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2994 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2997 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2998 && arith_double_operand (src, GET_MODE (src)))
2999 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3001 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
3002 && register_operand (src, SFmode))
3005 else if (GET_CODE (src) == PLUS
3006 && arith_operand (XEXP (src, 0), SImode)
3007 && arith_operand (XEXP (src, 1), SImode)
3008 && (register_operand (XEXP (src, 0), SImode)
3009 || register_operand (XEXP (src, 1), SImode)))
3012 else if (GET_CODE (src) == PLUS
3013 && arith_double_operand (XEXP (src, 0), DImode)
3014 && arith_double_operand (XEXP (src, 1), DImode)
3015 && (register_operand (XEXP (src, 0), DImode)
3016 || register_operand (XEXP (src, 1), DImode)))
3019 else if (GET_CODE (src) == LO_SUM
3020 && ! TARGET_CM_MEDMID
3021 && ((register_operand (XEXP (src, 0), SImode)
3022 && immediate_operand (XEXP (src, 1), SImode))
3024 && register_operand (XEXP (src, 0), DImode)
3025 && immediate_operand (XEXP (src, 1), DImode))))
3028 else if (GET_CODE (src) == ASHIFT
3029 && (register_operand (XEXP (src, 0), SImode)
3030 || register_operand (XEXP (src, 0), DImode))
3031 && XEXP (src, 1) == const1_rtx)
3038 check_return_regs (x)
3041 switch (GET_CODE (x))
3044 return IN_OR_GLOBAL_P (x);
3059 if (check_return_regs (XEXP (x, 1)) == 0)
3064 return check_return_regs (XEXP (x, 0));
3073 short_branch (uid1, uid2)
3076 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3078 /* Leave a few words of "slop". */
3079 if (delta >= -1023 && delta <= 1022)
3085 /* Return nonzero if REG is not used after INSN.
3086 We assume REG is a reload reg, and therefore does
3087 not live past labels or calls or jumps. */
3089 reg_unused_after (reg, insn)
3093 enum rtx_code code, prev_code = UNKNOWN;
3095 while ((insn = NEXT_INSN (insn)))
3097 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3100 code = GET_CODE (insn);
3101 if (GET_CODE (insn) == CODE_LABEL)
3104 if (GET_RTX_CLASS (code) == 'i')
3106 rtx set = single_set (insn);
3107 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3110 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3112 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3120 /* The table we use to reference PIC data. */
3121 static GTY(()) rtx global_offset_table;
3123 /* The function we use to get at it. */
3124 static GTY(()) rtx get_pc_symbol;
3125 static char get_pc_symbol_name[256];
3127 /* Ensure that we are not using patterns that are not OK with PIC. */
3136 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3137 || (GET_CODE (recog_data.operand[i]) == CONST
3138 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3139 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3140 == global_offset_table)
3141 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3150 /* Return true if X is an address which needs a temporary register when
3151 reloaded while generating PIC code. */
3154 pic_address_needs_scratch (x)
3157 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3158 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3159 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3160 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3161 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3167 /* Legitimize PIC addresses. If the address is already position-independent,
3168 we return ORIG. Newly generated position-independent addresses go into a
3169 reg. This is REG if nonzero, otherwise we allocate register(s) as
3173 legitimize_pic_address (orig, mode, reg)
3175 enum machine_mode mode ATTRIBUTE_UNUSED;
3178 if (GET_CODE (orig) == SYMBOL_REF)
3180 rtx pic_ref, address;
3185 if (reload_in_progress || reload_completed)
3188 reg = gen_reg_rtx (Pmode);
3193 /* If not during reload, allocate another temp reg here for loading
3194 in the address, so that these instructions can be optimized
3196 rtx temp_reg = ((reload_in_progress || reload_completed)
3197 ? reg : gen_reg_rtx (Pmode));
3199 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3200 won't get confused into thinking that these two instructions
3201 are loading in the true address of the symbol. If in the
3202 future a PIC rtx exists, that should be used instead. */
3203 if (Pmode == SImode)
3205 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3206 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3210 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3211 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3218 pic_ref = gen_rtx_MEM (Pmode,
3219 gen_rtx_PLUS (Pmode,
3220 pic_offset_table_rtx, address));
3221 current_function_uses_pic_offset_table = 1;
3222 RTX_UNCHANGING_P (pic_ref) = 1;
3223 insn = emit_move_insn (reg, pic_ref);
3224 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3226 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3230 else if (GET_CODE (orig) == CONST)
3234 if (GET_CODE (XEXP (orig, 0)) == PLUS
3235 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3240 if (reload_in_progress || reload_completed)
3243 reg = gen_reg_rtx (Pmode);
3246 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3248 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3249 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3250 base == reg ? 0 : reg);
3255 if (GET_CODE (offset) == CONST_INT)
3257 if (SMALL_INT (offset))
3258 return plus_constant (base, INTVAL (offset));
3259 else if (! reload_in_progress && ! reload_completed)
3260 offset = force_reg (Pmode, offset);
3262 /* If we reach here, then something is seriously wrong. */
3265 return gen_rtx_PLUS (Pmode, base, offset);
3267 else if (GET_CODE (orig) == LABEL_REF)
3268 /* ??? Why do we do this? */
3269 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3270 the register is live instead, in case it is eliminated. */
3271 current_function_uses_pic_offset_table = 1;
3276 /* Emit special PIC prologues. */
3279 load_pic_register ()
3281 /* Labels to get the PC in the prologue of this function. */
3282 int orig_flag_pic = flag_pic;
3287 /* If we haven't emitted the special get_pc helper function, do so now. */
3288 if (get_pc_symbol_name[0] == 0)
3292 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3295 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3297 ASM_OUTPUT_ALIGN (asm_out_file, align);
3298 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
3299 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3302 /* Initialize every time through, since we can't easily
3303 know this to be permanent. */
3304 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3305 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3308 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3311 flag_pic = orig_flag_pic;
3313 /* Need to emit this whether or not we obey regdecls,
3314 since setjmp/longjmp can cause life info to screw up.
3315 ??? In the case where we don't obey regdecls, this is not sufficient
3316 since we may not fall out the bottom. */
3317 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3320 /* Return 1 if RTX is a MEM which is known to be aligned to at
3321 least a DESIRED byte boundary. */
3324 mem_min_alignment (mem, desired)
3328 rtx addr, base, offset;
3330 /* If it's not a MEM we can't accept it. */
3331 if (GET_CODE (mem) != MEM)
3334 addr = XEXP (mem, 0);
3335 base = offset = NULL_RTX;
3336 if (GET_CODE (addr) == PLUS)
3338 if (GET_CODE (XEXP (addr, 0)) == REG)
3340 base = XEXP (addr, 0);
3342 /* What we are saying here is that if the base
3343 REG is aligned properly, the compiler will make
3344 sure any REG based index upon it will be so
3346 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3347 offset = XEXP (addr, 1);
3349 offset = const0_rtx;
3352 else if (GET_CODE (addr) == REG)
3355 offset = const0_rtx;
3358 if (base != NULL_RTX)
3360 int regno = REGNO (base);
3362 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3364 /* Check if the compiler has recorded some information
3365 about the alignment of the base REG. If reload has
3366 completed, we already matched with proper alignments.
3367 If not running global_alloc, reload might give us
3368 unaligned pointer to local stack though. */
3370 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3371 || (optimize && reload_completed))
3372 && (INTVAL (offset) & (desired - 1)) == 0)
3377 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3381 else if (! TARGET_UNALIGNED_DOUBLES
3382 || CONSTANT_P (addr)
3383 || GET_CODE (addr) == LO_SUM)
3385 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3386 is true, in which case we can only assume that an access is aligned if
3387 it is to a constant address, or the address involves a LO_SUM. */
3391 /* An obviously unaligned address. */
3396 /* Vectors to keep interesting information about registers where it can easily
3397 be got. We used to use the actual mode value as the bit number, but there
3398 are more than 32 modes now. Instead we use two tables: one indexed by
3399 hard register number, and one indexed by mode. */
3401 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3402 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3403 mapped into one sparc_mode_class mode. */
3405 enum sparc_mode_class {
3406 S_MODE, D_MODE, T_MODE, O_MODE,
3407 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3411 /* Modes for single-word and smaller quantities. */
3412 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3414 /* Modes for double-word and smaller quantities. */
3415 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3417 /* Modes for quad-word and smaller quantities. */
3418 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3420 /* Modes for 8-word and smaller quantities. */
3421 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3423 /* Modes for single-float quantities. We must allow any single word or
3424 smaller quantity. This is because the fix/float conversion instructions
3425 take integer inputs/outputs from the float registers. */
3426 #define SF_MODES (S_MODES)
3428 /* Modes for double-float and smaller quantities. */
3429 #define DF_MODES (S_MODES | D_MODES)
3431 /* Modes for double-float only quantities. */
3432 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3434 /* Modes for quad-float only quantities. */
3435 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3437 /* Modes for quad-float and smaller quantities. */
3438 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3440 /* Modes for quad-float and double-float quantities. */
3441 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3443 /* Modes for quad-float pair only quantities. */
3444 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3446 /* Modes for quad-float pairs and smaller quantities. */
3447 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3449 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3451 /* Modes for condition codes. */
3452 #define CC_MODES (1 << (int) CC_MODE)
3453 #define CCFP_MODES (1 << (int) CCFP_MODE)
3455 /* Value is 1 if register/mode pair is acceptable on sparc.
3456 The funny mixture of D and T modes is because integer operations
3457 do not specially operate on tetra quantities, so non-quad-aligned
3458 registers can hold quadword quantities (except %o4 and %i4 because
3459 they cross fixed registers). */
3461 /* This points to either the 32 bit or the 64 bit version. */
3462 const int *hard_regno_mode_classes;
3464 static const int hard_32bit_mode_classes[] = {
3465 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3466 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3467 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3468 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3470 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3471 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3472 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3473 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3475 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3476 and none can hold SFmode/SImode values. */
3477 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3478 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3479 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3480 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3483 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3489 static const int hard_64bit_mode_classes[] = {
3490 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3491 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3492 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3493 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3495 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3496 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3497 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3498 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3500 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3501 and none can hold SFmode/SImode values. */
3502 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3503 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3504 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3505 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3508 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3514 int sparc_mode_class [NUM_MACHINE_MODES];
3516 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3523 for (i = 0; i < NUM_MACHINE_MODES; i++)
3525 switch (GET_MODE_CLASS (i))
3528 case MODE_PARTIAL_INT:
3529 case MODE_COMPLEX_INT:
3530 if (GET_MODE_SIZE (i) <= 4)
3531 sparc_mode_class[i] = 1 << (int) S_MODE;
3532 else if (GET_MODE_SIZE (i) == 8)
3533 sparc_mode_class[i] = 1 << (int) D_MODE;
3534 else if (GET_MODE_SIZE (i) == 16)
3535 sparc_mode_class[i] = 1 << (int) T_MODE;
3536 else if (GET_MODE_SIZE (i) == 32)
3537 sparc_mode_class[i] = 1 << (int) O_MODE;
3539 sparc_mode_class[i] = 0;
3542 case MODE_COMPLEX_FLOAT:
3543 if (GET_MODE_SIZE (i) <= 4)
3544 sparc_mode_class[i] = 1 << (int) SF_MODE;
3545 else if (GET_MODE_SIZE (i) == 8)
3546 sparc_mode_class[i] = 1 << (int) DF_MODE;
3547 else if (GET_MODE_SIZE (i) == 16)
3548 sparc_mode_class[i] = 1 << (int) TF_MODE;
3549 else if (GET_MODE_SIZE (i) == 32)
3550 sparc_mode_class[i] = 1 << (int) OF_MODE;
3552 sparc_mode_class[i] = 0;
3556 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3557 we must explicitly check for them here. */
3558 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3559 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3560 else if (i == (int) CCmode || i == (int) CC_NOOVmode
3561 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3562 sparc_mode_class[i] = 1 << (int) CC_MODE;
3564 sparc_mode_class[i] = 0;
3570 hard_regno_mode_classes = hard_64bit_mode_classes;
3572 hard_regno_mode_classes = hard_32bit_mode_classes;
3574 /* Initialize the array used by REGNO_REG_CLASS. */
3575 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3577 if (i < 16 && TARGET_V8PLUS)
3578 sparc_regno_reg_class[i] = I64_REGS;
3579 else if (i < 32 || i == FRAME_POINTER_REGNUM)
3580 sparc_regno_reg_class[i] = GENERAL_REGS;
3582 sparc_regno_reg_class[i] = FP_REGS;
3584 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3586 sparc_regno_reg_class[i] = FPCC_REGS;
3588 sparc_regno_reg_class[i] = NO_REGS;
3592 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3593 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3594 v9 int regs as it simplifies the code. */
3597 save_regs (file, low, high, base, offset, n_regs, real_offset)
3607 if (TARGET_ARCH64 && high <= 32)
3609 for (i = low; i < high; i++)
3611 if (regs_ever_live[i] && ! call_used_regs[i])
3613 fprintf (file, "\tstx\t%s, [%s+%d]\n",
3614 reg_names[i], base, offset + 4 * n_regs);
3615 if (dwarf2out_do_frame ())
3616 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3623 for (i = low; i < high; i += 2)
3625 if (regs_ever_live[i] && ! call_used_regs[i])
3627 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3629 fprintf (file, "\tstd\t%s, [%s+%d]\n",
3630 reg_names[i], base, offset + 4 * n_regs);
3631 if (dwarf2out_do_frame ())
3633 char *l = dwarf2out_cfi_label ();
3634 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
3635 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
3641 fprintf (file, "\tst\t%s, [%s+%d]\n",
3642 reg_names[i], base, offset + 4 * n_regs);
3643 if (dwarf2out_do_frame ())
3644 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3650 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3652 fprintf (file, "\tst\t%s, [%s+%d]\n",
3653 reg_names[i+1], base, offset + 4 * n_regs + 4);
3654 if (dwarf2out_do_frame ())
3655 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
3664 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3666 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3667 v9 int regs as it simplifies the code. */
3670 restore_regs (file, low, high, base, offset, n_regs)
3679 if (TARGET_ARCH64 && high <= 32)
3681 for (i = low; i < high; i++)
3683 if (regs_ever_live[i] && ! call_used_regs[i])
3684 fprintf (file, "\tldx\t[%s+%d], %s\n",
3685 base, offset + 4 * n_regs, reg_names[i]),
3691 for (i = low; i < high; i += 2)
3693 if (regs_ever_live[i] && ! call_used_regs[i])
3694 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3695 fprintf (file, "\tldd\t[%s+%d], %s\n",
3696 base, offset + 4 * n_regs, reg_names[i]),
3699 fprintf (file, "\tld\t[%s+%d], %s\n",
3700 base, offset + 4 * n_regs, reg_names[i]),
3702 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3703 fprintf (file, "\tld\t[%s+%d], %s\n",
3704 base, offset + 4 * n_regs + 4, reg_names[i+1]),
3711 /* Compute the frame size required by the function. This function is called
3712 during the reload pass and also by output_function_prologue(). */
3715 compute_frame_size (size, leaf_function)
3720 int outgoing_args_size = (current_function_outgoing_args_size
3721 + REG_PARM_STACK_SPACE (current_function_decl));
3723 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3724 even to v9 int regs to be consistent with save_regs/restore_regs. */
3728 for (i = 0; i < 8; i++)
3729 if (regs_ever_live[i] && ! call_used_regs[i])
3734 for (i = 0; i < 8; i += 2)
3735 if ((regs_ever_live[i] && ! call_used_regs[i])
3736 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3740 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3741 if ((regs_ever_live[i] && ! call_used_regs[i])
3742 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3745 /* Set up values for use in `function_epilogue'. */
3746 num_gfregs = n_regs;
3748 if (leaf_function && n_regs == 0
3749 && size == 0 && current_function_outgoing_args_size == 0)
3751 actual_fsize = apparent_fsize = 0;
3755 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3756 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
3757 apparent_fsize += n_regs * 4;
3758 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3761 /* Make sure nothing can clobber our register windows.
3762 If a SAVE must be done, or there is a stack-local variable,
3763 the register window area must be allocated.
3764 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3765 if (leaf_function == 0 || size > 0)
3766 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3768 return SPARC_STACK_ALIGN (actual_fsize);
3771 /* Build a (32 bit) big number in a register. */
3772 /* ??? We may be able to use the set macro here too. */
3775 build_big_number (file, num, reg)
3780 if (num >= 0 || ! TARGET_ARCH64)
3782 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
3783 if ((num & 0x3ff) != 0)
3784 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
3786 else /* num < 0 && TARGET_ARCH64 */
3788 /* Sethi does not sign extend, so we must use a little trickery
3789 to use it for negative numbers. Invert the constant before
3790 loading it in, then use xor immediate to invert the loaded bits
3791 (along with the upper 32 bits) to the desired constant. This
3792 works because the sethi and immediate fields overlap. */
3795 int low = -0x400 + (asize & 0x3FF);
3797 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3798 inv, reg, reg, low, reg);
3802 /* Output any necessary .register pseudo-ops. */
3804 sparc_output_scratch_registers (file)
3805 FILE *file ATTRIBUTE_UNUSED;
3807 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3813 /* Check if %g[2367] were used without
3814 .register being printed for them already. */
3815 for (i = 2; i < 8; i++)
3817 if (regs_ever_live [i]
3818 && ! sparc_hard_reg_printed [i])
3820 sparc_hard_reg_printed [i] = 1;
3821 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
3828 /* This function generates the assembly code for function entry.
3829 FILE is a stdio stream to output the code to.
3830 SIZE is an int: how many units of temporary storage to allocate.
3831 Refer to the array `regs_ever_live' to determine which registers
3832 to save; `regs_ever_live[I]' is nonzero if register number I
3833 is ever used in the function. This macro is responsible for
3834 knowing which registers should not be saved even if used. */
3836 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
3837 of memory. If any fpu reg is used in the function, we allocate
3838 such a block here, at the bottom of the frame, just in case it's needed.
3840 If this function is a leaf procedure, then we may choose not
3841 to do a "save" insn. The decision about whether or not
3842 to do this is made in regclass.c. */
3845 sparc_output_function_prologue (file, size)
3850 sparc_flat_function_prologue (file, size);
3852 sparc_nonflat_function_prologue (file, size,
3853 current_function_uses_only_leaf_regs);
3856 /* Output code for the function prologue. */
3859 sparc_nonflat_function_prologue (file, size, leaf_function)
3864 sparc_output_scratch_registers (file);
3866 /* Need to use actual_fsize, since we are also allocating
3867 space for our callee (and our own register save area). */
3868 actual_fsize = compute_frame_size (size, leaf_function);
3872 frame_base_name = "%sp";
3873 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3877 frame_base_name = "%fp";
3878 frame_base_offset = SPARC_STACK_BIAS;
3881 /* This is only for the human reader. */
3882 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3884 if (actual_fsize == 0)
3886 else if (! leaf_function)
3888 if (actual_fsize <= 4096)
3889 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3890 else if (actual_fsize <= 8192)
3892 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3893 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3897 build_big_number (file, -actual_fsize, "%g1");
3898 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
3901 else /* leaf function */
3903 if (actual_fsize <= 4096)
3904 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3905 else if (actual_fsize <= 8192)
3907 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3908 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3912 build_big_number (file, -actual_fsize, "%g1");
3913 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3917 if (dwarf2out_do_frame () && actual_fsize)
3919 char *label = dwarf2out_cfi_label ();
3921 /* The canonical frame address refers to the top of the frame. */
3922 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3923 : HARD_FRAME_POINTER_REGNUM),
3926 if (! leaf_function)
3928 /* Note the register window save. This tells the unwinder that
3929 it needs to restore the window registers from the previous
3930 frame's window save area at 0(cfa). */
3931 dwarf2out_window_save (label);
3933 /* The return address (-8) is now in %i7. */
3934 dwarf2out_return_reg (label, 31);
3938 /* If doing anything with PIC, do it now. */
3940 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3942 /* Call saved registers are saved just above the outgoing argument area. */
3945 int offset, real_offset, n_regs;
3948 real_offset = -apparent_fsize;
3949 offset = -apparent_fsize + frame_base_offset;
3950 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3952 /* ??? This might be optimized a little as %g1 might already have a
3953 value close enough that a single add insn will do. */
3954 /* ??? Although, all of this is probably only a temporary fix
3955 because if %g1 can hold a function result, then
3956 output_function_epilogue will lose (the result will get
3958 build_big_number (file, offset, "%g1");
3959 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3965 base = frame_base_name;
3968 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3969 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3974 /* Output code to restore any call saved registers. */
3977 output_restore_regs (file, leaf_function)
3979 int leaf_function ATTRIBUTE_UNUSED;
3984 offset = -apparent_fsize + frame_base_offset;
3985 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3987 build_big_number (file, offset, "%g1");
3988 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3994 base = frame_base_name;
3997 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3998 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4001 /* This function generates the assembly code for function exit,
4002 on machines that need it.
4004 The function epilogue should not depend on the current stack pointer!
4005 It should use the frame pointer only. This is mandatory because
4006 of alloca; we also take advantage of it to omit stack adjustments
4007 before returning. */
4010 sparc_output_function_epilogue (file, size)
4015 sparc_flat_function_epilogue (file, size);
4017 sparc_nonflat_function_epilogue (file, size,
4018 current_function_uses_only_leaf_regs);
4021 /* Output code for the function epilogue. */
4024 sparc_nonflat_function_epilogue (file, size, leaf_function)
4026 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
4031 if (current_function_epilogue_delay_list == 0)
4033 /* If code does not drop into the epilogue, we need
4034 do nothing except output pending case vectors.
4036 We have to still output a dummy nop for the sake of
4037 sane backtraces. Otherwise, if the last two instructions
4038 of a function were call foo; dslot; this can make the return
4039 PC of foo (ie. address of call instruction plus 8) point to
4040 the first instruction in the next function. */
4041 rtx insn, last_real_insn;
4043 insn = get_last_insn ();
4045 last_real_insn = prev_real_insn (insn);
4047 && GET_CODE (last_real_insn) == INSN
4048 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4049 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4051 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4052 fputs("\tnop\n", file);
4054 if (GET_CODE (insn) == NOTE)
4055 insn = prev_nonnote_insn (insn);
4056 if (insn && GET_CODE (insn) == BARRIER)
4057 goto output_vectors;
4061 output_restore_regs (file, leaf_function);
4063 /* Work out how to skip the caller's unimp instruction if required. */
4065 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4067 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4069 if (! leaf_function)
4071 if (current_function_calls_eh_return)
4073 if (current_function_epilogue_delay_list)
4075 if (SKIP_CALLERS_UNIMP_P)
4078 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4080 /* If we wound up with things in our delay slot, flush them here. */
4081 else if (current_function_epilogue_delay_list)
4083 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4085 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4087 epilogue_renumber (&delay, 0);
4088 fputs (SKIP_CALLERS_UNIMP_P
4089 ? "\treturn\t%i7+12\n"
4090 : "\treturn\t%i7+8\n", file);
4091 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4098 if (GET_CODE (delay) != SET)
4101 src = SET_SRC (delay);
4102 if (GET_CODE (src) == ASHIFT)
4104 if (XEXP (src, 1) != const1_rtx)
4107 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4111 insn = gen_rtx_PARALLEL (VOIDmode,
4112 gen_rtvec (2, delay,
4113 gen_rtx_RETURN (VOIDmode)));
4114 insn = emit_jump_insn (insn);
4116 sparc_emitting_epilogue = true;
4117 final_scan_insn (insn, file, 1, 0, 1);
4118 sparc_emitting_epilogue = false;
4121 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4122 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4124 fprintf (file, "\t%s\n\trestore\n", ret);
4126 /* All of the following cases are for leaf functions. */
4127 else if (current_function_calls_eh_return)
4129 else if (current_function_epilogue_delay_list)
4131 /* eligible_for_epilogue_delay_slot ensures that if this is a
4132 leaf function, then we will only have insn in the delay slot
4133 if the frame size is zero, thus no adjust for the stack is
4135 if (actual_fsize != 0)
4137 fprintf (file, "\t%s\n", ret);
4138 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4141 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4142 avoid generating confusing assembly language output. */
4143 else if (actual_fsize == 0)
4144 fprintf (file, "\t%s\n\tnop\n", ret);
4145 else if (actual_fsize <= 4096)
4146 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
4147 else if (actual_fsize <= 8192)
4148 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4149 ret, actual_fsize - 4096);
4150 else if ((actual_fsize & 0x3ff) == 0)
4151 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4154 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4155 actual_fsize, actual_fsize, ret);
4158 sparc_output_deferred_case_vectors ();
4161 /* Output a sibling call. */
4164 output_sibcall (insn, call_operand)
4165 rtx insn, call_operand;
4167 int leaf_regs = current_function_uses_only_leaf_regs;
4169 int delay_slot = dbr_sequence_length () > 0;
4173 /* Call to restore global regs might clobber
4174 the delay slot. Instead of checking for this
4175 output the delay slot now. */
4178 rtx delay = NEXT_INSN (insn);
4183 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4184 PATTERN (delay) = gen_blockage ();
4185 INSN_CODE (delay) = -1;
4188 output_restore_regs (asm_out_file, leaf_regs);
4191 operands[0] = call_operand;
4195 #ifdef HAVE_AS_RELAX_OPTION
4196 /* If as and ld are relaxing tail call insns into branch always,
4197 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4198 be optimized. With sethi/jmpl as nor ld has no easy way how to
4199 find out if somebody does not branch between the sethi and jmpl. */
4202 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4206 if ((actual_fsize || ! spare_slot) && delay_slot)
4208 rtx delay = NEXT_INSN (insn);
4213 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4214 PATTERN (delay) = gen_blockage ();
4215 INSN_CODE (delay) = -1;
4220 if (actual_fsize <= 4096)
4221 size = actual_fsize;
4222 else if (actual_fsize <= 8192)
4224 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4225 size = actual_fsize - 4096;
4227 else if ((actual_fsize & 0x3ff) == 0)
4228 fprintf (asm_out_file,
4229 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4233 fprintf (asm_out_file,
4234 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4235 actual_fsize, actual_fsize);
4236 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4241 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4242 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4244 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size);
4245 else if (! delay_slot)
4246 fputs ("\t nop\n", asm_out_file);
4251 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size);
4252 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4253 it into branch if possible. */
4254 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4255 output_asm_insn ("call\t%a0, 0", operands);
4256 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4261 output_asm_insn ("call\t%a0, 0", operands);
4264 rtx delay = NEXT_INSN (insn), pat;
4269 pat = PATTERN (delay);
4270 if (GET_CODE (pat) != SET)
4273 operands[0] = SET_DEST (pat);
4274 pat = SET_SRC (pat);
4275 switch (GET_CODE (pat))
4278 operands[1] = XEXP (pat, 0);
4279 operands[2] = XEXP (pat, 1);
4280 output_asm_insn (" restore %r1, %2, %Y0", operands);
4283 operands[1] = XEXP (pat, 0);
4284 operands[2] = XEXP (pat, 1);
4285 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4288 operands[1] = XEXP (pat, 0);
4289 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4293 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4296 PATTERN (delay) = gen_blockage ();
4297 INSN_CODE (delay) = -1;
4300 fputs ("\t restore\n", asm_out_file);
4304 /* Functions for handling argument passing.
4306 For v8 the first six args are normally in registers and the rest are
4307 pushed. Any arg that starts within the first 6 words is at least
4308 partially passed in a register unless its data type forbids.
4310 For v9, the argument registers are laid out as an array of 16 elements
4311 and arguments are added sequentially. The first 6 int args and up to the
4312 first 16 fp args (depending on size) are passed in regs.
4314 Slot Stack Integral Float Float in structure Double Long Double
4315 ---- ----- -------- ----- ------------------ ------ -----------
4316 15 [SP+248] %f31 %f30,%f31 %d30
4317 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4318 13 [SP+232] %f27 %f26,%f27 %d26
4319 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4320 11 [SP+216] %f23 %f22,%f23 %d22
4321 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4322 9 [SP+200] %f19 %f18,%f19 %d18
4323 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4324 7 [SP+184] %f15 %f14,%f15 %d14
4325 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4326 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4327 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4328 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4329 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4330 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4331 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4333 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4335 Integral arguments are always passed as 64 bit quantities appropriately
4338 Passing of floating point values is handled as follows.
4339 If a prototype is in scope:
4340 If the value is in a named argument (i.e. not a stdarg function or a
4341 value not part of the `...') then the value is passed in the appropriate
4343 If the value is part of the `...' and is passed in one of the first 6
4344 slots then the value is passed in the appropriate int reg.
4345 If the value is part of the `...' and is not passed in one of the first 6
4346 slots then the value is passed in memory.
4347 If a prototype is not in scope:
4348 If the value is one of the first 6 arguments the value is passed in the
4349 appropriate integer reg and the appropriate fp reg.
4350 If the value is not one of the first 6 arguments the value is passed in
4351 the appropriate fp reg and in memory.
4354 /* Maximum number of int regs for args. */
4355 #define SPARC_INT_ARG_MAX 6
4356 /* Maximum number of fp regs for args. */
4357 #define SPARC_FP_ARG_MAX 16
4359 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4361 /* Handle the INIT_CUMULATIVE_ARGS macro.
4362 Initialize a variable CUM of type CUMULATIVE_ARGS
4363 for a call to a function whose data type is FNTYPE.
4364 For a library call, FNTYPE is 0. */
4367 init_cumulative_args (cum, fntype, libname, fndecl)
4368 CUMULATIVE_ARGS *cum;
4370 rtx libname ATTRIBUTE_UNUSED;
4371 tree fndecl ATTRIBUTE_UNUSED;
4374 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4375 cum->libcall_p = fntype == 0;
4378 /* Compute the slot number to pass an argument in.
4379 Returns the slot number or -1 if passing on the stack.
4381 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4382 the preceding args and about the function being called.
4383 MODE is the argument's machine mode.
4384 TYPE is the data type of the argument (as a tree).
4385 This is null for libcalls where that information may
4387 NAMED is nonzero if this argument is a named parameter
4388 (otherwise it is an extra parameter matching an ellipsis).
4389 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4390 *PREGNO records the register number to use if scalar type.
4391 *PPADDING records the amount of padding needed in words. */
4394 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
4395 const CUMULATIVE_ARGS *cum;
4396 enum machine_mode mode;
4403 int regbase = (incoming_p
4404 ? SPARC_INCOMING_INT_ARG_FIRST
4405 : SPARC_OUTGOING_INT_ARG_FIRST);
4406 int slotno = cum->words;
4411 if (type != 0 && TREE_ADDRESSABLE (type))
4414 && type != 0 && mode == BLKmode
4415 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4421 /* MODE is VOIDmode when generating the actual call.
4425 case QImode : case CQImode :
4426 case HImode : case CHImode :
4427 case SImode : case CSImode :
4428 case DImode : case CDImode :
4429 case TImode : case CTImode :
4430 if (slotno >= SPARC_INT_ARG_MAX)
4432 regno = regbase + slotno;
4435 case SFmode : case SCmode :
4436 case DFmode : case DCmode :
4437 case TFmode : case TCmode :
4440 if (slotno >= SPARC_INT_ARG_MAX)
4442 regno = regbase + slotno;
4446 if ((mode == TFmode || mode == TCmode)
4447 && (slotno & 1) != 0)
4448 slotno++, *ppadding = 1;
4449 if (TARGET_FPU && named)
4451 if (slotno >= SPARC_FP_ARG_MAX)
4453 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4459 if (slotno >= SPARC_INT_ARG_MAX)
4461 regno = regbase + slotno;
4467 /* For sparc64, objects requiring 16 byte alignment get it. */
4470 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
4471 slotno++, *ppadding = 1;
4475 || (type && TREE_CODE (type) == UNION_TYPE))
4477 if (slotno >= SPARC_INT_ARG_MAX)
4479 regno = regbase + slotno;
4484 int intregs_p = 0, fpregs_p = 0;
4485 /* The ABI obviously doesn't specify how packed
4486 structures are passed. These are defined to be passed
4487 in int regs if possible, otherwise memory. */
4490 /* First see what kinds of registers we need. */
4491 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4493 if (TREE_CODE (field) == FIELD_DECL)
4495 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4500 if (DECL_PACKED (field))
4504 if (packed_p || !named)
4505 fpregs_p = 0, intregs_p = 1;
4507 /* If all arg slots are filled, then must pass on stack. */
4508 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4510 /* If there are only int args and all int arg slots are filled,
4511 then must pass on stack. */
4512 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4514 /* Note that even if all int arg slots are filled, fp members may
4515 still be passed in regs if such regs are available.
4516 *PREGNO isn't set because there may be more than one, it's up
4517 to the caller to compute them. */
4530 /* Handle recursive register counting for structure field layout. */
4532 struct function_arg_record_value_parms
4534 rtx ret; /* return expression being built. */
4535 int slotno; /* slot number of the argument. */
4536 int named; /* whether the argument is named. */
4537 int regbase; /* regno of the base register. */
4538 int stack; /* 1 if part of the argument is on the stack. */
4539 int intoffset; /* offset of the pending integer field. */
4540 unsigned int nregs; /* number of words passed in registers. */
4543 static void function_arg_record_value_3
4544 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
4545 static void function_arg_record_value_2
4546 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *);
4547 static void function_arg_record_value_1
4548 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *);
4549 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
4551 /* A subroutine of function_arg_record_value. Traverse the structure
4552 recursively and determine how many registers will be required. */
4555 function_arg_record_value_1 (type, startbitpos, parms)
4557 HOST_WIDE_INT startbitpos;
4558 struct function_arg_record_value_parms *parms;
4562 /* The ABI obviously doesn't specify how packed structures are
4563 passed. These are defined to be passed in int regs if possible,
4564 otherwise memory. */
4567 /* We need to compute how many registers are needed so we can
4568 allocate the PARALLEL but before we can do that we need to know
4569 whether there are any packed fields. If there are, int regs are
4570 used regardless of whether there are fp values present. */
4571 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4573 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4580 /* Compute how many registers we need. */
4581 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4583 if (TREE_CODE (field) == FIELD_DECL)
4585 HOST_WIDE_INT bitpos = startbitpos;
4587 if (DECL_SIZE (field) != 0
4588 && host_integerp (bit_position (field), 1))
4589 bitpos += int_bit_position (field);
4591 /* ??? FIXME: else assume zero offset. */
4593 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4594 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
4595 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4596 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4597 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4603 if (parms->intoffset != -1)
4605 int intslots, this_slotno;
4607 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
4609 this_slotno = parms->slotno + parms->intoffset
4612 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
4614 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
4615 /* We need to pass this field on the stack. */
4619 parms->nregs += intslots;
4620 parms->intoffset = -1;
4623 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4624 If it wasn't true we wouldn't be here. */
4626 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4631 if (parms->intoffset == -1)
4632 parms->intoffset = bitpos;
4638 /* A subroutine of function_arg_record_value. Assign the bits of the
4639 structure between parms->intoffset and bitpos to integer registers. */
4642 function_arg_record_value_3 (bitpos, parms)
4643 HOST_WIDE_INT bitpos;
4644 struct function_arg_record_value_parms *parms;
4646 enum machine_mode mode;
4648 unsigned int startbit, endbit;
4649 int this_slotno, intslots, intoffset;
4652 if (parms->intoffset == -1)
4655 intoffset = parms->intoffset;
4656 parms->intoffset = -1;
4658 startbit = intoffset & -BITS_PER_WORD;
4659 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4660 intslots = (endbit - startbit) / BITS_PER_WORD;
4661 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
4663 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4667 /* If this is the trailing part of a word, only load that much into
4668 the register. Otherwise load the whole register. Note that in
4669 the latter case we may pick up unwanted bits. It's not a problem
4670 at the moment but may wish to revisit. */
4672 if (intoffset % BITS_PER_WORD != 0)
4673 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4678 intoffset /= BITS_PER_UNIT;
4681 regno = parms->regbase + this_slotno;
4682 reg = gen_rtx_REG (mode, regno);
4683 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
4684 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4687 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4691 while (intslots > 0);
4694 /* A subroutine of function_arg_record_value. Traverse the structure
4695 recursively and assign bits to floating point registers. Track which
4696 bits in between need integer registers; invoke function_arg_record_value_3
4697 to make that happen. */
4700 function_arg_record_value_2 (type, startbitpos, parms)
4702 HOST_WIDE_INT startbitpos;
4703 struct function_arg_record_value_parms *parms;
4708 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4710 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4717 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4719 if (TREE_CODE (field) == FIELD_DECL)
4721 HOST_WIDE_INT bitpos = startbitpos;
4723 if (DECL_SIZE (field) != 0
4724 && host_integerp (bit_position (field), 1))
4725 bitpos += int_bit_position (field);
4727 /* ??? FIXME: else assume zero offset. */
4729 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4730 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
4731 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4732 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4733 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4739 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
4741 enum machine_mode mode = DECL_MODE (field);
4744 function_arg_record_value_3 (bitpos, parms);
4745 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
4746 + ((mode == SFmode || mode == SCmode)
4747 && (bitpos & 32) != 0);
4750 case SCmode: mode = SFmode; break;
4751 case DCmode: mode = DFmode; break;
4752 case TCmode: mode = TFmode; break;
4755 reg = gen_rtx_REG (mode, regno);
4756 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
4757 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4758 GEN_INT (bitpos / BITS_PER_UNIT));
4760 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4762 regno += GET_MODE_SIZE (mode) / 4;
4763 reg = gen_rtx_REG (mode, regno);
4764 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
4765 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4766 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
4773 if (parms->intoffset == -1)
4774 parms->intoffset = bitpos;
4780 /* Used by function_arg and function_value to implement the complex
4781 conventions of the 64-bit ABI for passing and returning structures.
4782 Return an expression valid as a return value for the two macros
4783 FUNCTION_ARG and FUNCTION_VALUE.
4785 TYPE is the data type of the argument (as a tree).
4786 This is null for libcalls where that information may
4788 MODE is the argument's machine mode.
4789 SLOTNO is the index number of the argument's slot in the parameter array.
4790 NAMED is nonzero if this argument is a named parameter
4791 (otherwise it is an extra parameter matching an ellipsis).
4792 REGBASE is the regno of the base register for the parameter array. */
4795 function_arg_record_value (type, mode, slotno, named, regbase)
4797 enum machine_mode mode;
4798 int slotno, named, regbase;
4800 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4801 struct function_arg_record_value_parms parms;
4804 parms.ret = NULL_RTX;
4805 parms.slotno = slotno;
4806 parms.named = named;
4807 parms.regbase = regbase;
4810 /* Compute how many registers we need. */
4812 parms.intoffset = 0;
4813 function_arg_record_value_1 (type, 0, &parms);
4815 if (parms.intoffset != -1)
4817 unsigned int startbit, endbit;
4818 int intslots, this_slotno;
4820 startbit = parms.intoffset & -BITS_PER_WORD;
4821 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4822 intslots = (endbit - startbit) / BITS_PER_WORD;
4823 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
4825 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
4827 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
4828 /* We need to pass this field on the stack. */
4832 parms.nregs += intslots;
4834 nregs = parms.nregs;
4836 /* Allocate the vector and handle some annoying special cases. */
4839 /* ??? Empty structure has no value? Duh? */
4842 /* Though there's nothing really to store, return a word register
4843 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4844 leads to breakage due to the fact that there are zero bytes to
4846 return gen_rtx_REG (mode, regbase);
4850 /* ??? C++ has structures with no fields, and yet a size. Give up
4851 for now and pass everything back in integer registers. */
4852 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4854 if (nregs + slotno > SPARC_INT_ARG_MAX)
4855 nregs = SPARC_INT_ARG_MAX - slotno;
4860 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
4862 /* If at least one field must be passed on the stack, generate
4863 (parallel [(expr_list (nil) ...) ...]) so that all fields will
4864 also be passed on the stack. We can't do much better because the
4865 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
4866 of structures for which the fields passed exclusively in registers
4867 are not at the beginning of the structure. */
4869 XVECEXP (parms.ret, 0, 0)
4870 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4872 /* Fill in the entries. */
4874 parms.intoffset = 0;
4875 function_arg_record_value_2 (type, 0, &parms);
4876 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
4878 if (parms.nregs != nregs)
4884 /* Handle the FUNCTION_ARG macro.
4885 Determine where to put an argument to a function.
4886 Value is zero to push the argument on the stack,
4887 or a hard register in which to store the argument.
4889 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4890 the preceding args and about the function being called.
4891 MODE is the argument's machine mode.
4892 TYPE is the data type of the argument (as a tree).
4893 This is null for libcalls where that information may
4895 NAMED is nonzero if this argument is a named parameter
4896 (otherwise it is an extra parameter matching an ellipsis).
4897 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4900 function_arg (cum, mode, type, named, incoming_p)
4901 const CUMULATIVE_ARGS *cum;
4902 enum machine_mode mode;
4907 int regbase = (incoming_p
4908 ? SPARC_INCOMING_INT_ARG_FIRST
4909 : SPARC_OUTGOING_INT_ARG_FIRST);
4910 int slotno, regno, padding;
4913 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
4921 reg = gen_rtx_REG (mode, regno);
4925 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4926 but also have the slot allocated for them.
4927 If no prototype is in scope fp values in register slots get passed
4928 in two places, either fp regs and int regs or fp regs and memory. */
4929 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4930 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4931 && SPARC_FP_REG_P (regno))
4933 reg = gen_rtx_REG (mode, regno);
4934 if (cum->prototype_p || cum->libcall_p)
4936 /* "* 2" because fp reg numbers are recorded in 4 byte
4939 /* ??? This will cause the value to be passed in the fp reg and
4940 in the stack. When a prototype exists we want to pass the
4941 value in the reg but reserve space on the stack. That's an
4942 optimization, and is deferred [for a bit]. */
4943 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
4944 return gen_rtx_PARALLEL (mode,
4946 gen_rtx_EXPR_LIST (VOIDmode,
4947 NULL_RTX, const0_rtx),
4948 gen_rtx_EXPR_LIST (VOIDmode,
4952 /* ??? It seems that passing back a register even when past
4953 the area declared by REG_PARM_STACK_SPACE will allocate
4954 space appropriately, and will not copy the data onto the
4955 stack, exactly as we desire.
4957 This is due to locate_and_pad_parm being called in
4958 expand_call whenever reg_parm_stack_space > 0, which
4959 while beneficial to our example here, would seem to be
4960 in error from what had been intended. Ho hum... -- r~ */
4968 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
4972 /* On incoming, we don't need to know that the value
4973 is passed in %f0 and %i0, and it confuses other parts
4974 causing needless spillage even on the simplest cases. */
4978 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
4979 + (regno - SPARC_FP_ARG_FIRST) / 2);
4981 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4982 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
4984 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4988 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4989 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4990 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4994 else if (type && TREE_CODE (type) == RECORD_TYPE)
4996 /* Structures up to 16 bytes in size are passed in arg slots on the
4997 stack and are promoted to registers where possible. */
4999 if (int_size_in_bytes (type) > 16)
5000 abort (); /* shouldn't get here */
5002 return function_arg_record_value (type, mode, slotno, named, regbase);
5004 else if (type && TREE_CODE (type) == UNION_TYPE)
5006 enum machine_mode mode;
5007 int bytes = int_size_in_bytes (type);
5012 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5013 reg = gen_rtx_REG (mode, regno);
5017 /* Scalar or complex int. */
5018 reg = gen_rtx_REG (mode, regno);
5024 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5025 For an arg passed partly in registers and partly in memory,
5026 this is the number of registers used.
5027 For args passed entirely in registers or entirely in memory, zero.
5029 Any arg that starts in the first 6 regs but won't entirely fit in them
5030 needs partial registers on v8. On v9, structures with integer
5031 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5032 values that begin in the last fp reg [where "last fp reg" varies with the
5033 mode] will be split between that reg and memory. */
5036 function_arg_partial_nregs (cum, mode, type, named)
5037 const CUMULATIVE_ARGS *cum;
5038 enum machine_mode mode;
5042 int slotno, regno, padding;
5044 /* We pass 0 for incoming_p here, it doesn't matter. */
5045 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5052 if ((slotno + (mode == BLKmode
5053 ? ROUND_ADVANCE (int_size_in_bytes (type))
5054 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5055 > NPARM_REGS (SImode))
5056 return NPARM_REGS (SImode) - slotno;
5061 if (type && AGGREGATE_TYPE_P (type))
5063 int size = int_size_in_bytes (type);
5064 int align = TYPE_ALIGN (type);
5067 slotno += slotno & 1;
5068 if (size > 8 && size <= 16
5069 && slotno == SPARC_INT_ARG_MAX - 1)
5072 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5073 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5074 && ! (TARGET_FPU && named)))
5076 if (GET_MODE_ALIGNMENT (mode) == 128)
5078 slotno += slotno & 1;
5079 if (slotno == SPARC_INT_ARG_MAX - 2)
5084 if (slotno == SPARC_INT_ARG_MAX - 1)
5088 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5090 if (GET_MODE_ALIGNMENT (mode) == 128)
5091 slotno += slotno & 1;
5092 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5100 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5101 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5102 quad-precision floats by invisible reference.
5103 v9: Aggregates greater than 16 bytes are passed by reference.
5104 For Pascal, also pass arrays by reference. */
5107 function_arg_pass_by_reference (cum, mode, type, named)
5108 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
5109 enum machine_mode mode;
5111 int named ATTRIBUTE_UNUSED;
5115 return ((type && AGGREGATE_TYPE_P (type))
5116 || mode == TFmode || mode == TCmode);
5120 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5121 /* Consider complex values as aggregates, so care for TCmode. */
5122 || GET_MODE_SIZE (mode) > 16
5124 && AGGREGATE_TYPE_P (type)
5125 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5129 /* Handle the FUNCTION_ARG_ADVANCE macro.
5130 Update the data in CUM to advance over an argument
5131 of mode MODE and data type TYPE.
5132 TYPE is null for libcalls where that information may not be available. */
5135 function_arg_advance (cum, mode, type, named)
5136 CUMULATIVE_ARGS *cum;
5137 enum machine_mode mode;
5141 int slotno, regno, padding;
5143 /* We pass 0 for incoming_p here, it doesn't matter. */
5144 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5146 /* If register required leading padding, add it. */
5148 cum->words += padding;
5152 cum->words += (mode != BLKmode
5153 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5154 : ROUND_ADVANCE (int_size_in_bytes (type)));
5158 if (type && AGGREGATE_TYPE_P (type))
5160 int size = int_size_in_bytes (type);
5164 else if (size <= 16)
5166 else /* passed by reference */
5169 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
5173 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5175 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
5179 cum->words += (mode != BLKmode
5180 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5181 : ROUND_ADVANCE (int_size_in_bytes (type)));
5186 /* Handle the FUNCTION_ARG_PADDING macro.
5187 For the 64 bit ABI structs are always stored left shifted in their
5191 function_arg_padding (mode, type)
5192 enum machine_mode mode;
5195 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5198 /* This is the default definition. */
5199 return (! BYTES_BIG_ENDIAN
5202 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5203 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
5204 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5205 ? downward : upward));
5208 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5209 For v9, function return values are subject to the same rules as arguments,
5210 except that up to 32-bytes may be returned in registers. */
5213 function_value (type, mode, incoming_p)
5215 enum machine_mode mode;
5219 int regbase = (incoming_p
5220 ? SPARC_OUTGOING_INT_ARG_FIRST
5221 : SPARC_INCOMING_INT_ARG_FIRST);
5223 if (TARGET_ARCH64 && type)
5225 if (TREE_CODE (type) == RECORD_TYPE)
5227 /* Structures up to 32 bytes in size are passed in registers,
5228 promoted to fp registers where possible. */
5230 if (int_size_in_bytes (type) > 32)
5231 abort (); /* shouldn't get here */
5233 return function_arg_record_value (type, mode, 0, 1, regbase);
5235 else if (AGGREGATE_TYPE_P (type))
5237 /* All other aggregate types are passed in an integer register
5238 in a mode corresponding to the size of the type. */
5239 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5244 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5249 && GET_MODE_CLASS (mode) == MODE_INT
5250 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5251 && type && ! AGGREGATE_TYPE_P (type))
5255 regno = BASE_RETURN_VALUE_REG (mode);
5257 regno = BASE_OUTGOING_VALUE_REG (mode);
5259 return gen_rtx_REG (mode, regno);
5262 /* Do what is necessary for `va_start'. We look at the current function
5263 to determine if stdarg or varargs is used and return the address of
5264 the first unnamed parameter. */
5267 sparc_builtin_saveregs ()
5269 int first_reg = current_function_args_info.words;
5273 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5274 emit_move_insn (gen_rtx_MEM (word_mode,
5275 gen_rtx_PLUS (Pmode,
5277 GEN_INT (FIRST_PARM_OFFSET (0)
5280 gen_rtx_REG (word_mode,
5281 BASE_INCOMING_ARG_REG (word_mode) + regno));
5283 address = gen_rtx_PLUS (Pmode,
5285 GEN_INT (FIRST_PARM_OFFSET (0)
5286 + UNITS_PER_WORD * first_reg));
5291 /* Implement `va_start' for varargs and stdarg. */
5294 sparc_va_start (valist, nextarg)
5298 nextarg = expand_builtin_saveregs ();
5299 std_expand_builtin_va_start (valist, nextarg);
5302 /* Implement `va_arg'. */
5305 sparc_va_arg (valist, type)
5308 HOST_WIDE_INT size, rsize, align;
5313 /* Round up sizeof(type) to a word. */
5314 size = int_size_in_bytes (type);
5315 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5320 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5321 align = 2 * UNITS_PER_WORD;
5323 if (AGGREGATE_TYPE_P (type))
5325 if ((unsigned HOST_WIDE_INT) size > 16)
5328 size = rsize = UNITS_PER_WORD;
5331 /* SPARC v9 ABI states that structures up to 8 bytes in size are
5332 given one 8 byte slot. */
5334 size = rsize = UNITS_PER_WORD;
5341 if (AGGREGATE_TYPE_P (type)
5342 || TYPE_MODE (type) == TFmode
5343 || TYPE_MODE (type) == TCmode)
5346 size = rsize = UNITS_PER_WORD;
5353 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5354 build_int_2 (align - 1, 0)));
5355 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5356 build_int_2 (-align, -1)));
5359 addr = incr = save_expr (incr);
5360 if (BYTES_BIG_ENDIAN && size < rsize)
5362 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5363 build_int_2 (rsize - size, 0)));
5365 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5366 build_int_2 (rsize, 0)));
5368 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5369 TREE_SIDE_EFFECTS (incr) = 1;
5370 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5372 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5374 /* If the address isn't aligned properly for the type,
5375 we may need to copy to a temporary.
5376 FIXME: This is inefficient. Usually we can do this
5379 && TYPE_ALIGN (type) > BITS_PER_WORD
5382 /* FIXME: We really need to specify that the temporary is live
5383 for the whole function because expand_builtin_va_arg wants
5384 the alias set to be get_varargs_alias_set (), but in this
5385 case the alias set is that for TYPE and if the memory gets
5386 reused it will be reused with alias set TYPE. */
5387 rtx tmp = assign_temp (type, 0, 1, 0);
5390 addr_rtx = force_reg (Pmode, addr_rtx);
5391 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5392 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5393 set_mem_align (addr_rtx, BITS_PER_WORD);
5394 tmp = shallow_copy_rtx (tmp);
5395 PUT_MODE (tmp, BLKmode);
5396 set_mem_alias_set (tmp, 0);
5398 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
5400 if (dest_addr != NULL_RTX)
5401 addr_rtx = dest_addr;
5403 addr_rtx = XCEXP (tmp, 0, MEM);
5408 addr_rtx = force_reg (Pmode, addr_rtx);
5409 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5410 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5416 /* Return the string to output a conditional branch to LABEL, which is
5417 the operand number of the label. OP is the conditional expression.
5418 XEXP (OP, 0) is assumed to be a condition code register (integer or
5419 floating point) and its mode specifies what kind of comparison we made.
5421 REVERSED is nonzero if we should reverse the sense of the comparison.
5423 ANNUL is nonzero if we should generate an annulling branch.
5425 NOOP is nonzero if we have to follow this branch by a noop.
5427 INSN, if set, is the insn. */
5430 output_cbranch (op, dest, label, reversed, annul, noop, insn)
5433 int reversed, annul, noop;
5436 static char string[50];
5437 enum rtx_code code = GET_CODE (op);
5438 rtx cc_reg = XEXP (op, 0);
5439 enum machine_mode mode = GET_MODE (cc_reg);
5440 const char *labelno, *branch;
5441 int spaces = 8, far;
5444 /* v9 branches are limited to +-1MB. If it is too far away,
5457 fbne,a,pn %fcc2, .LC29
5465 far = get_attr_length (insn) >= 3;
5468 /* Reversal of FP compares takes care -- an ordered compare
5469 becomes an unordered compare and vice versa. */
5470 if (mode == CCFPmode || mode == CCFPEmode)
5471 code = reverse_condition_maybe_unordered (code);
5473 code = reverse_condition (code);
5476 /* Start by writing the branch condition. */
5477 if (mode == CCFPmode || mode == CCFPEmode)
5528 /* ??? !v9: FP branches cannot be preceded by another floating point
5529 insn. Because there is currently no concept of pre-delay slots,
5530 we can fix this only by always emitting a nop before a floating
5535 strcpy (string, "nop\n\t");
5536 strcat (string, branch);
5549 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5561 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5582 strcpy (string, branch);
5584 spaces -= strlen (branch);
5585 p = strchr (string, '\0');
5587 /* Now add the annulling, the label, and a possible noop. */
5602 if (! far && insn && INSN_ADDRESSES_SET_P ())
5604 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5605 - INSN_ADDRESSES (INSN_UID (insn)));
5606 /* Leave some instructions for "slop". */
5607 if (delta < -260000 || delta >= 260000)
5611 if (mode == CCFPmode || mode == CCFPEmode)
5613 static char v9_fcc_labelno[] = "%%fccX, ";
5614 /* Set the char indicating the number of the fcc reg to use. */
5615 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5616 labelno = v9_fcc_labelno;
5619 if (REGNO (cc_reg) == SPARC_FCC_REG)
5625 else if (mode == CCXmode || mode == CCX_NOOVmode)
5627 labelno = "%%xcc, ";
5633 labelno = "%%icc, ";
5638 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5641 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5651 strcpy (p, labelno);
5652 p = strchr (p, '\0');
5655 strcpy (p, ".+12\n\tnop\n\tb\t");
5662 /* Set the char indicating the number of the operand containing the
5667 strcpy (p, "\n\tnop");
5672 /* Emit a library call comparison between floating point X and Y.
5673 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5674 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5675 values as arguments instead of the TFmode registers themselves,
5676 that's why we cannot call emit_float_lib_cmp. */
5678 sparc_emit_float_lib_cmp (x, y, comparison)
5680 enum rtx_code comparison;
5683 rtx slot0, slot1, result, tem, tem2;
5684 enum machine_mode mode;
5689 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
5693 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
5697 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
5701 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
5705 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
5709 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
5720 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
5730 if (GET_CODE (x) != MEM)
5732 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5733 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
5738 if (GET_CODE (y) != MEM)
5740 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5741 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
5746 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5748 XEXP (slot0, 0), Pmode,
5749 XEXP (slot1, 0), Pmode);
5755 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5757 x, TFmode, y, TFmode);
5763 /* Immediately move the result of the libcall into a pseudo
5764 register so reload doesn't clobber the value if it needs
5765 the return register for a spill reg. */
5766 result = gen_reg_rtx (mode);
5767 emit_move_insn (result, hard_libcall_value (mode));
5772 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
5776 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
5781 emit_cmp_insn (result, const1_rtx,
5782 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
5785 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
5788 tem = gen_reg_rtx (mode);
5790 emit_insn (gen_andsi3 (tem, result, const1_rtx));
5792 emit_insn (gen_anddi3 (tem, result, const1_rtx));
5793 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
5797 tem = gen_reg_rtx (mode);
5799 emit_insn (gen_addsi3 (tem, result, const1_rtx));
5801 emit_insn (gen_adddi3 (tem, result, const1_rtx));
5802 tem2 = gen_reg_rtx (mode);
5804 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
5806 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
5807 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
5813 /* Generate an unsigned DImode to FP conversion. This is the same code
5814 optabs would emit if we didn't have TFmode patterns. */
5817 sparc_emit_floatunsdi (operands)
5820 rtx neglab, donelab, i0, i1, f0, in, out;
5821 enum machine_mode mode;
5824 in = force_reg (DImode, operands[1]);
5825 mode = GET_MODE (out);
5826 neglab = gen_label_rtx ();
5827 donelab = gen_label_rtx ();
5828 i0 = gen_reg_rtx (DImode);
5829 i1 = gen_reg_rtx (DImode);
5830 f0 = gen_reg_rtx (mode);
5832 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
5834 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
5835 emit_jump_insn (gen_jump (donelab));
5838 emit_label (neglab);
5840 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
5841 emit_insn (gen_anddi3 (i1, in, const1_rtx));
5842 emit_insn (gen_iordi3 (i0, i0, i1));
5843 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
5844 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
5846 emit_label (donelab);
5849 /* Return the string to output a conditional branch to LABEL, testing
5850 register REG. LABEL is the operand number of the label; REG is the
5851 operand number of the reg. OP is the conditional expression. The mode
5852 of REG says what kind of comparison we made.
5854 REVERSED is nonzero if we should reverse the sense of the comparison.
5856 ANNUL is nonzero if we should generate an annulling branch.
5858 NOOP is nonzero if we have to follow this branch by a noop. */
5861 output_v9branch (op, dest, reg, label, reversed, annul, noop, insn)
5864 int reversed, annul, noop;
5867 static char string[50];
5868 enum rtx_code code = GET_CODE (op);
5869 enum machine_mode mode = GET_MODE (XEXP (op, 0));
5874 /* branch on register are limited to +-128KB. If it is too far away,
5887 brgez,a,pn %o1, .LC29
5893 ba,pt %xcc, .LC29 */
5895 far = get_attr_length (insn) >= 3;
5897 /* If not floating-point or if EQ or NE, we can just reverse the code. */
5899 code = reverse_condition (code);
5901 /* Only 64 bit versions of these instructions exist. */
5905 /* Start by writing the branch condition. */
5910 strcpy (string, "brnz");
5914 strcpy (string, "brz");
5918 strcpy (string, "brgez");
5922 strcpy (string, "brlz");
5926 strcpy (string, "brlez");
5930 strcpy (string, "brgz");
5937 p = strchr (string, '\0');
5939 /* Now add the annulling, reg, label, and nop. */
5946 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5949 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5954 *p = p < string + 8 ? '\t' : ' ';
5962 int veryfar = 1, delta;
5964 if (INSN_ADDRESSES_SET_P ())
5966 delta = (INSN_ADDRESSES (INSN_UID (dest))
5967 - INSN_ADDRESSES (INSN_UID (insn)));
5968 /* Leave some instructions for "slop". */
5969 if (delta >= -260000 && delta < 260000)
5973 strcpy (p, ".+12\n\tnop\n\t");
5984 strcpy (p, "ba,pt\t%%xcc, ");
5994 strcpy (p, "\n\tnop");
5999 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6000 Such instructions cannot be used in the delay slot of return insn on v9.
6001 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6005 epilogue_renumber (where, test)
6006 register rtx *where;
6009 register const char *fmt;
6011 register enum rtx_code code;
6016 code = GET_CODE (*where);
6021 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6023 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6024 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6032 /* Do not replace the frame pointer with the stack pointer because
6033 it can cause the delayed instruction to load below the stack.
6034 This occurs when instructions like:
6036 (set (reg/i:SI 24 %i0)
6037 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6038 (const_int -20 [0xffffffec])) 0))
6040 are in the return delayed slot. */
6042 if (GET_CODE (XEXP (*where, 0)) == REG
6043 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6044 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6045 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6050 if (SPARC_STACK_BIAS
6051 && GET_CODE (XEXP (*where, 0)) == REG
6052 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6060 fmt = GET_RTX_FORMAT (code);
6062 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6067 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6068 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6071 else if (fmt[i] == 'e'
6072 && epilogue_renumber (&(XEXP (*where, i)), test))
6078 /* Leaf functions and non-leaf functions have different needs. */
6081 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6084 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6086 static const int *const reg_alloc_orders[] = {
6087 reg_leaf_alloc_order,
6088 reg_nonleaf_alloc_order};
6091 order_regs_for_local_alloc ()
6093 static int last_order_nonleaf = 1;
6095 if (regs_ever_live[15] != last_order_nonleaf)
6097 last_order_nonleaf = !last_order_nonleaf;
6098 memcpy ((char *) reg_alloc_order,
6099 (const char *) reg_alloc_orders[last_order_nonleaf],
6100 FIRST_PSEUDO_REGISTER * sizeof (int));
6104 /* Return 1 if REG and MEM are legitimate enough to allow the various
6105 mem<-->reg splits to be run. */
6108 sparc_splitdi_legitimate (reg, mem)
6112 /* Punt if we are here by mistake. */
6113 if (! reload_completed)
6116 /* We must have an offsettable memory reference. */
6117 if (! offsettable_memref_p (mem))
6120 /* If we have legitimate args for ldd/std, we do not want
6121 the split to happen. */
6122 if ((REGNO (reg) % 2) == 0
6123 && mem_min_alignment (mem, 8))
6130 /* Return 1 if x and y are some kind of REG and they refer to
6131 different hard registers. This test is guaranteed to be
6132 run after reload. */
6135 sparc_absnegfloat_split_legitimate (x, y)
6138 if (GET_CODE (x) != REG)
6140 if (GET_CODE (y) != REG)
6142 if (REGNO (x) == REGNO (y))
6147 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6148 This makes them candidates for using ldd and std insns.
6150 Note reg1 and reg2 *must* be hard registers. */
6153 registers_ok_for_ldd_peep (reg1, reg2)
6156 /* We might have been passed a SUBREG. */
6157 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6160 if (REGNO (reg1) % 2 != 0)
6163 /* Integer ldd is deprecated in SPARC V9 */
6164 if (TARGET_V9 && REGNO (reg1) < 32)
6167 return (REGNO (reg1) == REGNO (reg2) - 1);
6170 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6173 This can only happen when addr1 and addr2, the addresses in mem1
6174 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6175 addr1 must also be aligned on a 64-bit boundary.
6177 Also iff dependent_reg_rtx is not null it should not be used to
6178 compute the address for mem1, i.e. we cannot optimize a sequence
6190 But, note that the transformation from:
6195 is perfectly fine. Thus, the peephole2 patterns always pass us
6196 the destination register of the first load, never the second one.
6198 For stores we don't have a similar problem, so dependent_reg_rtx is
6202 mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx)
6203 rtx mem1, mem2, dependent_reg_rtx;
6209 /* The mems cannot be volatile. */
6210 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6213 /* MEM1 should be aligned on a 64-bit boundary. */
6214 if (MEM_ALIGN (mem1) < 64)
6217 addr1 = XEXP (mem1, 0);
6218 addr2 = XEXP (mem2, 0);
6220 /* Extract a register number and offset (if used) from the first addr. */
6221 if (GET_CODE (addr1) == PLUS)
6223 /* If not a REG, return zero. */
6224 if (GET_CODE (XEXP (addr1, 0)) != REG)
6228 reg1 = REGNO (XEXP (addr1, 0));
6229 /* The offset must be constant! */
6230 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6232 offset1 = INTVAL (XEXP (addr1, 1));
6235 else if (GET_CODE (addr1) != REG)
6239 reg1 = REGNO (addr1);
6240 /* This was a simple (mem (reg)) expression. Offset is 0. */
6244 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6245 if (GET_CODE (addr2) != PLUS)
6248 if (GET_CODE (XEXP (addr2, 0)) != REG
6249 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6252 if (reg1 != REGNO (XEXP (addr2, 0)))
6255 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6258 /* The first offset must be evenly divisible by 8 to ensure the
6259 address is 64 bit aligned. */
6260 if (offset1 % 8 != 0)
6263 /* The offset for the second addr must be 4 more than the first addr. */
6264 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6267 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6272 /* Return 1 if reg is a pseudo, or is the first register in
6273 a hard register pair. This makes it a candidate for use in
6274 ldd and std insns. */
6277 register_ok_for_ldd (reg)
6280 /* We might have been passed a SUBREG. */
6281 if (GET_CODE (reg) != REG)
6284 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6285 return (REGNO (reg) % 2 == 0);
6290 /* Print operand X (an rtx) in assembler syntax to file FILE.
6291 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6292 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6295 print_operand (file, x, code)
6303 /* Output a 'nop' if there's nothing for the delay slot. */
6304 if (dbr_sequence_length () == 0)
6305 fputs ("\n\t nop", file);
6308 /* Output an annul flag if there's nothing for the delay slot and we
6309 are optimizing. This is always used with '(' below. */
6310 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6311 this is a dbx bug. So, we only do this when optimizing. */
6312 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6313 Always emit a nop in case the next instruction is a branch. */
6314 if (dbr_sequence_length () == 0
6315 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6319 /* Output a 'nop' if there's nothing for the delay slot and we are
6320 not optimizing. This is always used with '*' above. */
6321 if (dbr_sequence_length () == 0
6322 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6323 fputs ("\n\t nop", file);
6326 /* Output the Embedded Medium/Anywhere code model base register. */
6327 fputs (EMBMEDANY_BASE_REG, file);
6330 /* Print out what we are using as the frame pointer. This might
6331 be %fp, or might be %sp+offset. */
6332 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6333 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
6336 /* Adjust the operand to take into account a RESTORE operation. */
6337 if (GET_CODE (x) == CONST_INT)
6339 else if (GET_CODE (x) != REG)
6340 output_operand_lossage ("invalid %%Y operand");
6341 else if (REGNO (x) < 8)
6342 fputs (reg_names[REGNO (x)], file);
6343 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6344 fputs (reg_names[REGNO (x)-16], file);
6346 output_operand_lossage ("invalid %%Y operand");
6349 /* Print out the low order register name of a register pair. */
6350 if (WORDS_BIG_ENDIAN)
6351 fputs (reg_names[REGNO (x)+1], file);
6353 fputs (reg_names[REGNO (x)], file);
6356 /* Print out the high order register name of a register pair. */
6357 if (WORDS_BIG_ENDIAN)
6358 fputs (reg_names[REGNO (x)], file);
6360 fputs (reg_names[REGNO (x)+1], file);
6363 /* Print out the second register name of a register pair or quad.
6364 I.e., R (%o0) => %o1. */
6365 fputs (reg_names[REGNO (x)+1], file);
6368 /* Print out the third register name of a register quad.
6369 I.e., S (%o0) => %o2. */
6370 fputs (reg_names[REGNO (x)+2], file);
6373 /* Print out the fourth register name of a register quad.
6374 I.e., T (%o0) => %o3. */
6375 fputs (reg_names[REGNO (x)+3], file);
6378 /* Print a condition code register. */
6379 if (REGNO (x) == SPARC_ICC_REG)
6381 /* We don't handle CC[X]_NOOVmode because they're not supposed
6383 if (GET_MODE (x) == CCmode)
6384 fputs ("%icc", file);
6385 else if (GET_MODE (x) == CCXmode)
6386 fputs ("%xcc", file);
6391 /* %fccN register */
6392 fputs (reg_names[REGNO (x)], file);
6395 /* Print the operand's address only. */
6396 output_address (XEXP (x, 0));
6399 /* In this case we need a register. Use %g0 if the
6400 operand is const0_rtx. */
6402 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
6404 fputs ("%g0", file);
6411 switch (GET_CODE (x))
6413 case IOR: fputs ("or", file); break;
6414 case AND: fputs ("and", file); break;
6415 case XOR: fputs ("xor", file); break;
6416 default: output_operand_lossage ("invalid %%A operand");
6421 switch (GET_CODE (x))
6423 case IOR: fputs ("orn", file); break;
6424 case AND: fputs ("andn", file); break;
6425 case XOR: fputs ("xnor", file); break;
6426 default: output_operand_lossage ("invalid %%B operand");
6430 /* These are used by the conditional move instructions. */
6434 enum rtx_code rc = GET_CODE (x);
6438 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6439 if (mode == CCFPmode || mode == CCFPEmode)
6440 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6442 rc = reverse_condition (GET_CODE (x));
6446 case NE: fputs ("ne", file); break;
6447 case EQ: fputs ("e", file); break;
6448 case GE: fputs ("ge", file); break;
6449 case GT: fputs ("g", file); break;
6450 case LE: fputs ("le", file); break;
6451 case LT: fputs ("l", file); break;
6452 case GEU: fputs ("geu", file); break;
6453 case GTU: fputs ("gu", file); break;
6454 case LEU: fputs ("leu", file); break;
6455 case LTU: fputs ("lu", file); break;
6456 case LTGT: fputs ("lg", file); break;
6457 case UNORDERED: fputs ("u", file); break;
6458 case ORDERED: fputs ("o", file); break;
6459 case UNLT: fputs ("ul", file); break;
6460 case UNLE: fputs ("ule", file); break;
6461 case UNGT: fputs ("ug", file); break;
6462 case UNGE: fputs ("uge", file); break;
6463 case UNEQ: fputs ("ue", file); break;
6464 default: output_operand_lossage (code == 'c'
6465 ? "invalid %%c operand"
6466 : "invalid %%C operand");
6471 /* These are used by the movr instruction pattern. */
6475 enum rtx_code rc = (code == 'd'
6476 ? reverse_condition (GET_CODE (x))
6480 case NE: fputs ("ne", file); break;
6481 case EQ: fputs ("e", file); break;
6482 case GE: fputs ("gez", file); break;
6483 case LT: fputs ("lz", file); break;
6484 case LE: fputs ("lez", file); break;
6485 case GT: fputs ("gz", file); break;
6486 default: output_operand_lossage (code == 'd'
6487 ? "invalid %%d operand"
6488 : "invalid %%D operand");
6495 /* Print a sign-extended character. */
6496 int i = trunc_int_for_mode (INTVAL (x), QImode);
6497 fprintf (file, "%d", i);
6502 /* Operand must be a MEM; write its address. */
6503 if (GET_CODE (x) != MEM)
6504 output_operand_lossage ("invalid %%f operand");
6505 output_address (XEXP (x, 0));
6510 /* Print a sign-extended 32-bit value. */
6512 if (GET_CODE(x) == CONST_INT)
6514 else if (GET_CODE(x) == CONST_DOUBLE)
6515 i = CONST_DOUBLE_LOW (x);
6518 output_operand_lossage ("invalid %%s operand");
6521 i = trunc_int_for_mode (i, SImode);
6522 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
6527 /* Do nothing special. */
6531 /* Undocumented flag. */
6532 output_operand_lossage ("invalid operand output code");
6535 if (GET_CODE (x) == REG)
6536 fputs (reg_names[REGNO (x)], file);
6537 else if (GET_CODE (x) == MEM)
6540 /* Poor Sun assembler doesn't understand absolute addressing. */
6541 if (CONSTANT_P (XEXP (x, 0)))
6542 fputs ("%g0+", file);
6543 output_address (XEXP (x, 0));
6546 else if (GET_CODE (x) == HIGH)
6548 fputs ("%hi(", file);
6549 output_addr_const (file, XEXP (x, 0));
6552 else if (GET_CODE (x) == LO_SUM)
6554 print_operand (file, XEXP (x, 0), 0);
6555 if (TARGET_CM_MEDMID)
6556 fputs ("+%l44(", file);
6558 fputs ("+%lo(", file);
6559 output_addr_const (file, XEXP (x, 1));
6562 else if (GET_CODE (x) == CONST_DOUBLE
6563 && (GET_MODE (x) == VOIDmode
6564 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
6566 if (CONST_DOUBLE_HIGH (x) == 0)
6567 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
6568 else if (CONST_DOUBLE_HIGH (x) == -1
6569 && CONST_DOUBLE_LOW (x) < 0)
6570 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
6572 output_operand_lossage ("long long constant not a valid immediate operand");
6574 else if (GET_CODE (x) == CONST_DOUBLE)
6575 output_operand_lossage ("floating point constant not a valid immediate operand");
6576 else { output_addr_const (file, x); }
6579 /* Target hook for assembling integer objects. The sparc version has
6580 special handling for aligned DI-mode objects. */
6583 sparc_assemble_integer (x, size, aligned_p)
6588 /* ??? We only output .xword's for symbols and only then in environments
6589 where the assembler can handle them. */
6590 if (aligned_p && size == 8
6591 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
6595 assemble_integer_with_op ("\t.xword\t", x);
6600 assemble_aligned_integer (4, const0_rtx);
6601 assemble_aligned_integer (4, x);
6605 return default_assemble_integer (x, size, aligned_p);
6608 /* Return the value of a code used in the .proc pseudo-op that says
6609 what kind of result this function returns. For non-C types, we pick
6610 the closest C type. */
6612 #ifndef SHORT_TYPE_SIZE
6613 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6616 #ifndef INT_TYPE_SIZE
6617 #define INT_TYPE_SIZE BITS_PER_WORD
6620 #ifndef LONG_TYPE_SIZE
6621 #define LONG_TYPE_SIZE BITS_PER_WORD
6624 #ifndef LONG_LONG_TYPE_SIZE
6625 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6628 #ifndef FLOAT_TYPE_SIZE
6629 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6632 #ifndef DOUBLE_TYPE_SIZE
6633 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6636 #ifndef LONG_DOUBLE_TYPE_SIZE
6637 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6641 sparc_type_code (type)
6644 register unsigned long qualifiers = 0;
6645 register unsigned shift;
6647 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6648 setting more, since some assemblers will give an error for this. Also,
6649 we must be careful to avoid shifts of 32 bits or more to avoid getting
6650 unpredictable results. */
6652 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
6654 switch (TREE_CODE (type))
6660 qualifiers |= (3 << shift);
6665 qualifiers |= (2 << shift);
6669 case REFERENCE_TYPE:
6671 qualifiers |= (1 << shift);
6675 return (qualifiers | 8);
6678 case QUAL_UNION_TYPE:
6679 return (qualifiers | 9);
6682 return (qualifiers | 10);
6685 return (qualifiers | 16);
6688 /* If this is a range type, consider it to be the underlying
6690 if (TREE_TYPE (type) != 0)
6693 /* Carefully distinguish all the standard types of C,
6694 without messing up if the language is not C. We do this by
6695 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6696 look at both the names and the above fields, but that's redundant.
6697 Any type whose size is between two C types will be considered
6698 to be the wider of the two types. Also, we do not have a
6699 special code to use for "long long", so anything wider than
6700 long is treated the same. Note that we can't distinguish
6701 between "int" and "long" in this code if they are the same
6702 size, but that's fine, since neither can the assembler. */
6704 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
6705 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
6707 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
6708 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
6710 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
6711 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
6714 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
6717 /* If this is a range type, consider it to be the underlying
6719 if (TREE_TYPE (type) != 0)
6722 /* Carefully distinguish all the standard types of C,
6723 without messing up if the language is not C. */
6725 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
6726 return (qualifiers | 6);
6729 return (qualifiers | 7);
6731 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
6732 /* ??? We need to distinguish between double and float complex types,
6733 but I don't know how yet because I can't reach this code from
6734 existing front-ends. */
6735 return (qualifiers | 7); /* Who knows? */
6737 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
6738 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
6739 case FILE_TYPE: /* GNU Pascal FILE type. */
6740 case SET_TYPE: /* GNU Pascal SET type. */
6741 case LANG_TYPE: /* ? */
6745 abort (); /* Not a type! */
6752 /* Nested function support. */
6754 /* Emit RTL insns to initialize the variable parts of a trampoline.
6755 FNADDR is an RTX for the address of the function's pure code.
6756 CXT is an RTX for the static chain value for the function.
6758 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6759 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6760 (to store insns). This is a bit excessive. Perhaps a different
6761 mechanism would be better here.
6763 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6766 sparc_initialize_trampoline (tramp, fnaddr, cxt)
6767 rtx tramp, fnaddr, cxt;
6769 /* SPARC 32 bit trampoline:
6772 sethi %hi(static), %g2
6774 or %g2, %lo(static), %g2
6776 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6777 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6779 #ifdef TRANSFER_FROM_TRAMPOLINE
6780 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6781 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
6785 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
6786 expand_binop (SImode, ior_optab,
6787 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
6788 size_int (10), 0, 1),
6789 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
6790 NULL_RTX, 1, OPTAB_DIRECT));
6793 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6794 expand_binop (SImode, ior_optab,
6795 expand_shift (RSHIFT_EXPR, SImode, cxt,
6796 size_int (10), 0, 1),
6797 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
6798 NULL_RTX, 1, OPTAB_DIRECT));
6801 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6802 expand_binop (SImode, ior_optab,
6803 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
6804 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
6805 NULL_RTX, 1, OPTAB_DIRECT));
6808 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6809 expand_binop (SImode, ior_optab,
6810 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
6811 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
6812 NULL_RTX, 1, OPTAB_DIRECT));
6814 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6815 aligned on a 16 byte boundary so one flush clears it all. */
6816 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
6817 if (sparc_cpu != PROCESSOR_ULTRASPARC
6818 && sparc_cpu != PROCESSOR_ULTRASPARC3)
6819 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
6820 plus_constant (tramp, 8)))));
6823 /* The 64 bit version is simpler because it makes more sense to load the
6824 values as "immediate" data out of the trampoline. It's also easier since
6825 we can read the PC without clobbering a register. */
6828 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
6829 rtx tramp, fnaddr, cxt;
6831 #ifdef TRANSFER_FROM_TRAMPOLINE
6832 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6833 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
6844 emit_move_insn (gen_rtx_MEM (SImode, tramp),
6845 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
6846 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6847 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
6848 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6849 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
6850 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6851 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
6852 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
6853 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
6854 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
6856 if (sparc_cpu != PROCESSOR_ULTRASPARC
6857 && sparc_cpu != PROCESSOR_ULTRASPARC3)
6858 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
6861 /* Subroutines to support a flat (single) register window calling
6864 /* Single-register window sparc stack frames look like:
6866 Before call After call
6867 +-----------------------+ +-----------------------+
6869 mem | caller's temps. | | caller's temps. |
6871 +-----------------------+ +-----------------------+
6873 | arguments on stack. | | arguments on stack. |
6875 +-----------------------+FP+92->+-----------------------+
6876 | 6 words to save | | 6 words to save |
6877 | arguments passed | | arguments passed |
6878 | in registers, even | | in registers, even |
6879 | if not passed. | | if not passed. |
6880 SP+68->+-----------------------+FP+68->+-----------------------+
6881 | 1 word struct addr | | 1 word struct addr |
6882 +-----------------------+FP+64->+-----------------------+
6884 | 16 word reg save area | | 16 word reg save area |
6886 SP->+-----------------------+ FP->+-----------------------+
6888 | fp/alu reg moves |
6889 FP-16->+-----------------------+
6893 +-----------------------+
6895 | fp register save |
6897 +-----------------------+
6899 | gp register save |
6901 +-----------------------+
6903 | alloca allocations |
6905 +-----------------------+
6907 | arguments on stack |
6909 SP+92->+-----------------------+
6911 | arguments passed |
6912 | in registers, even |
6913 low | if not passed. |
6914 memory SP+68->+-----------------------+
6915 | 1 word struct addr |
6916 SP+64->+-----------------------+
6918 I 16 word reg save area |
6920 SP->+-----------------------+ */
6922 /* Structure to be filled in by sparc_flat_compute_frame_size with register
6923 save masks, and offsets for the current function. */
6925 struct sparc_frame_info
6927 unsigned long total_size; /* # bytes that the entire frame takes up. */
6928 unsigned long var_size; /* # bytes that variables take up. */
6929 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6930 unsigned long extra_size; /* # bytes of extra gunk. */
6931 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6932 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6933 unsigned long gmask; /* Mask of saved gp registers. */
6934 unsigned long fmask; /* Mask of saved fp registers. */
6935 unsigned long reg_offset; /* Offset from new sp to store regs. */
6936 int initialized; /* Nonzero if frame size already calculated. */
6939 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6940 struct sparc_frame_info current_frame_info;
6942 /* Zero structure to initialize current_frame_info. */
6943 struct sparc_frame_info zero_frame_info;
6945 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6947 #define RETURN_ADDR_REGNUM 15
6948 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
6949 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6951 #define MUST_SAVE_REGISTER(regno) \
6952 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6953 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
6954 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6956 /* Return the bytes needed to compute the frame pointer from the current
6960 sparc_flat_compute_frame_size (size)
6961 int size; /* # of var. bytes allocated. */
6964 unsigned long total_size; /* # bytes that the entire frame takes up. */
6965 unsigned long var_size; /* # bytes that variables take up. */
6966 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6967 unsigned long extra_size; /* # extra bytes. */
6968 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6969 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6970 unsigned long gmask; /* Mask of saved gp registers. */
6971 unsigned long fmask; /* Mask of saved fp registers. */
6972 unsigned long reg_offset; /* Offset to register save area. */
6973 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
6975 /* This is the size of the 16 word reg save area, 1 word struct addr
6976 area, and 4 word fp/alu register copy area. */
6977 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
6987 if (!leaf_function_p ())
6989 /* Also include the size needed for the 6 parameter registers. */
6990 args_size = current_function_outgoing_args_size + 24;
6992 total_size = var_size + args_size;
6994 /* Calculate space needed for gp registers. */
6995 for (regno = 1; regno <= 31; regno++)
6997 if (MUST_SAVE_REGISTER (regno))
6999 /* If we need to save two regs in a row, ensure there's room to bump
7000 up the address to align it to a doubleword boundary. */
7001 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
7003 if (gp_reg_size % 8 != 0)
7005 gp_reg_size += 2 * UNITS_PER_WORD;
7006 gmask |= 3 << regno;
7012 gp_reg_size += UNITS_PER_WORD;
7013 gmask |= 1 << regno;
7018 /* Calculate space needed for fp registers. */
7019 for (regno = 32; regno <= 63; regno++)
7021 if (regs_ever_live[regno] && !call_used_regs[regno])
7023 fp_reg_size += UNITS_PER_WORD;
7024 fmask |= 1 << (regno - 32);
7031 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
7032 /* Ensure save area is 8 byte aligned if we need it. */
7034 if (need_aligned_p && n != 0)
7036 total_size += 8 - n;
7037 reg_offset += 8 - n;
7039 total_size += gp_reg_size + fp_reg_size;
7042 /* If we must allocate a stack frame at all, we must also allocate
7043 room for register window spillage, so as to be binary compatible
7044 with libraries and operating systems that do not use -mflat. */
7046 total_size += extra_size;
7050 total_size = SPARC_STACK_ALIGN (total_size);
7052 /* Save other computed information. */
7053 current_frame_info.total_size = total_size;
7054 current_frame_info.var_size = var_size;
7055 current_frame_info.args_size = args_size;
7056 current_frame_info.extra_size = extra_size;
7057 current_frame_info.gp_reg_size = gp_reg_size;
7058 current_frame_info.fp_reg_size = fp_reg_size;
7059 current_frame_info.gmask = gmask;
7060 current_frame_info.fmask = fmask;
7061 current_frame_info.reg_offset = reg_offset;
7062 current_frame_info.initialized = reload_completed;
7064 /* Ok, we're done. */
7068 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7071 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7072 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7073 [BASE_REG+OFFSET] will always be a valid address.
7075 WORD_OP is either "st" for save, "ld" for restore.
7076 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7079 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
7080 doubleword_op, base_offset)
7082 const char *base_reg;
7083 unsigned int offset;
7084 unsigned long gmask;
7085 unsigned long fmask;
7086 const char *word_op;
7087 const char *doubleword_op;
7088 unsigned long base_offset;
7092 if (gmask == 0 && fmask == 0)
7095 /* Save registers starting from high to low. We've already saved the
7096 previous frame pointer and previous return address for the debugger's
7097 sake. The debugger allows us to not need a nop in the epilog if at least
7098 one register is reloaded in addition to return address. */
7102 for (regno = 1; regno <= 31; regno++)
7104 if ((gmask & (1L << regno)) != 0)
7106 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7108 /* We can save two registers in a row. If we're not at a
7109 double word boundary, move to one.
7110 sparc_flat_compute_frame_size ensures there's room to do
7112 if (offset % 8 != 0)
7113 offset += UNITS_PER_WORD;
7115 if (word_op[0] == 's')
7117 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7118 doubleword_op, reg_names[regno],
7120 if (dwarf2out_do_frame ())
7122 char *l = dwarf2out_cfi_label ();
7123 dwarf2out_reg_save (l, regno, offset + base_offset);
7125 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7129 fprintf (file, "\t%s\t[%s+%d], %s\n",
7130 doubleword_op, base_reg, offset,
7133 offset += 2 * UNITS_PER_WORD;
7138 if (word_op[0] == 's')
7140 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7141 word_op, reg_names[regno],
7143 if (dwarf2out_do_frame ())
7144 dwarf2out_reg_save ("", regno, offset + base_offset);
7147 fprintf (file, "\t%s\t[%s+%d], %s\n",
7148 word_op, base_reg, offset, reg_names[regno]);
7150 offset += UNITS_PER_WORD;
7158 for (regno = 32; regno <= 63; regno++)
7160 if ((fmask & (1L << (regno - 32))) != 0)
7162 if (word_op[0] == 's')
7164 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7165 word_op, reg_names[regno],
7167 if (dwarf2out_do_frame ())
7168 dwarf2out_reg_save ("", regno, offset + base_offset);
7171 fprintf (file, "\t%s\t[%s+%d], %s\n",
7172 word_op, base_reg, offset, reg_names[regno]);
7174 offset += UNITS_PER_WORD;
7180 /* Set up the stack and frame (if desired) for the function. */
7183 sparc_flat_function_prologue (file, size)
7187 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7188 unsigned long gmask = current_frame_info.gmask;
7190 sparc_output_scratch_registers (file);
7192 /* This is only for the human reader. */
7193 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7194 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7196 current_frame_info.var_size,
7197 current_frame_info.gp_reg_size / 4,
7198 current_frame_info.fp_reg_size / 4,
7199 current_function_outgoing_args_size,
7200 current_frame_info.extra_size);
7202 size = SPARC_STACK_ALIGN (size);
7203 size = (! current_frame_info.initialized
7204 ? sparc_flat_compute_frame_size (size)
7205 : current_frame_info.total_size);
7207 /* These cases shouldn't happen. Catch them now. */
7208 if (size == 0 && (gmask || current_frame_info.fmask))
7211 /* Allocate our stack frame by decrementing %sp.
7212 At present, the only algorithm gdb can use to determine if this is a
7213 flat frame is if we always set %i7 if we set %sp. This can be optimized
7214 in the future by putting in some sort of debugging information that says
7215 this is a `flat' function. However, there is still the case of debugging
7216 code without such debugging information (including cases where most fns
7217 have such info, but there is one that doesn't). So, always do this now
7218 so we don't get a lot of code out there that gdb can't handle.
7219 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7220 distinguish us from a non-flat function but there won't (and shouldn't)
7221 be any differences anyway. The return pc is saved (if necessary) right
7222 after %i7 so gdb won't have to look too far to find it. */
7225 unsigned int reg_offset = current_frame_info.reg_offset;
7226 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7227 static const char *const t1_str = "%g1";
7229 /* Things get a little tricky if local variables take up more than ~4096
7230 bytes and outgoing arguments take up more than ~4096 bytes. When that
7231 happens, the register save area can't be accessed from either end of
7232 the frame. Handle this by decrementing %sp to the start of the gp
7233 register save area, save the regs, update %i7, and then set %sp to its
7234 final value. Given that we only have one scratch register to play
7235 with it is the cheapest solution, and it helps gdb out as it won't
7236 slow down recognition of flat functions.
7237 Don't change the order of insns emitted here without checking with
7238 the gdb folk first. */
7240 /* Is the entire register save area offsettable from %sp? */
7241 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7245 fprintf (file, "\tadd\t%s, %d, %s\n",
7246 sp_str, (int) -size, sp_str);
7247 if (gmask & HARD_FRAME_POINTER_MASK)
7249 fprintf (file, "\tst\t%s, [%s+%d]\n",
7250 fp_str, sp_str, reg_offset);
7251 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7252 sp_str, (int) -size, fp_str, ASM_COMMENT_START);
7258 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7259 ", %s\n\tsub\t%s, %s, %s\n",
7260 size, t1_str, sp_str, t1_str, sp_str);
7261 if (gmask & HARD_FRAME_POINTER_MASK)
7263 fprintf (file, "\tst\t%s, [%s+%d]\n",
7264 fp_str, sp_str, reg_offset);
7265 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7266 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7270 if (dwarf2out_do_frame ())
7272 char *l = dwarf2out_cfi_label ();
7273 if (gmask & HARD_FRAME_POINTER_MASK)
7275 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7276 reg_offset - 4 - size);
7277 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7280 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7282 if (gmask & RETURN_ADDR_MASK)
7284 fprintf (file, "\tst\t%s, [%s+%d]\n",
7285 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7286 if (dwarf2out_do_frame ())
7287 dwarf2out_return_save ("", reg_offset - size);
7290 sparc_flat_save_restore (file, sp_str, reg_offset,
7291 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7292 current_frame_info.fmask,
7293 "st", "std", -size);
7297 /* Subtract %sp in two steps, but make sure there is always a
7298 64 byte register save area, and %sp is properly aligned. */
7299 /* Amount to decrement %sp by, the first time. */
7300 unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7301 /* Offset to register save area from %sp. */
7302 unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset);
7306 fprintf (file, "\tadd\t%s, %d, %s\n",
7307 sp_str, (int) -size1, sp_str);
7308 if (gmask & HARD_FRAME_POINTER_MASK)
7310 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7311 fp_str, sp_str, (int) offset, sp_str, (int) -size1,
7312 fp_str, ASM_COMMENT_START);
7318 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7319 ", %s\n\tsub\t%s, %s, %s\n",
7320 size1, t1_str, sp_str, t1_str, sp_str);
7321 if (gmask & HARD_FRAME_POINTER_MASK)
7323 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7324 fp_str, sp_str, (int) offset, sp_str, t1_str,
7325 fp_str, ASM_COMMENT_START);
7329 if (dwarf2out_do_frame ())
7331 char *l = dwarf2out_cfi_label ();
7332 if (gmask & HARD_FRAME_POINTER_MASK)
7334 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7335 offset - 4 - size1);
7336 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7339 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7341 if (gmask & RETURN_ADDR_MASK)
7343 fprintf (file, "\tst\t%s, [%s+%d]\n",
7344 reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset);
7345 if (dwarf2out_do_frame ())
7346 /* offset - size1 == reg_offset - size
7347 if reg_offset were updated above like offset. */
7348 dwarf2out_return_save ("", offset - size1);
7351 sparc_flat_save_restore (file, sp_str, offset,
7352 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7353 current_frame_info.fmask,
7354 "st", "std", -size1);
7355 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7356 ", %s\n\tsub\t%s, %s, %s\n",
7357 size - size1, t1_str, sp_str, t1_str, sp_str);
7358 if (dwarf2out_do_frame ())
7359 if (! (gmask & HARD_FRAME_POINTER_MASK))
7360 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
7364 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
7367 /* Do any necessary cleanup after a function to restore stack, frame,
7371 sparc_flat_function_epilogue (file, size)
7375 rtx epilogue_delay = current_function_epilogue_delay_list;
7376 int noepilogue = FALSE;
7378 /* This is only for the human reader. */
7379 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
7381 /* The epilogue does not depend on any registers, but the stack
7382 registers, so we assume that if we have 1 pending nop, it can be
7383 ignored, and 2 it must be filled (2 nops occur for integer
7384 multiply and divide). */
7386 size = SPARC_STACK_ALIGN (size);
7387 size = (!current_frame_info.initialized
7388 ? sparc_flat_compute_frame_size (size)
7389 : current_frame_info.total_size);
7391 if (size == 0 && epilogue_delay == 0)
7393 rtx insn = get_last_insn ();
7395 /* If the last insn was a BARRIER, we don't have to write any code
7396 because a jump (aka return) was put there. */
7397 if (GET_CODE (insn) == NOTE)
7398 insn = prev_nonnote_insn (insn);
7399 if (insn && GET_CODE (insn) == BARRIER)
7405 unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset;
7406 unsigned HOST_WIDE_INT size1;
7407 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7408 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7409 static const char *const t1_str = "%g1";
7411 /* In the reload sequence, we don't need to fill the load delay
7412 slots for most of the loads, also see if we can fill the final
7413 delay slot if not otherwise filled by the reload sequence. */
7416 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC ", %s\n",
7419 if (frame_pointer_needed)
7422 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7423 fp_str, t1_str, sp_str, ASM_COMMENT_START);
7425 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
7426 fp_str, (int) size, sp_str, ASM_COMMENT_START);
7429 /* Is the entire register save area offsettable from %sp? */
7430 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7436 /* Restore %sp in two steps, but make sure there is always a
7437 64 byte register save area, and %sp is properly aligned. */
7438 /* Amount to increment %sp by, the first time. */
7439 size1 = ((reg_offset - 64 - 16) + 15) & -16;
7440 /* Offset to register save area from %sp. */
7441 reg_offset = size1 - reg_offset;
7443 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7444 ", %s\n\tadd\t%s, %s, %s\n",
7445 size1, t1_str, sp_str, t1_str, sp_str);
7448 /* We must restore the frame pointer and return address reg first
7449 because they are treated specially by the prologue output code. */
7450 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
7452 fprintf (file, "\tld\t[%s+%d], %s\n",
7453 sp_str, (int) reg_offset, fp_str);
7456 if (current_frame_info.gmask & RETURN_ADDR_MASK)
7458 fprintf (file, "\tld\t[%s+%d], %s\n",
7459 sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]);
7463 /* Restore any remaining saved registers. */
7464 sparc_flat_save_restore (file, sp_str, reg_offset,
7465 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7466 current_frame_info.fmask,
7469 /* If we had to increment %sp in two steps, record it so the second
7470 restoration in the epilogue finishes up. */
7475 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC ", %s\n",
7479 if (current_function_returns_struct)
7480 fprintf (file, "\tjmp\t%%o7+12\n");
7482 fprintf (file, "\tretl\n");
7484 /* If the only register saved is the return address, we need a
7485 nop, unless we have an instruction to put into it. Otherwise
7486 we don't since reloading multiple registers doesn't reference
7487 the register being loaded. */
7493 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
7496 else if (size > 4095)
7497 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7500 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str);
7503 fprintf (file, "\tnop\n");
7506 /* Reset state info for each function. */
7507 current_frame_info = zero_frame_info;
7509 sparc_output_deferred_case_vectors ();
7512 /* Define the number of delay slots needed for the function epilogue.
7514 On the sparc, we need a slot if either no stack has been allocated,
7515 or the only register saved is the return register. */
7518 sparc_flat_epilogue_delay_slots ()
7520 if (!current_frame_info.initialized)
7521 (void) sparc_flat_compute_frame_size (get_frame_size ());
7523 if (current_frame_info.total_size == 0)
7529 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7530 Any single length instruction which doesn't reference the stack or frame
7534 sparc_flat_eligible_for_epilogue_delay (trial, slot)
7536 int slot ATTRIBUTE_UNUSED;
7538 rtx pat = PATTERN (trial);
7540 if (get_attr_length (trial) != 1)
7543 if (! reg_mentioned_p (stack_pointer_rtx, pat)
7544 && ! reg_mentioned_p (frame_pointer_rtx, pat))
7550 /* Adjust the cost of a scheduling dependency. Return the new cost of
7551 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7554 supersparc_adjust_cost (insn, link, dep_insn, cost)
7560 enum attr_type insn_type;
7562 if (! recog_memoized (insn))
7565 insn_type = get_attr_type (insn);
7567 if (REG_NOTE_KIND (link) == 0)
7569 /* Data dependency; DEP_INSN writes a register that INSN reads some
7572 /* if a load, then the dependence must be on the memory address;
7573 add an extra "cycle". Note that the cost could be two cycles
7574 if the reg was written late in an instruction group; we ca not tell
7576 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7579 /* Get the delay only if the address of the store is the dependence. */
7580 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7582 rtx pat = PATTERN(insn);
7583 rtx dep_pat = PATTERN (dep_insn);
7585 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7586 return cost; /* This should not happen! */
7588 /* The dependency between the two instructions was on the data that
7589 is being stored. Assume that this implies that the address of the
7590 store is not dependent. */
7591 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7594 return cost + 3; /* An approximation. */
7597 /* A shift instruction cannot receive its data from an instruction
7598 in the same cycle; add a one cycle penalty. */
7599 if (insn_type == TYPE_SHIFT)
7600 return cost + 3; /* Split before cascade into shift. */
7604 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7605 INSN writes some cycles later. */
7607 /* These are only significant for the fpu unit; writing a fp reg before
7608 the fpu has finished with it stalls the processor. */
7610 /* Reusing an integer register causes no problems. */
7611 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7619 hypersparc_adjust_cost (insn, link, dep_insn, cost)
7625 enum attr_type insn_type, dep_type;
7626 rtx pat = PATTERN(insn);
7627 rtx dep_pat = PATTERN (dep_insn);
7629 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7632 insn_type = get_attr_type (insn);
7633 dep_type = get_attr_type (dep_insn);
7635 switch (REG_NOTE_KIND (link))
7638 /* Data dependency; DEP_INSN writes a register that INSN reads some
7645 /* Get the delay iff the address of the store is the dependence. */
7646 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7649 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7656 /* If a load, then the dependence must be on the memory address. If
7657 the addresses aren't equal, then it might be a false dependency */
7658 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7660 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7661 || GET_CODE (SET_DEST (dep_pat)) != MEM
7662 || GET_CODE (SET_SRC (pat)) != MEM
7663 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7664 XEXP (SET_SRC (pat), 0)))
7672 /* Compare to branch latency is 0. There is no benefit from
7673 separating compare and branch. */
7674 if (dep_type == TYPE_COMPARE)
7676 /* Floating point compare to branch latency is less than
7677 compare to conditional move. */
7678 if (dep_type == TYPE_FPCMP)
7687 /* Anti-dependencies only penalize the fpu unit. */
7688 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7700 sparc_adjust_cost(insn, link, dep, cost)
7708 case PROCESSOR_SUPERSPARC:
7709 cost = supersparc_adjust_cost (insn, link, dep, cost);
7711 case PROCESSOR_HYPERSPARC:
7712 case PROCESSOR_SPARCLITE86X:
7713 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7722 sparc_sched_init (dump, sched_verbose, max_ready)
7723 FILE *dump ATTRIBUTE_UNUSED;
7724 int sched_verbose ATTRIBUTE_UNUSED;
7725 int max_ready ATTRIBUTE_UNUSED;
7730 sparc_use_dfa_pipeline_interface ()
7732 if ((1 << sparc_cpu) &
7733 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
7734 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7735 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
7736 (1 << PROCESSOR_ULTRASPARC3)))
7742 sparc_use_sched_lookahead ()
7744 if (sparc_cpu == PROCESSOR_ULTRASPARC
7745 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7747 if ((1 << sparc_cpu) &
7748 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7749 (1 << PROCESSOR_SPARCLITE86X)))
7762 /* Assume V9 processors are capable of at least dual-issue. */
7764 case PROCESSOR_SUPERSPARC:
7766 case PROCESSOR_HYPERSPARC:
7767 case PROCESSOR_SPARCLITE86X:
7769 case PROCESSOR_ULTRASPARC:
7770 case PROCESSOR_ULTRASPARC3:
7779 register rtx pat = PATTERN (insn);
7781 switch (GET_CODE (SET_SRC (pat)))
7783 /* Load and some shift instructions zero extend. */
7786 /* sethi clears the high bits */
7788 /* LO_SUM is used with sethi. sethi cleared the high
7789 bits and the values used with lo_sum are positive */
7791 /* Store flag stores 0 or 1 */
7801 rtx op0 = XEXP (SET_SRC (pat), 0);
7802 rtx op1 = XEXP (SET_SRC (pat), 1);
7803 if (GET_CODE (op1) == CONST_INT)
7804 return INTVAL (op1) >= 0;
7805 if (GET_CODE (op0) != REG)
7807 if (sparc_check_64 (op0, insn) == 1)
7809 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7814 rtx op0 = XEXP (SET_SRC (pat), 0);
7815 rtx op1 = XEXP (SET_SRC (pat), 1);
7816 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7818 if (GET_CODE (op1) == CONST_INT)
7819 return INTVAL (op1) >= 0;
7820 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7823 return GET_MODE (SET_SRC (pat)) == SImode;
7824 /* Positive integers leave the high bits zero. */
7826 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7828 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7831 return - (GET_MODE (SET_SRC (pat)) == SImode);
7833 return sparc_check_64 (SET_SRC (pat), insn);
7839 /* We _ought_ to have only one kind per function, but... */
7840 static GTY(()) rtx sparc_addr_diff_list;
7841 static GTY(()) rtx sparc_addr_list;
7844 sparc_defer_case_vector (lab, vec, diff)
7848 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7850 sparc_addr_diff_list
7851 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7853 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7857 sparc_output_addr_vec (vec)
7860 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7861 int idx, vlen = XVECLEN (body, 0);
7863 #ifdef ASM_OUTPUT_ADDR_VEC_START
7864 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7867 #ifdef ASM_OUTPUT_CASE_LABEL
7868 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7871 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7874 for (idx = 0; idx < vlen; idx++)
7876 ASM_OUTPUT_ADDR_VEC_ELT
7877 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7880 #ifdef ASM_OUTPUT_ADDR_VEC_END
7881 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7886 sparc_output_addr_diff_vec (vec)
7889 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7890 rtx base = XEXP (XEXP (body, 0), 0);
7891 int idx, vlen = XVECLEN (body, 1);
7893 #ifdef ASM_OUTPUT_ADDR_VEC_START
7894 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7897 #ifdef ASM_OUTPUT_CASE_LABEL
7898 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7901 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7904 for (idx = 0; idx < vlen; idx++)
7906 ASM_OUTPUT_ADDR_DIFF_ELT
7909 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7910 CODE_LABEL_NUMBER (base));
7913 #ifdef ASM_OUTPUT_ADDR_VEC_END
7914 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7919 sparc_output_deferred_case_vectors ()
7924 if (sparc_addr_list == NULL_RTX
7925 && sparc_addr_diff_list == NULL_RTX)
7928 /* Align to cache line in the function's code section. */
7929 function_section (current_function_decl);
7931 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7933 ASM_OUTPUT_ALIGN (asm_out_file, align);
7935 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7936 sparc_output_addr_vec (XEXP (t, 0));
7937 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7938 sparc_output_addr_diff_vec (XEXP (t, 0));
7940 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7943 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7944 unknown. Return 1 if the high bits are zero, -1 if the register is
7947 sparc_check_64 (x, insn)
7950 /* If a register is set only once it is safe to ignore insns this
7951 code does not know how to handle. The loop will either recognize
7952 the single set and return the correct value or fail to recognize
7957 if (GET_CODE (x) != REG)
7960 if (GET_MODE (x) == DImode)
7961 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
7963 if (flag_expensive_optimizations
7964 && REG_N_SETS (REGNO (y)) == 1)
7970 insn = get_last_insn_anywhere ();
7975 while ((insn = PREV_INSN (insn)))
7977 switch (GET_CODE (insn))
7990 rtx pat = PATTERN (insn);
7991 if (GET_CODE (pat) != SET)
7993 if (rtx_equal_p (x, SET_DEST (pat)))
7994 return set_extends (insn);
7995 if (y && rtx_equal_p (y, SET_DEST (pat)))
7996 return set_extends (insn);
7997 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8005 /* Returns assembly code to perform a DImode shift using
8006 a 64-bit global or out register on SPARC-V8+. */
8008 sparc_v8plus_shift (operands, insn, opcode)
8013 static char asm_code[60];
8015 /* The scratch register is only required when the destination
8016 register is not a 64-bit global or out register. */
8017 if (which_alternative != 2)
8018 operands[3] = operands[0];
8020 if (GET_CODE (operands[1]) == CONST_INT)
8022 output_asm_insn ("mov\t%1, %3", operands);
8026 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8027 if (sparc_check_64 (operands[1], insn) <= 0)
8028 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8029 output_asm_insn ("or\t%L1, %3, %3", operands);
8032 strcpy(asm_code, opcode);
8034 if (which_alternative != 2)
8035 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8037 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8040 /* Output rtl to increment the profiler label LABELNO
8041 for profiling a function entry. */
8044 sparc_profile_hook (labelno)
8050 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8051 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8052 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8054 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8057 #ifdef OBJECT_FORMAT_ELF
8059 sparc_elf_asm_named_section (name, flags)
8063 if (flags & SECTION_MERGE)
8065 /* entsize cannot be expressed in this section attributes
8067 default_elf_asm_named_section (name, flags);
8071 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8073 if (!(flags & SECTION_DEBUG))
8074 fputs (",#alloc", asm_out_file);
8075 if (flags & SECTION_WRITE)
8076 fputs (",#write", asm_out_file);
8077 if (flags & SECTION_CODE)
8078 fputs (",#execinstr", asm_out_file);
8080 /* ??? Handle SECTION_BSS. */
8082 fputc ('\n', asm_out_file);
8084 #endif /* OBJECT_FORMAT_ELF */
8086 /* We do not allow sibling calls if -mflat, nor
8087 we do not allow indirect calls to be optimized into sibling calls.
8089 Also, on sparc 32-bit we cannot emit a sibling call when the
8090 current function returns a structure. This is because the "unimp
8091 after call" convention would cause the callee to return to the
8092 wrong place. The generic code already disallows cases where the
8093 function being called returns a structure.
8095 It may seem strange how this last case could occur. Usually there
8096 is code after the call which jumps to epilogue code which dumps the
8097 return value into the struct return area. That ought to invalidate
8098 the sibling call right? Well, in the c++ case we can end up passing
8099 the pointer to the struct return area to a constructor (which returns
8100 void) and then nothing else happens. Such a sibling call would look
8101 valid without the added check here. */
8103 sparc_function_ok_for_sibcall (decl, exp)
8105 tree exp ATTRIBUTE_UNUSED;
8109 && (TARGET_ARCH64 || ! current_function_returns_struct));
8112 /* ??? Similar to the standard section selection, but force reloc-y-ness
8113 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8114 pretending PIC always on), but that's what the old code did. */
8117 sparc_aout_select_section (t, reloc, align)
8120 unsigned HOST_WIDE_INT align;
8122 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
8125 /* Use text section for a constant unless we need more alignment than
8129 sparc_aout_select_rtx_section (mode, x, align)
8130 enum machine_mode mode;
8132 unsigned HOST_WIDE_INT align;
8134 if (align <= MAX_TEXT_ALIGN
8135 && ! (flag_pic && (symbolic_operand (x, mode)
8136 || SUNOS4_SHARED_LIBRARIES)))
8137 readonly_data_section ();
8143 sparc_extra_constraint_check (op, c, strict)
8151 && (c == 'T' || c == 'U'))
8157 return fp_sethi_p (op);
8160 return fp_mov_p (op);
8163 return fp_high_losum_p (op);
8167 || (GET_CODE (op) == REG
8168 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8169 || reg_renumber[REGNO (op)] >= 0)))
8170 return register_ok_for_ldd (op);
8182 /* Our memory extra constraints have to emulate the
8183 behavior of 'm' and 'o' in order for reload to work
8185 if (GET_CODE (op) == MEM)
8188 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8190 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8195 reload_ok_mem = (reload_in_progress
8196 && GET_CODE (op) == REG
8197 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8198 && reg_renumber [REGNO (op)] < 0);
8201 return reload_ok_mem;
8204 /* ??? This duplicates information provided to the compiler by the
8205 ??? scheduler description. Some day, teach genautomata to output
8206 ??? the latencies and then CSE will just use that. */
8209 sparc_rtx_costs (x, code, outer_code, total)
8211 int code, outer_code, *total;
8215 case PLUS: case MINUS: case ABS: case NEG:
8216 case FLOAT: case UNSIGNED_FLOAT:
8217 case FIX: case UNSIGNED_FIX:
8218 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8219 if (FLOAT_MODE_P (GET_MODE (x)))
8223 case PROCESSOR_ULTRASPARC:
8224 case PROCESSOR_ULTRASPARC3:
8225 *total = COSTS_N_INSNS (4);
8228 case PROCESSOR_SUPERSPARC:
8229 *total = COSTS_N_INSNS (3);
8232 case PROCESSOR_CYPRESS:
8233 *total = COSTS_N_INSNS (5);
8236 case PROCESSOR_HYPERSPARC:
8237 case PROCESSOR_SPARCLITE86X:
8239 *total = COSTS_N_INSNS (1);
8244 *total = COSTS_N_INSNS (1);
8250 case PROCESSOR_ULTRASPARC:
8251 if (GET_MODE (x) == SFmode)
8252 *total = COSTS_N_INSNS (13);
8254 *total = COSTS_N_INSNS (23);
8257 case PROCESSOR_ULTRASPARC3:
8258 if (GET_MODE (x) == SFmode)
8259 *total = COSTS_N_INSNS (20);
8261 *total = COSTS_N_INSNS (29);
8264 case PROCESSOR_SUPERSPARC:
8265 *total = COSTS_N_INSNS (12);
8268 case PROCESSOR_CYPRESS:
8269 *total = COSTS_N_INSNS (63);
8272 case PROCESSOR_HYPERSPARC:
8273 case PROCESSOR_SPARCLITE86X:
8274 *total = COSTS_N_INSNS (17);
8278 *total = COSTS_N_INSNS (30);
8283 if (FLOAT_MODE_P (GET_MODE (x)))
8287 case PROCESSOR_ULTRASPARC:
8288 case PROCESSOR_ULTRASPARC3:
8289 *total = COSTS_N_INSNS (1);
8292 case PROCESSOR_SUPERSPARC:
8293 *total = COSTS_N_INSNS (3);
8296 case PROCESSOR_CYPRESS:
8297 *total = COSTS_N_INSNS (5);
8300 case PROCESSOR_HYPERSPARC:
8301 case PROCESSOR_SPARCLITE86X:
8303 *total = COSTS_N_INSNS (1);
8308 /* ??? Maybe mark integer compares as zero cost on
8309 ??? all UltraSPARC processors because the result
8310 ??? can be bypassed to a branch in the same group. */
8312 *total = COSTS_N_INSNS (1);
8316 if (FLOAT_MODE_P (GET_MODE (x)))
8320 case PROCESSOR_ULTRASPARC:
8321 case PROCESSOR_ULTRASPARC3:
8322 *total = COSTS_N_INSNS (4);
8325 case PROCESSOR_SUPERSPARC:
8326 *total = COSTS_N_INSNS (3);
8329 case PROCESSOR_CYPRESS:
8330 *total = COSTS_N_INSNS (7);
8333 case PROCESSOR_HYPERSPARC:
8334 case PROCESSOR_SPARCLITE86X:
8335 *total = COSTS_N_INSNS (1);
8339 *total = COSTS_N_INSNS (5);
8344 /* The latency is actually variable for Ultra-I/II
8345 And if one of the inputs have a known constant
8346 value, we could calculate this precisely.
8348 However, for that to be useful we would need to
8349 add some machine description changes which would
8350 make sure small constants ended up in rs1 of the
8351 multiply instruction. This is because the multiply
8352 latency is determined by the number of clear (or
8353 set if the value is negative) bits starting from
8354 the most significant bit of the first input.
8356 The algorithm for computing num_cycles of a multiply
8360 highest_bit = highest_clear_bit(rs1);
8362 highest_bit = highest_set_bit(rs1);
8365 num_cycles = 4 + ((highest_bit - 3) / 2);
8367 If we did that we would have to also consider register
8368 allocation issues that would result from forcing such
8369 a value into a register.
8371 There are other similar tricks we could play if we
8372 knew, for example, that one input was an array index.
8374 Since we do not play any such tricks currently the
8375 safest thing to do is report the worst case latency. */
8376 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8378 *total = (GET_MODE (x) == DImode
8379 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8383 /* Multiply latency on Ultra-III, fortunately, is constant. */
8384 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8386 *total = COSTS_N_INSNS (6);
8390 if (sparc_cpu == PROCESSOR_HYPERSPARC
8391 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8393 *total = COSTS_N_INSNS (17);
8397 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
8404 if (FLOAT_MODE_P (GET_MODE (x)))
8408 case PROCESSOR_ULTRASPARC:
8409 if (GET_MODE (x) == SFmode)
8410 *total = COSTS_N_INSNS (13);
8412 *total = COSTS_N_INSNS (23);
8415 case PROCESSOR_ULTRASPARC3:
8416 if (GET_MODE (x) == SFmode)
8417 *total = COSTS_N_INSNS (17);
8419 *total = COSTS_N_INSNS (20);
8422 case PROCESSOR_SUPERSPARC:
8423 if (GET_MODE (x) == SFmode)
8424 *total = COSTS_N_INSNS (6);
8426 *total = COSTS_N_INSNS (9);
8429 case PROCESSOR_HYPERSPARC:
8430 case PROCESSOR_SPARCLITE86X:
8431 if (GET_MODE (x) == SFmode)
8432 *total = COSTS_N_INSNS (8);
8434 *total = COSTS_N_INSNS (12);
8438 *total = COSTS_N_INSNS (7);
8443 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8444 *total = (GET_MODE (x) == DImode
8445 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8446 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8447 *total = (GET_MODE (x) == DImode
8448 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8450 *total = COSTS_N_INSNS (25);
8454 /* Conditional moves. */
8457 case PROCESSOR_ULTRASPARC:
8458 *total = COSTS_N_INSNS (2);
8461 case PROCESSOR_ULTRASPARC3:
8462 if (FLOAT_MODE_P (GET_MODE (x)))
8463 *total = COSTS_N_INSNS (3);
8465 *total = COSTS_N_INSNS (2);
8469 *total = COSTS_N_INSNS (1);
8474 /* If outer-code is SIGN/ZERO extension we have to subtract
8475 out COSTS_N_INSNS (1) from whatever we return in determining
8479 case PROCESSOR_ULTRASPARC:
8480 if (outer_code == ZERO_EXTEND)
8481 *total = COSTS_N_INSNS (1);
8483 *total = COSTS_N_INSNS (2);
8486 case PROCESSOR_ULTRASPARC3:
8487 if (outer_code == ZERO_EXTEND)
8489 if (GET_MODE (x) == QImode
8490 || GET_MODE (x) == HImode
8491 || outer_code == SIGN_EXTEND)
8492 *total = COSTS_N_INSNS (2);
8494 *total = COSTS_N_INSNS (1);
8498 /* This handles sign extension (3 cycles)
8499 and everything else (2 cycles). */
8500 *total = COSTS_N_INSNS (2);
8504 case PROCESSOR_SUPERSPARC:
8505 if (FLOAT_MODE_P (GET_MODE (x))
8506 || outer_code == ZERO_EXTEND
8507 || outer_code == SIGN_EXTEND)
8508 *total = COSTS_N_INSNS (0);
8510 *total = COSTS_N_INSNS (1);
8513 case PROCESSOR_TSC701:
8514 if (outer_code == ZERO_EXTEND
8515 || outer_code == SIGN_EXTEND)
8516 *total = COSTS_N_INSNS (2);
8518 *total = COSTS_N_INSNS (3);
8521 case PROCESSOR_CYPRESS:
8522 if (outer_code == ZERO_EXTEND
8523 || outer_code == SIGN_EXTEND)
8524 *total = COSTS_N_INSNS (1);
8526 *total = COSTS_N_INSNS (2);
8529 case PROCESSOR_HYPERSPARC:
8530 case PROCESSOR_SPARCLITE86X:
8532 if (outer_code == ZERO_EXTEND
8533 || outer_code == SIGN_EXTEND)
8534 *total = COSTS_N_INSNS (0);
8536 *total = COSTS_N_INSNS (1);
8541 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8559 if (GET_MODE (x) == DImode
8560 && ((XINT (x, 3) == 0
8561 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8562 || (XINT (x, 3) == -1
8564 && XINT (x, 2) >= -0x1000)))
8575 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8576 Used for C++ multiple inheritance. */
8579 sparc_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
8581 tree thunk_fndecl ATTRIBUTE_UNUSED;
8582 HOST_WIDE_INT delta;
8583 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
8586 rtx this, insn, funexp, delta_rtx, tmp;
8588 reload_completed = 1;
8589 epilogue_completed = 1;
8591 current_function_uses_only_leaf_regs = 1;
8593 emit_note (NOTE_INSN_PROLOGUE_END);
8595 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8596 returns a structure, the structure return pointer is there instead. */
8597 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
8598 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
8600 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
8602 /* Add DELTA. When possible use a plain add, otherwise load it into
8603 a register first. */
8604 delta_rtx = GEN_INT (delta);
8605 if (!SPARC_SIMM13_P (delta))
8607 rtx scratch = gen_rtx_REG (Pmode, 1);
8609 sparc_emit_set_const64 (scratch, delta_rtx);
8611 sparc_emit_set_const32 (scratch, delta_rtx);
8612 delta_rtx = scratch;
8615 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
8616 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
8618 /* Generate a tail call to the target function. */
8619 if (! TREE_USED (function))
8621 assemble_external (function);
8622 TREE_USED (function) = 1;
8624 funexp = XEXP (DECL_RTL (function), 0);
8625 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8626 insn = emit_call_insn (gen_sibcall (funexp));
8627 SIBLING_CALL_P (insn) = 1;
8630 /* Run just enough of rest_of_compilation to get the insns emitted.
8631 There's not really enough bulk here to make other passes such as
8632 instruction scheduling worth while. Note that use_thunk calls
8633 assemble_start_function and assemble_end_function. */
8634 insn = get_insns ();
8635 insn_locators_initialize ();
8636 shorten_branches (insn);
8637 final_start_function (insn, file, 1);
8638 final (insn, file, 1, 0);
8639 final_end_function ();
8641 reload_completed = 0;
8642 epilogue_completed = 0;
8646 #include "gt-sparc.h"