1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-flags.h"
36 #include "insn-attr.h"
45 /* 1 if the caller has placed an "unimp" insn immediately after the call.
46 This is used in v8 code when calling a function that returns a structure.
47 v9 doesn't have this. Be careful to have this test be the same as that
50 #define SKIP_CALLERS_UNIMP_P \
51 (!TARGET_ARCH64 && current_function_returns_struct \
52 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
53 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
56 /* Global variables for machine-dependent things. */
58 /* Size of frame. Need to know this to emit return insns from leaf procedures.
59 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
60 reload pass. This is important as the value is later used in insn
61 scheduling (to see what can go in a delay slot).
62 APPARENT_FSIZE is the size of the stack less the register save area and less
63 the outgoing argument area. It is used when saving call preserved regs. */
64 static int apparent_fsize;
65 static int actual_fsize;
67 /* Number of live general or floating point registers needed to be saved
68 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
69 static int num_gfregs;
71 /* Save the operands last given to a compare for use when we
72 generate a scc or bcc insn. */
74 rtx sparc_compare_op0, sparc_compare_op1;
76 /* We may need an epilogue if we spill too many registers.
77 If this is non-zero, then we branch here for the epilogue. */
78 static rtx leaf_label;
82 /* Vector to say how input registers are mapped to output
83 registers. FRAME_POINTER_REGNUM cannot be remapped by
84 this function to eliminate it. You must use -fomit-frame-pointer
86 char leaf_reg_remap[] =
87 { 0, 1, 2, 3, 4, 5, 6, 7,
88 -1, -1, -1, -1, -1, -1, 14, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1,
90 8, 9, 10, 11, 12, 13, -1, 15,
92 32, 33, 34, 35, 36, 37, 38, 39,
93 40, 41, 42, 43, 44, 45, 46, 47,
94 48, 49, 50, 51, 52, 53, 54, 55,
95 56, 57, 58, 59, 60, 61, 62, 63,
96 64, 65, 66, 67, 68, 69, 70, 71,
97 72, 73, 74, 75, 76, 77, 78, 79,
98 80, 81, 82, 83, 84, 85, 86, 87,
99 88, 89, 90, 91, 92, 93, 94, 95,
100 96, 97, 98, 99, 100};
102 /* Vector, indexed by hard register number, which contains 1
103 for a register that is allowable in a candidate for leaf
104 function treatment. */
105 char sparc_leaf_regs[] =
106 { 1, 1, 1, 1, 1, 1, 1, 1,
107 0, 0, 0, 0, 0, 0, 1, 0,
108 0, 0, 0, 0, 0, 0, 0, 0,
109 1, 1, 1, 1, 1, 1, 0, 1,
110 1, 1, 1, 1, 1, 1, 1, 1,
111 1, 1, 1, 1, 1, 1, 1, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
122 /* Name of where we pretend to think the frame pointer points.
123 Normally, this is "%fp", but if we are in a leaf procedure,
124 this is "%sp+something". We record "something" separately as it may be
125 too big for reg+constant addressing. */
127 static const char *frame_base_name;
128 static int frame_base_offset;
130 static void sparc_init_modes PARAMS ((void));
131 static int save_regs PARAMS ((FILE *, int, int, const char *,
133 static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int));
134 static void build_big_number PARAMS ((FILE *, int, const char *));
135 static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *,
136 enum machine_mode, tree, int, int,
139 static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
140 static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
141 static int ultrasparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
143 static void sparc_output_addr_vec PARAMS ((rtx));
144 static void sparc_output_addr_diff_vec PARAMS ((rtx));
145 static void sparc_output_deferred_case_vectors PARAMS ((void));
146 static void sparc_add_gc_roots PARAMS ((void));
147 static void mark_ultrasparc_pipeline_state PARAMS ((void *));
148 static int check_return_regs PARAMS ((rtx));
149 static int epilogue_renumber PARAMS ((rtx *, int));
150 static int ultra_cmove_results_ready_p PARAMS ((rtx));
151 static int ultra_fpmode_conflict_exists PARAMS ((enum machine_mode));
152 static rtx *ultra_find_type PARAMS ((int, rtx *, int));
153 static void ultra_build_types_avail PARAMS ((rtx *, int));
154 static void ultra_flush_pipeline PARAMS ((void));
155 static void ultra_rescan_pipeline_state PARAMS ((rtx *, int));
156 static int set_extends PARAMS ((rtx));
157 static void output_restore_regs PARAMS ((FILE *, int));
159 /* Option handling. */
161 /* Code model option as passed by user. */
162 const char *sparc_cmodel_string;
164 enum cmodel sparc_cmodel;
166 char sparc_hard_reg_printed[8];
168 struct sparc_cpu_select sparc_select[] =
170 /* switch name, tune arch */
171 { (char *)0, "default", 1, 1 },
172 { (char *)0, "-mcpu=", 1, 1 },
173 { (char *)0, "-mtune=", 1, 0 },
177 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
178 enum processor_type sparc_cpu;
180 /* Validate and override various options, and do some machine dependent
184 sparc_override_options ()
186 static struct code_model {
191 { "medlow", CM_MEDLOW },
192 { "medmid", CM_MEDMID },
193 { "medany", CM_MEDANY },
194 { "embmedany", CM_EMBMEDANY },
197 struct code_model *cmodel;
198 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
199 static struct cpu_default {
203 /* There must be one entry here for each TARGET_CPU value. */
204 { TARGET_CPU_sparc, "cypress" },
205 { TARGET_CPU_sparclet, "tsc701" },
206 { TARGET_CPU_sparclite, "f930" },
207 { TARGET_CPU_v8, "v8" },
208 { TARGET_CPU_hypersparc, "hypersparc" },
209 { TARGET_CPU_sparclite86x, "sparclite86x" },
210 { TARGET_CPU_supersparc, "supersparc" },
211 { TARGET_CPU_v9, "v9" },
212 { TARGET_CPU_ultrasparc, "ultrasparc" },
215 struct cpu_default *def;
216 /* Table of values for -m{cpu,tune}=. */
217 static struct cpu_table {
219 enum processor_type processor;
223 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
224 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
225 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
226 /* TI TMS390Z55 supersparc */
227 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
228 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
229 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
230 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
231 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
232 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
233 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
234 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
236 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
238 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
239 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
240 /* TI ultrasparc I, II, IIi */
241 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
242 /* Although insns using %y are deprecated, it is a clear win on current
244 |MASK_DEPRECATED_V8_INSNS},
247 struct cpu_table *cpu;
248 struct sparc_cpu_select *sel;
251 #ifndef SPARC_BI_ARCH
252 /* Check for unsupported architecture size. */
253 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
254 error ("%s is not supported by this configuration",
255 DEFAULT_ARCH32_P ? "-m64" : "-m32");
258 /* We force all 64bit archs to use 128 bit long double */
259 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
261 error ("-mlong-double-64 not allowed with -m64");
262 target_flags |= MASK_LONG_DOUBLE_128;
265 /* Code model selection. */
266 sparc_cmodel = SPARC_DEFAULT_CMODEL;
270 sparc_cmodel = CM_32;
273 if (sparc_cmodel_string != NULL)
277 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
278 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
280 if (cmodel->name == NULL)
281 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
283 sparc_cmodel = cmodel->value;
286 error ("-mcmodel= is not supported on 32 bit systems");
289 fpu = TARGET_FPU; /* save current -mfpu status */
291 /* Set the default CPU. */
292 for (def = &cpu_default[0]; def->name; ++def)
293 if (def->cpu == TARGET_CPU_DEFAULT)
297 sparc_select[0].string = def->name;
299 for (sel = &sparc_select[0]; sel->name; ++sel)
303 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
304 if (! strcmp (sel->string, cpu->name))
307 sparc_cpu = cpu->processor;
311 target_flags &= ~cpu->disable;
312 target_flags |= cpu->enable;
318 error ("bad value (%s) for %s switch", sel->string, sel->name);
322 /* If -mfpu or -mno-fpu was explicitly used, don't override with
323 the processor default. Clear MASK_FPU_SET to avoid confusing
324 the reverse mapping from switch values to names. */
327 target_flags = (target_flags & ~MASK_FPU) | fpu;
328 target_flags &= ~MASK_FPU_SET;
331 /* Don't allow -mvis if FPU is disabled. */
333 target_flags &= ~MASK_VIS;
335 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
337 -m64 also implies v9. */
338 if (TARGET_VIS || TARGET_ARCH64)
339 target_flags |= MASK_V9;
341 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
342 if (TARGET_V9 && TARGET_ARCH32)
343 target_flags |= MASK_DEPRECATED_V8_INSNS;
345 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
346 if (! TARGET_V9 || TARGET_ARCH64)
347 target_flags &= ~MASK_V8PLUS;
349 /* Don't use stack biasing in 32 bit mode. */
351 target_flags &= ~MASK_STACK_BIAS;
353 /* Supply a default value for align_functions. */
354 if (align_functions == 0 && sparc_cpu == PROCESSOR_ULTRASPARC)
355 align_functions = 32;
357 /* Validate PCC_STRUCT_RETURN. */
358 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
359 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
361 /* Do various machine dependent initializations. */
364 if ((profile_flag || profile_block_flag)
365 && sparc_cmodel != CM_32 && sparc_cmodel != CM_MEDLOW)
367 error ("profiling does not support code models other than medlow");
370 /* Register global variables with the garbage collector. */
371 sparc_add_gc_roots ();
374 /* Miscellaneous utilities. */
376 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
377 or branch on register contents instructions. */
383 return (code == EQ || code == NE || code == GE || code == LT
384 || code == LE || code == GT);
388 /* Operand constraints. */
390 /* Return non-zero only if OP is a register of mode MODE,
394 reg_or_0_operand (op, mode)
396 enum machine_mode mode;
398 if (register_operand (op, mode))
400 if (op == const0_rtx)
402 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
403 && CONST_DOUBLE_HIGH (op) == 0
404 && CONST_DOUBLE_LOW (op) == 0)
406 if (fp_zero_operand (op, mode))
411 /* Nonzero if OP is a floating point value with value 0.0. */
414 fp_zero_operand (op, mode)
416 enum machine_mode mode;
418 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
420 return op == CONST0_RTX (mode);
423 /* Nonzero if OP is a floating point constant which can
424 be loaded into an integer register using a single
425 sethi instruction. */
431 if (GET_CODE (op) == CONST_DOUBLE)
436 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
437 if (REAL_VALUES_EQUAL (r, dconst0) &&
438 ! REAL_VALUE_MINUS_ZERO (r))
440 REAL_VALUE_TO_TARGET_SINGLE (r, i);
441 if (SPARC_SETHI_P (i))
448 /* Nonzero if OP is a floating point constant which can
449 be loaded into an integer register using a single
456 if (GET_CODE (op) == CONST_DOUBLE)
461 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
462 if (REAL_VALUES_EQUAL (r, dconst0) &&
463 ! REAL_VALUE_MINUS_ZERO (r))
465 REAL_VALUE_TO_TARGET_SINGLE (r, i);
466 if (SPARC_SIMM13_P (i))
473 /* Nonzero if OP is a floating point constant which can
474 be loaded into an integer register using a high/losum
475 instruction sequence. */
481 /* The constraints calling this should only be in
482 SFmode move insns, so any constant which cannot
483 be moved using a single insn will do. */
484 if (GET_CODE (op) == CONST_DOUBLE)
489 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
490 if (REAL_VALUES_EQUAL (r, dconst0) &&
491 ! REAL_VALUE_MINUS_ZERO (r))
493 REAL_VALUE_TO_TARGET_SINGLE (r, i);
494 if (! SPARC_SETHI_P (i)
495 && ! SPARC_SIMM13_P (i))
502 /* Nonzero if OP is an integer register. */
505 intreg_operand (op, mode)
507 enum machine_mode mode ATTRIBUTE_UNUSED;
509 return (register_operand (op, SImode)
510 || (TARGET_ARCH64 && register_operand (op, DImode)));
513 /* Nonzero if OP is a floating point condition code register. */
516 fcc_reg_operand (op, mode)
518 enum machine_mode mode;
520 /* This can happen when recog is called from combine. Op may be a MEM.
521 Fail instead of calling abort in this case. */
522 if (GET_CODE (op) != REG)
525 if (mode != VOIDmode && mode != GET_MODE (op))
528 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
531 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
532 if (reg_renumber == 0)
533 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
534 return REGNO_OK_FOR_CCFP_P (REGNO (op));
536 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
540 /* Nonzero if OP is an integer or floating point condition code register. */
543 icc_or_fcc_reg_operand (op, mode)
545 enum machine_mode mode;
547 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
549 if (mode != VOIDmode && mode != GET_MODE (op))
552 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
557 return fcc_reg_operand (op, mode);
560 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
562 restore_operand (op, mode)
564 enum machine_mode mode;
566 return (GET_CODE (op) == REG && GET_MODE (op) == mode
567 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
570 /* Call insn on SPARC can take a PC-relative constant address, or any regular
574 call_operand (op, mode)
576 enum machine_mode mode;
578 if (GET_CODE (op) != MEM)
581 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
585 call_operand_address (op, mode)
587 enum machine_mode mode;
589 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
592 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
593 reference and a constant. */
596 symbolic_operand (op, mode)
598 enum machine_mode mode;
600 enum machine_mode omode = GET_MODE (op);
602 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
605 switch (GET_CODE (op))
613 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
614 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
615 && GET_CODE (XEXP (op, 1)) == CONST_INT);
622 /* Return truth value of statement that OP is a symbolic memory
623 operand of mode MODE. */
626 symbolic_memory_operand (op, mode)
628 enum machine_mode mode ATTRIBUTE_UNUSED;
630 if (GET_CODE (op) == SUBREG)
631 op = SUBREG_REG (op);
632 if (GET_CODE (op) != MEM)
635 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
636 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
639 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
642 label_ref_operand (op, mode)
644 enum machine_mode mode;
646 if (GET_CODE (op) != LABEL_REF)
648 if (GET_MODE (op) != mode)
653 /* Return 1 if the operand is an argument used in generating pic references
654 in either the medium/low or medium/anywhere code models of sparc64. */
657 sp64_medium_pic_operand (op, mode)
659 enum machine_mode mode ATTRIBUTE_UNUSED;
661 /* Check for (const (minus (symbol_ref:GOT)
662 (const (minus (label) (pc))))). */
663 if (GET_CODE (op) != CONST)
666 if (GET_CODE (op) != MINUS)
668 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
670 /* ??? Ensure symbol is GOT. */
671 if (GET_CODE (XEXP (op, 1)) != CONST)
673 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
678 /* Return 1 if the operand is a data segment reference. This includes
679 the readonly data segment, or in other words anything but the text segment.
680 This is needed in the medium/anywhere code model on v9. These values
681 are accessed with EMBMEDANY_BASE_REG. */
684 data_segment_operand (op, mode)
686 enum machine_mode mode ATTRIBUTE_UNUSED;
688 switch (GET_CODE (op))
691 return ! SYMBOL_REF_FLAG (op);
693 /* Assume canonical format of symbol + constant.
696 return data_segment_operand (XEXP (op, 0), VOIDmode);
702 /* Return 1 if the operand is a text segment reference.
703 This is needed in the medium/anywhere code model on v9. */
706 text_segment_operand (op, mode)
708 enum machine_mode mode ATTRIBUTE_UNUSED;
710 switch (GET_CODE (op))
715 return SYMBOL_REF_FLAG (op);
717 /* Assume canonical format of symbol + constant.
720 return text_segment_operand (XEXP (op, 0), VOIDmode);
726 /* Return 1 if the operand is either a register or a memory operand that is
730 reg_or_nonsymb_mem_operand (op, mode)
732 enum machine_mode mode;
734 if (register_operand (op, mode))
737 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
744 splittable_symbolic_memory_operand (op, mode)
746 enum machine_mode mode ATTRIBUTE_UNUSED;
748 if (GET_CODE (op) != MEM)
750 if (! symbolic_operand (XEXP (op, 0), Pmode))
756 splittable_immediate_memory_operand (op, mode)
758 enum machine_mode mode ATTRIBUTE_UNUSED;
760 if (GET_CODE (op) != MEM)
762 if (! immediate_operand (XEXP (op, 0), Pmode))
767 /* Return truth value of whether OP is EQ or NE. */
772 enum machine_mode mode ATTRIBUTE_UNUSED;
774 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
777 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
778 or LTU for non-floating-point. We handle those specially. */
781 normal_comp_operator (op, mode)
783 enum machine_mode mode ATTRIBUTE_UNUSED;
785 enum rtx_code code = GET_CODE (op);
787 if (GET_RTX_CLASS (code) != '<')
790 if (GET_MODE (XEXP (op, 0)) == CCFPmode
791 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
794 return (code != NE && code != EQ && code != GEU && code != LTU);
797 /* Return 1 if this is a comparison operator. This allows the use of
798 MATCH_OPERATOR to recognize all the branch insns. */
801 noov_compare_op (op, mode)
803 enum machine_mode mode ATTRIBUTE_UNUSED;
805 enum rtx_code code = GET_CODE (op);
807 if (GET_RTX_CLASS (code) != '<')
810 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
811 /* These are the only branches which work with CC_NOOVmode. */
812 return (code == EQ || code == NE || code == GE || code == LT);
816 /* Nonzero if OP is a comparison operator suitable for use in v9
817 conditional move or branch on register contents instructions. */
820 v9_regcmp_op (op, mode)
822 enum machine_mode mode ATTRIBUTE_UNUSED;
824 enum rtx_code code = GET_CODE (op);
826 if (GET_RTX_CLASS (code) != '<')
829 return v9_regcmp_p (code);
832 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
837 enum machine_mode mode ATTRIBUTE_UNUSED;
839 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
842 /* Return nonzero if OP is an operator of mode MODE which can set
843 the condition codes explicitly. We do not include PLUS and MINUS
844 because these require CC_NOOVmode, which we handle explicitly. */
847 cc_arithop (op, mode)
849 enum machine_mode mode ATTRIBUTE_UNUSED;
851 if (GET_CODE (op) == AND
852 || GET_CODE (op) == IOR
853 || GET_CODE (op) == XOR)
859 /* Return nonzero if OP is an operator of mode MODE which can bitwise
860 complement its second operand and set the condition codes explicitly. */
863 cc_arithopn (op, mode)
865 enum machine_mode mode ATTRIBUTE_UNUSED;
867 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
868 and (xor ... (not ...)) to (not (xor ...)). */
869 return (GET_CODE (op) == AND
870 || GET_CODE (op) == IOR);
873 /* Return true if OP is a register, or is a CONST_INT that can fit in a
874 signed 13 bit immediate field. This is an acceptable SImode operand for
875 most 3 address instructions. */
878 arith_operand (op, mode)
880 enum machine_mode mode;
883 if (register_operand (op, mode))
885 if (GET_CODE (op) != CONST_INT)
887 val = INTVAL (op) & 0xffffffff;
888 return SPARC_SIMM13_P (val);
891 /* Return true if OP is a constant 4096 */
894 arith_4096_operand (op, mode)
896 enum machine_mode mode ATTRIBUTE_UNUSED;
899 if (GET_CODE (op) != CONST_INT)
901 val = INTVAL (op) & 0xffffffff;
905 /* Return true if OP is suitable as second operand for add/sub */
908 arith_add_operand (op, mode)
910 enum machine_mode mode;
912 return arith_operand (op, mode) || arith_4096_operand (op, mode);
915 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
916 immediate field of OR and XOR instructions. Used for 64-bit
917 constant formation patterns. */
919 const64_operand (op, mode)
921 enum machine_mode mode ATTRIBUTE_UNUSED;
923 return ((GET_CODE (op) == CONST_INT
924 && SPARC_SIMM13_P (INTVAL (op)))
925 #if HOST_BITS_PER_WIDE_INT != 64
926 || (GET_CODE (op) == CONST_DOUBLE
927 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
928 && (CONST_DOUBLE_HIGH (op) ==
929 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
930 (HOST_WIDE_INT)0xffffffff : 0)))
935 /* The same, but only for sethi instructions. */
937 const64_high_operand (op, mode)
939 enum machine_mode mode ATTRIBUTE_UNUSED;
941 return ((GET_CODE (op) == CONST_INT
942 && (INTVAL (op) & 0xfffffc00) != 0
943 && SPARC_SETHI_P (INTVAL (op))
944 #if HOST_BITS_PER_WIDE_INT != 64
945 /* Must be positive on non-64bit host else the
946 optimizer is fooled into thinking that sethi
947 sign extends, even though it does not. */
951 || (GET_CODE (op) == CONST_DOUBLE
952 && CONST_DOUBLE_HIGH (op) == 0
953 && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
954 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
957 /* Return true if OP is a register, or is a CONST_INT that can fit in a
958 signed 11 bit immediate field. This is an acceptable SImode operand for
959 the movcc instructions. */
962 arith11_operand (op, mode)
964 enum machine_mode mode;
966 return (register_operand (op, mode)
967 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
970 /* Return true if OP is a register, or is a CONST_INT that can fit in a
971 signed 10 bit immediate field. This is an acceptable SImode operand for
972 the movrcc instructions. */
975 arith10_operand (op, mode)
977 enum machine_mode mode;
979 return (register_operand (op, mode)
980 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
983 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
984 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
986 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
987 can fit in a 13 bit immediate field. This is an acceptable DImode operand
988 for most 3 address instructions. */
991 arith_double_operand (op, mode)
993 enum machine_mode mode;
995 return (register_operand (op, mode)
996 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
998 && GET_CODE (op) == CONST_DOUBLE
999 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1000 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1002 && GET_CODE (op) == CONST_DOUBLE
1003 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1004 && ((CONST_DOUBLE_HIGH (op) == -1
1005 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1006 || (CONST_DOUBLE_HIGH (op) == 0
1007 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1010 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1013 arith_double_4096_operand (op, mode)
1015 enum machine_mode mode ATTRIBUTE_UNUSED;
1017 return (TARGET_ARCH64 &&
1018 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1019 (GET_CODE (op) == CONST_DOUBLE &&
1020 CONST_DOUBLE_LOW (op) == 4096 &&
1021 CONST_DOUBLE_HIGH (op) == 0)));
1024 /* Return true if OP is suitable as second operand for add/sub in DImode */
1027 arith_double_add_operand (op, mode)
1029 enum machine_mode mode;
1031 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1034 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1035 can fit in an 11 bit immediate field. This is an acceptable DImode
1036 operand for the movcc instructions. */
1037 /* ??? Replace with arith11_operand? */
1040 arith11_double_operand (op, mode)
1042 enum machine_mode mode;
1044 return (register_operand (op, mode)
1045 || (GET_CODE (op) == CONST_DOUBLE
1046 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1047 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1048 && ((CONST_DOUBLE_HIGH (op) == -1
1049 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1050 || (CONST_DOUBLE_HIGH (op) == 0
1051 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1052 || (GET_CODE (op) == CONST_INT
1053 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1054 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1057 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1058 can fit in an 10 bit immediate field. This is an acceptable DImode
1059 operand for the movrcc instructions. */
1060 /* ??? Replace with arith10_operand? */
1063 arith10_double_operand (op, mode)
1065 enum machine_mode mode;
1067 return (register_operand (op, mode)
1068 || (GET_CODE (op) == CONST_DOUBLE
1069 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1070 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1071 && ((CONST_DOUBLE_HIGH (op) == -1
1072 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1073 || (CONST_DOUBLE_HIGH (op) == 0
1074 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1075 || (GET_CODE (op) == CONST_INT
1076 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1077 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1080 /* Return truth value of whether OP is a integer which fits the
1081 range constraining immediate operands in most three-address insns,
1082 which have a 13 bit immediate field. */
1085 small_int (op, mode)
1087 enum machine_mode mode ATTRIBUTE_UNUSED;
1089 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1093 small_int_or_double (op, mode)
1095 enum machine_mode mode ATTRIBUTE_UNUSED;
1097 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1098 || (GET_CODE (op) == CONST_DOUBLE
1099 && CONST_DOUBLE_HIGH (op) == 0
1100 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1103 /* Recognize operand values for the umul instruction. That instruction sign
1104 extends immediate values just like all other sparc instructions, but
1105 interprets the extended result as an unsigned number. */
1108 uns_small_int (op, mode)
1110 enum machine_mode mode ATTRIBUTE_UNUSED;
1112 #if HOST_BITS_PER_WIDE_INT > 32
1113 /* All allowed constants will fit a CONST_INT. */
1114 return (GET_CODE (op) == CONST_INT
1115 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1116 || (INTVAL (op) >= 0xFFFFF000
1117 && INTVAL (op) < 0x100000000)));
1119 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1120 || (GET_CODE (op) == CONST_DOUBLE
1121 && CONST_DOUBLE_HIGH (op) == 0
1122 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1127 uns_arith_operand (op, mode)
1129 enum machine_mode mode;
1131 return register_operand (op, mode) || uns_small_int (op, mode);
1134 /* Return truth value of statement that OP is a call-clobbered register. */
1136 clobbered_register (op, mode)
1138 enum machine_mode mode ATTRIBUTE_UNUSED;
1140 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1143 /* Return 1 if OP is a valid operand for the source of a move insn. */
1146 input_operand (op, mode)
1148 enum machine_mode mode;
1150 /* If both modes are non-void they must be the same. */
1151 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1154 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1155 if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX)
1158 /* Allow any one instruction integer constant, and all CONST_INT
1159 variants when we are working in DImode and !arch64. */
1160 if (GET_MODE_CLASS (mode) == MODE_INT
1161 && ((GET_CODE (op) == CONST_INT
1162 && ((SPARC_SETHI_P (INTVAL (op))
1164 || (INTVAL (op) >= 0)
1168 || SPARC_SIMM13_P (INTVAL (op))
1170 && ! TARGET_ARCH64)))
1172 && GET_CODE (op) == CONST_DOUBLE
1173 && ((CONST_DOUBLE_HIGH (op) == 0
1174 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1176 #if HOST_BITS_PER_WIDE_INT == 64
1177 (CONST_DOUBLE_HIGH (op) == 0
1178 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1180 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1181 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1182 && CONST_DOUBLE_HIGH (op) == 0)
1183 || (CONST_DOUBLE_HIGH (op) == -1
1184 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1189 /* If !arch64 and this is a DImode const, allow it so that
1190 the splits can be generated. */
1193 && GET_CODE (op) == CONST_DOUBLE)
1196 if (register_operand (op, mode))
1199 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1200 && GET_CODE (op) == CONST_DOUBLE)
1203 /* If this is a SUBREG, look inside so that we handle
1204 paradoxical ones. */
1205 if (GET_CODE (op) == SUBREG)
1206 op = SUBREG_REG (op);
1208 /* Check for valid MEM forms. */
1209 if (GET_CODE (op) == MEM)
1211 rtx inside = XEXP (op, 0);
1213 if (GET_CODE (inside) == LO_SUM)
1215 /* We can't allow these because all of the splits
1216 (eventually as they trickle down into DFmode
1217 splits) require offsettable memory references. */
1219 && GET_MODE (op) == TFmode)
1222 return (register_operand (XEXP (inside, 0), Pmode)
1223 && CONSTANT_P (XEXP (inside, 1)));
1225 return memory_address_p (mode, inside);
1232 /* We know it can't be done in one insn when we get here,
1233 the movsi expander guarentees this. */
1235 sparc_emit_set_const32 (op0, op1)
1239 enum machine_mode mode = GET_MODE (op0);
1242 if (GET_CODE (op1) == CONST_INT)
1244 HOST_WIDE_INT value = INTVAL (op1);
1246 if (SPARC_SETHI_P (value)
1247 || SPARC_SIMM13_P (value))
1251 /* Full 2-insn decomposition is needed. */
1252 if (reload_in_progress || reload_completed)
1255 temp = gen_reg_rtx (mode);
1257 if (GET_CODE (op1) == CONST_INT)
1259 /* Emit them as real moves instead of a HIGH/LO_SUM,
1260 this way CSE can see everything and reuse intermediate
1261 values if it wants. */
1263 && HOST_BITS_PER_WIDE_INT != 64
1264 && (INTVAL (op1) & 0x80000000) != 0)
1266 emit_insn (gen_rtx_SET (VOIDmode,
1268 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx,
1269 INTVAL (op1) & 0xfffffc00, 0)));
1273 emit_insn (gen_rtx_SET (VOIDmode,
1275 GEN_INT (INTVAL (op1) & 0xfffffc00)));
1277 emit_insn (gen_rtx_SET (VOIDmode,
1281 GEN_INT (INTVAL (op1) & 0x3ff))));
1285 /* A symbol, emit in the traditional way. */
1286 emit_insn (gen_rtx_SET (VOIDmode,
1290 emit_insn (gen_rtx_SET (VOIDmode,
1292 gen_rtx_LO_SUM (mode,
1300 /* Sparc-v9 code-model support. */
1302 sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1307 switch (sparc_cmodel)
1310 /* The range spanned by all instructions in the object is less
1311 than 2^31 bytes (2GB) and the distance from any instruction
1312 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1313 than 2^31 bytes (2GB).
1315 The executable must be in the low 4TB of the virtual address
1318 sethi %hi(symbol), %temp
1319 or %temp, %lo(symbol), %reg */
1320 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1321 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1325 /* The range spanned by all instructions in the object is less
1326 than 2^31 bytes (2GB) and the distance from any instruction
1327 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1328 than 2^31 bytes (2GB).
1330 The executable must be in the low 16TB of the virtual address
1333 sethi %h44(symbol), %temp1
1334 or %temp1, %m44(symbol), %temp2
1335 sllx %temp2, 12, %temp3
1336 or %temp3, %l44(symbol), %reg */
1337 emit_insn (gen_seth44 (op0, op1));
1338 emit_insn (gen_setm44 (op0, op0, op1));
1339 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1340 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1341 emit_insn (gen_setl44 (op0, temp1, op1));
1345 /* The range spanned by all instructions in the object is less
1346 than 2^31 bytes (2GB) and the distance from any instruction
1347 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1348 than 2^31 bytes (2GB).
1350 The executable can be placed anywhere in the virtual address
1353 sethi %hh(symbol), %temp1
1354 sethi %lm(symbol), %temp2
1355 or %temp1, %hm(symbol), %temp3
1356 or %temp2, %lo(symbol), %temp4
1357 sllx %temp3, 32, %temp5
1358 or %temp4, %temp5, %reg */
1360 /* Getting this right wrt. reloading is really tricky.
1361 We _MUST_ have a separate temporary at this point,
1362 if we don't barf immediately instead of generating
1367 emit_insn (gen_sethh (op0, op1));
1368 emit_insn (gen_setlm (temp1, op1));
1369 emit_insn (gen_sethm (op0, op0, op1));
1370 emit_insn (gen_rtx_SET (VOIDmode, op0,
1371 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1372 emit_insn (gen_rtx_SET (VOIDmode, op0,
1373 gen_rtx_PLUS (DImode, op0, temp1)));
1374 emit_insn (gen_setlo (op0, op0, op1));
1378 /* Old old old backwards compatibility kruft here.
1379 Essentially it is MEDLOW with a fixed 64-bit
1380 virtual base added to all data segment addresses.
1381 Text-segment stuff is computed like MEDANY, we can't
1382 reuse the code above because the relocation knobs
1385 Data segment: sethi %hi(symbol), %temp1
1386 or %temp1, %lo(symbol), %temp2
1387 add %temp2, EMBMEDANY_BASE_REG, %reg
1389 Text segment: sethi %uhi(symbol), %temp1
1390 sethi %hi(symbol), %temp2
1391 or %temp1, %ulo(symbol), %temp3
1392 or %temp2, %lo(symbol), %temp4
1393 sllx %temp3, 32, %temp5
1394 or %temp4, %temp5, %reg */
1395 if (data_segment_operand (op1, GET_MODE (op1)))
1397 emit_insn (gen_embmedany_sethi (temp1, op1));
1398 emit_insn (gen_embmedany_brsum (op0, temp1));
1399 emit_insn (gen_embmedany_losum (op0, op0, op1));
1403 /* Getting this right wrt. reloading is really tricky.
1404 We _MUST_ have a separate temporary at this point,
1405 so we barf immediately instead of generating
1410 emit_insn (gen_embmedany_textuhi (op0, op1));
1411 emit_insn (gen_embmedany_texthi (temp1, op1));
1412 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1413 emit_insn (gen_rtx_SET (VOIDmode, op0,
1414 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1415 emit_insn (gen_rtx_SET (VOIDmode, op0,
1416 gen_rtx_PLUS (DImode, op0, temp1)));
1417 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1426 /* These avoid problems when cross compiling. If we do not
1427 go through all this hair then the optimizer will see
1428 invalid REG_EQUAL notes or in some cases none at all. */
1429 static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT));
1430 static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT));
1431 static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT));
1432 static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
1434 #if HOST_BITS_PER_WIDE_INT == 64
1435 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
1436 #define GEN_INT64(__x) GEN_INT (__x)
1438 #define GEN_HIGHINT64(__x) \
1439 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1440 (__x) & 0xfffffc00, 0)
1441 #define GEN_INT64(__x) \
1442 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1443 (__x) & 0xffffffff, \
1444 ((__x) & 0x80000000 \
1448 /* The optimizer is not to assume anything about exactly
1449 which bits are set for a HIGH, they are unspecified.
1450 Unfortunately this leads to many missed optimizations
1451 during CSE. We mask out the non-HIGH bits, and matches
1452 a plain movdi, to alleviate this problem. */
1454 sparc_emit_set_safe_HIGH64 (dest, val)
1458 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1462 gen_safe_SET64 (dest, val)
1466 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1470 gen_safe_OR64 (src, val)
1474 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1478 gen_safe_XOR64 (src, val)
1482 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1485 /* Worker routines for 64-bit constant formation on arch64.
1486 One of the key things to be doing in these emissions is
1487 to create as many temp REGs as possible. This makes it
1488 possible for half-built constants to be used later when
1489 such values are similar to something required later on.
1490 Without doing this, the optimizer cannot see such
1493 static void sparc_emit_set_const64_quick1
1494 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int));
1497 sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1500 unsigned HOST_WIDE_INT low_bits;
1503 unsigned HOST_WIDE_INT high_bits;
1506 high_bits = (~low_bits) & 0xffffffff;
1508 high_bits = low_bits;
1510 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1513 emit_insn (gen_rtx_SET (VOIDmode, op0,
1514 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1518 /* If we are XOR'ing with -1, then we should emit a one's complement
1519 instead. This way the combiner will notice logical operations
1520 such as ANDN later on and substitute. */
1521 if ((low_bits & 0x3ff) == 0x3ff)
1523 emit_insn (gen_rtx_SET (VOIDmode, op0,
1524 gen_rtx_NOT (DImode, temp)));
1528 emit_insn (gen_rtx_SET (VOIDmode, op0,
1529 gen_safe_XOR64 (temp,
1530 (-0x400 | (low_bits & 0x3ff)))));
1535 static void sparc_emit_set_const64_quick2
1536 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT,
1537 unsigned HOST_WIDE_INT, int));
1540 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1543 unsigned HOST_WIDE_INT high_bits;
1544 unsigned HOST_WIDE_INT low_immediate;
1549 if ((high_bits & 0xfffffc00) != 0)
1551 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1552 if ((high_bits & ~0xfffffc00) != 0)
1553 emit_insn (gen_rtx_SET (VOIDmode, op0,
1554 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1560 emit_insn (gen_safe_SET64 (temp, high_bits));
1564 /* Now shift it up into place. */
1565 emit_insn (gen_rtx_SET (VOIDmode, op0,
1566 gen_rtx_ASHIFT (DImode, temp2,
1567 GEN_INT (shift_count))));
1569 /* If there is a low immediate part piece, finish up by
1570 putting that in as well. */
1571 if (low_immediate != 0)
1572 emit_insn (gen_rtx_SET (VOIDmode, op0,
1573 gen_safe_OR64 (op0, low_immediate)));
1576 static void sparc_emit_set_const64_longway
1577 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1579 /* Full 64-bit constant decomposition. Even though this is the
1580 'worst' case, we still optimize a few things away. */
1582 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1585 unsigned HOST_WIDE_INT high_bits;
1586 unsigned HOST_WIDE_INT low_bits;
1590 if (reload_in_progress || reload_completed)
1593 sub_temp = gen_reg_rtx (DImode);
1595 if ((high_bits & 0xfffffc00) != 0)
1597 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1598 if ((high_bits & ~0xfffffc00) != 0)
1599 emit_insn (gen_rtx_SET (VOIDmode,
1601 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1607 emit_insn (gen_safe_SET64 (temp, high_bits));
1611 if (!reload_in_progress && !reload_completed)
1613 rtx temp2 = gen_reg_rtx (DImode);
1614 rtx temp3 = gen_reg_rtx (DImode);
1615 rtx temp4 = gen_reg_rtx (DImode);
1617 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1618 gen_rtx_ASHIFT (DImode, sub_temp,
1621 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1622 if ((low_bits & ~0xfffffc00) != 0)
1624 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1625 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1626 emit_insn (gen_rtx_SET (VOIDmode, op0,
1627 gen_rtx_PLUS (DImode, temp4, temp3)));
1631 emit_insn (gen_rtx_SET (VOIDmode, op0,
1632 gen_rtx_PLUS (DImode, temp4, temp2)));
1637 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1638 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1639 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1642 /* We are in the middle of reload, so this is really
1643 painful. However we do still make an attempt to
1644 avoid emitting truly stupid code. */
1645 if (low1 != const0_rtx)
1647 emit_insn (gen_rtx_SET (VOIDmode, op0,
1648 gen_rtx_ASHIFT (DImode, sub_temp,
1649 GEN_INT (to_shift))));
1650 emit_insn (gen_rtx_SET (VOIDmode, op0,
1651 gen_rtx_IOR (DImode, op0, low1)));
1659 if (low2 != const0_rtx)
1661 emit_insn (gen_rtx_SET (VOIDmode, op0,
1662 gen_rtx_ASHIFT (DImode, sub_temp,
1663 GEN_INT (to_shift))));
1664 emit_insn (gen_rtx_SET (VOIDmode, op0,
1665 gen_rtx_IOR (DImode, op0, low2)));
1673 emit_insn (gen_rtx_SET (VOIDmode, op0,
1674 gen_rtx_ASHIFT (DImode, sub_temp,
1675 GEN_INT (to_shift))));
1676 if (low3 != const0_rtx)
1677 emit_insn (gen_rtx_SET (VOIDmode, op0,
1678 gen_rtx_IOR (DImode, op0, low3)));
1683 /* Analyze a 64-bit constant for certain properties. */
1684 static void analyze_64bit_constant
1685 PARAMS ((unsigned HOST_WIDE_INT,
1686 unsigned HOST_WIDE_INT,
1687 int *, int *, int *));
1690 analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
1691 unsigned HOST_WIDE_INT high_bits, low_bits;
1692 int *hbsp, *lbsp, *abbasp;
1694 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1697 lowest_bit_set = highest_bit_set = -1;
1701 if ((lowest_bit_set == -1)
1702 && ((low_bits >> i) & 1))
1704 if ((highest_bit_set == -1)
1705 && ((high_bits >> (32 - i - 1)) & 1))
1706 highest_bit_set = (64 - i - 1);
1709 && ((highest_bit_set == -1)
1710 || (lowest_bit_set == -1)));
1716 if ((lowest_bit_set == -1)
1717 && ((high_bits >> i) & 1))
1718 lowest_bit_set = i + 32;
1719 if ((highest_bit_set == -1)
1720 && ((low_bits >> (32 - i - 1)) & 1))
1721 highest_bit_set = 32 - i - 1;
1724 && ((highest_bit_set == -1)
1725 || (lowest_bit_set == -1)));
1727 /* If there are no bits set this should have gone out
1728 as one instruction! */
1729 if (lowest_bit_set == -1
1730 || highest_bit_set == -1)
1732 all_bits_between_are_set = 1;
1733 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1737 if ((low_bits & (1 << i)) != 0)
1742 if ((high_bits & (1 << (i - 32))) != 0)
1745 all_bits_between_are_set = 0;
1748 *hbsp = highest_bit_set;
1749 *lbsp = lowest_bit_set;
1750 *abbasp = all_bits_between_are_set;
1753 static int const64_is_2insns
1754 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1757 const64_is_2insns (high_bits, low_bits)
1758 unsigned HOST_WIDE_INT high_bits, low_bits;
1760 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1763 || high_bits == 0xffffffff)
1766 analyze_64bit_constant (high_bits, low_bits,
1767 &highest_bit_set, &lowest_bit_set,
1768 &all_bits_between_are_set);
1770 if ((highest_bit_set == 63
1771 || lowest_bit_set == 0)
1772 && all_bits_between_are_set != 0)
1775 if ((highest_bit_set - lowest_bit_set) < 21)
1781 static unsigned HOST_WIDE_INT create_simple_focus_bits
1782 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
1785 static unsigned HOST_WIDE_INT
1786 create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
1787 unsigned HOST_WIDE_INT high_bits, low_bits;
1788 int lowest_bit_set, shift;
1790 HOST_WIDE_INT hi, lo;
1792 if (lowest_bit_set < 32)
1794 lo = (low_bits >> lowest_bit_set) << shift;
1795 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1800 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1807 /* Here we are sure to be arch64 and this is an integer constant
1808 being loaded into a register. Emit the most efficient
1809 insn sequence possible. Detection of all the 1-insn cases
1810 has been done already. */
1812 sparc_emit_set_const64 (op0, op1)
1816 unsigned HOST_WIDE_INT high_bits, low_bits;
1817 int lowest_bit_set, highest_bit_set;
1818 int all_bits_between_are_set;
1821 /* Sanity check that we know what we are working with. */
1822 if (! TARGET_ARCH64)
1825 if (GET_CODE (op0) != SUBREG)
1827 if (GET_CODE (op0) != REG
1828 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1829 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1833 if (reload_in_progress || reload_completed)
1836 temp = gen_reg_rtx (DImode);
1838 if (GET_CODE (op1) != CONST_DOUBLE
1839 && GET_CODE (op1) != CONST_INT)
1841 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1845 if (GET_CODE (op1) == CONST_DOUBLE)
1847 #if HOST_BITS_PER_WIDE_INT == 64
1848 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1849 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1851 high_bits = CONST_DOUBLE_HIGH (op1);
1852 low_bits = CONST_DOUBLE_LOW (op1);
1857 #if HOST_BITS_PER_WIDE_INT == 64
1858 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1859 low_bits = (INTVAL (op1) & 0xffffffff);
1861 high_bits = ((INTVAL (op1) < 0) ?
1864 low_bits = INTVAL (op1);
1868 /* low_bits bits 0 --> 31
1869 high_bits bits 32 --> 63 */
1871 analyze_64bit_constant (high_bits, low_bits,
1872 &highest_bit_set, &lowest_bit_set,
1873 &all_bits_between_are_set);
1875 /* First try for a 2-insn sequence. */
1877 /* These situations are preferred because the optimizer can
1878 * do more things with them:
1880 * sllx %reg, shift, %reg
1882 * srlx %reg, shift, %reg
1883 * 3) mov some_small_const, %reg
1884 * sllx %reg, shift, %reg
1886 if (((highest_bit_set == 63
1887 || lowest_bit_set == 0)
1888 && all_bits_between_are_set != 0)
1889 || ((highest_bit_set - lowest_bit_set) < 12))
1891 HOST_WIDE_INT the_const = -1;
1892 int shift = lowest_bit_set;
1894 if ((highest_bit_set != 63
1895 && lowest_bit_set != 0)
1896 || all_bits_between_are_set == 0)
1899 create_simple_focus_bits (high_bits, low_bits,
1902 else if (lowest_bit_set == 0)
1903 shift = -(63 - highest_bit_set);
1905 if (! SPARC_SIMM13_P (the_const))
1908 emit_insn (gen_safe_SET64 (temp, the_const));
1910 emit_insn (gen_rtx_SET (VOIDmode,
1912 gen_rtx_ASHIFT (DImode,
1916 emit_insn (gen_rtx_SET (VOIDmode,
1918 gen_rtx_LSHIFTRT (DImode,
1920 GEN_INT (-shift))));
1926 /* Now a range of 22 or less bits set somewhere.
1927 * 1) sethi %hi(focus_bits), %reg
1928 * sllx %reg, shift, %reg
1929 * 2) sethi %hi(focus_bits), %reg
1930 * srlx %reg, shift, %reg
1932 if ((highest_bit_set - lowest_bit_set) < 21)
1934 unsigned HOST_WIDE_INT focus_bits =
1935 create_simple_focus_bits (high_bits, low_bits,
1936 lowest_bit_set, 10);
1938 if (! SPARC_SETHI_P (focus_bits))
1941 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
1943 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1944 if (lowest_bit_set < 10)
1945 emit_insn (gen_rtx_SET (VOIDmode,
1947 gen_rtx_LSHIFTRT (DImode, temp,
1948 GEN_INT (10 - lowest_bit_set))));
1949 else if (lowest_bit_set > 10)
1950 emit_insn (gen_rtx_SET (VOIDmode,
1952 gen_rtx_ASHIFT (DImode, temp,
1953 GEN_INT (lowest_bit_set - 10))));
1959 /* 1) sethi %hi(low_bits), %reg
1960 * or %reg, %lo(low_bits), %reg
1961 * 2) sethi %hi(~low_bits), %reg
1962 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1965 || high_bits == 0xffffffff)
1967 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1968 (high_bits == 0xffffffff));
1972 /* Now, try 3-insn sequences. */
1974 /* 1) sethi %hi(high_bits), %reg
1975 * or %reg, %lo(high_bits), %reg
1976 * sllx %reg, 32, %reg
1980 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
1984 /* We may be able to do something quick
1985 when the constant is negated, so try that. */
1986 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1987 (~low_bits) & 0xfffffc00))
1989 /* NOTE: The trailing bits get XOR'd so we need the
1990 non-negated bits, not the negated ones. */
1991 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
1993 if ((((~high_bits) & 0xffffffff) == 0
1994 && ((~low_bits) & 0x80000000) == 0)
1995 || (((~high_bits) & 0xffffffff) == 0xffffffff
1996 && ((~low_bits) & 0x80000000) != 0))
1998 int fast_int = (~low_bits & 0xffffffff);
2000 if ((SPARC_SETHI_P (fast_int)
2001 && (~high_bits & 0xffffffff) == 0)
2002 || SPARC_SIMM13_P (fast_int))
2003 emit_insn (gen_safe_SET64 (temp, fast_int));
2005 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2010 #if HOST_BITS_PER_WIDE_INT == 64
2011 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2012 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2014 negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx,
2015 (~low_bits) & 0xfffffc00,
2016 (~high_bits) & 0xffffffff);
2018 sparc_emit_set_const64 (temp, negated_const);
2021 /* If we are XOR'ing with -1, then we should emit a one's complement
2022 instead. This way the combiner will notice logical operations
2023 such as ANDN later on and substitute. */
2024 if (trailing_bits == 0x3ff)
2026 emit_insn (gen_rtx_SET (VOIDmode, op0,
2027 gen_rtx_NOT (DImode, temp)));
2031 emit_insn (gen_rtx_SET (VOIDmode,
2033 gen_safe_XOR64 (temp,
2034 (-0x400 | trailing_bits))));
2039 /* 1) sethi %hi(xxx), %reg
2040 * or %reg, %lo(xxx), %reg
2041 * sllx %reg, yyy, %reg
2043 * ??? This is just a generalized version of the low_bits==0
2044 * thing above, FIXME...
2046 if ((highest_bit_set - lowest_bit_set) < 32)
2048 unsigned HOST_WIDE_INT focus_bits =
2049 create_simple_focus_bits (high_bits, low_bits,
2052 /* We can't get here in this state. */
2053 if (highest_bit_set < 32
2054 || lowest_bit_set >= 32)
2057 /* So what we know is that the set bits straddle the
2058 middle of the 64-bit word. */
2059 sparc_emit_set_const64_quick2 (op0, temp,
2065 /* 1) sethi %hi(high_bits), %reg
2066 * or %reg, %lo(high_bits), %reg
2067 * sllx %reg, 32, %reg
2068 * or %reg, low_bits, %reg
2070 if (SPARC_SIMM13_P(low_bits)
2071 && ((int)low_bits > 0))
2073 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2077 /* The easiest way when all else fails, is full decomposition. */
2079 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2080 high_bits, low_bits, ~high_bits, ~low_bits);
2082 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2085 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2086 return the mode to be used for the comparison. For floating-point,
2087 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2088 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2089 processing is needed. */
2092 select_cc_mode (op, x, y)
2095 rtx y ATTRIBUTE_UNUSED;
2097 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2123 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2124 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2126 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2127 return CCX_NOOVmode;
2133 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2140 /* X and Y are two things to compare using CODE. Emit the compare insn and
2141 return the rtx for the cc reg in the proper mode. */
2144 gen_compare_reg (code, x, y)
2148 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2151 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2152 fcc regs (cse can't tell they're really call clobbered regs and will
2153 remove a duplicate comparison even if there is an intervening function
2154 call - it will then try to reload the cc reg via an int reg which is why
2155 we need the movcc patterns). It is possible to provide the movcc
2156 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2157 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2158 to tell cse that CCFPE mode registers (even pseudos) are call
2161 /* ??? This is an experiment. Rather than making changes to cse which may
2162 or may not be easy/clean, we do our own cse. This is possible because
2163 we will generate hard registers. Cse knows they're call clobbered (it
2164 doesn't know the same thing about pseudos). If we guess wrong, no big
2165 deal, but if we win, great! */
2167 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2168 #if 1 /* experiment */
2171 /* We cycle through the registers to ensure they're all exercised. */
2172 static int next_fcc_reg = 0;
2173 /* Previous x,y for each fcc reg. */
2174 static rtx prev_args[4][2];
2176 /* Scan prev_args for x,y. */
2177 for (reg = 0; reg < 4; reg++)
2178 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2183 prev_args[reg][0] = x;
2184 prev_args[reg][1] = y;
2185 next_fcc_reg = (next_fcc_reg + 1) & 3;
2187 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2190 cc_reg = gen_reg_rtx (mode);
2191 #endif /* ! experiment */
2192 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2193 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2195 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2197 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2198 gen_rtx_COMPARE (mode, x, y)));
2203 /* This function is used for v9 only.
2204 CODE is the code for an Scc's comparison.
2205 OPERANDS[0] is the target of the Scc insn.
2206 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2207 been generated yet).
2209 This function is needed to turn
2212 (gt (reg:CCX 100 %icc)
2216 (gt:DI (reg:CCX 100 %icc)
2219 IE: The instruction recognizer needs to see the mode of the comparison to
2220 find the right instruction. We could use "gt:DI" right in the
2221 define_expand, but leaving it out allows us to handle DI, SI, etc.
2223 We refer to the global sparc compare operands sparc_compare_op0 and
2224 sparc_compare_op1. */
2227 gen_v9_scc (compare_code, operands)
2228 enum rtx_code compare_code;
2229 register rtx *operands;
2234 && (GET_MODE (sparc_compare_op0) == DImode
2235 || GET_MODE (operands[0]) == DImode))
2238 /* Handle the case where operands[0] == sparc_compare_op0.
2239 We "early clobber" the result. */
2240 if (REGNO (operands[0]) == REGNO (sparc_compare_op0))
2242 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2243 emit_move_insn (op0, sparc_compare_op0);
2246 op0 = sparc_compare_op0;
2247 /* For consistency in the following. */
2248 op1 = sparc_compare_op1;
2250 /* Try to use the movrCC insns. */
2252 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2253 && op1 == const0_rtx
2254 && v9_regcmp_p (compare_code))
2256 /* Special case for op0 != 0. This can be done with one instruction if
2257 operands[0] == sparc_compare_op0. We don't assume they are equal
2260 if (compare_code == NE
2261 && GET_MODE (operands[0]) == DImode
2262 && GET_MODE (op0) == DImode)
2264 emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0));
2265 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2266 gen_rtx_IF_THEN_ELSE (DImode,
2267 gen_rtx_fmt_ee (compare_code, DImode,
2274 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2275 if (GET_MODE (op0) != DImode)
2277 temp = gen_reg_rtx (DImode);
2278 convert_move (temp, op0, 0);
2282 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2283 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2284 gen_rtx_fmt_ee (compare_code, DImode,
2292 operands[1] = gen_compare_reg (compare_code, op0, op1);
2294 switch (GET_MODE (operands[1]))
2304 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2305 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2306 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2307 gen_rtx_fmt_ee (compare_code,
2308 GET_MODE (operands[1]),
2309 operands[1], const0_rtx),
2310 const1_rtx, operands[0])));
2315 /* Emit a conditional jump insn for the v9 architecture using comparison code
2316 CODE and jump target LABEL.
2317 This function exists to take advantage of the v9 brxx insns. */
2320 emit_v9_brxx_insn (code, op0, label)
2324 emit_jump_insn (gen_rtx_SET (VOIDmode,
2326 gen_rtx_IF_THEN_ELSE (VOIDmode,
2327 gen_rtx_fmt_ee (code, GET_MODE (op0),
2329 gen_rtx_LABEL_REF (VOIDmode, label),
2333 /* Generate a DFmode part of a hard TFmode register.
2334 REG is the TFmode hard register, LOW is 1 for the
2335 low 64bit of the register and 0 otherwise.
2338 gen_df_reg (reg, low)
2342 int regno = REGNO (reg);
2344 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2345 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2346 return gen_rtx_REG (DFmode, regno);
2349 /* Return nonzero if a return peephole merging return with
2350 setting of output register is ok. */
2352 leaf_return_peephole_ok ()
2354 return (actual_fsize == 0);
2357 /* Return nonzero if TRIAL can go into the function epilogue's
2358 delay slot. SLOT is the slot we are trying to fill. */
2361 eligible_for_epilogue_delay (trial, slot)
2370 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2373 if (get_attr_length (trial) != 1)
2376 /* If there are any call-saved registers, we should scan TRIAL if it
2377 does not reference them. For now just make it easy. */
2381 /* In the case of a true leaf function, anything can go into the delay slot.
2382 A delay slot only exists however if the frame size is zero, otherwise
2383 we will put an insn to adjust the stack after the return. */
2384 if (current_function_uses_only_leaf_regs)
2386 if (leaf_return_peephole_ok ())
2387 return ((get_attr_in_uncond_branch_delay (trial)
2388 == IN_BRANCH_DELAY_TRUE));
2392 pat = PATTERN (trial);
2394 /* Otherwise, only operations which can be done in tandem with
2395 a `restore' or `return' insn can go into the delay slot. */
2396 if (GET_CODE (SET_DEST (pat)) != REG
2397 || REGNO (SET_DEST (pat)) < 24)
2400 /* If this instruction sets up floating point register and we have a return
2401 instruction, it can probably go in. But restore will not work
2403 if (REGNO (SET_DEST (pat)) >= 32)
2405 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2406 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2411 /* The set of insns matched here must agree precisely with the set of
2412 patterns paired with a RETURN in sparc.md. */
2414 src = SET_SRC (pat);
2416 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2417 if (arith_operand (src, GET_MODE (src)))
2420 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2422 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2425 /* This matches "*return_di". */
2426 else if (arith_double_operand (src, GET_MODE (src)))
2427 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2429 /* This matches "*return_sf_no_fpu". */
2430 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2431 && register_operand (src, SFmode))
2434 /* If we have return instruction, anything that does not use
2435 local or output registers and can go into a delay slot wins. */
2436 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2437 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2440 /* This matches "*return_addsi". */
2441 else if (GET_CODE (src) == PLUS
2442 && arith_operand (XEXP (src, 0), SImode)
2443 && arith_operand (XEXP (src, 1), SImode)
2444 && (register_operand (XEXP (src, 0), SImode)
2445 || register_operand (XEXP (src, 1), SImode)))
2448 /* This matches "*return_adddi". */
2449 else if (GET_CODE (src) == PLUS
2450 && arith_double_operand (XEXP (src, 0), DImode)
2451 && arith_double_operand (XEXP (src, 1), DImode)
2452 && (register_operand (XEXP (src, 0), DImode)
2453 || register_operand (XEXP (src, 1), DImode)))
2456 /* This can match "*return_losum_[sd]i".
2457 Catch only some cases, so that return_losum* don't have
2459 else if (GET_CODE (src) == LO_SUM
2460 && ! TARGET_CM_MEDMID
2461 && ((register_operand (XEXP (src, 0), SImode)
2462 && immediate_operand (XEXP (src, 1), SImode))
2464 && register_operand (XEXP (src, 0), DImode)
2465 && immediate_operand (XEXP (src, 1), DImode))))
2468 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2469 else if (GET_CODE (src) == ASHIFT
2470 && (register_operand (XEXP (src, 0), SImode)
2471 || register_operand (XEXP (src, 0), DImode))
2472 && XEXP (src, 1) == const1_rtx)
2478 /* Return nonzero if TRIAL can go into the sibling call
2482 eligible_for_sibcall_delay (trial)
2487 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2490 if (get_attr_length (trial) != 1 || profile_block_flag == 2)
2493 pat = PATTERN (trial);
2495 if (current_function_uses_only_leaf_regs)
2497 /* If the tail call is done using the call instruction,
2498 we have to restore %o7 in the delay slot. */
2499 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2502 /* %g1 is used to build the function address */
2503 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2509 /* Otherwise, only operations which can be done in tandem with
2510 a `restore' insn can go into the delay slot. */
2511 if (GET_CODE (SET_DEST (pat)) != REG
2512 || REGNO (SET_DEST (pat)) < 24
2513 || REGNO (SET_DEST (pat)) >= 32)
2516 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2518 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2521 src = SET_SRC (pat);
2523 if (arith_operand (src, GET_MODE (src)))
2526 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2528 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2531 else if (arith_double_operand (src, GET_MODE (src)))
2532 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2534 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2535 && register_operand (src, SFmode))
2538 else if (GET_CODE (src) == PLUS
2539 && arith_operand (XEXP (src, 0), SImode)
2540 && arith_operand (XEXP (src, 1), SImode)
2541 && (register_operand (XEXP (src, 0), SImode)
2542 || register_operand (XEXP (src, 1), SImode)))
2545 else if (GET_CODE (src) == PLUS
2546 && arith_double_operand (XEXP (src, 0), DImode)
2547 && arith_double_operand (XEXP (src, 1), DImode)
2548 && (register_operand (XEXP (src, 0), DImode)
2549 || register_operand (XEXP (src, 1), DImode)))
2552 else if (GET_CODE (src) == LO_SUM
2553 && ! TARGET_CM_MEDMID
2554 && ((register_operand (XEXP (src, 0), SImode)
2555 && immediate_operand (XEXP (src, 1), SImode))
2557 && register_operand (XEXP (src, 0), DImode)
2558 && immediate_operand (XEXP (src, 1), DImode))))
2561 else if (GET_CODE (src) == ASHIFT
2562 && (register_operand (XEXP (src, 0), SImode)
2563 || register_operand (XEXP (src, 0), DImode))
2564 && XEXP (src, 1) == const1_rtx)
2571 check_return_regs (x)
2574 switch (GET_CODE (x))
2577 return IN_OR_GLOBAL_P (x);
2592 if (check_return_regs (XEXP (x, 1)) == 0)
2597 return check_return_regs (XEXP (x, 0));
2605 /* Return 1 if TRIAL references only in and global registers. */
2607 eligible_for_return_delay (trial)
2610 if (GET_CODE (PATTERN (trial)) != SET)
2613 return check_return_regs (PATTERN (trial));
2617 short_branch (uid1, uid2)
2620 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
2622 /* Leave a few words of "slop". */
2623 if (delta >= -1023 && delta <= 1022)
2629 /* Return non-zero if REG is not used after INSN.
2630 We assume REG is a reload reg, and therefore does
2631 not live past labels or calls or jumps. */
2633 reg_unused_after (reg, insn)
2637 enum rtx_code code, prev_code = UNKNOWN;
2639 while ((insn = NEXT_INSN (insn)))
2641 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2644 code = GET_CODE (insn);
2645 if (GET_CODE (insn) == CODE_LABEL)
2648 if (GET_RTX_CLASS (code) == 'i')
2650 rtx set = single_set (insn);
2651 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2654 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2656 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2664 /* The table we use to reference PIC data. */
2665 static rtx global_offset_table;
2667 /* The function we use to get at it. */
2668 static rtx get_pc_symbol;
2669 static char get_pc_symbol_name[256];
2671 /* Ensure that we are not using patterns that are not OK with PIC. */
2680 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
2681 || (GET_CODE (recog_data.operand[i]) == CONST
2682 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
2683 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
2684 == global_offset_table)
2685 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
2694 /* Return true if X is an address which needs a temporary register when
2695 reloaded while generating PIC code. */
2698 pic_address_needs_scratch (x)
2701 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2702 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2703 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2704 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2705 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2711 /* Legitimize PIC addresses. If the address is already position-independent,
2712 we return ORIG. Newly generated position-independent addresses go into a
2713 reg. This is REG if non zero, otherwise we allocate register(s) as
2717 legitimize_pic_address (orig, mode, reg)
2719 enum machine_mode mode ATTRIBUTE_UNUSED;
2722 if (GET_CODE (orig) == SYMBOL_REF)
2724 rtx pic_ref, address;
2729 if (reload_in_progress || reload_completed)
2732 reg = gen_reg_rtx (Pmode);
2737 /* If not during reload, allocate another temp reg here for loading
2738 in the address, so that these instructions can be optimized
2740 rtx temp_reg = ((reload_in_progress || reload_completed)
2741 ? reg : gen_reg_rtx (Pmode));
2743 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
2744 won't get confused into thinking that these two instructions
2745 are loading in the true address of the symbol. If in the
2746 future a PIC rtx exists, that should be used instead. */
2747 if (Pmode == SImode)
2749 emit_insn (gen_movsi_high_pic (temp_reg, orig));
2750 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
2754 emit_insn (gen_movdi_high_pic (temp_reg, orig));
2755 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
2762 pic_ref = gen_rtx_MEM (Pmode,
2763 gen_rtx_PLUS (Pmode,
2764 pic_offset_table_rtx, address));
2765 current_function_uses_pic_offset_table = 1;
2766 RTX_UNCHANGING_P (pic_ref) = 1;
2767 insn = emit_move_insn (reg, pic_ref);
2768 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2770 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2774 else if (GET_CODE (orig) == CONST)
2778 if (GET_CODE (XEXP (orig, 0)) == PLUS
2779 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2784 if (reload_in_progress || reload_completed)
2787 reg = gen_reg_rtx (Pmode);
2790 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2792 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2793 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2794 base == reg ? 0 : reg);
2799 if (GET_CODE (offset) == CONST_INT)
2801 if (SMALL_INT (offset))
2802 return plus_constant_for_output (base, INTVAL (offset));
2803 else if (! reload_in_progress && ! reload_completed)
2804 offset = force_reg (Pmode, offset);
2806 /* If we reach here, then something is seriously wrong. */
2809 return gen_rtx_PLUS (Pmode, base, offset);
2811 else if (GET_CODE (orig) == LABEL_REF)
2812 /* ??? Why do we do this? */
2813 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
2814 the register is live instead, in case it is eliminated. */
2815 current_function_uses_pic_offset_table = 1;
2820 /* Emit special PIC prologues. */
2823 load_pic_register ()
2825 /* Labels to get the PC in the prologue of this function. */
2826 int orig_flag_pic = flag_pic;
2831 /* If we havn't emitted the special get_pc helper function, do so now. */
2832 if (get_pc_symbol_name[0] == 0)
2836 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
2839 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
2841 ASM_OUTPUT_ALIGN (asm_out_file, align);
2842 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0);
2843 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
2846 /* Initialize every time through, since we can't easily
2847 know this to be permanent. */
2848 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2849 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
2852 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
2855 flag_pic = orig_flag_pic;
2857 /* Need to emit this whether or not we obey regdecls,
2858 since setjmp/longjmp can cause life info to screw up.
2859 ??? In the case where we don't obey regdecls, this is not sufficient
2860 since we may not fall out the bottom. */
2861 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2864 /* Return 1 if RTX is a MEM which is known to be aligned to at
2865 least an 8 byte boundary. */
2868 mem_min_alignment (mem, desired)
2872 rtx addr, base, offset;
2874 /* If it's not a MEM we can't accept it. */
2875 if (GET_CODE (mem) != MEM)
2878 addr = XEXP (mem, 0);
2879 base = offset = NULL_RTX;
2880 if (GET_CODE (addr) == PLUS)
2882 if (GET_CODE (XEXP (addr, 0)) == REG)
2884 base = XEXP (addr, 0);
2886 /* What we are saying here is that if the base
2887 REG is aligned properly, the compiler will make
2888 sure any REG based index upon it will be so
2890 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2891 offset = XEXP (addr, 1);
2893 offset = const0_rtx;
2896 else if (GET_CODE (addr) == REG)
2899 offset = const0_rtx;
2902 if (base != NULL_RTX)
2904 int regno = REGNO (base);
2906 if (regno != FRAME_POINTER_REGNUM
2907 && regno != STACK_POINTER_REGNUM)
2909 /* Check if the compiler has recorded some information
2910 about the alignment of the base REG. If reload has
2911 completed, we already matched with proper alignments.
2912 If not running global_alloc, reload might give us
2913 unaligned pointer to local stack though. */
2915 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
2916 || (optimize && reload_completed))
2917 && (INTVAL (offset) & (desired - 1)) == 0)
2922 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
2926 else if (! TARGET_UNALIGNED_DOUBLES
2927 || CONSTANT_P (addr)
2928 || GET_CODE (addr) == LO_SUM)
2930 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
2931 is true, in which case we can only assume that an access is aligned if
2932 it is to a constant address, or the address involves a LO_SUM. */
2936 /* An obviously unaligned address. */
2941 /* Vectors to keep interesting information about registers where it can easily
2942 be got. We use to use the actual mode value as the bit number, but there
2943 are more than 32 modes now. Instead we use two tables: one indexed by
2944 hard register number, and one indexed by mode. */
2946 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2947 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2948 mapped into one sparc_mode_class mode. */
2950 enum sparc_mode_class {
2951 S_MODE, D_MODE, T_MODE, O_MODE,
2952 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
2956 /* Modes for single-word and smaller quantities. */
2957 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2959 /* Modes for double-word and smaller quantities. */
2960 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2962 /* Modes for quad-word and smaller quantities. */
2963 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2965 /* Modes for 8-word and smaller quantities. */
2966 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
2968 /* Modes for single-float quantities. We must allow any single word or
2969 smaller quantity. This is because the fix/float conversion instructions
2970 take integer inputs/outputs from the float registers. */
2971 #define SF_MODES (S_MODES)
2973 /* Modes for double-float and smaller quantities. */
2974 #define DF_MODES (S_MODES | D_MODES)
2976 /* Modes for double-float only quantities. */
2977 #define DF_MODES_NO_S (D_MODES)
2979 /* Modes for quad-float only quantities. */
2980 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2982 /* Modes for quad-float and smaller quantities. */
2983 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2985 /* Modes for quad-float and double-float quantities. */
2986 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
2988 /* Modes for quad-float pair only quantities. */
2989 #define OF_ONLY_MODES (1 << (int) OF_MODE)
2991 /* Modes for quad-float pairs and smaller quantities. */
2992 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
2994 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
2996 /* Modes for condition codes. */
2997 #define CC_MODES (1 << (int) CC_MODE)
2998 #define CCFP_MODES (1 << (int) CCFP_MODE)
3000 /* Value is 1 if register/mode pair is acceptable on sparc.
3001 The funny mixture of D and T modes is because integer operations
3002 do not specially operate on tetra quantities, so non-quad-aligned
3003 registers can hold quadword quantities (except %o4 and %i4 because
3004 they cross fixed registers). */
3006 /* This points to either the 32 bit or the 64 bit version. */
3007 int *hard_regno_mode_classes;
3009 static int hard_32bit_mode_classes[] = {
3010 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3011 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3012 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3013 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3015 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3016 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3017 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3018 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3020 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3021 and none can hold SFmode/SImode values. */
3022 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3023 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3024 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3025 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3028 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3034 static int hard_64bit_mode_classes[] = {
3035 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3036 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3037 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3038 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3040 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3041 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3042 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3043 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3045 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3046 and none can hold SFmode/SImode values. */
3047 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3048 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3049 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3050 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3053 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3059 int sparc_mode_class [NUM_MACHINE_MODES];
3061 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3068 for (i = 0; i < NUM_MACHINE_MODES; i++)
3070 switch (GET_MODE_CLASS (i))
3073 case MODE_PARTIAL_INT:
3074 case MODE_COMPLEX_INT:
3075 if (GET_MODE_SIZE (i) <= 4)
3076 sparc_mode_class[i] = 1 << (int) S_MODE;
3077 else if (GET_MODE_SIZE (i) == 8)
3078 sparc_mode_class[i] = 1 << (int) D_MODE;
3079 else if (GET_MODE_SIZE (i) == 16)
3080 sparc_mode_class[i] = 1 << (int) T_MODE;
3081 else if (GET_MODE_SIZE (i) == 32)
3082 sparc_mode_class[i] = 1 << (int) O_MODE;
3084 sparc_mode_class[i] = 0;
3087 case MODE_COMPLEX_FLOAT:
3088 if (GET_MODE_SIZE (i) <= 4)
3089 sparc_mode_class[i] = 1 << (int) SF_MODE;
3090 else if (GET_MODE_SIZE (i) == 8)
3091 sparc_mode_class[i] = 1 << (int) DF_MODE;
3092 else if (GET_MODE_SIZE (i) == 16)
3093 sparc_mode_class[i] = 1 << (int) TF_MODE;
3094 else if (GET_MODE_SIZE (i) == 32)
3095 sparc_mode_class[i] = 1 << (int) OF_MODE;
3097 sparc_mode_class[i] = 0;
3101 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3102 we must explicitly check for them here. */
3103 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3104 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3105 else if (i == (int) CCmode || i == (int) CC_NOOVmode
3106 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3107 sparc_mode_class[i] = 1 << (int) CC_MODE;
3109 sparc_mode_class[i] = 0;
3115 hard_regno_mode_classes = hard_64bit_mode_classes;
3117 hard_regno_mode_classes = hard_32bit_mode_classes;
3119 /* Initialize the array used by REGNO_REG_CLASS. */
3120 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3122 if (i < 16 && TARGET_V8PLUS)
3123 sparc_regno_reg_class[i] = I64_REGS;
3125 sparc_regno_reg_class[i] = GENERAL_REGS;
3127 sparc_regno_reg_class[i] = FP_REGS;
3129 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3131 sparc_regno_reg_class[i] = FPCC_REGS;
3133 sparc_regno_reg_class[i] = NO_REGS;
3137 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3138 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3139 v9 int regs as it simplifies the code. */
3142 save_regs (file, low, high, base, offset, n_regs, real_offset)
3152 if (TARGET_ARCH64 && high <= 32)
3154 for (i = low; i < high; i++)
3156 if (regs_ever_live[i] && ! call_used_regs[i])
3158 fprintf (file, "\tstx\t%s, [%s+%d]\n",
3159 reg_names[i], base, offset + 4 * n_regs);
3160 if (dwarf2out_do_frame ())
3161 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3168 for (i = low; i < high; i += 2)
3170 if (regs_ever_live[i] && ! call_used_regs[i])
3172 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3174 fprintf (file, "\tstd\t%s, [%s+%d]\n",
3175 reg_names[i], base, offset + 4 * n_regs);
3176 if (dwarf2out_do_frame ())
3178 char *l = dwarf2out_cfi_label ();
3179 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
3180 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
3186 fprintf (file, "\tst\t%s, [%s+%d]\n",
3187 reg_names[i], base, offset + 4 * n_regs);
3188 if (dwarf2out_do_frame ())
3189 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3195 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3197 fprintf (file, "\tst\t%s, [%s+%d]\n",
3198 reg_names[i+1], base, offset + 4 * n_regs + 4);
3199 if (dwarf2out_do_frame ())
3200 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
3209 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3211 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3212 v9 int regs as it simplifies the code. */
3215 restore_regs (file, low, high, base, offset, n_regs)
3224 if (TARGET_ARCH64 && high <= 32)
3226 for (i = low; i < high; i++)
3228 if (regs_ever_live[i] && ! call_used_regs[i])
3229 fprintf (file, "\tldx\t[%s+%d], %s\n",
3230 base, offset + 4 * n_regs, reg_names[i]),
3236 for (i = low; i < high; i += 2)
3238 if (regs_ever_live[i] && ! call_used_regs[i])
3239 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3240 fprintf (file, "\tldd\t[%s+%d], %s\n",
3241 base, offset + 4 * n_regs, reg_names[i]),
3244 fprintf (file, "\tld\t[%s+%d], %s\n",
3245 base, offset + 4 * n_regs, reg_names[i]),
3247 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3248 fprintf (file, "\tld\t[%s+%d], %s\n",
3249 base, offset + 4 * n_regs + 4, reg_names[i+1]),
3256 /* Compute the frame size required by the function. This function is called
3257 during the reload pass and also by output_function_prologue(). */
3260 compute_frame_size (size, leaf_function)
3265 int outgoing_args_size = (current_function_outgoing_args_size
3266 + REG_PARM_STACK_SPACE (current_function_decl));
3268 if (TARGET_EPILOGUE)
3270 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3271 even to v9 int regs to be consistent with save_regs/restore_regs. */
3275 for (i = 0; i < 8; i++)
3276 if (regs_ever_live[i] && ! call_used_regs[i])
3281 for (i = 0; i < 8; i += 2)
3282 if ((regs_ever_live[i] && ! call_used_regs[i])
3283 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3287 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3288 if ((regs_ever_live[i] && ! call_used_regs[i])
3289 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3293 /* Set up values for use in `function_epilogue'. */
3294 num_gfregs = n_regs;
3296 if (leaf_function && n_regs == 0
3297 && size == 0 && current_function_outgoing_args_size == 0)
3299 actual_fsize = apparent_fsize = 0;
3303 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3304 The stack bias (if any) is taken out to undo its effects. */
3305 apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8;
3306 apparent_fsize += n_regs * 4;
3307 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3310 /* Make sure nothing can clobber our register windows.
3311 If a SAVE must be done, or there is a stack-local variable,
3312 the register window area must be allocated.
3313 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3314 if (leaf_function == 0 || size > 0)
3315 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3317 return SPARC_STACK_ALIGN (actual_fsize);
3320 /* Build a (32 bit) big number in a register. */
3321 /* ??? We may be able to use the set macro here too. */
3324 build_big_number (file, num, reg)
3329 if (num >= 0 || ! TARGET_ARCH64)
3331 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
3332 if ((num & 0x3ff) != 0)
3333 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
3335 else /* num < 0 && TARGET_ARCH64 */
3337 /* Sethi does not sign extend, so we must use a little trickery
3338 to use it for negative numbers. Invert the constant before
3339 loading it in, then use xor immediate to invert the loaded bits
3340 (along with the upper 32 bits) to the desired constant. This
3341 works because the sethi and immediate fields overlap. */
3344 int low = -0x400 + (asize & 0x3FF);
3346 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3347 inv, reg, reg, low, reg);
3351 /* Output any necessary .register pseudo-ops. */
3353 sparc_output_scratch_registers (file)
3354 FILE *file ATTRIBUTE_UNUSED;
3356 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3362 /* Check if %g[2367] were used without
3363 .register being printed for them already. */
3364 for (i = 2; i < 8; i++)
3366 if (regs_ever_live [i]
3367 && ! sparc_hard_reg_printed [i])
3369 sparc_hard_reg_printed [i] = 1;
3370 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
3377 /* Output code for the function prologue. */
3380 output_function_prologue (file, size, leaf_function)
3385 sparc_output_scratch_registers (file);
3387 /* Need to use actual_fsize, since we are also allocating
3388 space for our callee (and our own register save area). */
3389 actual_fsize = compute_frame_size (size, leaf_function);
3393 frame_base_name = "%sp";
3394 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3398 frame_base_name = "%fp";
3399 frame_base_offset = SPARC_STACK_BIAS;
3402 /* This is only for the human reader. */
3403 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3405 if (actual_fsize == 0)
3407 else if (! leaf_function)
3409 if (actual_fsize <= 4096)
3410 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3411 else if (actual_fsize <= 8192)
3413 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3414 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3418 build_big_number (file, -actual_fsize, "%g1");
3419 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
3422 else /* leaf function */
3424 if (actual_fsize <= 4096)
3425 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3426 else if (actual_fsize <= 8192)
3428 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3429 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3433 build_big_number (file, -actual_fsize, "%g1");
3434 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3438 if (dwarf2out_do_frame () && actual_fsize)
3440 char *label = dwarf2out_cfi_label ();
3442 /* The canonical frame address refers to the top of the frame. */
3443 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3444 : FRAME_POINTER_REGNUM),
3447 if (! leaf_function)
3449 /* Note the register window save. This tells the unwinder that
3450 it needs to restore the window registers from the previous
3451 frame's window save area at 0(cfa). */
3452 dwarf2out_window_save (label);
3454 /* The return address (-8) is now in %i7. */
3455 dwarf2out_return_reg (label, 31);
3459 /* If doing anything with PIC, do it now. */
3461 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3463 /* Call saved registers are saved just above the outgoing argument area. */
3466 int offset, real_offset, n_regs;
3469 real_offset = -apparent_fsize;
3470 offset = -apparent_fsize + frame_base_offset;
3471 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3473 /* ??? This might be optimized a little as %g1 might already have a
3474 value close enough that a single add insn will do. */
3475 /* ??? Although, all of this is probably only a temporary fix
3476 because if %g1 can hold a function result, then
3477 output_function_epilogue will lose (the result will get
3479 build_big_number (file, offset, "%g1");
3480 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3486 base = frame_base_name;
3490 if (TARGET_EPILOGUE && ! leaf_function)
3491 /* ??? Originally saved regs 0-15 here. */
3492 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3493 else if (leaf_function)
3494 /* ??? Originally saved regs 0-31 here. */
3495 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3496 if (TARGET_EPILOGUE)
3497 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3502 if (leaf_function && actual_fsize != 0)
3504 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3505 if (! TARGET_EPILOGUE)
3506 leaf_label = gen_label_rtx ();
3510 /* Output code to restore any call saved registers. */
3513 output_restore_regs (file, leaf_function)
3520 offset = -apparent_fsize + frame_base_offset;
3521 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3523 build_big_number (file, offset, "%g1");
3524 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3530 base = frame_base_name;
3534 if (TARGET_EPILOGUE && ! leaf_function)
3535 /* ??? Originally saved regs 0-15 here. */
3536 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3537 else if (leaf_function)
3538 /* ??? Originally saved regs 0-31 here. */
3539 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3540 if (TARGET_EPILOGUE)
3541 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
3544 /* Output code for the function epilogue. */
3547 output_function_epilogue (file, size, leaf_function)
3549 int size ATTRIBUTE_UNUSED;
3556 emit_label_after (leaf_label, get_last_insn ());
3557 final_scan_insn (get_last_insn (), file, 0, 0, 1);
3560 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3561 else if (profile_block_flag == 2)
3563 FUNCTION_BLOCK_PROFILER_EXIT(file);
3567 else if (current_function_epilogue_delay_list == 0)
3569 /* If code does not drop into the epilogue, we need
3570 do nothing except output pending case vectors. */
3571 rtx insn = get_last_insn ();
3572 if (GET_CODE (insn) == NOTE)
3573 insn = prev_nonnote_insn (insn);
3574 if (insn && GET_CODE (insn) == BARRIER)
3575 goto output_vectors;
3579 output_restore_regs (file, leaf_function);
3581 /* Work out how to skip the caller's unimp instruction if required. */
3583 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
3585 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
3587 if (TARGET_EPILOGUE || leaf_label)
3589 int old_target_epilogue = TARGET_EPILOGUE;
3590 target_flags &= ~old_target_epilogue;
3592 if (! leaf_function)
3594 /* If we wound up with things in our delay slot, flush them here. */
3595 if (current_function_epilogue_delay_list)
3597 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
3599 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
3601 epilogue_renumber (&delay, 0);
3602 fputs (SKIP_CALLERS_UNIMP_P
3603 ? "\treturn\t%i7+12\n"
3604 : "\treturn\t%i7+8\n", file);
3605 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), file, 1, 0, 0);
3609 rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode),
3613 if (GET_CODE (delay) != SET)
3616 src = SET_SRC (delay);
3617 if (GET_CODE (src) == ASHIFT)
3619 if (XEXP (src, 1) != const1_rtx)
3621 SET_SRC (delay) = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
3625 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode,
3626 gen_rtvec (2, delay, PATTERN (insn)));
3627 final_scan_insn (insn, file, 1, 0, 1);
3630 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
3631 fputs ("\treturn\t%i7+8\n\tnop\n", file);
3633 fprintf (file, "\t%s\n\trestore\n", ret);
3635 /* All of the following cases are for leaf functions. */
3636 else if (current_function_epilogue_delay_list)
3638 /* eligible_for_epilogue_delay_slot ensures that if this is a
3639 leaf function, then we will only have insn in the delay slot
3640 if the frame size is zero, thus no adjust for the stack is
3642 if (actual_fsize != 0)
3644 fprintf (file, "\t%s\n", ret);
3645 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
3648 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3649 avoid generating confusing assembly language output. */
3650 else if (actual_fsize == 0)
3651 fprintf (file, "\t%s\n\tnop\n", ret);
3652 else if (actual_fsize <= 4096)
3653 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
3654 else if (actual_fsize <= 8192)
3655 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
3656 ret, actual_fsize - 4096);
3657 else if ((actual_fsize & 0x3ff) == 0)
3658 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3661 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3662 actual_fsize, actual_fsize, ret);
3663 target_flags |= old_target_epilogue;
3667 sparc_output_deferred_case_vectors ();
3670 /* Output a sibling call. */
3673 output_sibcall (insn, call_operand)
3674 rtx insn, call_operand;
3676 int leaf_regs = current_function_uses_only_leaf_regs;
3678 int delay_slot = dbr_sequence_length () > 0;
3682 /* Call to restore global regs might clobber
3683 the delay slot. Instead of checking for this
3684 output the delay slot now. */
3687 rtx delay = NEXT_INSN (insn);
3692 final_scan_insn (delay, asm_out_file, 1, 0, 1);
3693 PATTERN (delay) = gen_blockage ();
3694 INSN_CODE (delay) = -1;
3697 output_restore_regs (asm_out_file, leaf_regs);
3700 operands[0] = call_operand;
3704 #ifdef HAVE_AS_RELAX_OPTION
3705 /* If as and ld are relaxing tail call insns into branch always,
3706 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
3707 be optimized. With sethi/jmpl as nor ld has no easy way how to
3708 find out if somebody does not branch between the sethi and jmpl. */
3711 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
3715 if ((actual_fsize || ! spare_slot) && delay_slot)
3717 rtx delay = NEXT_INSN (insn);
3722 final_scan_insn (delay, asm_out_file, 1, 0, 1);
3723 PATTERN (delay) = gen_blockage ();
3724 INSN_CODE (delay) = -1;
3729 if (actual_fsize <= 4096)
3730 size = actual_fsize;
3731 else if (actual_fsize <= 8192)
3733 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
3734 size = actual_fsize - 4096;
3736 else if ((actual_fsize & 0x3ff) == 0)
3737 fprintf (asm_out_file,
3738 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
3742 fprintf (asm_out_file,
3743 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
3744 actual_fsize, actual_fsize);
3745 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
3750 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
3751 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
3753 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size);
3754 else if (! delay_slot)
3755 fputs ("\t nop\n", asm_out_file);
3760 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size);
3761 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
3762 it into branch if possible. */
3763 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
3764 output_asm_insn ("call\t%a0, 0", operands);
3765 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
3770 output_asm_insn ("call\t%a0, 0", operands);
3773 rtx delay = NEXT_INSN (insn), pat;
3778 pat = PATTERN (delay);
3779 if (GET_CODE (pat) != SET)
3782 operands[0] = SET_DEST (pat);
3783 pat = SET_SRC (pat);
3784 switch (GET_CODE (pat))
3787 operands[1] = XEXP (pat, 0);
3788 operands[2] = XEXP (pat, 1);
3789 output_asm_insn (" restore %r1, %2, %Y0", operands);
3792 operands[1] = XEXP (pat, 0);
3793 operands[2] = XEXP (pat, 1);
3794 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
3797 operands[1] = XEXP (pat, 0);
3798 output_asm_insn (" restore %r1, %r1, %Y0", operands);
3802 output_asm_insn (" restore %%g0, %1, %Y0", operands);
3805 PATTERN (delay) = gen_blockage ();
3806 INSN_CODE (delay) = -1;
3809 fputs ("\t restore\n", asm_out_file);
3813 /* Functions for handling argument passing.
3815 For v8 the first six args are normally in registers and the rest are
3816 pushed. Any arg that starts within the first 6 words is at least
3817 partially passed in a register unless its data type forbids.
3819 For v9, the argument registers are laid out as an array of 16 elements
3820 and arguments are added sequentially. The first 6 int args and up to the
3821 first 16 fp args (depending on size) are passed in regs.
3823 Slot Stack Integral Float Float in structure Double Long Double
3824 ---- ----- -------- ----- ------------------ ------ -----------
3825 15 [SP+248] %f31 %f30,%f31 %d30
3826 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3827 13 [SP+232] %f27 %f26,%f27 %d26
3828 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3829 11 [SP+216] %f23 %f22,%f23 %d22
3830 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3831 9 [SP+200] %f19 %f18,%f19 %d18
3832 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3833 7 [SP+184] %f15 %f14,%f15 %d14
3834 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3835 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3836 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3837 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3838 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3839 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3840 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3842 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3844 Integral arguments are always passed as 64 bit quantities appropriately
3847 Passing of floating point values is handled as follows.
3848 If a prototype is in scope:
3849 If the value is in a named argument (i.e. not a stdarg function or a
3850 value not part of the `...') then the value is passed in the appropriate
3852 If the value is part of the `...' and is passed in one of the first 6
3853 slots then the value is passed in the appropriate int reg.
3854 If the value is part of the `...' and is not passed in one of the first 6
3855 slots then the value is passed in memory.
3856 If a prototype is not in scope:
3857 If the value is one of the first 6 arguments the value is passed in the
3858 appropriate integer reg and the appropriate fp reg.
3859 If the value is not one of the first 6 arguments the value is passed in
3860 the appropriate fp reg and in memory.
3863 /* Maximum number of int regs for args. */
3864 #define SPARC_INT_ARG_MAX 6
3865 /* Maximum number of fp regs for args. */
3866 #define SPARC_FP_ARG_MAX 16
3868 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3870 /* Handle the INIT_CUMULATIVE_ARGS macro.
3871 Initialize a variable CUM of type CUMULATIVE_ARGS
3872 for a call to a function whose data type is FNTYPE.
3873 For a library call, FNTYPE is 0. */
3876 init_cumulative_args (cum, fntype, libname, indirect)
3877 CUMULATIVE_ARGS *cum;
3879 rtx libname ATTRIBUTE_UNUSED;
3880 int indirect ATTRIBUTE_UNUSED;
3883 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
3884 cum->libcall_p = fntype == 0;
3887 /* Compute the slot number to pass an argument in.
3888 Returns the slot number or -1 if passing on the stack.
3890 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3891 the preceding args and about the function being called.
3892 MODE is the argument's machine mode.
3893 TYPE is the data type of the argument (as a tree).
3894 This is null for libcalls where that information may
3896 NAMED is nonzero if this argument is a named parameter
3897 (otherwise it is an extra parameter matching an ellipsis).
3898 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3899 *PREGNO records the register number to use if scalar type.
3900 *PPADDING records the amount of padding needed in words. */
3903 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
3904 const CUMULATIVE_ARGS *cum;
3905 enum machine_mode mode;
3912 int regbase = (incoming_p
3913 ? SPARC_INCOMING_INT_ARG_FIRST
3914 : SPARC_OUTGOING_INT_ARG_FIRST);
3915 int slotno = cum->words;
3920 if (type != 0 && TREE_ADDRESSABLE (type))
3923 && type != 0 && mode == BLKmode
3924 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
3930 /* MODE is VOIDmode when generating the actual call.
3934 case QImode : case CQImode :
3935 case HImode : case CHImode :
3936 case SImode : case CSImode :
3937 case DImode : case CDImode :
3938 case TImode : case CTImode :
3939 if (slotno >= SPARC_INT_ARG_MAX)
3941 regno = regbase + slotno;
3944 case SFmode : case SCmode :
3945 case DFmode : case DCmode :
3946 case TFmode : case TCmode :
3949 if (slotno >= SPARC_INT_ARG_MAX)
3951 regno = regbase + slotno;
3955 if ((mode == TFmode || mode == TCmode)
3956 && (slotno & 1) != 0)
3957 slotno++, *ppadding = 1;
3958 if (TARGET_FPU && named)
3960 if (slotno >= SPARC_FP_ARG_MAX)
3962 regno = SPARC_FP_ARG_FIRST + slotno * 2;
3968 if (slotno >= SPARC_INT_ARG_MAX)
3970 regno = regbase + slotno;
3976 /* For sparc64, objects requiring 16 byte alignment get it. */
3979 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
3980 slotno++, *ppadding = 1;
3984 || (type && TREE_CODE (type) == UNION_TYPE))
3986 if (slotno >= SPARC_INT_ARG_MAX)
3988 regno = regbase + slotno;
3993 int intregs_p = 0, fpregs_p = 0;
3994 /* The ABI obviously doesn't specify how packed
3995 structures are passed. These are defined to be passed
3996 in int regs if possible, otherwise memory. */
3999 /* First see what kinds of registers we need. */
4000 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4002 if (TREE_CODE (field) == FIELD_DECL)
4004 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4009 if (DECL_PACKED (field))
4013 if (packed_p || !named)
4014 fpregs_p = 0, intregs_p = 1;
4016 /* If all arg slots are filled, then must pass on stack. */
4017 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4019 /* If there are only int args and all int arg slots are filled,
4020 then must pass on stack. */
4021 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4023 /* Note that even if all int arg slots are filled, fp members may
4024 still be passed in regs if such regs are available.
4025 *PREGNO isn't set because there may be more than one, it's up
4026 to the caller to compute them. */
4039 /* Handle recursive register counting for structure field layout. */
4041 struct function_arg_record_value_parms
4044 int slotno, named, regbase;
4049 static void function_arg_record_value_3
4050 PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *));
4051 static void function_arg_record_value_2
4052 PARAMS ((tree, HOST_WIDE_INT,
4053 struct function_arg_record_value_parms *));
4054 static void function_arg_record_value_1
4055 PARAMS ((tree, HOST_WIDE_INT,
4056 struct function_arg_record_value_parms *));
4057 static rtx function_arg_record_value
4058 PARAMS ((tree, enum machine_mode, int, int, int));
4061 function_arg_record_value_1 (type, startbitpos, parms)
4063 HOST_WIDE_INT startbitpos;
4064 struct function_arg_record_value_parms *parms;
4068 /* The ABI obviously doesn't specify how packed structures are
4069 passed. These are defined to be passed in int regs if possible,
4070 otherwise memory. */
4073 /* We need to compute how many registers are needed so we can
4074 allocate the PARALLEL but before we can do that we need to know
4075 whether there are any packed fields. If there are, int regs are
4076 used regardless of whether there are fp values present. */
4077 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4079 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4086 /* Compute how many registers we need. */
4087 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4089 if (TREE_CODE (field) == FIELD_DECL)
4091 HOST_WIDE_INT bitpos = startbitpos;
4093 if (DECL_SIZE (field) != 0
4094 && host_integerp (bit_position (field), 1))
4095 bitpos += int_bit_position (field);
4097 /* ??? FIXME: else assume zero offset. */
4099 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4100 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
4101 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4106 if (parms->intoffset != -1)
4108 int intslots, this_slotno;
4110 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
4112 this_slotno = parms->slotno + parms->intoffset
4115 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4116 intslots = MAX (intslots, 0);
4117 parms->nregs += intslots;
4118 parms->intoffset = -1;
4121 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4122 If it wasn't true we wouldn't be here. */
4127 if (parms->intoffset == -1)
4128 parms->intoffset = bitpos;
4134 /* Handle recursive structure field register assignment. */
4137 function_arg_record_value_3 (bitpos, parms)
4138 HOST_WIDE_INT bitpos;
4139 struct function_arg_record_value_parms *parms;
4141 enum machine_mode mode;
4143 int this_slotno, intslots, intoffset;
4146 if (parms->intoffset == -1)
4149 intoffset = parms->intoffset;
4150 parms->intoffset = -1;
4152 intslots = (bitpos - intoffset + BITS_PER_WORD - 1) / BITS_PER_WORD;
4153 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
4155 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4159 /* If this is the trailing part of a word, only load that much into
4160 the register. Otherwise load the whole register. Note that in
4161 the latter case we may pick up unwanted bits. It's not a problem
4162 at the moment but may wish to revisit. */
4164 if (intoffset % BITS_PER_WORD != 0)
4165 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4170 intoffset /= BITS_PER_UNIT;
4173 regno = parms->regbase + this_slotno;
4174 reg = gen_rtx_REG (mode, regno);
4175 XVECEXP (parms->ret, 0, parms->nregs)
4176 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4179 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4183 while (intslots > 0);
4187 function_arg_record_value_2 (type, startbitpos, parms)
4189 HOST_WIDE_INT startbitpos;
4190 struct function_arg_record_value_parms *parms;
4195 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4197 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4204 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4206 if (TREE_CODE (field) == FIELD_DECL)
4208 HOST_WIDE_INT bitpos = startbitpos;
4210 if (DECL_SIZE (field) != 0
4211 && host_integerp (bit_position (field), 1))
4212 bitpos += int_bit_position (field);
4214 /* ??? FIXME: else assume zero offset. */
4216 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4217 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
4218 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4223 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
4226 function_arg_record_value_3 (bitpos, parms);
4228 reg = gen_rtx_REG (DECL_MODE (field),
4229 (SPARC_FP_ARG_FIRST + this_slotno * 2
4230 + (DECL_MODE (field) == SFmode
4231 && (bitpos & 32) != 0)));
4232 XVECEXP (parms->ret, 0, parms->nregs)
4233 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4234 GEN_INT (bitpos / BITS_PER_UNIT));
4239 if (parms->intoffset == -1)
4240 parms->intoffset = bitpos;
4247 function_arg_record_value (type, mode, slotno, named, regbase)
4249 enum machine_mode mode;
4250 int slotno, named, regbase;
4252 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4253 struct function_arg_record_value_parms parms;
4256 parms.ret = NULL_RTX;
4257 parms.slotno = slotno;
4258 parms.named = named;
4259 parms.regbase = regbase;
4261 /* Compute how many registers we need. */
4263 parms.intoffset = 0;
4264 function_arg_record_value_1 (type, 0, &parms);
4266 if (parms.intoffset != -1)
4268 int intslots, this_slotno;
4270 intslots = (typesize*BITS_PER_UNIT - parms.intoffset + BITS_PER_WORD - 1)
4272 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
4274 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4275 intslots = MAX (intslots, 0);
4277 parms.nregs += intslots;
4279 nregs = parms.nregs;
4281 /* Allocate the vector and handle some annoying special cases. */
4284 /* ??? Empty structure has no value? Duh? */
4287 /* Though there's nothing really to store, return a word register
4288 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4289 leads to breakage due to the fact that there are zero bytes to
4291 return gen_rtx_REG (mode, regbase);
4295 /* ??? C++ has structures with no fields, and yet a size. Give up
4296 for now and pass everything back in integer registers. */
4297 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4299 if (nregs + slotno > SPARC_INT_ARG_MAX)
4300 nregs = SPARC_INT_ARG_MAX - slotno;
4305 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
4307 /* Fill in the entries. */
4309 parms.intoffset = 0;
4310 function_arg_record_value_2 (type, 0, &parms);
4311 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
4313 if (parms.nregs != nregs)
4319 /* Handle the FUNCTION_ARG macro.
4320 Determine where to put an argument to a function.
4321 Value is zero to push the argument on the stack,
4322 or a hard register in which to store the argument.
4324 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4325 the preceding args and about the function being called.
4326 MODE is the argument's machine mode.
4327 TYPE is the data type of the argument (as a tree).
4328 This is null for libcalls where that information may
4330 NAMED is nonzero if this argument is a named parameter
4331 (otherwise it is an extra parameter matching an ellipsis).
4332 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4335 function_arg (cum, mode, type, named, incoming_p)
4336 const CUMULATIVE_ARGS *cum;
4337 enum machine_mode mode;
4342 int regbase = (incoming_p
4343 ? SPARC_INCOMING_INT_ARG_FIRST
4344 : SPARC_OUTGOING_INT_ARG_FIRST);
4345 int slotno, regno, padding;
4348 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
4356 reg = gen_rtx_REG (mode, regno);
4360 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4361 but also have the slot allocated for them.
4362 If no prototype is in scope fp values in register slots get passed
4363 in two places, either fp regs and int regs or fp regs and memory. */
4364 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4365 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4366 && SPARC_FP_REG_P (regno))
4368 reg = gen_rtx_REG (mode, regno);
4369 if (cum->prototype_p || cum->libcall_p)
4371 /* "* 2" because fp reg numbers are recorded in 4 byte
4374 /* ??? This will cause the value to be passed in the fp reg and
4375 in the stack. When a prototype exists we want to pass the
4376 value in the reg but reserve space on the stack. That's an
4377 optimization, and is deferred [for a bit]. */
4378 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
4379 return gen_rtx_PARALLEL (mode,
4381 gen_rtx_EXPR_LIST (VOIDmode,
4382 NULL_RTX, const0_rtx),
4383 gen_rtx_EXPR_LIST (VOIDmode,
4387 /* ??? It seems that passing back a register even when past
4388 the area declared by REG_PARM_STACK_SPACE will allocate
4389 space appropriately, and will not copy the data onto the
4390 stack, exactly as we desire.
4392 This is due to locate_and_pad_parm being called in
4393 expand_call whenever reg_parm_stack_space > 0, which
4394 while benefical to our example here, would seem to be
4395 in error from what had been intended. Ho hum... -- r~ */
4403 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
4407 /* On incoming, we don't need to know that the value
4408 is passed in %f0 and %i0, and it confuses other parts
4409 causing needless spillage even on the simplest cases. */
4413 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
4414 + (regno - SPARC_FP_ARG_FIRST) / 2);
4416 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4417 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
4419 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4423 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4424 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4425 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4429 else if (type && TREE_CODE (type) == RECORD_TYPE)
4431 /* Structures up to 16 bytes in size are passed in arg slots on the
4432 stack and are promoted to registers where possible. */
4434 if (int_size_in_bytes (type) > 16)
4435 abort (); /* shouldn't get here */
4437 return function_arg_record_value (type, mode, slotno, named, regbase);
4439 else if (type && TREE_CODE (type) == UNION_TYPE)
4441 enum machine_mode mode;
4442 int bytes = int_size_in_bytes (type);
4447 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4448 reg = gen_rtx_REG (mode, regno);
4452 /* Scalar or complex int. */
4453 reg = gen_rtx_REG (mode, regno);
4459 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4460 For an arg passed partly in registers and partly in memory,
4461 this is the number of registers used.
4462 For args passed entirely in registers or entirely in memory, zero.
4464 Any arg that starts in the first 6 regs but won't entirely fit in them
4465 needs partial registers on v8. On v9, structures with integer
4466 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4467 values that begin in the last fp reg [where "last fp reg" varies with the
4468 mode] will be split between that reg and memory. */
4471 function_arg_partial_nregs (cum, mode, type, named)
4472 const CUMULATIVE_ARGS *cum;
4473 enum machine_mode mode;
4477 int slotno, regno, padding;
4479 /* We pass 0 for incoming_p here, it doesn't matter. */
4480 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4487 if ((slotno + (mode == BLKmode
4488 ? ROUND_ADVANCE (int_size_in_bytes (type))
4489 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
4490 > NPARM_REGS (SImode))
4491 return NPARM_REGS (SImode) - slotno;
4496 if (type && AGGREGATE_TYPE_P (type))
4498 int size = int_size_in_bytes (type);
4499 int align = TYPE_ALIGN (type);
4502 slotno += slotno & 1;
4503 if (size > 8 && size <= 16
4504 && slotno == SPARC_INT_ARG_MAX - 1)
4507 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
4508 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4511 if (GET_MODE_ALIGNMENT (mode) == 128)
4513 slotno += slotno & 1;
4514 if (slotno == SPARC_INT_ARG_MAX - 2)
4519 if (slotno == SPARC_INT_ARG_MAX - 1)
4523 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4525 if (GET_MODE_ALIGNMENT (mode) == 128)
4526 slotno += slotno & 1;
4527 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
4535 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
4536 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
4537 quad-precision floats by invisible reference.
4538 v9: Aggregates greater than 16 bytes are passed by reference.
4539 For Pascal, also pass arrays by reference. */
4542 function_arg_pass_by_reference (cum, mode, type, named)
4543 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
4544 enum machine_mode mode;
4546 int named ATTRIBUTE_UNUSED;
4550 return ((type && AGGREGATE_TYPE_P (type))
4551 || mode == TFmode || mode == TCmode);
4555 return ((type && TREE_CODE (type) == ARRAY_TYPE)
4556 /* Consider complex values as aggregates, so care for TCmode. */
4557 || GET_MODE_SIZE (mode) > 16
4558 || (type && AGGREGATE_TYPE_P (type)
4559 && int_size_in_bytes (type) > 16));
4563 /* Handle the FUNCTION_ARG_ADVANCE macro.
4564 Update the data in CUM to advance over an argument
4565 of mode MODE and data type TYPE.
4566 TYPE is null for libcalls where that information may not be available. */
4569 function_arg_advance (cum, mode, type, named)
4570 CUMULATIVE_ARGS *cum;
4571 enum machine_mode mode;
4575 int slotno, regno, padding;
4577 /* We pass 0 for incoming_p here, it doesn't matter. */
4578 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4580 /* If register required leading padding, add it. */
4582 cum->words += padding;
4586 cum->words += (mode != BLKmode
4587 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4588 : ROUND_ADVANCE (int_size_in_bytes (type)));
4592 if (type && AGGREGATE_TYPE_P (type))
4594 int size = int_size_in_bytes (type);
4598 else if (size <= 16)
4600 else /* passed by reference */
4603 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
4607 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4609 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
4613 cum->words += (mode != BLKmode
4614 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4615 : ROUND_ADVANCE (int_size_in_bytes (type)));
4620 /* Handle the FUNCTION_ARG_PADDING macro.
4621 For the 64 bit ABI structs are always stored left shifted in their
4625 function_arg_padding (mode, type)
4626 enum machine_mode mode;
4629 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
4632 /* This is the default definition. */
4633 return (! BYTES_BIG_ENDIAN
4636 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
4637 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
4638 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
4639 ? downward : upward));
4642 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
4643 For v9, function return values are subject to the same rules as arguments,
4644 except that up to 32-bytes may be returned in registers. */
4647 function_value (type, mode, incoming_p)
4649 enum machine_mode mode;
4653 int regbase = (incoming_p
4654 ? SPARC_OUTGOING_INT_ARG_FIRST
4655 : SPARC_INCOMING_INT_ARG_FIRST);
4657 if (TARGET_ARCH64 && type)
4659 if (TREE_CODE (type) == RECORD_TYPE)
4661 /* Structures up to 32 bytes in size are passed in registers,
4662 promoted to fp registers where possible. */
4664 if (int_size_in_bytes (type) > 32)
4665 abort (); /* shouldn't get here */
4667 return function_arg_record_value (type, mode, 0, 1, regbase);
4669 else if (TREE_CODE (type) == UNION_TYPE)
4671 int bytes = int_size_in_bytes (type);
4676 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4681 && GET_MODE_CLASS (mode) == MODE_INT
4682 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
4683 && type && TREE_CODE (type) != UNION_TYPE)
4687 regno = BASE_RETURN_VALUE_REG (mode);
4689 regno = BASE_OUTGOING_VALUE_REG (mode);
4691 return gen_rtx_REG (mode, regno);
4694 /* Do what is necessary for `va_start'. We look at the current function
4695 to determine if stdarg or varargs is used and return the address of
4696 the first unnamed parameter. */
4699 sparc_builtin_saveregs ()
4701 int first_reg = current_function_args_info.words;
4705 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
4706 emit_move_insn (gen_rtx_MEM (word_mode,
4707 gen_rtx_PLUS (Pmode,
4709 GEN_INT (STACK_POINTER_OFFSET
4710 + UNITS_PER_WORD * regno))),
4711 gen_rtx_REG (word_mode,
4712 BASE_INCOMING_ARG_REG (word_mode) + regno));
4714 address = gen_rtx_PLUS (Pmode,
4716 GEN_INT (STACK_POINTER_OFFSET
4717 + UNITS_PER_WORD * first_reg));
4719 if (current_function_check_memory_usage
4720 && first_reg < NPARM_REGS (word_mode))
4721 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4723 GEN_INT (UNITS_PER_WORD
4724 * (NPARM_REGS (word_mode) - first_reg)),
4725 TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW),
4726 TYPE_MODE (integer_type_node));
4731 /* Implement `va_start' for varargs and stdarg. */
4734 sparc_va_start (stdarg_p, valist, nextarg)
4735 int stdarg_p ATTRIBUTE_UNUSED;
4739 nextarg = expand_builtin_saveregs ();
4740 std_expand_builtin_va_start (1, valist, nextarg);
4743 /* Implement `va_arg'. */
4746 sparc_va_arg (valist, type)
4749 HOST_WIDE_INT size, rsize, align;
4754 /* Round up sizeof(type) to a word. */
4755 size = int_size_in_bytes (type);
4756 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4761 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
4762 align = 2 * UNITS_PER_WORD;
4764 if (AGGREGATE_TYPE_P (type))
4769 size = rsize = UNITS_PER_WORD;
4777 if (AGGREGATE_TYPE_P (type)
4778 || TYPE_MODE (type) == TFmode
4779 || TYPE_MODE (type) == TCmode)
4782 size = rsize = UNITS_PER_WORD;
4789 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4790 build_int_2 (align - 1, 0)));
4791 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
4792 build_int_2 (-align, -1)));
4795 addr = incr = save_expr (incr);
4796 if (BYTES_BIG_ENDIAN && size < rsize)
4798 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4799 build_int_2 (rsize - size, 0)));
4801 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4802 build_int_2 (rsize, 0)));
4804 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
4805 TREE_SIDE_EFFECTS (incr) = 1;
4806 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
4808 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
4810 /* If the address isn't aligned properly for the type,
4811 we may need to copy to a temporary.
4812 FIXME: This is inefficient. Usually we can do this
4815 && TYPE_ALIGN (type) > BITS_PER_WORD
4818 /* FIXME: We really need to specify that the temporary is live
4819 for the whole function because expand_builtin_va_arg wants
4820 the alias set to be get_varargs_alias_set (), but in this
4821 case the alias set is that for TYPE and if the memory gets
4822 reused it will be reused with alias set TYPE. */
4823 rtx tmp = assign_temp (type, 0, 1, 0);
4826 addr_rtx = force_reg (Pmode, addr_rtx);
4827 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
4828 MEM_ALIAS_SET (addr_rtx) = get_varargs_alias_set ();
4829 tmp = shallow_copy_rtx (tmp);
4830 PUT_MODE (tmp, BLKmode);
4831 MEM_ALIAS_SET (tmp) = 0;
4833 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
4835 if (dest_addr != NULL_RTX)
4836 addr_rtx = dest_addr;
4838 addr_rtx = XCEXP (tmp, 0, MEM);
4843 addr_rtx = force_reg (Pmode, addr_rtx);
4844 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
4845 MEM_ALIAS_SET (addr_rtx) = get_varargs_alias_set ();
4851 /* Return the string to output a conditional branch to LABEL, which is
4852 the operand number of the label. OP is the conditional expression.
4853 XEXP (OP, 0) is assumed to be a condition code register (integer or
4854 floating point) and its mode specifies what kind of comparison we made.
4856 REVERSED is non-zero if we should reverse the sense of the comparison.
4858 ANNUL is non-zero if we should generate an annulling branch.
4860 NOOP is non-zero if we have to follow this branch by a noop.
4862 INSN, if set, is the insn. */
4865 output_cbranch (op, label, reversed, annul, noop, insn)
4868 int reversed, annul, noop;
4871 static char string[32];
4872 enum rtx_code code = GET_CODE (op);
4873 rtx cc_reg = XEXP (op, 0);
4874 enum machine_mode mode = GET_MODE (cc_reg);
4875 static char v8_labelno[] = "%lX";
4876 static char v9_icc_labelno[] = "%%icc, %lX";
4877 static char v9_xcc_labelno[] = "%%xcc, %lX";
4878 static char v9_fcc_labelno[] = "%%fccX, %lY";
4881 int labeloff, spaces = 8;
4885 /* Reversal of FP compares takes care -- an ordered compare
4886 becomes an unordered compare and vice versa. */
4887 if (mode == CCFPmode || mode == CCFPEmode)
4888 code = reverse_condition_maybe_unordered (code);
4890 code = reverse_condition (code);
4893 /* Start by writing the branch condition. */
4894 if (mode == CCFPmode || mode == CCFPEmode)
4945 /* ??? !v9: FP branches cannot be preceded by another floating point
4946 insn. Because there is currently no concept of pre-delay slots,
4947 we can fix this only by always emitting a nop before a floating
4952 strcpy (string, "nop\n\t");
4953 strcat (string, branch);
4966 if (mode == CC_NOOVmode)
4978 if (mode == CC_NOOVmode)
4999 strcpy (string, branch);
5001 spaces -= strlen (branch);
5003 /* Now add the annulling, the label, and a possible noop. */
5006 strcat (string, ",a");
5013 labelno = v8_labelno;
5019 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
5022 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
5027 if (mode == CCFPmode || mode == CCFPEmode)
5030 labelno = v9_fcc_labelno;
5031 /* Set the char indicating the number of the fcc reg to use. */
5032 labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5034 else if (mode == CCXmode || mode == CCX_NOOVmode)
5035 labelno = v9_xcc_labelno;
5037 labelno = v9_icc_labelno;
5039 /* Set the char indicating the number of the operand containing the
5041 labelno[labeloff] = label + '0';
5043 strcat (string, "\t");
5045 strcat (string, " ");
5046 strcat (string, labelno);
5049 strcat (string, "\n\tnop");
5054 /* Emit a library call comparison between floating point X and Y.
5055 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5056 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5057 values as arguments instead of the TFmode registers themselves,
5058 that's why we cannot call emit_float_lib_cmp. */
5060 sparc_emit_float_lib_cmp (x, y, comparison)
5062 enum rtx_code comparison;
5065 rtx slot0, slot1, result, tem, tem2;
5066 enum machine_mode mode;
5071 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
5075 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
5079 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
5083 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
5087 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
5091 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
5102 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
5112 if (GET_CODE (x) != MEM)
5114 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5115 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
5120 if (GET_CODE (y) != MEM)
5122 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5123 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
5128 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), 1,
5130 XEXP (slot0, 0), Pmode,
5131 XEXP (slot1, 0), Pmode);
5137 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), 1,
5139 x, TFmode, y, TFmode);
5145 /* Immediately move the result of the libcall into a pseudo
5146 register so reload doesn't clobber the value if it needs
5147 the return register for a spill reg. */
5148 result = gen_reg_rtx (mode);
5149 emit_move_insn (result, hard_libcall_value (mode));
5154 emit_cmp_insn (result, const0_rtx, NE,
5155 NULL_RTX, mode, 0, 0);
5159 emit_cmp_insn (result, GEN_INT(3),
5160 (comparison == UNORDERED) ? EQ : NE,
5161 NULL_RTX, mode, 0, 0);
5165 emit_cmp_insn (result, const1_rtx,
5166 (comparison == UNGT) ? GT : NE,
5167 NULL_RTX, mode, 0, 0);
5170 emit_cmp_insn (result, const2_rtx, NE,
5171 NULL_RTX, mode, 0, 0);
5174 tem = gen_reg_rtx (mode);
5176 emit_insn (gen_andsi3 (tem, result, const1_rtx));
5178 emit_insn (gen_anddi3 (tem, result, const1_rtx));
5179 emit_cmp_insn (tem, const0_rtx, NE,
5180 NULL_RTX, mode, 0, 0);
5184 tem = gen_reg_rtx (mode);
5186 emit_insn (gen_addsi3 (tem, result, const1_rtx));
5188 emit_insn (gen_adddi3 (tem, result, const1_rtx));
5189 tem2 = gen_reg_rtx (mode);
5191 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
5193 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
5194 emit_cmp_insn (tem2, const0_rtx,
5195 (comparison == UNEQ) ? EQ : NE,
5196 NULL_RTX, mode, 0, 0);
5201 /* Return the string to output a conditional branch to LABEL, testing
5202 register REG. LABEL is the operand number of the label; REG is the
5203 operand number of the reg. OP is the conditional expression. The mode
5204 of REG says what kind of comparison we made.
5206 REVERSED is non-zero if we should reverse the sense of the comparison.
5208 ANNUL is non-zero if we should generate an annulling branch.
5210 NOOP is non-zero if we have to follow this branch by a noop. */
5213 output_v9branch (op, reg, label, reversed, annul, noop, insn)
5216 int reversed, annul, noop;
5219 static char string[20];
5220 enum rtx_code code = GET_CODE (op);
5221 enum machine_mode mode = GET_MODE (XEXP (op, 0));
5222 static char labelno[] = "%X, %lX";
5226 /* If not floating-point or if EQ or NE, we can just reverse the code. */
5228 code = reverse_condition (code), reversed = 0;
5230 /* Only 64 bit versions of these instructions exist. */
5234 /* Start by writing the branch condition. */
5239 strcpy (string, "brnz");
5244 strcpy (string, "brz");
5249 strcpy (string, "brgez");
5254 strcpy (string, "brlz");
5259 strcpy (string, "brlez");
5264 strcpy (string, "brgz");
5272 /* Now add the annulling, reg, label, and nop. */
5275 strcat (string, ",a");
5279 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
5282 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
5286 labelno[1] = reg + '0';
5287 labelno[6] = label + '0';
5289 strcat (string, "\t");
5291 strcat (string, " ");
5292 strcat (string, labelno);
5295 strcat (string, "\n\tnop");
5300 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
5301 Such instructions cannot be used in the delay slot of return insn on v9.
5302 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
5306 epilogue_renumber (where, test)
5307 register rtx *where;
5310 register const char *fmt;
5312 register enum rtx_code code;
5317 code = GET_CODE (*where);
5322 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
5324 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
5325 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
5337 fmt = GET_RTX_FORMAT (code);
5339 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5344 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5345 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
5348 else if (fmt[i] == 'e'
5349 && epilogue_renumber (&(XEXP (*where, i)), test))
5355 /* Output assembler code to return from a function. */
5358 output_return (operands)
5361 rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0;
5365 operands[0] = leaf_label;
5368 else if (current_function_uses_only_leaf_regs)
5370 /* No delay slot in a leaf function. */
5374 /* If we didn't allocate a frame pointer for the current function,
5375 the stack pointer might have been adjusted. Output code to
5378 operands[0] = GEN_INT (actual_fsize);
5380 /* Use sub of negated value in first two cases instead of add to
5381 allow actual_fsize == 4096. */
5383 if (actual_fsize <= 4096)
5385 if (SKIP_CALLERS_UNIMP_P)
5386 return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
5388 return "retl\n\tsub\t%%sp, -%0, %%sp";
5390 else if (actual_fsize <= 8192)
5392 operands[0] = GEN_INT (actual_fsize - 4096);
5393 if (SKIP_CALLERS_UNIMP_P)
5394 return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
5396 return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
5398 else if (SKIP_CALLERS_UNIMP_P)
5400 if ((actual_fsize & 0x3ff) != 0)
5401 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
5403 return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
5407 if ((actual_fsize & 0x3ff) != 0)
5408 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tretl\n\tadd\t%%sp, %%g1, %%sp";
5410 return "sethi\t%%hi(%a0), %%g1\n\tretl\n\tadd\t%%sp, %%g1, %%sp";
5417 epilogue_renumber (&SET_DEST (PATTERN (delay)), 0);
5418 epilogue_renumber (&SET_SRC (PATTERN (delay)), 0);
5420 if (SKIP_CALLERS_UNIMP_P)
5421 return "return\t%%i7+12%#";
5423 return "return\t%%i7+8%#";
5429 if (SKIP_CALLERS_UNIMP_P)
5430 return "jmp\t%%i7+12\n\trestore";
5432 return "ret\n\trestore";
5436 /* Leaf functions and non-leaf functions have different needs. */
5439 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
5442 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
5444 static int *reg_alloc_orders[] = {
5445 reg_leaf_alloc_order,
5446 reg_nonleaf_alloc_order};
5449 order_regs_for_local_alloc ()
5451 static int last_order_nonleaf = 1;
5453 if (regs_ever_live[15] != last_order_nonleaf)
5455 last_order_nonleaf = !last_order_nonleaf;
5456 memcpy ((char *) reg_alloc_order,
5457 (char *) reg_alloc_orders[last_order_nonleaf],
5458 FIRST_PSEUDO_REGISTER * sizeof (int));
5462 /* Return 1 if REG and MEM are legitimate enough to allow the various
5463 mem<-->reg splits to be run. */
5466 sparc_splitdi_legitimate (reg, mem)
5470 /* Punt if we are here by mistake. */
5471 if (! reload_completed)
5474 /* We must have an offsettable memory reference. */
5475 if (! offsettable_memref_p (mem))
5478 /* If we have legitimate args for ldd/std, we do not want
5479 the split to happen. */
5480 if ((REGNO (reg) % 2) == 0
5481 && mem_min_alignment (mem, 8))
5488 /* Return 1 if x and y are some kind of REG and they refer to
5489 different hard registers. This test is guarenteed to be
5490 run after reload. */
5493 sparc_absnegfloat_split_legitimate (x, y)
5496 if (GET_CODE (x) == SUBREG)
5497 x = alter_subreg (x);
5498 if (GET_CODE (x) != REG)
5500 if (GET_CODE (y) == SUBREG)
5501 y = alter_subreg (y);
5502 if (GET_CODE (y) != REG)
5504 if (REGNO (x) == REGNO (y))
5509 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
5510 This makes them candidates for using ldd and std insns.
5512 Note reg1 and reg2 *must* be hard registers. */
5515 registers_ok_for_ldd_peep (reg1, reg2)
5518 /* We might have been passed a SUBREG. */
5519 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
5522 if (REGNO (reg1) % 2 != 0)
5525 /* Integer ldd is deprecated in SPARC V9 */
5526 if (TARGET_V9 && REGNO (reg1) < 32)
5529 return (REGNO (reg1) == REGNO (reg2) - 1);
5532 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
5535 This can only happen when addr1 and addr2 are consecutive memory
5536 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
5537 64 bit boundary (addr1 % 8 == 0).
5539 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
5540 registers are assumed to *never* be properly aligned and are
5543 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
5544 need only check that the offset for addr1 % 8 == 0. */
5547 addrs_ok_for_ldd_peep (addr1, addr2)
5552 /* Extract a register number and offset (if used) from the first addr. */
5553 if (GET_CODE (addr1) == PLUS)
5555 /* If not a REG, return zero. */
5556 if (GET_CODE (XEXP (addr1, 0)) != REG)
5560 reg1 = REGNO (XEXP (addr1, 0));
5561 /* The offset must be constant! */
5562 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
5564 offset1 = INTVAL (XEXP (addr1, 1));
5567 else if (GET_CODE (addr1) != REG)
5571 reg1 = REGNO (addr1);
5572 /* This was a simple (mem (reg)) expression. Offset is 0. */
5576 /* Make sure the second address is a (mem (plus (reg) (const_int). */
5577 if (GET_CODE (addr2) != PLUS)
5580 if (GET_CODE (XEXP (addr2, 0)) != REG
5581 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
5584 /* Only %fp and %sp are allowed. Additionally both addresses must
5585 use the same register. */
5586 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
5589 if (reg1 != REGNO (XEXP (addr2, 0)))
5592 /* The first offset must be evenly divisible by 8 to ensure the
5593 address is 64 bit aligned. */
5594 if (offset1 % 8 != 0)
5597 /* The offset for the second addr must be 4 more than the first addr. */
5598 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
5601 /* All the tests passed. addr1 and addr2 are valid for ldd and std
5606 /* Return 1 if reg is a pseudo, or is the first register in
5607 a hard register pair. This makes it a candidate for use in
5608 ldd and std insns. */
5611 register_ok_for_ldd (reg)
5614 /* We might have been passed a SUBREG. */
5615 if (GET_CODE (reg) != REG)
5618 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
5619 return (REGNO (reg) % 2 == 0);
5624 /* Print operand X (an rtx) in assembler syntax to file FILE.
5625 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
5626 For `%' followed by punctuation, CODE is the punctuation and X is null. */
5629 print_operand (file, x, code)
5637 /* Output a 'nop' if there's nothing for the delay slot. */
5638 if (dbr_sequence_length () == 0)
5639 fputs ("\n\t nop", file);
5642 /* Output an annul flag if there's nothing for the delay slot and we
5643 are optimizing. This is always used with '(' below. */
5644 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
5645 this is a dbx bug. So, we only do this when optimizing. */
5646 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
5647 Always emit a nop in case the next instruction is a branch. */
5648 if (dbr_sequence_length () == 0
5649 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
5653 /* Output a 'nop' if there's nothing for the delay slot and we are
5654 not optimizing. This is always used with '*' above. */
5655 if (dbr_sequence_length () == 0
5656 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
5657 fputs ("\n\t nop", file);
5660 /* Output the Embedded Medium/Anywhere code model base register. */
5661 fputs (EMBMEDANY_BASE_REG, file);
5664 /* Print out what we are using as the frame pointer. This might
5665 be %fp, or might be %sp+offset. */
5666 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
5667 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
5670 /* Adjust the operand to take into account a RESTORE operation. */
5671 if (GET_CODE (x) == CONST_INT)
5673 else if (GET_CODE (x) != REG)
5674 output_operand_lossage ("Invalid %%Y operand");
5675 else if (REGNO (x) < 8)
5676 fputs (reg_names[REGNO (x)], file);
5677 else if (REGNO (x) >= 24 && REGNO (x) < 32)
5678 fputs (reg_names[REGNO (x)-16], file);
5680 output_operand_lossage ("Invalid %%Y operand");
5683 /* Print out the low order register name of a register pair. */
5684 if (WORDS_BIG_ENDIAN)
5685 fputs (reg_names[REGNO (x)+1], file);
5687 fputs (reg_names[REGNO (x)], file);
5690 /* Print out the high order register name of a register pair. */
5691 if (WORDS_BIG_ENDIAN)
5692 fputs (reg_names[REGNO (x)], file);
5694 fputs (reg_names[REGNO (x)+1], file);
5697 /* Print out the second register name of a register pair or quad.
5698 I.e., R (%o0) => %o1. */
5699 fputs (reg_names[REGNO (x)+1], file);
5702 /* Print out the third register name of a register quad.
5703 I.e., S (%o0) => %o2. */
5704 fputs (reg_names[REGNO (x)+2], file);
5707 /* Print out the fourth register name of a register quad.
5708 I.e., T (%o0) => %o3. */
5709 fputs (reg_names[REGNO (x)+3], file);
5712 /* Print a condition code register. */
5713 if (REGNO (x) == SPARC_ICC_REG)
5715 /* We don't handle CC[X]_NOOVmode because they're not supposed
5717 if (GET_MODE (x) == CCmode)
5718 fputs ("%icc", file);
5719 else if (GET_MODE (x) == CCXmode)
5720 fputs ("%xcc", file);
5725 /* %fccN register */
5726 fputs (reg_names[REGNO (x)], file);
5729 /* Print the operand's address only. */
5730 output_address (XEXP (x, 0));
5733 /* In this case we need a register. Use %g0 if the
5734 operand is const0_rtx. */
5736 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
5738 fputs ("%g0", file);
5745 switch (GET_CODE (x))
5747 case IOR: fputs ("or", file); break;
5748 case AND: fputs ("and", file); break;
5749 case XOR: fputs ("xor", file); break;
5750 default: output_operand_lossage ("Invalid %%A operand");
5755 switch (GET_CODE (x))
5757 case IOR: fputs ("orn", file); break;
5758 case AND: fputs ("andn", file); break;
5759 case XOR: fputs ("xnor", file); break;
5760 default: output_operand_lossage ("Invalid %%B operand");
5764 /* These are used by the conditional move instructions. */
5768 enum rtx_code rc = GET_CODE (x);
5772 enum machine_mode mode = GET_MODE (XEXP (x, 0));
5773 if (mode == CCFPmode || mode == CCFPEmode)
5774 rc = reverse_condition_maybe_unordered (GET_CODE (x));
5776 rc = reverse_condition (GET_CODE (x));
5780 case NE: fputs ("ne", file); break;
5781 case EQ: fputs ("e", file); break;
5782 case GE: fputs ("ge", file); break;
5783 case GT: fputs ("g", file); break;
5784 case LE: fputs ("le", file); break;
5785 case LT: fputs ("l", file); break;
5786 case GEU: fputs ("geu", file); break;
5787 case GTU: fputs ("gu", file); break;
5788 case LEU: fputs ("leu", file); break;
5789 case LTU: fputs ("lu", file); break;
5790 case LTGT: fputs ("lg", file); break;
5791 case UNORDERED: fputs ("u", file); break;
5792 case ORDERED: fputs ("o", file); break;
5793 case UNLT: fputs ("ul", file); break;
5794 case UNLE: fputs ("ule", file); break;
5795 case UNGT: fputs ("ug", file); break;
5796 case UNGE: fputs ("uge", file); break;
5797 case UNEQ: fputs ("ue", file); break;
5798 default: output_operand_lossage (code == 'c'
5799 ? "Invalid %%c operand"
5800 : "Invalid %%C operand");
5805 /* These are used by the movr instruction pattern. */
5809 enum rtx_code rc = (code == 'd'
5810 ? reverse_condition (GET_CODE (x))
5814 case NE: fputs ("ne", file); break;
5815 case EQ: fputs ("e", file); break;
5816 case GE: fputs ("gez", file); break;
5817 case LT: fputs ("lz", file); break;
5818 case LE: fputs ("lez", file); break;
5819 case GT: fputs ("gz", file); break;
5820 default: output_operand_lossage (code == 'd'
5821 ? "Invalid %%d operand"
5822 : "Invalid %%D operand");
5829 /* Print a sign-extended character. */
5830 int i = INTVAL (x) & 0xff;
5833 fprintf (file, "%d", i);
5838 /* Operand must be a MEM; write its address. */
5839 if (GET_CODE (x) != MEM)
5840 output_operand_lossage ("Invalid %%f operand");
5841 output_address (XEXP (x, 0));
5845 /* Do nothing special. */
5849 /* Undocumented flag. */
5850 output_operand_lossage ("invalid operand output code");
5853 if (GET_CODE (x) == REG)
5854 fputs (reg_names[REGNO (x)], file);
5855 else if (GET_CODE (x) == MEM)
5858 /* Poor Sun assembler doesn't understand absolute addressing. */
5859 if (CONSTANT_P (XEXP (x, 0)))
5860 fputs ("%g0+", file);
5861 output_address (XEXP (x, 0));
5864 else if (GET_CODE (x) == HIGH)
5866 fputs ("%hi(", file);
5867 output_addr_const (file, XEXP (x, 0));
5870 else if (GET_CODE (x) == LO_SUM)
5872 print_operand (file, XEXP (x, 0), 0);
5873 if (TARGET_CM_MEDMID)
5874 fputs ("+%l44(", file);
5876 fputs ("+%lo(", file);
5877 output_addr_const (file, XEXP (x, 1));
5880 else if (GET_CODE (x) == CONST_DOUBLE
5881 && (GET_MODE (x) == VOIDmode
5882 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
5884 if (CONST_DOUBLE_HIGH (x) == 0)
5885 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
5886 else if (CONST_DOUBLE_HIGH (x) == -1
5887 && CONST_DOUBLE_LOW (x) < 0)
5888 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
5890 output_operand_lossage ("long long constant not a valid immediate operand");
5892 else if (GET_CODE (x) == CONST_DOUBLE)
5893 output_operand_lossage ("floating point constant not a valid immediate operand");
5894 else { output_addr_const (file, x); }
5897 /* This function outputs assembler code for VALUE to FILE, where VALUE is
5898 a 64 bit (DImode) value. */
5900 /* ??? If there is a 64 bit counterpart to .word that the assembler
5901 understands, then using that would simply this code greatly. */
5902 /* ??? We only output .xword's for symbols and only then in environments
5903 where the assembler can handle them. */
5906 output_double_int (file, value)
5910 if (GET_CODE (value) == CONST_INT)
5912 /* ??? This has endianness issues. */
5913 #if HOST_BITS_PER_WIDE_INT == 64
5914 HOST_WIDE_INT xword = INTVAL (value);
5915 HOST_WIDE_INT high, low;
5917 high = (xword >> 32) & 0xffffffff;
5918 low = xword & 0xffffffff;
5919 ASM_OUTPUT_INT (file, GEN_INT (high));
5920 ASM_OUTPUT_INT (file, GEN_INT (low));
5922 if (INTVAL (value) < 0)
5923 ASM_OUTPUT_INT (file, constm1_rtx);
5925 ASM_OUTPUT_INT (file, const0_rtx);
5926 ASM_OUTPUT_INT (file, value);
5929 else if (GET_CODE (value) == CONST_DOUBLE)
5931 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value)));
5932 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value)));
5934 else if (GET_CODE (value) == SYMBOL_REF
5935 || GET_CODE (value) == CONST
5936 || GET_CODE (value) == PLUS
5937 || (TARGET_ARCH64 &&
5938 (GET_CODE (value) == LABEL_REF
5939 || GET_CODE (value) == CODE_LABEL
5940 || GET_CODE (value) == MINUS)))
5944 ASM_OUTPUT_INT (file, const0_rtx);
5945 ASM_OUTPUT_INT (file, value);
5949 fprintf (file, "\t%s\t", ASM_LONGLONG);
5950 output_addr_const (file, value);
5951 fprintf (file, "\n");
5958 /* Return the value of a code used in the .proc pseudo-op that says
5959 what kind of result this function returns. For non-C types, we pick
5960 the closest C type. */
5962 #ifndef CHAR_TYPE_SIZE
5963 #define CHAR_TYPE_SIZE BITS_PER_UNIT
5966 #ifndef SHORT_TYPE_SIZE
5967 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
5970 #ifndef INT_TYPE_SIZE
5971 #define INT_TYPE_SIZE BITS_PER_WORD
5974 #ifndef LONG_TYPE_SIZE
5975 #define LONG_TYPE_SIZE BITS_PER_WORD
5978 #ifndef LONG_LONG_TYPE_SIZE
5979 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
5982 #ifndef FLOAT_TYPE_SIZE
5983 #define FLOAT_TYPE_SIZE BITS_PER_WORD
5986 #ifndef DOUBLE_TYPE_SIZE
5987 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5990 #ifndef LONG_DOUBLE_TYPE_SIZE
5991 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5995 sparc_type_code (type)
5998 register unsigned long qualifiers = 0;
5999 register unsigned shift;
6001 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6002 setting more, since some assemblers will give an error for this. Also,
6003 we must be careful to avoid shifts of 32 bits or more to avoid getting
6004 unpredictable results. */
6006 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
6008 switch (TREE_CODE (type))
6014 qualifiers |= (3 << shift);
6019 qualifiers |= (2 << shift);
6023 case REFERENCE_TYPE:
6025 qualifiers |= (1 << shift);
6029 return (qualifiers | 8);
6032 case QUAL_UNION_TYPE:
6033 return (qualifiers | 9);
6036 return (qualifiers | 10);
6039 return (qualifiers | 16);
6042 /* If this is a range type, consider it to be the underlying
6044 if (TREE_TYPE (type) != 0)
6047 /* Carefully distinguish all the standard types of C,
6048 without messing up if the language is not C. We do this by
6049 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6050 look at both the names and the above fields, but that's redundant.
6051 Any type whose size is between two C types will be considered
6052 to be the wider of the two types. Also, we do not have a
6053 special code to use for "long long", so anything wider than
6054 long is treated the same. Note that we can't distinguish
6055 between "int" and "long" in this code if they are the same
6056 size, but that's fine, since neither can the assembler. */
6058 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
6059 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
6061 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
6062 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
6064 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
6065 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
6068 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
6071 /* If this is a range type, consider it to be the underlying
6073 if (TREE_TYPE (type) != 0)
6076 /* Carefully distinguish all the standard types of C,
6077 without messing up if the language is not C. */
6079 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
6080 return (qualifiers | 6);
6083 return (qualifiers | 7);
6085 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
6086 /* ??? We need to distinguish between double and float complex types,
6087 but I don't know how yet because I can't reach this code from
6088 existing front-ends. */
6089 return (qualifiers | 7); /* Who knows? */
6091 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
6092 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
6093 case FILE_TYPE: /* GNU Pascal FILE type. */
6094 case SET_TYPE: /* GNU Pascal SET type. */
6095 case LANG_TYPE: /* ? */
6099 abort (); /* Not a type! */
6106 /* Nested function support. */
6108 /* Emit RTL insns to initialize the variable parts of a trampoline.
6109 FNADDR is an RTX for the address of the function's pure code.
6110 CXT is an RTX for the static chain value for the function.
6112 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6113 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6114 (to store insns). This is a bit excessive. Perhaps a different
6115 mechanism would be better here.
6117 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6120 sparc_initialize_trampoline (tramp, fnaddr, cxt)
6121 rtx tramp, fnaddr, cxt;
6123 /* SPARC 32 bit trampoline:
6126 sethi %hi(static), %g2
6128 or %g2, %lo(static), %g2
6130 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6131 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6133 #ifdef TRANSFER_FROM_TRAMPOLINE
6134 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6135 0, VOIDmode, 1, tramp, Pmode);
6138 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
6139 expand_binop (SImode, ior_optab,
6140 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
6141 size_int (10), 0, 1),
6142 GEN_INT (0x03000000),
6143 NULL_RTX, 1, OPTAB_DIRECT));
6145 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6146 expand_binop (SImode, ior_optab,
6147 expand_shift (RSHIFT_EXPR, SImode, cxt,
6148 size_int (10), 0, 1),
6149 GEN_INT (0x05000000),
6150 NULL_RTX, 1, OPTAB_DIRECT));
6152 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6153 expand_binop (SImode, ior_optab,
6154 expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX),
6155 GEN_INT (0x81c06000),
6156 NULL_RTX, 1, OPTAB_DIRECT));
6158 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6159 expand_binop (SImode, ior_optab,
6160 expand_and (cxt, GEN_INT (0x3ff), NULL_RTX),
6161 GEN_INT (0x8410a000),
6162 NULL_RTX, 1, OPTAB_DIRECT));
6164 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
6165 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6166 aligned on a 16 byte boundary so one flush clears it all. */
6167 if (sparc_cpu != PROCESSOR_ULTRASPARC)
6168 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
6169 plus_constant (tramp, 8)))));
6172 /* The 64 bit version is simpler because it makes more sense to load the
6173 values as "immediate" data out of the trampoline. It's also easier since
6174 we can read the PC without clobbering a register. */
6177 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
6178 rtx tramp, fnaddr, cxt;
6180 #ifdef TRANSFER_FROM_TRAMPOLINE
6181 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6182 0, VOIDmode, 1, tramp, Pmode);
6193 emit_move_insn (gen_rtx_MEM (SImode, tramp),
6194 GEN_INT (0x83414000));
6195 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6196 GEN_INT (0xca586018));
6197 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6198 GEN_INT (0x81c14000));
6199 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6200 GEN_INT (0xca586010));
6201 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
6202 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
6203 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
6205 if (sparc_cpu != PROCESSOR_ULTRASPARC)
6206 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
6209 /* Subroutines to support a flat (single) register window calling
6212 /* Single-register window sparc stack frames look like:
6214 Before call After call
6215 +-----------------------+ +-----------------------+
6217 mem | caller's temps. | | caller's temps. |
6219 +-----------------------+ +-----------------------+
6221 | arguments on stack. | | arguments on stack. |
6223 +-----------------------+FP+92->+-----------------------+
6224 | 6 words to save | | 6 words to save |
6225 | arguments passed | | arguments passed |
6226 | in registers, even | | in registers, even |
6227 | if not passed. | | if not passed. |
6228 SP+68->+-----------------------+FP+68->+-----------------------+
6229 | 1 word struct addr | | 1 word struct addr |
6230 +-----------------------+FP+64->+-----------------------+
6232 | 16 word reg save area | | 16 word reg save area |
6234 SP->+-----------------------+ FP->+-----------------------+
6236 | fp/alu reg moves |
6237 FP-16->+-----------------------+
6241 +-----------------------+
6243 | fp register save |
6245 +-----------------------+
6247 | gp register save |
6249 +-----------------------+
6251 | alloca allocations |
6253 +-----------------------+
6255 | arguments on stack |
6257 SP+92->+-----------------------+
6259 | arguments passed |
6260 | in registers, even |
6261 low | if not passed. |
6262 memory SP+68->+-----------------------+
6263 | 1 word struct addr |
6264 SP+64->+-----------------------+
6266 I 16 word reg save area |
6268 SP->+-----------------------+ */
6270 /* Structure to be filled in by sparc_flat_compute_frame_size with register
6271 save masks, and offsets for the current function. */
6273 struct sparc_frame_info
6275 unsigned long total_size; /* # bytes that the entire frame takes up. */
6276 unsigned long var_size; /* # bytes that variables take up. */
6277 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6278 unsigned long extra_size; /* # bytes of extra gunk. */
6279 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6280 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6281 unsigned long gmask; /* Mask of saved gp registers. */
6282 unsigned long fmask; /* Mask of saved fp registers. */
6283 unsigned long reg_offset; /* Offset from new sp to store regs. */
6284 int initialized; /* Nonzero if frame size already calculated. */
6287 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6288 struct sparc_frame_info current_frame_info;
6290 /* Zero structure to initialize current_frame_info. */
6291 struct sparc_frame_info zero_frame_info;
6293 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6295 #define RETURN_ADDR_REGNUM 15
6296 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
6297 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6299 #define MUST_SAVE_REGISTER(regno) \
6300 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6301 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
6302 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6304 /* Return the bytes needed to compute the frame pointer from the current
6308 sparc_flat_compute_frame_size (size)
6309 int size; /* # of var. bytes allocated. */
6312 unsigned long total_size; /* # bytes that the entire frame takes up. */
6313 unsigned long var_size; /* # bytes that variables take up. */
6314 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6315 unsigned long extra_size; /* # extra bytes. */
6316 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6317 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6318 unsigned long gmask; /* Mask of saved gp registers. */
6319 unsigned long fmask; /* Mask of saved fp registers. */
6320 unsigned long reg_offset; /* Offset to register save area. */
6321 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
6323 /* This is the size of the 16 word reg save area, 1 word struct addr
6324 area, and 4 word fp/alu register copy area. */
6325 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
6335 if (!leaf_function_p ())
6337 /* Also include the size needed for the 6 parameter registers. */
6338 args_size = current_function_outgoing_args_size + 24;
6340 total_size = var_size + args_size;
6342 /* Calculate space needed for gp registers. */
6343 for (regno = 1; regno <= 31; regno++)
6345 if (MUST_SAVE_REGISTER (regno))
6347 /* If we need to save two regs in a row, ensure there's room to bump
6348 up the address to align it to a doubleword boundary. */
6349 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
6351 if (gp_reg_size % 8 != 0)
6353 gp_reg_size += 2 * UNITS_PER_WORD;
6354 gmask |= 3 << regno;
6360 gp_reg_size += UNITS_PER_WORD;
6361 gmask |= 1 << regno;
6366 /* Calculate space needed for fp registers. */
6367 for (regno = 32; regno <= 63; regno++)
6369 if (regs_ever_live[regno] && !call_used_regs[regno])
6371 fp_reg_size += UNITS_PER_WORD;
6372 fmask |= 1 << (regno - 32);
6379 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
6380 /* Ensure save area is 8 byte aligned if we need it. */
6382 if (need_aligned_p && n != 0)
6384 total_size += 8 - n;
6385 reg_offset += 8 - n;
6387 total_size += gp_reg_size + fp_reg_size;
6390 /* If we must allocate a stack frame at all, we must also allocate
6391 room for register window spillage, so as to be binary compatible
6392 with libraries and operating systems that do not use -mflat. */
6394 total_size += extra_size;
6398 total_size = SPARC_STACK_ALIGN (total_size);
6400 /* Save other computed information. */
6401 current_frame_info.total_size = total_size;
6402 current_frame_info.var_size = var_size;
6403 current_frame_info.args_size = args_size;
6404 current_frame_info.extra_size = extra_size;
6405 current_frame_info.gp_reg_size = gp_reg_size;
6406 current_frame_info.fp_reg_size = fp_reg_size;
6407 current_frame_info.gmask = gmask;
6408 current_frame_info.fmask = fmask;
6409 current_frame_info.reg_offset = reg_offset;
6410 current_frame_info.initialized = reload_completed;
6412 /* Ok, we're done. */
6416 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
6419 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
6420 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
6421 [BASE_REG+OFFSET] will always be a valid address.
6423 WORD_OP is either "st" for save, "ld" for restore.
6424 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
6427 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
6428 doubleword_op, base_offset)
6430 const char *base_reg;
6431 unsigned int offset;
6432 unsigned long gmask;
6433 unsigned long fmask;
6434 const char *word_op;
6435 const char *doubleword_op;
6436 unsigned long base_offset;
6440 if (gmask == 0 && fmask == 0)
6443 /* Save registers starting from high to low. We've already saved the
6444 previous frame pointer and previous return address for the debugger's
6445 sake. The debugger allows us to not need a nop in the epilog if at least
6446 one register is reloaded in addition to return address. */
6450 for (regno = 1; regno <= 31; regno++)
6452 if ((gmask & (1L << regno)) != 0)
6454 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
6456 /* We can save two registers in a row. If we're not at a
6457 double word boundary, move to one.
6458 sparc_flat_compute_frame_size ensures there's room to do
6460 if (offset % 8 != 0)
6461 offset += UNITS_PER_WORD;
6463 if (word_op[0] == 's')
6465 fprintf (file, "\t%s\t%s, [%s+%d]\n",
6466 doubleword_op, reg_names[regno],
6468 if (dwarf2out_do_frame ())
6470 char *l = dwarf2out_cfi_label ();
6471 dwarf2out_reg_save (l, regno, offset + base_offset);
6473 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
6477 fprintf (file, "\t%s\t[%s+%d], %s\n",
6478 doubleword_op, base_reg, offset,
6481 offset += 2 * UNITS_PER_WORD;
6486 if (word_op[0] == 's')
6488 fprintf (file, "\t%s\t%s, [%s+%d]\n",
6489 word_op, reg_names[regno],
6491 if (dwarf2out_do_frame ())
6492 dwarf2out_reg_save ("", regno, offset + base_offset);
6495 fprintf (file, "\t%s\t[%s+%d], %s\n",
6496 word_op, base_reg, offset, reg_names[regno]);
6498 offset += UNITS_PER_WORD;
6506 for (regno = 32; regno <= 63; regno++)
6508 if ((fmask & (1L << (regno - 32))) != 0)
6510 if (word_op[0] == 's')
6512 fprintf (file, "\t%s\t%s, [%s+%d]\n",
6513 word_op, reg_names[regno],
6515 if (dwarf2out_do_frame ())
6516 dwarf2out_reg_save ("", regno, offset + base_offset);
6519 fprintf (file, "\t%s\t[%s+%d], %s\n",
6520 word_op, base_reg, offset, reg_names[regno]);
6522 offset += UNITS_PER_WORD;
6528 /* Set up the stack and frame (if desired) for the function. */
6531 sparc_flat_output_function_prologue (file, size)
6535 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
6536 unsigned long gmask = current_frame_info.gmask;
6538 sparc_output_scratch_registers (file);
6540 /* This is only for the human reader. */
6541 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
6542 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6544 current_frame_info.var_size,
6545 current_frame_info.gp_reg_size / 4,
6546 current_frame_info.fp_reg_size / 4,
6547 current_function_outgoing_args_size,
6548 current_frame_info.extra_size);
6550 size = SPARC_STACK_ALIGN (size);
6551 size = (! current_frame_info.initialized
6552 ? sparc_flat_compute_frame_size (size)
6553 : current_frame_info.total_size);
6555 /* These cases shouldn't happen. Catch them now. */
6556 if (size == 0 && (gmask || current_frame_info.fmask))
6559 /* Allocate our stack frame by decrementing %sp.
6560 At present, the only algorithm gdb can use to determine if this is a
6561 flat frame is if we always set %i7 if we set %sp. This can be optimized
6562 in the future by putting in some sort of debugging information that says
6563 this is a `flat' function. However, there is still the case of debugging
6564 code without such debugging information (including cases where most fns
6565 have such info, but there is one that doesn't). So, always do this now
6566 so we don't get a lot of code out there that gdb can't handle.
6567 If the frame pointer isn't needn't then that's ok - gdb won't be able to
6568 distinguish us from a non-flat function but there won't (and shouldn't)
6569 be any differences anyway. The return pc is saved (if necessary) right
6570 after %i7 so gdb won't have to look too far to find it. */
6573 unsigned int reg_offset = current_frame_info.reg_offset;
6574 const char *fp_str = reg_names[FRAME_POINTER_REGNUM];
6575 const char *t1_str = "%g1";
6577 /* Things get a little tricky if local variables take up more than ~4096
6578 bytes and outgoing arguments take up more than ~4096 bytes. When that
6579 happens, the register save area can't be accessed from either end of
6580 the frame. Handle this by decrementing %sp to the start of the gp
6581 register save area, save the regs, update %i7, and then set %sp to its
6582 final value. Given that we only have one scratch register to play
6583 with it is the cheapest solution, and it helps gdb out as it won't
6584 slow down recognition of flat functions.
6585 Don't change the order of insns emitted here without checking with
6586 the gdb folk first. */
6588 /* Is the entire register save area offsettable from %sp? */
6589 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
6593 fprintf (file, "\tadd\t%s, %d, %s\n",
6594 sp_str, -size, sp_str);
6595 if (gmask & FRAME_POINTER_MASK)
6597 fprintf (file, "\tst\t%s, [%s+%d]\n",
6598 fp_str, sp_str, reg_offset);
6599 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
6600 sp_str, -size, fp_str, ASM_COMMENT_START);
6606 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6607 size, t1_str, sp_str, t1_str, sp_str);
6608 if (gmask & FRAME_POINTER_MASK)
6610 fprintf (file, "\tst\t%s, [%s+%d]\n",
6611 fp_str, sp_str, reg_offset);
6612 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
6613 sp_str, t1_str, fp_str, ASM_COMMENT_START);
6617 if (dwarf2out_do_frame ())
6619 char *l = dwarf2out_cfi_label ();
6620 if (gmask & FRAME_POINTER_MASK)
6622 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
6623 reg_offset - 4 - size);
6624 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
6627 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
6629 if (gmask & RETURN_ADDR_MASK)
6631 fprintf (file, "\tst\t%s, [%s+%d]\n",
6632 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
6633 if (dwarf2out_do_frame ())
6634 dwarf2out_return_save ("", reg_offset - size);
6637 sparc_flat_save_restore (file, sp_str, reg_offset,
6638 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6639 current_frame_info.fmask,
6640 "st", "std", -size);
6644 /* Subtract %sp in two steps, but make sure there is always a
6645 64 byte register save area, and %sp is properly aligned. */
6646 /* Amount to decrement %sp by, the first time. */
6647 unsigned int size1 = ((size - reg_offset + 64) + 15) & -16;
6648 /* Offset to register save area from %sp. */
6649 unsigned int offset = size1 - (size - reg_offset);
6653 fprintf (file, "\tadd\t%s, %d, %s\n",
6654 sp_str, -size1, sp_str);
6655 if (gmask & FRAME_POINTER_MASK)
6657 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
6658 fp_str, sp_str, offset, sp_str, -size1, fp_str,
6665 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6666 size1, t1_str, sp_str, t1_str, sp_str);
6667 if (gmask & FRAME_POINTER_MASK)
6669 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
6670 fp_str, sp_str, offset, sp_str, t1_str, fp_str,
6675 if (dwarf2out_do_frame ())
6677 char *l = dwarf2out_cfi_label ();
6678 if (gmask & FRAME_POINTER_MASK)
6680 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
6681 offset - 4 - size1);
6682 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
6685 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
6687 if (gmask & RETURN_ADDR_MASK)
6689 fprintf (file, "\tst\t%s, [%s+%d]\n",
6690 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
6691 if (dwarf2out_do_frame ())
6692 /* offset - size1 == reg_offset - size
6693 if reg_offset were updated above like offset. */
6694 dwarf2out_return_save ("", offset - size1);
6697 sparc_flat_save_restore (file, sp_str, offset,
6698 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6699 current_frame_info.fmask,
6700 "st", "std", -size1);
6701 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6702 size - size1, t1_str, sp_str, t1_str, sp_str);
6703 if (dwarf2out_do_frame ())
6704 if (! (gmask & FRAME_POINTER_MASK))
6705 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
6709 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
6712 /* Do any necessary cleanup after a function to restore stack, frame,
6716 sparc_flat_output_function_epilogue (file, size)
6720 rtx epilogue_delay = current_function_epilogue_delay_list;
6721 int noepilogue = FALSE;
6723 /* This is only for the human reader. */
6724 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
6726 /* The epilogue does not depend on any registers, but the stack
6727 registers, so we assume that if we have 1 pending nop, it can be
6728 ignored, and 2 it must be filled (2 nops occur for integer
6729 multiply and divide). */
6731 size = SPARC_STACK_ALIGN (size);
6732 size = (!current_frame_info.initialized
6733 ? sparc_flat_compute_frame_size (size)
6734 : current_frame_info.total_size);
6736 if (size == 0 && epilogue_delay == 0)
6738 rtx insn = get_last_insn ();
6740 /* If the last insn was a BARRIER, we don't have to write any code
6741 because a jump (aka return) was put there. */
6742 if (GET_CODE (insn) == NOTE)
6743 insn = prev_nonnote_insn (insn);
6744 if (insn && GET_CODE (insn) == BARRIER)
6750 unsigned int reg_offset = current_frame_info.reg_offset;
6752 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
6753 const char *fp_str = reg_names[FRAME_POINTER_REGNUM];
6754 const char *t1_str = "%g1";
6756 /* In the reload sequence, we don't need to fill the load delay
6757 slots for most of the loads, also see if we can fill the final
6758 delay slot if not otherwise filled by the reload sequence. */
6761 fprintf (file, "\tset\t%d, %s\n", size, t1_str);
6763 if (frame_pointer_needed)
6766 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
6767 fp_str, t1_str, sp_str, ASM_COMMENT_START);
6769 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
6770 fp_str, size, sp_str, ASM_COMMENT_START);
6773 /* Is the entire register save area offsettable from %sp? */
6774 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
6780 /* Restore %sp in two steps, but make sure there is always a
6781 64 byte register save area, and %sp is properly aligned. */
6782 /* Amount to increment %sp by, the first time. */
6783 size1 = ((reg_offset - 64 - 16) + 15) & -16;
6784 /* Offset to register save area from %sp. */
6785 reg_offset = size1 - reg_offset;
6787 fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n",
6788 size1, t1_str, sp_str, t1_str, sp_str);
6791 /* We must restore the frame pointer and return address reg first
6792 because they are treated specially by the prologue output code. */
6793 if (current_frame_info.gmask & FRAME_POINTER_MASK)
6795 fprintf (file, "\tld\t[%s+%d], %s\n",
6796 sp_str, reg_offset, fp_str);
6799 if (current_frame_info.gmask & RETURN_ADDR_MASK)
6801 fprintf (file, "\tld\t[%s+%d], %s\n",
6802 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
6806 /* Restore any remaining saved registers. */
6807 sparc_flat_save_restore (file, sp_str, reg_offset,
6808 current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6809 current_frame_info.fmask,
6812 /* If we had to increment %sp in two steps, record it so the second
6813 restoration in the epilogue finishes up. */
6818 fprintf (file, "\tset\t%d, %s\n",
6822 if (current_function_returns_struct)
6823 fprintf (file, "\tjmp\t%%o7+12\n");
6825 fprintf (file, "\tretl\n");
6827 /* If the only register saved is the return address, we need a
6828 nop, unless we have an instruction to put into it. Otherwise
6829 we don't since reloading multiple registers doesn't reference
6830 the register being loaded. */
6836 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
6839 else if (size > 4095)
6840 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
6843 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str);
6846 fprintf (file, "\tnop\n");
6849 /* Reset state info for each function. */
6850 current_frame_info = zero_frame_info;
6852 sparc_output_deferred_case_vectors ();
6855 /* Define the number of delay slots needed for the function epilogue.
6857 On the sparc, we need a slot if either no stack has been allocated,
6858 or the only register saved is the return register. */
6861 sparc_flat_epilogue_delay_slots ()
6863 if (!current_frame_info.initialized)
6864 (void) sparc_flat_compute_frame_size (get_frame_size ());
6866 if (current_frame_info.total_size == 0)
6872 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
6873 Any single length instruction which doesn't reference the stack or frame
6877 sparc_flat_eligible_for_epilogue_delay (trial, slot)
6879 int slot ATTRIBUTE_UNUSED;
6881 rtx pat = PATTERN (trial);
6883 if (get_attr_length (trial) != 1)
6886 if (! reg_mentioned_p (stack_pointer_rtx, pat)
6887 && ! reg_mentioned_p (frame_pointer_rtx, pat))
6893 /* Adjust the cost of a scheduling dependency. Return the new cost of
6894 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6897 supersparc_adjust_cost (insn, link, dep_insn, cost)
6903 enum attr_type insn_type;
6905 if (! recog_memoized (insn))
6908 insn_type = get_attr_type (insn);
6910 if (REG_NOTE_KIND (link) == 0)
6912 /* Data dependency; DEP_INSN writes a register that INSN reads some
6915 /* if a load, then the dependence must be on the memory address;
6916 add an extra "cycle". Note that the cost could be two cycles
6917 if the reg was written late in an instruction group; we ca not tell
6919 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
6922 /* Get the delay only if the address of the store is the dependence. */
6923 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
6925 rtx pat = PATTERN(insn);
6926 rtx dep_pat = PATTERN (dep_insn);
6928 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6929 return cost; /* This should not happen! */
6931 /* The dependency between the two instructions was on the data that
6932 is being stored. Assume that this implies that the address of the
6933 store is not dependent. */
6934 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6937 return cost + 3; /* An approximation. */
6940 /* A shift instruction cannot receive its data from an instruction
6941 in the same cycle; add a one cycle penalty. */
6942 if (insn_type == TYPE_SHIFT)
6943 return cost + 3; /* Split before cascade into shift. */
6947 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
6948 INSN writes some cycles later. */
6950 /* These are only significant for the fpu unit; writing a fp reg before
6951 the fpu has finished with it stalls the processor. */
6953 /* Reusing an integer register causes no problems. */
6954 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
6962 hypersparc_adjust_cost (insn, link, dep_insn, cost)
6968 enum attr_type insn_type, dep_type;
6969 rtx pat = PATTERN(insn);
6970 rtx dep_pat = PATTERN (dep_insn);
6972 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
6975 insn_type = get_attr_type (insn);
6976 dep_type = get_attr_type (dep_insn);
6978 switch (REG_NOTE_KIND (link))
6981 /* Data dependency; DEP_INSN writes a register that INSN reads some
6988 /* Get the delay iff the address of the store is the dependence. */
6989 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6992 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6999 /* If a load, then the dependence must be on the memory address. If
7000 the addresses aren't equal, then it might be a false dependency */
7001 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7003 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7004 || GET_CODE (SET_DEST (dep_pat)) != MEM
7005 || GET_CODE (SET_SRC (pat)) != MEM
7006 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7007 XEXP (SET_SRC (pat), 0)))
7015 /* Compare to branch latency is 0. There is no benefit from
7016 separating compare and branch. */
7017 if (dep_type == TYPE_COMPARE)
7019 /* Floating point compare to branch latency is less than
7020 compare to conditional move. */
7021 if (dep_type == TYPE_FPCMP)
7030 /* Anti-dependencies only penalize the fpu unit. */
7031 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7043 ultrasparc_adjust_cost (insn, link, dep_insn, cost)
7049 enum attr_type insn_type, dep_type;
7050 rtx pat = PATTERN(insn);
7051 rtx dep_pat = PATTERN (dep_insn);
7053 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7056 insn_type = get_attr_type (insn);
7057 dep_type = get_attr_type (dep_insn);
7059 /* Nothing issues in parallel with integer multiplies, so
7060 mark as zero cost since the scheduler can not do anything
7062 if (insn_type == TYPE_IMUL)
7065 #define SLOW_FP(dep_type) \
7066 (dep_type == TYPE_FPSQRTS || dep_type == TYPE_FPSQRTD || \
7067 dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
7069 switch (REG_NOTE_KIND (link))
7072 /* Data dependency; DEP_INSN writes a register that INSN reads some
7075 if (dep_type == TYPE_CMOVE)
7077 /* Instructions that read the result of conditional moves cannot
7078 be in the same group or the following group. */
7084 /* UltraSPARC can dual issue a store and an instruction setting
7085 the value stored, except for divide and square root. */
7087 if (! SLOW_FP (dep_type))
7092 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7095 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7096 /* The dependency between the two instructions is on the data
7097 that is being stored. Assume that the address of the store
7098 is not also dependent. */
7105 /* A load does not return data until at least 11 cycles after
7106 a store to the same location. 3 cycles are accounted for
7107 in the load latency; add the other 8 here. */
7108 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7110 /* If the addresses are not equal this may be a false
7111 dependency because pointer aliasing could not be
7112 determined. Add only 2 cycles in that case. 2 is
7113 an arbitrary compromise between 8, which would cause
7114 the scheduler to generate worse code elsewhere to
7115 compensate for a dependency which might not really
7117 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7118 || GET_CODE (SET_SRC (pat)) != MEM
7119 || GET_CODE (SET_DEST (dep_pat)) != MEM
7120 || ! rtx_equal_p (XEXP (SET_SRC (pat), 0),
7121 XEXP (SET_DEST (dep_pat), 0)))
7129 /* Compare to branch latency is 0. There is no benefit from
7130 separating compare and branch. */
7131 if (dep_type == TYPE_COMPARE)
7133 /* Floating point compare to branch latency is less than
7134 compare to conditional move. */
7135 if (dep_type == TYPE_FPCMP)
7140 /* FMOVR class instructions can not issue in the same cycle
7141 or the cycle after an instruction which writes any
7142 integer register. Model this as cost 2 for dependent
7144 if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY
7145 || dep_type == TYPE_BINARY)
7148 /* Otherwise check as for integer conditional moves. */
7151 /* Conditional moves involving integer registers wait until
7152 3 cycles after loads return data. The interlock applies
7153 to all loads, not just dependent loads, but that is hard
7155 if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD)
7165 /* Divide and square root lock destination registers for full latency. */
7166 if (! SLOW_FP (dep_type))
7170 case REG_DEP_OUTPUT:
7171 /* IEU and FPU instruction that have the same destination
7172 register cannot be grouped together. */
7179 /* Other costs not accounted for:
7180 - Single precision floating point loads lock the other half of
7181 the even/odd register pair.
7182 - Several hazards associated with ldd/std are ignored because these
7183 instructions are rarely generated for V9.
7184 - The floating point pipeline can not have both a single and double
7185 precision operation active at the same time. Format conversions
7186 and graphics instructions are given honorary double precision status.
7187 - call and jmpl are always the first instruction in a group. */
7195 sparc_adjust_cost(insn, link, dep, cost)
7203 case PROCESSOR_SUPERSPARC:
7204 cost = supersparc_adjust_cost (insn, link, dep, cost);
7206 case PROCESSOR_HYPERSPARC:
7207 case PROCESSOR_SPARCLITE86X:
7208 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7210 case PROCESSOR_ULTRASPARC:
7211 cost = ultrasparc_adjust_cost (insn, link, dep, cost);
7219 /* This describes the state of the UltraSPARC pipeline during
7220 instruction scheduling. */
7222 #define TMASK(__x) ((unsigned)1 << ((int)(__x)))
7223 #define UMASK(__x) ((unsigned)1 << ((int)(__x)))
7225 enum ultra_code { NONE=0, /* no insn at all */
7226 IEU0, /* shifts and conditional moves */
7227 IEU1, /* condition code setting insns, calls+jumps */
7228 IEUN, /* all other single cycle ieu insns */
7229 LSU, /* loads and stores */
7231 FPM, /* FPU pipeline 1, multiplies and divides */
7232 FPA, /* FPU pipeline 2, all other operations */
7233 SINGLE, /* single issue instructions */
7236 static enum ultra_code ultra_code_from_mask PARAMS ((int));
7237 static void ultra_schedule_insn PARAMS ((rtx *, rtx *, int, enum ultra_code));
7239 static const char *ultra_code_names[NUM_ULTRA_CODES] = {
7240 "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI",
7241 "FPM", "FPA", "SINGLE" };
7243 struct ultrasparc_pipeline_state {
7244 /* The insns in this group. */
7247 /* The code for each insn. */
7248 enum ultra_code codes[4];
7250 /* Which insns in this group have been committed by the
7251 scheduler. This is how we determine how many more
7252 can issue this cycle. */
7255 /* How many insns in this group. */
7258 /* Mask of free slots still in this group. */
7259 char free_slot_mask;
7261 /* The slotter uses the following to determine what other
7262 insn types can still make their way into this group. */
7263 char contents [NUM_ULTRA_CODES];
7267 #define ULTRA_NUM_HIST 8
7268 static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST];
7269 static int ultra_cur_hist;
7270 static int ultra_cycles_elapsed;
7272 #define ultra_pipe (ultra_pipe_hist[ultra_cur_hist])
7274 /* Given TYPE_MASK compute the ultra_code it has. */
7275 static enum ultra_code
7276 ultra_code_from_mask (type_mask)
7279 if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE)))
7281 else if (type_mask & (TMASK (TYPE_COMPARE) |
7283 TMASK (TYPE_SIBCALL) |
7284 TMASK (TYPE_UNCOND_BRANCH)))
7286 else if (type_mask & (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
7287 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY)))
7289 else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
7290 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
7291 TMASK (TYPE_FPSTORE)))
7293 else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) |
7294 TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRTS) |
7295 TMASK (TYPE_FPSQRTD)))
7297 else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
7298 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)))
7300 else if (type_mask & TMASK (TYPE_BRANCH))
7306 /* Check INSN (a conditional move) and make sure that it's
7307 results are available at this cycle. Return 1 if the
7308 results are in fact ready. */
7310 ultra_cmove_results_ready_p (insn)
7313 struct ultrasparc_pipeline_state *up;
7316 /* If this got dispatched in the previous
7317 group, the results are not ready. */
7318 entry = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1);
7319 up = &ultra_pipe_hist[entry];
7322 if (up->group[slot] == insn)
7328 /* Walk backwards in pipeline history looking for FPU
7329 operations which use a mode different than FPMODE and
7330 will create a stall if an insn using FPMODE were to be
7331 dispatched this cycle. */
7333 ultra_fpmode_conflict_exists (fpmode)
7334 enum machine_mode fpmode;
7339 hist_ent = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1);
7340 if (ultra_cycles_elapsed < 4)
7341 hist_lim = ultra_cycles_elapsed;
7344 while (hist_lim > 0)
7346 struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent];
7351 rtx insn = up->group[slot];
7352 enum machine_mode this_mode;
7356 || GET_CODE (insn) != INSN
7357 || (pat = PATTERN (insn)) == 0
7358 || GET_CODE (pat) != SET)
7361 this_mode = GET_MODE (SET_DEST (pat));
7362 if ((this_mode != SFmode
7363 && this_mode != DFmode)
7364 || this_mode == fpmode)
7367 /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then
7368 we will get a stall. Loads and stores are independant
7370 if (GET_CODE (SET_SRC (pat)) != ABS
7371 && GET_CODE (SET_SRC (pat)) != NEG
7372 && ((TMASK (get_attr_type (insn)) &
7373 (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) |
7374 TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRTS) |
7375 TMASK (TYPE_FPSQRTD) |
7376 TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0))
7380 hist_ent = (hist_ent - 1) & (ULTRA_NUM_HIST - 1);
7383 /* No conflicts, safe to dispatch. */
7387 /* Find an instruction in LIST which has one of the
7388 type attributes enumerated in TYPE_MASK. START
7389 says where to begin the search.
7391 NOTE: This scheme depends upon the fact that we
7392 have less than 32 distinct type attributes. */
7394 static int ultra_types_avail;
7397 ultra_find_type (type_mask, list, start)
7404 /* Short circuit if no such insn exists in the ready
7406 if ((type_mask & ultra_types_avail) == 0)
7409 for (i = start; i >= 0; i--)
7413 if (recog_memoized (insn) >= 0
7414 && (TMASK(get_attr_type (insn)) & type_mask))
7416 enum machine_mode fpmode = SFmode;
7419 int check_depend = 0;
7420 int check_fpmode_conflict = 0;
7422 if (GET_CODE (insn) == INSN
7423 && (pat = PATTERN(insn)) != 0
7424 && GET_CODE (pat) == SET
7425 && !(type_mask & (TMASK (TYPE_STORE) |
7426 TMASK (TYPE_FPSTORE))))
7429 if (GET_MODE (SET_DEST (pat)) == SFmode
7430 || GET_MODE (SET_DEST (pat)) == DFmode)
7432 fpmode = GET_MODE (SET_DEST (pat));
7433 check_fpmode_conflict = 1;
7440 rtx slot_insn = ultra_pipe.group[slot];
7443 /* Already issued, bad dependency, or FPU
7446 && (slot_pat = PATTERN (slot_insn)) != 0
7447 && ((insn == slot_insn)
7448 || (check_depend == 1
7449 && GET_CODE (slot_insn) == INSN
7450 && GET_CODE (slot_pat) == SET
7451 && ((GET_CODE (SET_DEST (slot_pat)) == REG
7452 && GET_CODE (SET_SRC (pat)) == REG
7453 && REGNO (SET_DEST (slot_pat)) ==
7454 REGNO (SET_SRC (pat)))
7455 || (GET_CODE (SET_DEST (slot_pat)) == SUBREG
7456 && GET_CODE (SET_SRC (pat)) == SUBREG
7457 && REGNO (SUBREG_REG (SET_DEST (slot_pat))) ==
7458 REGNO (SUBREG_REG (SET_SRC (pat)))
7459 && SUBREG_WORD (SET_DEST (slot_pat)) ==
7460 SUBREG_WORD (SET_SRC (pat)))))
7461 || (check_fpmode_conflict == 1
7462 && GET_CODE (slot_insn) == INSN
7463 && GET_CODE (slot_pat) == SET
7464 && (GET_MODE (SET_DEST (slot_pat)) == SFmode
7465 || GET_MODE (SET_DEST (slot_pat)) == DFmode)
7466 && GET_MODE (SET_DEST (slot_pat)) != fpmode)))
7470 /* Check for peculiar result availability and dispatch
7471 interference situations. */
7473 && ultra_cycles_elapsed > 0)
7477 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
7479 rtx link_insn = XEXP (link, 0);
7480 if (GET_CODE (link_insn) == INSN
7481 && recog_memoized (link_insn) >= 0
7482 && (TMASK (get_attr_type (link_insn)) &
7483 (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE)))
7484 && ! ultra_cmove_results_ready_p (link_insn))
7488 if (check_fpmode_conflict
7489 && ultra_fpmode_conflict_exists (fpmode))
7502 ultra_build_types_avail (ready, n_ready)
7506 int i = n_ready - 1;
7508 ultra_types_avail = 0;
7511 rtx insn = ready[i];
7513 if (recog_memoized (insn) >= 0)
7514 ultra_types_avail |= TMASK (get_attr_type (insn));
7520 /* Place insn pointed to my IP into the pipeline.
7521 Make element THIS of READY be that insn if it
7522 is not already. TYPE indicates the pipeline class
7523 this insn falls into. */
7525 ultra_schedule_insn (ip, ready, this, type)
7529 enum ultra_code type;
7532 char mask = ultra_pipe.free_slot_mask;
7535 /* Obtain free slot. */
7536 for (pipe_slot = 0; pipe_slot < 4; pipe_slot++)
7537 if ((mask & (1 << pipe_slot)) != 0)
7542 /* In it goes, and it hasn't been committed yet. */
7543 ultra_pipe.group[pipe_slot] = *ip;
7544 ultra_pipe.codes[pipe_slot] = type;
7545 ultra_pipe.contents[type] = 1;
7547 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
7548 ultra_pipe.num_ieu_insns += 1;
7550 ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot));
7551 ultra_pipe.group_size += 1;
7552 ultra_pipe.commit[pipe_slot] = 0;
7554 /* Update ready list. */
7556 while (ip != &ready[this])
7564 /* Advance to the next pipeline group. */
7566 ultra_flush_pipeline ()
7568 ultra_cur_hist = (ultra_cur_hist + 1) & (ULTRA_NUM_HIST - 1);
7569 ultra_cycles_elapsed += 1;
7570 memset ((char *) &ultra_pipe, 0, sizeof ultra_pipe);
7571 ultra_pipe.free_slot_mask = 0xf;
7574 /* Init our data structures for this current block. */
7576 ultrasparc_sched_init (dump, sched_verbose)
7577 FILE *dump ATTRIBUTE_UNUSED;
7578 int sched_verbose ATTRIBUTE_UNUSED;
7580 memset ((char *) ultra_pipe_hist, 0, sizeof ultra_pipe_hist);
7582 ultra_cycles_elapsed = 0;
7583 ultra_pipe.free_slot_mask = 0xf;
7586 /* INSN has been scheduled, update pipeline commit state
7587 and return how many instructions are still to be
7588 scheduled in this group. */
7590 ultrasparc_variable_issue (insn)
7593 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7594 int i, left_to_fire;
7597 for (i = 0; i < 4; i++)
7599 if (up->group[i] == 0)
7602 if (up->group[i] == insn)
7606 else if (! up->commit[i])
7610 return left_to_fire;
7613 /* In actual_hazard_this_instance, we may have yanked some
7614 instructions from the ready list due to conflict cost
7615 adjustments. If so, and such an insn was in our pipeline
7616 group, remove it and update state. */
7618 ultra_rescan_pipeline_state (ready, n_ready)
7622 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7625 for (i = 0; i < 4; i++)
7627 rtx insn = up->group[i];
7633 /* If it has been committed, then it was removed from
7634 the ready list because it was actually scheduled,
7635 and that is not the case we are searching for here. */
7636 if (up->commit[i] != 0)
7639 for (j = n_ready - 1; j >= 0; j--)
7640 if (ready[j] == insn)
7643 /* If we didn't find it, toss it. */
7646 enum ultra_code ucode = up->codes[i];
7649 up->codes[i] = NONE;
7650 up->contents[ucode] = 0;
7652 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
7653 up->num_ieu_insns -= 1;
7655 up->free_slot_mask |= (1 << i);
7656 up->group_size -= 1;
7663 ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
7669 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7676 fprintf (dump, "\n;;\tUltraSPARC Looking at [");
7677 for (n = n_ready - 1; n >= 0; n--)
7679 rtx insn = ready[n];
7680 enum ultra_code ucode;
7682 if (recog_memoized (insn) < 0)
7684 ucode = ultra_code_from_mask (TMASK (get_attr_type (insn)));
7686 fprintf (dump, "%s(%d) ",
7687 ultra_code_names[ucode],
7690 fprintf (dump, "%s(%d)",
7691 ultra_code_names[ucode],
7694 fprintf (dump, "]\n");
7697 this_insn = n_ready - 1;
7699 /* Skip over junk we don't understand. */
7700 while ((this_insn >= 0)
7701 && recog_memoized (ready[this_insn]) < 0)
7704 ultra_build_types_avail (ready, this_insn + 1);
7706 while (this_insn >= 0) {
7707 int old_group_size = up->group_size;
7709 if (up->group_size != 0)
7713 num_committed = (up->commit[0] + up->commit[1] +
7714 up->commit[2] + up->commit[3]);
7715 /* If nothing has been commited from our group, or all of
7716 them have. Clear out the (current cycle's) pipeline
7717 state and start afresh. */
7718 if (num_committed == 0
7719 || num_committed == up->group_size)
7721 ultra_flush_pipeline ();
7727 /* OK, some ready list insns got requeued and thus removed
7728 from the ready list. Account for this fact. */
7729 ultra_rescan_pipeline_state (ready, n_ready);
7731 /* Something "changed", make this look like a newly
7732 formed group so the code at the end of the loop
7733 knows that progress was in fact made. */
7734 if (up->group_size != old_group_size)
7739 if (up->group_size == 0)
7741 /* If the pipeline is (still) empty and we have any single
7742 group insns, get them out now as this is a good time. */
7743 rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_ADDRESS) |
7744 TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) |
7745 TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)),
7749 ultra_schedule_insn (ip, ready, this_insn, SINGLE);
7753 /* If we are not in the process of emptying out the pipe, try to
7754 obtain an instruction which must be the first in it's group. */
7755 ip = ultra_find_type ((TMASK (TYPE_CALL) |
7756 TMASK (TYPE_SIBCALL) |
7757 TMASK (TYPE_CALL_NO_DELAY_SLOT) |
7758 TMASK (TYPE_UNCOND_BRANCH)),
7762 ultra_schedule_insn (ip, ready, this_insn, IEU1);
7765 else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) |
7766 TMASK (TYPE_FPDIVD) |
7767 TMASK (TYPE_FPSQRTS) |
7768 TMASK (TYPE_FPSQRTD)),
7769 ready, this_insn)) != 0)
7771 ultra_schedule_insn (ip, ready, this_insn, FPM);
7776 /* Try to fill the integer pipeline. First, look for an IEU0 specific
7777 operation. We can't do more IEU operations if the first 3 slots are
7778 all full or we have dispatched two IEU insns already. */
7779 if ((up->free_slot_mask & 0x7) != 0
7780 && up->num_ieu_insns < 2
7781 && up->contents[IEU0] == 0
7782 && up->contents[IEUN] == 0)
7784 rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn);
7787 ultra_schedule_insn (ip, ready, this_insn, IEU0);
7792 /* If we can, try to find an IEU1 specific or an unnamed
7794 if ((up->free_slot_mask & 0x7) != 0
7795 && up->num_ieu_insns < 2)
7797 rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
7798 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY) |
7799 (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)),
7805 ultra_schedule_insn (ip, ready, this_insn,
7806 (!up->contents[IEU1]
7807 && get_attr_type (insn) == TYPE_COMPARE)
7813 /* If only one IEU insn has been found, try to find another unnamed
7814 IEU operation or an IEU1 specific one. */
7815 if ((up->free_slot_mask & 0x7) != 0
7816 && up->num_ieu_insns < 2)
7819 int tmask = (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
7820 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY));
7822 if (!up->contents[IEU1])
7823 tmask |= TMASK (TYPE_COMPARE);
7824 ip = ultra_find_type (tmask, ready, this_insn);
7829 ultra_schedule_insn (ip, ready, this_insn,
7830 (!up->contents[IEU1]
7831 && get_attr_type (insn) == TYPE_COMPARE)
7837 /* Try for a load or store, but such an insn can only be issued
7838 if it is within' one of the first 3 slots. */
7839 if ((up->free_slot_mask & 0x7) != 0
7840 && up->contents[LSU] == 0)
7842 rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
7843 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
7844 TMASK (TYPE_FPSTORE)), ready, this_insn);
7847 ultra_schedule_insn (ip, ready, this_insn, LSU);
7852 /* Now find FPU operations, first FPM class. But not divisions or
7853 square-roots because those will break the group up. Unlike all
7854 the previous types, these can go in any slot. */
7855 if (up->free_slot_mask != 0
7856 && up->contents[FPM] == 0)
7858 rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn);
7861 ultra_schedule_insn (ip, ready, this_insn, FPM);
7866 /* Continue on with FPA class if we have not filled the group already. */
7867 if (up->free_slot_mask != 0
7868 && up->contents[FPA] == 0)
7870 rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
7871 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)),
7875 ultra_schedule_insn (ip, ready, this_insn, FPA);
7880 /* Finally, maybe stick a branch in here. */
7881 if (up->free_slot_mask != 0
7882 && up->contents[CTI] == 0)
7884 rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn);
7886 /* Try to slip in a branch only if it is one of the
7887 next 2 in the ready list. */
7888 if (ip && ((&ready[this_insn] - ip) < 2))
7890 ultra_schedule_insn (ip, ready, this_insn, CTI);
7896 for (i = 0; i < 4; i++)
7897 if ((up->free_slot_mask & (1 << i)) == 0)
7900 /* See if we made any progress... */
7901 if (old_group_size != up->group_size)
7904 /* Clean out the (current cycle's) pipeline state
7905 and try once more. If we placed no instructions
7906 into the pipeline at all, it means a real hard
7907 conflict exists with some earlier issued instruction
7908 so we must advance to the next cycle to clear it up. */
7909 if (up->group_size == 0)
7911 ultra_flush_pipeline ();
7916 memset ((char *) &ultra_pipe, 0, sizeof ultra_pipe);
7917 ultra_pipe.free_slot_mask = 0xf;
7925 fprintf (dump, ";;\tUltraSPARC Launched [");
7926 gsize = up->group_size;
7927 for (n = 0; n < 4; n++)
7929 rtx insn = up->group[n];
7936 fprintf (dump, "%s(%d) ",
7937 ultra_code_names[up->codes[n]],
7940 fprintf (dump, "%s(%d)",
7941 ultra_code_names[up->codes[n]],
7944 fprintf (dump, "]\n");
7956 /* Assume V9 processors are capable of at least dual-issue. */
7958 case PROCESSOR_SUPERSPARC:
7960 case PROCESSOR_HYPERSPARC:
7961 case PROCESSOR_SPARCLITE86X:
7963 case PROCESSOR_ULTRASPARC:
7972 register rtx pat = PATTERN (insn);
7974 switch (GET_CODE (SET_SRC (pat)))
7976 /* Load and some shift instructions zero extend. */
7979 /* sethi clears the high bits */
7981 /* LO_SUM is used with sethi. sethi cleared the high
7982 bits and the values used with lo_sum are positive */
7984 /* Store flag stores 0 or 1 */
7994 rtx op0 = XEXP (SET_SRC (pat), 0);
7995 rtx op1 = XEXP (SET_SRC (pat), 1);
7996 if (GET_CODE (op1) == CONST_INT)
7997 return INTVAL (op1) >= 0;
7998 if (GET_CODE (op0) != REG)
8000 if (sparc_check_64 (op0, insn) == 1)
8002 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8007 rtx op0 = XEXP (SET_SRC (pat), 0);
8008 rtx op1 = XEXP (SET_SRC (pat), 1);
8009 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8011 if (GET_CODE (op1) == CONST_INT)
8012 return INTVAL (op1) >= 0;
8013 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8017 return GET_MODE (SET_SRC (pat)) == SImode;
8018 /* Positive integers leave the high bits zero. */
8020 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8022 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8025 return - (GET_MODE (SET_SRC (pat)) == SImode);
8027 return sparc_check_64 (SET_SRC (pat), insn);
8033 /* We _ought_ to have only one kind per function, but... */
8034 static rtx sparc_addr_diff_list;
8035 static rtx sparc_addr_list;
8038 sparc_defer_case_vector (lab, vec, diff)
8042 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8044 sparc_addr_diff_list
8045 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8047 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8051 sparc_output_addr_vec (vec)
8054 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8055 int idx, vlen = XVECLEN (body, 0);
8057 #ifdef ASM_OUTPUT_ADDR_VEC_START
8058 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8061 #ifdef ASM_OUTPUT_CASE_LABEL
8062 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8065 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8068 for (idx = 0; idx < vlen; idx++)
8070 ASM_OUTPUT_ADDR_VEC_ELT
8071 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8074 #ifdef ASM_OUTPUT_ADDR_VEC_END
8075 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8080 sparc_output_addr_diff_vec (vec)
8083 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8084 rtx base = XEXP (XEXP (body, 0), 0);
8085 int idx, vlen = XVECLEN (body, 1);
8087 #ifdef ASM_OUTPUT_ADDR_VEC_START
8088 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8091 #ifdef ASM_OUTPUT_CASE_LABEL
8092 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8095 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8098 for (idx = 0; idx < vlen; idx++)
8100 ASM_OUTPUT_ADDR_DIFF_ELT
8103 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8104 CODE_LABEL_NUMBER (base));
8107 #ifdef ASM_OUTPUT_ADDR_VEC_END
8108 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8113 sparc_output_deferred_case_vectors ()
8118 if (sparc_addr_list == NULL_RTX
8119 && sparc_addr_diff_list == NULL_RTX)
8122 /* Align to cache line in the function's code section. */
8123 function_section (current_function_decl);
8125 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8127 ASM_OUTPUT_ALIGN (asm_out_file, align);
8129 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8130 sparc_output_addr_vec (XEXP (t, 0));
8131 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8132 sparc_output_addr_diff_vec (XEXP (t, 0));
8134 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8137 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8138 unknown. Return 1 if the high bits are zero, -1 if the register is
8141 sparc_check_64 (x, insn)
8144 /* If a register is set only once it is safe to ignore insns this
8145 code does not know how to handle. The loop will either recognize
8146 the single set and return the correct value or fail to recognize
8151 if (GET_CODE (x) != REG)
8154 if (GET_MODE (x) == DImode)
8155 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8157 if (flag_expensive_optimizations
8158 && REG_N_SETS (REGNO (y)) == 1)
8164 insn = get_last_insn_anywhere ();
8169 while ((insn = PREV_INSN (insn)))
8171 switch (GET_CODE (insn))
8184 rtx pat = PATTERN (insn);
8185 if (GET_CODE (pat) != SET)
8187 if (rtx_equal_p (x, SET_DEST (pat)))
8188 return set_extends (insn);
8189 if (y && rtx_equal_p (y, SET_DEST (pat)))
8190 return set_extends (insn);
8191 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8200 sparc_v8plus_shift (operands, insn, opcode)
8205 static char asm_code[60];
8207 if (GET_CODE (operands[3]) == SCRATCH)
8208 operands[3] = operands[0];
8209 if (GET_CODE (operands[1]) == CONST_INT)
8211 output_asm_insn ("mov\t%1, %3", operands);
8215 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8216 if (sparc_check_64 (operands[1], insn) <= 0)
8217 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8218 output_asm_insn ("or\t%L1, %3, %3", operands);
8221 strcpy(asm_code, opcode);
8222 if (which_alternative != 2)
8223 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8225 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8229 /* Return 1 if DEST and SRC reference only global and in registers. */
8232 sparc_return_peephole_ok (dest, src)
8237 if (current_function_uses_only_leaf_regs)
8239 if (GET_CODE (src) != CONST_INT
8240 && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src)))
8242 return IN_OR_GLOBAL_P (dest);
8245 /* Output assembler code to FILE to increment profiler label # LABELNO
8246 for profiling a function entry.
8248 32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered
8249 during profiling so we need to save/restore it around the call to mcount.
8250 We're guaranteed that a save has just been done, and we use the space
8251 allocated for intreg/fpreg value passing. */
8254 sparc_function_profiler (file, labelno)
8259 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8261 if (! TARGET_ARCH64)
8262 fputs ("\tst\t%g2, [%fp-4]\n", file);
8264 fputs ("\tsethi\t%hi(", file);
8265 assemble_name (file, buf);
8266 fputs ("), %o0\n", file);
8268 fputs ("\tcall\t", file);
8269 assemble_name (file, MCOUNT_FUNCTION);
8272 fputs ("\t or\t%o0, %lo(", file);
8273 assemble_name (file, buf);
8274 fputs ("), %o0\n", file);
8276 if (! TARGET_ARCH64)
8277 fputs ("\tld\t[%fp-4], %g2\n", file);
8281 /* The following macro shall output assembler code to FILE
8282 to initialize basic-block profiling.
8284 If profile_block_flag == 2
8286 Output code to call the subroutine `__bb_init_trace_func'
8287 and pass two parameters to it. The first parameter is
8288 the address of a block allocated in the object module.
8289 The second parameter is the number of the first basic block
8292 The name of the block is a local symbol made with this statement:
8294 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
8296 Of course, since you are writing the definition of
8297 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
8298 can take a short cut in the definition of this macro and use the
8299 name that you know will result.
8301 The number of the first basic block of the function is
8302 passed to the macro in BLOCK_OR_LABEL.
8304 If described in a virtual assembler language the code to be
8308 parameter2 <- BLOCK_OR_LABEL
8309 call __bb_init_trace_func
8311 else if profile_block_flag != 0
8313 Output code to call the subroutine `__bb_init_func'
8314 and pass one single parameter to it, which is the same
8315 as the first parameter to `__bb_init_trace_func'.
8317 The first word of this parameter is a flag which will be nonzero if
8318 the object module has already been initialized. So test this word
8319 first, and do not call `__bb_init_func' if the flag is nonzero.
8320 Note: When profile_block_flag == 2 the test need not be done
8321 but `__bb_init_trace_func' *must* be called.
8323 BLOCK_OR_LABEL may be used to generate a label number as a
8324 branch destination in case `__bb_init_func' will not be called.
8326 If described in a virtual assembler language the code to be
8338 sparc_function_block_profiler(file, block_or_label)
8343 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0);
8345 if (profile_block_flag == 2)
8347 fputs ("\tsethi\t%hi(", file);
8348 assemble_name (file, LPBX);
8349 fputs ("), %o0\n", file);
8351 fprintf (file, "\tsethi\t%%hi(%d), %%o1\n", block_or_label);
8353 fputs ("\tor\t%o0, %lo(", file);
8354 assemble_name (file, LPBX);
8355 fputs ("), %o0\n", file);
8357 fprintf (file, "\tcall\t%s__bb_init_trace_func\n", user_label_prefix);
8359 fprintf (file, "\t or\t%%o1, %%lo(%d), %%o1\n", block_or_label);
8361 else if (profile_block_flag != 0)
8364 ASM_GENERATE_INTERNAL_LABEL (LPBY, "LPBY", block_or_label);
8366 fputs ("\tsethi\t%hi(", file);
8367 assemble_name (file, LPBX);
8368 fputs ("), %o0\n", file);
8370 fputs ("\tld\t[%lo(", file);
8371 assemble_name (file, LPBX);
8372 fputs (")+%o0], %o1\n", file);
8374 fputs ("\ttst\t%o1\n", file);
8378 fputs ("\tbne,pn\t%icc,", file);
8379 assemble_name (file, LPBY);
8384 fputs ("\tbne\t", file);
8385 assemble_name (file, LPBY);
8389 fputs ("\t or\t%o0, %lo(", file);
8390 assemble_name (file, LPBX);
8391 fputs ("), %o0\n", file);
8393 fprintf (file, "\tcall\t%s__bb_init_func\n\t nop\n", user_label_prefix);
8395 ASM_OUTPUT_INTERNAL_LABEL (file, "LPBY", block_or_label);
8399 /* The following macro shall output assembler code to FILE
8400 to increment a counter associated with basic block number BLOCKNO.
8402 If profile_block_flag == 2
8404 Output code to initialize the global structure `__bb' and
8405 call the function `__bb_trace_func' which will increment the
8408 `__bb' consists of two words. In the first word the number
8409 of the basic block has to be stored. In the second word
8410 the address of a block allocated in the object module
8413 The basic block number is given by BLOCKNO.
8415 The address of the block is given by the label created with
8417 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
8419 by FUNCTION_BLOCK_PROFILER.
8421 Of course, since you are writing the definition of
8422 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
8423 can take a short cut in the definition of this macro and use the
8424 name that you know will result.
8426 If described in a virtual assembler language the code to be
8429 move BLOCKNO -> (__bb)
8430 move LPBX0 -> (__bb+4)
8431 call __bb_trace_func
8433 Note that function `__bb_trace_func' must not change the
8434 machine state, especially the flag register. To grant
8435 this, you must output code to save and restore registers
8436 either in this macro or in the macros MACHINE_STATE_SAVE
8437 and MACHINE_STATE_RESTORE. The last two macros will be
8438 used in the function `__bb_trace_func', so you must make
8439 sure that the function prologue does not change any
8440 register prior to saving it with MACHINE_STATE_SAVE.
8442 else if profile_block_flag != 0
8444 Output code to increment the counter directly.
8445 Basic blocks are numbered separately from zero within each
8446 compiled object module. The count associated with block number
8447 BLOCKNO is at index BLOCKNO in an array of words; the name of
8448 this array is a local symbol made with this statement:
8450 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
8452 Of course, since you are writing the definition of
8453 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
8454 can take a short cut in the definition of this macro and use the
8455 name that you know will result.
8457 If described in a virtual assembler language, the code to be
8460 inc (LPBX2+4*BLOCKNO)
8465 sparc_block_profiler(file, blockno)
8470 int bbreg = TARGET_ARCH64 ? 4 : 2;
8472 if (profile_block_flag == 2)
8474 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0);
8476 fprintf (file, "\tsethi\t%%hi(%s__bb), %%g1\n", user_label_prefix);
8477 fprintf (file, "\tsethi\t%%hi(%d), %%g%d\n", blockno, bbreg);
8478 fprintf (file, "\tor\t%%g1, %%lo(%s__bb), %%g1\n", user_label_prefix);
8479 fprintf (file, "\tor\t%%g%d, %%lo(%d), %%g%d\n", bbreg, blockno, bbreg);
8481 fprintf (file, "\tst\t%%g%d, [%%g1]\n", bbreg);
8483 fputs ("\tsethi\t%hi(", file);
8484 assemble_name (file, LPBX);
8485 fprintf (file, "), %%g%d\n", bbreg);
8487 fputs ("\tor\t%o2, %lo(", file);
8488 assemble_name (file, LPBX);
8489 fprintf (file, "), %%g%d\n", bbreg);
8491 fprintf (file, "\tst\t%%g%d, [%%g1 + 4]\n", bbreg);
8492 fprintf (file, "\tmov\t%%o7, %%g%d\n", bbreg);
8494 fprintf (file, "\tcall\t%s__bb_trace_func\n\t nop\n", user_label_prefix);
8496 fprintf (file, "\tmov\t%%g%d, %%o7\n", bbreg);
8498 else if (profile_block_flag != 0)
8500 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 2);
8502 fputs ("\tsethi\t%hi(", file);
8503 assemble_name (file, LPBX);
8504 fprintf (file, "+%d), %%g1\n", blockno*4);
8506 fputs ("\tld\t[%g1+%lo(", file);
8507 assemble_name (file, LPBX);
8508 if (TARGET_ARCH64 && USE_AS_OFFSETABLE_LO10)
8509 fprintf (file, ")+%d], %%g%d\n", blockno*4, bbreg);
8511 fprintf (file, "+%d)], %%g%d\n", blockno*4, bbreg);
8513 fprintf (file, "\tadd\t%%g%d, 1, %%g%d\n", bbreg, bbreg);
8515 fprintf (file, "\tst\t%%g%d, [%%g1+%%lo(", bbreg);
8516 assemble_name (file, LPBX);
8517 if (TARGET_ARCH64 && USE_AS_OFFSETABLE_LO10)
8518 fprintf (file, ")+%d]\n", blockno*4);
8520 fprintf (file, "+%d)]\n", blockno*4);
8524 /* The following macro shall output assembler code to FILE
8525 to indicate a return from function during basic-block profiling.
8527 If profile_block_flag == 2:
8529 Output assembler code to call function `__bb_trace_ret'.
8531 Note that function `__bb_trace_ret' must not change the
8532 machine state, especially the flag register. To grant
8533 this, you must output code to save and restore registers
8534 either in this macro or in the macros MACHINE_STATE_SAVE_RET
8535 and MACHINE_STATE_RESTORE_RET. The last two macros will be
8536 used in the function `__bb_trace_ret', so you must make
8537 sure that the function prologue does not change any
8538 register prior to saving it with MACHINE_STATE_SAVE_RET.
8540 else if profile_block_flag != 0:
8542 The macro will not be used, so it need not distinguish
8547 sparc_function_block_profiler_exit(file)
8550 if (profile_block_flag == 2)
8551 fprintf (file, "\tcall\t%s__bb_trace_ret\n\t nop\n", user_label_prefix);
8556 /* Mark ARG, which is really a struct ultrasparc_pipline_state *, for
8560 mark_ultrasparc_pipeline_state (arg)
8563 struct ultrasparc_pipeline_state *ups;
8566 ups = (struct ultrasparc_pipeline_state *) arg;
8567 for (i = 0; i < sizeof (ups->group) / sizeof (rtx); ++i)
8568 ggc_mark_rtx (ups->group[i]);
8571 /* Called to register all of our global variables with the garbage
8575 sparc_add_gc_roots ()
8577 ggc_add_rtx_root (&sparc_compare_op0, 1);
8578 ggc_add_rtx_root (&sparc_compare_op1, 1);
8579 ggc_add_rtx_root (&leaf_label, 1);
8580 ggc_add_rtx_root (&global_offset_table, 1);
8581 ggc_add_rtx_root (&get_pc_symbol, 1);
8582 ggc_add_rtx_root (&sparc_addr_diff_list, 1);
8583 ggc_add_rtx_root (&sparc_addr_list, 1);
8584 ggc_add_root (ultra_pipe_hist, ARRAY_SIZE (ultra_pipe_hist),
8585 sizeof (ultra_pipe_hist[0]), &mark_ultrasparc_pipeline_state);