1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by Michael Tiemann (tiemann@cygnus.com)
7 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
45 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "cfglayout.h"
53 #include "langhooks.h"
57 #include "dwarf2out.h"
62 struct processor_costs cypress_costs = {
63 COSTS_N_INSNS (2), /* int load */
64 COSTS_N_INSNS (2), /* int signed load */
65 COSTS_N_INSNS (2), /* int zeroed load */
66 COSTS_N_INSNS (2), /* float load */
67 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
68 COSTS_N_INSNS (5), /* fadd, fsub */
69 COSTS_N_INSNS (1), /* fcmp */
70 COSTS_N_INSNS (1), /* fmov, fmovr */
71 COSTS_N_INSNS (7), /* fmul */
72 COSTS_N_INSNS (37), /* fdivs */
73 COSTS_N_INSNS (37), /* fdivd */
74 COSTS_N_INSNS (63), /* fsqrts */
75 COSTS_N_INSNS (63), /* fsqrtd */
76 COSTS_N_INSNS (1), /* imul */
77 COSTS_N_INSNS (1), /* imulX */
78 0, /* imul bit factor */
79 COSTS_N_INSNS (1), /* idiv */
80 COSTS_N_INSNS (1), /* idivX */
81 COSTS_N_INSNS (1), /* movcc/movr */
82 0, /* shift penalty */
86 struct processor_costs supersparc_costs = {
87 COSTS_N_INSNS (1), /* int load */
88 COSTS_N_INSNS (1), /* int signed load */
89 COSTS_N_INSNS (1), /* int zeroed load */
90 COSTS_N_INSNS (0), /* float load */
91 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
92 COSTS_N_INSNS (3), /* fadd, fsub */
93 COSTS_N_INSNS (3), /* fcmp */
94 COSTS_N_INSNS (1), /* fmov, fmovr */
95 COSTS_N_INSNS (3), /* fmul */
96 COSTS_N_INSNS (6), /* fdivs */
97 COSTS_N_INSNS (9), /* fdivd */
98 COSTS_N_INSNS (12), /* fsqrts */
99 COSTS_N_INSNS (12), /* fsqrtd */
100 COSTS_N_INSNS (4), /* imul */
101 COSTS_N_INSNS (4), /* imulX */
102 0, /* imul bit factor */
103 COSTS_N_INSNS (4), /* idiv */
104 COSTS_N_INSNS (4), /* idivX */
105 COSTS_N_INSNS (1), /* movcc/movr */
106 1, /* shift penalty */
110 struct processor_costs hypersparc_costs = {
111 COSTS_N_INSNS (1), /* int load */
112 COSTS_N_INSNS (1), /* int signed load */
113 COSTS_N_INSNS (1), /* int zeroed load */
114 COSTS_N_INSNS (1), /* float load */
115 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
116 COSTS_N_INSNS (1), /* fadd, fsub */
117 COSTS_N_INSNS (1), /* fcmp */
118 COSTS_N_INSNS (1), /* fmov, fmovr */
119 COSTS_N_INSNS (1), /* fmul */
120 COSTS_N_INSNS (8), /* fdivs */
121 COSTS_N_INSNS (12), /* fdivd */
122 COSTS_N_INSNS (17), /* fsqrts */
123 COSTS_N_INSNS (17), /* fsqrtd */
124 COSTS_N_INSNS (17), /* imul */
125 COSTS_N_INSNS (17), /* imulX */
126 0, /* imul bit factor */
127 COSTS_N_INSNS (17), /* idiv */
128 COSTS_N_INSNS (17), /* idivX */
129 COSTS_N_INSNS (1), /* movcc/movr */
130 0, /* shift penalty */
134 struct processor_costs leon_costs = {
135 COSTS_N_INSNS (1), /* int load */
136 COSTS_N_INSNS (1), /* int signed load */
137 COSTS_N_INSNS (1), /* int zeroed load */
138 COSTS_N_INSNS (1), /* float load */
139 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
140 COSTS_N_INSNS (1), /* fadd, fsub */
141 COSTS_N_INSNS (1), /* fcmp */
142 COSTS_N_INSNS (1), /* fmov, fmovr */
143 COSTS_N_INSNS (1), /* fmul */
144 COSTS_N_INSNS (15), /* fdivs */
145 COSTS_N_INSNS (15), /* fdivd */
146 COSTS_N_INSNS (23), /* fsqrts */
147 COSTS_N_INSNS (23), /* fsqrtd */
148 COSTS_N_INSNS (5), /* imul */
149 COSTS_N_INSNS (5), /* imulX */
150 0, /* imul bit factor */
151 COSTS_N_INSNS (5), /* idiv */
152 COSTS_N_INSNS (5), /* idivX */
153 COSTS_N_INSNS (1), /* movcc/movr */
154 0, /* shift penalty */
158 struct processor_costs sparclet_costs = {
159 COSTS_N_INSNS (3), /* int load */
160 COSTS_N_INSNS (3), /* int signed load */
161 COSTS_N_INSNS (1), /* int zeroed load */
162 COSTS_N_INSNS (1), /* float load */
163 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
164 COSTS_N_INSNS (1), /* fadd, fsub */
165 COSTS_N_INSNS (1), /* fcmp */
166 COSTS_N_INSNS (1), /* fmov, fmovr */
167 COSTS_N_INSNS (1), /* fmul */
168 COSTS_N_INSNS (1), /* fdivs */
169 COSTS_N_INSNS (1), /* fdivd */
170 COSTS_N_INSNS (1), /* fsqrts */
171 COSTS_N_INSNS (1), /* fsqrtd */
172 COSTS_N_INSNS (5), /* imul */
173 COSTS_N_INSNS (5), /* imulX */
174 0, /* imul bit factor */
175 COSTS_N_INSNS (5), /* idiv */
176 COSTS_N_INSNS (5), /* idivX */
177 COSTS_N_INSNS (1), /* movcc/movr */
178 0, /* shift penalty */
182 struct processor_costs ultrasparc_costs = {
183 COSTS_N_INSNS (2), /* int load */
184 COSTS_N_INSNS (3), /* int signed load */
185 COSTS_N_INSNS (2), /* int zeroed load */
186 COSTS_N_INSNS (2), /* float load */
187 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
188 COSTS_N_INSNS (4), /* fadd, fsub */
189 COSTS_N_INSNS (1), /* fcmp */
190 COSTS_N_INSNS (2), /* fmov, fmovr */
191 COSTS_N_INSNS (4), /* fmul */
192 COSTS_N_INSNS (13), /* fdivs */
193 COSTS_N_INSNS (23), /* fdivd */
194 COSTS_N_INSNS (13), /* fsqrts */
195 COSTS_N_INSNS (23), /* fsqrtd */
196 COSTS_N_INSNS (4), /* imul */
197 COSTS_N_INSNS (4), /* imulX */
198 2, /* imul bit factor */
199 COSTS_N_INSNS (37), /* idiv */
200 COSTS_N_INSNS (68), /* idivX */
201 COSTS_N_INSNS (2), /* movcc/movr */
202 2, /* shift penalty */
206 struct processor_costs ultrasparc3_costs = {
207 COSTS_N_INSNS (2), /* int load */
208 COSTS_N_INSNS (3), /* int signed load */
209 COSTS_N_INSNS (3), /* int zeroed load */
210 COSTS_N_INSNS (2), /* float load */
211 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
212 COSTS_N_INSNS (4), /* fadd, fsub */
213 COSTS_N_INSNS (5), /* fcmp */
214 COSTS_N_INSNS (3), /* fmov, fmovr */
215 COSTS_N_INSNS (4), /* fmul */
216 COSTS_N_INSNS (17), /* fdivs */
217 COSTS_N_INSNS (20), /* fdivd */
218 COSTS_N_INSNS (20), /* fsqrts */
219 COSTS_N_INSNS (29), /* fsqrtd */
220 COSTS_N_INSNS (6), /* imul */
221 COSTS_N_INSNS (6), /* imulX */
222 0, /* imul bit factor */
223 COSTS_N_INSNS (40), /* idiv */
224 COSTS_N_INSNS (71), /* idivX */
225 COSTS_N_INSNS (2), /* movcc/movr */
226 0, /* shift penalty */
230 struct processor_costs niagara_costs = {
231 COSTS_N_INSNS (3), /* int load */
232 COSTS_N_INSNS (3), /* int signed load */
233 COSTS_N_INSNS (3), /* int zeroed load */
234 COSTS_N_INSNS (9), /* float load */
235 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
236 COSTS_N_INSNS (8), /* fadd, fsub */
237 COSTS_N_INSNS (26), /* fcmp */
238 COSTS_N_INSNS (8), /* fmov, fmovr */
239 COSTS_N_INSNS (29), /* fmul */
240 COSTS_N_INSNS (54), /* fdivs */
241 COSTS_N_INSNS (83), /* fdivd */
242 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
243 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
244 COSTS_N_INSNS (11), /* imul */
245 COSTS_N_INSNS (11), /* imulX */
246 0, /* imul bit factor */
247 COSTS_N_INSNS (72), /* idiv */
248 COSTS_N_INSNS (72), /* idivX */
249 COSTS_N_INSNS (1), /* movcc/movr */
250 0, /* shift penalty */
254 struct processor_costs niagara2_costs = {
255 COSTS_N_INSNS (3), /* int load */
256 COSTS_N_INSNS (3), /* int signed load */
257 COSTS_N_INSNS (3), /* int zeroed load */
258 COSTS_N_INSNS (3), /* float load */
259 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
260 COSTS_N_INSNS (6), /* fadd, fsub */
261 COSTS_N_INSNS (6), /* fcmp */
262 COSTS_N_INSNS (6), /* fmov, fmovr */
263 COSTS_N_INSNS (6), /* fmul */
264 COSTS_N_INSNS (19), /* fdivs */
265 COSTS_N_INSNS (33), /* fdivd */
266 COSTS_N_INSNS (19), /* fsqrts */
267 COSTS_N_INSNS (33), /* fsqrtd */
268 COSTS_N_INSNS (5), /* imul */
269 COSTS_N_INSNS (5), /* imulX */
270 0, /* imul bit factor */
271 COSTS_N_INSNS (31), /* idiv, average of 12 - 41 cycle range */
272 COSTS_N_INSNS (31), /* idivX, average of 12 - 41 cycle range */
273 COSTS_N_INSNS (1), /* movcc/movr */
274 0, /* shift penalty */
277 const struct processor_costs *sparc_costs = &cypress_costs;
279 #ifdef HAVE_AS_RELAX_OPTION
280 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
281 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
282 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
283 somebody does not branch between the sethi and jmp. */
284 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
286 #define LEAF_SIBCALL_SLOT_RESERVED_P \
287 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
290 /* Global variables for machine-dependent things. */
292 /* Size of frame. Need to know this to emit return insns from leaf procedures.
293 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
294 reload pass. This is important as the value is later used for scheduling
295 (to see what can go in a delay slot).
296 APPARENT_FSIZE is the size of the stack less the register save area and less
297 the outgoing argument area. It is used when saving call preserved regs. */
298 static HOST_WIDE_INT apparent_fsize;
299 static HOST_WIDE_INT actual_fsize;
301 /* Number of live general or floating point registers needed to be
302 saved (as 4-byte quantities). */
303 static int num_gfregs;
305 /* Vector to say how input registers are mapped to output registers.
306 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
307 eliminate it. You must use -fomit-frame-pointer to get that. */
308 char leaf_reg_remap[] =
309 { 0, 1, 2, 3, 4, 5, 6, 7,
310 -1, -1, -1, -1, -1, -1, 14, -1,
311 -1, -1, -1, -1, -1, -1, -1, -1,
312 8, 9, 10, 11, 12, 13, -1, 15,
314 32, 33, 34, 35, 36, 37, 38, 39,
315 40, 41, 42, 43, 44, 45, 46, 47,
316 48, 49, 50, 51, 52, 53, 54, 55,
317 56, 57, 58, 59, 60, 61, 62, 63,
318 64, 65, 66, 67, 68, 69, 70, 71,
319 72, 73, 74, 75, 76, 77, 78, 79,
320 80, 81, 82, 83, 84, 85, 86, 87,
321 88, 89, 90, 91, 92, 93, 94, 95,
322 96, 97, 98, 99, 100};
324 /* Vector, indexed by hard register number, which contains 1
325 for a register that is allowable in a candidate for leaf
326 function treatment. */
327 char sparc_leaf_regs[] =
328 { 1, 1, 1, 1, 1, 1, 1, 1,
329 0, 0, 0, 0, 0, 0, 1, 0,
330 0, 0, 0, 0, 0, 0, 0, 0,
331 1, 1, 1, 1, 1, 1, 0, 1,
332 1, 1, 1, 1, 1, 1, 1, 1,
333 1, 1, 1, 1, 1, 1, 1, 1,
334 1, 1, 1, 1, 1, 1, 1, 1,
335 1, 1, 1, 1, 1, 1, 1, 1,
336 1, 1, 1, 1, 1, 1, 1, 1,
337 1, 1, 1, 1, 1, 1, 1, 1,
338 1, 1, 1, 1, 1, 1, 1, 1,
339 1, 1, 1, 1, 1, 1, 1, 1,
342 struct GTY(()) machine_function
344 /* Some local-dynamic TLS symbol name. */
345 const char *some_ld_name;
347 /* True if the current function is leaf and uses only leaf regs,
348 so that the SPARC leaf function optimization can be applied.
349 Private version of current_function_uses_only_leaf_regs, see
350 sparc_expand_prologue for the rationale. */
353 /* True if the data calculated by sparc_expand_prologue are valid. */
354 bool prologue_data_valid_p;
357 #define sparc_leaf_function_p cfun->machine->leaf_function_p
358 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
360 /* Register we pretend to think the frame pointer is allocated to.
361 Normally, this is %fp, but if we are in a leaf procedure, this
362 is %sp+"something". We record "something" separately as it may
363 be too big for reg+constant addressing. */
364 static rtx frame_base_reg;
365 static HOST_WIDE_INT frame_base_offset;
367 /* 1 if the next opcode is to be specially indented. */
368 int sparc_indent_opcode = 0;
370 static void sparc_option_override (void);
371 static void sparc_init_modes (void);
372 static void scan_record_type (const_tree, int *, int *, int *);
373 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
374 const_tree, bool, bool, int *, int *);
376 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
377 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
379 static void sparc_emit_set_const32 (rtx, rtx);
380 static void sparc_emit_set_const64 (rtx, rtx);
381 static void sparc_output_addr_vec (rtx);
382 static void sparc_output_addr_diff_vec (rtx);
383 static void sparc_output_deferred_case_vectors (void);
384 static bool sparc_legitimate_address_p (enum machine_mode, rtx, bool);
385 static rtx sparc_builtin_saveregs (void);
386 static int epilogue_renumber (rtx *, int);
387 static bool sparc_assemble_integer (rtx, unsigned int, int);
388 static int set_extends (rtx);
389 static void load_got_register (void);
390 static int save_or_restore_regs (int, int, rtx, int, int);
391 static void emit_save_or_restore_regs (int);
392 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
393 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
394 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
395 tree) ATTRIBUTE_UNUSED;
396 static int sparc_adjust_cost (rtx, rtx, rtx, int);
397 static int sparc_issue_rate (void);
398 static void sparc_sched_init (FILE *, int, int);
399 static int sparc_use_sched_lookahead (void);
401 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
402 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
403 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
404 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
405 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
407 static bool sparc_function_ok_for_sibcall (tree, tree);
408 static void sparc_init_libfuncs (void);
409 static void sparc_init_builtins (void);
410 static void sparc_vis_init_builtins (void);
411 static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
412 static tree sparc_fold_builtin (tree, int, tree *, bool);
413 static int sparc_vis_mul8x16 (int, int);
414 static tree sparc_handle_vis_mul8x16 (int, tree, tree, tree);
415 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
416 HOST_WIDE_INT, tree);
417 static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,
418 HOST_WIDE_INT, const_tree);
419 static struct machine_function * sparc_init_machine_status (void);
420 static bool sparc_cannot_force_const_mem (rtx);
421 static rtx sparc_tls_get_addr (void);
422 static rtx sparc_tls_got (void);
423 static const char *get_some_local_dynamic_name (void);
424 static int get_some_local_dynamic_name_1 (rtx *, void *);
425 static bool sparc_rtx_costs (rtx, int, int, int *, bool);
426 static rtx sparc_function_value (const_tree, const_tree, bool);
427 static rtx sparc_libcall_value (enum machine_mode, const_rtx);
428 static bool sparc_function_value_regno_p (const unsigned int);
429 static rtx sparc_struct_value_rtx (tree, int);
430 static enum machine_mode sparc_promote_function_mode (const_tree, enum machine_mode,
431 int *, const_tree, int);
432 static bool sparc_return_in_memory (const_tree, const_tree);
433 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
434 static void sparc_va_start (tree, rtx);
435 static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
436 static bool sparc_vector_mode_supported_p (enum machine_mode);
437 static bool sparc_tls_referenced_p (rtx);
438 static rtx sparc_legitimize_tls_address (rtx);
439 static rtx sparc_legitimize_pic_address (rtx, rtx);
440 static rtx sparc_legitimize_address (rtx, rtx, enum machine_mode);
441 static rtx sparc_delegitimize_address (rtx);
442 static bool sparc_mode_dependent_address_p (const_rtx);
443 static bool sparc_pass_by_reference (CUMULATIVE_ARGS *,
444 enum machine_mode, const_tree, bool);
445 static void sparc_function_arg_advance (CUMULATIVE_ARGS *,
446 enum machine_mode, const_tree, bool);
447 static rtx sparc_function_arg_1 (const CUMULATIVE_ARGS *,
448 enum machine_mode, const_tree, bool, bool);
449 static rtx sparc_function_arg (CUMULATIVE_ARGS *,
450 enum machine_mode, const_tree, bool);
451 static rtx sparc_function_incoming_arg (CUMULATIVE_ARGS *,
452 enum machine_mode, const_tree, bool);
453 static unsigned int sparc_function_arg_boundary (enum machine_mode,
455 static int sparc_arg_partial_bytes (CUMULATIVE_ARGS *,
456 enum machine_mode, tree, bool);
457 static void sparc_dwarf_handle_frame_unspec (const char *, rtx, int);
458 static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
459 static void sparc_file_end (void);
460 static bool sparc_frame_pointer_required (void);
461 static bool sparc_can_eliminate (const int, const int);
462 static void sparc_conditional_register_usage (void);
463 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
464 static const char *sparc_mangle_type (const_tree);
466 static void sparc_trampoline_init (rtx, tree, rtx);
467 static enum machine_mode sparc_preferred_simd_mode (enum machine_mode);
468 static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass);
470 #ifdef SUBTARGET_ATTRIBUTE_TABLE
471 /* Table of valid machine attributes. */
472 static const struct attribute_spec sparc_attribute_table[] =
474 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
476 SUBTARGET_ATTRIBUTE_TABLE,
477 { NULL, 0, 0, false, false, false, NULL, false }
481 /* Option handling. */
484 enum cmodel sparc_cmodel;
486 char sparc_hard_reg_printed[8];
488 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
489 static const struct default_options sparc_option_optimization_table[] =
491 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
492 { OPT_LEVELS_NONE, 0, NULL, 0 }
495 /* Initialize the GCC target structure. */
497 /* The default is to use .half rather than .short for aligned HI objects. */
498 #undef TARGET_ASM_ALIGNED_HI_OP
499 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
501 #undef TARGET_ASM_UNALIGNED_HI_OP
502 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
503 #undef TARGET_ASM_UNALIGNED_SI_OP
504 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
505 #undef TARGET_ASM_UNALIGNED_DI_OP
506 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
508 /* The target hook has to handle DI-mode values. */
509 #undef TARGET_ASM_INTEGER
510 #define TARGET_ASM_INTEGER sparc_assemble_integer
512 #undef TARGET_ASM_FUNCTION_PROLOGUE
513 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
514 #undef TARGET_ASM_FUNCTION_EPILOGUE
515 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
517 #undef TARGET_SCHED_ADJUST_COST
518 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
519 #undef TARGET_SCHED_ISSUE_RATE
520 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
521 #undef TARGET_SCHED_INIT
522 #define TARGET_SCHED_INIT sparc_sched_init
523 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
524 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
526 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
527 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
529 #undef TARGET_INIT_LIBFUNCS
530 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
531 #undef TARGET_INIT_BUILTINS
532 #define TARGET_INIT_BUILTINS sparc_init_builtins
534 #undef TARGET_LEGITIMIZE_ADDRESS
535 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
536 #undef TARGET_DELEGITIMIZE_ADDRESS
537 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
538 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
539 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
541 #undef TARGET_EXPAND_BUILTIN
542 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
543 #undef TARGET_FOLD_BUILTIN
544 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
547 #undef TARGET_HAVE_TLS
548 #define TARGET_HAVE_TLS true
551 #undef TARGET_CANNOT_FORCE_CONST_MEM
552 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
554 #undef TARGET_ASM_OUTPUT_MI_THUNK
555 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
556 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
557 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
559 #undef TARGET_RTX_COSTS
560 #define TARGET_RTX_COSTS sparc_rtx_costs
561 #undef TARGET_ADDRESS_COST
562 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
564 #undef TARGET_PROMOTE_FUNCTION_MODE
565 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
567 #undef TARGET_FUNCTION_VALUE
568 #define TARGET_FUNCTION_VALUE sparc_function_value
569 #undef TARGET_LIBCALL_VALUE
570 #define TARGET_LIBCALL_VALUE sparc_libcall_value
571 #undef TARGET_FUNCTION_VALUE_REGNO_P
572 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
574 #undef TARGET_STRUCT_VALUE_RTX
575 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
576 #undef TARGET_RETURN_IN_MEMORY
577 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
578 #undef TARGET_MUST_PASS_IN_STACK
579 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
580 #undef TARGET_PASS_BY_REFERENCE
581 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
582 #undef TARGET_ARG_PARTIAL_BYTES
583 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
584 #undef TARGET_FUNCTION_ARG_ADVANCE
585 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
586 #undef TARGET_FUNCTION_ARG
587 #define TARGET_FUNCTION_ARG sparc_function_arg
588 #undef TARGET_FUNCTION_INCOMING_ARG
589 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
590 #undef TARGET_FUNCTION_ARG_BOUNDARY
591 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
593 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
594 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
595 #undef TARGET_STRICT_ARGUMENT_NAMING
596 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
598 #undef TARGET_EXPAND_BUILTIN_VA_START
599 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
600 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
601 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
603 #undef TARGET_VECTOR_MODE_SUPPORTED_P
604 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
606 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
607 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
609 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
610 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC sparc_dwarf_handle_frame_unspec
612 #ifdef SUBTARGET_INSERT_ATTRIBUTES
613 #undef TARGET_INSERT_ATTRIBUTES
614 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
617 #ifdef SUBTARGET_ATTRIBUTE_TABLE
618 #undef TARGET_ATTRIBUTE_TABLE
619 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
622 #undef TARGET_RELAXED_ORDERING
623 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
625 #undef TARGET_DEFAULT_TARGET_FLAGS
626 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
627 #undef TARGET_OPTION_OVERRIDE
628 #define TARGET_OPTION_OVERRIDE sparc_option_override
629 #undef TARGET_OPTION_OPTIMIZATION_TABLE
630 #define TARGET_OPTION_OPTIMIZATION_TABLE sparc_option_optimization_table
632 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
633 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
634 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
637 #undef TARGET_ASM_FILE_END
638 #define TARGET_ASM_FILE_END sparc_file_end
640 #undef TARGET_FRAME_POINTER_REQUIRED
641 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
643 #undef TARGET_CAN_ELIMINATE
644 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
645 #undef TARGET_PREFERRED_RELOAD_CLASS
646 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
648 #undef TARGET_CONDITIONAL_REGISTER_USAGE
649 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
651 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
652 #undef TARGET_MANGLE_TYPE
653 #define TARGET_MANGLE_TYPE sparc_mangle_type
656 #undef TARGET_LEGITIMATE_ADDRESS_P
657 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
659 #undef TARGET_TRAMPOLINE_INIT
660 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
662 struct gcc_target targetm = TARGET_INITIALIZER;
664 /* Validate and override various options, and do some machine dependent
668 sparc_option_override (void)
670 static struct code_model {
671 const char *const name;
672 const enum cmodel value;
673 } const cmodels[] = {
675 { "medlow", CM_MEDLOW },
676 { "medmid", CM_MEDMID },
677 { "medany", CM_MEDANY },
678 { "embmedany", CM_EMBMEDANY },
679 { NULL, (enum cmodel) 0 }
681 const struct code_model *cmodel;
682 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
683 static struct cpu_default {
685 const enum processor_type processor;
686 } const cpu_default[] = {
687 /* There must be one entry here for each TARGET_CPU value. */
688 { TARGET_CPU_sparc, PROCESSOR_CYPRESS },
689 { TARGET_CPU_v8, PROCESSOR_V8 },
690 { TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC },
691 { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },
692 { TARGET_CPU_leon, PROCESSOR_LEON },
693 { TARGET_CPU_sparclite, PROCESSOR_F930 },
694 { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },
695 { TARGET_CPU_sparclet, PROCESSOR_TSC701 },
696 { TARGET_CPU_v9, PROCESSOR_V9 },
697 { TARGET_CPU_ultrasparc, PROCESSOR_ULTRASPARC },
698 { TARGET_CPU_ultrasparc3, PROCESSOR_ULTRASPARC3 },
699 { TARGET_CPU_niagara, PROCESSOR_NIAGARA },
700 { TARGET_CPU_niagara2, PROCESSOR_NIAGARA2 },
703 const struct cpu_default *def;
704 /* Table of values for -m{cpu,tune}=. This must match the order of
705 the PROCESSOR_* enumeration. */
706 static struct cpu_table {
709 } const cpu_table[] = {
712 { MASK_ISA, MASK_V8 },
713 /* TI TMS390Z55 supersparc */
714 { MASK_ISA, MASK_V8 },
715 { MASK_ISA, MASK_V8|MASK_FPU },
717 { MASK_ISA, MASK_V8|MASK_FPU },
718 { MASK_ISA, MASK_SPARCLITE },
719 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
720 { MASK_ISA|MASK_FPU, MASK_SPARCLITE },
721 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
722 { MASK_ISA, MASK_SPARCLITE|MASK_FPU },
723 { MASK_ISA|MASK_FPU, MASK_SPARCLITE },
724 { MASK_ISA, MASK_SPARCLET },
726 { MASK_ISA, MASK_SPARCLET },
727 { MASK_ISA, MASK_V9 },
728 /* UltraSPARC I, II, IIi */
730 /* Although insns using %y are deprecated, it is a clear win. */
731 MASK_V9|MASK_DEPRECATED_V8_INSNS},
733 /* ??? Check if %y issue still holds true. */
735 MASK_V9|MASK_DEPRECATED_V8_INSNS},
738 MASK_V9|MASK_DEPRECATED_V8_INSNS},
740 { MASK_ISA, MASK_V9},
742 const struct cpu_table *cpu;
745 #ifdef SUBTARGET_OVERRIDE_OPTIONS
746 SUBTARGET_OVERRIDE_OPTIONS;
749 #ifndef SPARC_BI_ARCH
750 /* Check for unsupported architecture size. */
751 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
752 error ("%s is not supported by this configuration",
753 DEFAULT_ARCH32_P ? "-m64" : "-m32");
756 /* We force all 64bit archs to use 128 bit long double */
757 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
759 error ("-mlong-double-64 not allowed with -m64");
760 target_flags |= MASK_LONG_DOUBLE_128;
763 /* Code model selection. */
764 sparc_cmodel = SPARC_DEFAULT_CMODEL;
768 sparc_cmodel = CM_32;
771 if (sparc_cmodel_string != NULL)
775 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
776 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
778 if (cmodel->name == NULL)
779 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
781 sparc_cmodel = cmodel->value;
784 error ("-mcmodel= is not supported on 32 bit systems");
787 fpu = target_flags & MASK_FPU; /* save current -mfpu status */
789 /* Set the default CPU. */
790 if (!global_options_set.x_sparc_cpu_and_features)
792 for (def = &cpu_default[0]; def->cpu != -1; ++def)
793 if (def->cpu == TARGET_CPU_DEFAULT)
795 gcc_assert (def->cpu != -1);
796 sparc_cpu_and_features = def->processor;
798 if (!global_options_set.x_sparc_cpu)
799 sparc_cpu = sparc_cpu_and_features;
801 cpu = &cpu_table[(int) sparc_cpu_and_features];
802 target_flags &= ~cpu->disable;
803 target_flags |= cpu->enable;
805 /* If -mfpu or -mno-fpu was explicitly used, don't override with
806 the processor default. */
807 if (target_flags_explicit & MASK_FPU)
808 target_flags = (target_flags & ~MASK_FPU) | fpu;
810 /* Don't allow -mvis if FPU is disabled. */
812 target_flags &= ~MASK_VIS;
814 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
816 -m64 also implies v9. */
817 if (TARGET_VIS || TARGET_ARCH64)
819 target_flags |= MASK_V9;
820 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
823 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
824 if (TARGET_V9 && TARGET_ARCH32)
825 target_flags |= MASK_DEPRECATED_V8_INSNS;
827 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
828 if (! TARGET_V9 || TARGET_ARCH64)
829 target_flags &= ~MASK_V8PLUS;
831 /* Don't use stack biasing in 32 bit mode. */
833 target_flags &= ~MASK_STACK_BIAS;
835 /* Supply a default value for align_functions. */
836 if (align_functions == 0
837 && (sparc_cpu == PROCESSOR_ULTRASPARC
838 || sparc_cpu == PROCESSOR_ULTRASPARC3
839 || sparc_cpu == PROCESSOR_NIAGARA
840 || sparc_cpu == PROCESSOR_NIAGARA2))
841 align_functions = 32;
843 /* Validate PCC_STRUCT_RETURN. */
844 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
845 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
847 /* Only use .uaxword when compiling for a 64-bit target. */
849 targetm.asm_out.unaligned_op.di = NULL;
851 /* Do various machine dependent initializations. */
854 /* Set up function hooks. */
855 init_machine_status = sparc_init_machine_status;
860 case PROCESSOR_CYPRESS:
861 sparc_costs = &cypress_costs;
864 case PROCESSOR_SPARCLITE:
865 case PROCESSOR_SUPERSPARC:
866 sparc_costs = &supersparc_costs;
870 case PROCESSOR_HYPERSPARC:
871 case PROCESSOR_SPARCLITE86X:
872 sparc_costs = &hypersparc_costs;
875 sparc_costs = &leon_costs;
877 case PROCESSOR_SPARCLET:
878 case PROCESSOR_TSC701:
879 sparc_costs = &sparclet_costs;
882 case PROCESSOR_ULTRASPARC:
883 sparc_costs = &ultrasparc_costs;
885 case PROCESSOR_ULTRASPARC3:
886 sparc_costs = &ultrasparc3_costs;
888 case PROCESSOR_NIAGARA:
889 sparc_costs = &niagara_costs;
891 case PROCESSOR_NIAGARA2:
892 sparc_costs = &niagara2_costs;
896 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
897 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
898 target_flags |= MASK_LONG_DOUBLE_128;
901 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
902 ((sparc_cpu == PROCESSOR_ULTRASPARC
903 || sparc_cpu == PROCESSOR_NIAGARA
904 || sparc_cpu == PROCESSOR_NIAGARA2)
906 : (sparc_cpu == PROCESSOR_ULTRASPARC3
908 global_options.x_param_values,
909 global_options_set.x_param_values);
910 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
911 ((sparc_cpu == PROCESSOR_ULTRASPARC
912 || sparc_cpu == PROCESSOR_ULTRASPARC3
913 || sparc_cpu == PROCESSOR_NIAGARA
914 || sparc_cpu == PROCESSOR_NIAGARA2)
916 global_options.x_param_values,
917 global_options_set.x_param_values);
920 /* Miscellaneous utilities. */
922 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
923 or branch on register contents instructions. */
926 v9_regcmp_p (enum rtx_code code)
928 return (code == EQ || code == NE || code == GE || code == LT
929 || code == LE || code == GT);
932 /* Nonzero if OP is a floating point constant which can
933 be loaded into an integer register using a single
934 sethi instruction. */
939 if (GET_CODE (op) == CONST_DOUBLE)
944 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
945 REAL_VALUE_TO_TARGET_SINGLE (r, i);
946 return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i);
952 /* Nonzero if OP is a floating point constant which can
953 be loaded into an integer register using a single
959 if (GET_CODE (op) == CONST_DOUBLE)
964 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
965 REAL_VALUE_TO_TARGET_SINGLE (r, i);
966 return SPARC_SIMM13_P (i);
972 /* Nonzero if OP is a floating point constant which can
973 be loaded into an integer register using a high/losum
974 instruction sequence. */
977 fp_high_losum_p (rtx op)
979 /* The constraints calling this should only be in
980 SFmode move insns, so any constant which cannot
981 be moved using a single insn will do. */
982 if (GET_CODE (op) == CONST_DOUBLE)
987 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
988 REAL_VALUE_TO_TARGET_SINGLE (r, i);
989 return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i);
995 /* Return true if the address of LABEL can be loaded by means of the
996 mov{si,di}_pic_label_ref patterns in PIC mode. */
999 can_use_mov_pic_label_ref (rtx label)
1001 /* VxWorks does not impose a fixed gap between segments; the run-time
1002 gap can be different from the object-file gap. We therefore can't
1003 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1004 are absolutely sure that X is in the same segment as the GOT.
1005 Unfortunately, the flexibility of linker scripts means that we
1006 can't be sure of that in general, so assume that GOT-relative
1007 accesses are never valid on VxWorks. */
1008 if (TARGET_VXWORKS_RTP)
1011 /* Similarly, if the label is non-local, it might end up being placed
1012 in a different section than the current one; now mov_pic_label_ref
1013 requires the label and the code to be in the same section. */
1014 if (LABEL_REF_NONLOCAL_P (label))
1017 /* Finally, if we are reordering basic blocks and partition into hot
1018 and cold sections, this might happen for any label. */
1019 if (flag_reorder_blocks_and_partition)
1025 /* Expand a move instruction. Return true if all work is done. */
1028 sparc_expand_move (enum machine_mode mode, rtx *operands)
1030 /* Handle sets of MEM first. */
1031 if (GET_CODE (operands[0]) == MEM)
1033 /* 0 is a register (or a pair of registers) on SPARC. */
1034 if (register_or_zero_operand (operands[1], mode))
1037 if (!reload_in_progress)
1039 operands[0] = validize_mem (operands[0]);
1040 operands[1] = force_reg (mode, operands[1]);
1044 /* Fixup TLS cases. */
1046 && CONSTANT_P (operands[1])
1047 && sparc_tls_referenced_p (operands [1]))
1049 operands[1] = sparc_legitimize_tls_address (operands[1]);
1053 /* Fixup PIC cases. */
1054 if (flag_pic && CONSTANT_P (operands[1]))
1056 if (pic_address_needs_scratch (operands[1]))
1057 operands[1] = sparc_legitimize_pic_address (operands[1], NULL_RTX);
1059 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1060 if (GET_CODE (operands[1]) == LABEL_REF
1061 && can_use_mov_pic_label_ref (operands[1]))
1065 emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
1071 gcc_assert (TARGET_ARCH64);
1072 emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
1077 if (symbolic_operand (operands[1], mode))
1080 = sparc_legitimize_pic_address (operands[1],
1082 ? operands[0] : NULL_RTX);
1087 /* If we are trying to toss an integer constant into FP registers,
1088 or loading a FP or vector constant, force it into memory. */
1089 if (CONSTANT_P (operands[1])
1090 && REG_P (operands[0])
1091 && (SPARC_FP_REG_P (REGNO (operands[0]))
1092 || SCALAR_FLOAT_MODE_P (mode)
1093 || VECTOR_MODE_P (mode)))
1095 /* emit_group_store will send such bogosity to us when it is
1096 not storing directly into memory. So fix this up to avoid
1097 crashes in output_constant_pool. */
1098 if (operands [1] == const0_rtx)
1099 operands[1] = CONST0_RTX (mode);
1101 /* We can clear FP registers if TARGET_VIS, and always other regs. */
1102 if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
1103 && const_zero_operand (operands[1], mode))
1106 if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
1107 /* We are able to build any SF constant in integer registers
1108 with at most 2 instructions. */
1110 /* And any DF constant in integer registers. */
1112 && (reload_completed || reload_in_progress))))
1115 operands[1] = force_const_mem (mode, operands[1]);
1116 if (!reload_in_progress)
1117 operands[1] = validize_mem (operands[1]);
1121 /* Accept non-constants and valid constants unmodified. */
1122 if (!CONSTANT_P (operands[1])
1123 || GET_CODE (operands[1]) == HIGH
1124 || input_operand (operands[1], mode))
1130 /* All QImode constants require only one insn, so proceed. */
1135 sparc_emit_set_const32 (operands[0], operands[1]);
1139 /* input_operand should have filtered out 32-bit mode. */
1140 sparc_emit_set_const64 (operands[0], operands[1]);
1150 /* Load OP1, a 32-bit constant, into OP0, a register.
1151 We know it can't be done in one insn when we get
1152 here, the move expander guarantees this. */
1155 sparc_emit_set_const32 (rtx op0, rtx op1)
1157 enum machine_mode mode = GET_MODE (op0);
1160 if (reload_in_progress || reload_completed)
1163 temp = gen_reg_rtx (mode);
1165 if (GET_CODE (op1) == CONST_INT)
1167 gcc_assert (!small_int_operand (op1, mode)
1168 && !const_high_operand (op1, mode));
1170 /* Emit them as real moves instead of a HIGH/LO_SUM,
1171 this way CSE can see everything and reuse intermediate
1172 values if it wants. */
1173 emit_insn (gen_rtx_SET (VOIDmode, temp,
1174 GEN_INT (INTVAL (op1)
1175 & ~(HOST_WIDE_INT)0x3ff)));
1177 emit_insn (gen_rtx_SET (VOIDmode,
1179 gen_rtx_IOR (mode, temp,
1180 GEN_INT (INTVAL (op1) & 0x3ff))));
1184 /* A symbol, emit in the traditional way. */
1185 emit_insn (gen_rtx_SET (VOIDmode, temp,
1186 gen_rtx_HIGH (mode, op1)));
1187 emit_insn (gen_rtx_SET (VOIDmode,
1188 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1192 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1193 If TEMP is nonzero, we are forbidden to use any other scratch
1194 registers. Otherwise, we are allowed to generate them as needed.
1196 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1197 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1200 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1202 rtx temp1, temp2, temp3, temp4, temp5;
1205 if (temp && GET_MODE (temp) == TImode)
1208 temp = gen_rtx_REG (DImode, REGNO (temp));
1211 /* SPARC-V9 code-model support. */
1212 switch (sparc_cmodel)
1215 /* The range spanned by all instructions in the object is less
1216 than 2^31 bytes (2GB) and the distance from any instruction
1217 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1218 than 2^31 bytes (2GB).
1220 The executable must be in the low 4TB of the virtual address
1223 sethi %hi(symbol), %temp1
1224 or %temp1, %lo(symbol), %reg */
1226 temp1 = temp; /* op0 is allowed. */
1228 temp1 = gen_reg_rtx (DImode);
1230 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1231 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1235 /* The range spanned by all instructions in the object is less
1236 than 2^31 bytes (2GB) and the distance from any instruction
1237 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1238 than 2^31 bytes (2GB).
1240 The executable must be in the low 16TB of the virtual address
1243 sethi %h44(symbol), %temp1
1244 or %temp1, %m44(symbol), %temp2
1245 sllx %temp2, 12, %temp3
1246 or %temp3, %l44(symbol), %reg */
1251 temp3 = temp; /* op0 is allowed. */
1255 temp1 = gen_reg_rtx (DImode);
1256 temp2 = gen_reg_rtx (DImode);
1257 temp3 = gen_reg_rtx (DImode);
1260 emit_insn (gen_seth44 (temp1, op1));
1261 emit_insn (gen_setm44 (temp2, temp1, op1));
1262 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1263 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1264 emit_insn (gen_setl44 (op0, temp3, op1));
1268 /* The range spanned by all instructions in the object is less
1269 than 2^31 bytes (2GB) and the distance from any instruction
1270 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1271 than 2^31 bytes (2GB).
1273 The executable can be placed anywhere in the virtual address
1276 sethi %hh(symbol), %temp1
1277 sethi %lm(symbol), %temp2
1278 or %temp1, %hm(symbol), %temp3
1279 sllx %temp3, 32, %temp4
1280 or %temp4, %temp2, %temp5
1281 or %temp5, %lo(symbol), %reg */
1284 /* It is possible that one of the registers we got for operands[2]
1285 might coincide with that of operands[0] (which is why we made
1286 it TImode). Pick the other one to use as our scratch. */
1287 if (rtx_equal_p (temp, op0))
1289 gcc_assert (ti_temp);
1290 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1293 temp2 = temp; /* op0 is _not_ allowed, see above. */
1300 temp1 = gen_reg_rtx (DImode);
1301 temp2 = gen_reg_rtx (DImode);
1302 temp3 = gen_reg_rtx (DImode);
1303 temp4 = gen_reg_rtx (DImode);
1304 temp5 = gen_reg_rtx (DImode);
1307 emit_insn (gen_sethh (temp1, op1));
1308 emit_insn (gen_setlm (temp2, op1));
1309 emit_insn (gen_sethm (temp3, temp1, op1));
1310 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1311 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1312 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1313 gen_rtx_PLUS (DImode, temp4, temp2)));
1314 emit_insn (gen_setlo (op0, temp5, op1));
1318 /* Old old old backwards compatibility kruft here.
1319 Essentially it is MEDLOW with a fixed 64-bit
1320 virtual base added to all data segment addresses.
1321 Text-segment stuff is computed like MEDANY, we can't
1322 reuse the code above because the relocation knobs
1325 Data segment: sethi %hi(symbol), %temp1
1326 add %temp1, EMBMEDANY_BASE_REG, %temp2
1327 or %temp2, %lo(symbol), %reg */
1328 if (data_segment_operand (op1, GET_MODE (op1)))
1332 temp1 = temp; /* op0 is allowed. */
1337 temp1 = gen_reg_rtx (DImode);
1338 temp2 = gen_reg_rtx (DImode);
1341 emit_insn (gen_embmedany_sethi (temp1, op1));
1342 emit_insn (gen_embmedany_brsum (temp2, temp1));
1343 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1346 /* Text segment: sethi %uhi(symbol), %temp1
1347 sethi %hi(symbol), %temp2
1348 or %temp1, %ulo(symbol), %temp3
1349 sllx %temp3, 32, %temp4
1350 or %temp4, %temp2, %temp5
1351 or %temp5, %lo(symbol), %reg */
1356 /* It is possible that one of the registers we got for operands[2]
1357 might coincide with that of operands[0] (which is why we made
1358 it TImode). Pick the other one to use as our scratch. */
1359 if (rtx_equal_p (temp, op0))
1361 gcc_assert (ti_temp);
1362 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1365 temp2 = temp; /* op0 is _not_ allowed, see above. */
1372 temp1 = gen_reg_rtx (DImode);
1373 temp2 = gen_reg_rtx (DImode);
1374 temp3 = gen_reg_rtx (DImode);
1375 temp4 = gen_reg_rtx (DImode);
1376 temp5 = gen_reg_rtx (DImode);
1379 emit_insn (gen_embmedany_textuhi (temp1, op1));
1380 emit_insn (gen_embmedany_texthi (temp2, op1));
1381 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1382 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1383 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1384 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1385 gen_rtx_PLUS (DImode, temp4, temp2)));
1386 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1395 #if HOST_BITS_PER_WIDE_INT == 32
1397 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED)
1402 /* These avoid problems when cross compiling. If we do not
1403 go through all this hair then the optimizer will see
1404 invalid REG_EQUAL notes or in some cases none at all. */
1405 static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT);
1406 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1407 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1408 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1410 /* The optimizer is not to assume anything about exactly
1411 which bits are set for a HIGH, they are unspecified.
1412 Unfortunately this leads to many missed optimizations
1413 during CSE. We mask out the non-HIGH bits, and matches
1414 a plain movdi, to alleviate this problem. */
1416 gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1418 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff));
1422 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1424 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val));
1428 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1430 return gen_rtx_IOR (DImode, src, GEN_INT (val));
1434 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1436 return gen_rtx_XOR (DImode, src, GEN_INT (val));
1439 /* Worker routines for 64-bit constant formation on arch64.
1440 One of the key things to be doing in these emissions is
1441 to create as many temp REGs as possible. This makes it
1442 possible for half-built constants to be used later when
1443 such values are similar to something required later on.
1444 Without doing this, the optimizer cannot see such
1447 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1448 unsigned HOST_WIDE_INT, int);
1451 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1452 unsigned HOST_WIDE_INT low_bits, int is_neg)
1454 unsigned HOST_WIDE_INT high_bits;
1457 high_bits = (~low_bits) & 0xffffffff;
1459 high_bits = low_bits;
1461 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1464 emit_insn (gen_rtx_SET (VOIDmode, op0,
1465 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1469 /* If we are XOR'ing with -1, then we should emit a one's complement
1470 instead. This way the combiner will notice logical operations
1471 such as ANDN later on and substitute. */
1472 if ((low_bits & 0x3ff) == 0x3ff)
1474 emit_insn (gen_rtx_SET (VOIDmode, op0,
1475 gen_rtx_NOT (DImode, temp)));
1479 emit_insn (gen_rtx_SET (VOIDmode, op0,
1480 gen_safe_XOR64 (temp,
1481 (-(HOST_WIDE_INT)0x400
1482 | (low_bits & 0x3ff)))));
1487 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1488 unsigned HOST_WIDE_INT, int);
1491 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1492 unsigned HOST_WIDE_INT high_bits,
1493 unsigned HOST_WIDE_INT low_immediate,
1498 if ((high_bits & 0xfffffc00) != 0)
1500 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1501 if ((high_bits & ~0xfffffc00) != 0)
1502 emit_insn (gen_rtx_SET (VOIDmode, op0,
1503 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1509 emit_insn (gen_safe_SET64 (temp, high_bits));
1513 /* Now shift it up into place. */
1514 emit_insn (gen_rtx_SET (VOIDmode, op0,
1515 gen_rtx_ASHIFT (DImode, temp2,
1516 GEN_INT (shift_count))));
1518 /* If there is a low immediate part piece, finish up by
1519 putting that in as well. */
1520 if (low_immediate != 0)
1521 emit_insn (gen_rtx_SET (VOIDmode, op0,
1522 gen_safe_OR64 (op0, low_immediate)));
1525 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1526 unsigned HOST_WIDE_INT);
1528 /* Full 64-bit constant decomposition. Even though this is the
1529 'worst' case, we still optimize a few things away. */
1531 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1532 unsigned HOST_WIDE_INT high_bits,
1533 unsigned HOST_WIDE_INT low_bits)
1537 if (reload_in_progress || reload_completed)
1540 sub_temp = gen_reg_rtx (DImode);
1542 if ((high_bits & 0xfffffc00) != 0)
1544 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1545 if ((high_bits & ~0xfffffc00) != 0)
1546 emit_insn (gen_rtx_SET (VOIDmode,
1548 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1554 emit_insn (gen_safe_SET64 (temp, high_bits));
1558 if (!reload_in_progress && !reload_completed)
1560 rtx temp2 = gen_reg_rtx (DImode);
1561 rtx temp3 = gen_reg_rtx (DImode);
1562 rtx temp4 = gen_reg_rtx (DImode);
1564 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1565 gen_rtx_ASHIFT (DImode, sub_temp,
1568 emit_insn (gen_safe_HIGH64 (temp2, low_bits));
1569 if ((low_bits & ~0xfffffc00) != 0)
1571 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1572 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1573 emit_insn (gen_rtx_SET (VOIDmode, op0,
1574 gen_rtx_PLUS (DImode, temp4, temp3)));
1578 emit_insn (gen_rtx_SET (VOIDmode, op0,
1579 gen_rtx_PLUS (DImode, temp4, temp2)));
1584 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1585 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1586 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1589 /* We are in the middle of reload, so this is really
1590 painful. However we do still make an attempt to
1591 avoid emitting truly stupid code. */
1592 if (low1 != const0_rtx)
1594 emit_insn (gen_rtx_SET (VOIDmode, op0,
1595 gen_rtx_ASHIFT (DImode, sub_temp,
1596 GEN_INT (to_shift))));
1597 emit_insn (gen_rtx_SET (VOIDmode, op0,
1598 gen_rtx_IOR (DImode, op0, low1)));
1606 if (low2 != const0_rtx)
1608 emit_insn (gen_rtx_SET (VOIDmode, op0,
1609 gen_rtx_ASHIFT (DImode, sub_temp,
1610 GEN_INT (to_shift))));
1611 emit_insn (gen_rtx_SET (VOIDmode, op0,
1612 gen_rtx_IOR (DImode, op0, low2)));
1620 emit_insn (gen_rtx_SET (VOIDmode, op0,
1621 gen_rtx_ASHIFT (DImode, sub_temp,
1622 GEN_INT (to_shift))));
1623 if (low3 != const0_rtx)
1624 emit_insn (gen_rtx_SET (VOIDmode, op0,
1625 gen_rtx_IOR (DImode, op0, low3)));
1630 /* Analyze a 64-bit constant for certain properties. */
1631 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1632 unsigned HOST_WIDE_INT,
1633 int *, int *, int *);
1636 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1637 unsigned HOST_WIDE_INT low_bits,
1638 int *hbsp, int *lbsp, int *abbasp)
1640 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1643 lowest_bit_set = highest_bit_set = -1;
1647 if ((lowest_bit_set == -1)
1648 && ((low_bits >> i) & 1))
1650 if ((highest_bit_set == -1)
1651 && ((high_bits >> (32 - i - 1)) & 1))
1652 highest_bit_set = (64 - i - 1);
1655 && ((highest_bit_set == -1)
1656 || (lowest_bit_set == -1)));
1662 if ((lowest_bit_set == -1)
1663 && ((high_bits >> i) & 1))
1664 lowest_bit_set = i + 32;
1665 if ((highest_bit_set == -1)
1666 && ((low_bits >> (32 - i - 1)) & 1))
1667 highest_bit_set = 32 - i - 1;
1670 && ((highest_bit_set == -1)
1671 || (lowest_bit_set == -1)));
1673 /* If there are no bits set this should have gone out
1674 as one instruction! */
1675 gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1);
1676 all_bits_between_are_set = 1;
1677 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1681 if ((low_bits & (1 << i)) != 0)
1686 if ((high_bits & (1 << (i - 32))) != 0)
1689 all_bits_between_are_set = 0;
1692 *hbsp = highest_bit_set;
1693 *lbsp = lowest_bit_set;
1694 *abbasp = all_bits_between_are_set;
1697 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1700 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1701 unsigned HOST_WIDE_INT low_bits)
1703 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1706 || high_bits == 0xffffffff)
1709 analyze_64bit_constant (high_bits, low_bits,
1710 &highest_bit_set, &lowest_bit_set,
1711 &all_bits_between_are_set);
1713 if ((highest_bit_set == 63
1714 || lowest_bit_set == 0)
1715 && all_bits_between_are_set != 0)
1718 if ((highest_bit_set - lowest_bit_set) < 21)
1724 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1725 unsigned HOST_WIDE_INT,
1728 static unsigned HOST_WIDE_INT
1729 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1730 unsigned HOST_WIDE_INT low_bits,
1731 int lowest_bit_set, int shift)
1733 HOST_WIDE_INT hi, lo;
1735 if (lowest_bit_set < 32)
1737 lo = (low_bits >> lowest_bit_set) << shift;
1738 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1743 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1745 gcc_assert (! (hi & lo));
1749 /* Here we are sure to be arch64 and this is an integer constant
1750 being loaded into a register. Emit the most efficient
1751 insn sequence possible. Detection of all the 1-insn cases
1752 has been done already. */
1754 sparc_emit_set_const64 (rtx op0, rtx op1)
1756 unsigned HOST_WIDE_INT high_bits, low_bits;
1757 int lowest_bit_set, highest_bit_set;
1758 int all_bits_between_are_set;
1761 /* Sanity check that we know what we are working with. */
1762 gcc_assert (TARGET_ARCH64
1763 && (GET_CODE (op0) == SUBREG
1764 || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));
1766 if (reload_in_progress || reload_completed)
1769 if (GET_CODE (op1) != CONST_INT)
1771 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1776 temp = gen_reg_rtx (DImode);
1778 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1779 low_bits = (INTVAL (op1) & 0xffffffff);
1781 /* low_bits bits 0 --> 31
1782 high_bits bits 32 --> 63 */
1784 analyze_64bit_constant (high_bits, low_bits,
1785 &highest_bit_set, &lowest_bit_set,
1786 &all_bits_between_are_set);
1788 /* First try for a 2-insn sequence. */
1790 /* These situations are preferred because the optimizer can
1791 * do more things with them:
1793 * sllx %reg, shift, %reg
1795 * srlx %reg, shift, %reg
1796 * 3) mov some_small_const, %reg
1797 * sllx %reg, shift, %reg
1799 if (((highest_bit_set == 63
1800 || lowest_bit_set == 0)
1801 && all_bits_between_are_set != 0)
1802 || ((highest_bit_set - lowest_bit_set) < 12))
1804 HOST_WIDE_INT the_const = -1;
1805 int shift = lowest_bit_set;
1807 if ((highest_bit_set != 63
1808 && lowest_bit_set != 0)
1809 || all_bits_between_are_set == 0)
1812 create_simple_focus_bits (high_bits, low_bits,
1815 else if (lowest_bit_set == 0)
1816 shift = -(63 - highest_bit_set);
1818 gcc_assert (SPARC_SIMM13_P (the_const));
1819 gcc_assert (shift != 0);
1821 emit_insn (gen_safe_SET64 (temp, the_const));
1823 emit_insn (gen_rtx_SET (VOIDmode,
1825 gen_rtx_ASHIFT (DImode,
1829 emit_insn (gen_rtx_SET (VOIDmode,
1831 gen_rtx_LSHIFTRT (DImode,
1833 GEN_INT (-shift))));
1837 /* Now a range of 22 or less bits set somewhere.
1838 * 1) sethi %hi(focus_bits), %reg
1839 * sllx %reg, shift, %reg
1840 * 2) sethi %hi(focus_bits), %reg
1841 * srlx %reg, shift, %reg
1843 if ((highest_bit_set - lowest_bit_set) < 21)
1845 unsigned HOST_WIDE_INT focus_bits =
1846 create_simple_focus_bits (high_bits, low_bits,
1847 lowest_bit_set, 10);
1849 gcc_assert (SPARC_SETHI_P (focus_bits));
1850 gcc_assert (lowest_bit_set != 10);
1852 emit_insn (gen_safe_HIGH64 (temp, focus_bits));
1854 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1855 if (lowest_bit_set < 10)
1856 emit_insn (gen_rtx_SET (VOIDmode,
1858 gen_rtx_LSHIFTRT (DImode, temp,
1859 GEN_INT (10 - lowest_bit_set))));
1860 else if (lowest_bit_set > 10)
1861 emit_insn (gen_rtx_SET (VOIDmode,
1863 gen_rtx_ASHIFT (DImode, temp,
1864 GEN_INT (lowest_bit_set - 10))));
1868 /* 1) sethi %hi(low_bits), %reg
1869 * or %reg, %lo(low_bits), %reg
1870 * 2) sethi %hi(~low_bits), %reg
1871 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1874 || high_bits == 0xffffffff)
1876 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1877 (high_bits == 0xffffffff));
1881 /* Now, try 3-insn sequences. */
1883 /* 1) sethi %hi(high_bits), %reg
1884 * or %reg, %lo(high_bits), %reg
1885 * sllx %reg, 32, %reg
1889 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
1893 /* We may be able to do something quick
1894 when the constant is negated, so try that. */
1895 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1896 (~low_bits) & 0xfffffc00))
1898 /* NOTE: The trailing bits get XOR'd so we need the
1899 non-negated bits, not the negated ones. */
1900 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
1902 if ((((~high_bits) & 0xffffffff) == 0
1903 && ((~low_bits) & 0x80000000) == 0)
1904 || (((~high_bits) & 0xffffffff) == 0xffffffff
1905 && ((~low_bits) & 0x80000000) != 0))
1907 unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff);
1909 if ((SPARC_SETHI_P (fast_int)
1910 && (~high_bits & 0xffffffff) == 0)
1911 || SPARC_SIMM13_P (fast_int))
1912 emit_insn (gen_safe_SET64 (temp, fast_int));
1914 sparc_emit_set_const64 (temp, GEN_INT (fast_int));
1919 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
1920 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
1921 sparc_emit_set_const64 (temp, negated_const);
1924 /* If we are XOR'ing with -1, then we should emit a one's complement
1925 instead. This way the combiner will notice logical operations
1926 such as ANDN later on and substitute. */
1927 if (trailing_bits == 0x3ff)
1929 emit_insn (gen_rtx_SET (VOIDmode, op0,
1930 gen_rtx_NOT (DImode, temp)));
1934 emit_insn (gen_rtx_SET (VOIDmode,
1936 gen_safe_XOR64 (temp,
1937 (-0x400 | trailing_bits))));
1942 /* 1) sethi %hi(xxx), %reg
1943 * or %reg, %lo(xxx), %reg
1944 * sllx %reg, yyy, %reg
1946 * ??? This is just a generalized version of the low_bits==0
1947 * thing above, FIXME...
1949 if ((highest_bit_set - lowest_bit_set) < 32)
1951 unsigned HOST_WIDE_INT focus_bits =
1952 create_simple_focus_bits (high_bits, low_bits,
1955 /* We can't get here in this state. */
1956 gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32);
1958 /* So what we know is that the set bits straddle the
1959 middle of the 64-bit word. */
1960 sparc_emit_set_const64_quick2 (op0, temp,
1966 /* 1) sethi %hi(high_bits), %reg
1967 * or %reg, %lo(high_bits), %reg
1968 * sllx %reg, 32, %reg
1969 * or %reg, low_bits, %reg
1971 if (SPARC_SIMM13_P(low_bits)
1972 && ((int)low_bits > 0))
1974 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
1978 /* The easiest way when all else fails, is full decomposition. */
1979 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
1981 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
1983 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1984 return the mode to be used for the comparison. For floating-point,
1985 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
1986 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1987 processing is needed. */
1990 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
1992 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2018 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2019 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2021 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2022 return CCX_NOOVmode;
2028 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2035 /* Emit the compare insn and return the CC reg for a CODE comparison
2036 with operands X and Y. */
2039 gen_compare_reg_1 (enum rtx_code code, rtx x, rtx y)
2041 enum machine_mode mode;
2044 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
2047 mode = SELECT_CC_MODE (code, x, y);
2049 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2050 fcc regs (cse can't tell they're really call clobbered regs and will
2051 remove a duplicate comparison even if there is an intervening function
2052 call - it will then try to reload the cc reg via an int reg which is why
2053 we need the movcc patterns). It is possible to provide the movcc
2054 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2055 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2056 to tell cse that CCFPE mode registers (even pseudos) are call
2059 /* ??? This is an experiment. Rather than making changes to cse which may
2060 or may not be easy/clean, we do our own cse. This is possible because
2061 we will generate hard registers. Cse knows they're call clobbered (it
2062 doesn't know the same thing about pseudos). If we guess wrong, no big
2063 deal, but if we win, great! */
2065 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2066 #if 1 /* experiment */
2069 /* We cycle through the registers to ensure they're all exercised. */
2070 static int next_fcc_reg = 0;
2071 /* Previous x,y for each fcc reg. */
2072 static rtx prev_args[4][2];
2074 /* Scan prev_args for x,y. */
2075 for (reg = 0; reg < 4; reg++)
2076 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2081 prev_args[reg][0] = x;
2082 prev_args[reg][1] = y;
2083 next_fcc_reg = (next_fcc_reg + 1) & 3;
2085 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2088 cc_reg = gen_reg_rtx (mode);
2089 #endif /* ! experiment */
2090 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2091 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2093 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2095 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2096 will only result in an unrecognizable insn so no point in asserting. */
2097 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y)));
2103 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2106 gen_compare_reg (rtx cmp)
2108 return gen_compare_reg_1 (GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1));
2111 /* This function is used for v9 only.
2112 DEST is the target of the Scc insn.
2113 CODE is the code for an Scc's comparison.
2114 X and Y are the values we compare.
2116 This function is needed to turn
2119 (gt (reg:CCX 100 %icc)
2123 (gt:DI (reg:CCX 100 %icc)
2126 IE: The instruction recognizer needs to see the mode of the comparison to
2127 find the right instruction. We could use "gt:DI" right in the
2128 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2131 gen_v9_scc (rtx dest, enum rtx_code compare_code, rtx x, rtx y)
2134 && (GET_MODE (x) == DImode
2135 || GET_MODE (dest) == DImode))
2138 /* Try to use the movrCC insns. */
2140 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT
2142 && v9_regcmp_p (compare_code))
2147 /* Special case for op0 != 0. This can be done with one instruction if
2150 if (compare_code == NE
2151 && GET_MODE (dest) == DImode
2152 && rtx_equal_p (op0, dest))
2154 emit_insn (gen_rtx_SET (VOIDmode, dest,
2155 gen_rtx_IF_THEN_ELSE (DImode,
2156 gen_rtx_fmt_ee (compare_code, DImode,
2163 if (reg_overlap_mentioned_p (dest, op0))
2165 /* Handle the case where dest == x.
2166 We "early clobber" the result. */
2167 op0 = gen_reg_rtx (GET_MODE (x));
2168 emit_move_insn (op0, x);
2171 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
2172 if (GET_MODE (op0) != DImode)
2174 temp = gen_reg_rtx (DImode);
2175 convert_move (temp, op0, 0);
2179 emit_insn (gen_rtx_SET (VOIDmode, dest,
2180 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
2181 gen_rtx_fmt_ee (compare_code, DImode,
2189 x = gen_compare_reg_1 (compare_code, x, y);
2192 gcc_assert (GET_MODE (x) != CC_NOOVmode
2193 && GET_MODE (x) != CCX_NOOVmode);
2195 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
2196 emit_insn (gen_rtx_SET (VOIDmode, dest,
2197 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
2198 gen_rtx_fmt_ee (compare_code,
2199 GET_MODE (x), x, y),
2200 const1_rtx, dest)));
2206 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2207 without jumps using the addx/subx instructions. */
2210 emit_scc_insn (rtx operands[])
2217 /* The quad-word fp compare library routines all return nonzero to indicate
2218 true, which is different from the equivalent libgcc routines, so we must
2219 handle them specially here. */
2220 if (GET_MODE (operands[2]) == TFmode && ! TARGET_HARD_QUAD)
2222 operands[1] = sparc_emit_float_lib_cmp (operands[2], operands[3],
2223 GET_CODE (operands[1]));
2224 operands[2] = XEXP (operands[1], 0);
2225 operands[3] = XEXP (operands[1], 1);
2228 code = GET_CODE (operands[1]);
2232 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2233 more applications). The exception to this is "reg != 0" which can
2234 be done in one instruction on v9 (so we do it). */
2237 if (GET_MODE (x) == SImode)
2239 rtx pat = gen_seqsi_special (operands[0], x, y);
2243 else if (GET_MODE (x) == DImode)
2245 rtx pat = gen_seqdi_special (operands[0], x, y);
2253 if (GET_MODE (x) == SImode)
2255 rtx pat = gen_snesi_special (operands[0], x, y);
2259 else if (GET_MODE (x) == DImode)
2261 rtx pat = gen_snedi_special (operands[0], x, y);
2267 /* For the rest, on v9 we can use conditional moves. */
2271 if (gen_v9_scc (operands[0], code, x, y))
2275 /* We can do LTU and GEU using the addx/subx instructions too. And
2276 for GTU/LEU, if both operands are registers swap them and fall
2277 back to the easy case. */
2278 if (code == GTU || code == LEU)
2280 if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2281 && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG))
2286 code = swap_condition (code);
2290 if (code == LTU || code == GEU)
2292 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2293 gen_rtx_fmt_ee (code, SImode,
2294 gen_compare_reg_1 (code, x, y),
2299 /* Nope, do branches. */
2303 /* Emit a conditional jump insn for the v9 architecture using comparison code
2304 CODE and jump target LABEL.
2305 This function exists to take advantage of the v9 brxx insns. */
2308 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2310 emit_jump_insn (gen_rtx_SET (VOIDmode,
2312 gen_rtx_IF_THEN_ELSE (VOIDmode,
2313 gen_rtx_fmt_ee (code, GET_MODE (op0),
2315 gen_rtx_LABEL_REF (VOIDmode, label),
2320 emit_conditional_branch_insn (rtx operands[])
2322 /* The quad-word fp compare library routines all return nonzero to indicate
2323 true, which is different from the equivalent libgcc routines, so we must
2324 handle them specially here. */
2325 if (GET_MODE (operands[1]) == TFmode && ! TARGET_HARD_QUAD)
2327 operands[0] = sparc_emit_float_lib_cmp (operands[1], operands[2],
2328 GET_CODE (operands[0]));
2329 operands[1] = XEXP (operands[0], 0);
2330 operands[2] = XEXP (operands[0], 1);
2333 if (TARGET_ARCH64 && operands[2] == const0_rtx
2334 && GET_CODE (operands[1]) == REG
2335 && GET_MODE (operands[1]) == DImode)
2337 emit_v9_brxx_insn (GET_CODE (operands[0]), operands[1], operands[3]);
2341 operands[1] = gen_compare_reg (operands[0]);
2342 operands[2] = const0_rtx;
2343 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]), VOIDmode,
2344 operands[1], operands[2]);
2345 emit_jump_insn (gen_cbranchcc4 (operands[0], operands[1], operands[2],
2350 /* Generate a DFmode part of a hard TFmode register.
2351 REG is the TFmode hard register, LOW is 1 for the
2352 low 64bit of the register and 0 otherwise.
2355 gen_df_reg (rtx reg, int low)
2357 int regno = REGNO (reg);
2359 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2360 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2361 return gen_rtx_REG (DFmode, regno);
2364 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2365 Unlike normal calls, TFmode operands are passed by reference. It is
2366 assumed that no more than 3 operands are required. */
2369 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2371 rtx ret_slot = NULL, arg[3], func_sym;
2374 /* We only expect to be called for conversions, unary, and binary ops. */
2375 gcc_assert (nargs == 2 || nargs == 3);
2377 for (i = 0; i < nargs; ++i)
2379 rtx this_arg = operands[i];
2382 /* TFmode arguments and return values are passed by reference. */
2383 if (GET_MODE (this_arg) == TFmode)
2385 int force_stack_temp;
2387 force_stack_temp = 0;
2388 if (TARGET_BUGGY_QP_LIB && i == 0)
2389 force_stack_temp = 1;
2391 if (GET_CODE (this_arg) == MEM
2392 && ! force_stack_temp)
2393 this_arg = XEXP (this_arg, 0);
2394 else if (CONSTANT_P (this_arg)
2395 && ! force_stack_temp)
2397 this_slot = force_const_mem (TFmode, this_arg);
2398 this_arg = XEXP (this_slot, 0);
2402 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2404 /* Operand 0 is the return value. We'll copy it out later. */
2406 emit_move_insn (this_slot, this_arg);
2408 ret_slot = this_slot;
2410 this_arg = XEXP (this_slot, 0);
2417 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2419 if (GET_MODE (operands[0]) == TFmode)
2422 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2423 arg[0], GET_MODE (arg[0]),
2424 arg[1], GET_MODE (arg[1]));
2426 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2427 arg[0], GET_MODE (arg[0]),
2428 arg[1], GET_MODE (arg[1]),
2429 arg[2], GET_MODE (arg[2]));
2432 emit_move_insn (operands[0], ret_slot);
2438 gcc_assert (nargs == 2);
2440 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2441 GET_MODE (operands[0]), 1,
2442 arg[1], GET_MODE (arg[1]));
2444 if (ret != operands[0])
2445 emit_move_insn (operands[0], ret);
2449 /* Expand soft-float TFmode calls to sparc abi routines. */
2452 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2474 emit_soft_tfmode_libcall (func, 3, operands);
2478 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2482 gcc_assert (code == SQRT);
2485 emit_soft_tfmode_libcall (func, 2, operands);
2489 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2496 switch (GET_MODE (operands[1]))
2509 case FLOAT_TRUNCATE:
2510 switch (GET_MODE (operands[0]))
2524 switch (GET_MODE (operands[1]))
2529 operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]);
2539 case UNSIGNED_FLOAT:
2540 switch (GET_MODE (operands[1]))
2545 operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2556 switch (GET_MODE (operands[0]))
2570 switch (GET_MODE (operands[0]))
2587 emit_soft_tfmode_libcall (func, 2, operands);
2590 /* Expand a hard-float tfmode operation. All arguments must be in
2594 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2598 if (GET_RTX_CLASS (code) == RTX_UNARY)
2600 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2601 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2605 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2606 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2607 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2608 operands[1], operands[2]);
2611 if (register_operand (operands[0], VOIDmode))
2614 dest = gen_reg_rtx (GET_MODE (operands[0]));
2616 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2618 if (dest != operands[0])
2619 emit_move_insn (operands[0], dest);
2623 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2625 if (TARGET_HARD_QUAD)
2626 emit_hard_tfmode_operation (code, operands);
2628 emit_soft_tfmode_binop (code, operands);
2632 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2634 if (TARGET_HARD_QUAD)
2635 emit_hard_tfmode_operation (code, operands);
2637 emit_soft_tfmode_unop (code, operands);
2641 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2643 if (TARGET_HARD_QUAD)
2644 emit_hard_tfmode_operation (code, operands);
2646 emit_soft_tfmode_cvt (code, operands);
2649 /* Return nonzero if a branch/jump/call instruction will be emitting
2650 nop into its delay slot. */
2653 empty_delay_slot (rtx insn)
2657 /* If no previous instruction (should not happen), return true. */
2658 if (PREV_INSN (insn) == NULL)
2661 seq = NEXT_INSN (PREV_INSN (insn));
2662 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2668 /* Return nonzero if TRIAL can go into the call delay slot. */
2671 tls_call_delay (rtx trial)
2676 call __tls_get_addr, %tgd_call (foo)
2677 add %l7, %o0, %o0, %tgd_add (foo)
2678 while Sun as/ld does not. */
2679 if (TARGET_GNU_TLS || !TARGET_TLS)
2682 pat = PATTERN (trial);
2684 /* We must reject tgd_add{32|64}, i.e.
2685 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2686 and tldm_add{32|64}, i.e.
2687 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2689 if (GET_CODE (pat) == SET
2690 && GET_CODE (SET_SRC (pat)) == PLUS)
2692 rtx unspec = XEXP (SET_SRC (pat), 1);
2694 if (GET_CODE (unspec) == UNSPEC
2695 && (XINT (unspec, 1) == UNSPEC_TLSGD
2696 || XINT (unspec, 1) == UNSPEC_TLSLDM))
2703 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2704 instruction. RETURN_P is true if the v9 variant 'return' is to be
2705 considered in the test too.
2707 TRIAL must be a SET whose destination is a REG appropriate for the
2708 'restore' instruction or, if RETURN_P is true, for the 'return'
2712 eligible_for_restore_insn (rtx trial, bool return_p)
2714 rtx pat = PATTERN (trial);
2715 rtx src = SET_SRC (pat);
2717 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2718 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2719 && arith_operand (src, GET_MODE (src)))
2722 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2724 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2727 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2728 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2729 && arith_double_operand (src, GET_MODE (src)))
2730 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2732 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2733 else if (! TARGET_FPU && register_operand (src, SFmode))
2736 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2737 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
2740 /* If we have the 'return' instruction, anything that does not use
2741 local or output registers and can go into a delay slot wins. */
2742 else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1)
2743 && (get_attr_in_uncond_branch_delay (trial)
2744 == IN_UNCOND_BRANCH_DELAY_TRUE))
2747 /* The 'restore src1,src2,dest' pattern for SImode. */
2748 else if (GET_CODE (src) == PLUS
2749 && register_operand (XEXP (src, 0), SImode)
2750 && arith_operand (XEXP (src, 1), SImode))
2753 /* The 'restore src1,src2,dest' pattern for DImode. */
2754 else if (GET_CODE (src) == PLUS
2755 && register_operand (XEXP (src, 0), DImode)
2756 && arith_double_operand (XEXP (src, 1), DImode))
2759 /* The 'restore src1,%lo(src2),dest' pattern. */
2760 else if (GET_CODE (src) == LO_SUM
2761 && ! TARGET_CM_MEDMID
2762 && ((register_operand (XEXP (src, 0), SImode)
2763 && immediate_operand (XEXP (src, 1), SImode))
2765 && register_operand (XEXP (src, 0), DImode)
2766 && immediate_operand (XEXP (src, 1), DImode))))
2769 /* The 'restore src,src,dest' pattern. */
2770 else if (GET_CODE (src) == ASHIFT
2771 && (register_operand (XEXP (src, 0), SImode)
2772 || register_operand (XEXP (src, 0), DImode))
2773 && XEXP (src, 1) == const1_rtx)
2779 /* Return nonzero if TRIAL can go into the function return's
2783 eligible_for_return_delay (rtx trial)
2787 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2790 if (get_attr_length (trial) != 1)
2793 /* If there are any call-saved registers, we should scan TRIAL if it
2794 does not reference them. For now just make it easy. */
2798 /* If the function uses __builtin_eh_return, the eh_return machinery
2799 occupies the delay slot. */
2800 if (crtl->calls_eh_return)
2803 /* In the case of a true leaf function, anything can go into the slot. */
2804 if (sparc_leaf_function_p)
2805 return get_attr_in_uncond_branch_delay (trial)
2806 == IN_UNCOND_BRANCH_DELAY_TRUE;
2808 pat = PATTERN (trial);
2810 /* Otherwise, only operations which can be done in tandem with
2811 a `restore' or `return' insn can go into the delay slot. */
2812 if (GET_CODE (SET_DEST (pat)) != REG
2813 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
2816 /* If this instruction sets up floating point register and we have a return
2817 instruction, it can probably go in. But restore will not work
2819 if (REGNO (SET_DEST (pat)) >= 32)
2821 && ! epilogue_renumber (&pat, 1)
2822 && (get_attr_in_uncond_branch_delay (trial)
2823 == IN_UNCOND_BRANCH_DELAY_TRUE));
2825 return eligible_for_restore_insn (trial, true);
2828 /* Return nonzero if TRIAL can go into the sibling call's
2832 eligible_for_sibcall_delay (rtx trial)
2836 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2839 if (get_attr_length (trial) != 1)
2842 pat = PATTERN (trial);
2844 if (sparc_leaf_function_p)
2846 /* If the tail call is done using the call instruction,
2847 we have to restore %o7 in the delay slot. */
2848 if (LEAF_SIBCALL_SLOT_RESERVED_P)
2851 /* %g1 is used to build the function address */
2852 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2858 /* Otherwise, only operations which can be done in tandem with
2859 a `restore' insn can go into the delay slot. */
2860 if (GET_CODE (SET_DEST (pat)) != REG
2861 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
2862 || REGNO (SET_DEST (pat)) >= 32)
2865 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2867 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2870 return eligible_for_restore_insn (trial, false);
2874 short_branch (int uid1, int uid2)
2876 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
2878 /* Leave a few words of "slop". */
2879 if (delta >= -1023 && delta <= 1022)
2885 /* Return nonzero if REG is not used after INSN.
2886 We assume REG is a reload reg, and therefore does
2887 not live past labels or calls or jumps. */
2889 reg_unused_after (rtx reg, rtx insn)
2891 enum rtx_code code, prev_code = UNKNOWN;
2893 while ((insn = NEXT_INSN (insn)))
2895 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2898 code = GET_CODE (insn);
2899 if (GET_CODE (insn) == CODE_LABEL)
2904 rtx set = single_set (insn);
2905 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2908 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2910 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2918 /* Determine if it's legal to put X into the constant pool. This
2919 is not possible if X contains the address of a symbol that is
2920 not constant (TLS) or not known at final link time (PIC). */
2923 sparc_cannot_force_const_mem (rtx x)
2925 switch (GET_CODE (x))
2930 /* Accept all non-symbolic constants. */
2934 /* Labels are OK iff we are non-PIC. */
2935 return flag_pic != 0;
2938 /* 'Naked' TLS symbol references are never OK,
2939 non-TLS symbols are OK iff we are non-PIC. */
2940 if (SYMBOL_REF_TLS_MODEL (x))
2943 return flag_pic != 0;
2946 return sparc_cannot_force_const_mem (XEXP (x, 0));
2949 return sparc_cannot_force_const_mem (XEXP (x, 0))
2950 || sparc_cannot_force_const_mem (XEXP (x, 1));
2958 /* Global Offset Table support. */
2959 static GTY(()) rtx got_helper_rtx = NULL_RTX;
2960 static GTY(()) rtx global_offset_table_rtx = NULL_RTX;
2962 /* Return the SYMBOL_REF for the Global Offset Table. */
2964 static GTY(()) rtx sparc_got_symbol = NULL_RTX;
2969 if (!sparc_got_symbol)
2970 sparc_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2972 return sparc_got_symbol;
2975 /* Ensure that we are not using patterns that are not OK with PIC. */
2985 op = recog_data.operand[i];
2986 gcc_assert (GET_CODE (op) != SYMBOL_REF
2987 && (GET_CODE (op) != CONST
2988 || (GET_CODE (XEXP (op, 0)) == MINUS
2989 && XEXP (XEXP (op, 0), 0) == sparc_got ()
2990 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST)));
2997 /* Return true if X is an address which needs a temporary register when
2998 reloaded while generating PIC code. */
3001 pic_address_needs_scratch (rtx x)
3003 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3004 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3005 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3006 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3007 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3013 /* Determine if a given RTX is a valid constant. We already know this
3014 satisfies CONSTANT_P. */
3017 legitimate_constant_p (rtx x)
3019 switch (GET_CODE (x))
3023 if (sparc_tls_referenced_p (x))
3028 if (GET_MODE (x) == VOIDmode)
3031 /* Floating point constants are generally not ok.
3032 The only exception is 0.0 in VIS. */
3034 && SCALAR_FLOAT_MODE_P (GET_MODE (x))
3035 && const_zero_operand (x, GET_MODE (x)))
3041 /* Vector constants are generally not ok.
3042 The only exception is 0 in VIS. */
3044 && const_zero_operand (x, GET_MODE (x)))
3056 /* Determine if a given RTX is a valid constant address. */
3059 constant_address_p (rtx x)
3061 switch (GET_CODE (x))
3069 if (flag_pic && pic_address_needs_scratch (x))
3071 return legitimate_constant_p (x);
3074 return !flag_pic && legitimate_constant_p (x);
3081 /* Nonzero if the constant value X is a legitimate general operand
3082 when generating PIC code. It is given that flag_pic is on and
3083 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3086 legitimate_pic_operand_p (rtx x)
3088 if (pic_address_needs_scratch (x))
3090 if (sparc_tls_referenced_p (x))
3095 /* Return nonzero if ADDR is a valid memory address.
3096 STRICT specifies whether strict register checking applies. */
3099 sparc_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3101 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
3103 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3105 else if (GET_CODE (addr) == PLUS)
3107 rs1 = XEXP (addr, 0);
3108 rs2 = XEXP (addr, 1);
3110 /* Canonicalize. REG comes first, if there are no regs,
3111 LO_SUM comes first. */
3113 && GET_CODE (rs1) != SUBREG
3115 || GET_CODE (rs2) == SUBREG
3116 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3118 rs1 = XEXP (addr, 1);
3119 rs2 = XEXP (addr, 0);
3123 && rs1 == pic_offset_table_rtx
3125 && GET_CODE (rs2) != SUBREG
3126 && GET_CODE (rs2) != LO_SUM
3127 && GET_CODE (rs2) != MEM
3128 && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
3129 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3130 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3132 || GET_CODE (rs1) == SUBREG)
3133 && RTX_OK_FOR_OFFSET_P (rs2)))
3138 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3139 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3141 /* We prohibit REG + REG for TFmode when there are no quad move insns
3142 and we consequently need to split. We do this because REG+REG
3143 is not an offsettable address. If we get the situation in reload
3144 where source and destination of a movtf pattern are both MEMs with
3145 REG+REG address, then only one of them gets converted to an
3146 offsettable address. */
3148 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
3151 /* We prohibit REG + REG on ARCH32 if not optimizing for
3152 DFmode/DImode because then mem_min_alignment is likely to be zero
3153 after reload and the forced split would lack a matching splitter
3155 if (TARGET_ARCH32 && !optimize
3156 && (mode == DFmode || mode == DImode))
3159 else if (USE_AS_OFFSETABLE_LO10
3160 && GET_CODE (rs1) == LO_SUM
3162 && ! TARGET_CM_MEDMID
3163 && RTX_OK_FOR_OLO10_P (rs2))
3166 imm1 = XEXP (rs1, 1);
3167 rs1 = XEXP (rs1, 0);
3168 if (!CONSTANT_P (imm1)
3169 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
3173 else if (GET_CODE (addr) == LO_SUM)
3175 rs1 = XEXP (addr, 0);
3176 imm1 = XEXP (addr, 1);
3178 if (!CONSTANT_P (imm1)
3179 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
3182 /* We can't allow TFmode in 32-bit mode, because an offset greater
3183 than the alignment (8) may cause the LO_SUM to overflow. */
3184 if (mode == TFmode && TARGET_ARCH32)
3187 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3192 if (GET_CODE (rs1) == SUBREG)
3193 rs1 = SUBREG_REG (rs1);
3199 if (GET_CODE (rs2) == SUBREG)
3200 rs2 = SUBREG_REG (rs2);
3207 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3208 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3213 if ((REGNO (rs1) >= 32
3214 && REGNO (rs1) != FRAME_POINTER_REGNUM
3215 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3217 && (REGNO (rs2) >= 32
3218 && REGNO (rs2) != FRAME_POINTER_REGNUM
3219 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3225 /* Return the SYMBOL_REF for the tls_get_addr function. */
3227 static GTY(()) rtx sparc_tls_symbol = NULL_RTX;
3230 sparc_tls_get_addr (void)
3232 if (!sparc_tls_symbol)
3233 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3235 return sparc_tls_symbol;
3238 /* Return the Global Offset Table to be used in TLS mode. */
3241 sparc_tls_got (void)
3243 /* In PIC mode, this is just the PIC offset table. */
3246 crtl->uses_pic_offset_table = 1;
3247 return pic_offset_table_rtx;
3250 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
3251 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
3252 if (TARGET_SUN_TLS && TARGET_ARCH32)
3254 load_got_register ();
3255 return global_offset_table_rtx;
3258 /* In all other cases, we load a new pseudo with the GOT symbol. */
3259 return copy_to_reg (sparc_got ());
3262 /* Return true if X contains a thread-local symbol. */
3265 sparc_tls_referenced_p (rtx x)
3267 if (!TARGET_HAVE_TLS)
3270 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
3271 x = XEXP (XEXP (x, 0), 0);
3273 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x))
3276 /* That's all we handle in sparc_legitimize_tls_address for now. */
3280 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3281 this (thread-local) address. */
3284 sparc_legitimize_tls_address (rtx addr)
3286 rtx temp1, temp2, temp3, ret, o0, got, insn;
3288 gcc_assert (can_create_pseudo_p ());
3290 if (GET_CODE (addr) == SYMBOL_REF)
3291 switch (SYMBOL_REF_TLS_MODEL (addr))
3293 case TLS_MODEL_GLOBAL_DYNAMIC:
3295 temp1 = gen_reg_rtx (SImode);
3296 temp2 = gen_reg_rtx (SImode);
3297 ret = gen_reg_rtx (Pmode);
3298 o0 = gen_rtx_REG (Pmode, 8);
3299 got = sparc_tls_got ();
3300 emit_insn (gen_tgd_hi22 (temp1, addr));
3301 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3304 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3305 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3310 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3311 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3314 CALL_INSN_FUNCTION_USAGE (insn)
3315 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3316 CALL_INSN_FUNCTION_USAGE (insn));
3317 insn = get_insns ();
3319 emit_libcall_block (insn, ret, o0, addr);
3322 case TLS_MODEL_LOCAL_DYNAMIC:
3324 temp1 = gen_reg_rtx (SImode);
3325 temp2 = gen_reg_rtx (SImode);
3326 temp3 = gen_reg_rtx (Pmode);
3327 ret = gen_reg_rtx (Pmode);
3328 o0 = gen_rtx_REG (Pmode, 8);
3329 got = sparc_tls_got ();
3330 emit_insn (gen_tldm_hi22 (temp1));
3331 emit_insn (gen_tldm_lo10 (temp2, temp1));
3334 emit_insn (gen_tldm_add32 (o0, got, temp2));
3335 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3340 emit_insn (gen_tldm_add64 (o0, got, temp2));
3341 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3344 CALL_INSN_FUNCTION_USAGE (insn)
3345 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3346 CALL_INSN_FUNCTION_USAGE (insn));
3347 insn = get_insns ();
3349 emit_libcall_block (insn, temp3, o0,
3350 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3351 UNSPEC_TLSLD_BASE));
3352 temp1 = gen_reg_rtx (SImode);
3353 temp2 = gen_reg_rtx (SImode);
3354 emit_insn (gen_tldo_hix22 (temp1, addr));
3355 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3357 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3359 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3362 case TLS_MODEL_INITIAL_EXEC:
3363 temp1 = gen_reg_rtx (SImode);
3364 temp2 = gen_reg_rtx (SImode);
3365 temp3 = gen_reg_rtx (Pmode);
3366 got = sparc_tls_got ();
3367 emit_insn (gen_tie_hi22 (temp1, addr));
3368 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3370 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3372 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3375 ret = gen_reg_rtx (Pmode);
3377 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3380 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3384 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3387 case TLS_MODEL_LOCAL_EXEC:
3388 temp1 = gen_reg_rtx (Pmode);
3389 temp2 = gen_reg_rtx (Pmode);
3392 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3393 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3397 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3398 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3400 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3407 else if (GET_CODE (addr) == CONST)
3411 gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS);
3413 base = sparc_legitimize_tls_address (XEXP (XEXP (addr, 0), 0));
3414 offset = XEXP (XEXP (addr, 0), 1);
3416 base = force_operand (base, NULL_RTX);
3417 if (!(GET_CODE (offset) == CONST_INT && SMALL_INT (offset)))
3418 offset = force_reg (Pmode, offset);
3419 ret = gen_rtx_PLUS (Pmode, base, offset);
3423 gcc_unreachable (); /* for now ... */
3428 /* Legitimize PIC addresses. If the address is already position-independent,
3429 we return ORIG. Newly generated position-independent addresses go into a
3430 reg. This is REG if nonzero, otherwise we allocate register(s) as
3434 sparc_legitimize_pic_address (rtx orig, rtx reg)
3436 bool gotdata_op = false;
3438 if (GET_CODE (orig) == SYMBOL_REF
3439 /* See the comment in sparc_expand_move. */
3440 || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig)))
3442 rtx pic_ref, address;
3447 gcc_assert (! reload_in_progress && ! reload_completed);
3448 reg = gen_reg_rtx (Pmode);
3453 /* If not during reload, allocate another temp reg here for loading
3454 in the address, so that these instructions can be optimized
3456 rtx temp_reg = ((reload_in_progress || reload_completed)
3457 ? reg : gen_reg_rtx (Pmode));
3459 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3460 won't get confused into thinking that these two instructions
3461 are loading in the true address of the symbol. If in the
3462 future a PIC rtx exists, that should be used instead. */
3465 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3466 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3470 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3471 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3479 crtl->uses_pic_offset_table = 1;
3483 insn = emit_insn (gen_movdi_pic_gotdata_op (reg,
3484 pic_offset_table_rtx,
3487 insn = emit_insn (gen_movsi_pic_gotdata_op (reg,
3488 pic_offset_table_rtx,
3494 = gen_const_mem (Pmode,
3495 gen_rtx_PLUS (Pmode,
3496 pic_offset_table_rtx, address));
3497 insn = emit_move_insn (reg, pic_ref);
3500 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3502 set_unique_reg_note (insn, REG_EQUAL, orig);
3505 else if (GET_CODE (orig) == CONST)
3509 if (GET_CODE (XEXP (orig, 0)) == PLUS
3510 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3515 gcc_assert (! reload_in_progress && ! reload_completed);
3516 reg = gen_reg_rtx (Pmode);
3519 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3520 base = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
3521 offset = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
3522 base == reg ? NULL_RTX : reg);
3524 if (GET_CODE (offset) == CONST_INT)
3526 if (SMALL_INT (offset))
3527 return plus_constant (base, INTVAL (offset));
3528 else if (! reload_in_progress && ! reload_completed)
3529 offset = force_reg (Pmode, offset);
3531 /* If we reach here, then something is seriously wrong. */
3534 return gen_rtx_PLUS (Pmode, base, offset);
3536 else if (GET_CODE (orig) == LABEL_REF)
3537 /* ??? We ought to be checking that the register is live instead, in case
3538 it is eliminated. */
3539 crtl->uses_pic_offset_table = 1;
3544 /* Try machine-dependent ways of modifying an illegitimate address X
3545 to be legitimate. If we find one, return the new, valid address.
3547 OLDX is the address as it was before break_out_memory_refs was called.
3548 In some cases it is useful to look at this to decide what needs to be done.
3550 MODE is the mode of the operand pointed to by X.
3552 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
3555 sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3556 enum machine_mode mode)
3560 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3561 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3562 force_operand (XEXP (x, 0), NULL_RTX));
3563 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3564 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3565 force_operand (XEXP (x, 1), NULL_RTX));
3566 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3567 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3569 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3570 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3571 force_operand (XEXP (x, 1), NULL_RTX));
3573 if (x != orig_x && sparc_legitimate_address_p (mode, x, FALSE))
3576 if (sparc_tls_referenced_p (x))
3577 x = sparc_legitimize_tls_address (x);
3579 x = sparc_legitimize_pic_address (x, NULL_RTX);
3580 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3581 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3582 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3583 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3584 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3585 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3586 else if (GET_CODE (x) == SYMBOL_REF
3587 || GET_CODE (x) == CONST
3588 || GET_CODE (x) == LABEL_REF)
3589 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3594 /* Delegitimize an address that was legitimized by the above function. */
3597 sparc_delegitimize_address (rtx x)
3599 x = delegitimize_mem_from_attrs (x);
3601 if (GET_CODE (x) == LO_SUM
3602 && GET_CODE (XEXP (x, 1)) == UNSPEC
3603 && XINT (XEXP (x, 1), 1) == UNSPEC_TLSLE)
3605 x = XVECEXP (XEXP (x, 1), 0, 0);
3606 gcc_assert (GET_CODE (x) == SYMBOL_REF);
3609 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
3610 if (GET_CODE (x) == MINUS
3611 && REG_P (XEXP (x, 0))
3612 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
3613 && GET_CODE (XEXP (x, 1)) == LO_SUM
3614 && GET_CODE (XEXP (XEXP (x, 1), 1)) == UNSPEC
3615 && XINT (XEXP (XEXP (x, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL)
3617 x = XVECEXP (XEXP (XEXP (x, 1), 1), 0, 0);
3618 gcc_assert (GET_CODE (x) == LABEL_REF);
3624 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3625 replace the input X, or the original X if no replacement is called for.
3626 The output parameter *WIN is 1 if the calling macro should goto WIN,
3629 For SPARC, we wish to handle addresses by splitting them into
3630 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
3631 This cuts the number of extra insns by one.
3633 Do nothing when generating PIC code and the address is a symbolic
3634 operand or requires a scratch register. */
3637 sparc_legitimize_reload_address (rtx x, enum machine_mode mode,
3638 int opnum, int type,
3639 int ind_levels ATTRIBUTE_UNUSED, int *win)
3641 /* Decompose SImode constants into HIGH+LO_SUM. */
3643 && (mode != TFmode || TARGET_ARCH64)
3644 && GET_MODE (x) == SImode
3645 && GET_CODE (x) != LO_SUM
3646 && GET_CODE (x) != HIGH
3647 && sparc_cmodel <= CM_MEDLOW
3649 && (symbolic_operand (x, Pmode) || pic_address_needs_scratch (x))))
3651 x = gen_rtx_LO_SUM (GET_MODE (x), gen_rtx_HIGH (GET_MODE (x), x), x);
3652 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3653 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3654 opnum, (enum reload_type)type);
3659 /* We have to recognize what we have already generated above. */
3660 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == HIGH)
3662 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3663 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3664 opnum, (enum reload_type)type);
3673 /* Return true if ADDR (a legitimate address expression)
3674 has an effect that depends on the machine mode it is used for.
3680 is not equivalent to
3682 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
3684 because [%l7+a+1] is interpreted as the address of (a+1). */
3688 sparc_mode_dependent_address_p (const_rtx addr)
3690 if (flag_pic && GET_CODE (addr) == PLUS)
3692 rtx op0 = XEXP (addr, 0);
3693 rtx op1 = XEXP (addr, 1);
3694 if (op0 == pic_offset_table_rtx
3695 && SYMBOLIC_CONST (op1))
3702 #ifdef HAVE_GAS_HIDDEN
3703 # define USE_HIDDEN_LINKONCE 1
3705 # define USE_HIDDEN_LINKONCE 0
3709 get_pc_thunk_name (char name[32], unsigned int regno)
3711 const char *reg_name = reg_names[regno];
3713 /* Skip the leading '%' as that cannot be used in a
3717 if (USE_HIDDEN_LINKONCE)
3718 sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
3720 ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
3723 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
3726 gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2, rtx op3)
3728 int orig_flag_pic = flag_pic;
3731 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
3734 insn = gen_load_pcrel_symdi (op0, op1, op2, op3);
3736 insn = gen_load_pcrel_symsi (op0, op1, op2, op3);
3737 flag_pic = orig_flag_pic;
3742 /* Emit code to load the GOT register. */
3745 load_got_register (void)
3747 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
3748 if (!global_offset_table_rtx)
3749 global_offset_table_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
3751 if (TARGET_VXWORKS_RTP)
3752 emit_insn (gen_vxworks_load_got ());
3755 /* The GOT symbol is subject to a PC-relative relocation so we need a
3756 helper function to add the PC value and thus get the final value. */
3757 if (!got_helper_rtx)
3760 get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
3761 got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
3764 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx, sparc_got (),
3766 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM)));
3769 /* Need to emit this whether or not we obey regdecls,
3770 since setjmp/longjmp can cause life info to screw up.
3771 ??? In the case where we don't obey regdecls, this is not sufficient
3772 since we may not fall out the bottom. */
3773 emit_use (global_offset_table_rtx);
3776 /* Emit a call instruction with the pattern given by PAT. ADDR is the
3777 address of the call target. */
3780 sparc_emit_call_insn (rtx pat, rtx addr)
3784 insn = emit_call_insn (pat);
3786 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
3787 if (TARGET_VXWORKS_RTP
3789 && GET_CODE (addr) == SYMBOL_REF
3790 && (SYMBOL_REF_DECL (addr)
3791 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
3792 : !SYMBOL_REF_LOCAL_P (addr)))
3794 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3795 crtl->uses_pic_offset_table = 1;
3799 /* Return 1 if RTX is a MEM which is known to be aligned to at
3800 least a DESIRED byte boundary. */
3803 mem_min_alignment (rtx mem, int desired)
3805 rtx addr, base, offset;
3807 /* If it's not a MEM we can't accept it. */
3808 if (GET_CODE (mem) != MEM)
3812 if (!TARGET_UNALIGNED_DOUBLES
3813 && MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired)
3816 /* ??? The rest of the function predates MEM_ALIGN so
3817 there is probably a bit of redundancy. */
3818 addr = XEXP (mem, 0);
3819 base = offset = NULL_RTX;
3820 if (GET_CODE (addr) == PLUS)
3822 if (GET_CODE (XEXP (addr, 0)) == REG)
3824 base = XEXP (addr, 0);
3826 /* What we are saying here is that if the base
3827 REG is aligned properly, the compiler will make
3828 sure any REG based index upon it will be so
3830 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3831 offset = XEXP (addr, 1);
3833 offset = const0_rtx;
3836 else if (GET_CODE (addr) == REG)
3839 offset = const0_rtx;
3842 if (base != NULL_RTX)
3844 int regno = REGNO (base);
3846 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3848 /* Check if the compiler has recorded some information
3849 about the alignment of the base REG. If reload has
3850 completed, we already matched with proper alignments.
3851 If not running global_alloc, reload might give us
3852 unaligned pointer to local stack though. */
3854 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3855 || (optimize && reload_completed))
3856 && (INTVAL (offset) & (desired - 1)) == 0)
3861 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3865 else if (! TARGET_UNALIGNED_DOUBLES
3866 || CONSTANT_P (addr)
3867 || GET_CODE (addr) == LO_SUM)
3869 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3870 is true, in which case we can only assume that an access is aligned if
3871 it is to a constant address, or the address involves a LO_SUM. */
3875 /* An obviously unaligned address. */
3880 /* Vectors to keep interesting information about registers where it can easily
3881 be got. We used to use the actual mode value as the bit number, but there
3882 are more than 32 modes now. Instead we use two tables: one indexed by
3883 hard register number, and one indexed by mode. */
3885 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3886 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
3887 mapped into one sparc_mode_class mode. */
3889 enum sparc_mode_class {
3890 S_MODE, D_MODE, T_MODE, O_MODE,
3891 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3895 /* Modes for single-word and smaller quantities. */
3896 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3898 /* Modes for double-word and smaller quantities. */
3899 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3901 /* Modes for quad-word and smaller quantities. */
3902 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3904 /* Modes for 8-word and smaller quantities. */
3905 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3907 /* Modes for single-float quantities. We must allow any single word or
3908 smaller quantity. This is because the fix/float conversion instructions
3909 take integer inputs/outputs from the float registers. */
3910 #define SF_MODES (S_MODES)
3912 /* Modes for double-float and smaller quantities. */
3913 #define DF_MODES (D_MODES)
3915 /* Modes for quad-float and smaller quantities. */
3916 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
3918 /* Modes for quad-float pairs and smaller quantities. */
3919 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
3921 /* Modes for double-float only quantities. */
3922 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3924 /* Modes for quad-float and double-float only quantities. */
3925 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
3927 /* Modes for quad-float pairs and double-float only quantities. */
3928 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
3930 /* Modes for condition codes. */
3931 #define CC_MODES (1 << (int) CC_MODE)
3932 #define CCFP_MODES (1 << (int) CCFP_MODE)
3934 /* Value is 1 if register/mode pair is acceptable on sparc.
3935 The funny mixture of D and T modes is because integer operations
3936 do not specially operate on tetra quantities, so non-quad-aligned
3937 registers can hold quadword quantities (except %o4 and %i4 because
3938 they cross fixed registers). */
3940 /* This points to either the 32 bit or the 64 bit version. */
3941 const int *hard_regno_mode_classes;
3943 static const int hard_32bit_mode_classes[] = {
3944 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3945 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3946 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3947 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3949 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3950 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3951 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3952 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3954 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3955 and none can hold SFmode/SImode values. */
3956 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3957 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3958 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3959 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3962 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3968 static const int hard_64bit_mode_classes[] = {
3969 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3970 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3971 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3972 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3974 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3975 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3976 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3977 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3979 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3980 and none can hold SFmode/SImode values. */
3981 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3982 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3983 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3984 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3987 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3993 int sparc_mode_class [NUM_MACHINE_MODES];
3995 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3998 sparc_init_modes (void)
4002 for (i = 0; i < NUM_MACHINE_MODES; i++)
4004 switch (GET_MODE_CLASS (i))
4007 case MODE_PARTIAL_INT:
4008 case MODE_COMPLEX_INT:
4009 if (GET_MODE_SIZE (i) <= 4)
4010 sparc_mode_class[i] = 1 << (int) S_MODE;
4011 else if (GET_MODE_SIZE (i) == 8)
4012 sparc_mode_class[i] = 1 << (int) D_MODE;
4013 else if (GET_MODE_SIZE (i) == 16)
4014 sparc_mode_class[i] = 1 << (int) T_MODE;
4015 else if (GET_MODE_SIZE (i) == 32)
4016 sparc_mode_class[i] = 1 << (int) O_MODE;
4018 sparc_mode_class[i] = 0;
4020 case MODE_VECTOR_INT:
4021 if (GET_MODE_SIZE (i) <= 4)
4022 sparc_mode_class[i] = 1 << (int)SF_MODE;
4023 else if (GET_MODE_SIZE (i) == 8)
4024 sparc_mode_class[i] = 1 << (int)DF_MODE;
4027 case MODE_COMPLEX_FLOAT:
4028 if (GET_MODE_SIZE (i) <= 4)
4029 sparc_mode_class[i] = 1 << (int) SF_MODE;
4030 else if (GET_MODE_SIZE (i) == 8)
4031 sparc_mode_class[i] = 1 << (int) DF_MODE;
4032 else if (GET_MODE_SIZE (i) == 16)
4033 sparc_mode_class[i] = 1 << (int) TF_MODE;
4034 else if (GET_MODE_SIZE (i) == 32)
4035 sparc_mode_class[i] = 1 << (int) OF_MODE;
4037 sparc_mode_class[i] = 0;
4040 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4041 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4043 sparc_mode_class[i] = 1 << (int) CC_MODE;
4046 sparc_mode_class[i] = 0;
4052 hard_regno_mode_classes = hard_64bit_mode_classes;
4054 hard_regno_mode_classes = hard_32bit_mode_classes;
4056 /* Initialize the array used by REGNO_REG_CLASS. */
4057 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4059 if (i < 16 && TARGET_V8PLUS)
4060 sparc_regno_reg_class[i] = I64_REGS;
4061 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4062 sparc_regno_reg_class[i] = GENERAL_REGS;
4064 sparc_regno_reg_class[i] = FP_REGS;
4066 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4068 sparc_regno_reg_class[i] = FPCC_REGS;
4070 sparc_regno_reg_class[i] = NO_REGS;
4074 /* Compute the frame size required by the function. This function is called
4075 during the reload pass and also by sparc_expand_prologue. */
4078 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p)
4080 int outgoing_args_size = (crtl->outgoing_args_size
4081 + REG_PARM_STACK_SPACE (current_function_decl));
4082 int n_regs = 0; /* N_REGS is the number of 4-byte regs saved thus far. */
4087 for (i = 0; i < 8; i++)
4088 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4093 for (i = 0; i < 8; i += 2)
4094 if ((df_regs_ever_live_p (i) && ! call_used_regs[i])
4095 || (df_regs_ever_live_p (i+1) && ! call_used_regs[i+1]))
4099 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4100 if ((df_regs_ever_live_p (i) && ! call_used_regs[i])
4101 || (df_regs_ever_live_p (i+1) && ! call_used_regs[i+1]))
4104 /* Set up values for use in prologue and epilogue. */
4105 num_gfregs = n_regs;
4110 && crtl->outgoing_args_size == 0)
4111 actual_fsize = apparent_fsize = 0;
4114 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4115 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4116 apparent_fsize += n_regs * 4;
4117 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4120 /* Make sure nothing can clobber our register windows.
4121 If a SAVE must be done, or there is a stack-local variable,
4122 the register window area must be allocated. */
4123 if (! leaf_function_p || size > 0)
4124 actual_fsize += FIRST_PARM_OFFSET (current_function_decl);
4126 return SPARC_STACK_ALIGN (actual_fsize);
4129 /* Output any necessary .register pseudo-ops. */
4132 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4134 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4140 /* Check if %g[2367] were used without
4141 .register being printed for them already. */
4142 for (i = 2; i < 8; i++)
4144 if (df_regs_ever_live_p (i)
4145 && ! sparc_hard_reg_printed [i])
4147 sparc_hard_reg_printed [i] = 1;
4148 /* %g7 is used as TLS base register, use #ignore
4149 for it instead of #scratch. */
4150 fprintf (file, "\t.register\t%%g%d, #%s\n", i,
4151 i == 7 ? "ignore" : "scratch");
4158 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
4160 #if PROBE_INTERVAL > 4096
4161 #error Cannot use indexed addressing mode for stack probing
4164 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
4165 inclusive. These are offsets from the current stack pointer.
4167 Note that we don't use the REG+REG addressing mode for the probes because
4168 of the stack bias in 64-bit mode. And it doesn't really buy us anything
4169 so the advantages of having a single code win here. */
4172 sparc_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
4174 rtx g1 = gen_rtx_REG (Pmode, 1);
4176 /* See if we have a constant small number of probes to generate. If so,
4177 that's the easy case. */
4178 if (size <= PROBE_INTERVAL)
4180 emit_move_insn (g1, GEN_INT (first));
4181 emit_insn (gen_rtx_SET (VOIDmode, g1,
4182 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4183 emit_stack_probe (plus_constant (g1, -size));
4186 /* The run-time loop is made up of 10 insns in the generic case while the
4187 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
4188 else if (size <= 5 * PROBE_INTERVAL)
4192 emit_move_insn (g1, GEN_INT (first + PROBE_INTERVAL));
4193 emit_insn (gen_rtx_SET (VOIDmode, g1,
4194 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4195 emit_stack_probe (g1);
4197 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
4198 it exceeds SIZE. If only two probes are needed, this will not
4199 generate any code. Then probe at FIRST + SIZE. */
4200 for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
4202 emit_insn (gen_rtx_SET (VOIDmode, g1,
4203 plus_constant (g1, -PROBE_INTERVAL)));
4204 emit_stack_probe (g1);
4207 emit_stack_probe (plus_constant (g1, (i - PROBE_INTERVAL) - size));
4210 /* Otherwise, do the same as above, but in a loop. Note that we must be
4211 extra careful with variables wrapping around because we might be at
4212 the very top (or the very bottom) of the address space and we have
4213 to be able to handle this case properly; in particular, we use an
4214 equality test for the loop condition. */
4217 HOST_WIDE_INT rounded_size;
4218 rtx g4 = gen_rtx_REG (Pmode, 4);
4220 emit_move_insn (g1, GEN_INT (first));
4223 /* Step 1: round SIZE to the previous multiple of the interval. */
4225 rounded_size = size & -PROBE_INTERVAL;
4226 emit_move_insn (g4, GEN_INT (rounded_size));
4229 /* Step 2: compute initial and final value of the loop counter. */
4231 /* TEST_ADDR = SP + FIRST. */
4232 emit_insn (gen_rtx_SET (VOIDmode, g1,
4233 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4235 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
4236 emit_insn (gen_rtx_SET (VOIDmode, g4, gen_rtx_MINUS (Pmode, g1, g4)));
4241 while (TEST_ADDR != LAST_ADDR)
4243 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
4247 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
4248 until it is equal to ROUNDED_SIZE. */
4251 emit_insn (gen_probe_stack_rangedi (g1, g1, g4));
4253 emit_insn (gen_probe_stack_rangesi (g1, g1, g4));
4256 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
4257 that SIZE is equal to ROUNDED_SIZE. */
4259 if (size != rounded_size)
4260 emit_stack_probe (plus_constant (g4, rounded_size - size));
4263 /* Make sure nothing is scheduled before we are done. */
4264 emit_insn (gen_blockage ());
4267 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
4268 absolute addresses. */
4271 output_probe_stack_range (rtx reg1, rtx reg2)
4273 static int labelno = 0;
4274 char loop_lab[32], end_lab[32];
4277 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
4278 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
4280 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
4282 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
4285 output_asm_insn ("cmp\t%0, %1", xops);
4287 fputs ("\tbe,pn\t%xcc,", asm_out_file);
4289 fputs ("\tbe\t", asm_out_file);
4290 assemble_name_raw (asm_out_file, end_lab);
4291 fputc ('\n', asm_out_file);
4293 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
4294 xops[1] = GEN_INT (-PROBE_INTERVAL);
4295 output_asm_insn (" add\t%0, %1, %0", xops);
4297 /* Probe at TEST_ADDR and branch. */
4299 fputs ("\tba,pt\t%xcc,", asm_out_file);
4301 fputs ("\tba\t", asm_out_file);
4302 assemble_name_raw (asm_out_file, loop_lab);
4303 fputc ('\n', asm_out_file);
4304 xops[1] = GEN_INT (SPARC_STACK_BIAS);
4305 output_asm_insn (" st\t%%g0, [%0+%1]", xops);
4307 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
4312 /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
4313 as needed. LOW should be double-word aligned for 32-bit registers.
4314 Return the new OFFSET. */
4317 #define SORR_RESTORE 1
4320 save_or_restore_regs (int low, int high, rtx base, int offset, int action)
4325 if (TARGET_ARCH64 && high <= 32)
4327 for (i = low; i < high; i++)
4329 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4331 mem = gen_frame_mem (DImode, plus_constant (base, offset));
4332 if (action == SORR_SAVE)
4334 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
4335 RTX_FRAME_RELATED_P (insn) = 1;
4337 else /* action == SORR_RESTORE */
4338 emit_move_insn (gen_rtx_REG (DImode, i), mem);
4345 for (i = low; i < high; i += 2)
4347 bool reg0 = df_regs_ever_live_p (i) && ! call_used_regs[i];
4348 bool reg1 = df_regs_ever_live_p (i+1) && ! call_used_regs[i+1];
4349 enum machine_mode mode;
4354 mode = i < 32 ? DImode : DFmode;
4359 mode = i < 32 ? SImode : SFmode;
4364 mode = i < 32 ? SImode : SFmode;
4371 mem = gen_frame_mem (mode, plus_constant (base, offset));
4372 if (action == SORR_SAVE)
4374 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4375 RTX_FRAME_RELATED_P (insn) = 1;
4377 else /* action == SORR_RESTORE */
4378 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4380 /* Always preserve double-word alignment. */
4381 offset = (offset + 7) & -8;
4388 /* Emit code to save call-saved registers. */
4391 emit_save_or_restore_regs (int action)
4393 HOST_WIDE_INT offset;
4396 offset = frame_base_offset - apparent_fsize;
4398 if (offset < -4096 || offset + num_gfregs * 4 > 4095)
4400 /* ??? This might be optimized a little as %g1 might already have a
4401 value close enough that a single add insn will do. */
4402 /* ??? Although, all of this is probably only a temporary fix
4403 because if %g1 can hold a function result, then
4404 sparc_expand_epilogue will lose (the result will be
4406 base = gen_rtx_REG (Pmode, 1);
4407 emit_move_insn (base, GEN_INT (offset));
4408 emit_insn (gen_rtx_SET (VOIDmode,
4410 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4414 base = frame_base_reg;
4416 offset = save_or_restore_regs (0, 8, base, offset, action);
4417 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, action);
4420 /* Generate a save_register_window insn. */
4423 gen_save_register_window (rtx increment)
4426 return gen_save_register_windowdi (increment);
4428 return gen_save_register_windowsi (increment);
4431 /* Generate an increment for the stack pointer. */
4434 gen_stack_pointer_inc (rtx increment)
4436 return gen_rtx_SET (VOIDmode,
4438 gen_rtx_PLUS (Pmode,
4443 /* Generate a decrement for the stack pointer. */
4446 gen_stack_pointer_dec (rtx decrement)
4448 return gen_rtx_SET (VOIDmode,
4450 gen_rtx_MINUS (Pmode,
4455 /* Expand the function prologue. The prologue is responsible for reserving
4456 storage for the frame, saving the call-saved registers and loading the
4457 GOT register if needed. */
4460 sparc_expand_prologue (void)
4465 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4466 on the final value of the flag means deferring the prologue/epilogue
4467 expansion until just before the second scheduling pass, which is too
4468 late to emit multiple epilogues or return insns.
4470 Of course we are making the assumption that the value of the flag
4471 will not change between now and its final value. Of the three parts
4472 of the formula, only the last one can reasonably vary. Let's take a
4473 closer look, after assuming that the first two ones are set to true
4474 (otherwise the last value is effectively silenced).
4476 If only_leaf_regs_used returns false, the global predicate will also
4477 be false so the actual frame size calculated below will be positive.
4478 As a consequence, the save_register_window insn will be emitted in
4479 the instruction stream; now this insn explicitly references %fp
4480 which is not a leaf register so only_leaf_regs_used will always
4481 return false subsequently.
4483 If only_leaf_regs_used returns true, we hope that the subsequent
4484 optimization passes won't cause non-leaf registers to pop up. For
4485 example, the regrename pass has special provisions to not rename to
4486 non-leaf registers in a leaf function. */
4487 sparc_leaf_function_p
4488 = optimize > 0 && leaf_function_p () && only_leaf_regs_used ();
4490 /* Need to use actual_fsize, since we are also allocating
4491 space for our callee (and our own register save area). */
4493 = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
4495 /* Advertise that the data calculated just above are now valid. */
4496 sparc_prologue_data_valid_p = true;
4498 if (flag_stack_usage)
4499 current_function_static_stack_size = actual_fsize;
4501 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && actual_fsize)
4502 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, actual_fsize);
4504 if (sparc_leaf_function_p)
4506 frame_base_reg = stack_pointer_rtx;
4507 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4511 frame_base_reg = hard_frame_pointer_rtx;
4512 frame_base_offset = SPARC_STACK_BIAS;
4515 if (actual_fsize == 0)
4517 else if (sparc_leaf_function_p)
4519 if (actual_fsize <= 4096)
4520 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-actual_fsize)));
4521 else if (actual_fsize <= 8192)
4523 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4524 /* %sp is still the CFA register. */
4525 RTX_FRAME_RELATED_P (insn) = 1;
4527 = emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize)));
4531 rtx reg = gen_rtx_REG (Pmode, 1);
4532 emit_move_insn (reg, GEN_INT (-actual_fsize));
4533 insn = emit_insn (gen_stack_pointer_inc (reg));
4534 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4535 gen_stack_pointer_inc (GEN_INT (-actual_fsize)));
4538 RTX_FRAME_RELATED_P (insn) = 1;
4542 if (actual_fsize <= 4096)
4543 insn = emit_insn (gen_save_register_window (GEN_INT (-actual_fsize)));
4544 else if (actual_fsize <= 8192)
4546 insn = emit_insn (gen_save_register_window (GEN_INT (-4096)));
4547 /* %sp is not the CFA register anymore. */
4548 emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize)));
4552 rtx reg = gen_rtx_REG (Pmode, 1);
4553 emit_move_insn (reg, GEN_INT (-actual_fsize));
4554 insn = emit_insn (gen_save_register_window (reg));
4557 RTX_FRAME_RELATED_P (insn) = 1;
4558 for (i=0; i < XVECLEN (PATTERN (insn), 0); i++)
4559 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, i)) = 1;
4563 emit_save_or_restore_regs (SORR_SAVE);
4565 /* Load the GOT register if needed. */
4566 if (crtl->uses_pic_offset_table)
4567 load_got_register ();
4570 /* This function generates the assembly code for function entry, which boils
4571 down to emitting the necessary .register directives. */
4574 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4576 /* Check that the assumption we made in sparc_expand_prologue is valid. */
4577 gcc_assert (sparc_leaf_function_p == current_function_uses_only_leaf_regs);
4579 sparc_output_scratch_registers (file);
4582 /* Expand the function epilogue, either normal or part of a sibcall.
4583 We emit all the instructions except the return or the call. */
4586 sparc_expand_epilogue (void)
4589 emit_save_or_restore_regs (SORR_RESTORE);
4591 if (actual_fsize == 0)
4593 else if (sparc_leaf_function_p)
4595 if (actual_fsize <= 4096)
4596 emit_insn (gen_stack_pointer_dec (GEN_INT (- actual_fsize)));
4597 else if (actual_fsize <= 8192)
4599 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4600 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - actual_fsize)));
4604 rtx reg = gen_rtx_REG (Pmode, 1);
4605 emit_move_insn (reg, GEN_INT (-actual_fsize));
4606 emit_insn (gen_stack_pointer_dec (reg));
4611 /* Return true if it is appropriate to emit `return' instructions in the
4612 body of a function. */
4615 sparc_can_use_return_insn_p (void)
4617 return sparc_prologue_data_valid_p
4618 && (actual_fsize == 0 || !sparc_leaf_function_p);
4621 /* This function generates the assembly code for function exit. */
4624 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4626 /* If the last two instructions of a function are "call foo; dslot;"
4627 the return address might point to the first instruction in the next
4628 function and we have to output a dummy nop for the sake of sane
4629 backtraces in such cases. This is pointless for sibling calls since
4630 the return address is explicitly adjusted. */
4632 rtx insn, last_real_insn;
4634 insn = get_last_insn ();
4636 last_real_insn = prev_real_insn (insn);
4638 && GET_CODE (last_real_insn) == INSN
4639 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4640 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4643 && CALL_P (last_real_insn)
4644 && !SIBLING_CALL_P (last_real_insn))
4645 fputs("\tnop\n", file);
4647 sparc_output_deferred_case_vectors ();
4650 /* Output a 'restore' instruction. */
4653 output_restore (rtx pat)
4659 fputs ("\t restore\n", asm_out_file);
4663 gcc_assert (GET_CODE (pat) == SET);
4665 operands[0] = SET_DEST (pat);
4666 pat = SET_SRC (pat);
4668 switch (GET_CODE (pat))
4671 operands[1] = XEXP (pat, 0);
4672 operands[2] = XEXP (pat, 1);
4673 output_asm_insn (" restore %r1, %2, %Y0", operands);
4676 operands[1] = XEXP (pat, 0);
4677 operands[2] = XEXP (pat, 1);
4678 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4681 operands[1] = XEXP (pat, 0);
4682 gcc_assert (XEXP (pat, 1) == const1_rtx);
4683 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4687 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4692 /* Output a return. */
4695 output_return (rtx insn)
4697 if (sparc_leaf_function_p)
4699 /* This is a leaf function so we don't have to bother restoring the
4700 register window, which frees us from dealing with the convoluted
4701 semantics of restore/return. We simply output the jump to the
4702 return address and the insn in the delay slot (if any). */
4704 gcc_assert (! crtl->calls_eh_return);
4706 return "jmp\t%%o7+%)%#";
4710 /* This is a regular function so we have to restore the register window.
4711 We may have a pending insn for the delay slot, which will be either
4712 combined with the 'restore' instruction or put in the delay slot of
4713 the 'return' instruction. */
4715 if (crtl->calls_eh_return)
4717 /* If the function uses __builtin_eh_return, the eh_return
4718 machinery occupies the delay slot. */
4719 gcc_assert (! final_sequence);
4721 if (! flag_delayed_branch)
4722 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file);
4725 fputs ("\treturn\t%i7+8\n", asm_out_file);
4727 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file);
4729 if (flag_delayed_branch)
4730 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
4732 fputs ("\t nop\n", asm_out_file);
4734 else if (final_sequence)
4738 delay = NEXT_INSN (insn);
4741 pat = PATTERN (delay);
4743 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
4745 epilogue_renumber (&pat, 0);
4746 return "return\t%%i7+%)%#";
4750 output_asm_insn ("jmp\t%%i7+%)", NULL);
4751 output_restore (pat);
4752 PATTERN (delay) = gen_blockage ();
4753 INSN_CODE (delay) = -1;
4758 /* The delay slot is empty. */
4760 return "return\t%%i7+%)\n\t nop";
4761 else if (flag_delayed_branch)
4762 return "jmp\t%%i7+%)\n\t restore";
4764 return "restore\n\tjmp\t%%o7+%)\n\t nop";
4771 /* Output a sibling call. */
4774 output_sibcall (rtx insn, rtx call_operand)
4778 gcc_assert (flag_delayed_branch);
4780 operands[0] = call_operand;
4782 if (sparc_leaf_function_p)
4784 /* This is a leaf function so we don't have to bother restoring the
4785 register window. We simply output the jump to the function and
4786 the insn in the delay slot (if any). */
4788 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence));
4791 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
4794 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4795 it into branch if possible. */
4796 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
4801 /* This is a regular function so we have to restore the register window.
4802 We may have a pending insn for the delay slot, which will be combined
4803 with the 'restore' instruction. */
4805 output_asm_insn ("call\t%a0, 0", operands);
4809 rtx delay = NEXT_INSN (insn);
4812 output_restore (PATTERN (delay));
4814 PATTERN (delay) = gen_blockage ();
4815 INSN_CODE (delay) = -1;
4818 output_restore (NULL_RTX);
4824 /* Functions for handling argument passing.
4826 For 32-bit, the first 6 args are normally in registers and the rest are
4827 pushed. Any arg that starts within the first 6 words is at least
4828 partially passed in a register unless its data type forbids.
4830 For 64-bit, the argument registers are laid out as an array of 16 elements
4831 and arguments are added sequentially. The first 6 int args and up to the
4832 first 16 fp args (depending on size) are passed in regs.
4834 Slot Stack Integral Float Float in structure Double Long Double
4835 ---- ----- -------- ----- ------------------ ------ -----------
4836 15 [SP+248] %f31 %f30,%f31 %d30
4837 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4838 13 [SP+232] %f27 %f26,%f27 %d26
4839 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4840 11 [SP+216] %f23 %f22,%f23 %d22
4841 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4842 9 [SP+200] %f19 %f18,%f19 %d18
4843 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4844 7 [SP+184] %f15 %f14,%f15 %d14
4845 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4846 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4847 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4848 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4849 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4850 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4851 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4853 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4855 Integral arguments are always passed as 64-bit quantities appropriately
4858 Passing of floating point values is handled as follows.
4859 If a prototype is in scope:
4860 If the value is in a named argument (i.e. not a stdarg function or a
4861 value not part of the `...') then the value is passed in the appropriate
4863 If the value is part of the `...' and is passed in one of the first 6
4864 slots then the value is passed in the appropriate int reg.
4865 If the value is part of the `...' and is not passed in one of the first 6
4866 slots then the value is passed in memory.
4867 If a prototype is not in scope:
4868 If the value is one of the first 6 arguments the value is passed in the
4869 appropriate integer reg and the appropriate fp reg.
4870 If the value is not one of the first 6 arguments the value is passed in
4871 the appropriate fp reg and in memory.
4874 Summary of the calling conventions implemented by GCC on the SPARC:
4877 size argument return value
4879 small integer <4 int. reg. int. reg.
4880 word 4 int. reg. int. reg.
4881 double word 8 int. reg. int. reg.
4883 _Complex small integer <8 int. reg. int. reg.
4884 _Complex word 8 int. reg. int. reg.
4885 _Complex double word 16 memory int. reg.
4887 vector integer <=8 int. reg. FP reg.
4888 vector integer >8 memory memory
4890 float 4 int. reg. FP reg.
4891 double 8 int. reg. FP reg.
4892 long double 16 memory memory
4894 _Complex float 8 memory FP reg.
4895 _Complex double 16 memory FP reg.
4896 _Complex long double 32 memory FP reg.
4898 vector float any memory memory
4900 aggregate any memory memory
4905 size argument return value
4907 small integer <8 int. reg. int. reg.
4908 word 8 int. reg. int. reg.
4909 double word 16 int. reg. int. reg.
4911 _Complex small integer <16 int. reg. int. reg.
4912 _Complex word 16 int. reg. int. reg.
4913 _Complex double word 32 memory int. reg.
4915 vector integer <=16 FP reg. FP reg.
4916 vector integer 16<s<=32 memory FP reg.
4917 vector integer >32 memory memory
4919 float 4 FP reg. FP reg.
4920 double 8 FP reg. FP reg.
4921 long double 16 FP reg. FP reg.
4923 _Complex float 8 FP reg. FP reg.
4924 _Complex double 16 FP reg. FP reg.
4925 _Complex long double 32 memory FP reg.
4927 vector float <=16 FP reg. FP reg.
4928 vector float 16<s<=32 memory FP reg.
4929 vector float >32 memory memory
4931 aggregate <=16 reg. reg.
4932 aggregate 16<s<=32 memory reg.
4933 aggregate >32 memory memory
4937 Note #1: complex floating-point types follow the extended SPARC ABIs as
4938 implemented by the Sun compiler.
4940 Note #2: integral vector types follow the scalar floating-point types
4941 conventions to match what is implemented by the Sun VIS SDK.
4943 Note #3: floating-point vector types follow the aggregate types
4947 /* Maximum number of int regs for args. */
4948 #define SPARC_INT_ARG_MAX 6
4949 /* Maximum number of fp regs for args. */
4950 #define SPARC_FP_ARG_MAX 16
4952 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4954 /* Handle the INIT_CUMULATIVE_ARGS macro.
4955 Initialize a variable CUM of type CUMULATIVE_ARGS
4956 for a call to a function whose data type is FNTYPE.
4957 For a library call, FNTYPE is 0. */
4960 init_cumulative_args (struct sparc_args *cum, tree fntype,
4961 rtx libname ATTRIBUTE_UNUSED,
4962 tree fndecl ATTRIBUTE_UNUSED)
4965 cum->prototype_p = fntype && prototype_p (fntype);
4966 cum->libcall_p = fntype == 0;
4969 /* Handle promotion of pointer and integer arguments. */
4971 static enum machine_mode
4972 sparc_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
4973 enum machine_mode mode,
4974 int *punsignedp ATTRIBUTE_UNUSED,
4975 const_tree fntype ATTRIBUTE_UNUSED,
4976 int for_return ATTRIBUTE_UNUSED)
4978 if (POINTER_TYPE_P (type))
4980 *punsignedp = POINTERS_EXTEND_UNSIGNED;
4984 /* Integral arguments are passed as full words, as per the ABI. */
4985 if (GET_MODE_CLASS (mode) == MODE_INT
4986 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
4992 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
4995 sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4997 return TARGET_ARCH64 ? true : false;
5000 /* Scan the record type TYPE and return the following predicates:
5001 - INTREGS_P: the record contains at least one field or sub-field
5002 that is eligible for promotion in integer registers.
5003 - FP_REGS_P: the record contains at least one field or sub-field
5004 that is eligible for promotion in floating-point registers.
5005 - PACKED_P: the record contains at least one field that is packed.
5007 Sub-fields are not taken into account for the PACKED_P predicate. */
5010 scan_record_type (const_tree type, int *intregs_p, int *fpregs_p,
5015 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5017 if (TREE_CODE (field) == FIELD_DECL)
5019 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5020 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
5021 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5022 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5028 if (packed_p && DECL_PACKED (field))
5034 /* Compute the slot number to pass an argument in.
5035 Return the slot number or -1 if passing on the stack.
5037 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5038 the preceding args and about the function being called.
5039 MODE is the argument's machine mode.
5040 TYPE is the data type of the argument (as a tree).
5041 This is null for libcalls where that information may
5043 NAMED is nonzero if this argument is a named parameter
5044 (otherwise it is an extra parameter matching an ellipsis).
5045 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5046 *PREGNO records the register number to use if scalar type.
5047 *PPADDING records the amount of padding needed in words. */
5050 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
5051 const_tree type, bool named, bool incoming_p,
5052 int *pregno, int *ppadding)
5054 int regbase = (incoming_p
5055 ? SPARC_INCOMING_INT_ARG_FIRST
5056 : SPARC_OUTGOING_INT_ARG_FIRST);
5057 int slotno = cum->words;
5058 enum mode_class mclass;
5063 if (type && TREE_ADDRESSABLE (type))
5069 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5072 /* For SPARC64, objects requiring 16-byte alignment get it. */
5074 && (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128
5075 && (slotno & 1) != 0)
5076 slotno++, *ppadding = 1;
5078 mclass = GET_MODE_CLASS (mode);
5079 if (type && TREE_CODE (type) == VECTOR_TYPE)
5081 /* Vector types deserve special treatment because they are
5082 polymorphic wrt their mode, depending upon whether VIS
5083 instructions are enabled. */
5084 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
5086 /* The SPARC port defines no floating-point vector modes. */
5087 gcc_assert (mode == BLKmode);
5091 /* Integral vector types should either have a vector
5092 mode or an integral mode, because we are guaranteed
5093 by pass_by_reference that their size is not greater
5094 than 16 bytes and TImode is 16-byte wide. */
5095 gcc_assert (mode != BLKmode);
5097 /* Vector integers are handled like floats according to
5099 mclass = MODE_FLOAT;
5106 case MODE_COMPLEX_FLOAT:
5107 case MODE_VECTOR_INT:
5108 if (TARGET_ARCH64 && TARGET_FPU && named)
5110 if (slotno >= SPARC_FP_ARG_MAX)
5112 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5113 /* Arguments filling only one single FP register are
5114 right-justified in the outer double FP register. */
5115 if (GET_MODE_SIZE (mode) <= 4)
5122 case MODE_COMPLEX_INT:
5123 if (slotno >= SPARC_INT_ARG_MAX)
5125 regno = regbase + slotno;
5129 if (mode == VOIDmode)
5130 /* MODE is VOIDmode when generating the actual call. */
5133 gcc_assert (mode == BLKmode);
5137 || (TREE_CODE (type) != VECTOR_TYPE
5138 && TREE_CODE (type) != RECORD_TYPE))
5140 if (slotno >= SPARC_INT_ARG_MAX)
5142 regno = regbase + slotno;
5144 else /* TARGET_ARCH64 && type */
5146 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5148 /* First see what kinds of registers we would need. */
5149 if (TREE_CODE (type) == VECTOR_TYPE)
5152 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5154 /* The ABI obviously doesn't specify how packed structures
5155 are passed. These are defined to be passed in int regs
5156 if possible, otherwise memory. */
5157 if (packed_p || !named)
5158 fpregs_p = 0, intregs_p = 1;
5160 /* If all arg slots are filled, then must pass on stack. */
5161 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5164 /* If there are only int args and all int arg slots are filled,
5165 then must pass on stack. */
5166 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5169 /* Note that even if all int arg slots are filled, fp members may
5170 still be passed in regs if such regs are available.
5171 *PREGNO isn't set because there may be more than one, it's up
5172 to the caller to compute them. */
5185 /* Handle recursive register counting for structure field layout. */
5187 struct function_arg_record_value_parms
5189 rtx ret; /* return expression being built. */
5190 int slotno; /* slot number of the argument. */
5191 int named; /* whether the argument is named. */
5192 int regbase; /* regno of the base register. */
5193 int stack; /* 1 if part of the argument is on the stack. */
5194 int intoffset; /* offset of the first pending integer field. */
5195 unsigned int nregs; /* number of words passed in registers. */
5198 static void function_arg_record_value_3
5199 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5200 static void function_arg_record_value_2
5201 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5202 static void function_arg_record_value_1
5203 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5204 static rtx function_arg_record_value (const_tree, enum machine_mode, int, int, int);
5205 static rtx function_arg_union_value (int, enum machine_mode, int, int);
5207 /* A subroutine of function_arg_record_value. Traverse the structure
5208 recursively and determine how many registers will be required. */
5211 function_arg_record_value_1 (const_tree type, HOST_WIDE_INT startbitpos,
5212 struct function_arg_record_value_parms *parms,
5217 /* We need to compute how many registers are needed so we can
5218 allocate the PARALLEL but before we can do that we need to know
5219 whether there are any packed fields. The ABI obviously doesn't
5220 specify how structures are passed in this case, so they are
5221 defined to be passed in int regs if possible, otherwise memory,
5222 regardless of whether there are fp values present. */
5225 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5227 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5234 /* Compute how many registers we need. */
5235 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5237 if (TREE_CODE (field) == FIELD_DECL)
5239 HOST_WIDE_INT bitpos = startbitpos;
5241 if (DECL_SIZE (field) != 0)
5243 if (integer_zerop (DECL_SIZE (field)))
5246 if (host_integerp (bit_position (field), 1))
5247 bitpos += int_bit_position (field);
5250 /* ??? FIXME: else assume zero offset. */
5252 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5253 function_arg_record_value_1 (TREE_TYPE (field),
5257 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5258 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5263 if (parms->intoffset != -1)
5265 unsigned int startbit, endbit;
5266 int intslots, this_slotno;
5268 startbit = parms->intoffset & -BITS_PER_WORD;
5269 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5271 intslots = (endbit - startbit) / BITS_PER_WORD;
5272 this_slotno = parms->slotno + parms->intoffset
5275 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5277 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5278 /* We need to pass this field on the stack. */
5282 parms->nregs += intslots;
5283 parms->intoffset = -1;
5286 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5287 If it wasn't true we wouldn't be here. */
5288 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
5289 && DECL_MODE (field) == BLKmode)
5290 parms->nregs += TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
5291 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5298 if (parms->intoffset == -1)
5299 parms->intoffset = bitpos;
5305 /* A subroutine of function_arg_record_value. Assign the bits of the
5306 structure between parms->intoffset and bitpos to integer registers. */
5309 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5310 struct function_arg_record_value_parms *parms)
5312 enum machine_mode mode;
5314 unsigned int startbit, endbit;
5315 int this_slotno, intslots, intoffset;
5318 if (parms->intoffset == -1)
5321 intoffset = parms->intoffset;
5322 parms->intoffset = -1;
5324 startbit = intoffset & -BITS_PER_WORD;
5325 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5326 intslots = (endbit - startbit) / BITS_PER_WORD;
5327 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5329 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5333 /* If this is the trailing part of a word, only load that much into
5334 the register. Otherwise load the whole register. Note that in
5335 the latter case we may pick up unwanted bits. It's not a problem
5336 at the moment but may wish to revisit. */
5338 if (intoffset % BITS_PER_WORD != 0)
5339 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5344 intoffset /= BITS_PER_UNIT;
5347 regno = parms->regbase + this_slotno;
5348 reg = gen_rtx_REG (mode, regno);
5349 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5350 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5353 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5358 while (intslots > 0);
5361 /* A subroutine of function_arg_record_value. Traverse the structure
5362 recursively and assign bits to floating point registers. Track which
5363 bits in between need integer registers; invoke function_arg_record_value_3
5364 to make that happen. */
5367 function_arg_record_value_2 (const_tree type, HOST_WIDE_INT startbitpos,
5368 struct function_arg_record_value_parms *parms,
5374 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5376 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5383 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5385 if (TREE_CODE (field) == FIELD_DECL)
5387 HOST_WIDE_INT bitpos = startbitpos;
5389 if (DECL_SIZE (field) != 0)
5391 if (integer_zerop (DECL_SIZE (field)))
5394 if (host_integerp (bit_position (field), 1))
5395 bitpos += int_bit_position (field);
5398 /* ??? FIXME: else assume zero offset. */
5400 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5401 function_arg_record_value_2 (TREE_TYPE (field),
5405 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5406 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5411 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5412 int regno, nregs, pos;
5413 enum machine_mode mode = DECL_MODE (field);
5416 function_arg_record_value_3 (bitpos, parms);
5418 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
5421 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
5422 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
5424 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5426 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
5432 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
5433 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
5435 reg = gen_rtx_REG (mode, regno);
5436 pos = bitpos / BITS_PER_UNIT;
5437 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5438 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
5442 regno += GET_MODE_SIZE (mode) / 4;
5443 reg = gen_rtx_REG (mode, regno);
5444 pos += GET_MODE_SIZE (mode);
5445 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5446 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
5452 if (parms->intoffset == -1)
5453 parms->intoffset = bitpos;
5459 /* Used by function_arg and sparc_function_value_1 to implement the complex
5460 conventions of the 64-bit ABI for passing and returning structures.
5461 Return an expression valid as a return value for the FUNCTION_ARG
5462 and TARGET_FUNCTION_VALUE.
5464 TYPE is the data type of the argument (as a tree).
5465 This is null for libcalls where that information may
5467 MODE is the argument's machine mode.
5468 SLOTNO is the index number of the argument's slot in the parameter array.
5469 NAMED is nonzero if this argument is a named parameter
5470 (otherwise it is an extra parameter matching an ellipsis).
5471 REGBASE is the regno of the base register for the parameter array. */
5474 function_arg_record_value (const_tree type, enum machine_mode mode,
5475 int slotno, int named, int regbase)
5477 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5478 struct function_arg_record_value_parms parms;
5481 parms.ret = NULL_RTX;
5482 parms.slotno = slotno;
5483 parms.named = named;
5484 parms.regbase = regbase;
5487 /* Compute how many registers we need. */
5489 parms.intoffset = 0;
5490 function_arg_record_value_1 (type, 0, &parms, false);
5492 /* Take into account pending integer fields. */
5493 if (parms.intoffset != -1)
5495 unsigned int startbit, endbit;
5496 int intslots, this_slotno;
5498 startbit = parms.intoffset & -BITS_PER_WORD;
5499 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5500 intslots = (endbit - startbit) / BITS_PER_WORD;
5501 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5503 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5505 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5506 /* We need to pass this field on the stack. */
5510 parms.nregs += intslots;
5512 nregs = parms.nregs;
5514 /* Allocate the vector and handle some annoying special cases. */
5517 /* ??? Empty structure has no value? Duh? */
5520 /* Though there's nothing really to store, return a word register
5521 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5522 leads to breakage due to the fact that there are zero bytes to
5524 return gen_rtx_REG (mode, regbase);
5528 /* ??? C++ has structures with no fields, and yet a size. Give up
5529 for now and pass everything back in integer registers. */
5530 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5532 if (nregs + slotno > SPARC_INT_ARG_MAX)
5533 nregs = SPARC_INT_ARG_MAX - slotno;
5535 gcc_assert (nregs != 0);
5537 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5539 /* If at least one field must be passed on the stack, generate
5540 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5541 also be passed on the stack. We can't do much better because the
5542 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
5543 of structures for which the fields passed exclusively in registers
5544 are not at the beginning of the structure. */
5546 XVECEXP (parms.ret, 0, 0)
5547 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5549 /* Fill in the entries. */
5551 parms.intoffset = 0;
5552 function_arg_record_value_2 (type, 0, &parms, false);
5553 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5555 gcc_assert (parms.nregs == nregs);
5560 /* Used by function_arg and sparc_function_value_1 to implement the conventions
5561 of the 64-bit ABI for passing and returning unions.
5562 Return an expression valid as a return value for the FUNCTION_ARG
5563 and TARGET_FUNCTION_VALUE.
5565 SIZE is the size in bytes of the union.
5566 MODE is the argument's machine mode.
5567 REGNO is the hard register the union will be passed in. */
5570 function_arg_union_value (int size, enum machine_mode mode, int slotno,
5573 int nwords = ROUND_ADVANCE (size), i;
5576 /* See comment in previous function for empty structures. */
5578 return gen_rtx_REG (mode, regno);
5580 if (slotno == SPARC_INT_ARG_MAX - 1)
5583 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
5585 for (i = 0; i < nwords; i++)
5587 /* Unions are passed left-justified. */
5588 XVECEXP (regs, 0, i)
5589 = gen_rtx_EXPR_LIST (VOIDmode,
5590 gen_rtx_REG (word_mode, regno),
5591 GEN_INT (UNITS_PER_WORD * i));
5598 /* Used by function_arg and sparc_function_value_1 to implement the conventions
5599 for passing and returning large (BLKmode) vectors.
5600 Return an expression valid as a return value for the FUNCTION_ARG
5601 and TARGET_FUNCTION_VALUE.
5603 SIZE is the size in bytes of the vector (at least 8 bytes).
5604 REGNO is the FP hard register the vector will be passed in. */
5607 function_arg_vector_value (int size, int regno)
5609 int i, nregs = size / 8;
5612 regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
5614 for (i = 0; i < nregs; i++)
5616 XVECEXP (regs, 0, i)
5617 = gen_rtx_EXPR_LIST (VOIDmode,
5618 gen_rtx_REG (DImode, regno + 2*i),
5625 /* Determine where to put an argument to a function.
5626 Value is zero to push the argument on the stack,
5627 or a hard register in which to store the argument.
5629 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5630 the preceding args and about the function being called.
5631 MODE is the argument's machine mode.
5632 TYPE is the data type of the argument (as a tree).
5633 This is null for libcalls where that information may
5635 NAMED is true if this argument is a named parameter
5636 (otherwise it is an extra parameter matching an ellipsis).
5637 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
5638 TARGET_FUNCTION_INCOMING_ARG. */
5641 sparc_function_arg_1 (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
5642 const_tree type, bool named, bool incoming_p)
5644 int regbase = (incoming_p
5645 ? SPARC_INCOMING_INT_ARG_FIRST
5646 : SPARC_OUTGOING_INT_ARG_FIRST);
5647 int slotno, regno, padding;
5648 enum mode_class mclass = GET_MODE_CLASS (mode);
5650 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5655 /* Vector types deserve special treatment because they are polymorphic wrt
5656 their mode, depending upon whether VIS instructions are enabled. */
5657 if (type && TREE_CODE (type) == VECTOR_TYPE)
5659 HOST_WIDE_INT size = int_size_in_bytes (type);
5660 gcc_assert ((TARGET_ARCH32 && size <= 8)
5661 || (TARGET_ARCH64 && size <= 16));
5663 if (mode == BLKmode)
5664 return function_arg_vector_value (size,
5665 SPARC_FP_ARG_FIRST + 2*slotno);
5667 mclass = MODE_FLOAT;
5671 return gen_rtx_REG (mode, regno);
5673 /* Structures up to 16 bytes in size are passed in arg slots on the stack
5674 and are promoted to registers if possible. */
5675 if (type && TREE_CODE (type) == RECORD_TYPE)
5677 HOST_WIDE_INT size = int_size_in_bytes (type);
5678 gcc_assert (size <= 16);
5680 return function_arg_record_value (type, mode, slotno, named, regbase);
5683 /* Unions up to 16 bytes in size are passed in integer registers. */
5684 else if (type && TREE_CODE (type) == UNION_TYPE)
5686 HOST_WIDE_INT size = int_size_in_bytes (type);
5687 gcc_assert (size <= 16);
5689 return function_arg_union_value (size, mode, slotno, regno);
5692 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5693 but also have the slot allocated for them.
5694 If no prototype is in scope fp values in register slots get passed
5695 in two places, either fp regs and int regs or fp regs and memory. */
5696 else if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
5697 && SPARC_FP_REG_P (regno))
5699 rtx reg = gen_rtx_REG (mode, regno);
5700 if (cum->prototype_p || cum->libcall_p)
5702 /* "* 2" because fp reg numbers are recorded in 4 byte
5705 /* ??? This will cause the value to be passed in the fp reg and
5706 in the stack. When a prototype exists we want to pass the
5707 value in the reg but reserve space on the stack. That's an
5708 optimization, and is deferred [for a bit]. */
5709 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5710 return gen_rtx_PARALLEL (mode,
5712 gen_rtx_EXPR_LIST (VOIDmode,
5713 NULL_RTX, const0_rtx),
5714 gen_rtx_EXPR_LIST (VOIDmode,
5718 /* ??? It seems that passing back a register even when past
5719 the area declared by REG_PARM_STACK_SPACE will allocate
5720 space appropriately, and will not copy the data onto the
5721 stack, exactly as we desire.
5723 This is due to locate_and_pad_parm being called in
5724 expand_call whenever reg_parm_stack_space > 0, which
5725 while beneficial to our example here, would seem to be
5726 in error from what had been intended. Ho hum... -- r~ */
5734 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5738 /* On incoming, we don't need to know that the value
5739 is passed in %f0 and %i0, and it confuses other parts
5740 causing needless spillage even on the simplest cases. */
5744 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5745 + (regno - SPARC_FP_ARG_FIRST) / 2);
5747 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5748 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5750 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5754 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5755 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5756 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5761 /* All other aggregate types are passed in an integer register in a mode
5762 corresponding to the size of the type. */
5763 else if (type && AGGREGATE_TYPE_P (type))
5765 HOST_WIDE_INT size = int_size_in_bytes (type);
5766 gcc_assert (size <= 16);
5768 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5771 return gen_rtx_REG (mode, regno);
5774 /* Handle the TARGET_FUNCTION_ARG target hook. */
5777 sparc_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5778 const_tree type, bool named)
5780 return sparc_function_arg_1 (cum, mode, type, named, false);
5783 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
5786 sparc_function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5787 const_tree type, bool named)
5789 return sparc_function_arg_1 (cum, mode, type, named, true);
5792 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
5795 sparc_function_arg_boundary (enum machine_mode mode, const_tree type)
5797 return ((TARGET_ARCH64
5798 && (GET_MODE_ALIGNMENT (mode) == 128
5799 || (type && TYPE_ALIGN (type) == 128)))
5804 /* For an arg passed partly in registers and partly in memory,
5805 this is the number of bytes of registers used.
5806 For args passed entirely in registers or entirely in memory, zero.
5808 Any arg that starts in the first 6 regs but won't entirely fit in them
5809 needs partial registers on v8. On v9, structures with integer
5810 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5811 values that begin in the last fp reg [where "last fp reg" varies with the
5812 mode] will be split between that reg and memory. */
5815 sparc_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5816 tree type, bool named)
5818 int slotno, regno, padding;
5820 /* We pass false for incoming_p here, it doesn't matter. */
5821 slotno = function_arg_slotno (cum, mode, type, named, false,
5829 if ((slotno + (mode == BLKmode
5830 ? ROUND_ADVANCE (int_size_in_bytes (type))
5831 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5832 > SPARC_INT_ARG_MAX)
5833 return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD;
5837 /* We are guaranteed by pass_by_reference that the size of the
5838 argument is not greater than 16 bytes, so we only need to return
5839 one word if the argument is partially passed in registers. */
5841 if (type && AGGREGATE_TYPE_P (type))
5843 int size = int_size_in_bytes (type);
5845 if (size > UNITS_PER_WORD
5846 && slotno == SPARC_INT_ARG_MAX - 1)
5847 return UNITS_PER_WORD;
5849 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5850 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5851 && ! (TARGET_FPU && named)))
5853 /* The complex types are passed as packed types. */
5854 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5855 && slotno == SPARC_INT_ARG_MAX - 1)
5856 return UNITS_PER_WORD;
5858 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5860 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5862 return UNITS_PER_WORD;
5869 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
5870 Specify whether to pass the argument by reference. */
5873 sparc_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5874 enum machine_mode mode, const_tree type,
5875 bool named ATTRIBUTE_UNUSED)
5878 /* Original SPARC 32-bit ABI says that structures and unions,
5879 and quad-precision floats are passed by reference. For Pascal,
5880 also pass arrays by reference. All other base types are passed
5883 Extended ABI (as implemented by the Sun compiler) says that all
5884 complex floats are passed by reference. Pass complex integers
5885 in registers up to 8 bytes. More generally, enforce the 2-word
5886 cap for passing arguments in registers.
5888 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5889 integers are passed like floats of the same size, that is in
5890 registers up to 8 bytes. Pass all vector floats by reference
5891 like structure and unions. */
5892 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
5894 /* Catch CDImode, TFmode, DCmode and TCmode. */
5895 || GET_MODE_SIZE (mode) > 8
5897 && TREE_CODE (type) == VECTOR_TYPE
5898 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
5900 /* Original SPARC 64-bit ABI says that structures and unions
5901 smaller than 16 bytes are passed in registers, as well as
5902 all other base types.
5904 Extended ABI (as implemented by the Sun compiler) says that
5905 complex floats are passed in registers up to 16 bytes. Pass
5906 all complex integers in registers up to 16 bytes. More generally,
5907 enforce the 2-word cap for passing arguments in registers.
5909 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5910 integers are passed like floats of the same size, that is in
5911 registers (up to 16 bytes). Pass all vector floats like structure
5914 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE)
5915 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
5916 /* Catch CTImode and TCmode. */
5917 || GET_MODE_SIZE (mode) > 16);
5920 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
5921 Update the data in CUM to advance over an argument
5922 of mode MODE and data type TYPE.
5923 TYPE is null for libcalls where that information may not be available. */
5926 sparc_function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5927 const_tree type, bool named)
5931 /* We pass false for incoming_p here, it doesn't matter. */
5932 function_arg_slotno (cum, mode, type, named, false, ®no, &padding);
5934 /* If argument requires leading padding, add it. */
5935 cum->words += padding;
5939 cum->words += (mode != BLKmode
5940 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5941 : ROUND_ADVANCE (int_size_in_bytes (type)));
5945 if (type && AGGREGATE_TYPE_P (type))
5947 int size = int_size_in_bytes (type);
5951 else if (size <= 16)
5953 else /* passed by reference */
5958 cum->words += (mode != BLKmode
5959 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5960 : ROUND_ADVANCE (int_size_in_bytes (type)));
5965 /* Handle the FUNCTION_ARG_PADDING macro.
5966 For the 64 bit ABI structs are always stored left shifted in their
5970 function_arg_padding (enum machine_mode mode, const_tree type)
5972 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5975 /* Fall back to the default. */
5976 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5979 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
5980 Specify whether to return the return value in memory. */
5983 sparc_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5986 /* Original SPARC 32-bit ABI says that structures and unions,
5987 and quad-precision floats are returned in memory. All other
5988 base types are returned in registers.
5990 Extended ABI (as implemented by the Sun compiler) says that
5991 all complex floats are returned in registers (8 FP registers
5992 at most for '_Complex long double'). Return all complex integers
5993 in registers (4 at most for '_Complex long long').
5995 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5996 integers are returned like floats of the same size, that is in
5997 registers up to 8 bytes and in memory otherwise. Return all
5998 vector floats in memory like structure and unions; note that
5999 they always have BLKmode like the latter. */
6000 return (TYPE_MODE (type) == BLKmode
6001 || TYPE_MODE (type) == TFmode
6002 || (TREE_CODE (type) == VECTOR_TYPE
6003 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
6005 /* Original SPARC 64-bit ABI says that structures and unions
6006 smaller than 32 bytes are returned in registers, as well as
6007 all other base types.
6009 Extended ABI (as implemented by the Sun compiler) says that all
6010 complex floats are returned in registers (8 FP registers at most
6011 for '_Complex long double'). Return all complex integers in
6012 registers (4 at most for '_Complex TItype').
6014 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6015 integers are returned like floats of the same size, that is in
6016 registers. Return all vector floats like structure and unions;
6017 note that they always have BLKmode like the latter. */
6018 return (TYPE_MODE (type) == BLKmode
6019 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32);
6022 /* Handle the TARGET_STRUCT_VALUE target hook.
6023 Return where to find the structure return value address. */
6026 sparc_struct_value_rtx (tree fndecl, int incoming)
6035 mem = gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx,
6036 STRUCT_VALUE_OFFSET));
6038 mem = gen_frame_mem (Pmode, plus_constant (stack_pointer_rtx,
6039 STRUCT_VALUE_OFFSET));
6041 /* Only follow the SPARC ABI for fixed-size structure returns.
6042 Variable size structure returns are handled per the normal
6043 procedures in GCC. This is enabled by -mstd-struct-return */
6045 && sparc_std_struct_return
6046 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl))
6047 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl))) == INTEGER_CST)
6049 /* We must check and adjust the return address, as it is
6050 optional as to whether the return object is really
6052 rtx ret_rtx = gen_rtx_REG (Pmode, 31);
6053 rtx scratch = gen_reg_rtx (SImode);
6054 rtx endlab = gen_label_rtx ();
6056 /* Calculate the return object size */
6057 tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl));
6058 rtx size_rtx = GEN_INT (TREE_INT_CST_LOW (size) & 0xfff);
6059 /* Construct a temporary return value */
6061 = assign_stack_local (Pmode, TREE_INT_CST_LOW (size), 0);
6063 /* Implement SPARC 32-bit psABI callee return struct checking:
6065 Fetch the instruction where we will return to and see if
6066 it's an unimp instruction (the most significant 10 bits
6068 emit_move_insn (scratch, gen_rtx_MEM (SImode,
6069 plus_constant (ret_rtx, 8)));
6070 /* Assume the size is valid and pre-adjust */
6071 emit_insn (gen_add3_insn (ret_rtx, ret_rtx, GEN_INT (4)));
6072 emit_cmp_and_jump_insns (scratch, size_rtx, EQ, const0_rtx, SImode,
6074 emit_insn (gen_sub3_insn (ret_rtx, ret_rtx, GEN_INT (4)));
6075 /* Write the address of the memory pointed to by temp_val into
6076 the memory pointed to by mem */
6077 emit_move_insn (mem, XEXP (temp_val, 0));
6078 emit_label (endlab);
6085 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
6086 For v9, function return values are subject to the same rules as arguments,
6087 except that up to 32 bytes may be returned in registers. */
6090 sparc_function_value_1 (const_tree type, enum machine_mode mode,
6093 /* Beware that the two values are swapped here wrt function_arg. */
6094 int regbase = (outgoing
6095 ? SPARC_INCOMING_INT_ARG_FIRST
6096 : SPARC_OUTGOING_INT_ARG_FIRST);
6097 enum mode_class mclass = GET_MODE_CLASS (mode);
6100 /* Vector types deserve special treatment because they are polymorphic wrt
6101 their mode, depending upon whether VIS instructions are enabled. */
6102 if (type && TREE_CODE (type) == VECTOR_TYPE)
6104 HOST_WIDE_INT size = int_size_in_bytes (type);
6105 gcc_assert ((TARGET_ARCH32 && size <= 8)
6106 || (TARGET_ARCH64 && size <= 32));
6108 if (mode == BLKmode)
6109 return function_arg_vector_value (size,
6110 SPARC_FP_ARG_FIRST);
6112 mclass = MODE_FLOAT;
6115 if (TARGET_ARCH64 && type)
6117 /* Structures up to 32 bytes in size are returned in registers. */
6118 if (TREE_CODE (type) == RECORD_TYPE)
6120 HOST_WIDE_INT size = int_size_in_bytes (type);
6121 gcc_assert (size <= 32);
6123 return function_arg_record_value (type, mode, 0, 1, regbase);
6126 /* Unions up to 32 bytes in size are returned in integer registers. */
6127 else if (TREE_CODE (type) == UNION_TYPE)
6129 HOST_WIDE_INT size = int_size_in_bytes (type);
6130 gcc_assert (size <= 32);
6132 return function_arg_union_value (size, mode, 0, regbase);
6135 /* Objects that require it are returned in FP registers. */
6136 else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6139 /* All other aggregate types are returned in an integer register in a
6140 mode corresponding to the size of the type. */
6141 else if (AGGREGATE_TYPE_P (type))
6143 /* All other aggregate types are passed in an integer register
6144 in a mode corresponding to the size of the type. */
6145 HOST_WIDE_INT size = int_size_in_bytes (type);
6146 gcc_assert (size <= 32);
6148 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
6150 /* ??? We probably should have made the same ABI change in
6151 3.4.0 as the one we made for unions. The latter was
6152 required by the SCD though, while the former is not
6153 specified, so we favored compatibility and efficiency.
6155 Now we're stuck for aggregates larger than 16 bytes,
6156 because OImode vanished in the meantime. Let's not
6157 try to be unduly clever, and simply follow the ABI
6158 for unions in that case. */
6159 if (mode == BLKmode)
6160 return function_arg_union_value (size, mode, 0, regbase);
6165 /* We should only have pointer and integer types at this point. This
6166 must match sparc_promote_function_mode. */
6167 else if (mclass == MODE_INT && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6171 /* We should only have pointer and integer types at this point. This must
6172 match sparc_promote_function_mode. */
6173 else if (TARGET_ARCH32
6174 && mclass == MODE_INT
6175 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6178 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) && TARGET_FPU)
6179 regno = SPARC_FP_ARG_FIRST;
6183 return gen_rtx_REG (mode, regno);
6186 /* Handle TARGET_FUNCTION_VALUE.
6187 On the SPARC, the value is found in the first "output" register, but the
6188 called function leaves it in the first "input" register. */
6191 sparc_function_value (const_tree valtype,
6192 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
6195 return sparc_function_value_1 (valtype, TYPE_MODE (valtype), outgoing);
6198 /* Handle TARGET_LIBCALL_VALUE. */
6201 sparc_libcall_value (enum machine_mode mode,
6202 const_rtx fun ATTRIBUTE_UNUSED)
6204 return sparc_function_value_1 (NULL_TREE, mode, false);
6207 /* Handle FUNCTION_VALUE_REGNO_P.
6208 On the SPARC, the first "output" reg is used for integer values, and the
6209 first floating point register is used for floating point values. */
6212 sparc_function_value_regno_p (const unsigned int regno)
6214 return (regno == 8 || regno == 32);
6217 /* Do what is necessary for `va_start'. We look at the current function
6218 to determine if stdarg or varargs is used and return the address of
6219 the first unnamed parameter. */
6222 sparc_builtin_saveregs (void)
6224 int first_reg = crtl->args.info.words;
6228 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
6229 emit_move_insn (gen_rtx_MEM (word_mode,
6230 gen_rtx_PLUS (Pmode,
6232 GEN_INT (FIRST_PARM_OFFSET (0)
6235 gen_rtx_REG (word_mode,
6236 SPARC_INCOMING_INT_ARG_FIRST + regno));
6238 address = gen_rtx_PLUS (Pmode,
6240 GEN_INT (FIRST_PARM_OFFSET (0)
6241 + UNITS_PER_WORD * first_reg));
6246 /* Implement `va_start' for stdarg. */
6249 sparc_va_start (tree valist, rtx nextarg)
6251 nextarg = expand_builtin_saveregs ();
6252 std_expand_builtin_va_start (valist, nextarg);
6255 /* Implement `va_arg' for stdarg. */
6258 sparc_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6261 HOST_WIDE_INT size, rsize, align;
6264 tree ptrtype = build_pointer_type (type);
6266 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6269 size = rsize = UNITS_PER_WORD;
6275 size = int_size_in_bytes (type);
6276 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6281 /* For SPARC64, objects requiring 16-byte alignment get it. */
6282 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
6283 align = 2 * UNITS_PER_WORD;
6285 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6286 are left-justified in their slots. */
6287 if (AGGREGATE_TYPE_P (type))
6290 size = rsize = UNITS_PER_WORD;
6300 incr = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr,
6301 size_int (align - 1));
6302 incr = fold_convert (sizetype, incr);
6303 incr = fold_build2 (BIT_AND_EXPR, sizetype, incr,
6305 incr = fold_convert (ptr_type_node, incr);
6308 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
6311 if (BYTES_BIG_ENDIAN && size < rsize)
6312 addr = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr,
6313 size_int (rsize - size));
6317 addr = fold_convert (build_pointer_type (ptrtype), addr);
6318 addr = build_va_arg_indirect_ref (addr);
6321 /* If the address isn't aligned properly for the type, we need a temporary.
6322 FIXME: This is inefficient, usually we can do this in registers. */
6323 else if (align == 0 && TYPE_ALIGN (type) > BITS_PER_WORD)
6325 tree tmp = create_tmp_var (type, "va_arg_tmp");
6326 tree dest_addr = build_fold_addr_expr (tmp);
6327 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6328 3, dest_addr, addr, size_int (rsize));
6329 TREE_ADDRESSABLE (tmp) = 1;
6330 gimplify_and_add (copy, pre_p);
6335 addr = fold_convert (ptrtype, addr);
6338 = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr, size_int (rsize));
6339 gimplify_assign (valist, incr, post_p);
6341 return build_va_arg_indirect_ref (addr);
6344 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6345 Specify whether the vector mode is supported by the hardware. */
6348 sparc_vector_mode_supported_p (enum machine_mode mode)
6350 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
6353 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
6355 static enum machine_mode
6356 sparc_preferred_simd_mode (enum machine_mode mode)
6374 /* Return the string to output an unconditional branch to LABEL, which is
6375 the operand number of the label.
6377 DEST is the destination insn (i.e. the label), INSN is the source. */
6380 output_ubranch (rtx dest, int label, rtx insn)
6382 static char string[64];
6383 bool v9_form = false;
6386 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
6388 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6389 - INSN_ADDRESSES (INSN_UID (insn)));
6390 /* Leave some instructions for "slop". */
6391 if (delta >= -260000 && delta < 260000)
6396 strcpy (string, "ba%*,pt\t%%xcc, ");
6398 strcpy (string, "b%*\t");
6400 p = strchr (string, '\0');
6411 /* Return the string to output a conditional branch to LABEL, which is
6412 the operand number of the label. OP is the conditional expression.
6413 XEXP (OP, 0) is assumed to be a condition code register (integer or
6414 floating point) and its mode specifies what kind of comparison we made.
6416 DEST is the destination insn (i.e. the label), INSN is the source.
6418 REVERSED is nonzero if we should reverse the sense of the comparison.
6420 ANNUL is nonzero if we should generate an annulling branch. */
6423 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
6426 static char string[64];
6427 enum rtx_code code = GET_CODE (op);
6428 rtx cc_reg = XEXP (op, 0);
6429 enum machine_mode mode = GET_MODE (cc_reg);
6430 const char *labelno, *branch;
6431 int spaces = 8, far;
6434 /* v9 branches are limited to +-1MB. If it is too far away,
6447 fbne,a,pn %fcc2, .LC29
6455 far = TARGET_V9 && (get_attr_length (insn) >= 3);
6458 /* Reversal of FP compares takes care -- an ordered compare
6459 becomes an unordered compare and vice versa. */
6460 if (mode == CCFPmode || mode == CCFPEmode)
6461 code = reverse_condition_maybe_unordered (code);
6463 code = reverse_condition (code);
6466 /* Start by writing the branch condition. */
6467 if (mode == CCFPmode || mode == CCFPEmode)
6518 /* ??? !v9: FP branches cannot be preceded by another floating point
6519 insn. Because there is currently no concept of pre-delay slots,
6520 we can fix this only by always emitting a nop before a floating
6525 strcpy (string, "nop\n\t");
6526 strcat (string, branch);
6539 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6551 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6572 strcpy (string, branch);
6574 spaces -= strlen (branch);
6575 p = strchr (string, '\0');
6577 /* Now add the annulling, the label, and a possible noop. */
6590 if (! far && insn && INSN_ADDRESSES_SET_P ())
6592 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6593 - INSN_ADDRESSES (INSN_UID (insn)));
6594 /* Leave some instructions for "slop". */
6595 if (delta < -260000 || delta >= 260000)
6599 if (mode == CCFPmode || mode == CCFPEmode)
6601 static char v9_fcc_labelno[] = "%%fccX, ";
6602 /* Set the char indicating the number of the fcc reg to use. */
6603 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6604 labelno = v9_fcc_labelno;
6607 gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG);
6611 else if (mode == CCXmode || mode == CCX_NOOVmode)
6613 labelno = "%%xcc, ";
6618 labelno = "%%icc, ";
6623 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6626 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6639 strcpy (p, labelno);
6640 p = strchr (p, '\0');
6643 strcpy (p, ".+12\n\t nop\n\tb\t");
6644 /* Skip the next insn if requested or
6645 if we know that it will be a nop. */
6646 if (annul || ! final_sequence)
6660 /* Emit a library call comparison between floating point X and Y.
6661 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
6662 Return the new operator to be used in the comparison sequence.
6664 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6665 values as arguments instead of the TFmode registers themselves,
6666 that's why we cannot call emit_float_lib_cmp. */
6669 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6672 rtx slot0, slot1, result, tem, tem2, libfunc;
6673 enum machine_mode mode;
6674 enum rtx_code new_comparison;
6679 qpfunc = (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq");
6683 qpfunc = (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne");
6687 qpfunc = (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt");
6691 qpfunc = (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge");
6695 qpfunc = (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt");
6699 qpfunc = (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle");
6710 qpfunc = (TARGET_ARCH64 ? "_Qp_cmp" : "_Q_cmp");
6723 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6724 emit_move_insn (slot0, x);
6731 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6732 emit_move_insn (slot1, y);
6735 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
6736 emit_library_call (libfunc, LCT_NORMAL,
6738 XEXP (slot0, 0), Pmode,
6739 XEXP (slot1, 0), Pmode);
6744 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
6745 emit_library_call (libfunc, LCT_NORMAL,
6747 x, TFmode, y, TFmode);
6752 /* Immediately move the result of the libcall into a pseudo
6753 register so reload doesn't clobber the value if it needs
6754 the return register for a spill reg. */
6755 result = gen_reg_rtx (mode);
6756 emit_move_insn (result, hard_libcall_value (mode, libfunc));
6761 return gen_rtx_NE (VOIDmode, result, const0_rtx);
6764 new_comparison = (comparison == UNORDERED ? EQ : NE);
6765 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, GEN_INT(3));
6768 new_comparison = (comparison == UNGT ? GT : NE);
6769 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, const1_rtx);
6771 return gen_rtx_NE (VOIDmode, result, const2_rtx);
6773 tem = gen_reg_rtx (mode);
6775 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6777 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6778 return gen_rtx_NE (VOIDmode, tem, const0_rtx);
6781 tem = gen_reg_rtx (mode);
6783 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6785 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6786 tem2 = gen_reg_rtx (mode);
6788 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6790 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6791 new_comparison = (comparison == UNEQ ? EQ : NE);
6792 return gen_rtx_fmt_ee (new_comparison, VOIDmode, tem2, const0_rtx);
6798 /* Generate an unsigned DImode to FP conversion. This is the same code
6799 optabs would emit if we didn't have TFmode patterns. */
6802 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
6804 rtx neglab, donelab, i0, i1, f0, in, out;
6807 in = force_reg (DImode, operands[1]);
6808 neglab = gen_label_rtx ();
6809 donelab = gen_label_rtx ();
6810 i0 = gen_reg_rtx (DImode);
6811 i1 = gen_reg_rtx (DImode);
6812 f0 = gen_reg_rtx (mode);
6814 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6816 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6817 emit_jump_insn (gen_jump (donelab));
6820 emit_label (neglab);
6822 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6823 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6824 emit_insn (gen_iordi3 (i0, i0, i1));
6825 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6826 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6828 emit_label (donelab);
6831 /* Generate an FP to unsigned DImode conversion. This is the same code
6832 optabs would emit if we didn't have TFmode patterns. */
6835 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
6837 rtx neglab, donelab, i0, i1, f0, in, out, limit;
6840 in = force_reg (mode, operands[1]);
6841 neglab = gen_label_rtx ();
6842 donelab = gen_label_rtx ();
6843 i0 = gen_reg_rtx (DImode);
6844 i1 = gen_reg_rtx (DImode);
6845 limit = gen_reg_rtx (mode);
6846 f0 = gen_reg_rtx (mode);
6848 emit_move_insn (limit,
6849 CONST_DOUBLE_FROM_REAL_VALUE (
6850 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
6851 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
6853 emit_insn (gen_rtx_SET (VOIDmode,
6855 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
6856 emit_jump_insn (gen_jump (donelab));
6859 emit_label (neglab);
6861 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
6862 emit_insn (gen_rtx_SET (VOIDmode,
6864 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6865 emit_insn (gen_movdi (i1, const1_rtx));
6866 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6867 emit_insn (gen_xordi3 (out, i0, i1));
6869 emit_label (donelab);
6872 /* Return the string to output a conditional branch to LABEL, testing
6873 register REG. LABEL is the operand number of the label; REG is the
6874 operand number of the reg. OP is the conditional expression. The mode
6875 of REG says what kind of comparison we made.
6877 DEST is the destination insn (i.e. the label), INSN is the source.
6879 REVERSED is nonzero if we should reverse the sense of the comparison.
6881 ANNUL is nonzero if we should generate an annulling branch. */
6884 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6885 int annul, rtx insn)
6887 static char string[64];
6888 enum rtx_code code = GET_CODE (op);
6889 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6894 /* branch on register are limited to +-128KB. If it is too far away,
6907 brgez,a,pn %o1, .LC29
6913 ba,pt %xcc, .LC29 */
6915 far = get_attr_length (insn) >= 3;
6917 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6919 code = reverse_condition (code);
6921 /* Only 64 bit versions of these instructions exist. */
6922 gcc_assert (mode == DImode);
6924 /* Start by writing the branch condition. */
6929 strcpy (string, "brnz");
6933 strcpy (string, "brz");
6937 strcpy (string, "brgez");
6941 strcpy (string, "brlz");
6945 strcpy (string, "brlez");
6949 strcpy (string, "brgz");
6956 p = strchr (string, '\0');
6958 /* Now add the annulling, reg, label, and nop. */
6965 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6968 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6973 *p = p < string + 8 ? '\t' : ' ';
6981 int veryfar = 1, delta;
6983 if (INSN_ADDRESSES_SET_P ())
6985 delta = (INSN_ADDRESSES (INSN_UID (dest))
6986 - INSN_ADDRESSES (INSN_UID (insn)));
6987 /* Leave some instructions for "slop". */
6988 if (delta >= -260000 && delta < 260000)
6992 strcpy (p, ".+12\n\t nop\n\t");
6993 /* Skip the next insn if requested or
6994 if we know that it will be a nop. */
6995 if (annul || ! final_sequence)
7005 strcpy (p, "ba,pt\t%%xcc, ");
7019 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
7020 Such instructions cannot be used in the delay slot of return insn on v9.
7021 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
7025 epilogue_renumber (register rtx *where, int test)
7027 register const char *fmt;
7029 register enum rtx_code code;
7034 code = GET_CODE (*where);
7039 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
7041 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
7042 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
7050 /* Do not replace the frame pointer with the stack pointer because
7051 it can cause the delayed instruction to load below the stack.
7052 This occurs when instructions like:
7054 (set (reg/i:SI 24 %i0)
7055 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7056 (const_int -20 [0xffffffec])) 0))
7058 are in the return delayed slot. */
7060 if (GET_CODE (XEXP (*where, 0)) == REG
7061 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
7062 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
7063 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
7068 if (SPARC_STACK_BIAS
7069 && GET_CODE (XEXP (*where, 0)) == REG
7070 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
7078 fmt = GET_RTX_FORMAT (code);
7080 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7085 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
7086 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
7089 else if (fmt[i] == 'e'
7090 && epilogue_renumber (&(XEXP (*where, i)), test))
7096 /* Leaf functions and non-leaf functions have different needs. */
7099 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
7102 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
7104 static const int *const reg_alloc_orders[] = {
7105 reg_leaf_alloc_order,
7106 reg_nonleaf_alloc_order};
7109 order_regs_for_local_alloc (void)
7111 static int last_order_nonleaf = 1;
7113 if (df_regs_ever_live_p (15) != last_order_nonleaf)
7115 last_order_nonleaf = !last_order_nonleaf;
7116 memcpy ((char *) reg_alloc_order,
7117 (const char *) reg_alloc_orders[last_order_nonleaf],
7118 FIRST_PSEUDO_REGISTER * sizeof (int));
7122 /* Return 1 if REG and MEM are legitimate enough to allow the various
7123 mem<-->reg splits to be run. */
7126 sparc_splitdi_legitimate (rtx reg, rtx mem)
7128 /* Punt if we are here by mistake. */
7129 gcc_assert (reload_completed);
7131 /* We must have an offsettable memory reference. */
7132 if (! offsettable_memref_p (mem))
7135 /* If we have legitimate args for ldd/std, we do not want
7136 the split to happen. */
7137 if ((REGNO (reg) % 2) == 0
7138 && mem_min_alignment (mem, 8))
7145 /* Return 1 if x and y are some kind of REG and they refer to
7146 different hard registers. This test is guaranteed to be
7147 run after reload. */
7150 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
7152 if (GET_CODE (x) != REG)
7154 if (GET_CODE (y) != REG)
7156 if (REGNO (x) == REGNO (y))
7161 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7162 This makes them candidates for using ldd and std insns.
7164 Note reg1 and reg2 *must* be hard registers. */
7167 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
7169 /* We might have been passed a SUBREG. */
7170 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
7173 if (REGNO (reg1) % 2 != 0)
7176 /* Integer ldd is deprecated in SPARC V9 */
7177 if (TARGET_V9 && REGNO (reg1) < 32)
7180 return (REGNO (reg1) == REGNO (reg2) - 1);
7183 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7186 This can only happen when addr1 and addr2, the addresses in mem1
7187 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7188 addr1 must also be aligned on a 64-bit boundary.
7190 Also iff dependent_reg_rtx is not null it should not be used to
7191 compute the address for mem1, i.e. we cannot optimize a sequence
7203 But, note that the transformation from:
7208 is perfectly fine. Thus, the peephole2 patterns always pass us
7209 the destination register of the first load, never the second one.
7211 For stores we don't have a similar problem, so dependent_reg_rtx is
7215 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
7219 HOST_WIDE_INT offset1;
7221 /* The mems cannot be volatile. */
7222 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
7225 /* MEM1 should be aligned on a 64-bit boundary. */
7226 if (MEM_ALIGN (mem1) < 64)
7229 addr1 = XEXP (mem1, 0);
7230 addr2 = XEXP (mem2, 0);
7232 /* Extract a register number and offset (if used) from the first addr. */
7233 if (GET_CODE (addr1) == PLUS)
7235 /* If not a REG, return zero. */
7236 if (GET_CODE (XEXP (addr1, 0)) != REG)
7240 reg1 = REGNO (XEXP (addr1, 0));
7241 /* The offset must be constant! */
7242 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
7244 offset1 = INTVAL (XEXP (addr1, 1));
7247 else if (GET_CODE (addr1) != REG)
7251 reg1 = REGNO (addr1);
7252 /* This was a simple (mem (reg)) expression. Offset is 0. */
7256 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7257 if (GET_CODE (addr2) != PLUS)
7260 if (GET_CODE (XEXP (addr2, 0)) != REG
7261 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
7264 if (reg1 != REGNO (XEXP (addr2, 0)))
7267 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
7270 /* The first offset must be evenly divisible by 8 to ensure the
7271 address is 64 bit aligned. */
7272 if (offset1 % 8 != 0)
7275 /* The offset for the second addr must be 4 more than the first addr. */
7276 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
7279 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7284 /* Return 1 if reg is a pseudo, or is the first register in
7285 a hard register pair. This makes it suitable for use in
7286 ldd and std insns. */
7289 register_ok_for_ldd (rtx reg)
7291 /* We might have been passed a SUBREG. */
7295 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
7296 return (REGNO (reg) % 2 == 0);
7301 /* Return 1 if OP is a memory whose address is known to be
7302 aligned to 8-byte boundary, or a pseudo during reload.
7303 This makes it suitable for use in ldd and std insns. */
7306 memory_ok_for_ldd (rtx op)
7310 /* In 64-bit mode, we assume that the address is word-aligned. */
7311 if (TARGET_ARCH32 && !mem_min_alignment (op, 8))
7314 if ((reload_in_progress || reload_completed)
7315 && !strict_memory_address_p (Pmode, XEXP (op, 0)))
7318 else if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
7320 if (!(reload_in_progress && reg_renumber [REGNO (op)] < 0))
7329 /* Print operand X (an rtx) in assembler syntax to file FILE.
7330 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7331 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7334 print_operand (FILE *file, rtx x, int code)
7339 /* Output an insn in a delay slot. */
7341 sparc_indent_opcode = 1;
7343 fputs ("\n\t nop", file);
7346 /* Output an annul flag if there's nothing for the delay slot and we
7347 are optimizing. This is always used with '(' below.
7348 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7349 this is a dbx bug. So, we only do this when optimizing.
7350 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7351 Always emit a nop in case the next instruction is a branch. */
7352 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9))
7356 /* Output a 'nop' if there's nothing for the delay slot and we are
7357 not optimizing. This is always used with '*' above. */
7358 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
7359 fputs ("\n\t nop", file);
7360 else if (final_sequence)
7361 sparc_indent_opcode = 1;
7364 /* Output the right displacement from the saved PC on function return.
7365 The caller may have placed an "unimp" insn immediately after the call
7366 so we have to account for it. This insn is used in the 32-bit ABI
7367 when calling a function that returns a non zero-sized structure. The
7368 64-bit ABI doesn't have it. Be careful to have this test be the same
7369 as that for the call. The exception is when sparc_std_struct_return
7370 is enabled, the psABI is followed exactly and the adjustment is made
7371 by the code in sparc_struct_value_rtx. The call emitted is the same
7372 when sparc_std_struct_return is enabled. */
7374 && cfun->returns_struct
7375 && !sparc_std_struct_return
7376 && DECL_SIZE (DECL_RESULT (current_function_decl))
7377 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
7379 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))))
7385 /* Output the Embedded Medium/Anywhere code model base register. */
7386 fputs (EMBMEDANY_BASE_REG, file);
7389 /* Print some local dynamic TLS name. */
7390 assemble_name (file, get_some_local_dynamic_name ());
7394 /* Adjust the operand to take into account a RESTORE operation. */
7395 if (GET_CODE (x) == CONST_INT)
7397 else if (GET_CODE (x) != REG)
7398 output_operand_lossage ("invalid %%Y operand");
7399 else if (REGNO (x) < 8)
7400 fputs (reg_names[REGNO (x)], file);
7401 else if (REGNO (x) >= 24 && REGNO (x) < 32)
7402 fputs (reg_names[REGNO (x)-16], file);
7404 output_operand_lossage ("invalid %%Y operand");
7407 /* Print out the low order register name of a register pair. */
7408 if (WORDS_BIG_ENDIAN)
7409 fputs (reg_names[REGNO (x)+1], file);
7411 fputs (reg_names[REGNO (x)], file);
7414 /* Print out the high order register name of a register pair. */
7415 if (WORDS_BIG_ENDIAN)
7416 fputs (reg_names[REGNO (x)], file);
7418 fputs (reg_names[REGNO (x)+1], file);
7421 /* Print out the second register name of a register pair or quad.
7422 I.e., R (%o0) => %o1. */
7423 fputs (reg_names[REGNO (x)+1], file);
7426 /* Print out the third register name of a register quad.
7427 I.e., S (%o0) => %o2. */
7428 fputs (reg_names[REGNO (x)+2], file);
7431 /* Print out the fourth register name of a register quad.
7432 I.e., T (%o0) => %o3. */
7433 fputs (reg_names[REGNO (x)+3], file);
7436 /* Print a condition code register. */
7437 if (REGNO (x) == SPARC_ICC_REG)
7439 /* We don't handle CC[X]_NOOVmode because they're not supposed
7441 if (GET_MODE (x) == CCmode)
7442 fputs ("%icc", file);
7443 else if (GET_MODE (x) == CCXmode)
7444 fputs ("%xcc", file);
7449 /* %fccN register */
7450 fputs (reg_names[REGNO (x)], file);
7453 /* Print the operand's address only. */
7454 output_address (XEXP (x, 0));
7457 /* In this case we need a register. Use %g0 if the
7458 operand is const0_rtx. */
7460 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
7462 fputs ("%g0", file);
7469 switch (GET_CODE (x))
7471 case IOR: fputs ("or", file); break;
7472 case AND: fputs ("and", file); break;
7473 case XOR: fputs ("xor", file); break;
7474 default: output_operand_lossage ("invalid %%A operand");
7479 switch (GET_CODE (x))
7481 case IOR: fputs ("orn", file); break;
7482 case AND: fputs ("andn", file); break;
7483 case XOR: fputs ("xnor", file); break;
7484 default: output_operand_lossage ("invalid %%B operand");
7488 /* These are used by the conditional move instructions. */
7492 enum rtx_code rc = GET_CODE (x);
7496 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7497 if (mode == CCFPmode || mode == CCFPEmode)
7498 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7500 rc = reverse_condition (GET_CODE (x));
7504 case NE: fputs ("ne", file); break;
7505 case EQ: fputs ("e", file); break;
7506 case GE: fputs ("ge", file); break;
7507 case GT: fputs ("g", file); break;
7508 case LE: fputs ("le", file); break;
7509 case LT: fputs ("l", file); break;
7510 case GEU: fputs ("geu", file); break;
7511 case GTU: fputs ("gu", file); break;
7512 case LEU: fputs ("leu", file); break;
7513 case LTU: fputs ("lu", file); break;
7514 case LTGT: fputs ("lg", file); break;
7515 case UNORDERED: fputs ("u", file); break;
7516 case ORDERED: fputs ("o", file); break;
7517 case UNLT: fputs ("ul", file); break;
7518 case UNLE: fputs ("ule", file); break;
7519 case UNGT: fputs ("ug", file); break;
7520 case UNGE: fputs ("uge", file); break;
7521 case UNEQ: fputs ("ue", file); break;
7522 default: output_operand_lossage (code == 'c'
7523 ? "invalid %%c operand"
7524 : "invalid %%C operand");
7529 /* These are used by the movr instruction pattern. */
7533 enum rtx_code rc = (code == 'd'
7534 ? reverse_condition (GET_CODE (x))
7538 case NE: fputs ("ne", file); break;
7539 case EQ: fputs ("e", file); break;
7540 case GE: fputs ("gez", file); break;
7541 case LT: fputs ("lz", file); break;
7542 case LE: fputs ("lez", file); break;
7543 case GT: fputs ("gz", file); break;
7544 default: output_operand_lossage (code == 'd'
7545 ? "invalid %%d operand"
7546 : "invalid %%D operand");
7553 /* Print a sign-extended character. */
7554 int i = trunc_int_for_mode (INTVAL (x), QImode);
7555 fprintf (file, "%d", i);
7560 /* Operand must be a MEM; write its address. */
7561 if (GET_CODE (x) != MEM)
7562 output_operand_lossage ("invalid %%f operand");
7563 output_address (XEXP (x, 0));
7568 /* Print a sign-extended 32-bit value. */
7570 if (GET_CODE(x) == CONST_INT)
7572 else if (GET_CODE(x) == CONST_DOUBLE)
7573 i = CONST_DOUBLE_LOW (x);
7576 output_operand_lossage ("invalid %%s operand");
7579 i = trunc_int_for_mode (i, SImode);
7580 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7585 /* Do nothing special. */
7589 /* Undocumented flag. */
7590 output_operand_lossage ("invalid operand output code");
7593 if (GET_CODE (x) == REG)
7594 fputs (reg_names[REGNO (x)], file);
7595 else if (GET_CODE (x) == MEM)
7598 /* Poor Sun assembler doesn't understand absolute addressing. */
7599 if (CONSTANT_P (XEXP (x, 0)))
7600 fputs ("%g0+", file);
7601 output_address (XEXP (x, 0));
7604 else if (GET_CODE (x) == HIGH)
7606 fputs ("%hi(", file);
7607 output_addr_const (file, XEXP (x, 0));
7610 else if (GET_CODE (x) == LO_SUM)
7612 print_operand (file, XEXP (x, 0), 0);
7613 if (TARGET_CM_MEDMID)
7614 fputs ("+%l44(", file);
7616 fputs ("+%lo(", file);
7617 output_addr_const (file, XEXP (x, 1));
7620 else if (GET_CODE (x) == CONST_DOUBLE
7621 && (GET_MODE (x) == VOIDmode
7622 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
7624 if (CONST_DOUBLE_HIGH (x) == 0)
7625 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
7626 else if (CONST_DOUBLE_HIGH (x) == -1
7627 && CONST_DOUBLE_LOW (x) < 0)
7628 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
7630 output_operand_lossage ("long long constant not a valid immediate operand");
7632 else if (GET_CODE (x) == CONST_DOUBLE)
7633 output_operand_lossage ("floating point constant not a valid immediate operand");
7634 else { output_addr_const (file, x); }
7637 /* Target hook for assembling integer objects. The sparc version has
7638 special handling for aligned DI-mode objects. */
7641 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7643 /* ??? We only output .xword's for symbols and only then in environments
7644 where the assembler can handle them. */
7645 if (aligned_p && size == 8
7646 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7650 assemble_integer_with_op ("\t.xword\t", x);
7655 assemble_aligned_integer (4, const0_rtx);
7656 assemble_aligned_integer (4, x);
7660 return default_assemble_integer (x, size, aligned_p);
7663 /* Return the value of a code used in the .proc pseudo-op that says
7664 what kind of result this function returns. For non-C types, we pick
7665 the closest C type. */
7667 #ifndef SHORT_TYPE_SIZE
7668 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7671 #ifndef INT_TYPE_SIZE
7672 #define INT_TYPE_SIZE BITS_PER_WORD
7675 #ifndef LONG_TYPE_SIZE
7676 #define LONG_TYPE_SIZE BITS_PER_WORD
7679 #ifndef LONG_LONG_TYPE_SIZE
7680 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7683 #ifndef FLOAT_TYPE_SIZE
7684 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7687 #ifndef DOUBLE_TYPE_SIZE
7688 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7691 #ifndef LONG_DOUBLE_TYPE_SIZE
7692 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7696 sparc_type_code (register tree type)
7698 register unsigned long qualifiers = 0;
7699 register unsigned shift;
7701 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7702 setting more, since some assemblers will give an error for this. Also,
7703 we must be careful to avoid shifts of 32 bits or more to avoid getting
7704 unpredictable results. */
7706 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7708 switch (TREE_CODE (type))
7714 qualifiers |= (3 << shift);
7719 qualifiers |= (2 << shift);
7723 case REFERENCE_TYPE:
7725 qualifiers |= (1 << shift);
7729 return (qualifiers | 8);
7732 case QUAL_UNION_TYPE:
7733 return (qualifiers | 9);
7736 return (qualifiers | 10);
7739 return (qualifiers | 16);
7742 /* If this is a range type, consider it to be the underlying
7744 if (TREE_TYPE (type) != 0)
7747 /* Carefully distinguish all the standard types of C,
7748 without messing up if the language is not C. We do this by
7749 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
7750 look at both the names and the above fields, but that's redundant.
7751 Any type whose size is between two C types will be considered
7752 to be the wider of the two types. Also, we do not have a
7753 special code to use for "long long", so anything wider than
7754 long is treated the same. Note that we can't distinguish
7755 between "int" and "long" in this code if they are the same
7756 size, but that's fine, since neither can the assembler. */
7758 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7759 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
7761 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7762 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
7764 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7765 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
7768 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
7771 /* If this is a range type, consider it to be the underlying
7773 if (TREE_TYPE (type) != 0)
7776 /* Carefully distinguish all the standard types of C,
7777 without messing up if the language is not C. */
7779 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7780 return (qualifiers | 6);
7783 return (qualifiers | 7);
7785 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7786 /* ??? We need to distinguish between double and float complex types,
7787 but I don't know how yet because I can't reach this code from
7788 existing front-ends. */
7789 return (qualifiers | 7); /* Who knows? */
7792 case BOOLEAN_TYPE: /* Boolean truth value type. */
7798 gcc_unreachable (); /* Not a type! */
7805 /* Nested function support. */
7807 /* Emit RTL insns to initialize the variable parts of a trampoline.
7808 FNADDR is an RTX for the address of the function's pure code.
7809 CXT is an RTX for the static chain value for the function.
7811 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7812 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7813 (to store insns). This is a bit excessive. Perhaps a different
7814 mechanism would be better here.
7816 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7819 sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
7821 /* SPARC 32-bit trampoline:
7824 sethi %hi(static), %g2
7826 or %g2, %lo(static), %g2
7828 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7829 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7833 (adjust_address (m_tramp, SImode, 0),
7834 expand_binop (SImode, ior_optab,
7835 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7836 size_int (10), 0, 1),
7837 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7838 NULL_RTX, 1, OPTAB_DIRECT));
7841 (adjust_address (m_tramp, SImode, 4),
7842 expand_binop (SImode, ior_optab,
7843 expand_shift (RSHIFT_EXPR, SImode, cxt,
7844 size_int (10), 0, 1),
7845 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7846 NULL_RTX, 1, OPTAB_DIRECT));
7849 (adjust_address (m_tramp, SImode, 8),
7850 expand_binop (SImode, ior_optab,
7851 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7852 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7853 NULL_RTX, 1, OPTAB_DIRECT));
7856 (adjust_address (m_tramp, SImode, 12),
7857 expand_binop (SImode, ior_optab,
7858 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7859 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7860 NULL_RTX, 1, OPTAB_DIRECT));
7862 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7863 aligned on a 16 byte boundary so one flush clears it all. */
7864 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 0))));
7865 if (sparc_cpu != PROCESSOR_ULTRASPARC
7866 && sparc_cpu != PROCESSOR_ULTRASPARC3
7867 && sparc_cpu != PROCESSOR_NIAGARA
7868 && sparc_cpu != PROCESSOR_NIAGARA2)
7869 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 8))));
7871 /* Call __enable_execute_stack after writing onto the stack to make sure
7872 the stack address is accessible. */
7873 #ifdef ENABLE_EXECUTE_STACK
7874 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7875 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
7880 /* The 64-bit version is simpler because it makes more sense to load the
7881 values as "immediate" data out of the trampoline. It's also easier since
7882 we can read the PC without clobbering a register. */
7885 sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
7887 /* SPARC 64-bit trampoline:
7896 emit_move_insn (adjust_address (m_tramp, SImode, 0),
7897 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7898 emit_move_insn (adjust_address (m_tramp, SImode, 4),
7899 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7900 emit_move_insn (adjust_address (m_tramp, SImode, 8),
7901 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7902 emit_move_insn (adjust_address (m_tramp, SImode, 12),
7903 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7904 emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt);
7905 emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr);
7906 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0))));
7908 if (sparc_cpu != PROCESSOR_ULTRASPARC
7909 && sparc_cpu != PROCESSOR_ULTRASPARC3
7910 && sparc_cpu != PROCESSOR_NIAGARA
7911 && sparc_cpu != PROCESSOR_NIAGARA2)
7912 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8))));
7914 /* Call __enable_execute_stack after writing onto the stack to make sure
7915 the stack address is accessible. */
7916 #ifdef ENABLE_EXECUTE_STACK
7917 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7918 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
7922 /* Worker for TARGET_TRAMPOLINE_INIT. */
7925 sparc_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
7927 rtx fnaddr = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0));
7928 cxt = force_reg (Pmode, cxt);
7930 sparc64_initialize_trampoline (m_tramp, fnaddr, cxt);
7932 sparc32_initialize_trampoline (m_tramp, fnaddr, cxt);
7935 /* Adjust the cost of a scheduling dependency. Return the new cost of
7936 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7939 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7941 enum attr_type insn_type;
7943 if (! recog_memoized (insn))
7946 insn_type = get_attr_type (insn);
7948 if (REG_NOTE_KIND (link) == 0)
7950 /* Data dependency; DEP_INSN writes a register that INSN reads some
7953 /* if a load, then the dependence must be on the memory address;
7954 add an extra "cycle". Note that the cost could be two cycles
7955 if the reg was written late in an instruction group; we ca not tell
7957 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7960 /* Get the delay only if the address of the store is the dependence. */
7961 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7963 rtx pat = PATTERN(insn);
7964 rtx dep_pat = PATTERN (dep_insn);
7966 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7967 return cost; /* This should not happen! */
7969 /* The dependency between the two instructions was on the data that
7970 is being stored. Assume that this implies that the address of the
7971 store is not dependent. */
7972 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7975 return cost + 3; /* An approximation. */
7978 /* A shift instruction cannot receive its data from an instruction
7979 in the same cycle; add a one cycle penalty. */
7980 if (insn_type == TYPE_SHIFT)
7981 return cost + 3; /* Split before cascade into shift. */
7985 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7986 INSN writes some cycles later. */
7988 /* These are only significant for the fpu unit; writing a fp reg before
7989 the fpu has finished with it stalls the processor. */
7991 /* Reusing an integer register causes no problems. */
7992 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8000 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8002 enum attr_type insn_type, dep_type;
8003 rtx pat = PATTERN(insn);
8004 rtx dep_pat = PATTERN (dep_insn);
8006 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
8009 insn_type = get_attr_type (insn);
8010 dep_type = get_attr_type (dep_insn);
8012 switch (REG_NOTE_KIND (link))
8015 /* Data dependency; DEP_INSN writes a register that INSN reads some
8022 /* Get the delay iff the address of the store is the dependence. */
8023 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8026 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8033 /* If a load, then the dependence must be on the memory address. If
8034 the addresses aren't equal, then it might be a false dependency */
8035 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
8037 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
8038 || GET_CODE (SET_DEST (dep_pat)) != MEM
8039 || GET_CODE (SET_SRC (pat)) != MEM
8040 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
8041 XEXP (SET_SRC (pat), 0)))
8049 /* Compare to branch latency is 0. There is no benefit from
8050 separating compare and branch. */
8051 if (dep_type == TYPE_COMPARE)
8053 /* Floating point compare to branch latency is less than
8054 compare to conditional move. */
8055 if (dep_type == TYPE_FPCMP)
8064 /* Anti-dependencies only penalize the fpu unit. */
8065 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8077 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8081 case PROCESSOR_SUPERSPARC:
8082 cost = supersparc_adjust_cost (insn, link, dep, cost);
8084 case PROCESSOR_HYPERSPARC:
8085 case PROCESSOR_SPARCLITE86X:
8086 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8095 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8096 int sched_verbose ATTRIBUTE_UNUSED,
8097 int max_ready ATTRIBUTE_UNUSED)
8101 sparc_use_sched_lookahead (void)
8103 if (sparc_cpu == PROCESSOR_NIAGARA
8104 || sparc_cpu == PROCESSOR_NIAGARA2)
8106 if (sparc_cpu == PROCESSOR_ULTRASPARC
8107 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8109 if ((1 << sparc_cpu) &
8110 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8111 (1 << PROCESSOR_SPARCLITE86X)))
8117 sparc_issue_rate (void)
8121 case PROCESSOR_NIAGARA:
8122 case PROCESSOR_NIAGARA2:
8126 /* Assume V9 processors are capable of at least dual-issue. */
8128 case PROCESSOR_SUPERSPARC:
8130 case PROCESSOR_HYPERSPARC:
8131 case PROCESSOR_SPARCLITE86X:
8133 case PROCESSOR_ULTRASPARC:
8134 case PROCESSOR_ULTRASPARC3:
8140 set_extends (rtx insn)
8142 register rtx pat = PATTERN (insn);
8144 switch (GET_CODE (SET_SRC (pat)))
8146 /* Load and some shift instructions zero extend. */
8149 /* sethi clears the high bits */
8151 /* LO_SUM is used with sethi. sethi cleared the high
8152 bits and the values used with lo_sum are positive */
8154 /* Store flag stores 0 or 1 */
8164 rtx op0 = XEXP (SET_SRC (pat), 0);
8165 rtx op1 = XEXP (SET_SRC (pat), 1);
8166 if (GET_CODE (op1) == CONST_INT)
8167 return INTVAL (op1) >= 0;
8168 if (GET_CODE (op0) != REG)
8170 if (sparc_check_64 (op0, insn) == 1)
8172 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8177 rtx op0 = XEXP (SET_SRC (pat), 0);
8178 rtx op1 = XEXP (SET_SRC (pat), 1);
8179 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8181 if (GET_CODE (op1) == CONST_INT)
8182 return INTVAL (op1) >= 0;
8183 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8186 return GET_MODE (SET_SRC (pat)) == SImode;
8187 /* Positive integers leave the high bits zero. */
8189 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8191 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8194 return - (GET_MODE (SET_SRC (pat)) == SImode);
8196 return sparc_check_64 (SET_SRC (pat), insn);
8202 /* We _ought_ to have only one kind per function, but... */
8203 static GTY(()) rtx sparc_addr_diff_list;
8204 static GTY(()) rtx sparc_addr_list;
8207 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8209 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8211 sparc_addr_diff_list
8212 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8214 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8218 sparc_output_addr_vec (rtx vec)
8220 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8221 int idx, vlen = XVECLEN (body, 0);
8223 #ifdef ASM_OUTPUT_ADDR_VEC_START
8224 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8227 #ifdef ASM_OUTPUT_CASE_LABEL
8228 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8231 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8234 for (idx = 0; idx < vlen; idx++)
8236 ASM_OUTPUT_ADDR_VEC_ELT
8237 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8240 #ifdef ASM_OUTPUT_ADDR_VEC_END
8241 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8246 sparc_output_addr_diff_vec (rtx vec)
8248 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8249 rtx base = XEXP (XEXP (body, 0), 0);
8250 int idx, vlen = XVECLEN (body, 1);
8252 #ifdef ASM_OUTPUT_ADDR_VEC_START
8253 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8256 #ifdef ASM_OUTPUT_CASE_LABEL
8257 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8260 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8263 for (idx = 0; idx < vlen; idx++)
8265 ASM_OUTPUT_ADDR_DIFF_ELT
8268 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8269 CODE_LABEL_NUMBER (base));
8272 #ifdef ASM_OUTPUT_ADDR_VEC_END
8273 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8278 sparc_output_deferred_case_vectors (void)
8283 if (sparc_addr_list == NULL_RTX
8284 && sparc_addr_diff_list == NULL_RTX)
8287 /* Align to cache line in the function's code section. */
8288 switch_to_section (current_function_section ());
8290 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8292 ASM_OUTPUT_ALIGN (asm_out_file, align);
8294 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8295 sparc_output_addr_vec (XEXP (t, 0));
8296 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8297 sparc_output_addr_diff_vec (XEXP (t, 0));
8299 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8302 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8303 unknown. Return 1 if the high bits are zero, -1 if the register is
8306 sparc_check_64 (rtx x, rtx insn)
8308 /* If a register is set only once it is safe to ignore insns this
8309 code does not know how to handle. The loop will either recognize
8310 the single set and return the correct value or fail to recognize
8315 gcc_assert (GET_CODE (x) == REG);
8317 if (GET_MODE (x) == DImode)
8318 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8320 if (flag_expensive_optimizations
8321 && df && DF_REG_DEF_COUNT (REGNO (y)) == 1)
8327 insn = get_last_insn_anywhere ();
8332 while ((insn = PREV_INSN (insn)))
8334 switch (GET_CODE (insn))
8347 rtx pat = PATTERN (insn);
8348 if (GET_CODE (pat) != SET)
8350 if (rtx_equal_p (x, SET_DEST (pat)))
8351 return set_extends (insn);
8352 if (y && rtx_equal_p (y, SET_DEST (pat)))
8353 return set_extends (insn);
8354 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8362 /* Returns assembly code to perform a DImode shift using
8363 a 64-bit global or out register on SPARC-V8+. */
8365 output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8367 static char asm_code[60];
8369 /* The scratch register is only required when the destination
8370 register is not a 64-bit global or out register. */
8371 if (which_alternative != 2)
8372 operands[3] = operands[0];
8374 /* We can only shift by constants <= 63. */
8375 if (GET_CODE (operands[2]) == CONST_INT)
8376 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8378 if (GET_CODE (operands[1]) == CONST_INT)
8380 output_asm_insn ("mov\t%1, %3", operands);
8384 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8385 if (sparc_check_64 (operands[1], insn) <= 0)
8386 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8387 output_asm_insn ("or\t%L1, %3, %3", operands);
8390 strcpy(asm_code, opcode);
8392 if (which_alternative != 2)
8393 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8395 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8398 /* Output rtl to increment the profiler label LABELNO
8399 for profiling a function entry. */
8402 sparc_profile_hook (int labelno)
8407 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8408 if (NO_PROFILE_COUNTERS)
8410 emit_library_call (fun, LCT_NORMAL, VOIDmode, 0);
8414 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8415 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8416 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8420 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
8423 sparc_solaris_elf_asm_named_section (const char *name, unsigned int flags,
8424 tree decl ATTRIBUTE_UNUSED)
8426 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8428 if (!(flags & SECTION_DEBUG))
8429 fputs (",#alloc", asm_out_file);
8430 if (flags & SECTION_WRITE)
8431 fputs (",#write", asm_out_file);
8432 if (flags & SECTION_TLS)
8433 fputs (",#tls", asm_out_file);
8434 if (flags & SECTION_CODE)
8435 fputs (",#execinstr", asm_out_file);
8437 /* ??? Handle SECTION_BSS. */
8439 fputc ('\n', asm_out_file);
8442 /* We do not allow indirect calls to be optimized into sibling calls.
8444 We cannot use sibling calls when delayed branches are disabled
8445 because they will likely require the call delay slot to be filled.
8447 Also, on SPARC 32-bit we cannot emit a sibling call when the
8448 current function returns a structure. This is because the "unimp
8449 after call" convention would cause the callee to return to the
8450 wrong place. The generic code already disallows cases where the
8451 function being called returns a structure.
8453 It may seem strange how this last case could occur. Usually there
8454 is code after the call which jumps to epilogue code which dumps the
8455 return value into the struct return area. That ought to invalidate
8456 the sibling call right? Well, in the C++ case we can end up passing
8457 the pointer to the struct return area to a constructor (which returns
8458 void) and then nothing else happens. Such a sibling call would look
8459 valid without the added check here.
8461 VxWorks PIC PLT entries require the global pointer to be initialized
8462 on entry. We therefore can't emit sibling calls to them. */
8464 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8467 && flag_delayed_branch
8468 && (TARGET_ARCH64 || ! cfun->returns_struct)
8469 && !(TARGET_VXWORKS_RTP
8471 && !targetm.binds_local_p (decl)));
8474 /* libfunc renaming. */
8477 sparc_init_libfuncs (void)
8481 /* Use the subroutines that Sun's library provides for integer
8482 multiply and divide. The `*' prevents an underscore from
8483 being prepended by the compiler. .umul is a little faster
8485 set_optab_libfunc (smul_optab, SImode, "*.umul");
8486 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8487 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8488 set_optab_libfunc (smod_optab, SImode, "*.rem");
8489 set_optab_libfunc (umod_optab, SImode, "*.urem");
8491 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8492 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8493 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8494 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8495 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8496 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8498 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8499 is because with soft-float, the SFmode and DFmode sqrt
8500 instructions will be absent, and the compiler will notice and
8501 try to use the TFmode sqrt instruction for calls to the
8502 builtin function sqrt, but this fails. */
8504 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8506 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8507 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8508 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8509 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8510 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8511 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8513 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8514 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8515 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8516 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8518 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8519 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8520 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8521 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_Q_utoq");
8523 if (DITF_CONVERSION_LIBFUNCS)
8525 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
8526 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
8527 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
8528 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq");
8531 if (SUN_CONVERSION_LIBFUNCS)
8533 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8534 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8535 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8536 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8541 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8542 do not exist in the library. Make sure the compiler does not
8543 emit calls to them by accident. (It should always use the
8544 hardware instructions.) */
8545 set_optab_libfunc (smul_optab, SImode, 0);
8546 set_optab_libfunc (sdiv_optab, SImode, 0);
8547 set_optab_libfunc (udiv_optab, SImode, 0);
8548 set_optab_libfunc (smod_optab, SImode, 0);
8549 set_optab_libfunc (umod_optab, SImode, 0);
8551 if (SUN_INTEGER_MULTIPLY_64)
8553 set_optab_libfunc (smul_optab, DImode, "__mul64");
8554 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8555 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8556 set_optab_libfunc (smod_optab, DImode, "__rem64");
8557 set_optab_libfunc (umod_optab, DImode, "__urem64");
8560 if (SUN_CONVERSION_LIBFUNCS)
8562 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8563 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8564 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8565 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8570 #define def_builtin(NAME, CODE, TYPE) \
8571 add_builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \
8574 /* Implement the TARGET_INIT_BUILTINS target hook.
8575 Create builtin functions for special SPARC instructions. */
8578 sparc_init_builtins (void)
8581 sparc_vis_init_builtins ();
8584 /* Create builtin functions for VIS 1.0 instructions. */
8587 sparc_vis_init_builtins (void)
8589 tree v4qi = build_vector_type (unsigned_intQI_type_node, 4);
8590 tree v8qi = build_vector_type (unsigned_intQI_type_node, 8);
8591 tree v4hi = build_vector_type (intHI_type_node, 4);
8592 tree v2hi = build_vector_type (intHI_type_node, 2);
8593 tree v2si = build_vector_type (intSI_type_node, 2);
8595 tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0);
8596 tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0);
8597 tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0);
8598 tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0);
8599 tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0);
8600 tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0);
8601 tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0);
8602 tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0);
8603 tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0);
8604 tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0);
8605 tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0);
8606 tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0);
8607 tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node,
8609 intDI_type_node, 0);
8610 tree di_ftype_di_di = build_function_type_list (intDI_type_node,
8612 intDI_type_node, 0);
8613 tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node,
8615 intSI_type_node, 0);
8616 tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node,
8618 intDI_type_node, 0);
8620 /* Packing and expanding vectors. */
8621 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis, v4qi_ftype_v4hi);
8622 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
8623 v8qi_ftype_v2si_v8qi);
8624 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
8626 def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis, v4hi_ftype_v4qi);
8627 def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis,
8628 v8qi_ftype_v4qi_v4qi);
8630 /* Multiplications. */
8631 def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis,
8632 v4hi_ftype_v4qi_v4hi);
8633 def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis,
8634 v4hi_ftype_v4qi_v2hi);
8635 def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis,
8636 v4hi_ftype_v4qi_v2hi);
8637 def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis,
8638 v4hi_ftype_v8qi_v4hi);
8639 def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis,
8640 v4hi_ftype_v8qi_v4hi);
8641 def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis,
8642 v2si_ftype_v4qi_v2hi);
8643 def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis,
8644 v2si_ftype_v4qi_v2hi);
8646 /* Data aligning. */
8647 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
8648 v4hi_ftype_v4hi_v4hi);
8649 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
8650 v8qi_ftype_v8qi_v8qi);
8651 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
8652 v2si_ftype_v2si_v2si);
8653 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis,
8656 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
8659 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
8662 /* Pixel distance. */
8663 def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
8664 di_ftype_v8qi_v8qi_di);
8667 /* Handle TARGET_EXPAND_BUILTIN target hook.
8668 Expand builtin functions for sparc intrinsics. */
8671 sparc_expand_builtin (tree exp, rtx target,
8672 rtx subtarget ATTRIBUTE_UNUSED,
8673 enum machine_mode tmode ATTRIBUTE_UNUSED,
8674 int ignore ATTRIBUTE_UNUSED)
8677 call_expr_arg_iterator iter;
8678 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8679 unsigned int icode = DECL_FUNCTION_CODE (fndecl);
8681 enum machine_mode mode[4];
8684 mode[0] = insn_data[icode].operand[0].mode;
8686 || GET_MODE (target) != mode[0]
8687 || ! (*insn_data[icode].operand[0].predicate) (target, mode[0]))
8688 op[0] = gen_reg_rtx (mode[0]);
8692 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
8695 mode[arg_count] = insn_data[icode].operand[arg_count].mode;
8696 op[arg_count] = expand_normal (arg);
8698 if (! (*insn_data[icode].operand[arg_count].predicate) (op[arg_count],
8700 op[arg_count] = copy_to_mode_reg (mode[arg_count], op[arg_count]);
8706 pat = GEN_FCN (icode) (op[0], op[1]);
8709 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
8712 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
8727 sparc_vis_mul8x16 (int e8, int e16)
8729 return (e8 * e16 + 128) / 256;
8732 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
8733 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
8734 constants. A tree list with the results of the multiplications is returned,
8735 and each element in the list is of INNER_TYPE. */
8738 sparc_handle_vis_mul8x16 (int fncode, tree inner_type, tree elts0, tree elts1)
8740 tree n_elts = NULL_TREE;
8745 case CODE_FOR_fmul8x16_vis:
8746 for (; elts0 && elts1;
8747 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
8750 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
8751 TREE_INT_CST_LOW (TREE_VALUE (elts1)));
8752 n_elts = tree_cons (NULL_TREE,
8753 build_int_cst (inner_type, val),
8758 case CODE_FOR_fmul8x16au_vis:
8759 scale = TREE_INT_CST_LOW (TREE_VALUE (elts1));
8761 for (; elts0; elts0 = TREE_CHAIN (elts0))
8764 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
8766 n_elts = tree_cons (NULL_TREE,
8767 build_int_cst (inner_type, val),
8772 case CODE_FOR_fmul8x16al_vis:
8773 scale = TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1)));
8775 for (; elts0; elts0 = TREE_CHAIN (elts0))
8778 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
8780 n_elts = tree_cons (NULL_TREE,
8781 build_int_cst (inner_type, val),
8790 return nreverse (n_elts);
8793 /* Handle TARGET_FOLD_BUILTIN target hook.
8794 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
8795 result of the function call is ignored. NULL_TREE is returned if the
8796 function could not be folded. */
8799 sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED,
8800 tree *args, bool ignore)
8802 tree arg0, arg1, arg2;
8803 tree rtype = TREE_TYPE (TREE_TYPE (fndecl));
8804 enum insn_code icode = (enum insn_code) DECL_FUNCTION_CODE (fndecl);
8807 && icode != CODE_FOR_alignaddrsi_vis
8808 && icode != CODE_FOR_alignaddrdi_vis)
8809 return build_zero_cst (rtype);
8813 case CODE_FOR_fexpand_vis:
8817 if (TREE_CODE (arg0) == VECTOR_CST)
8819 tree inner_type = TREE_TYPE (rtype);
8820 tree elts = TREE_VECTOR_CST_ELTS (arg0);
8821 tree n_elts = NULL_TREE;
8823 for (; elts; elts = TREE_CHAIN (elts))
8825 unsigned int val = TREE_INT_CST_LOW (TREE_VALUE (elts)) << 4;
8826 n_elts = tree_cons (NULL_TREE,
8827 build_int_cst (inner_type, val),
8830 return build_vector (rtype, nreverse (n_elts));
8834 case CODE_FOR_fmul8x16_vis:
8835 case CODE_FOR_fmul8x16au_vis:
8836 case CODE_FOR_fmul8x16al_vis:
8842 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
8844 tree inner_type = TREE_TYPE (rtype);
8845 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
8846 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
8847 tree n_elts = sparc_handle_vis_mul8x16 (icode, inner_type, elts0,
8850 return build_vector (rtype, n_elts);
8854 case CODE_FOR_fpmerge_vis:
8860 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
8862 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
8863 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
8864 tree n_elts = NULL_TREE;
8866 for (; elts0 && elts1;
8867 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
8869 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts0), n_elts);
8870 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts1), n_elts);
8873 return build_vector (rtype, nreverse (n_elts));
8877 case CODE_FOR_pdist_vis:
8885 if (TREE_CODE (arg0) == VECTOR_CST
8886 && TREE_CODE (arg1) == VECTOR_CST
8887 && TREE_CODE (arg2) == INTEGER_CST)
8890 unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (arg2);
8891 HOST_WIDE_INT high = TREE_INT_CST_HIGH (arg2);
8892 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
8893 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
8895 for (; elts0 && elts1;
8896 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
8898 unsigned HOST_WIDE_INT
8899 low0 = TREE_INT_CST_LOW (TREE_VALUE (elts0)),
8900 low1 = TREE_INT_CST_LOW (TREE_VALUE (elts1));
8901 HOST_WIDE_INT high0 = TREE_INT_CST_HIGH (TREE_VALUE (elts0));
8902 HOST_WIDE_INT high1 = TREE_INT_CST_HIGH (TREE_VALUE (elts1));
8904 unsigned HOST_WIDE_INT l;
8907 overflow |= neg_double (low1, high1, &l, &h);
8908 overflow |= add_double (low0, high0, l, h, &l, &h);
8910 overflow |= neg_double (l, h, &l, &h);
8912 overflow |= add_double (low, high, l, h, &low, &high);
8915 gcc_assert (overflow == 0);
8917 return build_int_cst_wide (rtype, low, high);
8927 /* ??? This duplicates information provided to the compiler by the
8928 ??? scheduler description. Some day, teach genautomata to output
8929 ??? the latencies and then CSE will just use that. */
8932 sparc_rtx_costs (rtx x, int code, int outer_code, int *total,
8933 bool speed ATTRIBUTE_UNUSED)
8935 enum machine_mode mode = GET_MODE (x);
8936 bool float_mode_p = FLOAT_MODE_P (mode);
8941 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8959 if (GET_MODE (x) == VOIDmode
8960 && ((CONST_DOUBLE_HIGH (x) == 0
8961 && CONST_DOUBLE_LOW (x) < 0x1000)
8962 || (CONST_DOUBLE_HIGH (x) == -1
8963 && CONST_DOUBLE_LOW (x) < 0
8964 && CONST_DOUBLE_LOW (x) >= -0x1000)))
8971 /* If outer-code was a sign or zero extension, a cost
8972 of COSTS_N_INSNS (1) was already added in. This is
8973 why we are subtracting it back out. */
8974 if (outer_code == ZERO_EXTEND)
8976 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
8978 else if (outer_code == SIGN_EXTEND)
8980 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
8982 else if (float_mode_p)
8984 *total = sparc_costs->float_load;
8988 *total = sparc_costs->int_load;
8996 *total = sparc_costs->float_plusminus;
8998 *total = COSTS_N_INSNS (1);
9003 *total = sparc_costs->float_mul;
9004 else if (! TARGET_HARD_MUL)
9005 *total = COSTS_N_INSNS (25);
9011 if (sparc_costs->int_mul_bit_factor)
9015 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
9017 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
9018 for (nbits = 0; value != 0; value &= value - 1)
9021 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
9022 && GET_MODE (XEXP (x, 1)) == VOIDmode)
9024 rtx x1 = XEXP (x, 1);
9025 unsigned HOST_WIDE_INT value1 = CONST_DOUBLE_LOW (x1);
9026 unsigned HOST_WIDE_INT value2 = CONST_DOUBLE_HIGH (x1);
9028 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
9030 for (; value2 != 0; value2 &= value2 - 1)
9038 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
9039 bit_cost = COSTS_N_INSNS (bit_cost);
9043 *total = sparc_costs->int_mulX + bit_cost;
9045 *total = sparc_costs->int_mul + bit_cost;
9052 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
9062 *total = sparc_costs->float_div_df;
9064 *total = sparc_costs->float_div_sf;
9069 *total = sparc_costs->int_divX;
9071 *total = sparc_costs->int_div;
9078 *total = COSTS_N_INSNS (1);
9085 case UNSIGNED_FLOAT:
9089 case FLOAT_TRUNCATE:
9090 *total = sparc_costs->float_move;
9095 *total = sparc_costs->float_sqrt_df;
9097 *total = sparc_costs->float_sqrt_sf;
9102 *total = sparc_costs->float_cmp;
9104 *total = COSTS_N_INSNS (1);
9109 *total = sparc_costs->float_cmove;
9111 *total = sparc_costs->int_cmove;
9115 /* Handle the NAND vector patterns. */
9116 if (sparc_vector_mode_supported_p (GET_MODE (x))
9117 && GET_CODE (XEXP (x, 0)) == NOT
9118 && GET_CODE (XEXP (x, 1)) == NOT)
9120 *total = COSTS_N_INSNS (1);
9131 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
9132 This is achieved by means of a manual dynamic stack space allocation in
9133 the current frame. We make the assumption that SEQ doesn't contain any
9134 function calls, with the possible exception of calls to the GOT helper. */
9137 emit_and_preserve (rtx seq, rtx reg, rtx reg2)
9139 /* We must preserve the lowest 16 words for the register save area. */
9140 HOST_WIDE_INT offset = 16*UNITS_PER_WORD;
9141 /* We really need only 2 words of fresh stack space. */
9142 HOST_WIDE_INT size = SPARC_STACK_ALIGN (offset + 2*UNITS_PER_WORD);
9145 = gen_rtx_MEM (word_mode, plus_constant (stack_pointer_rtx,
9146 SPARC_STACK_BIAS + offset));
9148 emit_insn (gen_stack_pointer_dec (GEN_INT (size)));
9149 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
9151 emit_insn (gen_rtx_SET (VOIDmode,
9152 adjust_address (slot, word_mode, UNITS_PER_WORD),
9156 emit_insn (gen_rtx_SET (VOIDmode,
9158 adjust_address (slot, word_mode, UNITS_PER_WORD)));
9159 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
9160 emit_insn (gen_stack_pointer_inc (GEN_INT (size)));
9163 /* Output the assembler code for a thunk function. THUNK_DECL is the
9164 declaration for the thunk function itself, FUNCTION is the decl for
9165 the target function. DELTA is an immediate constant offset to be
9166 added to THIS. If VCALL_OFFSET is nonzero, the word at address
9167 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
9170 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
9171 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9174 rtx this_rtx, insn, funexp;
9175 unsigned int int_arg_first;
9177 reload_completed = 1;
9178 epilogue_completed = 1;
9180 emit_note (NOTE_INSN_PROLOGUE_END);
9182 if (flag_delayed_branch)
9184 /* We will emit a regular sibcall below, so we need to instruct
9185 output_sibcall that we are in a leaf function. */
9186 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 1;
9188 /* This will cause final.c to invoke leaf_renumber_regs so we
9189 must behave as if we were in a not-yet-leafified function. */
9190 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
9194 /* We will emit the sibcall manually below, so we will need to
9195 manually spill non-leaf registers. */
9196 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 0;
9198 /* We really are in a leaf function. */
9199 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
9202 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
9203 returns a structure, the structure return pointer is there instead. */
9205 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9206 this_rtx = gen_rtx_REG (Pmode, int_arg_first + 1);
9208 this_rtx = gen_rtx_REG (Pmode, int_arg_first);
9210 /* Add DELTA. When possible use a plain add, otherwise load it into
9211 a register first. */
9214 rtx delta_rtx = GEN_INT (delta);
9216 if (! SPARC_SIMM13_P (delta))
9218 rtx scratch = gen_rtx_REG (Pmode, 1);
9219 emit_move_insn (scratch, delta_rtx);
9220 delta_rtx = scratch;
9223 /* THIS_RTX += DELTA. */
9224 emit_insn (gen_add2_insn (this_rtx, delta_rtx));
9227 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
9230 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
9231 rtx scratch = gen_rtx_REG (Pmode, 1);
9233 gcc_assert (vcall_offset < 0);
9235 /* SCRATCH = *THIS_RTX. */
9236 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this_rtx));
9238 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
9239 may not have any available scratch register at this point. */
9240 if (SPARC_SIMM13_P (vcall_offset))
9242 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
9243 else if (! fixed_regs[5]
9244 /* The below sequence is made up of at least 2 insns,
9245 while the default method may need only one. */
9246 && vcall_offset < -8192)
9248 rtx scratch2 = gen_rtx_REG (Pmode, 5);
9249 emit_move_insn (scratch2, vcall_offset_rtx);
9250 vcall_offset_rtx = scratch2;
9254 rtx increment = GEN_INT (-4096);
9256 /* VCALL_OFFSET is a negative number whose typical range can be
9257 estimated as -32768..0 in 32-bit mode. In almost all cases
9258 it is therefore cheaper to emit multiple add insns than
9259 spilling and loading the constant into a register (at least
9261 while (! SPARC_SIMM13_P (vcall_offset))
9263 emit_insn (gen_add2_insn (scratch, increment));
9264 vcall_offset += 4096;
9266 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
9269 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
9270 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
9271 gen_rtx_PLUS (Pmode,
9273 vcall_offset_rtx)));
9275 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
9276 emit_insn (gen_add2_insn (this_rtx, scratch));
9279 /* Generate a tail call to the target function. */
9280 if (! TREE_USED (function))
9282 assemble_external (function);
9283 TREE_USED (function) = 1;
9285 funexp = XEXP (DECL_RTL (function), 0);
9287 if (flag_delayed_branch)
9289 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
9290 insn = emit_call_insn (gen_sibcall (funexp));
9291 SIBLING_CALL_P (insn) = 1;
9295 /* The hoops we have to jump through in order to generate a sibcall
9296 without using delay slots... */
9297 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
9301 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
9303 /* Delay emitting the GOT helper function because it needs to
9304 change the section and we are emitting assembly code. */
9305 load_got_register (); /* clobbers %o7 */
9306 scratch = sparc_legitimize_pic_address (funexp, scratch);
9309 emit_and_preserve (seq, spill_reg, pic_offset_table_rtx);
9311 else if (TARGET_ARCH32)
9313 emit_insn (gen_rtx_SET (VOIDmode,
9315 gen_rtx_HIGH (SImode, funexp)));
9316 emit_insn (gen_rtx_SET (VOIDmode,
9318 gen_rtx_LO_SUM (SImode, scratch, funexp)));
9320 else /* TARGET_ARCH64 */
9322 switch (sparc_cmodel)
9326 /* The destination can serve as a temporary. */
9327 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
9332 /* The destination cannot serve as a temporary. */
9333 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
9335 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
9338 emit_and_preserve (seq, spill_reg, 0);
9346 emit_jump_insn (gen_indirect_jump (scratch));
9351 /* Run just enough of rest_of_compilation to get the insns emitted.
9352 There's not really enough bulk here to make other passes such as
9353 instruction scheduling worth while. Note that use_thunk calls
9354 assemble_start_function and assemble_end_function. */
9355 insn = get_insns ();
9356 insn_locators_alloc ();
9357 shorten_branches (insn);
9358 final_start_function (insn, file, 1);
9359 final (insn, file, 1);
9360 final_end_function ();
9362 reload_completed = 0;
9363 epilogue_completed = 0;
9366 /* Return true if sparc_output_mi_thunk would be able to output the
9367 assembler code for the thunk function specified by the arguments
9368 it is passed, and false otherwise. */
9370 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
9371 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
9372 HOST_WIDE_INT vcall_offset,
9373 const_tree function ATTRIBUTE_UNUSED)
9375 /* Bound the loop used in the default method above. */
9376 return (vcall_offset >= -32768 || ! fixed_regs[5]);
9379 /* How to allocate a 'struct machine_function'. */
9381 static struct machine_function *
9382 sparc_init_machine_status (void)
9384 return ggc_alloc_cleared_machine_function ();
9387 /* Locate some local-dynamic symbol still in use by this function
9388 so that we can print its name in local-dynamic base patterns. */
9391 get_some_local_dynamic_name (void)
9395 if (cfun->machine->some_ld_name)
9396 return cfun->machine->some_ld_name;
9398 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9400 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
9401 return cfun->machine->some_ld_name;
9407 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9412 && GET_CODE (x) == SYMBOL_REF
9413 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9415 cfun->machine->some_ld_name = XSTR (x, 0);
9422 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
9423 This is called from dwarf2out.c to emit call frame instructions
9424 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
9426 sparc_dwarf_handle_frame_unspec (const char *label,
9427 rtx pattern ATTRIBUTE_UNUSED,
9428 int index ATTRIBUTE_UNUSED)
9430 gcc_assert (index == UNSPECV_SAVEW);
9431 dwarf2out_window_save (label);
9434 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9435 We need to emit DTP-relative relocations. */
9438 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
9443 fputs ("\t.word\t%r_tls_dtpoff32(", file);
9446 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
9451 output_addr_const (file, x);
9455 /* Do whatever processing is required at the end of a file. */
9458 sparc_file_end (void)
9460 /* If we need to emit the special GOT helper function, do so now. */
9463 const char *name = XSTR (got_helper_rtx, 0);
9464 const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
9465 #ifdef DWARF2_UNWIND_INFO
9469 if (USE_HIDDEN_LINKONCE)
9471 tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
9472 get_identifier (name),
9473 build_function_type (void_type_node,
9475 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
9476 NULL_TREE, void_type_node);
9477 TREE_STATIC (decl) = 1;
9478 make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl));
9479 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
9480 DECL_VISIBILITY_SPECIFIED (decl) = 1;
9481 resolve_unique_section (decl, 0, flag_function_sections);
9482 allocate_struct_function (decl, true);
9484 current_function_decl = decl;
9485 init_varasm_status ();
9486 assemble_start_function (decl, name);
9490 const int align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
9491 switch_to_section (text_section);
9493 ASM_OUTPUT_ALIGN (asm_out_file, align);
9494 ASM_OUTPUT_LABEL (asm_out_file, name);
9497 #ifdef DWARF2_UNWIND_INFO
9498 do_cfi = dwarf2out_do_cfi_asm ();
9500 fprintf (asm_out_file, "\t.cfi_startproc\n");
9502 if (flag_delayed_branch)
9503 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
9504 reg_name, reg_name);
9506 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
9507 reg_name, reg_name);
9508 #ifdef DWARF2_UNWIND_INFO
9510 fprintf (asm_out_file, "\t.cfi_endproc\n");
9514 if (NEED_INDICATE_EXEC_STACK)
9515 file_end_indicate_exec_stack ();
9518 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9519 /* Implement TARGET_MANGLE_TYPE. */
9522 sparc_mangle_type (const_tree type)
9525 && TYPE_MAIN_VARIANT (type) == long_double_type_node
9526 && TARGET_LONG_DOUBLE_128)
9529 /* For all other types, use normal C++ mangling. */
9534 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
9535 compare and swap on the word containing the byte or half-word. */
9538 sparc_expand_compare_and_swap_12 (rtx result, rtx mem, rtx oldval, rtx newval)
9540 rtx addr1 = force_reg (Pmode, XEXP (mem, 0));
9541 rtx addr = gen_reg_rtx (Pmode);
9542 rtx off = gen_reg_rtx (SImode);
9543 rtx oldv = gen_reg_rtx (SImode);
9544 rtx newv = gen_reg_rtx (SImode);
9545 rtx oldvalue = gen_reg_rtx (SImode);
9546 rtx newvalue = gen_reg_rtx (SImode);
9547 rtx res = gen_reg_rtx (SImode);
9548 rtx resv = gen_reg_rtx (SImode);
9549 rtx memsi, val, mask, end_label, loop_label, cc;
9551 emit_insn (gen_rtx_SET (VOIDmode, addr,
9552 gen_rtx_AND (Pmode, addr1, GEN_INT (-4))));
9554 if (Pmode != SImode)
9555 addr1 = gen_lowpart (SImode, addr1);
9556 emit_insn (gen_rtx_SET (VOIDmode, off,
9557 gen_rtx_AND (SImode, addr1, GEN_INT (3))));
9559 memsi = gen_rtx_MEM (SImode, addr);
9560 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
9561 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
9563 val = force_reg (SImode, memsi);
9565 emit_insn (gen_rtx_SET (VOIDmode, off,
9566 gen_rtx_XOR (SImode, off,
9567 GEN_INT (GET_MODE (mem) == QImode
9570 emit_insn (gen_rtx_SET (VOIDmode, off,
9571 gen_rtx_ASHIFT (SImode, off, GEN_INT (3))));
9573 if (GET_MODE (mem) == QImode)
9574 mask = force_reg (SImode, GEN_INT (0xff));
9576 mask = force_reg (SImode, GEN_INT (0xffff));
9578 emit_insn (gen_rtx_SET (VOIDmode, mask,
9579 gen_rtx_ASHIFT (SImode, mask, off)));
9581 emit_insn (gen_rtx_SET (VOIDmode, val,
9582 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
9585 oldval = gen_lowpart (SImode, oldval);
9586 emit_insn (gen_rtx_SET (VOIDmode, oldv,
9587 gen_rtx_ASHIFT (SImode, oldval, off)));
9589 newval = gen_lowpart_common (SImode, newval);
9590 emit_insn (gen_rtx_SET (VOIDmode, newv,
9591 gen_rtx_ASHIFT (SImode, newval, off)));
9593 emit_insn (gen_rtx_SET (VOIDmode, oldv,
9594 gen_rtx_AND (SImode, oldv, mask)));
9596 emit_insn (gen_rtx_SET (VOIDmode, newv,
9597 gen_rtx_AND (SImode, newv, mask)));
9599 end_label = gen_label_rtx ();
9600 loop_label = gen_label_rtx ();
9601 emit_label (loop_label);
9603 emit_insn (gen_rtx_SET (VOIDmode, oldvalue,
9604 gen_rtx_IOR (SImode, oldv, val)));
9606 emit_insn (gen_rtx_SET (VOIDmode, newvalue,
9607 gen_rtx_IOR (SImode, newv, val)));
9609 emit_insn (gen_sync_compare_and_swapsi (res, memsi, oldvalue, newvalue));
9611 emit_cmp_and_jump_insns (res, oldvalue, EQ, NULL, SImode, 0, end_label);
9613 emit_insn (gen_rtx_SET (VOIDmode, resv,
9614 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
9617 cc = gen_compare_reg_1 (NE, resv, val);
9618 emit_insn (gen_rtx_SET (VOIDmode, val, resv));
9620 /* Use cbranchcc4 to separate the compare and branch! */
9621 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode, cc, const0_rtx),
9622 cc, const0_rtx, loop_label));
9624 emit_label (end_label);
9626 emit_insn (gen_rtx_SET (VOIDmode, res,
9627 gen_rtx_AND (SImode, res, mask)));
9629 emit_insn (gen_rtx_SET (VOIDmode, res,
9630 gen_rtx_LSHIFTRT (SImode, res, off)));
9632 emit_move_insn (result, gen_lowpart (GET_MODE (result), res));
9635 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9638 sparc_frame_pointer_required (void)
9640 return !(leaf_function_p () && only_leaf_regs_used ());
9643 /* The way this is structured, we can't eliminate SFP in favor of SP
9644 if the frame pointer is required: we want to use the SFP->HFP elimination
9645 in that case. But the test in update_eliminables doesn't know we are
9646 assuming below that we only do the former elimination. */
9649 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9651 return (to == HARD_FRAME_POINTER_REGNUM
9652 || !targetm.frame_pointer_required ());
9655 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
9656 they won't be allocated. */
9659 sparc_conditional_register_usage (void)
9661 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
9663 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9664 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9666 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
9667 /* then honor it. */
9668 if (TARGET_ARCH32 && fixed_regs[5])
9670 else if (TARGET_ARCH64 && fixed_regs[5] == 2)
9675 for (regno = SPARC_FIRST_V9_FP_REG;
9676 regno <= SPARC_LAST_V9_FP_REG;
9678 fixed_regs[regno] = 1;
9679 /* %fcc0 is used by v8 and v9. */
9680 for (regno = SPARC_FIRST_V9_FCC_REG + 1;
9681 regno <= SPARC_LAST_V9_FCC_REG;
9683 fixed_regs[regno] = 1;
9688 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++)
9689 fixed_regs[regno] = 1;
9691 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
9692 /* then honor it. Likewise with g3 and g4. */
9693 if (fixed_regs[2] == 2)
9694 fixed_regs[2] = ! TARGET_APP_REGS;
9695 if (fixed_regs[3] == 2)
9696 fixed_regs[3] = ! TARGET_APP_REGS;
9697 if (TARGET_ARCH32 && fixed_regs[4] == 2)
9698 fixed_regs[4] = ! TARGET_APP_REGS;
9699 else if (TARGET_CM_EMBMEDANY)
9701 else if (fixed_regs[4] == 2)
9705 /* Implement TARGET_PREFERRED_RELOAD_CLASS
9707 - We can't load constants into FP registers.
9708 - We can't load FP constants into integer registers when soft-float,
9709 because there is no soft-float pattern with a r/F constraint.
9710 - We can't load FP constants into integer registers for TFmode unless
9711 it is 0.0L, because there is no movtf pattern with a r/F constraint.
9712 - Try and reload integer constants (symbolic or otherwise) back into
9713 registers directly, rather than having them dumped to memory. */
9716 sparc_preferred_reload_class (rtx x, reg_class_t rclass)
9720 if (FP_REG_CLASS_P (rclass)
9721 || rclass == GENERAL_OR_FP_REGS
9722 || rclass == GENERAL_OR_EXTRA_FP_REGS
9723 || (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT && ! TARGET_FPU)
9724 || (GET_MODE (x) == TFmode && ! const_zero_operand (x, TFmode)))
9727 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
9728 return GENERAL_REGS;
9734 #include "gt-sparc.h"