1 ;; DFA scheduling description for SH4.
2 ;; Copyright (C) 2004, 2006 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19 ;; Boston, MA 02110-1301, USA.
21 ;; Load and store instructions save a cycle if they are aligned on a
22 ;; four byte boundary. Using a function unit for stores encourages
23 ;; gcc to separate load and store instructions by one instruction,
24 ;; which makes it more likely that the linker will be able to word
25 ;; align them when relaxing.
27 ;; The following description models the SH4 pipeline using the DFA based
28 ;; scheduler. The DFA based description is better way to model a
29 ;; superscalar pipeline as compared to function unit reservation model.
30 ;; 1. The function unit based model is oriented to describe at most one
31 ;; unit reservation by each insn. It is difficult to model unit reservations
32 ;; in multiple pipeline units by same insn. This can be done using DFA
34 ;; 2. The execution performance of DFA based scheduler does not depend on
35 ;; processor complexity.
36 ;; 3. Writing all unit reservations for an instruction class is a more natural
37 ;; description of the pipeline and makes the interface to the hazard
38 ;; recognizer simpler than the old function unit based model.
39 ;; 4. The DFA model is richer and is a part of greater overall framework
43 ;; Two automata are defined to reduce number of states
44 ;; which a single large automaton will have. (Factoring)
46 (define_automaton "inst_pipeline,fpu_pipe")
48 ;; This unit is basically the decode unit of the processor.
49 ;; Since SH4 is a dual issue machine,it is as if there are two
50 ;; units so that any insn can be processed by either one
51 ;; of the decoding unit.
53 (define_cpu_unit "pipe_01,pipe_02" "inst_pipeline")
56 ;; The fixed point arithmetic calculator(?? EX Unit).
58 (define_cpu_unit "int" "inst_pipeline")
60 ;; f1_1 and f1_2 are floating point units.Actually there is
61 ;; a f1 unit which can overlap with other f1 unit but
62 ;; not another F1 unit.It is as though there were two
65 (define_cpu_unit "f1_1,f1_2" "fpu_pipe")
67 ;; The floating point units (except FS - F2 always precedes it.)
69 (define_cpu_unit "F0,F1,F2,F3" "fpu_pipe")
71 ;; This is basically the MA unit of SH4
72 ;; used in LOAD/STORE pipeline.
74 (define_cpu_unit "memory" "inst_pipeline")
76 ;; However, there are LS group insns that don't use it, even ones that
77 ;; complete in 0 cycles. So we use an extra unit for the issue of LS insns.
78 (define_cpu_unit "load_store" "inst_pipeline")
80 ;; The address calculator used for branch instructions.
81 ;; This will be reserved after "issue" of branch instructions
82 ;; and this is to make sure that no two branch instructions
83 ;; can be issued in parallel.
85 (define_cpu_unit "pcr_addrcalc" "inst_pipeline")
87 ;; ----------------------------------------------------
88 ;; This reservation is to simplify the dual issue description.
90 (define_reservation "issue" "pipe_01|pipe_02")
92 ;; This is to express the locking of D stage.
93 ;; Note that the issue of a CO group insn also effectively locks the D stage.
95 (define_reservation "d_lock" "pipe_01+pipe_02")
97 ;; Every FE instruction but fipr / ftrv starts with issue and this.
98 (define_reservation "F01" "F0+F1")
100 ;; This is to simplify description where F1,F2,FS
101 ;; are used simultaneously.
103 (define_reservation "fpu" "F1+F2")
105 ;; This is to highlight the fact that f1
106 ;; cannot overlap with F1.
108 (exclusion_set "f1_1,f1_2" "F1")
110 (define_insn_reservation "nil" 0 (eq_attr "type" "nil") "nothing")
112 ;; Although reg moves have a latency of zero
113 ;; we need to highlight that they use D stage
118 (define_insn_reservation "reg_mov" 0
119 (and (eq_attr "pipe_model" "sh4")
120 (eq_attr "type" "move"))
125 (define_insn_reservation "freg_mov" 0
126 (and (eq_attr "pipe_model" "sh4")
127 (eq_attr "type" "fmove"))
130 ;; We don't model all pipeline stages; we model the issue ('D') stage
131 ;; inasmuch as we allow only two instructions to issue simultaneously,
132 ;; and CO instructions prevent any simultaneous issue of another instruction.
133 ;; (This uses pipe_01 and pipe_02).
134 ;; Double issue of EX insns is prevented by using the int unit in the EX stage.
135 ;; Double issue of EX / BR insns is prevented by using the int unit /
136 ;; pcr_addrcalc unit in the EX stage.
137 ;; Double issue of BR / LS instructions is prevented by using the
138 ;; pcr_addrcalc / load_store unit in the issue cycle.
139 ;; Double issue of FE instructions is prevented by using F0 in the first
140 ;; pipeline stage after the first D stage.
141 ;; There is no need to describe the [ES]X / [MN]A / S stages after a D stage
142 ;; (except in the cases outlined above), nor to describe the FS stage after
145 ;; Other MT group instructions(1 step operations)
150 (define_insn_reservation "mt" 1
151 (and (eq_attr "pipe_model" "sh4")
152 (eq_attr "type" "mt_group"))
155 ;; Fixed Point Arithmetic Instructions(1 step operations)
160 (define_insn_reservation "sh4_simple_arith" 1
161 (and (eq_attr "pipe_model" "sh4")
162 (eq_attr "insn_class" "ex_group"))
165 ;; Load and store instructions have no alignment peculiarities for the SH4,
166 ;; but they use the load-store unit, which they share with the fmove type
167 ;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
168 ;; Loads have a latency of two.
169 ;; However, call insns can only paired with a preceding insn, and have
170 ;; a delay slot, so that we want two more insns to be scheduled between the
171 ;; load of the function address and the call. This is equivalent to a
173 ;; ADJUST_COST can only properly handle reductions of the cost, so we
174 ;; use a latency of three here, which gets multiplied by 10 to yield 30.
175 ;; We only do this for SImode loads of general registers, to make the work
176 ;; for ADJUST_COST easier.
178 ;; Load Store instructions. (MOV.[BWL]@(d,GBR)
183 (define_insn_reservation "sh4_load" 2
184 (and (eq_attr "pipe_model" "sh4")
185 (eq_attr "type" "load,pcload"))
186 "issue+load_store,nothing,memory")
188 ;; calls / sfuncs need an extra instruction for their delay slot.
189 ;; Moreover, estimating the latency for SImode loads as 3 will also allow
190 ;; adjust_cost to meaningfully bump it back up to 3 if they load the shift
191 ;; count of a dynamic shift.
192 (define_insn_reservation "sh4_load_si" 3
193 (and (eq_attr "pipe_model" "sh4")
194 (eq_attr "type" "load_si,pcload_si"))
195 "issue+load_store,nothing,memory")
197 ;; (define_bypass 2 "sh4_load_si" "!sh4_call")
199 ;; The load latency is upped to three higher if the dependent insn does
200 ;; double precision computation. We want the 'default' latency to reflect
201 ;; that increased latency because otherwise the insn priorities won't
202 ;; allow proper scheduling.
203 (define_insn_reservation "sh4_fload" 3
204 (and (eq_attr "pipe_model" "sh4")
205 (eq_attr "type" "fload,pcfload"))
206 "issue+load_store,nothing,memory")
208 ;; (define_bypass 2 "sh4_fload" "!")
210 (define_insn_reservation "sh4_store" 1
211 (and (eq_attr "pipe_model" "sh4")
212 (eq_attr "type" "store,fstore"))
213 "issue+load_store,nothing,memory")
215 (define_insn_reservation "mac_mem" 1
216 (and (eq_attr "pipe_model" "sh4")
217 (eq_attr "type" "mac_mem"))
218 "d_lock,nothing,memory")
220 ;; Load Store instructions.
225 (define_insn_reservation "sh4_gp_fpul" 1
226 (and (eq_attr "pipe_model" "sh4")
227 (eq_attr "type" "gp_fpul"))
230 ;; Load Store instructions.
235 (define_insn_reservation "sh4_fpul_gp" 3
236 (and (eq_attr "pipe_model" "sh4")
237 (eq_attr "type" "fpul_gp"))
240 ;; Branch (BF,BF/S,BT,BT/S,BRA)
242 ;; Latency when taken: 2 (or 1)
244 ;; The latency is 1 when displacement is 0.
245 ;; We can't really do much with the latency, even if we could express it,
246 ;; but the pairing restrictions are useful to take into account.
247 ;; ??? If the branch is likely, we might want to fill the delay slot;
248 ;; if the branch is likely, but not very likely, should we pretend to use
249 ;; a resource that CO instructions use, to get a pairable delay slot insn?
251 (define_insn_reservation "sh4_branch" 1
252 (and (eq_attr "pipe_model" "sh4")
253 (eq_attr "type" "cbranch,jump"))
254 "issue+pcr_addrcalc")
256 ;; Branch Far (JMP,RTS,BRAF)
260 ;; ??? Scheduling happens before branch shortening, and hence jmp and braf
261 ;; can't be distinguished from bra for the "jump" pattern.
263 (define_insn_reservation "sh4_return" 3
264 (and (eq_attr "pipe_model" "sh4")
265 (eq_attr "type" "return,jump_ind"))
272 ;; this instruction can be executed in any of the pipelines
273 ;; and blocks the pipeline for next 4 stages.
275 (define_insn_reservation "sh4_return_from_exp" 5
276 (and (eq_attr "pipe_model" "sh4")
277 (eq_attr "type" "rte"))
285 ;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2
286 ;; ocbwb on its own would be "d_lock,nothing,memory*5"
287 (define_insn_reservation "ocbwb" 6
288 (and (eq_attr "pipe_model" "sh4")
289 (eq_attr "type" "cwb"))
290 "d_lock*2,(d_lock+memory)*3,issue+load_store+memory,memory*2")
296 ;; The SX stage is blocked for last 2 cycles.
297 ;; OTOH, the only time that has an effect for insns generated by the compiler
298 ;; is when lds to PR is followed by sts from PR - and that is highly unlikely -
299 ;; or when we are doing a function call - and we don't do inter-function
300 ;; scheduling. For the function call case, it's really best that we end with
301 ;; something that models an rts.
303 (define_insn_reservation "sh4_lds_to_pr" 3
304 (and (eq_attr "pipe_model" "sh4")
305 (eq_attr "type" "prset") )
308 ;; calls introduce a longisch delay that is likely to flush the pipelines
309 ;; of the caller's instructions. Ordinary functions tend to end with a
310 ;; load to restore a register (in the delay slot of rts), while sfuncs
311 ;; tend to end with an EX or MT insn. But that is not actually relevant,
312 ;; since there are no instructions that contend for memory access early.
313 ;; We could, of course, provide exact scheduling information for specific
314 ;; sfuncs, if that should prove useful.
316 (define_insn_reservation "sh4_call" 16
317 (and (eq_attr "pipe_model" "sh4")
318 (eq_attr "type" "call,sfunc"))
325 ;; The SX unit is blocked for last 2 cycles.
327 (define_insn_reservation "ldsmem_to_pr" 3
328 (and (eq_attr "pipe_model" "sh4")
329 (eq_attr "type" "pload"))
336 ;; The SX unit in second and third cycles.
338 (define_insn_reservation "sts_from_pr" 2
339 (and (eq_attr "pipe_model" "sh4")
340 (eq_attr "type" "prget"))
348 (define_insn_reservation "sh4_prstore_mem" 2
349 (and (eq_attr "pipe_model" "sh4")
350 (eq_attr "type" "pstore"))
351 "d_lock*2,nothing,memory")
357 ;; F1 is blocked for last three cycles.
359 (define_insn_reservation "fpscr_load" 4
360 (and (eq_attr "pipe_model" "sh4")
361 (eq_attr "type" "gp_fpscr"))
362 "d_lock,nothing,F1*3")
367 ;; Latency to update Rn is 1 and latency to update FPSCR is 4
369 ;; F1 is blocked for last three cycles.
371 (define_insn_reservation "fpscr_load_mem" 4
372 (and (eq_attr "pipe_model" "sh4")
373 (eq_attr "type" "mem_fpscr"))
374 "d_lock,nothing,(F1+memory),F1*2")
377 ;; Fixed point multiplication (DMULS.L DMULU.L MUL.L MULS.W,MULU.W)
382 (define_insn_reservation "multi" 4
383 (and (eq_attr "pipe_model" "sh4")
384 (eq_attr "type" "smpy,dmpy"))
385 "d_lock,(d_lock+f1_1),(f1_1|f1_2)*3,F2")
387 ;; Fixed STS from, and LDS to MACL / MACH
392 (define_insn_reservation "sh4_mac_gp" 3
393 (and (eq_attr "pipe_model" "sh4")
394 (eq_attr "type" "mac_gp,gp_mac,mem_mac"))
398 ;; Single precision floating point computation FCMP/EQ,
399 ;; FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRCHG, FSCHG
404 (define_insn_reservation "fp_arith" 3
405 (and (eq_attr "pipe_model" "sh4")
406 (eq_attr "type" "fp,fp_cmp"))
409 ;; We don't model the resource usage of this exactly because that would
410 ;; introduce a bogus latency.
411 (define_insn_reservation "sh4_fpscr_toggle" 1
412 (and (eq_attr "pipe_model" "sh4")
413 (eq_attr "type" "fpscr_toggle"))
416 (define_insn_reservation "fp_arith_ftrc" 3
417 (and (eq_attr "pipe_model" "sh4")
418 (eq_attr "type" "ftrc_s"))
421 (define_bypass 1 "fp_arith_ftrc" "sh4_fpul_gp")
423 ;; Single Precision FDIV/SQRT
425 ;; Latency: 12/13 (FDIV); 11/12 (FSQRT)
427 ;; We describe fdiv here; fsqrt is actually one cycle faster.
429 (define_insn_reservation "fp_div" 12
430 (and (eq_attr "pipe_model" "sh4")
431 (eq_attr "type" "fdiv"))
432 "issue,F01+F3,F2+F3,F3*7,F1+F3,F2")
434 ;; Double Precision floating point computation
435 ;; (FCNVDS, FCNVSD, FLOAT, FTRC)
440 (define_insn_reservation "dp_float" 4
441 (and (eq_attr "pipe_model" "sh4")
442 (eq_attr "type" "dfp_conv"))
443 "issue,F01,F1+F2,F2")
445 ;; Double-precision floating-point (FADD,FMUL,FSUB)
450 (define_insn_reservation "fp_double_arith" 8
451 (and (eq_attr "pipe_model" "sh4")
452 (eq_attr "type" "dfp_arith,dfp_mul"))
453 "issue,F01,F1+F2,fpu*4,F2")
455 ;; Double-precision FCMP (FCMP/EQ,FCMP/GT)
460 (define_insn_reservation "fp_double_cmp" 3
461 (and (eq_attr "pipe_model" "sh4")
462 (eq_attr "type" "dfp_cmp"))
463 "d_lock,(d_lock+F01),F1+F2,F2")
465 ;; Double precision FDIV/SQRT
467 ;; Latency: (24,25)/26
470 (define_insn_reservation "dp_div" 25
471 (and (eq_attr "pipe_model" "sh4")
472 (eq_attr "type" "dfdiv"))
473 "issue,F01+F3,F1+F2+F3,F2+F3,F3*16,F1+F3,(fpu+F3)*2,F2")
476 ;; Use the branch-not-taken case to model arith3 insns. For the branch taken
477 ;; case, we'd get a d_lock instead of issue at the end.
478 (define_insn_reservation "arith3" 3
479 (and (eq_attr "pipe_model" "sh4")
480 (eq_attr "type" "arith3"))
481 "issue,d_lock+pcr_addrcalc,issue")
483 ;; arith3b insns schedule the same no matter if the branch is taken or not.
484 (define_insn_reservation "arith3b" 2
485 (and (eq_attr "pipe_model" "sh4")
486 (eq_attr "type" "arith3"))
487 "issue,d_lock+pcr_addrcalc")