1 ;;- Machine description for the Hitachi SH.
2 ;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
5 ;; Improved by Jim Wilson (wilson@cygnus.com).
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
25 ;; ??? Should prepend a * to all pattern names which are not used.
26 ;; This will make the compiler smaller, and rebuilds after changes faster.
28 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
29 ;; sequences. Especially the sequences for arithmetic right shifts.
31 ;; ??? Should check all DImode patterns for consistency and usefulness.
33 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
34 ;; way to generate them.
36 ;; ??? The cmp/str instruction is not supported. Perhaps it can be used
37 ;; for a str* inline function.
39 ;; BSR is not generated by the compiler proper, but when relaxing, it
40 ;; generates .uses pseudo-ops that allow linker relaxation to create
41 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
43 ;; Special constraints for SH machine description:
50 ;; Special formats used for outputting SH instructions:
52 ;; %. -- print a .s if insn needs delay slot
53 ;; %@ -- print rte/rts if is/isn't an interrupt function
54 ;; %# -- output a nop if there is nothing to put in the delay slot
55 ;; %O -- print a constant without the #
56 ;; %R -- print the lsw reg of a double
57 ;; %S -- print the msw reg of a double
58 ;; %T -- print next word of a double REG or MEM
60 ;; Special predicates:
62 ;; arith_operand -- operand is valid source for arithmetic op
63 ;; arith_reg_operand -- operand is valid register for arithmetic op
64 ;; general_movdst_operand -- operand is valid move destination
65 ;; general_movsrc_operand -- operand is valid move source
66 ;; logical_operand -- operand is valid source for logical op
68 ;; -------------------------------------------------------------------------
70 ;; -------------------------------------------------------------------------
102 ;; These are used with unspec.
114 ;; These are used with unspec_volatile.
120 (UNSPECV_CONST_END 11)
123 ;; -------------------------------------------------------------------------
125 ;; -------------------------------------------------------------------------
130 "sh1,sh2,sh3,sh3e,sh4"
131 (const (symbol_ref "sh_cpu_attr")))
133 (define_attr "endian" "big,little"
134 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
135 (const_string "little") (const_string "big"))))
137 ;; Indicate if the default fpu mode is single precision.
138 (define_attr "fpu_single" "yes,no"
139 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
140 (const_string "yes") (const_string "no"))))
142 (define_attr "fmovd" "yes,no"
143 (const (if_then_else (symbol_ref "TARGET_FMOVD")
144 (const_string "yes") (const_string "no"))))
146 (define_attr "issues" "1,2"
147 (const (if_then_else (symbol_ref "TARGET_SUPERSCALAR") (const_string "2") (const_string "1"))))
149 ;; cbranch conditional branch instructions
150 ;; jump unconditional jumps
151 ;; arith ordinary arithmetic
152 ;; arith3 a compound insn that behaves similarly to a sequence of
153 ;; three insns of type arith
154 ;; arith3b like above, but might end with a redirected branch
156 ;; load_si Likewise, SImode variant for general register.
158 ;; move register to register
159 ;; fmove register to register, floating point
160 ;; smpy word precision integer multiply
161 ;; dmpy longword or doublelongword precision integer multiply
163 ;; pload load of pr reg, which can't be put into delay slot of rts
164 ;; prset copy register to pr reg, ditto
165 ;; pstore store of pr reg, which can't be put into delay slot of jsr
166 ;; prget copy pr to register, ditto
167 ;; pcload pc relative load of constant value
168 ;; pcload_si Likewise, SImode variant for general register.
169 ;; rte return from exception
170 ;; sfunc special function call with known used registers
171 ;; call function call
173 ;; fdiv floating point divide (or square root)
174 ;; gp_fpul move between general purpose register and fpul
175 ;; dfp_arith, dfp_cmp,dfp_conv
176 ;; dfdiv double precision floating point divide (or square root)
177 ;; nil no-op move, will be deleted.
180 "cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,other,load,load_si,store,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,rte,sfunc,call,fp,fdiv,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,nil"
181 (const_string "other"))
183 ;; Indicate what precision must be selected in fpscr for this insn, if any.
185 (define_attr "fp_mode" "single,double,none" (const_string "none"))
187 ; If a conditional branch destination is within -252..258 bytes away
188 ; from the instruction it can be 2 bytes long. Something in the
189 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
190 ; branches are initially assumed to be 16 bytes long.
191 ; In machine_dependent_reorg, we split all branches that are longer than
194 ;; The maximum range used for SImode constant pool entries is 1018. A final
195 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
196 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
197 ;; instruction around the pool table, 2 bytes of alignment before the table,
198 ;; and 30 bytes of alignment after the table. That gives a maximum total
199 ;; pool size of 1058 bytes.
200 ;; Worst case code/pool content size ratio is 1:2 (using asms).
201 ;; Thus, in the worst case, there is one instruction in front of a maximum
202 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
203 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
204 ;; If we have a forward branch, the initial table will be put after the
205 ;; unconditional branch.
207 ;; ??? We could do much better by keeping track of the actual pcloads within
208 ;; the branch range and in the pcload range in front of the branch range.
210 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
212 (define_attr "short_cbranch_p" "no,yes"
213 (cond [(ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
215 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
217 (ne (symbol_ref "NEXT_INSN (PREV_INSN (insn)) != insn") (const_int 0))
219 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
221 ] (const_string "no")))
223 (define_attr "med_branch_p" "no,yes"
224 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
227 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
229 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
232 ] (const_string "no")))
234 (define_attr "med_cbranch_p" "no,yes"
235 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
238 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
240 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
243 ] (const_string "no")))
245 (define_attr "braf_branch_p" "no,yes"
246 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
248 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
251 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
253 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
256 ] (const_string "no")))
258 (define_attr "braf_cbranch_p" "no,yes"
259 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
261 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
264 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
266 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
269 ] (const_string "no")))
271 ; An unconditional jump in the range -4092..4098 can be 2 bytes long.
272 ; For wider ranges, we need a combination of a code and a data part.
273 ; If we can get a scratch register for a long range jump, the code
274 ; part can be 4 bytes long; otherwise, it must be 8 bytes long.
275 ; If the jump is in the range -32764..32770, the data part can be 2 bytes
276 ; long; otherwise, it must be 6 bytes long.
278 ; All other instructions are two bytes long by default.
280 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
281 ;; but getattrtab doesn't understand this.
282 (define_attr "length" ""
283 (cond [(eq_attr "type" "cbranch")
284 (cond [(eq_attr "short_cbranch_p" "yes")
286 (eq_attr "med_cbranch_p" "yes")
288 (eq_attr "braf_cbranch_p" "yes")
290 ;; ??? using pc is not computed transitively.
291 (ne (match_dup 0) (match_dup 0))
293 (ne (symbol_ref ("flag_pic")) (const_int 0))
296 (eq_attr "type" "jump")
297 (cond [(eq_attr "med_branch_p" "yes")
299 (and (eq (symbol_ref "GET_CODE (PREV_INSN (insn))")
301 (eq (symbol_ref "INSN_CODE (PREV_INSN (insn))")
302 (symbol_ref "code_for_indirect_jump_scratch")))
303 (if_then_else (eq_attr "braf_branch_p" "yes")
306 (eq_attr "braf_branch_p" "yes")
308 ;; ??? using pc is not computed transitively.
309 (ne (match_dup 0) (match_dup 0))
311 (ne (symbol_ref ("flag_pic")) (const_int 0))
316 ;; (define_function_unit {name} {num-units} {n-users} {test}
317 ;; {ready-delay} {issue-delay} [{conflict-list}])
319 ;; Load and store instructions save a cycle if they are aligned on a
320 ;; four byte boundary. Using a function unit for stores encourages
321 ;; gcc to separate load and store instructions by one instruction,
322 ;; which makes it more likely that the linker will be able to word
323 ;; align them when relaxing.
325 ;; Loads have a latency of two.
326 ;; However, call insns can have a delay slot, so that we want one more
327 ;; insn to be scheduled between the load of the function address and the call.
328 ;; This is equivalent to a latency of three.
329 ;; We cannot use a conflict list for this, because we need to distinguish
330 ;; between the actual call address and the function arguments.
331 ;; ADJUST_COST can only properly handle reductions of the cost, so we
332 ;; use a latency of three here.
333 ;; We only do this for SImode loads of general registers, to make the work
334 ;; for ADJUST_COST easier.
335 (define_function_unit "memory" 1 0
336 (and (eq_attr "issues" "1")
337 (eq_attr "type" "load_si,pcload_si"))
339 (define_function_unit "memory" 1 0
340 (and (eq_attr "issues" "1")
341 (eq_attr "type" "load,pcload,pload,store,pstore"))
344 (define_function_unit "int" 1 0
345 (and (eq_attr "issues" "1") (eq_attr "type" "arith3,arith3b")) 3 3)
347 (define_function_unit "int" 1 0
348 (and (eq_attr "issues" "1") (eq_attr "type" "dyn_shift")) 2 2)
350 (define_function_unit "int" 1 0
351 (and (eq_attr "issues" "1") (eq_attr "type" "!arith3,arith3b,dyn_shift")) 1 1)
353 ;; ??? These are approximations.
354 (define_function_unit "mpy" 1 0
355 (and (eq_attr "issues" "1") (eq_attr "type" "smpy")) 2 2)
356 (define_function_unit "mpy" 1 0
357 (and (eq_attr "issues" "1") (eq_attr "type" "dmpy")) 3 3)
359 (define_function_unit "fp" 1 0
360 (and (eq_attr "issues" "1") (eq_attr "type" "fp,fmove")) 2 1)
361 (define_function_unit "fp" 1 0
362 (and (eq_attr "issues" "1") (eq_attr "type" "fdiv")) 13 12)
366 ;; The SH4 is a dual-issue implementation, thus we have to multiply all
367 ;; costs by at least two.
368 ;; There will be single increments of the modeled that don't correspond
369 ;; to the actual target ;; whenever two insns to be issued depend one a
370 ;; single resource, and the scheduler picks to be the first one.
371 ;; If we multiplied the costs just by two, just two of these single
372 ;; increments would amount to an actual cycle. By picking a larger
373 ;; factor, we can ameliorate the effect; However, we then have to make sure
374 ;; that only two insns are modeled as issued per actual cycle.
375 ;; Moreover, we need a way to specify the latency of insns that don't
376 ;; use an actual function unit.
377 ;; We use an 'issue' function unit to do that, and a cost factor of 10.
379 (define_function_unit "issue" 2 0
380 (and (eq_attr "issues" "2") (eq_attr "type" "!nil,arith3"))
383 (define_function_unit "issue" 2 0
384 (and (eq_attr "issues" "2") (eq_attr "type" "arith3"))
387 ;; There is no point in providing exact scheduling information about branches,
388 ;; because they are at the starts / ends of basic blocks anyways.
390 ;; Some insns cannot be issued before/after another insn in the same cycle,
391 ;; irrespective of the type of the other insn.
393 ;; default is dual-issue, but can't be paired with an insn that
394 ;; uses multiple function units.
395 (define_function_unit "single_issue" 1 0
396 (and (eq_attr "issues" "2")
397 (eq_attr "type" "!smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul,call,sfunc,arith3,arith3b"))
399 [(eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul")])
401 (define_function_unit "single_issue" 1 0
402 (and (eq_attr "issues" "2")
403 (eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul"))
407 ;; arith3 insns are always pairable at the start, but not inecessarily at
408 ;; the end; however, there doesn;t seem to be a way to express that.
409 (define_function_unit "single_issue" 1 0
410 (and (eq_attr "issues" "2")
411 (eq_attr "type" "arith3"))
415 ;; arith3b insn are pairable at the end and have latency that prevents pairing
416 ;; with the following branch, but we don't want this latency be respected;
417 ;; When the following branch is immediately adjacent, we can redirect the
418 ;; internal branch, which is likly to be a larger win.
419 (define_function_unit "single_issue" 1 0
420 (and (eq_attr "issues" "2")
421 (eq_attr "type" "arith3b"))
425 ;; calls introduce a longisch delay that is likely to flush the pipelines.
426 (define_function_unit "single_issue" 1 0
427 (and (eq_attr "issues" "2")
428 (eq_attr "type" "call,sfunc"))
430 [(eq_attr "type" "!call") (eq_attr "type" "call")])
432 ;; Load and store instructions have no alignment peculiarities for the SH4,
433 ;; but they use the load-store unit, which they share with the fmove type
434 ;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
435 ;; Loads have a latency of two.
436 ;; However, call insns can only paired with a preceding insn, and have
437 ;; a delay slot, so that we want two more insns to be scheduled between the
438 ;; load of the function address and the call. This is equivalent to a
440 ;; We cannot use a conflict list for this, because we need to distinguish
441 ;; between the actual call address and the function arguments.
442 ;; ADJUST_COST can only properly handle reductions of the cost, so we
443 ;; use a latency of three here, which gets multiplied by 10 to yield 30.
444 ;; We only do this for SImode loads of general registers, to make the work
445 ;; for ADJUST_COST easier.
447 ;; When specifying different latencies for different insns using the
448 ;; the same function unit, genattrtab.c assumes a 'FIFO constraint'
449 ;; so that the blockage is at least READY-COST (E) + 1 - READY-COST (C)
450 ;; for an executing insn E and a candidate insn C.
451 ;; Therefore, we define three different function units for load_store:
452 ;; load_store, load and load_si.
454 (define_function_unit "load_si" 1 0
455 (and (eq_attr "issues" "2")
456 (eq_attr "type" "load_si,pcload_si")) 30 10)
457 (define_function_unit "load" 1 0
458 (and (eq_attr "issues" "2")
459 (eq_attr "type" "load,pcload,pload")) 20 10)
460 (define_function_unit "load_store" 1 0
461 (and (eq_attr "issues" "2")
462 (eq_attr "type" "load_si,pcload_si,load,pcload,pload,store,pstore,fmove"))
465 (define_function_unit "int" 1 0
466 (and (eq_attr "issues" "2") (eq_attr "type" "arith,dyn_shift")) 10 10)
468 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
469 ;; spurious FIFO constraint; the multiply instructions use the "int"
470 ;; unit actually only for two cycles.
471 (define_function_unit "int" 1 0
472 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 20 20)
474 ;; We use a fictous "mpy" unit to express the actual latency.
475 (define_function_unit "mpy" 1 0
476 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 20)
478 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
479 ;; spurious FIFO constraint.
480 (define_function_unit "int" 1 0
481 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 10 10)
483 ;; We use a fictous "gp_fpul" unit to express the actual latency.
484 (define_function_unit "gp_fpul" 1 0
485 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 20 10)
487 ;; ??? multiply uses the floating point unit, but with a two cycle delay.
488 ;; Thus, a simple single-precision fp operation could finish if issued in
489 ;; the very next cycle, but stalls when issued two or three cycles later.
490 ;; Similarily, a divide / sqrt can work without stalls if issued in
491 ;; the very next cycle, while it would have to block if issued two or
492 ;; three cycles later.
493 ;; There is no way to model this with gcc's function units. This problem is
494 ;; actually mentioned in md.texi. Tackling this problem requires first that
495 ;; it is possible to speak about the target in an open discussion.
497 ;; However, simple double-precision operations always conflict.
499 (define_function_unit "fp" 1 0
500 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 40
501 [(eq_attr "type" "dfp_cmp,dfp_conv,dfp_arith")])
503 ;; The "fp" unit is for pipeline stages F1 and F2.
505 (define_function_unit "fp" 1 0
506 (and (eq_attr "issues" "2") (eq_attr "type" "fp")) 30 10)
508 ;; Again, we have to pretend a lower latency for the "fp" unit to avoid a
509 ;; spurious FIFO constraint; the bulk of the fdiv type insns executes in
511 (define_function_unit "fp" 1 0
512 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 30 10)
514 ;; The "fdiv" function unit models the aggregate effect of the F1, F2 and F3
515 ;; pipeline stages on the pipelining of fdiv/fsqrt insns.
516 ;; We also use it to give the actual latency here.
517 ;; fsqrt is actually one cycle faster than fdiv (and the value used here),
518 ;; but that will hardly matter in practice for scheduling.
519 (define_function_unit "fdiv" 1 0
520 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 120 100)
522 ;; There is again a late use of the "fp" unit by [d]fdiv type insns
523 ;; that we can't express.
525 (define_function_unit "fp" 1 0
526 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_cmp,dfp_conv")) 40 20)
528 (define_function_unit "fp" 1 0
529 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_arith")) 80 60)
531 (define_function_unit "fp" 1 0
532 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 10)
534 (define_function_unit "fdiv" 1 0
535 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 210)
537 ; Definitions for filling branch delay slots.
539 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
541 ;; ??? This should be (nil) instead of (const_int 0)
542 (define_attr "hit_stack" "yes,no"
543 (cond [(eq (symbol_ref "find_regno_note (insn, REG_INC, SP_REG)")
546 (const_string "yes")))
548 (define_attr "interrupt_function" "no,yes"
549 (const (symbol_ref "pragma_interrupt")))
551 (define_attr "in_delay_slot" "yes,no"
552 (cond [(eq_attr "type" "cbranch") (const_string "no")
553 (eq_attr "type" "pcload,pcload_si") (const_string "no")
554 (eq_attr "needs_delay_slot" "yes") (const_string "no")
555 (eq_attr "length" "2") (const_string "yes")
556 ] (const_string "no")))
558 (define_attr "is_sfunc" ""
559 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
562 (eq_attr "needs_delay_slot" "yes")
563 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
565 ;; On the SH and SH2, the rte instruction reads the return pc from the stack,
566 ;; and thus we can't put a pop instruction in its delay slot.
567 ;; ??? On the SH3, the rte instruction does not use the stack, so a pop
568 ;; instruction can go in the delay slot.
570 ;; Since a normal return (rts) implicitly uses the PR register,
571 ;; we can't allow PR register loads in an rts delay slot.
574 (eq_attr "type" "return")
575 [(and (eq_attr "in_delay_slot" "yes")
576 (ior (and (eq_attr "interrupt_function" "no")
577 (eq_attr "type" "!pload,prset"))
578 (and (eq_attr "interrupt_function" "yes")
579 (eq_attr "hit_stack" "no")))) (nil) (nil)])
581 ;; Since a call implicitly uses the PR register, we can't allow
582 ;; a PR register store in a jsr delay slot.
585 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
586 [(and (eq_attr "in_delay_slot" "yes")
587 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
589 ;; Say that we have annulled true branches, since this gives smaller and
590 ;; faster code when branches are predicted as not taken.
593 (and (eq_attr "type" "cbranch")
594 (ne (symbol_ref "TARGET_SH2") (const_int 0)))
595 [(eq_attr "in_delay_slot" "yes") (eq_attr "in_delay_slot" "yes") (nil)])
597 ;; -------------------------------------------------------------------------
598 ;; SImode signed integer comparisons
599 ;; -------------------------------------------------------------------------
603 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
604 (match_operand:SI 1 "arith_operand" "L,r"))
609 ;; ??? Perhaps should only accept reg/constant if the register is reg 0.
610 ;; That would still allow reload to create cmpi instructions, but would
611 ;; perhaps allow forcing the constant into a register when that is better.
612 ;; Probably should use r0 for mem/imm compares, but force constant into a
613 ;; register for pseudo/imm compares.
615 (define_insn "cmpeqsi_t"
617 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
618 (match_operand:SI 1 "arith_operand" "N,rI,r")))]
625 (define_insn "cmpgtsi_t"
627 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
628 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
634 (define_insn "cmpgesi_t"
636 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
637 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
643 ;; -------------------------------------------------------------------------
644 ;; SImode unsigned integer comparisons
645 ;; -------------------------------------------------------------------------
647 (define_insn "cmpgeusi_t"
649 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
650 (match_operand:SI 1 "arith_reg_operand" "r")))]
654 (define_insn "cmpgtusi_t"
656 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
657 (match_operand:SI 1 "arith_reg_operand" "r")))]
661 ;; We save the compare operands in the cmpxx patterns and use them when
662 ;; we generate the branch.
664 (define_expand "cmpsi"
666 (compare (match_operand:SI 0 "arith_operand" "")
667 (match_operand:SI 1 "arith_operand" "")))]
671 sh_compare_op0 = operands[0];
672 sh_compare_op1 = operands[1];
676 ;; -------------------------------------------------------------------------
677 ;; DImode signed integer comparisons
678 ;; -------------------------------------------------------------------------
680 ;; ??? Could get better scheduling by splitting the initial test from the
681 ;; rest of the insn after reload. However, the gain would hardly justify
682 ;; the sh.md size increase necessary to do that.
686 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
687 (match_operand:DI 1 "arith_operand" "r"))
690 "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
692 [(set_attr "length" "6")
693 (set_attr "type" "arith3b")])
695 (define_insn "cmpeqdi_t"
697 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
698 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
701 tst %S0,%S0\;bf %,Ldi%=\;tst %R0,%R0\\n%,Ldi%=:
702 cmp/eq %S1,%S0\;bf %,Ldi%=\;cmp/eq %R1,%R0\\n%,Ldi%=:"
703 [(set_attr "length" "6")
704 (set_attr "type" "arith3b")])
708 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
709 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
710 ;; If we applied this split when not optimizing, it would only be
711 ;; applied during the machine-dependent reorg, when no new basic blocks
713 "reload_completed && optimize"
714 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
715 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
716 (label_ref (match_dup 6))
718 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
723 = gen_rtx_REG (SImode,
724 true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
726 = (operands[1] == const0_rtx
728 : gen_rtx_REG (SImode,
729 true_regnum (operands[1])
730 + (TARGET_LITTLE_ENDIAN ? 1 : 0)));
731 operands[4] = gen_lowpart (SImode, operands[0]);
732 operands[5] = gen_lowpart (SImode, operands[1]);
733 operands[6] = gen_label_rtx ();
736 (define_insn "cmpgtdi_t"
738 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
739 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
742 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
743 tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
744 [(set_attr "length" "8")
745 (set_attr "type" "arith3")])
747 (define_insn "cmpgedi_t"
749 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
750 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
753 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
755 [(set_attr "length" "8,2")
756 (set_attr "type" "arith3,arith")])
758 ;; -------------------------------------------------------------------------
759 ;; DImode unsigned integer comparisons
760 ;; -------------------------------------------------------------------------
762 (define_insn "cmpgeudi_t"
764 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
765 (match_operand:DI 1 "arith_reg_operand" "r")))]
767 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
768 [(set_attr "length" "8")
769 (set_attr "type" "arith3")])
771 (define_insn "cmpgtudi_t"
773 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
774 (match_operand:DI 1 "arith_reg_operand" "r")))]
776 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
777 [(set_attr "length" "8")
778 (set_attr "type" "arith3")])
780 ;; We save the compare operands in the cmpxx patterns and use them when
781 ;; we generate the branch.
783 (define_expand "cmpdi"
785 (compare (match_operand:DI 0 "arith_operand" "")
786 (match_operand:DI 1 "arith_operand" "")))]
790 sh_compare_op0 = operands[0];
791 sh_compare_op1 = operands[1];
795 ;; -------------------------------------------------------------------------
796 ;; Addition instructions
797 ;; -------------------------------------------------------------------------
799 ;; ??? This should be a define expand.
801 (define_insn "adddi3"
802 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
803 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
804 (match_operand:DI 2 "arith_reg_operand" "r")))
805 (clobber (reg:SI T_REG))]
808 [(set_attr "length" "6")])
811 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
812 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
813 (match_operand:DI 2 "arith_reg_operand" "r")))
814 (clobber (reg:SI T_REG))]
819 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
820 high0 = gen_rtx_REG (SImode,
821 true_regnum (operands[0])
822 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
823 high2 = gen_rtx_REG (SImode,
824 true_regnum (operands[2])
825 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
826 emit_insn (gen_clrt ());
827 emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
828 emit_insn (gen_addc1 (high0, high0, high2));
833 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
834 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
835 (match_operand:SI 2 "arith_reg_operand" "r"))
838 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
841 [(set_attr "type" "arith")])
844 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
845 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
846 (match_operand:SI 2 "arith_reg_operand" "r"))
848 (clobber (reg:SI T_REG))]
851 [(set_attr "type" "arith")])
853 (define_insn "addsi3"
854 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
855 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
856 (match_operand:SI 2 "arith_operand" "rI")))]
859 [(set_attr "type" "arith")])
861 ;; -------------------------------------------------------------------------
862 ;; Subtraction instructions
863 ;; -------------------------------------------------------------------------
865 ;; ??? This should be a define expand.
867 (define_insn "subdi3"
868 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
869 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
870 (match_operand:DI 2 "arith_reg_operand" "r")))
871 (clobber (reg:SI T_REG))]
874 [(set_attr "length" "6")])
877 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
878 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
879 (match_operand:DI 2 "arith_reg_operand" "r")))
880 (clobber (reg:SI T_REG))]
885 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
886 high0 = gen_rtx_REG (SImode,
887 true_regnum (operands[0])
888 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
889 high2 = gen_rtx_REG (SImode,
890 true_regnum (operands[2])
891 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
892 emit_insn (gen_clrt ());
893 emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
894 emit_insn (gen_subc1 (high0, high0, high2));
899 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
900 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
901 (match_operand:SI 2 "arith_reg_operand" "r"))
904 (gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
907 [(set_attr "type" "arith")])
910 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
911 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
912 (match_operand:SI 2 "arith_reg_operand" "r"))
914 (clobber (reg:SI T_REG))]
917 [(set_attr "type" "arith")])
919 (define_insn "*subsi3_internal"
920 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
921 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
922 (match_operand:SI 2 "arith_reg_operand" "r")))]
925 [(set_attr "type" "arith")])
927 ;; Convert `constant - reg' to `neg rX; add rX, #const' since this
928 ;; will sometimes save one instruction. Otherwise we might get
929 ;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
932 (define_expand "subsi3"
933 [(set (match_operand:SI 0 "arith_reg_operand" "")
934 (minus:SI (match_operand:SI 1 "arith_operand" "")
935 (match_operand:SI 2 "arith_reg_operand" "")))]
939 if (GET_CODE (operands[1]) == CONST_INT)
941 emit_insn (gen_negsi2 (operands[0], operands[2]));
942 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
947 ;; -------------------------------------------------------------------------
948 ;; Division instructions
949 ;; -------------------------------------------------------------------------
951 ;; We take advantage of the library routines which don't clobber as many
952 ;; registers as a normal function call would.
954 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
955 ;; also has an effect on the register that holds the address of the sfunc.
956 ;; To make this work, we have an extra dummy insns that shows the use
957 ;; of this register for reorg.
959 (define_insn "use_sfunc_addr"
960 [(set (reg:SI PR_REG)
961 (unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
964 [(set_attr "length" "0")])
966 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
967 ;; hard register 0. If we used hard register 0, then the next instruction
968 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
969 ;; gets allocated to a stack slot that needs its address reloaded, then
970 ;; there is nothing to prevent reload from using r0 to reload the address.
971 ;; This reload would clobber the value in r0 we are trying to store.
972 ;; If we let reload allocate r0, then this problem can never happen.
974 (define_insn "udivsi3_i1"
975 [(set (match_operand:SI 0 "register_operand" "=z")
976 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
977 (clobber (reg:SI T_REG))
978 (clobber (reg:SI PR_REG))
979 (clobber (reg:SI R4_REG))
980 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
983 [(set_attr "type" "sfunc")
984 (set_attr "needs_delay_slot" "yes")])
986 (define_insn "udivsi3_i4"
987 [(set (match_operand:SI 0 "register_operand" "=y")
988 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
989 (clobber (reg:SI T_REG))
990 (clobber (reg:SI PR_REG))
991 (clobber (reg:DF DR0_REG))
992 (clobber (reg:DF DR2_REG))
993 (clobber (reg:DF DR4_REG))
994 (clobber (reg:SI R0_REG))
995 (clobber (reg:SI R1_REG))
996 (clobber (reg:SI R4_REG))
997 (clobber (reg:SI R5_REG))
998 (use (reg:PSI FPSCR_REG))
999 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1000 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1002 [(set_attr "type" "sfunc")
1003 (set_attr "fp_mode" "double")
1004 (set_attr "needs_delay_slot" "yes")])
1006 (define_insn "udivsi3_i4_single"
1007 [(set (match_operand:SI 0 "register_operand" "=y")
1008 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1009 (clobber (reg:SI T_REG))
1010 (clobber (reg:SI PR_REG))
1011 (clobber (reg:DF DR0_REG))
1012 (clobber (reg:DF DR2_REG))
1013 (clobber (reg:DF DR4_REG))
1014 (clobber (reg:SI R0_REG))
1015 (clobber (reg:SI R1_REG))
1016 (clobber (reg:SI R4_REG))
1017 (clobber (reg:SI R5_REG))
1018 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1019 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
1021 [(set_attr "type" "sfunc")
1022 (set_attr "needs_delay_slot" "yes")])
1024 (define_expand "udivsi3"
1025 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
1026 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1027 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1028 (parallel [(set (match_operand:SI 0 "register_operand" "")
1029 (udiv:SI (reg:SI R4_REG)
1031 (clobber (reg:SI T_REG))
1032 (clobber (reg:SI PR_REG))
1033 (clobber (reg:SI R4_REG))
1034 (use (match_dup 3))])]
1040 operands[3] = gen_reg_rtx(SImode);
1041 /* Emit the move of the address to a pseudo outside of the libcall. */
1042 if (TARGET_HARD_SH4 && TARGET_SH3E)
1044 emit_move_insn (operands[3],
1045 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
1046 if (TARGET_FPU_SINGLE)
1047 last = gen_udivsi3_i4_single (operands[0], operands[3]);
1049 last = gen_udivsi3_i4 (operands[0], operands[3]);
1053 emit_move_insn (operands[3],
1054 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3\"));
1055 last = gen_udivsi3_i1 (operands[0], operands[3]);
1057 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1058 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1059 last = emit_insn (last);
1060 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1061 invariant code motion can move it. */
1062 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1063 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1067 (define_insn "divsi3_i1"
1068 [(set (match_operand:SI 0 "register_operand" "=z")
1069 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1070 (clobber (reg:SI T_REG))
1071 (clobber (reg:SI PR_REG))
1072 (clobber (reg:SI R1_REG))
1073 (clobber (reg:SI R2_REG))
1074 (clobber (reg:SI R3_REG))
1075 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1078 [(set_attr "type" "sfunc")
1079 (set_attr "needs_delay_slot" "yes")])
1081 (define_insn "divsi3_i4"
1082 [(set (match_operand:SI 0 "register_operand" "=y")
1083 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1084 (clobber (reg:SI PR_REG))
1085 (clobber (reg:DF DR0_REG))
1086 (clobber (reg:DF DR2_REG))
1087 (use (reg:PSI FPSCR_REG))
1088 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1089 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1091 [(set_attr "type" "sfunc")
1092 (set_attr "fp_mode" "double")
1093 (set_attr "needs_delay_slot" "yes")])
1095 (define_insn "divsi3_i4_single"
1096 [(set (match_operand:SI 0 "register_operand" "=y")
1097 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1098 (clobber (reg:SI PR_REG))
1099 (clobber (reg:DF DR0_REG))
1100 (clobber (reg:DF DR2_REG))
1101 (clobber (reg:SI R2_REG))
1102 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1103 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
1105 [(set_attr "type" "sfunc")
1106 (set_attr "needs_delay_slot" "yes")])
1108 (define_expand "divsi3"
1109 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
1110 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1111 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1112 (parallel [(set (match_operand:SI 0 "register_operand" "")
1113 (div:SI (reg:SI R4_REG)
1115 (clobber (reg:SI T_REG))
1116 (clobber (reg:SI PR_REG))
1117 (clobber (reg:SI R1_REG))
1118 (clobber (reg:SI R2_REG))
1119 (clobber (reg:SI R3_REG))
1120 (use (match_dup 3))])]
1126 operands[3] = gen_reg_rtx(SImode);
1127 /* Emit the move of the address to a pseudo outside of the libcall. */
1128 if (TARGET_HARD_SH4 && TARGET_SH3E)
1130 emit_move_insn (operands[3],
1131 gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
1132 if (TARGET_FPU_SINGLE)
1133 last = gen_divsi3_i4_single (operands[0], operands[3]);
1135 last = gen_divsi3_i4 (operands[0], operands[3]);
1139 emit_move_insn (operands[3], gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3\"));
1140 last = gen_divsi3_i1 (operands[0], operands[3]);
1142 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1143 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1144 last = emit_insn (last);
1145 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1146 invariant code motion can move it. */
1147 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1148 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1152 ;; -------------------------------------------------------------------------
1153 ;; Multiplication instructions
1154 ;; -------------------------------------------------------------------------
1156 (define_insn "umulhisi3_i"
1157 [(set (reg:SI MACL_REG)
1158 (mult:SI (zero_extend:SI
1159 (match_operand:HI 0 "arith_reg_operand" "r"))
1161 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1164 [(set_attr "type" "smpy")])
1166 (define_insn "mulhisi3_i"
1167 [(set (reg:SI MACL_REG)
1168 (mult:SI (sign_extend:SI
1169 (match_operand:HI 0 "arith_reg_operand" "r"))
1171 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1174 [(set_attr "type" "smpy")])
1176 (define_expand "mulhisi3"
1177 [(set (reg:SI MACL_REG)
1178 (mult:SI (sign_extend:SI
1179 (match_operand:HI 1 "arith_reg_operand" ""))
1181 (match_operand:HI 2 "arith_reg_operand" ""))))
1182 (set (match_operand:SI 0 "arith_reg_operand" "")
1189 first = emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
1190 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
1191 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1192 invariant code motion can move it. */
1193 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1194 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1198 (define_expand "umulhisi3"
1199 [(set (reg:SI MACL_REG)
1200 (mult:SI (zero_extend:SI
1201 (match_operand:HI 1 "arith_reg_operand" ""))
1203 (match_operand:HI 2 "arith_reg_operand" ""))))
1204 (set (match_operand:SI 0 "arith_reg_operand" "")
1211 first = emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
1212 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
1213 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1214 invariant code motion can move it. */
1215 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1216 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1220 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
1221 ;; a call to a routine which clobbers known registers.
1224 [(set (match_operand:SI 1 "register_operand" "=z")
1225 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1226 (clobber (reg:SI MACL_REG))
1227 (clobber (reg:SI T_REG))
1228 (clobber (reg:SI PR_REG))
1229 (clobber (reg:SI R3_REG))
1230 (clobber (reg:SI R2_REG))
1231 (clobber (reg:SI R1_REG))
1232 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
1235 [(set_attr "type" "sfunc")
1236 (set_attr "needs_delay_slot" "yes")])
1238 (define_expand "mulsi3_call"
1239 [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1240 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1241 (parallel[(set (match_operand:SI 0 "register_operand" "")
1242 (mult:SI (reg:SI R4_REG)
1244 (clobber (reg:SI MACL_REG))
1245 (clobber (reg:SI T_REG))
1246 (clobber (reg:SI PR_REG))
1247 (clobber (reg:SI R3_REG))
1248 (clobber (reg:SI R2_REG))
1249 (clobber (reg:SI R1_REG))
1250 (use (match_operand:SI 3 "register_operand" ""))])]
1254 (define_insn "mul_l"
1255 [(set (reg:SI MACL_REG)
1256 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
1257 (match_operand:SI 1 "arith_reg_operand" "r")))]
1260 [(set_attr "type" "dmpy")])
1262 (define_expand "mulsi3"
1263 [(set (reg:SI MACL_REG)
1264 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
1265 (match_operand:SI 2 "arith_reg_operand" "")))
1266 (set (match_operand:SI 0 "arith_reg_operand" "")
1275 /* The address must be set outside the libcall,
1276 since it goes into a pseudo. */
1277 rtx sym = gen_rtx_SYMBOL_REF (SImode, \"__mulsi3\");
1278 rtx addr = force_reg (SImode, sym);
1279 rtx insns = gen_mulsi3_call (operands[0], operands[1],
1281 first = XVECEXP (insns, 0, 0);
1282 last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1287 rtx macl = gen_rtx_REG (SImode, MACL_REG);
1289 first = emit_insn (gen_mul_l (operands[1], operands[2]));
1290 /* consec_sets_giv can only recognize the first insn that sets a
1291 giv as the giv insn. So we must tag this also with a REG_EQUAL
1293 last = emit_insn (gen_movsi_i ((operands[0]), macl));
1295 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1296 invariant code motion can move it. */
1297 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1298 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1302 (define_insn "mulsidi3_i"
1303 [(set (reg:SI MACH_REG)
1307 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1308 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1310 (set (reg:SI MACL_REG)
1311 (mult:SI (match_dup 0)
1315 [(set_attr "type" "dmpy")])
1317 (define_insn "mulsidi3"
1318 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1320 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1321 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1322 (clobber (reg:SI MACH_REG))
1323 (clobber (reg:SI MACL_REG))]
1328 [(set (match_operand:DI 0 "arith_reg_operand" "")
1330 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1331 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1332 (clobber (reg:SI MACH_REG))
1333 (clobber (reg:SI MACL_REG))]
1338 rtx low_dst = gen_lowpart (SImode, operands[0]);
1339 rtx high_dst = gen_highpart (SImode, operands[0]);
1341 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
1343 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
1344 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
1345 /* We need something to tag the possible REG_EQUAL notes on to. */
1346 emit_move_insn (operands[0], operands[0]);
1350 (define_insn "umulsidi3_i"
1351 [(set (reg:SI MACH_REG)
1355 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1356 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1358 (set (reg:SI MACL_REG)
1359 (mult:SI (match_dup 0)
1363 [(set_attr "type" "dmpy")])
1365 (define_insn "umulsidi3"
1366 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1368 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1369 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1370 (clobber (reg:SI MACH_REG))
1371 (clobber (reg:SI MACL_REG))]
1376 [(set (match_operand:DI 0 "arith_reg_operand" "")
1377 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1378 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1379 (clobber (reg:SI MACH_REG))
1380 (clobber (reg:SI MACL_REG))]
1385 rtx low_dst = gen_lowpart (SImode, operands[0]);
1386 rtx high_dst = gen_highpart (SImode, operands[0]);
1388 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
1390 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
1391 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
1392 /* We need something to tag the possible REG_EQUAL notes on to. */
1393 emit_move_insn (operands[0], operands[0]);
1397 (define_insn "smulsi3_highpart_i"
1398 [(set (reg:SI MACH_REG)
1402 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1403 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1405 (clobber (reg:SI MACL_REG))]
1408 [(set_attr "type" "dmpy")])
1410 (define_expand "smulsi3_highpart"
1412 [(set (reg:SI MACH_REG)
1416 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1417 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1419 (clobber (reg:SI MACL_REG))])
1420 (set (match_operand:SI 0 "arith_reg_operand" "")
1427 first = emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
1428 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
1429 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1430 invariant code motion can move it. */
1431 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1432 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1433 /* expand_binop can't find a suitable code in mul_highpart_optab to
1434 make a REG_EQUAL note from, so make one here.
1435 ??? Alternatively, we could put this at the calling site of expand_binop,
1436 i.e. expand_mult_highpart. */
1438 = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
1443 (define_insn "umulsi3_highpart_i"
1444 [(set (reg:SI MACH_REG)
1448 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1449 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1451 (clobber (reg:SI MACL_REG))]
1454 [(set_attr "type" "dmpy")])
1456 (define_expand "umulsi3_highpart"
1458 [(set (reg:SI MACH_REG)
1462 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1463 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1465 (clobber (reg:SI MACL_REG))])
1466 (set (match_operand:SI 0 "arith_reg_operand" "")
1473 first = emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
1474 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
1475 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1476 invariant code motion can move it. */
1477 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1478 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1482 ;; -------------------------------------------------------------------------
1483 ;; Logical operations
1484 ;; -------------------------------------------------------------------------
1487 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1488 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1489 (match_operand:SI 2 "logical_operand" "r,L")))]
1492 [(set_attr "type" "arith")])
1494 ;; If the constant is 255, then emit a extu.b instruction instead of an
1495 ;; and, since that will give better code.
1497 (define_expand "andsi3"
1498 [(set (match_operand:SI 0 "arith_reg_operand" "")
1499 (and:SI (match_operand:SI 1 "arith_reg_operand" "")
1500 (match_operand:SI 2 "logical_operand" "")))]
1504 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
1506 emit_insn (gen_zero_extendqisi2 (operands[0],
1507 gen_lowpart (QImode, operands[1])));
1512 (define_insn "iorsi3"
1513 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1514 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1515 (match_operand:SI 2 "logical_operand" "r,L")))]
1518 [(set_attr "type" "arith")])
1520 (define_insn "xorsi3"
1521 [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
1522 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1523 (match_operand:SI 2 "logical_operand" "L,r")))]
1526 [(set_attr "type" "arith")])
1528 ;; -------------------------------------------------------------------------
1529 ;; Shifts and rotates
1530 ;; -------------------------------------------------------------------------
1532 (define_insn "rotlsi3_1"
1533 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1534 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1537 (lshiftrt:SI (match_dup 1) (const_int 31)))]
1540 [(set_attr "type" "arith")])
1542 (define_insn "rotlsi3_31"
1543 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1544 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1546 (clobber (reg:SI T_REG))]
1549 [(set_attr "type" "arith")])
1551 (define_insn "rotlsi3_16"
1552 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1553 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
1557 [(set_attr "type" "arith")])
1559 (define_expand "rotlsi3"
1560 [(set (match_operand:SI 0 "arith_reg_operand" "")
1561 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
1562 (match_operand:SI 2 "immediate_operand" "")))]
1566 static char rot_tab[] = {
1567 000, 000, 000, 000, 000, 000, 010, 001,
1568 001, 001, 011, 013, 003, 003, 003, 003,
1569 003, 003, 003, 003, 003, 013, 012, 002,
1570 002, 002, 010, 000, 000, 000, 000, 000,
1575 if (GET_CODE (operands[2]) != CONST_INT)
1577 count = INTVAL (operands[2]);
1578 choice = rot_tab[count];
1579 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
1585 emit_move_insn (operands[0], operands[1]);
1586 count -= (count & 16) * 2;
1589 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
1596 parts[0] = gen_reg_rtx (SImode);
1597 parts[1] = gen_reg_rtx (SImode);
1598 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
1599 parts[choice-1] = operands[1];
1600 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
1601 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
1602 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
1603 count = (count & ~16) - 8;
1607 for (; count > 0; count--)
1608 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1609 for (; count < 0; count++)
1610 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1615 (define_insn "*rotlhi3_8"
1616 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1617 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
1621 [(set_attr "type" "arith")])
1623 (define_expand "rotlhi3"
1624 [(set (match_operand:HI 0 "arith_reg_operand" "")
1625 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
1626 (match_operand:HI 2 "immediate_operand" "")))]
1630 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
1637 ;; This pattern is used by init_expmed for computing the costs of shift
1640 (define_insn_and_split "ashlsi3_std"
1641 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r")
1642 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
1643 (match_operand:SI 2 "nonmemory_operand" "r,M,K,?ri")))
1644 (clobber (match_scratch:SI 3 "=X,X,X,&r"))]
1646 || (GET_CODE (operands[2]) == CONST_INT
1647 && CONST_OK_FOR_K (INTVAL (operands[2])))"
1654 && GET_CODE (operands[2]) == CONST_INT
1655 && ! CONST_OK_FOR_K (INTVAL (operands[2]))"
1656 [(set (match_dup 3) (match_dup 2))
1658 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
1659 (clobber (match_dup 4))])]
1660 "operands[4] = gen_rtx_SCRATCH (SImode);"
1661 [(set_attr "length" "*,*,*,4")
1662 (set_attr "type" "dyn_shift,arith,arith,arith")])
1664 (define_insn "ashlhi3_k"
1665 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
1666 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
1667 (match_operand:HI 2 "const_int_operand" "M,K")))]
1668 "CONST_OK_FOR_K (INTVAL (operands[2]))"
1672 [(set_attr "type" "arith")])
1674 (define_insn "ashlsi3_n"
1675 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1676 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
1677 (match_operand:SI 2 "const_int_operand" "n")))
1678 (clobber (reg:SI T_REG))]
1679 "! sh_dynamicalize_shift_p (operands[2])"
1681 [(set (attr "length")
1682 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1684 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1686 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1688 (const_string "8")))
1689 (set_attr "type" "arith")])
1692 [(set (match_operand:SI 0 "arith_reg_operand" "")
1693 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1694 (match_operand:SI 2 "const_int_operand" "n")))
1695 (clobber (reg:SI T_REG))]
1697 [(use (reg:SI R0_REG))]
1700 gen_shifty_op (ASHIFT, operands);
1704 (define_expand "ashlsi3"
1705 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1706 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1707 (match_operand:SI 2 "nonmemory_operand" "")))
1708 (clobber (reg:SI T_REG))])]
1712 if (GET_CODE (operands[2]) == CONST_INT
1713 && sh_dynamicalize_shift_p (operands[2]))
1714 operands[2] = force_reg (SImode, operands[2]);
1717 emit_insn (gen_ashlsi3_std (operands[0], operands[1], operands[2]));
1720 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1724 (define_insn "ashlhi3"
1725 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1726 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
1727 (match_operand:HI 2 "const_int_operand" "n")))
1728 (clobber (reg:SI T_REG))]
1731 [(set (attr "length")
1732 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1734 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1736 (const_string "6")))
1737 (set_attr "type" "arith")])
1740 [(set (match_operand:HI 0 "arith_reg_operand" "")
1741 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
1742 (match_operand:HI 2 "const_int_operand" "n")))
1743 (clobber (reg:SI T_REG))]
1745 [(use (reg:SI R0_REG))]
1748 gen_shifty_hi_op (ASHIFT, operands);
1753 ; arithmetic shift right
1756 (define_insn "ashrsi3_k"
1757 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1758 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1759 (match_operand:SI 2 "const_int_operand" "M")))
1760 (clobber (reg:SI T_REG))]
1761 "INTVAL (operands[2]) == 1"
1763 [(set_attr "type" "arith")])
1765 ;; We can't do HImode right shifts correctly unless we start out with an
1766 ;; explicit zero / sign extension; doing that would result in worse overall
1767 ;; code, so just let the machine independent code widen the mode.
1768 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
1771 ;; ??? This should be a define expand.
1773 (define_insn "ashrsi2_16"
1774 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1775 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1779 [(set_attr "length" "4")])
1782 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1783 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1786 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
1787 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
1788 "operands[2] = gen_lowpart (HImode, operands[0]);")
1790 ;; ??? This should be a define expand.
1792 (define_insn "ashrsi2_31"
1793 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1794 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1796 (clobber (reg:SI T_REG))]
1799 [(set_attr "length" "4")])
1802 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1803 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1805 (clobber (reg:SI T_REG))]
1810 emit_insn (gen_ashlsi_c (operands[0], operands[1]));
1811 emit_insn (gen_subc1 (operands[0], operands[0], operands[0]));
1815 (define_insn "ashlsi_c"
1816 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1817 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
1819 (lt:SI (match_dup 1) (const_int 0)))]
1822 [(set_attr "type" "arith")])
1824 (define_insn "ashrsi3_d"
1825 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1826 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1827 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1830 [(set_attr "type" "dyn_shift")])
1832 (define_insn "ashrsi3_n"
1833 [(set (reg:SI R4_REG)
1834 (ashiftrt:SI (reg:SI R4_REG)
1835 (match_operand:SI 0 "const_int_operand" "i")))
1836 (clobber (reg:SI T_REG))
1837 (clobber (reg:SI PR_REG))
1838 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1841 [(set_attr "type" "sfunc")
1842 (set_attr "needs_delay_slot" "yes")])
1844 (define_expand "ashrsi3"
1845 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1846 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1847 (match_operand:SI 2 "nonmemory_operand" "")))
1848 (clobber (reg:SI T_REG))])]
1850 "if (expand_ashiftrt (operands)) DONE; else FAIL;")
1852 ;; logical shift right
1854 (define_insn "lshrsi3_d"
1855 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1856 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1857 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1860 [(set_attr "type" "dyn_shift")])
1862 ;; Only the single bit shift clobbers the T bit.
1864 (define_insn "lshrsi3_m"
1865 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1866 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1867 (match_operand:SI 2 "const_int_operand" "M")))
1868 (clobber (reg:SI T_REG))]
1869 "CONST_OK_FOR_M (INTVAL (operands[2]))"
1871 [(set_attr "type" "arith")])
1873 (define_insn "lshrsi3_k"
1874 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1875 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1876 (match_operand:SI 2 "const_int_operand" "K")))]
1877 "CONST_OK_FOR_K (INTVAL (operands[2]))
1878 && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
1880 [(set_attr "type" "arith")])
1882 (define_insn "lshrsi3_n"
1883 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1884 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1885 (match_operand:SI 2 "const_int_operand" "n")))
1886 (clobber (reg:SI T_REG))]
1887 "! sh_dynamicalize_shift_p (operands[2])"
1889 [(set (attr "length")
1890 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1892 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1894 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1896 (const_string "8")))
1897 (set_attr "type" "arith")])
1900 [(set (match_operand:SI 0 "arith_reg_operand" "")
1901 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1902 (match_operand:SI 2 "const_int_operand" "n")))
1903 (clobber (reg:SI T_REG))]
1905 [(use (reg:SI R0_REG))]
1908 gen_shifty_op (LSHIFTRT, operands);
1912 (define_expand "lshrsi3"
1913 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1914 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1915 (match_operand:SI 2 "nonmemory_operand" "")))
1916 (clobber (reg:SI T_REG))])]
1920 if (GET_CODE (operands[2]) == CONST_INT
1921 && sh_dynamicalize_shift_p (operands[2]))
1922 operands[2] = force_reg (SImode, operands[2]);
1923 if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
1925 rtx count = copy_to_mode_reg (SImode, operands[2]);
1926 emit_insn (gen_negsi2 (count, count));
1927 emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
1930 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1934 ;; ??? This should be a define expand.
1936 (define_insn "ashldi3_k"
1937 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1938 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
1940 (clobber (reg:SI T_REG))]
1942 "shll %R0\;rotcl %S0"
1943 [(set_attr "length" "4")
1944 (set_attr "type" "arith")])
1946 (define_expand "ashldi3"
1947 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1948 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
1949 (match_operand:DI 2 "immediate_operand" "")))
1950 (clobber (reg:SI T_REG))])]
1952 "{ if (GET_CODE (operands[2]) != CONST_INT
1953 || INTVAL (operands[2]) != 1) FAIL;} ")
1955 ;; ??? This should be a define expand.
1957 (define_insn "lshrdi3_k"
1958 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1959 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1961 (clobber (reg:SI T_REG))]
1963 "shlr %S0\;rotcr %R0"
1964 [(set_attr "length" "4")
1965 (set_attr "type" "arith")])
1967 (define_expand "lshrdi3"
1968 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1969 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1970 (match_operand:DI 2 "immediate_operand" "")))
1971 (clobber (reg:SI T_REG))])]
1973 "{ if (GET_CODE (operands[2]) != CONST_INT
1974 || INTVAL (operands[2]) != 1) FAIL;} ")
1976 ;; ??? This should be a define expand.
1978 (define_insn "ashrdi3_k"
1979 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1980 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1982 (clobber (reg:SI T_REG))]
1984 "shar %S0\;rotcr %R0"
1985 [(set_attr "length" "4")
1986 (set_attr "type" "arith")])
1988 (define_expand "ashrdi3"
1989 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1990 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1991 (match_operand:DI 2 "immediate_operand" "")))
1992 (clobber (reg:SI T_REG))])]
1994 "{ if (GET_CODE (operands[2]) != CONST_INT
1995 || INTVAL (operands[2]) != 1) FAIL; } ")
1997 ;; combined left/right shift
2000 [(set (match_operand:SI 0 "register_operand" "")
2001 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
2002 (match_operand:SI 2 "const_int_operand" "n"))
2003 (match_operand:SI 3 "const_int_operand" "n")))]
2004 "(unsigned)INTVAL (operands[2]) < 32"
2005 [(use (reg:SI R0_REG))]
2006 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
2010 [(set (match_operand:SI 0 "register_operand" "")
2011 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
2012 (match_operand:SI 2 "const_int_operand" "n"))
2013 (match_operand:SI 3 "const_int_operand" "n")))
2014 (clobber (reg:SI T_REG))]
2015 "(unsigned)INTVAL (operands[2]) < 32"
2016 [(use (reg:SI R0_REG))]
2017 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
2021 [(set (match_operand:SI 0 "register_operand" "=r")
2022 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2023 (match_operand:SI 2 "const_int_operand" "n"))
2024 (match_operand:SI 3 "const_int_operand" "n")))
2025 (clobber (reg:SI T_REG))]
2026 "shl_and_kind (operands[2], operands[3], 0) == 1"
2028 [(set (attr "length")
2029 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
2031 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
2033 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
2035 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
2037 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
2039 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
2041 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
2042 (const_string "16")]
2043 (const_string "18")))
2044 (set_attr "type" "arith")])
2047 [(set (match_operand:SI 0 "register_operand" "=z")
2048 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2049 (match_operand:SI 2 "const_int_operand" "n"))
2050 (match_operand:SI 3 "const_int_operand" "n")))
2051 (clobber (reg:SI T_REG))]
2052 "shl_and_kind (operands[2], operands[3], 0) == 2"
2054 [(set (attr "length")
2055 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
2057 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
2059 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
2061 (const_string "10")))
2062 (set_attr "type" "arith")])
2064 ;; shift left / and combination with a scratch register: The combine pass
2065 ;; does not accept the individual instructions, even though they are
2066 ;; cheap. But it needs a precise description so that it is usable after
2068 (define_insn "and_shl_scratch"
2069 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2073 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
2074 (match_operand:SI 2 "const_int_operand" "N,n"))
2075 (match_operand:SI 3 "" "0,r"))
2076 (match_operand:SI 4 "const_int_operand" "n,n"))
2077 (match_operand:SI 5 "const_int_operand" "n,n")))
2078 (clobber (reg:SI T_REG))]
2081 [(set (attr "length")
2082 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
2084 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
2086 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
2088 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
2089 (const_string "10")]
2090 (const_string "12")))
2091 (set_attr "type" "arith")])
2094 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2098 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
2099 (match_operand:SI 2 "const_int_operand" "N,n"))
2100 (match_operand:SI 3 "register_operand" "0,r"))
2101 (match_operand:SI 4 "const_int_operand" "n,n"))
2102 (match_operand:SI 5 "const_int_operand" "n,n")))
2103 (clobber (reg:SI T_REG))]
2105 [(use (reg:SI R0_REG))]
2108 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
2110 if (INTVAL (operands[2]))
2112 gen_shifty_op (LSHIFTRT, operands);
2114 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
2115 operands[2] = operands[4];
2116 gen_shifty_op (ASHIFT, operands);
2117 if (INTVAL (operands[5]))
2119 operands[2] = operands[5];
2120 gen_shifty_op (LSHIFTRT, operands);
2125 ;; signed left/right shift combination.
2127 [(set (match_operand:SI 0 "register_operand" "=r")
2129 (ashift:SI (match_operand:SI 1 "register_operand" "r")
2130 (match_operand:SI 2 "const_int_operand" "n"))
2131 (match_operand:SI 3 "const_int_operand" "n")
2133 (clobber (reg:SI T_REG))]
2135 [(use (reg:SI R0_REG))]
2136 "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
2139 (define_insn "shl_sext_ext"
2140 [(set (match_operand:SI 0 "register_operand" "=r")
2142 (ashift:SI (match_operand:SI 1 "register_operand" "0")
2143 (match_operand:SI 2 "const_int_operand" "n"))
2144 (match_operand:SI 3 "const_int_operand" "n")
2146 (clobber (reg:SI T_REG))]
2147 "(unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
2149 [(set (attr "length")
2150 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 1))
2152 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
2154 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2156 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2158 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2160 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2162 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
2164 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
2165 (const_string "16")]
2166 (const_string "18")))
2167 (set_attr "type" "arith")])
2169 (define_insn "shl_sext_sub"
2170 [(set (match_operand:SI 0 "register_operand" "=z")
2172 (ashift:SI (match_operand:SI 1 "register_operand" "0")
2173 (match_operand:SI 2 "const_int_operand" "n"))
2174 (match_operand:SI 3 "const_int_operand" "n")
2176 (clobber (reg:SI T_REG))]
2177 "(shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
2179 [(set (attr "length")
2180 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2182 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2184 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2186 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2187 (const_string "12")]
2188 (const_string "14")))
2189 (set_attr "type" "arith")])
2191 ;; These patterns are found in expansions of DImode shifts by 16, and
2192 ;; allow the xtrct instruction to be generated from C source.
2194 (define_insn "xtrct_left"
2195 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2196 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
2198 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
2202 [(set_attr "type" "arith")])
2204 (define_insn "xtrct_right"
2205 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2206 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2208 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
2212 [(set_attr "type" "arith")])
2214 ;; -------------------------------------------------------------------------
2216 ;; -------------------------------------------------------------------------
2219 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2220 (neg:SI (plus:SI (reg:SI T_REG)
2221 (match_operand:SI 1 "arith_reg_operand" "r"))))
2223 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
2227 [(set_attr "type" "arith")])
2229 (define_expand "negdi2"
2230 [(set (match_operand:DI 0 "arith_reg_operand" "")
2231 (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
2232 (clobber (reg:SI T_REG))]
2236 int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
2237 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
2239 rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
2240 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
2242 rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
2243 rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
2245 emit_insn (gen_clrt ());
2246 emit_insn (gen_negc (low_dst, low_src));
2247 emit_insn (gen_negc (high_dst, high_src));
2251 (define_insn "negsi2"
2252 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2253 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2256 [(set_attr "type" "arith")])
2258 (define_insn "one_cmplsi2"
2259 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2260 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2263 [(set_attr "type" "arith")])
2265 ;; -------------------------------------------------------------------------
2266 ;; Zero extension instructions
2267 ;; -------------------------------------------------------------------------
2269 (define_insn "zero_extendhisi2"
2270 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2271 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
2274 [(set_attr "type" "arith")])
2276 (define_insn "zero_extendqisi2"
2277 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2278 (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
2281 [(set_attr "type" "arith")])
2283 (define_insn "zero_extendqihi2"
2284 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
2285 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
2288 [(set_attr "type" "arith")])
2290 ;; -------------------------------------------------------------------------
2291 ;; Sign extension instructions
2292 ;; -------------------------------------------------------------------------
2294 ;; ??? This should be a define expand.
2295 ;; ??? Or perhaps it should be dropped?
2297 /* There is no point in defining extendsidi2; convert_move generates good
2300 (define_insn "extendhisi2"
2301 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2302 (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
2307 [(set_attr "type" "arith,load")])
2309 (define_insn "extendqisi2"
2310 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2311 (sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2316 [(set_attr "type" "arith,load")])
2318 (define_insn "extendqihi2"
2319 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
2320 (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2325 [(set_attr "type" "arith,load")])
2327 ;; -------------------------------------------------------------------------
2328 ;; Move instructions
2329 ;; -------------------------------------------------------------------------
2331 ;; define push and pop so it is easy for sh.c
2333 (define_expand "push"
2334 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2335 (match_operand:SI 0 "register_operand" "r,l,x"))]
2339 (define_expand "pop"
2340 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
2341 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2345 (define_expand "push_e"
2346 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
2347 (match_operand:SF 0 "" ""))
2348 (use (reg:PSI FPSCR_REG))
2349 (clobber (scratch:SI))])]
2353 (define_insn "push_fpul"
2354 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
2357 [(set_attr "type" "store")
2358 (set_attr "hit_stack" "yes")])
2360 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
2362 (define_expand "push_4"
2363 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
2364 (match_operand:DF 0 "" ""))
2365 (use (reg:PSI FPSCR_REG))
2366 (clobber (scratch:SI))])]
2370 (define_expand "pop_e"
2371 [(parallel [(set (match_operand:SF 0 "" "")
2372 (mem:SF (post_inc:SI (reg:SI SP_REG))))
2373 (use (reg:PSI FPSCR_REG))
2374 (clobber (scratch:SI))])]
2378 (define_insn "pop_fpul"
2379 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
2382 [(set_attr "type" "load")
2383 (set_attr "hit_stack" "yes")])
2385 (define_expand "pop_4"
2386 [(parallel [(set (match_operand:DF 0 "" "")
2387 (mem:DF (post_inc:SI (reg:SI SP_REG))))
2388 (use (reg:PSI FPSCR_REG))
2389 (clobber (scratch:SI))])]
2393 ;; These two patterns can happen as the result of optimization, when
2394 ;; comparisons get simplified to a move of zero or 1 into the T reg.
2395 ;; They don't disappear completely, because the T reg is a fixed hard reg.
2398 [(set (reg:SI T_REG) (const_int 0))]
2403 [(set (reg:SI T_REG) (const_int 1))]
2407 ;; t/r must come after r/r, lest reload will try to reload stuff like
2408 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
2409 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
2410 (define_insn "movsi_i"
2411 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
2412 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
2415 && (register_operand (operands[0], SImode)
2416 || register_operand (operands[1], SImode))"
2433 [(set_attr "type" "pcload_si,move,*,load_si,move,prget,move,store,store,pstore,move,prset,load,pload,pcload_si")
2434 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
2436 ;; t/r must come after r/r, lest reload will try to reload stuff like
2437 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
2438 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
2439 ;; will require a reload.
2440 (define_insn "movsi_ie"
2441 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,r,y,r,y")
2442 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,>,i,r,y,y"))]
2444 && (register_operand (operands[0], SImode)
2445 || register_operand (operands[1], SImode))"
2465 ! move optimized away"
2466 [(set_attr "type" "pcload_si,move,*,load_si,move,prget,move,store,store,pstore,move,prset,load,pload,load,pcload_si,gp_fpul,gp_fpul,nil")
2467 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
2469 (define_insn "movsi_i_lowpart"
2470 [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
2471 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,mr,x,l,t,r,i"))]
2472 "register_operand (operands[0], SImode)
2473 || register_operand (operands[1], SImode)"
2483 [(set_attr "type" "pcload,move,load,move,prget,move,store,pcload")])
2485 (define_expand "movsi"
2486 [(set (match_operand:SI 0 "general_movdst_operand" "")
2487 (match_operand:SI 1 "general_movsrc_operand" ""))]
2489 "{ if (prepare_move_operands (operands, SImode)) DONE; }")
2491 (define_expand "ic_invalidate_line"
2492 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
2493 (match_dup 1)] UNSPEC_ICACHE)
2494 (clobber (scratch:SI))])]
2498 operands[0] = force_reg (Pmode, operands[0]);
2499 operands[1] = force_reg (Pmode, GEN_INT (0xf0000008));
2502 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
2503 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
2504 ;; the requirement *1*00 for associative address writes. The alignment of
2505 ;; %0 implies that its least significant bit is cleared,
2506 ;; thus we clear the V bit of a matching entry if there is one.
2507 (define_insn "ic_invalidate_line_i"
2508 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
2509 (match_operand:SI 1 "register_operand" "r")]
2511 (clobber (match_scratch:SI 2 "=&r"))]
2513 "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
2514 [(set_attr "length" "8")])
2516 (define_insn "movqi_i"
2517 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
2518 (match_operand:QI 1 "general_movsrc_operand" "ri,m,r,t,l,r"))]
2519 "arith_reg_operand (operands[0], QImode)
2520 || arith_reg_operand (operands[1], QImode)"
2528 [(set_attr "type" "move,load,store,move,move,move")])
2530 (define_expand "movqi"
2531 [(set (match_operand:QI 0 "general_operand" "")
2532 (match_operand:QI 1 "general_operand" ""))]
2534 "{ if (prepare_move_operands (operands, QImode)) DONE; }")
2536 (define_insn "movhi_i"
2537 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
2538 (match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
2539 "arith_reg_operand (operands[0], HImode)
2540 || arith_reg_operand (operands[1], HImode)"
2550 [(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
2552 (define_expand "movhi"
2553 [(set (match_operand:HI 0 "general_movdst_operand" "")
2554 (match_operand:HI 1 "general_movsrc_operand" ""))]
2556 "{ if (prepare_move_operands (operands, HImode)) DONE; }")
2558 ;; ??? This should be a define expand.
2560 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
2561 ;; compiled with -m2 -ml -O3 -funroll-loops
2563 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
2564 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))]
2565 "arith_reg_operand (operands[0], DImode)
2566 || arith_reg_operand (operands[1], DImode)"
2567 "* return output_movedouble (insn, operands, DImode);"
2568 [(set_attr "length" "4")
2569 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
2571 ;; If the output is a register and the input is memory or a register, we have
2572 ;; to be careful and see which word needs to be loaded first.
2575 [(set (match_operand:DI 0 "general_movdst_operand" "")
2576 (match_operand:DI 1 "general_movsrc_operand" ""))]
2578 [(set (match_dup 2) (match_dup 3))
2579 (set (match_dup 4) (match_dup 5))]
2584 if ((GET_CODE (operands[0]) == MEM
2585 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2586 || (GET_CODE (operands[1]) == MEM
2587 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2590 if (GET_CODE (operands[0]) == REG)
2591 regno = REGNO (operands[0]);
2592 else if (GET_CODE (operands[0]) == SUBREG)
2593 regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
2594 else if (GET_CODE (operands[0]) == MEM)
2598 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2600 operands[2] = operand_subword (operands[0], 0, 0, DImode);
2601 operands[3] = operand_subword (operands[1], 0, 0, DImode);
2602 operands[4] = operand_subword (operands[0], 1, 0, DImode);
2603 operands[5] = operand_subword (operands[1], 1, 0, DImode);
2607 operands[2] = operand_subword (operands[0], 1, 0, DImode);
2608 operands[3] = operand_subword (operands[1], 1, 0, DImode);
2609 operands[4] = operand_subword (operands[0], 0, 0, DImode);
2610 operands[5] = operand_subword (operands[1], 0, 0, DImode);
2613 if (operands[2] == 0 || operands[3] == 0
2614 || operands[4] == 0 || operands[5] == 0)
2618 (define_expand "movdi"
2619 [(set (match_operand:DI 0 "general_movdst_operand" "")
2620 (match_operand:DI 1 "general_movsrc_operand" ""))]
2622 "{ if (prepare_move_operands (operands, DImode)) DONE; }")
2624 ;; ??? This should be a define expand.
2626 (define_insn "movdf_k"
2627 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
2628 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
2629 "(! TARGET_SH4 || reload_completed
2630 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
2631 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
2632 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
2633 && (arith_reg_operand (operands[0], DFmode)
2634 || arith_reg_operand (operands[1], DFmode))"
2635 "* return output_movedouble (insn, operands, DFmode);"
2636 [(set_attr "length" "4")
2637 (set_attr "type" "move,pcload,load,store")])
2639 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
2640 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
2641 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
2642 ;; the d/m/c/X alternative, which is split later into single-precision
2643 ;; instructions. And when not optimizing, no splits are done before fixing
2644 ;; up pcloads, so we need usable length information for that.
2645 (define_insn "movdf_i4"
2646 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
2647 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
2648 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
2649 (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
2651 && (arith_reg_operand (operands[0], DFmode)
2652 || arith_reg_operand (operands[1], DFmode))"
2664 [(set_attr_alternative "length"
2665 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
2667 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
2668 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2669 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2671 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
2672 (const_int 8) (const_int 8)])
2673 (set_attr "type" "fmove,move,pcload,load,store,pcload,load,store,load,load")
2674 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
2675 (const_string "double")
2676 (const_string "none")))])
2678 ;; Moving DFmode between fp/general registers through memory
2679 ;; (the top of the stack) is faster than moving through fpul even for
2680 ;; little endian. Because the type of an instruction is important for its
2681 ;; scheduling, it is beneficial to split these operations, rather than
2682 ;; emitting them in one single chunk, even if this will expose a stack
2683 ;; use that will prevent scheduling of other stack accesses beyond this
2686 [(set (match_operand:DF 0 "register_operand" "")
2687 (match_operand:DF 1 "register_operand" ""))
2688 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2689 (clobber (match_scratch:SI 3 "=X"))]
2690 "TARGET_SH4 && reload_completed
2691 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
2697 tos = gen_rtx (MEM, DFmode, gen_rtx (PRE_DEC, Pmode, stack_pointer_rtx));
2698 insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
2699 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2700 tos = gen_rtx (MEM, DFmode, gen_rtx (POST_INC, Pmode, stack_pointer_rtx));
2701 insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
2702 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2706 ;; local-alloc sometimes allocates scratch registers even when not required,
2707 ;; so we must be prepared to handle these.
2709 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
2711 [(set (match_operand:DF 0 "general_movdst_operand" "")
2712 (match_operand:DF 1 "general_movsrc_operand" ""))
2713 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2714 (clobber (match_scratch:SI 3 "X"))]
2717 && true_regnum (operands[0]) < 16
2718 && true_regnum (operands[1]) < 16"
2719 [(set (match_dup 0) (match_dup 1))]
2722 /* If this was a reg <-> mem operation with base + index reg addressing,
2723 we have to handle this in a special way. */
2724 rtx mem = operands[0];
2726 if (! memory_operand (mem, DFmode))
2731 if (GET_CODE (mem) == SUBREG && SUBREG_WORD (mem) == 0)
2732 mem = SUBREG_REG (mem);
2733 if (GET_CODE (mem) == MEM)
2735 rtx addr = XEXP (mem, 0);
2736 if (GET_CODE (addr) == PLUS
2737 && GET_CODE (XEXP (addr, 0)) == REG
2738 && GET_CODE (XEXP (addr, 1)) == REG)
2741 rtx reg0 = gen_rtx (REG, Pmode, 0);
2742 rtx regop = operands[store_p], word0 ,word1;
2744 if (GET_CODE (regop) == SUBREG)
2745 regop = alter_subreg (regop);
2746 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
2750 mem = copy_rtx (mem);
2751 PUT_MODE (mem, SImode);
2752 word0 = alter_subreg (gen_rtx (SUBREG, SImode, regop, 0));
2753 word1 = alter_subreg (gen_rtx (SUBREG, SImode, regop, 1));
2754 if (store_p || ! refers_to_regno_p (REGNO (word0),
2755 REGNO (word0) + 1, addr, 0))
2758 ? gen_movsi_ie (mem, word0)
2759 : gen_movsi_ie (word0, mem));
2760 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
2761 mem = copy_rtx (mem);
2763 ? gen_movsi_ie (mem, word1)
2764 : gen_movsi_ie (word1, mem));
2765 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
2769 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
2770 emit_insn (gen_movsi_ie (word1, mem));
2771 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
2772 mem = copy_rtx (mem);
2773 emit_insn (gen_movsi_ie (word0, mem));
2780 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
2782 [(set (match_operand:DF 0 "register_operand" "")
2783 (match_operand:DF 1 "memory_operand" ""))
2784 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2785 (clobber (reg:SI R0_REG))]
2786 "TARGET_SH4 && reload_completed"
2787 [(parallel [(set (match_dup 0) (match_dup 1))
2789 (clobber (scratch:SI))])]
2792 (define_expand "reload_indf"
2793 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
2794 (match_operand:DF 1 "immediate_operand" "FQ"))
2795 (use (reg:PSI FPSCR_REG))
2796 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
2800 (define_expand "reload_outdf"
2801 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
2802 (match_operand:DF 1 "register_operand" "af,r"))
2803 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
2807 ;; Simplify no-op moves.
2809 [(set (match_operand:SF 0 "register_operand" "")
2810 (match_operand:SF 1 "register_operand" ""))
2811 (use (match_operand:PSI 2 "fpscr_operand" ""))
2812 (clobber (match_scratch:SI 3 "X"))]
2813 "TARGET_SH3E && reload_completed
2814 && true_regnum (operands[0]) == true_regnum (operands[1])"
2815 [(set (match_dup 0) (match_dup 0))]
2818 ;; fmovd substitute post-reload splits
2820 [(set (match_operand:DF 0 "register_operand" "")
2821 (match_operand:DF 1 "register_operand" ""))
2822 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2823 (clobber (match_scratch:SI 3 "X"))]
2824 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2825 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
2826 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
2830 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
2831 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst),
2832 gen_rtx (REG, SFmode, src), operands[2]));
2833 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst + 1),
2834 gen_rtx (REG, SFmode, src + 1), operands[2]));
2839 [(set (match_operand:DF 0 "register_operand" "")
2840 (mem:DF (match_operand:SI 1 "register_operand" "")))
2841 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2842 (clobber (match_scratch:SI 3 "X"))]
2843 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2844 && FP_OR_XD_REGISTER_P (operands[0])
2845 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
2849 int regno = true_regnum (operands[0]);
2851 rtx mem2 = gen_rtx (MEM, SFmode, gen_rtx (POST_INC, Pmode, operands[1]));
2853 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2854 regno + !! TARGET_LITTLE_ENDIAN),
2855 mem2, operands[2]));
2856 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[1], NULL_RTX);
2857 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2858 regno + ! TARGET_LITTLE_ENDIAN),
2859 gen_rtx (MEM, SFmode, operands[1]),
2865 [(set (match_operand:DF 0 "register_operand" "")
2866 (match_operand:DF 1 "memory_operand" ""))
2867 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2868 (clobber (match_scratch:SI 3 "X"))]
2869 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2870 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
2874 int regno = true_regnum (operands[0]);
2875 rtx addr, insn, adjust = NULL_RTX;
2876 rtx mem2 = copy_rtx (operands[1]);
2877 rtx reg0 = gen_rtx_REG (SFmode, regno + !! TARGET_LITTLE_ENDIAN);
2878 rtx reg1 = gen_rtx_REG (SFmode, regno + ! TARGET_LITTLE_ENDIAN);
2880 PUT_MODE (mem2, SFmode);
2881 operands[1] = copy_rtx (mem2);
2882 addr = XEXP (mem2, 0);
2883 if (GET_CODE (addr) != POST_INC)
2885 /* If we have to modify the stack pointer, the value that we have
2886 read with post-increment might be modified by an interrupt,
2887 so write it back. */
2888 if (REGNO (addr) == STACK_POINTER_REGNUM)
2889 adjust = gen_push_e (reg0);
2891 adjust = gen_addsi3 (addr, addr, GEN_INT (-4));
2892 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
2894 addr = XEXP (addr, 0);
2895 insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
2896 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2897 insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
2901 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2906 [(set (match_operand:DF 0 "memory_operand" "")
2907 (match_operand:DF 1 "register_operand" ""))
2908 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2909 (clobber (match_scratch:SI 3 "X"))]
2910 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2911 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
2915 int regno = true_regnum (operands[1]);
2916 rtx insn, addr, adjust = NULL_RTX;
2918 operands[0] = copy_rtx (operands[0]);
2919 PUT_MODE (operands[0], SFmode);
2920 insn = emit_insn (gen_movsf_ie (operands[0],
2921 gen_rtx (REG, SFmode,
2922 regno + ! TARGET_LITTLE_ENDIAN),
2924 operands[0] = copy_rtx (operands[0]);
2925 addr = XEXP (operands[0], 0);
2926 if (GET_CODE (addr) != PRE_DEC)
2928 adjust = gen_addsi3 (addr, addr, GEN_INT (4));
2929 emit_insn_before (adjust, insn);
2930 XEXP (operands[0], 0) = addr = gen_rtx (PRE_DEC, SImode, addr);
2932 addr = XEXP (addr, 0);
2934 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2935 insn = emit_insn (gen_movsf_ie (operands[0],
2936 gen_rtx (REG, SFmode,
2937 regno + !! TARGET_LITTLE_ENDIAN),
2939 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2943 ;; The '&' for operand 2 is not really true, but push_secondary_reload
2945 ;; Operand 1 must accept FPUL_REGS in case fpul is reloaded to memory,
2946 ;; to avoid a bogus tertiary reload.
2947 ;; We need a tertiary reload when a floating point register is reloaded
2948 ;; to memory, so the predicate for operand 0 must accept this, while the
2949 ;; constraint of operand 1 must reject the secondary reload register.
2950 ;; Thus, the secondary reload register for this case has to be GENERAL_REGS,
2952 ;; By having the predicate for operand 0 reject any register, we make
2953 ;; sure that the ordinary moves that just need an intermediate register
2954 ;; won't get a bogus tertiary reload.
2955 ;; We use tertiary_reload_operand instead of memory_operand here because
2956 ;; memory_operand rejects operands that are not directly addressible, e.g.:
2957 ;; (mem:SF (plus:SI (reg:SI FP_REG)
2958 ;; (const_int 132)))
2960 (define_expand "reload_outsf"
2961 [(parallel [(set (match_operand:SF 2 "register_operand" "=&r")
2962 (match_operand:SF 1 "register_operand" "y"))
2963 (clobber (scratch:SI))])
2964 (parallel [(set (match_operand:SF 0 "tertiary_reload_operand" "=m")
2966 (clobber (scratch:SI))])]
2972 emit_insn (gen_movsf_ie (operands[2], operands[1], get_fpscr_rtx ()));
2973 emit_insn (gen_movsf_ie (operands[0], operands[2], get_fpscr_rtx ()));
2978 ;; If the output is a register and the input is memory or a register, we have
2979 ;; to be careful and see which word needs to be loaded first.
2982 [(set (match_operand:DF 0 "general_movdst_operand" "")
2983 (match_operand:DF 1 "general_movsrc_operand" ""))]
2985 [(set (match_dup 2) (match_dup 3))
2986 (set (match_dup 4) (match_dup 5))]
2991 if ((GET_CODE (operands[0]) == MEM
2992 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2993 || (GET_CODE (operands[1]) == MEM
2994 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2997 if (GET_CODE (operands[0]) == REG)
2998 regno = REGNO (operands[0]);
2999 else if (GET_CODE (operands[0]) == SUBREG)
3000 regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
3001 else if (GET_CODE (operands[0]) == MEM)
3005 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
3007 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
3008 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
3009 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
3010 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
3014 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
3015 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
3016 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
3017 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
3020 if (operands[2] == 0 || operands[3] == 0
3021 || operands[4] == 0 || operands[5] == 0)
3025 ;; If a base address generated by LEGITIMIZE_ADDRESS for SImode is
3026 ;; used only once, let combine add in the index again.
3029 [(set (match_operand:SI 0 "register_operand" "")
3030 (match_operand:SI 1 "" ""))
3031 (clobber (match_operand 2 "register_operand" ""))]
3032 "! reload_in_progress && ! reload_completed"
3033 [(use (reg:SI R0_REG))]
3036 rtx addr, reg, const_int;
3038 if (GET_CODE (operands[1]) != MEM)
3040 addr = XEXP (operands[1], 0);
3041 if (GET_CODE (addr) != PLUS)
3043 reg = XEXP (addr, 0);
3044 const_int = XEXP (addr, 1);
3045 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
3046 && GET_CODE (const_int) == CONST_INT))
3048 emit_move_insn (operands[2], const_int);
3049 emit_move_insn (operands[0],
3050 change_address (operands[1], VOIDmode,
3051 gen_rtx_PLUS (SImode, reg, operands[2])));
3056 [(set (match_operand:SI 1 "" "")
3057 (match_operand:SI 0 "register_operand" ""))
3058 (clobber (match_operand 2 "register_operand" ""))]
3059 "! reload_in_progress && ! reload_completed"
3060 [(use (reg:SI R0_REG))]
3063 rtx addr, reg, const_int;
3065 if (GET_CODE (operands[1]) != MEM)
3067 addr = XEXP (operands[1], 0);
3068 if (GET_CODE (addr) != PLUS)
3070 reg = XEXP (addr, 0);
3071 const_int = XEXP (addr, 1);
3072 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
3073 && GET_CODE (const_int) == CONST_INT))
3075 emit_move_insn (operands[2], const_int);
3076 emit_move_insn (change_address (operands[1], VOIDmode,
3077 gen_rtx_PLUS (SImode, reg, operands[2])),
3082 (define_expand "movdf"
3083 [(set (match_operand:DF 0 "general_movdst_operand" "")
3084 (match_operand:DF 1 "general_movsrc_operand" ""))]
3088 if (prepare_move_operands (operands, DFmode)) DONE;
3091 emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
3097 (define_insn "movsf_i"
3098 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
3099 (match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
3102 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
3103 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
3104 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
3105 && (arith_reg_operand (operands[0], SFmode)
3106 || arith_reg_operand (operands[1], SFmode))"
3115 [(set_attr "type" "move,move,pcload,load,store,move,move")])
3117 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
3118 ;; update_flow_info would not know where to put REG_EQUAL notes
3119 ;; when the destination changes mode.
3120 (define_insn "movsf_ie"
3121 [(set (match_operand:SF 0 "general_movdst_operand"
3122 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,y")
3123 (match_operand:SF 1 "general_movsrc_operand"
3124 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y"))
3125 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
3126 (clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X"))]
3129 && (arith_reg_operand (operands[0], SFmode)
3130 || arith_reg_operand (operands[1], SFmode))"
3148 ! move optimized away"
3149 [(set_attr "type" "fmove,move,fmove,fmove,pcload,load,store,pcload,load,store,fmove,fmove,load,*,gp_fpul,gp_fpul,nil")
3150 (set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,4,2,2,0")
3151 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
3152 (const_string "single")
3153 (const_string "none")))])
3155 [(set (match_operand:SF 0 "register_operand" "")
3156 (match_operand:SF 1 "register_operand" ""))
3157 (use (match_operand:PSI 2 "fpscr_operand" "c"))
3158 (clobber (reg:SI FPUL_REG))]
3160 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
3162 (clobber (scratch:SI))])
3163 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
3165 (clobber (scratch:SI))])]
3168 (define_expand "movsf"
3169 [(set (match_operand:SF 0 "general_movdst_operand" "")
3170 (match_operand:SF 1 "general_movsrc_operand" ""))]
3174 if (prepare_move_operands (operands, SFmode))
3178 emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
3183 (define_insn "mov_nop"
3184 [(set (match_operand 0 "register_operand" "") (match_dup 0))]
3187 [(set_attr "length" "0")
3188 (set_attr "type" "nil")])
3190 (define_expand "reload_insf"
3191 [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
3192 (match_operand:SF 1 "immediate_operand" "FQ"))
3193 (use (reg:PSI FPSCR_REG))
3194 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
3198 (define_expand "reload_insi"
3199 [(parallel [(set (match_operand:SF 0 "register_operand" "=y")
3200 (match_operand:SF 1 "immediate_operand" "FQ"))
3201 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
3205 (define_insn "*movsi_y"
3206 [(set (match_operand:SI 0 "register_operand" "=y,y")
3207 (match_operand:SI 1 "immediate_operand" "Qi,I"))
3208 (clobber (match_scratch:SI 2 "=&z,r"))]
3210 && (reload_in_progress || reload_completed)"
3212 [(set_attr "length" "4")
3213 (set_attr "type" "pcload,move")])
3216 [(set (match_operand:SI 0 "register_operand" "")
3217 (match_operand:SI 1 "immediate_operand" ""))
3218 (clobber (match_operand:SI 2 "register_operand" ""))]
3220 [(set (match_dup 2) (match_dup 1))
3221 (set (match_dup 0) (match_dup 2))]
3225 [(set (match_operand:SI 0 "register_operand" "")
3226 (match_operand:SI 1 "memory_operand" ""))
3227 (clobber (reg:SI R0_REG))]
3229 [(set (match_dup 0) (match_dup 1))]
3232 ;; ------------------------------------------------------------------------
3233 ;; Define the real conditional branch instructions.
3234 ;; ------------------------------------------------------------------------
3236 (define_insn "branch_true"
3237 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
3238 (label_ref (match_operand 0 "" ""))
3241 "* return output_branch (1, insn, operands);"
3242 [(set_attr "type" "cbranch")])
3244 (define_insn "branch_false"
3245 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
3246 (label_ref (match_operand 0 "" ""))
3249 "* return output_branch (0, insn, operands);"
3250 [(set_attr "type" "cbranch")])
3252 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
3253 ;; which destination is too far away.
3254 ;; The const_int_operand is distinct for each branch target; it avoids
3255 ;; unwanted matches with redundant_insn.
3256 (define_insn "block_branch_redirect"
3257 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
3260 [(set_attr "length" "0")])
3262 ;; This one has the additional purpose to record a possible scratch register
3263 ;; for the following branch.
3264 (define_insn "indirect_jump_scratch"
3265 [(set (match_operand 0 "register_operand" "=r")
3266 (unspec [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))]
3269 [(set_attr "length" "0")])
3271 ;; Conditional branch insns
3273 (define_expand "beq"
3275 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3276 (label_ref (match_operand 0 "" ""))
3279 "from_compare (operands, EQ);")
3281 (define_expand "bne"
3283 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3284 (label_ref (match_operand 0 "" ""))
3287 "from_compare (operands, EQ);")
3289 (define_expand "bgt"
3291 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3292 (label_ref (match_operand 0 "" ""))
3295 "from_compare (operands, GT);")
3297 (define_expand "blt"
3299 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3300 (label_ref (match_operand 0 "" ""))
3305 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3307 rtx tmp = sh_compare_op0;
3308 sh_compare_op0 = sh_compare_op1;
3309 sh_compare_op1 = tmp;
3310 emit_insn (gen_bgt (operands[0]));
3313 from_compare (operands, GE);
3316 (define_expand "ble"
3318 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3319 (label_ref (match_operand 0 "" ""))
3326 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3328 rtx tmp = sh_compare_op0;
3329 sh_compare_op0 = sh_compare_op1;
3330 sh_compare_op1 = tmp;
3331 emit_insn (gen_bge (operands[0]));
3334 from_compare (operands, GT);
3337 (define_expand "bge"
3339 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3340 (label_ref (match_operand 0 "" ""))
3347 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3349 rtx tmp = sh_compare_op0;
3350 sh_compare_op0 = sh_compare_op1;
3351 sh_compare_op1 = tmp;
3352 emit_insn (gen_ble (operands[0]));
3355 from_compare (operands, GE);
3358 (define_expand "bgtu"
3360 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3361 (label_ref (match_operand 0 "" ""))
3364 "from_compare (operands, GTU); ")
3366 (define_expand "bltu"
3368 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3369 (label_ref (match_operand 0 "" ""))
3372 "from_compare (operands, GEU);")
3374 (define_expand "bgeu"
3376 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3377 (label_ref (match_operand 0 "" ""))
3380 "from_compare (operands, GEU);")
3382 (define_expand "bleu"
3384 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3385 (label_ref (match_operand 0 "" ""))
3388 "from_compare (operands, GTU);")
3390 ;; ------------------------------------------------------------------------
3391 ;; Jump and linkage insns
3392 ;; ------------------------------------------------------------------------
3396 (label_ref (match_operand 0 "" "")))]
3400 /* The length is 16 if the delay slot is unfilled. */
3401 if (get_attr_length(insn) > 4)
3402 return output_far_jump(insn, operands[0]);
3404 return \"bra %l0%#\";
3406 [(set_attr "type" "jump")
3407 (set_attr "needs_delay_slot" "yes")])
3409 (define_insn "calli"
3410 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3411 (match_operand 1 "" ""))
3412 (use (reg:PSI FPSCR_REG))
3413 (clobber (reg:SI PR_REG))]
3416 [(set_attr "type" "call")
3417 (set (attr "fp_mode")
3418 (if_then_else (eq_attr "fpu_single" "yes")
3419 (const_string "single") (const_string "double")))
3420 (set_attr "needs_delay_slot" "yes")])
3422 ;; This is a pc-rel call, using bsrf, for use with PIC.
3424 (define_insn "calli_pcrel"
3425 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3426 (match_operand 1 "" ""))
3427 (use (reg:PSI FPSCR_REG))
3428 (use (reg:SI PIC_REG))
3429 (use (match_operand 2 "" ""))
3430 (clobber (reg:SI PR_REG))]
3433 [(set_attr "type" "call")
3434 (set (attr "fp_mode")
3435 (if_then_else (eq_attr "fpu_single" "yes")
3436 (const_string "single") (const_string "double")))
3437 (set_attr "needs_delay_slot" "yes")])
3439 (define_insn_and_split "call_pcrel"
3440 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
3441 (match_operand 1 "" ""))
3442 (use (reg:PSI FPSCR_REG))
3443 (use (reg:SI PIC_REG))
3444 (clobber (reg:SI PR_REG))
3445 (clobber (match_scratch:SI 2 "=r"))]
3452 rtx lab = gen_call_site ();
3454 if (SYMBOL_REF_FLAG (operands[0]))
3455 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
3457 emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
3458 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], lab));
3461 [(set_attr "type" "call")
3462 (set (attr "fp_mode")
3463 (if_then_else (eq_attr "fpu_single" "yes")
3464 (const_string "single") (const_string "double")))
3465 (set_attr "needs_delay_slot" "yes")])
3467 (define_insn "call_valuei"
3468 [(set (match_operand 0 "" "=rf")
3469 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3470 (match_operand 2 "" "")))
3471 (use (reg:PSI FPSCR_REG))
3472 (clobber (reg:SI PR_REG))]
3475 [(set_attr "type" "call")
3476 (set (attr "fp_mode")
3477 (if_then_else (eq_attr "fpu_single" "yes")
3478 (const_string "single") (const_string "double")))
3479 (set_attr "needs_delay_slot" "yes")])
3481 (define_insn "call_valuei_pcrel"
3482 [(set (match_operand 0 "" "=rf")
3483 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3484 (match_operand 2 "" "")))
3485 (use (reg:PSI FPSCR_REG))
3486 (use (reg:SI PIC_REG))
3487 (use (match_operand 3 "" ""))
3488 (clobber (reg:SI PR_REG))]
3491 [(set_attr "type" "call")
3492 (set (attr "fp_mode")
3493 (if_then_else (eq_attr "fpu_single" "yes")
3494 (const_string "single") (const_string "double")))
3495 (set_attr "needs_delay_slot" "yes")])
3497 (define_insn_and_split "call_value_pcrel"
3498 [(set (match_operand 0 "" "=rf")
3499 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
3500 (match_operand 2 "" "")))
3501 (use (reg:PSI FPSCR_REG))
3502 (use (reg:SI PIC_REG))
3503 (clobber (reg:SI PR_REG))
3504 (clobber (match_scratch:SI 3 "=r"))]
3511 rtx lab = gen_call_site ();
3513 if (SYMBOL_REF_FLAG (operands[1]))
3514 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
3516 emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
3517 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
3521 [(set_attr "type" "call")
3522 (set (attr "fp_mode")
3523 (if_then_else (eq_attr "fpu_single" "yes")
3524 (const_string "single") (const_string "double")))
3525 (set_attr "needs_delay_slot" "yes")])
3527 (define_expand "call"
3528 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
3529 (match_operand 1 "" ""))
3530 (use (reg:PSI FPSCR_REG))
3531 (clobber (reg:SI PR_REG))])]
3535 if (flag_pic && TARGET_SH2
3536 && GET_CODE (operands[0]) == MEM
3537 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
3539 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
3543 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
3546 (define_expand "call_value"
3547 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
3548 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
3549 (match_operand 2 "" "")))
3550 (use (reg:PSI FPSCR_REG))
3551 (clobber (reg:SI PR_REG))])]
3555 if (flag_pic && TARGET_SH2
3556 && GET_CODE (operands[1]) == MEM
3557 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
3559 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
3564 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
3567 (define_insn "sibcalli"
3568 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
3569 (match_operand 1 "" ""))
3570 (use (reg:PSI FPSCR_REG))
3574 [(set_attr "needs_delay_slot" "yes")
3575 (set_attr "type" "jump_ind")])
3577 (define_insn "sibcalli_pcrel"
3578 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
3579 (match_operand 1 "" ""))
3580 (use (match_operand 2 "" ""))
3581 (use (reg:PSI FPSCR_REG))
3585 [(set_attr "needs_delay_slot" "yes")
3586 (set_attr "type" "jump_ind")])
3588 (define_insn_and_split "sibcall_pcrel"
3589 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
3590 (match_operand 1 "" ""))
3591 (use (reg:PSI FPSCR_REG))
3592 (clobber (match_scratch:SI 2 "=k"))
3600 rtx lab = gen_call_site ();
3603 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
3604 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
3606 SIBLING_CALL_P (call_insn) = 1;
3610 (define_expand "sibcall"
3612 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
3613 (match_operand 1 "" ""))
3614 (use (reg:PSI FPSCR_REG))
3619 if (flag_pic && TARGET_SH2
3620 && GET_CODE (operands[0]) == MEM
3621 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
3622 /* The PLT needs the PIC register, but the epilogue would have
3623 to restore it, so we can only use PC-relative PIC calls for
3624 static functions. */
3625 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
3627 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
3631 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
3634 (define_expand "sibcall_value"
3635 [(set (match_operand 0 "" "")
3636 (call (match_operand 1 "" "")
3637 (match_operand 2 "" "")))]
3641 emit_call_insn (gen_sibcall (operands[1], operands[2]));
3645 (define_expand "sibcall_epilogue"
3650 sh_expand_epilogue ();
3654 (define_insn "indirect_jump"
3656 (match_operand:SI 0 "arith_reg_operand" "r"))]
3659 [(set_attr "needs_delay_slot" "yes")
3660 (set_attr "type" "jump_ind")])
3662 ;; The use of operand 1 / 2 helps us distinguish case table jumps
3663 ;; which can be present in structured code from indirect jumps which can not
3664 ;; be present in structured code. This allows -fprofile-arcs to work.
3666 ;; For SH1 processors.
3667 (define_insn "casesi_jump_1"
3669 (match_operand:SI 0 "register_operand" "r"))
3670 (use (label_ref (match_operand 1 "" "")))]
3673 [(set_attr "needs_delay_slot" "yes")
3674 (set_attr "type" "jump_ind")])
3676 ;; For all later processors.
3677 (define_insn "casesi_jump_2"
3678 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
3679 (label_ref (match_operand 1 "" ""))))
3680 (use (label_ref (match_operand 2 "" "")))]
3682 && (! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn)"
3684 [(set_attr "needs_delay_slot" "yes")
3685 (set_attr "type" "jump_ind")])
3687 ;; Call subroutine returning any type.
3688 ;; ??? This probably doesn't work.
3690 (define_expand "untyped_call"
3691 [(parallel [(call (match_operand 0 "" "")
3693 (match_operand 1 "" "")
3694 (match_operand 2 "" "")])]
3700 emit_call_insn (gen_call (operands[0], const0_rtx));
3702 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3704 rtx set = XVECEXP (operands[2], 0, i);
3705 emit_move_insn (SET_DEST (set), SET_SRC (set));
3708 /* The optimizer does not know that the call sets the function value
3709 registers we stored in the result block. We avoid problems by
3710 claiming that all hard registers are used and clobbered at this
3712 emit_insn (gen_blockage ());
3717 ;; ------------------------------------------------------------------------
3719 ;; ------------------------------------------------------------------------
3722 [(set (reg:SI T_REG)
3723 (eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
3724 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
3727 [(set_attr "type" "arith")])
3734 ;; Load address of a label. This is only generated by the casesi expand,
3735 ;; and by machine_dependent_reorg (fixing up fp moves).
3736 ;; This must use unspec, because this only works for labels that are
3740 [(set (reg:SI R0_REG)
3741 (unspec [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
3744 [(set_attr "in_delay_slot" "no")
3745 (set_attr "type" "arith")])
3747 ;; machine_dependent_reorg() will make this a `mova'.
3748 (define_insn "mova_const"
3749 [(set (reg:SI R0_REG)
3750 (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
3753 [(set_attr "in_delay_slot" "no")
3754 (set_attr "type" "arith")])
3756 (define_expand "GOTaddr2picreg"
3757 [(set (reg:SI R0_REG)
3758 (unspec [(const (unspec [(match_dup 1)] UNSPEC_PIC))]
3760 (set (match_dup 0) (const (unspec [(match_dup 1)] UNSPEC_PIC)))
3761 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
3764 operands[0] = pic_offset_table_rtx;
3765 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
3769 (define_expand "call_site"
3770 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
3774 static HOST_WIDE_INT i = 0;
3775 operands[0] = GEN_INT (i);
3779 (define_expand "sym_label2reg"
3780 [(set (match_operand:SI 0 "" "")
3782 (const (unspec [(match_operand:SI 1 "" "")] UNSPEC_PIC))
3784 (match_operand:SI 2 "" "")
3788 (define_expand "symGOT2reg"
3789 [(set (match_operand:SI 0 "" "")
3790 (const (unspec [(match_operand:SI 1 "" "")] UNSPEC_GOT)))
3791 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
3792 (set (match_dup 0) (mem:SI (match_dup 0)))]
3796 operands[2] = pic_offset_table_rtx;
3799 (define_expand "symGOTOFF2reg"
3800 [(set (match_operand:SI 0 "" "")
3801 (const (unspec [(match_operand:SI 1 "" "")] UNSPEC_GOTOFF)))
3802 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3806 operands[2] = pic_offset_table_rtx;
3809 (define_expand "symPLT_label2reg"
3810 [(set (match_operand:SI 0 "" "")
3813 (unspec [(match_operand:SI 1 "" "")] UNSPEC_PLT)
3816 (match_operand:SI 2 "" "")
3818 ;; Even though the PIC register is not really used by the call
3819 ;; sequence in which this is expanded, the PLT code assumes the PIC
3820 ;; register is set, so we must not skip its initialization. Since
3821 ;; we only use this expand as part of calling sequences, and never
3822 ;; to take the address of a function, this is the best point to
3823 ;; insert the (use). Using the PLT to take the address of a
3824 ;; function would be wrong, not only because the PLT entry could
3825 ;; then be called from a function that doesn't initialize the PIC
3826 ;; register to the proper GOT, but also because pointers to the
3827 ;; same function might not compare equal, should they be set by
3828 ;; different shared libraries.
3829 (use (reg:SI PIC_REG))]
3833 ;; case instruction for switch statements.
3835 ;; Operand 0 is index
3836 ;; operand 1 is the minimum bound
3837 ;; operand 2 is the maximum bound - minimum bound + 1
3838 ;; operand 3 is CODE_LABEL for the table;
3839 ;; operand 4 is the CODE_LABEL to go to if index out of range.
3841 (define_expand "casesi"
3842 [(match_operand:SI 0 "arith_reg_operand" "")
3843 (match_operand:SI 1 "arith_reg_operand" "")
3844 (match_operand:SI 2 "arith_reg_operand" "")
3845 (match_operand 3 "" "") (match_operand 4 "" "")]
3849 rtx reg = gen_reg_rtx (SImode);
3850 rtx reg2 = gen_reg_rtx (SImode);
3851 operands[1] = copy_to_mode_reg (SImode, operands[1]);
3852 operands[2] = copy_to_mode_reg (SImode, operands[2]);
3853 /* If optimizing, casesi_worker depends on the mode of the instruction
3854 before label it 'uses' - operands[3]. */
3855 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
3857 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
3859 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
3861 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
3862 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
3863 operands[3], but to lab. We will fix this up in
3864 machine_dependent_reorg. */
3869 (define_expand "casesi_0"
3870 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
3871 (set (match_dup 4) (minus:SI (match_dup 4)
3872 (match_operand:SI 1 "arith_operand" "")))
3874 (gtu:SI (match_dup 4)
3875 (match_operand:SI 2 "arith_reg_operand" "")))
3877 (if_then_else (ne (reg:SI T_REG)
3879 (label_ref (match_operand 3 "" ""))
3884 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
3885 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
3886 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
3888 (define_insn "casesi_worker_0"
3889 [(set (match_operand:SI 0 "register_operand" "=r,r")
3890 (unspec [(match_operand 1 "register_operand" "0,r")
3891 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3892 (clobber (match_scratch:SI 3 "=X,1"))
3893 (clobber (match_scratch:SI 4 "=&z,z"))]
3898 [(set (match_operand:SI 0 "register_operand" "")
3899 (unspec [(match_operand 1 "register_operand" "")
3900 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3901 (clobber (match_scratch:SI 3 ""))
3902 (clobber (match_scratch:SI 4 ""))]
3903 "! TARGET_SH2 && reload_completed"
3904 [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] UNSPEC_MOVA))
3905 (parallel [(set (match_dup 0)
3906 (unspec [(reg:SI R0_REG) (match_dup 1)
3907 (label_ref (match_dup 2))] UNSPEC_CASESI))
3908 (clobber (match_dup 3))])
3909 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
3910 "LABEL_NUSES (operands[2])++;")
3913 [(set (match_operand:SI 0 "register_operand" "")
3914 (unspec [(match_operand 1 "register_operand" "")
3915 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3916 (clobber (match_scratch:SI 3 ""))
3917 (clobber (match_scratch:SI 4 ""))]
3918 "TARGET_SH2 && reload_completed"
3919 [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] UNSPEC_MOVA))
3920 (parallel [(set (match_dup 0)
3921 (unspec [(reg:SI R0_REG) (match_dup 1)
3922 (label_ref (match_dup 2))] UNSPEC_CASESI))
3923 (clobber (match_dup 3))])]
3924 "LABEL_NUSES (operands[2])++;")
3926 (define_insn "*casesi_worker"
3927 [(set (match_operand:SI 0 "register_operand" "=r,r")
3928 (unspec [(reg:SI R0_REG) (match_operand 1 "register_operand" "0,r")
3929 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3930 (clobber (match_scratch:SI 3 "=X,1"))]
3934 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
3936 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
3939 switch (GET_MODE (diff_vec))
3942 return \"shll2 %1\;mov.l @(r0,%1),%0\";
3944 return \"add %1,%1\;mov.w @(r0,%1),%0\";
3946 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
3947 return \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
3948 return \"mov.b @(r0,%1),%0\";
3953 [(set_attr "length" "4")])
3955 (define_expand "return"
3957 "reload_completed && ! sh_need_epilogue ()"
3960 (define_insn "*return_i"
3964 [(set_attr "type" "return")
3965 (set_attr "needs_delay_slot" "yes")])
3967 (define_expand "prologue"
3970 "sh_expand_prologue (); DONE;")
3972 (define_expand "epilogue"
3975 "sh_expand_epilogue ();")
3977 (define_insn "blockage"
3978 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
3981 [(set_attr "length" "0")])
3983 ;; ------------------------------------------------------------------------
3985 ;; ------------------------------------------------------------------------
3988 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3989 (eq:SI (reg:SI T_REG) (const_int 1)))]
3992 [(set_attr "type" "arith")])
3994 (define_expand "seq"
3995 [(set (match_operand:SI 0 "arith_reg_operand" "")
3998 "operands[1] = prepare_scc_operands (EQ);")
4000 (define_expand "slt"
4001 [(set (match_operand:SI 0 "arith_reg_operand" "")
4004 "operands[1] = prepare_scc_operands (LT);")
4006 (define_expand "sle"
4007 [(match_operand:SI 0 "arith_reg_operand" "")]
4011 rtx tmp = sh_compare_op0;
4012 sh_compare_op0 = sh_compare_op1;
4013 sh_compare_op1 = tmp;
4014 emit_insn (gen_sge (operands[0]));
4018 (define_expand "sgt"
4019 [(set (match_operand:SI 0 "arith_reg_operand" "")
4022 "operands[1] = prepare_scc_operands (GT);")
4024 (define_expand "sge"
4025 [(set (match_operand:SI 0 "arith_reg_operand" "")
4030 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
4034 rtx lab = gen_label_rtx ();
4035 prepare_scc_operands (EQ);
4036 emit_jump_insn (gen_branch_true (lab));
4037 prepare_scc_operands (GT);
4039 emit_insn (gen_movt (operands[0]));
4042 emit_insn (gen_movnegt (operands[0], prepare_scc_operands (LT)));
4045 operands[1] = prepare_scc_operands (GE);
4048 (define_expand "sgtu"
4049 [(set (match_operand:SI 0 "arith_reg_operand" "")
4052 "operands[1] = prepare_scc_operands (GTU);")
4054 (define_expand "sltu"
4055 [(set (match_operand:SI 0 "arith_reg_operand" "")
4058 "operands[1] = prepare_scc_operands (LTU);")
4060 (define_expand "sleu"
4061 [(set (match_operand:SI 0 "arith_reg_operand" "")
4064 "operands[1] = prepare_scc_operands (LEU);")
4066 (define_expand "sgeu"
4067 [(set (match_operand:SI 0 "arith_reg_operand" "")
4070 "operands[1] = prepare_scc_operands (GEU);")
4072 ;; sne moves the complement of the T reg to DEST like this:
4076 ;; This is better than xoring compare result with 1 because it does
4077 ;; not require r0 and further, the -1 may be CSE-ed or lifted out of a
4080 (define_expand "sne"
4081 [(set (match_dup 2) (const_int -1))
4082 (parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
4083 (neg:SI (plus:SI (match_dup 1)
4086 (ne:SI (ior:SI (match_dup 1) (match_dup 2))
4091 operands[1] = prepare_scc_operands (EQ);
4092 operands[2] = gen_reg_rtx (SImode);
4095 ;; Use the same trick for FP sle / sge
4096 (define_expand "movnegt"
4097 [(set (match_dup 2) (const_int -1))
4098 (parallel [(set (match_operand 0 "" "")
4099 (neg:SI (plus:SI (match_dup 1)
4102 (ne:SI (ior:SI (match_operand 1 "" "") (match_dup 2))
4105 "operands[2] = gen_reg_rtx (SImode);")
4107 ;; Recognize mov #-1/negc/neg sequence, and change it to movt/add #-1.
4108 ;; This prevents a regression that occurred when we switched from xor to
4112 [(set (match_operand:SI 0 "arith_reg_operand" "")
4113 (plus:SI (reg:SI T_REG)
4116 [(set (match_dup 0) (eq:SI (reg:SI T_REG) (const_int 1)))
4117 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
4120 ;; -------------------------------------------------------------------------
4121 ;; Instructions to cope with inline literal tables
4122 ;; -------------------------------------------------------------------------
4124 ; 2 byte integer in line
4126 (define_insn "consttable_2"
4127 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")]
4132 assemble_integer (operands[0], 2, 1);
4135 [(set_attr "length" "2")
4136 (set_attr "in_delay_slot" "no")])
4138 ; 4 byte integer in line
4140 (define_insn "consttable_4"
4141 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")]
4146 assemble_integer (operands[0], 4, 1);
4149 [(set_attr "length" "4")
4150 (set_attr "in_delay_slot" "no")])
4152 ; 8 byte integer in line
4154 (define_insn "consttable_8"
4155 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")]
4160 assemble_integer (operands[0], 8, 1);
4163 [(set_attr "length" "8")
4164 (set_attr "in_delay_slot" "no")])
4166 ; 4 byte floating point
4168 (define_insn "consttable_sf"
4169 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")]
4174 union real_extract u;
4175 memcpy (&u, &CONST_DOUBLE_LOW (operands[0]), sizeof u);
4176 assemble_real (u.d, SFmode);
4179 [(set_attr "length" "4")
4180 (set_attr "in_delay_slot" "no")])
4182 ; 8 byte floating point
4184 (define_insn "consttable_df"
4185 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")]
4190 union real_extract u;
4191 memcpy (&u, &CONST_DOUBLE_LOW (operands[0]), sizeof u);
4192 assemble_real (u.d, DFmode);
4195 [(set_attr "length" "8")
4196 (set_attr "in_delay_slot" "no")])
4198 ;; Alignment is needed for some constant tables; it may also be added for
4199 ;; Instructions at the start of loops, or after unconditional branches.
4200 ;; ??? We would get more accurate lengths if we did instruction
4201 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
4202 ;; here is too conservative.
4204 ; align to a two byte boundary
4206 (define_expand "align_2"
4207 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
4211 ; align to a four byte boundary
4212 ;; align_4 and align_log are instructions for the starts of loops, or
4213 ;; after unconditional branches, which may take up extra room.
4215 (define_expand "align_4"
4216 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
4220 ; align to a cache line boundary
4222 (define_insn "align_log"
4223 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
4226 [(set_attr "length" "0")
4227 (set_attr "in_delay_slot" "no")])
4229 ; emitted at the end of the literal table, used to emit the
4230 ; 32bit branch labels if needed.
4232 (define_insn "consttable_end"
4233 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
4235 "* return output_jump_label_table ();"
4236 [(set_attr "in_delay_slot" "no")])
4238 ;; -------------------------------------------------------------------------
4240 ;; -------------------------------------------------------------------------
4242 ;; String/block move insn.
4244 (define_expand "movstrsi"
4245 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
4246 (mem:BLK (match_operand:BLK 1 "" "")))
4247 (use (match_operand:SI 2 "nonmemory_operand" ""))
4248 (use (match_operand:SI 3 "immediate_operand" ""))
4249 (clobber (reg:SI PR_REG))
4250 (clobber (reg:SI R4_REG))
4251 (clobber (reg:SI R5_REG))
4252 (clobber (reg:SI R0_REG))])]
4256 if(expand_block_move (operands))
4261 (define_insn "block_move_real"
4262 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4263 (mem:BLK (reg:SI R5_REG)))
4264 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4265 (clobber (reg:SI PR_REG))
4266 (clobber (reg:SI R0_REG))])]
4269 [(set_attr "type" "sfunc")
4270 (set_attr "needs_delay_slot" "yes")])
4272 (define_insn "block_lump_real"
4273 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4274 (mem:BLK (reg:SI R5_REG)))
4275 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4276 (use (reg:SI R6_REG))
4277 (clobber (reg:SI PR_REG))
4278 (clobber (reg:SI T_REG))
4279 (clobber (reg:SI R4_REG))
4280 (clobber (reg:SI R5_REG))
4281 (clobber (reg:SI R6_REG))
4282 (clobber (reg:SI R0_REG))])]
4285 [(set_attr "type" "sfunc")
4286 (set_attr "needs_delay_slot" "yes")])
4288 (define_insn "block_move_real_i4"
4289 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4290 (mem:BLK (reg:SI R5_REG)))
4291 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4292 (clobber (reg:SI PR_REG))
4293 (clobber (reg:SI R0_REG))
4294 (clobber (reg:SI R1_REG))
4295 (clobber (reg:SI R2_REG))])]
4298 [(set_attr "type" "sfunc")
4299 (set_attr "needs_delay_slot" "yes")])
4301 (define_insn "block_lump_real_i4"
4302 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4303 (mem:BLK (reg:SI R5_REG)))
4304 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4305 (use (reg:SI R6_REG))
4306 (clobber (reg:SI PR_REG))
4307 (clobber (reg:SI T_REG))
4308 (clobber (reg:SI R4_REG))
4309 (clobber (reg:SI R5_REG))
4310 (clobber (reg:SI R6_REG))
4311 (clobber (reg:SI R0_REG))
4312 (clobber (reg:SI R1_REG))
4313 (clobber (reg:SI R2_REG))
4314 (clobber (reg:SI R3_REG))])]
4317 [(set_attr "type" "sfunc")
4318 (set_attr "needs_delay_slot" "yes")])
4320 ;; -------------------------------------------------------------------------
4321 ;; Floating point instructions.
4322 ;; -------------------------------------------------------------------------
4324 ;; ??? All patterns should have a type attribute.
4326 (define_expand "fpu_switch0"
4327 [(set (match_operand:SI 0 "" "") (match_dup 2))
4328 (set (match_dup 1) (mem:PSI (match_dup 0)))]
4332 operands[1] = get_fpscr_rtx ();
4333 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
4335 operands[2] = legitimize_pic_address (operands[2], SImode,
4336 no_new_pseudos ? operands[0] : 0);
4339 (define_expand "fpu_switch1"
4340 [(set (match_operand:SI 0 "" "") (match_dup 2))
4341 (set (match_dup 3) (plus:SI (match_dup 0) (const_int 4)))
4342 (set (match_dup 1) (mem:PSI (match_dup 3)))]
4346 operands[1] = get_fpscr_rtx ();
4347 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
4349 operands[2] = legitimize_pic_address (operands[2], SImode,
4350 no_new_pseudos ? operands[0] : 0);
4351 operands[3] = no_new_pseudos ? operands[0] : gen_reg_rtx (SImode);
4354 (define_expand "movpsi"
4355 [(set (match_operand:PSI 0 "register_operand" "")
4356 (match_operand:PSI 1 "general_movsrc_operand" ""))]
4360 ;; The c / m alternative is a fake to guide reload to load directly into
4361 ;; fpscr, since reload doesn't know how to use post-increment.
4362 ;; GO_IF_LEGITIMATE_ADDRESS guards about bogus addresses before reload,
4363 ;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
4364 ;; predicate after reload.
4365 ;; The gp_fpul type for r/!c might look a bit odd, but it actually schedules
4366 ;; like a gpr <-> fpul move.
4367 (define_insn "fpu_switch"
4368 [(set (match_operand:PSI 0 "register_operand" "=c,c,r,c,c,r,m,r")
4369 (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c"))]
4371 && (! reload_completed
4372 || true_regnum (operands[0]) != FPSCR_REG
4373 || GET_CODE (operands[1]) != MEM
4374 || GET_CODE (XEXP (operands[1], 0)) != PLUS)"
4376 ! precision stays the same
4384 [(set_attr "length" "0,2,2,4,2,2,2,2")
4385 (set_attr "type" "dfp_conv,dfp_conv,load,dfp_conv,dfp_conv,move,store,gp_fpul")])
4388 [(set (reg:PSI FPSCR_REG)
4389 (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
4390 "TARGET_SH4 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
4391 [(set (match_dup 0) (match_dup 0))]
4394 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
4395 gen_rtx (MEM, PSImode,
4396 gen_rtx (POST_INC, Pmode,
4398 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
4402 [(set (reg:PSI FPSCR_REG)
4403 (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
4405 [(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))]
4408 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
4409 gen_rtx (MEM, PSImode,
4410 gen_rtx (POST_INC, Pmode,
4412 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
4415 ;; ??? This uses the fp unit, but has no type indicating that.
4416 ;; If we did that, this would either give a bogus latency or introduce
4417 ;; a bogus FIFO constraint.
4418 ;; Since this insn is currently only used for prologues/epilogues,
4419 ;; it is probably best to claim no function unit, which matches the
4421 (define_insn "toggle_sz"
4422 [(set (reg:PSI FPSCR_REG)
4423 (xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
4427 (define_expand "addsf3"
4428 [(match_operand:SF 0 "arith_reg_operand" "")
4429 (match_operand:SF 1 "arith_reg_operand" "")
4430 (match_operand:SF 2 "arith_reg_operand" "")]
4432 "{ expand_sf_binop (&gen_addsf3_i, operands); DONE; }")
4434 (define_insn "addsf3_i"
4435 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4436 (plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
4437 (match_operand:SF 2 "arith_reg_operand" "f")))
4438 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4441 [(set_attr "type" "fp")
4442 (set_attr "fp_mode" "single")])
4444 (define_expand "subsf3"
4445 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4446 (match_operand:SF 1 "fp_arith_reg_operand" "")
4447 (match_operand:SF 2 "fp_arith_reg_operand" "")]
4449 "{ expand_sf_binop (&gen_subsf3_i, operands); DONE; }")
4451 (define_insn "subsf3_i"
4452 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4453 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
4454 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
4455 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4458 [(set_attr "type" "fp")
4459 (set_attr "fp_mode" "single")])
4461 ;; Unfortunately, the combiner is unable to cope with the USE of the FPSCR
4462 ;; register in feeding fp instructions. Thus, we cannot generate fmac for
4463 ;; mixed-precision SH4 targets. To allow it to be still generated for the
4464 ;; SH3E, we use a separate insn for SH3E mulsf3.
4466 (define_expand "mulsf3"
4467 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4468 (match_operand:SF 1 "fp_arith_reg_operand" "")
4469 (match_operand:SF 2 "fp_arith_reg_operand" "")]
4474 expand_sf_binop (&gen_mulsf3_i4, operands);
4476 emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
4480 (define_insn "mulsf3_i4"
4481 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4482 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
4483 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
4484 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4487 [(set_attr "type" "fp")
4488 (set_attr "fp_mode" "single")])
4490 (define_insn "mulsf3_ie"
4491 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4492 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
4493 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
4494 "TARGET_SH3E && ! TARGET_SH4"
4496 [(set_attr "type" "fp")])
4498 (define_insn "*macsf3"
4499 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4500 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
4501 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
4502 (match_operand:SF 3 "arith_reg_operand" "0")))
4503 (use (match_operand:PSI 4 "fpscr_operand" "c"))]
4504 "TARGET_SH3E && ! TARGET_SH4"
4506 [(set_attr "type" "fp")
4507 (set_attr "fp_mode" "single")])
4509 (define_expand "divsf3"
4510 [(match_operand:SF 0 "arith_reg_operand" "")
4511 (match_operand:SF 1 "arith_reg_operand" "")
4512 (match_operand:SF 2 "arith_reg_operand" "")]
4514 "{ expand_sf_binop (&gen_divsf3_i, operands); DONE; }")
4516 (define_insn "divsf3_i"
4517 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4518 (div:SF (match_operand:SF 1 "arith_reg_operand" "0")
4519 (match_operand:SF 2 "arith_reg_operand" "f")))
4520 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4523 [(set_attr "type" "fdiv")
4524 (set_attr "fp_mode" "single")])
4526 (define_expand "floatsisf2"
4527 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
4528 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
4534 emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4539 (define_insn "floatsisf2_i4"
4540 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4541 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
4542 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4545 [(set_attr "type" "fp")
4546 (set_attr "fp_mode" "single")])
4548 (define_insn "*floatsisf2_ie"
4549 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4550 (float:SF (match_operand:SI 1 "fpul_operand" "y")))]
4551 "TARGET_SH3E && ! TARGET_SH4"
4553 [(set_attr "type" "fp")])
4555 (define_expand "fix_truncsfsi2"
4556 [(set (match_operand:SI 0 "fpul_operand" "=y")
4557 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4563 emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4568 (define_insn "fix_truncsfsi2_i4"
4569 [(set (match_operand:SI 0 "fpul_operand" "=y")
4570 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4571 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4574 [(set_attr "type" "fp")
4575 (set_attr "fp_mode" "single")])
4577 ;; ??? This pattern is used nowhere. fix_truncsfsi2 always expands to
4578 ;; fix_truncsfsi2_i4.
4579 ;; (define_insn "fix_truncsfsi2_i4_2"
4580 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4581 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4582 ;; (use (reg:PSI FPSCR_REG))
4583 ;; (clobber (reg:SI FPUL_REG))]
4586 ;; [(set_attr "length" "4")
4587 ;; (set_attr "fp_mode" "single")])
4590 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4591 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4592 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4593 ;; (clobber (reg:SI FPUL_REG))]
4595 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
4596 ;; (use (match_dup 2))])
4597 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
4599 (define_insn "*fixsfsi"
4600 [(set (match_operand:SI 0 "fpul_operand" "=y")
4601 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4602 "TARGET_SH3E && ! TARGET_SH4"
4604 [(set_attr "type" "fp")])
4606 (define_insn "cmpgtsf_t"
4607 [(set (reg:SI T_REG)
4608 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4609 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4610 "TARGET_SH3E && ! TARGET_SH4"
4612 [(set_attr "type" "fp")
4613 (set_attr "fp_mode" "single")])
4615 (define_insn "cmpeqsf_t"
4616 [(set (reg:SI T_REG)
4617 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4618 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4619 "TARGET_SH3E && ! TARGET_SH4"
4621 [(set_attr "type" "fp")
4622 (set_attr "fp_mode" "single")])
4624 (define_insn "ieee_ccmpeqsf_t"
4625 [(set (reg:SI T_REG)
4626 (ior:SI (reg:SI T_REG)
4627 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4628 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
4629 "TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
4630 "* return output_ieee_ccmpeq (insn, operands);"
4631 [(set_attr "length" "4")])
4634 (define_insn "cmpgtsf_t_i4"
4635 [(set (reg:SI T_REG)
4636 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4637 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4638 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4641 [(set_attr "type" "fp")
4642 (set_attr "fp_mode" "single")])
4644 (define_insn "cmpeqsf_t_i4"
4645 [(set (reg:SI T_REG)
4646 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4647 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4648 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4651 [(set_attr "type" "fp")
4652 (set_attr "fp_mode" "single")])
4654 (define_insn "*ieee_ccmpeqsf_t_4"
4655 [(set (reg:SI T_REG)
4656 (ior:SI (reg:SI T_REG)
4657 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4658 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
4659 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4660 "TARGET_IEEE && TARGET_SH4"
4661 "* return output_ieee_ccmpeq (insn, operands);"
4662 [(set_attr "length" "4")
4663 (set_attr "fp_mode" "single")])
4665 (define_expand "cmpsf"
4666 [(set (reg:SI T_REG)
4667 (compare (match_operand:SF 0 "arith_operand" "")
4668 (match_operand:SF 1 "arith_operand" "")))]
4672 sh_compare_op0 = operands[0];
4673 sh_compare_op1 = operands[1];
4677 (define_expand "negsf2"
4678 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4679 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4681 "{ expand_sf_unop (&gen_negsf2_i, operands); DONE; }")
4683 (define_insn "negsf2_i"
4684 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4685 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4686 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4689 [(set_attr "type" "fmove")
4690 (set_attr "fp_mode" "single")])
4692 (define_expand "sqrtsf2"
4693 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4694 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4696 "{ expand_sf_unop (&gen_sqrtsf2_i, operands); DONE; }")
4698 (define_insn "sqrtsf2_i"
4699 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4700 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4701 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4704 [(set_attr "type" "fdiv")
4705 (set_attr "fp_mode" "single")])
4707 (define_expand "abssf2"
4708 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4709 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4711 "{ expand_sf_unop (&gen_abssf2_i, operands); DONE; }")
4713 (define_insn "abssf2_i"
4714 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4715 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4716 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4719 [(set_attr "type" "fmove")
4720 (set_attr "fp_mode" "single")])
4722 (define_expand "adddf3"
4723 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4724 (match_operand:DF 1 "fp_arith_reg_operand" "")
4725 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4727 "{ expand_df_binop (&gen_adddf3_i, operands); DONE; }")
4729 (define_insn "adddf3_i"
4730 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4731 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
4732 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4733 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4736 [(set_attr "type" "dfp_arith")
4737 (set_attr "fp_mode" "double")])
4739 (define_expand "subdf3"
4740 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4741 (match_operand:DF 1 "fp_arith_reg_operand" "")
4742 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4744 "{ expand_df_binop (&gen_subdf3_i, operands); DONE; }")
4746 (define_insn "subdf3_i"
4747 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4748 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
4749 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4750 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4753 [(set_attr "type" "dfp_arith")
4754 (set_attr "fp_mode" "double")])
4756 (define_expand "muldf3"
4757 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4758 (match_operand:DF 1 "fp_arith_reg_operand" "")
4759 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4761 "{ expand_df_binop (&gen_muldf3_i, operands); DONE; }")
4763 (define_insn "muldf3_i"
4764 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4765 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
4766 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4767 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4770 [(set_attr "type" "dfp_arith")
4771 (set_attr "fp_mode" "double")])
4773 (define_expand "divdf3"
4774 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4775 (match_operand:DF 1 "fp_arith_reg_operand" "")
4776 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4778 "{ expand_df_binop (&gen_divdf3_i, operands); DONE; }")
4780 (define_insn "divdf3_i"
4781 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4782 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
4783 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4784 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4787 [(set_attr "type" "dfdiv")
4788 (set_attr "fp_mode" "double")])
4790 (define_expand "floatsidf2"
4791 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4792 (match_operand:SI 1 "fpul_operand" "")]
4796 emit_df_insn (gen_floatsidf2_i (operands[0], operands[1], get_fpscr_rtx ()));
4800 (define_insn "floatsidf2_i"
4801 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4802 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
4803 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4806 [(set_attr "type" "dfp_conv")
4807 (set_attr "fp_mode" "double")])
4809 (define_expand "fix_truncdfsi2"
4810 [(match_operand:SI 0 "fpul_operand" "")
4811 (match_operand:DF 1 "fp_arith_reg_operand" "")]
4815 emit_df_insn (gen_fix_truncdfsi2_i (operands[0], operands[1], get_fpscr_rtx ()));
4819 (define_insn "fix_truncdfsi2_i"
4820 [(set (match_operand:SI 0 "fpul_operand" "=y")
4821 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
4822 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4825 [(set_attr "type" "dfp_conv")
4826 (set_attr "fp_mode" "double")])
4828 ;; ??? This pattern is used nowhere. fix_truncdfsi2 always expands to
4829 ;; fix_truncdfsi2_i.
4830 ;; (define_insn "fix_truncdfsi2_i4"
4831 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4832 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4833 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4834 ;; (clobber (reg:SI FPUL_REG))]
4837 ;; [(set_attr "length" "4")
4838 ;; (set_attr "fp_mode" "double")])
4841 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4842 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4843 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4844 ;; (clobber (reg:SI FPUL_REG))]
4846 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
4847 ;; (use (match_dup 2))])
4848 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
4850 (define_insn "cmpgtdf_t"
4851 [(set (reg:SI T_REG)
4852 (gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
4853 (match_operand:DF 1 "arith_reg_operand" "f")))
4854 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4857 [(set_attr "type" "dfp_cmp")
4858 (set_attr "fp_mode" "double")])
4860 (define_insn "cmpeqdf_t"
4861 [(set (reg:SI T_REG)
4862 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4863 (match_operand:DF 1 "arith_reg_operand" "f")))
4864 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4867 [(set_attr "type" "dfp_cmp")
4868 (set_attr "fp_mode" "double")])
4870 (define_insn "*ieee_ccmpeqdf_t"
4871 [(set (reg:SI T_REG)
4872 (ior:SI (reg:SI T_REG)
4873 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4874 (match_operand:DF 1 "arith_reg_operand" "f"))))
4875 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4876 "TARGET_IEEE && TARGET_SH4"
4877 "* return output_ieee_ccmpeq (insn, operands);"
4878 [(set_attr "length" "4")
4879 (set_attr "fp_mode" "double")])
4881 (define_expand "cmpdf"
4882 [(set (reg:SI T_REG)
4883 (compare (match_operand:DF 0 "arith_operand" "")
4884 (match_operand:DF 1 "arith_operand" "")))]
4888 sh_compare_op0 = operands[0];
4889 sh_compare_op1 = operands[1];
4893 (define_expand "negdf2"
4894 [(match_operand:DF 0 "arith_reg_operand" "")
4895 (match_operand:DF 1 "arith_reg_operand" "")]
4897 "{ expand_df_unop (&gen_negdf2_i, operands); DONE; }")
4899 (define_insn "negdf2_i"
4900 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4901 (neg:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4902 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4905 [(set_attr "type" "fmove")
4906 (set_attr "fp_mode" "double")])
4908 (define_expand "sqrtdf2"
4909 [(match_operand:DF 0 "arith_reg_operand" "")
4910 (match_operand:DF 1 "arith_reg_operand" "")]
4912 "{ expand_df_unop (&gen_sqrtdf2_i, operands); DONE; }")
4914 (define_insn "sqrtdf2_i"
4915 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4916 (sqrt:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4917 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4920 [(set_attr "type" "dfdiv")
4921 (set_attr "fp_mode" "double")])
4923 (define_expand "absdf2"
4924 [(match_operand:DF 0 "arith_reg_operand" "")
4925 (match_operand:DF 1 "arith_reg_operand" "")]
4927 "{ expand_df_unop (&gen_absdf2_i, operands); DONE; }")
4929 (define_insn "absdf2_i"
4930 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4931 (abs:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4932 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4935 [(set_attr "type" "fmove")
4936 (set_attr "fp_mode" "double")])
4938 (define_expand "extendsfdf2"
4939 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4940 (match_operand:SF 1 "fpul_operand" "")]
4944 emit_df_insn (gen_extendsfdf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4948 (define_insn "extendsfdf2_i4"
4949 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4950 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
4951 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4954 [(set_attr "type" "fp")
4955 (set_attr "fp_mode" "double")])
4957 (define_expand "truncdfsf2"
4958 [(match_operand:SF 0 "fpul_operand" "")
4959 (match_operand:DF 1 "fp_arith_reg_operand" "")]
4963 emit_df_insn (gen_truncdfsf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4967 (define_insn "truncdfsf2_i4"
4968 [(set (match_operand:SF 0 "fpul_operand" "=y")
4969 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
4970 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4973 [(set_attr "type" "fp")
4974 (set_attr "fp_mode" "double")])
4976 ;; Bit field extract patterns. These give better code for packed bitfields,
4977 ;; because they allow auto-increment addresses to be generated.
4979 (define_expand "insv"
4980 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
4981 (match_operand:SI 1 "immediate_operand" "")
4982 (match_operand:SI 2 "immediate_operand" ""))
4983 (match_operand:SI 3 "general_operand" ""))]
4984 "! TARGET_LITTLE_ENDIAN"
4987 rtx addr_target, orig_address, shift_reg;
4990 /* ??? expmed doesn't care for non-register predicates. */
4991 if (! memory_operand (operands[0], VOIDmode)
4992 || ! immediate_operand (operands[1], VOIDmode)
4993 || ! immediate_operand (operands[2], VOIDmode)
4994 || ! general_operand (operands[3], VOIDmode))
4996 /* If this isn't a 16 / 24 / 32 bit field, or if
4997 it doesn't start on a byte boundary, then fail. */
4998 size = INTVAL (operands[1]);
4999 if (size < 16 || size > 32 || size % 8 != 0
5000 || (INTVAL (operands[2]) % 8) != 0)
5004 orig_address = XEXP (operands[0], 0);
5005 shift_reg = gen_reg_rtx (SImode);
5006 emit_insn (gen_movsi (shift_reg, operands[3]));
5007 addr_target = copy_addr_to_reg (plus_constant (orig_address, size - 1));
5009 operands[0] = change_address (operands[0], QImode, addr_target);
5010 emit_insn (gen_movqi (operands[0], gen_rtx_SUBREG (QImode, shift_reg, 0)));
5014 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
5015 emit_insn (gen_addsi3 (addr_target, addr_target, GEN_INT (-1)));
5016 emit_insn (gen_movqi (operands[0],
5017 gen_rtx_SUBREG (QImode, shift_reg, 0)));
5023 ;; -------------------------------------------------------------------------
5025 ;; -------------------------------------------------------------------------
5027 ;; This matches cases where a stack pointer increment at the start of the
5028 ;; epilogue combines with a stack slot read loading the return value.
5031 [(set (match_operand:SI 0 "arith_reg_operand" "")
5032 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
5033 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
5034 "REGNO (operands[1]) != REGNO (operands[0])"
5037 ;; See the comment on the dt combiner pattern above.
5040 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
5041 (plus:SI (match_dup 0)
5044 (eq:SI (match_dup 0)
5049 ;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn'
5050 ;; to `mov #k,r0; mov.l @(r0,r15),rn'. These sequences are generated by
5051 ;; reload when the constant is too large for a reg+offset address.
5053 ;; ??? We would get much better code if this was done in reload. This would
5054 ;; require modifying find_reloads_address to recognize that if the constant
5055 ;; is out-of-range for an immediate add, then we get better code by reloading
5056 ;; the constant into a register than by reloading the sum into a register,
5057 ;; since the former is one instruction shorter if the address does not need
5058 ;; to be offsettable. Unfortunately this does not work, because there is
5059 ;; only one register, r0, that can be used as an index register. This register
5060 ;; is also the function return value register. So, if we try to force reload
5061 ;; to use double-reg addresses, then we end up with some instructions that
5062 ;; need to use r0 twice. The only way to fix this is to change the calling
5063 ;; convention so that r0 is not used to return values.
5066 [(set (match_operand:SI 0 "register_operand" "=r")
5067 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5068 (set (mem:SI (match_dup 0))
5069 (match_operand:SI 2 "general_movsrc_operand" ""))]
5070 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5071 "mov.l %2,@(%0,%1)")
5074 [(set (match_operand:SI 0 "register_operand" "=r")
5075 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5076 (set (match_operand:SI 2 "general_movdst_operand" "")
5077 (mem:SI (match_dup 0)))]
5078 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5079 "mov.l @(%0,%1),%2")
5082 [(set (match_operand:SI 0 "register_operand" "=r")
5083 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5084 (set (mem:HI (match_dup 0))
5085 (match_operand:HI 2 "general_movsrc_operand" ""))]
5086 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5087 "mov.w %2,@(%0,%1)")
5090 [(set (match_operand:SI 0 "register_operand" "=r")
5091 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5092 (set (match_operand:HI 2 "general_movdst_operand" "")
5093 (mem:HI (match_dup 0)))]
5094 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5095 "mov.w @(%0,%1),%2")
5098 [(set (match_operand:SI 0 "register_operand" "=r")
5099 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5100 (set (mem:QI (match_dup 0))
5101 (match_operand:QI 2 "general_movsrc_operand" ""))]
5102 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5103 "mov.b %2,@(%0,%1)")
5106 [(set (match_operand:SI 0 "register_operand" "=r")
5107 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5108 (set (match_operand:QI 2 "general_movdst_operand" "")
5109 (mem:QI (match_dup 0)))]
5110 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5111 "mov.b @(%0,%1),%2")
5114 [(set (match_operand:SI 0 "register_operand" "=r")
5115 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5116 (set (mem:SF (match_dup 0))
5117 (match_operand:SF 2 "general_movsrc_operand" ""))]
5118 "REGNO (operands[0]) == 0
5119 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
5120 || (GET_CODE (operands[2]) == SUBREG
5121 && REGNO (SUBREG_REG (operands[2])) < 16))
5122 && reg_unused_after (operands[0], insn)"
5123 "mov.l %2,@(%0,%1)")
5126 [(set (match_operand:SI 0 "register_operand" "=r")
5127 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5128 (set (match_operand:SF 2 "general_movdst_operand" "")
5130 (mem:SF (match_dup 0)))]
5131 "REGNO (operands[0]) == 0
5132 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
5133 || (GET_CODE (operands[2]) == SUBREG
5134 && REGNO (SUBREG_REG (operands[2])) < 16))
5135 && reg_unused_after (operands[0], insn)"
5136 "mov.l @(%0,%1),%2")
5139 [(set (match_operand:SI 0 "register_operand" "=r")
5140 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5141 (set (mem:SF (match_dup 0))
5142 (match_operand:SF 2 "general_movsrc_operand" ""))]
5143 "REGNO (operands[0]) == 0
5144 && ((GET_CODE (operands[2]) == REG
5145 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
5146 || (GET_CODE (operands[2]) == SUBREG
5147 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
5148 && reg_unused_after (operands[0], insn)"
5149 "fmov{.s|} %2,@(%0,%1)")
5152 [(set (match_operand:SI 0 "register_operand" "=r")
5153 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5154 (set (match_operand:SF 2 "general_movdst_operand" "")
5156 (mem:SF (match_dup 0)))]
5157 "REGNO (operands[0]) == 0
5158 && ((GET_CODE (operands[2]) == REG
5159 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
5160 || (GET_CODE (operands[2]) == SUBREG
5161 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
5162 && reg_unused_after (operands[0], insn)"
5163 "fmov{.s|} @(%0,%1),%2")
5165 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF). */
5166 (define_insn "sp_switch_1"
5173 xoperands[0] = sp_switch;
5174 output_asm_insn (\"mov.l r0,@-r15\;mov.l %0,r0\", xoperands);
5175 output_asm_insn (\"mov.l @r0,r0\;mov.l r15,@-r0\", xoperands);
5176 return \"mov r0,r15\";
5178 [(set_attr "length" "10")])
5180 ;; Switch back to the original stack for interrupt functions with the
5181 ;; sp_switch attribute. */
5182 (define_insn "sp_switch_2"
5185 "mov.l @r15+,r15\;mov.l @r15+,r0"
5186 [(set_attr "length" "4")])