1 ;;- Machine description for the Hitachi SH.
2 ;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
5 ;; Improved by Jim Wilson (wilson@cygnus.com).
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
25 ;; ??? Should prepend a * to all pattern names which are not used.
26 ;; This will make the compiler smaller, and rebuilds after changes faster.
28 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
29 ;; sequences. Especially the sequences for arithmetic right shifts.
31 ;; ??? Should check all DImode patterns for consistency and usefulness.
33 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
34 ;; way to generate them.
36 ;; ??? The cmp/str instruction is not supported. Perhaps it can be used
37 ;; for a str* inline function.
39 ;; BSR is not generated by the compiler proper, but when relaxing, it
40 ;; generates .uses pseudo-ops that allow linker relaxation to create
41 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
43 ;; Special constraints for SH machine description:
50 ;; Special formats used for outputting SH instructions:
52 ;; %. -- print a .s if insn needs delay slot
53 ;; %@ -- print rte/rts if is/isn't an interrupt function
54 ;; %# -- output a nop if there is nothing to put in the delay slot
55 ;; %O -- print a constant without the #
56 ;; %R -- print the lsw reg of a double
57 ;; %S -- print the msw reg of a double
58 ;; %T -- print next word of a double REG or MEM
60 ;; Special predicates:
62 ;; arith_operand -- operand is valid source for arithmetic op
63 ;; arith_reg_operand -- operand is valid register for arithmetic op
64 ;; general_movdst_operand -- operand is valid move destination
65 ;; general_movsrc_operand -- operand is valid move source
66 ;; logical_operand -- operand is valid source for logical op
68 ;; -------------------------------------------------------------------------
70 ;; -------------------------------------------------------------------------
102 ;; These are used with unspec.
114 ;; These are used with unspec_volatile.
120 (UNSPECV_CONST_END 11)
123 ;; -------------------------------------------------------------------------
125 ;; -------------------------------------------------------------------------
130 "sh1,sh2,sh3,sh3e,sh4"
131 (const (symbol_ref "sh_cpu_attr")))
133 (define_attr "endian" "big,little"
134 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
135 (const_string "little") (const_string "big"))))
137 ;; Indicate if the default fpu mode is single precision.
138 (define_attr "fpu_single" "yes,no"
139 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
140 (const_string "yes") (const_string "no"))))
142 (define_attr "fmovd" "yes,no"
143 (const (if_then_else (symbol_ref "TARGET_FMOVD")
144 (const_string "yes") (const_string "no"))))
146 (define_attr "issues" "1,2"
147 (const (if_then_else (symbol_ref "TARGET_SUPERSCALAR") (const_string "2") (const_string "1"))))
149 ;; cbranch conditional branch instructions
150 ;; jump unconditional jumps
151 ;; arith ordinary arithmetic
152 ;; arith3 a compound insn that behaves similarly to a sequence of
153 ;; three insns of type arith
154 ;; arith3b like above, but might end with a redirected branch
156 ;; load_si Likewise, SImode variant for general register.
158 ;; move register to register
159 ;; fmove register to register, floating point
160 ;; smpy word precision integer multiply
161 ;; dmpy longword or doublelongword precision integer multiply
163 ;; pload load of pr reg, which can't be put into delay slot of rts
164 ;; prset copy register to pr reg, ditto
165 ;; pstore store of pr reg, which can't be put into delay slot of jsr
166 ;; prget copy pr to register, ditto
167 ;; pcload pc relative load of constant value
168 ;; pcload_si Likewise, SImode variant for general register.
169 ;; rte return from exception
170 ;; sfunc special function call with known used registers
171 ;; call function call
173 ;; fdiv floating point divide (or square root)
174 ;; gp_fpul move between general purpose register and fpul
175 ;; dfp_arith, dfp_cmp,dfp_conv
176 ;; dfdiv double precision floating point divide (or square root)
177 ;; nil no-op move, will be deleted.
180 "cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,other,load,load_si,store,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,rte,sfunc,call,fp,fdiv,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,nil"
181 (const_string "other"))
183 ;; Indicate what precision must be selected in fpscr for this insn, if any.
185 (define_attr "fp_mode" "single,double,none" (const_string "none"))
187 ; If a conditional branch destination is within -252..258 bytes away
188 ; from the instruction it can be 2 bytes long. Something in the
189 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
190 ; branches are initially assumed to be 16 bytes long.
191 ; In machine_dependent_reorg, we split all branches that are longer than
194 ;; The maximum range used for SImode constant pool entrys is 1018. A final
195 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
196 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
197 ;; instruction around the pool table, 2 bytes of alignment before the table,
198 ;; and 30 bytes of alignment after the table. That gives a maximum total
199 ;; pool size of 1058 bytes.
200 ;; Worst case code/pool content size ratio is 1:2 (using asms).
201 ;; Thus, in the worst case, there is one instruction in front of a maximum
202 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
203 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
204 ;; If we have a forward branch, the initial table will be put after the
205 ;; unconditional branch.
207 ;; ??? We could do much better by keeping track of the actual pcloads within
208 ;; the branch range and in the pcload range in front of the branch range.
210 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
212 (define_attr "short_cbranch_p" "no,yes"
213 (cond [(ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
215 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
217 (ne (symbol_ref "NEXT_INSN (PREV_INSN (insn)) != insn") (const_int 0))
219 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
221 ] (const_string "no")))
223 (define_attr "med_branch_p" "no,yes"
224 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
227 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
229 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
232 ] (const_string "no")))
234 (define_attr "med_cbranch_p" "no,yes"
235 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
238 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
240 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
243 ] (const_string "no")))
245 (define_attr "braf_branch_p" "no,yes"
246 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
248 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
251 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
253 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
256 ] (const_string "no")))
258 (define_attr "braf_cbranch_p" "no,yes"
259 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
261 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
264 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
266 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
269 ] (const_string "no")))
271 ; An unconditional jump in the range -4092..4098 can be 2 bytes long.
272 ; For wider ranges, we need a combination of a code and a data part.
273 ; If we can get a scratch register for a long range jump, the code
274 ; part can be 4 bytes long; otherwise, it must be 8 bytes long.
275 ; If the jump is in the range -32764..32770, the data part can be 2 bytes
276 ; long; otherwise, it must be 6 bytes long.
278 ; All other instructions are two bytes long by default.
280 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
281 ;; but getattrtab doesn't understand this.
282 (define_attr "length" ""
283 (cond [(eq_attr "type" "cbranch")
284 (cond [(eq_attr "short_cbranch_p" "yes")
286 (eq_attr "med_cbranch_p" "yes")
288 (eq_attr "braf_cbranch_p" "yes")
290 ;; ??? using pc is not computed transitively.
291 (ne (match_dup 0) (match_dup 0))
294 (eq_attr "type" "jump")
295 (cond [(eq_attr "med_branch_p" "yes")
297 (and (eq (symbol_ref "GET_CODE (PREV_INSN (insn))")
299 (eq (symbol_ref "INSN_CODE (PREV_INSN (insn))")
300 (symbol_ref "code_for_indirect_jump_scratch")))
301 (if_then_else (eq_attr "braf_branch_p" "yes")
304 (eq_attr "braf_branch_p" "yes")
306 ;; ??? using pc is not computed transitively.
307 (ne (match_dup 0) (match_dup 0))
312 ;; (define_function_unit {name} {num-units} {n-users} {test}
313 ;; {ready-delay} {issue-delay} [{conflict-list}])
315 ;; Load and store instructions save a cycle if they are aligned on a
316 ;; four byte boundary. Using a function unit for stores encourages
317 ;; gcc to separate load and store instructions by one instruction,
318 ;; which makes it more likely that the linker will be able to word
319 ;; align them when relaxing.
321 ;; Loads have a latency of two.
322 ;; However, call insns can have a delay slot, so that we want one more
323 ;; insn to be scheduled between the load of the function address and the call.
324 ;; This is equivalent to a latency of three.
325 ;; We cannot use a conflict list for this, because we need to distinguish
326 ;; between the actual call address and the function arguments.
327 ;; ADJUST_COST can only properly handle reductions of the cost, so we
328 ;; use a latency of three here.
329 ;; We only do this for SImode loads of general registers, to make the work
330 ;; for ADJUST_COST easier.
331 (define_function_unit "memory" 1 0
332 (and (eq_attr "issues" "1")
333 (eq_attr "type" "load_si,pcload_si"))
335 (define_function_unit "memory" 1 0
336 (and (eq_attr "issues" "1")
337 (eq_attr "type" "load,pcload,pload,store,pstore"))
340 (define_function_unit "int" 1 0
341 (and (eq_attr "issues" "1") (eq_attr "type" "arith3,arith3b")) 3 3)
343 (define_function_unit "int" 1 0
344 (and (eq_attr "issues" "1") (eq_attr "type" "dyn_shift")) 2 2)
346 (define_function_unit "int" 1 0
347 (and (eq_attr "issues" "1") (eq_attr "type" "!arith3,arith3b,dyn_shift")) 1 1)
349 ;; ??? These are approximations.
350 (define_function_unit "mpy" 1 0
351 (and (eq_attr "issues" "1") (eq_attr "type" "smpy")) 2 2)
352 (define_function_unit "mpy" 1 0
353 (and (eq_attr "issues" "1") (eq_attr "type" "dmpy")) 3 3)
355 (define_function_unit "fp" 1 0
356 (and (eq_attr "issues" "1") (eq_attr "type" "fp,fmove")) 2 1)
357 (define_function_unit "fp" 1 0
358 (and (eq_attr "issues" "1") (eq_attr "type" "fdiv")) 13 12)
362 ;; The SH4 is a dual-issue implementation, thus we have to multiply all
363 ;; costs by at least two.
364 ;; There will be single increments of the modeled that don't correspond
365 ;; to the actual target ;; whenever two insns to be issued depend one a
366 ;; single resource, and the scheduler picks to be the first one.
367 ;; If we multiplied the costs just by two, just two of these single
368 ;; increments would amount to an actual cycle. By picking a larger
369 ;; factor, we can ameliorate the effect; However, we then have to make sure
370 ;; that only two insns are modeled as issued per actual cycle.
371 ;; Moreover, we need a way to specify the latency of insns that don't
372 ;; use an actual function unit.
373 ;; We use an 'issue' function unit to do that, and a cost factor of 10.
375 (define_function_unit "issue" 2 0
376 (and (eq_attr "issues" "2") (eq_attr "type" "!nil,arith3"))
379 (define_function_unit "issue" 2 0
380 (and (eq_attr "issues" "2") (eq_attr "type" "arith3"))
383 ;; There is no point in providing exact scheduling information about branches,
384 ;; because they are at the starts / ends of basic blocks anyways.
386 ;; Some insns cannot be issued before/after another insn in the same cycle,
387 ;; irrespective of the type of the other insn.
389 ;; default is dual-issue, but can't be paired with an insn that
390 ;; uses multiple function units.
391 (define_function_unit "single_issue" 1 0
392 (and (eq_attr "issues" "2")
393 (eq_attr "type" "!smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul,call,sfunc,arith3,arith3b"))
395 [(eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul")])
397 (define_function_unit "single_issue" 1 0
398 (and (eq_attr "issues" "2")
399 (eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul"))
403 ;; arith3 insns are always pairable at the start, but not inecessarily at
404 ;; the end; however, there doesn;t seem to be a way to express that.
405 (define_function_unit "single_issue" 1 0
406 (and (eq_attr "issues" "2")
407 (eq_attr "type" "arith3"))
411 ;; arith3b insn are pairable at the end and have latency that prevents pairing
412 ;; with the following branch, but we don't want this latency be respected;
413 ;; When the following branch is immediately adjacent, we can redirect the
414 ;; internal branch, which is likly to be a larger win.
415 (define_function_unit "single_issue" 1 0
416 (and (eq_attr "issues" "2")
417 (eq_attr "type" "arith3b"))
421 ;; calls introduce a longisch delay that is likely to flush the pipelines.
422 (define_function_unit "single_issue" 1 0
423 (and (eq_attr "issues" "2")
424 (eq_attr "type" "call,sfunc"))
426 [(eq_attr "type" "!call") (eq_attr "type" "call")])
428 ;; Load and store instructions have no alignment peculiarities for the SH4,
429 ;; but they use the load-store unit, which they share with the fmove type
430 ;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
431 ;; Loads have a latency of two.
432 ;; However, call insns can only paired with a preceding insn, and have
433 ;; a delay slot, so that we want two more insns to be scheduled between the
434 ;; load of the function address and the call. This is equivalent to a
436 ;; We cannot use a conflict list for this, because we need to distinguish
437 ;; between the actual call address and the function arguments.
438 ;; ADJUST_COST can only properly handle reductions of the cost, so we
439 ;; use a latency of three here, which gets multiplied by 10 to yield 30.
440 ;; We only do this for SImode loads of general registers, to make the work
441 ;; for ADJUST_COST easier.
443 ;; When specifying different latencies for different insns using the
444 ;; the same function unit, genattrtab.c assumes a 'FIFO constraint'
445 ;; so that the blockage is at least READY-COST (E) + 1 - READY-COST (C)
446 ;; for an executing insn E and a candidate insn C.
447 ;; Therefore, we define three different function units for load_store:
448 ;; load_store, load and load_si.
450 (define_function_unit "load_si" 1 0
451 (and (eq_attr "issues" "2")
452 (eq_attr "type" "load_si,pcload_si")) 30 10)
453 (define_function_unit "load" 1 0
454 (and (eq_attr "issues" "2")
455 (eq_attr "type" "load,pcload,pload")) 20 10)
456 (define_function_unit "load_store" 1 0
457 (and (eq_attr "issues" "2")
458 (eq_attr "type" "load_si,pcload_si,load,pcload,pload,store,pstore,fmove"))
461 (define_function_unit "int" 1 0
462 (and (eq_attr "issues" "2") (eq_attr "type" "arith,dyn_shift")) 10 10)
464 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
465 ;; spurious FIFO constraint; the multiply instructions use the "int"
466 ;; unit actually only for two cycles.
467 (define_function_unit "int" 1 0
468 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 20 20)
470 ;; We use a fictous "mpy" unit to express the actual latency.
471 (define_function_unit "mpy" 1 0
472 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 20)
474 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
475 ;; spurious FIFO constraint.
476 (define_function_unit "int" 1 0
477 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 10 10)
479 ;; We use a fictous "gp_fpul" unit to express the actual latency.
480 (define_function_unit "gp_fpul" 1 0
481 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 20 10)
483 ;; ??? multiply uses the floating point unit, but with a two cycle delay.
484 ;; Thus, a simple single-precision fp operation could finish if issued in
485 ;; the very next cycle, but stalls when issued two or three cycles later.
486 ;; Similarily, a divide / sqrt can work without stalls if issued in
487 ;; the very next cycle, while it would have to block if issued two or
488 ;; three cycles later.
489 ;; There is no way to model this with gcc's function units. This problem is
490 ;; actually mentioned in md.texi. Tackling this problem requires first that
491 ;; it is possible to speak about the target in an open discussion.
493 ;; However, simple double-precision operations always conflict.
495 (define_function_unit "fp" 1 0
496 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 40
497 [(eq_attr "type" "dfp_cmp,dfp_conv,dfp_arith")])
499 ;; The "fp" unit is for pipeline stages F1 and F2.
501 (define_function_unit "fp" 1 0
502 (and (eq_attr "issues" "2") (eq_attr "type" "fp")) 30 10)
504 ;; Again, we have to pretend a lower latency for the "fp" unit to avoid a
505 ;; spurious FIFO constraint; the bulk of the fdiv type insns executes in
507 (define_function_unit "fp" 1 0
508 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 30 10)
510 ;; The "fdiv" function unit models the aggregate effect of the F1, F2 and F3
511 ;; pipeline stages on the pipelining of fdiv/fsqrt insns.
512 ;; We also use it to give the actual latency here.
513 ;; fsqrt is actually one cycle faster than fdiv (and the value used here),
514 ;; but that will hardly matter in practice for scheduling.
515 (define_function_unit "fdiv" 1 0
516 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 120 100)
518 ;; There is again a late use of the "fp" unit by [d]fdiv type insns
519 ;; that we can't express.
521 (define_function_unit "fp" 1 0
522 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_cmp,dfp_conv")) 40 20)
524 (define_function_unit "fp" 1 0
525 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_arith")) 80 60)
527 (define_function_unit "fp" 1 0
528 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 10)
530 (define_function_unit "fdiv" 1 0
531 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 210)
533 ; Definitions for filling branch delay slots.
535 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
537 ;; ??? This should be (nil) instead of (const_int 0)
538 (define_attr "hit_stack" "yes,no"
539 (cond [(eq (symbol_ref "find_regno_note (insn, REG_INC, SP_REG)")
542 (const_string "yes")))
544 (define_attr "interrupt_function" "no,yes"
545 (const (symbol_ref "pragma_interrupt")))
547 (define_attr "in_delay_slot" "yes,no"
548 (cond [(eq_attr "type" "cbranch") (const_string "no")
549 (eq_attr "type" "pcload,pcload_si") (const_string "no")
550 (eq_attr "needs_delay_slot" "yes") (const_string "no")
551 (eq_attr "length" "2") (const_string "yes")
552 ] (const_string "no")))
554 (define_attr "is_sfunc" ""
555 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
558 (eq_attr "needs_delay_slot" "yes")
559 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
561 ;; On the SH and SH2, the rte instruction reads the return pc from the stack,
562 ;; and thus we can't put a pop instruction in its delay slot.
563 ;; ??? On the SH3, the rte instruction does not use the stack, so a pop
564 ;; instruction can go in the delay slot.
566 ;; Since a normal return (rts) implicitly uses the PR register,
567 ;; we can't allow PR register loads in an rts delay slot.
570 (eq_attr "type" "return")
571 [(and (eq_attr "in_delay_slot" "yes")
572 (ior (and (eq_attr "interrupt_function" "no")
573 (eq_attr "type" "!pload,prset"))
574 (and (eq_attr "interrupt_function" "yes")
575 (eq_attr "hit_stack" "no")))) (nil) (nil)])
577 ;; Since a call implicitly uses the PR register, we can't allow
578 ;; a PR register store in a jsr delay slot.
581 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
582 [(and (eq_attr "in_delay_slot" "yes")
583 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
585 ;; Say that we have annulled true branches, since this gives smaller and
586 ;; faster code when branches are predicted as not taken.
589 (and (eq_attr "type" "cbranch")
590 (ne (symbol_ref "TARGET_SH2") (const_int 0)))
591 [(eq_attr "in_delay_slot" "yes") (eq_attr "in_delay_slot" "yes") (nil)])
593 ;; -------------------------------------------------------------------------
594 ;; SImode signed integer comparisons
595 ;; -------------------------------------------------------------------------
599 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
600 (match_operand:SI 1 "arith_operand" "L,r"))
605 ;; ??? Perhaps should only accept reg/constant if the register is reg 0.
606 ;; That would still allow reload to create cmpi instructions, but would
607 ;; perhaps allow forcing the constant into a register when that is better.
608 ;; Probably should use r0 for mem/imm compares, but force constant into a
609 ;; register for pseudo/imm compares.
611 (define_insn "cmpeqsi_t"
613 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
614 (match_operand:SI 1 "arith_operand" "N,rI,r")))]
621 (define_insn "cmpgtsi_t"
623 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
624 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
630 (define_insn "cmpgesi_t"
632 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
633 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
639 ;; -------------------------------------------------------------------------
640 ;; SImode unsigned integer comparisons
641 ;; -------------------------------------------------------------------------
643 (define_insn "cmpgeusi_t"
645 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
646 (match_operand:SI 1 "arith_reg_operand" "r")))]
650 (define_insn "cmpgtusi_t"
652 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
653 (match_operand:SI 1 "arith_reg_operand" "r")))]
657 ;; We save the compare operands in the cmpxx patterns and use them when
658 ;; we generate the branch.
660 (define_expand "cmpsi"
662 (compare (match_operand:SI 0 "arith_operand" "")
663 (match_operand:SI 1 "arith_operand" "")))]
667 sh_compare_op0 = operands[0];
668 sh_compare_op1 = operands[1];
672 ;; -------------------------------------------------------------------------
673 ;; DImode signed integer comparisons
674 ;; -------------------------------------------------------------------------
676 ;; ??? Could get better scheduling by splitting the initial test from the
677 ;; rest of the insn after reload. However, the gain would hardly justify
678 ;; the sh.md size increase necessary to do that.
682 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
683 (match_operand:DI 1 "arith_operand" "r"))
686 "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
688 [(set_attr "length" "6")
689 (set_attr "type" "arith3b")])
691 (define_insn "cmpeqdi_t"
693 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
694 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
697 tst %S0,%S0\;bf %,Ldi%=\;tst %R0,%R0\\n%,Ldi%=:
698 cmp/eq %S1,%S0\;bf %,Ldi%=\;cmp/eq %R1,%R0\\n%,Ldi%=:"
699 [(set_attr "length" "6")
700 (set_attr "type" "arith3b")])
704 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
705 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
706 ;; If we applied this split when not optimizing, it would only be
707 ;; applied during the machine-dependent reorg, when no new basic blocks
709 "reload_completed && optimize"
710 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
711 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
712 (label_ref (match_dup 6))
714 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
719 = gen_rtx_REG (SImode,
720 true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
722 = (operands[1] == const0_rtx
724 : gen_rtx_REG (SImode,
725 true_regnum (operands[1])
726 + (TARGET_LITTLE_ENDIAN ? 1 : 0)));
727 operands[4] = gen_lowpart (SImode, operands[0]);
728 operands[5] = gen_lowpart (SImode, operands[1]);
729 operands[6] = gen_label_rtx ();
732 (define_insn "cmpgtdi_t"
734 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
735 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
738 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
739 tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
740 [(set_attr "length" "8")
741 (set_attr "type" "arith3")])
743 (define_insn "cmpgedi_t"
745 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
746 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
749 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
751 [(set_attr "length" "8,2")
752 (set_attr "type" "arith3,arith")])
754 ;; -------------------------------------------------------------------------
755 ;; DImode unsigned integer comparisons
756 ;; -------------------------------------------------------------------------
758 (define_insn "cmpgeudi_t"
760 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
761 (match_operand:DI 1 "arith_reg_operand" "r")))]
763 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
764 [(set_attr "length" "8")
765 (set_attr "type" "arith3")])
767 (define_insn "cmpgtudi_t"
769 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
770 (match_operand:DI 1 "arith_reg_operand" "r")))]
772 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
773 [(set_attr "length" "8")
774 (set_attr "type" "arith3")])
776 ;; We save the compare operands in the cmpxx patterns and use them when
777 ;; we generate the branch.
779 (define_expand "cmpdi"
781 (compare (match_operand:DI 0 "arith_operand" "")
782 (match_operand:DI 1 "arith_operand" "")))]
786 sh_compare_op0 = operands[0];
787 sh_compare_op1 = operands[1];
791 ;; -------------------------------------------------------------------------
792 ;; Addition instructions
793 ;; -------------------------------------------------------------------------
795 ;; ??? This should be a define expand.
797 (define_insn "adddi3"
798 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
799 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
800 (match_operand:DI 2 "arith_reg_operand" "r")))
801 (clobber (reg:SI T_REG))]
804 [(set_attr "length" "6")])
807 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
808 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
809 (match_operand:DI 2 "arith_reg_operand" "r")))
810 (clobber (reg:SI T_REG))]
815 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
816 high0 = gen_rtx_REG (SImode,
817 true_regnum (operands[0])
818 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
819 high2 = gen_rtx_REG (SImode,
820 true_regnum (operands[2])
821 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
822 emit_insn (gen_clrt ());
823 emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
824 emit_insn (gen_addc1 (high0, high0, high2));
829 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
830 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
831 (match_operand:SI 2 "arith_reg_operand" "r"))
834 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
837 [(set_attr "type" "arith")])
840 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
841 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
842 (match_operand:SI 2 "arith_reg_operand" "r"))
844 (clobber (reg:SI T_REG))]
847 [(set_attr "type" "arith")])
849 (define_insn "addsi3"
850 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
851 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
852 (match_operand:SI 2 "arith_operand" "rI")))]
855 [(set_attr "type" "arith")])
857 ;; -------------------------------------------------------------------------
858 ;; Subtraction instructions
859 ;; -------------------------------------------------------------------------
861 ;; ??? This should be a define expand.
863 (define_insn "subdi3"
864 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
865 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
866 (match_operand:DI 2 "arith_reg_operand" "r")))
867 (clobber (reg:SI T_REG))]
870 [(set_attr "length" "6")])
873 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
874 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
875 (match_operand:DI 2 "arith_reg_operand" "r")))
876 (clobber (reg:SI T_REG))]
881 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
882 high0 = gen_rtx_REG (SImode,
883 true_regnum (operands[0])
884 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
885 high2 = gen_rtx_REG (SImode,
886 true_regnum (operands[2])
887 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
888 emit_insn (gen_clrt ());
889 emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
890 emit_insn (gen_subc1 (high0, high0, high2));
895 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
896 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
897 (match_operand:SI 2 "arith_reg_operand" "r"))
900 (gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
903 [(set_attr "type" "arith")])
906 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
907 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
908 (match_operand:SI 2 "arith_reg_operand" "r"))
910 (clobber (reg:SI T_REG))]
913 [(set_attr "type" "arith")])
915 (define_insn "*subsi3_internal"
916 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
917 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
918 (match_operand:SI 2 "arith_reg_operand" "r")))]
921 [(set_attr "type" "arith")])
923 ;; Convert `constant - reg' to `neg rX; add rX, #const' since this
924 ;; will sometimes save one instruction. Otherwise we might get
925 ;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
928 (define_expand "subsi3"
929 [(set (match_operand:SI 0 "arith_reg_operand" "")
930 (minus:SI (match_operand:SI 1 "arith_operand" "")
931 (match_operand:SI 2 "arith_reg_operand" "")))]
935 if (GET_CODE (operands[1]) == CONST_INT)
937 emit_insn (gen_negsi2 (operands[0], operands[2]));
938 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
943 ;; -------------------------------------------------------------------------
944 ;; Division instructions
945 ;; -------------------------------------------------------------------------
947 ;; We take advantage of the library routines which don't clobber as many
948 ;; registers as a normal function call would.
950 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
951 ;; also has an effect on the register that holds the address of the sfunc.
952 ;; To make this work, we have an extra dummy insns that shows the use
953 ;; of this register for reorg.
955 (define_insn "use_sfunc_addr"
956 [(set (reg:SI PR_REG)
957 (unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
960 [(set_attr "length" "0")])
962 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
963 ;; hard register 0. If we used hard register 0, then the next instruction
964 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
965 ;; gets allocated to a stack slot that needs its address reloaded, then
966 ;; there is nothing to prevent reload from using r0 to reload the address.
967 ;; This reload would clobber the value in r0 we are trying to store.
968 ;; If we let reload allocate r0, then this problem can never happen.
970 (define_insn "udivsi3_i1"
971 [(set (match_operand:SI 0 "register_operand" "=z")
972 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
973 (clobber (reg:SI T_REG))
974 (clobber (reg:SI PR_REG))
975 (clobber (reg:SI R4_REG))
976 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
979 [(set_attr "type" "sfunc")
980 (set_attr "needs_delay_slot" "yes")])
982 (define_insn "udivsi3_i4"
983 [(set (match_operand:SI 0 "register_operand" "=y")
984 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
985 (clobber (reg:SI T_REG))
986 (clobber (reg:SI PR_REG))
987 (clobber (reg:DF DR0_REG))
988 (clobber (reg:DF DR2_REG))
989 (clobber (reg:DF DR4_REG))
990 (clobber (reg:SI R0_REG))
991 (clobber (reg:SI R1_REG))
992 (clobber (reg:SI R4_REG))
993 (clobber (reg:SI R5_REG))
994 (use (reg:PSI FPSCR_REG))
995 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
996 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
998 [(set_attr "type" "sfunc")
999 (set_attr "fp_mode" "double")
1000 (set_attr "needs_delay_slot" "yes")])
1002 (define_insn "udivsi3_i4_single"
1003 [(set (match_operand:SI 0 "register_operand" "=y")
1004 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1005 (clobber (reg:SI T_REG))
1006 (clobber (reg:SI PR_REG))
1007 (clobber (reg:DF DR0_REG))
1008 (clobber (reg:DF DR2_REG))
1009 (clobber (reg:DF DR4_REG))
1010 (clobber (reg:SI R0_REG))
1011 (clobber (reg:SI R1_REG))
1012 (clobber (reg:SI R4_REG))
1013 (clobber (reg:SI R5_REG))
1014 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1015 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
1017 [(set_attr "type" "sfunc")
1018 (set_attr "needs_delay_slot" "yes")])
1020 (define_expand "udivsi3"
1021 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
1022 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1023 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1024 (parallel [(set (match_operand:SI 0 "register_operand" "")
1025 (udiv:SI (reg:SI R4_REG)
1027 (clobber (reg:SI T_REG))
1028 (clobber (reg:SI PR_REG))
1029 (clobber (reg:SI R4_REG))
1030 (use (match_dup 3))])]
1036 operands[3] = gen_reg_rtx(SImode);
1037 /* Emit the move of the address to a pseudo outside of the libcall. */
1038 if (TARGET_HARD_SH4 && TARGET_SH3E)
1040 emit_move_insn (operands[3],
1041 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
1042 if (TARGET_FPU_SINGLE)
1043 last = gen_udivsi3_i4_single (operands[0], operands[3]);
1045 last = gen_udivsi3_i4 (operands[0], operands[3]);
1049 emit_move_insn (operands[3],
1050 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3\"));
1051 last = gen_udivsi3_i1 (operands[0], operands[3]);
1053 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1054 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1055 last = emit_insn (last);
1056 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1057 invariant code motion can move it. */
1058 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1059 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1063 (define_insn "divsi3_i1"
1064 [(set (match_operand:SI 0 "register_operand" "=z")
1065 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1066 (clobber (reg:SI T_REG))
1067 (clobber (reg:SI PR_REG))
1068 (clobber (reg:SI R1_REG))
1069 (clobber (reg:SI R2_REG))
1070 (clobber (reg:SI R3_REG))
1071 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1074 [(set_attr "type" "sfunc")
1075 (set_attr "needs_delay_slot" "yes")])
1077 (define_insn "divsi3_i4"
1078 [(set (match_operand:SI 0 "register_operand" "=y")
1079 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1080 (clobber (reg:SI PR_REG))
1081 (clobber (reg:DF DR0_REG))
1082 (clobber (reg:DF DR2_REG))
1083 (use (reg:PSI FPSCR_REG))
1084 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1085 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1087 [(set_attr "type" "sfunc")
1088 (set_attr "fp_mode" "double")
1089 (set_attr "needs_delay_slot" "yes")])
1091 (define_insn "divsi3_i4_single"
1092 [(set (match_operand:SI 0 "register_operand" "=y")
1093 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1094 (clobber (reg:SI PR_REG))
1095 (clobber (reg:DF DR0_REG))
1096 (clobber (reg:DF DR2_REG))
1097 (clobber (reg:SI R2_REG))
1098 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1099 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
1101 [(set_attr "type" "sfunc")
1102 (set_attr "needs_delay_slot" "yes")])
1104 (define_expand "divsi3"
1105 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
1106 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1107 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1108 (parallel [(set (match_operand:SI 0 "register_operand" "")
1109 (div:SI (reg:SI R4_REG)
1111 (clobber (reg:SI T_REG))
1112 (clobber (reg:SI PR_REG))
1113 (clobber (reg:SI R1_REG))
1114 (clobber (reg:SI R2_REG))
1115 (clobber (reg:SI R3_REG))
1116 (use (match_dup 3))])]
1122 operands[3] = gen_reg_rtx(SImode);
1123 /* Emit the move of the address to a pseudo outside of the libcall. */
1124 if (TARGET_HARD_SH4 && TARGET_SH3E)
1126 emit_move_insn (operands[3],
1127 gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
1128 if (TARGET_FPU_SINGLE)
1129 last = gen_divsi3_i4_single (operands[0], operands[3]);
1131 last = gen_divsi3_i4 (operands[0], operands[3]);
1135 emit_move_insn (operands[3], gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3\"));
1136 last = gen_divsi3_i1 (operands[0], operands[3]);
1138 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1139 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1140 last = emit_insn (last);
1141 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1142 invariant code motion can move it. */
1143 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1144 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1148 ;; -------------------------------------------------------------------------
1149 ;; Multiplication instructions
1150 ;; -------------------------------------------------------------------------
1152 (define_insn "umulhisi3_i"
1153 [(set (reg:SI MACL_REG)
1154 (mult:SI (zero_extend:SI
1155 (match_operand:HI 0 "arith_reg_operand" "r"))
1157 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1160 [(set_attr "type" "smpy")])
1162 (define_insn "mulhisi3_i"
1163 [(set (reg:SI MACL_REG)
1164 (mult:SI (sign_extend:SI
1165 (match_operand:HI 0 "arith_reg_operand" "r"))
1167 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1170 [(set_attr "type" "smpy")])
1172 (define_expand "mulhisi3"
1173 [(set (reg:SI MACL_REG)
1174 (mult:SI (sign_extend:SI
1175 (match_operand:HI 1 "arith_reg_operand" ""))
1177 (match_operand:HI 2 "arith_reg_operand" ""))))
1178 (set (match_operand:SI 0 "arith_reg_operand" "")
1185 first = emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
1186 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
1187 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1188 invariant code motion can move it. */
1189 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1190 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1194 (define_expand "umulhisi3"
1195 [(set (reg:SI MACL_REG)
1196 (mult:SI (zero_extend:SI
1197 (match_operand:HI 1 "arith_reg_operand" ""))
1199 (match_operand:HI 2 "arith_reg_operand" ""))))
1200 (set (match_operand:SI 0 "arith_reg_operand" "")
1207 first = emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
1208 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
1209 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1210 invariant code motion can move it. */
1211 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1212 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1216 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
1217 ;; a call to a routine which clobbers known registers.
1220 [(set (match_operand:SI 1 "register_operand" "=z")
1221 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1222 (clobber (reg:SI MACL_REG))
1223 (clobber (reg:SI T_REG))
1224 (clobber (reg:SI PR_REG))
1225 (clobber (reg:SI R3_REG))
1226 (clobber (reg:SI R2_REG))
1227 (clobber (reg:SI R1_REG))
1228 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
1231 [(set_attr "type" "sfunc")
1232 (set_attr "needs_delay_slot" "yes")])
1234 (define_expand "mulsi3_call"
1235 [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1236 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1237 (parallel[(set (match_operand:SI 0 "register_operand" "")
1238 (mult:SI (reg:SI R4_REG)
1240 (clobber (reg:SI MACL_REG))
1241 (clobber (reg:SI T_REG))
1242 (clobber (reg:SI PR_REG))
1243 (clobber (reg:SI R3_REG))
1244 (clobber (reg:SI R2_REG))
1245 (clobber (reg:SI R1_REG))
1246 (use (match_operand:SI 3 "register_operand" ""))])]
1250 (define_insn "mul_l"
1251 [(set (reg:SI MACL_REG)
1252 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
1253 (match_operand:SI 1 "arith_reg_operand" "r")))]
1256 [(set_attr "type" "dmpy")])
1258 (define_expand "mulsi3"
1259 [(set (reg:SI MACL_REG)
1260 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
1261 (match_operand:SI 2 "arith_reg_operand" "")))
1262 (set (match_operand:SI 0 "arith_reg_operand" "")
1271 /* The address must be set outside the libcall,
1272 since it goes into a pseudo. */
1273 rtx sym = gen_rtx_SYMBOL_REF (SImode, \"__mulsi3\");
1274 rtx addr = force_reg (SImode, sym);
1275 rtx insns = gen_mulsi3_call (operands[0], operands[1],
1277 first = XVECEXP (insns, 0, 0);
1278 last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1283 rtx macl = gen_rtx_REG (SImode, MACL_REG);
1285 first = emit_insn (gen_mul_l (operands[1], operands[2]));
1286 /* consec_sets_giv can only recognize the first insn that sets a
1287 giv as the giv insn. So we must tag this also with a REG_EQUAL
1289 last = emit_insn (gen_movsi_i ((operands[0]), macl));
1291 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1292 invariant code motion can move it. */
1293 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1294 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1298 (define_insn "mulsidi3_i"
1299 [(set (reg:SI MACH_REG)
1303 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1304 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1306 (set (reg:SI MACL_REG)
1307 (mult:SI (match_dup 0)
1311 [(set_attr "type" "dmpy")])
1313 (define_insn "mulsidi3"
1314 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1316 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1317 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1318 (clobber (reg:SI MACH_REG))
1319 (clobber (reg:SI MACL_REG))]
1324 [(set (match_operand:DI 0 "arith_reg_operand" "")
1326 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1327 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1328 (clobber (reg:SI MACH_REG))
1329 (clobber (reg:SI MACL_REG))]
1334 rtx low_dst = gen_lowpart (SImode, operands[0]);
1335 rtx high_dst = gen_highpart (SImode, operands[0]);
1337 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
1339 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
1340 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
1341 /* We need something to tag the possible REG_EQUAL notes on to. */
1342 emit_move_insn (operands[0], operands[0]);
1346 (define_insn "umulsidi3_i"
1347 [(set (reg:SI MACH_REG)
1351 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1352 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1354 (set (reg:SI MACL_REG)
1355 (mult:SI (match_dup 0)
1359 [(set_attr "type" "dmpy")])
1361 (define_insn "umulsidi3"
1362 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1364 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1365 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1366 (clobber (reg:SI MACH_REG))
1367 (clobber (reg:SI MACL_REG))]
1372 [(set (match_operand:DI 0 "arith_reg_operand" "")
1373 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1374 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1375 (clobber (reg:SI MACH_REG))
1376 (clobber (reg:SI MACL_REG))]
1381 rtx low_dst = gen_lowpart (SImode, operands[0]);
1382 rtx high_dst = gen_highpart (SImode, operands[0]);
1384 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
1386 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
1387 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
1388 /* We need something to tag the possible REG_EQUAL notes on to. */
1389 emit_move_insn (operands[0], operands[0]);
1393 (define_insn "smulsi3_highpart_i"
1394 [(set (reg:SI MACH_REG)
1398 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1399 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1401 (clobber (reg:SI MACL_REG))]
1404 [(set_attr "type" "dmpy")])
1406 (define_expand "smulsi3_highpart"
1408 [(set (reg:SI MACH_REG)
1412 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1413 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1415 (clobber (reg:SI MACL_REG))])
1416 (set (match_operand:SI 0 "arith_reg_operand" "")
1423 first = emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
1424 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
1425 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1426 invariant code motion can move it. */
1427 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1428 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1429 /* expand_binop can't find a suitable code in mul_highpart_optab to
1430 make a REG_EQUAL note from, so make one here.
1431 ??? Alternatively, we could put this at the calling site of expand_binop,
1432 i.e. expand_mult_highpart. */
1434 = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
1439 (define_insn "umulsi3_highpart_i"
1440 [(set (reg:SI MACH_REG)
1444 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1445 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1447 (clobber (reg:SI MACL_REG))]
1450 [(set_attr "type" "dmpy")])
1452 (define_expand "umulsi3_highpart"
1454 [(set (reg:SI MACH_REG)
1458 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1459 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1461 (clobber (reg:SI MACL_REG))])
1462 (set (match_operand:SI 0 "arith_reg_operand" "")
1469 first = emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
1470 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
1471 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1472 invariant code motion can move it. */
1473 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1474 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1478 ;; -------------------------------------------------------------------------
1479 ;; Logical operations
1480 ;; -------------------------------------------------------------------------
1483 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1484 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1485 (match_operand:SI 2 "logical_operand" "r,L")))]
1488 [(set_attr "type" "arith")])
1490 ;; If the constant is 255, then emit a extu.b instruction instead of an
1491 ;; and, since that will give better code.
1493 (define_expand "andsi3"
1494 [(set (match_operand:SI 0 "arith_reg_operand" "")
1495 (and:SI (match_operand:SI 1 "arith_reg_operand" "")
1496 (match_operand:SI 2 "logical_operand" "")))]
1500 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
1502 emit_insn (gen_zero_extendqisi2 (operands[0],
1503 gen_lowpart (QImode, operands[1])));
1508 (define_insn "iorsi3"
1509 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1510 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1511 (match_operand:SI 2 "logical_operand" "r,L")))]
1514 [(set_attr "type" "arith")])
1516 (define_insn "xorsi3"
1517 [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
1518 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1519 (match_operand:SI 2 "logical_operand" "L,r")))]
1522 [(set_attr "type" "arith")])
1524 ;; -------------------------------------------------------------------------
1525 ;; Shifts and rotates
1526 ;; -------------------------------------------------------------------------
1528 (define_insn "rotlsi3_1"
1529 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1530 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1533 (lshiftrt:SI (match_dup 1) (const_int 31)))]
1536 [(set_attr "type" "arith")])
1538 (define_insn "rotlsi3_31"
1539 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1540 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1542 (clobber (reg:SI T_REG))]
1545 [(set_attr "type" "arith")])
1547 (define_insn "rotlsi3_16"
1548 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1549 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
1553 [(set_attr "type" "arith")])
1555 (define_expand "rotlsi3"
1556 [(set (match_operand:SI 0 "arith_reg_operand" "")
1557 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
1558 (match_operand:SI 2 "immediate_operand" "")))]
1562 static char rot_tab[] = {
1563 000, 000, 000, 000, 000, 000, 010, 001,
1564 001, 001, 011, 013, 003, 003, 003, 003,
1565 003, 003, 003, 003, 003, 013, 012, 002,
1566 002, 002, 010, 000, 000, 000, 000, 000,
1571 if (GET_CODE (operands[2]) != CONST_INT)
1573 count = INTVAL (operands[2]);
1574 choice = rot_tab[count];
1575 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
1581 emit_move_insn (operands[0], operands[1]);
1582 count -= (count & 16) * 2;
1585 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
1592 parts[0] = gen_reg_rtx (SImode);
1593 parts[1] = gen_reg_rtx (SImode);
1594 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
1595 parts[choice-1] = operands[1];
1596 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
1597 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
1598 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
1599 count = (count & ~16) - 8;
1603 for (; count > 0; count--)
1604 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1605 for (; count < 0; count++)
1606 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1611 (define_insn "*rotlhi3_8"
1612 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1613 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
1617 [(set_attr "type" "arith")])
1619 (define_expand "rotlhi3"
1620 [(set (match_operand:HI 0 "arith_reg_operand" "")
1621 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
1622 (match_operand:HI 2 "immediate_operand" "")))]
1626 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
1633 ;; This pattern is used by init_expmed for computing the costs of shift
1636 (define_insn_and_split "ashlsi3_std"
1637 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r")
1638 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
1639 (match_operand:SI 2 "nonmemory_operand" "r,M,K,?ri")))
1640 (clobber (match_scratch:SI 3 "=X,X,X,&r"))]
1642 || (GET_CODE (operands[2]) == CONST_INT
1643 && CONST_OK_FOR_K (INTVAL (operands[2])))"
1650 && GET_CODE (operands[2]) == CONST_INT
1651 && ! CONST_OK_FOR_K (INTVAL (operands[2]))"
1652 [(set (match_dup 3) (match_dup 2))
1654 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
1655 (clobber (match_dup 4))])]
1656 "operands[4] = gen_rtx_SCRATCH (SImode);"
1657 [(set_attr "length" "*,*,*,4")
1658 (set_attr "type" "dyn_shift,arith,arith,arith")])
1660 (define_insn "ashlhi3_k"
1661 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
1662 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
1663 (match_operand:HI 2 "const_int_operand" "M,K")))]
1664 "CONST_OK_FOR_K (INTVAL (operands[2]))"
1668 [(set_attr "type" "arith")])
1670 (define_insn "ashlsi3_n"
1671 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1672 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
1673 (match_operand:SI 2 "const_int_operand" "n")))
1674 (clobber (reg:SI T_REG))]
1675 "! sh_dynamicalize_shift_p (operands[2])"
1677 [(set (attr "length")
1678 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1680 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1682 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1684 (const_string "8")))
1685 (set_attr "type" "arith")])
1688 [(set (match_operand:SI 0 "arith_reg_operand" "")
1689 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1690 (match_operand:SI 2 "const_int_operand" "n")))
1691 (clobber (reg:SI T_REG))]
1693 [(use (reg:SI R0_REG))]
1696 gen_shifty_op (ASHIFT, operands);
1700 (define_expand "ashlsi3"
1701 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1702 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1703 (match_operand:SI 2 "nonmemory_operand" "")))
1704 (clobber (reg:SI T_REG))])]
1708 if (GET_CODE (operands[2]) == CONST_INT
1709 && sh_dynamicalize_shift_p (operands[2]))
1710 operands[2] = force_reg (SImode, operands[2]);
1713 emit_insn (gen_ashlsi3_std (operands[0], operands[1], operands[2]));
1716 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1720 (define_insn "ashlhi3"
1721 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1722 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
1723 (match_operand:HI 2 "const_int_operand" "n")))
1724 (clobber (reg:SI T_REG))]
1727 [(set (attr "length")
1728 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1730 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1732 (const_string "6")))
1733 (set_attr "type" "arith")])
1736 [(set (match_operand:HI 0 "arith_reg_operand" "")
1737 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
1738 (match_operand:HI 2 "const_int_operand" "n")))
1739 (clobber (reg:SI T_REG))]
1741 [(use (reg:SI R0_REG))]
1744 gen_shifty_hi_op (ASHIFT, operands);
1749 ; arithmetic shift right
1752 (define_insn "ashrsi3_k"
1753 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1754 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1755 (match_operand:SI 2 "const_int_operand" "M")))
1756 (clobber (reg:SI T_REG))]
1757 "INTVAL (operands[2]) == 1"
1759 [(set_attr "type" "arith")])
1761 ;; We can't do HImode right shifts correctly unless we start out with an
1762 ;; explicit zero / sign extension; doing that would result in worse overall
1763 ;; code, so just let the machine independent code widen the mode.
1764 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
1767 ;; ??? This should be a define expand.
1769 (define_insn "ashrsi2_16"
1770 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1771 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1775 [(set_attr "length" "4")])
1778 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1779 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1782 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
1783 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
1784 "operands[2] = gen_lowpart (HImode, operands[0]);")
1786 ;; ??? This should be a define expand.
1788 (define_insn "ashrsi2_31"
1789 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1790 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1792 (clobber (reg:SI T_REG))]
1795 [(set_attr "length" "4")])
1798 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1799 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1801 (clobber (reg:SI T_REG))]
1806 emit_insn (gen_ashlsi_c (operands[0], operands[1]));
1807 emit_insn (gen_subc1 (operands[0], operands[0], operands[0]));
1811 (define_insn "ashlsi_c"
1812 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1813 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
1815 (lt:SI (match_dup 1) (const_int 0)))]
1818 [(set_attr "type" "arith")])
1820 (define_insn "ashrsi3_d"
1821 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1822 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1823 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1826 [(set_attr "type" "dyn_shift")])
1828 (define_insn "ashrsi3_n"
1829 [(set (reg:SI R4_REG)
1830 (ashiftrt:SI (reg:SI R4_REG)
1831 (match_operand:SI 0 "const_int_operand" "i")))
1832 (clobber (reg:SI T_REG))
1833 (clobber (reg:SI PR_REG))
1834 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1837 [(set_attr "type" "sfunc")
1838 (set_attr "needs_delay_slot" "yes")])
1840 (define_expand "ashrsi3"
1841 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1842 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1843 (match_operand:SI 2 "nonmemory_operand" "")))
1844 (clobber (reg:SI T_REG))])]
1846 "if (expand_ashiftrt (operands)) DONE; else FAIL;")
1848 ;; logical shift right
1850 (define_insn "lshrsi3_d"
1851 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1852 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1853 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1856 [(set_attr "type" "dyn_shift")])
1858 ;; Only the single bit shift clobbers the T bit.
1860 (define_insn "lshrsi3_m"
1861 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1862 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1863 (match_operand:SI 2 "const_int_operand" "M")))
1864 (clobber (reg:SI T_REG))]
1865 "CONST_OK_FOR_M (INTVAL (operands[2]))"
1867 [(set_attr "type" "arith")])
1869 (define_insn "lshrsi3_k"
1870 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1871 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1872 (match_operand:SI 2 "const_int_operand" "K")))]
1873 "CONST_OK_FOR_K (INTVAL (operands[2]))
1874 && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
1876 [(set_attr "type" "arith")])
1878 (define_insn "lshrsi3_n"
1879 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1880 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1881 (match_operand:SI 2 "const_int_operand" "n")))
1882 (clobber (reg:SI T_REG))]
1883 "! sh_dynamicalize_shift_p (operands[2])"
1885 [(set (attr "length")
1886 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1888 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1890 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1892 (const_string "8")))
1893 (set_attr "type" "arith")])
1896 [(set (match_operand:SI 0 "arith_reg_operand" "")
1897 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1898 (match_operand:SI 2 "const_int_operand" "n")))
1899 (clobber (reg:SI T_REG))]
1901 [(use (reg:SI R0_REG))]
1904 gen_shifty_op (LSHIFTRT, operands);
1908 (define_expand "lshrsi3"
1909 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1910 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1911 (match_operand:SI 2 "nonmemory_operand" "")))
1912 (clobber (reg:SI T_REG))])]
1916 if (GET_CODE (operands[2]) == CONST_INT
1917 && sh_dynamicalize_shift_p (operands[2]))
1918 operands[2] = force_reg (SImode, operands[2]);
1919 if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
1921 rtx count = copy_to_mode_reg (SImode, operands[2]);
1922 emit_insn (gen_negsi2 (count, count));
1923 emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
1926 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1930 ;; ??? This should be a define expand.
1932 (define_insn "ashldi3_k"
1933 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1934 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
1936 (clobber (reg:SI T_REG))]
1938 "shll %R0\;rotcl %S0"
1939 [(set_attr "length" "4")
1940 (set_attr "type" "arith")])
1942 (define_expand "ashldi3"
1943 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1944 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
1945 (match_operand:DI 2 "immediate_operand" "")))
1946 (clobber (reg:SI T_REG))])]
1948 "{ if (GET_CODE (operands[2]) != CONST_INT
1949 || INTVAL (operands[2]) != 1) FAIL;} ")
1951 ;; ??? This should be a define expand.
1953 (define_insn "lshrdi3_k"
1954 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1955 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1957 (clobber (reg:SI T_REG))]
1959 "shlr %S0\;rotcr %R0"
1960 [(set_attr "length" "4")
1961 (set_attr "type" "arith")])
1963 (define_expand "lshrdi3"
1964 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1965 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1966 (match_operand:DI 2 "immediate_operand" "")))
1967 (clobber (reg:SI T_REG))])]
1969 "{ if (GET_CODE (operands[2]) != CONST_INT
1970 || INTVAL (operands[2]) != 1) FAIL;} ")
1972 ;; ??? This should be a define expand.
1974 (define_insn "ashrdi3_k"
1975 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1976 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1978 (clobber (reg:SI T_REG))]
1980 "shar %S0\;rotcr %R0"
1981 [(set_attr "length" "4")
1982 (set_attr "type" "arith")])
1984 (define_expand "ashrdi3"
1985 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1986 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1987 (match_operand:DI 2 "immediate_operand" "")))
1988 (clobber (reg:SI T_REG))])]
1990 "{ if (GET_CODE (operands[2]) != CONST_INT
1991 || INTVAL (operands[2]) != 1) FAIL; } ")
1993 ;; combined left/right shift
1996 [(set (match_operand:SI 0 "register_operand" "")
1997 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
1998 (match_operand:SI 2 "const_int_operand" "n"))
1999 (match_operand:SI 3 "const_int_operand" "n")))]
2000 "(unsigned)INTVAL (operands[2]) < 32"
2001 [(use (reg:SI R0_REG))]
2002 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
2006 [(set (match_operand:SI 0 "register_operand" "")
2007 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
2008 (match_operand:SI 2 "const_int_operand" "n"))
2009 (match_operand:SI 3 "const_int_operand" "n")))
2010 (clobber (reg:SI T_REG))]
2011 "(unsigned)INTVAL (operands[2]) < 32"
2012 [(use (reg:SI R0_REG))]
2013 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
2017 [(set (match_operand:SI 0 "register_operand" "=r")
2018 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2019 (match_operand:SI 2 "const_int_operand" "n"))
2020 (match_operand:SI 3 "const_int_operand" "n")))
2021 (clobber (reg:SI T_REG))]
2022 "shl_and_kind (operands[2], operands[3], 0) == 1"
2024 [(set (attr "length")
2025 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
2027 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
2029 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
2031 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
2033 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
2035 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
2037 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
2038 (const_string "16")]
2039 (const_string "18")))
2040 (set_attr "type" "arith")])
2043 [(set (match_operand:SI 0 "register_operand" "=z")
2044 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2045 (match_operand:SI 2 "const_int_operand" "n"))
2046 (match_operand:SI 3 "const_int_operand" "n")))
2047 (clobber (reg:SI T_REG))]
2048 "shl_and_kind (operands[2], operands[3], 0) == 2"
2050 [(set (attr "length")
2051 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
2053 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
2055 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
2057 (const_string "10")))
2058 (set_attr "type" "arith")])
2060 ;; shift left / and combination with a scratch register: The combine pass
2061 ;; does not accept the individual instructions, even though they are
2062 ;; cheap. But it needs a precise description so that it is usable after
2064 (define_insn "and_shl_scratch"
2065 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2069 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
2070 (match_operand:SI 2 "const_int_operand" "N,n"))
2071 (match_operand:SI 3 "" "0,r"))
2072 (match_operand:SI 4 "const_int_operand" "n,n"))
2073 (match_operand:SI 5 "const_int_operand" "n,n")))
2074 (clobber (reg:SI T_REG))]
2077 [(set (attr "length")
2078 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
2080 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
2082 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
2084 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
2085 (const_string "10")]
2086 (const_string "12")))
2087 (set_attr "type" "arith")])
2090 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2094 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
2095 (match_operand:SI 2 "const_int_operand" "N,n"))
2096 (match_operand:SI 3 "register_operand" "0,r"))
2097 (match_operand:SI 4 "const_int_operand" "n,n"))
2098 (match_operand:SI 5 "const_int_operand" "n,n")))
2099 (clobber (reg:SI T_REG))]
2101 [(use (reg:SI R0_REG))]
2104 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
2106 if (INTVAL (operands[2]))
2108 gen_shifty_op (LSHIFTRT, operands);
2110 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
2111 operands[2] = operands[4];
2112 gen_shifty_op (ASHIFT, operands);
2113 if (INTVAL (operands[5]))
2115 operands[2] = operands[5];
2116 gen_shifty_op (LSHIFTRT, operands);
2121 ;; signed left/right shift combination.
2123 [(set (match_operand:SI 0 "register_operand" "=r")
2125 (ashift:SI (match_operand:SI 1 "register_operand" "r")
2126 (match_operand:SI 2 "const_int_operand" "n"))
2127 (match_operand:SI 3 "const_int_operand" "n")
2129 (clobber (reg:SI T_REG))]
2131 [(use (reg:SI R0_REG))]
2132 "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
2135 (define_insn "shl_sext_ext"
2136 [(set (match_operand:SI 0 "register_operand" "=r")
2138 (ashift:SI (match_operand:SI 1 "register_operand" "0")
2139 (match_operand:SI 2 "const_int_operand" "n"))
2140 (match_operand:SI 3 "const_int_operand" "n")
2142 (clobber (reg:SI T_REG))]
2143 "(unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
2145 [(set (attr "length")
2146 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 1))
2148 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
2150 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2152 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2154 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2156 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2158 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
2160 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
2161 (const_string "16")]
2162 (const_string "18")))
2163 (set_attr "type" "arith")])
2165 (define_insn "shl_sext_sub"
2166 [(set (match_operand:SI 0 "register_operand" "=z")
2168 (ashift:SI (match_operand:SI 1 "register_operand" "0")
2169 (match_operand:SI 2 "const_int_operand" "n"))
2170 (match_operand:SI 3 "const_int_operand" "n")
2172 (clobber (reg:SI T_REG))]
2173 "(shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
2175 [(set (attr "length")
2176 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2178 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2180 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2182 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2183 (const_string "12")]
2184 (const_string "14")))
2185 (set_attr "type" "arith")])
2187 ;; These patterns are found in expansions of DImode shifts by 16, and
2188 ;; allow the xtrct instruction to be generated from C source.
2190 (define_insn "xtrct_left"
2191 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2192 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
2194 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
2198 [(set_attr "type" "arith")])
2200 (define_insn "xtrct_right"
2201 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2202 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2204 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
2208 [(set_attr "type" "arith")])
2210 ;; -------------------------------------------------------------------------
2212 ;; -------------------------------------------------------------------------
2215 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2216 (neg:SI (plus:SI (reg:SI T_REG)
2217 (match_operand:SI 1 "arith_reg_operand" "r"))))
2219 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
2223 [(set_attr "type" "arith")])
2225 (define_expand "negdi2"
2226 [(set (match_operand:DI 0 "arith_reg_operand" "")
2227 (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
2228 (clobber (reg:SI T_REG))]
2232 int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
2233 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
2235 rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
2236 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
2238 rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
2239 rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
2241 emit_insn (gen_clrt ());
2242 emit_insn (gen_negc (low_dst, low_src));
2243 emit_insn (gen_negc (high_dst, high_src));
2247 (define_insn "negsi2"
2248 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2249 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2252 [(set_attr "type" "arith")])
2254 (define_insn "one_cmplsi2"
2255 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2256 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2259 [(set_attr "type" "arith")])
2261 ;; -------------------------------------------------------------------------
2262 ;; Zero extension instructions
2263 ;; -------------------------------------------------------------------------
2265 (define_insn "zero_extendhisi2"
2266 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2267 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
2270 [(set_attr "type" "arith")])
2272 (define_insn "zero_extendqisi2"
2273 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2274 (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
2277 [(set_attr "type" "arith")])
2279 (define_insn "zero_extendqihi2"
2280 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
2281 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
2284 [(set_attr "type" "arith")])
2286 ;; -------------------------------------------------------------------------
2287 ;; Sign extension instructions
2288 ;; -------------------------------------------------------------------------
2290 ;; ??? This should be a define expand.
2291 ;; ??? Or perhaps it should be dropped?
2293 /* There is no point in defining extendsidi2; convert_move generates good
2296 (define_insn "extendhisi2"
2297 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2298 (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
2303 [(set_attr "type" "arith,load")])
2305 (define_insn "extendqisi2"
2306 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2307 (sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2312 [(set_attr "type" "arith,load")])
2314 (define_insn "extendqihi2"
2315 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
2316 (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2321 [(set_attr "type" "arith,load")])
2323 ;; -------------------------------------------------------------------------
2324 ;; Move instructions
2325 ;; -------------------------------------------------------------------------
2327 ;; define push and pop so it is easy for sh.c
2329 (define_expand "push"
2330 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2331 (match_operand:SI 0 "register_operand" "r,l,x"))]
2335 (define_expand "pop"
2336 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
2337 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2341 (define_expand "push_e"
2342 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
2343 (match_operand:SF 0 "" ""))
2344 (use (reg:PSI FPSCR_REG))
2345 (clobber (scratch:SI))])]
2349 (define_insn "push_fpul"
2350 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
2353 [(set_attr "type" "store")
2354 (set_attr "hit_stack" "yes")])
2356 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
2358 (define_expand "push_4"
2359 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
2360 (match_operand:DF 0 "" ""))
2361 (use (reg:PSI FPSCR_REG))
2362 (clobber (scratch:SI))])]
2366 (define_expand "pop_e"
2367 [(parallel [(set (match_operand:SF 0 "" "")
2368 (mem:SF (post_inc:SI (reg:SI SP_REG))))
2369 (use (reg:PSI FPSCR_REG))
2370 (clobber (scratch:SI))])]
2374 (define_insn "pop_fpul"
2375 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
2378 [(set_attr "type" "load")
2379 (set_attr "hit_stack" "yes")])
2381 (define_expand "pop_4"
2382 [(parallel [(set (match_operand:DF 0 "" "")
2383 (mem:DF (post_inc:SI (reg:SI SP_REG))))
2384 (use (reg:PSI FPSCR_REG))
2385 (clobber (scratch:SI))])]
2389 ;; These two patterns can happen as the result of optimization, when
2390 ;; comparisons get simplified to a move of zero or 1 into the T reg.
2391 ;; They don't disappear completely, because the T reg is a fixed hard reg.
2394 [(set (reg:SI T_REG) (const_int 0))]
2399 [(set (reg:SI T_REG) (const_int 1))]
2403 ;; t/r must come after r/r, lest reload will try to reload stuff like
2404 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
2405 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
2406 (define_insn "movsi_i"
2407 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
2408 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
2411 && (register_operand (operands[0], SImode)
2412 || register_operand (operands[1], SImode))"
2429 [(set_attr "type" "pcload_si,move,*,load_si,move,prget,move,store,store,pstore,move,prset,load,pload,pcload_si")
2430 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
2432 ;; t/r must come after r/r, lest reload will try to reload stuff like
2433 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
2434 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
2435 ;; will require a reload.
2436 (define_insn "movsi_ie"
2437 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,r,y,r,y")
2438 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,>,i,r,y,y"))]
2440 && (register_operand (operands[0], SImode)
2441 || register_operand (operands[1], SImode))"
2461 ! move optimized away"
2462 [(set_attr "type" "pcload_si,move,*,load_si,move,prget,move,store,store,pstore,move,prset,load,pload,load,pcload_si,gp_fpul,gp_fpul,nil")
2463 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
2465 (define_insn "movsi_i_lowpart"
2466 [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
2467 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,mr,x,l,t,r,i"))]
2468 "register_operand (operands[0], SImode)
2469 || register_operand (operands[1], SImode)"
2479 [(set_attr "type" "pcload,move,load,move,prget,move,store,pcload")])
2481 (define_expand "movsi"
2482 [(set (match_operand:SI 0 "general_movdst_operand" "")
2483 (match_operand:SI 1 "general_movsrc_operand" ""))]
2485 "{ if (prepare_move_operands (operands, SImode)) DONE; }")
2487 (define_expand "ic_invalidate_line"
2488 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
2489 (match_dup 1)] UNSPEC_ICACHE)
2490 (clobber (scratch:SI))])]
2494 operands[0] = force_reg (Pmode, operands[0]);
2495 operands[1] = force_reg (Pmode, GEN_INT (0xf0000008));
2498 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
2499 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
2500 ;; the requirement *1*00 for associative address writes. The alignment of
2501 ;; %0 implies that its least significant bit is cleared,
2502 ;; thus we clear the V bit of a matching entry if there is one.
2503 (define_insn "ic_invalidate_line_i"
2504 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
2505 (match_operand:SI 1 "register_operand" "r")]
2507 (clobber (match_scratch:SI 2 "=&r"))]
2509 "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
2510 [(set_attr "length" "8")])
2512 (define_insn "movqi_i"
2513 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
2514 (match_operand:QI 1 "general_movsrc_operand" "ri,m,r,t,l,r"))]
2515 "arith_reg_operand (operands[0], QImode)
2516 || arith_reg_operand (operands[1], QImode)"
2524 [(set_attr "type" "move,load,store,move,move,move")])
2526 (define_expand "movqi"
2527 [(set (match_operand:QI 0 "general_operand" "")
2528 (match_operand:QI 1 "general_operand" ""))]
2530 "{ if (prepare_move_operands (operands, QImode)) DONE; }")
2532 (define_insn "movhi_i"
2533 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
2534 (match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
2535 "arith_reg_operand (operands[0], HImode)
2536 || arith_reg_operand (operands[1], HImode)"
2546 [(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
2548 (define_expand "movhi"
2549 [(set (match_operand:HI 0 "general_movdst_operand" "")
2550 (match_operand:HI 1 "general_movsrc_operand" ""))]
2552 "{ if (prepare_move_operands (operands, HImode)) DONE; }")
2554 ;; ??? This should be a define expand.
2556 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
2557 ;; compiled with -m2 -ml -O3 -funroll-loops
2559 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
2560 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))]
2561 "arith_reg_operand (operands[0], DImode)
2562 || arith_reg_operand (operands[1], DImode)"
2563 "* return output_movedouble (insn, operands, DImode);"
2564 [(set_attr "length" "4")
2565 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
2567 ;; If the output is a register and the input is memory or a register, we have
2568 ;; to be careful and see which word needs to be loaded first.
2571 [(set (match_operand:DI 0 "general_movdst_operand" "")
2572 (match_operand:DI 1 "general_movsrc_operand" ""))]
2574 [(set (match_dup 2) (match_dup 3))
2575 (set (match_dup 4) (match_dup 5))]
2580 if ((GET_CODE (operands[0]) == MEM
2581 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2582 || (GET_CODE (operands[1]) == MEM
2583 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2586 if (GET_CODE (operands[0]) == REG)
2587 regno = REGNO (operands[0]);
2588 else if (GET_CODE (operands[0]) == SUBREG)
2589 regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
2590 else if (GET_CODE (operands[0]) == MEM)
2594 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2596 operands[2] = operand_subword (operands[0], 0, 0, DImode);
2597 operands[3] = operand_subword (operands[1], 0, 0, DImode);
2598 operands[4] = operand_subword (operands[0], 1, 0, DImode);
2599 operands[5] = operand_subword (operands[1], 1, 0, DImode);
2603 operands[2] = operand_subword (operands[0], 1, 0, DImode);
2604 operands[3] = operand_subword (operands[1], 1, 0, DImode);
2605 operands[4] = operand_subword (operands[0], 0, 0, DImode);
2606 operands[5] = operand_subword (operands[1], 0, 0, DImode);
2609 if (operands[2] == 0 || operands[3] == 0
2610 || operands[4] == 0 || operands[5] == 0)
2614 (define_expand "movdi"
2615 [(set (match_operand:DI 0 "general_movdst_operand" "")
2616 (match_operand:DI 1 "general_movsrc_operand" ""))]
2618 "{ if (prepare_move_operands (operands, DImode)) DONE; }")
2620 ;; ??? This should be a define expand.
2622 (define_insn "movdf_k"
2623 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
2624 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
2625 "(! TARGET_SH4 || reload_completed
2626 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
2627 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
2628 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
2629 && (arith_reg_operand (operands[0], DFmode)
2630 || arith_reg_operand (operands[1], DFmode))"
2631 "* return output_movedouble (insn, operands, DFmode);"
2632 [(set_attr "length" "4")
2633 (set_attr "type" "move,pcload,load,store")])
2635 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
2636 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
2637 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
2638 ;; the d/m/c/X alternative, which is split later into single-precision
2639 ;; instructions. And when not optimizing, no splits are done before fixing
2640 ;; up pcloads, so we need usable length information for that.
2641 (define_insn "movdf_i4"
2642 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
2643 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
2644 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
2645 (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
2647 && (arith_reg_operand (operands[0], DFmode)
2648 || arith_reg_operand (operands[1], DFmode))"
2660 [(set_attr_alternative "length"
2661 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
2663 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
2664 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2665 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2667 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
2668 (const_int 8) (const_int 8)])
2669 (set_attr "type" "fmove,move,pcload,load,store,pcload,load,store,load,load")
2670 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
2671 (const_string "double")
2672 (const_string "none")))])
2674 ;; Moving DFmode between fp/general registers through memory
2675 ;; (the top of the stack) is faster than moving through fpul even for
2676 ;; little endian. Because the type of an instruction is important for its
2677 ;; scheduling, it is beneficial to split these operations, rather than
2678 ;; emitting them in one single chunk, even if this will expose a stack
2679 ;; use that will prevent scheduling of other stack accesses beyond this
2682 [(set (match_operand:DF 0 "register_operand" "")
2683 (match_operand:DF 1 "register_operand" ""))
2684 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2685 (clobber (match_scratch:SI 3 "=X"))]
2686 "TARGET_SH4 && reload_completed
2687 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
2693 tos = gen_rtx (MEM, DFmode, gen_rtx (PRE_DEC, Pmode, stack_pointer_rtx));
2694 insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
2695 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2696 tos = gen_rtx (MEM, DFmode, gen_rtx (POST_INC, Pmode, stack_pointer_rtx));
2697 insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
2698 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2702 ;; local-alloc sometimes allocates scratch registers even when not required,
2703 ;; so we must be prepared to handle these.
2705 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
2707 [(set (match_operand:DF 0 "general_movdst_operand" "")
2708 (match_operand:DF 1 "general_movsrc_operand" ""))
2709 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2710 (clobber (match_scratch:SI 3 "X"))]
2713 && true_regnum (operands[0]) < 16
2714 && true_regnum (operands[1]) < 16"
2715 [(set (match_dup 0) (match_dup 1))]
2718 /* If this was a reg <-> mem operation with base + index reg addressing,
2719 we have to handle this in a special way. */
2720 rtx mem = operands[0];
2722 if (! memory_operand (mem, DFmode))
2727 if (GET_CODE (mem) == SUBREG && SUBREG_WORD (mem) == 0)
2728 mem = SUBREG_REG (mem);
2729 if (GET_CODE (mem) == MEM)
2731 rtx addr = XEXP (mem, 0);
2732 if (GET_CODE (addr) == PLUS
2733 && GET_CODE (XEXP (addr, 0)) == REG
2734 && GET_CODE (XEXP (addr, 1)) == REG)
2737 rtx reg0 = gen_rtx (REG, Pmode, 0);
2738 rtx regop = operands[store_p], word0 ,word1;
2740 if (GET_CODE (regop) == SUBREG)
2741 regop = alter_subreg (regop);
2742 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
2746 mem = copy_rtx (mem);
2747 PUT_MODE (mem, SImode);
2748 word0 = gen_rtx(SUBREG, SImode, regop, 0);
2750 ? gen_movsi_ie (mem, word0) : gen_movsi_ie (word0, mem));
2751 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
2752 mem = copy_rtx (mem);
2753 word1 = gen_rtx(SUBREG, SImode, regop, 1);
2755 ? gen_movsi_ie (mem, word1) : gen_movsi_ie (word1, mem));
2756 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
2762 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
2764 [(set (match_operand:DF 0 "register_operand" "")
2765 (match_operand:DF 1 "memory_operand" ""))
2766 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2767 (clobber (reg:SI R0_REG))]
2768 "TARGET_SH4 && reload_completed"
2769 [(parallel [(set (match_dup 0) (match_dup 1))
2771 (clobber (scratch:SI))])]
2774 (define_expand "reload_indf"
2775 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
2776 (match_operand:DF 1 "immediate_operand" "FQ"))
2777 (use (reg:PSI FPSCR_REG))
2778 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
2782 (define_expand "reload_outdf"
2783 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
2784 (match_operand:DF 1 "register_operand" "af,r"))
2785 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
2789 ;; Simplify no-op moves.
2791 [(set (match_operand:SF 0 "register_operand" "")
2792 (match_operand:SF 1 "register_operand" ""))
2793 (use (match_operand:PSI 2 "fpscr_operand" ""))
2794 (clobber (match_scratch:SI 3 "X"))]
2795 "TARGET_SH3E && reload_completed
2796 && true_regnum (operands[0]) == true_regnum (operands[1])"
2797 [(set (match_dup 0) (match_dup 0))]
2800 ;; fmovd substitute post-reload splits
2802 [(set (match_operand:DF 0 "register_operand" "")
2803 (match_operand:DF 1 "register_operand" ""))
2804 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2805 (clobber (match_scratch:SI 3 "X"))]
2806 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2807 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
2808 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
2812 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
2813 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst),
2814 gen_rtx (REG, SFmode, src), operands[2]));
2815 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst + 1),
2816 gen_rtx (REG, SFmode, src + 1), operands[2]));
2821 [(set (match_operand:DF 0 "register_operand" "")
2822 (mem:DF (match_operand:SI 1 "register_operand" "")))
2823 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2824 (clobber (match_scratch:SI 3 "X"))]
2825 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2826 && FP_OR_XD_REGISTER_P (operands[0])
2827 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
2831 int regno = true_regnum (operands[0]);
2833 rtx mem2 = gen_rtx (MEM, SFmode, gen_rtx (POST_INC, Pmode, operands[1]));
2835 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2836 regno + !! TARGET_LITTLE_ENDIAN),
2837 mem2, operands[2]));
2838 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[1], NULL_RTX);
2839 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2840 regno + ! TARGET_LITTLE_ENDIAN),
2841 gen_rtx (MEM, SFmode, operands[1]),
2847 [(set (match_operand:DF 0 "register_operand" "")
2848 (match_operand:DF 1 "memory_operand" ""))
2849 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2850 (clobber (match_scratch:SI 3 "X"))]
2851 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2852 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
2856 int regno = true_regnum (operands[0]);
2857 rtx addr, insn, adjust = NULL_RTX;
2858 rtx mem2 = copy_rtx (operands[1]);
2859 rtx reg0 = gen_rtx_REG (SFmode, regno + !! TARGET_LITTLE_ENDIAN);
2860 rtx reg1 = gen_rtx_REG (SFmode, regno + ! TARGET_LITTLE_ENDIAN);
2862 PUT_MODE (mem2, SFmode);
2863 operands[1] = copy_rtx (mem2);
2864 addr = XEXP (mem2, 0);
2865 if (GET_CODE (addr) != POST_INC)
2867 /* If we have to modify the stack pointer, the value that we have
2868 read with post-increment might be modified by an interrupt,
2869 so write it back. */
2870 if (REGNO (addr) == STACK_POINTER_REGNUM)
2871 adjust = gen_push_e (reg0);
2873 adjust = gen_addsi3 (addr, addr, GEN_INT (-4));
2874 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
2876 addr = XEXP (addr, 0);
2877 insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
2878 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2879 insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
2883 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2888 [(set (match_operand:DF 0 "memory_operand" "")
2889 (match_operand:DF 1 "register_operand" ""))
2890 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2891 (clobber (match_scratch:SI 3 "X"))]
2892 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2893 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
2897 int regno = true_regnum (operands[1]);
2898 rtx insn, addr, adjust = NULL_RTX;
2900 operands[0] = copy_rtx (operands[0]);
2901 PUT_MODE (operands[0], SFmode);
2902 insn = emit_insn (gen_movsf_ie (operands[0],
2903 gen_rtx (REG, SFmode,
2904 regno + ! TARGET_LITTLE_ENDIAN),
2906 operands[0] = copy_rtx (operands[0]);
2907 addr = XEXP (operands[0], 0);
2908 if (GET_CODE (addr) != PRE_DEC)
2910 adjust = gen_addsi3 (addr, addr, GEN_INT (4));
2911 emit_insn_before (adjust, insn);
2912 XEXP (operands[0], 0) = addr = gen_rtx (PRE_DEC, SImode, addr);
2914 addr = XEXP (addr, 0);
2916 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2917 insn = emit_insn (gen_movsf_ie (operands[0],
2918 gen_rtx (REG, SFmode,
2919 regno + !! TARGET_LITTLE_ENDIAN),
2921 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2925 ;; The '&' for operand 2 is not really true, but push_secondary_reload
2927 ;; Operand 1 must accept FPUL_REGS in case fpul is reloaded to memory,
2928 ;; to avoid a bogus tertiary reload.
2929 ;; We need a tertiary reload when a floating point register is reloaded
2930 ;; to memory, so the predicate for operand 0 must accept this, while the
2931 ;; constraint of operand 1 must reject the secondary reload register.
2932 ;; Thus, the secondary reload register for this case has to be GENERAL_REGS,
2934 ;; By having the predicate for operand 0 reject any register, we make
2935 ;; sure that the ordinary moves that just need an intermediate register
2936 ;; won't get a bogus tertiary reload.
2937 ;; We use tertiary_reload_operand instead of memory_operand here because
2938 ;; memory_operand rejects operands that are not directly addressible, e.g.:
2939 ;; (mem:SF (plus:SI (reg:SI FP_REG)
2940 ;; (const_int 132)))
2942 (define_expand "reload_outsf"
2943 [(parallel [(set (match_operand:SF 2 "register_operand" "=&r")
2944 (match_operand:SF 1 "register_operand" "y"))
2945 (clobber (scratch:SI))])
2946 (parallel [(set (match_operand:SF 0 "tertiary_reload_operand" "=m")
2948 (clobber (scratch:SI))])]
2952 ;; If the output is a register and the input is memory or a register, we have
2953 ;; to be careful and see which word needs to be loaded first.
2956 [(set (match_operand:DF 0 "general_movdst_operand" "")
2957 (match_operand:DF 1 "general_movsrc_operand" ""))]
2959 [(set (match_dup 2) (match_dup 3))
2960 (set (match_dup 4) (match_dup 5))]
2965 if ((GET_CODE (operands[0]) == MEM
2966 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2967 || (GET_CODE (operands[1]) == MEM
2968 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2971 if (GET_CODE (operands[0]) == REG)
2972 regno = REGNO (operands[0]);
2973 else if (GET_CODE (operands[0]) == SUBREG)
2974 regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
2975 else if (GET_CODE (operands[0]) == MEM)
2979 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2981 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2982 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2983 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2984 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
2988 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
2989 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
2990 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
2991 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
2994 if (operands[2] == 0 || operands[3] == 0
2995 || operands[4] == 0 || operands[5] == 0)
2999 ;; If a base address generated by LEGITIMIZE_ADDRESS for SImode is
3000 ;; used only once, let combine add in the index again.
3003 [(set (match_operand:SI 0 "register_operand" "")
3004 (match_operand:SI 1 "" ""))
3005 (clobber (match_operand 2 "register_operand" ""))]
3006 "! reload_in_progress && ! reload_completed"
3007 [(use (reg:SI R0_REG))]
3010 rtx addr, reg, const_int;
3012 if (GET_CODE (operands[1]) != MEM)
3014 addr = XEXP (operands[1], 0);
3015 if (GET_CODE (addr) != PLUS)
3017 reg = XEXP (addr, 0);
3018 const_int = XEXP (addr, 1);
3019 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
3020 && GET_CODE (const_int) == CONST_INT))
3022 emit_move_insn (operands[2], const_int);
3023 emit_move_insn (operands[0],
3024 change_address (operands[1], VOIDmode,
3025 gen_rtx_PLUS (SImode, reg, operands[2])));
3030 [(set (match_operand:SI 1 "" "")
3031 (match_operand:SI 0 "register_operand" ""))
3032 (clobber (match_operand 2 "register_operand" ""))]
3033 "! reload_in_progress && ! reload_completed"
3034 [(use (reg:SI R0_REG))]
3037 rtx addr, reg, const_int;
3039 if (GET_CODE (operands[1]) != MEM)
3041 addr = XEXP (operands[1], 0);
3042 if (GET_CODE (addr) != PLUS)
3044 reg = XEXP (addr, 0);
3045 const_int = XEXP (addr, 1);
3046 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
3047 && GET_CODE (const_int) == CONST_INT))
3049 emit_move_insn (operands[2], const_int);
3050 emit_move_insn (change_address (operands[1], VOIDmode,
3051 gen_rtx_PLUS (SImode, reg, operands[2])),
3056 (define_expand "movdf"
3057 [(set (match_operand:DF 0 "general_movdst_operand" "")
3058 (match_operand:DF 1 "general_movsrc_operand" ""))]
3062 if (prepare_move_operands (operands, DFmode)) DONE;
3065 emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
3071 (define_insn "movsf_i"
3072 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
3073 (match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
3076 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
3077 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
3078 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
3079 && (arith_reg_operand (operands[0], SFmode)
3080 || arith_reg_operand (operands[1], SFmode))"
3089 [(set_attr "type" "move,move,pcload,load,store,move,move")])
3091 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
3092 ;; update_flow_info would not know where to put REG_EQUAL notes
3093 ;; when the destination changes mode.
3094 (define_insn "movsf_ie"
3095 [(set (match_operand:SF 0 "general_movdst_operand"
3096 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,y")
3097 (match_operand:SF 1 "general_movsrc_operand"
3098 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y"))
3099 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
3100 (clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X"))]
3103 && (arith_reg_operand (operands[0], SFmode)
3104 || arith_reg_operand (operands[1], SFmode))"
3122 ! move optimized away"
3123 [(set_attr "type" "fmove,move,fmove,fmove,pcload,load,store,pcload,load,store,fmove,fmove,load,*,gp_fpul,gp_fpul,nil")
3124 (set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,4,2,2,0")
3125 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
3126 (const_string "single")
3127 (const_string "none")))])
3129 [(set (match_operand:SF 0 "register_operand" "")
3130 (match_operand:SF 1 "register_operand" ""))
3131 (use (match_operand:PSI 2 "fpscr_operand" "c"))
3132 (clobber (reg:SI FPUL_REG))]
3134 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
3136 (clobber (scratch:SI))])
3137 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
3139 (clobber (scratch:SI))])]
3142 (define_expand "movsf"
3143 [(set (match_operand:SF 0 "general_movdst_operand" "")
3144 (match_operand:SF 1 "general_movsrc_operand" ""))]
3148 if (prepare_move_operands (operands, SFmode))
3152 emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
3157 (define_insn "mov_nop"
3158 [(set (match_operand 0 "register_operand" "") (match_dup 0))]
3161 [(set_attr "length" "0")
3162 (set_attr "type" "nil")])
3164 (define_expand "reload_insf"
3165 [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
3166 (match_operand:SF 1 "immediate_operand" "FQ"))
3167 (use (reg:PSI FPSCR_REG))
3168 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
3172 (define_expand "reload_insi"
3173 [(parallel [(set (match_operand:SF 0 "register_operand" "=y")
3174 (match_operand:SF 1 "immediate_operand" "FQ"))
3175 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
3179 (define_insn "*movsi_y"
3180 [(set (match_operand:SI 0 "register_operand" "=y,y")
3181 (match_operand:SI 1 "immediate_operand" "Qi,I"))
3182 (clobber (match_scratch:SI 2 "=&z,r"))]
3184 && (reload_in_progress || reload_completed)"
3186 [(set_attr "length" "4")
3187 (set_attr "type" "pcload,move")])
3190 [(set (match_operand:SI 0 "register_operand" "")
3191 (match_operand:SI 1 "immediate_operand" ""))
3192 (clobber (match_operand:SI 2 "register_operand" ""))]
3194 [(set (match_dup 2) (match_dup 1))
3195 (set (match_dup 0) (match_dup 2))]
3199 [(set (match_operand:SI 0 "register_operand" "")
3200 (match_operand:SI 1 "memory_operand" ""))
3201 (clobber (reg:SI R0_REG))]
3203 [(set (match_dup 0) (match_dup 1))]
3206 ;; ------------------------------------------------------------------------
3207 ;; Define the real conditional branch instructions.
3208 ;; ------------------------------------------------------------------------
3210 (define_insn "branch_true"
3211 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
3212 (label_ref (match_operand 0 "" ""))
3215 "* return output_branch (1, insn, operands);"
3216 [(set_attr "type" "cbranch")])
3218 (define_insn "branch_false"
3219 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
3220 (label_ref (match_operand 0 "" ""))
3223 "* return output_branch (0, insn, operands);"
3224 [(set_attr "type" "cbranch")])
3226 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
3227 ;; which destination is too far away.
3228 ;; The const_int_operand is distinct for each branch target; it avoids
3229 ;; unwanted matches with redundant_insn.
3230 (define_insn "block_branch_redirect"
3231 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
3234 [(set_attr "length" "0")])
3236 ;; This one has the additional purpose to record a possible scratch register
3237 ;; for the following branch.
3238 (define_insn "indirect_jump_scratch"
3239 [(set (match_operand 0 "register_operand" "=r")
3240 (unspec [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))]
3243 [(set_attr "length" "0")])
3245 ;; Conditional branch insns
3247 (define_expand "beq"
3249 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3250 (label_ref (match_operand 0 "" ""))
3253 "from_compare (operands, EQ);")
3255 (define_expand "bne"
3257 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3258 (label_ref (match_operand 0 "" ""))
3261 "from_compare (operands, EQ);")
3263 (define_expand "bgt"
3265 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3266 (label_ref (match_operand 0 "" ""))
3269 "from_compare (operands, GT);")
3271 (define_expand "blt"
3273 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3274 (label_ref (match_operand 0 "" ""))
3279 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3281 rtx tmp = sh_compare_op0;
3282 sh_compare_op0 = sh_compare_op1;
3283 sh_compare_op1 = tmp;
3284 emit_insn (gen_bgt (operands[0]));
3287 from_compare (operands, GE);
3290 (define_expand "ble"
3292 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3293 (label_ref (match_operand 0 "" ""))
3300 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3302 rtx tmp = sh_compare_op0;
3303 sh_compare_op0 = sh_compare_op1;
3304 sh_compare_op1 = tmp;
3305 emit_insn (gen_bge (operands[0]));
3308 from_compare (operands, GT);
3311 (define_expand "bge"
3313 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3314 (label_ref (match_operand 0 "" ""))
3321 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3323 rtx tmp = sh_compare_op0;
3324 sh_compare_op0 = sh_compare_op1;
3325 sh_compare_op1 = tmp;
3326 emit_insn (gen_ble (operands[0]));
3329 from_compare (operands, GE);
3332 (define_expand "bgtu"
3334 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3335 (label_ref (match_operand 0 "" ""))
3338 "from_compare (operands, GTU); ")
3340 (define_expand "bltu"
3342 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3343 (label_ref (match_operand 0 "" ""))
3346 "from_compare (operands, GEU);")
3348 (define_expand "bgeu"
3350 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3351 (label_ref (match_operand 0 "" ""))
3354 "from_compare (operands, GEU);")
3356 (define_expand "bleu"
3358 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3359 (label_ref (match_operand 0 "" ""))
3362 "from_compare (operands, GTU);")
3364 ;; ------------------------------------------------------------------------
3365 ;; Jump and linkage insns
3366 ;; ------------------------------------------------------------------------
3370 (label_ref (match_operand 0 "" "")))]
3374 /* The length is 16 if the delay slot is unfilled. */
3375 if (get_attr_length(insn) > 4)
3376 return output_far_jump(insn, operands[0]);
3378 return \"bra %l0%#\";
3380 [(set_attr "type" "jump")
3381 (set_attr "needs_delay_slot" "yes")])
3383 (define_insn "calli"
3384 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3385 (match_operand 1 "" ""))
3386 (use (reg:PSI FPSCR_REG))
3387 (clobber (reg:SI PR_REG))]
3390 [(set_attr "type" "call")
3391 (set (attr "fp_mode")
3392 (if_then_else (eq_attr "fpu_single" "yes")
3393 (const_string "single") (const_string "double")))
3394 (set_attr "needs_delay_slot" "yes")])
3396 ;; This is a pc-rel call, using bsrf, for use with PIC.
3398 (define_insn "calli_pcrel"
3399 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3400 (match_operand 1 "" ""))
3401 (use (reg:PSI FPSCR_REG))
3402 (use (reg:SI PIC_REG))
3403 (use (match_operand 2 "" ""))
3404 (clobber (reg:SI PR_REG))]
3407 [(set_attr "type" "call")
3408 (set (attr "fp_mode")
3409 (if_then_else (eq_attr "fpu_single" "yes")
3410 (const_string "single") (const_string "double")))
3411 (set_attr "needs_delay_slot" "yes")])
3413 (define_insn_and_split "call_pcrel"
3414 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
3415 (match_operand 1 "" ""))
3416 (use (reg:PSI FPSCR_REG))
3417 (use (reg:SI PIC_REG))
3418 (clobber (reg:SI PR_REG))
3419 (clobber (match_scratch:SI 2 "=r"))]
3426 rtx lab = gen_call_site ();
3428 if (SYMBOL_REF_FLAG (operands[0]))
3429 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
3431 emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
3432 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], lab));
3435 [(set_attr "type" "call")
3436 (set (attr "fp_mode")
3437 (if_then_else (eq_attr "fpu_single" "yes")
3438 (const_string "single") (const_string "double")))
3439 (set_attr "needs_delay_slot" "yes")])
3441 (define_insn "call_valuei"
3442 [(set (match_operand 0 "" "=rf")
3443 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3444 (match_operand 2 "" "")))
3445 (use (reg:PSI FPSCR_REG))
3446 (clobber (reg:SI PR_REG))]
3449 [(set_attr "type" "call")
3450 (set (attr "fp_mode")
3451 (if_then_else (eq_attr "fpu_single" "yes")
3452 (const_string "single") (const_string "double")))
3453 (set_attr "needs_delay_slot" "yes")])
3455 (define_insn "call_valuei_pcrel"
3456 [(set (match_operand 0 "" "=rf")
3457 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3458 (match_operand 2 "" "")))
3459 (use (reg:PSI FPSCR_REG))
3460 (use (reg:SI PIC_REG))
3461 (use (match_operand 3 "" ""))
3462 (clobber (reg:SI PR_REG))]
3465 [(set_attr "type" "call")
3466 (set (attr "fp_mode")
3467 (if_then_else (eq_attr "fpu_single" "yes")
3468 (const_string "single") (const_string "double")))
3469 (set_attr "needs_delay_slot" "yes")])
3471 (define_insn_and_split "call_value_pcrel"
3472 [(set (match_operand 0 "" "=rf")
3473 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
3474 (match_operand 2 "" "")))
3475 (use (reg:PSI FPSCR_REG))
3476 (use (reg:SI PIC_REG))
3477 (clobber (reg:SI PR_REG))
3478 (clobber (match_scratch:SI 3 "=r"))]
3485 rtx lab = gen_call_site ();
3487 if (SYMBOL_REF_FLAG (operands[1]))
3488 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
3490 emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
3491 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
3495 [(set_attr "type" "call")
3496 (set (attr "fp_mode")
3497 (if_then_else (eq_attr "fpu_single" "yes")
3498 (const_string "single") (const_string "double")))
3499 (set_attr "needs_delay_slot" "yes")])
3501 (define_expand "call"
3502 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
3503 (match_operand 1 "" ""))
3504 (use (reg:PSI FPSCR_REG))
3505 (clobber (reg:SI PR_REG))])]
3509 if (flag_pic && TARGET_SH2
3510 && GET_CODE (operands[0]) == MEM
3511 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
3513 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
3517 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
3520 (define_expand "call_value"
3521 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
3522 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
3523 (match_operand 2 "" "")))
3524 (use (reg:PSI FPSCR_REG))
3525 (clobber (reg:SI PR_REG))])]
3529 if (flag_pic && TARGET_SH2
3530 && GET_CODE (operands[1]) == MEM
3531 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
3533 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
3538 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
3541 (define_insn "sibcalli"
3542 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
3543 (match_operand 1 "" ""))
3544 (use (reg:PSI FPSCR_REG))
3548 [(set_attr "needs_delay_slot" "yes")
3549 (set_attr "type" "jump_ind")])
3551 (define_insn "sibcalli_pcrel"
3552 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
3553 (match_operand 1 "" ""))
3554 (use (match_operand 2 "" ""))
3555 (use (reg:PSI FPSCR_REG))
3559 [(set_attr "needs_delay_slot" "yes")
3560 (set_attr "type" "jump_ind")])
3562 (define_insn_and_split "sibcall_pcrel"
3563 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
3564 (match_operand 1 "" ""))
3565 (use (reg:PSI FPSCR_REG))
3566 (clobber (match_scratch:SI 2 "=k"))
3574 rtx lab = gen_call_site ();
3577 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
3578 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
3580 SIBLING_CALL_P (call_insn) = 1;
3584 (define_expand "sibcall"
3586 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
3587 (match_operand 1 "" ""))
3588 (use (reg:PSI FPSCR_REG))
3593 if (flag_pic && TARGET_SH2
3594 && GET_CODE (operands[0]) == MEM
3595 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
3596 /* The PLT needs the PIC register, but the epilogue would have
3597 to restore it, so we can only use PC-relative PIC calls for
3598 static functions. */
3599 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
3601 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
3605 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
3608 (define_expand "sibcall_value"
3609 [(set (match_operand 0 "" "")
3610 (call (match_operand 1 "" "")
3611 (match_operand 2 "" "")))]
3615 emit_call_insn (gen_sibcall (operands[1], operands[2]));
3619 (define_expand "sibcall_epilogue"
3624 sh_expand_epilogue ();
3628 (define_insn "indirect_jump"
3630 (match_operand:SI 0 "arith_reg_operand" "r"))]
3633 [(set_attr "needs_delay_slot" "yes")
3634 (set_attr "type" "jump_ind")])
3636 ;; The use of operand 1 / 2 helps us distinguish case table jumps
3637 ;; which can be present in structured code from indirect jumps which can not
3638 ;; be present in structured code. This allows -fprofile-arcs to work.
3640 ;; For SH1 processors.
3641 (define_insn "casesi_jump_1"
3643 (match_operand:SI 0 "register_operand" "r"))
3644 (use (label_ref (match_operand 1 "" "")))]
3647 [(set_attr "needs_delay_slot" "yes")
3648 (set_attr "type" "jump_ind")])
3650 ;; For all later processors.
3651 (define_insn "casesi_jump_2"
3652 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
3653 (label_ref (match_operand 1 "" ""))))
3654 (use (label_ref (match_operand 2 "" "")))]
3655 "! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn"
3657 [(set_attr "needs_delay_slot" "yes")
3658 (set_attr "type" "jump_ind")])
3660 ;; Call subroutine returning any type.
3661 ;; ??? This probably doesn't work.
3663 (define_expand "untyped_call"
3664 [(parallel [(call (match_operand 0 "" "")
3666 (match_operand 1 "" "")
3667 (match_operand 2 "" "")])]
3673 emit_call_insn (gen_call (operands[0], const0_rtx));
3675 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3677 rtx set = XVECEXP (operands[2], 0, i);
3678 emit_move_insn (SET_DEST (set), SET_SRC (set));
3681 /* The optimizer does not know that the call sets the function value
3682 registers we stored in the result block. We avoid problems by
3683 claiming that all hard registers are used and clobbered at this
3685 emit_insn (gen_blockage ());
3690 ;; ------------------------------------------------------------------------
3692 ;; ------------------------------------------------------------------------
3695 [(set (reg:SI T_REG)
3696 (eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
3697 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
3700 [(set_attr "type" "arith")])
3707 ;; Load address of a label. This is only generated by the casesi expand,
3708 ;; and by machine_dependent_reorg (fixing up fp moves).
3709 ;; This must use unspec, because this only works for labels that are
3713 [(set (reg:SI R0_REG)
3714 (unspec [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
3717 [(set_attr "in_delay_slot" "no")
3718 (set_attr "type" "arith")])
3720 ;; machine_dependent_reorg() will make this a `mova'.
3721 (define_insn "mova_const"
3722 [(set (reg:SI R0_REG)
3723 (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
3726 [(set_attr "in_delay_slot" "no")
3727 (set_attr "type" "arith")])
3729 (define_expand "GOTaddr2picreg"
3730 [(set (reg:SI R0_REG)
3731 (unspec [(const (unspec [(match_dup 1)] UNSPEC_PIC))]
3733 (set (match_dup 0) (const (unspec [(match_dup 1)] UNSPEC_PIC)))
3734 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
3737 operands[0] = pic_offset_table_rtx;
3738 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
3742 (define_expand "call_site"
3743 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
3747 static HOST_WIDE_INT i = 0;
3748 operands[0] = GEN_INT (i);
3752 (define_expand "sym_label2reg"
3753 [(set (match_operand:SI 0 "" "")
3755 (const (unspec [(match_operand:SI 1 "" "")] UNSPEC_PIC))
3757 (match_operand:SI 2 "" "")
3761 (define_expand "symGOT2reg"
3762 [(set (match_operand:SI 0 "" "")
3763 (const (unspec [(match_operand:SI 1 "" "")] UNSPEC_GOT)))
3764 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
3765 (set (match_dup 0) (mem:SI (match_dup 0)))]
3769 operands[2] = pic_offset_table_rtx;
3772 (define_expand "symGOTOFF2reg"
3773 [(set (match_operand:SI 0 "" "")
3774 (const (unspec [(match_operand:SI 1 "" "")] UNSPEC_GOTOFF)))
3775 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3779 operands[2] = pic_offset_table_rtx;
3782 (define_expand "symPLT_label2reg"
3783 [(set (match_operand:SI 0 "" "")
3786 (unspec [(match_operand:SI 1 "" "")] UNSPEC_PLT)
3789 (match_operand:SI 2 "" "")
3791 ;; Even though the PIC register is not really used by the call
3792 ;; sequence in which this is expanded, the PLT code assumes the PIC
3793 ;; register is set, so we must not skip its initialization. Since
3794 ;; we only use this expand as part of calling sequences, and never
3795 ;; to take the address of a function, this is the best point to
3796 ;; insert the (use). Using the PLT to take the address of a
3797 ;; function would be wrong, not only because the PLT entry could
3798 ;; then be called from a function that doesn't initialize the PIC
3799 ;; register to the proper GOT, but also because pointers to the
3800 ;; same function might not compare equal, should they be set by
3801 ;; different shared libraries.
3802 (use (reg:SI PIC_REG))]
3806 ;; case instruction for switch statements.
3808 ;; Operand 0 is index
3809 ;; operand 1 is the minimum bound
3810 ;; operand 2 is the maximum bound - minimum bound + 1
3811 ;; operand 3 is CODE_LABEL for the table;
3812 ;; operand 4 is the CODE_LABEL to go to if index out of range.
3814 (define_expand "casesi"
3815 [(match_operand:SI 0 "arith_reg_operand" "")
3816 (match_operand:SI 1 "arith_reg_operand" "")
3817 (match_operand:SI 2 "arith_reg_operand" "")
3818 (match_operand 3 "" "") (match_operand 4 "" "")]
3822 rtx reg = gen_reg_rtx (SImode);
3823 rtx reg2 = gen_reg_rtx (SImode);
3824 operands[1] = copy_to_mode_reg (SImode, operands[1]);
3825 operands[2] = copy_to_mode_reg (SImode, operands[2]);
3826 /* If optimizing, casesi_worker depends on the mode of the instruction
3827 before label it 'uses' - operands[3]. */
3828 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
3830 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
3832 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
3834 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
3835 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
3836 operands[3], but to lab. We will fix this up in
3837 machine_dependent_reorg. */
3842 (define_expand "casesi_0"
3843 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
3844 (set (match_dup 4) (minus:SI (match_dup 4)
3845 (match_operand:SI 1 "arith_operand" "")))
3847 (gtu:SI (match_dup 4)
3848 (match_operand:SI 2 "arith_reg_operand" "")))
3850 (if_then_else (ne (reg:SI T_REG)
3852 (label_ref (match_operand 3 "" ""))
3857 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
3858 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
3859 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
3861 (define_insn "casesi_worker_0"
3862 [(set (match_operand:SI 0 "register_operand" "=r,r")
3863 (unspec [(match_operand 1 "register_operand" "0,r")
3864 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3865 (clobber (match_scratch:SI 3 "=X,1"))
3866 (clobber (match_scratch:SI 4 "=&z,z"))]
3871 [(set (match_operand:SI 0 "register_operand" "")
3872 (unspec [(match_operand 1 "register_operand" "")
3873 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3874 (clobber (match_scratch:SI 3 ""))
3875 (clobber (match_scratch:SI 4 ""))]
3876 "! TARGET_SH2 && reload_completed"
3877 [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] UNSPEC_MOVA))
3878 (parallel [(set (match_dup 0)
3879 (unspec [(reg:SI R0_REG) (match_dup 1)
3880 (label_ref (match_dup 2))] UNSPEC_CASESI))
3881 (clobber (match_dup 3))])
3882 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
3883 "LABEL_NUSES (operands[2])++;")
3886 [(set (match_operand:SI 0 "register_operand" "")
3887 (unspec [(match_operand 1 "register_operand" "")
3888 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3889 (clobber (match_scratch:SI 3 ""))
3890 (clobber (match_scratch:SI 4 ""))]
3891 "TARGET_SH2 && reload_completed"
3892 [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] UNSPEC_MOVA))
3893 (parallel [(set (match_dup 0)
3894 (unspec [(reg:SI R0_REG) (match_dup 1)
3895 (label_ref (match_dup 2))] UNSPEC_CASESI))
3896 (clobber (match_dup 3))])]
3897 "LABEL_NUSES (operands[2])++;")
3899 (define_insn "*casesi_worker"
3900 [(set (match_operand:SI 0 "register_operand" "=r,r")
3901 (unspec [(reg:SI R0_REG) (match_operand 1 "register_operand" "0,r")
3902 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3903 (clobber (match_scratch:SI 3 "=X,1"))]
3907 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
3909 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
3912 switch (GET_MODE (diff_vec))
3915 return \"shll2 %1\;mov.l @(r0,%1),%0\";
3917 return \"add %1,%1\;mov.w @(r0,%1),%0\";
3919 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
3920 return \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
3921 return \"mov.b @(r0,%1),%0\";
3926 [(set_attr "length" "4")])
3928 (define_expand "return"
3930 "reload_completed && ! sh_need_epilogue ()"
3933 (define_insn "*return_i"
3937 [(set_attr "type" "return")
3938 (set_attr "needs_delay_slot" "yes")])
3940 (define_expand "prologue"
3943 "sh_expand_prologue (); DONE;")
3945 (define_expand "epilogue"
3948 "sh_expand_epilogue ();")
3950 (define_insn "blockage"
3951 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
3954 [(set_attr "length" "0")])
3956 ;; ------------------------------------------------------------------------
3958 ;; ------------------------------------------------------------------------
3961 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3962 (eq:SI (reg:SI T_REG) (const_int 1)))]
3965 [(set_attr "type" "arith")])
3967 (define_expand "seq"
3968 [(set (match_operand:SI 0 "arith_reg_operand" "")
3971 "operands[1] = prepare_scc_operands (EQ);")
3973 (define_expand "slt"
3974 [(set (match_operand:SI 0 "arith_reg_operand" "")
3977 "operands[1] = prepare_scc_operands (LT);")
3979 (define_expand "sle"
3980 [(match_operand:SI 0 "arith_reg_operand" "")]
3984 rtx tmp = sh_compare_op0;
3985 sh_compare_op0 = sh_compare_op1;
3986 sh_compare_op1 = tmp;
3987 emit_insn (gen_sge (operands[0]));
3991 (define_expand "sgt"
3992 [(set (match_operand:SI 0 "arith_reg_operand" "")
3995 "operands[1] = prepare_scc_operands (GT);")
3997 (define_expand "sge"
3998 [(set (match_operand:SI 0 "arith_reg_operand" "")
4003 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
4007 rtx lab = gen_label_rtx ();
4008 prepare_scc_operands (EQ);
4009 emit_jump_insn (gen_branch_true (lab));
4010 prepare_scc_operands (GT);
4012 emit_insn (gen_movt (operands[0]));
4015 emit_insn (gen_movnegt (operands[0], prepare_scc_operands (LT)));
4018 operands[1] = prepare_scc_operands (GE);
4021 (define_expand "sgtu"
4022 [(set (match_operand:SI 0 "arith_reg_operand" "")
4025 "operands[1] = prepare_scc_operands (GTU);")
4027 (define_expand "sltu"
4028 [(set (match_operand:SI 0 "arith_reg_operand" "")
4031 "operands[1] = prepare_scc_operands (LTU);")
4033 (define_expand "sleu"
4034 [(set (match_operand:SI 0 "arith_reg_operand" "")
4037 "operands[1] = prepare_scc_operands (LEU);")
4039 (define_expand "sgeu"
4040 [(set (match_operand:SI 0 "arith_reg_operand" "")
4043 "operands[1] = prepare_scc_operands (GEU);")
4045 ;; sne moves the complement of the T reg to DEST like this:
4049 ;; This is better than xoring compare result with 1 because it does
4050 ;; not require r0 and further, the -1 may be CSE-ed or lifted out of a
4053 (define_expand "sne"
4054 [(set (match_dup 2) (const_int -1))
4055 (parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
4056 (neg:SI (plus:SI (match_dup 1)
4059 (ne:SI (ior:SI (match_dup 1) (match_dup 2))
4064 operands[1] = prepare_scc_operands (EQ);
4065 operands[2] = gen_reg_rtx (SImode);
4068 ;; Use the same trick for FP sle / sge
4069 (define_expand "movnegt"
4070 [(set (match_dup 2) (const_int -1))
4071 (parallel [(set (match_operand 0 "" "")
4072 (neg:SI (plus:SI (match_dup 1)
4075 (ne:SI (ior:SI (match_operand 1 "" "") (match_dup 2))
4078 "operands[2] = gen_reg_rtx (SImode);")
4080 ;; Recognize mov #-1/negc/neg sequence, and change it to movt/add #-1.
4081 ;; This prevents a regression that occurred when we switched from xor to
4085 [(set (match_operand:SI 0 "arith_reg_operand" "")
4086 (plus:SI (reg:SI T_REG)
4089 [(set (match_dup 0) (eq:SI (reg:SI T_REG) (const_int 1)))
4090 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
4093 ;; -------------------------------------------------------------------------
4094 ;; Instructions to cope with inline literal tables
4095 ;; -------------------------------------------------------------------------
4097 ; 2 byte integer in line
4099 (define_insn "consttable_2"
4100 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")]
4105 assemble_integer (operands[0], 2, 1);
4108 [(set_attr "length" "2")
4109 (set_attr "in_delay_slot" "no")])
4111 ; 4 byte integer in line
4113 (define_insn "consttable_4"
4114 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")]
4119 assemble_integer (operands[0], 4, 1);
4122 [(set_attr "length" "4")
4123 (set_attr "in_delay_slot" "no")])
4125 ; 8 byte integer in line
4127 (define_insn "consttable_8"
4128 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")]
4133 assemble_integer (operands[0], 8, 1);
4136 [(set_attr "length" "8")
4137 (set_attr "in_delay_slot" "no")])
4139 ; 4 byte floating point
4141 (define_insn "consttable_sf"
4142 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")]
4147 union real_extract u;
4148 memcpy (&u, &CONST_DOUBLE_LOW (operands[0]), sizeof u);
4149 assemble_real (u.d, SFmode);
4152 [(set_attr "length" "4")
4153 (set_attr "in_delay_slot" "no")])
4155 ; 8 byte floating point
4157 (define_insn "consttable_df"
4158 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")]
4163 union real_extract u;
4164 memcpy (&u, &CONST_DOUBLE_LOW (operands[0]), sizeof u);
4165 assemble_real (u.d, DFmode);
4168 [(set_attr "length" "8")
4169 (set_attr "in_delay_slot" "no")])
4171 ;; Alignment is needed for some constant tables; it may also be added for
4172 ;; Instructions at the start of loops, or after unconditional branches.
4173 ;; ??? We would get more accurate lengths if we did instruction
4174 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
4175 ;; here is too conservative.
4177 ; align to a two byte boundary
4179 (define_expand "align_2"
4180 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
4184 ; align to a four byte boundary
4185 ;; align_4 and align_log are instructions for the starts of loops, or
4186 ;; after unconditional branches, which may take up extra room.
4188 (define_expand "align_4"
4189 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
4193 ; align to a cache line boundary
4195 (define_insn "align_log"
4196 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
4199 [(set_attr "length" "0")
4200 (set_attr "in_delay_slot" "no")])
4202 ; emitted at the end of the literal table, used to emit the
4203 ; 32bit branch labels if needed.
4205 (define_insn "consttable_end"
4206 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
4208 "* return output_jump_label_table ();"
4209 [(set_attr "in_delay_slot" "no")])
4211 ;; -------------------------------------------------------------------------
4213 ;; -------------------------------------------------------------------------
4215 ;; String/block move insn.
4217 (define_expand "movstrsi"
4218 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
4219 (mem:BLK (match_operand:BLK 1 "" "")))
4220 (use (match_operand:SI 2 "nonmemory_operand" ""))
4221 (use (match_operand:SI 3 "immediate_operand" ""))
4222 (clobber (reg:SI PR_REG))
4223 (clobber (reg:SI R4_REG))
4224 (clobber (reg:SI R5_REG))
4225 (clobber (reg:SI R0_REG))])]
4229 if(expand_block_move (operands))
4234 (define_insn "block_move_real"
4235 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4236 (mem:BLK (reg:SI R5_REG)))
4237 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4238 (clobber (reg:SI PR_REG))
4239 (clobber (reg:SI R0_REG))])]
4242 [(set_attr "type" "sfunc")
4243 (set_attr "needs_delay_slot" "yes")])
4245 (define_insn "block_lump_real"
4246 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4247 (mem:BLK (reg:SI R5_REG)))
4248 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4249 (use (reg:SI R6_REG))
4250 (clobber (reg:SI PR_REG))
4251 (clobber (reg:SI T_REG))
4252 (clobber (reg:SI R4_REG))
4253 (clobber (reg:SI R5_REG))
4254 (clobber (reg:SI R6_REG))
4255 (clobber (reg:SI R0_REG))])]
4258 [(set_attr "type" "sfunc")
4259 (set_attr "needs_delay_slot" "yes")])
4261 (define_insn "block_move_real_i4"
4262 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4263 (mem:BLK (reg:SI R5_REG)))
4264 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4265 (clobber (reg:SI PR_REG))
4266 (clobber (reg:SI R0_REG))
4267 (clobber (reg:SI R1_REG))
4268 (clobber (reg:SI R2_REG))])]
4271 [(set_attr "type" "sfunc")
4272 (set_attr "needs_delay_slot" "yes")])
4274 (define_insn "block_lump_real_i4"
4275 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4276 (mem:BLK (reg:SI R5_REG)))
4277 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4278 (use (reg:SI R6_REG))
4279 (clobber (reg:SI PR_REG))
4280 (clobber (reg:SI T_REG))
4281 (clobber (reg:SI R4_REG))
4282 (clobber (reg:SI R5_REG))
4283 (clobber (reg:SI R6_REG))
4284 (clobber (reg:SI R0_REG))
4285 (clobber (reg:SI R1_REG))
4286 (clobber (reg:SI R2_REG))
4287 (clobber (reg:SI R3_REG))])]
4290 [(set_attr "type" "sfunc")
4291 (set_attr "needs_delay_slot" "yes")])
4293 ;; -------------------------------------------------------------------------
4294 ;; Floating point instructions.
4295 ;; -------------------------------------------------------------------------
4297 ;; ??? All patterns should have a type attribute.
4299 (define_expand "fpu_switch0"
4300 [(set (match_operand:SI 0 "" "") (match_dup 2))
4301 (set (match_dup 1) (mem:PSI (match_dup 0)))]
4305 operands[1] = get_fpscr_rtx ();
4306 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
4308 operands[2] = legitimize_pic_address (operands[2], SImode,
4309 no_new_pseudos ? operands[0] : 0);
4312 (define_expand "fpu_switch1"
4313 [(set (match_operand:SI 0 "" "") (match_dup 2))
4314 (set (match_dup 3) (plus:SI (match_dup 0) (const_int 4)))
4315 (set (match_dup 1) (mem:PSI (match_dup 3)))]
4319 operands[1] = get_fpscr_rtx ();
4320 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
4322 operands[2] = legitimize_pic_address (operands[2], SImode,
4323 no_new_pseudos ? operands[0] : 0);
4324 operands[3] = no_new_pseudos ? operands[0] : gen_reg_rtx (SImode);
4327 (define_expand "movpsi"
4328 [(set (match_operand:PSI 0 "register_operand" "")
4329 (match_operand:PSI 1 "general_movsrc_operand" ""))]
4333 ;; The c / m alternative is a fake to guide reload to load directly into
4334 ;; fpscr, since reload doesn't know how to use post-increment.
4335 ;; GO_IF_LEGITIMATE_ADDRESS guards about bogus addresses before reload,
4336 ;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
4337 ;; predicate after reload.
4338 ;; The gp_fpul type for r/!c might look a bit odd, but it actually schedules
4339 ;; like a gpr <-> fpul move.
4340 (define_insn "fpu_switch"
4341 [(set (match_operand:PSI 0 "register_operand" "=c,c,r,c,c,r,m,r")
4342 (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c"))]
4344 && (! reload_completed
4345 || true_regnum (operands[0]) != FPSCR_REG
4346 || GET_CODE (operands[1]) != MEM
4347 || GET_CODE (XEXP (operands[1], 0)) != PLUS)"
4349 ! precision stays the same
4357 [(set_attr "length" "0,2,2,4,2,2,2,2")
4358 (set_attr "type" "dfp_conv,dfp_conv,load,dfp_conv,dfp_conv,move,store,gp_fpul")])
4361 [(set (reg:PSI FPSCR_REG)
4362 (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
4363 "TARGET_SH4 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
4364 [(set (match_dup 0) (match_dup 0))]
4367 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
4368 gen_rtx (MEM, PSImode,
4369 gen_rtx (POST_INC, Pmode,
4371 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
4375 [(set (reg:PSI FPSCR_REG)
4376 (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
4378 [(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))]
4381 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
4382 gen_rtx (MEM, PSImode,
4383 gen_rtx (POST_INC, Pmode,
4385 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
4388 ;; ??? This uses the fp unit, but has no type indicating that.
4389 ;; If we did that, this would either give a bogus latency or introduce
4390 ;; a bogus FIFO constraint.
4391 ;; Since this insn is currently only used for prologues/epilogues,
4392 ;; it is probably best to claim no function unit, which matches the
4394 (define_insn "toggle_sz"
4395 [(set (reg:PSI FPSCR_REG)
4396 (xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
4400 (define_expand "addsf3"
4401 [(match_operand:SF 0 "arith_reg_operand" "")
4402 (match_operand:SF 1 "arith_reg_operand" "")
4403 (match_operand:SF 2 "arith_reg_operand" "")]
4405 "{ expand_sf_binop (&gen_addsf3_i, operands); DONE; }")
4407 (define_insn "addsf3_i"
4408 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4409 (plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
4410 (match_operand:SF 2 "arith_reg_operand" "f")))
4411 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4414 [(set_attr "type" "fp")
4415 (set_attr "fp_mode" "single")])
4417 (define_expand "subsf3"
4418 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4419 (match_operand:SF 1 "fp_arith_reg_operand" "")
4420 (match_operand:SF 2 "fp_arith_reg_operand" "")]
4422 "{ expand_sf_binop (&gen_subsf3_i, operands); DONE; }")
4424 (define_insn "subsf3_i"
4425 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4426 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
4427 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
4428 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4431 [(set_attr "type" "fp")
4432 (set_attr "fp_mode" "single")])
4434 ;; Unfortunately, the combiner is unable to cope with the USE of the FPSCR
4435 ;; register in feeding fp instructions. Thus, we cannot generate fmac for
4436 ;; mixed-precision SH4 targets. To allow it to be still generated for the
4437 ;; SH3E, we use a separate insn for SH3E mulsf3.
4439 (define_expand "mulsf3"
4440 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4441 (match_operand:SF 1 "fp_arith_reg_operand" "")
4442 (match_operand:SF 2 "fp_arith_reg_operand" "")]
4447 expand_sf_binop (&gen_mulsf3_i4, operands);
4449 emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
4453 (define_insn "mulsf3_i4"
4454 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4455 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
4456 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
4457 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4460 [(set_attr "type" "fp")
4461 (set_attr "fp_mode" "single")])
4463 (define_insn "mulsf3_ie"
4464 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4465 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
4466 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
4467 "TARGET_SH3E && ! TARGET_SH4"
4469 [(set_attr "type" "fp")])
4471 (define_insn "*macsf3"
4472 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4473 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
4474 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
4475 (match_operand:SF 3 "arith_reg_operand" "0")))
4476 (use (match_operand:PSI 4 "fpscr_operand" "c"))]
4477 "TARGET_SH3E && ! TARGET_SH4"
4479 [(set_attr "type" "fp")
4480 (set_attr "fp_mode" "single")])
4482 (define_expand "divsf3"
4483 [(match_operand:SF 0 "arith_reg_operand" "")
4484 (match_operand:SF 1 "arith_reg_operand" "")
4485 (match_operand:SF 2 "arith_reg_operand" "")]
4487 "{ expand_sf_binop (&gen_divsf3_i, operands); DONE; }")
4489 (define_insn "divsf3_i"
4490 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4491 (div:SF (match_operand:SF 1 "arith_reg_operand" "0")
4492 (match_operand:SF 2 "arith_reg_operand" "f")))
4493 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4496 [(set_attr "type" "fdiv")
4497 (set_attr "fp_mode" "single")])
4499 (define_expand "floatsisf2"
4500 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
4501 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
4507 emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4512 (define_insn "floatsisf2_i4"
4513 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4514 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
4515 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4518 [(set_attr "type" "fp")
4519 (set_attr "fp_mode" "single")])
4521 (define_insn "*floatsisf2_ie"
4522 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4523 (float:SF (match_operand:SI 1 "fpul_operand" "y")))]
4524 "TARGET_SH3E && ! TARGET_SH4"
4526 [(set_attr "type" "fp")])
4528 (define_expand "fix_truncsfsi2"
4529 [(set (match_operand:SI 0 "fpul_operand" "=y")
4530 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4536 emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4541 (define_insn "fix_truncsfsi2_i4"
4542 [(set (match_operand:SI 0 "fpul_operand" "=y")
4543 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4544 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4547 [(set_attr "type" "fp")
4548 (set_attr "fp_mode" "single")])
4550 ;; ??? This pattern is used nowhere. fix_truncsfsi2 always expands to
4551 ;; fix_truncsfsi2_i4.
4552 ;; (define_insn "fix_truncsfsi2_i4_2"
4553 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4554 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4555 ;; (use (reg:PSI FPSCR_REG))
4556 ;; (clobber (reg:SI FPUL_REG))]
4559 ;; [(set_attr "length" "4")
4560 ;; (set_attr "fp_mode" "single")])
4563 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4564 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4565 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4566 ;; (clobber (reg:SI FPUL_REG))]
4568 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
4569 ;; (use (match_dup 2))])
4570 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
4572 (define_insn "*fixsfsi"
4573 [(set (match_operand:SI 0 "fpul_operand" "=y")
4574 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4575 "TARGET_SH3E && ! TARGET_SH4"
4577 [(set_attr "type" "fp")])
4579 (define_insn "cmpgtsf_t"
4580 [(set (reg:SI T_REG)
4581 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4582 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4583 "TARGET_SH3E && ! TARGET_SH4"
4585 [(set_attr "type" "fp")
4586 (set_attr "fp_mode" "single")])
4588 (define_insn "cmpeqsf_t"
4589 [(set (reg:SI T_REG)
4590 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4591 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4592 "TARGET_SH3E && ! TARGET_SH4"
4594 [(set_attr "type" "fp")
4595 (set_attr "fp_mode" "single")])
4597 (define_insn "ieee_ccmpeqsf_t"
4598 [(set (reg:SI T_REG)
4599 (ior:SI (reg:SI T_REG)
4600 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4601 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
4602 "TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
4603 "* return output_ieee_ccmpeq (insn, operands);"
4604 [(set_attr "length" "4")])
4607 (define_insn "cmpgtsf_t_i4"
4608 [(set (reg:SI T_REG)
4609 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4610 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4611 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4614 [(set_attr "type" "fp")
4615 (set_attr "fp_mode" "single")])
4617 (define_insn "cmpeqsf_t_i4"
4618 [(set (reg:SI T_REG)
4619 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4620 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4621 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4624 [(set_attr "type" "fp")
4625 (set_attr "fp_mode" "single")])
4627 (define_insn "*ieee_ccmpeqsf_t_4"
4628 [(set (reg:SI T_REG)
4629 (ior:SI (reg:SI T_REG)
4630 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4631 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
4632 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4633 "TARGET_IEEE && TARGET_SH4"
4634 "* return output_ieee_ccmpeq (insn, operands);"
4635 [(set_attr "length" "4")
4636 (set_attr "fp_mode" "single")])
4638 (define_expand "cmpsf"
4639 [(set (reg:SI T_REG)
4640 (compare (match_operand:SF 0 "arith_operand" "")
4641 (match_operand:SF 1 "arith_operand" "")))]
4645 sh_compare_op0 = operands[0];
4646 sh_compare_op1 = operands[1];
4650 (define_expand "negsf2"
4651 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4652 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4654 "{ expand_sf_unop (&gen_negsf2_i, operands); DONE; }")
4656 (define_insn "negsf2_i"
4657 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4658 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4659 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4662 [(set_attr "type" "fmove")
4663 (set_attr "fp_mode" "single")])
4665 (define_expand "sqrtsf2"
4666 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4667 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4669 "{ expand_sf_unop (&gen_sqrtsf2_i, operands); DONE; }")
4671 (define_insn "sqrtsf2_i"
4672 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4673 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4674 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4677 [(set_attr "type" "fdiv")
4678 (set_attr "fp_mode" "single")])
4680 (define_expand "abssf2"
4681 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4682 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4684 "{ expand_sf_unop (&gen_abssf2_i, operands); DONE; }")
4686 (define_insn "abssf2_i"
4687 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4688 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4689 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4692 [(set_attr "type" "fmove")
4693 (set_attr "fp_mode" "single")])
4695 (define_expand "adddf3"
4696 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4697 (match_operand:DF 1 "fp_arith_reg_operand" "")
4698 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4700 "{ expand_df_binop (&gen_adddf3_i, operands); DONE; }")
4702 (define_insn "adddf3_i"
4703 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4704 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
4705 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4706 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4709 [(set_attr "type" "dfp_arith")
4710 (set_attr "fp_mode" "double")])
4712 (define_expand "subdf3"
4713 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4714 (match_operand:DF 1 "fp_arith_reg_operand" "")
4715 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4717 "{ expand_df_binop (&gen_subdf3_i, operands); DONE; }")
4719 (define_insn "subdf3_i"
4720 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4721 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
4722 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4723 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4726 [(set_attr "type" "dfp_arith")
4727 (set_attr "fp_mode" "double")])
4729 (define_expand "muldf3"
4730 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4731 (match_operand:DF 1 "fp_arith_reg_operand" "")
4732 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4734 "{ expand_df_binop (&gen_muldf3_i, operands); DONE; }")
4736 (define_insn "muldf3_i"
4737 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4738 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
4739 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4740 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4743 [(set_attr "type" "dfp_arith")
4744 (set_attr "fp_mode" "double")])
4746 (define_expand "divdf3"
4747 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4748 (match_operand:DF 1 "fp_arith_reg_operand" "")
4749 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4751 "{ expand_df_binop (&gen_divdf3_i, operands); DONE; }")
4753 (define_insn "divdf3_i"
4754 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4755 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
4756 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4757 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4760 [(set_attr "type" "dfdiv")
4761 (set_attr "fp_mode" "double")])
4763 (define_expand "floatsidf2"
4764 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4765 (match_operand:SI 1 "fpul_operand" "")]
4769 emit_df_insn (gen_floatsidf2_i (operands[0], operands[1], get_fpscr_rtx ()));
4773 (define_insn "floatsidf2_i"
4774 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4775 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
4776 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4779 [(set_attr "type" "dfp_conv")
4780 (set_attr "fp_mode" "double")])
4782 (define_expand "fix_truncdfsi2"
4783 [(match_operand:SI 0 "fpul_operand" "")
4784 (match_operand:DF 1 "fp_arith_reg_operand" "")]
4788 emit_df_insn (gen_fix_truncdfsi2_i (operands[0], operands[1], get_fpscr_rtx ()));
4792 (define_insn "fix_truncdfsi2_i"
4793 [(set (match_operand:SI 0 "fpul_operand" "=y")
4794 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
4795 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4798 [(set_attr "type" "dfp_conv")
4799 (set_attr "fp_mode" "double")])
4801 ;; ??? This pattern is used nowhere. fix_truncdfsi2 always expands to
4802 ;; fix_truncdfsi2_i.
4803 ;; (define_insn "fix_truncdfsi2_i4"
4804 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4805 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4806 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4807 ;; (clobber (reg:SI FPUL_REG))]
4810 ;; [(set_attr "length" "4")
4811 ;; (set_attr "fp_mode" "double")])
4814 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4815 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4816 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4817 ;; (clobber (reg:SI FPUL_REG))]
4819 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
4820 ;; (use (match_dup 2))])
4821 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
4823 (define_insn "cmpgtdf_t"
4824 [(set (reg:SI T_REG)
4825 (gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
4826 (match_operand:DF 1 "arith_reg_operand" "f")))
4827 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4830 [(set_attr "type" "dfp_cmp")
4831 (set_attr "fp_mode" "double")])
4833 (define_insn "cmpeqdf_t"
4834 [(set (reg:SI T_REG)
4835 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4836 (match_operand:DF 1 "arith_reg_operand" "f")))
4837 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4840 [(set_attr "type" "dfp_cmp")
4841 (set_attr "fp_mode" "double")])
4843 (define_insn "*ieee_ccmpeqdf_t"
4844 [(set (reg:SI T_REG)
4845 (ior:SI (reg:SI T_REG)
4846 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4847 (match_operand:DF 1 "arith_reg_operand" "f"))))
4848 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4849 "TARGET_IEEE && TARGET_SH4"
4850 "* return output_ieee_ccmpeq (insn, operands);"
4851 [(set_attr "length" "4")
4852 (set_attr "fp_mode" "double")])
4854 (define_expand "cmpdf"
4855 [(set (reg:SI T_REG)
4856 (compare (match_operand:DF 0 "arith_operand" "")
4857 (match_operand:DF 1 "arith_operand" "")))]
4861 sh_compare_op0 = operands[0];
4862 sh_compare_op1 = operands[1];
4866 (define_expand "negdf2"
4867 [(match_operand:DF 0 "arith_reg_operand" "")
4868 (match_operand:DF 1 "arith_reg_operand" "")]
4870 "{ expand_df_unop (&gen_negdf2_i, operands); DONE; }")
4872 (define_insn "negdf2_i"
4873 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4874 (neg:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4875 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4878 [(set_attr "type" "fmove")
4879 (set_attr "fp_mode" "double")])
4881 (define_expand "sqrtdf2"
4882 [(match_operand:DF 0 "arith_reg_operand" "")
4883 (match_operand:DF 1 "arith_reg_operand" "")]
4885 "{ expand_df_unop (&gen_sqrtdf2_i, operands); DONE; }")
4887 (define_insn "sqrtdf2_i"
4888 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4889 (sqrt:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4890 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4893 [(set_attr "type" "dfdiv")
4894 (set_attr "fp_mode" "double")])
4896 (define_expand "absdf2"
4897 [(match_operand:DF 0 "arith_reg_operand" "")
4898 (match_operand:DF 1 "arith_reg_operand" "")]
4900 "{ expand_df_unop (&gen_absdf2_i, operands); DONE; }")
4902 (define_insn "absdf2_i"
4903 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4904 (abs:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4905 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4908 [(set_attr "type" "fmove")
4909 (set_attr "fp_mode" "double")])
4911 (define_expand "extendsfdf2"
4912 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4913 (match_operand:SF 1 "fpul_operand" "")]
4917 emit_df_insn (gen_extendsfdf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4921 (define_insn "extendsfdf2_i4"
4922 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4923 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
4924 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4927 [(set_attr "type" "fp")
4928 (set_attr "fp_mode" "double")])
4930 (define_expand "truncdfsf2"
4931 [(match_operand:SF 0 "fpul_operand" "")
4932 (match_operand:DF 1 "fp_arith_reg_operand" "")]
4936 emit_df_insn (gen_truncdfsf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4940 (define_insn "truncdfsf2_i4"
4941 [(set (match_operand:SF 0 "fpul_operand" "=y")
4942 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
4943 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4946 [(set_attr "type" "fp")
4947 (set_attr "fp_mode" "double")])
4949 ;; Bit field extract patterns. These give better code for packed bitfields,
4950 ;; because they allow auto-increment addresses to be generated.
4952 (define_expand "insv"
4953 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
4954 (match_operand:SI 1 "immediate_operand" "")
4955 (match_operand:SI 2 "immediate_operand" ""))
4956 (match_operand:SI 3 "general_operand" ""))]
4957 "! TARGET_LITTLE_ENDIAN"
4960 rtx addr_target, orig_address, shift_reg;
4963 /* ??? expmed doesn't care for non-register predicates. */
4964 if (! memory_operand (operands[0], VOIDmode)
4965 || ! immediate_operand (operands[1], VOIDmode)
4966 || ! immediate_operand (operands[2], VOIDmode)
4967 || ! general_operand (operands[3], VOIDmode))
4969 /* If this isn't a 16 / 24 / 32 bit field, or if
4970 it doesn't start on a byte boundary, then fail. */
4971 size = INTVAL (operands[1]);
4972 if (size < 16 || size > 32 || size % 8 != 0
4973 || (INTVAL (operands[2]) % 8) != 0)
4977 orig_address = XEXP (operands[0], 0);
4978 shift_reg = gen_reg_rtx (SImode);
4979 emit_insn (gen_movsi (shift_reg, operands[3]));
4980 addr_target = copy_addr_to_reg (plus_constant (orig_address, size - 1));
4982 operands[0] = change_address (operands[0], QImode, addr_target);
4983 emit_insn (gen_movqi (operands[0], gen_rtx_SUBREG (QImode, shift_reg, 0)));
4987 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
4988 emit_insn (gen_addsi3 (addr_target, addr_target, GEN_INT (-1)));
4989 emit_insn (gen_movqi (operands[0],
4990 gen_rtx_SUBREG (QImode, shift_reg, 0)));
4996 ;; -------------------------------------------------------------------------
4998 ;; -------------------------------------------------------------------------
5000 ;; This matches cases where a stack pointer increment at the start of the
5001 ;; epilogue combines with a stack slot read loading the return value.
5004 [(set (match_operand:SI 0 "arith_reg_operand" "")
5005 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
5006 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
5007 "REGNO (operands[1]) != REGNO (operands[0])"
5010 ;; See the comment on the dt combiner pattern above.
5013 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
5014 (plus:SI (match_dup 0)
5017 (eq:SI (match_dup 0)
5022 ;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn'
5023 ;; to `mov #k,r0; mov.l @(r0,r15),rn'. These sequences are generated by
5024 ;; reload when the constant is too large for a reg+offset address.
5026 ;; ??? We would get much better code if this was done in reload. This would
5027 ;; require modifying find_reloads_address to recognize that if the constant
5028 ;; is out-of-range for an immediate add, then we get better code by reloading
5029 ;; the constant into a register than by reloading the sum into a register,
5030 ;; since the former is one instruction shorter if the address does not need
5031 ;; to be offsettable. Unfortunately this does not work, because there is
5032 ;; only one register, r0, that can be used as an index register. This register
5033 ;; is also the function return value register. So, if we try to force reload
5034 ;; to use double-reg addresses, then we end up with some instructions that
5035 ;; need to use r0 twice. The only way to fix this is to change the calling
5036 ;; convention so that r0 is not used to return values.
5039 [(set (match_operand:SI 0 "register_operand" "=r")
5040 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5041 (set (mem:SI (match_dup 0))
5042 (match_operand:SI 2 "general_movsrc_operand" ""))]
5043 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5044 "mov.l %2,@(%0,%1)")
5047 [(set (match_operand:SI 0 "register_operand" "=r")
5048 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5049 (set (match_operand:SI 2 "general_movdst_operand" "")
5050 (mem:SI (match_dup 0)))]
5051 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5052 "mov.l @(%0,%1),%2")
5055 [(set (match_operand:SI 0 "register_operand" "=r")
5056 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5057 (set (mem:HI (match_dup 0))
5058 (match_operand:HI 2 "general_movsrc_operand" ""))]
5059 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5060 "mov.w %2,@(%0,%1)")
5063 [(set (match_operand:SI 0 "register_operand" "=r")
5064 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5065 (set (match_operand:HI 2 "general_movdst_operand" "")
5066 (mem:HI (match_dup 0)))]
5067 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5068 "mov.w @(%0,%1),%2")
5071 [(set (match_operand:SI 0 "register_operand" "=r")
5072 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5073 (set (mem:QI (match_dup 0))
5074 (match_operand:QI 2 "general_movsrc_operand" ""))]
5075 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5076 "mov.b %2,@(%0,%1)")
5079 [(set (match_operand:SI 0 "register_operand" "=r")
5080 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5081 (set (match_operand:QI 2 "general_movdst_operand" "")
5082 (mem:QI (match_dup 0)))]
5083 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5084 "mov.b @(%0,%1),%2")
5087 [(set (match_operand:SI 0 "register_operand" "=r")
5088 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5089 (set (mem:SF (match_dup 0))
5090 (match_operand:SF 2 "general_movsrc_operand" ""))]
5091 "REGNO (operands[0]) == 0
5092 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
5093 || (GET_CODE (operands[2]) == SUBREG
5094 && REGNO (SUBREG_REG (operands[2])) < 16))
5095 && reg_unused_after (operands[0], insn)"
5096 "mov.l %2,@(%0,%1)")
5099 [(set (match_operand:SI 0 "register_operand" "=r")
5100 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5101 (set (match_operand:SF 2 "general_movdst_operand" "")
5103 (mem:SF (match_dup 0)))]
5104 "REGNO (operands[0]) == 0
5105 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
5106 || (GET_CODE (operands[2]) == SUBREG
5107 && REGNO (SUBREG_REG (operands[2])) < 16))
5108 && reg_unused_after (operands[0], insn)"
5109 "mov.l @(%0,%1),%2")
5112 [(set (match_operand:SI 0 "register_operand" "=r")
5113 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5114 (set (mem:SF (match_dup 0))
5115 (match_operand:SF 2 "general_movsrc_operand" ""))]
5116 "REGNO (operands[0]) == 0
5117 && ((GET_CODE (operands[2]) == REG
5118 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
5119 || (GET_CODE (operands[2]) == SUBREG
5120 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
5121 && reg_unused_after (operands[0], insn)"
5122 "fmov{.s|} %2,@(%0,%1)")
5125 [(set (match_operand:SI 0 "register_operand" "=r")
5126 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5127 (set (match_operand:SF 2 "general_movdst_operand" "")
5129 (mem:SF (match_dup 0)))]
5130 "REGNO (operands[0]) == 0
5131 && ((GET_CODE (operands[2]) == REG
5132 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
5133 || (GET_CODE (operands[2]) == SUBREG
5134 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
5135 && reg_unused_after (operands[0], insn)"
5136 "fmov{.s|} @(%0,%1),%2")
5138 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF). */
5139 (define_insn "sp_switch_1"
5146 xoperands[0] = sp_switch;
5147 output_asm_insn (\"mov.l r0,@-r15\;mov.l %0,r0\", xoperands);
5148 output_asm_insn (\"mov.l @r0,r0\;mov.l r15,@-r0\", xoperands);
5149 return \"mov r0,r15\";
5151 [(set_attr "length" "10")])
5153 ;; Switch back to the original stack for interrupt functions with the
5154 ;; sp_switch attribute. */
5155 (define_insn "sp_switch_2"
5158 "mov.l @r15+,r15\;mov.l @r15+,r0"
5159 [(set_attr "length" "4")])