1 ;;- Machine description for the Hitachi SH.
2 ;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
5 ;; Improved by Jim Wilson (wilson@cygnus.com).
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
25 ;; ??? Should prepend a * to all pattern names which are not used.
26 ;; This will make the compiler smaller, and rebuilds after changes faster.
28 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
29 ;; sequences. Especially the sequences for arithmetic right shifts.
31 ;; ??? Should check all DImode patterns for consistency and usefulness.
33 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
34 ;; way to generate them.
36 ;; ??? The cmp/str instruction is not supported. Perhaps it can be used
37 ;; for a str* inline function.
39 ;; BSR is not generated by the compiler proper, but when relaxing, it
40 ;; generates .uses pseudo-ops that allow linker relaxation to create
41 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
43 ;; Special constraints for SH machine description:
50 ;; Special formats used for outputting SH instructions:
52 ;; %. -- print a .s if insn needs delay slot
53 ;; %@ -- print rte/rts if is/isn't an interrupt function
54 ;; %# -- output a nop if there is nothing to put in the delay slot
55 ;; %O -- print a constant without the #
56 ;; %R -- print the lsw reg of a double
57 ;; %S -- print the msw reg of a double
58 ;; %T -- print next word of a double REG or MEM
60 ;; Special predicates:
62 ;; arith_operand -- operand is valid source for arithmetic op
63 ;; arith_reg_operand -- operand is valid register for arithmetic op
64 ;; general_movdst_operand -- operand is valid move destination
65 ;; general_movsrc_operand -- operand is valid move source
66 ;; logical_operand -- operand is valid source for logical op
67 ;; -------------------------------------------------------------------------
69 ;; -------------------------------------------------------------------------
74 "sh1,sh2,sh3,sh3e,sh4"
75 (const (symbol_ref "sh_cpu_attr")))
77 (define_attr "endian" "big,little"
78 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
79 (const_string "little") (const_string "big"))))
81 ;; Indicate if the default fpu mode is single precision.
82 (define_attr "fpu_single" "yes,no"
83 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
84 (const_string "yes") (const_string "no"))))
86 (define_attr "fmovd" "yes,no"
87 (const (if_then_else (symbol_ref "TARGET_FMOVD")
88 (const_string "yes") (const_string "no"))))
90 (define_attr "issues" "1,2"
91 (const (if_then_else (symbol_ref "TARGET_SUPERSCALAR") (const_string "2") (const_string "1"))))
93 ;; cbranch conditional branch instructions
94 ;; jump unconditional jumps
95 ;; arith ordinary arithmetic
96 ;; arith3 a compound insn that behaves similarly to a sequence of
97 ;; three insns of type arith
98 ;; arith3b like above, but might end with a redirected branch
100 ;; load_si Likewise, SImode variant for general register.
102 ;; move register to register
103 ;; fmove register to register, floating point
104 ;; smpy word precision integer multiply
105 ;; dmpy longword or doublelongword precision integer multiply
107 ;; pload load of pr reg, which can't be put into delay slot of rts
108 ;; pstore store of pr reg, which can't be put into delay slot of jsr
109 ;; pcload pc relative load of constant value
110 ;; pcload_si Likewise, SImode variant for general register.
111 ;; rte return from exception
112 ;; sfunc special function call with known used registers
113 ;; call function call
115 ;; fdiv floating point divide (or square root)
116 ;; gp_fpul move between general purpose register and fpul
117 ;; dfp_arith, dfp_cmp,dfp_conv
118 ;; dfdiv double precision floating point divide (or square root)
119 ;; nil no-op move, will be deleted.
122 "cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,other,load,load_si,store,move,fmove,smpy,dmpy,return,pload,pstore,pcload,pcload_si,rte,sfunc,call,fp,fdiv,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,nil"
123 (const_string "other"))
125 ;; Indicate what precision must be selected in fpscr for this insn, if any.
127 (define_attr "fp_mode" "single,double,none" (const_string "none"))
129 ; If a conditional branch destination is within -252..258 bytes away
130 ; from the instruction it can be 2 bytes long. Something in the
131 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
132 ; branches are initially assumed to be 16 bytes long.
133 ; In machine_dependent_reorg, we split all branches that are longer than
136 ;; The maximum range used for SImode constant pool entrys is 1018. A final
137 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
138 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
139 ;; instruction around the pool table, 2 bytes of alignment before the table,
140 ;; and 30 bytes of alignment after the table. That gives a maximum total
141 ;; pool size of 1058 bytes.
142 ;; Worst case code/pool content size ratio is 1:2 (using asms).
143 ;; Thus, in the worst case, there is one instruction in front of a maximum
144 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
145 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
146 ;; If we have a forward branch, the initial table will be put after the
147 ;; unconditional branch.
149 ;; ??? We could do much better by keeping track of the actual pcloads within
150 ;; the branch range and in the pcload range in front of the branch range.
152 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
154 (define_attr "short_cbranch_p" "no,yes"
155 (cond [(ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
157 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
159 (ne (symbol_ref "NEXT_INSN (PREV_INSN (insn)) != insn") (const_int 0))
161 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
163 ] (const_string "no")))
165 (define_attr "med_branch_p" "no,yes"
166 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
169 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
171 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
174 ] (const_string "no")))
176 (define_attr "med_cbranch_p" "no,yes"
177 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
180 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
182 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
185 ] (const_string "no")))
187 (define_attr "braf_branch_p" "no,yes"
188 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
190 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
193 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
195 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
198 ] (const_string "no")))
200 (define_attr "braf_cbranch_p" "no,yes"
201 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
203 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
206 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
208 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
211 ] (const_string "no")))
213 ; An unconditional jump in the range -4092..4098 can be 2 bytes long.
214 ; For wider ranges, we need a combination of a code and a data part.
215 ; If we can get a scratch register for a long range jump, the code
216 ; part can be 4 bytes long; otherwise, it must be 8 bytes long.
217 ; If the jump is in the range -32764..32770, the data part can be 2 bytes
218 ; long; otherwise, it must be 6 bytes long.
220 ; All other instructions are two bytes long by default.
222 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
223 ;; but getattrtab doesn't understand this.
224 (define_attr "length" ""
225 (cond [(eq_attr "type" "cbranch")
226 (cond [(eq_attr "short_cbranch_p" "yes")
228 (eq_attr "med_cbranch_p" "yes")
230 (eq_attr "braf_cbranch_p" "yes")
232 ;; ??? using pc is not computed transitively.
233 (ne (match_dup 0) (match_dup 0))
236 (eq_attr "type" "jump")
237 (cond [(eq_attr "med_branch_p" "yes")
239 (and (eq (symbol_ref "GET_CODE (PREV_INSN (insn))")
241 (eq (symbol_ref "INSN_CODE (PREV_INSN (insn))")
242 (symbol_ref "code_for_indirect_jump_scratch")))
243 (if_then_else (eq_attr "braf_branch_p" "yes")
246 (eq_attr "braf_branch_p" "yes")
248 ;; ??? using pc is not computed transitively.
249 (ne (match_dup 0) (match_dup 0))
254 ;; (define_function_unit {name} {num-units} {n-users} {test}
255 ;; {ready-delay} {issue-delay} [{conflict-list}])
257 ;; Load and store instructions save a cycle if they are aligned on a
258 ;; four byte boundary. Using a function unit for stores encourages
259 ;; gcc to separate load and store instructions by one instruction,
260 ;; which makes it more likely that the linker will be able to word
261 ;; align them when relaxing.
263 ;; Loads have a latency of two.
264 ;; However, call insns can have a delay slot, so that we want one more
265 ;; insn to be scheduled between the load of the function address and the call.
266 ;; This is equivalent to a latency of three.
267 ;; We cannot use a conflict list for this, because we need to distinguish
268 ;; between the actual call address and the function arguments.
269 ;; ADJUST_COST can only properly handle reductions of the cost, so we
270 ;; use a latency of three here.
271 ;; We only do this for SImode loads of general registers, to make the work
272 ;; for ADJUST_COST easier.
273 (define_function_unit "memory" 1 0
274 (and (eq_attr "issues" "1")
275 (eq_attr "type" "load_si,pcload_si"))
277 (define_function_unit "memory" 1 0
278 (and (eq_attr "issues" "1")
279 (eq_attr "type" "load,pcload,pload,store,pstore"))
282 (define_function_unit "int" 1 0
283 (and (eq_attr "issues" "1") (eq_attr "type" "arith3,arith3b")) 3 3)
285 (define_function_unit "int" 1 0
286 (and (eq_attr "issues" "1") (eq_attr "type" "dyn_shift")) 2 2)
288 (define_function_unit "int" 1 0
289 (and (eq_attr "issues" "1") (eq_attr "type" "!arith3,arith3b,dyn_shift")) 1 1)
291 ;; ??? These are approximations.
292 (define_function_unit "mpy" 1 0
293 (and (eq_attr "issues" "1") (eq_attr "type" "smpy")) 2 2)
294 (define_function_unit "mpy" 1 0
295 (and (eq_attr "issues" "1") (eq_attr "type" "dmpy")) 3 3)
297 (define_function_unit "fp" 1 0
298 (and (eq_attr "issues" "1") (eq_attr "type" "fp,fmove")) 2 1)
299 (define_function_unit "fp" 1 0
300 (and (eq_attr "issues" "1") (eq_attr "type" "fdiv")) 13 12)
304 ;; The SH4 is a dual-issue implementation, thus we have to multiply all
305 ;; costs by at least two.
306 ;; There will be single increments of the modeled that don't correspond
307 ;; to the actual target ;; whenever two insns to be issued depend one a
308 ;; single resource, and the scheduler picks to be the first one.
309 ;; If we multiplied the costs just by two, just two of these single
310 ;; increments would amount to an actual cycle. By picking a larger
311 ;; factor, we can ameliorate the effect; However, we then have to make sure
312 ;; that only two insns are modeled as issued per actual cycle.
313 ;; Moreover, we need a way to specify the latency of insns that don't
314 ;; use an actual function unit.
315 ;; We use an 'issue' function unit to do that, and a cost factor of 10.
317 (define_function_unit "issue" 2 0
318 (and (eq_attr "issues" "2") (eq_attr "type" "!nil,arith3"))
321 (define_function_unit "issue" 2 0
322 (and (eq_attr "issues" "2") (eq_attr "type" "arith3"))
325 ;; There is no point in providing exact scheduling information about branches,
326 ;; because they are at the starts / ends of basic blocks anyways.
328 ;; Some insns cannot be issued before/after another insn in the same cycle,
329 ;; irrespective of the type of the other insn.
331 ;; default is dual-issue, but can't be paired with an insn that
332 ;; uses multiple function units.
333 (define_function_unit "single_issue" 1 0
334 (and (eq_attr "issues" "2")
335 (eq_attr "type" "!smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul,call,sfunc,arith3,arith3b"))
337 [(eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul")])
339 (define_function_unit "single_issue" 1 0
340 (and (eq_attr "issues" "2")
341 (eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul"))
345 ;; arith3 insns are always pairable at the start, but not inecessarily at
346 ;; the end; however, there doesn;t seem to be a way to express that.
347 (define_function_unit "single_issue" 1 0
348 (and (eq_attr "issues" "2")
349 (eq_attr "type" "arith3"))
353 ;; arith3b insn are pairable at the end and have latency that prevents pairing
354 ;; with the following branch, but we don't want this latency be respected;
355 ;; When the following branch is immediately adjacent, we can redirect the
356 ;; internal branch, which is likly to be a larger win.
357 (define_function_unit "single_issue" 1 0
358 (and (eq_attr "issues" "2")
359 (eq_attr "type" "arith3b"))
363 ;; calls introduce a longisch delay that is likely to flush the pipelines.
364 (define_function_unit "single_issue" 1 0
365 (and (eq_attr "issues" "2")
366 (eq_attr "type" "call,sfunc"))
368 [(eq_attr "type" "!call") (eq_attr "type" "call")])
370 ;; Load and store instructions have no alignment peculiarities for the SH4,
371 ;; but they use the load-store unit, which they share with the fmove type
372 ;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
373 ;; Loads have a latency of two.
374 ;; However, call insns can only paired with a preceding insn, and have
375 ;; a delay slot, so that we want two more insns to be scheduled between the
376 ;; load of the function address and the call. This is equivalent to a
378 ;; We cannot use a conflict list for this, because we need to distinguish
379 ;; between the actual call address and the function arguments.
380 ;; ADJUST_COST can only properly handle reductions of the cost, so we
381 ;; use a latency of three here, which gets multiplied by 10 to yield 30.
382 ;; We only do this for SImode loads of general registers, to make the work
383 ;; for ADJUST_COST easier.
385 ;; When specifying different latencies for different insns using the
386 ;; the same function unit, genattrtab.c assumes a 'FIFO constraint'
387 ;; so that the blockage is at least READY-COST (E) + 1 - READY-COST (C)
388 ;; for an executing insn E and a candidate insn C.
389 ;; Therefore, we define three different function units for load_store:
390 ;; load_store, load and load_si.
392 (define_function_unit "load_si" 1 0
393 (and (eq_attr "issues" "2")
394 (eq_attr "type" "load_si,pcload_si")) 30 10)
395 (define_function_unit "load" 1 0
396 (and (eq_attr "issues" "2")
397 (eq_attr "type" "load,pcload,pload")) 20 10)
398 (define_function_unit "load_store" 1 0
399 (and (eq_attr "issues" "2")
400 (eq_attr "type" "load_si,pcload_si,load,pcload,pload,store,pstore,fmove"))
403 (define_function_unit "int" 1 0
404 (and (eq_attr "issues" "2") (eq_attr "type" "arith,dyn_shift")) 10 10)
406 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
407 ;; spurious FIFO constraint; the multiply instructions use the "int"
408 ;; unit actually only for two cycles.
409 (define_function_unit "int" 1 0
410 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 20 20)
412 ;; We use a fictous "mpy" unit to express the actual latency.
413 (define_function_unit "mpy" 1 0
414 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 20)
416 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
417 ;; spurious FIFO constraint.
418 (define_function_unit "int" 1 0
419 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 10 10)
421 ;; We use a fictous "gp_fpul" unit to express the actual latency.
422 (define_function_unit "gp_fpul" 1 0
423 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 20 10)
425 ;; ??? multiply uses the floating point unit, but with a two cycle delay.
426 ;; Thus, a simple single-precision fp operation could finish if issued in
427 ;; the very next cycle, but stalls when issued two or three cycles later.
428 ;; Similarily, a divide / sqrt can work without stalls if issued in
429 ;; the very next cycle, while it would have to block if issued two or
430 ;; three cycles later.
431 ;; There is no way to model this with gcc's function units. This problem is
432 ;; actually mentioned in md.texi. Tackling this problem requires first that
433 ;; it is possible to speak about the target in an open discussion.
435 ;; However, simple double-precision operations always conflict.
437 (define_function_unit "fp" 1 0
438 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 40
439 [(eq_attr "type" "dfp_cmp,dfp_conv,dfp_arith")])
441 ;; The "fp" unit is for pipeline stages F1 and F2.
443 (define_function_unit "fp" 1 0
444 (and (eq_attr "issues" "2") (eq_attr "type" "fp")) 30 10)
446 ;; Again, we have to pretend a lower latency for the "fp" unit to avoid a
447 ;; spurious FIFO constraint; the bulk of the fdiv type insns executes in
449 (define_function_unit "fp" 1 0
450 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 30 10)
452 ;; The "fdiv" function unit models the aggregate effect of the F1, F2 and F3
453 ;; pipeline stages on the pipelining of fdiv/fsqrt insns.
454 ;; We also use it to give the actual latency here.
455 ;; fsqrt is actually one cycle faster than fdiv (and the value used here),
456 ;; but that will hardly matter in practice for scheduling.
457 (define_function_unit "fdiv" 1 0
458 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 120 100)
460 ;; There is again a late use of the "fp" unit by [d]fdiv type insns
461 ;; that we can't express.
463 (define_function_unit "fp" 1 0
464 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_cmp,dfp_conv")) 40 20)
466 (define_function_unit "fp" 1 0
467 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_arith")) 80 60)
469 (define_function_unit "fp" 1 0
470 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 10)
472 (define_function_unit "fdiv" 1 0
473 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 210)
475 ; Definitions for filling branch delay slots.
477 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
479 ;; ??? This should be (nil) instead of (const_int 0)
480 (define_attr "hit_stack" "yes,no"
481 (cond [(eq (symbol_ref "find_regno_note (insn, REG_INC, 15)") (const_int 0))
483 (const_string "yes")))
485 (define_attr "interrupt_function" "no,yes"
486 (const (symbol_ref "pragma_interrupt")))
488 (define_attr "in_delay_slot" "yes,no"
489 (cond [(eq_attr "type" "cbranch") (const_string "no")
490 (eq_attr "type" "pcload,pcload_si") (const_string "no")
491 (eq_attr "needs_delay_slot" "yes") (const_string "no")
492 (eq_attr "length" "2") (const_string "yes")
493 ] (const_string "no")))
495 (define_attr "is_sfunc" ""
496 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
499 (eq_attr "needs_delay_slot" "yes")
500 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
502 ;; On the SH and SH2, the rte instruction reads the return pc from the stack,
503 ;; and thus we can't put a pop instruction in its delay slot.
504 ;; ??? On the SH3, the rte instruction does not use the stack, so a pop
505 ;; instruction can go in the delay slot.
507 ;; Since a normal return (rts) implicitly uses the PR register,
508 ;; we can't allow PR register loads in an rts delay slot.
511 (eq_attr "type" "return")
512 [(and (eq_attr "in_delay_slot" "yes")
513 (ior (and (eq_attr "interrupt_function" "no")
514 (eq_attr "type" "!pload"))
515 (and (eq_attr "interrupt_function" "yes")
516 (eq_attr "hit_stack" "no")))) (nil) (nil)])
518 ;; Since a call implicitly uses the PR register, we can't allow
519 ;; a PR register store in a jsr delay slot.
522 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
523 [(and (eq_attr "in_delay_slot" "yes")
524 (eq_attr "type" "!pstore")) (nil) (nil)])
526 ;; Say that we have annulled true branches, since this gives smaller and
527 ;; faster code when branches are predicted as not taken.
530 (and (eq_attr "type" "cbranch")
531 (ne (symbol_ref "TARGET_SH2") (const_int 0)))
532 [(eq_attr "in_delay_slot" "yes") (eq_attr "in_delay_slot" "yes") (nil)])
534 ;; -------------------------------------------------------------------------
535 ;; SImode signed integer comparisons
536 ;; -------------------------------------------------------------------------
540 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
541 (match_operand:SI 1 "arith_operand" "L,r"))
546 ;; ??? Perhaps should only accept reg/constant if the register is reg 0.
547 ;; That would still allow reload to create cmpi instructions, but would
548 ;; perhaps allow forcing the constant into a register when that is better.
549 ;; Probably should use r0 for mem/imm compares, but force constant into a
550 ;; register for pseudo/imm compares.
552 (define_insn "cmpeqsi_t"
553 [(set (reg:SI 18) (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
554 (match_operand:SI 1 "arith_operand" "N,rI,r")))]
561 (define_insn "cmpgtsi_t"
562 [(set (reg:SI 18) (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
563 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
569 (define_insn "cmpgesi_t"
570 [(set (reg:SI 18) (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
571 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
577 ;; -------------------------------------------------------------------------
578 ;; SImode unsigned integer comparisons
579 ;; -------------------------------------------------------------------------
581 (define_insn "cmpgeusi_t"
582 [(set (reg:SI 18) (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
583 (match_operand:SI 1 "arith_reg_operand" "r")))]
587 (define_insn "cmpgtusi_t"
588 [(set (reg:SI 18) (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
589 (match_operand:SI 1 "arith_reg_operand" "r")))]
593 ;; We save the compare operands in the cmpxx patterns and use them when
594 ;; we generate the branch.
596 (define_expand "cmpsi"
597 [(set (reg:SI 18) (compare (match_operand:SI 0 "arith_operand" "")
598 (match_operand:SI 1 "arith_operand" "")))]
602 sh_compare_op0 = operands[0];
603 sh_compare_op1 = operands[1];
607 ;; -------------------------------------------------------------------------
608 ;; DImode signed integer comparisons
609 ;; -------------------------------------------------------------------------
611 ;; ??? Could get better scheduling by splitting the initial test from the
612 ;; rest of the insn after reload. However, the gain would hardly justify
613 ;; the sh.md size increase necessary to do that.
617 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
618 (match_operand:DI 1 "arith_operand" "r"))
621 "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
623 [(set_attr "length" "6")
624 (set_attr "type" "arith3b")])
626 (define_insn "cmpeqdi_t"
627 [(set (reg:SI 18) (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
628 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
631 tst %S0,%S0\;bf %,Ldi%=\;tst %R0,%R0\\n%,Ldi%=:
632 cmp/eq %S1,%S0\;bf %,Ldi%=\;cmp/eq %R1,%R0\\n%,Ldi%=:"
633 [(set_attr "length" "6")
634 (set_attr "type" "arith3b")])
637 [(set (reg:SI 18) (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
638 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
639 ;; If we applied this split when not optimizing, it would only be
640 ;; applied during the machine-dependent reorg, when no new basic blocks
642 "reload_completed && optimize"
643 [(set (reg:SI 18) (eq:SI (match_dup 2) (match_dup 3)))
644 (set (pc) (if_then_else (eq (reg:SI 18) (const_int 0))
645 (label_ref (match_dup 6))
647 (set (reg:SI 18) (eq:SI (match_dup 4) (match_dup 5)))
652 = gen_rtx_REG (SImode,
653 true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
655 = (operands[1] == const0_rtx
657 : gen_rtx_REG (SImode,
658 true_regnum (operands[1])
659 + (TARGET_LITTLE_ENDIAN ? 1 : 0)));
660 operands[4] = gen_lowpart (SImode, operands[0]);
661 operands[5] = gen_lowpart (SImode, operands[1]);
662 operands[6] = gen_label_rtx ();
665 (define_insn "cmpgtdi_t"
666 [(set (reg:SI 18) (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
667 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
670 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
671 tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
672 [(set_attr "length" "8")
673 (set_attr "type" "arith3")])
675 (define_insn "cmpgedi_t"
676 [(set (reg:SI 18) (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
677 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
680 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
682 [(set_attr "length" "8,2")
683 (set_attr "type" "arith3,arith")])
685 ;; -------------------------------------------------------------------------
686 ;; DImode unsigned integer comparisons
687 ;; -------------------------------------------------------------------------
689 (define_insn "cmpgeudi_t"
690 [(set (reg:SI 18) (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
691 (match_operand:DI 1 "arith_reg_operand" "r")))]
693 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
694 [(set_attr "length" "8")
695 (set_attr "type" "arith3")])
697 (define_insn "cmpgtudi_t"
698 [(set (reg:SI 18) (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
699 (match_operand:DI 1 "arith_reg_operand" "r")))]
701 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
702 [(set_attr "length" "8")
703 (set_attr "type" "arith3")])
705 ;; We save the compare operands in the cmpxx patterns and use them when
706 ;; we generate the branch.
708 (define_expand "cmpdi"
709 [(set (reg:SI 18) (compare (match_operand:DI 0 "arith_operand" "")
710 (match_operand:DI 1 "arith_operand" "")))]
714 sh_compare_op0 = operands[0];
715 sh_compare_op1 = operands[1];
719 ;; -------------------------------------------------------------------------
720 ;; Addition instructions
721 ;; -------------------------------------------------------------------------
723 ;; ??? This should be a define expand.
725 (define_insn "adddi3"
726 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
727 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
728 (match_operand:DI 2 "arith_reg_operand" "r")))
729 (clobber (reg:SI 18))]
732 [(set_attr "length" "6")])
735 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
736 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
737 (match_operand:DI 2 "arith_reg_operand" "r")))
738 (clobber (reg:SI 18))]
743 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
744 high0 = gen_rtx_REG (SImode,
745 true_regnum (operands[0])
746 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
747 high2 = gen_rtx_REG (SImode,
748 true_regnum (operands[2])
749 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
750 emit_insn (gen_clrt ());
751 emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
752 emit_insn (gen_addc1 (high0, high0, high2));
757 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
758 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
759 (match_operand:SI 2 "arith_reg_operand" "r"))
762 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
765 [(set_attr "type" "arith")])
768 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
769 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
770 (match_operand:SI 2 "arith_reg_operand" "r"))
772 (clobber (reg:SI 18))]
775 [(set_attr "type" "arith")])
777 (define_insn "addsi3"
778 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
779 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
780 (match_operand:SI 2 "arith_operand" "rI")))]
783 [(set_attr "type" "arith")])
785 ;; -------------------------------------------------------------------------
786 ;; Subtraction instructions
787 ;; -------------------------------------------------------------------------
789 ;; ??? This should be a define expand.
791 (define_insn "subdi3"
792 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
793 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
794 (match_operand:DI 2 "arith_reg_operand" "r")))
795 (clobber (reg:SI 18))]
798 [(set_attr "length" "6")])
801 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
802 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
803 (match_operand:DI 2 "arith_reg_operand" "r")))
804 (clobber (reg:SI 18))]
809 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
810 high0 = gen_rtx_REG (SImode,
811 true_regnum (operands[0])
812 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
813 high2 = gen_rtx_REG (SImode,
814 true_regnum (operands[2])
815 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
816 emit_insn (gen_clrt ());
817 emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
818 emit_insn (gen_subc1 (high0, high0, high2));
823 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
824 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
825 (match_operand:SI 2 "arith_reg_operand" "r"))
828 (gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
831 [(set_attr "type" "arith")])
834 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
835 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
836 (match_operand:SI 2 "arith_reg_operand" "r"))
838 (clobber (reg:SI 18))]
841 [(set_attr "type" "arith")])
843 (define_insn "*subsi3_internal"
844 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
845 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
846 (match_operand:SI 2 "arith_reg_operand" "r")))]
849 [(set_attr "type" "arith")])
851 ;; Convert `constant - reg' to `neg rX; add rX, #const' since this
852 ;; will sometimes save one instruction. Otherwise we might get
853 ;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
856 (define_expand "subsi3"
857 [(set (match_operand:SI 0 "arith_reg_operand" "")
858 (minus:SI (match_operand:SI 1 "arith_operand" "")
859 (match_operand:SI 2 "arith_reg_operand" "")))]
863 if (GET_CODE (operands[1]) == CONST_INT)
865 emit_insn (gen_negsi2 (operands[0], operands[2]));
866 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
871 ;; -------------------------------------------------------------------------
872 ;; Division instructions
873 ;; -------------------------------------------------------------------------
875 ;; We take advantage of the library routines which don't clobber as many
876 ;; registers as a normal function call would.
878 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
879 ;; also has an effect on the register that holds the address of the sfunc.
880 ;; To make this work, we have an extra dummy insns that shows the use
881 ;; of this register for reorg.
883 (define_insn "use_sfunc_addr"
884 [(set (reg:SI 17) (unspec [(match_operand:SI 0 "register_operand" "r")] 5))]
887 [(set_attr "length" "0")])
889 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
890 ;; hard register 0. If we used hard register 0, then the next instruction
891 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
892 ;; gets allocated to a stack slot that needs its address reloaded, then
893 ;; there is nothing to prevent reload from using r0 to reload the address.
894 ;; This reload would clobber the value in r0 we are trying to store.
895 ;; If we let reload allocate r0, then this problem can never happen.
897 (define_insn "udivsi3_i1"
898 [(set (match_operand:SI 0 "register_operand" "=z")
899 (udiv:SI (reg:SI 4) (reg:SI 5)))
900 (clobber (reg:SI 18))
901 (clobber (reg:SI 17))
903 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
906 [(set_attr "type" "sfunc")
907 (set_attr "needs_delay_slot" "yes")])
909 (define_insn "udivsi3_i4"
910 [(set (match_operand:SI 0 "register_operand" "=y")
911 (udiv:SI (reg:SI 4) (reg:SI 5)))
912 (clobber (reg:SI 17))
913 (clobber (reg:DF 24))
914 (clobber (reg:DF 26))
915 (clobber (reg:DF 28))
921 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
922 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
924 [(set_attr "type" "sfunc")
925 (set_attr "fp_mode" "double")
926 (set_attr "needs_delay_slot" "yes")])
928 (define_insn "udivsi3_i4_single"
929 [(set (match_operand:SI 0 "register_operand" "=y")
930 (udiv:SI (reg:SI 4) (reg:SI 5)))
931 (clobber (reg:SI 17))
932 (clobber (reg:DF 24))
933 (clobber (reg:DF 26))
934 (clobber (reg:DF 28))
939 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
940 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
942 [(set_attr "type" "sfunc")
943 (set_attr "needs_delay_slot" "yes")])
945 (define_expand "udivsi3"
946 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
947 (set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
948 (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
949 (parallel [(set (match_operand:SI 0 "register_operand" "")
952 (clobber (reg:SI 18))
953 (clobber (reg:SI 17))
955 (use (match_dup 3))])]
961 operands[3] = gen_reg_rtx(SImode);
962 /* Emit the move of the address to a pseudo outside of the libcall. */
963 if (TARGET_HARD_SH4 && TARGET_SH3E)
965 emit_move_insn (operands[3],
966 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
967 if (TARGET_FPU_SINGLE)
968 last = gen_udivsi3_i4_single (operands[0], operands[3]);
970 last = gen_udivsi3_i4 (operands[0], operands[3]);
974 emit_move_insn (operands[3],
975 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3\"));
976 last = gen_udivsi3_i1 (operands[0], operands[3]);
978 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
979 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
980 last = emit_insn (last);
981 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
982 invariant code motion can move it. */
983 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
984 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
988 (define_insn "divsi3_i1"
989 [(set (match_operand:SI 0 "register_operand" "=z")
990 (div:SI (reg:SI 4) (reg:SI 5)))
991 (clobber (reg:SI 18))
992 (clobber (reg:SI 17))
996 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
999 [(set_attr "type" "sfunc")
1000 (set_attr "needs_delay_slot" "yes")])
1002 (define_insn "divsi3_i4"
1003 [(set (match_operand:SI 0 "register_operand" "=y")
1004 (div:SI (reg:SI 4) (reg:SI 5)))
1005 (clobber (reg:SI 17))
1006 (clobber (reg:DF 24))
1007 (clobber (reg:DF 26))
1009 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1010 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1012 [(set_attr "type" "sfunc")
1013 (set_attr "fp_mode" "double")
1014 (set_attr "needs_delay_slot" "yes")])
1016 (define_insn "divsi3_i4_single"
1017 [(set (match_operand:SI 0 "register_operand" "=y")
1018 (div:SI (reg:SI 4) (reg:SI 5)))
1019 (clobber (reg:SI 17))
1020 (clobber (reg:DF 24))
1021 (clobber (reg:DF 26))
1022 (clobber (reg:SI 2))
1023 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1024 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
1026 [(set_attr "type" "sfunc")
1027 (set_attr "needs_delay_slot" "yes")])
1029 (define_expand "divsi3"
1030 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
1031 (set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
1032 (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
1033 (parallel [(set (match_operand:SI 0 "register_operand" "")
1036 (clobber (reg:SI 18))
1037 (clobber (reg:SI 17))
1038 (clobber (reg:SI 1))
1039 (clobber (reg:SI 2))
1040 (clobber (reg:SI 3))
1041 (use (match_dup 3))])]
1047 operands[3] = gen_reg_rtx(SImode);
1048 /* Emit the move of the address to a pseudo outside of the libcall. */
1049 if (TARGET_HARD_SH4 && TARGET_SH3E)
1051 emit_move_insn (operands[3],
1052 gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
1053 if (TARGET_FPU_SINGLE)
1054 last = gen_divsi3_i4_single (operands[0], operands[3]);
1056 last = gen_divsi3_i4 (operands[0], operands[3]);
1060 emit_move_insn (operands[3], gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3\"));
1061 last = gen_divsi3_i1 (operands[0], operands[3]);
1063 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1064 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1065 last = emit_insn (last);
1066 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1067 invariant code motion can move it. */
1068 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1069 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1073 ;; -------------------------------------------------------------------------
1074 ;; Multiplication instructions
1075 ;; -------------------------------------------------------------------------
1077 (define_insn "umulhisi3_i"
1079 (mult:SI (zero_extend:SI (match_operand:HI 0 "arith_reg_operand" "r"))
1080 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r"))))]
1083 [(set_attr "type" "smpy")])
1085 (define_insn "mulhisi3_i"
1087 (mult:SI (sign_extend:SI
1088 (match_operand:HI 0 "arith_reg_operand" "r"))
1090 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1093 [(set_attr "type" "smpy")])
1095 (define_expand "mulhisi3"
1097 (mult:SI (sign_extend:SI
1098 (match_operand:HI 1 "arith_reg_operand" ""))
1100 (match_operand:HI 2 "arith_reg_operand" ""))))
1101 (set (match_operand:SI 0 "arith_reg_operand" "")
1108 first = emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
1109 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 21));
1110 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1111 invariant code motion can move it. */
1112 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1113 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1117 (define_expand "umulhisi3"
1119 (mult:SI (zero_extend:SI
1120 (match_operand:HI 1 "arith_reg_operand" ""))
1122 (match_operand:HI 2 "arith_reg_operand" ""))))
1123 (set (match_operand:SI 0 "arith_reg_operand" "")
1130 first = emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
1131 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 21));
1132 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1133 invariant code motion can move it. */
1134 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1135 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1139 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
1140 ;; a call to a routine which clobbers known registers.
1143 [(set (match_operand:SI 1 "register_operand" "=z")
1144 (mult:SI (reg:SI 4) (reg:SI 5)))
1145 (clobber (reg:SI 21))
1146 (clobber (reg:SI 18))
1147 (clobber (reg:SI 17))
1148 (clobber (reg:SI 3))
1149 (clobber (reg:SI 2))
1150 (clobber (reg:SI 1))
1151 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
1154 [(set_attr "type" "sfunc")
1155 (set_attr "needs_delay_slot" "yes")])
1157 (define_expand "mulsi3_call"
1158 [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
1159 (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
1160 (parallel[(set (match_operand:SI 0 "register_operand" "")
1163 (clobber (reg:SI 21))
1164 (clobber (reg:SI 18))
1165 (clobber (reg:SI 17))
1166 (clobber (reg:SI 3))
1167 (clobber (reg:SI 2))
1168 (clobber (reg:SI 1))
1169 (use (match_operand:SI 3 "register_operand" ""))])]
1173 (define_insn "mul_l"
1175 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
1176 (match_operand:SI 1 "arith_reg_operand" "r")))]
1179 [(set_attr "type" "dmpy")])
1181 (define_expand "mulsi3"
1183 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
1184 (match_operand:SI 2 "arith_reg_operand" "")))
1185 (set (match_operand:SI 0 "arith_reg_operand" "")
1194 /* The address must be set outside the libcall,
1195 since it goes into a pseudo. */
1196 rtx sym = gen_rtx_SYMBOL_REF (SImode, \"__mulsi3\");
1197 rtx addr = force_reg (SImode, sym);
1198 rtx insns = gen_mulsi3_call (operands[0], operands[1],
1200 first = XVECEXP (insns, 0, 0);
1201 last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1206 rtx macl = gen_rtx_REG (SImode, MACL_REG);
1208 first = emit_insn (gen_mul_l (operands[1], operands[2]));
1209 /* consec_sets_giv can only recognize the first insn that sets a
1210 giv as the giv insn. So we must tag this also with a REG_EQUAL
1212 last = emit_insn (gen_movsi_i ((operands[0]), macl));
1214 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1215 invariant code motion can move it. */
1216 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1217 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1221 (define_insn "mulsidi3_i"
1224 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1225 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1228 (mult:SI (match_dup 0)
1232 [(set_attr "type" "dmpy")])
1234 (define_insn "mulsidi3"
1235 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1236 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1237 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1238 (clobber (reg:DI 20))]
1243 [(set (match_operand:DI 0 "arith_reg_operand" "")
1244 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1245 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1246 (clobber (reg:DI 20))]
1251 rtx low_dst = gen_lowpart (SImode, operands[0]);
1252 rtx high_dst = gen_highpart (SImode, operands[0]);
1254 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
1256 emit_move_insn (low_dst, gen_rtx_REG (SImode, 21));
1257 emit_move_insn (high_dst, gen_rtx_REG (SImode, 20));
1258 /* We need something to tag the possible REG_EQUAL notes on to. */
1259 emit_move_insn (operands[0], operands[0]);
1263 (define_insn "umulsidi3_i"
1266 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1267 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1270 (mult:SI (match_dup 0)
1274 [(set_attr "type" "dmpy")])
1276 (define_insn "umulsidi3"
1277 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1278 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1279 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1280 (clobber (reg:DI 20))]
1285 [(set (match_operand:DI 0 "arith_reg_operand" "")
1286 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1287 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1288 (clobber (reg:DI 20))]
1293 rtx low_dst = gen_lowpart (SImode, operands[0]);
1294 rtx high_dst = gen_highpart (SImode, operands[0]);
1296 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
1298 emit_move_insn (low_dst, gen_rtx_REG (SImode, 21));
1299 emit_move_insn (high_dst, gen_rtx_REG (SImode, 20));
1300 /* We need something to tag the possible REG_EQUAL notes on to. */
1301 emit_move_insn (operands[0], operands[0]);
1305 (define_insn "smulsi3_highpart_i"
1308 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1309 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1311 (clobber (reg:SI 21))]
1314 [(set_attr "type" "dmpy")])
1316 (define_expand "smulsi3_highpart"
1317 [(parallel [(set (reg:SI 20)
1319 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1320 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1322 (clobber (reg:SI 21))])
1323 (set (match_operand:SI 0 "arith_reg_operand" "")
1330 first = emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
1331 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 20));
1332 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1333 invariant code motion can move it. */
1334 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1335 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1336 /* expand_binop can't find a suitable code in mul_highpart_optab to
1337 make a REG_EQUAL note from, so make one here.
1338 ??? Alternatively, we could put this at the calling site of expand_binop,
1339 i.e. expand_mult_highpart. */
1341 = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
1346 (define_insn "umulsi3_highpart_i"
1349 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1350 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1352 (clobber (reg:SI 21))]
1355 [(set_attr "type" "dmpy")])
1357 (define_expand "umulsi3_highpart"
1358 [(parallel [(set (reg:SI 20)
1360 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1361 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1363 (clobber (reg:SI 21))])
1364 (set (match_operand:SI 0 "arith_reg_operand" "")
1371 first = emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
1372 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 20));
1373 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1374 invariant code motion can move it. */
1375 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1376 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1380 ;; -------------------------------------------------------------------------
1381 ;; Logical operations
1382 ;; -------------------------------------------------------------------------
1385 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1386 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1387 (match_operand:SI 2 "logical_operand" "r,L")))]
1390 [(set_attr "type" "arith")])
1392 ;; If the constant is 255, then emit a extu.b instruction instead of an
1393 ;; and, since that will give better code.
1395 (define_expand "andsi3"
1396 [(set (match_operand:SI 0 "arith_reg_operand" "")
1397 (and:SI (match_operand:SI 1 "arith_reg_operand" "")
1398 (match_operand:SI 2 "logical_operand" "")))]
1402 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
1404 emit_insn (gen_zero_extendqisi2 (operands[0],
1405 gen_lowpart (QImode, operands[1])));
1410 (define_insn "iorsi3"
1411 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1412 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1413 (match_operand:SI 2 "logical_operand" "r,L")))]
1416 [(set_attr "type" "arith")])
1418 (define_insn "xorsi3"
1419 [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
1420 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1421 (match_operand:SI 2 "logical_operand" "L,r")))]
1424 [(set_attr "type" "arith")])
1426 ;; -------------------------------------------------------------------------
1427 ;; Shifts and rotates
1428 ;; -------------------------------------------------------------------------
1430 (define_insn "rotlsi3_1"
1431 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1432 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1435 (lshiftrt:SI (match_dup 1) (const_int 31)))]
1438 [(set_attr "type" "arith")])
1440 (define_insn "rotlsi3_31"
1441 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1442 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1444 (clobber (reg:SI 18))]
1447 [(set_attr "type" "arith")])
1449 (define_insn "rotlsi3_16"
1450 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1451 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
1455 [(set_attr "type" "arith")])
1457 (define_expand "rotlsi3"
1458 [(set (match_operand:SI 0 "arith_reg_operand" "")
1459 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
1460 (match_operand:SI 2 "immediate_operand" "")))]
1464 static char rot_tab[] = {
1465 000, 000, 000, 000, 000, 000, 010, 001,
1466 001, 001, 011, 013, 003, 003, 003, 003,
1467 003, 003, 003, 003, 003, 013, 012, 002,
1468 002, 002, 010, 000, 000, 000, 000, 000,
1473 if (GET_CODE (operands[2]) != CONST_INT)
1475 count = INTVAL (operands[2]);
1476 choice = rot_tab[count];
1477 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
1483 emit_move_insn (operands[0], operands[1]);
1484 count -= (count & 16) * 2;
1487 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
1494 parts[0] = gen_reg_rtx (SImode);
1495 parts[1] = gen_reg_rtx (SImode);
1496 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
1497 parts[choice-1] = operands[1];
1498 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
1499 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
1500 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
1501 count = (count & ~16) - 8;
1505 for (; count > 0; count--)
1506 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1507 for (; count < 0; count++)
1508 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1513 (define_insn "*rotlhi3_8"
1514 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1515 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
1519 [(set_attr "type" "arith")])
1521 (define_expand "rotlhi3"
1522 [(set (match_operand:HI 0 "arith_reg_operand" "")
1523 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
1524 (match_operand:HI 2 "immediate_operand" "")))]
1528 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
1535 ;; This pattern is used by init_expmed for computing the costs of shift
1538 (define_insn_and_split "ashlsi3_std"
1539 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r")
1540 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
1541 (match_operand:SI 2 "nonmemory_operand" "r,M,K,?ri")))
1542 (clobber (match_scratch:SI 3 "=X,X,X,&r"))]
1544 || (GET_CODE (operands[2]) == CONST_INT
1545 && CONST_OK_FOR_K (INTVAL (operands[2])))"
1552 && GET_CODE (operands[2]) == CONST_INT
1553 && ! CONST_OK_FOR_K (INTVAL (operands[2]))"
1554 [(set (match_dup 3) (match_dup 2))
1556 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
1557 (clobber (match_dup 4))])]
1558 "operands[4] = gen_rtx_SCRATCH (SImode);"
1559 [(set_attr "length" "*,*,*,4")
1560 (set_attr "type" "dyn_shift,arith,arith,arith")])
1562 (define_insn "ashlhi3_k"
1563 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
1564 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
1565 (match_operand:HI 2 "const_int_operand" "M,K")))]
1566 "CONST_OK_FOR_K (INTVAL (operands[2]))"
1570 [(set_attr "type" "arith")])
1572 (define_insn "ashlsi3_n"
1573 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1574 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
1575 (match_operand:SI 2 "const_int_operand" "n")))
1576 (clobber (reg:SI 18))]
1577 "! sh_dynamicalize_shift_p (operands[2])"
1579 [(set (attr "length")
1580 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1582 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1584 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1586 (const_string "8")))
1587 (set_attr "type" "arith")])
1590 [(set (match_operand:SI 0 "arith_reg_operand" "")
1591 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1592 (match_operand:SI 2 "const_int_operand" "n")))
1593 (clobber (reg:SI 18))]
1598 gen_shifty_op (ASHIFT, operands);
1602 (define_expand "ashlsi3"
1603 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1604 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1605 (match_operand:SI 2 "nonmemory_operand" "")))
1606 (clobber (reg:SI 18))])]
1610 if (GET_CODE (operands[2]) == CONST_INT
1611 && sh_dynamicalize_shift_p (operands[2]))
1612 operands[2] = force_reg (SImode, operands[2]);
1615 emit_insn (gen_ashlsi3_std (operands[0], operands[1], operands[2]));
1618 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1622 (define_insn "ashlhi3"
1623 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1624 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
1625 (match_operand:HI 2 "const_int_operand" "n")))
1626 (clobber (reg:SI 18))]
1629 [(set (attr "length")
1630 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1632 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1634 (const_string "6")))
1635 (set_attr "type" "arith")])
1638 [(set (match_operand:HI 0 "arith_reg_operand" "")
1639 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
1640 (match_operand:HI 2 "const_int_operand" "n")))
1641 (clobber (reg:SI 18))]
1646 gen_shifty_hi_op (ASHIFT, operands);
1651 ; arithmetic shift right
1654 (define_insn "ashrsi3_k"
1655 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1656 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1657 (match_operand:SI 2 "const_int_operand" "M")))
1658 (clobber (reg:SI 18))]
1659 "INTVAL (operands[2]) == 1"
1661 [(set_attr "type" "arith")])
1663 ;; We can't do HImode right shifts correctly unless we start out with an
1664 ;; explicit zero / sign extension; doing that would result in worse overall
1665 ;; code, so just let the machine independent code widen the mode.
1666 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
1669 ;; ??? This should be a define expand.
1671 (define_insn "ashrsi2_16"
1672 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1673 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1677 [(set_attr "length" "4")])
1680 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1681 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1684 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
1685 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
1686 "operands[2] = gen_lowpart (HImode, operands[0]);")
1688 ;; ??? This should be a define expand.
1690 (define_insn "ashrsi2_31"
1691 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1692 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1694 (clobber (reg:SI 18))]
1697 [(set_attr "length" "4")])
1700 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1701 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1703 (clobber (reg:SI 18))]
1708 emit_insn (gen_ashlsi_c (operands[0], operands[1]));
1709 emit_insn (gen_subc1 (operands[0], operands[0], operands[0]));
1713 (define_insn "ashlsi_c"
1714 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1715 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
1716 (set (reg:SI 18) (lt:SI (match_dup 1)
1720 [(set_attr "type" "arith")])
1722 (define_insn "ashrsi3_d"
1723 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1724 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1725 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1728 [(set_attr "type" "dyn_shift")])
1730 (define_insn "ashrsi3_n"
1732 (ashiftrt:SI (reg:SI 4)
1733 (match_operand:SI 0 "const_int_operand" "i")))
1734 (clobber (reg:SI 18))
1735 (clobber (reg:SI 17))
1736 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1739 [(set_attr "type" "sfunc")
1740 (set_attr "needs_delay_slot" "yes")])
1742 (define_expand "ashrsi3"
1743 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1744 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1745 (match_operand:SI 2 "nonmemory_operand" "")))
1746 (clobber (reg:SI 18))])]
1748 "if (expand_ashiftrt (operands)) DONE; else FAIL;")
1750 ;; logical shift right
1752 (define_insn "lshrsi3_d"
1753 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1754 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1755 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1758 [(set_attr "type" "dyn_shift")])
1760 ;; Only the single bit shift clobbers the T bit.
1762 (define_insn "lshrsi3_m"
1763 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1764 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1765 (match_operand:SI 2 "const_int_operand" "M")))
1766 (clobber (reg:SI 18))]
1767 "CONST_OK_FOR_M (INTVAL (operands[2]))"
1769 [(set_attr "type" "arith")])
1771 (define_insn "lshrsi3_k"
1772 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1773 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1774 (match_operand:SI 2 "const_int_operand" "K")))]
1775 "CONST_OK_FOR_K (INTVAL (operands[2]))
1776 && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
1778 [(set_attr "type" "arith")])
1780 (define_insn "lshrsi3_n"
1781 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1782 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1783 (match_operand:SI 2 "const_int_operand" "n")))
1784 (clobber (reg:SI 18))]
1785 "! sh_dynamicalize_shift_p (operands[2])"
1787 [(set (attr "length")
1788 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1790 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1792 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1794 (const_string "8")))
1795 (set_attr "type" "arith")])
1798 [(set (match_operand:SI 0 "arith_reg_operand" "")
1799 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1800 (match_operand:SI 2 "const_int_operand" "n")))
1801 (clobber (reg:SI 18))]
1806 gen_shifty_op (LSHIFTRT, operands);
1810 (define_expand "lshrsi3"
1811 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1812 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1813 (match_operand:SI 2 "nonmemory_operand" "")))
1814 (clobber (reg:SI 18))])]
1818 if (GET_CODE (operands[2]) == CONST_INT
1819 && sh_dynamicalize_shift_p (operands[2]))
1820 operands[2] = force_reg (SImode, operands[2]);
1821 if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
1823 rtx count = copy_to_mode_reg (SImode, operands[2]);
1824 emit_insn (gen_negsi2 (count, count));
1825 emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
1828 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1832 ;; ??? This should be a define expand.
1834 (define_insn "ashldi3_k"
1835 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1836 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
1838 (clobber (reg:SI 18))]
1840 "shll %R0\;rotcl %S0"
1841 [(set_attr "length" "4")
1842 (set_attr "type" "arith")])
1844 (define_expand "ashldi3"
1845 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1846 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
1847 (match_operand:DI 2 "immediate_operand" "")))
1848 (clobber (reg:SI 18))])]
1850 "{ if (GET_CODE (operands[2]) != CONST_INT
1851 || INTVAL (operands[2]) != 1) FAIL;} ")
1853 ;; ??? This should be a define expand.
1855 (define_insn "lshrdi3_k"
1856 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1857 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1859 (clobber (reg:SI 18))]
1861 "shlr %S0\;rotcr %R0"
1862 [(set_attr "length" "4")
1863 (set_attr "type" "arith")])
1865 (define_expand "lshrdi3"
1866 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1867 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1868 (match_operand:DI 2 "immediate_operand" "")))
1869 (clobber (reg:SI 18))])]
1871 "{ if (GET_CODE (operands[2]) != CONST_INT
1872 || INTVAL (operands[2]) != 1) FAIL;} ")
1874 ;; ??? This should be a define expand.
1876 (define_insn "ashrdi3_k"
1877 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1878 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1880 (clobber (reg:SI 18))]
1882 "shar %S0\;rotcr %R0"
1883 [(set_attr "length" "4")
1884 (set_attr "type" "arith")])
1886 (define_expand "ashrdi3"
1887 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1888 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1889 (match_operand:DI 2 "immediate_operand" "")))
1890 (clobber (reg:SI 18))])]
1892 "{ if (GET_CODE (operands[2]) != CONST_INT
1893 || INTVAL (operands[2]) != 1) FAIL; } ")
1895 ;; combined left/right shift
1898 [(set (match_operand:SI 0 "register_operand" "")
1899 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
1900 (match_operand:SI 2 "const_int_operand" "n"))
1901 (match_operand:SI 3 "const_int_operand" "n")))]
1902 "(unsigned)INTVAL (operands[2]) < 32"
1904 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
1908 [(set (match_operand:SI 0 "register_operand" "")
1909 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
1910 (match_operand:SI 2 "const_int_operand" "n"))
1911 (match_operand:SI 3 "const_int_operand" "n")))
1912 (clobber (reg:SI 18))]
1913 "(unsigned)INTVAL (operands[2]) < 32"
1915 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
1919 [(set (match_operand:SI 0 "register_operand" "=r")
1920 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
1921 (match_operand:SI 2 "const_int_operand" "n"))
1922 (match_operand:SI 3 "const_int_operand" "n")))
1923 (clobber (reg:SI 18))]
1924 "shl_and_kind (operands[2], operands[3], 0) == 1"
1926 [(set (attr "length")
1927 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
1929 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
1931 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
1933 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
1935 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
1937 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
1939 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
1940 (const_string "16")]
1941 (const_string "18")))
1942 (set_attr "type" "arith")])
1945 [(set (match_operand:SI 0 "register_operand" "=z")
1946 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
1947 (match_operand:SI 2 "const_int_operand" "n"))
1948 (match_operand:SI 3 "const_int_operand" "n")))
1949 (clobber (reg:SI 18))]
1950 "shl_and_kind (operands[2], operands[3], 0) == 2"
1952 [(set (attr "length")
1953 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
1955 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
1957 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
1959 (const_string "10")))
1960 (set_attr "type" "arith")])
1962 ;; shift left / and combination with a scratch register: The combine pass
1963 ;; does not accept the individual instructions, even though they are
1964 ;; cheap. But it needs a precise description so that it is usable after
1966 (define_insn "and_shl_scratch"
1967 [(set (match_operand:SI 0 "register_operand" "=r,&r")
1968 (lshiftrt:SI (ashift:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
1969 (match_operand:SI 2 "const_int_operand" "N,n"))
1970 (match_operand:SI 3 "" "0,r"))
1971 (match_operand:SI 4 "const_int_operand" "n,n"))
1972 (match_operand:SI 5 "const_int_operand" "n,n")))
1973 (clobber (reg:SI 18))]
1976 [(set (attr "length")
1977 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
1979 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
1981 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
1983 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
1984 (const_string "10")]
1985 (const_string "12")))
1986 (set_attr "type" "arith")])
1989 [(set (match_operand:SI 0 "register_operand" "=r,&r")
1990 (lshiftrt:SI (ashift:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
1991 (match_operand:SI 2 "const_int_operand" "N,n"))
1992 (match_operand:SI 3 "register_operand" "0,r"))
1993 (match_operand:SI 4 "const_int_operand" "n,n"))
1994 (match_operand:SI 5 "const_int_operand" "n,n")))
1995 (clobber (reg:SI 18))]
2000 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
2002 if (INTVAL (operands[2]))
2004 gen_shifty_op (LSHIFTRT, operands);
2006 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
2007 operands[2] = operands[4];
2008 gen_shifty_op (ASHIFT, operands);
2009 if (INTVAL (operands[5]))
2011 operands[2] = operands[5];
2012 gen_shifty_op (LSHIFTRT, operands);
2017 ;; signed left/right shift combination.
2019 [(set (match_operand:SI 0 "register_operand" "=r")
2020 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2021 (match_operand:SI 2 "const_int_operand" "n"))
2022 (match_operand:SI 3 "const_int_operand" "n")
2024 (clobber (reg:SI 18))]
2027 "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
2030 (define_insn "shl_sext_ext"
2031 [(set (match_operand:SI 0 "register_operand" "=r")
2032 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2033 (match_operand:SI 2 "const_int_operand" "n"))
2034 (match_operand:SI 3 "const_int_operand" "n")
2036 (clobber (reg:SI 18))]
2037 "(unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
2039 [(set (attr "length")
2040 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 1))
2042 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
2044 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2046 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2048 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2050 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2052 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
2054 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
2055 (const_string "16")]
2056 (const_string "18")))
2057 (set_attr "type" "arith")])
2059 (define_insn "shl_sext_sub"
2060 [(set (match_operand:SI 0 "register_operand" "=z")
2061 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2062 (match_operand:SI 2 "const_int_operand" "n"))
2063 (match_operand:SI 3 "const_int_operand" "n")
2065 (clobber (reg:SI 18))]
2066 "(shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
2068 [(set (attr "length")
2069 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2071 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2073 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2075 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2076 (const_string "12")]
2077 (const_string "14")))
2078 (set_attr "type" "arith")])
2080 ;; These patterns are found in expansions of DImode shifts by 16, and
2081 ;; allow the xtrct instruction to be generated from C source.
2083 (define_insn "xtrct_left"
2084 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2085 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
2087 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
2091 [(set_attr "type" "arith")])
2093 (define_insn "xtrct_right"
2094 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2095 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2097 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
2101 [(set_attr "type" "arith")])
2103 ;; -------------------------------------------------------------------------
2105 ;; -------------------------------------------------------------------------
2108 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2109 (neg:SI (plus:SI (reg:SI 18)
2110 (match_operand:SI 1 "arith_reg_operand" "r"))))
2112 (ne:SI (ior:SI (reg:SI 18) (match_dup 1))
2116 [(set_attr "type" "arith")])
2118 (define_expand "negdi2"
2119 [(set (match_operand:DI 0 "arith_reg_operand" "")
2120 (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
2121 (clobber (reg:SI 18))]
2125 int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
2126 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
2128 rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
2129 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
2131 rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
2132 rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
2134 emit_insn (gen_clrt ());
2135 emit_insn (gen_negc (low_dst, low_src));
2136 emit_insn (gen_negc (high_dst, high_src));
2140 (define_insn "negsi2"
2141 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2142 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2145 [(set_attr "type" "arith")])
2147 (define_insn "one_cmplsi2"
2148 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2149 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2152 [(set_attr "type" "arith")])
2154 ;; -------------------------------------------------------------------------
2155 ;; Zero extension instructions
2156 ;; -------------------------------------------------------------------------
2158 (define_insn "zero_extendhisi2"
2159 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2160 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
2163 [(set_attr "type" "arith")])
2165 (define_insn "zero_extendqisi2"
2166 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2167 (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
2170 [(set_attr "type" "arith")])
2172 (define_insn "zero_extendqihi2"
2173 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
2174 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
2177 [(set_attr "type" "arith")])
2179 ;; -------------------------------------------------------------------------
2180 ;; Sign extension instructions
2181 ;; -------------------------------------------------------------------------
2183 ;; ??? This should be a define expand.
2184 ;; ??? Or perhaps it should be dropped?
2186 /* There is no point in defining extendsidi2; convert_move generates good
2189 (define_insn "extendhisi2"
2190 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2191 (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
2196 [(set_attr "type" "arith,load")])
2198 (define_insn "extendqisi2"
2199 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2200 (sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2205 [(set_attr "type" "arith,load")])
2207 (define_insn "extendqihi2"
2208 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
2209 (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2214 [(set_attr "type" "arith,load")])
2216 ;; -------------------------------------------------------------------------
2217 ;; Move instructions
2218 ;; -------------------------------------------------------------------------
2220 ;; define push and pop so it is easy for sh.c
2222 (define_expand "push"
2223 [(set (mem:SI (pre_dec:SI (reg:SI 15)))
2224 (match_operand:SI 0 "register_operand" "r,l,x"))]
2228 (define_expand "pop"
2229 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
2230 (mem:SI (post_inc:SI (reg:SI 15))))]
2234 (define_expand "push_e"
2235 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI 15)))
2236 (match_operand:SF 0 "" ""))
2238 (clobber (scratch:SI))])]
2242 (define_insn "push_fpul"
2243 [(set (mem:SF (pre_dec:SI (reg:SI 15))) (reg:SF 22))]
2246 [(set_attr "type" "store")
2247 (set_attr "hit_stack" "yes")])
2249 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
2251 (define_expand "push_4"
2252 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI 15))) (match_operand:DF 0 "" ""))
2254 (clobber (scratch:SI))])]
2258 (define_expand "pop_e"
2259 [(parallel [(set (match_operand:SF 0 "" "")
2260 (mem:SF (post_inc:SI (reg:SI 15))))
2262 (clobber (scratch:SI))])]
2266 (define_insn "pop_fpul"
2267 [(set (reg:SF 22) (mem:SF (post_inc:SI (reg:SI 15))))]
2270 [(set_attr "type" "load")
2271 (set_attr "hit_stack" "yes")])
2273 (define_expand "pop_4"
2274 [(parallel [(set (match_operand:DF 0 "" "")
2275 (mem:DF (post_inc:SI (reg:SI 15))))
2277 (clobber (scratch:SI))])]
2281 ;; These two patterns can happen as the result of optimization, when
2282 ;; comparisons get simplified to a move of zero or 1 into the T reg.
2283 ;; They don't disappear completely, because the T reg is a fixed hard reg.
2286 [(set (reg:SI 18) (const_int 0))]
2291 [(set (reg:SI 18) (const_int 1))]
2295 ;; t/r must come after r/r, lest reload will try to reload stuff like
2296 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI 15 r15) (const_int 12)) 0) 0)
2297 ;; (made from (set (subreg:SI (reg:QI 73) 0) ) into T.
2298 (define_insn "movsi_i"
2299 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,m,<,<,xl,x,l,r")
2300 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,xl,t,r,x,l,r,>,>,i"))]
2303 && (register_operand (operands[0], SImode)
2304 || register_operand (operands[1], SImode))"
2319 [(set_attr "type" "pcload_si,move,*,load_si,move,move,store,store,pstore,move,load,pload,pcload_si")
2320 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*")])
2322 ;; t/r must come after r/r, lest reload will try to reload stuff like
2323 ;; (subreg:SI (reg:SF 38 fr14) 0) into T (compiling stdlib/strtod.c -m3e -O2)
2324 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
2325 ;; will require a reload.
2326 (define_insn "movsi_ie"
2327 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,m,<,<,xl,x,l,y,r,y,r,y")
2328 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,xl,t,r,x,l,r,>,>,>,i,r,y,y"))]
2330 && (register_operand (operands[0], SImode)
2331 || register_operand (operands[1], SImode))"
2349 ! move optimized away"
2350 [(set_attr "type" "pcload_si,move,*,load_si,move,move,store,store,pstore,move,load,pload,load,pcload_si,gp_fpul,gp_fpul,nil")
2351 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
2353 (define_insn "movsi_i_lowpart"
2354 [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,m,r"))
2355 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,mr,xl,t,r,i"))]
2356 "register_operand (operands[0], SImode)
2357 || register_operand (operands[1], SImode)"
2366 [(set_attr "type" "pcload,move,load,move,move,store,pcload")])
2368 (define_expand "movsi"
2369 [(set (match_operand:SI 0 "general_movdst_operand" "")
2370 (match_operand:SI 1 "general_movsrc_operand" ""))]
2372 "{ if (prepare_move_operands (operands, SImode)) DONE; }")
2374 (define_expand "ic_invalidate_line"
2375 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
2377 (clobber (scratch:SI))])]
2381 operands[0] = force_reg (Pmode, operands[0]);
2382 operands[1] = force_reg (Pmode, GEN_INT (0xf0000008));
2385 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
2386 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
2387 ;; the requirement *1*00 for associative address writes. The alignment of
2388 ;; %0 implies that its least significant bit is cleared,
2389 ;; thus we clear the V bit of a matching entry if there is one.
2390 (define_insn "ic_invalidate_line_i"
2391 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
2392 (match_operand:SI 1 "register_operand" "r")] 12)
2393 (clobber (match_scratch:SI 2 "=&r"))]
2395 "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
2396 [(set_attr "length" "8")])
2398 (define_insn "movqi_i"
2399 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
2400 (match_operand:QI 1 "general_movsrc_operand" "ri,m,r,t,l,r"))]
2401 "arith_reg_operand (operands[0], QImode)
2402 || arith_reg_operand (operands[1], QImode)"
2410 [(set_attr "type" "move,load,store,move,move,move")])
2412 (define_expand "movqi"
2413 [(set (match_operand:QI 0 "general_operand" "")
2414 (match_operand:QI 1 "general_operand" ""))]
2416 "{ if (prepare_move_operands (operands, QImode)) DONE; }")
2418 (define_insn "movhi_i"
2419 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
2420 (match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
2421 "arith_reg_operand (operands[0], HImode)
2422 || arith_reg_operand (operands[1], HImode)"
2432 [(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
2434 (define_expand "movhi"
2435 [(set (match_operand:HI 0 "general_movdst_operand" "")
2436 (match_operand:HI 1 "general_movsrc_operand" ""))]
2438 "{ if (prepare_move_operands (operands, HImode)) DONE; }")
2440 ;; ??? This should be a define expand.
2442 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
2443 ;; compiled with -m2 -ml -O3 -funroll-loops
2445 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
2446 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))]
2447 "arith_reg_operand (operands[0], DImode)
2448 || arith_reg_operand (operands[1], DImode)"
2449 "* return output_movedouble (insn, operands, DImode);"
2450 [(set_attr "length" "4")
2451 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
2453 ;; If the output is a register and the input is memory or a register, we have
2454 ;; to be careful and see which word needs to be loaded first.
2457 [(set (match_operand:DI 0 "general_movdst_operand" "")
2458 (match_operand:DI 1 "general_movsrc_operand" ""))]
2460 [(set (match_dup 2) (match_dup 3))
2461 (set (match_dup 4) (match_dup 5))]
2466 if ((GET_CODE (operands[0]) == MEM
2467 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2468 || (GET_CODE (operands[1]) == MEM
2469 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2472 if (GET_CODE (operands[0]) == REG)
2473 regno = REGNO (operands[0]);
2474 else if (GET_CODE (operands[0]) == SUBREG)
2475 regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
2476 else if (GET_CODE (operands[0]) == MEM)
2480 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2482 operands[2] = operand_subword (operands[0], 0, 0, DImode);
2483 operands[3] = operand_subword (operands[1], 0, 0, DImode);
2484 operands[4] = operand_subword (operands[0], 1, 0, DImode);
2485 operands[5] = operand_subword (operands[1], 1, 0, DImode);
2489 operands[2] = operand_subword (operands[0], 1, 0, DImode);
2490 operands[3] = operand_subword (operands[1], 1, 0, DImode);
2491 operands[4] = operand_subword (operands[0], 0, 0, DImode);
2492 operands[5] = operand_subword (operands[1], 0, 0, DImode);
2495 if (operands[2] == 0 || operands[3] == 0
2496 || operands[4] == 0 || operands[5] == 0)
2500 (define_expand "movdi"
2501 [(set (match_operand:DI 0 "general_movdst_operand" "")
2502 (match_operand:DI 1 "general_movsrc_operand" ""))]
2504 "{ if (prepare_move_operands (operands, DImode)) DONE; }")
2506 ;; ??? This should be a define expand.
2508 (define_insn "movdf_k"
2509 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
2510 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
2511 "(! TARGET_SH4 || reload_completed
2512 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
2513 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
2514 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
2515 && (arith_reg_operand (operands[0], DFmode)
2516 || arith_reg_operand (operands[1], DFmode))"
2517 "* return output_movedouble (insn, operands, DFmode);"
2518 [(set_attr "length" "4")
2519 (set_attr "type" "move,pcload,load,store")])
2521 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
2522 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
2523 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
2524 ;; the d/m/c/X alternative, which is split later into single-precision
2525 ;; instructions. And when not optimizing, no splits are done before fixing
2526 ;; up pcloads, so we need usable length information for that.
2527 (define_insn "movdf_i4"
2528 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
2529 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
2530 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
2531 (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
2533 && (arith_reg_operand (operands[0], DFmode)
2534 || arith_reg_operand (operands[1], DFmode))"
2546 [(set_attr_alternative "length"
2547 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
2549 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
2550 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2551 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2553 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
2554 (const_int 8) (const_int 8)])
2555 (set_attr "type" "fmove,move,pcload,load,store,pcload,load,store,load,load")
2556 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
2557 (const_string "double")
2558 (const_string "none")))])
2560 ;; Moving DFmode between fp/general registers through memory
2561 ;; (the top of the stack) is faster than moving through fpul even for
2562 ;; little endian. Because the type of an instruction is important for its
2563 ;; scheduling, it is beneficial to split these operations, rather than
2564 ;; emitting them in one single chunk, even if this will expose a stack
2565 ;; use that will prevent scheduling of other stack accesses beyond this
2568 [(set (match_operand:DF 0 "register_operand" "")
2569 (match_operand:DF 1 "register_operand" ""))
2570 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2571 (clobber (match_scratch:SI 3 "=X"))]
2572 "TARGET_SH4 && reload_completed
2573 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
2579 tos = gen_rtx (MEM, DFmode, gen_rtx (PRE_DEC, Pmode, stack_pointer_rtx));
2580 insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
2581 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2582 tos = gen_rtx (MEM, DFmode, gen_rtx (POST_INC, Pmode, stack_pointer_rtx));
2583 insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
2584 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2588 ;; local-alloc sometimes allocates scratch registers even when not required,
2589 ;; so we must be prepared to handle these.
2591 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
2593 [(set (match_operand:DF 0 "general_movdst_operand" "")
2594 (match_operand:DF 1 "general_movsrc_operand" ""))
2595 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2596 (clobber (match_scratch:SI 3 "X"))]
2599 && true_regnum (operands[0]) < 16
2600 && true_regnum (operands[1]) < 16"
2601 [(set (match_dup 0) (match_dup 1))]
2604 /* If this was a reg <-> mem operation with base + index reg addressing,
2605 we have to handle this in a special way. */
2606 rtx mem = operands[0];
2608 if (! memory_operand (mem, DFmode))
2613 if (GET_CODE (mem) == SUBREG && SUBREG_WORD (mem) == 0)
2614 mem = SUBREG_REG (mem);
2615 if (GET_CODE (mem) == MEM)
2617 rtx addr = XEXP (mem, 0);
2618 if (GET_CODE (addr) == PLUS
2619 && GET_CODE (XEXP (addr, 0)) == REG
2620 && GET_CODE (XEXP (addr, 1)) == REG)
2623 rtx reg0 = gen_rtx (REG, Pmode, 0);
2624 rtx regop = operands[store_p], word0 ,word1;
2626 if (GET_CODE (regop) == SUBREG)
2627 regop = alter_subreg (regop);
2628 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
2632 mem = copy_rtx (mem);
2633 PUT_MODE (mem, SImode);
2634 word0 = gen_rtx(SUBREG, SImode, regop, 0);
2636 ? gen_movsi_ie (mem, word0) : gen_movsi_ie (word0, mem));
2637 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
2638 mem = copy_rtx (mem);
2639 word1 = gen_rtx(SUBREG, SImode, regop, 1);
2641 ? gen_movsi_ie (mem, word1) : gen_movsi_ie (word1, mem));
2642 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
2648 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
2650 [(set (match_operand:DF 0 "register_operand" "")
2651 (match_operand:DF 1 "memory_operand" ""))
2652 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2653 (clobber (reg:SI 0))]
2654 "TARGET_SH4 && reload_completed"
2655 [(parallel [(set (match_dup 0) (match_dup 1))
2657 (clobber (scratch:SI))])]
2660 (define_expand "reload_indf"
2661 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
2662 (match_operand:DF 1 "immediate_operand" "FQ"))
2664 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
2668 (define_expand "reload_outdf"
2669 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
2670 (match_operand:DF 1 "register_operand" "af,r"))
2671 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
2675 ;; Simplify no-op moves.
2677 [(set (match_operand:SF 0 "register_operand" "")
2678 (match_operand:SF 1 "register_operand" ""))
2679 (use (match_operand:PSI 2 "fpscr_operand" ""))
2680 (clobber (match_scratch:SI 3 "X"))]
2681 "TARGET_SH3E && reload_completed
2682 && true_regnum (operands[0]) == true_regnum (operands[1])"
2683 [(set (match_dup 0) (match_dup 0))]
2686 ;; fmovd substitute post-reload splits
2688 [(set (match_operand:DF 0 "register_operand" "")
2689 (match_operand:DF 1 "register_operand" ""))
2690 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2691 (clobber (match_scratch:SI 3 "X"))]
2692 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2693 && true_regnum (operands[0]) >= FIRST_FP_REG
2694 && true_regnum (operands[1]) >= FIRST_FP_REG"
2698 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
2699 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst),
2700 gen_rtx (REG, SFmode, src), operands[2]));
2701 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst + 1),
2702 gen_rtx (REG, SFmode, src + 1), operands[2]));
2707 [(set (match_operand:DF 0 "register_operand" "")
2708 (mem:DF (match_operand:SI 1 "register_operand" "")))
2709 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2710 (clobber (match_scratch:SI 3 "X"))]
2711 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2712 && true_regnum (operands[0]) >= FIRST_FP_REG
2713 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
2717 int regno = true_regnum (operands[0]);
2719 rtx mem2 = gen_rtx (MEM, SFmode, gen_rtx (POST_INC, Pmode, operands[1]));
2721 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2722 regno + !! TARGET_LITTLE_ENDIAN),
2723 mem2, operands[2]));
2724 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[1], NULL_RTX);
2725 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2726 regno + ! TARGET_LITTLE_ENDIAN),
2727 gen_rtx (MEM, SFmode, operands[1]),
2733 [(set (match_operand:DF 0 "register_operand" "")
2734 (match_operand:DF 1 "memory_operand" ""))
2735 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2736 (clobber (match_scratch:SI 3 "X"))]
2737 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2738 && true_regnum (operands[0]) >= FIRST_FP_REG"
2742 int regno = true_regnum (operands[0]);
2743 rtx addr, insn, adjust = NULL_RTX;
2744 rtx mem2 = copy_rtx (operands[1]);
2745 rtx reg0 = gen_rtx_REG (SFmode, regno + !! TARGET_LITTLE_ENDIAN);
2746 rtx reg1 = gen_rtx_REG (SFmode, regno + ! TARGET_LITTLE_ENDIAN);
2748 PUT_MODE (mem2, SFmode);
2749 operands[1] = copy_rtx (mem2);
2750 addr = XEXP (mem2, 0);
2751 if (GET_CODE (addr) != POST_INC)
2753 /* If we have to modify the stack pointer, the value that we have
2754 read with post-increment might be modified by an interrupt,
2755 so write it back. */
2756 if (REGNO (addr) == STACK_POINTER_REGNUM)
2757 adjust = gen_push_e (reg0);
2759 adjust = gen_addsi3 (addr, addr, GEN_INT (-4));
2760 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
2762 addr = XEXP (addr, 0);
2763 insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
2764 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2765 insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
2769 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2774 [(set (match_operand:DF 0 "memory_operand" "")
2775 (match_operand:DF 1 "register_operand" ""))
2776 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2777 (clobber (match_scratch:SI 3 "X"))]
2778 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2779 && true_regnum (operands[1]) >= FIRST_FP_REG"
2783 int regno = true_regnum (operands[1]);
2784 rtx insn, addr, adjust = NULL_RTX;
2786 operands[0] = copy_rtx (operands[0]);
2787 PUT_MODE (operands[0], SFmode);
2788 insn = emit_insn (gen_movsf_ie (operands[0],
2789 gen_rtx (REG, SFmode,
2790 regno + ! TARGET_LITTLE_ENDIAN),
2792 operands[0] = copy_rtx (operands[0]);
2793 addr = XEXP (operands[0], 0);
2794 if (GET_CODE (addr) != PRE_DEC)
2796 adjust = gen_addsi3 (addr, addr, GEN_INT (4));
2797 emit_insn_before (adjust, insn);
2798 XEXP (operands[0], 0) = addr = gen_rtx (PRE_DEC, SImode, addr);
2800 addr = XEXP (addr, 0);
2802 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2803 insn = emit_insn (gen_movsf_ie (operands[0],
2804 gen_rtx (REG, SFmode,
2805 regno + !! TARGET_LITTLE_ENDIAN),
2807 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2811 ;; The '&' for operand 2 is not really true, but push_secondary_reload
2813 ;; Operand 1 must accept FPUL_REGS in case fpul is reloaded to memory,
2814 ;; to avoid a bogus tertiary reload.
2815 ;; We need a tertiary reload when a floating point register is reloaded
2816 ;; to memory, so the predicate for operand 0 must accept this, while the
2817 ;; constraint of operand 1 must reject the secondary reload register.
2818 ;; Thus, the secondary reload register for this case has to be GENERAL_REGS,
2820 ;; By having the predicate for operand 0 reject any register, we make
2821 ;; sure that the ordinary moves that just need an intermediate register
2822 ;; won't get a bogus tertiary reload.
2823 ;; We use tertiary_reload_operand instead of memory_operand here because
2824 ;; memory_operand rejects operands that are not directly addressible, e.g.:
2825 ;; (mem:SF (plus:SI (reg:SI 14 r14)
2826 ;; (const_int 132)))
2828 (define_expand "reload_outsf"
2829 [(parallel [(set (match_operand:SF 2 "register_operand" "=&r")
2830 (match_operand:SF 1 "register_operand" "y"))
2831 (clobber (scratch:SI))])
2832 (parallel [(set (match_operand:SF 0 "tertiary_reload_operand" "=m")
2834 (clobber (scratch:SI))])]
2838 ;; If the output is a register and the input is memory or a register, we have
2839 ;; to be careful and see which word needs to be loaded first.
2842 [(set (match_operand:DF 0 "general_movdst_operand" "")
2843 (match_operand:DF 1 "general_movsrc_operand" ""))]
2845 [(set (match_dup 2) (match_dup 3))
2846 (set (match_dup 4) (match_dup 5))]
2851 if ((GET_CODE (operands[0]) == MEM
2852 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2853 || (GET_CODE (operands[1]) == MEM
2854 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2857 if (GET_CODE (operands[0]) == REG)
2858 regno = REGNO (operands[0]);
2859 else if (GET_CODE (operands[0]) == SUBREG)
2860 regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
2861 else if (GET_CODE (operands[0]) == MEM)
2865 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2867 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2868 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2869 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2870 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
2874 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
2875 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
2876 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
2877 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
2880 if (operands[2] == 0 || operands[3] == 0
2881 || operands[4] == 0 || operands[5] == 0)
2885 ;; If a base address generated by LEGITIMIZE_ADDRESS for SImode is
2886 ;; used only once, let combine add in the index again.
2889 [(set (match_operand:SI 0 "register_operand" "")
2890 (match_operand:SI 1 "" ""))
2891 (clobber (match_operand 2 "register_operand" ""))]
2892 "! reload_in_progress && ! reload_completed"
2896 rtx addr, reg, const_int;
2898 if (GET_CODE (operands[1]) != MEM)
2900 addr = XEXP (operands[1], 0);
2901 if (GET_CODE (addr) != PLUS)
2903 reg = XEXP (addr, 0);
2904 const_int = XEXP (addr, 1);
2905 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
2906 && GET_CODE (const_int) == CONST_INT))
2908 emit_move_insn (operands[2], const_int);
2909 emit_move_insn (operands[0],
2910 change_address (operands[1], VOIDmode,
2911 gen_rtx_PLUS (SImode, reg, operands[2])));
2916 [(set (match_operand:SI 1 "" "")
2917 (match_operand:SI 0 "register_operand" ""))
2918 (clobber (match_operand 2 "register_operand" ""))]
2919 "! reload_in_progress && ! reload_completed"
2923 rtx addr, reg, const_int;
2925 if (GET_CODE (operands[1]) != MEM)
2927 addr = XEXP (operands[1], 0);
2928 if (GET_CODE (addr) != PLUS)
2930 reg = XEXP (addr, 0);
2931 const_int = XEXP (addr, 1);
2932 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
2933 && GET_CODE (const_int) == CONST_INT))
2935 emit_move_insn (operands[2], const_int);
2936 emit_move_insn (change_address (operands[1], VOIDmode,
2937 gen_rtx_PLUS (SImode, reg, operands[2])),
2942 (define_expand "movdf"
2943 [(set (match_operand:DF 0 "general_movdst_operand" "")
2944 (match_operand:DF 1 "general_movsrc_operand" ""))]
2948 if (prepare_move_operands (operands, DFmode)) DONE;
2951 emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
2957 (define_insn "movsf_i"
2958 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
2959 (match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
2962 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
2963 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
2964 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
2965 && (arith_reg_operand (operands[0], SFmode)
2966 || arith_reg_operand (operands[1], SFmode))"
2975 [(set_attr "type" "move,move,pcload,load,store,move,move")])
2977 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
2978 ;; update_flow_info would not know where to put REG_EQUAL notes
2979 ;; when the destination changes mode.
2980 (define_insn "movsf_ie"
2981 [(set (match_operand:SF 0 "general_movdst_operand"
2982 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,y")
2983 (match_operand:SF 1 "general_movsrc_operand"
2984 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y"))
2985 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
2986 (clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X"))]
2989 && (arith_reg_operand (operands[0], SFmode)
2990 || arith_reg_operand (operands[1], SFmode))"
3008 ! move optimized away"
3009 [(set_attr "type" "fmove,move,fmove,fmove,pcload,load,store,pcload,load,store,fmove,fmove,load,*,gp_fpul,gp_fpul,nil")
3010 (set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,4,2,2,0")
3011 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
3012 (const_string "single")
3013 (const_string "none")))])
3015 [(set (match_operand:SF 0 "register_operand" "")
3016 (match_operand:SF 1 "register_operand" ""))
3017 (use (match_operand:PSI 2 "fpscr_operand" "c"))
3018 (clobber (reg:SI 22))]
3020 [(parallel [(set (reg:SF 22) (match_dup 1))
3022 (clobber (scratch:SI))])
3023 (parallel [(set (match_dup 0) (reg:SF 22))
3025 (clobber (scratch:SI))])]
3028 (define_expand "movsf"
3029 [(set (match_operand:SF 0 "general_movdst_operand" "")
3030 (match_operand:SF 1 "general_movsrc_operand" ""))]
3034 if (prepare_move_operands (operands, SFmode))
3038 emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
3043 (define_insn "mov_nop"
3044 [(set (match_operand 0 "register_operand" "") (match_dup 0))]
3047 [(set_attr "length" "0")
3048 (set_attr "type" "nil")])
3050 (define_expand "reload_insf"
3051 [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
3052 (match_operand:SF 1 "immediate_operand" "FQ"))
3054 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
3058 (define_expand "reload_insi"
3059 [(parallel [(set (match_operand:SF 0 "register_operand" "=y")
3060 (match_operand:SF 1 "immediate_operand" "FQ"))
3061 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
3065 (define_insn "*movsi_y"
3066 [(set (match_operand:SI 0 "register_operand" "=y,y")
3067 (match_operand:SI 1 "immediate_operand" "Qi,I"))
3068 (clobber (match_scratch:SI 3 "=&z,r"))]
3070 && (reload_in_progress || reload_completed)"
3072 [(set_attr "length" "4")
3073 (set_attr "type" "pcload,move")])
3076 [(set (match_operand:SI 0 "register_operand" "")
3077 (match_operand:SI 1 "immediate_operand" ""))
3078 (clobber (match_operand:SI 2 "register_operand" ""))]
3080 [(set (match_dup 2) (match_dup 1))
3081 (set (match_dup 0) (match_dup 2))]
3085 [(set (match_operand:SI 0 "register_operand" "")
3086 (match_operand:SI 1 "memory_operand" ""))
3087 (clobber (reg:SI 0))]
3089 [(set (match_dup 0) (match_dup 1))]
3092 ;; ------------------------------------------------------------------------
3093 ;; Define the real conditional branch instructions.
3094 ;; ------------------------------------------------------------------------
3096 (define_insn "branch_true"
3097 [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 0))
3098 (label_ref (match_operand 0 "" ""))
3101 "* return output_branch (1, insn, operands);"
3102 [(set_attr "type" "cbranch")])
3104 (define_insn "branch_false"
3105 [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 0))
3106 (label_ref (match_operand 0 "" ""))
3109 "* return output_branch (0, insn, operands);"
3110 [(set_attr "type" "cbranch")])
3112 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
3113 ;; which destination is too far away.
3114 ;; The const_int_operand is distinct for each branch target; it avoids
3115 ;; unwanted matches with redundant_insn.
3116 (define_insn "block_branch_redirect"
3117 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] 4))]
3120 [(set_attr "length" "0")])
3122 ;; This one has the additional purpose to record a possible scratch register
3123 ;; for the following branch.
3124 (define_insn "indirect_jump_scratch"
3125 [(set (match_operand 0 "register_operand" "=r")
3126 (unspec [(match_operand 1 "const_int_operand" "")] 4))]
3129 [(set_attr "length" "0")])
3131 ;; Conditional branch insns
3133 (define_expand "beq"
3135 (if_then_else (ne (reg:SI 18) (const_int 0))
3136 (label_ref (match_operand 0 "" ""))
3139 "from_compare (operands, EQ);")
3141 (define_expand "bne"
3143 (if_then_else (eq (reg:SI 18) (const_int 0))
3144 (label_ref (match_operand 0 "" ""))
3147 "from_compare (operands, EQ);")
3149 (define_expand "bgt"
3151 (if_then_else (ne (reg:SI 18) (const_int 0))
3152 (label_ref (match_operand 0 "" ""))
3155 "from_compare (operands, GT);")
3157 (define_expand "blt"
3159 (if_then_else (eq (reg:SI 18) (const_int 0))
3160 (label_ref (match_operand 0 "" ""))
3165 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3167 rtx tmp = sh_compare_op0;
3168 sh_compare_op0 = sh_compare_op1;
3169 sh_compare_op1 = tmp;
3170 emit_insn (gen_bgt (operands[0]));
3173 from_compare (operands, GE);
3176 (define_expand "ble"
3178 (if_then_else (eq (reg:SI 18) (const_int 0))
3179 (label_ref (match_operand 0 "" ""))
3186 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3188 rtx tmp = sh_compare_op0;
3189 sh_compare_op0 = sh_compare_op1;
3190 sh_compare_op1 = tmp;
3191 emit_insn (gen_bge (operands[0]));
3194 from_compare (operands, GT);
3197 (define_expand "bge"
3199 (if_then_else (ne (reg:SI 18) (const_int 0))
3200 (label_ref (match_operand 0 "" ""))
3207 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3209 rtx tmp = sh_compare_op0;
3210 sh_compare_op0 = sh_compare_op1;
3211 sh_compare_op1 = tmp;
3212 emit_insn (gen_ble (operands[0]));
3215 from_compare (operands, GE);
3218 (define_expand "bgtu"
3220 (if_then_else (ne (reg:SI 18) (const_int 0))
3221 (label_ref (match_operand 0 "" ""))
3224 "from_compare (operands, GTU); ")
3226 (define_expand "bltu"
3228 (if_then_else (eq (reg:SI 18) (const_int 0))
3229 (label_ref (match_operand 0 "" ""))
3232 "from_compare (operands, GEU);")
3234 (define_expand "bgeu"
3236 (if_then_else (ne (reg:SI 18) (const_int 0))
3237 (label_ref (match_operand 0 "" ""))
3240 "from_compare (operands, GEU);")
3242 (define_expand "bleu"
3244 (if_then_else (eq (reg:SI 18) (const_int 0))
3245 (label_ref (match_operand 0 "" ""))
3248 "from_compare (operands, GTU);")
3250 ;; ------------------------------------------------------------------------
3251 ;; Jump and linkage insns
3252 ;; ------------------------------------------------------------------------
3256 (label_ref (match_operand 0 "" "")))]
3260 /* The length is 16 if the delay slot is unfilled. */
3261 if (get_attr_length(insn) > 4)
3262 return output_far_jump(insn, operands[0]);
3264 return \"bra %l0%#\";
3266 [(set_attr "type" "jump")
3267 (set_attr "needs_delay_slot" "yes")])
3269 (define_insn "calli"
3270 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3271 (match_operand 1 "" ""))
3273 (clobber (reg:SI 17))]
3276 [(set_attr "type" "call")
3277 (set (attr "fp_mode")
3278 (if_then_else (eq_attr "fpu_single" "yes")
3279 (const_string "single") (const_string "double")))
3280 (set_attr "needs_delay_slot" "yes")])
3282 ;; This is a pc-rel call, using bsrf, for use with PIC.
3284 (define_insn "calli_pcrel"
3285 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3286 (match_operand 1 "" ""))
3288 (use (match_operand 2 "" ""))
3289 (clobber (reg:SI 17))]
3292 [(set_attr "type" "call")
3293 (set (attr "fp_mode")
3294 (if_then_else (eq_attr "fpu_single" "yes")
3295 (const_string "single") (const_string "double")))
3296 (set_attr "needs_delay_slot" "yes")])
3298 (define_insn "call_valuei"
3299 [(set (match_operand 0 "" "=rf")
3300 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3301 (match_operand 2 "" "")))
3303 (clobber (reg:SI 17))]
3306 [(set_attr "type" "call")
3307 (set (attr "fp_mode")
3308 (if_then_else (eq_attr "fpu_single" "yes")
3309 (const_string "single") (const_string "double")))
3310 (set_attr "needs_delay_slot" "yes")])
3312 (define_insn "call_valuei_pcrel"
3313 [(set (match_operand 0 "" "=rf")
3314 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3315 (match_operand 2 "" "")))
3317 (use (match_operand 3 "" ""))
3318 (clobber (reg:SI 17))]
3321 [(set_attr "type" "call")
3322 (set (attr "fp_mode")
3323 (if_then_else (eq_attr "fpu_single" "yes")
3324 (const_string "single") (const_string "double")))
3325 (set_attr "needs_delay_slot" "yes")])
3327 (define_expand "call"
3328 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
3329 (match_operand 1 "" ""))
3331 (clobber (reg:SI 17))])]
3334 if (flag_pic && ! TARGET_SH1 && ! flag_unroll_loops
3335 && GET_CODE (operands[0]) == MEM
3336 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
3338 rtx reg = gen_reg_rtx (SImode), lab = gen_label_rtx ();
3340 if (SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
3341 emit_insn (gen_sym_label2reg (reg, XEXP (operands[0], 0), lab));
3343 emit_insn (gen_symPLT_label2reg (reg, XEXP (operands[0], 0), lab));
3345 emit_call_insn (gen_calli_pcrel (operands[0], operands[1], lab));
3349 operands[0] = force_reg (SImode, XEXP (operands[0], 0));")
3351 (define_expand "call_value"
3352 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
3353 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
3354 (match_operand 2 "" "")))
3356 (clobber (reg:SI 17))])]
3359 if (flag_pic && ! TARGET_SH1 && ! flag_unroll_loops
3360 && GET_CODE (operands[1]) == MEM
3361 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
3363 rtx reg = gen_reg_rtx (SImode), lab = gen_label_rtx ();
3365 if (SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
3366 emit_insn (gen_sym_label2reg (reg, XEXP (operands[1], 0), lab));
3368 emit_insn (gen_symPLT_label2reg (reg, XEXP (operands[1], 0), lab));
3370 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[1],
3375 operands[1] = force_reg (SImode, XEXP (operands[1], 0));")
3377 (define_insn "indirect_jump"
3379 (match_operand:SI 0 "arith_reg_operand" "r"))]
3382 [(set_attr "needs_delay_slot" "yes")
3383 (set_attr "type" "jump_ind")])
3385 ;; The use of operand 1 / 2 helps us distinguish case table jumps
3386 ;; which can be present in structured code from indirect jumps which can not
3387 ;; be present in structured code. This allows -fprofile-arcs to work.
3389 ;; For SH1 processors.
3390 (define_insn "casesi_jump_1"
3392 (match_operand:SI 0 "register_operand" "r"))
3393 (use (label_ref (match_operand 1 "" "")))]
3396 [(set_attr "needs_delay_slot" "yes")
3397 (set_attr "type" "jump_ind")])
3399 ;; For all later processors.
3400 (define_insn "casesi_jump_2"
3401 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
3402 (label_ref (match_operand 1 "" ""))))
3403 (use (label_ref (match_operand 2 "" "")))]
3404 "! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn"
3406 [(set_attr "needs_delay_slot" "yes")
3407 (set_attr "type" "jump_ind")])
3409 ;; Call subroutine returning any type.
3410 ;; ??? This probably doesn't work.
3412 (define_expand "untyped_call"
3413 [(parallel [(call (match_operand 0 "" "")
3415 (match_operand 1 "" "")
3416 (match_operand 2 "" "")])]
3422 emit_call_insn (gen_call (operands[0], const0_rtx));
3424 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3426 rtx set = XVECEXP (operands[2], 0, i);
3427 emit_move_insn (SET_DEST (set), SET_SRC (set));
3430 /* The optimizer does not know that the call sets the function value
3431 registers we stored in the result block. We avoid problems by
3432 claiming that all hard registers are used and clobbered at this
3434 emit_insn (gen_blockage ());
3439 ;; ------------------------------------------------------------------------
3441 ;; ------------------------------------------------------------------------
3445 (eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
3446 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
3449 [(set_attr "type" "arith")])
3456 ;; Load address of a label. This is only generated by the casesi expand,
3457 ;; and by machine_dependent_reorg (fixing up fp moves).
3458 ;; This must use unspec, because this only works for labels that are
3463 (unspec [(label_ref (match_operand 0 "" ""))] 1))]
3466 [(set_attr "in_delay_slot" "no")
3467 (set_attr "type" "arith")])
3469 (define_expand "GOTaddr2picreg"
3470 [(set (reg:SI 0) (const (unspec [(const (unspec [(match_dup 1)] 6))] 1)))
3471 (set (match_dup 0) (const (unspec [(match_dup 1)] 6)))
3472 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI 0)))]
3475 operands[0] = pic_offset_table_rtx;
3476 current_function_uses_pic_offset_table = 1;
3477 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
3481 (define_expand "sym_label2reg"
3482 [(set (match_operand:SI 0 "" "")
3484 (unspec [(match_operand:SI 1 "" "")] 6)
3486 (unspec [(label_ref (match_operand:SI 2 "" ""))] 6)
3490 (define_expand "symGOT2reg"
3491 [(set (match_operand:SI 0 "" "")
3492 (const (unspec [(match_operand:SI 1 "" "")] 7)))
3493 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
3494 (set (match_dup 0) (mem:SI (match_dup 0)))]
3498 operands[2] = pic_offset_table_rtx;
3499 current_function_uses_pic_offset_table = 1;
3502 (define_expand "symGOTOFF2reg"
3503 [(set (match_operand:SI 0 "" "")
3504 (const (unspec [(match_operand:SI 1 "" "")] 8)))
3505 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3509 operands[2] = pic_offset_table_rtx;
3510 current_function_uses_pic_offset_table = 1;
3513 (define_expand "symPLT_label2reg"
3514 [(set (match_operand:SI 0 "" "")
3517 (unspec [(match_operand:SI 1 "" "")] 9))
3520 (unspec [(label_ref (match_operand:SI 2 "" ""))] 6)
3522 (use (match_dup 3))]
3523 ;; Even though the PIC register is not really used by the call
3524 ;; sequence in which this is expanded, the PLT code assumes the PIC
3525 ;; register is set, so we must not skip its initialization. Since
3526 ;; we only use this expand as part of calling sequences, and never
3527 ;; to take the address of a function, this is the best point to
3528 ;; insert the (use). Using the PLT to take the address of a
3529 ;; function would be wrong, not only because the PLT entry could
3530 ;; then be called from a function that doesn't initialize the PIC
3531 ;; register to the proper GOT, but also because pointers to the same
3532 ;; function might not compare equal, should they be set by different
3533 ;; shared libraries.
3536 operands[3] = pic_offset_table_rtx;
3537 current_function_uses_pic_offset_table = 1;
3540 ;; case instruction for switch statements.
3542 ;; Operand 0 is index
3543 ;; operand 1 is the minimum bound
3544 ;; operand 2 is the maximum bound - minimum bound + 1
3545 ;; operand 3 is CODE_LABEL for the table;
3546 ;; operand 4 is the CODE_LABEL to go to if index out of range.
3548 (define_expand "casesi"
3549 [(match_operand:SI 0 "arith_reg_operand" "")
3550 (match_operand:SI 1 "arith_reg_operand" "")
3551 (match_operand:SI 2 "arith_reg_operand" "")
3552 (match_operand 3 "" "") (match_operand 4 "" "")]
3556 rtx reg = gen_reg_rtx (SImode);
3557 rtx reg2 = gen_reg_rtx (SImode);
3558 operands[1] = copy_to_mode_reg (SImode, operands[1]);
3559 operands[2] = copy_to_mode_reg (SImode, operands[2]);
3560 /* If optimizing, casesi_worker depends on the mode of the instruction
3561 before label it 'uses' - operands[3]. */
3562 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
3564 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
3566 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
3568 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
3569 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
3570 operands[3], but to lab. We will fix this up in
3571 machine_dependent_reorg. */
3576 (define_expand "casesi_0"
3577 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
3578 (set (match_dup 4) (minus:SI (match_dup 4)
3579 (match_operand:SI 1 "arith_operand" "")))
3581 (gtu:SI (match_dup 4)
3582 (match_operand:SI 2 "arith_reg_operand" "")))
3584 (if_then_else (ne (reg:SI 18)
3586 (label_ref (match_operand 3 "" ""))
3591 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
3592 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
3593 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
3595 (define_insn "casesi_worker_0"
3596 [(set (match_operand:SI 0 "register_operand" "=r,r")
3597 (unspec [(match_operand 1 "register_operand" "0,r")
3598 (label_ref (match_operand 2 "" ""))] 2))
3599 (clobber (match_scratch:SI 3 "=X,1"))
3600 (clobber (match_scratch:SI 4 "=&z,z"))]
3605 [(set (match_operand:SI 0 "register_operand" "")
3606 (unspec [(match_operand 1 "register_operand" "")
3607 (label_ref (match_operand 2 "" ""))] 2))
3608 (clobber (match_scratch:SI 3 ""))
3609 (clobber (match_scratch:SI 4 ""))]
3610 "! TARGET_SH2 && reload_completed"
3611 [(set (reg:SI 0) (unspec [(label_ref (match_dup 2))] 1))
3612 (parallel [(set (match_dup 0)
3613 (unspec [(reg:SI 0) (match_dup 1) (label_ref (match_dup 2))] 2))
3614 (clobber (match_dup 3))])
3615 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI 0)))]
3616 "LABEL_NUSES (operands[2])++;")
3619 [(set (match_operand:SI 0 "register_operand" "")
3620 (unspec [(match_operand 1 "register_operand" "")
3621 (label_ref (match_operand 2 "" ""))] 2))
3622 (clobber (match_scratch:SI 3 ""))
3623 (clobber (match_scratch:SI 4 ""))]
3624 "TARGET_SH2 && reload_completed"
3625 [(set (reg:SI 0) (unspec [(label_ref (match_dup 2))] 1))
3626 (parallel [(set (match_dup 0)
3627 (unspec [(reg:SI 0) (match_dup 1) (label_ref (match_dup 2))] 2))
3628 (clobber (match_dup 3))])]
3629 "LABEL_NUSES (operands[2])++;")
3631 (define_insn "*casesi_worker"
3632 [(set (match_operand:SI 0 "register_operand" "=r,r")
3633 (unspec [(reg:SI 0) (match_operand 1 "register_operand" "0,r")
3634 (label_ref (match_operand 2 "" ""))] 2))
3635 (clobber (match_scratch:SI 3 "=X,1"))]
3639 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
3641 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
3644 switch (GET_MODE (diff_vec))
3647 return \"shll2 %1\;mov.l @(r0,%1),%0\";
3649 return \"add %1,%1\;mov.w @(r0,%1),%0\";
3651 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
3652 return \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
3653 return \"mov.b @(r0,%1),%0\";
3658 [(set_attr "length" "4")])
3660 (define_expand "return"
3662 "reload_completed && ! sh_need_epilogue ()"
3665 (define_insn "*return_i"
3669 [(set_attr "type" "return")
3670 (set_attr "needs_delay_slot" "yes")])
3672 (define_expand "prologue"
3675 "sh_expand_prologue (); DONE;")
3677 (define_expand "epilogue"
3680 "sh_expand_epilogue ();")
3682 (define_insn "blockage"
3683 [(unspec_volatile [(const_int 0)] 0)]
3686 [(set_attr "length" "0")])
3688 ;; ------------------------------------------------------------------------
3690 ;; ------------------------------------------------------------------------
3693 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3694 (eq:SI (reg:SI 18) (const_int 1)))]
3697 [(set_attr "type" "arith")])
3699 (define_expand "seq"
3700 [(set (match_operand:SI 0 "arith_reg_operand" "")
3703 "operands[1] = prepare_scc_operands (EQ);")
3705 (define_expand "slt"
3706 [(set (match_operand:SI 0 "arith_reg_operand" "")
3709 "operands[1] = prepare_scc_operands (LT);")
3711 (define_expand "sle"
3712 [(match_operand:SI 0 "arith_reg_operand" "")]
3716 rtx tmp = sh_compare_op0;
3717 sh_compare_op0 = sh_compare_op1;
3718 sh_compare_op1 = tmp;
3719 emit_insn (gen_sge (operands[0]));
3723 (define_expand "sgt"
3724 [(set (match_operand:SI 0 "arith_reg_operand" "")
3727 "operands[1] = prepare_scc_operands (GT);")
3729 (define_expand "sge"
3730 [(set (match_operand:SI 0 "arith_reg_operand" "")
3735 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3739 rtx lab = gen_label_rtx ();
3740 prepare_scc_operands (EQ);
3741 emit_jump_insn (gen_branch_true (lab));
3742 prepare_scc_operands (GT);
3744 emit_insn (gen_movt (operands[0]));
3747 emit_insn (gen_movnegt (operands[0], prepare_scc_operands (LT)));
3750 operands[1] = prepare_scc_operands (GE);
3753 (define_expand "sgtu"
3754 [(set (match_operand:SI 0 "arith_reg_operand" "")
3757 "operands[1] = prepare_scc_operands (GTU);")
3759 (define_expand "sltu"
3760 [(set (match_operand:SI 0 "arith_reg_operand" "")
3763 "operands[1] = prepare_scc_operands (LTU);")
3765 (define_expand "sleu"
3766 [(set (match_operand:SI 0 "arith_reg_operand" "")
3769 "operands[1] = prepare_scc_operands (LEU);")
3771 (define_expand "sgeu"
3772 [(set (match_operand:SI 0 "arith_reg_operand" "")
3775 "operands[1] = prepare_scc_operands (GEU);")
3777 ;; sne moves the complement of the T reg to DEST like this:
3781 ;; This is better than xoring compare result with 1 because it does
3782 ;; not require r0 and further, the -1 may be CSE-ed or lifted out of a
3785 (define_expand "sne"
3786 [(set (match_dup 2) (const_int -1))
3787 (parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
3788 (neg:SI (plus:SI (match_dup 1)
3791 (ne:SI (ior:SI (match_dup 1) (match_dup 2))
3796 operands[1] = prepare_scc_operands (EQ);
3797 operands[2] = gen_reg_rtx (SImode);
3800 ;; Use the same trick for FP sle / sge
3801 (define_expand "movnegt"
3802 [(set (match_dup 2) (const_int -1))
3803 (parallel [(set (match_operand 0 "" "")
3804 (neg:SI (plus:SI (match_dup 1)
3807 (ne:SI (ior:SI (match_operand 1 "" "") (match_dup 2))
3810 "operands[2] = gen_reg_rtx (SImode);")
3812 ;; Recognize mov #-1/negc/neg sequence, and change it to movt/add #-1.
3813 ;; This prevents a regression that occurred when we switched from xor to
3817 [(set (match_operand:SI 0 "arith_reg_operand" "")
3818 (plus:SI (reg:SI 18)
3821 [(set (match_dup 0) (eq:SI (reg:SI 18) (const_int 1)))
3822 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
3825 ;; -------------------------------------------------------------------------
3826 ;; Instructions to cope with inline literal tables
3827 ;; -------------------------------------------------------------------------
3829 ; 2 byte integer in line
3831 (define_insn "consttable_2"
3832 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 2)]
3836 assemble_integer (operands[0], 2, 1);
3839 [(set_attr "length" "2")
3840 (set_attr "in_delay_slot" "no")])
3842 ; 4 byte integer in line
3844 (define_insn "consttable_4"
3845 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 4)]
3849 assemble_integer (operands[0], 4, 1);
3852 [(set_attr "length" "4")
3853 (set_attr "in_delay_slot" "no")])
3855 ; 8 byte integer in line
3857 (define_insn "consttable_8"
3858 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 6)]
3862 assemble_integer (operands[0], 8, 1);
3865 [(set_attr "length" "8")
3866 (set_attr "in_delay_slot" "no")])
3868 ; 4 byte floating point
3870 (define_insn "consttable_sf"
3871 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")] 4)]
3875 union real_extract u;
3876 bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
3877 assemble_real (u.d, SFmode);
3880 [(set_attr "length" "4")
3881 (set_attr "in_delay_slot" "no")])
3883 ; 8 byte floating point
3885 (define_insn "consttable_df"
3886 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")] 6)]
3890 union real_extract u;
3891 bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
3892 assemble_real (u.d, DFmode);
3895 [(set_attr "length" "8")
3896 (set_attr "in_delay_slot" "no")])
3898 ;; Alignment is needed for some constant tables; it may also be added for
3899 ;; Instructions at the start of loops, or after unconditional branches.
3900 ;; ??? We would get more accurate lengths if we did instruction
3901 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
3902 ;; here is too conservative.
3904 ; align to a two byte boundary
3906 (define_expand "align_2"
3907 [(unspec_volatile [(const_int 1)] 1)]
3911 ; align to a four byte boundary
3912 ;; align_4 and align_log are instructions for the starts of loops, or
3913 ;; after unconditional branches, which may take up extra room.
3915 (define_expand "align_4"
3916 [(unspec_volatile [(const_int 2)] 1)]
3920 ; align to a cache line boundary
3922 (define_insn "align_log"
3923 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 1)]
3926 [(set_attr "length" "0")
3927 (set_attr "in_delay_slot" "no")])
3929 ; emitted at the end of the literal table, used to emit the
3930 ; 32bit branch labels if needed.
3932 (define_insn "consttable_end"
3933 [(unspec_volatile [(const_int 0)] 11)]
3935 "* return output_jump_label_table ();"
3936 [(set_attr "in_delay_slot" "no")])
3938 ;; -------------------------------------------------------------------------
3940 ;; -------------------------------------------------------------------------
3942 ;; String/block move insn.
3944 (define_expand "movstrsi"
3945 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
3946 (mem:BLK (match_operand:BLK 1 "" "")))
3947 (use (match_operand:SI 2 "nonmemory_operand" ""))
3948 (use (match_operand:SI 3 "immediate_operand" ""))
3949 (clobber (reg:SI 17))
3950 (clobber (reg:SI 4))
3951 (clobber (reg:SI 5))
3952 (clobber (reg:SI 0))])]
3956 if(expand_block_move (operands))
3961 (define_insn "block_move_real"
3962 [(parallel [(set (mem:BLK (reg:SI 4))
3963 (mem:BLK (reg:SI 5)))
3964 (use (match_operand:SI 0 "arith_reg_operand" "r"))
3965 (clobber (reg:SI 17))
3966 (clobber (reg:SI 0))])]
3969 [(set_attr "type" "sfunc")
3970 (set_attr "needs_delay_slot" "yes")])
3972 (define_insn "block_lump_real"
3973 [(parallel [(set (mem:BLK (reg:SI 4))
3974 (mem:BLK (reg:SI 5)))
3975 (use (match_operand:SI 0 "arith_reg_operand" "r"))
3977 (clobber (reg:SI 17))
3978 (clobber (reg:SI 18))
3979 (clobber (reg:SI 4))
3980 (clobber (reg:SI 5))
3981 (clobber (reg:SI 6))
3982 (clobber (reg:SI 0))])]
3985 [(set_attr "type" "sfunc")
3986 (set_attr "needs_delay_slot" "yes")])
3988 (define_insn "block_move_real_i4"
3989 [(parallel [(set (mem:BLK (reg:SI 4))
3990 (mem:BLK (reg:SI 5)))
3991 (use (match_operand:SI 0 "arith_reg_operand" "r"))
3992 (clobber (reg:SI 17))
3993 (clobber (reg:SI 0))
3994 (clobber (reg:SI 1))
3995 (clobber (reg:SI 2))])]
3998 [(set_attr "type" "sfunc")
3999 (set_attr "needs_delay_slot" "yes")])
4001 (define_insn "block_lump_real_i4"
4002 [(parallel [(set (mem:BLK (reg:SI 4))
4003 (mem:BLK (reg:SI 5)))
4004 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4006 (clobber (reg:SI 17))
4007 (clobber (reg:SI 18))
4008 (clobber (reg:SI 4))
4009 (clobber (reg:SI 5))
4010 (clobber (reg:SI 6))
4011 (clobber (reg:SI 0))
4012 (clobber (reg:SI 1))
4013 (clobber (reg:SI 2))
4014 (clobber (reg:SI 3))])]
4017 [(set_attr "type" "sfunc")
4018 (set_attr "needs_delay_slot" "yes")])
4020 ;; -------------------------------------------------------------------------
4021 ;; Floating point instructions.
4022 ;; -------------------------------------------------------------------------
4024 ;; ??? All patterns should have a type attribute.
4026 (define_expand "fpu_switch0"
4027 [(set (match_operand:SI 0 "" "") (match_dup 2))
4028 (set (match_dup 1) (mem:PSI (match_dup 0)))]
4032 operands[1] = get_fpscr_rtx ();
4033 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
4035 operands[2] = legitimize_pic_address (operands[2], SImode,
4036 no_new_pseudos ? operands[0] : 0);
4039 (define_expand "fpu_switch1"
4040 [(set (match_operand:SI 0 "" "") (match_dup 2))
4041 (set (match_dup 3) (plus:SI (match_dup 0) (const_int 4)))
4042 (set (match_dup 1) (mem:PSI (match_dup 3)))]
4046 operands[1] = get_fpscr_rtx ();
4047 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
4049 operands[2] = legitimize_pic_address (operands[2], SImode,
4050 no_new_pseudos ? operands[0] : 0);
4051 operands[3] = no_new_pseudos ? operands[0] : gen_reg_rtx (SImode);
4054 (define_expand "movpsi"
4055 [(set (match_operand:PSI 0 "register_operand" "")
4056 (match_operand:PSI 1 "general_movsrc_operand" ""))]
4060 ;; The c / m alternative is a fake to guide reload to load directly into
4061 ;; fpscr, since reload doesn't know how to use post-increment.
4062 ;; GO_IF_LEGITIMATE_ADDRESS guards about bogus addresses before reload,
4063 ;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
4064 ;; predicate after reload.
4065 ;; The gp_fpul type for r/!c might look a bit odd, but it actually schedules
4066 ;; like a gpr <-> fpul move.
4067 (define_insn "fpu_switch"
4068 [(set (match_operand:PSI 0 "register_operand" "=c,c,r,c,c,r,m,r")
4069 (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c"))]
4071 || true_regnum (operands[0]) != FPSCR_REG || GET_CODE (operands[1]) != MEM
4072 || GET_CODE (XEXP (operands[1], 0)) != PLUS"
4074 ! precision stays the same
4082 [(set_attr "length" "0,2,2,4,2,2,2,2")
4083 (set_attr "type" "dfp_conv,dfp_conv,load,dfp_conv,dfp_conv,move,store,gp_fpul")])
4086 [(set (reg:PSI 48) (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
4087 "find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
4088 [(set (match_dup 0) (match_dup 0))]
4091 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
4092 gen_rtx (MEM, PSImode,
4093 gen_rtx (POST_INC, Pmode,
4095 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
4099 [(set (reg:PSI 48) (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
4101 [(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))]
4104 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
4105 gen_rtx (MEM, PSImode,
4106 gen_rtx (POST_INC, Pmode,
4108 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
4111 ;; ??? This uses the fp unit, but has no type indicating that.
4112 ;; If we did that, this would either give a bogus latency or introduce
4113 ;; a bogus FIFO constraint.
4114 ;; Since this insn is currently only used for prologues/epilogues,
4115 ;; it is probably best to claim no function unit, which matches the
4117 (define_insn "toggle_sz"
4118 [(set (reg:PSI 48) (xor:PSI (reg:PSI 48) (const_int 1048576)))]
4122 (define_expand "addsf3"
4123 [(match_operand:SF 0 "arith_reg_operand" "")
4124 (match_operand:SF 1 "arith_reg_operand" "")
4125 (match_operand:SF 2 "arith_reg_operand" "")]
4127 "{ expand_sf_binop (&gen_addsf3_i, operands); DONE; }")
4129 (define_insn "addsf3_i"
4130 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4131 (plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
4132 (match_operand:SF 2 "arith_reg_operand" "f")))
4133 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4136 [(set_attr "type" "fp")
4137 (set_attr "fp_mode" "single")])
4139 (define_expand "subsf3"
4140 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4141 (match_operand:SF 1 "fp_arith_reg_operand" "")
4142 (match_operand:SF 2 "fp_arith_reg_operand" "")]
4144 "{ expand_sf_binop (&gen_subsf3_i, operands); DONE; }")
4146 (define_insn "subsf3_i"
4147 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4148 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
4149 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
4150 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4153 [(set_attr "type" "fp")
4154 (set_attr "fp_mode" "single")])
4156 ;; Unfortunately, the combiner is unable to cope with the USE of the FPSCR
4157 ;; register in feeding fp instructions. Thus, we cannot generate fmac for
4158 ;; mixed-precision SH4 targets. To allow it to be still generated for the
4159 ;; SH3E, we use a separate insn for SH3E mulsf3.
4161 (define_expand "mulsf3"
4162 [(match_operand:SF 0 "arith_reg_operand" "")
4163 (match_operand:SF 1 "arith_reg_operand" "")
4164 (match_operand:SF 2 "arith_reg_operand" "")]
4169 expand_sf_binop (&gen_mulsf3_i4, operands);
4171 emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
4175 (define_insn "mulsf3_i4"
4176 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4177 (mult:SF (match_operand:SF 1 "arith_reg_operand" "%0")
4178 (match_operand:SF 2 "arith_reg_operand" "f")))
4179 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4182 [(set_attr "type" "fp")
4183 (set_attr "fp_mode" "single")])
4185 (define_insn "mulsf3_ie"
4186 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4187 (mult:SF (match_operand:SF 1 "arith_reg_operand" "%0")
4188 (match_operand:SF 2 "arith_reg_operand" "f")))]
4189 "TARGET_SH3E && ! TARGET_SH4"
4191 [(set_attr "type" "fp")])
4193 (define_insn "*macsf3"
4194 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4195 (plus:SF (mult:SF (match_operand:SF 1 "arith_reg_operand" "%w")
4196 (match_operand:SF 2 "arith_reg_operand" "f"))
4197 (match_operand:SF 3 "arith_reg_operand" "0")))
4198 (use (match_operand:PSI 4 "fpscr_operand" "c"))]
4199 "TARGET_SH3E && ! TARGET_SH4"
4201 [(set_attr "type" "fp")
4202 (set_attr "fp_mode" "single")])
4204 (define_expand "divsf3"
4205 [(match_operand:SF 0 "arith_reg_operand" "")
4206 (match_operand:SF 1 "arith_reg_operand" "")
4207 (match_operand:SF 2 "arith_reg_operand" "")]
4209 "{ expand_sf_binop (&gen_divsf3_i, operands); DONE; }")
4211 (define_insn "divsf3_i"
4212 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4213 (div:SF (match_operand:SF 1 "arith_reg_operand" "0")
4214 (match_operand:SF 2 "arith_reg_operand" "f")))
4215 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4218 [(set_attr "type" "fdiv")
4219 (set_attr "fp_mode" "single")])
4221 (define_expand "floatsisf2"
4222 [(parallel [(set (match_operand:SF 0 "arith_reg_operand" "")
4223 (float:SF (match_operand:SI 1 "arith_reg_operand" "")))
4224 (use (match_dup 2))])]
4230 emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4233 operands[2] = get_fpscr_rtx ();
4236 (define_insn "floatsisf2_i4"
4237 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4238 (float:SF (match_operand:SI 1 "reg_no_subreg_operand" "y")))
4239 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4242 [(set_attr "type" "fp")
4243 (set_attr "fp_mode" "single")])
4245 ;; ??? This pattern is used nowhere. floatsisf always expands to floatsisf_i4.
4246 ;; (define_insn "*floatsisf2_ie"
4247 ;; [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4248 ;; (float:SF (reg:SI 22)))]
4249 ;; "TARGET_SH3E && ! TARGET_SH4"
4251 ;; [(set_attr "type" "fp")])
4253 (define_expand "fix_truncsfsi2"
4254 [(set (match_operand:SI 0 "register_operand" "=y")
4255 (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))]
4261 emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4266 (define_insn "fix_truncsfsi2_i4"
4267 [(set (match_operand:SI 0 "register_operand" "=y")
4268 (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4269 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4272 [(set_attr "type" "fp")
4273 (set_attr "fp_mode" "single")])
4275 ;; ??? This pattern is used nowhere. fix_truncsfsi2 always expands to
4276 ;; fix_truncsfsi2_i4.
4277 ;; (define_insn "fix_truncsfsi2_i4_2"
4278 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4279 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4280 ;; (use (reg:SI 48))
4281 ;; (clobber (reg:SI 22))]
4284 ;; [(set_attr "length" "4")
4285 ;; (set_attr "fp_mode" "single")])
4288 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4289 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4290 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4291 ;; (clobber (reg:SI 22))]
4293 ;; [(parallel [(set (reg:SI 22) (fix:SI (match_dup 1)))
4294 ;; (use (match_dup 2))])
4295 ;; (set (match_dup 0) (reg:SI 22))])
4297 (define_insn "*fixsfsi"
4298 [(set (match_operand:SI 0 "register_operand" "=y")
4299 (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))]
4300 "TARGET_SH3E && ! TARGET_SH4"
4302 [(set_attr "type" "fp")])
4304 (define_insn "cmpgtsf_t"
4305 [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "arith_reg_operand" "f")
4306 (match_operand:SF 1 "arith_reg_operand" "f")))]
4307 "TARGET_SH3E && ! TARGET_SH4"
4309 [(set_attr "type" "fp")
4310 (set_attr "fp_mode" "single")])
4312 (define_insn "cmpeqsf_t"
4313 [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
4314 (match_operand:SF 1 "arith_reg_operand" "f")))]
4315 "TARGET_SH3E && ! TARGET_SH4"
4317 [(set_attr "type" "fp")
4318 (set_attr "fp_mode" "single")])
4320 (define_insn "ieee_ccmpeqsf_t"
4321 [(set (reg:SI 18) (ior:SI (reg:SI 18)
4322 (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
4323 (match_operand:SF 1 "arith_reg_operand" "f"))))]
4324 "TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
4325 "* return output_ieee_ccmpeq (insn, operands);"
4326 [(set_attr "length" "4")])
4329 (define_insn "cmpgtsf_t_i4"
4330 [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "arith_reg_operand" "f")
4331 (match_operand:SF 1 "arith_reg_operand" "f")))
4332 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4335 [(set_attr "type" "fp")
4336 (set_attr "fp_mode" "single")])
4338 (define_insn "cmpeqsf_t_i4"
4339 [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
4340 (match_operand:SF 1 "arith_reg_operand" "f")))
4341 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4344 [(set_attr "type" "fp")
4345 (set_attr "fp_mode" "single")])
4347 (define_insn "*ieee_ccmpeqsf_t_4"
4348 [(set (reg:SI 18) (ior:SI (reg:SI 18)
4349 (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
4350 (match_operand:SF 1 "arith_reg_operand" "f"))))
4351 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4352 "TARGET_IEEE && TARGET_SH4"
4353 "* return output_ieee_ccmpeq (insn, operands);"
4354 [(set_attr "length" "4")
4355 (set_attr "fp_mode" "single")])
4357 (define_expand "cmpsf"
4358 [(set (reg:SI 18) (compare (match_operand:SF 0 "arith_operand" "")
4359 (match_operand:SF 1 "arith_operand" "")))]
4363 sh_compare_op0 = operands[0];
4364 sh_compare_op1 = operands[1];
4368 (define_expand "negsf2"
4369 [(match_operand:SF 0 "arith_reg_operand" "")
4370 (match_operand:SF 1 "arith_reg_operand" "")]
4372 "{ expand_sf_unop (&gen_negsf2_i, operands); DONE; }")
4374 (define_insn "negsf2_i"
4375 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4376 (neg:SF (match_operand:SF 1 "arith_reg_operand" "0")))
4377 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4380 [(set_attr "type" "fmove")
4381 (set_attr "fp_mode" "single")])
4383 (define_expand "sqrtsf2"
4384 [(match_operand:SF 0 "arith_reg_operand" "")
4385 (match_operand:SF 1 "arith_reg_operand" "")]
4387 "{ expand_sf_unop (&gen_sqrtsf2_i, operands); DONE; }")
4389 (define_insn "sqrtsf2_i"
4390 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4391 (sqrt:SF (match_operand:SF 1 "arith_reg_operand" "0")))
4392 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4395 [(set_attr "type" "fdiv")
4396 (set_attr "fp_mode" "single")])
4398 (define_expand "abssf2"
4399 [(match_operand:SF 0 "arith_reg_operand" "")
4400 (match_operand:SF 1 "arith_reg_operand" "")]
4402 "{ expand_sf_unop (&gen_abssf2_i, operands); DONE; }")
4404 (define_insn "abssf2_i"
4405 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4406 (abs:SF (match_operand:SF 1 "arith_reg_operand" "0")))
4407 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4410 [(set_attr "type" "fmove")
4411 (set_attr "fp_mode" "single")])
4413 (define_expand "adddf3"
4414 [(match_operand:DF 0 "arith_reg_operand" "")
4415 (match_operand:DF 1 "arith_reg_operand" "")
4416 (match_operand:DF 2 "arith_reg_operand" "")]
4418 "{ expand_df_binop (&gen_adddf3_i, operands); DONE; }")
4420 (define_insn "adddf3_i"
4421 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4422 (plus:DF (match_operand:DF 1 "arith_reg_operand" "%0")
4423 (match_operand:DF 2 "arith_reg_operand" "f")))
4424 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4427 [(set_attr "type" "dfp_arith")
4428 (set_attr "fp_mode" "double")])
4430 (define_expand "subdf3"
4431 [(match_operand:DF 0 "arith_reg_operand" "")
4432 (match_operand:DF 1 "arith_reg_operand" "")
4433 (match_operand:DF 2 "arith_reg_operand" "")]
4435 "{ expand_df_binop (&gen_subdf3_i, operands); DONE; }")
4437 (define_insn "subdf3_i"
4438 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4439 (minus:DF (match_operand:DF 1 "arith_reg_operand" "0")
4440 (match_operand:DF 2 "arith_reg_operand" "f")))
4441 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4444 [(set_attr "type" "dfp_arith")
4445 (set_attr "fp_mode" "double")])
4447 (define_expand "muldf3"
4448 [(match_operand:DF 0 "arith_reg_operand" "")
4449 (match_operand:DF 1 "arith_reg_operand" "")
4450 (match_operand:DF 2 "arith_reg_operand" "")]
4452 "{ expand_df_binop (&gen_muldf3_i, operands); DONE; }")
4454 (define_insn "muldf3_i"
4455 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4456 (mult:DF (match_operand:DF 1 "arith_reg_operand" "%0")
4457 (match_operand:DF 2 "arith_reg_operand" "f")))
4458 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4461 [(set_attr "type" "dfp_arith")
4462 (set_attr "fp_mode" "double")])
4464 (define_expand "divdf3"
4465 [(match_operand:DF 0 "arith_reg_operand" "")
4466 (match_operand:DF 1 "arith_reg_operand" "")
4467 (match_operand:DF 2 "arith_reg_operand" "")]
4469 "{ expand_df_binop (&gen_divdf3_i, operands); DONE; }")
4471 (define_insn "divdf3_i"
4472 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4473 (div:DF (match_operand:DF 1 "arith_reg_operand" "0")
4474 (match_operand:DF 2 "arith_reg_operand" "f")))
4475 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4478 [(set_attr "type" "dfdiv")
4479 (set_attr "fp_mode" "double")])
4481 (define_expand "floatsidf2"
4482 [(match_operand:DF 0 "arith_reg_operand" "")
4483 (match_operand:SI 1 "arith_reg_operand" "")]
4487 emit_df_insn (gen_floatsidf2_i (operands[0], operands[1], get_fpscr_rtx ()));
4491 (define_insn "floatsidf2_i"
4492 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4493 (float:DF (match_operand:SI 1 "reg_no_subreg_operand" "y")))
4494 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4497 [(set_attr "type" "dfp_conv")
4498 (set_attr "fp_mode" "double")])
4500 (define_expand "fix_truncdfsi2"
4501 [(match_operand:SI 0 "arith_reg_operand" "=r")
4502 (match_operand:DF 1 "arith_reg_operand" "f")]
4506 emit_df_insn (gen_fix_truncdfsi2_i (operands[0], operands[1], get_fpscr_rtx ()));
4510 (define_insn "fix_truncdfsi2_i"
4511 [(set (match_operand:SI 0 "register_operand" "=y")
4512 (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4513 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4516 [(set_attr "type" "dfp_conv")
4517 (set_attr "fp_mode" "double")])
4519 ;; ??? This pattern is used nowhere. fix_truncdfsi2 always expands to
4520 ;; fix_truncdfsi2_i.
4521 ;; (define_insn "fix_truncdfsi2_i4"
4522 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4523 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4524 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4525 ;; (clobber (reg:SI 22))]
4528 ;; [(set_attr "length" "4")
4529 ;; (set_attr "fp_mode" "double")])
4532 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4533 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4534 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4535 ;; (clobber (reg:SI 22))]
4537 ;; [(parallel [(set (reg:SI 22) (fix:SI (match_dup 1)))
4538 ;; (use (match_dup 2))])
4539 ;; (set (match_dup 0) (reg:SI 22))])
4541 (define_insn "cmpgtdf_t"
4542 [(set (reg:SI 18) (gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
4543 (match_operand:DF 1 "arith_reg_operand" "f")))
4544 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4547 [(set_attr "type" "dfp_cmp")
4548 (set_attr "fp_mode" "double")])
4550 (define_insn "cmpeqdf_t"
4551 [(set (reg:SI 18) (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4552 (match_operand:DF 1 "arith_reg_operand" "f")))
4553 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4556 [(set_attr "type" "dfp_cmp")
4557 (set_attr "fp_mode" "double")])
4559 (define_insn "*ieee_ccmpeqdf_t"
4560 [(set (reg:SI 18) (ior:SI (reg:SI 18)
4561 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4562 (match_operand:DF 1 "arith_reg_operand" "f"))))
4563 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4564 "TARGET_IEEE && TARGET_SH4"
4565 "* return output_ieee_ccmpeq (insn, operands);"
4566 [(set_attr "length" "4")
4567 (set_attr "fp_mode" "double")])
4569 (define_expand "cmpdf"
4570 [(set (reg:SI 18) (compare (match_operand:DF 0 "arith_operand" "")
4571 (match_operand:DF 1 "arith_operand" "")))]
4575 sh_compare_op0 = operands[0];
4576 sh_compare_op1 = operands[1];
4580 (define_expand "negdf2"
4581 [(match_operand:DF 0 "arith_reg_operand" "")
4582 (match_operand:DF 1 "arith_reg_operand" "")]
4584 "{ expand_df_unop (&gen_negdf2_i, operands); DONE; }")
4586 (define_insn "negdf2_i"
4587 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4588 (neg:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4589 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4592 [(set_attr "type" "fmove")
4593 (set_attr "fp_mode" "double")])
4595 (define_expand "sqrtdf2"
4596 [(match_operand:DF 0 "arith_reg_operand" "")
4597 (match_operand:DF 1 "arith_reg_operand" "")]
4599 "{ expand_df_unop (&gen_sqrtdf2_i, operands); DONE; }")
4601 (define_insn "sqrtdf2_i"
4602 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4603 (sqrt:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4604 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4607 [(set_attr "type" "dfdiv")
4608 (set_attr "fp_mode" "double")])
4610 (define_expand "absdf2"
4611 [(match_operand:DF 0 "arith_reg_operand" "")
4612 (match_operand:DF 1 "arith_reg_operand" "")]
4614 "{ expand_df_unop (&gen_absdf2_i, operands); DONE; }")
4616 (define_insn "absdf2_i"
4617 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4618 (abs:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4619 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4622 [(set_attr "type" "fmove")
4623 (set_attr "fp_mode" "double")])
4625 (define_expand "extendsfdf2"
4626 [(match_operand:DF 0 "arith_reg_operand" "")
4627 (match_operand:SF 1 "arith_reg_operand" "")]
4631 emit_df_insn (gen_extendsfdf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4635 (define_insn "extendsfdf2_i4"
4636 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4637 (float_extend:DF (match_operand:SF 1 "reg_no_subreg_operand" "y")))
4638 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4641 [(set_attr "type" "fp")
4642 (set_attr "fp_mode" "double")])
4644 (define_expand "truncdfsf2"
4645 [(match_operand:SF 0 "arith_reg_operand" "")
4646 (match_operand:DF 1 "arith_reg_operand" "")]
4650 emit_df_insn (gen_truncdfsf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4654 (define_insn "truncdfsf2_i4"
4655 [(set (match_operand:SF 0 "register_operand" "=y")
4656 (float_truncate:SF (match_operand:DF 1 "arith_reg_operand" "f")))
4657 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4660 [(set_attr "type" "fp")
4661 (set_attr "fp_mode" "double")])
4663 ;; Bit field extract patterns. These give better code for packed bitfields,
4664 ;; because they allow auto-increment addresses to be generated.
4666 (define_expand "insv"
4667 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
4668 (match_operand:SI 1 "immediate_operand" "")
4669 (match_operand:SI 2 "immediate_operand" ""))
4670 (match_operand:SI 3 "general_operand" ""))]
4671 "! TARGET_LITTLE_ENDIAN"
4674 rtx addr_target, orig_address, shift_reg;
4677 /* ??? expmed doesn't care for non-register predicates. */
4678 if (! memory_operand (operands[0], VOIDmode)
4679 || ! immediate_operand (operands[1], VOIDmode)
4680 || ! immediate_operand (operands[2], VOIDmode)
4681 || ! general_operand (operands[3], VOIDmode))
4683 /* If this isn't a 16 / 24 / 32 bit field, or if
4684 it doesn't start on a byte boundary, then fail. */
4685 size = INTVAL (operands[1]);
4686 if (size < 16 || size > 32 || size % 8 != 0
4687 || (INTVAL (operands[2]) % 8) != 0)
4691 orig_address = XEXP (operands[0], 0);
4692 shift_reg = gen_reg_rtx (SImode);
4693 emit_insn (gen_movsi (shift_reg, operands[3]));
4694 addr_target = copy_addr_to_reg (plus_constant (orig_address, size - 1));
4696 operands[0] = change_address (operands[0], QImode, addr_target);
4697 emit_insn (gen_movqi (operands[0], gen_rtx_SUBREG (QImode, shift_reg, 0)));
4701 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
4702 emit_insn (gen_addsi3 (addr_target, addr_target, GEN_INT (-1)));
4703 emit_insn (gen_movqi (operands[0],
4704 gen_rtx_SUBREG (QImode, shift_reg, 0)));
4710 ;; -------------------------------------------------------------------------
4712 ;; -------------------------------------------------------------------------
4714 ;; This matches cases where a stack pointer increment at the start of the
4715 ;; epilogue combines with a stack slot read loading the return value.
4718 [(set (match_operand:SI 0 "arith_reg_operand" "")
4719 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
4720 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
4721 "REGNO (operands[1]) != REGNO (operands[0])"
4724 ;; See the comment on the dt combiner pattern above.
4727 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4728 (plus:SI (match_dup 0)
4731 (eq:SI (match_dup 0)
4736 ;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn'
4737 ;; to `mov #k,r0; mov.l @(r0,r15),rn'. These sequences are generated by
4738 ;; reload when the constant is too large for a reg+offset address.
4740 ;; ??? We would get much better code if this was done in reload. This would
4741 ;; require modifying find_reloads_address to recognize that if the constant
4742 ;; is out-of-range for an immediate add, then we get better code by reloading
4743 ;; the constant into a register than by reloading the sum into a register,
4744 ;; since the former is one instruction shorter if the address does not need
4745 ;; to be offsettable. Unfortunately this does not work, because there is
4746 ;; only one register, r0, that can be used as an index register. This register
4747 ;; is also the function return value register. So, if we try to force reload
4748 ;; to use double-reg addresses, then we end up with some instructions that
4749 ;; need to use r0 twice. The only way to fix this is to change the calling
4750 ;; convention so that r0 is not used to return values.
4753 [(set (match_operand:SI 0 "register_operand" "=r")
4754 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4755 (set (mem:SI (match_dup 0))
4756 (match_operand:SI 2 "general_movsrc_operand" ""))]
4757 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4758 "mov.l %2,@(%0,%1)")
4761 [(set (match_operand:SI 0 "register_operand" "=r")
4762 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4763 (set (match_operand:SI 2 "general_movdst_operand" "")
4764 (mem:SI (match_dup 0)))]
4765 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4766 "mov.l @(%0,%1),%2")
4769 [(set (match_operand:SI 0 "register_operand" "=r")
4770 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4771 (set (mem:HI (match_dup 0))
4772 (match_operand:HI 2 "general_movsrc_operand" ""))]
4773 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4774 "mov.w %2,@(%0,%1)")
4777 [(set (match_operand:SI 0 "register_operand" "=r")
4778 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4779 (set (match_operand:HI 2 "general_movdst_operand" "")
4780 (mem:HI (match_dup 0)))]
4781 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4782 "mov.w @(%0,%1),%2")
4785 [(set (match_operand:SI 0 "register_operand" "=r")
4786 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4787 (set (mem:QI (match_dup 0))
4788 (match_operand:QI 2 "general_movsrc_operand" ""))]
4789 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4790 "mov.b %2,@(%0,%1)")
4793 [(set (match_operand:SI 0 "register_operand" "=r")
4794 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4795 (set (match_operand:QI 2 "general_movdst_operand" "")
4796 (mem:QI (match_dup 0)))]
4797 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4798 "mov.b @(%0,%1),%2")
4801 [(set (match_operand:SI 0 "register_operand" "=r")
4802 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4803 (set (mem:SF (match_dup 0))
4804 (match_operand:SF 2 "general_movsrc_operand" ""))]
4805 "REGNO (operands[0]) == 0
4806 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
4807 || (GET_CODE (operands[2]) == SUBREG
4808 && REGNO (SUBREG_REG (operands[2])) < 16))
4809 && reg_unused_after (operands[0], insn)"
4810 "mov.l %2,@(%0,%1)")
4813 [(set (match_operand:SI 0 "register_operand" "=r")
4814 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4815 (set (match_operand:SF 2 "general_movdst_operand" "")
4817 (mem:SF (match_dup 0)))]
4818 "REGNO (operands[0]) == 0
4819 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
4820 || (GET_CODE (operands[2]) == SUBREG
4821 && REGNO (SUBREG_REG (operands[2])) < 16))
4822 && reg_unused_after (operands[0], insn)"
4823 "mov.l @(%0,%1),%2")
4826 [(set (match_operand:SI 0 "register_operand" "=r")
4827 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4828 (set (mem:SF (match_dup 0))
4829 (match_operand:SF 2 "general_movsrc_operand" ""))]
4830 "REGNO (operands[0]) == 0
4831 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) >= FIRST_FP_REG)
4832 || (GET_CODE (operands[2]) == SUBREG
4833 && REGNO (SUBREG_REG (operands[2])) >= FIRST_FP_REG))
4834 && reg_unused_after (operands[0], insn)"
4835 "fmov{.s|} %2,@(%0,%1)")
4838 [(set (match_operand:SI 0 "register_operand" "=r")
4839 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4840 (set (match_operand:SF 2 "general_movdst_operand" "")
4842 (mem:SF (match_dup 0)))]
4843 "REGNO (operands[0]) == 0
4844 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) >= FIRST_FP_REG)
4845 || (GET_CODE (operands[2]) == SUBREG
4846 && REGNO (SUBREG_REG (operands[2])) >= FIRST_FP_REG))
4847 && reg_unused_after (operands[0], insn)"
4848 "fmov{.s|} @(%0,%1),%2")
4850 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF). */
4851 (define_insn "sp_switch_1"
4858 xoperands[0] = sp_switch;
4859 output_asm_insn (\"mov.l r0,@-r15\;mov.l %0,r0\", xoperands);
4860 output_asm_insn (\"mov.l @r0,r0\;mov.l r15,@-r0\", xoperands);
4861 return \"mov r0,r15\";
4863 [(set_attr "length" "10")])
4865 ;; Switch back to the original stack for interrupt functions with the
4866 ;; sp_switch attribute. */
4867 (define_insn "sp_switch_2"
4870 "mov.l @r15+,r15\;mov.l @r15+,r0"
4871 [(set_attr "length" "4")])