1 ;;- Machine description for the Hitachi SH.
2 ;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
5 ;; Improved by Jim Wilson (wilson@cygnus.com).
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
25 ;; ??? Should prepend a * to all pattern names which are not used.
26 ;; This will make the compiler smaller, and rebuilds after changes faster.
28 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
29 ;; sequences. Especially the sequences for arithmetic right shifts.
31 ;; ??? Should check all DImode patterns for consistency and usefulness.
33 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
34 ;; way to generate them.
36 ;; ??? The cmp/str instruction is not supported. Perhaps it can be used
37 ;; for a str* inline function.
39 ;; BSR is not generated by the compiler proper, but when relaxing, it
40 ;; generates .uses pseudo-ops that allow linker relaxation to create
41 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
43 ;; Special constraints for SH machine description:
50 ;; Special formats used for outputting SH instructions:
52 ;; %. -- print a .s if insn needs delay slot
53 ;; %@ -- print rte/rts if is/isn't an interrupt function
54 ;; %# -- output a nop if there is nothing to put in the delay slot
55 ;; %O -- print a constant without the #
56 ;; %R -- print the lsw reg of a double
57 ;; %S -- print the msw reg of a double
58 ;; %T -- print next word of a double REG or MEM
60 ;; Special predicates:
62 ;; arith_operand -- operand is valid source for arithmetic op
63 ;; arith_reg_operand -- operand is valid register for arithmetic op
64 ;; general_movdst_operand -- operand is valid move destination
65 ;; general_movsrc_operand -- operand is valid move source
66 ;; logical_operand -- operand is valid source for logical op
67 ;; -------------------------------------------------------------------------
69 ;; -------------------------------------------------------------------------
74 "sh1,sh2,sh3,sh3e,sh4"
75 (const (symbol_ref "sh_cpu_attr")))
77 (define_attr "endian" "big,little"
78 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
79 (const_string "little") (const_string "big"))))
81 ;; Indicate if the default fpu mode is single precision.
82 (define_attr "fpu_single" "yes,no"
83 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
84 (const_string "yes") (const_string "no"))))
86 (define_attr "fmovd" "yes,no"
87 (const (if_then_else (symbol_ref "TARGET_FMOVD")
88 (const_string "yes") (const_string "no"))))
90 (define_attr "issues" "1,2"
91 (const (if_then_else (symbol_ref "TARGET_SUPERSCALAR") (const_string "2") (const_string "1"))))
93 ;; cbranch conditional branch instructions
94 ;; jump unconditional jumps
95 ;; arith ordinary arithmetic
96 ;; arith3 a compound insn that behaves similarly to a sequence of
97 ;; three insns of type arith
98 ;; arith3b like above, but might end with a redirected branch
100 ;; load_si Likewise, SImode variant for general register.
102 ;; move register to register
103 ;; fmove register to register, floating point
104 ;; smpy word precision integer multiply
105 ;; dmpy longword or doublelongword precision integer multiply
107 ;; pload load of pr reg, which can't be put into delay slot of rts
108 ;; pstore store of pr reg, which can't be put into delay slot of jsr
109 ;; pcload pc relative load of constant value
110 ;; pcload_si Likewise, SImode variant for general register.
111 ;; rte return from exception
112 ;; sfunc special function call with known used registers
113 ;; call function call
115 ;; fdiv floating point divide (or square root)
116 ;; gp_fpul move between general purpose register and fpul
117 ;; dfp_arith, dfp_cmp,dfp_conv
118 ;; dfdiv double precision floating point divide (or square root)
119 ;; nil no-op move, will be deleted.
122 "cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,other,load,load_si,store,move,fmove,smpy,dmpy,return,pload,pstore,pcload,pcload_si,rte,sfunc,call,fp,fdiv,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,nil"
123 (const_string "other"))
125 ;; Indicate what precision must be selected in fpscr for this insn, if any.
127 (define_attr "fp_mode" "single,double,none" (const_string "none"))
129 ; If a conditional branch destination is within -252..258 bytes away
130 ; from the instruction it can be 2 bytes long. Something in the
131 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
132 ; branches are initially assumed to be 16 bytes long.
133 ; In machine_dependent_reorg, we split all branches that are longer than
136 ;; The maximum range used for SImode constant pool entrys is 1018. A final
137 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
138 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
139 ;; instruction around the pool table, 2 bytes of alignment before the table,
140 ;; and 30 bytes of alignment after the table. That gives a maximum total
141 ;; pool size of 1058 bytes.
142 ;; Worst case code/pool content size ratio is 1:2 (using asms).
143 ;; Thus, in the worst case, there is one instruction in front of a maximum
144 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
145 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
146 ;; If we have a forward branch, the initial table will be put after the
147 ;; unconditional branch.
149 ;; ??? We could do much better by keeping track of the actual pcloads within
150 ;; the branch range and in the pcload range in front of the branch range.
152 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
154 (define_attr "short_cbranch_p" "no,yes"
155 (cond [(ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
157 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
159 (ne (symbol_ref "NEXT_INSN (PREV_INSN (insn)) != insn") (const_int 0))
161 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
163 ] (const_string "no")))
165 (define_attr "med_branch_p" "no,yes"
166 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
169 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
171 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
174 ] (const_string "no")))
176 (define_attr "med_cbranch_p" "no,yes"
177 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
180 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
182 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
185 ] (const_string "no")))
187 (define_attr "braf_branch_p" "no,yes"
188 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
190 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
193 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
195 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
198 ] (const_string "no")))
200 (define_attr "braf_cbranch_p" "no,yes"
201 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
203 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
206 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
208 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
211 ] (const_string "no")))
213 ; An unconditional jump in the range -4092..4098 can be 2 bytes long.
214 ; For wider ranges, we need a combination of a code and a data part.
215 ; If we can get a scratch register for a long range jump, the code
216 ; part can be 4 bytes long; otherwise, it must be 8 bytes long.
217 ; If the jump is in the range -32764..32770, the data part can be 2 bytes
218 ; long; otherwise, it must be 6 bytes long.
220 ; All other instructions are two bytes long by default.
222 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
223 ;; but getattrtab doesn't understand this.
224 (define_attr "length" ""
225 (cond [(eq_attr "type" "cbranch")
226 (cond [(eq_attr "short_cbranch_p" "yes")
228 (eq_attr "med_cbranch_p" "yes")
230 (eq_attr "braf_cbranch_p" "yes")
232 ;; ??? using pc is not computed transitively.
233 (ne (match_dup 0) (match_dup 0))
236 (eq_attr "type" "jump")
237 (cond [(eq_attr "med_branch_p" "yes")
239 (and (eq (symbol_ref "GET_CODE (PREV_INSN (insn))")
241 (eq (symbol_ref "INSN_CODE (PREV_INSN (insn))")
242 (symbol_ref "code_for_indirect_jump_scratch")))
243 (if_then_else (eq_attr "braf_branch_p" "yes")
246 (eq_attr "braf_branch_p" "yes")
248 ;; ??? using pc is not computed transitively.
249 (ne (match_dup 0) (match_dup 0))
254 ;; (define_function_unit {name} {num-units} {n-users} {test}
255 ;; {ready-delay} {issue-delay} [{conflict-list}])
257 ;; Load and store instructions save a cycle if they are aligned on a
258 ;; four byte boundary. Using a function unit for stores encourages
259 ;; gcc to separate load and store instructions by one instruction,
260 ;; which makes it more likely that the linker will be able to word
261 ;; align them when relaxing.
263 ;; Loads have a latency of two.
264 ;; However, call insns can have a delay slot, so that we want one more
265 ;; insn to be scheduled between the load of the function address and the call.
266 ;; This is equivalent to a latency of three.
267 ;; We cannot use a conflict list for this, because we need to distinguish
268 ;; between the actual call address and the function arguments.
269 ;; ADJUST_COST can only properly handle reductions of the cost, so we
270 ;; use a latency of three here.
271 ;; We only do this for SImode loads of general registers, to make the work
272 ;; for ADJUST_COST easier.
273 (define_function_unit "memory" 1 0
274 (and (eq_attr "issues" "1")
275 (eq_attr "type" "load_si,pcload_si"))
277 (define_function_unit "memory" 1 0
278 (and (eq_attr "issues" "1")
279 (eq_attr "type" "load,pcload,pload,store,pstore"))
282 (define_function_unit "int" 1 0
283 (and (eq_attr "issues" "1") (eq_attr "type" "arith3,arith3b")) 3 3)
285 (define_function_unit "int" 1 0
286 (and (eq_attr "issues" "1") (eq_attr "type" "dyn_shift")) 2 2)
288 (define_function_unit "int" 1 0
289 (and (eq_attr "issues" "1") (eq_attr "type" "!arith3,arith3b,dyn_shift")) 1 1)
291 ;; ??? These are approximations.
292 (define_function_unit "mpy" 1 0
293 (and (eq_attr "issues" "1") (eq_attr "type" "smpy")) 2 2)
294 (define_function_unit "mpy" 1 0
295 (and (eq_attr "issues" "1") (eq_attr "type" "dmpy")) 3 3)
297 (define_function_unit "fp" 1 0
298 (and (eq_attr "issues" "1") (eq_attr "type" "fp,fmove")) 2 1)
299 (define_function_unit "fp" 1 0
300 (and (eq_attr "issues" "1") (eq_attr "type" "fdiv")) 13 12)
304 ;; The SH4 is a dual-issue implementation, thus we have to multiply all
305 ;; costs by at least two.
306 ;; There will be single increments of the modeled that don't correspond
307 ;; to the actual target ;; whenever two insns to be issued depend one a
308 ;; single resource, and the scheduler picks to be the first one.
309 ;; If we multiplied the costs just by two, just two of these single
310 ;; increments would amount to an actual cycle. By picking a larger
311 ;; factor, we can ameliorate the effect; However, we then have to make sure
312 ;; that only two insns are modeled as issued per actual cycle.
313 ;; Moreover, we need a way to specify the latency of insns that don't
314 ;; use an actual function unit.
315 ;; We use an 'issue' function unit to do that, and a cost factor of 10.
317 (define_function_unit "issue" 2 0
318 (and (eq_attr "issues" "2") (eq_attr "type" "!nil,arith3"))
321 (define_function_unit "issue" 2 0
322 (and (eq_attr "issues" "2") (eq_attr "type" "arith3"))
325 ;; There is no point in providing exact scheduling information about branches,
326 ;; because they are at the starts / ends of basic blocks anyways.
328 ;; Some insns cannot be issued before/after another insn in the same cycle,
329 ;; irrespective of the type of the other insn.
331 ;; default is dual-issue, but can't be paired with an insn that
332 ;; uses multiple function units.
333 (define_function_unit "single_issue" 1 0
334 (and (eq_attr "issues" "2")
335 (eq_attr "type" "!smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul,call,sfunc,arith3,arith3b"))
337 [(eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul")])
339 (define_function_unit "single_issue" 1 0
340 (and (eq_attr "issues" "2")
341 (eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul"))
345 ;; arith3 insns are always pairable at the start, but not inecessarily at
346 ;; the end; however, there doesn;t seem to be a way to express that.
347 (define_function_unit "single_issue" 1 0
348 (and (eq_attr "issues" "2")
349 (eq_attr "type" "arith3"))
353 ;; arith3b insn are pairable at the end and have latency that prevents pairing
354 ;; with the following branch, but we don't want this latency be respected;
355 ;; When the following branch is immediately adjacent, we can redirect the
356 ;; internal branch, which is likly to be a larger win.
357 (define_function_unit "single_issue" 1 0
358 (and (eq_attr "issues" "2")
359 (eq_attr "type" "arith3b"))
363 ;; calls introduce a longisch delay that is likely to flush the pipelines.
364 (define_function_unit "single_issue" 1 0
365 (and (eq_attr "issues" "2")
366 (eq_attr "type" "call,sfunc"))
368 [(eq_attr "type" "!call") (eq_attr "type" "call")])
370 ;; Load and store instructions have no alignment peculiarities for the SH4,
371 ;; but they use the load-store unit, which they share with the fmove type
372 ;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
373 ;; Loads have a latency of two.
374 ;; However, call insns can only paired with a preceding insn, and have
375 ;; a delay slot, so that we want two more insns to be scheduled between the
376 ;; load of the function address and the call. This is equivalent to a
378 ;; We cannot use a conflict list for this, because we need to distinguish
379 ;; between the actual call address and the function arguments.
380 ;; ADJUST_COST can only properly handle reductions of the cost, so we
381 ;; use a latency of three here, which gets multiplied by 10 to yield 30.
382 ;; We only do this for SImode loads of general registers, to make the work
383 ;; for ADJUST_COST easier.
385 ;; When specifying different latencies for different insns using the
386 ;; the same function unit, genattrtab.c assumes a 'FIFO constraint'
387 ;; so that the blockage is at least READY-COST (E) + 1 - READY-COST (C)
388 ;; for an executing insn E and a candidate insn C.
389 ;; Therefore, we define three different function units for load_store:
390 ;; load_store, load and load_si.
392 (define_function_unit "load_si" 1 0
393 (and (eq_attr "issues" "2")
394 (eq_attr "type" "load_si,pcload_si")) 30 10)
395 (define_function_unit "load" 1 0
396 (and (eq_attr "issues" "2")
397 (eq_attr "type" "load,pcload,pload")) 20 10)
398 (define_function_unit "load_store" 1 0
399 (and (eq_attr "issues" "2")
400 (eq_attr "type" "load_si,pcload_si,load,pcload,pload,store,pstore,fmove"))
403 (define_function_unit "int" 1 0
404 (and (eq_attr "issues" "2") (eq_attr "type" "arith,dyn_shift")) 10 10)
406 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
407 ;; spurious FIFO constraint; the multiply instructions use the "int"
408 ;; unit actually only for two cycles.
409 (define_function_unit "int" 1 0
410 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 20 20)
412 ;; We use a fictous "mpy" unit to express the actual latency.
413 (define_function_unit "mpy" 1 0
414 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 20)
416 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
417 ;; spurious FIFO constraint.
418 (define_function_unit "int" 1 0
419 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 10 10)
421 ;; We use a fictous "gp_fpul" unit to express the actual latency.
422 (define_function_unit "gp_fpul" 1 0
423 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 20 10)
425 ;; ??? multiply uses the floating point unit, but with a two cycle delay.
426 ;; Thus, a simple single-precision fp operation could finish if issued in
427 ;; the very next cycle, but stalls when issued two or three cycles later.
428 ;; Similarily, a divide / sqrt can work without stalls if issued in
429 ;; the very next cycle, while it would have to block if issued two or
430 ;; three cycles later.
431 ;; There is no way to model this with gcc's function units. This problem is
432 ;; actually mentioned in md.texi. Tackling this problem requires first that
433 ;; it is possible to speak about the target in an open discussion.
435 ;; However, simple double-precision operations always conflict.
437 (define_function_unit "fp" 1 0
438 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 40
439 [(eq_attr "type" "dfp_cmp,dfp_conv,dfp_arith")])
441 ;; The "fp" unit is for pipeline stages F1 and F2.
443 (define_function_unit "fp" 1 0
444 (and (eq_attr "issues" "2") (eq_attr "type" "fp")) 30 10)
446 ;; Again, we have to pretend a lower latency for the "fp" unit to avoid a
447 ;; spurious FIFO constraint; the bulk of the fdiv type insns executes in
449 (define_function_unit "fp" 1 0
450 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 30 10)
452 ;; The "fdiv" function unit models the aggregate effect of the F1, F2 and F3
453 ;; pipeline stages on the pipelining of fdiv/fsqrt insns.
454 ;; We also use it to give the actual latency here.
455 ;; fsqrt is actually one cycle faster than fdiv (and the value used here),
456 ;; but that will hardly matter in practice for scheduling.
457 (define_function_unit "fdiv" 1 0
458 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 120 100)
460 ;; There is again a late use of the "fp" unit by [d]fdiv type insns
461 ;; that we can't express.
463 (define_function_unit "fp" 1 0
464 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_cmp,dfp_conv")) 40 20)
466 (define_function_unit "fp" 1 0
467 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_arith")) 80 60)
469 (define_function_unit "fp" 1 0
470 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 10)
472 (define_function_unit "fdiv" 1 0
473 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 210)
475 ; Definitions for filling branch delay slots.
477 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
479 ;; ??? This should be (nil) instead of (const_int 0)
480 (define_attr "hit_stack" "yes,no"
481 (cond [(eq (symbol_ref "find_regno_note (insn, REG_INC, 15)") (const_int 0))
483 (const_string "yes")))
485 (define_attr "interrupt_function" "no,yes"
486 (const (symbol_ref "pragma_interrupt")))
488 (define_attr "in_delay_slot" "yes,no"
489 (cond [(eq_attr "type" "cbranch") (const_string "no")
490 (eq_attr "type" "pcload,pcload_si") (const_string "no")
491 (eq_attr "needs_delay_slot" "yes") (const_string "no")
492 (eq_attr "length" "2") (const_string "yes")
493 ] (const_string "no")))
495 (define_attr "is_sfunc" ""
496 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
499 (eq_attr "needs_delay_slot" "yes")
500 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
502 ;; On the SH and SH2, the rte instruction reads the return pc from the stack,
503 ;; and thus we can't put a pop instruction in its delay slot.
504 ;; ??? On the SH3, the rte instruction does not use the stack, so a pop
505 ;; instruction can go in the delay slot.
507 ;; Since a normal return (rts) implicitly uses the PR register,
508 ;; we can't allow PR register loads in an rts delay slot.
511 (eq_attr "type" "return")
512 [(and (eq_attr "in_delay_slot" "yes")
513 (ior (and (eq_attr "interrupt_function" "no")
514 (eq_attr "type" "!pload"))
515 (and (eq_attr "interrupt_function" "yes")
516 (eq_attr "hit_stack" "no")))) (nil) (nil)])
518 ;; Since a call implicitly uses the PR register, we can't allow
519 ;; a PR register store in a jsr delay slot.
522 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
523 [(and (eq_attr "in_delay_slot" "yes")
524 (eq_attr "type" "!pstore")) (nil) (nil)])
526 ;; Say that we have annulled true branches, since this gives smaller and
527 ;; faster code when branches are predicted as not taken.
530 (and (eq_attr "type" "cbranch")
531 (ne (symbol_ref "TARGET_SH2") (const_int 0)))
532 [(eq_attr "in_delay_slot" "yes") (eq_attr "in_delay_slot" "yes") (nil)])
534 ;; -------------------------------------------------------------------------
535 ;; SImode signed integer comparisons
536 ;; -------------------------------------------------------------------------
540 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
541 (match_operand:SI 1 "arith_operand" "L,r"))
546 ;; ??? Perhaps should only accept reg/constant if the register is reg 0.
547 ;; That would still allow reload to create cmpi instructions, but would
548 ;; perhaps allow forcing the constant into a register when that is better.
549 ;; Probably should use r0 for mem/imm compares, but force constant into a
550 ;; register for pseudo/imm compares.
552 (define_insn "cmpeqsi_t"
553 [(set (reg:SI 18) (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
554 (match_operand:SI 1 "arith_operand" "N,rI,r")))]
561 (define_insn "cmpeqsi_ior_t"
564 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
565 (match_operand:SI 1 "arith_operand" "N,rI,r"))))]
570 bt .+4\;cmp/eq %1,%0"
571 [(set_attr "length" "4")])
573 (define_insn "cmpeqsi_and_t"
576 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
577 (match_operand:SI 1 "arith_operand" "N,rI,r"))))]
582 bf .+4\;cmp/eq %1,%0"
583 [(set_attr "length" "4")])
585 (define_insn "cmpgtsi_t"
586 [(set (reg:SI 18) (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
587 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
593 (define_insn "cmpgesi_t"
594 [(set (reg:SI 18) (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
595 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
601 ;; -------------------------------------------------------------------------
602 ;; SImode unsigned integer comparisons
603 ;; -------------------------------------------------------------------------
605 (define_insn "cmpgeusi_t"
606 [(set (reg:SI 18) (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
607 (match_operand:SI 1 "arith_reg_operand" "r")))]
611 (define_insn "cmpgtusi_t"
612 [(set (reg:SI 18) (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
613 (match_operand:SI 1 "arith_reg_operand" "r")))]
617 ;; We save the compare operands in the cmpxx patterns and use them when
618 ;; we generate the branch.
620 (define_expand "cmpsi"
621 [(set (reg:SI 18) (compare (match_operand:SI 0 "arith_operand" "")
622 (match_operand:SI 1 "arith_operand" "")))]
626 sh_compare_op0 = operands[0];
627 sh_compare_op1 = operands[1];
631 ;; -------------------------------------------------------------------------
632 ;; DImode signed integer comparisons
633 ;; -------------------------------------------------------------------------
635 ;; ??? Could get better scheduling by splitting the initial test from the
636 ;; rest of the insn after reload. However, the gain would hardly justify
637 ;; the sh.md size increase necessary to do that.
641 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
642 (match_operand:DI 1 "arith_operand" "r"))
645 "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
647 [(set_attr "length" "6")
648 (set_attr "type" "arith3b")])
650 (define_insn "cmpeqdi_t"
651 [(set (reg:SI 18) (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
652 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
655 [(set_attr "length" "6")
656 (set_attr "type" "arith3b")])
659 [(set (reg:SI 18) (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
660 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
662 [(set (reg:SI 18) (eq:SI (match_dup 2) (match_dup 3)))
665 (eq:SI (match_dup 4) (match_dup 5))))]
669 = gen_rtx_REG (SImode,
670 true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
672 = (operands[1] == const0_rtx
674 : gen_rtx_REG (SImode,
675 true_regnum (operands[1])
676 + (TARGET_LITTLE_ENDIAN ? 1 : 0)));
677 operands[4] = gen_lowpart (SImode, operands[0]);
678 operands[5] = gen_lowpart (SImode, operands[1]);
681 (define_insn "cmpgtdi_t"
682 [(set (reg:SI 18) (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
683 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
686 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
687 tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
688 [(set_attr "length" "8")
689 (set_attr "type" "arith3")])
691 (define_insn "cmpgedi_t"
692 [(set (reg:SI 18) (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
693 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
696 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
698 [(set_attr "length" "8,2")
699 (set_attr "type" "arith3,arith")])
701 ;; -------------------------------------------------------------------------
702 ;; DImode unsigned integer comparisons
703 ;; -------------------------------------------------------------------------
705 (define_insn "cmpgeudi_t"
706 [(set (reg:SI 18) (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
707 (match_operand:DI 1 "arith_reg_operand" "r")))]
709 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
710 [(set_attr "length" "8")
711 (set_attr "type" "arith3")])
713 (define_insn "cmpgtudi_t"
714 [(set (reg:SI 18) (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
715 (match_operand:DI 1 "arith_reg_operand" "r")))]
717 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
718 [(set_attr "length" "8")
719 (set_attr "type" "arith3")])
721 ;; We save the compare operands in the cmpxx patterns and use them when
722 ;; we generate the branch.
724 (define_expand "cmpdi"
725 [(set (reg:SI 18) (compare (match_operand:DI 0 "arith_operand" "")
726 (match_operand:DI 1 "arith_operand" "")))]
730 sh_compare_op0 = operands[0];
731 sh_compare_op1 = operands[1];
735 ;; -------------------------------------------------------------------------
736 ;; Addition instructions
737 ;; -------------------------------------------------------------------------
739 ;; ??? This should be a define expand.
741 (define_insn "adddi3"
742 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
743 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
744 (match_operand:DI 2 "arith_reg_operand" "r")))
745 (clobber (reg:SI 18))]
748 [(set_attr "length" "6")])
751 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
752 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
753 (match_operand:DI 2 "arith_reg_operand" "r")))
754 (clobber (reg:SI 18))]
759 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
760 high0 = gen_rtx_REG (SImode,
761 true_regnum (operands[0])
762 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
763 high2 = gen_rtx_REG (SImode,
764 true_regnum (operands[2])
765 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
766 emit_insn (gen_clrt ());
767 emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
768 emit_insn (gen_addc1 (high0, high0, high2));
773 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
774 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
775 (match_operand:SI 2 "arith_reg_operand" "r"))
778 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
781 [(set_attr "type" "arith")])
784 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
785 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
786 (match_operand:SI 2 "arith_reg_operand" "r"))
788 (clobber (reg:SI 18))]
791 [(set_attr "type" "arith")])
793 (define_insn "addsi3"
794 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
795 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
796 (match_operand:SI 2 "arith_operand" "rI")))]
799 [(set_attr "type" "arith")])
801 ;; -------------------------------------------------------------------------
802 ;; Subtraction instructions
803 ;; -------------------------------------------------------------------------
805 ;; ??? This should be a define expand.
807 (define_insn "subdi3"
808 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
809 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
810 (match_operand:DI 2 "arith_reg_operand" "r")))
811 (clobber (reg:SI 18))]
814 [(set_attr "length" "6")])
817 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
818 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
819 (match_operand:DI 2 "arith_reg_operand" "r")))
820 (clobber (reg:SI 18))]
825 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
826 high0 = gen_rtx_REG (SImode,
827 true_regnum (operands[0])
828 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
829 high2 = gen_rtx_REG (SImode,
830 true_regnum (operands[2])
831 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
832 emit_insn (gen_clrt ());
833 emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
834 emit_insn (gen_subc1 (high0, high0, high2));
839 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
840 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
841 (match_operand:SI 2 "arith_reg_operand" "r"))
844 (gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
847 [(set_attr "type" "arith")])
850 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
851 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
852 (match_operand:SI 2 "arith_reg_operand" "r"))
854 (clobber (reg:SI 18))]
857 [(set_attr "type" "arith")])
859 (define_insn "*subsi3_internal"
860 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
861 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
862 (match_operand:SI 2 "arith_reg_operand" "r")))]
865 [(set_attr "type" "arith")])
867 ;; Convert `constant - reg' to `neg rX; add rX, #const' since this
868 ;; will sometimes save one instruction. Otherwise we might get
869 ;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
872 (define_expand "subsi3"
873 [(set (match_operand:SI 0 "arith_reg_operand" "")
874 (minus:SI (match_operand:SI 1 "arith_operand" "")
875 (match_operand:SI 2 "arith_reg_operand" "")))]
879 if (GET_CODE (operands[1]) == CONST_INT)
881 emit_insn (gen_negsi2 (operands[0], operands[2]));
882 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
887 ;; -------------------------------------------------------------------------
888 ;; Division instructions
889 ;; -------------------------------------------------------------------------
891 ;; We take advantage of the library routines which don't clobber as many
892 ;; registers as a normal function call would.
894 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
895 ;; also has an effect on the register that holds the address of the sfunc.
896 ;; To make this work, we have an extra dummy insns that shows the use
897 ;; of this register for reorg.
899 (define_insn "use_sfunc_addr"
900 [(set (reg:SI 17) (unspec [(match_operand:SI 0 "register_operand" "r")] 5))]
903 [(set_attr "length" "0")])
905 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
906 ;; hard register 0. If we used hard register 0, then the next instruction
907 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
908 ;; gets allocated to a stack slot that needs its address reloaded, then
909 ;; there is nothing to prevent reload from using r0 to reload the address.
910 ;; This reload would clobber the value in r0 we are trying to store.
911 ;; If we let reload allocate r0, then this problem can never happen.
913 (define_insn "udivsi3_i1"
914 [(set (match_operand:SI 0 "register_operand" "=z")
915 (udiv:SI (reg:SI 4) (reg:SI 5)))
916 (clobber (reg:SI 18))
917 (clobber (reg:SI 17))
919 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
922 [(set_attr "type" "sfunc")
923 (set_attr "needs_delay_slot" "yes")])
925 (define_insn "udivsi3_i4"
926 [(set (match_operand:SI 0 "register_operand" "=y")
927 (udiv:SI (reg:SI 4) (reg:SI 5)))
928 (clobber (reg:SI 17))
929 (clobber (reg:DF 24))
930 (clobber (reg:DF 26))
931 (clobber (reg:DF 28))
937 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
938 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
940 [(set_attr "type" "sfunc")
941 (set_attr "fp_mode" "double")
942 (set_attr "needs_delay_slot" "yes")])
944 (define_insn "udivsi3_i4_single"
945 [(set (match_operand:SI 0 "register_operand" "=y")
946 (udiv:SI (reg:SI 4) (reg:SI 5)))
947 (clobber (reg:SI 17))
948 (clobber (reg:DF 24))
949 (clobber (reg:DF 26))
950 (clobber (reg:DF 28))
955 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
956 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
958 [(set_attr "type" "sfunc")
959 (set_attr "needs_delay_slot" "yes")])
961 (define_expand "udivsi3"
962 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
963 (set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
964 (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
965 (parallel [(set (match_operand:SI 0 "register_operand" "")
968 (clobber (reg:SI 18))
969 (clobber (reg:SI 17))
971 (use (match_dup 3))])]
977 operands[3] = gen_reg_rtx(SImode);
978 /* Emit the move of the address to a pseudo outside of the libcall. */
979 if (TARGET_HARD_SH4 && TARGET_SH3E)
981 emit_move_insn (operands[3],
982 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
983 if (TARGET_FPU_SINGLE)
984 last = gen_udivsi3_i4_single (operands[0], operands[3]);
986 last = gen_udivsi3_i4 (operands[0], operands[3]);
990 emit_move_insn (operands[3],
991 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3\"));
992 last = gen_udivsi3_i1 (operands[0], operands[3]);
994 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
995 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
996 last = emit_insn (last);
997 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
998 invariant code motion can move it. */
999 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1000 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1004 (define_insn "divsi3_i1"
1005 [(set (match_operand:SI 0 "register_operand" "=z")
1006 (div:SI (reg:SI 4) (reg:SI 5)))
1007 (clobber (reg:SI 18))
1008 (clobber (reg:SI 17))
1009 (clobber (reg:SI 1))
1010 (clobber (reg:SI 2))
1011 (clobber (reg:SI 3))
1012 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1015 [(set_attr "type" "sfunc")
1016 (set_attr "needs_delay_slot" "yes")])
1018 (define_insn "divsi3_i4"
1019 [(set (match_operand:SI 0 "register_operand" "=y")
1020 (div:SI (reg:SI 4) (reg:SI 5)))
1021 (clobber (reg:SI 17))
1022 (clobber (reg:DF 24))
1023 (clobber (reg:DF 26))
1025 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1026 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1028 [(set_attr "type" "sfunc")
1029 (set_attr "fp_mode" "double")
1030 (set_attr "needs_delay_slot" "yes")])
1032 (define_insn "divsi3_i4_single"
1033 [(set (match_operand:SI 0 "register_operand" "=y")
1034 (div:SI (reg:SI 4) (reg:SI 5)))
1035 (clobber (reg:SI 17))
1036 (clobber (reg:DF 24))
1037 (clobber (reg:DF 26))
1038 (clobber (reg:SI 2))
1039 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1040 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
1042 [(set_attr "type" "sfunc")
1043 (set_attr "needs_delay_slot" "yes")])
1045 (define_expand "divsi3"
1046 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
1047 (set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
1048 (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
1049 (parallel [(set (match_operand:SI 0 "register_operand" "")
1052 (clobber (reg:SI 18))
1053 (clobber (reg:SI 17))
1054 (clobber (reg:SI 1))
1055 (clobber (reg:SI 2))
1056 (clobber (reg:SI 3))
1057 (use (match_dup 3))])]
1063 operands[3] = gen_reg_rtx(SImode);
1064 /* Emit the move of the address to a pseudo outside of the libcall. */
1065 if (TARGET_HARD_SH4 && TARGET_SH3E)
1067 emit_move_insn (operands[3],
1068 gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
1069 if (TARGET_FPU_SINGLE)
1070 last = gen_divsi3_i4_single (operands[0], operands[3]);
1072 last = gen_divsi3_i4 (operands[0], operands[3]);
1076 emit_move_insn (operands[3], gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3\"));
1077 last = gen_divsi3_i1 (operands[0], operands[3]);
1079 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1080 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1081 last = emit_insn (last);
1082 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1083 invariant code motion can move it. */
1084 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1085 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1089 ;; -------------------------------------------------------------------------
1090 ;; Multiplication instructions
1091 ;; -------------------------------------------------------------------------
1093 (define_insn "umulhisi3_i"
1095 (mult:SI (zero_extend:SI (match_operand:HI 0 "arith_reg_operand" "r"))
1096 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r"))))]
1099 [(set_attr "type" "smpy")])
1101 (define_insn "mulhisi3_i"
1103 (mult:SI (sign_extend:SI
1104 (match_operand:HI 0 "arith_reg_operand" "r"))
1106 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1109 [(set_attr "type" "smpy")])
1111 (define_expand "mulhisi3"
1113 (mult:SI (sign_extend:SI
1114 (match_operand:HI 1 "arith_reg_operand" ""))
1116 (match_operand:HI 2 "arith_reg_operand" ""))))
1117 (set (match_operand:SI 0 "arith_reg_operand" "")
1124 first = emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
1125 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 21));
1126 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1127 invariant code motion can move it. */
1128 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1129 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1133 (define_expand "umulhisi3"
1135 (mult:SI (zero_extend:SI
1136 (match_operand:HI 1 "arith_reg_operand" ""))
1138 (match_operand:HI 2 "arith_reg_operand" ""))))
1139 (set (match_operand:SI 0 "arith_reg_operand" "")
1146 first = emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
1147 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 21));
1148 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1149 invariant code motion can move it. */
1150 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1151 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1155 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
1156 ;; a call to a routine which clobbers known registers.
1159 [(set (match_operand:SI 1 "register_operand" "=z")
1160 (mult:SI (reg:SI 4) (reg:SI 5)))
1161 (clobber (reg:SI 21))
1162 (clobber (reg:SI 18))
1163 (clobber (reg:SI 17))
1164 (clobber (reg:SI 3))
1165 (clobber (reg:SI 2))
1166 (clobber (reg:SI 1))
1167 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
1170 [(set_attr "type" "sfunc")
1171 (set_attr "needs_delay_slot" "yes")])
1173 (define_expand "mulsi3_call"
1174 [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
1175 (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
1176 (parallel[(set (match_operand:SI 0 "register_operand" "")
1179 (clobber (reg:SI 21))
1180 (clobber (reg:SI 18))
1181 (clobber (reg:SI 17))
1182 (clobber (reg:SI 3))
1183 (clobber (reg:SI 2))
1184 (clobber (reg:SI 1))
1185 (use (match_operand:SI 3 "register_operand" ""))])]
1189 (define_insn "mul_l"
1191 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
1192 (match_operand:SI 1 "arith_reg_operand" "r")))]
1195 [(set_attr "type" "dmpy")])
1197 (define_expand "mulsi3"
1199 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
1200 (match_operand:SI 2 "arith_reg_operand" "")))
1201 (set (match_operand:SI 0 "arith_reg_operand" "")
1210 /* The address must be set outside the libcall,
1211 since it goes into a pseudo. */
1212 rtx sym = gen_rtx_SYMBOL_REF (SImode, \"__mulsi3\");
1213 rtx addr = force_reg (SImode, sym);
1214 rtx insns = gen_mulsi3_call (operands[0], operands[1],
1216 first = XVECEXP (insns, 0, 0);
1217 last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1222 rtx macl = gen_rtx_REG (SImode, MACL_REG);
1224 first = emit_insn (gen_mul_l (operands[1], operands[2]));
1225 /* consec_sets_giv can only recognize the first insn that sets a
1226 giv as the giv insn. So we must tag this also with a REG_EQUAL
1228 last = emit_insn (gen_movsi_i ((operands[0]), macl));
1230 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1231 invariant code motion can move it. */
1232 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1233 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1237 (define_insn "mulsidi3_i"
1240 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1241 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1244 (mult:SI (match_dup 0)
1248 [(set_attr "type" "dmpy")])
1250 (define_insn "mulsidi3"
1251 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1252 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1253 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1254 (clobber (reg:DI 20))]
1259 [(set (match_operand:DI 0 "arith_reg_operand" "")
1260 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1261 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1262 (clobber (reg:DI 20))]
1267 rtx low_dst = gen_lowpart (SImode, operands[0]);
1268 rtx high_dst = gen_highpart (SImode, operands[0]);
1270 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
1272 emit_move_insn (low_dst, gen_rtx_REG (SImode, 21));
1273 emit_move_insn (high_dst, gen_rtx_REG (SImode, 20));
1274 /* We need something to tag the possible REG_EQUAL notes on to. */
1275 emit_move_insn (operands[0], operands[0]);
1279 (define_insn "umulsidi3_i"
1282 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1283 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1286 (mult:SI (match_dup 0)
1290 [(set_attr "type" "dmpy")])
1292 (define_insn "umulsidi3"
1293 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1294 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1295 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1296 (clobber (reg:DI 20))]
1301 [(set (match_operand:DI 0 "arith_reg_operand" "")
1302 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1303 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1304 (clobber (reg:DI 20))]
1309 rtx low_dst = gen_lowpart (SImode, operands[0]);
1310 rtx high_dst = gen_highpart (SImode, operands[0]);
1312 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
1314 emit_move_insn (low_dst, gen_rtx_REG (SImode, 21));
1315 emit_move_insn (high_dst, gen_rtx_REG (SImode, 20));
1316 /* We need something to tag the possible REG_EQUAL notes on to. */
1317 emit_move_insn (operands[0], operands[0]);
1321 (define_insn "smulsi3_highpart_i"
1324 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1325 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1327 (clobber (reg:SI 21))]
1330 [(set_attr "type" "dmpy")])
1332 (define_expand "smulsi3_highpart"
1333 [(parallel [(set (reg:SI 20)
1335 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1336 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1338 (clobber (reg:SI 21))])
1339 (set (match_operand:SI 0 "arith_reg_operand" "")
1346 first = emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
1347 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 20));
1348 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1349 invariant code motion can move it. */
1350 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1351 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1352 /* expand_binop can't find a suitable code in mul_highpart_optab to
1353 make a REG_EQUAL note from, so make one here.
1354 ??? Alternatively, we could put this at the calling site of expand_binop,
1355 i.e. expand_mult_highpart. */
1357 = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
1362 (define_insn "umulsi3_highpart_i"
1365 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1366 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1368 (clobber (reg:SI 21))]
1371 [(set_attr "type" "dmpy")])
1373 (define_expand "umulsi3_highpart"
1374 [(parallel [(set (reg:SI 20)
1376 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1377 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1379 (clobber (reg:SI 21))])
1380 (set (match_operand:SI 0 "arith_reg_operand" "")
1387 first = emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
1388 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 20));
1389 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1390 invariant code motion can move it. */
1391 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1392 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1396 ;; -------------------------------------------------------------------------
1397 ;; Logical operations
1398 ;; -------------------------------------------------------------------------
1401 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1402 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1403 (match_operand:SI 2 "logical_operand" "r,L")))]
1406 [(set_attr "type" "arith")])
1408 ;; If the constant is 255, then emit a extu.b instruction instead of an
1409 ;; and, since that will give better code.
1411 (define_expand "andsi3"
1412 [(set (match_operand:SI 0 "arith_reg_operand" "")
1413 (and:SI (match_operand:SI 1 "arith_reg_operand" "")
1414 (match_operand:SI 2 "logical_operand" "")))]
1418 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
1420 emit_insn (gen_zero_extendqisi2 (operands[0],
1421 gen_lowpart (QImode, operands[1])));
1426 (define_insn "iorsi3"
1427 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1428 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1429 (match_operand:SI 2 "logical_operand" "r,L")))]
1432 [(set_attr "type" "arith")])
1434 (define_insn "xorsi3"
1435 [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
1436 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1437 (match_operand:SI 2 "logical_operand" "L,r")))]
1440 [(set_attr "type" "arith")])
1442 ;; -------------------------------------------------------------------------
1443 ;; Shifts and rotates
1444 ;; -------------------------------------------------------------------------
1446 (define_insn "rotlsi3_1"
1447 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1448 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1451 (lshiftrt:SI (match_dup 1) (const_int 31)))]
1454 [(set_attr "type" "arith")])
1456 (define_insn "rotlsi3_31"
1457 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1458 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1460 (clobber (reg:SI 18))]
1463 [(set_attr "type" "arith")])
1465 (define_insn "rotlsi3_16"
1466 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1467 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
1471 [(set_attr "type" "arith")])
1473 (define_expand "rotlsi3"
1474 [(set (match_operand:SI 0 "arith_reg_operand" "")
1475 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
1476 (match_operand:SI 2 "immediate_operand" "")))]
1480 static char rot_tab[] = {
1481 000, 000, 000, 000, 000, 000, 010, 001,
1482 001, 001, 011, 013, 003, 003, 003, 003,
1483 003, 003, 003, 003, 003, 013, 012, 002,
1484 002, 002, 010, 000, 000, 000, 000, 000,
1489 if (GET_CODE (operands[2]) != CONST_INT)
1491 count = INTVAL (operands[2]);
1492 choice = rot_tab[count];
1493 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
1499 emit_move_insn (operands[0], operands[1]);
1500 count -= (count & 16) * 2;
1503 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
1510 parts[0] = gen_reg_rtx (SImode);
1511 parts[1] = gen_reg_rtx (SImode);
1512 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
1513 parts[choice-1] = operands[1];
1514 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
1515 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
1516 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
1517 count = (count & ~16) - 8;
1521 for (; count > 0; count--)
1522 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1523 for (; count < 0; count++)
1524 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1529 (define_insn "*rotlhi3_8"
1530 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1531 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
1535 [(set_attr "type" "arith")])
1537 (define_expand "rotlhi3"
1538 [(set (match_operand:HI 0 "arith_reg_operand" "")
1539 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
1540 (match_operand:HI 2 "immediate_operand" "")))]
1544 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
1551 ;; This pattern is used by init_expmed for computing the costs of shift
1554 (define_insn_and_split "ashlsi3_std"
1555 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r")
1556 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
1557 (match_operand:SI 2 "nonmemory_operand" "r,M,K,?ri")))
1558 (clobber (match_scratch:SI 3 "=X,X,X,&r"))]
1560 || (GET_CODE (operands[2]) == CONST_INT
1561 && CONST_OK_FOR_K (INTVAL (operands[2])))"
1568 && GET_CODE (operands[2]) == CONST_INT
1569 && ! CONST_OK_FOR_K (INTVAL (operands[2]))"
1570 [(set (match_dup 3) (match_dup 2))
1572 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
1573 (clobber (match_dup 4))])]
1574 "operands[4] = gen_rtx_SCRATCH (SImode);"
1575 [(set_attr "length" "*,*,*,4")
1576 (set_attr "type" "dyn_shift,arith,arith,arith")])
1578 (define_insn "ashlhi3_k"
1579 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
1580 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
1581 (match_operand:HI 2 "const_int_operand" "M,K")))]
1582 "CONST_OK_FOR_K (INTVAL (operands[2]))"
1586 [(set_attr "type" "arith")])
1588 (define_insn "ashlsi3_n"
1589 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1590 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
1591 (match_operand:SI 2 "const_int_operand" "n")))
1592 (clobber (reg:SI 18))]
1593 "! sh_dynamicalize_shift_p (operands[2])"
1595 [(set (attr "length")
1596 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1598 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1600 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1602 (const_string "8")))
1603 (set_attr "type" "arith")])
1606 [(set (match_operand:SI 0 "arith_reg_operand" "")
1607 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1608 (match_operand:SI 2 "const_int_operand" "n")))
1609 (clobber (reg:SI 18))]
1614 gen_shifty_op (ASHIFT, operands);
1618 (define_expand "ashlsi3"
1619 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1620 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1621 (match_operand:SI 2 "nonmemory_operand" "")))
1622 (clobber (reg:SI 18))])]
1626 if (GET_CODE (operands[2]) == CONST_INT
1627 && sh_dynamicalize_shift_p (operands[2]))
1628 operands[2] = force_reg (SImode, operands[2]);
1631 emit_insn (gen_ashlsi3_std (operands[0], operands[1], operands[2]));
1634 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1638 (define_insn "ashlhi3"
1639 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1640 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
1641 (match_operand:HI 2 "const_int_operand" "n")))
1642 (clobber (reg:SI 18))]
1645 [(set (attr "length")
1646 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1648 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1650 (const_string "6")))
1651 (set_attr "type" "arith")])
1654 [(set (match_operand:HI 0 "arith_reg_operand" "")
1655 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
1656 (match_operand:HI 2 "const_int_operand" "n")))
1657 (clobber (reg:SI 18))]
1662 gen_shifty_hi_op (ASHIFT, operands);
1667 ; arithmetic shift right
1670 (define_insn "ashrsi3_k"
1671 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1672 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1673 (match_operand:SI 2 "const_int_operand" "M")))
1674 (clobber (reg:SI 18))]
1675 "INTVAL (operands[2]) == 1"
1677 [(set_attr "type" "arith")])
1679 ;; We can't do HImode right shifts correctly unless we start out with an
1680 ;; explicit zero / sign extension; doing that would result in worse overall
1681 ;; code, so just let the machine independent code widen the mode.
1682 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
1685 ;; ??? This should be a define expand.
1687 (define_insn "ashrsi2_16"
1688 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1689 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1693 [(set_attr "length" "4")])
1696 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1697 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1700 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
1701 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
1702 "operands[2] = gen_lowpart (HImode, operands[0]);")
1704 ;; ??? This should be a define expand.
1706 (define_insn "ashrsi2_31"
1707 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1708 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1710 (clobber (reg:SI 18))]
1713 [(set_attr "length" "4")])
1716 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1717 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1719 (clobber (reg:SI 18))]
1724 emit_insn (gen_ashlsi_c (operands[0], operands[1]));
1725 emit_insn (gen_subc1 (operands[0], operands[0], operands[0]));
1729 (define_insn "ashlsi_c"
1730 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1731 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
1732 (set (reg:SI 18) (lt:SI (match_dup 1)
1736 [(set_attr "type" "arith")])
1738 (define_insn "ashrsi3_d"
1739 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1740 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1741 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1744 [(set_attr "type" "dyn_shift")])
1746 (define_insn "ashrsi3_n"
1748 (ashiftrt:SI (reg:SI 4)
1749 (match_operand:SI 0 "const_int_operand" "i")))
1750 (clobber (reg:SI 18))
1751 (clobber (reg:SI 17))
1752 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1755 [(set_attr "type" "sfunc")
1756 (set_attr "needs_delay_slot" "yes")])
1758 (define_expand "ashrsi3"
1759 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1760 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1761 (match_operand:SI 2 "nonmemory_operand" "")))
1762 (clobber (reg:SI 18))])]
1764 "if (expand_ashiftrt (operands)) DONE; else FAIL;")
1766 ;; logical shift right
1768 (define_insn "lshrsi3_d"
1769 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1770 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1771 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1774 [(set_attr "type" "dyn_shift")])
1776 ;; Only the single bit shift clobbers the T bit.
1778 (define_insn "lshrsi3_m"
1779 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1780 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1781 (match_operand:SI 2 "const_int_operand" "M")))
1782 (clobber (reg:SI 18))]
1783 "CONST_OK_FOR_M (INTVAL (operands[2]))"
1785 [(set_attr "type" "arith")])
1787 (define_insn "lshrsi3_k"
1788 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1789 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1790 (match_operand:SI 2 "const_int_operand" "K")))]
1791 "CONST_OK_FOR_K (INTVAL (operands[2]))
1792 && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
1794 [(set_attr "type" "arith")])
1796 (define_insn "lshrsi3_n"
1797 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1798 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1799 (match_operand:SI 2 "const_int_operand" "n")))
1800 (clobber (reg:SI 18))]
1801 "! sh_dynamicalize_shift_p (operands[2])"
1803 [(set (attr "length")
1804 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1806 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1808 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1810 (const_string "8")))
1811 (set_attr "type" "arith")])
1814 [(set (match_operand:SI 0 "arith_reg_operand" "")
1815 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1816 (match_operand:SI 2 "const_int_operand" "n")))
1817 (clobber (reg:SI 18))]
1822 gen_shifty_op (LSHIFTRT, operands);
1826 (define_expand "lshrsi3"
1827 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1828 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1829 (match_operand:SI 2 "nonmemory_operand" "")))
1830 (clobber (reg:SI 18))])]
1834 if (GET_CODE (operands[2]) == CONST_INT
1835 && sh_dynamicalize_shift_p (operands[2]))
1836 operands[2] = force_reg (SImode, operands[2]);
1837 if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
1839 rtx count = copy_to_mode_reg (SImode, operands[2]);
1840 emit_insn (gen_negsi2 (count, count));
1841 emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
1844 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1848 ;; ??? This should be a define expand.
1850 (define_insn "ashldi3_k"
1851 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1852 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
1854 (clobber (reg:SI 18))]
1856 "shll %R0\;rotcl %S0"
1857 [(set_attr "length" "4")
1858 (set_attr "type" "arith")])
1860 (define_expand "ashldi3"
1861 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1862 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
1863 (match_operand:DI 2 "immediate_operand" "")))
1864 (clobber (reg:SI 18))])]
1866 "{ if (GET_CODE (operands[2]) != CONST_INT
1867 || INTVAL (operands[2]) != 1) FAIL;} ")
1869 ;; ??? This should be a define expand.
1871 (define_insn "lshrdi3_k"
1872 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1873 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1875 (clobber (reg:SI 18))]
1877 "shlr %S0\;rotcr %R0"
1878 [(set_attr "length" "4")
1879 (set_attr "type" "arith")])
1881 (define_expand "lshrdi3"
1882 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1883 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1884 (match_operand:DI 2 "immediate_operand" "")))
1885 (clobber (reg:SI 18))])]
1887 "{ if (GET_CODE (operands[2]) != CONST_INT
1888 || INTVAL (operands[2]) != 1) FAIL;} ")
1890 ;; ??? This should be a define expand.
1892 (define_insn "ashrdi3_k"
1893 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1894 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1896 (clobber (reg:SI 18))]
1898 "shar %S0\;rotcr %R0"
1899 [(set_attr "length" "4")
1900 (set_attr "type" "arith")])
1902 (define_expand "ashrdi3"
1903 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1904 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1905 (match_operand:DI 2 "immediate_operand" "")))
1906 (clobber (reg:SI 18))])]
1908 "{ if (GET_CODE (operands[2]) != CONST_INT
1909 || INTVAL (operands[2]) != 1) FAIL; } ")
1911 ;; combined left/right shift
1914 [(set (match_operand:SI 0 "register_operand" "")
1915 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
1916 (match_operand:SI 2 "const_int_operand" "n"))
1917 (match_operand:SI 3 "const_int_operand" "n")))]
1918 "(unsigned)INTVAL (operands[2]) < 32"
1920 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
1924 [(set (match_operand:SI 0 "register_operand" "")
1925 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
1926 (match_operand:SI 2 "const_int_operand" "n"))
1927 (match_operand:SI 3 "const_int_operand" "n")))
1928 (clobber (reg:SI 18))]
1929 "(unsigned)INTVAL (operands[2]) < 32"
1931 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
1935 [(set (match_operand:SI 0 "register_operand" "=r")
1936 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
1937 (match_operand:SI 2 "const_int_operand" "n"))
1938 (match_operand:SI 3 "const_int_operand" "n")))
1939 (clobber (reg:SI 18))]
1940 "shl_and_kind (operands[2], operands[3], 0) == 1"
1942 [(set (attr "length")
1943 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
1945 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
1947 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
1949 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
1951 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
1953 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
1955 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
1956 (const_string "16")]
1957 (const_string "18")))
1958 (set_attr "type" "arith")])
1961 [(set (match_operand:SI 0 "register_operand" "=z")
1962 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
1963 (match_operand:SI 2 "const_int_operand" "n"))
1964 (match_operand:SI 3 "const_int_operand" "n")))
1965 (clobber (reg:SI 18))]
1966 "shl_and_kind (operands[2], operands[3], 0) == 2"
1968 [(set (attr "length")
1969 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
1971 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
1973 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
1975 (const_string "10")))
1976 (set_attr "type" "arith")])
1978 ;; shift left / and combination with a scratch register: The combine pass
1979 ;; does not accept the individual instructions, even though they are
1980 ;; cheap. But it needs a precise description so that it is usable after
1982 (define_insn "and_shl_scratch"
1983 [(set (match_operand:SI 0 "register_operand" "=r,&r")
1984 (lshiftrt:SI (ashift:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
1985 (match_operand:SI 2 "const_int_operand" "N,n"))
1986 (match_operand:SI 3 "" "0,r"))
1987 (match_operand:SI 4 "const_int_operand" "n,n"))
1988 (match_operand:SI 5 "const_int_operand" "n,n")))
1989 (clobber (reg:SI 18))]
1992 [(set (attr "length")
1993 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
1995 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
1997 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
1999 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
2000 (const_string "10")]
2001 (const_string "12")))
2002 (set_attr "type" "arith")])
2005 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2006 (lshiftrt:SI (ashift:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
2007 (match_operand:SI 2 "const_int_operand" "N,n"))
2008 (match_operand:SI 3 "register_operand" "0,r"))
2009 (match_operand:SI 4 "const_int_operand" "n,n"))
2010 (match_operand:SI 5 "const_int_operand" "n,n")))
2011 (clobber (reg:SI 18))]
2016 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
2018 if (INTVAL (operands[2]))
2020 gen_shifty_op (LSHIFTRT, operands);
2022 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
2023 operands[2] = operands[4];
2024 gen_shifty_op (ASHIFT, operands);
2025 if (INTVAL (operands[5]))
2027 operands[2] = operands[5];
2028 gen_shifty_op (LSHIFTRT, operands);
2033 ;; signed left/right shift combination.
2035 [(set (match_operand:SI 0 "register_operand" "=r")
2036 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2037 (match_operand:SI 2 "const_int_operand" "n"))
2038 (match_operand:SI 3 "const_int_operand" "n")
2040 (clobber (reg:SI 18))]
2043 "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
2046 (define_insn "shl_sext_ext"
2047 [(set (match_operand:SI 0 "register_operand" "=r")
2048 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2049 (match_operand:SI 2 "const_int_operand" "n"))
2050 (match_operand:SI 3 "const_int_operand" "n")
2052 (clobber (reg:SI 18))]
2053 "(unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
2055 [(set (attr "length")
2056 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 1))
2058 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
2060 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2062 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2064 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2066 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2068 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
2070 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
2071 (const_string "16")]
2072 (const_string "18")))
2073 (set_attr "type" "arith")])
2075 (define_insn "shl_sext_sub"
2076 [(set (match_operand:SI 0 "register_operand" "=z")
2077 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2078 (match_operand:SI 2 "const_int_operand" "n"))
2079 (match_operand:SI 3 "const_int_operand" "n")
2081 (clobber (reg:SI 18))]
2082 "(shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
2084 [(set (attr "length")
2085 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2087 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2089 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2091 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2092 (const_string "12")]
2093 (const_string "14")))
2094 (set_attr "type" "arith")])
2096 ;; These patterns are found in expansions of DImode shifts by 16, and
2097 ;; allow the xtrct instruction to be generated from C source.
2099 (define_insn "xtrct_left"
2100 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2101 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
2103 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
2107 [(set_attr "type" "arith")])
2109 (define_insn "xtrct_right"
2110 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2111 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2113 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
2117 [(set_attr "type" "arith")])
2119 ;; -------------------------------------------------------------------------
2121 ;; -------------------------------------------------------------------------
2124 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2125 (neg:SI (plus:SI (reg:SI 18)
2126 (match_operand:SI 1 "arith_reg_operand" "r"))))
2128 (ne:SI (ior:SI (reg:SI 18) (match_dup 1))
2132 [(set_attr "type" "arith")])
2134 (define_expand "negdi2"
2135 [(set (match_operand:DI 0 "arith_reg_operand" "")
2136 (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
2137 (clobber (reg:SI 18))]
2141 int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
2142 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
2144 rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
2145 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
2147 rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
2148 rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
2150 emit_insn (gen_clrt ());
2151 emit_insn (gen_negc (low_dst, low_src));
2152 emit_insn (gen_negc (high_dst, high_src));
2156 (define_insn "negsi2"
2157 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2158 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2161 [(set_attr "type" "arith")])
2163 (define_insn "one_cmplsi2"
2164 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2165 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2168 [(set_attr "type" "arith")])
2170 ;; -------------------------------------------------------------------------
2171 ;; Zero extension instructions
2172 ;; -------------------------------------------------------------------------
2174 (define_insn "zero_extendhisi2"
2175 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2176 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
2179 [(set_attr "type" "arith")])
2181 (define_insn "zero_extendqisi2"
2182 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2183 (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
2186 [(set_attr "type" "arith")])
2188 (define_insn "zero_extendqihi2"
2189 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
2190 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
2193 [(set_attr "type" "arith")])
2195 ;; -------------------------------------------------------------------------
2196 ;; Sign extension instructions
2197 ;; -------------------------------------------------------------------------
2199 ;; ??? This should be a define expand.
2200 ;; ??? Or perhaps it should be dropped?
2202 /* There is no point in defining extendsidi2; convert_move generates good
2205 (define_insn "extendhisi2"
2206 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2207 (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
2212 [(set_attr "type" "arith,load")])
2214 (define_insn "extendqisi2"
2215 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2216 (sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2221 [(set_attr "type" "arith,load")])
2223 (define_insn "extendqihi2"
2224 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
2225 (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2230 [(set_attr "type" "arith,load")])
2232 ;; -------------------------------------------------------------------------
2233 ;; Move instructions
2234 ;; -------------------------------------------------------------------------
2236 ;; define push and pop so it is easy for sh.c
2238 (define_expand "push"
2239 [(set (mem:SI (pre_dec:SI (reg:SI 15)))
2240 (match_operand:SI 0 "register_operand" "r,l,x"))]
2244 (define_expand "pop"
2245 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
2246 (mem:SI (post_inc:SI (reg:SI 15))))]
2250 (define_expand "push_e"
2251 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI 15)))
2252 (match_operand:SF 0 "" ""))
2254 (clobber (scratch:SI))])]
2258 (define_insn "push_fpul"
2259 [(set (mem:SF (pre_dec:SI (reg:SI 15))) (reg:SF 22))]
2262 [(set_attr "type" "store")
2263 (set_attr "hit_stack" "yes")])
2265 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
2267 (define_expand "push_4"
2268 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI 15))) (match_operand:DF 0 "" ""))
2270 (clobber (scratch:SI))])]
2274 (define_expand "pop_e"
2275 [(parallel [(set (match_operand:SF 0 "" "")
2276 (mem:SF (post_inc:SI (reg:SI 15))))
2278 (clobber (scratch:SI))])]
2282 (define_insn "pop_fpul"
2283 [(set (reg:SF 22) (mem:SF (post_inc:SI (reg:SI 15))))]
2286 [(set_attr "type" "load")
2287 (set_attr "hit_stack" "yes")])
2289 (define_expand "pop_4"
2290 [(parallel [(set (match_operand:DF 0 "" "")
2291 (mem:DF (post_inc:SI (reg:SI 15))))
2293 (clobber (scratch:SI))])]
2297 ;; These two patterns can happen as the result of optimization, when
2298 ;; comparisons get simplified to a move of zero or 1 into the T reg.
2299 ;; They don't disappear completely, because the T reg is a fixed hard reg.
2302 [(set (reg:SI 18) (const_int 0))]
2307 [(set (reg:SI 18) (const_int 1))]
2311 ;; t/r must come after r/r, lest reload will try to reload stuff like
2312 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI 15 r15) (const_int 12)) 0) 0)
2313 ;; (made from (set (subreg:SI (reg:QI 73) 0) ) into T.
2314 (define_insn "movsi_i"
2315 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,m,<,<,xl,x,l,r")
2316 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,xl,t,r,x,l,r,>,>,i"))]
2319 && (register_operand (operands[0], SImode)
2320 || register_operand (operands[1], SImode))"
2335 [(set_attr "type" "pcload_si,move,*,load_si,move,move,store,store,pstore,move,load,pload,pcload_si")
2336 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*")])
2338 ;; t/r must come after r/r, lest reload will try to reload stuff like
2339 ;; (subreg:SI (reg:SF 38 fr14) 0) into T (compiling stdlib/strtod.c -m3e -O2)
2340 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
2341 ;; will require a reload.
2342 (define_insn "movsi_ie"
2343 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,m,<,<,xl,x,l,y,r,y,r,y")
2344 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,xl,t,r,x,l,r,>,>,>,i,r,y,y"))]
2346 && (register_operand (operands[0], SImode)
2347 || register_operand (operands[1], SImode))"
2365 ! move optimized away"
2366 [(set_attr "type" "pcload_si,move,*,load_si,move,move,store,store,pstore,move,load,pload,load,pcload_si,gp_fpul,gp_fpul,nil")
2367 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
2369 (define_insn "movsi_i_lowpart"
2370 [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,r,m,r"))
2371 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,mr,xl,t,r,i"))]
2372 "register_operand (operands[0], SImode)
2373 || register_operand (operands[1], SImode)"
2382 [(set_attr "type" "pcload,move,load,move,move,store,pcload")])
2384 (define_expand "movsi"
2385 [(set (match_operand:SI 0 "general_movdst_operand" "")
2386 (match_operand:SI 1 "general_movsrc_operand" ""))]
2388 "{ if (prepare_move_operands (operands, SImode)) DONE; }")
2390 (define_expand "ic_invalidate_line"
2391 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
2393 (clobber (scratch:SI))])]
2397 operands[0] = force_reg (Pmode, operands[0]);
2398 operands[1] = force_reg (Pmode, GEN_INT (0xf0000008));
2401 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
2402 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
2403 ;; the requirement *1*00 for associative address writes. The alignment of
2404 ;; %0 implies that its least significant bit is cleared,
2405 ;; thus we clear the V bit of a matching entry if there is one.
2406 (define_insn "ic_invalidate_line_i"
2407 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
2408 (match_operand:SI 1 "register_operand" "r")] 12)
2409 (clobber (match_scratch:SI 2 "=&r"))]
2411 "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
2412 [(set_attr "length" "8")])
2414 (define_insn "movqi_i"
2415 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
2416 (match_operand:QI 1 "general_movsrc_operand" "ri,m,r,t,l,r"))]
2417 "arith_reg_operand (operands[0], QImode)
2418 || arith_reg_operand (operands[1], QImode)"
2426 [(set_attr "type" "move,load,store,move,move,move")])
2428 (define_expand "movqi"
2429 [(set (match_operand:QI 0 "general_operand" "")
2430 (match_operand:QI 1 "general_operand" ""))]
2432 "{ if (prepare_move_operands (operands, QImode)) DONE; }")
2434 (define_insn "movhi_i"
2435 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
2436 (match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
2437 "arith_reg_operand (operands[0], HImode)
2438 || arith_reg_operand (operands[1], HImode)"
2448 [(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
2450 (define_expand "movhi"
2451 [(set (match_operand:HI 0 "general_movdst_operand" "")
2452 (match_operand:HI 1 "general_movsrc_operand" ""))]
2454 "{ if (prepare_move_operands (operands, HImode)) DONE; }")
2456 ;; ??? This should be a define expand.
2458 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
2459 ;; compiled with -m2 -ml -O3 -funroll-loops
2461 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
2462 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))]
2463 "arith_reg_operand (operands[0], DImode)
2464 || arith_reg_operand (operands[1], DImode)"
2465 "* return output_movedouble (insn, operands, DImode);"
2466 [(set_attr "length" "4")
2467 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
2469 ;; If the output is a register and the input is memory or a register, we have
2470 ;; to be careful and see which word needs to be loaded first.
2473 [(set (match_operand:DI 0 "general_movdst_operand" "")
2474 (match_operand:DI 1 "general_movsrc_operand" ""))]
2476 [(set (match_dup 2) (match_dup 3))
2477 (set (match_dup 4) (match_dup 5))]
2482 if ((GET_CODE (operands[0]) == MEM
2483 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2484 || (GET_CODE (operands[1]) == MEM
2485 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2488 if (GET_CODE (operands[0]) == REG)
2489 regno = REGNO (operands[0]);
2490 else if (GET_CODE (operands[0]) == SUBREG)
2491 regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
2492 else if (GET_CODE (operands[0]) == MEM)
2496 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2498 operands[2] = operand_subword (operands[0], 0, 0, DImode);
2499 operands[3] = operand_subword (operands[1], 0, 0, DImode);
2500 operands[4] = operand_subword (operands[0], 1, 0, DImode);
2501 operands[5] = operand_subword (operands[1], 1, 0, DImode);
2505 operands[2] = operand_subword (operands[0], 1, 0, DImode);
2506 operands[3] = operand_subword (operands[1], 1, 0, DImode);
2507 operands[4] = operand_subword (operands[0], 0, 0, DImode);
2508 operands[5] = operand_subword (operands[1], 0, 0, DImode);
2511 if (operands[2] == 0 || operands[3] == 0
2512 || operands[4] == 0 || operands[5] == 0)
2516 (define_expand "movdi"
2517 [(set (match_operand:DI 0 "general_movdst_operand" "")
2518 (match_operand:DI 1 "general_movsrc_operand" ""))]
2520 "{ if (prepare_move_operands (operands, DImode)) DONE; }")
2522 ;; ??? This should be a define expand.
2524 (define_insn "movdf_k"
2525 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
2526 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
2527 "(! TARGET_SH4 || reload_completed
2528 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
2529 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
2530 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
2531 && (arith_reg_operand (operands[0], DFmode)
2532 || arith_reg_operand (operands[1], DFmode))"
2533 "* return output_movedouble (insn, operands, DFmode);"
2534 [(set_attr "length" "4")
2535 (set_attr "type" "move,pcload,load,store")])
2537 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
2538 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
2539 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
2540 ;; the d/m/c/X alternative, which is split later into single-precision
2541 ;; instructions. And when not optimizing, no splits are done before fixing
2542 ;; up pcloads, so we need usable length information for that.
2543 (define_insn "movdf_i4"
2544 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
2545 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
2546 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
2547 (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
2549 && (arith_reg_operand (operands[0], DFmode)
2550 || arith_reg_operand (operands[1], DFmode))"
2562 [(set_attr_alternative "length"
2563 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
2565 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
2566 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2567 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2569 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
2570 (const_int 8) (const_int 8)])
2571 (set_attr "type" "fmove,move,pcload,load,store,pcload,load,store,load,load")
2572 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
2573 (const_string "double")
2574 (const_string "none")))])
2576 ;; Moving DFmode between fp/general registers through memory
2577 ;; (the top of the stack) is faster than moving through fpul even for
2578 ;; little endian. Because the type of an instruction is important for its
2579 ;; scheduling, it is beneficial to split these operations, rather than
2580 ;; emitting them in one single chunk, even if this will expose a stack
2581 ;; use that will prevent scheduling of other stack accesses beyond this
2584 [(set (match_operand:DF 0 "register_operand" "")
2585 (match_operand:DF 1 "register_operand" ""))
2586 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2587 (clobber (match_scratch:SI 3 "=X"))]
2588 "TARGET_SH4 && reload_completed
2589 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
2595 tos = gen_rtx (MEM, DFmode, gen_rtx (PRE_DEC, Pmode, stack_pointer_rtx));
2596 insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
2597 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2598 tos = gen_rtx (MEM, DFmode, gen_rtx (POST_INC, Pmode, stack_pointer_rtx));
2599 insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
2600 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2604 ;; local-alloc sometimes allocates scratch registers even when not required,
2605 ;; so we must be prepared to handle these.
2607 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
2609 [(set (match_operand:DF 0 "general_movdst_operand" "")
2610 (match_operand:DF 1 "general_movsrc_operand" ""))
2611 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2612 (clobber (match_scratch:SI 3 "X"))]
2615 && true_regnum (operands[0]) < 16
2616 && true_regnum (operands[1]) < 16"
2617 [(set (match_dup 0) (match_dup 1))]
2620 /* If this was a reg <-> mem operation with base + index reg addressing,
2621 we have to handle this in a special way. */
2622 rtx mem = operands[0];
2624 if (! memory_operand (mem, DFmode))
2629 if (GET_CODE (mem) == SUBREG && SUBREG_WORD (mem) == 0)
2630 mem = SUBREG_REG (mem);
2631 if (GET_CODE (mem) == MEM)
2633 rtx addr = XEXP (mem, 0);
2634 if (GET_CODE (addr) == PLUS
2635 && GET_CODE (XEXP (addr, 0)) == REG
2636 && GET_CODE (XEXP (addr, 1)) == REG)
2639 rtx reg0 = gen_rtx (REG, Pmode, 0);
2640 rtx regop = operands[store_p], word0 ,word1;
2642 if (GET_CODE (regop) == SUBREG)
2643 regop = alter_subreg (regop);
2644 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
2648 mem = copy_rtx (mem);
2649 PUT_MODE (mem, SImode);
2650 word0 = gen_rtx(SUBREG, SImode, regop, 0);
2652 ? gen_movsi_ie (mem, word0) : gen_movsi_ie (word0, mem));
2653 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
2654 mem = copy_rtx (mem);
2655 word1 = gen_rtx(SUBREG, SImode, regop, 1);
2657 ? gen_movsi_ie (mem, word1) : gen_movsi_ie (word1, mem));
2658 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
2664 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
2666 [(set (match_operand:DF 0 "register_operand" "")
2667 (match_operand:DF 1 "memory_operand" ""))
2668 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2669 (clobber (reg:SI 0))]
2670 "TARGET_SH4 && reload_completed"
2671 [(parallel [(set (match_dup 0) (match_dup 1))
2673 (clobber (scratch:SI))])]
2676 (define_expand "reload_indf"
2677 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
2678 (match_operand:DF 1 "immediate_operand" "FQ"))
2680 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
2684 (define_expand "reload_outdf"
2685 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
2686 (match_operand:DF 1 "register_operand" "af,r"))
2687 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
2691 ;; Simplify no-op moves.
2693 [(set (match_operand:SF 0 "register_operand" "")
2694 (match_operand:SF 1 "register_operand" ""))
2695 (use (match_operand:PSI 2 "fpscr_operand" ""))
2696 (clobber (match_scratch:SI 3 "X"))]
2697 "TARGET_SH3E && reload_completed
2698 && true_regnum (operands[0]) == true_regnum (operands[1])"
2699 [(set (match_dup 0) (match_dup 0))]
2702 ;; fmovd substitute post-reload splits
2704 [(set (match_operand:DF 0 "register_operand" "")
2705 (match_operand:DF 1 "register_operand" ""))
2706 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2707 (clobber (match_scratch:SI 3 "X"))]
2708 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2709 && true_regnum (operands[0]) >= FIRST_FP_REG
2710 && true_regnum (operands[1]) >= FIRST_FP_REG"
2714 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
2715 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst),
2716 gen_rtx (REG, SFmode, src), operands[2]));
2717 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst + 1),
2718 gen_rtx (REG, SFmode, src + 1), operands[2]));
2723 [(set (match_operand:DF 0 "register_operand" "")
2724 (mem:DF (match_operand:SI 1 "register_operand" "")))
2725 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2726 (clobber (match_scratch:SI 3 "X"))]
2727 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2728 && true_regnum (operands[0]) >= FIRST_FP_REG
2729 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
2733 int regno = true_regnum (operands[0]);
2735 rtx mem2 = gen_rtx (MEM, SFmode, gen_rtx (POST_INC, Pmode, operands[1]));
2737 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2738 regno + !! TARGET_LITTLE_ENDIAN),
2739 mem2, operands[2]));
2740 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[1], NULL_RTX);
2741 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2742 regno + ! TARGET_LITTLE_ENDIAN),
2743 gen_rtx (MEM, SFmode, operands[1]),
2749 [(set (match_operand:DF 0 "register_operand" "")
2750 (match_operand:DF 1 "memory_operand" ""))
2751 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2752 (clobber (match_scratch:SI 3 "X"))]
2753 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2754 && true_regnum (operands[0]) >= FIRST_FP_REG"
2758 int regno = true_regnum (operands[0]);
2759 rtx addr, insn, adjust = NULL_RTX;
2760 rtx mem2 = copy_rtx (operands[1]);
2761 rtx reg0 = gen_rtx_REG (SFmode, regno + !! TARGET_LITTLE_ENDIAN);
2762 rtx reg1 = gen_rtx_REG (SFmode, regno + ! TARGET_LITTLE_ENDIAN);
2764 PUT_MODE (mem2, SFmode);
2765 operands[1] = copy_rtx (mem2);
2766 addr = XEXP (mem2, 0);
2767 if (GET_CODE (addr) != POST_INC)
2769 /* If we have to modify the stack pointer, the value that we have
2770 read with post-increment might be modified by an interrupt,
2771 so write it back. */
2772 if (REGNO (addr) == STACK_POINTER_REGNUM)
2773 adjust = gen_push_e (reg0);
2775 adjust = gen_addsi3 (addr, addr, GEN_INT (-4));
2776 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
2778 addr = XEXP (addr, 0);
2779 insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
2780 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2781 insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
2785 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2790 [(set (match_operand:DF 0 "memory_operand" "")
2791 (match_operand:DF 1 "register_operand" ""))
2792 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2793 (clobber (match_scratch:SI 3 "X"))]
2794 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2795 && true_regnum (operands[1]) >= FIRST_FP_REG"
2799 int regno = true_regnum (operands[1]);
2800 rtx insn, addr, adjust = NULL_RTX;
2802 operands[0] = copy_rtx (operands[0]);
2803 PUT_MODE (operands[0], SFmode);
2804 insn = emit_insn (gen_movsf_ie (operands[0],
2805 gen_rtx (REG, SFmode,
2806 regno + ! TARGET_LITTLE_ENDIAN),
2808 operands[0] = copy_rtx (operands[0]);
2809 addr = XEXP (operands[0], 0);
2810 if (GET_CODE (addr) != PRE_DEC)
2812 adjust = gen_addsi3 (addr, addr, GEN_INT (4));
2813 emit_insn_before (adjust, insn);
2814 XEXP (operands[0], 0) = addr = gen_rtx (PRE_DEC, SImode, addr);
2816 addr = XEXP (addr, 0);
2818 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2819 insn = emit_insn (gen_movsf_ie (operands[0],
2820 gen_rtx (REG, SFmode,
2821 regno + !! TARGET_LITTLE_ENDIAN),
2823 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2827 ;; The '&' for operand 2 is not really true, but push_secondary_reload
2829 ;; Operand 1 must accept FPUL_REGS in case fpul is reloaded to memory,
2830 ;; to avoid a bogus tertiary reload.
2831 ;; We need a tertiary reload when a floating point register is reloaded
2832 ;; to memory, so the predicate for operand 0 must accept this, while the
2833 ;; constraint of operand 1 must reject the secondary reload register.
2834 ;; Thus, the secondary reload register for this case has to be GENERAL_REGS,
2836 ;; By having the predicate for operand 0 reject any register, we make
2837 ;; sure that the ordinary moves that just need an intermediate register
2838 ;; won't get a bogus tertiary reload.
2839 ;; We use tertiary_reload_operand instead of memory_operand here because
2840 ;; memory_operand rejects operands that are not directly addressible, e.g.:
2841 ;; (mem:SF (plus:SI (reg:SI 14 r14)
2842 ;; (const_int 132)))
2844 (define_expand "reload_outsf"
2845 [(parallel [(set (match_operand:SF 2 "register_operand" "=&r")
2846 (match_operand:SF 1 "register_operand" "y"))
2847 (clobber (scratch:SI))])
2848 (parallel [(set (match_operand:SF 0 "tertiary_reload_operand" "=m")
2850 (clobber (scratch:SI))])]
2854 ;; If the output is a register and the input is memory or a register, we have
2855 ;; to be careful and see which word needs to be loaded first.
2858 [(set (match_operand:DF 0 "general_movdst_operand" "")
2859 (match_operand:DF 1 "general_movsrc_operand" ""))]
2861 [(set (match_dup 2) (match_dup 3))
2862 (set (match_dup 4) (match_dup 5))]
2867 if ((GET_CODE (operands[0]) == MEM
2868 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2869 || (GET_CODE (operands[1]) == MEM
2870 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2873 if (GET_CODE (operands[0]) == REG)
2874 regno = REGNO (operands[0]);
2875 else if (GET_CODE (operands[0]) == SUBREG)
2876 regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
2877 else if (GET_CODE (operands[0]) == MEM)
2881 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2883 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2884 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2885 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2886 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
2890 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
2891 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
2892 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
2893 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
2896 if (operands[2] == 0 || operands[3] == 0
2897 || operands[4] == 0 || operands[5] == 0)
2901 ;; If a base address generated by LEGITIMIZE_ADDRESS for SImode is
2902 ;; used only once, let combine add in the index again.
2905 [(set (match_operand:SI 0 "register_operand" "")
2906 (match_operand:SI 1 "" ""))
2907 (clobber (match_operand 2 "register_operand" ""))]
2908 "! reload_in_progress && ! reload_completed"
2912 rtx addr, reg, const_int;
2914 if (GET_CODE (operands[1]) != MEM)
2916 addr = XEXP (operands[1], 0);
2917 if (GET_CODE (addr) != PLUS)
2919 reg = XEXP (addr, 0);
2920 const_int = XEXP (addr, 1);
2921 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
2922 && GET_CODE (const_int) == CONST_INT))
2924 emit_move_insn (operands[2], const_int);
2925 emit_move_insn (operands[0],
2926 change_address (operands[1], VOIDmode,
2927 gen_rtx_PLUS (SImode, reg, operands[2])));
2932 [(set (match_operand:SI 1 "" "")
2933 (match_operand:SI 0 "register_operand" ""))
2934 (clobber (match_operand 2 "register_operand" ""))]
2935 "! reload_in_progress && ! reload_completed"
2939 rtx addr, reg, const_int;
2941 if (GET_CODE (operands[1]) != MEM)
2943 addr = XEXP (operands[1], 0);
2944 if (GET_CODE (addr) != PLUS)
2946 reg = XEXP (addr, 0);
2947 const_int = XEXP (addr, 1);
2948 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
2949 && GET_CODE (const_int) == CONST_INT))
2951 emit_move_insn (operands[2], const_int);
2952 emit_move_insn (change_address (operands[1], VOIDmode,
2953 gen_rtx_PLUS (SImode, reg, operands[2])),
2958 (define_expand "movdf"
2959 [(set (match_operand:DF 0 "general_movdst_operand" "")
2960 (match_operand:DF 1 "general_movsrc_operand" ""))]
2964 if (prepare_move_operands (operands, DFmode)) DONE;
2967 emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
2973 (define_insn "movsf_i"
2974 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
2975 (match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
2978 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
2979 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
2980 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
2981 && (arith_reg_operand (operands[0], SFmode)
2982 || arith_reg_operand (operands[1], SFmode))"
2991 [(set_attr "type" "move,move,pcload,load,store,move,move")])
2993 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
2994 ;; update_flow_info would not know where to put REG_EQUAL notes
2995 ;; when the destination changes mode.
2996 (define_insn "movsf_ie"
2997 [(set (match_operand:SF 0 "general_movdst_operand"
2998 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,y")
2999 (match_operand:SF 1 "general_movsrc_operand"
3000 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y"))
3001 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
3002 (clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X"))]
3005 && (arith_reg_operand (operands[0], SFmode)
3006 || arith_reg_operand (operands[1], SFmode))"
3024 ! move optimized away"
3025 [(set_attr "type" "fmove,move,fmove,fmove,pcload,load,store,pcload,load,store,fmove,fmove,load,*,gp_fpul,gp_fpul,nil")
3026 (set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,4,2,2,0")
3027 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
3028 (const_string "single")
3029 (const_string "none")))])
3031 [(set (match_operand:SF 0 "register_operand" "")
3032 (match_operand:SF 1 "register_operand" ""))
3033 (use (match_operand:PSI 2 "fpscr_operand" "c"))
3034 (clobber (reg:SI 22))]
3036 [(parallel [(set (reg:SF 22) (match_dup 1))
3038 (clobber (scratch:SI))])
3039 (parallel [(set (match_dup 0) (reg:SF 22))
3041 (clobber (scratch:SI))])]
3044 (define_expand "movsf"
3045 [(set (match_operand:SF 0 "general_movdst_operand" "")
3046 (match_operand:SF 1 "general_movsrc_operand" ""))]
3050 if (prepare_move_operands (operands, SFmode))
3054 emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
3059 (define_insn "mov_nop"
3060 [(set (match_operand 0 "register_operand" "") (match_dup 0))]
3063 [(set_attr "length" "0")
3064 (set_attr "type" "nil")])
3066 (define_expand "reload_insf"
3067 [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
3068 (match_operand:SF 1 "immediate_operand" "FQ"))
3070 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
3074 (define_expand "reload_insi"
3075 [(parallel [(set (match_operand:SF 0 "register_operand" "=y")
3076 (match_operand:SF 1 "immediate_operand" "FQ"))
3077 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
3081 (define_insn "*movsi_y"
3082 [(set (match_operand:SI 0 "register_operand" "=y,y")
3083 (match_operand:SI 1 "immediate_operand" "Qi,I"))
3084 (clobber (match_scratch:SI 3 "=&z,r"))]
3086 && (reload_in_progress || reload_completed)"
3088 [(set_attr "length" "4")
3089 (set_attr "type" "pcload,move")])
3092 [(set (match_operand:SI 0 "register_operand" "")
3093 (match_operand:SI 1 "immediate_operand" ""))
3094 (clobber (match_operand:SI 2 "register_operand" ""))]
3096 [(set (match_dup 2) (match_dup 1))
3097 (set (match_dup 0) (match_dup 2))]
3101 [(set (match_operand:SI 0 "register_operand" "")
3102 (match_operand:SI 1 "memory_operand" ""))
3103 (clobber (reg:SI 0))]
3105 [(set (match_dup 0) (match_dup 1))]
3108 ;; ------------------------------------------------------------------------
3109 ;; Define the real conditional branch instructions.
3110 ;; ------------------------------------------------------------------------
3112 (define_insn "branch_true"
3113 [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 0))
3114 (label_ref (match_operand 0 "" ""))
3117 "* return output_branch (1, insn, operands);"
3118 [(set_attr "type" "cbranch")])
3120 (define_insn "branch_false"
3121 [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 0))
3122 (label_ref (match_operand 0 "" ""))
3125 "* return output_branch (0, insn, operands);"
3126 [(set_attr "type" "cbranch")])
3128 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
3129 ;; which destination is too far away.
3130 ;; The const_int_operand is distinct for each branch target; it avoids
3131 ;; unwanted matches with redundant_insn.
3132 (define_insn "block_branch_redirect"
3133 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] 4))]
3136 [(set_attr "length" "0")])
3138 ;; This one has the additional purpose to record a possible scratch register
3139 ;; for the following branch.
3140 (define_insn "indirect_jump_scratch"
3141 [(set (match_operand 0 "register_operand" "=r")
3142 (unspec [(match_operand 1 "const_int_operand" "")] 4))]
3145 [(set_attr "length" "0")])
3147 ;; Conditional branch insns
3149 (define_expand "beq"
3151 (if_then_else (ne (reg:SI 18) (const_int 0))
3152 (label_ref (match_operand 0 "" ""))
3155 "from_compare (operands, EQ);")
3157 (define_expand "bne"
3159 (if_then_else (eq (reg:SI 18) (const_int 0))
3160 (label_ref (match_operand 0 "" ""))
3163 "from_compare (operands, EQ);")
3165 (define_expand "bgt"
3167 (if_then_else (ne (reg:SI 18) (const_int 0))
3168 (label_ref (match_operand 0 "" ""))
3171 "from_compare (operands, GT);")
3173 (define_expand "blt"
3175 (if_then_else (eq (reg:SI 18) (const_int 0))
3176 (label_ref (match_operand 0 "" ""))
3181 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3183 rtx tmp = sh_compare_op0;
3184 sh_compare_op0 = sh_compare_op1;
3185 sh_compare_op1 = tmp;
3186 emit_insn (gen_bgt (operands[0]));
3189 from_compare (operands, GE);
3192 (define_expand "ble"
3194 (if_then_else (eq (reg:SI 18) (const_int 0))
3195 (label_ref (match_operand 0 "" ""))
3202 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3204 rtx tmp = sh_compare_op0;
3205 sh_compare_op0 = sh_compare_op1;
3206 sh_compare_op1 = tmp;
3207 emit_insn (gen_bge (operands[0]));
3210 from_compare (operands, GT);
3213 (define_expand "bge"
3215 (if_then_else (ne (reg:SI 18) (const_int 0))
3216 (label_ref (match_operand 0 "" ""))
3223 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3225 rtx tmp = sh_compare_op0;
3226 sh_compare_op0 = sh_compare_op1;
3227 sh_compare_op1 = tmp;
3228 emit_insn (gen_ble (operands[0]));
3231 from_compare (operands, GE);
3234 (define_expand "bgtu"
3236 (if_then_else (ne (reg:SI 18) (const_int 0))
3237 (label_ref (match_operand 0 "" ""))
3240 "from_compare (operands, GTU); ")
3242 (define_expand "bltu"
3244 (if_then_else (eq (reg:SI 18) (const_int 0))
3245 (label_ref (match_operand 0 "" ""))
3248 "from_compare (operands, GEU);")
3250 (define_expand "bgeu"
3252 (if_then_else (ne (reg:SI 18) (const_int 0))
3253 (label_ref (match_operand 0 "" ""))
3256 "from_compare (operands, GEU);")
3258 (define_expand "bleu"
3260 (if_then_else (eq (reg:SI 18) (const_int 0))
3261 (label_ref (match_operand 0 "" ""))
3264 "from_compare (operands, GTU);")
3266 ;; ------------------------------------------------------------------------
3267 ;; Jump and linkage insns
3268 ;; ------------------------------------------------------------------------
3272 (label_ref (match_operand 0 "" "")))]
3276 /* The length is 16 if the delay slot is unfilled. */
3277 if (get_attr_length(insn) > 4)
3278 return output_far_jump(insn, operands[0]);
3280 return \"bra %l0%#\";
3282 [(set_attr "type" "jump")
3283 (set_attr "needs_delay_slot" "yes")])
3285 (define_insn "calli"
3286 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3287 (match_operand 1 "" ""))
3289 (clobber (reg:SI 17))]
3292 [(set_attr "type" "call")
3293 (set (attr "fp_mode")
3294 (if_then_else (eq_attr "fpu_single" "yes")
3295 (const_string "single") (const_string "double")))
3296 (set_attr "needs_delay_slot" "yes")])
3298 ;; This is a pc-rel call, using bsrf, for use with PIC.
3300 (define_insn "calli_pcrel"
3301 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3302 (match_operand 1 "" ""))
3304 (use (match_operand 2 "" ""))
3305 (clobber (reg:SI 17))]
3308 [(set_attr "type" "call")
3309 (set (attr "fp_mode")
3310 (if_then_else (eq_attr "fpu_single" "yes")
3311 (const_string "single") (const_string "double")))
3312 (set_attr "needs_delay_slot" "yes")])
3314 (define_insn "call_valuei"
3315 [(set (match_operand 0 "" "=rf")
3316 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3317 (match_operand 2 "" "")))
3319 (clobber (reg:SI 17))]
3322 [(set_attr "type" "call")
3323 (set (attr "fp_mode")
3324 (if_then_else (eq_attr "fpu_single" "yes")
3325 (const_string "single") (const_string "double")))
3326 (set_attr "needs_delay_slot" "yes")])
3328 (define_insn "call_valuei_pcrel"
3329 [(set (match_operand 0 "" "=rf")
3330 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3331 (match_operand 2 "" "")))
3333 (use (match_operand 3 "" ""))
3334 (clobber (reg:SI 17))]
3337 [(set_attr "type" "call")
3338 (set (attr "fp_mode")
3339 (if_then_else (eq_attr "fpu_single" "yes")
3340 (const_string "single") (const_string "double")))
3341 (set_attr "needs_delay_slot" "yes")])
3343 (define_expand "call"
3344 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
3345 (match_operand 1 "" ""))
3347 (clobber (reg:SI 17))])]
3350 if (flag_pic && ! TARGET_SH1 && ! flag_unroll_loops
3351 && GET_CODE (operands[0]) == MEM
3352 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
3354 rtx reg = gen_reg_rtx (SImode), lab = gen_label_rtx ();
3356 if (SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
3357 emit_insn (gen_sym_label2reg (reg, XEXP (operands[0], 0), lab));
3359 emit_insn (gen_symPLT_label2reg (reg, XEXP (operands[0], 0), lab));
3361 emit_call_insn (gen_calli_pcrel (operands[0], operands[1], lab));
3365 operands[0] = force_reg (SImode, XEXP (operands[0], 0));")
3367 (define_expand "call_value"
3368 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
3369 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
3370 (match_operand 2 "" "")))
3372 (clobber (reg:SI 17))])]
3375 if (flag_pic && ! TARGET_SH1 && ! flag_unroll_loops
3376 && GET_CODE (operands[1]) == MEM
3377 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
3379 rtx reg = gen_reg_rtx (SImode), lab = gen_label_rtx ();
3381 if (SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
3382 emit_insn (gen_sym_label2reg (reg, XEXP (operands[1], 0), lab));
3384 emit_insn (gen_symPLT_label2reg (reg, XEXP (operands[1], 0), lab));
3386 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[1],
3391 operands[1] = force_reg (SImode, XEXP (operands[1], 0));")
3393 (define_insn "indirect_jump"
3395 (match_operand:SI 0 "arith_reg_operand" "r"))]
3398 [(set_attr "needs_delay_slot" "yes")
3399 (set_attr "type" "jump_ind")])
3401 ;; The use of operand 1 / 2 helps us distinguish case table jumps
3402 ;; which can be present in structured code from indirect jumps which can not
3403 ;; be present in structured code. This allows -fprofile-arcs to work.
3405 ;; For SH1 processors.
3406 (define_insn "casesi_jump_1"
3408 (match_operand:SI 0 "register_operand" "r"))
3409 (use (label_ref (match_operand 1 "" "")))]
3412 [(set_attr "needs_delay_slot" "yes")
3413 (set_attr "type" "jump_ind")])
3415 ;; For all later processors.
3416 (define_insn "casesi_jump_2"
3417 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
3418 (label_ref (match_operand 1 "" ""))))
3419 (use (label_ref (match_operand 2 "" "")))]
3420 "! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn"
3422 [(set_attr "needs_delay_slot" "yes")
3423 (set_attr "type" "jump_ind")])
3425 ;; Call subroutine returning any type.
3426 ;; ??? This probably doesn't work.
3428 (define_expand "untyped_call"
3429 [(parallel [(call (match_operand 0 "" "")
3431 (match_operand 1 "" "")
3432 (match_operand 2 "" "")])]
3438 emit_call_insn (gen_call (operands[0], const0_rtx));
3440 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3442 rtx set = XVECEXP (operands[2], 0, i);
3443 emit_move_insn (SET_DEST (set), SET_SRC (set));
3446 /* The optimizer does not know that the call sets the function value
3447 registers we stored in the result block. We avoid problems by
3448 claiming that all hard registers are used and clobbered at this
3450 emit_insn (gen_blockage ());
3455 ;; ------------------------------------------------------------------------
3457 ;; ------------------------------------------------------------------------
3461 (eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
3462 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
3465 [(set_attr "type" "arith")])
3472 ;; Load address of a label. This is only generated by the casesi expand,
3473 ;; and by machine_dependent_reorg (fixing up fp moves).
3474 ;; This must use unspec, because this only works for labels that are
3479 (unspec [(label_ref (match_operand 0 "" ""))] 1))]
3482 [(set_attr "in_delay_slot" "no")
3483 (set_attr "type" "arith")])
3485 (define_expand "GOTaddr2picreg"
3486 [(set (reg:SI 0) (const (unspec [(const (unspec [(match_dup 1)] 6))] 1)))
3487 (set (match_dup 0) (const (unspec [(match_dup 1)] 6)))
3488 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI 0)))]
3491 operands[0] = pic_offset_table_rtx;
3492 current_function_uses_pic_offset_table = 1;
3493 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
3497 (define_expand "sym_label2reg"
3498 [(set (match_operand:SI 0 "" "")
3500 (unspec [(match_operand:SI 1 "" "")] 6)
3501 (const (plus:SI (label_ref (match_operand:SI 2 "" ""))
3505 (define_expand "symGOT2reg"
3506 [(set (match_operand:SI 0 "" "")
3507 (const (unspec [(match_operand:SI 1 "" "")] 7)))
3508 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
3509 (set (match_dup 0) (mem:SI (match_dup 0)))]
3513 operands[2] = pic_offset_table_rtx;
3514 current_function_uses_pic_offset_table = 1;
3517 (define_expand "symGOTOFF2reg"
3518 [(set (match_operand:SI 0 "" "")
3519 (const (unspec [(match_operand:SI 1 "" "")] 8)))
3520 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3524 operands[2] = pic_offset_table_rtx;
3525 current_function_uses_pic_offset_table = 1;
3528 (define_expand "symPLT_label2reg"
3529 [(set (match_operand:SI 0 "" "")
3532 (unspec [(match_operand:SI 1 "" "")] 9))
3533 (const (plus:SI (label_ref (match_operand:SI 2 "" ""))
3537 ;; case instruction for switch statements.
3539 ;; Operand 0 is index
3540 ;; operand 1 is the minimum bound
3541 ;; operand 2 is the maximum bound - minimum bound + 1
3542 ;; operand 3 is CODE_LABEL for the table;
3543 ;; operand 4 is the CODE_LABEL to go to if index out of range.
3545 (define_expand "casesi"
3546 [(match_operand:SI 0 "arith_reg_operand" "")
3547 (match_operand:SI 1 "arith_reg_operand" "")
3548 (match_operand:SI 2 "arith_reg_operand" "")
3549 (match_operand 3 "" "") (match_operand 4 "" "")]
3553 rtx reg = gen_reg_rtx (SImode);
3554 rtx reg2 = gen_reg_rtx (SImode);
3555 operands[1] = copy_to_mode_reg (SImode, operands[1]);
3556 operands[2] = copy_to_mode_reg (SImode, operands[2]);
3557 /* If optimizing, casesi_worker depends on the mode of the instruction
3558 before label it 'uses' - operands[3]. */
3559 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
3561 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
3563 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
3565 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
3566 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
3567 operands[3], but to lab. We will fix this up in
3568 machine_dependent_reorg. */
3573 (define_expand "casesi_0"
3574 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
3575 (set (match_dup 4) (minus:SI (match_dup 4)
3576 (match_operand:SI 1 "arith_operand" "")))
3578 (gtu:SI (match_dup 4)
3579 (match_operand:SI 2 "arith_reg_operand" "")))
3581 (if_then_else (ne (reg:SI 18)
3583 (label_ref (match_operand 3 "" ""))
3588 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
3589 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
3590 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
3592 (define_insn "casesi_worker_0"
3593 [(set (match_operand:SI 0 "register_operand" "=r,r")
3594 (unspec [(match_operand 1 "register_operand" "0,r")
3595 (label_ref (match_operand 2 "" ""))] 2))
3596 (clobber (match_scratch:SI 3 "=X,1"))
3597 (clobber (match_scratch:SI 4 "=&z,z"))]
3602 [(set (match_operand:SI 0 "register_operand" "")
3603 (unspec [(match_operand 1 "register_operand" "")
3604 (label_ref (match_operand 2 "" ""))] 2))
3605 (clobber (match_scratch:SI 3 ""))
3606 (clobber (match_scratch:SI 4 ""))]
3607 "! TARGET_SH2 && reload_completed"
3608 [(set (reg:SI 0) (unspec [(label_ref (match_dup 2))] 1))
3609 (parallel [(set (match_dup 0)
3610 (unspec [(reg:SI 0) (match_dup 1) (label_ref (match_dup 2))] 2))
3611 (clobber (match_dup 3))])
3612 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI 0)))]
3613 "LABEL_NUSES (operands[2])++;")
3616 [(set (match_operand:SI 0 "register_operand" "")
3617 (unspec [(match_operand 1 "register_operand" "")
3618 (label_ref (match_operand 2 "" ""))] 2))
3619 (clobber (match_scratch:SI 3 ""))
3620 (clobber (match_scratch:SI 4 ""))]
3621 "TARGET_SH2 && reload_completed"
3622 [(set (reg:SI 0) (unspec [(label_ref (match_dup 2))] 1))
3623 (parallel [(set (match_dup 0)
3624 (unspec [(reg:SI 0) (match_dup 1) (label_ref (match_dup 2))] 2))
3625 (clobber (match_dup 3))])]
3626 "LABEL_NUSES (operands[2])++;")
3628 (define_insn "*casesi_worker"
3629 [(set (match_operand:SI 0 "register_operand" "=r,r")
3630 (unspec [(reg:SI 0) (match_operand 1 "register_operand" "0,r")
3631 (label_ref (match_operand 2 "" ""))] 2))
3632 (clobber (match_scratch:SI 3 "=X,1"))]
3636 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
3638 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
3641 switch (GET_MODE (diff_vec))
3644 return \"shll2 %1\;mov.l @(r0,%1),%0\";
3646 return \"add %1,%1\;mov.w @(r0,%1),%0\";
3648 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
3649 return \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
3650 return \"mov.b @(r0,%1),%0\";
3655 [(set_attr "length" "4")])
3657 (define_expand "return"
3659 "reload_completed && ! sh_need_epilogue ()"
3662 (define_insn "*return_i"
3666 [(set_attr "type" "return")
3667 (set_attr "needs_delay_slot" "yes")])
3669 (define_expand "prologue"
3672 "sh_expand_prologue (); DONE;")
3674 (define_expand "epilogue"
3677 "sh_expand_epilogue ();")
3679 (define_insn "blockage"
3680 [(unspec_volatile [(const_int 0)] 0)]
3683 [(set_attr "length" "0")])
3685 ;; ------------------------------------------------------------------------
3687 ;; ------------------------------------------------------------------------
3690 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3691 (eq:SI (reg:SI 18) (const_int 1)))]
3694 [(set_attr "type" "arith")])
3696 (define_expand "seq"
3697 [(set (match_operand:SI 0 "arith_reg_operand" "")
3700 "operands[1] = prepare_scc_operands (EQ);")
3702 (define_expand "slt"
3703 [(set (match_operand:SI 0 "arith_reg_operand" "")
3706 "operands[1] = prepare_scc_operands (LT);")
3708 (define_expand "sle"
3709 [(match_operand:SI 0 "arith_reg_operand" "")]
3713 rtx tmp = sh_compare_op0;
3714 sh_compare_op0 = sh_compare_op1;
3715 sh_compare_op1 = tmp;
3716 emit_insn (gen_sge (operands[0]));
3720 (define_expand "sgt"
3721 [(set (match_operand:SI 0 "arith_reg_operand" "")
3724 "operands[1] = prepare_scc_operands (GT);")
3726 (define_expand "sge"
3727 [(set (match_operand:SI 0 "arith_reg_operand" "")
3732 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3736 rtx lab = gen_label_rtx ();
3737 prepare_scc_operands (EQ);
3738 emit_jump_insn (gen_branch_true (lab));
3739 prepare_scc_operands (GT);
3741 emit_insn (gen_movt (operands[0]));
3744 emit_insn (gen_movnegt (operands[0], prepare_scc_operands (LT)));
3747 operands[1] = prepare_scc_operands (GE);
3750 (define_expand "sgtu"
3751 [(set (match_operand:SI 0 "arith_reg_operand" "")
3754 "operands[1] = prepare_scc_operands (GTU);")
3756 (define_expand "sltu"
3757 [(set (match_operand:SI 0 "arith_reg_operand" "")
3760 "operands[1] = prepare_scc_operands (LTU);")
3762 (define_expand "sleu"
3763 [(set (match_operand:SI 0 "arith_reg_operand" "")
3766 "operands[1] = prepare_scc_operands (LEU);")
3768 (define_expand "sgeu"
3769 [(set (match_operand:SI 0 "arith_reg_operand" "")
3772 "operands[1] = prepare_scc_operands (GEU);")
3774 ;; sne moves the complement of the T reg to DEST like this:
3778 ;; This is better than xoring compare result with 1 because it does
3779 ;; not require r0 and further, the -1 may be CSE-ed or lifted out of a
3782 (define_expand "sne"
3783 [(set (match_dup 2) (const_int -1))
3784 (parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
3785 (neg:SI (plus:SI (match_dup 1)
3788 (ne:SI (ior:SI (match_dup 1) (match_dup 2))
3793 operands[1] = prepare_scc_operands (EQ);
3794 operands[2] = gen_reg_rtx (SImode);
3797 ;; Use the same trick for FP sle / sge
3798 (define_expand "movnegt"
3799 [(set (match_dup 2) (const_int -1))
3800 (parallel [(set (match_operand 0 "" "")
3801 (neg:SI (plus:SI (match_dup 1)
3804 (ne:SI (ior:SI (match_operand 1 "" "") (match_dup 2))
3807 "operands[2] = gen_reg_rtx (SImode);")
3809 ;; Recognize mov #-1/negc/neg sequence, and change it to movt/add #-1.
3810 ;; This prevents a regression that occurred when we switched from xor to
3814 [(set (match_operand:SI 0 "arith_reg_operand" "")
3815 (plus:SI (reg:SI 18)
3818 [(set (match_dup 0) (eq:SI (reg:SI 18) (const_int 1)))
3819 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
3822 ;; -------------------------------------------------------------------------
3823 ;; Instructions to cope with inline literal tables
3824 ;; -------------------------------------------------------------------------
3826 ; 2 byte integer in line
3828 (define_insn "consttable_2"
3829 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 2)]
3833 assemble_integer (operands[0], 2, 1);
3836 [(set_attr "length" "2")
3837 (set_attr "in_delay_slot" "no")])
3839 ; 4 byte integer in line
3841 (define_insn "consttable_4"
3842 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 4)]
3846 assemble_integer (operands[0], 4, 1);
3849 [(set_attr "length" "4")
3850 (set_attr "in_delay_slot" "no")])
3852 ; 8 byte integer in line
3854 (define_insn "consttable_8"
3855 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 6)]
3859 assemble_integer (operands[0], 8, 1);
3862 [(set_attr "length" "8")
3863 (set_attr "in_delay_slot" "no")])
3865 ; 4 byte floating point
3867 (define_insn "consttable_sf"
3868 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")] 4)]
3872 union real_extract u;
3873 bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
3874 assemble_real (u.d, SFmode);
3877 [(set_attr "length" "4")
3878 (set_attr "in_delay_slot" "no")])
3880 ; 8 byte floating point
3882 (define_insn "consttable_df"
3883 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")] 6)]
3887 union real_extract u;
3888 bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
3889 assemble_real (u.d, DFmode);
3892 [(set_attr "length" "8")
3893 (set_attr "in_delay_slot" "no")])
3895 ;; Alignment is needed for some constant tables; it may also be added for
3896 ;; Instructions at the start of loops, or after unconditional branches.
3897 ;; ??? We would get more accurate lengths if we did instruction
3898 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
3899 ;; here is too conservative.
3901 ; align to a two byte boundary
3903 (define_expand "align_2"
3904 [(unspec_volatile [(const_int 1)] 1)]
3908 ; align to a four byte boundary
3909 ;; align_4 and align_log are instructions for the starts of loops, or
3910 ;; after unconditional branches, which may take up extra room.
3912 (define_expand "align_4"
3913 [(unspec_volatile [(const_int 2)] 1)]
3917 ; align to a cache line boundary
3919 (define_insn "align_log"
3920 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 1)]
3923 [(set_attr "length" "0")
3924 (set_attr "in_delay_slot" "no")])
3926 ; emitted at the end of the literal table, used to emit the
3927 ; 32bit branch labels if needed.
3929 (define_insn "consttable_end"
3930 [(unspec_volatile [(const_int 0)] 11)]
3932 "* return output_jump_label_table ();"
3933 [(set_attr "in_delay_slot" "no")])
3935 ;; -------------------------------------------------------------------------
3937 ;; -------------------------------------------------------------------------
3939 ;; String/block move insn.
3941 (define_expand "movstrsi"
3942 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
3943 (mem:BLK (match_operand:BLK 1 "" "")))
3944 (use (match_operand:SI 2 "nonmemory_operand" ""))
3945 (use (match_operand:SI 3 "immediate_operand" ""))
3946 (clobber (reg:SI 17))
3947 (clobber (reg:SI 4))
3948 (clobber (reg:SI 5))
3949 (clobber (reg:SI 0))])]
3953 if(expand_block_move (operands))
3958 (define_insn "block_move_real"
3959 [(parallel [(set (mem:BLK (reg:SI 4))
3960 (mem:BLK (reg:SI 5)))
3961 (use (match_operand:SI 0 "arith_reg_operand" "r"))
3962 (clobber (reg:SI 17))
3963 (clobber (reg:SI 0))])]
3966 [(set_attr "type" "sfunc")
3967 (set_attr "needs_delay_slot" "yes")])
3969 (define_insn "block_lump_real"
3970 [(parallel [(set (mem:BLK (reg:SI 4))
3971 (mem:BLK (reg:SI 5)))
3972 (use (match_operand:SI 0 "arith_reg_operand" "r"))
3974 (clobber (reg:SI 17))
3975 (clobber (reg:SI 18))
3976 (clobber (reg:SI 4))
3977 (clobber (reg:SI 5))
3978 (clobber (reg:SI 6))
3979 (clobber (reg:SI 0))])]
3982 [(set_attr "type" "sfunc")
3983 (set_attr "needs_delay_slot" "yes")])
3985 (define_insn "block_move_real_i4"
3986 [(parallel [(set (mem:BLK (reg:SI 4))
3987 (mem:BLK (reg:SI 5)))
3988 (use (match_operand:SI 0 "arith_reg_operand" "r"))
3989 (clobber (reg:SI 17))
3990 (clobber (reg:SI 0))
3991 (clobber (reg:SI 1))
3992 (clobber (reg:SI 2))])]
3995 [(set_attr "type" "sfunc")
3996 (set_attr "needs_delay_slot" "yes")])
3998 (define_insn "block_lump_real_i4"
3999 [(parallel [(set (mem:BLK (reg:SI 4))
4000 (mem:BLK (reg:SI 5)))
4001 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4003 (clobber (reg:SI 17))
4004 (clobber (reg:SI 18))
4005 (clobber (reg:SI 4))
4006 (clobber (reg:SI 5))
4007 (clobber (reg:SI 6))
4008 (clobber (reg:SI 0))
4009 (clobber (reg:SI 1))
4010 (clobber (reg:SI 2))
4011 (clobber (reg:SI 3))])]
4014 [(set_attr "type" "sfunc")
4015 (set_attr "needs_delay_slot" "yes")])
4017 ;; -------------------------------------------------------------------------
4018 ;; Floating point instructions.
4019 ;; -------------------------------------------------------------------------
4021 ;; ??? All patterns should have a type attribute.
4023 (define_expand "fpu_switch0"
4024 [(set (match_operand:SI 0 "" "") (match_dup 2))
4025 (set (match_dup 1) (mem:PSI (match_dup 0)))]
4029 operands[1] = get_fpscr_rtx ();
4030 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
4032 operands[2] = legitimize_pic_address (operands[2], SImode,
4033 no_new_pseudos ? operands[0] : 0);
4036 (define_expand "fpu_switch1"
4037 [(set (match_operand:SI 0 "" "") (match_dup 2))
4038 (set (match_dup 3) (plus:SI (match_dup 0) (const_int 4)))
4039 (set (match_dup 1) (mem:PSI (match_dup 3)))]
4043 operands[1] = get_fpscr_rtx ();
4044 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
4046 operands[2] = legitimize_pic_address (operands[2], SImode,
4047 no_new_pseudos ? operands[0] : 0);
4048 operands[3] = no_new_pseudos ? operands[0] : gen_reg_rtx (SImode);
4051 (define_expand "movpsi"
4052 [(set (match_operand:PSI 0 "register_operand" "")
4053 (match_operand:PSI 1 "general_movsrc_operand" ""))]
4057 ;; The c / m alternative is a fake to guide reload to load directly into
4058 ;; fpscr, since reload doesn't know how to use post-increment.
4059 ;; GO_IF_LEGITIMATE_ADDRESS guards about bogus addresses before reload,
4060 ;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
4061 ;; predicate after reload.
4062 ;; The gp_fpul type for r/!c might look a bit odd, but it actually schedules
4063 ;; like a gpr <-> fpul move.
4064 (define_insn "fpu_switch"
4065 [(set (match_operand:PSI 0 "register_operand" "=c,c,r,c,c,r,m,r")
4066 (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c"))]
4068 || true_regnum (operands[0]) != FPSCR_REG || GET_CODE (operands[1]) != MEM
4069 || GET_CODE (XEXP (operands[1], 0)) != PLUS"
4071 ! precision stays the same
4079 [(set_attr "length" "0,2,2,4,2,2,2,2")
4080 (set_attr "type" "dfp_conv,dfp_conv,load,dfp_conv,dfp_conv,move,store,gp_fpul")])
4083 [(set (reg:PSI 48) (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
4084 "find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
4085 [(set (match_dup 0) (match_dup 0))]
4088 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
4089 gen_rtx (MEM, PSImode,
4090 gen_rtx (POST_INC, Pmode,
4092 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
4096 [(set (reg:PSI 48) (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
4098 [(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))]
4101 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
4102 gen_rtx (MEM, PSImode,
4103 gen_rtx (POST_INC, Pmode,
4105 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
4108 ;; ??? This uses the fp unit, but has no type indicating that.
4109 ;; If we did that, this would either give a bogus latency or introduce
4110 ;; a bogus FIFO constraint.
4111 ;; Since this insn is currently only used for prologues/epilogues,
4112 ;; it is probably best to claim no function unit, which matches the
4114 (define_insn "toggle_sz"
4115 [(set (reg:PSI 48) (xor:PSI (reg:PSI 48) (const_int 1048576)))]
4119 (define_expand "addsf3"
4120 [(match_operand:SF 0 "arith_reg_operand" "")
4121 (match_operand:SF 1 "arith_reg_operand" "")
4122 (match_operand:SF 2 "arith_reg_operand" "")]
4124 "{ expand_sf_binop (&gen_addsf3_i, operands); DONE; }")
4126 (define_insn "addsf3_i"
4127 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4128 (plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
4129 (match_operand:SF 2 "arith_reg_operand" "f")))
4130 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4133 [(set_attr "type" "fp")
4134 (set_attr "fp_mode" "single")])
4136 (define_expand "subsf3"
4137 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4138 (match_operand:SF 1 "fp_arith_reg_operand" "")
4139 (match_operand:SF 2 "fp_arith_reg_operand" "")]
4141 "{ expand_sf_binop (&gen_subsf3_i, operands); DONE; }")
4143 (define_insn "subsf3_i"
4144 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4145 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
4146 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
4147 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4150 [(set_attr "type" "fp")
4151 (set_attr "fp_mode" "single")])
4153 ;; Unfortunately, the combiner is unable to cope with the USE of the FPSCR
4154 ;; register in feeding fp instructions. Thus, we cannot generate fmac for
4155 ;; mixed-precision SH4 targets. To allow it to be still generated for the
4156 ;; SH3E, we use a separate insn for SH3E mulsf3.
4158 (define_expand "mulsf3"
4159 [(match_operand:SF 0 "arith_reg_operand" "")
4160 (match_operand:SF 1 "arith_reg_operand" "")
4161 (match_operand:SF 2 "arith_reg_operand" "")]
4166 expand_sf_binop (&gen_mulsf3_i4, operands);
4168 emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
4172 (define_insn "mulsf3_i4"
4173 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4174 (mult:SF (match_operand:SF 1 "arith_reg_operand" "%0")
4175 (match_operand:SF 2 "arith_reg_operand" "f")))
4176 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4179 [(set_attr "type" "fp")
4180 (set_attr "fp_mode" "single")])
4182 (define_insn "mulsf3_ie"
4183 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4184 (mult:SF (match_operand:SF 1 "arith_reg_operand" "%0")
4185 (match_operand:SF 2 "arith_reg_operand" "f")))]
4186 "TARGET_SH3E && ! TARGET_SH4"
4188 [(set_attr "type" "fp")])
4190 (define_insn "*macsf3"
4191 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4192 (plus:SF (mult:SF (match_operand:SF 1 "arith_reg_operand" "%w")
4193 (match_operand:SF 2 "arith_reg_operand" "f"))
4194 (match_operand:SF 3 "arith_reg_operand" "0")))
4195 (use (match_operand:PSI 4 "fpscr_operand" "c"))]
4196 "TARGET_SH3E && ! TARGET_SH4"
4198 [(set_attr "type" "fp")
4199 (set_attr "fp_mode" "single")])
4201 (define_expand "divsf3"
4202 [(match_operand:SF 0 "arith_reg_operand" "")
4203 (match_operand:SF 1 "arith_reg_operand" "")
4204 (match_operand:SF 2 "arith_reg_operand" "")]
4206 "{ expand_sf_binop (&gen_divsf3_i, operands); DONE; }")
4208 (define_insn "divsf3_i"
4209 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4210 (div:SF (match_operand:SF 1 "arith_reg_operand" "0")
4211 (match_operand:SF 2 "arith_reg_operand" "f")))
4212 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4215 [(set_attr "type" "fdiv")
4216 (set_attr "fp_mode" "single")])
4218 (define_expand "floatsisf2"
4220 (match_operand:SI 1 "arith_reg_operand" ""))
4221 (parallel [(set (match_operand:SF 0 "arith_reg_operand" "")
4222 (float:SF (reg:SI 22)))
4223 (use (match_dup 2))])]
4229 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 22),
4231 emit_sf_insn (gen_floatsisf2_i4 (operands[0], get_fpscr_rtx ()));
4234 operands[2] = get_fpscr_rtx ();
4237 (define_insn "floatsisf2_i4"
4238 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4239 (float:SF (reg:SI 22)))
4240 (use (match_operand:PSI 1 "fpscr_operand" "c"))]
4243 [(set_attr "type" "fp")
4244 (set_attr "fp_mode" "single")])
4246 (define_insn "*floatsisf2_ie"
4247 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4248 (float:SF (reg:SI 22)))]
4249 "TARGET_SH3E && ! TARGET_SH4"
4251 [(set_attr "type" "fp")])
4253 (define_expand "fix_truncsfsi2"
4255 (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4256 (set (match_operand:SI 0 "arith_reg_operand" "=r")
4263 emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[1], get_fpscr_rtx ()));
4264 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
4265 gen_rtx (REG, SImode, 22)));
4270 (define_insn "fix_truncsfsi2_i4"
4272 (fix:SI (match_operand:SF 0 "arith_reg_operand" "f")))
4273 (use (match_operand:PSI 1 "fpscr_operand" "c"))]
4276 [(set_attr "type" "fp")
4277 (set_attr "fp_mode" "single")])
4279 (define_insn "fix_truncsfsi2_i4_2"
4280 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4281 (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4283 (clobber (reg:SI 22))]
4286 [(set_attr "length" "4")
4287 (set_attr "fp_mode" "single")])
4290 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4291 (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4292 (use (match_operand:PSI 2 "fpscr_operand" "c"))
4293 (clobber (reg:SI 22))]
4295 [(parallel [(set (reg:SI 22) (fix:SI (match_dup 1)))
4296 (use (match_dup 2))])
4297 (set (match_dup 0) (reg:SI 22))])
4299 (define_insn "*fixsfsi"
4301 (fix:SI (match_operand:SF 0 "arith_reg_operand" "f")))]
4302 "TARGET_SH3E && ! TARGET_SH4"
4304 [(set_attr "type" "fp")])
4306 (define_insn "cmpgtsf_t"
4307 [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "arith_reg_operand" "f")
4308 (match_operand:SF 1 "arith_reg_operand" "f")))]
4309 "TARGET_SH3E && ! TARGET_SH4"
4311 [(set_attr "type" "fp")
4312 (set_attr "fp_mode" "single")])
4314 (define_insn "cmpeqsf_t"
4315 [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
4316 (match_operand:SF 1 "arith_reg_operand" "f")))]
4317 "TARGET_SH3E && ! TARGET_SH4"
4319 [(set_attr "type" "fp")
4320 (set_attr "fp_mode" "single")])
4322 (define_insn "ieee_ccmpeqsf_t"
4323 [(set (reg:SI 18) (ior:SI (reg:SI 18)
4324 (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
4325 (match_operand:SF 1 "arith_reg_operand" "f"))))]
4326 "TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
4327 "* return output_ieee_ccmpeq (insn, operands);"
4328 [(set_attr "length" "4")])
4331 (define_insn "cmpgtsf_t_i4"
4332 [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "arith_reg_operand" "f")
4333 (match_operand:SF 1 "arith_reg_operand" "f")))
4334 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4337 [(set_attr "type" "fp")
4338 (set_attr "fp_mode" "single")])
4340 (define_insn "cmpeqsf_t_i4"
4341 [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
4342 (match_operand:SF 1 "arith_reg_operand" "f")))
4343 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4346 [(set_attr "type" "fp")
4347 (set_attr "fp_mode" "single")])
4349 (define_insn "*ieee_ccmpeqsf_t_4"
4350 [(set (reg:SI 18) (ior:SI (reg:SI 18)
4351 (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
4352 (match_operand:SF 1 "arith_reg_operand" "f"))))
4353 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4354 "TARGET_IEEE && TARGET_SH4"
4355 "* return output_ieee_ccmpeq (insn, operands);"
4356 [(set_attr "length" "4")
4357 (set_attr "fp_mode" "single")])
4359 (define_expand "cmpsf"
4360 [(set (reg:SI 18) (compare (match_operand:SF 0 "arith_operand" "")
4361 (match_operand:SF 1 "arith_operand" "")))]
4365 sh_compare_op0 = operands[0];
4366 sh_compare_op1 = operands[1];
4370 (define_expand "negsf2"
4371 [(match_operand:SF 0 "arith_reg_operand" "")
4372 (match_operand:SF 1 "arith_reg_operand" "")]
4374 "{ expand_sf_unop (&gen_negsf2_i, operands); DONE; }")
4376 (define_insn "negsf2_i"
4377 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4378 (neg:SF (match_operand:SF 1 "arith_reg_operand" "0")))
4379 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4382 [(set_attr "type" "fmove")
4383 (set_attr "fp_mode" "single")])
4385 (define_expand "sqrtsf2"
4386 [(match_operand:SF 0 "arith_reg_operand" "")
4387 (match_operand:SF 1 "arith_reg_operand" "")]
4389 "{ expand_sf_unop (&gen_sqrtsf2_i, operands); DONE; }")
4391 (define_insn "sqrtsf2_i"
4392 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4393 (sqrt:SF (match_operand:SF 1 "arith_reg_operand" "0")))
4394 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4397 [(set_attr "type" "fdiv")
4398 (set_attr "fp_mode" "single")])
4400 (define_expand "abssf2"
4401 [(match_operand:SF 0 "arith_reg_operand" "")
4402 (match_operand:SF 1 "arith_reg_operand" "")]
4404 "{ expand_sf_unop (&gen_abssf2_i, operands); DONE; }")
4406 (define_insn "abssf2_i"
4407 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4408 (abs:SF (match_operand:SF 1 "arith_reg_operand" "0")))
4409 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4412 [(set_attr "type" "fmove")
4413 (set_attr "fp_mode" "single")])
4415 (define_expand "adddf3"
4416 [(match_operand:DF 0 "arith_reg_operand" "")
4417 (match_operand:DF 1 "arith_reg_operand" "")
4418 (match_operand:DF 2 "arith_reg_operand" "")]
4420 "{ expand_df_binop (&gen_adddf3_i, operands); DONE; }")
4422 (define_insn "adddf3_i"
4423 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4424 (plus:DF (match_operand:DF 1 "arith_reg_operand" "%0")
4425 (match_operand:DF 2 "arith_reg_operand" "f")))
4426 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4429 [(set_attr "type" "dfp_arith")
4430 (set_attr "fp_mode" "double")])
4432 (define_expand "subdf3"
4433 [(match_operand:DF 0 "arith_reg_operand" "")
4434 (match_operand:DF 1 "arith_reg_operand" "")
4435 (match_operand:DF 2 "arith_reg_operand" "")]
4437 "{ expand_df_binop (&gen_subdf3_i, operands); DONE; }")
4439 (define_insn "subdf3_i"
4440 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4441 (minus:DF (match_operand:DF 1 "arith_reg_operand" "0")
4442 (match_operand:DF 2 "arith_reg_operand" "f")))
4443 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4446 [(set_attr "type" "dfp_arith")
4447 (set_attr "fp_mode" "double")])
4449 (define_expand "muldf3"
4450 [(match_operand:DF 0 "arith_reg_operand" "")
4451 (match_operand:DF 1 "arith_reg_operand" "")
4452 (match_operand:DF 2 "arith_reg_operand" "")]
4454 "{ expand_df_binop (&gen_muldf3_i, operands); DONE; }")
4456 (define_insn "muldf3_i"
4457 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4458 (mult:DF (match_operand:DF 1 "arith_reg_operand" "%0")
4459 (match_operand:DF 2 "arith_reg_operand" "f")))
4460 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4463 [(set_attr "type" "dfp_arith")
4464 (set_attr "fp_mode" "double")])
4466 (define_expand "divdf3"
4467 [(match_operand:DF 0 "arith_reg_operand" "")
4468 (match_operand:DF 1 "arith_reg_operand" "")
4469 (match_operand:DF 2 "arith_reg_operand" "")]
4471 "{ expand_df_binop (&gen_divdf3_i, operands); DONE; }")
4473 (define_insn "divdf3_i"
4474 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4475 (div:DF (match_operand:DF 1 "arith_reg_operand" "0")
4476 (match_operand:DF 2 "arith_reg_operand" "f")))
4477 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4480 [(set_attr "type" "dfdiv")
4481 (set_attr "fp_mode" "double")])
4483 (define_expand "floatsidf2"
4484 [(match_operand:DF 0 "arith_reg_operand" "")
4485 (match_operand:SI 1 "arith_reg_operand" "")]
4489 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 22), operands[1]));
4490 emit_df_insn (gen_floatsidf2_i (operands[0], get_fpscr_rtx ()));
4494 (define_insn "floatsidf2_i"
4495 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4496 (float:DF (reg:SI 22)))
4497 (use (match_operand:PSI 1 "fpscr_operand" "c"))]
4500 [(set_attr "type" "dfp_conv")
4501 (set_attr "fp_mode" "double")])
4503 (define_expand "fix_truncdfsi2"
4504 [(match_operand:SI 0 "arith_reg_operand" "=r")
4505 (match_operand:DF 1 "arith_reg_operand" "f")]
4509 emit_df_insn (gen_fix_truncdfsi2_i (operands[1], get_fpscr_rtx ()));
4510 emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (REG, SImode, 22)));
4514 (define_insn "fix_truncdfsi2_i"
4516 (fix:SI (match_operand:DF 0 "arith_reg_operand" "f")))
4517 (use (match_operand:PSI 1 "fpscr_operand" "c"))]
4520 [(set_attr "type" "dfp_conv")
4521 (set_attr "fp_mode" "double")])
4523 (define_insn "fix_truncdfsi2_i4"
4524 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4525 (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4526 (use (match_operand:PSI 2 "fpscr_operand" "c"))
4527 (clobber (reg:SI 22))]
4530 [(set_attr "length" "4")
4531 (set_attr "fp_mode" "double")])
4534 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4535 (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4536 (use (match_operand:PSI 2 "fpscr_operand" "c"))
4537 (clobber (reg:SI 22))]
4539 [(parallel [(set (reg:SI 22) (fix:SI (match_dup 1)))
4540 (use (match_dup 2))])
4541 (set (match_dup 0) (reg:SI 22))])
4543 (define_insn "cmpgtdf_t"
4544 [(set (reg:SI 18) (gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
4545 (match_operand:DF 1 "arith_reg_operand" "f")))
4546 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4549 [(set_attr "type" "dfp_cmp")
4550 (set_attr "fp_mode" "double")])
4552 (define_insn "cmpeqdf_t"
4553 [(set (reg:SI 18) (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4554 (match_operand:DF 1 "arith_reg_operand" "f")))
4555 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4558 [(set_attr "type" "dfp_cmp")
4559 (set_attr "fp_mode" "double")])
4561 (define_insn "*ieee_ccmpeqdf_t"
4562 [(set (reg:SI 18) (ior:SI (reg:SI 18)
4563 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4564 (match_operand:DF 1 "arith_reg_operand" "f"))))
4565 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4566 "TARGET_IEEE && TARGET_SH4"
4567 "* return output_ieee_ccmpeq (insn, operands);"
4568 [(set_attr "length" "4")
4569 (set_attr "fp_mode" "double")])
4571 (define_expand "cmpdf"
4572 [(set (reg:SI 18) (compare (match_operand:DF 0 "arith_operand" "")
4573 (match_operand:DF 1 "arith_operand" "")))]
4577 sh_compare_op0 = operands[0];
4578 sh_compare_op1 = operands[1];
4582 (define_expand "negdf2"
4583 [(match_operand:DF 0 "arith_reg_operand" "")
4584 (match_operand:DF 1 "arith_reg_operand" "")]
4586 "{ expand_df_unop (&gen_negdf2_i, operands); DONE; }")
4588 (define_insn "negdf2_i"
4589 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4590 (neg:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4591 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4594 [(set_attr "type" "fmove")
4595 (set_attr "fp_mode" "double")])
4597 (define_expand "sqrtdf2"
4598 [(match_operand:DF 0 "arith_reg_operand" "")
4599 (match_operand:DF 1 "arith_reg_operand" "")]
4601 "{ expand_df_unop (&gen_sqrtdf2_i, operands); DONE; }")
4603 (define_insn "sqrtdf2_i"
4604 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4605 (sqrt:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4606 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4609 [(set_attr "type" "dfdiv")
4610 (set_attr "fp_mode" "double")])
4612 (define_expand "absdf2"
4613 [(match_operand:DF 0 "arith_reg_operand" "")
4614 (match_operand:DF 1 "arith_reg_operand" "")]
4616 "{ expand_df_unop (&gen_absdf2_i, operands); DONE; }")
4618 (define_insn "absdf2_i"
4619 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4620 (abs:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4621 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4624 [(set_attr "type" "fmove")
4625 (set_attr "fp_mode" "double")])
4627 (define_expand "extendsfdf2"
4628 [(match_operand:DF 0 "arith_reg_operand" "")
4629 (match_operand:SF 1 "arith_reg_operand" "")]
4633 emit_sf_insn (gen_movsf_ie (gen_rtx (REG, SFmode, 22), operands[1],
4635 emit_df_insn (gen_extendsfdf2_i4 (operands[0], get_fpscr_rtx ()));
4639 (define_insn "extendsfdf2_i4"
4640 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4641 (float_extend:DF (reg:SF 22)))
4642 (use (match_operand:PSI 1 "fpscr_operand" "c"))]
4645 [(set_attr "type" "fp")
4646 (set_attr "fp_mode" "double")])
4648 (define_expand "truncdfsf2"
4649 [(match_operand:SF 0 "arith_reg_operand" "")
4650 (match_operand:DF 1 "arith_reg_operand" "")]
4654 emit_df_insn (gen_truncdfsf2_i4 (operands[1], get_fpscr_rtx ()));
4655 emit_sf_insn (gen_movsf_ie (operands[0], gen_rtx (REG, SFmode, 22),
4660 (define_insn "truncdfsf2_i4"
4662 (float_truncate:SF (match_operand:DF 0 "arith_reg_operand" "f")))
4663 (use (match_operand:PSI 1 "fpscr_operand" "c"))]
4666 [(set_attr "type" "fp")
4667 (set_attr "fp_mode" "double")])
4669 ;; Bit field extract patterns. These give better code for packed bitfields,
4670 ;; because they allow auto-increment addresses to be generated.
4672 (define_expand "insv"
4673 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
4674 (match_operand:SI 1 "immediate_operand" "")
4675 (match_operand:SI 2 "immediate_operand" ""))
4676 (match_operand:SI 3 "general_operand" ""))]
4677 "! TARGET_LITTLE_ENDIAN"
4680 rtx addr_target, orig_address, shift_reg;
4683 /* ??? expmed doesn't care for non-register predicates. */
4684 if (! memory_operand (operands[0], VOIDmode)
4685 || ! immediate_operand (operands[1], VOIDmode)
4686 || ! immediate_operand (operands[2], VOIDmode)
4687 || ! general_operand (operands[3], VOIDmode))
4689 /* If this isn't a 16 / 24 / 32 bit field, or if
4690 it doesn't start on a byte boundary, then fail. */
4691 size = INTVAL (operands[1]);
4692 if (size < 16 || size > 32 || size % 8 != 0
4693 || (INTVAL (operands[2]) % 8) != 0)
4697 orig_address = XEXP (operands[0], 0);
4698 shift_reg = gen_reg_rtx (SImode);
4699 emit_insn (gen_movsi (shift_reg, operands[3]));
4700 addr_target = copy_addr_to_reg (plus_constant (orig_address, size - 1));
4702 operands[0] = change_address (operands[0], QImode, addr_target);
4703 emit_insn (gen_movqi (operands[0], gen_rtx_SUBREG (QImode, shift_reg, 0)));
4707 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
4708 emit_insn (gen_addsi3 (addr_target, addr_target, GEN_INT (-1)));
4709 emit_insn (gen_movqi (operands[0],
4710 gen_rtx_SUBREG (QImode, shift_reg, 0)));
4716 ;; -------------------------------------------------------------------------
4718 ;; -------------------------------------------------------------------------
4720 ;; This matches cases where a stack pointer increment at the start of the
4721 ;; epilogue combines with a stack slot read loading the return value.
4724 [(set (match_operand:SI 0 "arith_reg_operand" "")
4725 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
4726 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
4727 "REGNO (operands[1]) != REGNO (operands[0])"
4730 ;; See the comment on the dt combiner pattern above.
4733 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4734 (plus:SI (match_dup 0)
4737 (eq:SI (match_dup 0)
4742 ;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn'
4743 ;; to `mov #k,r0; mov.l @(r0,r15),rn'. These sequences are generated by
4744 ;; reload when the constant is too large for a reg+offset address.
4746 ;; ??? We would get much better code if this was done in reload. This would
4747 ;; require modifying find_reloads_address to recognize that if the constant
4748 ;; is out-of-range for an immediate add, then we get better code by reloading
4749 ;; the constant into a register than by reloading the sum into a register,
4750 ;; since the former is one instruction shorter if the address does not need
4751 ;; to be offsettable. Unfortunately this does not work, because there is
4752 ;; only one register, r0, that can be used as an index register. This register
4753 ;; is also the function return value register. So, if we try to force reload
4754 ;; to use double-reg addresses, then we end up with some instructions that
4755 ;; need to use r0 twice. The only way to fix this is to change the calling
4756 ;; convention so that r0 is not used to return values.
4759 [(set (match_operand:SI 0 "register_operand" "=r")
4760 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4761 (set (mem:SI (match_dup 0))
4762 (match_operand:SI 2 "general_movsrc_operand" ""))]
4763 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4764 "mov.l %2,@(%0,%1)")
4767 [(set (match_operand:SI 0 "register_operand" "=r")
4768 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4769 (set (match_operand:SI 2 "general_movdst_operand" "")
4770 (mem:SI (match_dup 0)))]
4771 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4772 "mov.l @(%0,%1),%2")
4775 [(set (match_operand:SI 0 "register_operand" "=r")
4776 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4777 (set (mem:HI (match_dup 0))
4778 (match_operand:HI 2 "general_movsrc_operand" ""))]
4779 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4780 "mov.w %2,@(%0,%1)")
4783 [(set (match_operand:SI 0 "register_operand" "=r")
4784 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4785 (set (match_operand:HI 2 "general_movdst_operand" "")
4786 (mem:HI (match_dup 0)))]
4787 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4788 "mov.w @(%0,%1),%2")
4791 [(set (match_operand:SI 0 "register_operand" "=r")
4792 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4793 (set (mem:QI (match_dup 0))
4794 (match_operand:QI 2 "general_movsrc_operand" ""))]
4795 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4796 "mov.b %2,@(%0,%1)")
4799 [(set (match_operand:SI 0 "register_operand" "=r")
4800 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4801 (set (match_operand:QI 2 "general_movdst_operand" "")
4802 (mem:QI (match_dup 0)))]
4803 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4804 "mov.b @(%0,%1),%2")
4807 [(set (match_operand:SI 0 "register_operand" "=r")
4808 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4809 (set (mem:SF (match_dup 0))
4810 (match_operand:SF 2 "general_movsrc_operand" ""))]
4811 "REGNO (operands[0]) == 0
4812 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
4813 || (GET_CODE (operands[2]) == SUBREG
4814 && REGNO (SUBREG_REG (operands[2])) < 16))
4815 && reg_unused_after (operands[0], insn)"
4816 "mov.l %2,@(%0,%1)")
4819 [(set (match_operand:SI 0 "register_operand" "=r")
4820 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4821 (set (match_operand:SF 2 "general_movdst_operand" "")
4823 (mem:SF (match_dup 0)))]
4824 "REGNO (operands[0]) == 0
4825 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
4826 || (GET_CODE (operands[2]) == SUBREG
4827 && REGNO (SUBREG_REG (operands[2])) < 16))
4828 && reg_unused_after (operands[0], insn)"
4829 "mov.l @(%0,%1),%2")
4832 [(set (match_operand:SI 0 "register_operand" "=r")
4833 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4834 (set (mem:SF (match_dup 0))
4835 (match_operand:SF 2 "general_movsrc_operand" ""))]
4836 "REGNO (operands[0]) == 0
4837 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) >= FIRST_FP_REG)
4838 || (GET_CODE (operands[2]) == SUBREG
4839 && REGNO (SUBREG_REG (operands[2])) >= FIRST_FP_REG))
4840 && reg_unused_after (operands[0], insn)"
4841 "fmov{.s|} %2,@(%0,%1)")
4844 [(set (match_operand:SI 0 "register_operand" "=r")
4845 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4846 (set (match_operand:SF 2 "general_movdst_operand" "")
4848 (mem:SF (match_dup 0)))]
4849 "REGNO (operands[0]) == 0
4850 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) >= FIRST_FP_REG)
4851 || (GET_CODE (operands[2]) == SUBREG
4852 && REGNO (SUBREG_REG (operands[2])) >= FIRST_FP_REG))
4853 && reg_unused_after (operands[0], insn)"
4854 "fmov{.s|} @(%0,%1),%2")
4856 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF). */
4857 (define_insn "sp_switch_1"
4864 xoperands[0] = sp_switch;
4865 output_asm_insn (\"mov.l r0,@-r15\;mov.l %0,r0\", xoperands);
4866 output_asm_insn (\"mov.l @r0,r0\;mov.l r15,@-r0\", xoperands);
4867 return \"mov r0,r15\";
4869 [(set_attr "length" "10")])
4871 ;; Switch back to the original stack for interrupt functions with the
4872 ;; sp_switch attribute. */
4873 (define_insn "sp_switch_2"
4876 "mov.l @r15+,r15\;mov.l @r15+,r0"
4877 [(set_attr "length" "4")])