1 ;;- Machine description for Renesas / SuperH SH.
2 ;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 ;; 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
5 ;; Improved by Jim Wilson (wilson@cygnus.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
25 ;; ??? Should prepend a * to all pattern names which are not used.
26 ;; This will make the compiler smaller, and rebuilds after changes faster.
28 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
29 ;; sequences. Especially the sequences for arithmetic right shifts.
31 ;; ??? Should check all DImode patterns for consistency and usefulness.
33 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
34 ;; way to generate them.
36 ;; ??? The cmp/str instruction is not supported. Perhaps it can be used
37 ;; for a str* inline function.
39 ;; BSR is not generated by the compiler proper, but when relaxing, it
40 ;; generates .uses pseudo-ops that allow linker relaxation to create
41 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
43 ;; Special constraints for SH machine description:
50 ;; Special formats used for outputting SH instructions:
52 ;; %. -- print a .s if insn needs delay slot
53 ;; %@ -- print rte/rts if is/isn't an interrupt function
54 ;; %# -- output a nop if there is nothing to put in the delay slot
55 ;; %O -- print a constant without the #
56 ;; %R -- print the lsw reg of a double
57 ;; %S -- print the msw reg of a double
58 ;; %T -- print next word of a double REG or MEM
60 ;; Special predicates:
62 ;; arith_operand -- operand is valid source for arithmetic op
63 ;; arith_reg_operand -- operand is valid register for arithmetic op
64 ;; general_movdst_operand -- operand is valid move destination
65 ;; general_movsrc_operand -- operand is valid move source
66 ;; logical_operand -- operand is valid source for logical op
68 ;; -------------------------------------------------------------------------
70 ;; -------------------------------------------------------------------------
118 ;; These are used with unspec.
119 (UNSPEC_COMPACT_ARGS 0)
132 (UNSPEC_INIT_TRAMP 13)
138 (UNSPEC_EH_RETURN 19)
147 ;; These are used with unspec_volatile.
153 (UNSPECV_WINDOW_END 10)
154 (UNSPECV_CONST_END 11)
157 ;; -------------------------------------------------------------------------
159 ;; -------------------------------------------------------------------------
164 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a,sh5"
165 (const (symbol_ref "sh_cpu_attr")))
167 (define_attr "endian" "big,little"
168 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
169 (const_string "little") (const_string "big"))))
171 ;; Indicate if the default fpu mode is single precision.
172 (define_attr "fpu_single" "yes,no"
173 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
174 (const_string "yes") (const_string "no"))))
176 (define_attr "fmovd" "yes,no"
177 (const (if_then_else (symbol_ref "TARGET_FMOVD")
178 (const_string "yes") (const_string "no"))))
180 (define_attr "pipe_model" "sh1,sh4,sh5media"
182 (cond [(symbol_ref "TARGET_SHMEDIA") (const_string "sh5media")
183 (symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
184 (const_string "sh1"))))
186 ;; cbranch conditional branch instructions
187 ;; jump unconditional jumps
188 ;; arith ordinary arithmetic
189 ;; arith3 a compound insn that behaves similarly to a sequence of
190 ;; three insns of type arith
191 ;; arith3b like above, but might end with a redirected branch
193 ;; load_si Likewise, SImode variant for general register.
194 ;; fload Likewise, but load to fp register.
196 ;; move general purpose register to register
197 ;; mt_group other sh4 mt instructions
198 ;; fmove register to register, floating point
199 ;; smpy word precision integer multiply
200 ;; dmpy longword or doublelongword precision integer multiply
202 ;; pload load of pr reg, which can't be put into delay slot of rts
203 ;; prset copy register to pr reg, ditto
204 ;; pstore store of pr reg, which can't be put into delay slot of jsr
205 ;; prget copy pr to register, ditto
206 ;; pcload pc relative load of constant value
207 ;; pcfload Likewise, but load to fp register.
208 ;; pcload_si Likewise, SImode variant for general register.
209 ;; rte return from exception
210 ;; sfunc special function call with known used registers
211 ;; call function call
213 ;; fdiv floating point divide (or square root)
214 ;; gp_fpul move from general purpose register to fpul
215 ;; fpul_gp move from fpul to general purpose register
216 ;; mac_gp move from mac[lh] to general purpose register
217 ;; dfp_arith, dfp_cmp,dfp_conv
218 ;; ftrc_s fix_truncsfsi2_i4
219 ;; dfdiv double precision floating point divide (or square root)
220 ;; cwb ic_invalidate_line_i
221 ;; movua SH4a unaligned load
222 ;; fsrra square root reciprocal approximate
223 ;; fsca sine and cosine approximate
224 ;; tls_load load TLS related address
225 ;; arith_media SHmedia arithmetic, logical, and shift instructions
226 ;; cbranch_media SHmedia conditional branch instructions
227 ;; cmp_media SHmedia compare instructions
228 ;; dfdiv_media SHmedia double precision divide and square root
229 ;; dfmul_media SHmedia double precision multiply instruction
230 ;; dfparith_media SHmedia double precision floating point arithmetic
231 ;; dfpconv_media SHmedia double precision floating point conversions
232 ;; dmpy_media SHmedia longword multiply
233 ;; fcmp_media SHmedia floating point compare instructions
234 ;; fdiv_media SHmedia single precision divide and square root
235 ;; fload_media SHmedia floating point register load instructions
236 ;; fmove_media SHmedia floating point register moves (inc. fabs and fneg)
237 ;; fparith_media SHmedia single precision floating point arithmetic
238 ;; fpconv_media SHmedia single precision floating point conversions
239 ;; fstore_media SHmedia floating point register store instructions
240 ;; gettr_media SHmedia gettr instruction
241 ;; invalidate_line_media SHmedia invalidate_line sequence
242 ;; jump_media SHmedia unconditional branch instructions
243 ;; load_media SHmedia general register load instructions
244 ;; pt_media SHmedia pt instruction (expanded by assembler)
245 ;; ptabs_media SHmedia ptabs instruction
246 ;; store_media SHmedia general register store instructions
247 ;; mcmp_media SHmedia multimedia compare, absolute, saturating ops
248 ;; mac_media SHmedia mac-style fixed point operations
249 ;; d2mpy_media SHmedia: two 32 bit integer multiplies
250 ;; atrans SHmedia approximate transcendental functions
251 ;; ustore_media SHmedia unaligned stores
252 ;; nil no-op move, will be deleted.
255 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,fload,store,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fdiv,ftrc_s,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media,nil,other"
256 (const_string "other"))
258 ;; We define a new attribute namely "insn_class".We use
259 ;; this for the DFA based pipeline description.
261 ;; mt_group SH4 "mt" group instructions.
263 ;; ex_group SH4 "ex" group instructions.
265 ;; ls_group SH4 "ls" group instructions.
268 (define_attr "insn_class"
269 "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
270 (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
271 (eq_attr "type" "arith,dyn_shift") (const_string "ex_group")
272 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,store,gp_fpul,fpul_gp") (const_string "ls_group")
273 (eq_attr "type" "cbranch,jump") (const_string "br_group")
274 (eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_conv,dfdiv")
275 (const_string "fe_group")
276 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb") (const_string "co_group")]
277 (const_string "none")))
278 ;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
279 ;; so these do not belong in an insn group, although they are modeled
280 ;; with their own define_insn_reservations.
282 ;; Indicate what precision must be selected in fpscr for this insn, if any.
284 (define_attr "fp_mode" "single,double,none" (const_string "none"))
286 ;; Indicate if the fpu mode is set by this instruction
287 ;; "unknown" must have the value as "none" in fp_mode, and means
288 ;; that the instruction/abi has left the processor in an unknown
290 ;; "none" means that nothing has changed and no mode is set.
291 ;; This attribute is only used for the Renesas ABI.
292 (define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
294 ; If a conditional branch destination is within -252..258 bytes away
295 ; from the instruction it can be 2 bytes long. Something in the
296 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
297 ; branches are initially assumed to be 16 bytes long.
298 ; In machine_dependent_reorg, we split all branches that are longer than
301 ;; The maximum range used for SImode constant pool entries is 1018. A final
302 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
303 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
304 ;; instruction around the pool table, 2 bytes of alignment before the table,
305 ;; and 30 bytes of alignment after the table. That gives a maximum total
306 ;; pool size of 1058 bytes.
307 ;; Worst case code/pool content size ratio is 1:2 (using asms).
308 ;; Thus, in the worst case, there is one instruction in front of a maximum
309 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
310 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
311 ;; If we have a forward branch, the initial table will be put after the
312 ;; unconditional branch.
314 ;; ??? We could do much better by keeping track of the actual pcloads within
315 ;; the branch range and in the pcload range in front of the branch range.
317 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
319 (define_attr "short_cbranch_p" "no,yes"
320 (cond [(ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
322 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
324 (ne (symbol_ref "NEXT_INSN (PREV_INSN (insn)) != insn") (const_int 0))
326 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
328 ] (const_string "no")))
330 (define_attr "med_branch_p" "no,yes"
331 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
334 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
336 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
339 ] (const_string "no")))
341 (define_attr "med_cbranch_p" "no,yes"
342 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
345 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
347 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
350 ] (const_string "no")))
352 (define_attr "braf_branch_p" "no,yes"
353 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
355 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
358 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
360 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
363 ] (const_string "no")))
365 (define_attr "braf_cbranch_p" "no,yes"
366 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
368 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
371 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
373 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
376 ] (const_string "no")))
378 ; An unconditional jump in the range -4092..4098 can be 2 bytes long.
379 ; For wider ranges, we need a combination of a code and a data part.
380 ; If we can get a scratch register for a long range jump, the code
381 ; part can be 4 bytes long; otherwise, it must be 8 bytes long.
382 ; If the jump is in the range -32764..32770, the data part can be 2 bytes
383 ; long; otherwise, it must be 6 bytes long.
385 ; All other instructions are two bytes long by default.
387 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
388 ;; but getattrtab doesn't understand this.
389 (define_attr "length" ""
390 (cond [(eq_attr "type" "cbranch")
391 (cond [(eq_attr "short_cbranch_p" "yes")
393 (eq_attr "med_cbranch_p" "yes")
395 (eq_attr "braf_cbranch_p" "yes")
397 ;; ??? using pc is not computed transitively.
398 (ne (match_dup 0) (match_dup 0))
400 (ne (symbol_ref ("flag_pic")) (const_int 0))
403 (eq_attr "type" "jump")
404 (cond [(eq_attr "med_branch_p" "yes")
406 (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
408 (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
409 (symbol_ref "code_for_indirect_jump_scratch")))
410 (cond [(eq_attr "braf_branch_p" "yes")
412 (eq (symbol_ref "flag_pic") (const_int 0))
414 (ne (symbol_ref "TARGET_SH2") (const_int 0))
415 (const_int 10)] (const_int 18))
416 (eq_attr "braf_branch_p" "yes")
418 ;; ??? using pc is not computed transitively.
419 (ne (match_dup 0) (match_dup 0))
421 (ne (symbol_ref ("flag_pic")) (const_int 0))
424 (eq_attr "type" "pt_media")
425 (if_then_else (ne (symbol_ref "TARGET_SHMEDIA64") (const_int 0))
426 (const_int 20) (const_int 12))
427 ] (if_then_else (ne (symbol_ref "TARGET_SHMEDIA") (const_int 0))
431 ;; DFA descriptions for the pipelines
434 (include "shmedia.md")
437 ;; Definitions for filling delay slots
439 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
441 ;; ??? This should be (nil) instead of (const_int 0)
442 (define_attr "hit_stack" "yes,no"
443 (cond [(eq (symbol_ref "find_regno_note (insn, REG_INC, SP_REG)")
446 (const_string "yes")))
448 (define_attr "interrupt_function" "no,yes"
449 (const (symbol_ref "current_function_interrupt")))
451 (define_attr "in_delay_slot" "yes,no"
452 (cond [(eq_attr "type" "cbranch") (const_string "no")
453 (eq_attr "type" "pcload,pcload_si") (const_string "no")
454 (eq_attr "needs_delay_slot" "yes") (const_string "no")
455 (eq_attr "length" "2") (const_string "yes")
456 ] (const_string "no")))
458 (define_attr "cond_delay_slot" "yes,no"
459 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
460 ] (const_string "no")))
462 (define_attr "is_sfunc" ""
463 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
465 (define_attr "is_mac_media" ""
466 (if_then_else (eq_attr "type" "mac_media") (const_int 1) (const_int 0)))
468 (define_attr "branch_zero" "yes,no"
469 (cond [(eq_attr "type" "!cbranch") (const_string "no")
470 (ne (symbol_ref "(next_active_insn (insn)\
471 == (prev_active_insn\
472 (XEXP (SET_SRC (PATTERN (insn)), 1))))\
473 && get_attr_length (next_active_insn (insn)) == 2")
475 (const_string "yes")]
476 (const_string "no")))
478 ;; SH4 Double-precision computation with double-precision result -
479 ;; the two halves are ready at different times.
480 (define_attr "dfp_comp" "yes,no"
481 (cond [(eq_attr "type" "dfp_arith,dfp_conv,dfdiv") (const_string "yes")]
482 (const_string "no")))
484 ;; Insns for which the latency of a preceding fp insn is decreased by one.
485 (define_attr "late_fp_use" "yes,no" (const_string "no"))
486 ;; And feeding insns for which this relevant.
487 (define_attr "any_fp_comp" "yes,no"
488 (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_conv,dfdiv")
489 (const_string "yes")]
490 (const_string "no")))
492 (define_attr "any_int_load" "yes,no"
493 (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
494 (const_string "yes")]
495 (const_string "no")))
498 (eq_attr "needs_delay_slot" "yes")
499 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
501 ;; On the SH and SH2, the rte instruction reads the return pc from the stack,
502 ;; and thus we can't put a pop instruction in its delay slot.
503 ;; ??? On the SH3, the rte instruction does not use the stack, so a pop
504 ;; instruction can go in the delay slot.
506 ;; Since a normal return (rts) implicitly uses the PR register,
507 ;; we can't allow PR register loads in an rts delay slot.
510 (eq_attr "type" "return")
511 [(and (eq_attr "in_delay_slot" "yes")
512 (ior (and (eq_attr "interrupt_function" "no")
513 (eq_attr "type" "!pload,prset"))
514 (and (eq_attr "interrupt_function" "yes")
516 (ne (symbol_ref "TARGET_SH3") (const_int 0))
517 (eq_attr "hit_stack" "no"))))) (nil) (nil)])
519 ;; Since a call implicitly uses the PR register, we can't allow
520 ;; a PR register store in a jsr delay slot.
523 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
524 [(and (eq_attr "in_delay_slot" "yes")
525 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
527 ;; Say that we have annulled true branches, since this gives smaller and
528 ;; faster code when branches are predicted as not taken.
530 ;; ??? The non-annulled condition should really be "in_delay_slot",
531 ;; but insns that can be filled in non-annulled get priority over insns
532 ;; that can only be filled in anulled.
535 (and (eq_attr "type" "cbranch")
536 (ne (symbol_ref "TARGET_SH2") (const_int 0)))
537 ;; SH2e has a hardware bug that pretty much prohibits the use of
538 ;; annuled delay slots.
539 [(eq_attr "cond_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
540 (not (eq_attr "cpu" "sh2e"))) (nil)])
542 ;; -------------------------------------------------------------------------
543 ;; SImode signed integer comparisons
544 ;; -------------------------------------------------------------------------
548 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
549 (match_operand:SI 1 "arith_operand" "K08,r"))
553 [(set_attr "type" "mt_group")])
555 ;; ??? Perhaps should only accept reg/constant if the register is reg 0.
556 ;; That would still allow reload to create cmpi instructions, but would
557 ;; perhaps allow forcing the constant into a register when that is better.
558 ;; Probably should use r0 for mem/imm compares, but force constant into a
559 ;; register for pseudo/imm compares.
561 (define_insn "cmpeqsi_t"
563 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
564 (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
570 [(set_attr "type" "mt_group")])
572 (define_insn "cmpgtsi_t"
574 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
575 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
580 [(set_attr "type" "mt_group")])
582 (define_insn "cmpgesi_t"
584 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
585 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
590 [(set_attr "type" "mt_group")])
592 ;; -------------------------------------------------------------------------
593 ;; SImode unsigned integer comparisons
594 ;; -------------------------------------------------------------------------
596 (define_insn "cmpgeusi_t"
598 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
599 (match_operand:SI 1 "arith_reg_operand" "r")))]
602 [(set_attr "type" "mt_group")])
604 (define_insn "cmpgtusi_t"
606 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
607 (match_operand:SI 1 "arith_reg_operand" "r")))]
610 [(set_attr "type" "mt_group")])
612 ;; We save the compare operands in the cmpxx patterns and use them when
613 ;; we generate the branch.
615 (define_expand "cmpsi"
617 (compare (match_operand:SI 0 "cmpsi_operand" "")
618 (match_operand:SI 1 "arith_operand" "")))]
622 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == T_REG
623 && GET_CODE (operands[1]) != CONST_INT)
624 operands[0] = copy_to_mode_reg (SImode, operands[0]);
625 sh_compare_op0 = operands[0];
626 sh_compare_op1 = operands[1];
630 ;; -------------------------------------------------------------------------
631 ;; DImode signed integer comparisons
632 ;; -------------------------------------------------------------------------
634 ;; ??? Could get better scheduling by splitting the initial test from the
635 ;; rest of the insn after reload. However, the gain would hardly justify
636 ;; the sh.md size increase necessary to do that.
640 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
641 (match_operand:DI 1 "arith_operand" "r"))
644 "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
646 [(set_attr "length" "6")
647 (set_attr "type" "arith3b")])
649 (define_insn "cmpeqdi_t"
651 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
652 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
655 tst %S0,%S0\;bf %,Ldi%=\;tst %R0,%R0\\n%,Ldi%=:
656 cmp/eq %S1,%S0\;bf %,Ldi%=\;cmp/eq %R1,%R0\\n%,Ldi%=:"
657 [(set_attr "length" "6")
658 (set_attr "type" "arith3b")])
662 (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
663 (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
664 ;; If we applied this split when not optimizing, it would only be
665 ;; applied during the machine-dependent reorg, when no new basic blocks
667 "TARGET_SH1 && reload_completed && optimize"
668 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
669 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
670 (label_ref (match_dup 6))
672 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
677 = gen_rtx_REG (SImode,
678 true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
680 = (operands[1] == const0_rtx
682 : gen_rtx_REG (SImode,
683 true_regnum (operands[1])
684 + (TARGET_LITTLE_ENDIAN ? 1 : 0)));
685 operands[4] = gen_lowpart (SImode, operands[0]);
686 operands[5] = gen_lowpart (SImode, operands[1]);
687 operands[6] = gen_label_rtx ();
690 (define_insn "cmpgtdi_t"
692 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
693 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
696 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
697 tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
698 [(set_attr "length" "8")
699 (set_attr "type" "arith3")])
701 (define_insn "cmpgedi_t"
703 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
704 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
707 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
709 [(set_attr "length" "8,2")
710 (set_attr "type" "arith3,mt_group")])
712 ;; -------------------------------------------------------------------------
713 ;; DImode unsigned integer comparisons
714 ;; -------------------------------------------------------------------------
716 (define_insn "cmpgeudi_t"
718 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
719 (match_operand:DI 1 "arith_reg_operand" "r")))]
721 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
722 [(set_attr "length" "8")
723 (set_attr "type" "arith3")])
725 (define_insn "cmpgtudi_t"
727 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
728 (match_operand:DI 1 "arith_reg_operand" "r")))]
730 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
731 [(set_attr "length" "8")
732 (set_attr "type" "arith3")])
734 (define_insn "cmpeqdi_media"
735 [(set (match_operand:DI 0 "register_operand" "=r")
736 (eq:DI (match_operand:DI 1 "register_operand" "%r")
737 (match_operand:DI 2 "arith_reg_or_0_operand" "Nr")))]
740 [(set_attr "type" "cmp_media")])
742 (define_insn "cmpgtdi_media"
743 [(set (match_operand:DI 0 "register_operand" "=r")
744 (gt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
745 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
748 [(set_attr "type" "cmp_media")])
750 (define_insn "cmpgtudi_media"
751 [(set (match_operand:DI 0 "register_operand" "=r")
752 (gtu:DI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
753 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
755 "cmpgtu %N1, %N2, %0"
756 [(set_attr "type" "cmp_media")])
758 ;; We save the compare operands in the cmpxx patterns and use them when
759 ;; we generate the branch.
761 (define_expand "cmpdi"
763 (compare (match_operand:DI 0 "arith_operand" "")
764 (match_operand:DI 1 "arith_operand" "")))]
765 "TARGET_SH2 || TARGET_SHMEDIA"
768 sh_compare_op0 = operands[0];
769 sh_compare_op1 = operands[1];
772 ;; -------------------------------------------------------------------------
773 ;; Conditional move instructions
774 ;; -------------------------------------------------------------------------
776 ;; The insn names may seem reversed, but note that cmveq performs the move
777 ;; if op1 == 0, and cmvne does it if op1 != 0.
779 (define_insn "movdicc_false"
780 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
781 (if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r")
783 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
784 (match_operand:DI 3 "arith_reg_operand" "0")))]
787 [(set_attr "type" "arith_media")])
789 (define_insn "movdicc_true"
790 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
791 (if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r")
793 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
794 (match_operand:DI 3 "arith_reg_operand" "0")))]
797 [(set_attr "type" "arith_media")])
799 (define_expand "movdicc"
800 [(set (match_operand:DI 0 "register_operand" "")
801 (if_then_else:DI (match_operand 1 "comparison_operator" "")
802 (match_operand:DI 2 "register_operand" "")
803 (match_operand:DI 3 "register_operand" "")))]
807 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
808 && GET_MODE (sh_compare_op0) == DImode
809 && sh_compare_op1 == const0_rtx)
810 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
811 sh_compare_op0, sh_compare_op1);
819 tmp = gen_reg_rtx (DImode);
821 switch (GET_CODE (operands[1]))
824 emit_insn (gen_seq (tmp));
825 operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
829 emit_insn (gen_seq (tmp));
830 operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
834 emit_insn (gen_sgt (tmp));
835 operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
839 emit_insn (gen_slt (tmp));
840 operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
844 emit_insn (gen_slt (tmp));
845 operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
849 emit_insn (gen_sgt (tmp));
850 operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
854 emit_insn (gen_sgtu (tmp));
855 operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
859 emit_insn (gen_sltu (tmp));
860 operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
864 emit_insn (gen_sltu (tmp));
865 operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
869 emit_insn (gen_sgtu (tmp));
870 operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
874 emit_insn (gen_sunordered (tmp));
875 operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
879 emit_insn (gen_sunordered (tmp));
880 operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
897 ;; -------------------------------------------------------------------------
898 ;; Addition instructions
899 ;; -------------------------------------------------------------------------
901 (define_expand "adddi3"
902 [(set (match_operand:DI 0 "arith_reg_operand" "")
903 (plus:DI (match_operand:DI 1 "arith_reg_operand" "")
904 (match_operand:DI 2 "arith_operand" "")))]
910 if (no_new_pseudos && ! arith_reg_operand (operands[2], DImode))
912 operands[2] = force_reg (DImode, operands[2]);
913 emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
918 (define_insn "*adddi3_media"
919 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
920 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
921 (match_operand:DI 2 "arith_operand" "r,I10")))]
926 [(set_attr "type" "arith_media")])
928 (define_insn "adddi3z_media"
929 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
931 (plus:SI (match_operand:SI 1 "extend_reg_operand" "r")
932 (match_operand:SI 2 "extend_reg_or_0_operand" "rN"))))]
935 [(set_attr "type" "arith_media")])
937 (define_insn "adddi3_compact"
938 [(set (match_operand:DI 0 "arith_reg_operand" "=&r")
939 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
940 (match_operand:DI 2 "arith_reg_operand" "r")))
941 (clobber (reg:SI T_REG))]
944 [(set_attr "length" "6")])
947 [(set (match_operand:DI 0 "arith_reg_operand" "")
948 (plus:DI (match_operand:DI 1 "arith_reg_operand" "")
949 (match_operand:DI 2 "arith_reg_operand" "")))
950 (clobber (reg:SI T_REG))]
951 "TARGET_SH1 && reload_completed"
955 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
956 high0 = gen_rtx_REG (SImode,
957 true_regnum (operands[0])
958 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
959 high2 = gen_rtx_REG (SImode,
960 true_regnum (operands[2])
961 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
962 emit_insn (gen_clrt ());
963 emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
964 emit_insn (gen_addc1 (high0, high0, high2));
969 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
970 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
971 (match_operand:SI 2 "arith_reg_operand" "r"))
974 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
977 [(set_attr "type" "arith")])
980 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
981 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
982 (match_operand:SI 2 "arith_reg_operand" "r"))
984 (clobber (reg:SI T_REG))]
987 [(set_attr "type" "arith")])
989 (define_expand "addsi3"
990 [(set (match_operand:SI 0 "arith_reg_operand" "")
991 (plus:SI (match_operand:SI 1 "arith_operand" "")
992 (match_operand:SI 2 "arith_operand" "")))]
997 operands[1] = force_reg (SImode, operands[1]);
1000 (define_insn "addsi3_media"
1001 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
1002 (plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
1003 (match_operand:SI 2 "arith_operand" "r,I10")))]
1008 [(set_attr "type" "arith_media")])
1010 (define_insn "*addsi3_compact"
1011 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1012 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
1013 (match_operand:SI 2 "arith_operand" "rI08")))]
1016 [(set_attr "type" "arith")])
1018 ;; -------------------------------------------------------------------------
1019 ;; Subtraction instructions
1020 ;; -------------------------------------------------------------------------
1022 (define_expand "subdi3"
1023 [(set (match_operand:DI 0 "arith_reg_operand" "")
1024 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "")
1025 (match_operand:DI 2 "arith_reg_operand" "")))]
1031 operands[1] = force_reg (DImode, operands[1]);
1032 emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
1037 (define_insn "*subdi3_media"
1038 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1039 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
1040 (match_operand:DI 2 "arith_reg_operand" "r")))]
1043 [(set_attr "type" "arith_media")])
1045 (define_insn "subdi3_compact"
1046 [(set (match_operand:DI 0 "arith_reg_operand" "=&r")
1047 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
1048 (match_operand:DI 2 "arith_reg_operand" "r")))
1049 (clobber (reg:SI T_REG))]
1052 [(set_attr "length" "6")])
1055 [(set (match_operand:DI 0 "arith_reg_operand" "")
1056 (minus:DI (match_operand:DI 1 "arith_reg_operand" "")
1057 (match_operand:DI 2 "arith_reg_operand" "")))
1058 (clobber (reg:SI T_REG))]
1059 "TARGET_SH1 && reload_completed"
1063 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
1064 high0 = gen_rtx_REG (SImode,
1065 true_regnum (operands[0])
1066 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
1067 high2 = gen_rtx_REG (SImode,
1068 true_regnum (operands[2])
1069 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
1070 emit_insn (gen_clrt ());
1071 emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
1072 emit_insn (gen_subc1 (high0, high0, high2));
1077 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1078 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1079 (match_operand:SI 2 "arith_reg_operand" "r"))
1082 (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
1087 [(set_attr "type" "arith")])
1089 (define_insn "subc1"
1090 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1091 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1092 (match_operand:SI 2 "arith_reg_operand" "r"))
1094 (clobber (reg:SI T_REG))]
1097 [(set_attr "type" "arith")])
1099 (define_insn "*subsi3_internal"
1100 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1101 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1102 (match_operand:SI 2 "arith_reg_operand" "r")))]
1105 [(set_attr "type" "arith")])
1107 (define_insn "*subsi3_media"
1108 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1109 (minus:SI (match_operand:SI 1 "extend_reg_or_0_operand" "rN")
1110 (match_operand:SI 2 "extend_reg_operand" "r")))]
1113 [(set_attr "type" "arith_media")])
1115 ;; Convert `constant - reg' to `neg rX; add rX, #const' since this
1116 ;; will sometimes save one instruction. Otherwise we might get
1117 ;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
1120 (define_expand "subsi3"
1121 [(set (match_operand:SI 0 "arith_reg_operand" "")
1122 (minus:SI (match_operand:SI 1 "arith_operand" "")
1123 (match_operand:SI 2 "arith_reg_operand" "")))]
1127 if (TARGET_SH1 && GET_CODE (operands[1]) == CONST_INT)
1129 emit_insn (gen_negsi2 (operands[0], operands[2]));
1130 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
1135 if (no_new_pseudos && ! arith_reg_or_0_operand (operands[1], SImode))
1137 if (operands[1] != const0_rtx)
1138 operands[1] = force_reg (SImode, operands[1]);
1142 ;; -------------------------------------------------------------------------
1143 ;; Division instructions
1144 ;; -------------------------------------------------------------------------
1146 ;; We take advantage of the library routines which don't clobber as many
1147 ;; registers as a normal function call would.
1149 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
1150 ;; also has an effect on the register that holds the address of the sfunc.
1151 ;; To make this work, we have an extra dummy insn that shows the use
1152 ;; of this register for reorg.
1154 (define_insn "use_sfunc_addr"
1155 [(set (reg:SI PR_REG)
1156 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
1157 "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
1159 [(set_attr "length" "0")])
1161 (define_insn "udivsi3_sh2a"
1162 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1163 (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
1164 (match_operand:SI 2 "arith_reg_operand" "z")))]
1167 [(set_attr "type" "arith")
1168 (set_attr "in_delay_slot" "no")])
1170 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
1171 ;; hard register 0. If we used hard register 0, then the next instruction
1172 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
1173 ;; gets allocated to a stack slot that needs its address reloaded, then
1174 ;; there is nothing to prevent reload from using r0 to reload the address.
1175 ;; This reload would clobber the value in r0 we are trying to store.
1176 ;; If we let reload allocate r0, then this problem can never happen.
1178 (define_insn "udivsi3_i1"
1179 [(set (match_operand:SI 0 "register_operand" "=z")
1180 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1181 (clobber (reg:SI T_REG))
1182 (clobber (reg:SI PR_REG))
1183 (clobber (reg:SI R4_REG))
1184 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1185 "TARGET_SH1 && ! TARGET_SH4"
1187 [(set_attr "type" "sfunc")
1188 (set_attr "needs_delay_slot" "yes")])
1190 ; Since shmedia-nofpu code could be linked against shcompact code, and
1191 ; the udivsi3 libcall has the same name, we must consider all registers
1192 ; clobbered that are in the union of the registers clobbered by the
1193 ; shmedia and the shcompact implementation. Note, if the shcompact
1194 ; implementation actually used shcompact code, we'd need to clobber
1195 ; also r23 and fr23.
1196 (define_insn "udivsi3_i1_media"
1197 [(set (match_operand:SI 0 "register_operand" "=z")
1198 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1199 (clobber (reg:SI T_MEDIA_REG))
1200 (clobber (reg:SI PR_MEDIA_REG))
1201 (clobber (reg:SI R20_REG))
1202 (clobber (reg:SI R21_REG))
1203 (clobber (reg:SI R22_REG))
1204 (clobber (reg:DI TR0_REG))
1205 (clobber (reg:DI TR1_REG))
1206 (clobber (reg:DI TR2_REG))
1207 (use (match_operand:DI 1 "target_operand" "b"))]
1208 "TARGET_SHMEDIA && ! TARGET_SHMEDIA_FPU"
1210 [(set_attr "type" "sfunc")
1211 (set_attr "needs_delay_slot" "yes")])
1213 (define_expand "udivsi3_i4_media"
1215 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
1217 (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
1218 (set (match_dup 5) (float:DF (match_dup 3)))
1219 (set (match_dup 6) (float:DF (match_dup 4)))
1220 (set (match_dup 7) (div:DF (match_dup 5) (match_dup 6)))
1221 (set (match_dup 8) (fix:DI (match_dup 7)))
1222 (set (match_operand:SI 0 "register_operand" "")
1223 (truncate:SI (match_dup 8)))]
1224 "TARGET_SHMEDIA_FPU"
1227 operands[3] = gen_reg_rtx (DImode);
1228 operands[4] = gen_reg_rtx (DImode);
1229 operands[5] = gen_reg_rtx (DFmode);
1230 operands[6] = gen_reg_rtx (DFmode);
1231 operands[7] = gen_reg_rtx (DFmode);
1232 operands[8] = gen_reg_rtx (DImode);
1235 (define_insn "udivsi3_i4"
1236 [(set (match_operand:SI 0 "register_operand" "=y")
1237 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1238 (clobber (reg:SI T_REG))
1239 (clobber (reg:SI PR_REG))
1240 (clobber (reg:DF DR0_REG))
1241 (clobber (reg:DF DR2_REG))
1242 (clobber (reg:DF DR4_REG))
1243 (clobber (reg:SI R0_REG))
1244 (clobber (reg:SI R1_REG))
1245 (clobber (reg:SI R4_REG))
1246 (clobber (reg:SI R5_REG))
1247 (use (reg:PSI FPSCR_REG))
1248 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1249 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1251 [(set_attr "type" "sfunc")
1252 (set_attr "fp_mode" "double")
1253 (set_attr "needs_delay_slot" "yes")])
1255 (define_insn "udivsi3_i4_single"
1256 [(set (match_operand:SI 0 "register_operand" "=y")
1257 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1258 (clobber (reg:SI T_REG))
1259 (clobber (reg:SI PR_REG))
1260 (clobber (reg:DF DR0_REG))
1261 (clobber (reg:DF DR2_REG))
1262 (clobber (reg:DF DR4_REG))
1263 (clobber (reg:SI R0_REG))
1264 (clobber (reg:SI R1_REG))
1265 (clobber (reg:SI R4_REG))
1266 (clobber (reg:SI R5_REG))
1267 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1268 "(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && TARGET_FPU_SINGLE"
1270 [(set_attr "type" "sfunc")
1271 (set_attr "needs_delay_slot" "yes")])
1273 (define_expand "udivsi3"
1274 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
1275 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1276 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1277 (parallel [(set (match_operand:SI 0 "register_operand" "")
1278 (udiv:SI (reg:SI R4_REG)
1280 (clobber (reg:SI T_REG))
1281 (clobber (reg:SI PR_REG))
1282 (clobber (reg:SI R4_REG))
1283 (use (match_dup 3))])]
1289 operands[3] = gen_reg_rtx (Pmode);
1290 /* Emit the move of the address to a pseudo outside of the libcall. */
1291 if (TARGET_HARD_SH4 && TARGET_SH2E)
1293 emit_move_insn (operands[3], function_symbol (\"__udivsi3_i4\"));
1294 if (TARGET_FPU_SINGLE)
1295 last = gen_udivsi3_i4_single (operands[0], operands[3]);
1297 last = gen_udivsi3_i4 (operands[0], operands[3]);
1299 else if (TARGET_SHMEDIA_FPU)
1301 operands[1] = force_reg (SImode, operands[1]);
1302 operands[2] = force_reg (SImode, operands[2]);
1303 emit_insn (gen_udivsi3_i4_media (operands[0], operands[1], operands[2]));
1306 else if (TARGET_SH2A)
1308 operands[1] = force_reg (SImode, operands[1]);
1309 operands[2] = force_reg (SImode, operands[2]);
1310 emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
1313 else if (TARGET_SH5)
1315 emit_move_insn (operands[3],
1316 function_symbol (TARGET_FPU_ANY
1321 last = gen_udivsi3_i1_media (operands[0],
1324 : gen_rtx_SUBREG (DImode, operands[3],
1326 else if (TARGET_FPU_ANY)
1327 last = gen_udivsi3_i4_single (operands[0], operands[3]);
1329 last = gen_udivsi3_i1 (operands[0], operands[3]);
1333 emit_move_insn (operands[3], function_symbol (\"__udivsi3\"));
1334 last = gen_udivsi3_i1 (operands[0], operands[3]);
1336 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1337 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1338 last = emit_insn (last);
1339 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1340 invariant code motion can move it. */
1341 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1342 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1346 (define_insn "divsi3_sh2a"
1347 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1348 (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
1349 (match_operand:SI 2 "arith_reg_operand" "z")))]
1352 [(set_attr "type" "arith")
1353 (set_attr "in_delay_slot" "no")])
1355 (define_insn "divsi3_i1"
1356 [(set (match_operand:SI 0 "register_operand" "=z")
1357 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1358 (clobber (reg:SI T_REG))
1359 (clobber (reg:SI PR_REG))
1360 (clobber (reg:SI R1_REG))
1361 (clobber (reg:SI R2_REG))
1362 (clobber (reg:SI R3_REG))
1363 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1364 "TARGET_SH1 && ! TARGET_SH4"
1366 [(set_attr "type" "sfunc")
1367 (set_attr "needs_delay_slot" "yes")])
1369 ; Since shmedia-nofpu code could be linked against shcompact code, and
1370 ; the sdivsi3 libcall has the same name, we must consider all registers
1371 ; clobbered that are in the union of the registers clobbered by the
1372 ; shmedia and the shcompact implementation. Note, if the shcompact
1373 ; implementation actually used shcompact code, we'd need to clobber
1374 ; also r22, r23 and fr23.
1375 (define_insn "divsi3_i1_media"
1376 [(set (match_operand:SI 0 "register_operand" "=z")
1377 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1378 (clobber (reg:SI T_MEDIA_REG))
1379 (clobber (reg:SI PR_MEDIA_REG))
1380 (clobber (reg:SI R1_REG))
1381 (clobber (reg:SI R2_REG))
1382 (clobber (reg:SI R3_REG))
1383 (clobber (reg:SI R20_REG))
1384 (clobber (reg:SI R21_REG))
1385 (clobber (reg:DI TR0_REG))
1386 (clobber (reg:DI TR1_REG))
1387 (clobber (reg:DI TR2_REG))
1388 (use (match_operand:DI 1 "target_operand" "b"))]
1389 "TARGET_SHMEDIA && ! TARGET_SHMEDIA_FPU"
1391 [(set_attr "type" "sfunc")])
1393 (define_expand "divsi3_i4_media"
1394 [(set (match_dup 3) (float:DF (match_operand:SI 1 "register_operand" "r")))
1395 (set (match_dup 4) (float:DF (match_operand:SI 2 "register_operand" "r")))
1396 (set (match_dup 5) (div:DF (match_dup 3) (match_dup 4)))
1397 (set (match_operand:SI 0 "register_operand" "=r")
1398 (fix:SI (match_dup 5)))]
1399 "TARGET_SHMEDIA_FPU"
1402 operands[3] = gen_reg_rtx (DFmode);
1403 operands[4] = gen_reg_rtx (DFmode);
1404 operands[5] = gen_reg_rtx (DFmode);
1407 (define_insn "divsi3_i4"
1408 [(set (match_operand:SI 0 "register_operand" "=y")
1409 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1410 (clobber (reg:SI PR_REG))
1411 (clobber (reg:DF DR0_REG))
1412 (clobber (reg:DF DR2_REG))
1413 (use (reg:PSI FPSCR_REG))
1414 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1415 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1417 [(set_attr "type" "sfunc")
1418 (set_attr "fp_mode" "double")
1419 (set_attr "needs_delay_slot" "yes")])
1421 (define_insn "divsi3_i4_single"
1422 [(set (match_operand:SI 0 "register_operand" "=y")
1423 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1424 (clobber (reg:SI PR_REG))
1425 (clobber (reg:DF DR0_REG))
1426 (clobber (reg:DF DR2_REG))
1427 (clobber (reg:SI R2_REG))
1428 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1429 "(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && TARGET_FPU_SINGLE"
1431 [(set_attr "type" "sfunc")
1432 (set_attr "needs_delay_slot" "yes")])
1434 (define_expand "divsi3"
1435 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
1436 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1437 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1438 (parallel [(set (match_operand:SI 0 "register_operand" "")
1439 (div:SI (reg:SI R4_REG)
1441 (clobber (reg:SI T_REG))
1442 (clobber (reg:SI PR_REG))
1443 (clobber (reg:SI R1_REG))
1444 (clobber (reg:SI R2_REG))
1445 (clobber (reg:SI R3_REG))
1446 (use (match_dup 3))])]
1452 operands[3] = gen_reg_rtx (Pmode);
1453 /* Emit the move of the address to a pseudo outside of the libcall. */
1454 if (TARGET_HARD_SH4 && TARGET_SH2E)
1456 emit_move_insn (operands[3], function_symbol (\"__sdivsi3_i4\"));
1457 if (TARGET_FPU_SINGLE)
1458 last = gen_divsi3_i4_single (operands[0], operands[3]);
1460 last = gen_divsi3_i4 (operands[0], operands[3]);
1462 else if (TARGET_SH2A)
1464 operands[1] = force_reg (SImode, operands[1]);
1465 operands[2] = force_reg (SImode, operands[2]);
1466 emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
1469 else if (TARGET_SHMEDIA_FPU)
1471 operands[1] = force_reg (SImode, operands[1]);
1472 operands[2] = force_reg (SImode, operands[2]);
1473 emit_insn (gen_divsi3_i4_media (operands[0], operands[1], operands[2]));
1476 else if (TARGET_SH5)
1478 emit_move_insn (operands[3],
1479 function_symbol (TARGET_FPU_ANY
1484 last = gen_divsi3_i1_media (operands[0],
1487 : gen_rtx_SUBREG (DImode, operands[3],
1489 else if (TARGET_FPU_ANY)
1490 last = gen_divsi3_i4_single (operands[0], operands[3]);
1492 last = gen_divsi3_i1 (operands[0], operands[3]);
1496 emit_move_insn (operands[3], function_symbol (\"__sdivsi3\"));
1497 last = gen_divsi3_i1 (operands[0], operands[3]);
1499 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1500 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1501 last = emit_insn (last);
1502 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1503 invariant code motion can move it. */
1504 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1505 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1509 ;; -------------------------------------------------------------------------
1510 ;; Multiplication instructions
1511 ;; -------------------------------------------------------------------------
1513 (define_insn "umulhisi3_i"
1514 [(set (reg:SI MACL_REG)
1515 (mult:SI (zero_extend:SI
1516 (match_operand:HI 0 "arith_reg_operand" "r"))
1518 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1521 [(set_attr "type" "smpy")])
1523 (define_insn "mulhisi3_i"
1524 [(set (reg:SI MACL_REG)
1525 (mult:SI (sign_extend:SI
1526 (match_operand:HI 0 "arith_reg_operand" "r"))
1528 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1531 [(set_attr "type" "smpy")])
1533 (define_expand "mulhisi3"
1534 [(set (reg:SI MACL_REG)
1535 (mult:SI (sign_extend:SI
1536 (match_operand:HI 1 "arith_reg_operand" ""))
1538 (match_operand:HI 2 "arith_reg_operand" ""))))
1539 (set (match_operand:SI 0 "arith_reg_operand" "")
1546 first = emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
1547 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
1548 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1549 invariant code motion can move it. */
1550 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1551 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1552 /* expand_binop can't find a suitable code in umul_widen_optab to
1553 make a REG_EQUAL note from, so make one here.
1554 See also smulsi3_highpart.
1555 ??? Alternatively, we could put this at the calling site of expand_binop,
1556 i.e. expand_expr. */
1558 = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
1563 (define_expand "umulhisi3"
1564 [(set (reg:SI MACL_REG)
1565 (mult:SI (zero_extend:SI
1566 (match_operand:HI 1 "arith_reg_operand" ""))
1568 (match_operand:HI 2 "arith_reg_operand" ""))))
1569 (set (match_operand:SI 0 "arith_reg_operand" "")
1576 first = emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
1577 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
1578 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1579 invariant code motion can move it. */
1580 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1581 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1582 /* expand_binop can't find a suitable code in umul_widen_optab to
1583 make a REG_EQUAL note from, so make one here.
1584 See also smulsi3_highpart.
1585 ??? Alternatively, we could put this at the calling site of expand_binop,
1586 i.e. expand_expr. */
1588 = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
1593 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
1594 ;; a call to a routine which clobbers known registers.
1597 [(set (match_operand:SI 1 "register_operand" "=z")
1598 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1599 (clobber (reg:SI MACL_REG))
1600 (clobber (reg:SI T_REG))
1601 (clobber (reg:SI PR_REG))
1602 (clobber (reg:SI R3_REG))
1603 (clobber (reg:SI R2_REG))
1604 (clobber (reg:SI R1_REG))
1605 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
1608 [(set_attr "type" "sfunc")
1609 (set_attr "needs_delay_slot" "yes")])
1611 (define_expand "mulsi3_call"
1612 [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1613 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1614 (parallel[(set (match_operand:SI 0 "register_operand" "")
1615 (mult:SI (reg:SI R4_REG)
1617 (clobber (reg:SI MACL_REG))
1618 (clobber (reg:SI T_REG))
1619 (clobber (reg:SI PR_REG))
1620 (clobber (reg:SI R3_REG))
1621 (clobber (reg:SI R2_REG))
1622 (clobber (reg:SI R1_REG))
1623 (use (match_operand:SI 3 "register_operand" ""))])]
1627 (define_insn "mul_r"
1628 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1629 (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
1630 (match_operand:SI 2 "arith_reg_operand" "z")))]
1633 [(set_attr "type" "dmpy")])
1635 (define_insn "mul_l"
1636 [(set (reg:SI MACL_REG)
1637 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
1638 (match_operand:SI 1 "arith_reg_operand" "r")))]
1641 [(set_attr "type" "dmpy")])
1643 (define_expand "mulsi3"
1644 [(set (reg:SI MACL_REG)
1645 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
1646 (match_operand:SI 2 "arith_reg_operand" "")))
1647 (set (match_operand:SI 0 "arith_reg_operand" "")
1656 /* The address must be set outside the libcall,
1657 since it goes into a pseudo. */
1658 rtx sym = function_symbol (\"__mulsi3\");
1659 rtx addr = force_reg (SImode, sym);
1660 rtx insns = gen_mulsi3_call (operands[0], operands[1],
1663 last = emit_insn (insns);
1667 rtx macl = gen_rtx_REG (SImode, MACL_REG);
1669 first = emit_insn (gen_mul_l (operands[1], operands[2]));
1670 /* consec_sets_giv can only recognize the first insn that sets a
1671 giv as the giv insn. So we must tag this also with a REG_EQUAL
1673 last = emit_insn (gen_movsi_i ((operands[0]), macl));
1675 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1676 invariant code motion can move it. */
1677 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1678 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1682 (define_insn "mulsidi3_i"
1683 [(set (reg:SI MACH_REG)
1687 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1688 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1690 (set (reg:SI MACL_REG)
1691 (mult:SI (match_dup 0)
1695 [(set_attr "type" "dmpy")])
1697 (define_expand "mulsidi3"
1698 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1699 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1700 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1701 "TARGET_SH2 || TARGET_SHMEDIA"
1706 emit_insn (gen_mulsidi3_compact (operands[0], operands[1],
1712 (define_insn "mulsidi3_media"
1713 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1714 (mult:DI (sign_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
1715 (sign_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
1718 [(set_attr "type" "dmpy_media")])
1720 (define_insn "mulsidi3_compact"
1721 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1723 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1724 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1725 (clobber (reg:SI MACH_REG))
1726 (clobber (reg:SI MACL_REG))]
1731 [(set (match_operand:DI 0 "arith_reg_operand" "")
1733 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1734 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1735 (clobber (reg:SI MACH_REG))
1736 (clobber (reg:SI MACL_REG))]
1741 rtx low_dst = gen_lowpart (SImode, operands[0]);
1742 rtx high_dst = gen_highpart (SImode, operands[0]);
1744 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
1746 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
1747 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
1748 /* We need something to tag the possible REG_EQUAL notes on to. */
1749 emit_move_insn (operands[0], operands[0]);
1753 (define_insn "umulsidi3_i"
1754 [(set (reg:SI MACH_REG)
1758 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1759 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1761 (set (reg:SI MACL_REG)
1762 (mult:SI (match_dup 0)
1766 [(set_attr "type" "dmpy")])
1768 (define_expand "umulsidi3"
1769 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1770 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1771 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1772 "TARGET_SH2 || TARGET_SHMEDIA"
1777 emit_insn (gen_umulsidi3_compact (operands[0], operands[1],
1783 (define_insn "umulsidi3_media"
1784 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1785 (mult:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
1786 (zero_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
1789 [(set_attr "type" "dmpy_media")])
1791 (define_insn "umulsidi3_compact"
1792 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1794 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1795 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1796 (clobber (reg:SI MACH_REG))
1797 (clobber (reg:SI MACL_REG))]
1802 [(set (match_operand:DI 0 "arith_reg_operand" "")
1803 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1804 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1805 (clobber (reg:SI MACH_REG))
1806 (clobber (reg:SI MACL_REG))]
1811 rtx low_dst = gen_lowpart (SImode, operands[0]);
1812 rtx high_dst = gen_highpart (SImode, operands[0]);
1814 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
1816 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
1817 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
1818 /* We need something to tag the possible REG_EQUAL notes on to. */
1819 emit_move_insn (operands[0], operands[0]);
1823 (define_insn "smulsi3_highpart_i"
1824 [(set (reg:SI MACH_REG)
1828 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1829 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1831 (clobber (reg:SI MACL_REG))]
1834 [(set_attr "type" "dmpy")])
1836 (define_expand "smulsi3_highpart"
1838 [(set (reg:SI MACH_REG)
1842 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1843 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1845 (clobber (reg:SI MACL_REG))])
1846 (set (match_operand:SI 0 "arith_reg_operand" "")
1853 first = emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
1854 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
1855 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1856 invariant code motion can move it. */
1857 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1858 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1859 /* expand_binop can't find a suitable code in mul_highpart_optab to
1860 make a REG_EQUAL note from, so make one here.
1861 See also {,u}mulhisi.
1862 ??? Alternatively, we could put this at the calling site of expand_binop,
1863 i.e. expand_mult_highpart. */
1865 = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
1870 (define_insn "umulsi3_highpart_i"
1871 [(set (reg:SI MACH_REG)
1875 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1876 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1878 (clobber (reg:SI MACL_REG))]
1881 [(set_attr "type" "dmpy")])
1883 (define_expand "umulsi3_highpart"
1885 [(set (reg:SI MACH_REG)
1889 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1890 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1892 (clobber (reg:SI MACL_REG))])
1893 (set (match_operand:SI 0 "arith_reg_operand" "")
1900 first = emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
1901 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
1902 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1903 invariant code motion can move it. */
1904 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1905 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1909 ;; -------------------------------------------------------------------------
1910 ;; Logical operations
1911 ;; -------------------------------------------------------------------------
1913 (define_insn "*andsi3_compact"
1914 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1915 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1916 (match_operand:SI 2 "logical_operand" "r,K08")))]
1919 [(set_attr "type" "arith")])
1921 ;; If the constant is 255, then emit an extu.b instruction instead of an
1922 ;; and, since that will give better code.
1924 (define_expand "andsi3"
1925 [(set (match_operand:SI 0 "arith_reg_operand" "")
1926 (and:SI (match_operand:SI 1 "arith_reg_operand" "")
1927 (match_operand:SI 2 "logical_operand" "")))]
1931 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
1933 emit_insn (gen_zero_extendqisi2 (operands[0],
1934 gen_lowpart (QImode, operands[1])));
1939 (define_insn_and_split "anddi3"
1940 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r,r")
1941 (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
1942 (match_operand:DI 2 "and_operand" "r,I10,J16")))]
1949 && ! logical_operand (operands[2], DImode)"
1953 if (INTVAL (operands[2]) == (unsigned) 0xffffffff)
1954 emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode)));
1956 emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1]));
1959 [(set_attr "type" "arith_media")])
1961 (define_insn "andcdi3"
1962 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1963 (and:DI (match_operand:DI 1 "arith_reg_operand" "r")
1964 (not:DI (match_operand:DI 2 "arith_reg_operand" "r"))))]
1967 [(set_attr "type" "arith_media")])
1969 (define_insn "iorsi3"
1970 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1971 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1972 (match_operand:SI 2 "logical_operand" "r,K08")))]
1975 [(set_attr "type" "arith")])
1977 (define_insn "iordi3"
1978 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
1979 (ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1980 (match_operand:DI 2 "logical_operand" "r,I10")))]
1985 [(set_attr "type" "arith_media")])
1987 (define_insn "xorsi3"
1988 [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
1989 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1990 (match_operand:SI 2 "logical_operand" "K08,r")))]
1993 [(set_attr "type" "arith")])
1995 (define_insn "xordi3"
1996 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
1997 (xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1998 (match_operand:DI 2 "shmedia_6bit_operand" "r,I06")))]
2003 [(set_attr "type" "arith_media")])
2005 ;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate.
2006 ;; converts 2 * sign extend -> logical op into logical op -> sign extend
2008 [(set (match_operand:DI 0 "arith_reg_operand" "")
2009 (sign_extend:DI (match_operator 4 "binary_logical_operator"
2010 [(match_operand 1 "any_register_operand" "")
2011 (match_operand 2 "any_register_operand" "")])))]
2013 [(set (match_dup 5) (match_dup 4))
2014 (set (match_dup 0) (sign_extend:DI (match_dup 5)))]
2017 enum machine_mode inmode = GET_MODE (operands[1]);
2020 if (GET_CODE (operands[0]) == SUBREG)
2022 offset = SUBREG_BYTE (operands[0]);
2023 operands[0] = SUBREG_REG (operands[0]);
2025 if (GET_CODE (operands[0]) != REG)
2027 if (! TARGET_LITTLE_ENDIAN)
2028 offset += 8 - GET_MODE_SIZE (inmode);
2029 operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
2032 ;; -------------------------------------------------------------------------
2033 ;; Shifts and rotates
2034 ;; -------------------------------------------------------------------------
2036 (define_expand "rotldi3"
2037 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2038 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
2039 (match_operand:HI 2 "mextr_bit_offset" "i")))]
2041 "if (! mextr_bit_offset (operands[2], HImode)) FAIL;")
2043 (define_insn "rotldi3_mextr"
2044 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2045 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
2046 (match_operand:HI 2 "mextr_bit_offset" "i")))]
2050 static char templ[16];
2052 sprintf (templ, \"mextr%d\\t%%1,%%1,%%0\",
2053 8 - (int) (INTVAL (operands[2]) >> 3));
2056 [(set_attr "type" "arith_media")])
2058 (define_expand "rotrdi3"
2059 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2060 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
2061 (match_operand:HI 2 "mextr_bit_offset" "i")))]
2063 "if (! mextr_bit_offset (operands[2], HImode)) FAIL;")
2065 (define_insn "rotrdi3_mextr"
2066 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2067 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
2068 (match_operand:HI 2 "mextr_bit_offset" "i")))]
2072 static char templ[16];
2074 sprintf (templ, \"mextr%d\\t%%1,%%1,%%0\", (int) INTVAL (operands[2]) >> 3);
2077 [(set_attr "type" "arith_media")])
2079 (define_insn "rotlsi3_1"
2080 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2081 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2084 (lshiftrt:SI (match_dup 1) (const_int 31)))]
2087 [(set_attr "type" "arith")])
2089 (define_insn "rotlsi3_31"
2090 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2091 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2093 (clobber (reg:SI T_REG))]
2096 [(set_attr "type" "arith")])
2098 (define_insn "rotlsi3_16"
2099 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2100 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
2104 [(set_attr "type" "arith")])
2106 (define_expand "rotlsi3"
2107 [(set (match_operand:SI 0 "arith_reg_operand" "")
2108 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
2109 (match_operand:SI 2 "immediate_operand" "")))]
2113 static const char rot_tab[] = {
2114 000, 000, 000, 000, 000, 000, 010, 001,
2115 001, 001, 011, 013, 003, 003, 003, 003,
2116 003, 003, 003, 003, 003, 013, 012, 002,
2117 002, 002, 010, 000, 000, 000, 000, 000,
2122 if (GET_CODE (operands[2]) != CONST_INT)
2124 count = INTVAL (operands[2]);
2125 choice = rot_tab[count];
2126 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
2132 emit_move_insn (operands[0], operands[1]);
2133 count -= (count & 16) * 2;
2136 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
2143 parts[0] = gen_reg_rtx (SImode);
2144 parts[1] = gen_reg_rtx (SImode);
2145 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
2146 emit_move_insn (parts[choice-1], operands[1]);
2147 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
2148 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
2149 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
2150 count = (count & ~16) - 8;
2154 for (; count > 0; count--)
2155 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2156 for (; count < 0; count++)
2157 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2162 (define_insn "*rotlhi3_8"
2163 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
2164 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
2168 [(set_attr "type" "arith")])
2170 (define_expand "rotlhi3"
2171 [(set (match_operand:HI 0 "arith_reg_operand" "")
2172 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
2173 (match_operand:HI 2 "immediate_operand" "")))]
2177 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
2184 (define_insn "ashlsi3_sh2a"
2185 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2186 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
2187 (match_operand:SI 2 "arith_reg_operand" "r")))]
2190 [(set_attr "type" "arith")
2191 (set_attr "length" "4")])
2193 ;; This pattern is used by init_expmed for computing the costs of shift
2196 (define_insn_and_split "ashlsi3_std"
2197 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r")
2198 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
2199 (match_operand:SI 2 "nonmemory_operand" "r,M,P27,?ri")))
2200 (clobber (match_scratch:SI 3 "=X,X,X,&r"))]
2202 || (TARGET_SH1 && GET_CODE (operands[2]) == CONST_INT
2203 && CONST_OK_FOR_P27 (INTVAL (operands[2])))"
2211 && GET_CODE (operands[2]) == CONST_INT
2212 && ! CONST_OK_FOR_P27 (INTVAL (operands[2]))"
2213 [(set (match_dup 3) (match_dup 2))
2215 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
2216 (clobber (match_dup 4))])]
2217 "operands[4] = gen_rtx_SCRATCH (SImode);"
2218 [(set_attr "length" "*,*,*,4")
2219 (set_attr "type" "dyn_shift,arith,arith,arith")])
2221 (define_insn "ashlhi3_k"
2222 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
2223 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
2224 (match_operand:HI 2 "const_int_operand" "M,P27")))]
2225 "TARGET_SH1 && CONST_OK_FOR_P27 (INTVAL (operands[2]))"
2229 [(set_attr "type" "arith")])
2231 (define_insn "ashlsi3_n"
2232 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2233 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
2234 (match_operand:SI 2 "const_int_operand" "n")))
2235 (clobber (reg:SI T_REG))]
2236 "TARGET_SH1 && ! sh_dynamicalize_shift_p (operands[2])"
2238 [(set (attr "length")
2239 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
2241 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
2243 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
2245 (const_string "8")))
2246 (set_attr "type" "arith")])
2249 [(set (match_operand:SI 0 "arith_reg_operand" "")
2250 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
2251 (match_operand:SI 2 "const_int_operand" "")))
2252 (clobber (reg:SI T_REG))]
2253 "TARGET_SH1 && reload_completed"
2254 [(use (reg:SI R0_REG))]
2257 gen_shifty_op (ASHIFT, operands);
2261 (define_insn "ashlsi3_media"
2262 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2263 (ashift:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
2264 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
2269 [(set_attr "type" "arith_media")])
2271 (define_expand "ashlsi3"
2272 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
2273 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
2274 (match_operand:SI 2 "nonmemory_operand" "")))
2275 (clobber (reg:SI T_REG))])]
2281 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
2284 if (GET_CODE (operands[2]) == CONST_INT
2285 && sh_dynamicalize_shift_p (operands[2]))
2286 operands[2] = force_reg (SImode, operands[2]);
2289 emit_insn (gen_ashlsi3_std (operands[0], operands[1], operands[2]));
2292 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
2296 (define_insn "*ashlhi3_n"
2297 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
2298 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
2299 (match_operand:HI 2 "const_int_operand" "n")))
2300 (clobber (reg:SI T_REG))]
2303 [(set (attr "length")
2304 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
2306 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
2308 (const_string "6")))
2309 (set_attr "type" "arith")])
2311 (define_expand "ashlhi3"
2312 [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
2313 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
2314 (match_operand:SI 2 "nonmemory_operand" "")))
2315 (clobber (reg:SI T_REG))])]
2319 if (GET_CODE (operands[2]) != CONST_INT)
2321 /* It may be possible to call gen_ashlhi3 directly with more generic
2322 operands. Make sure operands[1] is a HImode register here. */
2323 if (!arith_reg_operand (operands[1], HImode))
2324 operands[1] = copy_to_mode_reg (HImode, operands[1]);
2328 [(set (match_operand:HI 0 "arith_reg_operand" "")
2329 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
2330 (match_operand:HI 2 "const_int_operand" "")))
2331 (clobber (reg:SI T_REG))]
2332 "TARGET_SH1 && reload_completed"
2333 [(use (reg:SI R0_REG))]
2336 gen_shifty_hi_op (ASHIFT, operands);
2341 ; arithmetic shift right
2344 (define_insn "ashrsi3_sh2a"
2345 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2346 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2347 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
2350 [(set_attr "type" "dyn_shift")
2351 (set_attr "length" "4")])
2353 (define_insn "ashrsi3_k"
2354 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2355 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2356 (match_operand:SI 2 "const_int_operand" "M")))
2357 (clobber (reg:SI T_REG))]
2358 "TARGET_SH1 && INTVAL (operands[2]) == 1"
2360 [(set_attr "type" "arith")])
2362 ;; We can't do HImode right shifts correctly unless we start out with an
2363 ;; explicit zero / sign extension; doing that would result in worse overall
2364 ;; code, so just let the machine independent code widen the mode.
2365 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
2368 ;; ??? This should be a define expand.
2370 (define_insn "ashrsi2_16"
2371 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2372 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
2376 [(set_attr "length" "4")])
2379 [(set (match_operand:SI 0 "arith_reg_operand" "")
2380 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
2383 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
2384 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
2385 "operands[2] = gen_lowpart (HImode, operands[0]);")
2387 ;; ??? This should be a define expand.
2389 (define_insn "ashrsi2_31"
2390 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2391 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2393 (clobber (reg:SI T_REG))]
2396 [(set_attr "length" "4")])
2399 [(set (match_operand:SI 0 "arith_reg_operand" "")
2400 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
2402 (clobber (reg:SI T_REG))]
2407 emit_insn (gen_ashlsi_c (operands[0], operands[1]));
2408 emit_insn (gen_subc1 (operands[0], operands[0], operands[0]));
2412 (define_insn "ashlsi_c"
2413 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2414 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
2416 (lt:SI (match_dup 1) (const_int 0)))]
2419 [(set_attr "type" "arith")])
2421 (define_insn "ashrsi3_d"
2422 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2423 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2424 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
2427 [(set_attr "type" "dyn_shift")])
2429 (define_insn "ashrsi3_n"
2430 [(set (reg:SI R4_REG)
2431 (ashiftrt:SI (reg:SI R4_REG)
2432 (match_operand:SI 0 "const_int_operand" "i")))
2433 (clobber (reg:SI T_REG))
2434 (clobber (reg:SI PR_REG))
2435 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2438 [(set_attr "type" "sfunc")
2439 (set_attr "needs_delay_slot" "yes")])
2441 (define_insn "ashrsi3_media"
2442 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2443 (ashiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
2444 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
2449 [(set_attr "type" "arith_media")])
2451 (define_expand "ashrsi3"
2452 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
2453 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
2454 (match_operand:SI 2 "nonmemory_operand" "")))
2455 (clobber (reg:SI T_REG))])]
2461 emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
2464 if (expand_ashiftrt (operands))
2470 ;; logical shift right
2472 (define_insn "lshrsi3_sh2a"
2473 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2474 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2475 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
2478 [(set_attr "type" "dyn_shift")
2479 (set_attr "length" "4")])
2481 (define_insn "lshrsi3_d"
2482 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2483 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2484 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
2487 [(set_attr "type" "dyn_shift")])
2489 ;; Only the single bit shift clobbers the T bit.
2491 (define_insn "lshrsi3_m"
2492 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2493 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2494 (match_operand:SI 2 "const_int_operand" "M")))
2495 (clobber (reg:SI T_REG))]
2496 "TARGET_SH1 && CONST_OK_FOR_M (INTVAL (operands[2]))"
2498 [(set_attr "type" "arith")])
2500 (define_insn "lshrsi3_k"
2501 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2502 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2503 (match_operand:SI 2 "const_int_operand" "P27")))]
2504 "TARGET_SH1 && CONST_OK_FOR_P27 (INTVAL (operands[2]))
2505 && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
2507 [(set_attr "type" "arith")])
2509 (define_insn "lshrsi3_n"
2510 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2511 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2512 (match_operand:SI 2 "const_int_operand" "n")))
2513 (clobber (reg:SI T_REG))]
2514 "TARGET_SH1 && ! sh_dynamicalize_shift_p (operands[2])"
2516 [(set (attr "length")
2517 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
2519 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
2521 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
2523 (const_string "8")))
2524 (set_attr "type" "arith")])
2527 [(set (match_operand:SI 0 "arith_reg_operand" "")
2528 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
2529 (match_operand:SI 2 "const_int_operand" "")))
2530 (clobber (reg:SI T_REG))]
2531 "TARGET_SH1 && reload_completed"
2532 [(use (reg:SI R0_REG))]
2535 gen_shifty_op (LSHIFTRT, operands);
2539 (define_insn "lshrsi3_media"
2540 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2541 (lshiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
2542 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
2547 [(set_attr "type" "arith_media")])
2549 (define_expand "lshrsi3"
2550 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
2551 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
2552 (match_operand:SI 2 "nonmemory_operand" "")))
2553 (clobber (reg:SI T_REG))])]
2559 emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2]));
2562 if (GET_CODE (operands[2]) == CONST_INT
2563 && sh_dynamicalize_shift_p (operands[2]))
2564 operands[2] = force_reg (SImode, operands[2]);
2565 if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
2567 rtx count = copy_to_mode_reg (SImode, operands[2]);
2568 emit_insn (gen_negsi2 (count, count));
2569 emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
2572 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
2576 ;; ??? This should be a define expand.
2578 (define_insn "ashldi3_k"
2579 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
2580 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
2582 (clobber (reg:SI T_REG))]
2584 "shll %R0\;rotcl %S0"
2585 [(set_attr "length" "4")
2586 (set_attr "type" "arith")])
2588 (define_insn "ashldi3_media"
2589 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
2590 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
2591 (match_operand:DI 2 "nonmemory_operand" "r,n")))]
2596 [(set_attr "type" "arith_media")])
2598 (define_expand "ashldi3"
2599 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
2600 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
2601 (match_operand:DI 2 "immediate_operand" "")))
2602 (clobber (reg:SI T_REG))])]
2608 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
2611 if (GET_CODE (operands[2]) != CONST_INT
2612 || INTVAL (operands[2]) != 1)
2616 ;; ??? This should be a define expand.
2618 (define_insn "lshrdi3_k"
2619 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
2620 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
2622 (clobber (reg:SI T_REG))]
2624 "shlr %S0\;rotcr %R0"
2625 [(set_attr "length" "4")
2626 (set_attr "type" "arith")])
2628 (define_insn "lshrdi3_media"
2629 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
2630 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
2631 (match_operand:DI 2 "nonmemory_operand" "r,n")))]
2636 [(set_attr "type" "arith_media")])
2638 (define_expand "lshrdi3"
2639 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
2640 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
2641 (match_operand:DI 2 "immediate_operand" "")))
2642 (clobber (reg:SI T_REG))])]
2648 emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2]));
2651 if (GET_CODE (operands[2]) != CONST_INT
2652 || INTVAL (operands[2]) != 1)
2656 ;; ??? This should be a define expand.
2658 (define_insn "ashrdi3_k"
2659 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
2660 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
2662 (clobber (reg:SI T_REG))]
2664 "shar %S0\;rotcr %R0"
2665 [(set_attr "length" "4")
2666 (set_attr "type" "arith")])
2668 (define_insn "ashrdi3_media"
2669 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
2670 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
2671 (match_operand:DI 2 "nonmemory_operand" "r,n")))]
2676 [(set_attr "type" "arith_media")])
2678 (define_expand "ashrdi3"
2679 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
2680 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
2681 (match_operand:DI 2 "immediate_operand" "")))
2682 (clobber (reg:SI T_REG))])]
2688 emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
2691 if (GET_CODE (operands[2]) != CONST_INT
2692 || INTVAL (operands[2]) != 1)
2696 ;; combined left/right shift
2699 [(set (match_operand:SI 0 "register_operand" "")
2700 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
2701 (match_operand:SI 2 "const_int_operand" ""))
2702 (match_operand:SI 3 "const_int_operand" "")))]
2703 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
2704 [(use (reg:SI R0_REG))]
2705 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
2709 [(set (match_operand:SI 0 "register_operand" "")
2710 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
2711 (match_operand:SI 2 "const_int_operand" ""))
2712 (match_operand:SI 3 "const_int_operand" "")))
2713 (clobber (reg:SI T_REG))]
2714 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
2715 [(use (reg:SI R0_REG))]
2716 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
2720 [(set (match_operand:SI 0 "register_operand" "=r")
2721 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2722 (match_operand:SI 2 "const_int_operand" "n"))
2723 (match_operand:SI 3 "const_int_operand" "n")))
2724 (clobber (reg:SI T_REG))]
2725 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
2727 [(set (attr "length")
2728 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
2730 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
2732 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
2734 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
2736 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
2738 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
2740 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
2741 (const_string "16")]
2742 (const_string "18")))
2743 (set_attr "type" "arith")])
2746 [(set (match_operand:SI 0 "register_operand" "=z")
2747 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2748 (match_operand:SI 2 "const_int_operand" "n"))
2749 (match_operand:SI 3 "const_int_operand" "n")))
2750 (clobber (reg:SI T_REG))]
2751 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
2753 [(set (attr "length")
2754 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
2756 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
2758 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
2760 (const_string "10")))
2761 (set_attr "type" "arith")])
2763 ;; shift left / and combination with a scratch register: The combine pass
2764 ;; does not accept the individual instructions, even though they are
2765 ;; cheap. But it needs a precise description so that it is usable after
2767 (define_insn "and_shl_scratch"
2768 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2772 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
2773 (match_operand:SI 2 "const_int_operand" "N,n"))
2774 (match_operand:SI 3 "" "0,r"))
2775 (match_operand:SI 4 "const_int_operand" "n,n"))
2776 (match_operand:SI 5 "const_int_operand" "n,n")))
2777 (clobber (reg:SI T_REG))]
2780 [(set (attr "length")
2781 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
2783 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
2785 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
2787 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
2788 (const_string "10")]
2789 (const_string "12")))
2790 (set_attr "type" "arith")])
2793 [(set (match_operand:SI 0 "register_operand" "")
2797 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
2798 (match_operand:SI 2 "const_int_operand" ""))
2799 (match_operand:SI 3 "register_operand" ""))
2800 (match_operand:SI 4 "const_int_operand" ""))
2801 (match_operand:SI 5 "const_int_operand" "")))
2802 (clobber (reg:SI T_REG))]
2804 [(use (reg:SI R0_REG))]
2807 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
2809 if (INTVAL (operands[2]))
2811 gen_shifty_op (LSHIFTRT, operands);
2813 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
2814 operands[2] = operands[4];
2815 gen_shifty_op (ASHIFT, operands);
2816 if (INTVAL (operands[5]))
2818 operands[2] = operands[5];
2819 gen_shifty_op (LSHIFTRT, operands);
2824 ;; signed left/right shift combination.
2826 [(set (match_operand:SI 0 "register_operand" "")
2828 (ashift:SI (match_operand:SI 1 "register_operand" "")
2829 (match_operand:SI 2 "const_int_operand" ""))
2830 (match_operand:SI 3 "const_int_operand" "")
2832 (clobber (reg:SI T_REG))]
2834 [(use (reg:SI R0_REG))]
2835 "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
2838 (define_insn "shl_sext_ext"
2839 [(set (match_operand:SI 0 "register_operand" "=r")
2841 (ashift:SI (match_operand:SI 1 "register_operand" "0")
2842 (match_operand:SI 2 "const_int_operand" "n"))
2843 (match_operand:SI 3 "const_int_operand" "n")
2845 (clobber (reg:SI T_REG))]
2846 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
2848 [(set (attr "length")
2849 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 1))
2851 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
2853 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2855 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2857 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2859 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2861 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
2863 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
2864 (const_string "16")]
2865 (const_string "18")))
2866 (set_attr "type" "arith")])
2868 (define_insn "shl_sext_sub"
2869 [(set (match_operand:SI 0 "register_operand" "=z")
2871 (ashift:SI (match_operand:SI 1 "register_operand" "0")
2872 (match_operand:SI 2 "const_int_operand" "n"))
2873 (match_operand:SI 3 "const_int_operand" "n")
2875 (clobber (reg:SI T_REG))]
2876 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
2878 [(set (attr "length")
2879 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2881 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2883 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2885 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2886 (const_string "12")]
2887 (const_string "14")))
2888 (set_attr "type" "arith")])
2890 ;; These patterns are found in expansions of DImode shifts by 16, and
2891 ;; allow the xtrct instruction to be generated from C source.
2893 (define_insn "xtrct_left"
2894 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2895 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
2897 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
2901 [(set_attr "type" "arith")])
2903 (define_insn "xtrct_right"
2904 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2905 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2907 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
2911 [(set_attr "type" "arith")])
2913 ;; -------------------------------------------------------------------------
2915 ;; -------------------------------------------------------------------------
2918 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2919 (neg:SI (plus:SI (reg:SI T_REG)
2920 (match_operand:SI 1 "arith_reg_operand" "r"))))
2922 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
2926 [(set_attr "type" "arith")])
2928 (define_insn "*negdi_media"
2929 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
2930 (neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
2933 [(set_attr "type" "arith_media")])
2935 (define_expand "negdi2"
2936 [(set (match_operand:DI 0 "arith_reg_operand" "")
2937 (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))]
2943 int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
2944 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
2946 rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
2947 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
2949 rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
2950 rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
2952 emit_insn (gen_clrt ());
2953 emit_insn (gen_negc (low_dst, low_src));
2954 emit_insn (gen_negc (high_dst, high_src));
2959 (define_insn "negsi2"
2960 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2961 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2964 [(set_attr "type" "arith")])
2966 (define_insn "one_cmplsi2"
2967 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2968 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2971 [(set_attr "type" "arith")])
2973 (define_expand "one_cmpldi2"
2974 [(set (match_operand:DI 0 "arith_reg_operand" "")
2975 (xor:DI (match_operand:DI 1 "arith_reg_operand" "")
2977 "TARGET_SHMEDIA" "")
2979 ;; -------------------------------------------------------------------------
2980 ;; Zero extension instructions
2981 ;; -------------------------------------------------------------------------
2983 (define_insn "zero_extendsidi2"
2984 [(set (match_operand:DI 0 "register_operand" "=r")
2985 (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "r")))]
2987 "addz.l %1, r63, %0"
2988 [(set_attr "type" "arith_media")])
2990 (define_insn "zero_extendhidi2"
2991 [(set (match_operand:DI 0 "register_operand" "=r,r")
2992 (zero_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
2997 [(set_attr "type" "*,load_media")])
3000 [(set (match_operand:DI 0 "register_operand" "")
3001 (zero_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
3002 "TARGET_SHMEDIA && reload_completed"
3003 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
3004 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))]
3007 if (GET_CODE (operands[1]) == TRUNCATE)
3008 operands[1] = XEXP (operands[1], 0);
3011 ;; ??? when a truncated input to a zero_extend is reloaded, reload will
3012 ;; reload the entire truncate expression.
3013 (define_insn_and_split "*loaddi_trunc"
3014 [(set (match_operand 0 "int_gpr_dest" "=r")
3015 (truncate (match_operand:DI 1 "memory_operand" "m")))]
3016 "TARGET_SHMEDIA && reload_completed"
3018 "TARGET_SHMEDIA && reload_completed"
3019 [(set (match_dup 0) (match_dup 1))]
3020 "operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));")
3022 (define_insn "zero_extendqidi2"
3023 [(set (match_operand:DI 0 "register_operand" "=r,r")
3024 (zero_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
3029 [(set_attr "type" "arith_media,load_media")])
3031 (define_expand "zero_extendhisi2"
3032 [(set (match_operand:SI 0 "arith_reg_operand" "")
3033 (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "")))]
3037 if (! TARGET_SHMEDIA && ! arith_reg_operand (operands[1], HImode))
3038 operands[1] = copy_to_mode_reg (HImode, operands[1]);
3041 (define_insn "*zero_extendhisi2_compact"
3042 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3043 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
3046 [(set_attr "type" "arith")])
3048 (define_insn "*zero_extendhisi2_media"
3049 [(set (match_operand:SI 0 "register_operand" "=r,r")
3050 (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
3055 [(set_attr "type" "arith_media,load_media")])
3058 [(set (match_operand:SI 0 "register_operand" "")
3059 (zero_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
3060 "TARGET_SHMEDIA && reload_completed"
3061 [(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 16)))
3062 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
3065 if (GET_CODE (operands[1]) == TRUNCATE)
3066 operands[1] = XEXP (operands[1], 0);
3069 (define_expand "zero_extendqisi2"
3070 [(set (match_operand:SI 0 "arith_reg_operand" "")
3071 (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "")))]
3075 if (! TARGET_SHMEDIA && ! arith_reg_operand (operands[1], QImode))
3076 operands[1] = copy_to_mode_reg (QImode, operands[1]);
3079 (define_insn "*zero_extendqisi2_compact"
3080 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3081 (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
3084 [(set_attr "type" "arith")])
3086 (define_insn "*zero_extendqisi2_media"
3087 [(set (match_operand:SI 0 "register_operand" "=r,r")
3088 (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
3093 [(set_attr "type" "arith_media,load_media")])
3095 (define_insn "zero_extendqihi2"
3096 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
3097 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
3100 [(set_attr "type" "arith")])
3102 ;; -------------------------------------------------------------------------
3103 ;; Sign extension instructions
3104 ;; -------------------------------------------------------------------------
3106 ;; ??? This should be a define expand.
3107 ;; ??? Or perhaps it should be dropped?
3109 ;; convert_move generates good code for SH[1-4].
3110 (define_insn "extendsidi2"
3111 [(set (match_operand:DI 0 "register_operand" "=r,r")
3112 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
3117 [(set_attr "type" "arith_media,load_media")])
3119 (define_insn "extendhidi2"
3120 [(set (match_operand:DI 0 "register_operand" "=r,r")
3121 (sign_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
3126 [(set_attr "type" "*,load_media")])
3129 [(set (match_operand:DI 0 "register_operand" "")
3130 (sign_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
3131 "TARGET_SHMEDIA && reload_completed"
3132 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
3133 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))]
3136 if (GET_CODE (operands[1]) == TRUNCATE)
3137 operands[1] = XEXP (operands[1], 0);
3140 (define_insn "extendqidi2"
3141 [(set (match_operand:DI 0 "register_operand" "=r,r")
3142 (sign_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
3147 [(set_attr "type" "*,load_media")])
3150 [(set (match_operand:DI 0 "register_operand" "")
3151 (sign_extend:DI (match_operand:QI 1 "extend_reg_operand" "")))]
3152 "TARGET_SHMEDIA && reload_completed"
3153 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 56)))
3154 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))]
3157 if (GET_CODE (operands[1]) == TRUNCATE)
3158 operands[1] = XEXP (operands[1], 0);
3161 (define_expand "extendhisi2"
3162 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
3163 (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
3167 (define_insn "*extendhisi2_compact"
3168 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
3169 (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
3174 [(set_attr "type" "arith,load")])
3176 (define_insn "*extendhisi2_media"
3177 [(set (match_operand:SI 0 "register_operand" "=r,r")
3178 (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
3183 [(set_attr "type" "arith_media,load_media")])
3186 [(set (match_operand:SI 0 "register_operand" "")
3187 (sign_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
3188 "TARGET_SHMEDIA && reload_completed"
3189 [(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 16)))
3190 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
3193 if (GET_CODE (operands[1]) == TRUNCATE)
3194 operands[1] = XEXP (operands[1], 0);
3197 (define_expand "extendqisi2"
3198 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
3199 (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
3203 (define_insn "*extendqisi2_compact"
3204 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
3205 (sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
3210 [(set_attr "type" "arith,load")])
3212 (define_insn "*extendqisi2_media"
3213 [(set (match_operand:SI 0 "register_operand" "=r,r")
3214 (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
3219 [(set_attr "type" "arith_media,load_media")])
3222 [(set (match_operand:SI 0 "register_operand" "")
3223 (sign_extend:SI (match_operand:QI 1 "extend_reg_operand" "")))]
3224 "TARGET_SHMEDIA && reload_completed"
3225 [(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 24)))
3226 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
3229 if (GET_CODE (operands[1]) == TRUNCATE)
3230 operands[1] = XEXP (operands[1], 0);
3233 (define_insn "extendqihi2"
3234 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
3235 (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
3240 [(set_attr "type" "arith,load")])
3242 /* It would seem useful to combine the truncXi patterns into the movXi
3243 patterns, but unary operators are ignored when matching constraints,
3244 so we need separate patterns. */
3245 (define_insn "truncdisi2"
3246 [(set (match_operand:SI 0 "general_movdst_operand" "=r,m,m,f,r,f")
3247 (truncate:SI (match_operand:DI 1 "register_operand" "r,r,f,r,f,f")))]
3256 [(set_attr "type" "arith_media,store_media,fstore_media,fload_media,fpconv_media,fmove_media")])
3259 (define_insn "truncdihi2"
3260 [(set (match_operand:HI 0 "general_movdst_operand" "=?r,m")
3261 (truncate:HI (match_operand:DI 1 "register_operand" "r,r")))]
3264 shlli\\t%1,48,%0\;shlri\\t%0,48,%0
3266 [(set_attr "type" "arith_media,store_media")
3267 (set_attr "length" "8,4")])
3269 ; N.B. This should agree with LOAD_EXTEND_OP and movqi.
3270 ; Because we use zero extension, we can't provide signed QImode compares
3271 ; using a simple compare or conditional banch insn.
3272 (define_insn "truncdiqi2"
3273 [(set (match_operand:QI 0 "general_movdst_operand" "=r,m")
3274 (truncate:QI (match_operand:DI 1 "register_operand" "r,r")))]
3279 [(set_attr "type" "arith_media,store")])
3281 ;; -------------------------------------------------------------------------
3282 ;; Move instructions
3283 ;; -------------------------------------------------------------------------
3285 ;; define push and pop so it is easy for sh.c
3286 ;; We can't use push and pop on SHcompact because the stack must always
3287 ;; be 8-byte aligned.
3289 (define_expand "push"
3290 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3291 (match_operand:SI 0 "register_operand" "r,l,x"))]
3292 "TARGET_SH1 && ! TARGET_SH5"
3295 (define_expand "pop"
3296 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
3297 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
3298 "TARGET_SH1 && ! TARGET_SH5"
3301 (define_expand "push_e"
3302 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
3303 (match_operand:SF 0 "" ""))
3304 (use (reg:PSI FPSCR_REG))
3305 (clobber (scratch:SI))])]
3306 "TARGET_SH1 && ! TARGET_SH5"
3309 (define_insn "push_fpul"
3310 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
3311 "TARGET_SH2E && ! TARGET_SH5"
3313 [(set_attr "type" "store")
3314 (set_attr "late_fp_use" "yes")
3315 (set_attr "hit_stack" "yes")])
3317 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
3319 (define_expand "push_4"
3320 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
3321 (match_operand:DF 0 "" ""))
3322 (use (reg:PSI FPSCR_REG))
3323 (clobber (scratch:SI))])]
3324 "TARGET_SH1 && ! TARGET_SH5"
3327 (define_expand "pop_e"
3328 [(parallel [(set (match_operand:SF 0 "" "")
3329 (mem:SF (post_inc:SI (reg:SI SP_REG))))
3330 (use (reg:PSI FPSCR_REG))
3331 (clobber (scratch:SI))])]
3332 "TARGET_SH1 && ! TARGET_SH5"
3335 (define_insn "pop_fpul"
3336 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
3337 "TARGET_SH2E && ! TARGET_SH5"
3339 [(set_attr "type" "load")
3340 (set_attr "hit_stack" "yes")])
3342 (define_expand "pop_4"
3343 [(parallel [(set (match_operand:DF 0 "" "")
3344 (mem:DF (post_inc:SI (reg:SI SP_REG))))
3345 (use (reg:PSI FPSCR_REG))
3346 (clobber (scratch:SI))])]
3347 "TARGET_SH1 && ! TARGET_SH5"
3350 (define_expand "push_fpscr"
3355 rtx insn = emit_insn (gen_fpu_switch (gen_rtx_MEM (PSImode,
3356 gen_rtx_PRE_DEC (Pmode,
3357 stack_pointer_rtx)),
3359 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, NULL_RTX);
3363 (define_expand "pop_fpscr"
3368 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
3369 gen_rtx_MEM (PSImode,
3370 gen_rtx_POST_INC (Pmode,
3371 stack_pointer_rtx))));
3372 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, NULL_RTX);
3376 ;; These two patterns can happen as the result of optimization, when
3377 ;; comparisons get simplified to a move of zero or 1 into the T reg.
3378 ;; They don't disappear completely, because the T reg is a fixed hard reg.
3381 [(set (reg:SI T_REG) (const_int 0))]
3386 [(set (reg:SI T_REG) (const_int 1))]
3390 ;; t/r must come after r/r, lest reload will try to reload stuff like
3391 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
3392 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
3393 (define_insn "movsi_i"
3394 [(set (match_operand:SI 0 "general_movdst_operand"
3395 "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
3396 (match_operand:SI 1 "general_movsrc_operand"
3397 "Q,rI08,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
3401 && (register_operand (operands[0], SImode)
3402 || register_operand (operands[1], SImode))"
3419 [(set_attr "type" "pcload_si,move,mt_group,load_si,mac_gp,prget,move,store,store,pstore,move,prset,load,pload,pcload_si")
3420 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
3422 ;; t/r must come after r/r, lest reload will try to reload stuff like
3423 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
3424 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
3425 ;; will require a reload.
3426 ;; ??? We can't include f/f because we need the proper FPSCR setting when
3427 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
3428 (define_insn "movsi_ie"
3429 [(set (match_operand:SI 0 "general_movdst_operand"
3430 "=r,r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
3431 (match_operand:SI 1 "general_movsrc_operand"
3432 "Q,rI08,I20,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
3433 "(TARGET_SH2E || TARGET_SH2A)
3434 && (register_operand (operands[0], SImode)
3435 || register_operand (operands[1], SImode))"
3460 ! move optimized away"
3461 [(set_attr "type" "pcload_si,move,move,*,load_si,mac_gp,prget,move,store,store,pstore,move,prset,load,pload,load,store,pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
3462 (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
3463 (set_attr "length" "*,*,4,*,4,*,*,*,4,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
3465 (define_insn "movsi_i_lowpart"
3466 [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
3467 (match_operand:SI 1 "general_movsrc_operand" "Q,rI08,mr,x,l,t,r,i"))]
3469 && (register_operand (operands[0], SImode)
3470 || register_operand (operands[1], SImode))"
3480 [(set_attr "type" "pcload,move,load,move,prget,move,store,pcload")])
3482 (define_insn_and_split "load_ra"
3483 [(set (match_operand:SI 0 "general_movdst_operand" "")
3484 (unspec:SI [(match_operand 1 "register_operand" "")] UNSPEC_RA))]
3487 "&& ! currently_expanding_to_rtl"
3488 [(set (match_dup 0) (match_dup 1))]
3491 if (TARGET_SHCOMPACT && current_function_has_nonlocal_label)
3492 operands[1] = gen_rtx_MEM (SImode, return_address_pointer_rtx);
3495 (define_insn "*movsi_media"
3496 [(set (match_operand:SI 0 "general_movdst_operand"
3497 "=r,r,r,r,m,f,m,f,r,f,*b,r,b")
3498 (match_operand:SI 1 "general_movsrc_operand"
3499 "r,I16C16,nCpg,m,rZ,m,f,rZ,f,f,r,*b,Csy"))]
3501 && (register_operand (operands[0], SImode)
3502 || sh_register_operand (operands[1], SImode))"
3517 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,fload_media,fstore_media,fload_media,fpconv_media,fmove_media,ptabs_media,gettr_media,pt_media")
3518 (set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12")])
3520 (define_insn "*movsi_media_nofpu"
3521 [(set (match_operand:SI 0 "general_movdst_operand"
3522 "=r,r,r,r,m,*b,r,b")
3523 (match_operand:SI 1 "general_movsrc_operand"
3524 "r,I16C16,nCpg,m,rZ,r,*b,Csy"))]
3526 && (register_operand (operands[0], SImode)
3527 || sh_register_operand (operands[1], SImode))"
3537 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,ptabs_media,gettr_media,pt_media")
3538 (set_attr "length" "4,4,8,4,4,4,4,12")])
3541 [(set (match_operand:SI 0 "arith_reg_operand" "")
3542 (match_operand:SI 1 "immediate_operand" ""))]
3543 "TARGET_SHMEDIA && reload_completed
3544 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
3545 [(set (subreg:DI (match_dup 0) 0) (match_dup 2))]
3548 operands[2] = shallow_copy_rtx (operands[1]);
3549 PUT_MODE (operands[2], DImode);
3553 [(set (match_operand:SI 0 "register_operand" "")
3554 (match_operand:SI 1 "immediate_operand" ""))]
3555 "TARGET_SHMEDIA && reload_completed
3556 && ((GET_CODE (operands[1]) == CONST_INT
3557 && ! CONST_OK_FOR_I16 (INTVAL (operands[1])))
3558 || GET_CODE (operands[1]) == CONST_DOUBLE)"
3559 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
3561 (define_expand "movsi"
3562 [(set (match_operand:SI 0 "general_movdst_operand" "")
3563 (match_operand:SI 1 "general_movsrc_operand" ""))]
3565 "{ if (prepare_move_operands (operands, SImode)) DONE; }")
3567 (define_expand "ic_invalidate_line"
3568 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
3569 (match_dup 1)] UNSPEC_ICACHE)
3570 (clobber (scratch:SI))])]
3571 "TARGET_HARD_SH4 || TARGET_SH5"
3576 emit_insn (gen_ic_invalidate_line_media (operands[0]));
3579 else if (TARGET_SHCOMPACT)
3581 operands[1] = function_symbol (\"__ic_invalidate\");
3582 operands[1] = force_reg (Pmode, operands[1]);
3583 emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1]));
3586 else if (TARGET_SH4A_ARCH)
3588 emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
3591 operands[0] = force_reg (Pmode, operands[0]);
3592 operands[1] = force_reg (Pmode, GEN_INT (trunc_int_for_mode (0xf0000008,
3596 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
3597 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
3598 ;; the requirement *1*00 for associative address writes. The alignment of
3599 ;; %0 implies that its least significant bit is cleared,
3600 ;; thus we clear the V bit of a matching entry if there is one.
3601 (define_insn "ic_invalidate_line_i"
3602 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
3603 (match_operand:SI 1 "register_operand" "r")]
3605 (clobber (match_scratch:SI 2 "=&r"))]
3607 "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
3608 [(set_attr "length" "8")
3609 (set_attr "type" "cwb")])
3611 (define_insn "ic_invalidate_line_sh4a"
3612 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
3615 "ocbwb\\t@%0\;synco\;icbi\\t@%0"
3616 [(set_attr "length" "16")
3617 (set_attr "type" "cwb")])
3619 ;; ??? could make arg 0 an offsettable memory operand to allow to save
3620 ;; an add in the code that calculates the address.
3621 (define_insn "ic_invalidate_line_media"
3622 [(unspec_volatile [(match_operand 0 "register_operand" "r")]
3625 "ocbwb %0,0\;synco\;icbi %0, 0\;synci"
3626 [(set_attr "length" "16")
3627 (set_attr "type" "invalidate_line_media")])
3629 (define_insn "ic_invalidate_line_compact"
3630 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
3631 (match_operand:SI 1 "register_operand" "r")]
3633 (clobber (reg:SI PR_REG))]
3636 [(set_attr "type" "sfunc")
3637 (set_attr "needs_delay_slot" "yes")])
3639 (define_expand "initialize_trampoline"
3640 [(match_operand:SI 0 "" "")
3641 (match_operand:SI 1 "" "")
3642 (match_operand:SI 2 "" "")]
3648 tramp = force_reg (Pmode, operands[0]);
3649 sfun = force_reg (Pmode, function_symbol (\"__init_trampoline\"));
3650 emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]);
3651 emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]);
3653 emit_insn (gen_initialize_trampoline_compact (tramp, sfun));
3657 (define_insn "initialize_trampoline_compact"
3658 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
3659 (match_operand:SI 1 "register_operand" "r")
3660 (reg:SI R2_REG) (reg:SI R3_REG)]
3663 (clobber (reg:SI PR_REG))]
3666 [(set_attr "type" "sfunc")
3667 (set_attr "needs_delay_slot" "yes")])
3669 (define_insn "movqi_i"
3670 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
3671 (match_operand:QI 1 "general_movsrc_operand" "ri,m,r,t,l,r"))]
3673 && (arith_reg_operand (operands[0], QImode)
3674 || arith_reg_operand (operands[1], QImode))"
3682 [(set_attr "type" "move,load,store,move,move,move")])
3684 (define_insn "*movqi_media"
3685 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
3686 (match_operand:QI 1 "general_movsrc_operand" "r,I16C16,m,rZ"))]
3688 && (arith_reg_operand (operands[0], QImode)
3689 || arith_reg_or_0_operand (operands[1], QImode))"
3695 [(set_attr "type" "arith_media,arith_media,load_media,store_media")])
3697 (define_expand "movqi"
3698 [(set (match_operand:QI 0 "general_operand" "")
3699 (match_operand:QI 1 "general_operand" ""))]
3701 "{ if (prepare_move_operands (operands, QImode)) DONE; }")
3703 (define_expand "reload_inqi"
3704 [(set (match_operand:SI 2 "" "=&r")
3705 (match_operand:QI 1 "inqhi_operand" ""))
3706 (set (match_operand:QI 0 "arith_reg_operand" "=r")
3707 (truncate:QI (match_dup 3)))]
3711 rtx inner = XEXP (operands[1], 0);
3712 int regno = REGNO (inner);
3714 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
3715 operands[1] = gen_rtx_REG (SImode, regno);
3716 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
3719 /* When storing r0, we have to avoid reg+reg addressing. */
3720 (define_insn "movhi_i"
3721 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
3722 (match_operand:HI 1 "general_movsrc_operand" "Q,rI08,m,t,r,l,r,i"))]
3724 && (arith_reg_operand (operands[0], HImode)
3725 || arith_reg_operand (operands[1], HImode))
3726 && (GET_CODE (operands[0]) != MEM
3727 || GET_CODE (XEXP (operands[0], 0)) != PLUS
3728 || GET_CODE (XEXP (XEXP (operands[0], 0), 1)) != REG
3729 || ! refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0))"
3739 [(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
3741 (define_insn "*movhi_media"
3742 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
3743 (match_operand:HI 1 "general_movsrc_operand" "r,I16C16,n,m,rZ"))]
3745 && (arith_reg_operand (operands[0], HImode)
3746 || arith_reg_or_0_operand (operands[1], HImode))"
3753 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")])
3756 [(set (match_operand:HI 0 "register_operand" "")
3757 (match_operand:HI 1 "immediate_operand" ""))]
3758 "TARGET_SHMEDIA && reload_completed
3759 && ! CONST_OK_FOR_I16 (INTVAL (operands[1]))"
3760 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
3762 (define_expand "movhi"
3763 [(set (match_operand:HI 0 "general_movdst_operand" "")
3764 (match_operand:HI 1 "general_movsrc_operand" ""))]
3766 "{ if (prepare_move_operands (operands, HImode)) DONE; }")
3768 (define_expand "reload_inhi"
3769 [(set (match_operand:SI 2 "" "=&r")
3770 (match_operand:HI 1 "inqhi_operand" ""))
3771 (set (match_operand:HI 0 "arith_reg_operand" "=r")
3772 (truncate:HI (match_dup 3)))]
3776 rtx inner = XEXP (operands[1], 0);
3777 int regno = REGNO (inner);
3779 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
3780 operands[1] = gen_rtx_REG (SImode, regno);
3781 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
3784 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
3785 ;; compiled with -m2 -ml -O3 -funroll-loops
3786 (define_insn "*movdi_i"
3787 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
3788 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I08,i,x,r"))]
3790 && (arith_reg_operand (operands[0], DImode)
3791 || arith_reg_operand (operands[1], DImode))"
3792 "* return output_movedouble (insn, operands, DImode);"
3793 [(set_attr "length" "4")
3794 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
3796 ;; If the output is a register and the input is memory or a register, we have
3797 ;; to be careful and see which word needs to be loaded first.
3800 [(set (match_operand:DI 0 "general_movdst_operand" "")
3801 (match_operand:DI 1 "general_movsrc_operand" ""))]
3802 "TARGET_SH1 && reload_completed"
3803 [(set (match_dup 2) (match_dup 3))
3804 (set (match_dup 4) (match_dup 5))]
3809 if ((GET_CODE (operands[0]) == MEM
3810 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
3811 || (GET_CODE (operands[1]) == MEM
3812 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
3815 if (GET_CODE (operands[0]) == REG)
3816 regno = REGNO (operands[0]);
3817 else if (GET_CODE (operands[0]) == SUBREG)
3818 regno = subreg_regno (operands[0]);
3819 else if (GET_CODE (operands[0]) == MEM)
3825 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
3827 operands[2] = operand_subword (operands[0], 0, 0, DImode);
3828 operands[3] = operand_subword (operands[1], 0, 0, DImode);
3829 operands[4] = operand_subword (operands[0], 1, 0, DImode);
3830 operands[5] = operand_subword (operands[1], 1, 0, DImode);
3834 operands[2] = operand_subword (operands[0], 1, 0, DImode);
3835 operands[3] = operand_subword (operands[1], 1, 0, DImode);
3836 operands[4] = operand_subword (operands[0], 0, 0, DImode);
3837 operands[5] = operand_subword (operands[1], 0, 0, DImode);
3840 if (operands[2] == 0 || operands[3] == 0
3841 || operands[4] == 0 || operands[5] == 0)
3845 (define_insn "*movdi_media"
3846 [(set (match_operand:DI 0 "general_movdst_operand"
3847 "=r,r,r,rl,m,f,m,f,r,f,*b,r,b")
3848 (match_operand:DI 1 "general_movsrc_operand"
3849 "r,I16C16,nCpgF,m,rlZ,m,f,rZ,f,f,r,*b,Csy"))]
3851 && (register_operand (operands[0], DImode)
3852 || sh_register_operand (operands[1], DImode))"
3867 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,fload_media,fstore_media,fload_media,dfpconv_media,fmove_media,ptabs_media,gettr_media,pt_media")
3868 (set_attr "length" "4,4,16,4,4,4,4,4,4,4,4,4,*")])
3870 (define_insn "*movdi_media_nofpu"
3871 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,b")
3872 (match_operand:DI 1 "general_movsrc_operand" "r,I16C16,nCpgF,m,rlZ,r,*b,Csy"))]
3874 && (register_operand (operands[0], DImode)
3875 || sh_register_operand (operands[1], DImode))"
3885 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,ptabs_media,gettr_media,pt_media")
3886 (set_attr "length" "4,4,16,4,4,4,4,*")])
3889 [(set (match_operand:DI 0 "arith_reg_operand" "")
3890 (match_operand:DI 1 "immediate_operand" ""))]
3891 "TARGET_SHMEDIA && reload_completed
3892 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
3893 [(set (match_dup 0) (match_dup 1))]
3898 if (TARGET_SHMEDIA64)
3899 insn = emit_insn (gen_movdi_const (operands[0], operands[1]));
3901 insn = emit_insn (gen_movdi_const_32bit (operands[0], operands[1]));
3903 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
3909 (define_expand "movdi_const"
3910 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
3911 (const:DI (sign_extend:DI
3914 (match_operand:DI 1 "immediate_operand" "s")
3917 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
3925 (const_int 32)))))))))
3927 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
3935 (const_int 16)))))))))
3937 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
3943 (match_dup 1))))))))]
3944 "TARGET_SHMEDIA64 && reload_completed
3945 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
3948 sh_mark_label (operands[1], 4);
3951 (define_expand "movdi_const_32bit"
3952 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
3953 (const:DI (sign_extend:DI
3956 (match_operand:DI 1 "immediate_operand" "s")
3959 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
3965 (match_dup 1))))))))]
3966 "TARGET_SHMEDIA32 && reload_completed
3967 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
3970 sh_mark_label (operands[1], 2);
3973 (define_expand "movdi_const_16bit"
3974 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
3975 (const:DI (sign_extend:DI
3977 (match_operand:DI 1 "immediate_operand" "s")))))]
3978 "TARGET_SHMEDIA && flag_pic && reload_completed
3979 && GET_CODE (operands[1]) == SYMBOL_REF"
3983 [(set (match_operand:DI 0 "arith_reg_operand" "")
3984 (match_operand:DI 1 "immediate_operand" ""))]
3985 "TARGET_SHMEDIA && reload_completed
3986 && GET_CODE (operands[1]) == CONST_INT
3987 && ! CONST_OK_FOR_I16 (INTVAL (operands[1]))"
3988 [(set (match_dup 0) (match_dup 2))
3992 unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
3993 unsigned HOST_WIDE_INT low = val;
3994 unsigned HOST_WIDE_INT high = val;
3995 unsigned HOST_WIDE_INT sign;
3996 unsigned HOST_WIDE_INT val2 = val ^ (val-1);
3998 /* Sign-extend the 16 least-significant bits. */
4003 /* Arithmetic shift right the word by 16 bits. */
4006 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
4011 /* If we can't generate the constant with a two-insn movi / shori
4012 sequence, try some other strategies. */
4013 if (! CONST_OK_FOR_I16 (high))
4015 /* Try constant load / left shift. We know VAL != 0. */
4016 val2 = val ^ (val-1);
4019 int trailing_zeroes = exact_log2 ((val2 >> 16) + 1) + 15;
4021 if (CONST_OK_FOR_I16 (val >> trailing_zeroes)
4022 || (! CONST_OK_FOR_I16 (high >> 16)
4023 && CONST_OK_FOR_I16 (val >> (trailing_zeroes + 16))))
4025 val2 = (HOST_WIDE_INT) val >> trailing_zeroes;
4026 operands[1] = gen_ashldi3_media (operands[0], operands[0],
4027 GEN_INT (trailing_zeroes));
4031 /* Try constant load / right shift. */
4032 val2 = (val >> 15) + 1;
4033 if (val2 == (val2 & -val2))
4035 int shift = 49 - exact_log2 (val2);
4037 val2 = trunc_int_for_mode (val << shift, DImode);
4038 if (CONST_OK_FOR_I16 (val2))
4040 operands[1] = gen_lshrdi3_media (operands[0], operands[0],
4046 val2 = val & 0xffff;
4047 if ((val >> 16 & 0xffff) == val2
4048 && (val >> 32 & 0xffff) == val2
4049 && (val >> 48 & 0xffff) == val2)
4051 val2 = (HOST_WIDE_INT) val >> 48;
4052 operands[1] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
4053 operands[1] = gen_mperm_w0 (operands[1], operands[1]);
4056 /* Try movi / mshflo.l */
4057 val2 = (HOST_WIDE_INT) val >> 32;
4058 if (val2 == ((unsigned HOST_WIDE_INT)
4059 trunc_int_for_mode (val, SImode)))
4061 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
4065 /* Try movi / mshflo.l w/ r63. */
4066 val2 = val + ((HOST_WIDE_INT) -1 << 32);
4067 if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
4069 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
4075 operands[1] = gen_shori_media (operands[0], operands[0], GEN_INT (low));
4078 operands[2] = GEN_INT (val2);
4082 [(set (match_operand:DI 0 "arith_reg_operand" "")
4083 (match_operand:DI 1 "immediate_operand" ""))]
4084 "TARGET_SHMEDIA && reload_completed
4085 && GET_CODE (operands[1]) == CONST_DOUBLE"
4086 [(set (match_dup 0) (match_dup 2))
4088 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
4089 (zero_extend:DI (truncate:HI (match_dup 1)))))]
4092 unsigned HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
4093 unsigned HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
4094 unsigned HOST_WIDE_INT val = low;
4095 unsigned HOST_WIDE_INT sign;
4097 /* Sign-extend the 16 least-significant bits. */
4101 operands[1] = GEN_INT (val);
4103 /* Arithmetic shift right the double-word by 16 bits. */
4105 low |= (high & 0xffff) << (HOST_BITS_PER_WIDE_INT - 16);
4108 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
4112 /* This will only be true if high is a sign-extension of low, i.e.,
4113 it must be either 0 or (unsigned)-1, and be zero iff the
4114 most-significant bit of low is set. */
4115 if (high + (low >> (HOST_BITS_PER_WIDE_INT - 1)) == 0)
4116 operands[2] = GEN_INT (low);
4118 operands[2] = immed_double_const (low, high, DImode);
4121 (define_insn "shori_media"
4122 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
4123 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0,0")
4127 (match_operand:DI 2 "immediate_operand" "I16C16,nF")))))]
4132 [(set_attr "type" "arith_media,*")])
4134 (define_expand "movdi"
4135 [(set (match_operand:DI 0 "general_movdst_operand" "")
4136 (match_operand:DI 1 "general_movsrc_operand" ""))]
4138 "{ if (prepare_move_operands (operands, DImode)) DONE; }")
4140 (define_insn "movdf_media"
4141 [(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
4142 (match_operand:DF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
4144 && (register_operand (operands[0], DFmode)
4145 || sh_register_operand (operands[1], DFmode))"
4156 [(set_attr "type" "fmove_media,fload_media,dfpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")])
4158 (define_insn "movdf_media_nofpu"
4159 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
4160 (match_operand:DF 1 "general_movsrc_operand" "r,F,m,rZ"))]
4162 && (register_operand (operands[0], DFmode)
4163 || sh_register_operand (operands[1], DFmode))"
4169 [(set_attr "type" "arith_media,*,load_media,store_media")])
4172 [(set (match_operand:DF 0 "arith_reg_operand" "")
4173 (match_operand:DF 1 "immediate_operand" ""))]
4174 "TARGET_SHMEDIA && reload_completed"
4175 [(set (match_dup 3) (match_dup 2))]
4178 int endian = WORDS_BIG_ENDIAN ? 1 : 0;
4180 REAL_VALUE_TYPE value;
4182 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
4183 REAL_VALUE_TO_TARGET_DOUBLE (value, values);
4185 if (HOST_BITS_PER_WIDE_INT >= 64)
4186 operands[2] = immed_double_const ((unsigned long) values[endian]
4187 | ((HOST_WIDE_INT) values[1 - endian]
4189 else if (HOST_BITS_PER_WIDE_INT == 32)
4190 operands[2] = immed_double_const (values[endian], values[1 - endian],
4195 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
4198 ;; ??? This should be a define expand.
4200 (define_insn "movdf_k"
4201 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
4202 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
4204 && (! (TARGET_SH4 || TARGET_SH2A_DOUBLE) || reload_completed
4205 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
4206 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
4207 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
4208 && (arith_reg_operand (operands[0], DFmode)
4209 || arith_reg_operand (operands[1], DFmode))"
4210 "* return output_movedouble (insn, operands, DFmode);"
4211 [(set_attr "length" "4")
4212 (set_attr "type" "move,pcload,load,store")])
4214 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
4215 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
4216 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
4217 ;; the d/m/c/X alternative, which is split later into single-precision
4218 ;; instructions. And when not optimizing, no splits are done before fixing
4219 ;; up pcloads, so we need usable length information for that.
4220 (define_insn "movdf_i4"
4221 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
4222 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
4223 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
4224 (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
4225 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
4226 && (arith_reg_operand (operands[0], DFmode)
4227 || arith_reg_operand (operands[1], DFmode))"
4239 [(set_attr_alternative "length"
4240 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
4242 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
4243 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
4244 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
4246 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
4247 ;; We can't use 4-byte push/pop on SHcompact, so we have to
4248 ;; increment or decrement r15 explicitly.
4250 (ne (symbol_ref "TARGET_SHCOMPACT") (const_int 0))
4251 (const_int 10) (const_int 8))
4253 (ne (symbol_ref "TARGET_SHCOMPACT") (const_int 0))
4254 (const_int 10) (const_int 8))])
4255 (set_attr "type" "fmove,move,pcfload,fload,store,pcload,load,store,load,fload")
4256 (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*")
4257 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
4258 (const_string "double")
4259 (const_string "none")))])
4261 ;; Moving DFmode between fp/general registers through memory
4262 ;; (the top of the stack) is faster than moving through fpul even for
4263 ;; little endian. Because the type of an instruction is important for its
4264 ;; scheduling, it is beneficial to split these operations, rather than
4265 ;; emitting them in one single chunk, even if this will expose a stack
4266 ;; use that will prevent scheduling of other stack accesses beyond this
4269 [(set (match_operand:DF 0 "register_operand" "")
4270 (match_operand:DF 1 "register_operand" ""))
4271 (use (match_operand:PSI 2 "fpscr_operand" ""))
4272 (clobber (match_scratch:SI 3 "=X"))]
4273 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed
4274 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
4280 if (TARGET_SH5 && true_regnum (operands[1]) < 16)
4282 emit_move_insn (stack_pointer_rtx,
4283 plus_constant (stack_pointer_rtx, -8));
4284 tos = gen_rtx_MEM (DFmode, stack_pointer_rtx);
4287 tos = gen_rtx_MEM (DFmode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
4288 insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
4289 if (! (TARGET_SH5 && true_regnum (operands[1]) < 16))
4290 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, NULL_RTX);
4291 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
4292 tos = gen_rtx_MEM (DFmode, stack_pointer_rtx);
4294 tos = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
4295 insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
4296 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
4297 emit_move_insn (stack_pointer_rtx, plus_constant (stack_pointer_rtx, 8));
4299 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, NULL_RTX);
4303 ;; local-alloc sometimes allocates scratch registers even when not required,
4304 ;; so we must be prepared to handle these.
4306 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
4308 [(set (match_operand:DF 0 "general_movdst_operand" "")
4309 (match_operand:DF 1 "general_movsrc_operand" ""))
4310 (use (match_operand:PSI 2 "fpscr_operand" ""))
4311 (clobber (match_scratch:SI 3 ""))]
4312 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
4314 && true_regnum (operands[0]) < 16
4315 && true_regnum (operands[1]) < 16"
4316 [(set (match_dup 0) (match_dup 1))]
4319 /* If this was a reg <-> mem operation with base + index reg addressing,
4320 we have to handle this in a special way. */
4321 rtx mem = operands[0];
4323 if (! memory_operand (mem, DFmode))
4328 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
4329 mem = SUBREG_REG (mem);
4330 if (GET_CODE (mem) == MEM)
4332 rtx addr = XEXP (mem, 0);
4333 if (GET_CODE (addr) == PLUS
4334 && GET_CODE (XEXP (addr, 0)) == REG
4335 && GET_CODE (XEXP (addr, 1)) == REG)
4338 rtx reg0 = gen_rtx_REG (Pmode, 0);
4339 rtx regop = operands[store_p], word0 ,word1;
4341 if (GET_CODE (regop) == SUBREG)
4342 alter_subreg (®op);
4343 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
4347 mem = copy_rtx (mem);
4348 PUT_MODE (mem, SImode);
4349 word0 = gen_rtx_SUBREG (SImode, regop, 0);
4350 alter_subreg (&word0);
4351 word1 = gen_rtx_SUBREG (SImode, regop, 4);
4352 alter_subreg (&word1);
4353 if (store_p || ! refers_to_regno_p (REGNO (word0),
4354 REGNO (word0) + 1, addr, 0))
4357 ? gen_movsi_ie (mem, word0)
4358 : gen_movsi_ie (word0, mem));
4359 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
4360 mem = copy_rtx (mem);
4362 ? gen_movsi_ie (mem, word1)
4363 : gen_movsi_ie (word1, mem));
4364 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
4368 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
4369 emit_insn (gen_movsi_ie (word1, mem));
4370 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
4371 mem = copy_rtx (mem);
4372 emit_insn (gen_movsi_ie (word0, mem));
4379 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
4381 [(set (match_operand:DF 0 "register_operand" "")
4382 (match_operand:DF 1 "memory_operand" ""))
4383 (use (match_operand:PSI 2 "fpscr_operand" ""))
4384 (clobber (reg:SI R0_REG))]
4385 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed"
4386 [(parallel [(set (match_dup 0) (match_dup 1))
4388 (clobber (scratch:SI))])]
4391 (define_expand "reload_indf"
4392 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
4393 (match_operand:DF 1 "immediate_operand" "FQ"))
4394 (use (reg:PSI FPSCR_REG))
4395 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
4399 (define_expand "reload_outdf"
4400 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
4401 (match_operand:DF 1 "register_operand" "af,r"))
4402 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
4406 ;; Simplify no-op moves.
4408 [(set (match_operand:SF 0 "register_operand" "")
4409 (match_operand:SF 1 "register_operand" ""))
4410 (use (match_operand:PSI 2 "fpscr_operand" ""))
4411 (clobber (match_scratch:SI 3 ""))]
4412 "TARGET_SH2E && reload_completed
4413 && true_regnum (operands[0]) == true_regnum (operands[1])"
4414 [(set (match_dup 0) (match_dup 0))]
4417 ;; fmovd substitute post-reload splits
4419 [(set (match_operand:DF 0 "register_operand" "")
4420 (match_operand:DF 1 "register_operand" ""))
4421 (use (match_operand:PSI 2 "fpscr_operand" ""))
4422 (clobber (match_scratch:SI 3 ""))]
4423 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
4424 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
4425 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
4429 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
4430 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst),
4431 gen_rtx_REG (SFmode, src), operands[2]));
4432 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1),
4433 gen_rtx_REG (SFmode, src + 1), operands[2]));
4438 [(set (match_operand:DF 0 "register_operand" "")
4439 (mem:DF (match_operand:SI 1 "register_operand" "")))
4440 (use (match_operand:PSI 2 "fpscr_operand" ""))
4441 (clobber (match_scratch:SI 3 ""))]
4442 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
4443 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
4444 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
4448 int regno = true_regnum (operands[0]);
4450 rtx mem2 = gen_rtx_MEM (SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
4452 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
4453 regno + !! TARGET_LITTLE_ENDIAN),
4454 mem2, operands[2]));
4455 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, operands[1], NULL_RTX);
4456 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
4457 regno + ! TARGET_LITTLE_ENDIAN),
4458 gen_rtx_MEM (SFmode, operands[1]),
4464 [(set (match_operand:DF 0 "register_operand" "")
4465 (match_operand:DF 1 "memory_operand" ""))
4466 (use (match_operand:PSI 2 "fpscr_operand" ""))
4467 (clobber (match_scratch:SI 3 ""))]
4468 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
4469 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
4473 int regno = true_regnum (operands[0]);
4474 rtx addr, insn, adjust = NULL_RTX;
4475 rtx mem2 = copy_rtx (operands[1]);
4476 rtx reg0 = gen_rtx_REG (SFmode, regno + !! TARGET_LITTLE_ENDIAN);
4477 rtx reg1 = gen_rtx_REG (SFmode, regno + ! TARGET_LITTLE_ENDIAN);
4479 PUT_MODE (mem2, SFmode);
4480 operands[1] = copy_rtx (mem2);
4481 addr = XEXP (mem2, 0);
4482 if (GET_CODE (addr) != POST_INC)
4484 /* If we have to modify the stack pointer, the value that we have
4485 read with post-increment might be modified by an interrupt,
4486 so write it back. */
4487 if (REGNO (addr) == STACK_POINTER_REGNUM)
4488 adjust = gen_push_e (reg0);
4490 adjust = gen_addsi3 (addr, addr, GEN_INT (-4));
4491 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
4493 addr = XEXP (addr, 0);
4494 insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
4495 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
4496 insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
4500 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
4505 [(set (match_operand:DF 0 "memory_operand" "")
4506 (match_operand:DF 1 "register_operand" ""))
4507 (use (match_operand:PSI 2 "fpscr_operand" ""))
4508 (clobber (match_scratch:SI 3 ""))]
4509 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
4510 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
4514 int regno = true_regnum (operands[1]);
4515 rtx insn, addr, adjust = NULL_RTX;
4517 operands[0] = copy_rtx (operands[0]);
4518 PUT_MODE (operands[0], SFmode);
4519 insn = emit_insn (gen_movsf_ie (operands[0],
4520 gen_rtx_REG (SFmode,
4521 regno + ! TARGET_LITTLE_ENDIAN),
4523 operands[0] = copy_rtx (operands[0]);
4524 addr = XEXP (operands[0], 0);
4525 if (GET_CODE (addr) != PRE_DEC)
4527 adjust = gen_addsi3 (addr, addr, GEN_INT (4));
4528 emit_insn_before (adjust, insn);
4529 XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
4531 addr = XEXP (addr, 0);
4533 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
4534 insn = emit_insn (gen_movsf_ie (operands[0],
4535 gen_rtx_REG (SFmode,
4536 regno + !! TARGET_LITTLE_ENDIAN),
4538 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
4542 ;; If the output is a register and the input is memory or a register, we have
4543 ;; to be careful and see which word needs to be loaded first.
4546 [(set (match_operand:DF 0 "general_movdst_operand" "")
4547 (match_operand:DF 1 "general_movsrc_operand" ""))]
4548 "TARGET_SH1 && reload_completed"
4549 [(set (match_dup 2) (match_dup 3))
4550 (set (match_dup 4) (match_dup 5))]
4555 if ((GET_CODE (operands[0]) == MEM
4556 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4557 || (GET_CODE (operands[1]) == MEM
4558 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
4561 if (GET_CODE (operands[0]) == REG)
4562 regno = REGNO (operands[0]);
4563 else if (GET_CODE (operands[0]) == SUBREG)
4564 regno = subreg_regno (operands[0]);
4565 else if (GET_CODE (operands[0]) == MEM)
4571 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
4573 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
4574 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
4575 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
4576 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
4580 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
4581 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
4582 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
4583 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
4586 if (operands[2] == 0 || operands[3] == 0
4587 || operands[4] == 0 || operands[5] == 0)
4591 ;; If a base address generated by LEGITIMIZE_ADDRESS for SImode is
4592 ;; used only once, let combine add in the index again.
4595 [(set (match_operand:SI 0 "register_operand" "")
4596 (match_operand:SI 1 "" ""))
4597 (clobber (match_operand 2 "register_operand" ""))]
4598 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
4599 [(use (reg:SI R0_REG))]
4602 rtx addr, reg, const_int;
4604 if (GET_CODE (operands[1]) != MEM)
4606 addr = XEXP (operands[1], 0);
4607 if (GET_CODE (addr) != PLUS)
4609 reg = XEXP (addr, 0);
4610 const_int = XEXP (addr, 1);
4611 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
4612 && GET_CODE (const_int) == CONST_INT))
4614 emit_move_insn (operands[2], const_int);
4615 emit_move_insn (operands[0],
4616 change_address (operands[1], VOIDmode,
4617 gen_rtx_PLUS (SImode, reg, operands[2])));
4622 [(set (match_operand:SI 1 "" "")
4623 (match_operand:SI 0 "register_operand" ""))
4624 (clobber (match_operand 2 "register_operand" ""))]
4625 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
4626 [(use (reg:SI R0_REG))]
4629 rtx addr, reg, const_int;
4631 if (GET_CODE (operands[1]) != MEM)
4633 addr = XEXP (operands[1], 0);
4634 if (GET_CODE (addr) != PLUS)
4636 reg = XEXP (addr, 0);
4637 const_int = XEXP (addr, 1);
4638 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
4639 && GET_CODE (const_int) == CONST_INT))
4641 emit_move_insn (operands[2], const_int);
4642 emit_move_insn (change_address (operands[1], VOIDmode,
4643 gen_rtx_PLUS (SImode, reg, operands[2])),
4648 (define_expand "movdf"
4649 [(set (match_operand:DF 0 "general_movdst_operand" "")
4650 (match_operand:DF 1 "general_movsrc_operand" ""))]
4654 if (prepare_move_operands (operands, DFmode)) DONE;
4657 if (TARGET_SHMEDIA_FPU)
4658 emit_insn (gen_movdf_media (operands[0], operands[1]));
4660 emit_insn (gen_movdf_media_nofpu (operands[0], operands[1]));
4663 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
4665 emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4670 ;;This is incompatible with the way gcc uses subregs.
4671 ;;(define_insn "movv2sf_i"
4672 ;; [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,m")
4673 ;; (match_operand:V2SF 1 "nonimmediate_operand" "f,m,f"))]
4674 ;; "TARGET_SHMEDIA_FPU
4675 ;; && (fp_arith_reg_operand (operands[0], V2SFmode)
4676 ;; || fp_arith_reg_operand (operands[1], V2SFmode))"
4680 ;; fst%M0.p %m0, %1"
4681 ;; [(set_attr "type" "*,fload_media,fstore_media")])
4683 (define_insn_and_split "movv2sf_i"
4684 [(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
4685 (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
4686 "TARGET_SHMEDIA_FPU"
4688 "TARGET_SHMEDIA_FPU && reload_completed"
4689 [(set (match_dup 0) (match_dup 1))]
4692 operands[0] = simplify_gen_subreg (DFmode, operands[0], V2SFmode, 0);
4693 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2SFmode, 0);
4696 (define_expand "movv2sf"
4697 [(set (match_operand:V2SF 0 "general_movdst_operand" "")
4698 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
4699 "TARGET_SHMEDIA_FPU"
4702 if (prepare_move_operands (operands, V2SFmode))
4706 (define_expand "addv2sf3"
4707 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
4708 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
4709 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
4710 "TARGET_SHMEDIA_FPU"
4713 sh_expand_binop_v2sf (PLUS, operands[0], operands[1], operands[2]);
4717 (define_expand "subv2sf3"
4718 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
4719 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
4720 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
4721 "TARGET_SHMEDIA_FPU"
4724 sh_expand_binop_v2sf (MINUS, operands[0], operands[1], operands[2]);
4728 (define_expand "mulv2sf3"
4729 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
4730 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
4731 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
4732 "TARGET_SHMEDIA_FPU"
4735 sh_expand_binop_v2sf (MULT, operands[0], operands[1], operands[2]);
4739 (define_expand "divv2sf3"
4740 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
4741 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
4742 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
4743 "TARGET_SHMEDIA_FPU"
4746 sh_expand_binop_v2sf (DIV, operands[0], operands[1], operands[2]);
4750 (define_insn_and_split "*movv4sf_i"
4751 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=f,f,m")
4752 (match_operand:V4SF 1 "general_operand" "fZ,m,fZ"))]
4753 "TARGET_SHMEDIA_FPU"
4755 "&& reload_completed"
4761 for (i = 0; i < 4/2; i++)
4765 if (GET_CODE (operands[0]) == MEM)
4766 x = gen_rtx_MEM (V2SFmode,
4767 plus_constant (XEXP (operands[0], 0),
4768 i * GET_MODE_SIZE (V2SFmode)));
4770 x = simplify_gen_subreg (V2SFmode, operands[0], V4SFmode, i * 8);
4772 if (GET_CODE (operands[1]) == MEM)
4773 y = gen_rtx_MEM (V2SFmode,
4774 plus_constant (XEXP (operands[1], 0),
4775 i * GET_MODE_SIZE (V2SFmode)));
4777 y = simplify_gen_subreg (V2SFmode, operands[1], V4SFmode, i * 8);
4779 emit_insn (gen_movv2sf_i (x, y));
4784 [(set_attr "length" "8")])
4786 (define_expand "movv4sf"
4787 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
4788 (match_operand:V4SF 1 "general_operand" ""))]
4789 "TARGET_SHMEDIA_FPU"
4792 if (prepare_move_operands (operands, V4SFmode))
4796 (define_insn_and_split "*movv16sf_i"
4797 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
4798 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
4799 "TARGET_SHMEDIA_FPU"
4801 "&& reload_completed"
4807 for (i = 0; i < 16/2; i++)
4811 if (GET_CODE (operands[0]) == MEM)
4812 x = gen_rtx_MEM (V2SFmode,
4813 plus_constant (XEXP (operands[0], 0),
4814 i * GET_MODE_SIZE (V2SFmode)));
4817 x = gen_rtx_SUBREG (V2SFmode, operands[0], i * 8);
4821 if (GET_CODE (operands[1]) == MEM)
4822 y = gen_rtx_MEM (V2SFmode,
4823 plus_constant (XEXP (operands[1], 0),
4824 i * GET_MODE_SIZE (V2SFmode)));
4827 y = gen_rtx_SUBREG (V2SFmode, operands[1], i * 8);
4831 emit_insn (gen_movv2sf_i (x, y));
4836 [(set_attr "length" "32")])
4838 (define_expand "movv16sf"
4839 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
4840 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
4841 "TARGET_SHMEDIA_FPU"
4844 if (prepare_move_operands (operands, V16SFmode))
4848 (define_insn "movsf_media"
4849 [(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
4850 (match_operand:SF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
4852 && (register_operand (operands[0], SFmode)
4853 || sh_register_operand (operands[1], SFmode))"
4864 [(set_attr "type" "fmove_media,fload_media,fpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")])
4866 (define_insn "movsf_media_nofpu"
4867 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m")
4868 (match_operand:SF 1 "general_movsrc_operand" "r,F,m,rZ"))]
4870 && (register_operand (operands[0], SFmode)
4871 || sh_register_operand (operands[1], SFmode))"
4877 [(set_attr "type" "arith_media,*,load_media,store_media")])
4880 [(set (match_operand:SF 0 "arith_reg_operand" "")
4881 (match_operand:SF 1 "immediate_operand" ""))]
4882 "TARGET_SHMEDIA && reload_completed
4883 && ! FP_REGISTER_P (true_regnum (operands[0]))"
4884 [(set (match_dup 3) (match_dup 2))]
4888 REAL_VALUE_TYPE value;
4890 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
4891 REAL_VALUE_TO_TARGET_SINGLE (value, values);
4892 operands[2] = GEN_INT (values);
4894 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
4897 (define_insn "movsf_i"
4898 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
4899 (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
4902 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
4903 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
4904 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
4905 && (arith_reg_operand (operands[0], SFmode)
4906 || arith_reg_operand (operands[1], SFmode))"
4915 [(set_attr "type" "move,move,pcload,load,store,move,move")])
4917 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
4918 ;; update_flow_info would not know where to put REG_EQUAL notes
4919 ;; when the destination changes mode.
4920 (define_insn "movsf_ie"
4921 [(set (match_operand:SF 0 "general_movdst_operand"
4922 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,<,y,y")
4923 (match_operand:SF 1 "general_movsrc_operand"
4924 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
4925 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
4926 (clobber (match_scratch:SI 3 "=X,X,Bsc,Bsc,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
4929 && (arith_reg_operand (operands[0], SFmode)
4930 || arith_reg_operand (operands[1], SFmode)
4931 || arith_reg_operand (operands[3], SImode)
4932 || (fpul_operand (operands[0], SFmode)
4933 && memory_operand (operands[1], SFmode)
4934 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
4935 || (fpul_operand (operands[1], SFmode)
4936 && memory_operand (operands[0], SFmode)
4937 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))"
4957 ! move optimized away"
4958 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,store,pcload,load,store,fmove,fmove,load,*,fpul_gp,gp_fpul,store,load,nil")
4959 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
4960 (set_attr "length" "*,*,*,*,4,4,4,*,*,*,2,2,2,4,2,2,2,2,0")
4961 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
4962 (const_string "single")
4963 (const_string "none")))])
4966 [(set (match_operand:SF 0 "register_operand" "")
4967 (match_operand:SF 1 "register_operand" ""))
4968 (use (match_operand:PSI 2 "fpscr_operand" ""))
4969 (clobber (reg:SI FPUL_REG))]
4971 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
4973 (clobber (scratch:SI))])
4974 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
4976 (clobber (scratch:SI))])]
4979 (define_expand "movsf"
4980 [(set (match_operand:SF 0 "general_movdst_operand" "")
4981 (match_operand:SF 1 "general_movsrc_operand" ""))]
4985 if (prepare_move_operands (operands, SFmode))
4989 if (TARGET_SHMEDIA_FPU)
4990 emit_insn (gen_movsf_media (operands[0], operands[1]));
4992 emit_insn (gen_movsf_media_nofpu (operands[0], operands[1]));
4997 emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
5002 (define_insn "mov_nop"
5003 [(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
5006 [(set_attr "length" "0")
5007 (set_attr "type" "nil")])
5009 (define_expand "reload_insf"
5010 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
5011 (match_operand:SF 1 "immediate_operand" "FQ"))
5012 (use (reg:PSI FPSCR_REG))
5013 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
5017 (define_expand "reload_insi"
5018 [(parallel [(set (match_operand:SF 0 "register_operand" "=y")
5019 (match_operand:SF 1 "immediate_operand" "FQ"))
5020 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
5024 (define_insn "*movsi_y"
5025 [(set (match_operand:SI 0 "register_operand" "=y,y")
5026 (match_operand:SI 1 "immediate_operand" "Qi,I08"))
5027 (clobber (match_scratch:SI 2 "=&z,r"))]
5029 && (reload_in_progress || reload_completed)"
5031 [(set_attr "length" "4")
5032 (set_attr "type" "pcload,move")])
5035 [(set (match_operand:SI 0 "register_operand" "")
5036 (match_operand:SI 1 "immediate_operand" ""))
5037 (clobber (match_operand:SI 2 "register_operand" ""))]
5039 [(set (match_dup 2) (match_dup 1))
5040 (set (match_dup 0) (match_dup 2))]
5044 [(set (match_operand:SI 0 "register_operand" "")
5045 (match_operand:SI 1 "memory_operand" ""))
5046 (clobber (reg:SI R0_REG))]
5048 [(set (match_dup 0) (match_dup 1))]
5051 ;; ------------------------------------------------------------------------
5052 ;; Define the real conditional branch instructions.
5053 ;; ------------------------------------------------------------------------
5055 (define_insn "branch_true"
5056 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
5057 (label_ref (match_operand 0 "" ""))
5060 "* return output_branch (1, insn, operands);"
5061 [(set_attr "type" "cbranch")])
5063 (define_insn "branch_false"
5064 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
5065 (label_ref (match_operand 0 "" ""))
5068 "* return output_branch (0, insn, operands);"
5069 [(set_attr "type" "cbranch")])
5071 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
5072 ;; which destination is too far away.
5073 ;; The const_int_operand is distinct for each branch target; it avoids
5074 ;; unwanted matches with redundant_insn.
5075 (define_insn "block_branch_redirect"
5076 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
5079 [(set_attr "length" "0")])
5081 ;; This one has the additional purpose to record a possible scratch register
5082 ;; for the following branch.
5083 ;; ??? Unfortunately, just setting the scratch register is not good enough,
5084 ;; because the insn then might be deemed dead and deleted. And we can't
5085 ;; make the use in the jump insn explicit because that would disable
5086 ;; delay slot scheduling from the target.
5087 (define_insn "indirect_jump_scratch"
5088 [(set (match_operand:SI 0 "register_operand" "=r")
5089 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
5090 (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
5093 [(set_attr "length" "0")])
5095 ;; This one is used to preemt an insn from beyond the bra / braf / jmp
5096 ;; being pulled into the delay slot of a condbranch that has been made to
5097 ;; jump around the unconditional jump because it was out of range.
5098 (define_insn "stuff_delay_slot"
5100 (unspec [(match_operand 0 "const_int_operand" "") (pc)] UNSPEC_BBR))
5101 (set (reg:SI T_REG) (match_operand 1 "const_int_operand" ""))]
5104 [(set_attr "length" "0")
5105 (set_attr "cond_delay_slot" "yes")])
5107 ;; Conditional branch insns
5109 (define_expand "beq_media"
5111 (if_then_else (eq (match_operand:DI 1 "arith_reg_operand" "r,r")
5112 (match_operand:DI 2 "arith_operand" "r,I06"))
5113 (label_ref:DI (match_operand 0 "" ""))
5118 (define_insn "*beq_media_i"
5120 (if_then_else (match_operator 3 "equality_comparison_operator"
5121 [(match_operand:DI 1 "arith_reg_operand" "r,r")
5122 (match_operand:DI 2 "arith_operand" "r,I06")])
5123 (match_operand:DI 0 "target_operand" "b,b")
5129 [(set_attr "type" "cbranch_media")])
5131 (define_expand "bne_media"
5133 (if_then_else (ne (match_operand:DI 1 "arith_reg_operand" "r,r")
5134 (match_operand:DI 2 "arith_operand" "r,I06"))
5135 (label_ref:DI (match_operand 0 "" ""))
5140 (define_expand "bgt_media"
5142 (if_then_else (gt (match_operand:DI 1 "arith_reg_or_0_operand" "r")
5143 (match_operand:DI 2 "arith_reg_or_0_operand" "r"))
5144 (label_ref:DI (match_operand 0 "" ""))
5149 (define_expand "bge_media"
5151 (if_then_else (ge (match_operand:DI 1 "arith_reg_or_0_operand" "r")
5152 (match_operand:DI 2 "arith_reg_or_0_operand" "r"))
5153 (label_ref:DI (match_operand 0 "" ""))
5158 (define_expand "bgtu_media"
5160 (if_then_else (gtu (match_operand:DI 1 "arith_reg_or_0_operand" "r")
5161 (match_operand:DI 2 "arith_reg_or_0_operand" "r"))
5162 (label_ref:DI (match_operand 0 "" ""))
5167 (define_expand "bgeu_media"
5169 (if_then_else (geu (match_operand:DI 1 "arith_reg_or_0_operand" "r")
5170 (match_operand:DI 2 "arith_reg_or_0_operand" "r"))
5171 (label_ref:DI (match_operand 0 "" ""))
5176 (define_insn "*bgt_media_i"
5178 (if_then_else (match_operator 3 "greater_comparison_operator"
5179 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
5180 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
5181 (match_operand:DI 0 "target_operand" "b")
5184 "b%o3%' %N1, %N2, %0"
5185 [(set_attr "type" "cbranch_media")])
5187 ;; These are only needed to make invert_jump() happy.
5188 (define_insn "*blt_media_i"
5190 (if_then_else (match_operator 3 "less_comparison_operator"
5191 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
5192 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
5193 (match_operand:DI 0 "target_operand" "b")
5196 "b%o3%' %N2, %N1, %0"
5197 [(set_attr "type" "cbranch_media")])
5199 (define_expand "beq"
5201 (if_then_else (ne (reg:SI T_REG) (const_int 0))
5202 (label_ref (match_operand 0 "" ""))
5209 if (GET_MODE (sh_compare_op0) != DImode)
5211 rtx tmp = gen_reg_rtx (DImode);
5213 emit_insn (gen_seq (tmp));
5214 emit_jump_insn (gen_bne_media (operands[0], tmp, const0_rtx));
5218 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5219 emit_jump_insn (gen_beq_media (operands[0],
5220 sh_compare_op0, sh_compare_op1));
5224 from_compare (operands, EQ);
5227 (define_expand "bne"
5229 (if_then_else (eq (reg:SI T_REG) (const_int 0))
5230 (label_ref (match_operand 0 "" ""))
5237 if (GET_MODE (sh_compare_op0) != DImode)
5239 rtx tmp = gen_reg_rtx (DImode);
5241 emit_insn (gen_seq (tmp));
5242 emit_jump_insn (gen_beq_media (operands[0], tmp, const0_rtx));
5246 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5247 emit_jump_insn (gen_bne_media (operands[0],
5248 sh_compare_op0, sh_compare_op1));
5252 from_compare (operands, EQ);
5255 (define_expand "bgt"
5257 (if_then_else (ne (reg:SI T_REG) (const_int 0))
5258 (label_ref (match_operand 0 "" ""))
5265 if (GET_MODE (sh_compare_op0) != DImode)
5267 rtx tmp = gen_reg_rtx (DImode);
5269 emit_insn (gen_sgt (tmp));
5270 emit_jump_insn (gen_bne_media (operands[0], tmp, const0_rtx));
5274 if (sh_compare_op0 != const0_rtx)
5275 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5276 if (sh_compare_op1 != const0_rtx)
5277 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5278 emit_jump_insn (gen_bgt_media (operands[0],
5279 sh_compare_op0, sh_compare_op1));
5283 from_compare (operands, GT);
5286 (define_expand "blt"
5288 (if_then_else (eq (reg:SI T_REG) (const_int 0))
5289 (label_ref (match_operand 0 "" ""))
5296 if (GET_MODE (sh_compare_op0) != DImode)
5298 rtx tmp = gen_reg_rtx (DImode);
5300 emit_insn (gen_slt (tmp));
5301 emit_jump_insn (gen_bne_media (operands[0], tmp, const0_rtx));
5305 if (sh_compare_op0 != const0_rtx)
5306 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5307 if (sh_compare_op1 != const0_rtx)
5308 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5309 emit_jump_insn (gen_bgt_media (operands[0],
5310 sh_compare_op1, sh_compare_op0));
5314 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
5316 rtx tmp = sh_compare_op0;
5317 sh_compare_op0 = sh_compare_op1;
5318 sh_compare_op1 = tmp;
5319 emit_insn (gen_bgt (operands[0]));
5322 from_compare (operands, GE);
5325 (define_expand "ble"
5327 (if_then_else (eq (reg:SI T_REG) (const_int 0))
5328 (label_ref (match_operand 0 "" ""))
5335 if (GET_MODE (sh_compare_op0) != DImode)
5337 rtx tmp = gen_reg_rtx (DImode);
5339 emit_insn (gen_sle (tmp));
5340 emit_jump_insn (gen_bne_media (operands[0], tmp, const0_rtx));
5344 if (sh_compare_op0 != const0_rtx)
5345 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5346 if (sh_compare_op1 != const0_rtx)
5347 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5348 emit_jump_insn (gen_bge_media (operands[0],
5349 sh_compare_op1, sh_compare_op0));
5355 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
5357 rtx tmp = sh_compare_op0;
5358 sh_compare_op0 = sh_compare_op1;
5359 sh_compare_op1 = tmp;
5360 emit_insn (gen_bge (operands[0]));
5363 from_compare (operands, GT);
5366 (define_expand "bge"
5368 (if_then_else (ne (reg:SI T_REG) (const_int 0))
5369 (label_ref (match_operand 0 "" ""))
5376 if (GET_MODE (sh_compare_op0) != DImode)
5378 rtx tmp = gen_reg_rtx (DImode);
5380 emit_insn (gen_sge (tmp));
5381 emit_jump_insn (gen_bne_media (operands[0], tmp, const0_rtx));
5385 if (sh_compare_op0 != const0_rtx)
5386 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5387 if (sh_compare_op1 != const0_rtx)
5388 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5389 emit_jump_insn (gen_bge_media (operands[0],
5390 sh_compare_op0, sh_compare_op1));
5396 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
5398 rtx tmp = sh_compare_op0;
5399 sh_compare_op0 = sh_compare_op1;
5400 sh_compare_op1 = tmp;
5401 emit_insn (gen_ble (operands[0]));
5404 from_compare (operands, GE);
5407 (define_expand "bgtu"
5409 (if_then_else (ne (reg:SI T_REG) (const_int 0))
5410 (label_ref (match_operand 0 "" ""))
5417 if (sh_compare_op0 != const0_rtx)
5418 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5419 if (sh_compare_op1 != const0_rtx)
5420 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5421 emit_jump_insn (gen_bgtu_media (operands[0],
5422 sh_compare_op0, sh_compare_op1));
5426 from_compare (operands, GTU);
5429 (define_expand "bltu"
5431 (if_then_else (eq (reg:SI T_REG) (const_int 0))
5432 (label_ref (match_operand 0 "" ""))
5439 if (sh_compare_op0 != const0_rtx)
5440 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5441 if (sh_compare_op1 != const0_rtx)
5442 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5443 emit_jump_insn (gen_bgtu_media (operands[0],
5444 sh_compare_op1, sh_compare_op0));
5448 from_compare (operands, GEU);
5451 (define_expand "bgeu"
5453 (if_then_else (ne (reg:SI T_REG) (const_int 0))
5454 (label_ref (match_operand 0 "" ""))
5461 if (sh_compare_op0 != const0_rtx)
5462 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5463 if (sh_compare_op1 != const0_rtx)
5464 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5465 emit_jump_insn (gen_bgeu_media (operands[0],
5466 sh_compare_op0, sh_compare_op1));
5470 from_compare (operands, GEU);
5473 (define_expand "bleu"
5475 (if_then_else (eq (reg:SI T_REG) (const_int 0))
5476 (label_ref (match_operand 0 "" ""))
5483 if (sh_compare_op0 != const0_rtx)
5484 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5485 if (sh_compare_op1 != const0_rtx)
5486 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5487 emit_jump_insn (gen_bgeu_media (operands[0],
5488 sh_compare_op1, sh_compare_op0));
5492 from_compare (operands, GTU);
5495 (define_expand "bunordered"
5496 [(set (match_dup 1) (unordered:DI (match_dup 2) (match_dup 3)))
5498 (if_then_else (ne (match_dup 1) (const_int 0))
5499 (label_ref:DI (match_operand 0 "" ""))
5504 operands[1] = gen_reg_rtx (DImode);
5505 operands[2] = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
5506 operands[3] = force_reg (GET_MODE (sh_compare_op1), sh_compare_op1);
5509 ;; ------------------------------------------------------------------------
5510 ;; Jump and linkage insns
5511 ;; ------------------------------------------------------------------------
5513 (define_insn "jump_compact"
5515 (label_ref (match_operand 0 "" "")))]
5519 /* The length is 16 if the delay slot is unfilled. */
5520 if (get_attr_length(insn) > 4)
5521 return output_far_jump(insn, operands[0]);
5523 return \"bra %l0%#\";
5525 [(set_attr "type" "jump")
5526 (set_attr "needs_delay_slot" "yes")])
5528 ;; ??? It would be much saner to explicitly use the scratch register
5529 ;; in the jump insn, and have indirect_jump_scratch only set it,
5530 ;; but fill_simple_delay_slots would refuse to do delay slot filling
5531 ;; from the target then, as it uses simplejump_p.
5532 ;;(define_insn "jump_compact_far"
5534 ;; (label_ref (match_operand 0 "" "")))
5535 ;; (use (match_operand 1 "register_operand" "r")]
5537 ;; "* return output_far_jump(insn, operands[0], operands[1]);"
5538 ;; [(set_attr "type" "jump")
5539 ;; (set_attr "needs_delay_slot" "yes")])
5541 (define_insn "jump_media"
5543 (match_operand:DI 0 "target_operand" "b"))]
5546 [(set_attr "type" "jump_media")])
5548 (define_expand "jump"
5550 (label_ref (match_operand 0 "" "")))]
5555 emit_jump_insn (gen_jump_compact (operands[0]));
5556 else if (TARGET_SHMEDIA)
5558 if (reload_in_progress || reload_completed)
5560 emit_jump_insn (gen_jump_media (gen_rtx_LABEL_REF (DImode,
5566 (define_insn "force_mode_for_call"
5567 [(use (reg:PSI FPSCR_REG))]
5570 [(set_attr "length" "0")
5571 (set (attr "fp_mode")
5572 (if_then_else (eq_attr "fpu_single" "yes")
5573 (const_string "single") (const_string "double")))])
5575 (define_insn "calli"
5576 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
5577 (match_operand 1 "" ""))
5578 (use (reg:PSI FPSCR_REG))
5579 (clobber (reg:SI PR_REG))]
5582 [(set_attr "type" "call")
5583 (set (attr "fp_mode")
5584 (if_then_else (eq_attr "fpu_single" "yes")
5585 (const_string "single") (const_string "double")))
5586 (set_attr "needs_delay_slot" "yes")
5587 (set_attr "fp_set" "unknown")])
5589 ;; This is a pc-rel call, using bsrf, for use with PIC.
5591 (define_insn "calli_pcrel"
5592 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
5593 (match_operand 1 "" ""))
5594 (use (reg:PSI FPSCR_REG))
5595 (use (reg:SI PIC_REG))
5596 (use (match_operand 2 "" ""))
5597 (clobber (reg:SI PR_REG))]
5600 [(set_attr "type" "call")
5601 (set (attr "fp_mode")
5602 (if_then_else (eq_attr "fpu_single" "yes")
5603 (const_string "single") (const_string "double")))
5604 (set_attr "needs_delay_slot" "yes")
5605 (set_attr "fp_set" "unknown")])
5607 (define_insn_and_split "call_pcrel"
5608 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
5609 (match_operand 1 "" ""))
5610 (use (reg:PSI FPSCR_REG))
5611 (use (reg:SI PIC_REG))
5612 (clobber (reg:SI PR_REG))
5613 (clobber (match_scratch:SI 2 "=r"))]
5620 rtx lab = PATTERN (gen_call_site ());
5622 if (SYMBOL_REF_LOCAL_P (operands[0]))
5623 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
5625 emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
5626 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], lab));
5629 [(set_attr "type" "call")
5630 (set (attr "fp_mode")
5631 (if_then_else (eq_attr "fpu_single" "yes")
5632 (const_string "single") (const_string "double")))
5633 (set_attr "needs_delay_slot" "yes")
5634 (set_attr "fp_set" "unknown")])
5636 (define_insn "call_compact"
5637 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
5638 (match_operand 1 "" ""))
5639 (match_operand 2 "immediate_operand" "n")
5640 (use (reg:SI R0_REG))
5641 (use (reg:SI R1_REG))
5642 (use (reg:PSI FPSCR_REG))
5643 (clobber (reg:SI PR_REG))]
5644 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
5646 [(set_attr "type" "call")
5647 (set (attr "fp_mode")
5648 (if_then_else (eq_attr "fpu_single" "yes")
5649 (const_string "single") (const_string "double")))
5650 (set_attr "needs_delay_slot" "yes")])
5652 (define_insn "call_compact_rettramp"
5653 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
5654 (match_operand 1 "" ""))
5655 (match_operand 2 "immediate_operand" "n")
5656 (use (reg:SI R0_REG))
5657 (use (reg:SI R1_REG))
5658 (use (reg:PSI FPSCR_REG))
5659 (clobber (reg:SI R10_REG))
5660 (clobber (reg:SI PR_REG))]
5661 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
5663 [(set_attr "type" "call")
5664 (set (attr "fp_mode")
5665 (if_then_else (eq_attr "fpu_single" "yes")
5666 (const_string "single") (const_string "double")))
5667 (set_attr "needs_delay_slot" "yes")])
5669 (define_insn "call_media"
5670 [(call (mem:DI (match_operand:DI 0 "target_reg_operand" "b"))
5671 (match_operand 1 "" ""))
5672 (clobber (reg:DI PR_MEDIA_REG))]
5675 [(set_attr "type" "jump_media")])
5677 (define_insn "call_valuei"
5678 [(set (match_operand 0 "" "=rf")
5679 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
5680 (match_operand 2 "" "")))
5681 (use (reg:PSI FPSCR_REG))
5682 (clobber (reg:SI PR_REG))]
5685 [(set_attr "type" "call")
5686 (set (attr "fp_mode")
5687 (if_then_else (eq_attr "fpu_single" "yes")
5688 (const_string "single") (const_string "double")))
5689 (set_attr "needs_delay_slot" "yes")
5690 (set_attr "fp_set" "unknown")])
5692 (define_insn "call_valuei_pcrel"
5693 [(set (match_operand 0 "" "=rf")
5694 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
5695 (match_operand 2 "" "")))
5696 (use (reg:PSI FPSCR_REG))
5697 (use (reg:SI PIC_REG))
5698 (use (match_operand 3 "" ""))
5699 (clobber (reg:SI PR_REG))]
5702 [(set_attr "type" "call")
5703 (set (attr "fp_mode")
5704 (if_then_else (eq_attr "fpu_single" "yes")
5705 (const_string "single") (const_string "double")))
5706 (set_attr "needs_delay_slot" "yes")
5707 (set_attr "fp_set" "unknown")])
5709 (define_insn_and_split "call_value_pcrel"
5710 [(set (match_operand 0 "" "=rf")
5711 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
5712 (match_operand 2 "" "")))
5713 (use (reg:PSI FPSCR_REG))
5714 (use (reg:SI PIC_REG))
5715 (clobber (reg:SI PR_REG))
5716 (clobber (match_scratch:SI 3 "=r"))]
5723 rtx lab = PATTERN (gen_call_site ());
5725 if (SYMBOL_REF_LOCAL_P (operands[1]))
5726 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
5728 emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
5729 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
5733 [(set_attr "type" "call")
5734 (set (attr "fp_mode")
5735 (if_then_else (eq_attr "fpu_single" "yes")
5736 (const_string "single") (const_string "double")))
5737 (set_attr "needs_delay_slot" "yes")
5738 (set_attr "fp_set" "unknown")])
5740 (define_insn "call_value_compact"
5741 [(set (match_operand 0 "" "=rf")
5742 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
5743 (match_operand 2 "" "")))
5744 (match_operand 3 "immediate_operand" "n")
5745 (use (reg:SI R0_REG))
5746 (use (reg:SI R1_REG))
5747 (use (reg:PSI FPSCR_REG))
5748 (clobber (reg:SI PR_REG))]
5749 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
5751 [(set_attr "type" "call")
5752 (set (attr "fp_mode")
5753 (if_then_else (eq_attr "fpu_single" "yes")
5754 (const_string "single") (const_string "double")))
5755 (set_attr "needs_delay_slot" "yes")])
5757 (define_insn "call_value_compact_rettramp"
5758 [(set (match_operand 0 "" "=rf")
5759 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
5760 (match_operand 2 "" "")))
5761 (match_operand 3 "immediate_operand" "n")
5762 (use (reg:SI R0_REG))
5763 (use (reg:SI R1_REG))
5764 (use (reg:PSI FPSCR_REG))
5765 (clobber (reg:SI R10_REG))
5766 (clobber (reg:SI PR_REG))]
5767 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
5769 [(set_attr "type" "call")
5770 (set (attr "fp_mode")
5771 (if_then_else (eq_attr "fpu_single" "yes")
5772 (const_string "single") (const_string "double")))
5773 (set_attr "needs_delay_slot" "yes")])
5775 (define_insn "call_value_media"
5776 [(set (match_operand 0 "" "=rf")
5777 (call (mem:DI (match_operand:DI 1 "target_reg_operand" "b"))
5778 (match_operand 2 "" "")))
5779 (clobber (reg:DI PR_MEDIA_REG))]
5782 [(set_attr "type" "jump_media")])
5784 (define_expand "call"
5785 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
5786 (match_operand 1 "" ""))
5787 (match_operand 2 "" "")
5788 (use (reg:PSI FPSCR_REG))
5789 (clobber (reg:SI PR_REG))])]
5795 operands[0] = XEXP (operands[0], 0);
5796 if (flag_pic && GET_CODE (operands[0]) == SYMBOL_REF)
5798 if (! SYMBOL_REF_LOCAL_P (operands[0]))
5800 rtx reg = gen_reg_rtx (Pmode);
5802 emit_insn (gen_symGOTPLT2reg (reg, operands[0]));
5807 operands[0] = gen_sym2PIC (operands[0]);
5808 PUT_MODE (operands[0], Pmode);
5811 if (GET_MODE (operands[0]) == SImode)
5813 if (GET_CODE (operands[0]) == REG)
5814 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
5815 else if (GET_CODE (operands[0]) == SUBREG)
5817 operands[0] = SUBREG_REG (operands[0]);
5818 if (GET_MODE (operands[0]) != DImode)
5819 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
5821 else if (TARGET_SHMEDIA64)
5823 operands[0] = shallow_copy_rtx (operands[0]);
5824 PUT_MODE (operands[0], DImode);
5828 rtx reg = gen_reg_rtx (DImode);
5830 operands[0] = copy_to_mode_reg (SImode, operands[0]);
5831 emit_insn (gen_extendsidi2 (reg, operands[0]));
5835 if (! target_reg_operand (operands[0], DImode))
5836 operands[0] = copy_to_mode_reg (DImode, operands[0]);
5837 emit_call_insn (gen_call_media (operands[0], operands[1]));
5840 else if (TARGET_SHCOMPACT && operands[2] && INTVAL (operands[2]))
5842 rtx cookie_rtx = operands[2];
5843 long cookie = INTVAL (cookie_rtx);
5844 rtx func = XEXP (operands[0], 0);
5849 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
5851 rtx reg = gen_reg_rtx (Pmode);
5853 emit_insn (gen_symGOTPLT2reg (reg, func));
5857 func = legitimize_pic_address (func, Pmode, 0);
5860 r0 = gen_rtx_REG (SImode, R0_REG);
5861 r1 = gen_rtx_REG (SImode, R1_REG);
5863 /* Since such a call function may use all call-clobbered
5864 registers, we force a mode switch earlier, so that we don't
5865 run out of registers when adjusting fpscr for the call. */
5866 emit_insn (gen_force_mode_for_call ());
5868 operands[0] = function_symbol (\"__GCC_shcompact_call_trampoline\");
5871 rtx reg = gen_reg_rtx (Pmode);
5873 emit_insn (gen_symGOTPLT2reg (reg, operands[0]));
5876 operands[0] = force_reg (SImode, operands[0]);
5878 emit_move_insn (r0, func);
5879 emit_move_insn (r1, cookie_rtx);
5881 if (cookie & CALL_COOKIE_RET_TRAMP (1))
5882 emit_call_insn (gen_call_compact_rettramp (operands[0], operands[1],
5885 emit_call_insn (gen_call_compact (operands[0], operands[1],
5890 else if (TARGET_SHCOMPACT && flag_pic
5891 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
5892 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
5894 rtx reg = gen_reg_rtx (Pmode);
5896 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[0], 0)));
5897 XEXP (operands[0], 0) = reg;
5899 if (flag_pic && TARGET_SH2
5900 && GET_CODE (operands[0]) == MEM
5901 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5903 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
5908 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
5909 operands[1] = operands[2];
5912 emit_call_insn (gen_calli (operands[0], operands[1]));
5916 (define_insn "call_pop_compact"
5917 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
5918 (match_operand 1 "" ""))
5919 (match_operand 2 "immediate_operand" "n")
5920 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
5921 (match_operand 3 "immediate_operand" "n")))
5922 (use (reg:SI R0_REG))
5923 (use (reg:SI R1_REG))
5924 (use (reg:PSI FPSCR_REG))
5925 (clobber (reg:SI PR_REG))]
5926 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
5928 [(set_attr "type" "call")
5929 (set (attr "fp_mode")
5930 (if_then_else (eq_attr "fpu_single" "yes")
5931 (const_string "single") (const_string "double")))
5932 (set_attr "needs_delay_slot" "yes")])
5934 (define_insn "call_pop_compact_rettramp"
5935 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
5936 (match_operand 1 "" ""))
5937 (match_operand 2 "immediate_operand" "n")
5938 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
5939 (match_operand 3 "immediate_operand" "n")))
5940 (use (reg:SI R0_REG))
5941 (use (reg:SI R1_REG))
5942 (use (reg:PSI FPSCR_REG))
5943 (clobber (reg:SI R10_REG))
5944 (clobber (reg:SI PR_REG))]
5945 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
5947 [(set_attr "type" "call")
5948 (set (attr "fp_mode")
5949 (if_then_else (eq_attr "fpu_single" "yes")
5950 (const_string "single") (const_string "double")))
5951 (set_attr "needs_delay_slot" "yes")])
5953 (define_expand "call_pop"
5954 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
5955 (match_operand 1 "" ""))
5956 (match_operand 2 "" "")
5957 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
5958 (match_operand 3 "" "")))])]
5962 if (operands[2] && INTVAL (operands[2]))
5964 rtx cookie_rtx = operands[2];
5965 long cookie = INTVAL (cookie_rtx);
5966 rtx func = XEXP (operands[0], 0);
5971 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
5973 rtx reg = gen_reg_rtx (Pmode);
5975 emit_insn (gen_symGOTPLT2reg (reg, func));
5979 func = legitimize_pic_address (func, Pmode, 0);
5982 r0 = gen_rtx_REG (SImode, R0_REG);
5983 r1 = gen_rtx_REG (SImode, R1_REG);
5985 /* Since such a call function may use all call-clobbered
5986 registers, we force a mode switch earlier, so that we don't
5987 run out of registers when adjusting fpscr for the call. */
5988 emit_insn (gen_force_mode_for_call ());
5990 operands[0] = function_symbol (\"__GCC_shcompact_call_trampoline\");
5993 rtx reg = gen_reg_rtx (Pmode);
5995 emit_insn (gen_symGOTPLT2reg (reg, operands[0]));
5998 operands[0] = force_reg (SImode, operands[0]);
6000 emit_move_insn (r0, func);
6001 emit_move_insn (r1, cookie_rtx);
6003 if (cookie & CALL_COOKIE_RET_TRAMP (1))
6004 emit_call_insn (gen_call_pop_compact_rettramp
6005 (operands[0], operands[1], operands[2], operands[3]));
6007 emit_call_insn (gen_call_pop_compact
6008 (operands[0], operands[1], operands[2], operands[3]));
6016 (define_expand "call_value"
6017 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
6018 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
6019 (match_operand 2 "" "")))
6020 (match_operand 3 "" "")
6021 (use (reg:PSI FPSCR_REG))
6022 (clobber (reg:SI PR_REG))])]
6028 operands[1] = XEXP (operands[1], 0);
6029 if (flag_pic && GET_CODE (operands[1]) == SYMBOL_REF)
6031 if (! SYMBOL_REF_LOCAL_P (operands[1]))
6033 rtx reg = gen_reg_rtx (Pmode);
6035 emit_insn (gen_symGOTPLT2reg (reg, operands[1]));
6040 operands[1] = gen_sym2PIC (operands[1]);
6041 PUT_MODE (operands[1], Pmode);
6044 if (GET_MODE (operands[1]) == SImode)
6046 if (GET_CODE (operands[1]) == REG)
6047 operands[1] = gen_rtx_SUBREG (DImode, operands[1], 0);
6048 else if (GET_CODE (operands[1]) == SUBREG)
6050 operands[1] = SUBREG_REG (operands[1]);
6051 if (GET_MODE (operands[1]) != DImode)
6052 operands[1] = gen_rtx_SUBREG (DImode, operands[1], 0);
6054 else if (TARGET_SHMEDIA64)
6056 operands[1] = shallow_copy_rtx (operands[1]);
6057 PUT_MODE (operands[1], DImode);
6061 rtx reg = gen_reg_rtx (DImode);
6063 operands[1] = copy_to_mode_reg (SImode, operands[1]);
6064 emit_insn (gen_extendsidi2 (reg, operands[1]));
6068 if (! target_reg_operand (operands[1], DImode))
6069 operands[1] = copy_to_mode_reg (DImode, operands[1]);
6070 emit_call_insn (gen_call_value_media (operands[0], operands[1],
6074 else if (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]))
6076 rtx cookie_rtx = operands[3];
6077 long cookie = INTVAL (cookie_rtx);
6078 rtx func = XEXP (operands[1], 0);
6083 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
6085 rtx reg = gen_reg_rtx (Pmode);
6087 emit_insn (gen_symGOTPLT2reg (reg, func));
6091 func = legitimize_pic_address (func, Pmode, 0);
6094 r0 = gen_rtx_REG (SImode, R0_REG);
6095 r1 = gen_rtx_REG (SImode, R1_REG);
6097 /* Since such a call function may use all call-clobbered
6098 registers, we force a mode switch earlier, so that we don't
6099 run out of registers when adjusting fpscr for the call. */
6100 emit_insn (gen_force_mode_for_call ());
6102 operands[1] = function_symbol (\"__GCC_shcompact_call_trampoline\");
6105 rtx reg = gen_reg_rtx (Pmode);
6107 emit_insn (gen_symGOTPLT2reg (reg, operands[1]));
6110 operands[1] = force_reg (SImode, operands[1]);
6112 emit_move_insn (r0, func);
6113 emit_move_insn (r1, cookie_rtx);
6115 if (cookie & CALL_COOKIE_RET_TRAMP (1))
6116 emit_call_insn (gen_call_value_compact_rettramp (operands[0],
6121 emit_call_insn (gen_call_value_compact (operands[0], operands[1],
6122 operands[2], operands[3]));
6126 else if (TARGET_SHCOMPACT && flag_pic
6127 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
6128 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
6130 rtx reg = gen_reg_rtx (Pmode);
6132 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[1], 0)));
6133 XEXP (operands[1], 0) = reg;
6135 if (flag_pic && TARGET_SH2
6136 && GET_CODE (operands[1]) == MEM
6137 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6139 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
6144 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
6146 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
6150 (define_insn "sibcalli"
6151 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
6152 (match_operand 1 "" ""))
6153 (use (reg:PSI FPSCR_REG))
6157 [(set_attr "needs_delay_slot" "yes")
6158 (set (attr "fp_mode")
6159 (if_then_else (eq_attr "fpu_single" "yes")
6160 (const_string "single") (const_string "double")))
6161 (set_attr "type" "jump_ind")])
6163 (define_insn "sibcalli_pcrel"
6164 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
6165 (match_operand 1 "" ""))
6166 (use (match_operand 2 "" ""))
6167 (use (reg:PSI FPSCR_REG))
6171 [(set_attr "needs_delay_slot" "yes")
6172 (set (attr "fp_mode")
6173 (if_then_else (eq_attr "fpu_single" "yes")
6174 (const_string "single") (const_string "double")))
6175 (set_attr "type" "jump_ind")])
6177 (define_insn_and_split "sibcall_pcrel"
6178 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
6179 (match_operand 1 "" ""))
6180 (use (reg:PSI FPSCR_REG))
6181 (clobber (match_scratch:SI 2 "=k"))
6189 rtx lab = PATTERN (gen_call_site ());
6192 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
6193 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
6195 SIBLING_CALL_P (call_insn) = 1;
6198 [(set_attr "needs_delay_slot" "yes")
6199 (set (attr "fp_mode")
6200 (if_then_else (eq_attr "fpu_single" "yes")
6201 (const_string "single") (const_string "double")))
6202 (set_attr "type" "jump_ind")])
6204 (define_insn "sibcall_compact"
6205 [(call (mem:SI (match_operand:SI 0 "register_operand" "k,k"))
6206 (match_operand 1 "" ""))
6208 (use (match_operand:SI 2 "register_operand" "z,x"))
6209 (use (reg:SI R1_REG))
6210 (use (reg:PSI FPSCR_REG))
6211 ;; We want to make sure the `x' above will only match MACH_REG
6212 ;; because sibcall_epilogue may clobber MACL_REG.
6213 (clobber (reg:SI MACL_REG))]
6217 jmp @%0\\n sts %2, r0"
6218 [(set_attr "needs_delay_slot" "yes,no")
6219 (set_attr "length" "2,4")
6220 (set (attr "fp_mode") (const_string "single"))
6221 (set_attr "type" "jump_ind")])
6223 (define_insn "sibcall_media"
6224 [(call (mem:DI (match_operand:DI 0 "target_reg_operand" "k"))
6225 (match_operand 1 "" ""))
6226 (use (reg:SI PR_MEDIA_REG))
6230 [(set_attr "type" "jump_media")])
6232 (define_expand "sibcall"
6234 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
6235 (match_operand 1 "" ""))
6236 (match_operand 2 "" "")
6237 (use (reg:PSI FPSCR_REG))
6244 operands[0] = XEXP (operands[0], 0);
6245 if (flag_pic && GET_CODE (operands[0]) == SYMBOL_REF)
6247 if (! SYMBOL_REF_LOCAL_P (operands[0]))
6249 rtx reg = gen_reg_rtx (Pmode);
6251 /* We must not use GOTPLT for sibcalls, because PIC_REG
6252 must be restored before the PLT code gets to run. */
6253 emit_insn (gen_symGOT2reg (reg, operands[0]));
6258 operands[0] = gen_sym2PIC (operands[0]);
6259 PUT_MODE (operands[0], Pmode);
6262 if (GET_MODE (operands[0]) == SImode)
6264 if (GET_CODE (operands[0]) == REG)
6265 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
6266 else if (GET_CODE (operands[0]) == SUBREG)
6268 operands[0] = SUBREG_REG (operands[0]);
6269 if (GET_MODE (operands[0]) != DImode)
6270 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
6274 operands[0] = shallow_copy_rtx (operands[0]);
6275 PUT_MODE (operands[0], DImode);
6278 if (! target_reg_operand (operands[0], DImode))
6279 operands[0] = copy_to_mode_reg (DImode, operands[0]);
6280 emit_call_insn (gen_sibcall_media (operands[0], operands[1]));
6283 else if (TARGET_SHCOMPACT && operands[2]
6284 && (INTVAL (operands[2]) & ~ CALL_COOKIE_RET_TRAMP (1)))
6286 rtx cookie_rtx = operands[2];
6287 long cookie = INTVAL (cookie_rtx);
6288 rtx func = XEXP (operands[0], 0);
6293 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
6295 rtx reg = gen_reg_rtx (Pmode);
6297 emit_insn (gen_symGOT2reg (reg, func));
6301 func = legitimize_pic_address (func, Pmode, 0);
6304 /* FIXME: if we could tell whether all argument registers are
6305 already taken, we could decide whether to force the use of
6306 MACH_REG or to stick to R0_REG. Unfortunately, there's no
6307 simple way to tell. We could use the CALL_COOKIE, but we
6308 can't currently tell a register used for regular argument
6309 passing from one that is unused. If we leave it up to reload
6310 to decide which register to use, it seems to always choose
6311 R0_REG, which leaves no available registers in SIBCALL_REGS
6312 to hold the address of the trampoline. */
6313 mach = gen_rtx_REG (SImode, MACH_REG);
6314 r1 = gen_rtx_REG (SImode, R1_REG);
6316 /* Since such a call function may use all call-clobbered
6317 registers, we force a mode switch earlier, so that we don't
6318 run out of registers when adjusting fpscr for the call. */
6319 emit_insn (gen_force_mode_for_call ());
6321 operands[0] = function_symbol (\"__GCC_shcompact_call_trampoline\");
6324 rtx reg = gen_reg_rtx (Pmode);
6326 emit_insn (gen_symGOT2reg (reg, operands[0]));
6329 operands[0] = force_reg (SImode, operands[0]);
6331 /* We don't need a return trampoline, since the callee will
6332 return directly to the upper caller. */
6333 if (cookie & CALL_COOKIE_RET_TRAMP (1))
6335 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
6336 cookie_rtx = GEN_INT (cookie);
6339 emit_move_insn (mach, func);
6340 emit_move_insn (r1, cookie_rtx);
6342 emit_call_insn (gen_sibcall_compact (operands[0], operands[1], mach));
6345 else if (TARGET_SHCOMPACT && flag_pic
6346 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
6347 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
6349 rtx reg = gen_reg_rtx (Pmode);
6351 emit_insn (gen_symGOT2reg (reg, XEXP (operands[0], 0)));
6352 XEXP (operands[0], 0) = reg;
6354 if (flag_pic && TARGET_SH2
6355 && GET_CODE (operands[0]) == MEM
6356 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
6357 /* The PLT needs the PIC register, but the epilogue would have
6358 to restore it, so we can only use PC-relative PIC calls for
6359 static functions. */
6360 && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
6362 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
6366 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
6368 emit_call_insn (gen_sibcalli (operands[0], operands[1]));
6372 (define_expand "sibcall_value"
6373 [(set (match_operand 0 "" "")
6374 (call (match_operand 1 "" "")
6375 (match_operand 2 "" "")))
6376 (match_operand 3 "" "")]
6380 emit_call_insn (gen_sibcall (operands[1], operands[2], operands[3]));
6384 (define_insn "call_value_pop_compact"
6385 [(set (match_operand 0 "" "=rf")
6386 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6387 (match_operand 2 "" "")))
6388 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
6389 (match_operand 4 "immediate_operand" "n")))
6390 (match_operand 3 "immediate_operand" "n")
6391 (use (reg:SI R0_REG))
6392 (use (reg:SI R1_REG))
6393 (use (reg:PSI FPSCR_REG))
6394 (clobber (reg:SI PR_REG))]
6395 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
6397 [(set_attr "type" "call")
6398 (set (attr "fp_mode")
6399 (if_then_else (eq_attr "fpu_single" "yes")
6400 (const_string "single") (const_string "double")))
6401 (set_attr "needs_delay_slot" "yes")])
6403 (define_insn "call_value_pop_compact_rettramp"
6404 [(set (match_operand 0 "" "=rf")
6405 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6406 (match_operand 2 "" "")))
6407 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
6408 (match_operand 4 "immediate_operand" "n")))
6409 (match_operand 3 "immediate_operand" "n")
6410 (use (reg:SI R0_REG))
6411 (use (reg:SI R1_REG))
6412 (use (reg:PSI FPSCR_REG))
6413 (clobber (reg:SI R10_REG))
6414 (clobber (reg:SI PR_REG))]
6415 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
6417 [(set_attr "type" "call")
6418 (set (attr "fp_mode")
6419 (if_then_else (eq_attr "fpu_single" "yes")
6420 (const_string "single") (const_string "double")))
6421 (set_attr "needs_delay_slot" "yes")])
6423 (define_expand "call_value_pop"
6424 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
6425 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
6426 (match_operand 2 "" "")))
6427 (match_operand 3 "" "")
6428 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
6429 (match_operand 4 "" "")))])]
6433 if (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]))
6435 rtx cookie_rtx = operands[3];
6436 long cookie = INTVAL (cookie_rtx);
6437 rtx func = XEXP (operands[1], 0);
6442 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
6444 rtx reg = gen_reg_rtx (Pmode);
6446 emit_insn (gen_symGOTPLT2reg (reg, func));
6450 func = legitimize_pic_address (func, Pmode, 0);
6453 r0 = gen_rtx_REG (SImode, R0_REG);
6454 r1 = gen_rtx_REG (SImode, R1_REG);
6456 /* Since such a call function may use all call-clobbered
6457 registers, we force a mode switch earlier, so that we don't
6458 run out of registers when adjusting fpscr for the call. */
6459 emit_insn (gen_force_mode_for_call ());
6461 operands[1] = function_symbol (\"__GCC_shcompact_call_trampoline\");
6464 rtx reg = gen_reg_rtx (Pmode);
6466 emit_insn (gen_symGOTPLT2reg (reg, operands[1]));
6469 operands[1] = force_reg (SImode, operands[1]);
6471 emit_move_insn (r0, func);
6472 emit_move_insn (r1, cookie_rtx);
6474 if (cookie & CALL_COOKIE_RET_TRAMP (1))
6475 emit_call_insn (gen_call_value_pop_compact_rettramp
6476 (operands[0], operands[1], operands[2],
6477 operands[3], operands[4]));
6479 emit_call_insn (gen_call_value_pop_compact
6480 (operands[0], operands[1], operands[2],
6481 operands[3], operands[4]));
6489 (define_expand "sibcall_epilogue"
6494 sh_expand_epilogue (1);
6495 if (TARGET_SHCOMPACT)
6499 /* If epilogue clobbers r0, preserve it in macl. */
6500 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6501 if ((set = single_set (insn))
6502 && GET_CODE (SET_DEST (set)) == REG
6503 && REGNO (SET_DEST (set)) == R0_REG)
6505 rtx r0 = gen_rtx_REG (SImode, R0_REG);
6506 rtx tmp = gen_rtx_REG (SImode, MACL_REG);
6509 /* We can't tell at this point whether the sibcall is a
6510 sibcall_compact and, if it is, whether it uses r0 or
6511 mach as operand 2, so let the instructions that
6512 preserve r0 be optimized away if r0 turns out to be
6514 i = emit_insn_before (gen_rtx_SET (SImode, tmp, r0), insn);
6515 REG_NOTES (i) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx,
6517 i = emit_move_insn (r0, tmp);
6518 REG_NOTES (i) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx,
6526 (define_insn "indirect_jump_compact"
6528 (match_operand:SI 0 "arith_reg_operand" "r"))]
6531 [(set_attr "needs_delay_slot" "yes")
6532 (set_attr "type" "jump_ind")])
6534 (define_expand "indirect_jump"
6536 (match_operand 0 "register_operand" ""))]
6540 if (TARGET_SHMEDIA && GET_MODE (operands[0]) == SImode)
6541 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
6544 ;; The use of operand 1 / 2 helps us distinguish case table jumps
6545 ;; which can be present in structured code from indirect jumps which can not
6546 ;; be present in structured code. This allows -fprofile-arcs to work.
6548 ;; For SH1 processors.
6549 (define_insn "casesi_jump_1"
6551 (match_operand:SI 0 "register_operand" "r"))
6552 (use (label_ref (match_operand 1 "" "")))]
6555 [(set_attr "needs_delay_slot" "yes")
6556 (set_attr "type" "jump_ind")])
6558 ;; For all later processors.
6559 (define_insn "casesi_jump_2"
6560 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
6561 (label_ref (match_operand 1 "" ""))))
6562 (use (label_ref (match_operand 2 "" "")))]
6564 && (! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn)"
6566 [(set_attr "needs_delay_slot" "yes")
6567 (set_attr "type" "jump_ind")])
6569 (define_insn "casesi_jump_media"
6570 [(set (pc) (match_operand:DI 0 "target_reg_operand" "b"))
6571 (use (label_ref (match_operand 1 "" "")))]
6574 [(set_attr "type" "jump_media")])
6576 ;; Call subroutine returning any type.
6577 ;; ??? This probably doesn't work.
6579 (define_expand "untyped_call"
6580 [(parallel [(call (match_operand 0 "" "")
6582 (match_operand 1 "" "")
6583 (match_operand 2 "" "")])]
6584 "(TARGET_SH2E || TARGET_SH2A) || TARGET_SHMEDIA"
6589 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6591 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6593 rtx set = XVECEXP (operands[2], 0, i);
6594 emit_move_insn (SET_DEST (set), SET_SRC (set));
6597 /* The optimizer does not know that the call sets the function value
6598 registers we stored in the result block. We avoid problems by
6599 claiming that all hard registers are used and clobbered at this
6601 emit_insn (gen_blockage ());
6606 ;; ------------------------------------------------------------------------
6608 ;; ------------------------------------------------------------------------
6611 [(set (reg:SI T_REG)
6612 (eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
6613 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
6616 [(set_attr "type" "arith")])
6623 ;; Load address of a label. This is only generated by the casesi expand,
6624 ;; and by machine_dependent_reorg (fixing up fp moves).
6625 ;; This must use unspec, because this only works for labels that are
6629 [(set (reg:SI R0_REG)
6630 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
6633 [(set_attr "in_delay_slot" "no")
6634 (set_attr "type" "arith")])
6636 ;; machine_dependent_reorg will make this a `mova'.
6637 (define_insn "mova_const"
6638 [(set (reg:SI R0_REG)
6639 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
6642 [(set_attr "in_delay_slot" "no")
6643 (set_attr "type" "arith")])
6645 (define_expand "GOTaddr2picreg"
6646 [(set (reg:SI R0_REG)
6647 (unspec:SI [(const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC))]
6649 (set (match_dup 0) (const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC)))
6650 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
6653 operands[0] = gen_rtx_REG (Pmode, PIC_REG);
6654 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
6657 operands[1] = gen_datalabel_ref (operands[1]);
6661 rtx tr = gen_rtx_REG (DImode, TR0_REG);
6662 rtx dipic = operands[0];
6663 rtx lab = PATTERN (gen_call_site ());
6666 equiv = operands[1];
6667 operands[1] = gen_rtx_MINUS (DImode,
6671 gen_rtx_MINUS (DImode,
6672 gen_rtx_CONST (DImode,
6675 operands[1] = gen_sym2PIC (operands[1]);
6676 PUT_MODE (operands[1], DImode);
6678 if (GET_MODE (dipic) != DImode)
6679 dipic = gen_rtx_SUBREG (DImode, dipic, 0);
6681 if (TARGET_SHMEDIA64)
6682 emit_insn (gen_movdi_const (dipic, operands[1]));
6684 emit_insn (gen_movdi_const_32bit (dipic, operands[1]));
6686 emit_insn (gen_ptrel (tr, dipic, lab));
6688 if (GET_MODE (operands[0]) != GET_MODE (tr))
6689 tr = gen_lowpart (GET_MODE (operands[0]), tr);
6691 insn = emit_move_insn (operands[0], tr);
6693 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, equiv,
6702 [(set (match_operand:DI 0 "target_reg_operand" "=b")
6703 (const:DI (unspec:DI [(match_operand:DI 1 "" "Csy")]
6704 UNSPEC_DATALABEL)))]
6705 "TARGET_SHMEDIA && flag_pic
6706 && EXTRA_CONSTRAINT_Csy (operands[1])"
6707 "ptb/u datalabel %1, %0"
6708 [(set_attr "type" "pt_media")
6709 (set_attr "length" "*")])
6711 (define_insn "ptrel"
6712 [(set (match_operand:DI 0 "target_reg_operand" "=b")
6713 (plus:DI (match_operand:DI 1 "register_operand" "r")
6715 (match_operand:DI 2 "" "")]
6717 "%O2: ptrel/u %1, %0"
6718 [(set_attr "type" "ptabs_media")])
6720 (define_expand "builtin_setjmp_receiver"
6721 [(match_operand 0 "" "")]
6725 emit_insn (gen_GOTaddr2picreg ());
6729 (define_expand "call_site"
6730 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
6734 static HOST_WIDE_INT i = 0;
6735 operands[0] = GEN_INT (i);
6739 (define_expand "sym_label2reg"
6740 [(set (match_operand:SI 0 "" "")
6743 (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC))
6746 (match_operand:SI 2 "" "")
6750 (define_expand "symGOT_load"
6751 [(set (match_dup 2) (match_operand 1 "" ""))
6752 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
6753 (set (match_operand 0 "" "") (mem (match_dup 3)))]
6759 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
6760 operands[3] = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
6764 rtx reg = operands[2];
6766 if (GET_MODE (reg) != DImode)
6767 reg = gen_rtx_SUBREG (DImode, reg, 0);
6770 emit_insn (gen_movdi_const_32bit (reg, operands[1]));
6772 emit_insn (gen_movdi_const_16bit (reg, operands[1]));
6775 emit_move_insn (operands[2], operands[1]);
6777 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode,
6779 gen_rtx_REG (Pmode, PIC_REG)));
6781 insn = emit_move_insn (operands[0], gen_rtx_MEM (Pmode, operands[3]));
6783 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, XVECEXP (XEXP (operands[1],
6790 (define_expand "sym2GOT"
6791 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))]
6795 (define_expand "symGOT2reg"
6796 [(match_operand 0 "" "") (match_operand 1 "" "")]
6802 gotsym = gen_sym2GOT (operands[1]);
6803 PUT_MODE (gotsym, Pmode);
6804 insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
6806 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
6811 (define_expand "sym2GOTPLT"
6812 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTPLT))]
6816 (define_expand "symGOTPLT2reg"
6817 [(match_operand 0 "" "") (match_operand 1 "" "")]
6821 emit_insn (gen_symGOT_load (operands[0], gen_sym2GOTPLT (operands[1])));
6825 (define_expand "sym2GOTOFF"
6826 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))]
6830 (define_expand "symGOTOFF2reg"
6831 [(match_operand 0 "" "") (match_operand 1 "" "")]
6835 rtx gotoffsym, insn;
6836 rtx t = no_new_pseudos ? operands[0] : gen_reg_rtx (GET_MODE (operands[0]));
6838 gotoffsym = gen_sym2GOTOFF (operands[1]);
6839 PUT_MODE (gotoffsym, Pmode);
6840 emit_move_insn (t, gotoffsym);
6841 insn = emit_move_insn (operands[0],
6842 gen_rtx_PLUS (Pmode, t,
6843 gen_rtx_REG (Pmode, PIC_REG)));
6845 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
6851 (define_expand "symPLT_label2reg"
6852 [(set (match_operand:SI 0 "" "")
6855 (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT))
6859 (match_operand:SI 2 "" "")
6861 (const:SI (unspec:SI [(pc)] UNSPEC_PIC)))))))
6862 ;; Even though the PIC register is not really used by the call
6863 ;; sequence in which this is expanded, the PLT code assumes the PIC
6864 ;; register is set, so we must not skip its initialization. Since
6865 ;; we only use this expand as part of calling sequences, and never
6866 ;; to take the address of a function, this is the best point to
6867 ;; insert the (use). Using the PLT to take the address of a
6868 ;; function would be wrong, not only because the PLT entry could
6869 ;; then be called from a function that doesn't initialize the PIC
6870 ;; register to the proper GOT, but also because pointers to the
6871 ;; same function might not compare equal, should they be set by
6872 ;; different shared libraries.
6873 (use (reg:SI PIC_REG))]
6877 (define_expand "sym2PIC"
6878 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))]
6882 ;; TLS code generation.
6883 ;; ??? this should be a define_insn_and_split
6884 ;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
6885 ;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
6888 (define_insn "tls_global_dynamic"
6889 [(set (match_operand:SI 0 "register_operand" "=&z")
6890 (call (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
6893 (use (reg:PSI FPSCR_REG))
6894 (use (reg:SI PIC_REG))
6895 (clobber (reg:SI PR_REG))
6896 (clobber (scratch:SI))]
6902 \\tmova\\t2f,r0\\n\\
6903 \\tmov.l\\t2f,r1\\n\\
6906 \\tadd\\tr12,r4\\n\\
6910 1:\\t.long\\t%a1@TLSGD\\n\\
6911 2:\\t.long\\t__tls_get_addr@PLT\\n\\
6914 [(set_attr "type" "tls_load")
6915 (set_attr "length" "26")])
6917 (define_insn "tls_local_dynamic"
6918 [(set (match_operand:SI 0 "register_operand" "=&z")
6919 (call (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
6922 (use (reg:PSI FPSCR_REG))
6923 (use (reg:SI PIC_REG))
6924 (clobber (reg:SI PR_REG))
6925 (clobber (scratch:SI))]
6931 \\tmova\\t2f,r0\\n\\
6932 \\tmov.l\\t2f,r1\\n\\
6935 \\tadd\\tr12,r4\\n\\
6939 1:\\t.long\\t%a1@TLSLDM\\n\\
6940 2:\\t.long\\t__tls_get_addr@PLT\\n\\
6943 [(set_attr "type" "tls_load")
6944 (set_attr "length" "26")])
6946 (define_expand "sym2DTPOFF"
6947 [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
6951 (define_expand "symDTPOFF2reg"
6952 [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
6956 rtx dtpoffsym, insn;
6957 rtx t = no_new_pseudos ? operands[0] : gen_reg_rtx (GET_MODE (operands[0]));
6959 dtpoffsym = gen_sym2DTPOFF (operands[1]);
6960 PUT_MODE (dtpoffsym, Pmode);
6961 emit_move_insn (t, dtpoffsym);
6962 insn = emit_move_insn (operands[0],
6963 gen_rtx_PLUS (Pmode, t, operands[2]));
6967 (define_expand "sym2GOTTPOFF"
6968 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
6972 (define_insn "tls_initial_exec"
6973 [(set (match_operand:SI 0 "register_operand" "=&r")
6974 (unspec:SI [(match_operand:SI 1 "" "")]
6976 (use (reg:SI GBR_REG))
6977 (use (reg:SI PIC_REG))
6978 (clobber (reg:SI R0_REG))]
6984 \\tstc\\tgbr,%0\\n\\
6985 \\tmov.l\\t@(r0,r12),r0\\n\\
6989 1:\\t.long\\t%a1\\n\\
6992 [(set_attr "type" "tls_load")
6993 (set_attr "length" "16")])
6995 (define_expand "sym2TPOFF"
6996 [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
7000 (define_expand "symTPOFF2reg"
7001 [(match_operand 0 "" "") (match_operand 1 "" "")]
7007 tpoffsym = gen_sym2TPOFF (operands[1]);
7008 PUT_MODE (tpoffsym, Pmode);
7009 insn = emit_move_insn (operands[0], tpoffsym);
7013 (define_insn "load_gbr"
7014 [(set (match_operand:SI 0 "register_operand" "") (reg:SI GBR_REG))
7015 (use (reg:SI GBR_REG))]
7018 [(set_attr "type" "tls_load")])
7020 ;; case instruction for switch statements.
7022 ;; Operand 0 is index
7023 ;; operand 1 is the minimum bound
7024 ;; operand 2 is the maximum bound - minimum bound + 1
7025 ;; operand 3 is CODE_LABEL for the table;
7026 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7028 (define_expand "casesi"
7029 [(match_operand:SI 0 "arith_reg_operand" "")
7030 (match_operand:SI 1 "arith_reg_operand" "")
7031 (match_operand:SI 2 "arith_reg_operand" "")
7032 (match_operand 3 "" "") (match_operand 4 "" "")]
7036 rtx reg = gen_reg_rtx (SImode);
7037 rtx reg2 = gen_reg_rtx (SImode);
7040 rtx reg = gen_reg_rtx (DImode);
7041 rtx reg2 = gen_reg_rtx (DImode);
7042 rtx reg3 = gen_reg_rtx (DImode);
7043 rtx reg4 = gen_reg_rtx (DImode);
7044 rtx reg5 = gen_reg_rtx (DImode);
7046 operands[0] = convert_modes (DImode, SImode, operands[0], 0);
7047 operands[1] = convert_modes (DImode, SImode, operands[1], 0);
7048 operands[2] = convert_modes (DImode, SImode, operands[2], 1);
7050 emit_jump_insn (gen_bgt_media (operands[4], operands[1], operands[0]));
7051 emit_move_insn (reg, gen_rtx_MINUS (DImode, operands[0], operands[1]));
7052 emit_jump_insn (gen_bgtu_media (operands[4], reg, operands[2]));
7053 emit_insn (gen_casesi_shift_media (reg2, reg, operands[3]));
7054 emit_move_insn (reg3, gen_datalabel_ref (gen_rtx_LABEL_REF
7055 (DImode, operands[3])));
7056 emit_insn (gen_casesi_load_media (reg4, reg3, reg2, operands[3]));
7057 emit_move_insn (reg5, gen_rtx_PLUS (DImode, reg3, reg4));
7058 emit_jump_insn (gen_casesi_jump_media (reg5, operands[3]));
7062 operands[1] = copy_to_mode_reg (SImode, operands[1]);
7063 operands[2] = copy_to_mode_reg (SImode, operands[2]);
7064 /* If optimizing, casesi_worker depends on the mode of the instruction
7065 before label it 'uses' - operands[3]. */
7066 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
7068 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
7070 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
7072 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
7073 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
7074 operands[3], but to lab. We will fix this up in
7075 machine_dependent_reorg. */
7080 (define_expand "casesi_0"
7081 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
7082 (set (match_dup 4) (minus:SI (match_dup 4)
7083 (match_operand:SI 1 "arith_operand" "")))
7085 (gtu:SI (match_dup 4)
7086 (match_operand:SI 2 "arith_reg_operand" "")))
7088 (if_then_else (ne (reg:SI T_REG)
7090 (label_ref (match_operand 3 "" ""))
7095 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
7096 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
7097 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
7099 (define_insn "casesi_worker_0"
7100 [(set (match_operand:SI 0 "register_operand" "=r,r")
7101 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
7102 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7103 (clobber (match_scratch:SI 3 "=X,1"))
7104 (clobber (match_scratch:SI 4 "=&z,z"))]
7109 [(set (match_operand:SI 0 "register_operand" "")
7110 (unspec:SI [(match_operand:SI 1 "register_operand" "")
7111 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7112 (clobber (match_scratch:SI 3 ""))
7113 (clobber (match_scratch:SI 4 ""))]
7114 "TARGET_SH1 && ! TARGET_SH2 && reload_completed"
7115 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
7116 (parallel [(set (match_dup 0)
7117 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
7118 (label_ref (match_dup 2))] UNSPEC_CASESI))
7119 (clobber (match_dup 3))])
7120 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
7121 "if (GET_CODE (operands[2]) == CODE_LABEL) LABEL_NUSES (operands[2])++;")
7124 [(set (match_operand:SI 0 "register_operand" "")
7125 (unspec:SI [(match_operand:SI 1 "register_operand" "")
7126 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7127 (clobber (match_scratch:SI 3 ""))
7128 (clobber (match_scratch:SI 4 ""))]
7129 "TARGET_SH2 && reload_completed"
7130 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
7131 (parallel [(set (match_dup 0)
7132 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
7133 (label_ref (match_dup 2))] UNSPEC_CASESI))
7134 (clobber (match_dup 3))])]
7135 "if (GET_CODE (operands[2]) == CODE_LABEL) LABEL_NUSES (operands[2])++;")
7137 (define_insn "casesi_worker_1"
7138 [(set (match_operand:SI 0 "register_operand" "=r,r")
7139 (unspec:SI [(reg:SI R0_REG)
7140 (match_operand:SI 1 "register_operand" "0,r")
7141 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7142 (clobber (match_scratch:SI 3 "=X,1"))]
7146 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
7148 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
7151 switch (GET_MODE (diff_vec))
7154 return \"shll2 %1\;mov.l @(r0,%1),%0\";
7156 return \"add %1,%1\;mov.w @(r0,%1),%0\";
7158 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
7159 return \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
7160 return \"mov.b @(r0,%1),%0\";
7165 [(set_attr "length" "4")])
7167 (define_insn "casesi_worker_2"
7168 [(set (match_operand:SI 0 "register_operand" "=r,r")
7169 (unspec:SI [(reg:SI R0_REG)
7170 (match_operand:SI 1 "register_operand" "0,r")
7171 (label_ref (match_operand 2 "" ""))
7172 (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))
7173 (clobber (match_operand:SI 4 "" "=X,1"))]
7174 "TARGET_SH2 && reload_completed && flag_pic"
7177 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
7180 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
7183 switch (GET_MODE (diff_vec))
7186 output_asm_insn (\"shll2 %1\", operands);
7187 load = \"mov.l @(r0,%1),%0\"; break;
7189 output_asm_insn (\"add %1,%1\", operands);
7190 load = \"mov.w @(r0,%1),%0\"; break;
7192 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
7193 load = \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
7195 load = \"mov.b @(r0,%1),%0\";
7200 output_asm_insn (\"add\tr0,%1\;mova\t%O3,r0\\n\", operands);
7203 [(set_attr "length" "8")])
7205 (define_insn "casesi_shift_media"
7206 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7207 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
7208 (unspec:DI [(label_ref:DI (match_operand 2 "" ""))]
7213 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
7215 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
7218 switch (GET_MODE (diff_vec))
7221 return \"shlli %1, 2, %0\";
7223 return \"shlli %1, 1, %0\";
7225 if (rtx_equal_p (operands[0], operands[1]))
7227 return \"add %1, r63, %0\";
7232 [(set_attr "type" "arith_media")])
7234 (define_insn "casesi_load_media"
7235 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7236 (mem:DI (unspec [(match_operand 1 "arith_reg_operand" "r")
7237 (match_operand 2 "arith_reg_operand" "r")
7238 (label_ref:DI (match_operand 3 "" ""))] 2)))]
7242 rtx diff_vec = PATTERN (next_real_insn (operands[3]));
7244 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
7247 switch (GET_MODE (diff_vec))
7250 return \"ldx.l %1, %2, %0\";
7253 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
7254 return \"ldx.uw %1, %2, %0\";
7256 return \"ldx.w %1, %2, %0\";
7258 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
7259 return \"ldx.ub %1, %2, %0\";
7260 return \"ldx.b %1, %2, %0\";
7265 [(set_attr "type" "load_media")])
7267 (define_expand "return"
7269 "reload_completed && ! sh_need_epilogue ()"
7274 emit_jump_insn (gen_return_media ());
7278 if (TARGET_SHCOMPACT
7279 && (current_function_args_info.call_cookie & CALL_COOKIE_RET_TRAMP (1)))
7281 emit_jump_insn (gen_shcompact_return_tramp ());
7286 (define_insn "*return_i"
7288 "TARGET_SH1 && ! (TARGET_SHCOMPACT
7289 && (current_function_args_info.call_cookie
7290 & CALL_COOKIE_RET_TRAMP (1)))
7291 && reload_completed"
7293 [(set_attr "type" "return")
7294 (set_attr "needs_delay_slot" "yes")])
7296 (define_expand "shcompact_return_tramp"
7299 && (current_function_args_info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
7302 rtx reg = gen_rtx_REG (Pmode, R0_REG);
7303 rtx sym = function_symbol (\"__GCC_shcompact_return_trampoline\");
7306 emit_insn (gen_symGOTPLT2reg (reg, sym));
7308 emit_move_insn (reg, sym);
7310 emit_jump_insn (gen_shcompact_return_tramp_i ());
7314 (define_insn "shcompact_return_tramp_i"
7315 [(parallel [(return) (use (reg:SI R0_REG))])]
7317 && (current_function_args_info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
7319 [(set_attr "type" "jump_ind")
7320 (set_attr "needs_delay_slot" "yes")])
7322 (define_insn "return_media_i"
7323 [(parallel [(return) (use (match_operand:DI 0 "target_reg_operand" "k"))])]
7324 "TARGET_SHMEDIA && reload_completed"
7326 [(set_attr "type" "jump_media")])
7328 (define_insn "return_media_rte"
7330 "TARGET_SHMEDIA && reload_completed && current_function_interrupt"
7332 [(set_attr "type" "jump_media")])
7334 (define_expand "return_media"
7336 "TARGET_SHMEDIA && reload_completed"
7339 int tr_regno = sh_media_register_for_return ();
7342 if (current_function_interrupt)
7344 emit_jump_insn (gen_return_media_rte ());
7349 rtx r18 = gen_rtx_REG (DImode, PR_MEDIA_REG);
7351 if (! call_really_used_regs[TR0_REG] || fixed_regs[TR0_REG])
7354 tr = gen_rtx_REG (DImode, tr_regno);
7355 emit_move_insn (tr, r18);
7358 tr = gen_rtx_REG (DImode, tr_regno);
7360 emit_jump_insn (gen_return_media_i (tr));
7364 (define_insn "shcompact_preserve_incoming_args"
7365 [(set (match_operand:SI 0 "register_operand" "+r")
7366 (unspec:SI [(match_dup 0)] UNSPEC_COMPACT_ARGS))]
7369 [(set_attr "length" "0")])
7371 (define_insn "shcompact_incoming_args"
7372 [(set (reg:SI R2_REG) (unspec:SI [(reg:SI R2_REG)] UNSPEC_COMPACT_ARGS))
7373 (set (reg:SI R3_REG) (unspec:SI [(reg:SI R3_REG)] UNSPEC_COMPACT_ARGS))
7374 (set (reg:SI R4_REG) (unspec:SI [(reg:SI R4_REG)] UNSPEC_COMPACT_ARGS))
7375 (set (reg:SI R5_REG) (unspec:SI [(reg:SI R5_REG)] UNSPEC_COMPACT_ARGS))
7376 (set (reg:SI R6_REG) (unspec:SI [(reg:SI R6_REG)] UNSPEC_COMPACT_ARGS))
7377 (set (reg:SI R7_REG) (unspec:SI [(reg:SI R7_REG)] UNSPEC_COMPACT_ARGS))
7378 (set (reg:SI R8_REG) (unspec:SI [(reg:SI R8_REG)] UNSPEC_COMPACT_ARGS))
7379 (set (reg:SI R9_REG) (unspec:SI [(reg:SI R9_REG)] UNSPEC_COMPACT_ARGS))
7380 (set (mem:BLK (reg:SI MACL_REG))
7381 (unspec:BLK [(reg:SI MACH_REG)] UNSPEC_COMPACT_ARGS))
7382 (use (reg:SI R0_REG))
7383 (clobber (reg:SI R0_REG))
7384 (clobber (reg:SI MACL_REG))
7385 (clobber (reg:SI MACH_REG))
7386 (clobber (reg:SI PR_REG))]
7389 [(set_attr "needs_delay_slot" "yes")])
7391 (define_insn "shmedia_save_restore_regs_compact"
7392 [(set (reg:SI SP_REG)
7393 (plus:SI (reg:SI SP_REG)
7394 (match_operand:SI 0 "immediate_operand" "i")))
7395 (use (reg:SI R0_REG))
7396 (clobber (reg:SI PR_REG))]
7398 && (INTVAL (operands[0]) == SHMEDIA_REGS_STACK_ADJUST ()
7399 || INTVAL (operands[0]) == - SHMEDIA_REGS_STACK_ADJUST ())"
7401 [(set_attr "needs_delay_slot" "yes")])
7403 (define_expand "prologue"
7406 "sh_expand_prologue (); DONE;")
7408 (define_expand "epilogue"
7413 sh_expand_epilogue (0);
7414 emit_jump_insn (gen_return ());
7418 (define_expand "eh_return"
7419 [(use (match_operand 0 "register_operand" ""))]
7422 rtx ra = operands[0];
7424 if (TARGET_SHMEDIA64)
7425 emit_insn (gen_eh_set_ra_di (ra));
7427 emit_insn (gen_eh_set_ra_si (ra));
7432 ;; Clobber the return address on the stack. We can't expand this
7433 ;; until we know where it will be put in the stack frame.
7435 (define_insn "eh_set_ra_si"
7436 [(unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_EH_RETURN)
7437 (clobber (match_scratch:SI 1 "=&r"))]
7438 "! TARGET_SHMEDIA64"
7441 (define_insn "eh_set_ra_di"
7442 [(unspec [(match_operand:DI 0 "register_operand" "r")] UNSPEC_EH_RETURN)
7443 (clobber (match_scratch:DI 1 "=&r"))]
7448 [(unspec [(match_operand 0 "register_operand" "")] UNSPEC_EH_RETURN)
7449 (clobber (match_scratch 1 ""))]
7454 sh_set_return_address (operands[0], operands[1]);
7458 (define_insn "blockage"
7459 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7462 [(set_attr "length" "0")])
7464 ;; ------------------------------------------------------------------------
7466 ;; ------------------------------------------------------------------------
7469 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
7470 (eq:SI (reg:SI T_REG) (const_int 1)))]
7473 [(set_attr "type" "arith")])
7475 (define_expand "seq"
7476 [(set (match_operand:SI 0 "arith_reg_operand" "")
7483 if (GET_MODE (operands[0]) != DImode)
7484 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7485 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7486 if (sh_compare_op1 != const0_rtx)
7487 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7488 ? GET_MODE (sh_compare_op0)
7489 : GET_MODE (sh_compare_op1),
7492 switch (GET_MODE (sh_compare_op0))
7495 emit_insn (gen_cmpeqdi_media (operands[0],
7496 sh_compare_op0, sh_compare_op1));
7500 if (! TARGET_SHMEDIA_FPU)
7502 emit_insn (gen_cmpeqsf_media (operands[0],
7503 sh_compare_op0, sh_compare_op1));
7507 if (! TARGET_SHMEDIA_FPU)
7509 emit_insn (gen_cmpeqdf_media (operands[0],
7510 sh_compare_op0, sh_compare_op1));
7518 if (sh_expand_t_scc (EQ, operands[0]))
7520 if (! currently_expanding_to_rtl)
7522 operands[1] = prepare_scc_operands (EQ);
7525 (define_expand "slt"
7526 [(set (match_operand:SI 0 "arith_reg_operand" "")
7533 if (GET_MODE (operands[0]) != DImode)
7534 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7535 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7536 if (sh_compare_op1 != const0_rtx)
7537 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7538 ? GET_MODE (sh_compare_op0)
7539 : GET_MODE (sh_compare_op1),
7542 switch (GET_MODE (sh_compare_op0))
7545 emit_insn (gen_cmpgtdi_media (operands[0],
7546 sh_compare_op1, sh_compare_op0));
7550 if (! TARGET_SHMEDIA_FPU)
7552 emit_insn (gen_cmpgtsf_media (operands[0],
7553 sh_compare_op1, sh_compare_op0));
7557 if (! TARGET_SHMEDIA_FPU)
7559 emit_insn (gen_cmpgtdf_media (operands[0],
7560 sh_compare_op1, sh_compare_op0));
7568 if (! currently_expanding_to_rtl)
7570 operands[1] = prepare_scc_operands (LT);
7573 (define_expand "sle"
7574 [(match_operand:SI 0 "arith_reg_operand" "")]
7578 rtx tmp = sh_compare_op0;
7582 if (GET_MODE (operands[0]) != DImode)
7583 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7584 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7585 if (sh_compare_op1 != const0_rtx)
7586 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7587 ? GET_MODE (sh_compare_op0)
7588 : GET_MODE (sh_compare_op1),
7591 switch (GET_MODE (sh_compare_op0))
7595 tmp = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
7597 emit_insn (gen_cmpgtdi_media (tmp,
7598 sh_compare_op0, sh_compare_op1));
7599 emit_insn (gen_cmpeqdi_media (operands[0], tmp, const0_rtx));
7604 if (! TARGET_SHMEDIA_FPU)
7606 emit_insn (gen_cmpgesf_media (operands[0],
7607 sh_compare_op1, sh_compare_op0));
7611 if (! TARGET_SHMEDIA_FPU)
7613 emit_insn (gen_cmpgedf_media (operands[0],
7614 sh_compare_op1, sh_compare_op0));
7623 sh_compare_op0 = sh_compare_op1;
7624 sh_compare_op1 = tmp;
7625 emit_insn (gen_sge (operands[0]));
7629 (define_expand "sgt"
7630 [(set (match_operand:SI 0 "arith_reg_operand" "")
7637 if (GET_MODE (operands[0]) != DImode)
7638 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7639 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7640 if (sh_compare_op1 != const0_rtx)
7641 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7642 ? GET_MODE (sh_compare_op0)
7643 : GET_MODE (sh_compare_op1),
7646 switch (GET_MODE (sh_compare_op0))
7649 emit_insn (gen_cmpgtdi_media (operands[0],
7650 sh_compare_op0, sh_compare_op1));
7654 if (! TARGET_SHMEDIA_FPU)
7656 emit_insn (gen_cmpgtsf_media (operands[0],
7657 sh_compare_op0, sh_compare_op1));
7661 if (! TARGET_SHMEDIA_FPU)
7663 emit_insn (gen_cmpgtdf_media (operands[0],
7664 sh_compare_op0, sh_compare_op1));
7672 if (! currently_expanding_to_rtl)
7674 operands[1] = prepare_scc_operands (GT);
7677 (define_expand "sge"
7678 [(set (match_operand:SI 0 "arith_reg_operand" "")
7685 if (GET_MODE (operands[0]) != DImode)
7686 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7687 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7688 if (sh_compare_op1 != const0_rtx)
7689 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7690 ? GET_MODE (sh_compare_op0)
7691 : GET_MODE (sh_compare_op1),
7694 switch (GET_MODE (sh_compare_op0))
7698 rtx tmp = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
7700 emit_insn (gen_cmpgtdi_media (tmp,
7701 sh_compare_op1, sh_compare_op0));
7702 emit_insn (gen_cmpeqdi_media (operands[0], tmp, const0_rtx));
7707 if (! TARGET_SHMEDIA_FPU)
7709 emit_insn (gen_cmpgesf_media (operands[0],
7710 sh_compare_op0, sh_compare_op1));
7714 if (! TARGET_SHMEDIA_FPU)
7716 emit_insn (gen_cmpgedf_media (operands[0],
7717 sh_compare_op0, sh_compare_op1));
7726 if (! currently_expanding_to_rtl)
7728 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
7732 rtx lab = gen_label_rtx ();
7733 prepare_scc_operands (EQ);
7734 emit_jump_insn (gen_branch_true (lab));
7735 prepare_scc_operands (GT);
7737 emit_insn (gen_movt (operands[0]));
7740 emit_insn (gen_movnegt (operands[0], prepare_scc_operands (LT)));
7743 operands[1] = prepare_scc_operands (GE);
7746 (define_expand "sgtu"
7747 [(set (match_operand:SI 0 "arith_reg_operand" "")
7754 if (GET_MODE (operands[0]) != DImode)
7755 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7756 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7757 if (sh_compare_op1 != const0_rtx)
7758 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7759 ? GET_MODE (sh_compare_op0)
7760 : GET_MODE (sh_compare_op1),
7763 emit_insn (gen_cmpgtudi_media (operands[0],
7764 sh_compare_op0, sh_compare_op1));
7767 if (! currently_expanding_to_rtl)
7769 operands[1] = prepare_scc_operands (GTU);
7772 (define_expand "sltu"
7773 [(set (match_operand:SI 0 "arith_reg_operand" "")
7780 if (GET_MODE (operands[0]) != DImode)
7781 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7782 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7783 if (sh_compare_op1 != const0_rtx)
7784 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7785 ? GET_MODE (sh_compare_op0)
7786 : GET_MODE (sh_compare_op1),
7789 emit_insn (gen_cmpgtudi_media (operands[0],
7790 sh_compare_op1, sh_compare_op0));
7793 if (! currently_expanding_to_rtl)
7795 operands[1] = prepare_scc_operands (LTU);
7798 (define_expand "sleu"
7799 [(set (match_operand:SI 0 "arith_reg_operand" "")
7808 if (GET_MODE (operands[0]) != DImode)
7809 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7810 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7811 if (sh_compare_op1 != const0_rtx)
7812 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7813 ? GET_MODE (sh_compare_op0)
7814 : GET_MODE (sh_compare_op1),
7817 tmp = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
7819 emit_insn (gen_cmpgtudi_media (tmp, sh_compare_op0, sh_compare_op1));
7820 emit_insn (gen_cmpeqdi_media (operands[0], tmp, const0_rtx));
7824 if (! currently_expanding_to_rtl)
7826 operands[1] = prepare_scc_operands (LEU);
7829 (define_expand "sgeu"
7830 [(set (match_operand:SI 0 "arith_reg_operand" "")
7839 if (GET_MODE (operands[0]) != DImode)
7840 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7841 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7842 if (sh_compare_op1 != const0_rtx)
7843 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7844 ? GET_MODE (sh_compare_op0)
7845 : GET_MODE (sh_compare_op1),
7848 tmp = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
7850 emit_insn (gen_cmpgtudi_media (tmp, sh_compare_op1, sh_compare_op0));
7851 emit_insn (gen_cmpeqdi_media (operands[0], tmp, const0_rtx));
7856 if (! currently_expanding_to_rtl)
7858 operands[1] = prepare_scc_operands (GEU);
7861 ;; sne moves the complement of the T reg to DEST like this:
7865 ;; This is better than xoring compare result with 1 because it does
7866 ;; not require r0 and further, the -1 may be CSE-ed or lifted out of a
7869 (define_expand "sne"
7870 [(set (match_dup 2) (const_int -1))
7871 (parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
7872 (neg:SI (plus:SI (match_dup 1)
7875 (ne:SI (ior:SI (match_dup 1) (match_dup 2))
7884 if (GET_MODE (operands[0]) != DImode)
7885 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7887 if (! TARGET_SHMEDIA_FPU && GET_MODE (sh_compare_op0) != DImode)
7890 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7891 if (sh_compare_op1 != const0_rtx)
7892 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7893 ? GET_MODE (sh_compare_op0)
7894 : GET_MODE (sh_compare_op1),
7897 tmp = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
7899 emit_insn (gen_seq (tmp));
7900 emit_insn (gen_cmpeqdi_media (operands[0], tmp, const0_rtx));
7905 if (sh_expand_t_scc (NE, operands[0]))
7907 if (! currently_expanding_to_rtl)
7909 operands[1] = prepare_scc_operands (EQ);
7910 operands[2] = gen_reg_rtx (SImode);
7913 (define_expand "sunordered"
7914 [(set (match_operand:DI 0 "arith_reg_operand" "")
7915 (unordered:DI (match_dup 1) (match_dup 2)))]
7916 "TARGET_SHMEDIA_FPU"
7919 operands[1] = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7920 operands[2] = force_reg (GET_MODE (sh_compare_op1), sh_compare_op1);
7923 ;; Use the same trick for FP sle / sge
7924 (define_expand "movnegt"
7925 [(set (match_dup 2) (const_int -1))
7926 (parallel [(set (match_operand 0 "" "")
7927 (neg:SI (plus:SI (match_dup 1)
7930 (ne:SI (ior:SI (match_operand 1 "" "") (match_dup 2))
7933 "operands[2] = gen_reg_rtx (SImode);")
7935 ;; Recognize mov #-1/negc/neg sequence, and change it to movt/add #-1.
7936 ;; This prevents a regression that occurred when we switched from xor to
7940 [(set (match_operand:SI 0 "arith_reg_operand" "")
7941 (plus:SI (reg:SI T_REG)
7944 [(set (match_dup 0) (eq:SI (reg:SI T_REG) (const_int 1)))
7945 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
7948 ;; -------------------------------------------------------------------------
7949 ;; Instructions to cope with inline literal tables
7950 ;; -------------------------------------------------------------------------
7952 ; 2 byte integer in line
7954 (define_insn "consttable_2"
7955 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
7956 (match_operand 1 "" "")]
7961 if (operands[1] != const0_rtx)
7962 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
7965 [(set_attr "length" "2")
7966 (set_attr "in_delay_slot" "no")])
7968 ; 4 byte integer in line
7970 (define_insn "consttable_4"
7971 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
7972 (match_operand 1 "" "")]
7977 if (operands[1] != const0_rtx)
7978 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
7981 [(set_attr "length" "4")
7982 (set_attr "in_delay_slot" "no")])
7984 ; 8 byte integer in line
7986 (define_insn "consttable_8"
7987 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
7988 (match_operand 1 "" "")]
7993 if (operands[1] != const0_rtx)
7994 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
7997 [(set_attr "length" "8")
7998 (set_attr "in_delay_slot" "no")])
8000 ; 4 byte floating point
8002 (define_insn "consttable_sf"
8003 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
8004 (match_operand 1 "" "")]
8009 if (operands[1] != const0_rtx)
8012 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
8013 assemble_real (d, SFmode, GET_MODE_ALIGNMENT (SFmode));
8017 [(set_attr "length" "4")
8018 (set_attr "in_delay_slot" "no")])
8020 ; 8 byte floating point
8022 (define_insn "consttable_df"
8023 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
8024 (match_operand 1 "" "")]
8029 if (operands[1] != const0_rtx)
8032 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
8033 assemble_real (d, DFmode, GET_MODE_ALIGNMENT (DFmode));
8037 [(set_attr "length" "8")
8038 (set_attr "in_delay_slot" "no")])
8040 ;; Alignment is needed for some constant tables; it may also be added for
8041 ;; Instructions at the start of loops, or after unconditional branches.
8042 ;; ??? We would get more accurate lengths if we did instruction
8043 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
8044 ;; here is too conservative.
8046 ; align to a two byte boundary
8048 (define_expand "align_2"
8049 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
8053 ; align to a four byte boundary
8054 ;; align_4 and align_log are instructions for the starts of loops, or
8055 ;; after unconditional branches, which may take up extra room.
8057 (define_expand "align_4"
8058 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
8062 ; align to a cache line boundary
8064 (define_insn "align_log"
8065 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
8068 [(set_attr "length" "0")
8069 (set_attr "in_delay_slot" "no")])
8071 ; emitted at the end of the literal table, used to emit the
8072 ; 32bit branch labels if needed.
8074 (define_insn "consttable_end"
8075 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
8077 "* return output_jump_label_table ();"
8078 [(set_attr "in_delay_slot" "no")])
8080 ; emitted at the end of the window in the literal table.
8082 (define_insn "consttable_window_end"
8083 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
8086 [(set_attr "length" "0")
8087 (set_attr "in_delay_slot" "no")])
8089 ;; -------------------------------------------------------------------------
8091 ;; -------------------------------------------------------------------------
8093 ;; String/block move insn.
8095 (define_expand "movmemsi"
8096 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
8097 (mem:BLK (match_operand:BLK 1 "" "")))
8098 (use (match_operand:SI 2 "nonmemory_operand" ""))
8099 (use (match_operand:SI 3 "immediate_operand" ""))
8100 (clobber (reg:SI PR_REG))
8101 (clobber (reg:SI R4_REG))
8102 (clobber (reg:SI R5_REG))
8103 (clobber (reg:SI R0_REG))])]
8104 "TARGET_SH1 && ! TARGET_SH5"
8107 if(expand_block_move (operands))
8112 (define_insn "block_move_real"
8113 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8114 (mem:BLK (reg:SI R5_REG)))
8115 (use (match_operand:SI 0 "arith_reg_operand" "r"))
8116 (clobber (reg:SI PR_REG))
8117 (clobber (reg:SI R0_REG))])]
8118 "TARGET_SH1 && ! TARGET_HARD_SH4"
8120 [(set_attr "type" "sfunc")
8121 (set_attr "needs_delay_slot" "yes")])
8123 (define_insn "block_lump_real"
8124 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8125 (mem:BLK (reg:SI R5_REG)))
8126 (use (match_operand:SI 0 "arith_reg_operand" "r"))
8127 (use (reg:SI R6_REG))
8128 (clobber (reg:SI PR_REG))
8129 (clobber (reg:SI T_REG))
8130 (clobber (reg:SI R4_REG))
8131 (clobber (reg:SI R5_REG))
8132 (clobber (reg:SI R6_REG))
8133 (clobber (reg:SI R0_REG))])]
8134 "TARGET_SH1 && ! TARGET_HARD_SH4"
8136 [(set_attr "type" "sfunc")
8137 (set_attr "needs_delay_slot" "yes")])
8139 (define_insn "block_move_real_i4"
8140 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8141 (mem:BLK (reg:SI R5_REG)))
8142 (use (match_operand:SI 0 "arith_reg_operand" "r"))
8143 (clobber (reg:SI PR_REG))
8144 (clobber (reg:SI R0_REG))
8145 (clobber (reg:SI R1_REG))
8146 (clobber (reg:SI R2_REG))])]
8149 [(set_attr "type" "sfunc")
8150 (set_attr "needs_delay_slot" "yes")])
8152 (define_insn "block_lump_real_i4"
8153 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8154 (mem:BLK (reg:SI R5_REG)))
8155 (use (match_operand:SI 0 "arith_reg_operand" "r"))
8156 (use (reg:SI R6_REG))
8157 (clobber (reg:SI PR_REG))
8158 (clobber (reg:SI T_REG))
8159 (clobber (reg:SI R4_REG))
8160 (clobber (reg:SI R5_REG))
8161 (clobber (reg:SI R6_REG))
8162 (clobber (reg:SI R0_REG))
8163 (clobber (reg:SI R1_REG))
8164 (clobber (reg:SI R2_REG))
8165 (clobber (reg:SI R3_REG))])]
8168 [(set_attr "type" "sfunc")
8169 (set_attr "needs_delay_slot" "yes")])
8171 ;; -------------------------------------------------------------------------
8172 ;; Floating point instructions.
8173 ;; -------------------------------------------------------------------------
8175 ;; ??? All patterns should have a type attribute.
8177 (define_expand "fpu_switch0"
8178 [(set (match_operand:SI 0 "" "") (match_dup 2))
8179 (set (match_dup 1) (mem:PSI (match_dup 0)))]
8180 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
8183 operands[1] = get_fpscr_rtx ();
8184 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
8186 operands[2] = legitimize_pic_address (operands[2], SImode,
8187 no_new_pseudos ? operands[0] : 0);
8190 (define_expand "fpu_switch1"
8191 [(set (match_operand:SI 0 "" "") (match_dup 2))
8192 (set (match_dup 3) (plus:SI (match_dup 0) (const_int 4)))
8193 (set (match_dup 1) (mem:PSI (match_dup 3)))]
8194 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
8197 operands[1] = get_fpscr_rtx ();
8198 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
8200 operands[2] = legitimize_pic_address (operands[2], SImode,
8201 no_new_pseudos ? operands[0] : 0);
8202 operands[3] = no_new_pseudos ? operands[0] : gen_reg_rtx (SImode);
8205 (define_expand "movpsi"
8206 [(set (match_operand:PSI 0 "register_operand" "")
8207 (match_operand:PSI 1 "general_movsrc_operand" ""))]
8208 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
8211 ;; The c / m alternative is a fake to guide reload to load directly into
8212 ;; fpscr, since reload doesn't know how to use post-increment.
8213 ;; GO_IF_LEGITIMATE_ADDRESS guards about bogus addresses before reload,
8214 ;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
8215 ;; predicate after reload.
8216 ;; The mac_gp type for r/!c might look a bit odd, but it actually schedules
8217 ;; like a mac -> gpr move.
8218 (define_insn "fpu_switch"
8219 [(set (match_operand:PSI 0 "general_movdst_operand" "=c,c,r,c,c,r,m,r,<")
8220 (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c,c"))]
8222 && (! reload_completed
8223 || true_regnum (operands[0]) != FPSCR_REG
8224 || GET_CODE (operands[1]) != MEM
8225 || GET_CODE (XEXP (operands[1], 0)) != PLUS)"
8227 ! precision stays the same
8236 [(set_attr "length" "0,2,2,4,2,2,2,2,2")
8237 (set_attr "type" "nil,mem_fpscr,load,mem_fpscr,gp_fpscr,move,store,mac_gp,store")])
8240 [(set (reg:PSI FPSCR_REG)
8241 (mem:PSI (match_operand:SI 0 "register_operand" "")))]
8242 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
8243 [(set (match_dup 0) (match_dup 0))]
8246 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
8247 gen_rtx_MEM (PSImode,
8248 gen_rtx_POST_INC (Pmode,
8250 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, operands[0], NULL_RTX);
8254 [(set (reg:PSI FPSCR_REG)
8255 (mem:PSI (match_operand:SI 0 "register_operand" "")))]
8256 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
8257 [(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))]
8260 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
8261 gen_rtx_MEM (PSImode,
8262 gen_rtx_POST_INC (Pmode,
8264 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, operands[0], NULL_RTX);
8267 ;; ??? This uses the fp unit, but has no type indicating that.
8268 ;; If we did that, this would either give a bogus latency or introduce
8269 ;; a bogus FIFO constraint.
8270 ;; Since this insn is currently only used for prologues/epilogues,
8271 ;; it is probably best to claim no function unit, which matches the
8273 (define_insn "toggle_sz"
8274 [(set (reg:PSI FPSCR_REG)
8275 (xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
8276 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
8278 [(set_attr "type" "fp") (set_attr "fp_set" "unknown")])
8280 ;; There's no way we can use it today, since optimize mode switching
8281 ;; doesn't enable us to know from which mode we're switching to the
8282 ;; mode it requests, to tell whether we can use a relative mode switch
8283 ;; (like toggle_pr) or an absolute switch (like loading fpscr from
8285 (define_insn "toggle_pr"
8286 [(set (reg:PSI FPSCR_REG)
8287 (xor:PSI (reg:PSI FPSCR_REG) (const_int 524288)))]
8288 "TARGET_SH4A_FP && ! TARGET_FPU_SINGLE"
8290 [(set_attr "type" "fp")])
8292 (define_expand "addsf3"
8293 [(set (match_operand:SF 0 "arith_reg_operand" "")
8294 (plus:SF (match_operand:SF 1 "arith_reg_operand" "")
8295 (match_operand:SF 2 "arith_reg_operand" "")))]
8296 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
8301 expand_sf_binop (&gen_addsf3_i, operands);
8306 (define_insn "*addsf3_media"
8307 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8308 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
8309 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8310 "TARGET_SHMEDIA_FPU"
8312 [(set_attr "type" "fparith_media")])
8314 (define_insn_and_split "unary_sf_op"
8315 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
8320 (parallel [(not:BI (match_operand 3 "const_int_operand" "n"))]))
8321 (match_operator:SF 2 "unary_float_operator"
8322 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
8323 (parallel [(match_operand 4
8324 "const_int_operand" "n")]))]))
8325 (parallel [(not:BI (match_dup 3)) (match_dup 3)])))]
8326 "TARGET_SHMEDIA_FPU"
8328 "TARGET_SHMEDIA_FPU && reload_completed"
8329 [(set (match_dup 5) (match_dup 6))]
8332 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
8333 rtx op1 = gen_rtx_REG (SFmode,
8334 (true_regnum (operands[1])
8335 + (INTVAL (operands[4]) ^ endian)));
8337 operands[7] = gen_rtx_REG (SFmode,
8338 (true_regnum (operands[0])
8339 + (INTVAL (operands[3]) ^ endian)));
8340 operands[6] = gen_rtx_fmt_e (GET_CODE (operands[2]), SFmode, op1);
8342 [(set_attr "type" "fparith_media")])
8344 (define_insn_and_split "binary_sf_op"
8345 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
8350 (parallel [(match_operand 7 "const_int_operand" "n")]))
8351 (match_operator:SF 3 "binary_float_operator"
8352 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
8353 (parallel [(match_operand 5
8354 "const_int_operand" "n")]))
8355 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
8356 (parallel [(match_operand 6
8357 "const_int_operand" "n")]))]))
8358 (parallel [(match_dup 7) (match_operand 4 "const_int_operand" "n")])))]
8359 "TARGET_SHMEDIA_FPU && INTVAL (operands[4]) != INTVAL (operands[7])"
8361 "&& reload_completed"
8362 [(set (match_dup 8) (match_dup 9))]
8365 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
8366 rtx op1 = gen_rtx_REG (SFmode,
8367 (true_regnum (operands[1])
8368 + (INTVAL (operands[5]) ^ endian)));
8369 rtx op2 = gen_rtx_REG (SFmode,
8370 (true_regnum (operands[2])
8371 + (INTVAL (operands[6]) ^ endian)));
8373 operands[8] = gen_rtx_REG (SFmode,
8374 (true_regnum (operands[0])
8375 + (INTVAL (operands[4]) ^ endian)));
8376 operands[9] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
8378 [(set_attr "type" "fparith_media")])
8380 (define_insn "addsf3_i"
8381 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
8382 (plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
8383 (match_operand:SF 2 "arith_reg_operand" "f")))
8384 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8387 [(set_attr "type" "fp")
8388 (set_attr "fp_mode" "single")])
8390 (define_expand "subsf3"
8391 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
8392 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
8393 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
8394 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
8399 expand_sf_binop (&gen_subsf3_i, operands);
8404 (define_insn "*subsf3_media"
8405 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8406 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
8407 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8408 "TARGET_SHMEDIA_FPU"
8410 [(set_attr "type" "fparith_media")])
8412 (define_insn "subsf3_i"
8413 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8414 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
8415 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
8416 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8419 [(set_attr "type" "fp")
8420 (set_attr "fp_mode" "single")])
8422 ;; Unfortunately, the combiner is unable to cope with the USE of the FPSCR
8423 ;; register in feeding fp instructions. Thus, we cannot generate fmac for
8424 ;; mixed-precision SH4 targets. To allow it to be still generated for the
8425 ;; SH3E, we use a separate insn for SH3E mulsf3.
8427 (define_expand "mulsf3"
8428 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
8429 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
8430 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
8431 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
8434 if (TARGET_SH4 || TARGET_SH2A_SINGLE)
8435 expand_sf_binop (&gen_mulsf3_i4, operands);
8436 else if (TARGET_SH2E)
8437 emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
8438 if (! TARGET_SHMEDIA)
8442 (define_insn "*mulsf3_media"
8443 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8444 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
8445 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8446 "TARGET_SHMEDIA_FPU"
8448 [(set_attr "type" "fparith_media")])
8450 (define_insn "mulsf3_i4"
8451 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8452 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
8453 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
8454 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8457 [(set_attr "type" "fp")
8458 (set_attr "fp_mode" "single")])
8460 (define_insn "mulsf3_ie"
8461 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8462 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
8463 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8464 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
8466 [(set_attr "type" "fp")])
8468 (define_insn "*mac_media"
8469 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8470 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
8471 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
8472 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
8473 "TARGET_SHMEDIA_FPU"
8475 [(set_attr "type" "fparith_media")])
8477 (define_insn "*macsf3"
8478 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8479 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
8480 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
8481 (match_operand:SF 3 "arith_reg_operand" "0")))
8482 (use (match_operand:PSI 4 "fpscr_operand" "c"))]
8483 "TARGET_SH2E && ! TARGET_SH4"
8485 [(set_attr "type" "fp")
8486 (set_attr "fp_mode" "single")])
8488 (define_expand "divsf3"
8489 [(set (match_operand:SF 0 "arith_reg_operand" "")
8490 (div:SF (match_operand:SF 1 "arith_reg_operand" "")
8491 (match_operand:SF 2 "arith_reg_operand" "")))]
8492 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
8497 expand_sf_binop (&gen_divsf3_i, operands);
8502 (define_insn "*divsf3_media"
8503 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8504 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
8505 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8506 "TARGET_SHMEDIA_FPU"
8508 [(set_attr "type" "fdiv_media")])
8510 (define_insn "divsf3_i"
8511 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
8512 (div:SF (match_operand:SF 1 "arith_reg_operand" "0")
8513 (match_operand:SF 2 "arith_reg_operand" "f")))
8514 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8517 [(set_attr "type" "fdiv")
8518 (set_attr "fp_mode" "single")])
8520 (define_insn "floatdisf2"
8521 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8522 (float:SF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
8523 "TARGET_SHMEDIA_FPU"
8525 [(set_attr "type" "fpconv_media")])
8527 (define_expand "floatsisf2"
8528 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
8529 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
8530 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
8533 if (TARGET_SH4 || TARGET_SH2A_SINGLE)
8535 emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
8540 (define_insn "*floatsisf2_media"
8541 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8542 (float:SF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
8543 "TARGET_SHMEDIA_FPU"
8545 [(set_attr "type" "fpconv_media")])
8547 (define_insn "floatsisf2_i4"
8548 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8549 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
8550 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8551 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
8553 [(set_attr "type" "fp")
8554 (set_attr "fp_mode" "single")])
8556 (define_insn "*floatsisf2_ie"
8557 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8558 (float:SF (match_operand:SI 1 "fpul_operand" "y")))]
8559 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
8561 [(set_attr "type" "fp")])
8563 (define_insn "fix_truncsfdi2"
8564 [(set (match_operand:DI 0 "fp_arith_reg_operand" "=f")
8565 (fix:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8566 "TARGET_SHMEDIA_FPU"
8568 [(set_attr "type" "fpconv_media")])
8570 (define_expand "fix_truncsfsi2"
8571 [(set (match_operand:SI 0 "fpul_operand" "=y")
8572 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8573 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
8576 if (TARGET_SH4 || TARGET_SH2A_SINGLE)
8578 emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
8583 (define_insn "*fix_truncsfsi2_media"
8584 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
8585 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8586 "TARGET_SHMEDIA_FPU"
8588 [(set_attr "type" "fpconv_media")])
8590 (define_insn "fix_truncsfsi2_i4"
8591 [(set (match_operand:SI 0 "fpul_operand" "=y")
8592 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
8593 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8594 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
8596 [(set_attr "type" "ftrc_s")
8597 (set_attr "fp_mode" "single")])
8599 ;; ??? This pattern is used nowhere. fix_truncsfsi2 always expands to
8600 ;; fix_truncsfsi2_i4.
8601 ;; (define_insn "fix_truncsfsi2_i4_2"
8602 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
8603 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
8604 ;; (use (reg:PSI FPSCR_REG))
8605 ;; (clobber (reg:SI FPUL_REG))]
8608 ;; [(set_attr "length" "4")
8609 ;; (set_attr "fp_mode" "single")])
8612 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
8613 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
8614 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
8615 ;; (clobber (reg:SI FPUL_REG))]
8617 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
8618 ;; (use (match_dup 2))])
8619 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
8621 (define_insn "*fixsfsi"
8622 [(set (match_operand:SI 0 "fpul_operand" "=y")
8623 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8624 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
8626 [(set_attr "type" "fp")])
8628 (define_insn "cmpgtsf_t"
8629 [(set (reg:SI T_REG)
8630 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
8631 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8632 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
8634 [(set_attr "type" "fp")
8635 (set_attr "fp_mode" "single")])
8637 (define_insn "cmpeqsf_t"
8638 [(set (reg:SI T_REG)
8639 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
8640 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8641 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
8643 [(set_attr "type" "fp")
8644 (set_attr "fp_mode" "single")])
8646 (define_insn "ieee_ccmpeqsf_t"
8647 [(set (reg:SI T_REG)
8648 (ior:SI (reg:SI T_REG)
8649 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
8650 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
8651 "TARGET_SH2E && TARGET_IEEE && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
8652 "* return output_ieee_ccmpeq (insn, operands);"
8653 [(set_attr "length" "4")])
8656 (define_insn "cmpgtsf_t_i4"
8657 [(set (reg:SI T_REG)
8658 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
8659 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
8660 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8661 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
8663 [(set_attr "type" "fp")
8664 (set_attr "fp_mode" "single")])
8666 (define_insn "cmpeqsf_t_i4"
8667 [(set (reg:SI T_REG)
8668 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
8669 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
8670 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8671 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
8673 [(set_attr "type" "fp")
8674 (set_attr "fp_mode" "single")])
8676 (define_insn "*ieee_ccmpeqsf_t_4"
8677 [(set (reg:SI T_REG)
8678 (ior:SI (reg:SI T_REG)
8679 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
8680 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
8681 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8682 "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_SINGLE)"
8683 "* return output_ieee_ccmpeq (insn, operands);"
8684 [(set_attr "length" "4")
8685 (set_attr "fp_mode" "single")])
8687 (define_insn "cmpeqsf_media"
8688 [(set (match_operand:DI 0 "register_operand" "=r")
8689 (eq:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")
8690 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8691 "TARGET_SHMEDIA_FPU"
8692 "fcmpeq.s %1, %2, %0"
8693 [(set_attr "type" "fcmp_media")])
8695 (define_insn "cmpgtsf_media"
8696 [(set (match_operand:DI 0 "register_operand" "=r")
8697 (gt:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")
8698 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8699 "TARGET_SHMEDIA_FPU"
8700 "fcmpgt.s %1, %2, %0"
8701 [(set_attr "type" "fcmp_media")])
8703 (define_insn "cmpgesf_media"
8704 [(set (match_operand:DI 0 "register_operand" "=r")
8705 (ge:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")
8706 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8707 "TARGET_SHMEDIA_FPU"
8708 "fcmpge.s %1, %2, %0"
8709 [(set_attr "type" "fcmp_media")])
8711 (define_insn "cmpunsf_media"
8712 [(set (match_operand:DI 0 "register_operand" "=r")
8713 (unordered:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")
8714 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8715 "TARGET_SHMEDIA_FPU"
8716 "fcmpun.s %1, %2, %0"
8717 [(set_attr "type" "fcmp_media")])
8719 (define_expand "cmpsf"
8720 [(set (reg:SI T_REG)
8721 (compare (match_operand:SF 0 "arith_operand" "")
8722 (match_operand:SF 1 "arith_operand" "")))]
8723 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
8726 sh_compare_op0 = operands[0];
8727 sh_compare_op1 = operands[1];
8731 (define_expand "negsf2"
8732 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
8733 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
8734 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
8739 expand_sf_unop (&gen_negsf2_i, operands);
8744 (define_insn "*negsf2_media"
8745 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8746 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8747 "TARGET_SHMEDIA_FPU"
8749 [(set_attr "type" "fmove_media")])
8751 (define_insn "negsf2_i"
8752 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8753 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
8754 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8757 [(set_attr "type" "fmove")
8758 (set_attr "fp_mode" "single")])
8760 (define_expand "sqrtsf2"
8761 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
8762 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
8763 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
8768 expand_sf_unop (&gen_sqrtsf2_i, operands);
8773 (define_insn "*sqrtsf2_media"
8774 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8775 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8776 "TARGET_SHMEDIA_FPU"
8778 [(set_attr "type" "fdiv_media")])
8780 (define_insn "sqrtsf2_i"
8781 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8782 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
8783 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8786 [(set_attr "type" "fdiv")
8787 (set_attr "fp_mode" "single")])
8789 (define_insn "rsqrtsf2"
8790 [(set (match_operand:SF 0 "register_operand" "=f")
8791 (div:SF (match_operand:SF 1 "immediate_operand" "i")
8792 (sqrt:SF (match_operand:SF 2 "register_operand" "0"))))
8793 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8794 "TARGET_SH4A_FP && flag_unsafe_math_optimizations
8795 && operands[1] == CONST1_RTX (SFmode)"
8797 [(set_attr "type" "fsrra")
8798 (set_attr "fp_mode" "single")])
8801 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
8803 (unspec:SF [(mult:SF
8804 (float:SF (match_operand:SI 1 "fpul_operand" "y"))
8805 (match_operand:SF 2 "immediate_operand" "i"))
8807 (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2))
8809 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8810 "TARGET_SH4A_FP && flag_unsafe_math_optimizations
8811 && operands[2] == sh_fsca_int2sf ()"
8813 [(set_attr "type" "fsca")
8814 (set_attr "fp_mode" "single")])
8816 (define_expand "sinsf2"
8817 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8818 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "")]
8820 "TARGET_SH4A_FP && flag_unsafe_math_optimizations"
8823 rtx scaled = gen_reg_rtx (SFmode);
8824 rtx truncated = gen_reg_rtx (SImode);
8825 rtx fsca = gen_reg_rtx (V2SFmode);
8826 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
8828 emit_sf_insn (gen_mulsf3 (scaled, operands[1], scale_reg));
8829 emit_sf_insn (gen_fix_truncsfsi2 (truncated, scaled));
8830 emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
8832 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 0));
8836 (define_expand "cossf2"
8837 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8838 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "")]
8840 "TARGET_SH4A_FP && flag_unsafe_math_optimizations"
8843 rtx scaled = gen_reg_rtx (SFmode);
8844 rtx truncated = gen_reg_rtx (SImode);
8845 rtx fsca = gen_reg_rtx (V2SFmode);
8846 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
8848 emit_sf_insn (gen_mulsf3 (scaled, operands[1], scale_reg));
8849 emit_sf_insn (gen_fix_truncsfsi2 (truncated, scaled));
8850 emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
8852 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4));
8856 (define_expand "sindf2"
8857 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
8858 (unspec:DF [(match_operand:DF 1 "fp_arith_reg_operand" "")]
8860 "TARGET_SH4A_FP && ! TARGET_FPU_SINGLE && flag_unsafe_math_optimizations"
8863 rtx scaled = gen_reg_rtx (DFmode);
8864 rtx truncated = gen_reg_rtx (SImode);
8865 rtx fsca = gen_reg_rtx (V2SFmode);
8866 rtx scale_reg = force_reg (DFmode, sh_fsca_df2int ());
8867 rtx sfresult = gen_reg_rtx (SFmode);
8869 emit_df_insn (gen_muldf3 (scaled, operands[1], scale_reg));
8870 emit_df_insn (gen_fix_truncdfsi2 (truncated, scaled));
8871 emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
8873 emit_move_insn (sfresult, gen_rtx_SUBREG (SFmode, fsca, 0));
8874 emit_df_insn (gen_extendsfdf2 (operands[0], sfresult));
8878 (define_expand "cosdf2"
8879 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
8880 (unspec:DF [(match_operand:DF 1 "fp_arith_reg_operand" "")]
8882 "TARGET_SH4A_FP && ! TARGET_FPU_SINGLE && flag_unsafe_math_optimizations"
8885 rtx scaled = gen_reg_rtx (DFmode);
8886 rtx truncated = gen_reg_rtx (SImode);
8887 rtx fsca = gen_reg_rtx (V2SFmode);
8888 rtx scale_reg = force_reg (DFmode, sh_fsca_df2int ());
8889 rtx sfresult = gen_reg_rtx (SFmode);
8891 emit_df_insn (gen_muldf3 (scaled, operands[1], scale_reg));
8892 emit_df_insn (gen_fix_truncdfsi2 (truncated, scaled));
8893 emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
8895 emit_move_insn (sfresult, gen_rtx_SUBREG (SFmode, fsca, 4));
8896 emit_df_insn (gen_extendsfdf2 (operands[0], sfresult));
8900 (define_expand "abssf2"
8901 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
8902 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
8903 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
8908 expand_sf_unop (&gen_abssf2_i, operands);
8913 (define_insn "*abssf2_media"
8914 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8915 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8916 "TARGET_SHMEDIA_FPU"
8918 [(set_attr "type" "fmove_media")])
8920 (define_insn "abssf2_i"
8921 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8922 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
8923 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8926 [(set_attr "type" "fmove")
8927 (set_attr "fp_mode" "single")])
8929 (define_expand "adddf3"
8930 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
8931 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
8932 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
8933 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
8936 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
8938 expand_df_binop (&gen_adddf3_i, operands);
8943 (define_insn "*adddf3_media"
8944 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8945 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
8946 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
8947 "TARGET_SHMEDIA_FPU"
8949 [(set_attr "type" "dfparith_media")])
8951 (define_insn "adddf3_i"
8952 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8953 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
8954 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
8955 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8956 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
8958 [(set_attr "type" "dfp_arith")
8959 (set_attr "fp_mode" "double")])
8961 (define_expand "subdf3"
8962 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
8963 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
8964 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
8965 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
8968 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
8970 expand_df_binop (&gen_subdf3_i, operands);
8975 (define_insn "*subdf3_media"
8976 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8977 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
8978 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
8979 "TARGET_SHMEDIA_FPU"
8981 [(set_attr "type" "dfparith_media")])
8983 (define_insn "subdf3_i"
8984 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8985 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
8986 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
8987 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8988 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
8990 [(set_attr "type" "dfp_arith")
8991 (set_attr "fp_mode" "double")])
8993 (define_expand "muldf3"
8994 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
8995 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
8996 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
8997 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
9000 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
9002 expand_df_binop (&gen_muldf3_i, operands);
9007 (define_insn "*muldf3_media"
9008 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9009 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
9010 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
9011 "TARGET_SHMEDIA_FPU"
9013 [(set_attr "type" "dfmul_media")])
9015 (define_insn "muldf3_i"
9016 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9017 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
9018 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9019 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
9020 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
9022 [(set_attr "type" "dfp_arith")
9023 (set_attr "fp_mode" "double")])
9025 (define_expand "divdf3"
9026 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9027 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9028 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9029 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
9032 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
9034 expand_df_binop (&gen_divdf3_i, operands);
9039 (define_insn "*divdf3_media"
9040 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9041 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
9042 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
9043 "TARGET_SHMEDIA_FPU"
9045 [(set_attr "type" "dfdiv_media")])
9047 (define_insn "divdf3_i"
9048 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9049 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
9050 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9051 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
9052 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
9054 [(set_attr "type" "dfdiv")
9055 (set_attr "fp_mode" "double")])
9057 (define_insn "floatdidf2"
9058 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9059 (float:DF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
9060 "TARGET_SHMEDIA_FPU"
9062 [(set_attr "type" "dfpconv_media")])
9064 (define_expand "floatsidf2"
9065 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9066 (float:DF (match_operand:SI 1 "fpul_operand" "")))]
9067 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
9070 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
9072 emit_df_insn (gen_floatsidf2_i (operands[0], operands[1],
9078 (define_insn "*floatsidf2_media"
9079 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9080 (float:DF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
9081 "TARGET_SHMEDIA_FPU"
9083 [(set_attr "type" "dfpconv_media")])
9085 (define_insn "floatsidf2_i"
9086 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9087 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
9088 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
9089 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
9091 [(set_attr "type" "dfp_conv")
9092 (set_attr "fp_mode" "double")])
9094 (define_insn "fix_truncdfdi2"
9095 [(set (match_operand:DI 0 "fp_arith_reg_operand" "=f")
9096 (fix:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
9097 "TARGET_SHMEDIA_FPU"
9099 [(set_attr "type" "dfpconv_media")])
9101 (define_expand "fix_truncdfsi2"
9102 [(set (match_operand:SI 0 "fpul_operand" "")
9103 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
9104 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
9107 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
9109 emit_df_insn (gen_fix_truncdfsi2_i (operands[0], operands[1],
9115 (define_insn "*fix_truncdfsi2_media"
9116 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
9117 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
9118 "TARGET_SHMEDIA_FPU"
9120 [(set_attr "type" "dfpconv_media")])
9122 (define_insn "fix_truncdfsi2_i"
9123 [(set (match_operand:SI 0 "fpul_operand" "=y")
9124 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9125 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
9126 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
9128 [(set_attr "type" "dfp_conv")
9129 (set_attr "dfp_comp" "no")
9130 (set_attr "fp_mode" "double")])
9132 ;; ??? This pattern is used nowhere. fix_truncdfsi2 always expands to
9133 ;; fix_truncdfsi2_i.
9134 ;; (define_insn "fix_truncdfsi2_i4"
9135 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
9136 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
9137 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
9138 ;; (clobber (reg:SI FPUL_REG))]
9141 ;; [(set_attr "length" "4")
9142 ;; (set_attr "fp_mode" "double")])
9145 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
9146 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
9147 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
9148 ;; (clobber (reg:SI FPUL_REG))]
9150 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
9151 ;; (use (match_dup 2))])
9152 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
9154 (define_insn "cmpgtdf_t"
9155 [(set (reg:SI T_REG)
9156 (gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
9157 (match_operand:DF 1 "arith_reg_operand" "f")))
9158 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
9159 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
9161 [(set_attr "type" "dfp_cmp")
9162 (set_attr "fp_mode" "double")])
9164 (define_insn "cmpeqdf_t"
9165 [(set (reg:SI T_REG)
9166 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
9167 (match_operand:DF 1 "arith_reg_operand" "f")))
9168 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
9169 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
9171 [(set_attr "type" "dfp_cmp")
9172 (set_attr "fp_mode" "double")])
9174 (define_insn "*ieee_ccmpeqdf_t"
9175 [(set (reg:SI T_REG)
9176 (ior:SI (reg:SI T_REG)
9177 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
9178 (match_operand:DF 1 "arith_reg_operand" "f"))))
9179 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
9180 "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_DOUBLE)"
9181 "* return output_ieee_ccmpeq (insn, operands);"
9182 [(set_attr "length" "4")
9183 (set_attr "fp_mode" "double")])
9185 (define_insn "cmpeqdf_media"
9186 [(set (match_operand:DI 0 "register_operand" "=r")
9187 (eq:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")
9188 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
9189 "TARGET_SHMEDIA_FPU"
9191 [(set_attr "type" "fcmp_media")])
9193 (define_insn "cmpgtdf_media"
9194 [(set (match_operand:DI 0 "register_operand" "=r")
9195 (gt:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")
9196 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
9197 "TARGET_SHMEDIA_FPU"
9199 [(set_attr "type" "fcmp_media")])
9201 (define_insn "cmpgedf_media"
9202 [(set (match_operand:DI 0 "register_operand" "=r")
9203 (ge:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")
9204 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
9205 "TARGET_SHMEDIA_FPU"
9207 [(set_attr "type" "fcmp_media")])
9209 (define_insn "cmpundf_media"
9210 [(set (match_operand:DI 0 "register_operand" "=r")
9211 (unordered:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")
9212 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
9213 "TARGET_SHMEDIA_FPU"
9215 [(set_attr "type" "fcmp_media")])
9217 (define_expand "cmpdf"
9218 [(set (reg:SI T_REG)
9219 (compare (match_operand:DF 0 "arith_operand" "")
9220 (match_operand:DF 1 "arith_operand" "")))]
9221 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
9224 sh_compare_op0 = operands[0];
9225 sh_compare_op1 = operands[1];
9229 (define_expand "negdf2"
9230 [(set (match_operand:DF 0 "arith_reg_operand" "")
9231 (neg:DF (match_operand:DF 1 "arith_reg_operand" "")))]
9232 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
9235 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
9237 expand_df_unop (&gen_negdf2_i, operands);
9242 (define_insn "*negdf2_media"
9243 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9244 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
9245 "TARGET_SHMEDIA_FPU"
9247 [(set_attr "type" "fmove_media")])
9249 (define_insn "negdf2_i"
9250 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
9251 (neg:DF (match_operand:DF 1 "arith_reg_operand" "0")))
9252 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
9253 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
9255 [(set_attr "type" "fmove")
9256 (set_attr "fp_mode" "double")])
9258 (define_expand "sqrtdf2"
9259 [(set (match_operand:DF 0 "arith_reg_operand" "")
9260 (sqrt:DF (match_operand:DF 1 "arith_reg_operand" "")))]
9261 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
9264 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
9266 expand_df_unop (&gen_sqrtdf2_i, operands);
9271 (define_insn "*sqrtdf2_media"
9272 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9273 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
9274 "TARGET_SHMEDIA_FPU"
9276 [(set_attr "type" "dfdiv_media")])
9278 (define_insn "sqrtdf2_i"
9279 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
9280 (sqrt:DF (match_operand:DF 1 "arith_reg_operand" "0")))
9281 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
9282 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
9284 [(set_attr "type" "dfdiv")
9285 (set_attr "fp_mode" "double")])
9287 (define_expand "absdf2"
9288 [(set (match_operand:DF 0 "arith_reg_operand" "")
9289 (abs:DF (match_operand:DF 1 "arith_reg_operand" "")))]
9290 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
9293 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
9295 expand_df_unop (&gen_absdf2_i, operands);
9300 (define_insn "*absdf2_media"
9301 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9302 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
9303 "TARGET_SHMEDIA_FPU"
9305 [(set_attr "type" "fmove_media")])
9307 (define_insn "absdf2_i"
9308 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
9309 (abs:DF (match_operand:DF 1 "arith_reg_operand" "0")))
9310 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
9311 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
9313 [(set_attr "type" "fmove")
9314 (set_attr "fp_mode" "double")])
9316 (define_expand "extendsfdf2"
9317 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9318 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
9319 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
9322 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
9324 emit_df_insn (gen_extendsfdf2_i4 (operands[0], operands[1],
9330 (define_insn "*extendsfdf2_media"
9331 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9332 (float_extend:DF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
9333 "TARGET_SHMEDIA_FPU"
9335 [(set_attr "type" "dfpconv_media")])
9337 (define_insn "extendsfdf2_i4"
9338 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9339 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
9340 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
9341 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
9343 [(set_attr "type" "fp")
9344 (set_attr "fp_mode" "double")])
9346 (define_expand "truncdfsf2"
9347 [(set (match_operand:SF 0 "fpul_operand" "")
9348 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
9349 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
9352 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
9354 emit_df_insn (gen_truncdfsf2_i4 (operands[0], operands[1],
9360 (define_insn "*truncdfsf2_media"
9361 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9362 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
9363 "TARGET_SHMEDIA_FPU"
9365 [(set_attr "type" "dfpconv_media")])
9367 (define_insn "truncdfsf2_i4"
9368 [(set (match_operand:SF 0 "fpul_operand" "=y")
9369 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9370 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
9371 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
9373 [(set_attr "type" "fp")
9374 (set_attr "fp_mode" "double")])
9376 ;; Bit field extract patterns. These give better code for packed bitfields,
9377 ;; because they allow auto-increment addresses to be generated.
9379 (define_expand "insv"
9380 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
9381 (match_operand:SI 1 "immediate_operand" "")
9382 (match_operand:SI 2 "immediate_operand" ""))
9383 (match_operand:SI 3 "general_operand" ""))]
9384 "TARGET_SH1 && ! TARGET_LITTLE_ENDIAN"
9387 rtx addr_target, orig_address, shift_reg, qi_val;
9388 HOST_WIDE_INT bitsize, size, v = 0;
9389 rtx x = operands[3];
9391 /* ??? expmed doesn't care for non-register predicates. */
9392 if (! memory_operand (operands[0], VOIDmode)
9393 || ! immediate_operand (operands[1], VOIDmode)
9394 || ! immediate_operand (operands[2], VOIDmode)
9395 || ! general_operand (x, VOIDmode))
9397 /* If this isn't a 16 / 24 / 32 bit field, or if
9398 it doesn't start on a byte boundary, then fail. */
9399 bitsize = INTVAL (operands[1]);
9400 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0
9401 || (INTVAL (operands[2]) % 8) != 0)
9405 orig_address = XEXP (operands[0], 0);
9406 shift_reg = gen_reg_rtx (SImode);
9407 if (GET_CODE (x) == CONST_INT)
9410 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
9414 emit_insn (gen_movsi (shift_reg, operands[3]));
9415 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
9417 addr_target = copy_addr_to_reg (plus_constant (orig_address, size - 1));
9419 operands[0] = replace_equiv_address (operands[0], addr_target);
9420 emit_insn (gen_movqi (operands[0], qi_val));
9424 if (GET_CODE (x) == CONST_INT)
9426 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
9429 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
9430 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
9432 emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
9433 emit_insn (gen_movqi (operands[0], qi_val));
9439 (define_insn "movua"
9440 [(set (match_operand:SI 0 "register_operand" "=z")
9441 (sign_extract:SI (match_operand:SI 1 "unaligned_load_operand" "Sua>")
9442 (const_int 32) (const_int 0)))]
9445 [(set_attr "type" "movua")])
9447 ;; We shouldn't need this, but cse replaces increments with references
9448 ;; to other regs before flow has a chance to create post_inc
9449 ;; addressing modes, and only postreload's cse_move2add brings the
9450 ;; increments back to a usable form.
9452 [(set (match_operand:SI 0 "register_operand" "")
9453 (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
9454 (const_int 32) (const_int 0)))
9455 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
9456 "TARGET_SH4A_ARCH && REGNO (operands[0]) != REGNO (operands[1])"
9457 [(set (match_operand:SI 0 "register_operand" "")
9458 (sign_extract:SI (mem:SI (post_inc:SI
9459 (match_operand:SI 1 "register_operand" "")))
9460 (const_int 32) (const_int 0)))]
9463 (define_expand "extv"
9464 [(set (match_operand:SI 0 "register_operand" "")
9465 (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
9466 (match_operand 2 "const_int_operand" "")
9467 (match_operand 3 "const_int_operand" "")))]
9470 if (TARGET_SH4A_ARCH
9471 && INTVAL (operands[2]) == 32
9472 && INTVAL (operands[3]) == -24 * (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
9473 && GET_CODE (operands[1]) == MEM && MEM_ALIGN (operands[1]) < 32)
9475 emit_insn (gen_movua (operands[0],
9476 adjust_address (operands[1], SImode, 0)));
9483 (define_expand "extzv"
9484 [(set (match_operand:SI 0 "register_operand" "")
9485 (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
9486 (match_operand 2 "const_int_operand" "")
9487 (match_operand 3 "const_int_operand" "")))]
9490 if (TARGET_SH4A_ARCH
9491 && INTVAL (operands[2]) == 32
9492 && INTVAL (operands[3]) == -24 * (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
9493 && GET_CODE (operands[1]) == MEM && MEM_ALIGN (operands[1]) < 32)
9495 emit_insn (gen_movua (operands[0],
9496 adjust_address (operands[1], SImode, 0)));
9504 ;; -------------------------------------------------------------------------
9506 ;; -------------------------------------------------------------------------
9508 ;; This matches cases where a stack pointer increment at the start of the
9509 ;; epilogue combines with a stack slot read loading the return value.
9512 [(set (match_operand:SI 0 "arith_reg_operand" "")
9513 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
9514 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
9515 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])"
9518 ;; See the comment on the dt combiner pattern above.
9521 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
9522 (plus:SI (match_dup 0)
9525 (eq:SI (match_dup 0)
9530 ;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn'
9531 ;; to `mov #k,r0; mov.l @(r0,r15),rn'. These sequences are generated by
9532 ;; reload when the constant is too large for a reg+offset address.
9534 ;; ??? We would get much better code if this was done in reload. This would
9535 ;; require modifying find_reloads_address to recognize that if the constant
9536 ;; is out-of-range for an immediate add, then we get better code by reloading
9537 ;; the constant into a register than by reloading the sum into a register,
9538 ;; since the former is one instruction shorter if the address does not need
9539 ;; to be offsettable. Unfortunately this does not work, because there is
9540 ;; only one register, r0, that can be used as an index register. This register
9541 ;; is also the function return value register. So, if we try to force reload
9542 ;; to use double-reg addresses, then we end up with some instructions that
9543 ;; need to use r0 twice. The only way to fix this is to change the calling
9544 ;; convention so that r0 is not used to return values.
9547 [(set (match_operand:SI 0 "register_operand" "=r")
9548 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9549 (set (mem:SI (match_dup 0))
9550 (match_operand:SI 2 "general_movsrc_operand" ""))]
9551 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
9552 "mov.l %2,@(%0,%1)")
9555 [(set (match_operand:SI 0 "register_operand" "=r")
9556 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9557 (set (match_operand:SI 2 "general_movdst_operand" "")
9558 (mem:SI (match_dup 0)))]
9559 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
9560 "mov.l @(%0,%1),%2")
9563 [(set (match_operand:SI 0 "register_operand" "=r")
9564 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9565 (set (mem:HI (match_dup 0))
9566 (match_operand:HI 2 "general_movsrc_operand" ""))]
9567 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
9568 "mov.w %2,@(%0,%1)")
9571 [(set (match_operand:SI 0 "register_operand" "=r")
9572 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9573 (set (match_operand:HI 2 "general_movdst_operand" "")
9574 (mem:HI (match_dup 0)))]
9575 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
9576 "mov.w @(%0,%1),%2")
9579 [(set (match_operand:SI 0 "register_operand" "=r")
9580 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9581 (set (mem:QI (match_dup 0))
9582 (match_operand:QI 2 "general_movsrc_operand" ""))]
9583 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
9584 "mov.b %2,@(%0,%1)")
9587 [(set (match_operand:SI 0 "register_operand" "=r")
9588 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9589 (set (match_operand:QI 2 "general_movdst_operand" "")
9590 (mem:QI (match_dup 0)))]
9591 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
9592 "mov.b @(%0,%1),%2")
9595 [(set (match_operand:SI 0 "register_operand" "=r")
9596 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9597 (set (mem:SF (match_dup 0))
9598 (match_operand:SF 2 "general_movsrc_operand" ""))]
9599 "TARGET_SH1 && REGNO (operands[0]) == 0
9600 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
9601 || (GET_CODE (operands[2]) == SUBREG
9602 && REGNO (SUBREG_REG (operands[2])) < 16))
9603 && reg_unused_after (operands[0], insn)"
9604 "mov.l %2,@(%0,%1)")
9607 [(set (match_operand:SI 0 "register_operand" "=r")
9608 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9609 (set (match_operand:SF 2 "general_movdst_operand" "")
9611 (mem:SF (match_dup 0)))]
9612 "TARGET_SH1 && REGNO (operands[0]) == 0
9613 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
9614 || (GET_CODE (operands[2]) == SUBREG
9615 && REGNO (SUBREG_REG (operands[2])) < 16))
9616 && reg_unused_after (operands[0], insn)"
9617 "mov.l @(%0,%1),%2")
9620 [(set (match_operand:SI 0 "register_operand" "=r")
9621 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9622 (set (mem:SF (match_dup 0))
9623 (match_operand:SF 2 "general_movsrc_operand" ""))]
9624 "TARGET_SH2E && REGNO (operands[0]) == 0
9625 && ((GET_CODE (operands[2]) == REG
9626 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
9627 || (GET_CODE (operands[2]) == SUBREG
9628 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
9629 && reg_unused_after (operands[0], insn)"
9630 "fmov{.s|} %2,@(%0,%1)")
9633 [(set (match_operand:SI 0 "register_operand" "=r")
9634 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9635 (set (match_operand:SF 2 "general_movdst_operand" "")
9637 (mem:SF (match_dup 0)))]
9638 "TARGET_SH2E && REGNO (operands[0]) == 0
9639 && ((GET_CODE (operands[2]) == REG
9640 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
9641 || (GET_CODE (operands[2]) == SUBREG
9642 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
9643 && reg_unused_after (operands[0], insn)"
9644 "fmov{.s|} @(%0,%1),%2")
9646 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF). */
9647 (define_insn "sp_switch_1"
9654 xoperands[0] = sp_switch;
9655 output_asm_insn (\"mov.l r0,@-r15\;mov.l %0,r0\", xoperands);
9656 output_asm_insn (\"mov.l @r0,r0\;mov.l r15,@-r0\", xoperands);
9657 return \"mov r0,r15\";
9659 [(set_attr "length" "10")])
9661 ;; Switch back to the original stack for interrupt functions with the
9662 ;; sp_switch attribute. */
9663 (define_insn "sp_switch_2"
9666 "mov.l @r15+,r15\;mov.l @r15+,r0"
9667 [(set_attr "length" "4")])
9669 ;; Integer vector moves
9671 (define_expand "movv8qi"
9672 [(set (match_operand:V8QI 0 "general_movdst_operand" "")
9673 (match_operand:V8QI 1 "general_movsrc_operand" ""))]
9675 "{ if (prepare_move_operands (operands, V8QImode)) DONE; }")
9677 (define_insn "movv8qi_i"
9678 [(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m")
9679 (match_operand:V8QI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
9681 && (register_operand (operands[0], V8QImode)
9682 || sh_register_operand (operands[1], V8QImode))"
9689 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
9690 (set_attr "length" "4,4,16,4,4")])
9693 [(set (match_operand:V8QI 0 "arith_reg_dest" "")
9694 (subreg:V8QI (const_int 0) 0))]
9697 (const_vector:V8QI [(const_int 0) (const_int 0) (const_int 0)
9698 (const_int 0) (const_int 0) (const_int 0)
9699 (const_int 0) (const_int 0)]))])
9702 [(set (match_operand 0 "arith_reg_dest" "")
9703 (match_operand 1 "sh_rep_vec" ""))]
9704 "TARGET_SHMEDIA && reload_completed
9705 && GET_MODE (operands[0]) == GET_MODE (operands[1])
9706 && sh_vector_mode_supported_p (GET_MODE (operands[0]))
9707 && GET_MODE_SIZE (GET_MODE (operands[0])) == 8
9708 && (XVECEXP (operands[1], 0, 0) != const0_rtx
9709 || XVECEXP (operands[1], 0, 1) != const0_rtx)
9710 && (XVECEXP (operands[1], 0, 0) != constm1_rtx
9711 || XVECEXP (operands[1], 0, 1) != constm1_rtx)"
9712 [(set (match_dup 0) (match_dup 1))
9716 int unit_size = GET_MODE_UNIT_SIZE (GET_MODE (operands[1]));
9717 rtx elt1 = XVECEXP (operands[1], 0, 1);
9720 operands[2] = gen_mshflo_l (operands[0], operands[0], operands[0]);
9724 operands[0] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
9725 operands[2] = gen_mperm_w0 (operands[0], operands[0]);
9727 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
9728 operands[1] = XVECEXP (operands[1], 0, 0);
9731 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (elt1) == CONST_INT)
9733 = GEN_INT (TARGET_LITTLE_ENDIAN
9734 ? (INTVAL (operands[1]) & 0xff) + (INTVAL (elt1) << 8)
9735 : (INTVAL (operands[1]) << 8) + (INTVAL (elt1) & 0xff));
9738 operands[0] = gen_rtx_REG (V2QImode, true_regnum (operands[0]));
9740 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, operands[1], elt1));
9746 [(set (match_operand 0 "arith_reg_dest" "")
9747 (match_operand 1 "sh_const_vec" ""))]
9748 "TARGET_SHMEDIA && reload_completed
9749 && GET_MODE (operands[0]) == GET_MODE (operands[1])
9750 && sh_vector_mode_supported_p (GET_MODE (operands[0]))
9751 && operands[1] != CONST0_RTX (GET_MODE (operands[1]))"
9752 [(set (match_dup 0) (match_dup 1))]
9755 rtx v = operands[1];
9756 enum machine_mode new_mode
9757 = mode_for_size (GET_MODE_BITSIZE (GET_MODE (v)), MODE_INT, 0);
9759 operands[0] = gen_rtx_REG (new_mode, true_regnum (operands[0]));
9761 = simplify_subreg (new_mode, operands[1], GET_MODE (operands[1]), 0);
9764 (define_expand "movv2hi"
9765 [(set (match_operand:V2HI 0 "general_movdst_operand" "")
9766 (match_operand:V2HI 1 "general_movsrc_operand" ""))]
9768 "{ if (prepare_move_operands (operands, V2HImode)) DONE; }")
9770 (define_insn "movv2hi_i"
9771 [(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m")
9772 (match_operand:V2HI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
9774 && (register_operand (operands[0], V2HImode)
9775 || sh_register_operand (operands[1], V2HImode))"
9782 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
9783 (set_attr "length" "4,4,16,4,4")])
9785 (define_expand "movv4hi"
9786 [(set (match_operand:V4HI 0 "general_movdst_operand" "")
9787 (match_operand:V4HI 1 "general_movsrc_operand" ""))]
9789 "{ if (prepare_move_operands (operands, V4HImode)) DONE; }")
9791 (define_insn "movv4hi_i"
9792 [(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m")
9793 (match_operand:V4HI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
9795 && (register_operand (operands[0], V4HImode)
9796 || sh_register_operand (operands[1], V4HImode))"
9803 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
9804 (set_attr "length" "4,4,16,4,4")])
9806 (define_expand "movv2si"
9807 [(set (match_operand:V2SI 0 "general_movdst_operand" "")
9808 (match_operand:V2SI 1 "general_movsrc_operand" ""))]
9810 "{ if (prepare_move_operands (operands, V2SImode)) DONE; }")
9812 (define_insn "movv2si_i"
9813 [(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m")
9814 (match_operand:V2SI 1 "general_movsrc_operand" "r,I16C16Z,nW,m,rlZ"))]
9816 && (register_operand (operands[0], V2SImode)
9817 || sh_register_operand (operands[1], V2SImode))"
9824 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
9825 (set_attr "length" "4,4,16,4,4")])
9827 ;; Multimedia Intrinsics
9829 (define_insn "absv2si2"
9830 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9831 (abs:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")))]
9834 [(set_attr "type" "mcmp_media")])
9836 (define_insn "absv4hi2"
9837 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9838 (abs:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")))]
9841 [(set_attr "type" "mcmp_media")])
9843 (define_insn "addv2si3"
9844 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9845 (plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
9846 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
9849 [(set_attr "type" "arith_media")])
9851 (define_insn "addv4hi3"
9852 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9853 (plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
9854 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
9857 [(set_attr "type" "arith_media")])
9859 (define_insn "ssaddv2si3"
9860 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9861 (ss_plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
9862 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
9864 "madds.l %1, %2, %0"
9865 [(set_attr "type" "mcmp_media")])
9867 (define_insn "usaddv8qi3"
9868 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
9869 (us_plus:V8QI (match_operand:V8QI 1 "arith_reg_operand" "%r")
9870 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
9872 "madds.ub %1, %2, %0"
9873 [(set_attr "type" "mcmp_media")])
9875 (define_insn "ssaddv4hi3"
9876 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9877 (ss_plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
9878 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
9880 "madds.w %1, %2, %0"
9881 [(set_attr "type" "mcmp_media")])
9883 (define_insn "negcmpeqv8qi"
9884 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
9885 (neg:V8QI (eq:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
9886 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
9888 "mcmpeq.b %N1, %N2, %0"
9889 [(set_attr "type" "mcmp_media")])
9891 (define_insn "negcmpeqv2si"
9892 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9893 (neg:V2SI (eq:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
9894 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
9896 "mcmpeq.l %N1, %N2, %0"
9897 [(set_attr "type" "mcmp_media")])
9899 (define_insn "negcmpeqv4hi"
9900 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9901 (neg:V4HI (eq:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
9902 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
9904 "mcmpeq.w %N1, %N2, %0"
9905 [(set_attr "type" "mcmp_media")])
9907 (define_insn "negcmpgtuv8qi"
9908 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
9909 (neg:V8QI (gtu:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
9910 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
9912 "mcmpgt.ub %N1, %N2, %0"
9913 [(set_attr "type" "mcmp_media")])
9915 (define_insn "negcmpgtv2si"
9916 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9917 (neg:V2SI (gt:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
9918 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
9920 "mcmpgt.l %N1, %N2, %0"
9921 [(set_attr "type" "mcmp_media")])
9923 (define_insn "negcmpgtv4hi"
9924 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9925 (neg:V4HI (gt:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
9926 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
9928 "mcmpgt.w %N1, %N2, %0"
9929 [(set_attr "type" "mcmp_media")])
9932 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
9933 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
9934 (match_operand:DI 2 "arith_reg_operand" "r"))
9935 (and:DI (match_operand:DI 3 "arith_reg_operand" "0")
9936 (not:DI (match_dup 2)))))]
9939 [(set_attr "type" "arith_media")])
9941 (define_insn "mcnvs_lw"
9942 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9944 (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ"))
9945 (ss_truncate:V2HI (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
9947 "mcnvs.lw %N1, %N2, %0"
9948 [(set_attr "type" "mcmp_media")])
9950 (define_insn "mcnvs_wb"
9951 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
9953 (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
9954 (ss_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
9956 "mcnvs.wb %N1, %N2, %0"
9957 [(set_attr "type" "mcmp_media")])
9959 (define_insn "mcnvs_wub"
9960 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
9962 (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
9963 (us_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
9965 "mcnvs.wub %N1, %N2, %0"
9966 [(set_attr "type" "mcmp_media")])
9968 (define_insn "mextr_rl"
9969 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
9970 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
9971 (match_operand:HI 3 "mextr_bit_offset" "i"))
9972 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
9973 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
9974 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
9977 static char templ[16];
9979 sprintf (templ, \"mextr%d\\t%%N1, %%N2, %%0\",
9980 (int) INTVAL (operands[3]) >> 3);
9983 [(set_attr "type" "arith_media")])
9985 (define_insn "*mextr_lr"
9986 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
9987 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
9988 (match_operand:HI 3 "mextr_bit_offset" "i"))
9989 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
9990 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
9991 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
9994 static char templ[16];
9996 sprintf (templ, \"mextr%d\\t%%N2, %%N1, %%0\",
9997 (int) INTVAL (operands[4]) >> 3);
10000 [(set_attr "type" "arith_media")])
10002 ; mextrN can be modelled with vec_select / vec_concat, but the selection
10003 ; vector then varies depending on endianness.
10004 (define_expand "mextr1"
10005 [(match_operand:DI 0 "arith_reg_dest" "")
10006 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
10007 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
10011 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
10012 GEN_INT (1 * 8), GEN_INT (7 * 8)));
10016 (define_expand "mextr2"
10017 [(match_operand:DI 0 "arith_reg_dest" "")
10018 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
10019 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
10023 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
10024 GEN_INT (2 * 8), GEN_INT (6 * 8)));
10028 (define_expand "mextr3"
10029 [(match_operand:DI 0 "arith_reg_dest" "")
10030 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
10031 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
10035 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
10036 GEN_INT (3 * 8), GEN_INT (5 * 8)));
10040 (define_expand "mextr4"
10041 [(match_operand:DI 0 "arith_reg_dest" "")
10042 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
10043 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
10047 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
10048 GEN_INT (4 * 8), GEN_INT (4 * 8)));
10052 (define_expand "mextr5"
10053 [(match_operand:DI 0 "arith_reg_dest" "")
10054 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
10055 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
10059 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
10060 GEN_INT (5 * 8), GEN_INT (3 * 8)));
10064 (define_expand "mextr6"
10065 [(match_operand:DI 0 "arith_reg_dest" "")
10066 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
10067 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
10071 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
10072 GEN_INT (6 * 8), GEN_INT (2 * 8)));
10076 (define_expand "mextr7"
10077 [(match_operand:DI 0 "arith_reg_dest" "")
10078 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
10079 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
10083 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
10084 GEN_INT (7 * 8), GEN_INT (1 * 8)));
10088 (define_expand "mmacfx_wl"
10089 [(match_operand:V2SI 0 "arith_reg_dest" "")
10090 (match_operand:V2HI 1 "extend_reg_operand" "")
10091 (match_operand:V2HI 2 "extend_reg_operand" "")
10092 (match_operand:V2SI 3 "arith_reg_operand" "")]
10096 emit_insn (gen_mmacfx_wl_i (operands[0], operands[3],
10097 operands[1], operands[2]));
10101 (define_insn "mmacfx_wl_i"
10102 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10104 (match_operand:V2SI 1 "arith_reg_operand" "0")
10109 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
10110 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
10113 "mmacfx.wl %2, %3, %0"
10114 [(set_attr "type" "mac_media")])
10116 (define_expand "mmacnfx_wl"
10117 [(match_operand:V2SI 0 "arith_reg_dest" "")
10118 (match_operand:V2HI 1 "extend_reg_operand" "")
10119 (match_operand:V2HI 2 "extend_reg_operand" "")
10120 (match_operand:V2SI 3 "arith_reg_operand" "")]
10124 emit_insn (gen_mmacnfx_wl_i (operands[0], operands[3],
10125 operands[1], operands[2]));
10129 (define_insn "mmacnfx_wl_i"
10130 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10132 (match_operand:V2SI 1 "arith_reg_operand" "0")
10137 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
10138 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
10141 "mmacnfx.wl %2, %3, %0"
10142 [(set_attr "type" "mac_media")])
10144 (define_insn "mulv2si3"
10145 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10146 (mult:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
10147 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
10149 "mmul.l %1, %2, %0"
10150 [(set_attr "type" "d2mpy_media")])
10152 (define_insn "mulv4hi3"
10153 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10154 (mult:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
10155 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
10157 "mmul.w %1, %2, %0"
10158 [(set_attr "type" "dmpy_media")])
10160 (define_insn "mmulfx_l"
10161 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10165 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
10166 (sign_extend:V2DI (match_operand:V2SI 2 "arith_reg_operand" "r")))
10169 "mmulfx.l %1, %2, %0"
10170 [(set_attr "type" "d2mpy_media")])
10172 (define_insn "mmulfx_w"
10173 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10177 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
10178 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
10181 "mmulfx.w %1, %2, %0"
10182 [(set_attr "type" "dmpy_media")])
10184 (define_insn "mmulfxrp_w"
10185 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10190 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
10191 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
10195 "mmulfxrp.w %1, %2, %0"
10196 [(set_attr "type" "dmpy_media")])
10198 (define_expand "mmulhi_wl"
10199 [(match_operand:V2SI 0 "arith_reg_dest" "")
10200 (match_operand:V4HI 1 "arith_reg_operand" "")
10201 (match_operand:V4HI 2 "arith_reg_operand" "")]
10205 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul23_wl : gen_mmul01_wl)
10206 (operands[0], operands[1], operands[2]));
10210 (define_expand "mmullo_wl"
10211 [(match_operand:V2SI 0 "arith_reg_dest" "")
10212 (match_operand:V4HI 1 "arith_reg_operand" "")
10213 (match_operand:V4HI 2 "arith_reg_operand" "")]
10217 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul01_wl : gen_mmul23_wl)
10218 (operands[0], operands[1], operands[2]));
10222 (define_insn "mmul23_wl"
10223 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10226 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
10227 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
10228 (parallel [(const_int 2) (const_int 3)])))]
10230 "* return (TARGET_LITTLE_ENDIAN
10231 ? \"mmulhi.wl %1, %2, %0\"
10232 : \"mmullo.wl %1, %2, %0\");"
10233 [(set_attr "type" "dmpy_media")])
10235 (define_insn "mmul01_wl"
10236 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10239 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
10240 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
10241 (parallel [(const_int 0) (const_int 1)])))]
10243 "* return (TARGET_LITTLE_ENDIAN
10244 ? \"mmullo.wl %1, %2, %0\"
10245 : \"mmulhi.wl %1, %2, %0\");"
10246 [(set_attr "type" "dmpy_media")])
10248 (define_expand "mmulsum_wq"
10249 [(match_operand:DI 0 "arith_reg_dest" "")
10250 (match_operand:V4HI 1 "arith_reg_operand" "")
10251 (match_operand:V4HI 2 "arith_reg_operand" "")
10252 (match_operand:DI 3 "arith_reg_operand" "")]
10256 emit_insn (gen_mmulsum_wq_i (operands[0], operands[3],
10257 operands[1], operands[2]));
10261 (define_insn "mmulsum_wq_i"
10262 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10263 (plus:DI (match_operand:DI 1 "arith_reg_operand" "0")
10268 (sign_extend:V4DI (match_operand:V4HI 2 "arith_reg_operand" "r"))
10269 (sign_extend:V4DI (match_operand:V4HI 3 "arith_reg_operand" "r")))
10270 (parallel [(const_int 0)]))
10271 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
10272 (sign_extend:V4DI (match_dup 3)))
10273 (parallel [(const_int 1)])))
10275 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
10276 (sign_extend:V4DI (match_dup 3)))
10277 (parallel [(const_int 2)]))
10278 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
10279 (sign_extend:V4DI (match_dup 3)))
10280 (parallel [(const_int 3)]))))))]
10282 "mmulsum.wq %2, %3, %0"
10283 [(set_attr "type" "mac_media")])
10285 (define_expand "mperm_w"
10286 [(match_operand:V4HI 0 "arith_reg_dest" "=r")
10287 (match_operand:V4HI 1 "arith_reg_operand" "r")
10288 (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")]
10292 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mperm_w_little : gen_mperm_w_big)
10293 (operands[0], operands[1], operands[2]));
10297 ; This use of vec_select isn't exactly correct according to rtl.texi
10298 ; (because not constant), but it seems a straightforward extension.
10299 (define_insn "mperm_w_little"
10300 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10302 (match_operand:V4HI 1 "arith_reg_operand" "r")
10304 [(zero_extract:QI (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")
10305 (const_int 2) (const_int 0))
10306 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 2))
10307 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 4))
10308 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 6))])))]
10309 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
10310 "mperm.w %1, %N2, %0"
10311 [(set_attr "type" "arith_media")])
10313 (define_insn "mperm_w_big"
10314 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10316 (match_operand:V4HI 1 "arith_reg_operand" "r")
10318 [(zero_extract:QI (not:QI (match_operand:QI 2
10319 "extend_reg_or_0_operand" "rZ"))
10320 (const_int 2) (const_int 0))
10321 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 2))
10322 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 4))
10323 (zero_extract:QI (not:QI (match_dup 2))
10324 (const_int 2) (const_int 6))])))]
10325 "TARGET_SHMEDIA && ! TARGET_LITTLE_ENDIAN"
10326 "mperm.w %1, %N2, %0"
10327 [(set_attr "type" "arith_media")])
10329 (define_insn "mperm_w0"
10330 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10331 (vec_duplicate:V4HI (truncate:HI (match_operand 1
10332 "trunc_hi_operand" "r"))))]
10334 "mperm.w %1, r63, %0"
10335 [(set_attr "type" "arith_media")])
10337 (define_expand "msad_ubq"
10338 [(match_operand:DI 0 "arith_reg_dest" "")
10339 (match_operand:V8QI 1 "arith_reg_or_0_operand" "")
10340 (match_operand:V8QI 2 "arith_reg_or_0_operand" "")
10341 (match_operand:DI 3 "arith_reg_operand" "")]
10345 emit_insn (gen_msad_ubq_i (operands[0], operands[3],
10346 operands[1], operands[2]));
10350 (define_insn "msad_ubq_i"
10351 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10356 (match_operand:DI 1 "arith_reg_operand" "0")
10357 (abs:DI (vec_select:DI
10360 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
10362 (match_operand:V8QI 3 "arith_reg_or_0_operand" "rZ")))
10363 (parallel [(const_int 0)]))))
10364 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
10365 (zero_extend:V8DI (match_dup 3)))
10366 (parallel [(const_int 1)]))))
10368 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
10369 (zero_extend:V8DI (match_dup 3)))
10370 (parallel [(const_int 2)])))
10371 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
10372 (zero_extend:V8DI (match_dup 3)))
10373 (parallel [(const_int 3)])))))
10376 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
10377 (zero_extend:V8DI (match_dup 3)))
10378 (parallel [(const_int 4)])))
10379 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
10380 (zero_extend:V8DI (match_dup 3)))
10381 (parallel [(const_int 5)]))))
10383 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
10384 (zero_extend:V8DI (match_dup 3)))
10385 (parallel [(const_int 6)])))
10386 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
10387 (zero_extend:V8DI (match_dup 3)))
10388 (parallel [(const_int 7)])))))))]
10390 "msad.ubq %N2, %N3, %0"
10391 [(set_attr "type" "mac_media")])
10393 (define_insn "mshalds_l"
10394 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10397 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
10398 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
10399 (const_int 31)))))]
10401 "mshalds.l %1, %2, %0"
10402 [(set_attr "type" "mcmp_media")])
10404 (define_insn "mshalds_w"
10405 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10408 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
10409 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
10410 (const_int 15)))))]
10412 "mshalds.w %1, %2, %0"
10413 [(set_attr "type" "mcmp_media")])
10415 (define_insn "ashrv2si3"
10416 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10417 (ashiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
10418 (match_operand:DI 2 "arith_reg_operand" "r")))]
10420 "mshard.l %1, %2, %0"
10421 [(set_attr "type" "arith_media")])
10423 (define_insn "ashrv4hi3"
10424 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10425 (ashiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
10426 (match_operand:DI 2 "arith_reg_operand" "r")))]
10428 "mshard.w %1, %2, %0"
10429 [(set_attr "type" "arith_media")])
10431 (define_insn "mshards_q"
10432 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
10434 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
10435 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ"))))]
10437 "mshards.q %1, %N2, %0"
10438 [(set_attr "type" "mcmp_media")])
10440 (define_expand "mshfhi_b"
10441 [(match_operand:V8QI 0 "arith_reg_dest" "")
10442 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
10443 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
10447 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_b : gen_mshf0_b)
10448 (operands[0], operands[1], operands[2]));
10452 (define_expand "mshflo_b"
10453 [(match_operand:V8QI 0 "arith_reg_dest" "")
10454 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
10455 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
10459 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_b : gen_mshf4_b)
10460 (operands[0], operands[1], operands[2]));
10464 (define_insn "mshf4_b"
10466 (match_operand:V8QI 0 "arith_reg_dest" "=r")
10468 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
10469 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
10470 (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13)
10471 (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))]
10473 "* return (TARGET_LITTLE_ENDIAN
10474 ? \"mshfhi.b %N1, %N2, %0\"
10475 : \"mshflo.b %N1, %N2, %0\");"
10476 [(set_attr "type" "arith_media")])
10478 (define_insn "mshf0_b"
10480 (match_operand:V8QI 0 "arith_reg_dest" "=r")
10482 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
10483 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
10484 (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9)
10485 (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))]
10487 "* return (TARGET_LITTLE_ENDIAN
10488 ? \"mshflo.b %N1, %N2, %0\"
10489 : \"mshfhi.b %N1, %N2, %0\");"
10490 [(set_attr "type" "arith_media")])
10492 (define_expand "mshfhi_l"
10493 [(match_operand:V2SI 0 "arith_reg_dest" "")
10494 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
10495 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
10499 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_l : gen_mshf0_l)
10500 (operands[0], operands[1], operands[2]));
10504 (define_expand "mshflo_l"
10505 [(match_operand:V2SI 0 "arith_reg_dest" "")
10506 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
10507 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
10511 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_l : gen_mshf4_l)
10512 (operands[0], operands[1], operands[2]));
10516 (define_insn "mshf4_l"
10517 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10519 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
10520 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
10521 (parallel [(const_int 1) (const_int 3)])))]
10523 "* return (TARGET_LITTLE_ENDIAN
10524 ? \"mshfhi.l %N1, %N2, %0\"
10525 : \"mshflo.l %N1, %N2, %0\");"
10526 [(set_attr "type" "arith_media")])
10528 (define_insn "mshf0_l"
10529 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10531 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
10532 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
10533 (parallel [(const_int 0) (const_int 2)])))]
10535 "* return (TARGET_LITTLE_ENDIAN
10536 ? \"mshflo.l %N1, %N2, %0\"
10537 : \"mshfhi.l %N1, %N2, %0\");"
10538 [(set_attr "type" "arith_media")])
10540 (define_expand "mshfhi_w"
10541 [(match_operand:V4HI 0 "arith_reg_dest" "")
10542 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
10543 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
10547 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_w : gen_mshf0_w)
10548 (operands[0], operands[1], operands[2]));
10552 (define_expand "mshflo_w"
10553 [(match_operand:V4HI 0 "arith_reg_dest" "")
10554 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
10555 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
10559 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_w : gen_mshf4_w)
10560 (operands[0], operands[1], operands[2]));
10564 (define_insn "mshf4_w"
10565 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10567 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
10568 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
10569 (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))]
10571 "* return (TARGET_LITTLE_ENDIAN
10572 ? \"mshfhi.w %N1, %N2, %0\"
10573 : \"mshflo.w %N1, %N2, %0\");"
10574 [(set_attr "type" "arith_media")])
10576 (define_insn "mshf0_w"
10577 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10579 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
10580 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
10581 (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))]
10583 "* return (TARGET_LITTLE_ENDIAN
10584 ? \"mshflo.w %N1, %N2, %0\"
10585 : \"mshfhi.w %N1, %N2, %0\");"
10586 [(set_attr "type" "arith_media")])
10588 (define_insn "mshflo_w_x"
10589 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10591 (vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rZ")
10592 (match_operand:V2HI 2 "extend_reg_or_0_operand" "rZ"))
10593 (parallel [(const_int 2) (const_int 0) (const_int 3) (const_int 1)])))]
10595 "mshflo.w %N1, %N2, %0"
10596 [(set_attr "type" "arith_media")])
10598 /* These are useful to expand ANDs and as combiner patterns. */
10599 (define_insn_and_split "mshfhi_l_di"
10600 [(set (match_operand:DI 0 "arith_reg_dest" "=r,f")
10601 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f")
10603 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ,?f")
10604 (const_int -4294967296))))]
10607 mshfhi.l %N1, %N2, %0
10609 "TARGET_SHMEDIA && reload_completed
10610 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
10611 [(set (match_dup 3) (match_dup 4))
10612 (set (match_dup 5) (match_dup 6))]
10615 operands[3] = gen_lowpart (SImode, operands[0]);
10616 operands[4] = gen_highpart (SImode, operands[1]);
10617 operands[5] = gen_highpart (SImode, operands[0]);
10618 operands[6] = gen_highpart (SImode, operands[2]);
10620 [(set_attr "type" "arith_media")])
10622 (define_insn "*mshfhi_l_di_rev"
10623 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10624 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
10625 (const_int -4294967296))
10626 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
10629 "mshfhi.l %N2, %N1, %0"
10630 [(set_attr "type" "arith_media")])
10633 [(set (match_operand:DI 0 "arith_reg_dest" "")
10634 (ior:DI (zero_extend:DI (match_operand:SI 1
10635 "extend_reg_or_0_operand" ""))
10636 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "")
10637 (const_int -4294967296))))
10638 (clobber (match_operand:DI 3 "arith_reg_dest" ""))]
10643 emit_insn (gen_ashldi3_media (operands[3],
10644 simplify_gen_subreg (DImode, operands[1],
10647 emit_insn (gen_mshfhi_l_di (operands[0], operands[3], operands[2]));
10651 (define_insn "mshflo_l_di"
10652 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10653 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
10654 (const_int 4294967295))
10655 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
10659 "mshflo.l %N1, %N2, %0"
10660 [(set_attr "type" "arith_media")])
10662 (define_insn "*mshflo_l_di_rev"
10663 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10664 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
10666 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
10667 (const_int 4294967295))))]
10670 "mshflo.l %N2, %N1, %0"
10671 [(set_attr "type" "arith_media")])
10673 ;; Combiner pattern for trampoline initialization.
10674 (define_insn_and_split "*double_shori"
10675 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10676 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
10678 (match_operand:DI 2 "const_int_operand" "n")))]
10680 && INTVAL (operands[2]) == trunc_int_for_mode (INTVAL (operands[2]), SImode)"
10682 "rtx_equal_p (operands[0], operands[1])"
10686 HOST_WIDE_INT v = INTVAL (operands[2]);
10688 emit_insn (gen_shori_media (operands[0], operands[0],
10689 gen_int_mode (INTVAL (operands[2]) >> 16, HImode)));
10690 emit_insn (gen_shori_media (operands[0], operands[0],
10691 gen_int_mode (v, HImode)));
10696 (define_insn "*mshflo_l_di_x"
10697 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10698 (ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand"
10700 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
10704 "mshflo.l %N1, %N2, %0"
10705 [(set_attr "type" "arith_media")])
10707 (define_insn_and_split "concat_v2sf"
10708 [(set (match_operand:V2SF 0 "register_operand" "=r,f,f?")
10709 ;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f")
10710 (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f")
10711 (match_operand:SF 2 "register_operand" "rZ,f,f")))]
10715 mshflo.l %N1, %N2, %0
10718 "TARGET_SHMEDIA && reload_completed
10719 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
10720 [(set (match_dup 3) (match_dup 1))
10721 (set (match_dup 4) (match_dup 2))]
10724 operands[3] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 0);
10725 operands[4] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 4);
10727 [(set_attr "type" "arith_media")])
10729 (define_insn "*mshflo_l_di_x_rev"
10730 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10731 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
10733 (zero_extend:DI (match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))]
10736 "mshflo.l %N2, %N1, %0"
10737 [(set_attr "type" "arith_media")])
10739 (define_insn "ashlv2si3"
10740 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10741 (ashift:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
10742 (match_operand:DI 2 "arith_reg_operand" "r")))]
10744 "mshlld.l %1, %2, %0"
10745 [(set_attr "type" "arith_media")])
10747 (define_insn "ashlv4hi3"
10748 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10749 (ashift:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
10750 (match_operand:DI 2 "arith_reg_operand" "r")))]
10752 "mshlld.w %1, %2, %0"
10753 [(set_attr "type" "arith_media")])
10755 (define_insn "lshrv2si3"
10756 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10757 (lshiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
10758 (match_operand:DI 2 "arith_reg_operand" "r")))]
10760 "mshlrd.l %1, %2, %0"
10761 [(set_attr "type" "arith_media")])
10763 (define_insn "lshrv4hi3"
10764 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10765 (lshiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
10766 (match_operand:DI 2 "arith_reg_operand" "r")))]
10768 "mshlrd.w %1, %2, %0"
10769 [(set_attr "type" "arith_media")])
10771 (define_insn "subv2si3"
10772 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10773 (minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
10774 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
10776 "msub.l %N1, %2, %0"
10777 [(set_attr "type" "arith_media")])
10779 (define_insn "subv4hi3"
10780 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10781 (minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
10782 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
10784 "msub.w %N1, %2, %0"
10785 [(set_attr "type" "arith_media")])
10787 (define_insn "sssubv2si3"
10788 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10789 (ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
10790 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
10792 "msubs.l %N1, %2, %0"
10793 [(set_attr "type" "mcmp_media")])
10795 (define_insn "ussubv8qi3"
10796 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
10797 (us_minus:V8QI (match_operand:V8QI 1 "arith_reg_operand" "r")
10798 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
10800 "msubs.ub %1, %2, %0"
10801 [(set_attr "type" "mcmp_media")])
10803 (define_insn "sssubv4hi3"
10804 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10805 (ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
10806 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
10808 "msubs.w %N1, %2, %0"
10809 [(set_attr "type" "mcmp_media")])
10811 ;; Floating Point Intrinsics
10813 (define_insn "fcosa_s"
10814 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10815 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
10819 [(set_attr "type" "atrans_media")])
10821 (define_insn "fsina_s"
10822 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10823 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
10827 [(set_attr "type" "atrans_media")])
10829 (define_insn "fipr"
10830 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10831 (plus:SF (plus:SF (vec_select:SF (mult:V4SF (match_operand:V4SF 1
10832 "fp_arith_reg_operand" "f")
10833 (match_operand:V4SF 2
10834 "fp_arith_reg_operand" "f"))
10835 (parallel [(const_int 0)]))
10836 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
10837 (parallel [(const_int 1)])))
10838 (plus:SF (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
10839 (parallel [(const_int 2)]))
10840 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
10841 (parallel [(const_int 3)])))))]
10843 "fipr.s %1, %2, %0"
10844 [(set_attr "type" "fparith_media")])
10846 (define_insn "fsrra_s"
10847 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10848 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "f")]
10852 [(set_attr "type" "atrans_media")])
10854 (define_insn "ftrv"
10855 [(set (match_operand:V4SF 0 "fp_arith_reg_operand" "=f")
10859 (vec_select:V4SF (match_operand:V16SF 1 "fp_arith_reg_operand" "f")
10860 (parallel [(const_int 0) (const_int 5)
10861 (const_int 10) (const_int 15)]))
10862 (match_operand:V4SF 2 "fp_arith_reg_operand" "f"))
10864 (vec_select:V4SF (match_dup 1)
10865 (parallel [(const_int 4) (const_int 9)
10866 (const_int 14) (const_int 3)]))
10867 (vec_select:V4SF (match_dup 2)
10868 (parallel [(const_int 1) (const_int 2)
10869 (const_int 3) (const_int 0)]))))
10872 (vec_select:V4SF (match_dup 1)
10873 (parallel [(const_int 8) (const_int 13)
10874 (const_int 2) (const_int 7)]))
10875 (vec_select:V4SF (match_dup 2)
10876 (parallel [(const_int 2) (const_int 3)
10877 (const_int 0) (const_int 1)])))
10879 (vec_select:V4SF (match_dup 1)
10880 (parallel [(const_int 12) (const_int 1)
10881 (const_int 6) (const_int 11)]))
10882 (vec_select:V4SF (match_dup 2)
10883 (parallel [(const_int 3) (const_int 0)
10884 (const_int 1) (const_int 2)]))))))]
10886 "ftrv.s %1, %2, %0"
10887 [(set_attr "type" "fparith_media")])
10890 [(set (match_operand:QI 0 "arith_reg_dest" "=r")
10891 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
10895 [(set_attr "type" "arith_media")])
10897 (define_insn "nsbsi"
10898 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
10900 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
10904 [(set_attr "type" "arith_media")])
10906 (define_insn "nsbdi"
10907 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10909 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
10913 [(set_attr "type" "arith_media")])
10915 (define_expand "ffsdi2"
10916 [(set (match_operand:DI 0 "arith_reg_dest" "")
10917 (ffs:DI (match_operand:DI 1 "arith_reg_operand" "")))]
10921 rtx scratch = gen_reg_rtx (DImode);
10924 emit_insn (gen_adddi3 (scratch, operands[1], constm1_rtx));
10925 emit_insn (gen_xordi3 (scratch, operands[1], scratch));
10926 emit_insn (gen_lshrdi3_media (scratch, scratch, const1_rtx));
10927 emit_insn (gen_nsbdi (scratch, scratch));
10928 emit_insn (gen_adddi3 (scratch, scratch, GEN_INT (-64)));
10929 emit_insn (gen_movdicc_false (scratch, operands[1], const0_rtx, scratch));
10930 last = emit_insn (gen_subdi3 (operands[0], const0_rtx, scratch));
10932 = gen_rtx_EXPR_LIST (REG_EQUAL,
10933 gen_rtx_FFS (DImode, operands[0]), REG_NOTES (last));
10937 (define_expand "ffssi2"
10938 [(set (match_operand:SI 0 "arith_reg_dest" "")
10939 (ffs:SI (match_operand:SI 1 "arith_reg_operand" "")))]
10943 rtx scratch = gen_reg_rtx (SImode);
10944 rtx discratch = gen_reg_rtx (DImode);
10947 emit_insn (gen_adddi3 (discratch,
10948 simplify_gen_subreg (DImode, operands[1], SImode, 0),
10950 emit_insn (gen_andcdi3 (discratch,
10951 simplify_gen_subreg (DImode, operands[1], SImode, 0),
10953 emit_insn (gen_nsbsi (scratch, discratch));
10954 last = emit_insn (gen_subsi3 (operands[0],
10955 force_reg (SImode, GEN_INT (63)), scratch));
10957 = gen_rtx_EXPR_LIST (REG_EQUAL,
10958 gen_rtx_FFS (SImode, operands[0]), REG_NOTES (last));
10962 (define_insn "byterev"
10963 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
10964 (vec_select:V8QI (match_operand:V8QI 1 "arith_reg_operand" "r")
10965 (parallel [(const_int 7) (const_int 6) (const_int 5)
10966 (const_int 4) (const_int 3) (const_int 2)
10967 (const_int 1) (const_int 0)])))]
10970 [(set_attr "type" "arith_media")])
10972 (define_insn "prefetch_media"
10973 [(prefetch (match_operand:QI 0 "address_operand" "p")
10974 (match_operand:SI 1 "const_int_operand" "n")
10975 (match_operand:SI 2 "const_int_operand" "n"))]
10979 operands[0] = gen_rtx_MEM (QImode, operands[0]);
10980 output_asm_insn (\"ld%M0.b %m0,r63\", operands);
10983 [(set_attr "type" "other")])
10985 (define_insn "prefetch_i4"
10986 [(prefetch (match_operand:SI 0 "register_operand" "r")
10987 (match_operand:SI 1 "const_int_operand" "n")
10988 (match_operand:SI 2 "const_int_operand" "n"))]
10992 return \"pref @%0\";
10994 [(set_attr "type" "other")])
10996 (define_expand "prefetch"
10997 [(prefetch (match_operand:QI 0 "address_operand" "p")
10998 (match_operand:SI 1 "const_int_operand" "n")
10999 (match_operand:SI 2 "const_int_operand" "n"))]
11000 "TARGET_SHMEDIA || TARGET_HARD_SH4"
11003 if (TARGET_HARD_SH4 && ! register_operand (operands[0], SImode))
11005 rtx reg = gen_reg_rtx (SImode);
11006 emit_move_insn (reg, operands[0]);
11010 emit_insn ((TARGET_SHMEDIA ? gen_prefetch_media : gen_prefetch_i4)
11011 (operands[0], operands[1], operands[2]));