1 ;;- Machine description for Hitachi / SuperH SH.
2 ;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
5 ;; Improved by Jim Wilson (wilson@cygnus.com).
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
25 ;; ??? Should prepend a * to all pattern names which are not used.
26 ;; This will make the compiler smaller, and rebuilds after changes faster.
28 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
29 ;; sequences. Especially the sequences for arithmetic right shifts.
31 ;; ??? Should check all DImode patterns for consistency and usefulness.
33 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
34 ;; way to generate them.
36 ;; ??? The cmp/str instruction is not supported. Perhaps it can be used
37 ;; for a str* inline function.
39 ;; BSR is not generated by the compiler proper, but when relaxing, it
40 ;; generates .uses pseudo-ops that allow linker relaxation to create
41 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
43 ;; Special constraints for SH machine description:
50 ;; Special formats used for outputting SH instructions:
52 ;; %. -- print a .s if insn needs delay slot
53 ;; %@ -- print rte/rts if is/isn't an interrupt function
54 ;; %# -- output a nop if there is nothing to put in the delay slot
55 ;; %O -- print a constant without the #
56 ;; %R -- print the lsw reg of a double
57 ;; %S -- print the msw reg of a double
58 ;; %T -- print next word of a double REG or MEM
60 ;; Special predicates:
62 ;; arith_operand -- operand is valid source for arithmetic op
63 ;; arith_reg_operand -- operand is valid register for arithmetic op
64 ;; general_movdst_operand -- operand is valid move destination
65 ;; general_movsrc_operand -- operand is valid move source
66 ;; logical_operand -- operand is valid source for logical op
68 ;; -------------------------------------------------------------------------
70 ;; -------------------------------------------------------------------------
118 ;; These are used with unspec.
119 (UNSPEC_COMPACT_ARGS 0)
132 (UNSPEC_INIT_TRAMP 13)
139 ;; These are used with unspec_volatile.
145 (UNSPECV_WINDOW_END 10)
146 (UNSPECV_CONST_END 11)
149 ;; -------------------------------------------------------------------------
151 ;; -------------------------------------------------------------------------
156 "sh1,sh2,sh3,sh3e,sh4,sh5"
157 (const (symbol_ref "sh_cpu_attr")))
159 (define_attr "endian" "big,little"
160 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
161 (const_string "little") (const_string "big"))))
163 ;; Indicate if the default fpu mode is single precision.
164 (define_attr "fpu_single" "yes,no"
165 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
166 (const_string "yes") (const_string "no"))))
168 (define_attr "fmovd" "yes,no"
169 (const (if_then_else (symbol_ref "TARGET_FMOVD")
170 (const_string "yes") (const_string "no"))))
172 (define_attr "pipe_model" "sh1,sh4,sh5media"
174 (cond [(symbol_ref "TARGET_SHMEDIA") (const_string "sh5media")
175 (symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
176 (const_string "sh1"))))
178 ;; cbranch conditional branch instructions
179 ;; jump unconditional jumps
180 ;; arith ordinary arithmetic
181 ;; arith3 a compound insn that behaves similarly to a sequence of
182 ;; three insns of type arith
183 ;; arith3b like above, but might end with a redirected branch
185 ;; load_si Likewise, SImode variant for general register.
187 ;; move register to register
188 ;; fmove register to register, floating point
189 ;; smpy word precision integer multiply
190 ;; dmpy longword or doublelongword precision integer multiply
192 ;; pload load of pr reg, which can't be put into delay slot of rts
193 ;; prset copy register to pr reg, ditto
194 ;; pstore store of pr reg, which can't be put into delay slot of jsr
195 ;; prget copy pr to register, ditto
196 ;; pcload pc relative load of constant value
197 ;; pcload_si Likewise, SImode variant for general register.
198 ;; rte return from exception
199 ;; sfunc special function call with known used registers
200 ;; call function call
202 ;; fdiv floating point divide (or square root)
203 ;; gp_fpul move between general purpose register and fpul
204 ;; dfp_arith, dfp_cmp,dfp_conv
205 ;; dfdiv double precision floating point divide (or square root)
206 ;; arith_media SHmedia arithmetic, logical, and shift instructions
207 ;; cbranch_media SHmedia conditional branch instructions
208 ;; cmp_media SHmedia compare instructions
209 ;; dfdiv_media SHmedia double precision divide and square root
210 ;; dfmul_media SHmedia double precision multiply instruction
211 ;; dfparith_media SHmedia double precision floating point arithmetic
212 ;; dfpconv_media SHmedia double precision floating point conversions
213 ;; dmpy_media SHmedia longword multiply
214 ;; fcmp_media SHmedia floating point compare instructions
215 ;; fdiv_media SHmedia single precision divide and square root
216 ;; fload_media SHmedia floating point register load instructions
217 ;; fmove_media SHmedia floating point register moves (inc. fabs and fneg)
218 ;; fparith_media SHmedia single precision floating point arithmetic
219 ;; fpconv_media SHmedia single precision floating point conversions
220 ;; fstore_media SHmedia floating point register store instructions
221 ;; gettr_media SHmedia gettr instruction
222 ;; invalidate_line_media SHmedia invaldiate_line sequence
223 ;; jump_media SHmedia unconditional branch instructions
224 ;; load_media SHmedia general register load instructions
225 ;; pt_media SHmedia pt instruction (expanded by assembler)
226 ;; ptabs_media SHmedia ptabs instruction
227 ;; store_media SHmedia general register store instructions
228 ;; mcmp_media SHmedia multimedia compare, absolute, saturating ops
229 ;; mac_media SHmedia mac-style fixed point operations
230 ;; d2mpy_media SHmedia: two 32 bit integer multiplies
231 ;; atrans SHmedia approximate transcendential functions
232 ;; ustore_media SHmedia unaligned stores
233 ;; nil no-op move, will be deleted.
236 "cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,store,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,rte,sfunc,call,fp,fdiv,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media,nil,other"
237 (const_string "other"))
239 ;; We define a new attribute namely "insn_class".We use
240 ;; this for DFA based pipeline description.
241 ;; Although the "type" attribute covers almost all insn
242 ;; classes,it is more convenient to define new attribute
243 ;; for certain reservations.
245 ;; mt_group SH4 "mt" group instructions.
247 ;; ex_group SH4 "ex" group instructions.They mostly
248 ;; overlap with arithmetic instructions but
249 ;; new attribute defined to distinguish from
250 ;; mt group instructions.
252 ;; lds_to_fpscr The "type" attribute couldn't sufficiently
253 ;; distinguish it from others.It is part of
254 ;; new attribute.Similar case with ldsmem_to_fpscr
257 (define_attr "insn_class"
258 "mt_group,ex_group,lds_to_fpscr,ldsmem_to_fpscr,cwb,none"
259 (const_string "none"))
261 ;; Indicate what precision must be selected in fpscr for this insn, if any.
263 (define_attr "fp_mode" "single,double,none" (const_string "none"))
265 ; If a conditional branch destination is within -252..258 bytes away
266 ; from the instruction it can be 2 bytes long. Something in the
267 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
268 ; branches are initially assumed to be 16 bytes long.
269 ; In machine_dependent_reorg, we split all branches that are longer than
272 ;; The maximum range used for SImode constant pool entries is 1018. A final
273 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
274 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
275 ;; instruction around the pool table, 2 bytes of alignment before the table,
276 ;; and 30 bytes of alignment after the table. That gives a maximum total
277 ;; pool size of 1058 bytes.
278 ;; Worst case code/pool content size ratio is 1:2 (using asms).
279 ;; Thus, in the worst case, there is one instruction in front of a maximum
280 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
281 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
282 ;; If we have a forward branch, the initial table will be put after the
283 ;; unconditional branch.
285 ;; ??? We could do much better by keeping track of the actual pcloads within
286 ;; the branch range and in the pcload range in front of the branch range.
288 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
290 (define_attr "short_cbranch_p" "no,yes"
291 (cond [(ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
293 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
295 (ne (symbol_ref "NEXT_INSN (PREV_INSN (insn)) != insn") (const_int 0))
297 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
299 ] (const_string "no")))
301 (define_attr "med_branch_p" "no,yes"
302 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
305 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
307 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
310 ] (const_string "no")))
312 (define_attr "med_cbranch_p" "no,yes"
313 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
316 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
318 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
321 ] (const_string "no")))
323 (define_attr "braf_branch_p" "no,yes"
324 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
326 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
329 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
331 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
334 ] (const_string "no")))
336 (define_attr "braf_cbranch_p" "no,yes"
337 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
339 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
342 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
344 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
347 ] (const_string "no")))
349 ; An unconditional jump in the range -4092..4098 can be 2 bytes long.
350 ; For wider ranges, we need a combination of a code and a data part.
351 ; If we can get a scratch register for a long range jump, the code
352 ; part can be 4 bytes long; otherwise, it must be 8 bytes long.
353 ; If the jump is in the range -32764..32770, the data part can be 2 bytes
354 ; long; otherwise, it must be 6 bytes long.
356 ; All other instructions are two bytes long by default.
358 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
359 ;; but getattrtab doesn't understand this.
360 (define_attr "length" ""
361 (cond [(eq_attr "type" "cbranch")
362 (cond [(eq_attr "short_cbranch_p" "yes")
364 (eq_attr "med_cbranch_p" "yes")
366 (eq_attr "braf_cbranch_p" "yes")
368 ;; ??? using pc is not computed transitively.
369 (ne (match_dup 0) (match_dup 0))
371 (ne (symbol_ref ("flag_pic")) (const_int 0))
374 (eq_attr "type" "jump")
375 (cond [(eq_attr "med_branch_p" "yes")
377 (and (eq (symbol_ref "GET_CODE (PREV_INSN (insn))")
379 (eq (symbol_ref "INSN_CODE (PREV_INSN (insn))")
380 (symbol_ref "code_for_indirect_jump_scratch")))
381 (if_then_else (eq_attr "braf_branch_p" "yes")
384 (eq_attr "braf_branch_p" "yes")
386 ;; ??? using pc is not computed transitively.
387 (ne (match_dup 0) (match_dup 0))
389 (ne (symbol_ref ("flag_pic")) (const_int 0))
392 (eq_attr "type" "pt_media")
393 (if_then_else (ne (symbol_ref "TARGET_SHMEDIA64") (const_int 0))
394 (const_int 20) (const_int 12))
395 ] (if_then_else (ne (symbol_ref "TARGET_SHMEDIA") (const_int 0))
399 ;; (define_function_unit {name} {num-units} {n-users} {test}
400 ;; {ready-delay} {issue-delay} [{conflict-list}])
402 ;; Load and store instructions save a cycle if they are aligned on a
403 ;; four byte boundary. Using a function unit for stores encourages
404 ;; gcc to separate load and store instructions by one instruction,
405 ;; which makes it more likely that the linker will be able to word
406 ;; align them when relaxing.
408 ;; Loads have a latency of two.
409 ;; However, call insns can have a delay slot, so that we want one more
410 ;; insn to be scheduled between the load of the function address and the call.
411 ;; This is equivalent to a latency of three.
412 ;; We cannot use a conflict list for this, because we need to distinguish
413 ;; between the actual call address and the function arguments.
414 ;; ADJUST_COST can only properly handle reductions of the cost, so we
415 ;; use a latency of three here.
416 ;; We only do this for SImode loads of general registers, to make the work
417 ;; for ADJUST_COST easier.
418 (define_function_unit "memory" 1 0
419 (and (eq_attr "pipe_model" "sh1")
420 (eq_attr "type" "load_si,pcload_si"))
422 (define_function_unit "memory" 1 0
423 (and (eq_attr "pipe_model" "sh1")
424 (eq_attr "type" "load,pcload,pload,store,pstore"))
427 (define_function_unit "int" 1 0
428 (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "arith3,arith3b")) 3 3)
430 (define_function_unit "int" 1 0
431 (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "dyn_shift")) 2 2)
433 (define_function_unit "int" 1 0
434 (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "!arith3,arith3b,dyn_shift")) 1 1)
436 ;; ??? These are approximations.
437 (define_function_unit "mpy" 1 0
438 (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "smpy")) 2 2)
439 (define_function_unit "mpy" 1 0
440 (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "dmpy")) 3 3)
442 (define_function_unit "fp" 1 0
443 (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "fp,fmove")) 2 1)
444 (define_function_unit "fp" 1 0
445 (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "fdiv")) 13 12)
449 ;; The SH4 is a dual-issue implementation, thus we have to multiply all
450 ;; costs by at least two.
451 ;; There will be single increments of the modeled that don't correspond
452 ;; to the actual target ;; whenever two insns to be issued depend one a
453 ;; single resource, and the scheduler picks to be the first one.
454 ;; If we multiplied the costs just by two, just two of these single
455 ;; increments would amount to an actual cycle. By picking a larger
456 ;; factor, we can ameliorate the effect; However, we then have to make sure
457 ;; that only two insns are modeled as issued per actual cycle.
458 ;; Moreover, we need a way to specify the latency of insns that don't
459 ;; use an actual function unit.
460 ;; We use an 'issue' function unit to do that, and a cost factor of 10.
462 (define_function_unit "issue" 2 0
463 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "!nil,arith3"))
466 (define_function_unit "issue" 2 0
467 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "arith3"))
470 ;; There is no point in providing exact scheduling information about branches,
471 ;; because they are at the starts / ends of basic blocks anyways.
473 ;; Some insns cannot be issued before/after another insn in the same cycle,
474 ;; irrespective of the type of the other insn.
476 ;; default is dual-issue, but can't be paired with an insn that
477 ;; uses multiple function units.
478 (define_function_unit "single_issue" 1 0
479 (and (eq_attr "pipe_model" "sh4")
480 (eq_attr "type" "!smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul,call,sfunc,arith3,arith3b"))
482 [(eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul")])
484 (define_function_unit "single_issue" 1 0
485 (and (eq_attr "pipe_model" "sh4")
486 (eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul"))
490 ;; arith3 insns are always pairable at the start, but not inecessarily at
491 ;; the end; however, there doesn't seem to be a way to express that.
492 (define_function_unit "single_issue" 1 0
493 (and (eq_attr "pipe_model" "sh4")
494 (eq_attr "type" "arith3"))
498 ;; arith3b insn are pairable at the end and have latency that prevents pairing
499 ;; with the following branch, but we don't want this latency be respected;
500 ;; When the following branch is immediately adjacent, we can redirect the
501 ;; internal branch, which is likly to be a larger win.
502 (define_function_unit "single_issue" 1 0
503 (and (eq_attr "pipe_model" "sh4")
504 (eq_attr "type" "arith3b"))
508 ;; calls introduce a longisch delay that is likely to flush the pipelines.
509 (define_function_unit "single_issue" 1 0
510 (and (eq_attr "pipe_model" "sh4")
511 (eq_attr "type" "call,sfunc"))
513 [(eq_attr "type" "!call") (eq_attr "type" "call")])
515 ;; Load and store instructions have no alignment peculiarities for the SH4,
516 ;; but they use the load-store unit, which they share with the fmove type
517 ;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
518 ;; Loads have a latency of two.
519 ;; However, call insns can only paired with a preceding insn, and have
520 ;; a delay slot, so that we want two more insns to be scheduled between the
521 ;; load of the function address and the call. This is equivalent to a
523 ;; We cannot use a conflict list for this, because we need to distinguish
524 ;; between the actual call address and the function arguments.
525 ;; ADJUST_COST can only properly handle reductions of the cost, so we
526 ;; use a latency of three here, which gets multiplied by 10 to yield 30.
527 ;; We only do this for SImode loads of general registers, to make the work
528 ;; for ADJUST_COST easier.
530 ;; When specifying different latencies for different insns using the
531 ;; the same function unit, genattrtab.c assumes a 'FIFO constraint'
532 ;; so that the blockage is at least READY-COST (E) + 1 - READY-COST (C)
533 ;; for an executing insn E and a candidate insn C.
534 ;; Therefore, we define three different function units for load_store:
535 ;; load_store, load and load_si.
537 (define_function_unit "load_si" 1 0
538 (and (eq_attr "pipe_model" "sh4")
539 (eq_attr "type" "load_si,pcload_si")) 30 10)
540 (define_function_unit "load" 1 0
541 (and (eq_attr "pipe_model" "sh4")
542 (eq_attr "type" "load,pcload,pload")) 20 10)
543 (define_function_unit "load_store" 1 0
544 (and (eq_attr "pipe_model" "sh4")
545 (eq_attr "type" "load_si,pcload_si,load,pcload,pload,store,pstore,fmove"))
548 (define_function_unit "int" 1 0
549 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "arith,dyn_shift")) 10 10)
551 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
552 ;; spurious FIFO constraint; the multiply instructions use the "int"
553 ;; unit actually only for two cycles.
554 (define_function_unit "int" 1 0
555 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "smpy,dmpy")) 20 20)
557 ;; We use a fictous "mpy" unit to express the actual latency.
558 (define_function_unit "mpy" 1 0
559 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "smpy,dmpy")) 40 20)
561 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
562 ;; spurious FIFO constraint.
563 (define_function_unit "int" 1 0
564 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "gp_fpul")) 10 10)
566 ;; We use a fictous "gp_fpul" unit to express the actual latency.
567 (define_function_unit "gp_fpul" 1 0
568 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "gp_fpul")) 20 10)
570 ;; ??? multiply uses the floating point unit, but with a two cycle delay.
571 ;; Thus, a simple single-precision fp operation could finish if issued in
572 ;; the very next cycle, but stalls when issued two or three cycles later.
573 ;; Similarily, a divide / sqrt can work without stalls if issued in
574 ;; the very next cycle, while it would have to block if issued two or
575 ;; three cycles later.
576 ;; There is no way to model this with gcc's function units. This problem is
577 ;; actually mentioned in md.texi. Tackling this problem requires first that
578 ;; it is possible to speak about the target in an open discussion.
580 ;; However, simple double-precision operations always conflict.
582 (define_function_unit "fp" 1 0
583 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "smpy,dmpy")) 40 40
584 [(eq_attr "type" "dfp_cmp,dfp_conv,dfp_arith")])
586 ;; The "fp" unit is for pipeline stages F1 and F2.
588 (define_function_unit "fp" 1 0
589 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "fp")) 30 10)
591 ;; Again, we have to pretend a lower latency for the "fp" unit to avoid a
592 ;; spurious FIFO constraint; the bulk of the fdiv type insns executes in
594 (define_function_unit "fp" 1 0
595 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "fdiv")) 30 10)
597 ;; The "fdiv" function unit models the aggregate effect of the F1, F2 and F3
598 ;; pipeline stages on the pipelining of fdiv/fsqrt insns.
599 ;; We also use it to give the actual latency here.
600 ;; fsqrt is actually one cycle faster than fdiv (and the value used here),
601 ;; but that will hardly matter in practice for scheduling.
602 (define_function_unit "fdiv" 1 0
603 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "fdiv")) 120 100)
605 ;; There is again a late use of the "fp" unit by [d]fdiv type insns
606 ;; that we can't express.
608 (define_function_unit "fp" 1 0
609 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "dfp_cmp,dfp_conv")) 40 20)
611 (define_function_unit "fp" 1 0
612 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "dfp_arith")) 80 60)
614 (define_function_unit "fp" 1 0
615 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "dfdiv")) 230 10)
617 (define_function_unit "fdiv" 1 0
618 (and (eq_attr "pipe_model" "sh4") (eq_attr "type" "dfdiv")) 230 210)
620 ;; SH-5 SHmedia scheduling
621 ;; When executing SHmedia code, the SH-5 is a fairly straightforward
622 ;; single-issue machine. It has four pipelines, the branch unit (br),
623 ;; the integer and multimedia unit (imu), the load/store unit (lsu), and
624 ;; the floating point unit (fpu).
625 ;; Here model the instructions with a latency greater than one cycle.
627 ;; Every instruction on SH-5 occupies the issue resource for at least one
629 (define_function_unit "sh5issue" 1 0
630 (and (eq_attr "pipe_model" "sh5media")
631 (eq_attr "type" "!pt_media,ptabs_media,invalidate_line_media,dmpy_media,load_media,fload_media,fcmp_media,fmove_media,fparith_media,dfparith_media,fpconv_media,dfpconv_media,dfmul_media,store_media,fstore_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media")) 1 1)
633 ;; Specify the various types of instruction which have latency > 1
634 (define_function_unit "sh5issue" 1 0
635 (and (eq_attr "pipe_model" "sh5media")
636 (eq_attr "type" "mcmp_media")) 2 1)
638 (define_function_unit "sh5issue" 1 0
639 (and (eq_attr "pipe_model" "sh5media")
640 (eq_attr "type" "dmpy_media,load_media,fcmp_media,mac_media")) 3 1)
641 ;; but see sh_adjust_cost for mac_media exception.
643 (define_function_unit "sh5issue" 1 0
644 (and (eq_attr "pipe_model" "sh5media")
645 (eq_attr "type" "fload_media,fmove_media")) 4 1)
647 (define_function_unit "sh5issue" 1 0
648 (and (eq_attr "pipe_model" "sh5media")
649 (eq_attr "type" "d2mpy_media")) 4 2)
651 (define_function_unit "sh5issue" 1 0
652 (and (eq_attr "pipe_model" "sh5media")
653 (eq_attr "type" "pt_media,ptabs_media")) 5 1)
655 (define_function_unit "sh5issue" 1 0
656 (and (eq_attr "pipe_model" "sh5media")
657 (eq_attr "type" "fparith_media,dfparith_media,fpconv_media,dfpconv_media")) 6 1)
659 (define_function_unit "sh5issue" 1 0
660 (and (eq_attr "pipe_model" "sh5media")
661 (eq_attr "type" "invalidate_line_media")) 7 7)
663 (define_function_unit "sh5issue" 1 0
664 (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfmul_media")) 9 4)
666 (define_function_unit "sh5issue" 1 0
667 (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "atrans_media")) 10 5)
669 ;; Floating-point divide and square-root occupy an additional resource,
670 ;; which is not internally pipelined. However, other instructions
671 ;; can continue to issue.
672 (define_function_unit "sh5fds" 1 0
673 (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "fdiv_media")) 19 19)
675 (define_function_unit "sh5fds" 1 0
676 (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfdiv_media")) 35 35)
678 ; Definitions for filling branch delay slots.
680 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
682 ;; ??? This should be (nil) instead of (const_int 0)
683 (define_attr "hit_stack" "yes,no"
684 (cond [(eq (symbol_ref "find_regno_note (insn, REG_INC, SP_REG)")
687 (const_string "yes")))
689 (define_attr "interrupt_function" "no,yes"
690 (const (symbol_ref "current_function_interrupt")))
692 (define_attr "in_delay_slot" "yes,no"
693 (cond [(eq_attr "type" "cbranch") (const_string "no")
694 (eq_attr "type" "pcload,pcload_si") (const_string "no")
695 (eq_attr "needs_delay_slot" "yes") (const_string "no")
696 (eq_attr "length" "2") (const_string "yes")
697 ] (const_string "no")))
699 (define_attr "cond_delay_slot" "yes,no"
700 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
701 ] (const_string "no")))
703 (define_attr "is_sfunc" ""
704 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
706 (define_attr "is_mac_media" ""
707 (if_then_else (eq_attr "type" "mac_media") (const_int 1) (const_int 0)))
710 (eq_attr "needs_delay_slot" "yes")
711 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
713 ;; On the SH and SH2, the rte instruction reads the return pc from the stack,
714 ;; and thus we can't put a pop instruction in its delay slot.
715 ;; ??? On the SH3, the rte instruction does not use the stack, so a pop
716 ;; instruction can go in the delay slot.
718 ;; Since a normal return (rts) implicitly uses the PR register,
719 ;; we can't allow PR register loads in an rts delay slot.
722 (eq_attr "type" "return")
723 [(and (eq_attr "in_delay_slot" "yes")
724 (ior (and (eq_attr "interrupt_function" "no")
725 (eq_attr "type" "!pload,prset"))
726 (and (eq_attr "interrupt_function" "yes")
728 (ne (symbol_ref "TARGET_SH3") (const_int 0))
729 (eq_attr "hit_stack" "no"))))) (nil) (nil)])
731 ;; Since a call implicitly uses the PR register, we can't allow
732 ;; a PR register store in a jsr delay slot.
735 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
736 [(and (eq_attr "in_delay_slot" "yes")
737 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
739 ;; Say that we have annulled true branches, since this gives smaller and
740 ;; faster code when branches are predicted as not taken.
743 (and (eq_attr "type" "cbranch")
744 (ne (symbol_ref "TARGET_SH2") (const_int 0)))
745 [(eq_attr "in_delay_slot" "yes") (eq_attr "cond_delay_slot" "yes") (nil)])
747 ;; -------------------------------------------------------------------------
748 ;; SImode signed integer comparisons
749 ;; -------------------------------------------------------------------------
753 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
754 (match_operand:SI 1 "arith_operand" "L,r"))
758 [(set_attr "insn_class" "mt_group")])
760 ;; ??? Perhaps should only accept reg/constant if the register is reg 0.
761 ;; That would still allow reload to create cmpi instructions, but would
762 ;; perhaps allow forcing the constant into a register when that is better.
763 ;; Probably should use r0 for mem/imm compares, but force constant into a
764 ;; register for pseudo/imm compares.
766 (define_insn "cmpeqsi_t"
768 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
769 (match_operand:SI 1 "arith_operand" "N,rI,r")))]
775 [(set_attr "insn_class" "mt_group,mt_group,mt_group")])
777 (define_insn "cmpgtsi_t"
779 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
780 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
785 [(set_attr "insn_class" "mt_group,mt_group")])
787 (define_insn "cmpgesi_t"
789 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
790 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
795 [(set_attr "insn_class" "mt_group,mt_group")])
797 ;; -------------------------------------------------------------------------
798 ;; SImode unsigned integer comparisons
799 ;; -------------------------------------------------------------------------
801 (define_insn "cmpgeusi_t"
803 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
804 (match_operand:SI 1 "arith_reg_operand" "r")))]
807 [(set_attr "insn_class" "mt_group")])
809 (define_insn "cmpgtusi_t"
811 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
812 (match_operand:SI 1 "arith_reg_operand" "r")))]
815 [(set_attr "insn_class" "mt_group")])
817 ;; We save the compare operands in the cmpxx patterns and use them when
818 ;; we generate the branch.
820 (define_expand "cmpsi"
822 (compare (match_operand:SI 0 "arith_operand" "")
823 (match_operand:SI 1 "arith_operand" "")))]
827 sh_compare_op0 = operands[0];
828 sh_compare_op1 = operands[1];
832 ;; -------------------------------------------------------------------------
833 ;; DImode signed integer comparisons
834 ;; -------------------------------------------------------------------------
836 ;; ??? Could get better scheduling by splitting the initial test from the
837 ;; rest of the insn after reload. However, the gain would hardly justify
838 ;; the sh.md size increase necessary to do that.
842 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
843 (match_operand:DI 1 "arith_operand" "r"))
846 "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
848 [(set_attr "length" "6")
849 (set_attr "type" "arith3b")])
851 (define_insn "cmpeqdi_t"
853 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
854 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
857 tst %S0,%S0\;bf %,Ldi%=\;tst %R0,%R0\\n%,Ldi%=:
858 cmp/eq %S1,%S0\;bf %,Ldi%=\;cmp/eq %R1,%R0\\n%,Ldi%=:"
859 [(set_attr "length" "6")
860 (set_attr "type" "arith3b")])
864 (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
865 (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
866 ;; If we applied this split when not optimizing, it would only be
867 ;; applied during the machine-dependent reorg, when no new basic blocks
869 "TARGET_SH1 && reload_completed && optimize"
870 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
871 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
872 (label_ref (match_dup 6))
874 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
879 = gen_rtx_REG (SImode,
880 true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
882 = (operands[1] == const0_rtx
884 : gen_rtx_REG (SImode,
885 true_regnum (operands[1])
886 + (TARGET_LITTLE_ENDIAN ? 1 : 0)));
887 operands[4] = gen_lowpart (SImode, operands[0]);
888 operands[5] = gen_lowpart (SImode, operands[1]);
889 operands[6] = gen_label_rtx ();
892 (define_insn "cmpgtdi_t"
894 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
895 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
898 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
899 tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
900 [(set_attr "length" "8")
901 (set_attr "type" "arith3")])
903 (define_insn "cmpgedi_t"
905 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
906 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
909 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
911 [(set_attr "length" "8,2")
912 (set_attr "type" "arith3,arith")])
914 ;; -------------------------------------------------------------------------
915 ;; DImode unsigned integer comparisons
916 ;; -------------------------------------------------------------------------
918 (define_insn "cmpgeudi_t"
920 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
921 (match_operand:DI 1 "arith_reg_operand" "r")))]
923 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
924 [(set_attr "length" "8")
925 (set_attr "type" "arith3")])
927 (define_insn "cmpgtudi_t"
929 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
930 (match_operand:DI 1 "arith_reg_operand" "r")))]
932 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
933 [(set_attr "length" "8")
934 (set_attr "type" "arith3")])
936 (define_insn "cmpeqdi_media"
937 [(set (match_operand:DI 0 "register_operand" "=r")
938 (eq:DI (match_operand:DI 1 "register_operand" "%r")
939 (match_operand:DI 2 "arith_reg_or_0_operand" "Nr")))]
942 [(set_attr "type" "cmp_media")])
944 (define_insn "cmpgtdi_media"
945 [(set (match_operand:DI 0 "register_operand" "=r")
946 (gt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
947 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
950 [(set_attr "type" "cmp_media")])
952 (define_insn "cmpgtudi_media"
953 [(set (match_operand:DI 0 "register_operand" "=r")
954 (gtu:DI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
955 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
957 "cmpgtu %N1, %N2, %0"
958 [(set_attr "type" "cmp_media")])
960 ;; We save the compare operands in the cmpxx patterns and use them when
961 ;; we generate the branch.
963 (define_expand "cmpdi"
965 (compare (match_operand:DI 0 "arith_operand" "")
966 (match_operand:DI 1 "arith_operand" "")))]
967 "TARGET_SH2 || TARGET_SHMEDIA"
970 sh_compare_op0 = operands[0];
971 sh_compare_op1 = operands[1];
974 ;; -------------------------------------------------------------------------
975 ;; Conditional move instructions
976 ;; -------------------------------------------------------------------------
978 ;; The insn names may seem reversed, but note that cmveq performs the move
979 ;; if op1 == 0, and cmvne does it if op1 != 0.
981 (define_insn "movdicc_false"
982 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
983 (if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r")
985 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
986 (match_operand:DI 3 "arith_reg_operand" "0")))]
989 [(set_attr "type" "arith_media")])
991 (define_insn "movdicc_true"
992 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
993 (if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r")
995 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
996 (match_operand:DI 3 "arith_reg_operand" "0")))]
999 [(set_attr "type" "arith_media")])
1001 (define_expand "movdicc"
1002 [(set (match_operand:DI 0 "register_operand" "")
1003 (if_then_else:DI (match_operand 1 "comparison_operator" "")
1004 (match_operand:DI 2 "register_operand" "")
1005 (match_operand:DI 3 "register_operand" "")))]
1009 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1010 && GET_MODE (sh_compare_op0) == DImode
1011 && sh_compare_op1 == const0_rtx)
1012 operands[1] = gen_rtx (GET_CODE (operands[1]), VOIDmode,
1013 sh_compare_op0, sh_compare_op1);
1021 tmp = gen_reg_rtx (DImode);
1023 switch (GET_CODE (operands[1]))
1026 emit_insn (gen_seq (tmp));
1027 operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
1031 emit_insn (gen_seq (tmp));
1032 operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
1036 emit_insn (gen_sgt (tmp));
1037 operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
1041 emit_insn (gen_slt (tmp));
1042 operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
1046 emit_insn (gen_slt (tmp));
1047 operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
1051 emit_insn (gen_sgt (tmp));
1052 operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
1056 emit_insn (gen_sgtu (tmp));
1057 operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
1061 emit_insn (gen_sltu (tmp));
1062 operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
1066 emit_insn (gen_sltu (tmp));
1067 operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
1071 emit_insn (gen_sgtu (tmp));
1072 operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
1076 emit_insn (gen_sunordered (tmp));
1077 operands[1] = gen_rtx (NE, VOIDmode, tmp, const0_rtx);
1081 emit_insn (gen_sunordered (tmp));
1082 operands[1] = gen_rtx (EQ, VOIDmode, tmp, const0_rtx);
1099 ;; -------------------------------------------------------------------------
1100 ;; Addition instructions
1101 ;; -------------------------------------------------------------------------
1103 (define_expand "adddi3"
1104 [(set (match_operand:DI 0 "arith_reg_operand" "")
1105 (plus:DI (match_operand:DI 1 "arith_reg_operand" "")
1106 (match_operand:DI 2 "arith_operand" "")))]
1112 if (no_new_pseudos && ! arith_reg_operand (operands[2], DImode))
1114 operands[2] = force_reg (DImode, operands[2]);
1115 emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
1120 (define_insn "*adddi3_media"
1121 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
1122 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1123 (match_operand:DI 2 "arith_operand" "r,P")))]
1128 [(set_attr "type" "arith_media")])
1130 (define_insn "adddi3z_media"
1131 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1133 (plus:SI (match_operand:SI 1 "extend_reg_operand" "r")
1134 (match_operand:SI 2 "extend_reg_or_0_operand" "rN"))))]
1136 "addz.l %1, %N2, %0"
1137 [(set_attr "type" "arith_media")])
1139 (define_insn "adddi3_compact"
1140 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1141 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
1142 (match_operand:DI 2 "arith_reg_operand" "r")))
1143 (clobber (reg:SI T_REG))]
1146 [(set_attr "length" "6")])
1149 [(set (match_operand:DI 0 "arith_reg_operand" "")
1150 (plus:DI (match_operand:DI 1 "arith_reg_operand" "")
1151 (match_operand:DI 2 "arith_reg_operand" "")))
1152 (clobber (reg:SI T_REG))]
1153 "TARGET_SH1 && reload_completed"
1157 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
1158 high0 = gen_rtx_REG (SImode,
1159 true_regnum (operands[0])
1160 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
1161 high2 = gen_rtx_REG (SImode,
1162 true_regnum (operands[2])
1163 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
1164 emit_insn (gen_clrt ());
1165 emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
1166 emit_insn (gen_addc1 (high0, high0, high2));
1171 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1172 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1173 (match_operand:SI 2 "arith_reg_operand" "r"))
1176 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
1179 [(set_attr "type" "arith")
1180 (set_attr "insn_class" "ex_group")])
1182 (define_insn "addc1"
1183 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1184 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1185 (match_operand:SI 2 "arith_reg_operand" "r"))
1187 (clobber (reg:SI T_REG))]
1190 [(set_attr "type" "arith")
1191 (set_attr "insn_class" "ex_group")])
1193 (define_expand "addsi3"
1194 [(set (match_operand:SI 0 "arith_reg_operand" "")
1195 (plus:SI (match_operand:SI 1 "arith_operand" "")
1196 (match_operand:SI 2 "arith_operand" "")))]
1201 operands[1] = force_reg (SImode, operands[1]);
1204 (define_insn "addsi3_media"
1205 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
1206 (plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
1207 (match_operand:SI 2 "arith_operand" "r,P")))]
1212 [(set_attr "type" "arith_media")])
1214 (define_insn "*addsi3_compact"
1215 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1216 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
1217 (match_operand:SI 2 "arith_operand" "rI")))]
1220 [(set_attr "type" "arith")
1221 (set_attr "insn_class" "ex_group")])
1223 ;; -------------------------------------------------------------------------
1224 ;; Subtraction instructions
1225 ;; -------------------------------------------------------------------------
1227 (define_expand "subdi3"
1228 [(set (match_operand:DI 0 "arith_reg_operand" "")
1229 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "")
1230 (match_operand:DI 2 "arith_reg_operand" "")))]
1236 operands[1] = force_reg (DImode, operands[1]);
1237 emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
1242 (define_insn "*subdi3_media"
1243 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1244 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
1245 (match_operand:DI 2 "arith_reg_operand" "r")))]
1248 [(set_attr "type" "arith_media")])
1250 (define_insn "subdi3_compact"
1251 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1252 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
1253 (match_operand:DI 2 "arith_reg_operand" "r")))
1254 (clobber (reg:SI T_REG))]
1257 [(set_attr "length" "6")])
1260 [(set (match_operand:DI 0 "arith_reg_operand" "")
1261 (minus:DI (match_operand:DI 1 "arith_reg_operand" "")
1262 (match_operand:DI 2 "arith_reg_operand" "")))
1263 (clobber (reg:SI T_REG))]
1264 "TARGET_SH1 && reload_completed"
1268 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
1269 high0 = gen_rtx_REG (SImode,
1270 true_regnum (operands[0])
1271 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
1272 high2 = gen_rtx_REG (SImode,
1273 true_regnum (operands[2])
1274 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
1275 emit_insn (gen_clrt ());
1276 emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
1277 emit_insn (gen_subc1 (high0, high0, high2));
1282 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1283 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1284 (match_operand:SI 2 "arith_reg_operand" "r"))
1287 (gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
1290 [(set_attr "type" "arith")
1291 (set_attr "insn_class" "ex_group")])
1293 (define_insn "subc1"
1294 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1295 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1296 (match_operand:SI 2 "arith_reg_operand" "r"))
1298 (clobber (reg:SI T_REG))]
1301 [(set_attr "type" "arith")
1302 (set_attr "insn_class" "ex_group")])
1304 (define_insn "*subsi3_internal"
1305 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1306 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1307 (match_operand:SI 2 "arith_reg_operand" "r")))]
1310 [(set_attr "type" "arith")
1311 (set_attr "insn_class" "ex_group")])
1313 (define_insn "*subsi3_media"
1314 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1315 (minus:SI (match_operand:SI 1 "extend_reg_or_0_operand" "rN")
1316 (match_operand:SI 2 "extend_reg_operand" "r")))]
1319 [(set_attr "type" "arith_media")])
1321 ;; Convert `constant - reg' to `neg rX; add rX, #const' since this
1322 ;; will sometimes save one instruction. Otherwise we might get
1323 ;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
1326 (define_expand "subsi3"
1327 [(set (match_operand:SI 0 "arith_reg_operand" "")
1328 (minus:SI (match_operand:SI 1 "arith_operand" "")
1329 (match_operand:SI 2 "arith_reg_operand" "")))]
1333 if (TARGET_SH1 && GET_CODE (operands[1]) == CONST_INT)
1335 emit_insn (gen_negsi2 (operands[0], operands[2]));
1336 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
1341 if (no_new_pseudos && ! arith_reg_or_0_operand (operands[1], SImode))
1343 if (operands[1] != const0_rtx)
1344 operands[1] = force_reg (SImode, operands[1]);
1348 ;; -------------------------------------------------------------------------
1349 ;; Division instructions
1350 ;; -------------------------------------------------------------------------
1352 ;; We take advantage of the library routines which don't clobber as many
1353 ;; registers as a normal function call would.
1355 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
1356 ;; also has an effect on the register that holds the address of the sfunc.
1357 ;; To make this work, we have an extra dummy insn that shows the use
1358 ;; of this register for reorg.
1360 (define_insn "use_sfunc_addr"
1361 [(set (reg:SI PR_REG)
1362 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
1365 [(set_attr "length" "0")])
1367 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
1368 ;; hard register 0. If we used hard register 0, then the next instruction
1369 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
1370 ;; gets allocated to a stack slot that needs its address reloaded, then
1371 ;; there is nothing to prevent reload from using r0 to reload the address.
1372 ;; This reload would clobber the value in r0 we are trying to store.
1373 ;; If we let reload allocate r0, then this problem can never happen.
1375 (define_insn "udivsi3_i1"
1376 [(set (match_operand:SI 0 "register_operand" "=z")
1377 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1378 (clobber (reg:SI T_REG))
1379 (clobber (reg:SI PR_REG))
1380 (clobber (reg:SI R4_REG))
1381 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1382 "TARGET_SH1 && ! TARGET_SH4"
1384 [(set_attr "type" "sfunc")
1385 (set_attr "needs_delay_slot" "yes")])
1387 ; Since shmedia-nofpu code could be linked against shcompact code, and
1388 ; the udivsi3 libcall has the same name, we must consider all registers
1389 ; clobbered that are in the union of the registers clobbered by the
1390 ; shmedia and the shcompact implementation. Note, if the shcompact
1391 ; implemenation actually used shcompact code, we'd need to clobber
1392 ; also r23 and fr23.
1393 (define_insn "udivsi3_i1_media"
1394 [(set (match_operand:SI 0 "register_operand" "=z")
1395 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1396 (clobber (reg:SI T_MEDIA_REG))
1397 (clobber (reg:SI PR_MEDIA_REG))
1398 (clobber (reg:SI R20_REG))
1399 (clobber (reg:SI R21_REG))
1400 (clobber (reg:SI R22_REG))
1401 (clobber (reg:DI TR0_REG))
1402 (clobber (reg:DI TR1_REG))
1403 (clobber (reg:DI TR2_REG))
1404 (use (match_operand:DI 1 "target_operand" "b"))]
1405 "TARGET_SHMEDIA && ! TARGET_SHMEDIA_FPU"
1407 [(set_attr "type" "sfunc")
1408 (set_attr "needs_delay_slot" "yes")])
1410 (define_expand "udivsi3_i4_media"
1412 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
1414 (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
1415 (set (match_dup 5) (float:DF (match_dup 3)))
1416 (set (match_dup 6) (float:DF (match_dup 4)))
1417 (set (match_dup 7) (div:DF (match_dup 5) (match_dup 6)))
1418 (set (match_dup 8) (fix:DI (match_dup 7)))
1419 (set (match_operand:SI 0 "register_operand" "")
1420 (truncate:SI (match_dup 8)))]
1421 "TARGET_SHMEDIA_FPU"
1424 operands[3] = gen_reg_rtx (DImode);
1425 operands[4] = gen_reg_rtx (DImode);
1426 operands[5] = gen_reg_rtx (DFmode);
1427 operands[6] = gen_reg_rtx (DFmode);
1428 operands[7] = gen_reg_rtx (DFmode);
1429 operands[8] = gen_reg_rtx (DImode);
1432 (define_insn "udivsi3_i4"
1433 [(set (match_operand:SI 0 "register_operand" "=y")
1434 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1435 (clobber (reg:SI T_REG))
1436 (clobber (reg:SI PR_REG))
1437 (clobber (reg:DF DR0_REG))
1438 (clobber (reg:DF DR2_REG))
1439 (clobber (reg:DF DR4_REG))
1440 (clobber (reg:SI R0_REG))
1441 (clobber (reg:SI R1_REG))
1442 (clobber (reg:SI R4_REG))
1443 (clobber (reg:SI R5_REG))
1444 (use (reg:PSI FPSCR_REG))
1445 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1446 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1448 [(set_attr "type" "sfunc")
1449 (set_attr "fp_mode" "double")
1450 (set_attr "needs_delay_slot" "yes")])
1452 (define_insn "udivsi3_i4_single"
1453 [(set (match_operand:SI 0 "register_operand" "=y")
1454 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1455 (clobber (reg:SI T_REG))
1456 (clobber (reg:SI PR_REG))
1457 (clobber (reg:DF DR0_REG))
1458 (clobber (reg:DF DR2_REG))
1459 (clobber (reg:DF DR4_REG))
1460 (clobber (reg:SI R0_REG))
1461 (clobber (reg:SI R1_REG))
1462 (clobber (reg:SI R4_REG))
1463 (clobber (reg:SI R5_REG))
1464 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1465 "(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && TARGET_FPU_SINGLE"
1467 [(set_attr "type" "sfunc")
1468 (set_attr "needs_delay_slot" "yes")])
1470 (define_expand "udivsi3"
1471 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
1472 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1473 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1474 (parallel [(set (match_operand:SI 0 "register_operand" "")
1475 (udiv:SI (reg:SI R4_REG)
1477 (clobber (reg:SI T_REG))
1478 (clobber (reg:SI PR_REG))
1479 (clobber (reg:SI R4_REG))
1480 (use (match_dup 3))])]
1484 rtx first = 0, last;
1486 operands[3] = gen_reg_rtx (Pmode);
1487 /* Emit the move of the address to a pseudo outside of the libcall. */
1488 if (TARGET_HARD_SH4 && TARGET_SH3E)
1490 emit_move_insn (operands[3],
1491 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
1492 if (TARGET_FPU_SINGLE)
1493 last = gen_udivsi3_i4_single (operands[0], operands[3]);
1495 last = gen_udivsi3_i4 (operands[0], operands[3]);
1497 else if (TARGET_SHMEDIA_FPU)
1499 operands[1] = force_reg (SImode, operands[1]);
1500 operands[2] = force_reg (SImode, operands[2]);
1501 last = gen_udivsi3_i4_media (operands[0], operands[1], operands[2]);
1504 else if (TARGET_SH5)
1506 emit_move_insn (operands[3],
1507 gen_rtx_SYMBOL_REF (Pmode,
1513 last = gen_udivsi3_i1_media (operands[0],
1516 : gen_rtx_SUBREG (DImode, operands[3],
1518 else if (TARGET_FPU_ANY)
1519 last = gen_udivsi3_i4_single (operands[0], operands[3]);
1521 last = gen_udivsi3_i1 (operands[0], operands[3]);
1525 emit_move_insn (operands[3],
1526 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3\"));
1527 last = gen_udivsi3_i1 (operands[0], operands[3]);
1531 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1532 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1534 last = emit_insn (last);
1535 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1536 invariant code motion can move it. */
1537 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1538 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1542 (define_insn "divsi3_i1"
1543 [(set (match_operand:SI 0 "register_operand" "=z")
1544 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1545 (clobber (reg:SI T_REG))
1546 (clobber (reg:SI PR_REG))
1547 (clobber (reg:SI R1_REG))
1548 (clobber (reg:SI R2_REG))
1549 (clobber (reg:SI R3_REG))
1550 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1551 "TARGET_SH1 && ! TARGET_SH4"
1553 [(set_attr "type" "sfunc")
1554 (set_attr "needs_delay_slot" "yes")])
1556 ; Since shmedia-nofpu code could be linked against shcompact code, and
1557 ; the sdivsi3 libcall has the same name, we must consider all registers
1558 ; clobbered that are in the union of the registers clobbered by the
1559 ; shmedia and the shcompact implementation. Note, if the shcompact
1560 ; implemenation actually used shcompact code, we'd need to clobber
1561 ; also r22, r23 and fr23.
1562 (define_insn "divsi3_i1_media"
1563 [(set (match_operand:SI 0 "register_operand" "=z")
1564 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1565 (clobber (reg:SI T_MEDIA_REG))
1566 (clobber (reg:SI PR_MEDIA_REG))
1567 (clobber (reg:SI R1_REG))
1568 (clobber (reg:SI R2_REG))
1569 (clobber (reg:SI R3_REG))
1570 (clobber (reg:SI R20_REG))
1571 (clobber (reg:SI R21_REG))
1572 (clobber (reg:DI TR0_REG))
1573 (clobber (reg:DI TR1_REG))
1574 (clobber (reg:DI TR2_REG))
1575 (use (match_operand:DI 1 "target_operand" "b"))]
1576 "TARGET_SHMEDIA && ! TARGET_SHMEDIA_FPU"
1578 [(set_attr "type" "sfunc")])
1580 (define_expand "divsi3_i4_media"
1581 [(set (match_dup 3) (float:DF (match_operand:SI 1 "register_operand" "r")))
1582 (set (match_dup 4) (float:DF (match_operand:SI 2 "register_operand" "r")))
1583 (set (match_dup 5) (div:DF (match_dup 3) (match_dup 4)))
1584 (set (match_operand:SI 0 "register_operand" "=r")
1585 (fix:SI (match_dup 5)))]
1586 "TARGET_SHMEDIA_FPU"
1589 operands[3] = gen_reg_rtx (DFmode);
1590 operands[4] = gen_reg_rtx (DFmode);
1591 operands[5] = gen_reg_rtx (DFmode);
1594 (define_insn "divsi3_i4"
1595 [(set (match_operand:SI 0 "register_operand" "=y")
1596 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1597 (clobber (reg:SI PR_REG))
1598 (clobber (reg:DF DR0_REG))
1599 (clobber (reg:DF DR2_REG))
1600 (use (reg:PSI FPSCR_REG))
1601 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1602 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1604 [(set_attr "type" "sfunc")
1605 (set_attr "fp_mode" "double")
1606 (set_attr "needs_delay_slot" "yes")])
1608 (define_insn "divsi3_i4_single"
1609 [(set (match_operand:SI 0 "register_operand" "=y")
1610 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1611 (clobber (reg:SI PR_REG))
1612 (clobber (reg:DF DR0_REG))
1613 (clobber (reg:DF DR2_REG))
1614 (clobber (reg:SI R2_REG))
1615 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1616 "(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && TARGET_FPU_SINGLE"
1618 [(set_attr "type" "sfunc")
1619 (set_attr "needs_delay_slot" "yes")])
1621 (define_expand "divsi3"
1622 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
1623 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1624 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1625 (parallel [(set (match_operand:SI 0 "register_operand" "")
1626 (div:SI (reg:SI R4_REG)
1628 (clobber (reg:SI T_REG))
1629 (clobber (reg:SI PR_REG))
1630 (clobber (reg:SI R1_REG))
1631 (clobber (reg:SI R2_REG))
1632 (clobber (reg:SI R3_REG))
1633 (use (match_dup 3))])]
1637 rtx first = 0, last;
1639 operands[3] = gen_reg_rtx (Pmode);
1640 /* Emit the move of the address to a pseudo outside of the libcall. */
1641 if (TARGET_HARD_SH4 && TARGET_SH3E)
1643 emit_move_insn (operands[3],
1644 gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
1645 if (TARGET_FPU_SINGLE)
1646 last = gen_divsi3_i4_single (operands[0], operands[3]);
1648 last = gen_divsi3_i4 (operands[0], operands[3]);
1650 else if (TARGET_SHMEDIA_FPU)
1652 operands[1] = force_reg (SImode, operands[1]);
1653 operands[2] = force_reg (SImode, operands[2]);
1654 last = gen_divsi3_i4_media (operands[0], operands[1], operands[2]);
1657 else if (TARGET_SH5)
1659 emit_move_insn (operands[3],
1660 gen_rtx_SYMBOL_REF (Pmode,
1666 last = gen_divsi3_i1_media (operands[0],
1669 : gen_rtx_SUBREG (DImode, operands[3],
1671 else if (TARGET_FPU_ANY)
1672 last = gen_divsi3_i4_single (operands[0], operands[3]);
1674 last = gen_divsi3_i1 (operands[0], operands[3]);
1678 emit_move_insn (operands[3], gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3\"));
1679 last = gen_divsi3_i1 (operands[0], operands[3]);
1683 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1684 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1686 last = emit_insn (last);
1687 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1688 invariant code motion can move it. */
1689 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1690 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1694 ;; -------------------------------------------------------------------------
1695 ;; Multiplication instructions
1696 ;; -------------------------------------------------------------------------
1698 (define_insn "umulhisi3_i"
1699 [(set (reg:SI MACL_REG)
1700 (mult:SI (zero_extend:SI
1701 (match_operand:HI 0 "arith_reg_operand" "r"))
1703 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1706 [(set_attr "type" "smpy")])
1708 (define_insn "mulhisi3_i"
1709 [(set (reg:SI MACL_REG)
1710 (mult:SI (sign_extend:SI
1711 (match_operand:HI 0 "arith_reg_operand" "r"))
1713 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1716 [(set_attr "type" "smpy")])
1718 (define_expand "mulhisi3"
1719 [(set (reg:SI MACL_REG)
1720 (mult:SI (sign_extend:SI
1721 (match_operand:HI 1 "arith_reg_operand" ""))
1723 (match_operand:HI 2 "arith_reg_operand" ""))))
1724 (set (match_operand:SI 0 "arith_reg_operand" "")
1731 first = emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
1732 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
1733 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1734 invariant code motion can move it. */
1735 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1736 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1740 (define_expand "umulhisi3"
1741 [(set (reg:SI MACL_REG)
1742 (mult:SI (zero_extend:SI
1743 (match_operand:HI 1 "arith_reg_operand" ""))
1745 (match_operand:HI 2 "arith_reg_operand" ""))))
1746 (set (match_operand:SI 0 "arith_reg_operand" "")
1753 first = emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
1754 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
1755 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1756 invariant code motion can move it. */
1757 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1758 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1762 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
1763 ;; a call to a routine which clobbers known registers.
1766 [(set (match_operand:SI 1 "register_operand" "=z")
1767 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1768 (clobber (reg:SI MACL_REG))
1769 (clobber (reg:SI T_REG))
1770 (clobber (reg:SI PR_REG))
1771 (clobber (reg:SI R3_REG))
1772 (clobber (reg:SI R2_REG))
1773 (clobber (reg:SI R1_REG))
1774 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
1777 [(set_attr "type" "sfunc")
1778 (set_attr "needs_delay_slot" "yes")])
1780 (define_expand "mulsi3_call"
1781 [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1782 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1783 (parallel[(set (match_operand:SI 0 "register_operand" "")
1784 (mult:SI (reg:SI R4_REG)
1786 (clobber (reg:SI MACL_REG))
1787 (clobber (reg:SI T_REG))
1788 (clobber (reg:SI PR_REG))
1789 (clobber (reg:SI R3_REG))
1790 (clobber (reg:SI R2_REG))
1791 (clobber (reg:SI R1_REG))
1792 (use (match_operand:SI 3 "register_operand" ""))])]
1796 (define_insn "mul_l"
1797 [(set (reg:SI MACL_REG)
1798 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
1799 (match_operand:SI 1 "arith_reg_operand" "r")))]
1802 [(set_attr "type" "dmpy")])
1804 (define_expand "mulsi3"
1805 [(set (reg:SI MACL_REG)
1806 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
1807 (match_operand:SI 2 "arith_reg_operand" "")))
1808 (set (match_operand:SI 0 "arith_reg_operand" "")
1817 /* The address must be set outside the libcall,
1818 since it goes into a pseudo. */
1819 rtx sym = gen_rtx_SYMBOL_REF (SImode, \"__mulsi3\");
1820 rtx addr = force_reg (SImode, sym);
1821 rtx insns = gen_mulsi3_call (operands[0], operands[1],
1824 last = emit_insn (insns);
1828 rtx macl = gen_rtx_REG (SImode, MACL_REG);
1830 first = emit_insn (gen_mul_l (operands[1], operands[2]));
1831 /* consec_sets_giv can only recognize the first insn that sets a
1832 giv as the giv insn. So we must tag this also with a REG_EQUAL
1834 last = emit_insn (gen_movsi_i ((operands[0]), macl));
1836 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1837 invariant code motion can move it. */
1838 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1839 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1843 (define_insn "mulsidi3_i"
1844 [(set (reg:SI MACH_REG)
1848 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1849 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1851 (set (reg:SI MACL_REG)
1852 (mult:SI (match_dup 0)
1856 [(set_attr "type" "dmpy")])
1858 (define_expand "mulsidi3"
1859 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1860 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1861 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1862 "TARGET_SH2 || TARGET_SHMEDIA"
1867 emit_insn (gen_mulsidi3_compact (operands[0], operands[1],
1873 (define_insn "mulsidi3_media"
1874 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1875 (mult:DI (sign_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
1876 (sign_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
1879 [(set_attr "type" "dmpy_media")])
1881 (define_insn "mulsidi3_compact"
1882 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1884 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1885 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1886 (clobber (reg:SI MACH_REG))
1887 (clobber (reg:SI MACL_REG))]
1892 [(set (match_operand:DI 0 "arith_reg_operand" "")
1894 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1895 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1896 (clobber (reg:SI MACH_REG))
1897 (clobber (reg:SI MACL_REG))]
1902 rtx low_dst = gen_lowpart (SImode, operands[0]);
1903 rtx high_dst = gen_highpart (SImode, operands[0]);
1905 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
1907 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
1908 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
1909 /* We need something to tag the possible REG_EQUAL notes on to. */
1910 emit_move_insn (operands[0], operands[0]);
1914 (define_insn "umulsidi3_i"
1915 [(set (reg:SI MACH_REG)
1919 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1920 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1922 (set (reg:SI MACL_REG)
1923 (mult:SI (match_dup 0)
1927 [(set_attr "type" "dmpy")])
1929 (define_expand "umulsidi3"
1930 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1931 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1932 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1933 "TARGET_SH2 || TARGET_SHMEDIA"
1938 emit_insn (gen_umulsidi3_compact (operands[0], operands[1],
1944 (define_insn "umulsidi3_media"
1945 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1946 (mult:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
1947 (zero_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
1950 [(set_attr "type" "dmpy_media")])
1952 (define_insn "umulsidi3_compact"
1953 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1955 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1956 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1957 (clobber (reg:SI MACH_REG))
1958 (clobber (reg:SI MACL_REG))]
1963 [(set (match_operand:DI 0 "arith_reg_operand" "")
1964 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1965 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1966 (clobber (reg:SI MACH_REG))
1967 (clobber (reg:SI MACL_REG))]
1972 rtx low_dst = gen_lowpart (SImode, operands[0]);
1973 rtx high_dst = gen_highpart (SImode, operands[0]);
1975 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
1977 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
1978 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
1979 /* We need something to tag the possible REG_EQUAL notes on to. */
1980 emit_move_insn (operands[0], operands[0]);
1984 (define_insn "smulsi3_highpart_i"
1985 [(set (reg:SI MACH_REG)
1989 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1990 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1992 (clobber (reg:SI MACL_REG))]
1995 [(set_attr "type" "dmpy")])
1997 (define_expand "smulsi3_highpart"
1999 [(set (reg:SI MACH_REG)
2003 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
2004 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
2006 (clobber (reg:SI MACL_REG))])
2007 (set (match_operand:SI 0 "arith_reg_operand" "")
2014 first = emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
2015 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
2016 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
2017 invariant code motion can move it. */
2018 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
2019 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
2020 /* expand_binop can't find a suitable code in mul_highpart_optab to
2021 make a REG_EQUAL note from, so make one here.
2022 ??? Alternatively, we could put this at the calling site of expand_binop,
2023 i.e. expand_mult_highpart. */
2025 = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
2030 (define_insn "umulsi3_highpart_i"
2031 [(set (reg:SI MACH_REG)
2035 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2036 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2038 (clobber (reg:SI MACL_REG))]
2041 [(set_attr "type" "dmpy")])
2043 (define_expand "umulsi3_highpart"
2045 [(set (reg:SI MACH_REG)
2049 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
2050 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
2052 (clobber (reg:SI MACL_REG))])
2053 (set (match_operand:SI 0 "arith_reg_operand" "")
2060 first = emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
2061 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
2062 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
2063 invariant code motion can move it. */
2064 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
2065 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
2069 ;; -------------------------------------------------------------------------
2070 ;; Logical operations
2071 ;; -------------------------------------------------------------------------
2073 (define_insn "*andsi3_compact"
2074 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
2075 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
2076 (match_operand:SI 2 "logical_operand" "r,L")))]
2079 [(set_attr "type" "arith")
2080 (set_attr "insn_class" "ex_group")])
2082 ;; If the constant is 255, then emit a extu.b instruction instead of an
2083 ;; and, since that will give better code.
2085 (define_expand "andsi3"
2086 [(set (match_operand:SI 0 "arith_reg_operand" "")
2087 (and:SI (match_operand:SI 1 "arith_reg_operand" "")
2088 (match_operand:SI 2 "logical_operand" "")))]
2092 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
2094 emit_insn (gen_zero_extendqisi2 (operands[0],
2095 gen_lowpart (QImode, operands[1])));
2100 (define_insn_and_split "anddi3"
2101 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r,r")
2102 (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
2103 (match_operand:DI 2 "and_operand" "r,P,n")))]
2110 && ! logical_operand (operands[2], DImode)"
2114 if (INTVAL (operands[2]) == (unsigned) 0xffffffff)
2115 emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode)));
2117 emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1]));
2120 [(set_attr "type" "arith_media")])
2122 (define_insn "andcdi3"
2123 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
2124 (and:DI (match_operand:DI 1 "arith_reg_operand" "r")
2125 (not:DI (match_operand:DI 2 "arith_reg_operand" "r"))))]
2128 [(set_attr "type" "arith_media")])
2130 (define_insn "iorsi3"
2131 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
2132 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
2133 (match_operand:SI 2 "logical_operand" "r,L")))]
2136 [(set_attr "type" "arith")
2137 (set_attr "insn_class" "ex_group")])
2139 (define_insn "iordi3"
2140 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
2141 (ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
2142 (match_operand:DI 2 "logical_operand" "r,P")))]
2147 [(set_attr "type" "arith_media")])
2149 (define_insn "xorsi3"
2150 [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
2151 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
2152 (match_operand:SI 2 "logical_operand" "L,r")))]
2155 [(set_attr "type" "arith")
2156 (set_attr "insn_class" "ex_group")])
2158 (define_insn "xordi3"
2159 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
2160 (xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
2161 (match_operand:DI 2 "shmedia_6bit_operand" "r,O")))]
2166 [(set_attr "type" "arith_media")])
2168 ;; -------------------------------------------------------------------------
2169 ;; Shifts and rotates
2170 ;; -------------------------------------------------------------------------
2172 (define_expand "rotldi3"
2173 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2174 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
2175 (match_operand:HI 2 "mextr_bit_offset" "i")))]
2177 "if (! mextr_bit_offset (operands[2], HImode)) FAIL;")
2179 (define_insn "rotldi3_mextr"
2180 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2181 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
2182 (match_operand:HI 2 "mextr_bit_offset" "i")))]
2186 static char templ[16];
2188 sprintf (templ, \"mextr%d\\t%%1,%%1,%%0\",
2189 8 - (int) (INTVAL (operands[2]) >> 3));
2192 [(set_attr "type" "arith_media")])
2194 (define_expand "rotrdi3"
2195 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2196 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
2197 (match_operand:HI 2 "mextr_bit_offset" "i")))]
2199 "if (! mextr_bit_offset (operands[2], HImode)) FAIL;")
2201 (define_insn "rotrdi3_mextr"
2202 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2203 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
2204 (match_operand:HI 2 "mextr_bit_offset" "i")))]
2208 static char templ[16];
2210 sprintf (templ, \"mextr%d\\t%%1,%%1,%%0\", (int) INTVAL (operands[2]) >> 3);
2213 [(set_attr "type" "arith_media")])
2215 (define_insn "rotlsi3_1"
2216 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2217 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2220 (lshiftrt:SI (match_dup 1) (const_int 31)))]
2223 [(set_attr "type" "arith")
2224 (set_attr "insn_class" "ex_group")])
2226 (define_insn "rotlsi3_31"
2227 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2228 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2230 (clobber (reg:SI T_REG))]
2233 [(set_attr "type" "arith")
2234 (set_attr "insn_class" "ex_group")])
2236 (define_insn "rotlsi3_16"
2237 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2238 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
2242 [(set_attr "type" "arith")
2243 (set_attr "insn_class" "ex_group")])
2245 (define_expand "rotlsi3"
2246 [(set (match_operand:SI 0 "arith_reg_operand" "")
2247 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
2248 (match_operand:SI 2 "immediate_operand" "")))]
2252 static const char rot_tab[] = {
2253 000, 000, 000, 000, 000, 000, 010, 001,
2254 001, 001, 011, 013, 003, 003, 003, 003,
2255 003, 003, 003, 003, 003, 013, 012, 002,
2256 002, 002, 010, 000, 000, 000, 000, 000,
2261 if (GET_CODE (operands[2]) != CONST_INT)
2263 count = INTVAL (operands[2]);
2264 choice = rot_tab[count];
2265 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
2271 emit_move_insn (operands[0], operands[1]);
2272 count -= (count & 16) * 2;
2275 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
2282 parts[0] = gen_reg_rtx (SImode);
2283 parts[1] = gen_reg_rtx (SImode);
2284 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
2285 parts[choice-1] = operands[1];
2286 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
2287 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
2288 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
2289 count = (count & ~16) - 8;
2293 for (; count > 0; count--)
2294 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2295 for (; count < 0; count++)
2296 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2301 (define_insn "*rotlhi3_8"
2302 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
2303 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
2307 [(set_attr "type" "arith")
2308 (set_attr "insn_class" "ex_group")])
2310 (define_expand "rotlhi3"
2311 [(set (match_operand:HI 0 "arith_reg_operand" "")
2312 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
2313 (match_operand:HI 2 "immediate_operand" "")))]
2317 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
2324 ;; This pattern is used by init_expmed for computing the costs of shift
2327 (define_insn_and_split "ashlsi3_std"
2328 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r")
2329 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
2330 (match_operand:SI 2 "nonmemory_operand" "r,M,K,?ri")))
2331 (clobber (match_scratch:SI 3 "=X,X,X,&r"))]
2333 || (TARGET_SH1 && GET_CODE (operands[2]) == CONST_INT
2334 && CONST_OK_FOR_K (INTVAL (operands[2])))"
2342 && GET_CODE (operands[2]) == CONST_INT
2343 && ! CONST_OK_FOR_K (INTVAL (operands[2]))"
2344 [(set (match_dup 3) (match_dup 2))
2346 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
2347 (clobber (match_dup 4))])]
2348 "operands[4] = gen_rtx_SCRATCH (SImode);"
2349 [(set_attr "length" "*,*,*,4")
2350 (set_attr "type" "dyn_shift,arith,arith,arith")
2351 (set_attr "insn_class" "ex_group,ex_group,ex_group,ex_group")])
2353 (define_insn "ashlhi3_k"
2354 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
2355 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
2356 (match_operand:HI 2 "const_int_operand" "M,K")))]
2357 "TARGET_SH1 && CONST_OK_FOR_K (INTVAL (operands[2]))"
2361 [(set_attr "type" "arith")
2362 (set_attr "insn_class" "ex_group")])
2364 (define_insn "ashlsi3_n"
2365 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2366 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
2367 (match_operand:SI 2 "const_int_operand" "n")))
2368 (clobber (reg:SI T_REG))]
2369 "TARGET_SH1 && ! sh_dynamicalize_shift_p (operands[2])"
2371 [(set (attr "length")
2372 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
2374 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
2376 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
2378 (const_string "8")))
2379 (set_attr "type" "arith")
2380 (set_attr "insn_class" "ex_group")])
2383 [(set (match_operand:SI 0 "arith_reg_operand" "")
2384 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
2385 (match_operand:SI 2 "const_int_operand" "")))
2386 (clobber (reg:SI T_REG))]
2387 "TARGET_SH1 && reload_completed"
2388 [(use (reg:SI R0_REG))]
2391 gen_shifty_op (ASHIFT, operands);
2395 (define_insn "ashlsi3_media"
2396 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2397 (ashift:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
2398 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
2403 [(set_attr "type" "arith_media")])
2405 (define_expand "ashlsi3"
2406 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
2407 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
2408 (match_operand:SI 2 "nonmemory_operand" "")))
2409 (clobber (reg:SI T_REG))])]
2415 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
2418 if (GET_CODE (operands[2]) == CONST_INT
2419 && sh_dynamicalize_shift_p (operands[2]))
2420 operands[2] = force_reg (SImode, operands[2]);
2423 emit_insn (gen_ashlsi3_std (operands[0], operands[1], operands[2]));
2426 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
2430 (define_insn "ashlhi3"
2431 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
2432 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
2433 (match_operand:HI 2 "const_int_operand" "n")))
2434 (clobber (reg:SI T_REG))]
2437 [(set (attr "length")
2438 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
2440 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
2442 (const_string "6")))
2443 (set_attr "type" "arith")])
2446 [(set (match_operand:HI 0 "arith_reg_operand" "")
2447 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
2448 (match_operand:HI 2 "const_int_operand" "")))
2449 (clobber (reg:SI T_REG))]
2450 "TARGET_SH1 && reload_completed"
2451 [(use (reg:SI R0_REG))]
2454 gen_shifty_hi_op (ASHIFT, operands);
2459 ; arithmetic shift right
2462 (define_insn "ashrsi3_k"
2463 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2464 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2465 (match_operand:SI 2 "const_int_operand" "M")))
2466 (clobber (reg:SI T_REG))]
2467 "TARGET_SH1 && INTVAL (operands[2]) == 1"
2469 [(set_attr "type" "arith")
2470 (set_attr "insn_class" "ex_group")])
2472 ;; We can't do HImode right shifts correctly unless we start out with an
2473 ;; explicit zero / sign extension; doing that would result in worse overall
2474 ;; code, so just let the machine independent code widen the mode.
2475 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
2478 ;; ??? This should be a define expand.
2480 (define_insn "ashrsi2_16"
2481 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2482 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
2486 [(set_attr "length" "4")])
2489 [(set (match_operand:SI 0 "arith_reg_operand" "")
2490 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
2493 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
2494 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
2495 "operands[2] = gen_lowpart (HImode, operands[0]);")
2497 ;; ??? This should be a define expand.
2499 (define_insn "ashrsi2_31"
2500 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2501 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2503 (clobber (reg:SI T_REG))]
2506 [(set_attr "length" "4")])
2509 [(set (match_operand:SI 0 "arith_reg_operand" "")
2510 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
2512 (clobber (reg:SI T_REG))]
2517 emit_insn (gen_ashlsi_c (operands[0], operands[1]));
2518 emit_insn (gen_subc1 (operands[0], operands[0], operands[0]));
2522 (define_insn "ashlsi_c"
2523 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2524 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
2526 (lt:SI (match_dup 1) (const_int 0)))]
2529 [(set_attr "type" "arith")
2530 (set_attr "insn_class" "ex_group")])
2532 (define_insn "ashrsi3_d"
2533 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2534 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2535 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
2538 [(set_attr "type" "dyn_shift")
2539 (set_attr "insn_class" "ex_group")])
2541 (define_insn "ashrsi3_n"
2542 [(set (reg:SI R4_REG)
2543 (ashiftrt:SI (reg:SI R4_REG)
2544 (match_operand:SI 0 "const_int_operand" "i")))
2545 (clobber (reg:SI T_REG))
2546 (clobber (reg:SI PR_REG))
2547 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2550 [(set_attr "type" "sfunc")
2551 (set_attr "needs_delay_slot" "yes")])
2553 (define_insn "ashrsi3_media"
2554 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2555 (ashiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
2556 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
2561 [(set_attr "type" "arith_media")])
2563 (define_expand "ashrsi3"
2564 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
2565 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
2566 (match_operand:SI 2 "nonmemory_operand" "")))
2567 (clobber (reg:SI T_REG))])]
2573 emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
2576 if (expand_ashiftrt (operands))
2582 ;; logical shift right
2584 (define_insn "lshrsi3_d"
2585 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2586 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2587 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
2590 [(set_attr "type" "dyn_shift")
2591 (set_attr "insn_class" "ex_group")])
2593 ;; Only the single bit shift clobbers the T bit.
2595 (define_insn "lshrsi3_m"
2596 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2597 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2598 (match_operand:SI 2 "const_int_operand" "M")))
2599 (clobber (reg:SI T_REG))]
2600 "TARGET_SH1 && CONST_OK_FOR_M (INTVAL (operands[2]))"
2602 [(set_attr "type" "arith")
2603 (set_attr "insn_class" "ex_group")])
2605 (define_insn "lshrsi3_k"
2606 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2607 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2608 (match_operand:SI 2 "const_int_operand" "K")))]
2609 "TARGET_SH1 && CONST_OK_FOR_K (INTVAL (operands[2]))
2610 && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
2612 [(set_attr "type" "arith")
2613 (set_attr "insn_class" "ex_group")])
2615 (define_insn "lshrsi3_n"
2616 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2617 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2618 (match_operand:SI 2 "const_int_operand" "n")))
2619 (clobber (reg:SI T_REG))]
2620 "TARGET_SH1 && ! sh_dynamicalize_shift_p (operands[2])"
2622 [(set (attr "length")
2623 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
2625 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
2627 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
2629 (const_string "8")))
2630 (set_attr "type" "arith")])
2633 [(set (match_operand:SI 0 "arith_reg_operand" "")
2634 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
2635 (match_operand:SI 2 "const_int_operand" "")))
2636 (clobber (reg:SI T_REG))]
2637 "TARGET_SH1 && reload_completed"
2638 [(use (reg:SI R0_REG))]
2641 gen_shifty_op (LSHIFTRT, operands);
2645 (define_insn "lshrsi3_media"
2646 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2647 (lshiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
2648 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
2653 [(set_attr "type" "arith_media")])
2655 (define_expand "lshrsi3"
2656 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
2657 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
2658 (match_operand:SI 2 "nonmemory_operand" "")))
2659 (clobber (reg:SI T_REG))])]
2665 emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2]));
2668 if (GET_CODE (operands[2]) == CONST_INT
2669 && sh_dynamicalize_shift_p (operands[2]))
2670 operands[2] = force_reg (SImode, operands[2]);
2671 if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
2673 rtx count = copy_to_mode_reg (SImode, operands[2]);
2674 emit_insn (gen_negsi2 (count, count));
2675 emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
2678 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
2682 ;; ??? This should be a define expand.
2684 (define_insn "ashldi3_k"
2685 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
2686 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
2688 (clobber (reg:SI T_REG))]
2690 "shll %R0\;rotcl %S0"
2691 [(set_attr "length" "4")
2692 (set_attr "type" "arith")
2693 (set_attr "insn_class" "ex_group")])
2695 (define_insn "ashldi3_media"
2696 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
2697 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
2698 (match_operand:DI 2 "nonmemory_operand" "r,n")))]
2703 [(set_attr "type" "arith_media")])
2705 (define_expand "ashldi3"
2706 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
2707 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
2708 (match_operand:DI 2 "immediate_operand" "")))
2709 (clobber (reg:SI T_REG))])]
2715 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
2718 if (GET_CODE (operands[2]) != CONST_INT
2719 || INTVAL (operands[2]) != 1)
2723 ;; ??? This should be a define expand.
2725 (define_insn "lshrdi3_k"
2726 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
2727 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
2729 (clobber (reg:SI T_REG))]
2731 "shlr %S0\;rotcr %R0"
2732 [(set_attr "length" "4")
2733 (set_attr "type" "arith")
2734 (set_attr "insn_class" "ex_group")])
2736 (define_insn "lshrdi3_media"
2737 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
2738 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
2739 (match_operand:DI 2 "nonmemory_operand" "r,n")))]
2744 [(set_attr "type" "arith_media")])
2746 (define_expand "lshrdi3"
2747 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
2748 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
2749 (match_operand:DI 2 "immediate_operand" "")))
2750 (clobber (reg:SI T_REG))])]
2756 emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2]));
2759 if (GET_CODE (operands[2]) != CONST_INT
2760 || INTVAL (operands[2]) != 1)
2764 ;; ??? This should be a define expand.
2766 (define_insn "ashrdi3_k"
2767 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
2768 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
2770 (clobber (reg:SI T_REG))]
2772 "shar %S0\;rotcr %R0"
2773 [(set_attr "length" "4")
2774 (set_attr "type" "arith")
2775 (set_attr "insn_class" "ex_group")])
2777 (define_insn "ashrdi3_media"
2778 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
2779 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
2780 (match_operand:DI 2 "nonmemory_operand" "r,n")))]
2785 [(set_attr "type" "arith_media")])
2787 (define_expand "ashrdi3"
2788 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
2789 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
2790 (match_operand:DI 2 "immediate_operand" "")))
2791 (clobber (reg:SI T_REG))])]
2797 emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
2800 if (GET_CODE (operands[2]) != CONST_INT
2801 || INTVAL (operands[2]) != 1)
2805 ;; combined left/right shift
2808 [(set (match_operand:SI 0 "register_operand" "")
2809 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
2810 (match_operand:SI 2 "const_int_operand" ""))
2811 (match_operand:SI 3 "const_int_operand" "")))]
2812 "TARGET_SH1 && (unsigned)INTVAL (operands[2]) < 32"
2813 [(use (reg:SI R0_REG))]
2814 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
2818 [(set (match_operand:SI 0 "register_operand" "")
2819 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
2820 (match_operand:SI 2 "const_int_operand" ""))
2821 (match_operand:SI 3 "const_int_operand" "")))
2822 (clobber (reg:SI T_REG))]
2823 "TARGET_SH1 && (unsigned)INTVAL (operands[2]) < 32"
2824 [(use (reg:SI R0_REG))]
2825 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
2829 [(set (match_operand:SI 0 "register_operand" "=r")
2830 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2831 (match_operand:SI 2 "const_int_operand" "n"))
2832 (match_operand:SI 3 "const_int_operand" "n")))
2833 (clobber (reg:SI T_REG))]
2834 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
2836 [(set (attr "length")
2837 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
2839 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
2841 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
2843 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
2845 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
2847 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
2849 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
2850 (const_string "16")]
2851 (const_string "18")))
2852 (set_attr "type" "arith")])
2855 [(set (match_operand:SI 0 "register_operand" "=z")
2856 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2857 (match_operand:SI 2 "const_int_operand" "n"))
2858 (match_operand:SI 3 "const_int_operand" "n")))
2859 (clobber (reg:SI T_REG))]
2860 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
2862 [(set (attr "length")
2863 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
2865 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
2867 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
2869 (const_string "10")))
2870 (set_attr "type" "arith")])
2872 ;; shift left / and combination with a scratch register: The combine pass
2873 ;; does not accept the individual instructions, even though they are
2874 ;; cheap. But it needs a precise description so that it is usable after
2876 (define_insn "and_shl_scratch"
2877 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2881 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
2882 (match_operand:SI 2 "const_int_operand" "N,n"))
2883 (match_operand:SI 3 "" "0,r"))
2884 (match_operand:SI 4 "const_int_operand" "n,n"))
2885 (match_operand:SI 5 "const_int_operand" "n,n")))
2886 (clobber (reg:SI T_REG))]
2889 [(set (attr "length")
2890 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
2892 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
2894 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
2896 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
2897 (const_string "10")]
2898 (const_string "12")))
2899 (set_attr "type" "arith")])
2902 [(set (match_operand:SI 0 "register_operand" "")
2906 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
2907 (match_operand:SI 2 "const_int_operand" ""))
2908 (match_operand:SI 3 "register_operand" ""))
2909 (match_operand:SI 4 "const_int_operand" ""))
2910 (match_operand:SI 5 "const_int_operand" "")))
2911 (clobber (reg:SI T_REG))]
2913 [(use (reg:SI R0_REG))]
2916 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
2918 if (INTVAL (operands[2]))
2920 gen_shifty_op (LSHIFTRT, operands);
2922 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
2923 operands[2] = operands[4];
2924 gen_shifty_op (ASHIFT, operands);
2925 if (INTVAL (operands[5]))
2927 operands[2] = operands[5];
2928 gen_shifty_op (LSHIFTRT, operands);
2933 ;; signed left/right shift combination.
2935 [(set (match_operand:SI 0 "register_operand" "")
2937 (ashift:SI (match_operand:SI 1 "register_operand" "")
2938 (match_operand:SI 2 "const_int_operand" ""))
2939 (match_operand:SI 3 "const_int_operand" "")
2941 (clobber (reg:SI T_REG))]
2943 [(use (reg:SI R0_REG))]
2944 "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
2947 (define_insn "shl_sext_ext"
2948 [(set (match_operand:SI 0 "register_operand" "=r")
2950 (ashift:SI (match_operand:SI 1 "register_operand" "0")
2951 (match_operand:SI 2 "const_int_operand" "n"))
2952 (match_operand:SI 3 "const_int_operand" "n")
2954 (clobber (reg:SI T_REG))]
2955 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
2957 [(set (attr "length")
2958 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 1))
2960 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
2962 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2964 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2966 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2968 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2970 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
2972 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
2973 (const_string "16")]
2974 (const_string "18")))
2975 (set_attr "type" "arith")])
2977 (define_insn "shl_sext_sub"
2978 [(set (match_operand:SI 0 "register_operand" "=z")
2980 (ashift:SI (match_operand:SI 1 "register_operand" "0")
2981 (match_operand:SI 2 "const_int_operand" "n"))
2982 (match_operand:SI 3 "const_int_operand" "n")
2984 (clobber (reg:SI T_REG))]
2985 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
2987 [(set (attr "length")
2988 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2990 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2992 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2994 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2995 (const_string "12")]
2996 (const_string "14")))
2997 (set_attr "type" "arith")])
2999 ;; These patterns are found in expansions of DImode shifts by 16, and
3000 ;; allow the xtrct instruction to be generated from C source.
3002 (define_insn "xtrct_left"
3003 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3004 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
3006 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
3010 [(set_attr "type" "arith")
3011 (set_attr "insn_class" "ex_group")])
3013 (define_insn "xtrct_right"
3014 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3015 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3017 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
3021 [(set_attr "type" "arith")
3022 (set_attr "insn_class" "ex_group")])
3024 ;; -------------------------------------------------------------------------
3026 ;; -------------------------------------------------------------------------
3029 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3030 (neg:SI (plus:SI (reg:SI T_REG)
3031 (match_operand:SI 1 "arith_reg_operand" "r"))))
3033 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
3037 [(set_attr "type" "arith")
3038 (set_attr "insn_class" "ex_group")])
3040 (define_insn "*negdi_media"
3041 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
3042 (neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
3045 [(set_attr "type" "arith_media")])
3047 (define_expand "negdi2"
3048 [(set (match_operand:DI 0 "arith_reg_operand" "")
3049 (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))]
3055 int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
3056 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
3058 rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
3059 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
3061 rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
3062 rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
3064 emit_insn (gen_clrt ());
3065 emit_insn (gen_negc (low_dst, low_src));
3066 emit_insn (gen_negc (high_dst, high_src));
3071 (define_insn "negsi2"
3072 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3073 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
3076 [(set_attr "type" "arith")
3077 (set_attr "insn_class" "ex_group")])
3079 (define_insn "one_cmplsi2"
3080 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3081 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
3084 [(set_attr "type" "arith")
3085 (set_attr "insn_class" "ex_group")])
3087 (define_expand "one_cmpldi2"
3088 [(set (match_operand:DI 0 "arith_reg_operand" "")
3089 (xor:DI (match_operand:DI 1 "arith_reg_operand" "")
3091 "TARGET_SHMEDIA" "")
3093 ;; -------------------------------------------------------------------------
3094 ;; Zero extension instructions
3095 ;; -------------------------------------------------------------------------
3097 (define_insn "zero_extendsidi2"
3098 [(set (match_operand:DI 0 "register_operand" "=r")
3099 (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "r")))]
3101 "addz.l %1, r63, %0"
3102 [(set_attr "type" "arith_media")])
3104 (define_insn "zero_extendhidi2"
3105 [(set (match_operand:DI 0 "register_operand" "=r,r")
3106 (zero_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
3111 [(set_attr "type" "*,load_media")])
3114 [(set (match_operand:DI 0 "register_operand" "")
3115 (zero_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
3116 "TARGET_SHMEDIA && reload_completed"
3117 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
3118 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))]
3121 if (GET_CODE (operands[1]) == TRUNCATE)
3122 operands[1] = XEXP (operands[1], 0);
3125 ;; ??? when a truncated input to a zero_extrend is reloaded, reload will
3126 ;; reload the entrire truncate expression.
3127 (define_insn_and_split "*loaddi_trunc"
3128 [(set (match_operand 0 "int_gpr_dest" "=r")
3129 (truncate (match_operand:DI 1 "memory_operand" "m")))]
3130 "TARGET_SHMEDIA && reload_completed"
3132 "TARGET_SHMEDIA && reload_completed"
3133 [(set (match_dup 0) (match_dup 1))]
3134 "operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));")
3136 (define_insn "zero_extendqidi2"
3137 [(set (match_operand:DI 0 "register_operand" "=r,r")
3138 (zero_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
3143 [(set_attr "type" "arith_media,load_media")])
3145 (define_expand "zero_extendhisi2"
3146 [(set (match_operand:SI 0 "arith_reg_operand" "")
3147 (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "")))]
3151 if (! TARGET_SHMEDIA && ! arith_reg_operand (operands[1], HImode))
3152 operands[1] = copy_to_mode_reg (HImode, operands[1]);
3155 (define_insn "*zero_extendhisi2_compact"
3156 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3157 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
3160 [(set_attr "type" "arith")
3161 (set_attr "insn_class" "ex_group")])
3163 (define_insn "*zero_extendhisi2_media"
3164 [(set (match_operand:SI 0 "register_operand" "=r,r")
3165 (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
3170 [(set_attr "type" "arith_media,load_media")])
3173 [(set (match_operand:SI 0 "register_operand" "")
3174 (zero_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
3175 "TARGET_SHMEDIA && reload_completed"
3176 [(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 16)))
3177 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
3180 if (GET_CODE (operands[1]) == TRUNCATE)
3181 operands[1] = XEXP (operands[1], 0);
3184 (define_expand "zero_extendqisi2"
3185 [(set (match_operand:SI 0 "arith_reg_operand" "")
3186 (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "")))]
3190 if (! TARGET_SHMEDIA && ! arith_reg_operand (operands[1], QImode))
3191 operands[1] = copy_to_mode_reg (QImode, operands[1]);
3194 (define_insn "*zero_extendqisi2_compact"
3195 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3196 (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
3199 [(set_attr "type" "arith")
3200 (set_attr "insn_class" "ex_group")])
3202 (define_insn "*zero_extendqisi2_media"
3203 [(set (match_operand:SI 0 "register_operand" "=r,r")
3204 (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
3209 [(set_attr "type" "arith_media,load_media")])
3211 (define_insn "zero_extendqihi2"
3212 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
3213 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
3216 [(set_attr "type" "arith")
3217 (set_attr "insn_class" "ex_group")])
3219 ;; -------------------------------------------------------------------------
3220 ;; Sign extension instructions
3221 ;; -------------------------------------------------------------------------
3223 ;; ??? This should be a define expand.
3224 ;; ??? Or perhaps it should be dropped?
3226 ;; convert_move generates good code for SH[1-4].
3227 (define_insn "extendsidi2"
3228 [(set (match_operand:DI 0 "register_operand" "=r,r")
3229 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
3234 [(set_attr "type" "arith_media,load_media")])
3236 (define_insn "extendhidi2"
3237 [(set (match_operand:DI 0 "register_operand" "=r,r")
3238 (sign_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
3243 [(set_attr "type" "*,load_media")])
3246 [(set (match_operand:DI 0 "register_operand" "")
3247 (sign_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
3248 "TARGET_SHMEDIA && reload_completed"
3249 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
3250 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))]
3253 if (GET_CODE (operands[1]) == TRUNCATE)
3254 operands[1] = XEXP (operands[1], 0);
3257 (define_insn "extendqidi2"
3258 [(set (match_operand:DI 0 "register_operand" "=r,r")
3259 (sign_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
3264 [(set_attr "type" "*,load_media")])
3267 [(set (match_operand:DI 0 "register_operand" "")
3268 (sign_extend:DI (match_operand:QI 1 "extend_reg_operand" "")))]
3269 "TARGET_SHMEDIA && reload_completed"
3270 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 56)))
3271 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))]
3274 if (GET_CODE (operands[1]) == TRUNCATE)
3275 operands[1] = XEXP (operands[1], 0);
3278 (define_expand "extendhisi2"
3279 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
3280 (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
3284 (define_insn "*extendhisi2_compact"
3285 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
3286 (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
3291 [(set_attr "type" "arith,load")
3292 (set_attr "insn_class" "ex_group,*")])
3294 (define_insn "*extendhisi2_media"
3295 [(set (match_operand:SI 0 "register_operand" "=r,r")
3296 (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
3301 [(set_attr "type" "arith_media,load_media")])
3304 [(set (match_operand:SI 0 "register_operand" "")
3305 (sign_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
3306 "TARGET_SHMEDIA && reload_completed"
3307 [(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 16)))
3308 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
3311 if (GET_CODE (operands[1]) == TRUNCATE)
3312 operands[1] = XEXP (operands[1], 0);
3315 (define_expand "extendqisi2"
3316 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
3317 (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
3321 (define_insn "*extendqisi2_compact"
3322 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
3323 (sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
3328 [(set_attr "type" "arith,load")
3329 (set_attr "insn_class" "ex_group,*")])
3331 (define_insn "*extendqisi2_media"
3332 [(set (match_operand:SI 0 "register_operand" "=r,r")
3333 (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
3338 [(set_attr "type" "arith_media,load_media")])
3341 [(set (match_operand:SI 0 "register_operand" "")
3342 (sign_extend:SI (match_operand:QI 1 "extend_reg_operand" "")))]
3343 "TARGET_SHMEDIA && reload_completed"
3344 [(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 24)))
3345 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
3348 if (GET_CODE (operands[1]) == TRUNCATE)
3349 operands[1] = XEXP (operands[1], 0);
3352 (define_insn "extendqihi2"
3353 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
3354 (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
3359 [(set_attr "type" "arith,load")
3360 (set_attr "insn_class" "ex_group,*")])
3362 /* It would seem useful to combine the truncXi patterns into the movXi
3363 patterns, but unary operators are ignored when matching constraints,
3364 so we need separate patterns. */
3365 (define_insn "truncdisi2"
3366 [(set (match_operand:SI 0 "general_movdst_operand" "=r,m,m,f,r,f")
3367 (truncate:SI (match_operand:DI 1 "register_operand" "r,r,f,r,f,f")))]
3376 [(set_attr "type" "arith_media,store_media,fstore_media,fload_media,fpconv_media,fmove_media")])
3379 (define_insn "truncdihi2"
3380 [(set (match_operand:HI 0 "general_movdst_operand" "=?r,m")
3381 (truncate:HI (match_operand:DI 1 "register_operand" "r,r")))]
3384 shlli\\t%1,48,%0\;shlri\\t%0,48,%0
3386 [(set_attr "type" "arith_media,store_media")
3387 (set_attr "length" "8,4")])
3389 ; N.B. This should agree with LOAD_EXTEND_OP and movqi.
3390 ; Because we use zero extension, we can't provide signed QImode compares
3391 ; using a simple compare or conditional banch insn.
3392 (define_insn "truncdiqi2"
3393 [(set (match_operand:QI 0 "general_movdst_operand" "=r,m")
3394 (truncate:QI (match_operand:DI 1 "register_operand" "r,r")))]
3399 [(set_attr "type" "arith_media,store")])
3401 ;; -------------------------------------------------------------------------
3402 ;; Move instructions
3403 ;; -------------------------------------------------------------------------
3405 ;; define push and pop so it is easy for sh.c
3406 ;; We can't use push and pop on SHcompact because the stack must always
3407 ;; be 8-byte aligned.
3409 (define_expand "push"
3410 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3411 (match_operand:SI 0 "register_operand" "r,l,x"))]
3412 "TARGET_SH1 && ! TARGET_SH5"
3415 (define_expand "pop"
3416 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
3417 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
3418 "TARGET_SH1 && ! TARGET_SH5"
3421 (define_expand "push_e"
3422 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
3423 (match_operand:SF 0 "" ""))
3424 (use (reg:PSI FPSCR_REG))
3425 (clobber (scratch:SI))])]
3426 "TARGET_SH1 && ! TARGET_SH5"
3429 (define_insn "push_fpul"
3430 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
3431 "TARGET_SH3E && ! TARGET_SH5"
3433 [(set_attr "type" "store")
3434 (set_attr "hit_stack" "yes")])
3436 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
3438 (define_expand "push_4"
3439 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
3440 (match_operand:DF 0 "" ""))
3441 (use (reg:PSI FPSCR_REG))
3442 (clobber (scratch:SI))])]
3443 "TARGET_SH1 && ! TARGET_SH5"
3446 (define_expand "pop_e"
3447 [(parallel [(set (match_operand:SF 0 "" "")
3448 (mem:SF (post_inc:SI (reg:SI SP_REG))))
3449 (use (reg:PSI FPSCR_REG))
3450 (clobber (scratch:SI))])]
3451 "TARGET_SH1 && ! TARGET_SH5"
3454 (define_insn "pop_fpul"
3455 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
3456 "TARGET_SH3E && ! TARGET_SH5"
3458 [(set_attr "type" "load")
3459 (set_attr "hit_stack" "yes")])
3461 (define_expand "pop_4"
3462 [(parallel [(set (match_operand:DF 0 "" "")
3463 (mem:DF (post_inc:SI (reg:SI SP_REG))))
3464 (use (reg:PSI FPSCR_REG))
3465 (clobber (scratch:SI))])]
3466 "TARGET_SH1 && ! TARGET_SH5"
3469 ;; These two patterns can happen as the result of optimization, when
3470 ;; comparisons get simplified to a move of zero or 1 into the T reg.
3471 ;; They don't disappear completely, because the T reg is a fixed hard reg.
3474 [(set (reg:SI T_REG) (const_int 0))]
3479 [(set (reg:SI T_REG) (const_int 1))]
3483 ;; t/r must come after r/r, lest reload will try to reload stuff like
3484 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
3485 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
3486 (define_insn "movsi_i"
3487 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
3488 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
3491 && (register_operand (operands[0], SImode)
3492 || register_operand (operands[1], SImode))"
3509 [(set_attr "type" "pcload_si,move,*,load_si,move,prget,move,store,store,pstore,move,prset,load,pload,pcload_si")
3510 (set_attr "insn_class" "*,*,mt_group,*,*,*,*,*,*,*,*,*,*,*,*")
3511 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
3513 ;; t/r must come after r/r, lest reload will try to reload stuff like
3514 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
3515 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
3516 ;; will require a reload.
3517 (define_insn "movsi_ie"
3518 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,y")
3519 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y"))]
3521 && (register_operand (operands[0], SImode)
3522 || register_operand (operands[1], SImode))"
3543 ! move optimized away"
3544 [(set_attr "type" "pcload_si,move,*,load_si,move,prget,move,store,store,pstore,move,prset,load,pload,load,store,pcload_si,gp_fpul,gp_fpul,nil")
3545 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
3547 (define_insn "movsi_i_lowpart"
3548 [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
3549 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,mr,x,l,t,r,i"))]
3551 && (register_operand (operands[0], SImode)
3552 || register_operand (operands[1], SImode))"
3562 [(set_attr "type" "pcload,move,load,move,prget,move,store,pcload")])
3564 (define_insn "*movsi_media"
3565 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,m,f,m,f,r,f,*b,r,b")
3566 (match_operand:SI 1 "general_movsrc_operand" "r,JS,ns,m,r,m,f,rU,f,f,r,*b,T"))]
3568 && (register_operand (operands[0], SImode)
3569 || register_operand (operands[1], SImode))"
3584 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,fload_media,fstore_media,fload_media,fpconv_media,fmove_media,ptabs_media,gettr_media,pt_media")
3585 (set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12")])
3587 (define_insn "*movsi_media_nofpu"
3588 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,m,*b,r,b")
3589 (match_operand:SI 1 "general_movsrc_operand" "r,JS,ns,m,r,r,*b,T"))]
3591 && (register_operand (operands[0], SImode)
3592 || register_operand (operands[1], SImode))"
3602 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,ptabs_media,gettr_media,pt_media")
3603 (set_attr "length" "4,4,8,4,4,4,4,12")])
3606 [(set (match_operand:SI 0 "arith_reg_operand" "")
3607 (match_operand:SI 1 "immediate_operand" ""))]
3608 "TARGET_SHMEDIA && reload_completed
3609 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
3610 [(set (subreg:DI (match_dup 0) 0) (match_dup 2))]
3613 operands[2] = shallow_copy_rtx (operands[1]);
3614 PUT_MODE (operands[2], DImode);
3618 [(set (match_operand:SI 0 "register_operand" "")
3619 (match_operand:SI 1 "immediate_operand" ""))]
3620 "TARGET_SHMEDIA && reload_completed
3621 && ((GET_CODE (operands[1]) == CONST_INT
3622 && ! CONST_OK_FOR_J (INTVAL (operands[1])))
3623 || GET_CODE (operands[1]) == CONST_DOUBLE)"
3624 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
3626 (define_expand "movsi"
3627 [(set (match_operand:SI 0 "general_movdst_operand" "")
3628 (match_operand:SI 1 "general_movsrc_operand" ""))]
3630 "{ if (prepare_move_operands (operands, SImode)) DONE; }")
3632 (define_expand "ic_invalidate_line"
3633 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
3634 (match_dup 1)] UNSPEC_ICACHE)
3635 (clobber (scratch:SI))])]
3636 "TARGET_HARD_SH4 || TARGET_SH5"
3641 emit_insn (gen_ic_invalidate_line_media (operands[0]));
3644 else if (TARGET_SHCOMPACT)
3646 operands[1] = gen_rtx_SYMBOL_REF (Pmode, \"__ic_invalidate\");
3647 operands[1] = force_reg (Pmode, operands[1]);
3648 emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1]));
3651 operands[0] = force_reg (Pmode, operands[0]);
3652 operands[1] = force_reg (Pmode, GEN_INT (trunc_int_for_mode (0xf0000008,
3656 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
3657 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
3658 ;; the requirement *1*00 for associative address writes. The alignment of
3659 ;; %0 implies that its least significant bit is cleared,
3660 ;; thus we clear the V bit of a matching entry if there is one.
3661 (define_insn "ic_invalidate_line_i"
3662 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
3663 (match_operand:SI 1 "register_operand" "r")]
3665 (clobber (match_scratch:SI 2 "=&r"))]
3667 "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
3668 [(set_attr "length" "8")
3669 (set_attr "insn_class" "cwb")])
3671 ;; ??? could make arg 0 an offsettable memory operand to allow to save
3672 ;; an add in the code that calculates the address.
3673 (define_insn "ic_invalidate_line_media"
3674 [(unspec_volatile [(match_operand 0 "register_operand" "r")]
3677 "ocbwb %0,0\;synco\;icbi %0, 0\;synci"
3678 [(set_attr "length" "16")
3679 (set_attr "type" "invalidate_line_media")])
3681 (define_insn "ic_invalidate_line_compact"
3682 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
3683 (match_operand:SI 1 "register_operand" "r")]
3685 (clobber (reg:SI PR_REG))]
3688 [(set_attr "type" "sfunc")
3689 (set_attr "needs_delay_slot" "yes")])
3691 (define_expand "initialize_trampoline"
3692 [(match_operand:SI 0 "" "")
3693 (match_operand:SI 1 "" "")
3694 (match_operand:SI 2 "" "")]
3700 sfun = force_reg (Pmode, gen_rtx_SYMBOL_REF (Pmode, \"__init_trampoline\"));
3701 tramp = gen_rtx_REG (SImode, R0_REG);
3702 emit_move_insn (tramp, operands[0]);
3703 emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]);
3704 emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]);
3706 emit_insn (gen_initialize_trampoline_compact (tramp, sfun));
3710 (define_insn "initialize_trampoline_compact"
3711 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
3712 (match_operand:SI 1 "register_operand" "r")
3713 (reg:SI R2_REG) (reg:SI R3_REG)]
3716 (clobber (reg:SI PR_REG))]
3719 [(set_attr "type" "sfunc")
3720 (set_attr "needs_delay_slot" "yes")])
3722 (define_insn "movqi_i"
3723 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
3724 (match_operand:QI 1 "general_movsrc_operand" "ri,m,r,t,l,r"))]
3726 && (arith_reg_operand (operands[0], QImode)
3727 || arith_reg_operand (operands[1], QImode))"
3735 [(set_attr "type" "move,load,store,move,move,move")])
3737 (define_insn "*movqi_media"
3738 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
3739 (match_operand:QI 1 "general_movsrc_operand" "r,JS,m,r"))]
3741 && (arith_reg_operand (operands[0], QImode)
3742 || arith_reg_operand (operands[1], QImode))"
3748 [(set_attr "type" "arith_media,arith_media,load_media,store_media")])
3750 (define_expand "movqi"
3751 [(set (match_operand:QI 0 "general_operand" "")
3752 (match_operand:QI 1 "general_operand" ""))]
3754 "{ if (prepare_move_operands (operands, QImode)) DONE; }")
3756 (define_expand "reload_inqi"
3757 [(set (match_operand:SI 2 "" "=&r")
3758 (match_operand:QI 1 "inqhi_operand" ""))
3759 (set (match_operand:QI 0 "arith_reg_operand" "=r")
3760 (truncate:HI (match_dup 3)))]
3764 rtx inner = XEXP (operands[1], 0);
3765 int regno = REGNO (inner);
3767 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
3768 operands[1] = gen_rtx_REG (SImode, regno);
3769 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
3772 (define_insn "movhi_i"
3773 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
3774 (match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
3776 && (arith_reg_operand (operands[0], HImode)
3777 || arith_reg_operand (operands[1], HImode))"
3787 [(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
3789 (define_insn "*movhi_media"
3790 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
3791 (match_operand:HI 1 "general_movsrc_operand" "r,JS,n,m,r"))]
3793 && (arith_reg_operand (operands[0], HImode)
3794 || arith_reg_operand (operands[1], HImode))"
3801 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")])
3804 [(set (match_operand:HI 0 "register_operand" "")
3805 (match_operand:HI 1 "immediate_operand" ""))]
3806 "TARGET_SHMEDIA && reload_completed
3807 && ! CONST_OK_FOR_J (INTVAL (operands[1]))"
3808 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
3810 (define_expand "movhi"
3811 [(set (match_operand:HI 0 "general_movdst_operand" "")
3812 (match_operand:HI 1 "general_movsrc_operand" ""))]
3814 "{ if (prepare_move_operands (operands, HImode)) DONE; }")
3816 (define_expand "reload_inhi"
3817 [(set (match_operand:SI 2 "" "=&r")
3818 (match_operand:HI 1 "inqhi_operand" ""))
3819 (set (match_operand:HI 0 "arith_reg_operand" "=r")
3820 (truncate:HI (match_dup 3)))]
3824 rtx inner = XEXP (operands[1], 0);
3825 int regno = REGNO (inner);
3827 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
3828 operands[1] = gen_rtx_REG (SImode, regno);
3829 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
3832 ;; ??? This should be a define expand.
3834 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
3835 ;; compiled with -m2 -ml -O3 -funroll-loops
3837 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
3838 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))]
3840 && (arith_reg_operand (operands[0], DImode)
3841 || arith_reg_operand (operands[1], DImode))"
3842 "* return output_movedouble (insn, operands, DImode);"
3843 [(set_attr "length" "4")
3844 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
3846 ;; If the output is a register and the input is memory or a register, we have
3847 ;; to be careful and see which word needs to be loaded first.
3850 [(set (match_operand:DI 0 "general_movdst_operand" "")
3851 (match_operand:DI 1 "general_movsrc_operand" ""))]
3852 "TARGET_SH1 && reload_completed"
3853 [(set (match_dup 2) (match_dup 3))
3854 (set (match_dup 4) (match_dup 5))]
3859 if ((GET_CODE (operands[0]) == MEM
3860 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
3861 || (GET_CODE (operands[1]) == MEM
3862 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
3865 if (GET_CODE (operands[0]) == REG)
3866 regno = REGNO (operands[0]);
3867 else if (GET_CODE (operands[0]) == SUBREG)
3868 regno = subreg_regno (operands[0]);
3869 else if (GET_CODE (operands[0]) == MEM)
3875 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
3877 operands[2] = operand_subword (operands[0], 0, 0, DImode);
3878 operands[3] = operand_subword (operands[1], 0, 0, DImode);
3879 operands[4] = operand_subword (operands[0], 1, 0, DImode);
3880 operands[5] = operand_subword (operands[1], 1, 0, DImode);
3884 operands[2] = operand_subword (operands[0], 1, 0, DImode);
3885 operands[3] = operand_subword (operands[1], 1, 0, DImode);
3886 operands[4] = operand_subword (operands[0], 0, 0, DImode);
3887 operands[5] = operand_subword (operands[1], 0, 0, DImode);
3890 if (operands[2] == 0 || operands[3] == 0
3891 || operands[4] == 0 || operands[5] == 0)
3895 (define_insn "*movdi_media"
3896 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,f,m,f,r,f,*b,r,b")
3897 (match_operand:DI 1 "general_movsrc_operand" "r,JS,iF,m,rl,m,f,rU,f,f,r,*b,T"))]
3899 && (register_operand (operands[0], DImode)
3900 || register_operand (operands[1], DImode))"
3915 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,fload_media,fstore_media,fload_media,dfpconv_media,fmove_media,ptabs_media,gettr_media,pt_media")
3916 (set_attr "length" "4,4,16,4,4,4,4,4,4,4,4,4,*")])
3918 (define_insn "*movdi_media_nofpu"
3919 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,b")
3920 (match_operand:DI 1 "general_movsrc_operand" "r,JS,iF,m,rl,r,*b,T"))]
3922 && (register_operand (operands[0], DImode)
3923 || register_operand (operands[1], DImode))"
3933 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,ptabs_media,gettr_media,pt_media")
3934 (set_attr "length" "4,4,16,4,4,4,4,*")])
3937 [(set (match_operand:DI 0 "arith_reg_operand" "")
3938 (match_operand:DI 1 "immediate_operand" ""))]
3939 "TARGET_SHMEDIA && reload_completed
3940 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
3941 [(set (match_dup 0) (match_dup 1))]
3946 if (TARGET_SHMEDIA64)
3947 insn = emit_insn (gen_movdi_const (operands[0], operands[1]));
3949 insn = emit_insn (gen_movdi_const_32bit (operands[0], operands[1]));
3951 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
3957 (define_expand "movdi_const"
3958 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
3959 (const:DI (sign_extend:DI
3962 (match_operand:DI 1 "immediate_operand" "s")
3965 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
3973 (const_int 32)))))))))
3975 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
3983 (const_int 16)))))))))
3985 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
3991 (match_dup 1))))))))]
3992 "TARGET_SHMEDIA64 && reload_completed
3993 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
3996 if (GET_CODE (operands[1]) == LABEL_REF
3997 && GET_CODE (XEXP (operands[1], 0)) == CODE_LABEL)
3998 LABEL_NUSES (XEXP (operands[1], 0)) += 4;
3999 else if (GOTOFF_P (operands[1])
4000 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == LABEL_REF
4001 && (GET_CODE (XEXP (XVECEXP (XEXP (operands[1], 0), 0, 0), 0))
4003 LABEL_NUSES (XEXP (XVECEXP (XEXP (operands[1], 0), 0, 0), 0)) += 4;
4006 (define_expand "movdi_const_32bit"
4007 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
4008 (const:DI (sign_extend:DI
4011 (match_operand:DI 1 "immediate_operand" "s")
4014 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
4020 (match_dup 1))))))))]
4021 "TARGET_SHMEDIA32 && reload_completed
4022 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
4025 if (GET_CODE (operands[1]) == LABEL_REF
4026 && GET_CODE (XEXP (operands[1], 0)) == CODE_LABEL)
4027 LABEL_NUSES (XEXP (operands[1], 0)) += 2;
4028 else if (GOTOFF_P (operands[1])
4029 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == LABEL_REF
4030 && (GET_CODE (XEXP (XVECEXP (XEXP (operands[1], 0), 0, 0), 0))
4032 LABEL_NUSES (XEXP (XVECEXP (XEXP (operands[1], 0), 0, 0), 0)) += 2;
4035 (define_expand "movdi_const_16bit"
4036 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
4037 (const:DI (sign_extend:DI
4039 (match_operand:DI 1 "immediate_operand" "s")))))]
4040 "TARGET_SHMEDIA && flag_pic && reload_completed
4041 && GET_CODE (operands[1]) == SYMBOL_REF"
4045 [(set (match_operand:DI 0 "arith_reg_operand" "")
4046 (match_operand:DI 1 "immediate_operand" ""))]
4047 "TARGET_SHMEDIA && reload_completed
4048 && GET_CODE (operands[1]) == CONST_INT
4049 && ! CONST_OK_FOR_J (INTVAL (operands[1]))"
4050 [(set (match_dup 0) (match_dup 2))
4054 unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
4055 unsigned HOST_WIDE_INT low = val;
4056 unsigned HOST_WIDE_INT high = val;
4057 unsigned HOST_WIDE_INT sign;
4058 unsigned HOST_WIDE_INT val2 = val ^ (val-1);
4060 /* Sign-extend the 16 least-significant bits. */
4065 /* Arithmetic shift right the word by 16 bits. */
4068 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
4073 /* If we can't generate the constant with a two-insn movi / shori
4074 sequence, try some other strategies. */
4075 if (! CONST_OK_FOR_J (high))
4077 /* Try constant load / left shift. We know VAL != 0. */
4078 val2 = val ^ (val-1);
4081 int trailing_zeroes = exact_log2 ((val2 >> 16) + 1) + 15;
4083 if (CONST_OK_FOR_J (val >> trailing_zeroes)
4084 || (! CONST_OK_FOR_J (high >> 16)
4085 && CONST_OK_FOR_J (val >> (trailing_zeroes + 16))))
4087 val2 = (HOST_WIDE_INT) val >> trailing_zeroes;
4088 operands[1] = gen_ashldi3_media (operands[0], operands[0],
4089 GEN_INT (trailing_zeroes));
4093 /* Try constant load / right shift. */
4094 val2 = (val >> 15) + 1;
4095 if (val2 == (val2 & -val2))
4097 int shift = 49 - exact_log2 (val2);
4099 val2 = trunc_int_for_mode (val << shift, DImode);
4100 if (CONST_OK_FOR_J (val2))
4102 operands[1] = gen_lshrdi3_media (operands[0], operands[0],
4108 val2 = val & 0xffff;
4109 if ((val >> 16 & 0xffff) == val2
4110 && (val >> 32 & 0xffff) == val2
4111 && (val >> 48 & 0xffff) == val2)
4113 val2 = (HOST_WIDE_INT) val >> 48;
4114 operands[1] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
4115 operands[1] = gen_mperm_w0 (operands[1], operands[1]);
4118 /* Try movi / mshflo.l */
4119 val2 = (HOST_WIDE_INT) val >> 32;
4120 if (val2 == trunc_int_for_mode (val, SImode))
4122 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
4126 /* Try movi / mshflo.l w/ r63. */
4127 val2 = val + ((HOST_WIDE_INT) -1 << 32);
4128 if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_J (val2))
4130 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
4136 operands[1] = gen_shori_media (operands[0], operands[0], GEN_INT (low));
4139 operands[2] = GEN_INT (val2);
4143 [(set (match_operand:DI 0 "arith_reg_operand" "")
4144 (match_operand:DI 1 "immediate_operand" ""))]
4145 "TARGET_SHMEDIA && reload_completed
4146 && GET_CODE (operands[1]) == CONST_DOUBLE"
4147 [(set (match_dup 0) (match_dup 2))
4149 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
4150 (zero_extend:DI (truncate:HI (match_dup 1)))))]
4153 unsigned HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
4154 unsigned HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
4155 unsigned HOST_WIDE_INT val = low;
4156 unsigned HOST_WIDE_INT sign;
4158 /* Sign-extend the 16 least-significant bits. */
4162 operands[1] = GEN_INT (val);
4164 /* Arithmetic shift right the double-word by 16 bits. */
4166 low |= (high & 0xffff) << (HOST_BITS_PER_WIDE_INT - 16);
4169 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
4173 /* This will only be true if high is a sign-extension of low, i.e.,
4174 it must be either 0 or (unsigned)-1, and be zero iff the
4175 most-significant bit of low is set. */
4176 if (high + (low >> (HOST_BITS_PER_WIDE_INT - 1)) == 0)
4177 operands[2] = GEN_INT (low);
4179 operands[2] = immed_double_const (low, high, DImode);
4182 (define_insn "shori_media"
4183 [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
4184 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0,0")
4188 (match_operand:DI 2 "immediate_operand" "JS,nF")))))]
4193 [(set_attr "type" "arith_media,*")])
4195 (define_expand "movdi"
4196 [(set (match_operand:DI 0 "general_movdst_operand" "")
4197 (match_operand:DI 1 "general_movsrc_operand" ""))]
4199 "{ if (prepare_move_operands (operands, DImode)) DONE; }")
4201 (define_insn "movdf_media"
4202 [(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
4203 (match_operand:DF 1 "general_movsrc_operand" "f,rU,f,r,F,m,f,m,r"))]
4205 && (register_operand (operands[0], DFmode)
4206 || register_operand (operands[1], DFmode))"
4217 [(set_attr "type" "fmove_media,fload_media,dfpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")])
4219 (define_insn "movdf_media_nofpu"
4220 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
4221 (match_operand:DF 1 "general_movsrc_operand" "r,F,m,r"))]
4223 && (register_operand (operands[0], DFmode)
4224 || register_operand (operands[1], DFmode))"
4230 [(set_attr "type" "arith_media,*,load_media,store_media")])
4233 [(set (match_operand:DF 0 "arith_reg_operand" "")
4234 (match_operand:DF 1 "immediate_operand" ""))]
4235 "TARGET_SHMEDIA && reload_completed"
4236 [(set (match_dup 3) (match_dup 2))]
4239 int endian = WORDS_BIG_ENDIAN ? 1 : 0;
4241 REAL_VALUE_TYPE value;
4243 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
4244 REAL_VALUE_TO_TARGET_DOUBLE (value, values);
4246 if (HOST_BITS_PER_WIDE_INT >= 64)
4247 operands[2] = immed_double_const ((unsigned long) values[endian]
4248 | ((HOST_WIDE_INT) values[1 - endian]
4250 else if (HOST_BITS_PER_WIDE_INT == 32)
4251 operands[2] = immed_double_const (values[endian], values[1 - endian],
4256 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
4259 ;; ??? This should be a define expand.
4261 (define_insn "movdf_k"
4262 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
4263 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
4265 && (! TARGET_SH4 || reload_completed
4266 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
4267 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
4268 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
4269 && (arith_reg_operand (operands[0], DFmode)
4270 || arith_reg_operand (operands[1], DFmode))"
4271 "* return output_movedouble (insn, operands, DFmode);"
4272 [(set_attr "length" "4")
4273 (set_attr "type" "move,pcload,load,store")])
4275 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
4276 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
4277 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
4278 ;; the d/m/c/X alternative, which is split later into single-precision
4279 ;; instructions. And when not optimizing, no splits are done before fixing
4280 ;; up pcloads, so we need usable length information for that.
4281 (define_insn "movdf_i4"
4282 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
4283 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
4284 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
4285 (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
4287 && (arith_reg_operand (operands[0], DFmode)
4288 || arith_reg_operand (operands[1], DFmode))"
4300 [(set_attr_alternative "length"
4301 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
4303 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
4304 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
4305 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
4307 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
4308 ;; We can't use 4-byte push/pop on SHcompact, so we have to
4309 ;; increment or decrement r15 explicitly.
4311 (ne (symbol_ref "TARGET_SHCOMPACT") (const_int 0))
4312 (const_int 10) (const_int 8))
4314 (ne (symbol_ref "TARGET_SHCOMPACT") (const_int 0))
4315 (const_int 10) (const_int 8))])
4316 (set_attr "type" "fmove,move,pcload,load,store,pcload,load,store,load,load")
4317 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
4318 (const_string "double")
4319 (const_string "none")))])
4321 ;; Moving DFmode between fp/general registers through memory
4322 ;; (the top of the stack) is faster than moving through fpul even for
4323 ;; little endian. Because the type of an instruction is important for its
4324 ;; scheduling, it is beneficial to split these operations, rather than
4325 ;; emitting them in one single chunk, even if this will expose a stack
4326 ;; use that will prevent scheduling of other stack accesses beyond this
4329 [(set (match_operand:DF 0 "register_operand" "")
4330 (match_operand:DF 1 "register_operand" ""))
4331 (use (match_operand:PSI 2 "fpscr_operand" ""))
4332 (clobber (match_scratch:SI 3 "=X"))]
4333 "TARGET_SH4 && reload_completed
4334 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
4340 if (TARGET_SH5 && true_regnum (operands[1]) < 16)
4342 emit_move_insn (stack_pointer_rtx,
4343 plus_constant (stack_pointer_rtx, -8));
4344 tos = gen_rtx_MEM (DFmode, stack_pointer_rtx);
4347 tos = gen_rtx (MEM, DFmode, gen_rtx (PRE_DEC, Pmode, stack_pointer_rtx));
4348 insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
4349 if (! (TARGET_SH5 && true_regnum (operands[1]) < 16))
4350 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
4351 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
4352 tos = gen_rtx_MEM (DFmode, stack_pointer_rtx);
4354 tos = gen_rtx (MEM, DFmode, gen_rtx (POST_INC, Pmode, stack_pointer_rtx));
4355 insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
4356 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
4357 emit_move_insn (stack_pointer_rtx, plus_constant (stack_pointer_rtx, 8));
4359 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
4363 ;; local-alloc sometimes allocates scratch registers even when not required,
4364 ;; so we must be prepared to handle these.
4366 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
4368 [(set (match_operand:DF 0 "general_movdst_operand" "")
4369 (match_operand:DF 1 "general_movsrc_operand" ""))
4370 (use (match_operand:PSI 2 "fpscr_operand" ""))
4371 (clobber (match_scratch:SI 3 ""))]
4374 && true_regnum (operands[0]) < 16
4375 && true_regnum (operands[1]) < 16"
4376 [(set (match_dup 0) (match_dup 1))]
4379 /* If this was a reg <-> mem operation with base + index reg addressing,
4380 we have to handle this in a special way. */
4381 rtx mem = operands[0];
4383 if (! memory_operand (mem, DFmode))
4388 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
4389 mem = SUBREG_REG (mem);
4390 if (GET_CODE (mem) == MEM)
4392 rtx addr = XEXP (mem, 0);
4393 if (GET_CODE (addr) == PLUS
4394 && GET_CODE (XEXP (addr, 0)) == REG
4395 && GET_CODE (XEXP (addr, 1)) == REG)
4398 rtx reg0 = gen_rtx (REG, Pmode, 0);
4399 rtx regop = operands[store_p], word0 ,word1;
4401 if (GET_CODE (regop) == SUBREG)
4402 alter_subreg (®op);
4403 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
4407 mem = copy_rtx (mem);
4408 PUT_MODE (mem, SImode);
4409 word0 = gen_rtx (SUBREG, SImode, regop, 0);
4410 alter_subreg (&word0);
4411 word1 = gen_rtx (SUBREG, SImode, regop, 4);
4412 alter_subreg (&word1);
4413 if (store_p || ! refers_to_regno_p (REGNO (word0),
4414 REGNO (word0) + 1, addr, 0))
4417 ? gen_movsi_ie (mem, word0)
4418 : gen_movsi_ie (word0, mem));
4419 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
4420 mem = copy_rtx (mem);
4422 ? gen_movsi_ie (mem, word1)
4423 : gen_movsi_ie (word1, mem));
4424 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
4428 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
4429 emit_insn (gen_movsi_ie (word1, mem));
4430 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
4431 mem = copy_rtx (mem);
4432 emit_insn (gen_movsi_ie (word0, mem));
4439 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
4441 [(set (match_operand:DF 0 "register_operand" "")
4442 (match_operand:DF 1 "memory_operand" ""))
4443 (use (match_operand:PSI 2 "fpscr_operand" ""))
4444 (clobber (reg:SI R0_REG))]
4445 "TARGET_SH4 && reload_completed"
4446 [(parallel [(set (match_dup 0) (match_dup 1))
4448 (clobber (scratch:SI))])]
4451 (define_expand "reload_indf"
4452 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
4453 (match_operand:DF 1 "immediate_operand" "FQ"))
4454 (use (reg:PSI FPSCR_REG))
4455 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
4459 (define_expand "reload_outdf"
4460 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
4461 (match_operand:DF 1 "register_operand" "af,r"))
4462 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
4466 ;; Simplify no-op moves.
4468 [(set (match_operand:SF 0 "register_operand" "")
4469 (match_operand:SF 1 "register_operand" ""))
4470 (use (match_operand:PSI 2 "fpscr_operand" ""))
4471 (clobber (match_scratch:SI 3 "X"))]
4472 "TARGET_SH3E && reload_completed
4473 && true_regnum (operands[0]) == true_regnum (operands[1])"
4474 [(set (match_dup 0) (match_dup 0))]
4477 ;; fmovd substitute post-reload splits
4479 [(set (match_operand:DF 0 "register_operand" "")
4480 (match_operand:DF 1 "register_operand" ""))
4481 (use (match_operand:PSI 2 "fpscr_operand" ""))
4482 (clobber (match_scratch:SI 3 "X"))]
4483 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
4484 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
4485 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
4489 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
4490 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst),
4491 gen_rtx (REG, SFmode, src), operands[2]));
4492 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst + 1),
4493 gen_rtx (REG, SFmode, src + 1), operands[2]));
4498 [(set (match_operand:DF 0 "register_operand" "")
4499 (mem:DF (match_operand:SI 1 "register_operand" "")))
4500 (use (match_operand:PSI 2 "fpscr_operand" ""))
4501 (clobber (match_scratch:SI 3 ""))]
4502 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
4503 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
4504 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
4508 int regno = true_regnum (operands[0]);
4510 rtx mem2 = gen_rtx (MEM, SFmode, gen_rtx (POST_INC, Pmode, operands[1]));
4512 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
4513 regno + !! TARGET_LITTLE_ENDIAN),
4514 mem2, operands[2]));
4515 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[1], NULL_RTX);
4516 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
4517 regno + ! TARGET_LITTLE_ENDIAN),
4518 gen_rtx (MEM, SFmode, operands[1]),
4524 [(set (match_operand:DF 0 "register_operand" "")
4525 (match_operand:DF 1 "memory_operand" ""))
4526 (use (match_operand:PSI 2 "fpscr_operand" ""))
4527 (clobber (match_scratch:SI 3 ""))]
4528 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
4529 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
4533 int regno = true_regnum (operands[0]);
4534 rtx addr, insn, adjust = NULL_RTX;
4535 rtx mem2 = copy_rtx (operands[1]);
4536 rtx reg0 = gen_rtx_REG (SFmode, regno + !! TARGET_LITTLE_ENDIAN);
4537 rtx reg1 = gen_rtx_REG (SFmode, regno + ! TARGET_LITTLE_ENDIAN);
4539 PUT_MODE (mem2, SFmode);
4540 operands[1] = copy_rtx (mem2);
4541 addr = XEXP (mem2, 0);
4542 if (GET_CODE (addr) != POST_INC)
4544 /* If we have to modify the stack pointer, the value that we have
4545 read with post-increment might be modified by an interrupt,
4546 so write it back. */
4547 if (REGNO (addr) == STACK_POINTER_REGNUM)
4548 adjust = gen_push_e (reg0);
4550 adjust = gen_addsi3 (addr, addr, GEN_INT (-4));
4551 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
4553 addr = XEXP (addr, 0);
4554 insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
4555 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
4556 insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
4560 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
4565 [(set (match_operand:DF 0 "memory_operand" "")
4566 (match_operand:DF 1 "register_operand" ""))
4567 (use (match_operand:PSI 2 "fpscr_operand" ""))
4568 (clobber (match_scratch:SI 3 ""))]
4569 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
4570 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
4574 int regno = true_regnum (operands[1]);
4575 rtx insn, addr, adjust = NULL_RTX;
4577 operands[0] = copy_rtx (operands[0]);
4578 PUT_MODE (operands[0], SFmode);
4579 insn = emit_insn (gen_movsf_ie (operands[0],
4580 gen_rtx (REG, SFmode,
4581 regno + ! TARGET_LITTLE_ENDIAN),
4583 operands[0] = copy_rtx (operands[0]);
4584 addr = XEXP (operands[0], 0);
4585 if (GET_CODE (addr) != PRE_DEC)
4587 adjust = gen_addsi3 (addr, addr, GEN_INT (4));
4588 emit_insn_before (adjust, insn);
4589 XEXP (operands[0], 0) = addr = gen_rtx (PRE_DEC, SImode, addr);
4591 addr = XEXP (addr, 0);
4593 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
4594 insn = emit_insn (gen_movsf_ie (operands[0],
4595 gen_rtx (REG, SFmode,
4596 regno + !! TARGET_LITTLE_ENDIAN),
4598 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
4602 ;; If the output is a register and the input is memory or a register, we have
4603 ;; to be careful and see which word needs to be loaded first.
4606 [(set (match_operand:DF 0 "general_movdst_operand" "")
4607 (match_operand:DF 1 "general_movsrc_operand" ""))]
4608 "TARGET_SH1 && reload_completed"
4609 [(set (match_dup 2) (match_dup 3))
4610 (set (match_dup 4) (match_dup 5))]
4615 if ((GET_CODE (operands[0]) == MEM
4616 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4617 || (GET_CODE (operands[1]) == MEM
4618 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
4621 if (GET_CODE (operands[0]) == REG)
4622 regno = REGNO (operands[0]);
4623 else if (GET_CODE (operands[0]) == SUBREG)
4624 regno = subreg_regno (operands[0]);
4625 else if (GET_CODE (operands[0]) == MEM)
4631 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
4633 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
4634 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
4635 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
4636 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
4640 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
4641 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
4642 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
4643 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
4646 if (operands[2] == 0 || operands[3] == 0
4647 || operands[4] == 0 || operands[5] == 0)
4651 ;; If a base address generated by LEGITIMIZE_ADDRESS for SImode is
4652 ;; used only once, let combine add in the index again.
4655 [(set (match_operand:SI 0 "register_operand" "")
4656 (match_operand:SI 1 "" ""))
4657 (clobber (match_operand 2 "register_operand" ""))]
4658 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
4659 [(use (reg:SI R0_REG))]
4662 rtx addr, reg, const_int;
4664 if (GET_CODE (operands[1]) != MEM)
4666 addr = XEXP (operands[1], 0);
4667 if (GET_CODE (addr) != PLUS)
4669 reg = XEXP (addr, 0);
4670 const_int = XEXP (addr, 1);
4671 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
4672 && GET_CODE (const_int) == CONST_INT))
4674 emit_move_insn (operands[2], const_int);
4675 emit_move_insn (operands[0],
4676 change_address (operands[1], VOIDmode,
4677 gen_rtx_PLUS (SImode, reg, operands[2])));
4682 [(set (match_operand:SI 1 "" "")
4683 (match_operand:SI 0 "register_operand" ""))
4684 (clobber (match_operand 2 "register_operand" ""))]
4685 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
4686 [(use (reg:SI R0_REG))]
4689 rtx addr, reg, const_int;
4691 if (GET_CODE (operands[1]) != MEM)
4693 addr = XEXP (operands[1], 0);
4694 if (GET_CODE (addr) != PLUS)
4696 reg = XEXP (addr, 0);
4697 const_int = XEXP (addr, 1);
4698 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
4699 && GET_CODE (const_int) == CONST_INT))
4701 emit_move_insn (operands[2], const_int);
4702 emit_move_insn (change_address (operands[1], VOIDmode,
4703 gen_rtx_PLUS (SImode, reg, operands[2])),
4708 (define_expand "movdf"
4709 [(set (match_operand:DF 0 "general_movdst_operand" "")
4710 (match_operand:DF 1 "general_movsrc_operand" ""))]
4714 if (prepare_move_operands (operands, DFmode)) DONE;
4717 if (TARGET_SHMEDIA_FPU)
4718 emit_insn (gen_movdf_media (operands[0], operands[1]));
4720 emit_insn (gen_movdf_media_nofpu (operands[0], operands[1]));
4725 emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4730 ;;This is incompatible with the way gcc uses subregs.
4731 ;;(define_insn "movv2sf_i"
4732 ;; [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,m")
4733 ;; (match_operand:V2SF 1 "nonimmediate_operand" "f,m,f"))]
4734 ;; "TARGET_SHMEDIA_FPU
4735 ;; && (fp_arith_reg_operand (operands[0], V2SFmode)
4736 ;; || fp_arith_reg_operand (operands[1], V2SFmode))"
4740 ;; fst%M0.p %m0, %1"
4741 ;; [(set_attr "type" "*,fload_media,fstore_media")])
4743 (define_insn_and_split "movv2sf_i"
4744 [(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
4745 (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfU?"))]
4746 "TARGET_SHMEDIA_FPU"
4748 "TARGET_SHMEDIA_FPU && reload_completed"
4749 [(set (match_dup 0) (match_dup 1))]
4752 operands[0] = simplify_gen_subreg (DFmode, operands[0], V2SFmode, 0);
4753 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2SFmode, 0);
4756 (define_expand "movv2sf"
4757 [(set (match_operand:V2SF 0 "general_movdst_operand" "")
4758 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
4759 "TARGET_SHMEDIA_FPU"
4762 if (prepare_move_operands (operands, V2SFmode))
4766 (define_expand "addv2sf3"
4767 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
4768 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
4769 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
4770 "TARGET_SHMEDIA_FPU"
4773 sh_expand_binop_v2sf (PLUS, operands[0], operands[1], operands[2]);
4777 (define_expand "subv2sf3"
4778 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
4779 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
4780 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
4781 "TARGET_SHMEDIA_FPU"
4784 sh_expand_binop_v2sf (MINUS, operands[0], operands[1], operands[2]);
4788 (define_expand "mulv2sf3"
4789 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
4790 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
4791 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
4792 "TARGET_SHMEDIA_FPU"
4795 sh_expand_binop_v2sf (MULT, operands[0], operands[1], operands[2]);
4799 (define_expand "divv2sf3"
4800 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
4801 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
4802 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
4803 "TARGET_SHMEDIA_FPU"
4806 sh_expand_binop_v2sf (DIV, operands[0], operands[1], operands[2]);
4810 (define_insn_and_split "*movv4sf_i"
4811 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=f,f,m")
4812 (match_operand:V4SF 1 "general_operand" "fU,m,f"))]
4813 "TARGET_SHMEDIA_FPU"
4815 "&& reload_completed"
4821 for (i = 0; i < 4/2; i++)
4825 if (GET_CODE (operands[0]) == MEM)
4826 x = gen_rtx_MEM (V2SFmode,
4827 plus_constant (XEXP (operands[0], 0),
4828 i * GET_MODE_SIZE (V2SFmode)));
4830 x = simplify_gen_subreg (V2SFmode, operands[0], V4SFmode, i * 8);
4832 if (GET_CODE (operands[1]) == MEM)
4833 y = gen_rtx_MEM (V2SFmode,
4834 plus_constant (XEXP (operands[1], 0),
4835 i * GET_MODE_SIZE (V2SFmode)));
4837 y = simplify_gen_subreg (V2SFmode, operands[1], V4SFmode, i * 8);
4839 emit_insn (gen_movv2sf_i (x, y));
4844 [(set_attr "length" "8")])
4846 (define_expand "movv4sf"
4847 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
4848 (match_operand:V4SF 1 "general_operand" ""))]
4849 "TARGET_SHMEDIA_FPU"
4852 if (prepare_move_operands (operands, V4SFmode))
4856 (define_insn_and_split "*movv16sf_i"
4857 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
4858 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
4859 "TARGET_SHMEDIA_FPU"
4861 "&& reload_completed"
4867 for (i = 0; i < 16/2; i++)
4871 if (GET_CODE (operands[0]) == MEM)
4872 x = gen_rtx_MEM (V2SFmode,
4873 plus_constant (XEXP (operands[0], 0),
4874 i * GET_MODE_SIZE (V2SFmode)));
4877 x = gen_rtx_SUBREG (V2SFmode, operands[0], i * 2);
4881 if (GET_CODE (operands[1]) == MEM)
4882 y = gen_rtx_MEM (V2SFmode,
4883 plus_constant (XEXP (operands[1], 0),
4884 i * GET_MODE_SIZE (V2SFmode)));
4887 y = gen_rtx_SUBREG (V2SFmode, operands[1], i * 2);
4891 emit_insn (gen_movv2sf_i (x, y));
4896 [(set_attr "length" "32")])
4898 (define_expand "movv16sf"
4899 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
4900 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
4901 "TARGET_SHMEDIA_FPU"
4904 if (prepare_move_operands (operands, V16SFmode))
4908 (define_insn "movsf_media"
4909 [(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
4910 (match_operand:SF 1 "general_movsrc_operand" "f,rU,f,r,F,m,f,m,r"))]
4912 && (register_operand (operands[0], SFmode)
4913 || register_operand (operands[1], SFmode))"
4924 [(set_attr "type" "fmove_media,fload_media,fpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")])
4926 (define_insn "movsf_media_nofpu"
4927 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m")
4928 (match_operand:SF 1 "general_movsrc_operand" "r,F,m,r"))]
4930 && (register_operand (operands[0], SFmode)
4931 || register_operand (operands[1], SFmode))"
4937 [(set_attr "type" "arith_media,*,load_media,store_media")])
4940 [(set (match_operand:SF 0 "arith_reg_operand" "")
4941 (match_operand:SF 1 "immediate_operand" ""))]
4942 "TARGET_SHMEDIA && reload_completed
4943 && ! FP_REGISTER_P (true_regnum (operands[0]))"
4944 [(set (match_dup 3) (match_dup 2))]
4948 REAL_VALUE_TYPE value;
4950 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
4951 REAL_VALUE_TO_TARGET_SINGLE (value, values);
4952 operands[2] = GEN_INT (values);
4954 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
4957 (define_insn "movsf_i"
4958 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
4959 (match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
4962 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
4963 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
4964 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
4965 && (arith_reg_operand (operands[0], SFmode)
4966 || arith_reg_operand (operands[1], SFmode))"
4975 [(set_attr "type" "move,move,pcload,load,store,move,move")])
4977 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
4978 ;; update_flow_info would not know where to put REG_EQUAL notes
4979 ;; when the destination changes mode.
4980 (define_insn "movsf_ie"
4981 [(set (match_operand:SF 0 "general_movdst_operand"
4982 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,<,y,y")
4983 (match_operand:SF 1 "general_movsrc_operand"
4984 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
4985 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
4986 (clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
4989 && (arith_reg_operand (operands[0], SFmode)
4990 || arith_reg_operand (operands[1], SFmode)
4991 || arith_reg_operand (operands[3], SImode)
4992 || (fpul_operand (operands[0], SFmode)
4993 && memory_operand (operands[1], SFmode)
4994 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
4995 || (fpul_operand (operands[1], SFmode)
4996 && memory_operand (operands[0], SFmode)
4997 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))"
5017 ! move optimized away"
5018 [(set_attr "type" "fmove,move,fmove,fmove,pcload,load,store,pcload,load,store,fmove,fmove,load,*,gp_fpul,gp_fpul,store,load,nil")
5019 (set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,4,2,2,2,2,0")
5020 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
5021 (const_string "single")
5022 (const_string "none")))])
5025 [(set (match_operand:SF 0 "register_operand" "")
5026 (match_operand:SF 1 "register_operand" ""))
5027 (use (match_operand:PSI 2 "fpscr_operand" ""))
5028 (clobber (reg:SI FPUL_REG))]
5030 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
5032 (clobber (scratch:SI))])
5033 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
5035 (clobber (scratch:SI))])]
5038 (define_expand "movsf"
5039 [(set (match_operand:SF 0 "general_movdst_operand" "")
5040 (match_operand:SF 1 "general_movsrc_operand" ""))]
5044 if (prepare_move_operands (operands, SFmode))
5048 if (TARGET_SHMEDIA_FPU)
5049 emit_insn (gen_movsf_media (operands[0], operands[1]));
5051 emit_insn (gen_movsf_media_nofpu (operands[0], operands[1]));
5056 emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
5061 (define_insn "mov_nop"
5062 [(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
5065 [(set_attr "length" "0")
5066 (set_attr "type" "nil")])
5068 (define_expand "reload_insf"
5069 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
5070 (match_operand:SF 1 "immediate_operand" "FQ"))
5071 (use (reg:PSI FPSCR_REG))
5072 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
5076 (define_expand "reload_insi"
5077 [(parallel [(set (match_operand:SF 0 "register_operand" "=y")
5078 (match_operand:SF 1 "immediate_operand" "FQ"))
5079 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
5083 (define_insn "*movsi_y"
5084 [(set (match_operand:SI 0 "register_operand" "=y,y")
5085 (match_operand:SI 1 "immediate_operand" "Qi,I"))
5086 (clobber (match_scratch:SI 2 "=&z,r"))]
5088 && (reload_in_progress || reload_completed)"
5090 [(set_attr "length" "4")
5091 (set_attr "type" "pcload,move")])
5094 [(set (match_operand:SI 0 "register_operand" "")
5095 (match_operand:SI 1 "immediate_operand" ""))
5096 (clobber (match_operand:SI 2 "register_operand" ""))]
5098 [(set (match_dup 2) (match_dup 1))
5099 (set (match_dup 0) (match_dup 2))]
5103 [(set (match_operand:SI 0 "register_operand" "")
5104 (match_operand:SI 1 "memory_operand" ""))
5105 (clobber (reg:SI R0_REG))]
5107 [(set (match_dup 0) (match_dup 1))]
5110 ;; ------------------------------------------------------------------------
5111 ;; Define the real conditional branch instructions.
5112 ;; ------------------------------------------------------------------------
5114 (define_insn "branch_true"
5115 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
5116 (label_ref (match_operand 0 "" ""))
5119 "* return output_branch (1, insn, operands);"
5120 [(set_attr "type" "cbranch")])
5122 (define_insn "branch_false"
5123 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
5124 (label_ref (match_operand 0 "" ""))
5127 "* return output_branch (0, insn, operands);"
5128 [(set_attr "type" "cbranch")])
5130 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
5131 ;; which destination is too far away.
5132 ;; The const_int_operand is distinct for each branch target; it avoids
5133 ;; unwanted matches with redundant_insn.
5134 (define_insn "block_branch_redirect"
5135 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
5138 [(set_attr "length" "0")])
5140 ;; This one has the additional purpose to record a possible scratch register
5141 ;; for the following branch.
5142 (define_insn "indirect_jump_scratch"
5143 [(set (match_operand:SI 0 "register_operand" "=r")
5144 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))]
5147 [(set_attr "length" "0")])
5149 ;; This one is used to preemt an insn from beyond the bra / braf / jmp
5150 ;; being pulled into the delay slot of a condbranch that has been made to
5151 ;; jump around the unconditional jump because it was out of range.
5152 (define_insn "stuff_delay_slot"
5154 (unspec [(match_operand 0 "const_int_operand" "") (pc)] UNSPEC_BBR))
5155 (set (reg:SI T_REG) (match_operand 1 "const_int_operand" ""))]
5158 [(set_attr "length" "0")
5159 (set_attr "cond_delay_slot" "yes")])
5161 ;; Conditional branch insns
5163 (define_expand "beq_media"
5165 (if_then_else (eq (match_operand:DI 1 "arith_reg_operand" "r,r")
5166 (match_operand:DI 2 "arith_operand" "r,O"))
5167 (label_ref:DI (match_operand 0 "" ""))
5172 (define_insn "*beq_media_i"
5174 (if_then_else (match_operator 3 "equality_comparison_operator"
5175 [(match_operand:DI 1 "arith_reg_operand" "r,r")
5176 (match_operand:DI 2 "arith_operand" "r,O")])
5177 (match_operand:DI 0 "target_operand" "b,b")
5183 [(set_attr "type" "cbranch_media")])
5185 (define_expand "bne_media"
5187 (if_then_else (ne (match_operand:DI 1 "arith_reg_operand" "r,r")
5188 (match_operand:DI 2 "arith_operand" "r,O"))
5189 (label_ref:DI (match_operand 0 "" ""))
5194 (define_expand "bgt_media"
5196 (if_then_else (gt (match_operand:DI 1 "arith_reg_or_0_operand" "r")
5197 (match_operand:DI 2 "arith_reg_or_0_operand" "r"))
5198 (label_ref:DI (match_operand 0 "" ""))
5203 (define_expand "bge_media"
5205 (if_then_else (ge (match_operand:DI 1 "arith_reg_or_0_operand" "r")
5206 (match_operand:DI 2 "arith_reg_or_0_operand" "r"))
5207 (label_ref:DI (match_operand 0 "" ""))
5212 (define_expand "bgtu_media"
5214 (if_then_else (gtu (match_operand:DI 1 "arith_reg_or_0_operand" "r")
5215 (match_operand:DI 2 "arith_reg_or_0_operand" "r"))
5216 (label_ref:DI (match_operand 0 "" ""))
5221 (define_expand "bgeu_media"
5223 (if_then_else (geu (match_operand:DI 1 "arith_reg_or_0_operand" "r")
5224 (match_operand:DI 2 "arith_reg_or_0_operand" "r"))
5225 (label_ref:DI (match_operand 0 "" ""))
5230 (define_insn "*bgt_media_i"
5232 (if_then_else (match_operator 3 "greater_comparison_operator"
5233 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
5234 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
5235 (match_operand:DI 0 "target_operand" "b")
5238 "b%o3%' %N1, %N2, %0"
5239 [(set_attr "type" "cbranch_media")])
5241 ;; These are only needed to make invert_jump() happy.
5242 (define_insn "*blt_media_i"
5244 (if_then_else (match_operator 3 "less_comparison_operator"
5245 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
5246 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
5247 (match_operand:DI 0 "target_operand" "b")
5250 "b%o3%' %N2, %N1, %0"
5251 [(set_attr "type" "cbranch_media")])
5253 (define_expand "beq"
5255 (if_then_else (ne (reg:SI T_REG) (const_int 0))
5256 (label_ref (match_operand 0 "" ""))
5263 if (GET_MODE (sh_compare_op0) != DImode)
5265 rtx tmp = gen_reg_rtx (DImode);
5267 emit_insn (gen_seq (tmp));
5268 emit_jump_insn (gen_bne_media (operands[0], tmp, const0_rtx));
5272 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5273 emit_jump_insn (gen_beq_media (operands[0],
5274 sh_compare_op0, sh_compare_op1));
5278 from_compare (operands, EQ);
5281 (define_expand "bne"
5283 (if_then_else (eq (reg:SI T_REG) (const_int 0))
5284 (label_ref (match_operand 0 "" ""))
5291 if (GET_MODE (sh_compare_op0) != DImode)
5293 rtx tmp = gen_reg_rtx (DImode);
5295 emit_insn (gen_seq (tmp));
5296 emit_jump_insn (gen_beq_media (operands[0], tmp, const0_rtx));
5300 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5301 emit_jump_insn (gen_bne_media (operands[0],
5302 sh_compare_op0, sh_compare_op1));
5306 from_compare (operands, EQ);
5309 (define_expand "bgt"
5311 (if_then_else (ne (reg:SI T_REG) (const_int 0))
5312 (label_ref (match_operand 0 "" ""))
5319 if (GET_MODE (sh_compare_op0) != DImode)
5321 rtx tmp = gen_reg_rtx (DImode);
5323 emit_insn (gen_sgt (tmp));
5324 emit_jump_insn (gen_bne_media (operands[0], tmp, const0_rtx));
5328 if (sh_compare_op0 != const0_rtx)
5329 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5330 if (sh_compare_op1 != const0_rtx)
5331 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5332 emit_jump_insn (gen_bgt_media (operands[0],
5333 sh_compare_op0, sh_compare_op1));
5337 from_compare (operands, GT);
5340 (define_expand "blt"
5342 (if_then_else (eq (reg:SI T_REG) (const_int 0))
5343 (label_ref (match_operand 0 "" ""))
5350 if (GET_MODE (sh_compare_op0) != DImode)
5352 rtx tmp = gen_reg_rtx (DImode);
5354 emit_insn (gen_slt (tmp));
5355 emit_jump_insn (gen_bne_media (operands[0], tmp, const0_rtx));
5359 if (sh_compare_op0 != const0_rtx)
5360 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5361 if (sh_compare_op1 != const0_rtx)
5362 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5363 emit_jump_insn (gen_bgt_media (operands[0],
5364 sh_compare_op1, sh_compare_op0));
5368 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
5370 rtx tmp = sh_compare_op0;
5371 sh_compare_op0 = sh_compare_op1;
5372 sh_compare_op1 = tmp;
5373 emit_insn (gen_bgt (operands[0]));
5376 from_compare (operands, GE);
5379 (define_expand "ble"
5381 (if_then_else (eq (reg:SI T_REG) (const_int 0))
5382 (label_ref (match_operand 0 "" ""))
5389 if (GET_MODE (sh_compare_op0) != DImode)
5391 rtx tmp = gen_reg_rtx (DImode);
5393 emit_insn (gen_sle (tmp));
5394 emit_jump_insn (gen_bne_media (operands[0], tmp, const0_rtx));
5398 if (sh_compare_op0 != const0_rtx)
5399 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5400 if (sh_compare_op1 != const0_rtx)
5401 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5402 emit_jump_insn (gen_bge_media (operands[0],
5403 sh_compare_op1, sh_compare_op0));
5409 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
5411 rtx tmp = sh_compare_op0;
5412 sh_compare_op0 = sh_compare_op1;
5413 sh_compare_op1 = tmp;
5414 emit_insn (gen_bge (operands[0]));
5417 from_compare (operands, GT);
5420 (define_expand "bge"
5422 (if_then_else (ne (reg:SI T_REG) (const_int 0))
5423 (label_ref (match_operand 0 "" ""))
5430 if (GET_MODE (sh_compare_op0) != DImode)
5432 rtx tmp = gen_reg_rtx (DImode);
5434 emit_insn (gen_sge (tmp));
5435 emit_jump_insn (gen_bne_media (operands[0], tmp, const0_rtx));
5439 if (sh_compare_op0 != const0_rtx)
5440 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5441 if (sh_compare_op1 != const0_rtx)
5442 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5443 emit_jump_insn (gen_bge_media (operands[0],
5444 sh_compare_op0, sh_compare_op1));
5450 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
5452 rtx tmp = sh_compare_op0;
5453 sh_compare_op0 = sh_compare_op1;
5454 sh_compare_op1 = tmp;
5455 emit_insn (gen_ble (operands[0]));
5458 from_compare (operands, GE);
5461 (define_expand "bgtu"
5463 (if_then_else (ne (reg:SI T_REG) (const_int 0))
5464 (label_ref (match_operand 0 "" ""))
5471 if (sh_compare_op0 != const0_rtx)
5472 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5473 if (sh_compare_op1 != const0_rtx)
5474 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5475 emit_jump_insn (gen_bgtu_media (operands[0],
5476 sh_compare_op0, sh_compare_op1));
5480 from_compare (operands, GTU);
5483 (define_expand "bltu"
5485 (if_then_else (eq (reg:SI T_REG) (const_int 0))
5486 (label_ref (match_operand 0 "" ""))
5493 if (sh_compare_op0 != const0_rtx)
5494 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5495 if (sh_compare_op1 != const0_rtx)
5496 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5497 emit_jump_insn (gen_bgtu_media (operands[0],
5498 sh_compare_op1, sh_compare_op0));
5502 from_compare (operands, GEU);
5505 (define_expand "bgeu"
5507 (if_then_else (ne (reg:SI T_REG) (const_int 0))
5508 (label_ref (match_operand 0 "" ""))
5515 if (sh_compare_op0 != const0_rtx)
5516 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5517 if (sh_compare_op1 != const0_rtx)
5518 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5519 emit_jump_insn (gen_bgeu_media (operands[0],
5520 sh_compare_op0, sh_compare_op1));
5524 from_compare (operands, GEU);
5527 (define_expand "bleu"
5529 (if_then_else (eq (reg:SI T_REG) (const_int 0))
5530 (label_ref (match_operand 0 "" ""))
5537 if (sh_compare_op0 != const0_rtx)
5538 sh_compare_op0 = force_reg (DImode, sh_compare_op0);
5539 if (sh_compare_op1 != const0_rtx)
5540 sh_compare_op1 = force_reg (DImode, sh_compare_op1);
5541 emit_jump_insn (gen_bgeu_media (operands[0],
5542 sh_compare_op1, sh_compare_op0));
5546 from_compare (operands, GTU);
5549 (define_expand "bunordered"
5550 [(set (match_dup 1) (unordered:DI (match_dup 2) (match_dup 3)))
5552 (if_then_else (ne (match_dup 1) (const_int 0))
5553 (label_ref:DI (match_operand 0 "" ""))
5558 operands[1] = gen_reg_rtx (DImode);
5559 operands[2] = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
5560 operands[3] = force_reg (GET_MODE (sh_compare_op1), sh_compare_op1);
5563 ;; ------------------------------------------------------------------------
5564 ;; Jump and linkage insns
5565 ;; ------------------------------------------------------------------------
5567 (define_insn "jump_compact"
5569 (label_ref (match_operand 0 "" "")))]
5573 /* The length is 16 if the delay slot is unfilled. */
5574 if (get_attr_length(insn) > 4)
5575 return output_far_jump(insn, operands[0]);
5577 return \"bra %l0%#\";
5579 [(set_attr "type" "jump")
5580 (set_attr "needs_delay_slot" "yes")])
5582 (define_insn "jump_media"
5584 (match_operand:DI 0 "target_operand" "b"))]
5587 [(set_attr "type" "jump_media")])
5589 (define_expand "jump"
5591 (label_ref (match_operand 0 "" "")))]
5596 emit_jump_insn (gen_jump_compact (operands[0]));
5597 else if (TARGET_SHMEDIA)
5599 if (reload_in_progress || reload_completed)
5601 emit_jump_insn (gen_jump_media (gen_rtx_LABEL_REF (DImode,
5607 (define_insn "force_mode_for_call"
5608 [(use (reg:PSI FPSCR_REG))]
5611 [(set_attr "length" "0")
5612 (set (attr "fp_mode")
5613 (if_then_else (eq_attr "fpu_single" "yes")
5614 (const_string "single") (const_string "double")))])
5616 (define_insn "calli"
5617 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
5618 (match_operand 1 "" ""))
5619 (use (reg:PSI FPSCR_REG))
5620 (clobber (reg:SI PR_REG))]
5623 [(set_attr "type" "call")
5624 (set (attr "fp_mode")
5625 (if_then_else (eq_attr "fpu_single" "yes")
5626 (const_string "single") (const_string "double")))
5627 (set_attr "needs_delay_slot" "yes")])
5629 ;; This is a pc-rel call, using bsrf, for use with PIC.
5631 (define_insn "calli_pcrel"
5632 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
5633 (match_operand 1 "" ""))
5634 (use (reg:PSI FPSCR_REG))
5635 (use (reg:SI PIC_REG))
5636 (use (match_operand 2 "" ""))
5637 (clobber (reg:SI PR_REG))]
5640 [(set_attr "type" "call")
5641 (set (attr "fp_mode")
5642 (if_then_else (eq_attr "fpu_single" "yes")
5643 (const_string "single") (const_string "double")))
5644 (set_attr "needs_delay_slot" "yes")])
5646 (define_insn_and_split "call_pcrel"
5647 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
5648 (match_operand 1 "" ""))
5649 (use (reg:PSI FPSCR_REG))
5650 (use (reg:SI PIC_REG))
5651 (clobber (reg:SI PR_REG))
5652 (clobber (match_scratch:SI 2 "=r"))]
5659 rtx lab = PATTERN (gen_call_site ());
5661 if (SYMBOL_REF_FLAG (operands[0]))
5662 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
5664 emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
5665 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], lab));
5668 [(set_attr "type" "call")
5669 (set (attr "fp_mode")
5670 (if_then_else (eq_attr "fpu_single" "yes")
5671 (const_string "single") (const_string "double")))
5672 (set_attr "needs_delay_slot" "yes")])
5674 (define_insn "call_compact"
5675 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
5676 (match_operand 1 "" ""))
5677 (match_operand 2 "immediate_operand" "n")
5678 (use (reg:SI R0_REG))
5679 (use (reg:SI R1_REG))
5680 (use (reg:PSI FPSCR_REG))
5681 (clobber (reg:SI PR_REG))]
5682 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
5684 [(set_attr "type" "call")
5685 (set (attr "fp_mode")
5686 (if_then_else (eq_attr "fpu_single" "yes")
5687 (const_string "single") (const_string "double")))
5688 (set_attr "needs_delay_slot" "yes")])
5690 (define_insn "call_compact_rettramp"
5691 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
5692 (match_operand 1 "" ""))
5693 (match_operand 2 "immediate_operand" "n")
5694 (use (reg:SI R0_REG))
5695 (use (reg:SI R1_REG))
5696 (use (reg:PSI FPSCR_REG))
5697 (clobber (reg:SI R10_REG))
5698 (clobber (reg:SI PR_REG))]
5699 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
5701 [(set_attr "type" "call")
5702 (set (attr "fp_mode")
5703 (if_then_else (eq_attr "fpu_single" "yes")
5704 (const_string "single") (const_string "double")))
5705 (set_attr "needs_delay_slot" "yes")])
5707 (define_insn "call_media"
5708 [(call (mem:DI (match_operand:DI 0 "target_reg_operand" "b"))
5709 (match_operand 1 "" ""))
5710 (clobber (reg:DI PR_MEDIA_REG))]
5713 [(set_attr "type" "jump_media")])
5715 (define_insn "call_valuei"
5716 [(set (match_operand 0 "" "=rf")
5717 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
5718 (match_operand 2 "" "")))
5719 (use (reg:PSI FPSCR_REG))
5720 (clobber (reg:SI PR_REG))]
5723 [(set_attr "type" "call")
5724 (set (attr "fp_mode")
5725 (if_then_else (eq_attr "fpu_single" "yes")
5726 (const_string "single") (const_string "double")))
5727 (set_attr "needs_delay_slot" "yes")])
5729 (define_insn "call_valuei_pcrel"
5730 [(set (match_operand 0 "" "=rf")
5731 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
5732 (match_operand 2 "" "")))
5733 (use (reg:PSI FPSCR_REG))
5734 (use (reg:SI PIC_REG))
5735 (use (match_operand 3 "" ""))
5736 (clobber (reg:SI PR_REG))]
5739 [(set_attr "type" "call")
5740 (set (attr "fp_mode")
5741 (if_then_else (eq_attr "fpu_single" "yes")
5742 (const_string "single") (const_string "double")))
5743 (set_attr "needs_delay_slot" "yes")])
5745 (define_insn_and_split "call_value_pcrel"
5746 [(set (match_operand 0 "" "=rf")
5747 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
5748 (match_operand 2 "" "")))
5749 (use (reg:PSI FPSCR_REG))
5750 (use (reg:SI PIC_REG))
5751 (clobber (reg:SI PR_REG))
5752 (clobber (match_scratch:SI 3 "=r"))]
5759 rtx lab = PATTERN (gen_call_site ());
5761 if (SYMBOL_REF_FLAG (operands[1]))
5762 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
5764 emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
5765 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
5769 [(set_attr "type" "call")
5770 (set (attr "fp_mode")
5771 (if_then_else (eq_attr "fpu_single" "yes")
5772 (const_string "single") (const_string "double")))
5773 (set_attr "needs_delay_slot" "yes")])
5775 (define_insn "call_value_compact"
5776 [(set (match_operand 0 "" "=rf")
5777 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
5778 (match_operand 2 "" "")))
5779 (match_operand 3 "immediate_operand" "n")
5780 (use (reg:SI R0_REG))
5781 (use (reg:SI R1_REG))
5782 (use (reg:PSI FPSCR_REG))
5783 (clobber (reg:SI PR_REG))]
5784 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
5786 [(set_attr "type" "call")
5787 (set (attr "fp_mode")
5788 (if_then_else (eq_attr "fpu_single" "yes")
5789 (const_string "single") (const_string "double")))
5790 (set_attr "needs_delay_slot" "yes")])
5792 (define_insn "call_value_compact_rettramp"
5793 [(set (match_operand 0 "" "=rf")
5794 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
5795 (match_operand 2 "" "")))
5796 (match_operand 3 "immediate_operand" "n")
5797 (use (reg:SI R0_REG))
5798 (use (reg:SI R1_REG))
5799 (use (reg:PSI FPSCR_REG))
5800 (clobber (reg:SI R10_REG))
5801 (clobber (reg:SI PR_REG))]
5802 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
5804 [(set_attr "type" "call")
5805 (set (attr "fp_mode")
5806 (if_then_else (eq_attr "fpu_single" "yes")
5807 (const_string "single") (const_string "double")))
5808 (set_attr "needs_delay_slot" "yes")])
5810 (define_insn "call_value_media"
5811 [(set (match_operand 0 "" "=rf")
5812 (call (mem:DI (match_operand:DI 1 "target_reg_operand" "b"))
5813 (match_operand 2 "" "")))
5814 (clobber (reg:DI PR_MEDIA_REG))]
5817 [(set_attr "type" "jump_media")])
5819 (define_expand "call"
5820 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
5821 (match_operand 1 "" ""))
5822 (match_operand 2 "" "")
5823 (use (reg:PSI FPSCR_REG))
5824 (clobber (reg:SI PR_REG))])]
5830 operands[0] = XEXP (operands[0], 0);
5831 if (flag_pic && GET_CODE (operands[0]) == SYMBOL_REF)
5833 if (! SYMBOL_REF_FLAG (operands[0]))
5835 rtx reg = gen_reg_rtx (Pmode);
5837 emit_insn (gen_symGOTPLT2reg (reg, operands[0]));
5842 operands[0] = gen_sym2PIC (operands[0]);
5843 PUT_MODE (operands[0], Pmode);
5846 if (GET_MODE (operands[0]) == SImode)
5848 if (GET_CODE (operands[0]) == REG)
5849 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
5850 else if (GET_CODE (operands[0]) == SUBREG)
5852 operands[0] = SUBREG_REG (operands[0]);
5853 if (GET_MODE (operands[0]) != DImode)
5854 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
5858 operands[0] = shallow_copy_rtx (operands[0]);
5859 PUT_MODE (operands[0], DImode);
5862 if (! target_reg_operand (operands[0], DImode))
5863 operands[0] = copy_to_mode_reg (DImode, operands[0]);
5864 emit_call_insn (gen_call_media (operands[0], operands[1]));
5867 else if (TARGET_SHCOMPACT && operands[2] && INTVAL (operands[2]))
5869 rtx cookie_rtx = operands[2];
5870 long cookie = INTVAL (cookie_rtx);
5871 rtx func = XEXP (operands[0], 0);
5876 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
5878 rtx reg = gen_reg_rtx (Pmode);
5880 emit_insn (gen_symGOTPLT2reg (reg, func));
5884 func = legitimize_pic_address (func, Pmode, 0);
5887 r0 = gen_rtx_REG (SImode, R0_REG);
5888 r1 = gen_rtx_REG (SImode, R1_REG);
5890 /* Since such a call function may use all call-clobbered
5891 registers, we force a mode switch earlier, so that we don't
5892 run out of registers when adjusting fpscr for the call. */
5893 emit_insn (gen_force_mode_for_call ());
5895 operands[0] = gen_rtx_SYMBOL_REF (SImode,
5896 \"__GCC_shcompact_call_trampoline\");
5899 rtx reg = gen_reg_rtx (Pmode);
5901 emit_insn (gen_symGOTPLT2reg (reg, operands[0]));
5904 operands[0] = force_reg (SImode, operands[0]);
5906 emit_move_insn (r0, func);
5907 emit_move_insn (r1, cookie_rtx);
5909 if (cookie & CALL_COOKIE_RET_TRAMP (1))
5910 emit_call_insn (gen_call_compact_rettramp (operands[0], operands[1],
5913 emit_call_insn (gen_call_compact (operands[0], operands[1],
5918 else if (TARGET_SHCOMPACT && flag_pic
5919 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
5920 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
5922 rtx reg = gen_reg_rtx (Pmode);
5924 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[0], 0)));
5925 XEXP (operands[0], 0) = reg;
5927 if (flag_pic && TARGET_SH2
5928 && GET_CODE (operands[0]) == MEM
5929 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5931 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
5935 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
5937 emit_call_insn (gen_calli (operands[0], operands[1]));
5941 (define_insn "call_pop_compact"
5942 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
5943 (match_operand 1 "" ""))
5944 (match_operand 2 "immediate_operand" "n")
5945 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
5946 (match_operand 3 "immediate_operand" "n")))
5947 (use (reg:SI R0_REG))
5948 (use (reg:SI R1_REG))
5949 (use (reg:PSI FPSCR_REG))
5950 (clobber (reg:SI PR_REG))]
5951 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
5953 [(set_attr "type" "call")
5954 (set (attr "fp_mode")
5955 (if_then_else (eq_attr "fpu_single" "yes")
5956 (const_string "single") (const_string "double")))
5957 (set_attr "needs_delay_slot" "yes")])
5959 (define_insn "call_pop_compact_rettramp"
5960 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
5961 (match_operand 1 "" ""))
5962 (match_operand 2 "immediate_operand" "n")
5963 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
5964 (match_operand 3 "immediate_operand" "n")))
5965 (use (reg:SI R0_REG))
5966 (use (reg:SI R1_REG))
5967 (use (reg:PSI FPSCR_REG))
5968 (clobber (reg:SI R10_REG))
5969 (clobber (reg:SI PR_REG))]
5970 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
5972 [(set_attr "type" "call")
5973 (set (attr "fp_mode")
5974 (if_then_else (eq_attr "fpu_single" "yes")
5975 (const_string "single") (const_string "double")))
5976 (set_attr "needs_delay_slot" "yes")])
5978 (define_expand "call_pop"
5979 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
5980 (match_operand 1 "" ""))
5981 (match_operand 2 "" "")
5982 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
5983 (match_operand 3 "" "")))])]
5987 if (operands[2] && INTVAL (operands[2]))
5989 rtx cookie_rtx = operands[2];
5990 long cookie = INTVAL (cookie_rtx);
5991 rtx func = XEXP (operands[0], 0);
5996 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
5998 rtx reg = gen_reg_rtx (Pmode);
6000 emit_insn (gen_symGOTPLT2reg (reg, func));
6004 func = legitimize_pic_address (func, Pmode, 0);
6007 r0 = gen_rtx_REG (SImode, R0_REG);
6008 r1 = gen_rtx_REG (SImode, R1_REG);
6010 /* Since such a call function may use all call-clobbered
6011 registers, we force a mode switch earlier, so that we don't
6012 run out of registers when adjusting fpscr for the call. */
6013 emit_insn (gen_force_mode_for_call ());
6015 operands[0] = gen_rtx_SYMBOL_REF (SImode,
6016 \"__GCC_shcompact_call_trampoline\");
6019 rtx reg = gen_reg_rtx (Pmode);
6021 emit_insn (gen_symGOTPLT2reg (reg, operands[0]));
6024 operands[0] = force_reg (SImode, operands[0]);
6026 emit_move_insn (r0, func);
6027 emit_move_insn (r1, cookie_rtx);
6029 if (cookie & CALL_COOKIE_RET_TRAMP (1))
6030 emit_call_insn (gen_call_pop_compact_rettramp
6031 (operands[0], operands[1], operands[2], operands[3]));
6033 emit_call_insn (gen_call_pop_compact
6034 (operands[0], operands[1], operands[2], operands[3]));
6042 (define_expand "call_value"
6043 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
6044 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
6045 (match_operand 2 "" "")))
6046 (match_operand 3 "" "")
6047 (use (reg:PSI FPSCR_REG))
6048 (clobber (reg:SI PR_REG))])]
6054 operands[1] = XEXP (operands[1], 0);
6055 if (flag_pic && GET_CODE (operands[1]) == SYMBOL_REF)
6057 if (! SYMBOL_REF_FLAG (operands[1]))
6059 rtx reg = gen_reg_rtx (Pmode);
6061 emit_insn (gen_symGOTPLT2reg (reg, operands[1]));
6066 operands[1] = gen_sym2PIC (operands[1]);
6067 PUT_MODE (operands[1], Pmode);
6070 if (GET_MODE (operands[1]) == SImode)
6072 if (GET_CODE (operands[1]) == REG)
6073 operands[1] = gen_rtx_SUBREG (DImode, operands[1], 0);
6074 else if (GET_CODE (operands[1]) == SUBREG)
6076 operands[1] = SUBREG_REG (operands[1]);
6077 if (GET_MODE (operands[1]) != DImode)
6078 operands[1] = gen_rtx_SUBREG (DImode, operands[1], 0);
6082 operands[1] = shallow_copy_rtx (operands[1]);
6083 PUT_MODE (operands[1], DImode);
6086 if (! target_reg_operand (operands[1], DImode))
6087 operands[1] = copy_to_mode_reg (DImode, operands[1]);
6088 emit_call_insn (gen_call_value_media (operands[0], operands[1],
6092 else if (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]))
6094 rtx cookie_rtx = operands[3];
6095 long cookie = INTVAL (cookie_rtx);
6096 rtx func = XEXP (operands[1], 0);
6101 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
6103 rtx reg = gen_reg_rtx (Pmode);
6105 emit_insn (gen_symGOTPLT2reg (reg, func));
6109 func = legitimize_pic_address (func, Pmode, 0);
6112 r0 = gen_rtx_REG (SImode, R0_REG);
6113 r1 = gen_rtx_REG (SImode, R1_REG);
6115 /* Since such a call function may use all call-clobbered
6116 registers, we force a mode switch earlier, so that we don't
6117 run out of registers when adjusting fpscr for the call. */
6118 emit_insn (gen_force_mode_for_call ());
6120 operands[1] = gen_rtx_SYMBOL_REF (SImode,
6121 \"__GCC_shcompact_call_trampoline\");
6124 rtx reg = gen_reg_rtx (Pmode);
6126 emit_insn (gen_symGOTPLT2reg (reg, operands[1]));
6129 operands[1] = force_reg (SImode, operands[1]);
6131 emit_move_insn (r0, func);
6132 emit_move_insn (r1, cookie_rtx);
6134 if (cookie & CALL_COOKIE_RET_TRAMP (1))
6135 emit_call_insn (gen_call_value_compact_rettramp (operands[0],
6140 emit_call_insn (gen_call_value_compact (operands[0], operands[1],
6141 operands[2], operands[3]));
6145 else if (TARGET_SHCOMPACT && flag_pic
6146 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
6147 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
6149 rtx reg = gen_reg_rtx (Pmode);
6151 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[1], 0)));
6152 XEXP (operands[1], 0) = reg;
6154 if (flag_pic && TARGET_SH2
6155 && GET_CODE (operands[1]) == MEM
6156 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6158 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
6163 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
6165 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
6169 (define_insn "sibcalli"
6170 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
6171 (match_operand 1 "" ""))
6172 (use (reg:PSI FPSCR_REG))
6176 [(set_attr "needs_delay_slot" "yes")
6177 (set (attr "fp_mode")
6178 (if_then_else (eq_attr "fpu_single" "yes")
6179 (const_string "single") (const_string "double")))
6180 (set_attr "type" "jump_ind")])
6182 (define_insn "sibcalli_pcrel"
6183 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
6184 (match_operand 1 "" ""))
6185 (use (match_operand 2 "" ""))
6186 (use (reg:PSI FPSCR_REG))
6190 [(set_attr "needs_delay_slot" "yes")
6191 (set (attr "fp_mode")
6192 (if_then_else (eq_attr "fpu_single" "yes")
6193 (const_string "single") (const_string "double")))
6194 (set_attr "type" "jump_ind")])
6196 (define_insn_and_split "sibcall_pcrel"
6197 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
6198 (match_operand 1 "" ""))
6199 (use (reg:PSI FPSCR_REG))
6200 (clobber (match_scratch:SI 2 "=k"))
6208 rtx lab = PATTERN (gen_call_site ());
6211 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
6212 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
6214 SIBLING_CALL_P (call_insn) = 1;
6217 [(set_attr "needs_delay_slot" "yes")
6218 (set (attr "fp_mode")
6219 (if_then_else (eq_attr "fpu_single" "yes")
6220 (const_string "single") (const_string "double")))
6221 (set_attr "type" "jump_ind")])
6223 (define_insn "sibcall_compact"
6224 [(call (mem:SI (match_operand:SI 0 "register_operand" "k,k"))
6225 (match_operand 1 "" ""))
6227 (use (match_operand:SI 2 "register_operand" "z,x"))
6228 (use (reg:SI R1_REG))
6229 (use (reg:PSI FPSCR_REG))
6230 ;; We want to make sure the `x' above will only match MACH_REG
6231 ;; because sibcall_epilogue may clobber MACL_REG.
6232 (clobber (reg:SI MACL_REG))]
6236 jmp @%0\\n sts %2, r0"
6237 [(set_attr "needs_delay_slot" "yes,no")
6238 (set_attr "length" "2,4")
6239 (set (attr "fp_mode") (const_string "single"))
6240 (set_attr "type" "jump_ind")])
6242 (define_insn "sibcall_media"
6243 [(call (mem:DI (match_operand:DI 0 "target_reg_operand" "k"))
6244 (match_operand 1 "" ""))
6248 [(set_attr "type" "jump_media")])
6250 (define_expand "sibcall"
6252 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
6253 (match_operand 1 "" ""))
6254 (match_operand 2 "" "")
6255 (use (reg:PSI FPSCR_REG))
6262 operands[0] = XEXP (operands[0], 0);
6263 if (flag_pic && GET_CODE (operands[0]) == SYMBOL_REF)
6265 if (! SYMBOL_REF_FLAG (operands[0]))
6267 rtx reg = gen_reg_rtx (Pmode);
6269 /* We must not use GOTPLT for sibcalls, because PIC_REG
6270 must be restored before the PLT code gets to run. */
6271 emit_insn (gen_symGOT2reg (reg, operands[0]));
6276 operands[0] = gen_sym2PIC (operands[0]);
6277 PUT_MODE (operands[0], Pmode);
6280 if (GET_MODE (operands[0]) == SImode)
6282 if (GET_CODE (operands[0]) == REG)
6283 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
6284 else if (GET_CODE (operands[0]) == SUBREG)
6286 operands[0] = SUBREG_REG (operands[0]);
6287 if (GET_MODE (operands[0]) != DImode)
6288 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
6292 operands[0] = shallow_copy_rtx (operands[0]);
6293 PUT_MODE (operands[0], DImode);
6296 if (! target_reg_operand (operands[0], DImode))
6297 operands[0] = copy_to_mode_reg (DImode, operands[0]);
6298 emit_call_insn (gen_sibcall_media (operands[0], operands[1]));
6301 else if (TARGET_SHCOMPACT && operands[2]
6302 && (INTVAL (operands[2]) & ~ CALL_COOKIE_RET_TRAMP (1)))
6304 rtx cookie_rtx = operands[2];
6305 long cookie = INTVAL (cookie_rtx);
6306 rtx func = XEXP (operands[0], 0);
6311 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
6313 rtx reg = gen_reg_rtx (Pmode);
6315 emit_insn (gen_symGOT2reg (reg, func));
6319 func = legitimize_pic_address (func, Pmode, 0);
6322 /* FIXME: if we could tell whether all argument registers are
6323 already taken, we could decide whether to force the use of
6324 MACH_REG or to stick to R0_REG. Unfortunately, there's no
6325 simple way to tell. We could use the CALL_COOKIE, but we
6326 can't currently tell a register used for regular argument
6327 passing from one that is unused. If we leave it up to reload
6328 to decide which register to use, it seems to always choose
6329 R0_REG, which leaves no available registers in SIBCALL_REGS
6330 to hold the address of the trampoline. */
6331 mach = gen_rtx_REG (SImode, MACH_REG);
6332 r1 = gen_rtx_REG (SImode, R1_REG);
6334 /* Since such a call function may use all call-clobbered
6335 registers, we force a mode switch earlier, so that we don't
6336 run out of registers when adjusting fpscr for the call. */
6337 emit_insn (gen_force_mode_for_call ());
6339 operands[0] = gen_rtx_SYMBOL_REF (SImode,
6340 \"__GCC_shcompact_call_trampoline\");
6343 rtx reg = gen_reg_rtx (Pmode);
6345 emit_insn (gen_symGOT2reg (reg, operands[0]));
6348 operands[0] = force_reg (SImode, operands[0]);
6350 /* We don't need a return trampoline, since the callee will
6351 return directly to the upper caller. */
6352 if (cookie & CALL_COOKIE_RET_TRAMP (1))
6354 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
6355 cookie_rtx = GEN_INT (cookie);
6358 emit_move_insn (mach, func);
6359 emit_move_insn (r1, cookie_rtx);
6361 emit_call_insn (gen_sibcall_compact (operands[0], operands[1], mach));
6364 else if (TARGET_SHCOMPACT && flag_pic
6365 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
6366 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
6368 rtx reg = gen_reg_rtx (Pmode);
6370 emit_insn (gen_symGOT2reg (reg, XEXP (operands[0], 0)));
6371 XEXP (operands[0], 0) = reg;
6373 if (flag_pic && TARGET_SH2
6374 && GET_CODE (operands[0]) == MEM
6375 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
6376 /* The PLT needs the PIC register, but the epilogue would have
6377 to restore it, so we can only use PC-relative PIC calls for
6378 static functions. */
6379 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
6381 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
6385 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
6387 emit_call_insn (gen_sibcalli (operands[0], operands[1]));
6391 (define_expand "sibcall_value"
6392 [(set (match_operand 0 "" "")
6393 (call (match_operand 1 "" "")
6394 (match_operand 2 "" "")))
6395 (match_operand 3 "" "")]
6399 emit_call_insn (gen_sibcall (operands[1], operands[2], operands[3]));
6403 (define_insn "call_value_pop_compact"
6404 [(set (match_operand 0 "" "=rf")
6405 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6406 (match_operand 2 "" "")))
6407 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
6408 (match_operand 4 "immediate_operand" "n")))
6409 (match_operand 3 "immediate_operand" "n")
6410 (use (reg:SI R0_REG))
6411 (use (reg:SI R1_REG))
6412 (use (reg:PSI FPSCR_REG))
6413 (clobber (reg:SI PR_REG))]
6414 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
6416 [(set_attr "type" "call")
6417 (set (attr "fp_mode")
6418 (if_then_else (eq_attr "fpu_single" "yes")
6419 (const_string "single") (const_string "double")))
6420 (set_attr "needs_delay_slot" "yes")])
6422 (define_insn "call_value_pop_compact_rettramp"
6423 [(set (match_operand 0 "" "=rf")
6424 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6425 (match_operand 2 "" "")))
6426 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
6427 (match_operand 4 "immediate_operand" "n")))
6428 (match_operand 3 "immediate_operand" "n")
6429 (use (reg:SI R0_REG))
6430 (use (reg:SI R1_REG))
6431 (use (reg:PSI FPSCR_REG))
6432 (clobber (reg:SI R10_REG))
6433 (clobber (reg:SI PR_REG))]
6434 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
6436 [(set_attr "type" "call")
6437 (set (attr "fp_mode")
6438 (if_then_else (eq_attr "fpu_single" "yes")
6439 (const_string "single") (const_string "double")))
6440 (set_attr "needs_delay_slot" "yes")])
6442 (define_expand "call_value_pop"
6443 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
6444 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
6445 (match_operand 2 "" "")))
6446 (match_operand 3 "" "")
6447 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
6448 (match_operand 4 "" "")))])]
6452 if (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]))
6454 rtx cookie_rtx = operands[3];
6455 long cookie = INTVAL (cookie_rtx);
6456 rtx func = XEXP (operands[1], 0);
6461 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_FLAG (func))
6463 rtx reg = gen_reg_rtx (Pmode);
6465 emit_insn (gen_symGOTPLT2reg (reg, func));
6469 func = legitimize_pic_address (func, Pmode, 0);
6472 r0 = gen_rtx_REG (SImode, R0_REG);
6473 r1 = gen_rtx_REG (SImode, R1_REG);
6475 /* Since such a call function may use all call-clobbered
6476 registers, we force a mode switch earlier, so that we don't
6477 run out of registers when adjusting fpscr for the call. */
6478 emit_insn (gen_force_mode_for_call ());
6480 operands[1] = gen_rtx_SYMBOL_REF (SImode,
6481 \"__GCC_shcompact_call_trampoline\");
6484 rtx reg = gen_reg_rtx (Pmode);
6486 emit_insn (gen_symGOTPLT2reg (reg, operands[1]));
6489 operands[1] = force_reg (SImode, operands[1]);
6491 emit_move_insn (r0, func);
6492 emit_move_insn (r1, cookie_rtx);
6494 if (cookie & CALL_COOKIE_RET_TRAMP (1))
6495 emit_call_insn (gen_call_value_pop_compact_rettramp
6496 (operands[0], operands[1], operands[2],
6497 operands[3], operands[4]));
6499 emit_call_insn (gen_call_value_pop_compact
6500 (operands[0], operands[1], operands[2],
6501 operands[3], operands[4]));
6509 (define_expand "sibcall_epilogue"
6514 sh_expand_epilogue ();
6515 if (TARGET_SHCOMPACT)
6519 /* If epilogue clobbers r0, preserve it in macl. */
6520 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6521 if ((set = single_set (insn))
6522 && GET_CODE (SET_DEST (set)) == REG
6523 && REGNO (SET_DEST (set)) == R0_REG)
6525 rtx r0 = gen_rtx_REG (SImode, R0_REG);
6526 rtx tmp = gen_rtx_REG (SImode, MACL_REG);
6529 /* We can't tell at this point whether the sibcall is a
6530 sibcall_compact and, if it is, whether it uses r0 or
6531 mach as operand 2, so let the instructions that
6532 preserve r0 be optimized away if r0 turns out to be
6534 i = emit_insn_before (gen_rtx_SET (SImode, tmp, r0), insn);
6535 REG_NOTES (i) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx,
6537 i = emit_move_insn (r0, tmp);
6538 REG_NOTES (i) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx,
6546 (define_insn "indirect_jump_compact"
6548 (match_operand:SI 0 "arith_reg_operand" "r"))]
6551 [(set_attr "needs_delay_slot" "yes")
6552 (set_attr "type" "jump_ind")])
6554 (define_expand "indirect_jump"
6556 (match_operand 0 "register_operand" ""))]
6560 if (TARGET_SHMEDIA && GET_MODE (operands[0]) == SImode)
6561 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
6564 ;; The use of operand 1 / 2 helps us distinguish case table jumps
6565 ;; which can be present in structured code from indirect jumps which can not
6566 ;; be present in structured code. This allows -fprofile-arcs to work.
6568 ;; For SH1 processors.
6569 (define_insn "casesi_jump_1"
6571 (match_operand:SI 0 "register_operand" "r"))
6572 (use (label_ref (match_operand 1 "" "")))]
6575 [(set_attr "needs_delay_slot" "yes")
6576 (set_attr "type" "jump_ind")])
6578 ;; For all later processors.
6579 (define_insn "casesi_jump_2"
6580 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
6581 (label_ref (match_operand 1 "" ""))))
6582 (use (label_ref (match_operand 2 "" "")))]
6584 && (! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn)"
6586 [(set_attr "needs_delay_slot" "yes")
6587 (set_attr "type" "jump_ind")])
6589 (define_insn "casesi_jump_media"
6590 [(set (pc) (match_operand:DI 0 "target_reg_operand" "b"))
6591 (use (label_ref (match_operand 1 "" "")))]
6594 [(set_attr "type" "jump_media")])
6596 ;; Call subroutine returning any type.
6597 ;; ??? This probably doesn't work.
6599 (define_expand "untyped_call"
6600 [(parallel [(call (match_operand 0 "" "")
6602 (match_operand 1 "" "")
6603 (match_operand 2 "" "")])]
6604 "TARGET_SH3E || TARGET_SHMEDIA"
6609 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6611 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6613 rtx set = XVECEXP (operands[2], 0, i);
6614 emit_move_insn (SET_DEST (set), SET_SRC (set));
6617 /* The optimizer does not know that the call sets the function value
6618 registers we stored in the result block. We avoid problems by
6619 claiming that all hard registers are used and clobbered at this
6621 emit_insn (gen_blockage ());
6626 ;; ------------------------------------------------------------------------
6628 ;; ------------------------------------------------------------------------
6631 [(set (reg:SI T_REG)
6632 (eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
6633 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
6636 [(set_attr "type" "arith")])
6643 ;; Load address of a label. This is only generated by the casesi expand,
6644 ;; and by machine_dependent_reorg (fixing up fp moves).
6645 ;; This must use unspec, because this only works for labels that are
6649 [(set (reg:SI R0_REG)
6650 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
6653 [(set_attr "in_delay_slot" "no")
6654 (set_attr "type" "arith")])
6656 ;; machine_dependent_reorg() will make this a `mova'.
6657 (define_insn "mova_const"
6658 [(set (reg:SI R0_REG)
6659 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
6662 [(set_attr "in_delay_slot" "no")
6663 (set_attr "type" "arith")])
6665 (define_expand "GOTaddr2picreg"
6666 [(set (reg:SI R0_REG)
6667 (unspec:SI [(const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC))]
6669 (set (match_dup 0) (const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC)))
6670 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
6673 operands[0] = gen_rtx_REG (Pmode, PIC_REG);
6674 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
6677 operands[1] = gen_datalabel_ref (operands[1]);
6681 rtx tr = gen_rtx_REG (DImode, TR0_REG);
6682 rtx dipic = operands[0];
6683 rtx lab = PATTERN (gen_call_site ());
6686 equiv = operands[1];
6687 operands[1] = gen_rtx_MINUS (DImode,
6691 gen_rtx_MINUS (DImode,
6692 gen_rtx_CONST (DImode,
6695 operands[1] = gen_sym2PIC (operands[1]);
6696 PUT_MODE (operands[1], DImode);
6698 if (GET_MODE (dipic) != DImode)
6699 dipic = gen_rtx_SUBREG (DImode, dipic, 0);
6701 if (TARGET_SHMEDIA64)
6702 emit_insn (gen_movdi_const (dipic, operands[1]));
6704 emit_insn (gen_movdi_const_32bit (dipic, operands[1]));
6706 emit_insn (gen_ptrel (tr, dipic, lab));
6708 if (GET_MODE (operands[0]) != GET_MODE (tr))
6709 tr = gen_rtx_SUBREG (GET_MODE (operands[0]), tr, 0);
6711 insn = emit_move_insn (operands[0], tr);
6713 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, equiv,
6721 ;; When generating PIC, we must match label_refs especially, because
6722 ;; they do not satisfy LEGITIMATE_PIC_OPERAND_P(), and we don't want
6723 ;; them to do, because they can't be loaded directly into
6724 ;; non-branch-target registers.
6726 [(set (match_operand:DI 0 "target_reg_operand" "=b")
6727 (match_operand:DI 1 "" "T"))]
6728 "TARGET_SHMEDIA && flag_pic
6729 && EXTRA_CONSTRAINT_T (operands[1])"
6731 [(set_attr "type" "pt_media")
6732 (set_attr "length" "*")])
6735 [(set (match_operand:DI 0 "target_reg_operand" "=b")
6736 (const:DI (unspec:DI [(match_operand:DI 1 "" "T")]
6737 UNSPEC_DATALABEL)))]
6738 "TARGET_SHMEDIA && flag_pic
6739 && EXTRA_CONSTRAINT_T (operands[1])"
6740 "ptb/u datalabel %1, %0"
6741 [(set_attr "type" "pt_media")
6742 (set_attr "length" "*")])
6744 (define_insn "ptrel"
6745 [(set (match_operand:DI 0 "target_reg_operand" "=b")
6746 (plus:DI (match_operand:DI 1 "register_operand" "r")
6748 (match_operand:DI 2 "" "")]
6750 "%O2: ptrel/u %1, %0"
6751 [(set_attr "type" "ptabs_media")])
6753 (define_expand "builtin_setjmp_receiver"
6754 [(match_operand 0 "" "")]
6758 emit_insn (gen_GOTaddr2picreg ());
6762 (define_expand "call_site"
6763 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
6767 static HOST_WIDE_INT i = 0;
6768 operands[0] = GEN_INT (i);
6772 (define_expand "sym_label2reg"
6773 [(set (match_operand:SI 0 "" "")
6776 (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC))
6779 (match_operand:SI 2 "" "")
6783 (define_expand "symGOT_load"
6784 [(set (match_dup 2) (match_operand 1 "" ""))
6785 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
6786 (set (match_operand 0 "" "") (mem (match_dup 3)))]
6792 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
6793 operands[3] = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
6797 rtx reg = operands[2];
6799 if (GET_MODE (reg) != DImode)
6800 reg = gen_rtx_SUBREG (DImode, reg, 0);
6803 emit_insn (gen_movdi_const_32bit (reg, operands[1]));
6805 emit_insn (gen_movdi_const_16bit (reg, operands[1]));
6808 emit_move_insn (operands[2], operands[1]);
6810 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode,
6812 gen_rtx_REG (Pmode, PIC_REG)));
6814 insn = emit_move_insn (operands[0], gen_rtx_MEM (Pmode, operands[3]));
6816 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, XVECEXP (XEXP (operands[1],
6823 (define_expand "sym2GOT"
6824 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))]
6828 (define_expand "symGOT2reg"
6829 [(match_operand 0 "" "") (match_operand 1 "" "")]
6835 gotsym = gen_sym2GOT (operands[1]);
6836 PUT_MODE (gotsym, Pmode);
6837 insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
6839 RTX_UNCHANGING_P (SET_SRC (PATTERN (insn))) = 1;
6844 (define_expand "sym2GOTPLT"
6845 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTPLT))]
6849 (define_expand "symGOTPLT2reg"
6850 [(match_operand 0 "" "") (match_operand 1 "" "")]
6854 emit_insn (gen_symGOT_load (operands[0], gen_sym2GOTPLT (operands[1])));
6858 (define_expand "sym2GOTOFF"
6859 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))]
6863 (define_expand "symGOTOFF2reg"
6864 [(match_operand 0 "" "") (match_operand 1 "" "")]
6868 rtx gotoffsym, insn;
6869 rtx t = no_new_pseudos ? operands[0] : gen_reg_rtx (GET_MODE (operands[0]));
6871 gotoffsym = gen_sym2GOTOFF (operands[1]);
6872 PUT_MODE (gotoffsym, Pmode);
6873 emit_move_insn (t, gotoffsym);
6874 insn = emit_move_insn (operands[0],
6875 gen_rtx_PLUS (Pmode, t,
6876 gen_rtx_REG (Pmode, PIC_REG)));
6878 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
6884 (define_expand "symPLT_label2reg"
6885 [(set (match_operand:SI 0 "" "")
6888 (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT))
6892 (match_operand:SI 2 "" "")
6894 (const:SI (unspec:SI [(pc)] UNSPEC_PIC)))))))
6895 ;; Even though the PIC register is not really used by the call
6896 ;; sequence in which this is expanded, the PLT code assumes the PIC
6897 ;; register is set, so we must not skip its initialization. Since
6898 ;; we only use this expand as part of calling sequences, and never
6899 ;; to take the address of a function, this is the best point to
6900 ;; insert the (use). Using the PLT to take the address of a
6901 ;; function would be wrong, not only because the PLT entry could
6902 ;; then be called from a function that doesn't initialize the PIC
6903 ;; register to the proper GOT, but also because pointers to the
6904 ;; same function might not compare equal, should they be set by
6905 ;; different shared libraries.
6906 (use (reg:SI PIC_REG))]
6910 (define_expand "sym2PIC"
6911 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))]
6915 ;; case instruction for switch statements.
6917 ;; Operand 0 is index
6918 ;; operand 1 is the minimum bound
6919 ;; operand 2 is the maximum bound - minimum bound + 1
6920 ;; operand 3 is CODE_LABEL for the table;
6921 ;; operand 4 is the CODE_LABEL to go to if index out of range.
6923 (define_expand "casesi"
6924 [(match_operand:SI 0 "arith_reg_operand" "")
6925 (match_operand:SI 1 "arith_reg_operand" "")
6926 (match_operand:SI 2 "arith_reg_operand" "")
6927 (match_operand 3 "" "") (match_operand 4 "" "")]
6931 rtx reg = gen_reg_rtx (SImode);
6932 rtx reg2 = gen_reg_rtx (SImode);
6935 rtx reg = gen_reg_rtx (DImode);
6936 rtx reg2 = gen_reg_rtx (DImode);
6937 rtx reg3 = gen_reg_rtx (DImode);
6938 rtx reg4 = gen_reg_rtx (DImode);
6939 rtx reg5 = gen_reg_rtx (DImode);
6941 operands[0] = convert_modes (DImode, SImode, operands[0], 0);
6942 operands[1] = convert_modes (DImode, SImode, operands[1], 0);
6943 operands[2] = convert_modes (DImode, SImode, operands[2], 1);
6945 emit_jump_insn (gen_bgt_media (operands[4], operands[1], operands[0]));
6946 emit_move_insn (reg, gen_rtx_MINUS (DImode, operands[0], operands[1]));
6947 emit_jump_insn (gen_bgtu_media (operands[4], reg, operands[2]));
6948 emit_insn (gen_casesi_shift_media (reg2, reg, operands[3]));
6949 emit_move_insn (reg3, gen_datalabel_ref (gen_rtx_LABEL_REF
6950 (DImode, operands[3])));
6951 emit_insn (gen_casesi_load_media (reg4, reg3, reg2, operands[3]));
6952 emit_move_insn (reg5, gen_rtx_PLUS (DImode, reg3, reg4));
6953 emit_jump_insn (gen_casesi_jump_media (reg5, operands[3]));
6957 operands[1] = copy_to_mode_reg (SImode, operands[1]);
6958 operands[2] = copy_to_mode_reg (SImode, operands[2]);
6959 /* If optimizing, casesi_worker depends on the mode of the instruction
6960 before label it 'uses' - operands[3]. */
6961 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
6963 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
6965 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
6967 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
6968 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
6969 operands[3], but to lab. We will fix this up in
6970 machine_dependent_reorg. */
6975 (define_expand "casesi_0"
6976 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
6977 (set (match_dup 4) (minus:SI (match_dup 4)
6978 (match_operand:SI 1 "arith_operand" "")))
6980 (gtu:SI (match_dup 4)
6981 (match_operand:SI 2 "arith_reg_operand" "")))
6983 (if_then_else (ne (reg:SI T_REG)
6985 (label_ref (match_operand 3 "" ""))
6990 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
6991 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
6992 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
6994 (define_insn "casesi_worker_0"
6995 [(set (match_operand:SI 0 "register_operand" "=r,r")
6996 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
6997 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
6998 (clobber (match_scratch:SI 3 "=X,1"))
6999 (clobber (match_scratch:SI 4 "=&z,z"))]
7004 [(set (match_operand:SI 0 "register_operand" "")
7005 (unspec:SI [(match_operand:SI 1 "register_operand" "")
7006 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7007 (clobber (match_scratch:SI 3 ""))
7008 (clobber (match_scratch:SI 4 ""))]
7009 "TARGET_SH1 && ! TARGET_SH2 && reload_completed"
7010 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
7011 (parallel [(set (match_dup 0)
7012 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
7013 (label_ref (match_dup 2))] UNSPEC_CASESI))
7014 (clobber (match_dup 3))])
7015 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
7016 "if (GET_CODE (operands[2]) == CODE_LABEL) LABEL_NUSES (operands[2])++;")
7019 [(set (match_operand:SI 0 "register_operand" "")
7020 (unspec:SI [(match_operand:SI 1 "register_operand" "")
7021 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7022 (clobber (match_scratch:SI 3 ""))
7023 (clobber (match_scratch:SI 4 ""))]
7024 "TARGET_SH2 && reload_completed"
7025 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
7026 (parallel [(set (match_dup 0)
7027 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
7028 (label_ref (match_dup 2))] UNSPEC_CASESI))
7029 (clobber (match_dup 3))])]
7030 "if (GET_CODE (operands[2]) == CODE_LABEL) LABEL_NUSES (operands[2])++;")
7032 (define_insn "*casesi_worker"
7033 [(set (match_operand:SI 0 "register_operand" "=r,r")
7034 (unspec:SI [(reg:SI R0_REG)
7035 (match_operand:SI 1 "register_operand" "0,r")
7036 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7037 (clobber (match_scratch:SI 3 "=X,1"))]
7041 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
7043 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
7046 switch (GET_MODE (diff_vec))
7049 return \"shll2 %1\;mov.l @(r0,%1),%0\";
7051 return \"add %1,%1\;mov.w @(r0,%1),%0\";
7053 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
7054 return \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
7055 return \"mov.b @(r0,%1),%0\";
7060 [(set_attr "length" "4")])
7062 (define_insn "casesi_shift_media"
7063 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7064 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
7065 (unspec:DI [(label_ref:DI (match_operand 2 "" ""))]
7070 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
7072 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
7075 switch (GET_MODE (diff_vec))
7078 return \"shlli %1, 2, %0\";
7080 return \"shlli %1, 1, %0\";
7082 if (rtx_equal_p (operands[0], operands[1]))
7084 return \"add %1, r63, %0\";
7089 [(set_attr "type" "arith_media")])
7091 (define_insn "casesi_load_media"
7092 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7093 (mem:DI (unspec [(match_operand 1 "arith_reg_operand" "r")
7094 (match_operand 2 "arith_reg_operand" "r")
7095 (label_ref:DI (match_operand 3 "" ""))] 2)))]
7099 rtx diff_vec = PATTERN (next_real_insn (operands[3]));
7101 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
7104 switch (GET_MODE (diff_vec))
7107 return \"ldx.l %1, %2, %0\";
7110 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
7111 return \"ldx.uw %1, %2, %0\";
7113 return \"ldx.w %1, %2, %0\";
7115 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
7116 return \"ldx.ub %1, %2, %0\";
7117 return \"ldx.b %1, %2, %0\";
7122 [(set_attr "type" "load_media")])
7124 (define_expand "return"
7126 "reload_completed && ! sh_need_epilogue ()"
7131 emit_jump_insn (gen_return_media ());
7135 if (TARGET_SHCOMPACT
7136 && (current_function_args_info.call_cookie & CALL_COOKIE_RET_TRAMP (1)))
7138 emit_jump_insn (gen_shcompact_return_tramp ());
7143 (define_insn "*return_i"
7145 "TARGET_SH1 && ! (TARGET_SHCOMPACT
7146 && (current_function_args_info.call_cookie
7147 & CALL_COOKIE_RET_TRAMP (1)))
7148 && reload_completed"
7150 [(set_attr "type" "return")
7151 (set_attr "needs_delay_slot" "yes")])
7153 (define_expand "shcompact_return_tramp"
7156 && (current_function_args_info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
7159 rtx reg = gen_rtx_REG (Pmode, R0_REG);
7160 rtx sym = gen_rtx_SYMBOL_REF (Pmode,
7161 \"__GCC_shcompact_return_trampoline\");
7164 emit_insn (gen_symGOTPLT2reg (reg, sym));
7166 emit_move_insn (reg, sym);
7168 emit_jump_insn (gen_shcompact_return_tramp_i ());
7172 (define_insn "shcompact_return_tramp_i"
7173 [(parallel [(return) (use (reg:SI R0_REG))])]
7175 && (current_function_args_info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
7177 [(set_attr "type" "jump_ind")
7178 (set_attr "needs_delay_slot" "yes")])
7180 (define_insn "return_media_i"
7181 [(parallel [(return) (use (match_operand:DI 0 "target_reg_operand" "k"))])]
7182 "TARGET_SHMEDIA && reload_completed"
7184 [(set_attr "type" "jump_media")])
7186 (define_expand "return_media"
7188 "TARGET_SHMEDIA && reload_completed"
7191 int tr_regno = sh_media_register_for_return ();
7196 rtx r18 = gen_rtx_REG (DImode, PR_MEDIA_REG);
7199 tr = gen_rtx_REG (DImode, tr_regno);
7200 emit_move_insn (tr, r18);
7203 tr = gen_rtx_REG (DImode, tr_regno);
7205 emit_jump_insn (gen_return_media_i (tr));
7209 (define_insn "shcompact_preserve_incoming_args"
7210 [(set (match_operand:SI 0 "register_operand" "+r")
7211 (unspec:SI [(match_dup 0)] UNSPEC_COMPACT_ARGS))]
7214 [(set_attr "length" "0")])
7216 (define_insn "shcompact_incoming_args"
7217 [(set (reg:SI R2_REG) (unspec:SI [(reg:SI R2_REG)] UNSPEC_COMPACT_ARGS))
7218 (set (reg:SI R3_REG) (unspec:SI [(reg:SI R3_REG)] UNSPEC_COMPACT_ARGS))
7219 (set (reg:SI R4_REG) (unspec:SI [(reg:SI R4_REG)] UNSPEC_COMPACT_ARGS))
7220 (set (reg:SI R5_REG) (unspec:SI [(reg:SI R5_REG)] UNSPEC_COMPACT_ARGS))
7221 (set (reg:SI R6_REG) (unspec:SI [(reg:SI R6_REG)] UNSPEC_COMPACT_ARGS))
7222 (set (reg:SI R7_REG) (unspec:SI [(reg:SI R7_REG)] UNSPEC_COMPACT_ARGS))
7223 (set (reg:SI R8_REG) (unspec:SI [(reg:SI R8_REG)] UNSPEC_COMPACT_ARGS))
7224 (set (reg:SI R9_REG) (unspec:SI [(reg:SI R9_REG)] UNSPEC_COMPACT_ARGS))
7225 (set (mem:BLK (reg:SI MACL_REG))
7226 (unspec:BLK [(reg:SI MACH_REG)] UNSPEC_COMPACT_ARGS))
7227 (use (reg:SI R0_REG))
7228 (clobber (reg:SI R0_REG))
7229 (clobber (reg:SI MACL_REG))
7230 (clobber (reg:SI MACH_REG))
7231 (clobber (reg:SI PR_REG))]
7234 [(set_attr "needs_delay_slot" "yes")])
7236 (define_insn "shmedia_save_restore_regs_compact"
7237 [(set (reg:SI SP_REG)
7238 (plus:SI (reg:SI SP_REG)
7239 (match_operand:SI 0 "immediate_operand" "i")))
7240 (use (reg:SI R0_REG))
7241 (clobber (reg:SI PR_REG))]
7243 && (INTVAL (operands[0]) == SHMEDIA_REGS_STACK_ADJUST ()
7244 || INTVAL (operands[0]) == - SHMEDIA_REGS_STACK_ADJUST ())"
7246 [(set_attr "needs_delay_slot" "yes")])
7248 (define_expand "prologue"
7251 "sh_expand_prologue (); DONE;")
7253 (define_expand "epilogue"
7258 sh_expand_epilogue ();
7259 emit_jump_insn (gen_return ());
7263 (define_insn "blockage"
7264 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7267 [(set_attr "length" "0")])
7269 ;; ------------------------------------------------------------------------
7271 ;; ------------------------------------------------------------------------
7274 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
7275 (eq:SI (reg:SI T_REG) (const_int 1)))]
7278 [(set_attr "type" "arith")])
7280 (define_expand "seq"
7281 [(set (match_operand:SI 0 "arith_reg_operand" "")
7288 if (GET_MODE (operands[0]) != DImode)
7289 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7290 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7291 if (sh_compare_op1 != const0_rtx)
7292 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7293 ? GET_MODE (sh_compare_op0)
7294 : GET_MODE (sh_compare_op1),
7297 switch (GET_MODE (sh_compare_op0))
7300 emit_insn (gen_cmpeqdi_media (operands[0],
7301 sh_compare_op0, sh_compare_op1));
7305 if (! TARGET_SHMEDIA_FPU)
7307 emit_insn (gen_cmpeqsf_media (operands[0],
7308 sh_compare_op0, sh_compare_op1));
7312 if (! TARGET_SHMEDIA_FPU)
7314 emit_insn (gen_cmpeqdf_media (operands[0],
7315 sh_compare_op0, sh_compare_op1));
7323 operands[1] = prepare_scc_operands (EQ);
7326 (define_expand "slt"
7327 [(set (match_operand:SI 0 "arith_reg_operand" "")
7334 if (GET_MODE (operands[0]) != DImode)
7335 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7336 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7337 if (sh_compare_op1 != const0_rtx)
7338 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7339 ? GET_MODE (sh_compare_op0)
7340 : GET_MODE (sh_compare_op1),
7343 switch (GET_MODE (sh_compare_op0))
7346 emit_insn (gen_cmpgtdi_media (operands[0],
7347 sh_compare_op1, sh_compare_op0));
7351 if (! TARGET_SHMEDIA_FPU)
7353 emit_insn (gen_cmpgtsf_media (operands[0],
7354 sh_compare_op1, sh_compare_op0));
7358 if (! TARGET_SHMEDIA_FPU)
7360 emit_insn (gen_cmpgtdf_media (operands[0],
7361 sh_compare_op1, sh_compare_op0));
7369 operands[1] = prepare_scc_operands (LT);
7372 (define_expand "sle"
7373 [(match_operand:SI 0 "arith_reg_operand" "")]
7377 rtx tmp = sh_compare_op0;
7381 if (GET_MODE (operands[0]) != DImode)
7382 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7383 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7384 if (sh_compare_op1 != const0_rtx)
7385 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7386 ? GET_MODE (sh_compare_op0)
7387 : GET_MODE (sh_compare_op1),
7390 switch (GET_MODE (sh_compare_op0))
7394 tmp = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
7396 emit_insn (gen_cmpgtdi_media (tmp,
7397 sh_compare_op0, sh_compare_op1));
7398 emit_insn (gen_cmpeqdi_media (operands[0], tmp, const0_rtx));
7403 if (! TARGET_SHMEDIA_FPU)
7405 emit_insn (gen_cmpgesf_media (operands[0],
7406 sh_compare_op1, sh_compare_op0));
7410 if (! TARGET_SHMEDIA_FPU)
7412 emit_insn (gen_cmpgedf_media (operands[0],
7413 sh_compare_op1, sh_compare_op0));
7422 sh_compare_op0 = sh_compare_op1;
7423 sh_compare_op1 = tmp;
7424 emit_insn (gen_sge (operands[0]));
7428 (define_expand "sgt"
7429 [(set (match_operand:SI 0 "arith_reg_operand" "")
7436 if (GET_MODE (operands[0]) != DImode)
7437 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7438 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7439 if (sh_compare_op1 != const0_rtx)
7440 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7441 ? GET_MODE (sh_compare_op0)
7442 : GET_MODE (sh_compare_op1),
7445 switch (GET_MODE (sh_compare_op0))
7448 emit_insn (gen_cmpgtdi_media (operands[0],
7449 sh_compare_op0, sh_compare_op1));
7453 if (! TARGET_SHMEDIA_FPU)
7455 emit_insn (gen_cmpgtsf_media (operands[0],
7456 sh_compare_op0, sh_compare_op1));
7460 if (! TARGET_SHMEDIA_FPU)
7462 emit_insn (gen_cmpgtdf_media (operands[0],
7463 sh_compare_op0, sh_compare_op1));
7471 operands[1] = prepare_scc_operands (GT);
7474 (define_expand "sge"
7475 [(set (match_operand:SI 0 "arith_reg_operand" "")
7482 if (GET_MODE (operands[0]) != DImode)
7483 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7484 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7485 if (sh_compare_op1 != const0_rtx)
7486 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7487 ? GET_MODE (sh_compare_op0)
7488 : GET_MODE (sh_compare_op1),
7491 switch (GET_MODE (sh_compare_op0))
7495 rtx tmp = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
7497 emit_insn (gen_cmpgtdi_media (tmp,
7498 sh_compare_op1, sh_compare_op0));
7499 emit_insn (gen_cmpeqdi_media (operands[0], tmp, const0_rtx));
7504 if (! TARGET_SHMEDIA_FPU)
7506 emit_insn (gen_cmpgesf_media (operands[0],
7507 sh_compare_op0, sh_compare_op1));
7511 if (! TARGET_SHMEDIA_FPU)
7513 emit_insn (gen_cmpgedf_media (operands[0],
7514 sh_compare_op0, sh_compare_op1));
7523 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
7527 rtx lab = gen_label_rtx ();
7528 prepare_scc_operands (EQ);
7529 emit_jump_insn (gen_branch_true (lab));
7530 prepare_scc_operands (GT);
7532 emit_insn (gen_movt (operands[0]));
7535 emit_insn (gen_movnegt (operands[0], prepare_scc_operands (LT)));
7538 operands[1] = prepare_scc_operands (GE);
7541 (define_expand "sgtu"
7542 [(set (match_operand:SI 0 "arith_reg_operand" "")
7549 if (GET_MODE (operands[0]) != DImode)
7550 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7551 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7552 if (sh_compare_op1 != const0_rtx)
7553 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7554 ? GET_MODE (sh_compare_op0)
7555 : GET_MODE (sh_compare_op1),
7558 emit_insn (gen_cmpgtudi_media (operands[0],
7559 sh_compare_op0, sh_compare_op1));
7562 operands[1] = prepare_scc_operands (GTU);
7565 (define_expand "sltu"
7566 [(set (match_operand:SI 0 "arith_reg_operand" "")
7573 if (GET_MODE (operands[0]) != DImode)
7574 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7575 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7576 if (sh_compare_op1 != const0_rtx)
7577 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7578 ? GET_MODE (sh_compare_op0)
7579 : GET_MODE (sh_compare_op1),
7582 emit_insn (gen_cmpgtudi_media (operands[0],
7583 sh_compare_op1, sh_compare_op0));
7586 operands[1] = prepare_scc_operands (LTU);
7589 (define_expand "sleu"
7590 [(set (match_operand:SI 0 "arith_reg_operand" "")
7599 if (GET_MODE (operands[0]) != DImode)
7600 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7601 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7602 if (sh_compare_op1 != const0_rtx)
7603 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7604 ? GET_MODE (sh_compare_op0)
7605 : GET_MODE (sh_compare_op1),
7608 tmp = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
7610 emit_insn (gen_cmpgtudi_media (tmp, sh_compare_op0, sh_compare_op1));
7611 emit_insn (gen_cmpeqdi_media (operands[0], tmp, const0_rtx));
7615 operands[1] = prepare_scc_operands (LEU);
7618 (define_expand "sgeu"
7619 [(set (match_operand:SI 0 "arith_reg_operand" "")
7628 if (GET_MODE (operands[0]) != DImode)
7629 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7630 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7631 if (sh_compare_op1 != const0_rtx)
7632 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7633 ? GET_MODE (sh_compare_op0)
7634 : GET_MODE (sh_compare_op1),
7637 tmp = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
7639 emit_insn (gen_cmpgtudi_media (tmp, sh_compare_op1, sh_compare_op0));
7640 emit_insn (gen_cmpeqdi_media (operands[0], tmp, const0_rtx));
7645 operands[1] = prepare_scc_operands (GEU);
7648 ;; sne moves the complement of the T reg to DEST like this:
7652 ;; This is better than xoring compare result with 1 because it does
7653 ;; not require r0 and further, the -1 may be CSE-ed or lifted out of a
7656 (define_expand "sne"
7657 [(set (match_dup 2) (const_int -1))
7658 (parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
7659 (neg:SI (plus:SI (match_dup 1)
7662 (ne:SI (ior:SI (match_dup 1) (match_dup 2))
7671 if (GET_MODE (operands[0]) != DImode)
7672 operands[0] = gen_rtx_SUBREG (DImode, operands[0], 0);
7674 if (! TARGET_SHMEDIA_FPU && GET_MODE (sh_compare_op0) != DImode)
7677 sh_compare_op0 = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7678 if (sh_compare_op1 != const0_rtx)
7679 sh_compare_op1 = force_reg (GET_MODE (sh_compare_op1) == VOIDmode
7680 ? GET_MODE (sh_compare_op0)
7681 : GET_MODE (sh_compare_op1),
7684 tmp = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
7686 emit_insn (gen_seq (tmp));
7687 emit_insn (gen_cmpeqdi_media (operands[0], tmp, const0_rtx));
7692 operands[1] = prepare_scc_operands (EQ);
7693 operands[2] = gen_reg_rtx (SImode);
7696 (define_expand "sunordered"
7697 [(set (match_operand:DI 0 "arith_reg_operand" "")
7698 (unordered:DI (match_dup 1) (match_dup 2)))]
7699 "TARGET_SHMEDIA_FPU"
7702 operands[1] = force_reg (GET_MODE (sh_compare_op0), sh_compare_op0);
7703 operands[2] = force_reg (GET_MODE (sh_compare_op1), sh_compare_op1);
7706 ;; Use the same trick for FP sle / sge
7707 (define_expand "movnegt"
7708 [(set (match_dup 2) (const_int -1))
7709 (parallel [(set (match_operand 0 "" "")
7710 (neg:SI (plus:SI (match_dup 1)
7713 (ne:SI (ior:SI (match_operand 1 "" "") (match_dup 2))
7716 "operands[2] = gen_reg_rtx (SImode);")
7718 ;; Recognize mov #-1/negc/neg sequence, and change it to movt/add #-1.
7719 ;; This prevents a regression that occurred when we switched from xor to
7723 [(set (match_operand:SI 0 "arith_reg_operand" "")
7724 (plus:SI (reg:SI T_REG)
7727 [(set (match_dup 0) (eq:SI (reg:SI T_REG) (const_int 1)))
7728 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
7731 ;; -------------------------------------------------------------------------
7732 ;; Instructions to cope with inline literal tables
7733 ;; -------------------------------------------------------------------------
7735 ; 2 byte integer in line
7737 (define_insn "consttable_2"
7738 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
7739 (match_operand 1 "" "")]
7744 if (operands[1] != const0_rtx)
7745 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
7748 [(set_attr "length" "2")
7749 (set_attr "in_delay_slot" "no")])
7751 ; 4 byte integer in line
7753 (define_insn "consttable_4"
7754 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
7755 (match_operand 1 "" "")]
7760 if (operands[1] != const0_rtx)
7761 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
7764 [(set_attr "length" "4")
7765 (set_attr "in_delay_slot" "no")])
7767 ; 8 byte integer in line
7769 (define_insn "consttable_8"
7770 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
7771 (match_operand 1 "" "")]
7776 if (operands[1] != const0_rtx)
7777 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
7780 [(set_attr "length" "8")
7781 (set_attr "in_delay_slot" "no")])
7783 ; 4 byte floating point
7785 (define_insn "consttable_sf"
7786 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
7787 (match_operand 1 "" "")]
7792 if (operands[1] != const0_rtx)
7795 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
7796 assemble_real (d, SFmode, GET_MODE_ALIGNMENT (SFmode));
7800 [(set_attr "length" "4")
7801 (set_attr "in_delay_slot" "no")])
7803 ; 8 byte floating point
7805 (define_insn "consttable_df"
7806 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
7807 (match_operand 1 "" "")]
7812 if (operands[1] != const0_rtx)
7815 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
7816 assemble_real (d, DFmode, GET_MODE_ALIGNMENT (DFmode));
7820 [(set_attr "length" "8")
7821 (set_attr "in_delay_slot" "no")])
7823 ;; Alignment is needed for some constant tables; it may also be added for
7824 ;; Instructions at the start of loops, or after unconditional branches.
7825 ;; ??? We would get more accurate lengths if we did instruction
7826 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
7827 ;; here is too conservative.
7829 ; align to a two byte boundary
7831 (define_expand "align_2"
7832 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
7836 ; align to a four byte boundary
7837 ;; align_4 and align_log are instructions for the starts of loops, or
7838 ;; after unconditional branches, which may take up extra room.
7840 (define_expand "align_4"
7841 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
7845 ; align to a cache line boundary
7847 (define_insn "align_log"
7848 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
7851 [(set_attr "length" "0")
7852 (set_attr "in_delay_slot" "no")])
7854 ; emitted at the end of the literal table, used to emit the
7855 ; 32bit branch labels if needed.
7857 (define_insn "consttable_end"
7858 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
7860 "* return output_jump_label_table ();"
7861 [(set_attr "in_delay_slot" "no")])
7863 ; emitted at the end of the window in the literal table.
7865 (define_insn "consttable_window_end"
7866 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
7869 [(set_attr "length" "0")
7870 (set_attr "in_delay_slot" "no")])
7872 ;; -------------------------------------------------------------------------
7874 ;; -------------------------------------------------------------------------
7876 ;; String/block move insn.
7878 (define_expand "movstrsi"
7879 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
7880 (mem:BLK (match_operand:BLK 1 "" "")))
7881 (use (match_operand:SI 2 "nonmemory_operand" ""))
7882 (use (match_operand:SI 3 "immediate_operand" ""))
7883 (clobber (reg:SI PR_REG))
7884 (clobber (reg:SI R4_REG))
7885 (clobber (reg:SI R5_REG))
7886 (clobber (reg:SI R0_REG))])]
7887 "TARGET_SH1 && ! TARGET_SH5"
7890 if(expand_block_move (operands))
7895 (define_insn "block_move_real"
7896 [(parallel [(set (mem:BLK (reg:SI R4_REG))
7897 (mem:BLK (reg:SI R5_REG)))
7898 (use (match_operand:SI 0 "arith_reg_operand" "r"))
7899 (clobber (reg:SI PR_REG))
7900 (clobber (reg:SI R0_REG))])]
7901 "TARGET_SH1 && ! TARGET_HARD_SH4"
7903 [(set_attr "type" "sfunc")
7904 (set_attr "needs_delay_slot" "yes")])
7906 (define_insn "block_lump_real"
7907 [(parallel [(set (mem:BLK (reg:SI R4_REG))
7908 (mem:BLK (reg:SI R5_REG)))
7909 (use (match_operand:SI 0 "arith_reg_operand" "r"))
7910 (use (reg:SI R6_REG))
7911 (clobber (reg:SI PR_REG))
7912 (clobber (reg:SI T_REG))
7913 (clobber (reg:SI R4_REG))
7914 (clobber (reg:SI R5_REG))
7915 (clobber (reg:SI R6_REG))
7916 (clobber (reg:SI R0_REG))])]
7917 "TARGET_SH1 && ! TARGET_HARD_SH4"
7919 [(set_attr "type" "sfunc")
7920 (set_attr "needs_delay_slot" "yes")])
7922 (define_insn "block_move_real_i4"
7923 [(parallel [(set (mem:BLK (reg:SI R4_REG))
7924 (mem:BLK (reg:SI R5_REG)))
7925 (use (match_operand:SI 0 "arith_reg_operand" "r"))
7926 (clobber (reg:SI PR_REG))
7927 (clobber (reg:SI R0_REG))
7928 (clobber (reg:SI R1_REG))
7929 (clobber (reg:SI R2_REG))])]
7932 [(set_attr "type" "sfunc")
7933 (set_attr "needs_delay_slot" "yes")])
7935 (define_insn "block_lump_real_i4"
7936 [(parallel [(set (mem:BLK (reg:SI R4_REG))
7937 (mem:BLK (reg:SI R5_REG)))
7938 (use (match_operand:SI 0 "arith_reg_operand" "r"))
7939 (use (reg:SI R6_REG))
7940 (clobber (reg:SI PR_REG))
7941 (clobber (reg:SI T_REG))
7942 (clobber (reg:SI R4_REG))
7943 (clobber (reg:SI R5_REG))
7944 (clobber (reg:SI R6_REG))
7945 (clobber (reg:SI R0_REG))
7946 (clobber (reg:SI R1_REG))
7947 (clobber (reg:SI R2_REG))
7948 (clobber (reg:SI R3_REG))])]
7951 [(set_attr "type" "sfunc")
7952 (set_attr "needs_delay_slot" "yes")])
7954 ;; -------------------------------------------------------------------------
7955 ;; Floating point instructions.
7956 ;; -------------------------------------------------------------------------
7958 ;; ??? All patterns should have a type attribute.
7960 (define_expand "fpu_switch0"
7961 [(set (match_operand:SI 0 "" "") (match_dup 2))
7962 (set (match_dup 1) (mem:PSI (match_dup 0)))]
7966 operands[1] = get_fpscr_rtx ();
7967 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
7969 operands[2] = legitimize_pic_address (operands[2], SImode,
7970 no_new_pseudos ? operands[0] : 0);
7973 (define_expand "fpu_switch1"
7974 [(set (match_operand:SI 0 "" "") (match_dup 2))
7975 (set (match_dup 3) (plus:SI (match_dup 0) (const_int 4)))
7976 (set (match_dup 1) (mem:PSI (match_dup 3)))]
7980 operands[1] = get_fpscr_rtx ();
7981 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
7983 operands[2] = legitimize_pic_address (operands[2], SImode,
7984 no_new_pseudos ? operands[0] : 0);
7985 operands[3] = no_new_pseudos ? operands[0] : gen_reg_rtx (SImode);
7988 (define_expand "movpsi"
7989 [(set (match_operand:PSI 0 "register_operand" "")
7990 (match_operand:PSI 1 "general_movsrc_operand" ""))]
7994 ;; The c / m alternative is a fake to guide reload to load directly into
7995 ;; fpscr, since reload doesn't know how to use post-increment.
7996 ;; GO_IF_LEGITIMATE_ADDRESS guards about bogus addresses before reload,
7997 ;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
7998 ;; predicate after reload.
7999 ;; The gp_fpul type for r/!c might look a bit odd, but it actually schedules
8000 ;; like a gpr <-> fpul move.
8001 (define_insn "fpu_switch"
8002 [(set (match_operand:PSI 0 "register_operand" "=c,c,r,c,c,r,m,r")
8003 (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c"))]
8005 && (! reload_completed
8006 || true_regnum (operands[0]) != FPSCR_REG
8007 || GET_CODE (operands[1]) != MEM
8008 || GET_CODE (XEXP (operands[1], 0)) != PLUS)"
8010 ! precision stays the same
8018 [(set_attr "length" "0,2,2,4,2,2,2,2")
8019 (set_attr "type" "dfp_conv,dfp_conv,load,dfp_conv,dfp_conv,move,store,gp_fpul")
8020 (set_attr "insn_class" "ldsmem_to_fpscr,*,*,lds_to_fpscr,*,*,*,*")])
8023 [(set (reg:PSI FPSCR_REG)
8024 (mem:PSI (match_operand:SI 0 "register_operand" "")))]
8025 "TARGET_SH4 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
8026 [(set (match_dup 0) (match_dup 0))]
8029 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
8030 gen_rtx (MEM, PSImode,
8031 gen_rtx (POST_INC, Pmode,
8033 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
8037 [(set (reg:PSI FPSCR_REG)
8038 (mem:PSI (match_operand:SI 0 "register_operand" "")))]
8040 [(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))]
8043 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
8044 gen_rtx (MEM, PSImode,
8045 gen_rtx (POST_INC, Pmode,
8047 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
8050 ;; ??? This uses the fp unit, but has no type indicating that.
8051 ;; If we did that, this would either give a bogus latency or introduce
8052 ;; a bogus FIFO constraint.
8053 ;; Since this insn is currently only used for prologues/epilogues,
8054 ;; it is probably best to claim no function unit, which matches the
8056 (define_insn "toggle_sz"
8057 [(set (reg:PSI FPSCR_REG)
8058 (xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
8062 (define_expand "addsf3"
8063 [(set (match_operand:SF 0 "arith_reg_operand" "")
8064 (plus:SF (match_operand:SF 1 "arith_reg_operand" "")
8065 (match_operand:SF 2 "arith_reg_operand" "")))]
8066 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
8071 expand_sf_binop (&gen_addsf3_i, operands);
8076 (define_insn "*addsf3_media"
8077 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8078 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
8079 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8080 "TARGET_SHMEDIA_FPU"
8082 [(set_attr "type" "fparith_media")])
8084 (define_insn_and_split "unary_sf_op"
8085 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
8090 (parallel [(not:BI (match_operand 3 "const_int_operand" "n"))]))
8091 (match_operator:SF 2 "unary_float_operator"
8092 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
8093 (parallel [(match_operand 4
8094 "const_int_operand" "n")]))]))
8095 (parallel [(not:BI (match_dup 3)) (match_dup 3)])))]
8096 "TARGET_SHMEDIA_FPU"
8098 "TARGET_SHMEDIA_FPU && reload_completed"
8099 [(set (match_dup 5) (match_dup 6))]
8102 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
8103 rtx op1 = gen_rtx_REG (SFmode,
8104 (true_regnum (operands[1])
8105 + (INTVAL (operands[4]) ^ endian)));
8107 operands[7] = gen_rtx_REG (SFmode,
8108 (true_regnum (operands[0])
8109 + (INTVAL (operands[3]) ^ endian)));
8110 operands[6] = gen_rtx (GET_CODE (operands[2]), SFmode, op1);
8112 [(set_attr "type" "fparith_media")])
8114 (define_insn_and_split "binary_sf_op"
8115 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
8120 (parallel [(not:BI (match_operand 4 "const_int_operand" "n"))]))
8121 (match_operator:SF 3 "binary_float_operator"
8122 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
8123 (parallel [(match_operand 5
8124 "const_int_operand" "n")]))
8125 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
8126 (parallel [(match_operand 6
8127 "const_int_operand" "n")]))]))
8128 (parallel [(not:BI (match_dup 4)) (match_dup 4)])))]
8129 "TARGET_SHMEDIA_FPU"
8131 "TARGET_SHMEDIA_FPU && reload_completed"
8132 [(set (match_dup 7) (match_dup 8))]
8135 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
8136 rtx op1 = gen_rtx_REG (SFmode,
8137 (true_regnum (operands[1])
8138 + (INTVAL (operands[5]) ^ endian)));
8139 rtx op2 = gen_rtx_REG (SFmode,
8140 (true_regnum (operands[2])
8141 + (INTVAL (operands[6]) ^ endian)));
8143 operands[7] = gen_rtx_REG (SFmode,
8144 (true_regnum (operands[0])
8145 + (INTVAL (operands[4]) ^ endian)));
8146 operands[8] = gen_rtx (GET_CODE (operands[3]), SFmode, op1, op2);
8148 [(set_attr "type" "fparith_media")])
8150 (define_insn "addsf3_i"
8151 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
8152 (plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
8153 (match_operand:SF 2 "arith_reg_operand" "f")))
8154 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8157 [(set_attr "type" "fp")
8158 (set_attr "fp_mode" "single")])
8160 (define_expand "subsf3"
8161 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
8162 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
8163 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
8164 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
8169 expand_sf_binop (&gen_subsf3_i, operands);
8174 (define_insn "*subsf3_media"
8175 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8176 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
8177 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8178 "TARGET_SHMEDIA_FPU"
8180 [(set_attr "type" "fparith_media")])
8182 (define_insn "subsf3_i"
8183 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8184 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
8185 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
8186 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8189 [(set_attr "type" "fp")
8190 (set_attr "fp_mode" "single")])
8192 ;; Unfortunately, the combiner is unable to cope with the USE of the FPSCR
8193 ;; register in feeding fp instructions. Thus, we cannot generate fmac for
8194 ;; mixed-precision SH4 targets. To allow it to be still generated for the
8195 ;; SH3E, we use a separate insn for SH3E mulsf3.
8197 (define_expand "mulsf3"
8198 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
8199 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
8200 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
8201 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
8205 expand_sf_binop (&gen_mulsf3_i4, operands);
8206 else if (TARGET_SH3E)
8207 emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
8208 if (! TARGET_SHMEDIA)
8212 (define_insn "*mulsf3_media"
8213 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8214 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
8215 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8216 "TARGET_SHMEDIA_FPU"
8218 [(set_attr "type" "fparith_media")])
8220 (define_insn "mulsf3_i4"
8221 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8222 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
8223 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
8224 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8227 [(set_attr "type" "fp")
8228 (set_attr "fp_mode" "single")])
8230 (define_insn "mulsf3_ie"
8231 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8232 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
8233 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8234 "TARGET_SH3E && ! TARGET_SH4"
8236 [(set_attr "type" "fp")])
8238 (define_insn "*mac_media"
8239 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8240 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
8241 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
8242 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
8243 "TARGET_SHMEDIA_FPU"
8245 [(set_attr "type" "fparith_media")])
8247 (define_insn "*macsf3"
8248 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8249 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
8250 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
8251 (match_operand:SF 3 "arith_reg_operand" "0")))
8252 (use (match_operand:PSI 4 "fpscr_operand" "c"))]
8253 "TARGET_SH3E && ! TARGET_SH4"
8255 [(set_attr "type" "fp")
8256 (set_attr "fp_mode" "single")])
8258 (define_expand "divsf3"
8259 [(set (match_operand:SF 0 "arith_reg_operand" "")
8260 (div:SF (match_operand:SF 1 "arith_reg_operand" "")
8261 (match_operand:SF 2 "arith_reg_operand" "")))]
8262 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
8267 expand_sf_binop (&gen_divsf3_i, operands);
8272 (define_insn "*divsf3_media"
8273 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8274 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
8275 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8276 "TARGET_SHMEDIA_FPU"
8278 [(set_attr "type" "fdiv_media")])
8280 (define_insn "divsf3_i"
8281 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
8282 (div:SF (match_operand:SF 1 "arith_reg_operand" "0")
8283 (match_operand:SF 2 "arith_reg_operand" "f")))
8284 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8287 [(set_attr "type" "fdiv")
8288 (set_attr "fp_mode" "single")])
8290 (define_insn "floatdisf2"
8291 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8292 (float:SF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
8293 "TARGET_SHMEDIA_FPU"
8295 [(set_attr "type" "fpconv_media")])
8297 (define_expand "floatsisf2"
8298 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
8299 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
8300 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
8305 emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
8310 (define_insn "*floatsisf2_media"
8311 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8312 (float:SF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
8313 "TARGET_SHMEDIA_FPU"
8315 [(set_attr "type" "fpconv_media")])
8317 (define_insn "floatsisf2_i4"
8318 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8319 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
8320 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8323 [(set_attr "type" "fp")
8324 (set_attr "fp_mode" "single")])
8326 (define_insn "*floatsisf2_ie"
8327 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8328 (float:SF (match_operand:SI 1 "fpul_operand" "y")))]
8329 "TARGET_SH3E && ! TARGET_SH4"
8331 [(set_attr "type" "fp")])
8333 (define_insn "fix_truncsfdi2"
8334 [(set (match_operand:DI 0 "fp_arith_reg_operand" "=f")
8335 (fix:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8336 "TARGET_SHMEDIA_FPU"
8338 [(set_attr "type" "fpconv_media")])
8340 (define_expand "fix_truncsfsi2"
8341 [(set (match_operand:SI 0 "fpul_operand" "=y")
8342 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8343 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
8348 emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
8353 (define_insn "*fix_truncsfsi2_media"
8354 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
8355 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8356 "TARGET_SHMEDIA_FPU"
8358 [(set_attr "type" "fpconv_media")])
8360 (define_insn "fix_truncsfsi2_i4"
8361 [(set (match_operand:SI 0 "fpul_operand" "=y")
8362 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
8363 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8366 [(set_attr "type" "fp")
8367 (set_attr "fp_mode" "single")])
8369 ;; ??? This pattern is used nowhere. fix_truncsfsi2 always expands to
8370 ;; fix_truncsfsi2_i4.
8371 ;; (define_insn "fix_truncsfsi2_i4_2"
8372 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
8373 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
8374 ;; (use (reg:PSI FPSCR_REG))
8375 ;; (clobber (reg:SI FPUL_REG))]
8378 ;; [(set_attr "length" "4")
8379 ;; (set_attr "fp_mode" "single")])
8382 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
8383 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
8384 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
8385 ;; (clobber (reg:SI FPUL_REG))]
8387 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
8388 ;; (use (match_dup 2))])
8389 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
8391 (define_insn "*fixsfsi"
8392 [(set (match_operand:SI 0 "fpul_operand" "=y")
8393 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8394 "TARGET_SH3E && ! TARGET_SH4"
8396 [(set_attr "type" "fp")])
8398 (define_insn "cmpgtsf_t"
8399 [(set (reg:SI T_REG)
8400 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
8401 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8402 "TARGET_SH3E && ! TARGET_SH4"
8404 [(set_attr "type" "fp")
8405 (set_attr "fp_mode" "single")])
8407 (define_insn "cmpeqsf_t"
8408 [(set (reg:SI T_REG)
8409 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
8410 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8411 "TARGET_SH3E && ! TARGET_SH4"
8413 [(set_attr "type" "fp")
8414 (set_attr "fp_mode" "single")])
8416 (define_insn "ieee_ccmpeqsf_t"
8417 [(set (reg:SI T_REG)
8418 (ior:SI (reg:SI T_REG)
8419 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
8420 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
8421 "TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
8422 "* return output_ieee_ccmpeq (insn, operands);"
8423 [(set_attr "length" "4")])
8426 (define_insn "cmpgtsf_t_i4"
8427 [(set (reg:SI T_REG)
8428 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
8429 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
8430 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8433 [(set_attr "type" "fp")
8434 (set_attr "fp_mode" "single")])
8436 (define_insn "cmpeqsf_t_i4"
8437 [(set (reg:SI T_REG)
8438 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
8439 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
8440 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8443 [(set_attr "type" "fp")
8444 (set_attr "fp_mode" "single")])
8446 (define_insn "*ieee_ccmpeqsf_t_4"
8447 [(set (reg:SI T_REG)
8448 (ior:SI (reg:SI T_REG)
8449 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
8450 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
8451 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8452 "TARGET_IEEE && TARGET_SH4"
8453 "* return output_ieee_ccmpeq (insn, operands);"
8454 [(set_attr "length" "4")
8455 (set_attr "fp_mode" "single")])
8457 (define_insn "cmpeqsf_media"
8458 [(set (match_operand:DI 0 "register_operand" "=r")
8459 (eq:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")
8460 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8461 "TARGET_SHMEDIA_FPU"
8462 "fcmpeq.s %1, %2, %0"
8463 [(set_attr "type" "fcmp_media")])
8465 (define_insn "cmpgtsf_media"
8466 [(set (match_operand:DI 0 "register_operand" "=r")
8467 (gt:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")
8468 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8469 "TARGET_SHMEDIA_FPU"
8470 "fcmpgt.s %1, %2, %0"
8471 [(set_attr "type" "fcmp_media")])
8473 (define_insn "cmpgesf_media"
8474 [(set (match_operand:DI 0 "register_operand" "=r")
8475 (ge:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")
8476 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8477 "TARGET_SHMEDIA_FPU"
8478 "fcmpge.s %1, %2, %0"
8479 [(set_attr "type" "fcmp_media")])
8481 (define_insn "cmpunsf_media"
8482 [(set (match_operand:DI 0 "register_operand" "=r")
8483 (unordered:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")
8484 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
8485 "TARGET_SHMEDIA_FPU"
8486 "fcmpun.s %1, %2, %0"
8487 [(set_attr "type" "fcmp_media")])
8489 (define_expand "cmpsf"
8490 [(set (reg:SI T_REG)
8491 (compare (match_operand:SF 0 "arith_operand" "")
8492 (match_operand:SF 1 "arith_operand" "")))]
8493 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
8496 sh_compare_op0 = operands[0];
8497 sh_compare_op1 = operands[1];
8501 (define_expand "negsf2"
8502 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
8503 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
8504 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
8509 expand_sf_unop (&gen_negsf2_i, operands);
8514 (define_insn "*negsf2_media"
8515 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8516 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8517 "TARGET_SHMEDIA_FPU"
8519 [(set_attr "type" "fmove_media")])
8521 (define_insn "negsf2_i"
8522 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8523 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
8524 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8527 [(set_attr "type" "fmove")
8528 (set_attr "fp_mode" "single")])
8530 (define_expand "sqrtsf2"
8531 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
8532 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
8533 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
8538 expand_sf_unop (&gen_sqrtsf2_i, operands);
8543 (define_insn "*sqrtsf2_media"
8544 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8545 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8546 "TARGET_SHMEDIA_FPU"
8548 [(set_attr "type" "fdiv_media")])
8550 (define_insn "sqrtsf2_i"
8551 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8552 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
8553 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8556 [(set_attr "type" "fdiv")
8557 (set_attr "fp_mode" "single")])
8559 (define_expand "abssf2"
8560 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
8561 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
8562 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
8567 expand_sf_unop (&gen_abssf2_i, operands);
8572 (define_insn "*abssf2_media"
8573 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8574 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8575 "TARGET_SHMEDIA_FPU"
8577 [(set_attr "type" "fmove_media")])
8579 (define_insn "abssf2_i"
8580 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
8581 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
8582 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8585 [(set_attr "type" "fmove")
8586 (set_attr "fp_mode" "single")])
8588 (define_expand "adddf3"
8589 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
8590 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
8591 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
8592 "TARGET_SH4 || TARGET_SHMEDIA_FPU"
8597 expand_df_binop (&gen_adddf3_i, operands);
8602 (define_insn "*adddf3_media"
8603 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8604 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
8605 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
8606 "TARGET_SHMEDIA_FPU"
8608 [(set_attr "type" "dfparith_media")])
8610 (define_insn "adddf3_i"
8611 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8612 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
8613 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
8614 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8617 [(set_attr "type" "dfp_arith")
8618 (set_attr "fp_mode" "double")])
8620 (define_expand "subdf3"
8621 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
8622 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
8623 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
8624 "TARGET_SH4 || TARGET_SHMEDIA_FPU"
8629 expand_df_binop (&gen_subdf3_i, operands);
8634 (define_insn "*subdf3_media"
8635 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8636 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
8637 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
8638 "TARGET_SHMEDIA_FPU"
8640 [(set_attr "type" "dfparith_media")])
8642 (define_insn "subdf3_i"
8643 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8644 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
8645 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
8646 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8649 [(set_attr "type" "dfp_arith")
8650 (set_attr "fp_mode" "double")])
8652 (define_expand "muldf3"
8653 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
8654 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
8655 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
8656 "TARGET_SH4 || TARGET_SHMEDIA_FPU"
8661 expand_df_binop (&gen_muldf3_i, operands);
8666 (define_insn "*muldf3_media"
8667 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8668 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
8669 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
8670 "TARGET_SHMEDIA_FPU"
8672 [(set_attr "type" "dfmul_media")])
8674 (define_insn "muldf3_i"
8675 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8676 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
8677 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
8678 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8681 [(set_attr "type" "dfp_arith")
8682 (set_attr "fp_mode" "double")])
8684 (define_expand "divdf3"
8685 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
8686 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
8687 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
8688 "TARGET_SH4 || TARGET_SHMEDIA_FPU"
8693 expand_df_binop (&gen_divdf3_i, operands);
8698 (define_insn "*divdf3_media"
8699 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8700 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
8701 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
8702 "TARGET_SHMEDIA_FPU"
8704 [(set_attr "type" "dfdiv_media")])
8706 (define_insn "divdf3_i"
8707 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8708 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
8709 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
8710 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
8713 [(set_attr "type" "dfdiv")
8714 (set_attr "fp_mode" "double")])
8716 (define_insn "floatdidf2"
8717 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8718 (float:DF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
8719 "TARGET_SHMEDIA_FPU"
8721 [(set_attr "type" "dfpconv_media")])
8723 (define_expand "floatsidf2"
8724 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
8725 (float:DF (match_operand:SI 1 "fpul_operand" "")))]
8726 "TARGET_SH4 || TARGET_SHMEDIA_FPU"
8731 emit_df_insn (gen_floatsidf2_i (operands[0], operands[1],
8737 (define_insn "*floatsidf2_media"
8738 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8739 (float:DF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
8740 "TARGET_SHMEDIA_FPU"
8742 [(set_attr "type" "dfpconv_media")])
8744 (define_insn "floatsidf2_i"
8745 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8746 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
8747 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8750 [(set_attr "type" "dfp_conv")
8751 (set_attr "fp_mode" "double")])
8753 (define_insn "fix_truncdfdi2"
8754 [(set (match_operand:DI 0 "fp_arith_reg_operand" "=f")
8755 (fix:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
8756 "TARGET_SHMEDIA_FPU"
8758 [(set_attr "type" "dfpconv_media")])
8760 (define_expand "fix_truncdfsi2"
8761 [(set (match_operand:SI 0 "fpul_operand" "")
8762 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
8763 "TARGET_SH4 || TARGET_SHMEDIA_FPU"
8768 emit_df_insn (gen_fix_truncdfsi2_i (operands[0], operands[1],
8774 (define_insn "*fix_truncdfsi2_media"
8775 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
8776 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
8777 "TARGET_SHMEDIA_FPU"
8779 [(set_attr "type" "dfpconv_media")])
8781 (define_insn "fix_truncdfsi2_i"
8782 [(set (match_operand:SI 0 "fpul_operand" "=y")
8783 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
8784 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8787 [(set_attr "type" "dfp_conv")
8788 (set_attr "fp_mode" "double")])
8790 ;; ??? This pattern is used nowhere. fix_truncdfsi2 always expands to
8791 ;; fix_truncdfsi2_i.
8792 ;; (define_insn "fix_truncdfsi2_i4"
8793 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
8794 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
8795 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
8796 ;; (clobber (reg:SI FPUL_REG))]
8799 ;; [(set_attr "length" "4")
8800 ;; (set_attr "fp_mode" "double")])
8803 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
8804 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
8805 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
8806 ;; (clobber (reg:SI FPUL_REG))]
8808 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
8809 ;; (use (match_dup 2))])
8810 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
8812 (define_insn "cmpgtdf_t"
8813 [(set (reg:SI T_REG)
8814 (gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
8815 (match_operand:DF 1 "arith_reg_operand" "f")))
8816 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8819 [(set_attr "type" "dfp_cmp")
8820 (set_attr "fp_mode" "double")])
8822 (define_insn "cmpeqdf_t"
8823 [(set (reg:SI T_REG)
8824 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
8825 (match_operand:DF 1 "arith_reg_operand" "f")))
8826 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8829 [(set_attr "type" "dfp_cmp")
8830 (set_attr "fp_mode" "double")])
8832 (define_insn "*ieee_ccmpeqdf_t"
8833 [(set (reg:SI T_REG)
8834 (ior:SI (reg:SI T_REG)
8835 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
8836 (match_operand:DF 1 "arith_reg_operand" "f"))))
8837 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8838 "TARGET_IEEE && TARGET_SH4"
8839 "* return output_ieee_ccmpeq (insn, operands);"
8840 [(set_attr "length" "4")
8841 (set_attr "fp_mode" "double")])
8843 (define_insn "cmpeqdf_media"
8844 [(set (match_operand:DI 0 "register_operand" "=r")
8845 (eq:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")
8846 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
8847 "TARGET_SHMEDIA_FPU"
8849 [(set_attr "type" "fcmp_media")])
8851 (define_insn "cmpgtdf_media"
8852 [(set (match_operand:DI 0 "register_operand" "=r")
8853 (gt:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")
8854 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
8855 "TARGET_SHMEDIA_FPU"
8857 [(set_attr "type" "fcmp_media")])
8859 (define_insn "cmpgedf_media"
8860 [(set (match_operand:DI 0 "register_operand" "=r")
8861 (ge:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")
8862 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
8863 "TARGET_SHMEDIA_FPU"
8865 [(set_attr "type" "fcmp_media")])
8867 (define_insn "cmpundf_media"
8868 [(set (match_operand:DI 0 "register_operand" "=r")
8869 (unordered:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")
8870 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
8871 "TARGET_SHMEDIA_FPU"
8873 [(set_attr "type" "fcmp_media")])
8875 (define_expand "cmpdf"
8876 [(set (reg:SI T_REG)
8877 (compare (match_operand:DF 0 "arith_operand" "")
8878 (match_operand:DF 1 "arith_operand" "")))]
8879 "TARGET_SH4 || TARGET_SHMEDIA_FPU"
8882 sh_compare_op0 = operands[0];
8883 sh_compare_op1 = operands[1];
8887 (define_expand "negdf2"
8888 [(set (match_operand:DF 0 "arith_reg_operand" "")
8889 (neg:DF (match_operand:DF 1 "arith_reg_operand" "")))]
8890 "TARGET_SH4 || TARGET_SHMEDIA_FPU"
8895 expand_df_unop (&gen_negdf2_i, operands);
8900 (define_insn "*negdf2_media"
8901 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8902 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
8903 "TARGET_SHMEDIA_FPU"
8905 [(set_attr "type" "fmove_media")])
8907 (define_insn "negdf2_i"
8908 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
8909 (neg:DF (match_operand:DF 1 "arith_reg_operand" "0")))
8910 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8913 [(set_attr "type" "fmove")
8914 (set_attr "fp_mode" "double")])
8916 (define_expand "sqrtdf2"
8917 [(set (match_operand:DF 0 "arith_reg_operand" "")
8918 (sqrt:DF (match_operand:DF 1 "arith_reg_operand" "")))]
8919 "TARGET_SH4 || TARGET_SHMEDIA_FPU"
8924 expand_df_unop (&gen_sqrtdf2_i, operands);
8929 (define_insn "*sqrtdf2_media"
8930 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8931 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
8932 "TARGET_SHMEDIA_FPU"
8934 [(set_attr "type" "dfdiv_media")])
8936 (define_insn "sqrtdf2_i"
8937 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
8938 (sqrt:DF (match_operand:DF 1 "arith_reg_operand" "0")))
8939 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8942 [(set_attr "type" "dfdiv")
8943 (set_attr "fp_mode" "double")])
8945 (define_expand "absdf2"
8946 [(set (match_operand:DF 0 "arith_reg_operand" "")
8947 (abs:DF (match_operand:DF 1 "arith_reg_operand" "")))]
8948 "TARGET_SH4 || TARGET_SHMEDIA_FPU"
8953 expand_df_unop (&gen_absdf2_i, operands);
8958 (define_insn "*absdf2_media"
8959 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8960 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
8961 "TARGET_SHMEDIA_FPU"
8963 [(set_attr "type" "fmove_media")])
8965 (define_insn "absdf2_i"
8966 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
8967 (abs:DF (match_operand:DF 1 "arith_reg_operand" "0")))
8968 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
8971 [(set_attr "type" "fmove")
8972 (set_attr "fp_mode" "double")])
8974 (define_expand "extendsfdf2"
8975 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
8976 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
8977 "TARGET_SH4 || TARGET_SHMEDIA_FPU"
8982 emit_df_insn (gen_extendsfdf2_i4 (operands[0], operands[1],
8988 (define_insn "*extendsfdf2_media"
8989 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8990 (float_extend:DF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
8991 "TARGET_SHMEDIA_FPU"
8993 [(set_attr "type" "dfpconv_media")])
8995 (define_insn "extendsfdf2_i4"
8996 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
8997 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
8998 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
9001 [(set_attr "type" "fp")
9002 (set_attr "fp_mode" "double")])
9004 (define_expand "truncdfsf2"
9005 [(set (match_operand:SF 0 "fpul_operand" "")
9006 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
9007 "TARGET_SH4 || TARGET_SHMEDIA_FPU"
9012 emit_df_insn (gen_truncdfsf2_i4 (operands[0], operands[1],
9018 (define_insn "*truncdfsf2_media"
9019 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9020 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
9021 "TARGET_SHMEDIA_FPU"
9023 [(set_attr "type" "dfpconv_media")])
9025 (define_insn "truncdfsf2_i4"
9026 [(set (match_operand:SF 0 "fpul_operand" "=y")
9027 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9028 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
9031 [(set_attr "type" "fp")
9032 (set_attr "fp_mode" "double")])
9034 ;; Bit field extract patterns. These give better code for packed bitfields,
9035 ;; because they allow auto-increment addresses to be generated.
9037 (define_expand "insv"
9038 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
9039 (match_operand:SI 1 "immediate_operand" "")
9040 (match_operand:SI 2 "immediate_operand" ""))
9041 (match_operand:SI 3 "general_operand" ""))]
9042 "TARGET_SH1 && ! TARGET_LITTLE_ENDIAN"
9045 rtx addr_target, orig_address, shift_reg, qi_val;
9046 HOST_WIDE_INT bitsize, size, v;
9047 rtx x = operands[3];
9049 /* ??? expmed doesn't care for non-register predicates. */
9050 if (! memory_operand (operands[0], VOIDmode)
9051 || ! immediate_operand (operands[1], VOIDmode)
9052 || ! immediate_operand (operands[2], VOIDmode)
9053 || ! general_operand (x, VOIDmode))
9055 /* If this isn't a 16 / 24 / 32 bit field, or if
9056 it doesn't start on a byte boundary, then fail. */
9057 bitsize = INTVAL (operands[1]);
9058 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0
9059 || (INTVAL (operands[2]) % 8) != 0)
9063 orig_address = XEXP (operands[0], 0);
9064 shift_reg = gen_reg_rtx (SImode);
9065 if (GET_CODE (x) == CONST_INT)
9068 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
9072 emit_insn (gen_movsi (shift_reg, operands[3]));
9073 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
9075 addr_target = copy_addr_to_reg (plus_constant (orig_address, size - 1));
9077 operands[0] = replace_equiv_address (operands[0], addr_target);
9078 emit_insn (gen_movqi (operands[0], qi_val));
9082 if (GET_CODE (x) == CONST_INT)
9084 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
9087 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
9088 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
9090 emit_insn (gen_addsi3 (addr_target, addr_target, GEN_INT (-1)));
9091 emit_insn (gen_movqi (operands[0], qi_val));
9097 ;; -------------------------------------------------------------------------
9099 ;; -------------------------------------------------------------------------
9101 ;; This matches cases where a stack pointer increment at the start of the
9102 ;; epilogue combines with a stack slot read loading the return value.
9105 [(set (match_operand:SI 0 "arith_reg_operand" "")
9106 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
9107 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
9108 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])"
9111 ;; See the comment on the dt combiner pattern above.
9114 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
9115 (plus:SI (match_dup 0)
9118 (eq:SI (match_dup 0)
9123 ;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn'
9124 ;; to `mov #k,r0; mov.l @(r0,r15),rn'. These sequences are generated by
9125 ;; reload when the constant is too large for a reg+offset address.
9127 ;; ??? We would get much better code if this was done in reload. This would
9128 ;; require modifying find_reloads_address to recognize that if the constant
9129 ;; is out-of-range for an immediate add, then we get better code by reloading
9130 ;; the constant into a register than by reloading the sum into a register,
9131 ;; since the former is one instruction shorter if the address does not need
9132 ;; to be offsettable. Unfortunately this does not work, because there is
9133 ;; only one register, r0, that can be used as an index register. This register
9134 ;; is also the function return value register. So, if we try to force reload
9135 ;; to use double-reg addresses, then we end up with some instructions that
9136 ;; need to use r0 twice. The only way to fix this is to change the calling
9137 ;; convention so that r0 is not used to return values.
9140 [(set (match_operand:SI 0 "register_operand" "=r")
9141 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9142 (set (mem:SI (match_dup 0))
9143 (match_operand:SI 2 "general_movsrc_operand" ""))]
9144 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
9145 "mov.l %2,@(%0,%1)")
9148 [(set (match_operand:SI 0 "register_operand" "=r")
9149 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9150 (set (match_operand:SI 2 "general_movdst_operand" "")
9151 (mem:SI (match_dup 0)))]
9152 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
9153 "mov.l @(%0,%1),%2")
9156 [(set (match_operand:SI 0 "register_operand" "=r")
9157 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9158 (set (mem:HI (match_dup 0))
9159 (match_operand:HI 2 "general_movsrc_operand" ""))]
9160 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
9161 "mov.w %2,@(%0,%1)")
9164 [(set (match_operand:SI 0 "register_operand" "=r")
9165 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9166 (set (match_operand:HI 2 "general_movdst_operand" "")
9167 (mem:HI (match_dup 0)))]
9168 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
9169 "mov.w @(%0,%1),%2")
9172 [(set (match_operand:SI 0 "register_operand" "=r")
9173 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9174 (set (mem:QI (match_dup 0))
9175 (match_operand:QI 2 "general_movsrc_operand" ""))]
9176 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
9177 "mov.b %2,@(%0,%1)")
9180 [(set (match_operand:SI 0 "register_operand" "=r")
9181 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9182 (set (match_operand:QI 2 "general_movdst_operand" "")
9183 (mem:QI (match_dup 0)))]
9184 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
9185 "mov.b @(%0,%1),%2")
9188 [(set (match_operand:SI 0 "register_operand" "=r")
9189 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9190 (set (mem:SF (match_dup 0))
9191 (match_operand:SF 2 "general_movsrc_operand" ""))]
9192 "TARGET_SH1 && REGNO (operands[0]) == 0
9193 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
9194 || (GET_CODE (operands[2]) == SUBREG
9195 && REGNO (SUBREG_REG (operands[2])) < 16))
9196 && reg_unused_after (operands[0], insn)"
9197 "mov.l %2,@(%0,%1)")
9200 [(set (match_operand:SI 0 "register_operand" "=r")
9201 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9202 (set (match_operand:SF 2 "general_movdst_operand" "")
9204 (mem:SF (match_dup 0)))]
9205 "TARGET_SH1 && REGNO (operands[0]) == 0
9206 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
9207 || (GET_CODE (operands[2]) == SUBREG
9208 && REGNO (SUBREG_REG (operands[2])) < 16))
9209 && reg_unused_after (operands[0], insn)"
9210 "mov.l @(%0,%1),%2")
9213 [(set (match_operand:SI 0 "register_operand" "=r")
9214 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9215 (set (mem:SF (match_dup 0))
9216 (match_operand:SF 2 "general_movsrc_operand" ""))]
9217 "TARGET_SH3E && REGNO (operands[0]) == 0
9218 && ((GET_CODE (operands[2]) == REG
9219 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
9220 || (GET_CODE (operands[2]) == SUBREG
9221 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
9222 && reg_unused_after (operands[0], insn)"
9223 "fmov{.s|} %2,@(%0,%1)")
9226 [(set (match_operand:SI 0 "register_operand" "=r")
9227 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
9228 (set (match_operand:SF 2 "general_movdst_operand" "")
9230 (mem:SF (match_dup 0)))]
9231 "TARGET_SH3E && REGNO (operands[0]) == 0
9232 && ((GET_CODE (operands[2]) == REG
9233 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
9234 || (GET_CODE (operands[2]) == SUBREG
9235 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
9236 && reg_unused_after (operands[0], insn)"
9237 "fmov{.s|} @(%0,%1),%2")
9239 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF). */
9240 (define_insn "sp_switch_1"
9247 xoperands[0] = sp_switch;
9248 output_asm_insn (\"mov.l r0,@-r15\;mov.l %0,r0\", xoperands);
9249 output_asm_insn (\"mov.l @r0,r0\;mov.l r15,@-r0\", xoperands);
9250 return \"mov r0,r15\";
9252 [(set_attr "length" "10")])
9254 ;; Switch back to the original stack for interrupt functions with the
9255 ;; sp_switch attribute. */
9256 (define_insn "sp_switch_2"
9259 "mov.l @r15+,r15\;mov.l @r15+,r0"
9260 [(set_attr "length" "4")])
9262 ;; Integer vector moves
9264 (define_expand "movv8qi"
9265 [(set (match_operand:V8QI 0 "general_movdst_operand" "")
9266 (match_operand:V8QI 1 "general_movsrc_operand" ""))]
9268 "{ if (prepare_move_operands (operands, V8QImode)) DONE; }")
9270 (define_insn "movv8qi_i"
9271 [(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m")
9272 (match_operand:V8QI 1 "general_movsrc_operand" "r,JSU,nW,m,rl"))]
9274 && (register_operand (operands[0], V8QImode)
9275 || register_operand (operands[1], V8QImode))"
9282 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
9283 (set_attr "length" "4,4,16,4,4")])
9286 [(set (match_operand:V8QI 0 "arith_reg_dest" "")
9287 (subreg:V8QI (const_int 0) 0))]
9290 (const_vector:V8QI [(const_int 0) (const_int 0) (const_int 0)
9291 (const_int 0) (const_int 0) (const_int 0)
9292 (const_int 0) (const_int 0)]))])
9295 [(set (match_operand 0 "arith_reg_dest" "")
9296 (match_operand 1 "sh_rep_vec" ""))]
9297 "TARGET_SHMEDIA && reload_completed
9298 && GET_MODE (operands[0]) == GET_MODE (operands[1])
9299 && VECTOR_MODE_SUPPORTED_P (GET_MODE (operands[0]))
9300 && GET_MODE_SIZE (GET_MODE (operands[0])) == 8
9301 && (XVECEXP (operands[1], 0, 0) != const0_rtx
9302 || XVECEXP (operands[1], 0, 1) != const0_rtx)"
9303 [(set (match_dup 0) (match_dup 1))
9307 int unit_size = GET_MODE_UNIT_SIZE (GET_MODE (operands[1]));
9308 rtx elt1 = XVECEXP (operands[1], 0, 1);
9311 operands[2] = gen_mshflo_l (operands[0], operands[0], operands[0]);
9313 operands[2] = gen_mperm_w0 (operands[0], operands[0]);
9314 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
9315 operands[1] = XVECEXP (operands[1], 0, 0);
9318 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (elt1) == CONST_INT)
9319 operands[1] = GEN_INT (TARGET_LITTLE_ENDIAN
9320 ? INTVAL (operands[1]) + (INTVAL (elt1) << 8)
9321 : (INTVAL (operands[1]) << 8) + INTVAL (elt1));
9324 operands[0] = gen_rtx_REG (V2QImode, true_regnum (operands[0]));
9326 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, operands[1], elt1));
9332 [(set (match_operand 0 "arith_reg_dest" "")
9333 (match_operand 1 "sh_const_vec" ""))]
9334 "TARGET_SHMEDIA && reload_completed
9335 && GET_MODE (operands[0]) == GET_MODE (operands[1])
9336 && VECTOR_MODE_SUPPORTED_P (GET_MODE (operands[0]))
9337 && operands[1] != CONST0_RTX (GET_MODE (operands[1]))"
9338 [(set (match_dup 0) (match_dup 1))]
9341 rtx v = operands[1];
9342 enum machine_mode new_mode
9343 = mode_for_size (GET_MODE_BITSIZE (GET_MODE (v)), MODE_INT, 0);
9345 operands[0] = gen_rtx_REG (new_mode, true_regnum (operands[0]));
9347 = simplify_subreg (new_mode, operands[1], GET_MODE (operands[1]), 0);
9350 (define_expand "movv2hi"
9351 [(set (match_operand:V2HI 0 "general_movdst_operand" "")
9352 (match_operand:V2HI 1 "general_movsrc_operand" ""))]
9354 "{ if (prepare_move_operands (operands, V2HImode)) DONE; }")
9356 (define_insn "movv2hi_i"
9357 [(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m")
9358 (match_operand:V2HI 1 "general_movsrc_operand" "r,JSU,nW,m,rl"))]
9360 && (register_operand (operands[0], V2HImode)
9361 || register_operand (operands[1], V2HImode))"
9368 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
9369 (set_attr "length" "4,4,16,4,4")])
9371 (define_expand "movv4hi"
9372 [(set (match_operand:V4HI 0 "general_movdst_operand" "")
9373 (match_operand:V4HI 1 "general_movsrc_operand" ""))]
9375 "{ if (prepare_move_operands (operands, V4HImode)) DONE; }")
9377 (define_insn "movv4hi_i"
9378 [(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m")
9379 (match_operand:V4HI 1 "general_movsrc_operand" "r,JSU,nW,m,rl"))]
9381 && (register_operand (operands[0], V4HImode)
9382 || register_operand (operands[1], V4HImode))"
9389 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
9390 (set_attr "length" "4,4,16,4,4")])
9392 (define_expand "movv2si"
9393 [(set (match_operand:V2SI 0 "general_movdst_operand" "")
9394 (match_operand:V2SI 1 "general_movsrc_operand" ""))]
9396 "{ if (prepare_move_operands (operands, V2SImode)) DONE; }")
9398 (define_insn "movv2si_i"
9399 [(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m")
9400 (match_operand:V2SI 1 "general_movsrc_operand" "r,JSU,nW,m,rl"))]
9402 && (register_operand (operands[0], V2SImode)
9403 || register_operand (operands[1], V2SImode))"
9410 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
9411 (set_attr "length" "4,4,16,4,4")])
9413 ;; Multimedia Intrinsics
9415 (define_insn "absv2si2"
9416 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9417 (abs:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")))]
9420 [(set_attr "type" "mcmp_media")])
9422 (define_insn "absv4hi2"
9423 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9424 (abs:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")))]
9427 [(set_attr "type" "mcmp_media")])
9429 (define_insn "addv2si3"
9430 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9431 (plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
9432 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
9435 [(set_attr "type" "arith_media")])
9437 (define_insn "addv4hi3"
9438 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9439 (plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
9440 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
9443 [(set_attr "type" "arith_media")])
9445 (define_insn "ssaddv2si3"
9446 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9447 (ss_plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
9448 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
9450 "madds.l %1, %2, %0"
9451 [(set_attr "type" "mcmp_media")])
9453 (define_insn "usaddv8qi3"
9454 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
9455 (us_plus:V8QI (match_operand:V8QI 1 "arith_reg_operand" "%r")
9456 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
9458 "madds.ub %1, %2, %0"
9459 [(set_attr "type" "mcmp_media")])
9461 (define_insn "ssaddv4hi3"
9462 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9463 (ss_plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
9464 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
9466 "madds.w %1, %2, %0"
9467 [(set_attr "type" "mcmp_media")])
9469 (define_insn "negcmpeqv8qi"
9470 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
9471 (neg:V8QI (eq:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rU")
9472 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rU"))))]
9474 "mcmpeq.b %N1, %N2, %0"
9475 [(set_attr "type" "mcmp_media")])
9477 (define_insn "negcmpeqv2si"
9478 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9479 (neg:V2SI (eq:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rU")
9480 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU"))))]
9482 "mcmpeq.l %N1, %N2, %0"
9483 [(set_attr "type" "mcmp_media")])
9485 (define_insn "negcmpeqv4hi"
9486 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9487 (neg:V4HI (eq:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rU")
9488 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))))]
9490 "mcmpeq.w %N1, %N2, %0"
9491 [(set_attr "type" "mcmp_media")])
9493 (define_insn "negcmpgtuv8qi"
9494 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
9495 (neg:V8QI (gtu:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rU")
9496 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rU"))))]
9498 "mcmpgt.ub %N1, %N2, %0"
9499 [(set_attr "type" "mcmp_media")])
9501 (define_insn "negcmpgtv2si"
9502 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9503 (neg:V2SI (gt:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rU")
9504 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU"))))]
9506 "mcmpgt.l %N1, %N2, %0"
9507 [(set_attr "type" "mcmp_media")])
9509 (define_insn "negcmpgtv4hi"
9510 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9511 (neg:V4HI (gt:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rU")
9512 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))))]
9514 "mcmpgt.w %N1, %N2, %0"
9515 [(set_attr "type" "mcmp_media")])
9518 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
9519 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
9520 (match_operand:DI 2 "arith_reg_operand" "r"))
9521 (and:DI (match_operand:DI 3 "arith_reg_operand" "0")
9522 (not:DI (match_dup 2)))))]
9525 [(set_attr "type" "arith_media")])
9527 (define_insn "mcnvs_lw"
9528 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9530 (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU"))
9531 (ss_truncate:V2HI (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU"))))]
9533 "mcnvs.lw %N1, %N2, %0"
9534 [(set_attr "type" "mcmp_media")])
9536 (define_insn "mcnvs_wb"
9537 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
9539 (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU"))
9540 (ss_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))))]
9542 "mcnvs.wb %N1, %N2, %0"
9543 [(set_attr "type" "mcmp_media")])
9545 (define_insn "mcnvs_wub"
9546 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
9548 (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU"))
9549 (us_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))))]
9551 "mcnvs.wub %N1, %N2, %0"
9552 [(set_attr "type" "mcmp_media")])
9554 (define_insn "mextr_rl"
9555 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
9556 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
9557 (match_operand:HI 3 "mextr_bit_offset" "i"))
9558 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU")
9559 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
9560 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
9563 static char templ[16];
9565 sprintf (templ, \"mextr%d\\t%%N1, %%N2, %%0\",
9566 (int) INTVAL (operands[3]) >> 3);
9569 [(set_attr "type" "arith_media")])
9571 (define_insn "*mextr_lr"
9572 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
9573 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
9574 (match_operand:HI 3 "mextr_bit_offset" "i"))
9575 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU")
9576 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
9577 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
9580 static char templ[16];
9582 sprintf (templ, \"mextr%d\\t%%N2, %%N1, %%0\",
9583 (int) INTVAL (operands[4]) >> 3);
9586 [(set_attr "type" "arith_media")])
9588 ; mextrN can be modelled with vec_select / vec_concat, but the selection
9589 ; vector then varies depending on endianness.
9590 (define_expand "mextr1"
9591 [(match_operand:DI 0 "arith_reg_dest" "")
9592 (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
9593 (match_operand:DI 2 "arith_reg_or_0_operand" "rU")]
9597 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
9598 GEN_INT (1 * 8), GEN_INT (7 * 8)));
9602 (define_expand "mextr2"
9603 [(match_operand:DI 0 "arith_reg_dest" "")
9604 (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
9605 (match_operand:DI 2 "arith_reg_or_0_operand" "rU")]
9609 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
9610 GEN_INT (2 * 8), GEN_INT (6 * 8)));
9614 (define_expand "mextr3"
9615 [(match_operand:DI 0 "arith_reg_dest" "")
9616 (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
9617 (match_operand:DI 2 "arith_reg_or_0_operand" "rU")]
9621 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
9622 GEN_INT (3 * 8), GEN_INT (5 * 8)));
9626 (define_expand "mextr4"
9627 [(match_operand:DI 0 "arith_reg_dest" "")
9628 (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
9629 (match_operand:DI 2 "arith_reg_or_0_operand" "rU")]
9633 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
9634 GEN_INT (4 * 8), GEN_INT (4 * 8)));
9638 (define_expand "mextr5"
9639 [(match_operand:DI 0 "arith_reg_dest" "")
9640 (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
9641 (match_operand:DI 2 "arith_reg_or_0_operand" "rU")]
9645 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
9646 GEN_INT (5 * 8), GEN_INT (3 * 8)));
9650 (define_expand "mextr6"
9651 [(match_operand:DI 0 "arith_reg_dest" "")
9652 (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
9653 (match_operand:DI 2 "arith_reg_or_0_operand" "rU")]
9657 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
9658 GEN_INT (6 * 8), GEN_INT (2 * 8)));
9662 (define_expand "mextr7"
9663 [(match_operand:DI 0 "arith_reg_dest" "")
9664 (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
9665 (match_operand:DI 2 "arith_reg_or_0_operand" "rU")]
9669 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
9670 GEN_INT (7 * 8), GEN_INT (1 * 8)));
9674 (define_expand "mmacfx_wl"
9675 [(match_operand:V2SI 0 "arith_reg_dest" "")
9676 (match_operand:V2HI 1 "extend_reg_operand" "")
9677 (match_operand:V2HI 2 "extend_reg_operand" "")
9678 (match_operand:V2SI 3 "arith_reg_operand" "")]
9682 emit_insn (gen_mmacfx_wl_i (operands[0], operands[3],
9683 operands[1], operands[2]));
9687 (define_insn "mmacfx_wl_i"
9688 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9690 (match_operand:V2SI 1 "arith_reg_operand" "0")
9695 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
9696 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
9699 "mmacfx.wl %2, %3, %0"
9700 [(set_attr "type" "mac_media")])
9702 (define_expand "mmacnfx_wl"
9703 [(match_operand:V2SI 0 "arith_reg_dest" "")
9704 (match_operand:V2HI 1 "extend_reg_operand" "")
9705 (match_operand:V2HI 2 "extend_reg_operand" "")
9706 (match_operand:V2SI 3 "arith_reg_operand" "")]
9710 emit_insn (gen_mmacnfx_wl_i (operands[0], operands[3],
9711 operands[1], operands[2]));
9715 (define_insn "mmacnfx_wl_i"
9716 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9718 (match_operand:V2SI 1 "arith_reg_operand" "0")
9723 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
9724 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
9727 "mmacnfx.wl %2, %3, %0"
9728 [(set_attr "type" "mac_media")])
9730 (define_insn "mulv2si3"
9731 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9732 (mult:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
9733 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
9736 [(set_attr "type" "d2mpy_media")])
9738 (define_insn "mulv4hi3"
9739 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9740 (mult:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
9741 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
9744 [(set_attr "type" "dmpy_media")])
9746 (define_insn "mmulfx_l"
9747 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9751 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
9752 (sign_extend:V2DI (match_operand:V2SI 2 "arith_reg_operand" "r")))
9755 "mmulfx.l %1, %2, %0"
9756 [(set_attr "type" "d2mpy_media")])
9758 (define_insn "mmulfx_w"
9759 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9763 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
9764 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
9767 "mmulfx.w %1, %2, %0"
9768 [(set_attr "type" "dmpy_media")])
9770 (define_insn "mmulfxrp_w"
9771 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9776 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
9777 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
9781 "mmulfxrp.w %1, %2, %0"
9782 [(set_attr "type" "dmpy_media")])
9784 (define_expand "mmulhi_wl"
9785 [(match_operand:V2SI 0 "arith_reg_dest" "")
9786 (match_operand:V4HI 1 "arith_reg_operand" "")
9787 (match_operand:V4HI 2 "arith_reg_operand" "")]
9791 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul23_wl : gen_mmul01_wl)
9792 (operands[0], operands[1], operands[2]));
9796 (define_expand "mmullo_wl"
9797 [(match_operand:V2SI 0 "arith_reg_dest" "")
9798 (match_operand:V4HI 1 "arith_reg_operand" "")
9799 (match_operand:V4HI 2 "arith_reg_operand" "")]
9803 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul01_wl : gen_mmul23_wl)
9804 (operands[0], operands[1], operands[2]));
9808 (define_insn "mmul23_wl"
9809 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9812 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
9813 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
9814 (parallel [(const_int 2) (const_int 3)])))]
9816 "* return (TARGET_LITTLE_ENDIAN
9817 ? \"mmulhi.wl %1, %2, %0\"
9818 : \"mmullo.wl %1, %2, %0\");"
9819 [(set_attr "type" "dmpy_media")])
9821 (define_insn "mmul01_wl"
9822 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9825 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
9826 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
9827 (parallel [(const_int 0) (const_int 1)])))]
9829 "* return (TARGET_LITTLE_ENDIAN
9830 ? \"mmullo.wl %1, %2, %0\"
9831 : \"mmulhi.wl %1, %2, %0\");"
9832 [(set_attr "type" "dmpy_media")])
9834 (define_expand "mmulsum_wq"
9835 [(match_operand:DI 0 "arith_reg_dest" "")
9836 (match_operand:V4HI 1 "arith_reg_operand" "")
9837 (match_operand:V4HI 2 "arith_reg_operand" "")
9838 (match_operand:DI 3 "arith_reg_operand" "")]
9842 emit_insn (gen_mmulsum_wq_i (operands[0], operands[3],
9843 operands[1], operands[2]));
9847 (define_insn "mmulsum_wq_i"
9848 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
9849 (plus:DI (match_operand:DI 1 "arith_reg_operand" "0")
9854 (sign_extend:V4DI (match_operand:V4HI 2 "arith_reg_operand" "r"))
9855 (sign_extend:V4DI (match_operand:V4HI 3 "arith_reg_operand" "r")))
9856 (parallel [(const_int 0)]))
9857 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
9858 (sign_extend:V4DI (match_dup 3)))
9859 (parallel [(const_int 1)])))
9861 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
9862 (sign_extend:V4DI (match_dup 3)))
9863 (parallel [(const_int 2)]))
9864 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
9865 (sign_extend:V4DI (match_dup 3)))
9866 (parallel [(const_int 3)]))))))]
9868 "mmulsum.wq %2, %3, %0"
9869 [(set_attr "type" "mac_media")])
9871 (define_expand "mperm_w"
9872 [(match_operand:V4HI 0 "arith_reg_dest" "=r")
9873 (match_operand:V4HI 1 "arith_reg_operand" "r")
9874 (match_operand:QI 2 "extend_reg_or_0_operand" "rU")]
9878 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mperm_w_little : gen_mperm_w_big)
9879 (operands[0], operands[1], operands[2]));
9882 ; This use of vec_select isn't exactly correct according to rtl.texi
9883 ; (because not constant), but it seems a straightforward extension.
9884 (define_insn "mperm_w_little"
9885 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9887 (match_operand:V4HI 1 "arith_reg_operand" "r")
9889 [(zero_extract (match_operand:QI 2 "extend_reg_or_0_operand" "rU")
9890 (const_int 2) (const_int 0))
9891 (zero_extract (match_dup 2) (const_int 2) (const_int 2))
9892 (zero_extract (match_dup 2) (const_int 2) (const_int 4))
9893 (zero_extract (match_dup 2) (const_int 2) (const_int 6))])))]
9894 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
9895 "mperm.w %1, %N2, %0"
9896 [(set_attr "type" "arith_media")])
9898 (define_insn "mperm_w_big"
9899 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9901 (match_operand:V4HI 1 "arith_reg_operand" "r")
9903 [(zero_extract (not:QI (match_operand:QI 2
9904 "extend_reg_or_0_operand" "rU"))
9905 (const_int 2) (const_int 0))
9906 (zero_extract (not:QI (match_dup 2)) (const_int 2) (const_int 2))
9907 (zero_extract (not:QI (match_dup 2)) (const_int 2) (const_int 4))
9908 (zero_extract (not:QI (match_dup 2)) (const_int 2) (const_int 6))])))]
9909 "TARGET_SHMEDIA && ! TARGET_LITTLE_ENDIAN"
9910 "mperm.w %1, %N2, %0"
9911 [(set_attr "type" "arith_media")])
9913 (define_insn "mperm_w0"
9914 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9915 (vec_duplicate:V4HI (truncate:HI (match_operand 1
9916 "trunc_hi_operand" "r"))))]
9918 "mperm.w %1, r63, %0"
9919 [(set_attr "type" "arith_media")])
9921 (define_expand "msad_ubq"
9922 [(match_operand:DI 0 "arith_reg_dest" "")
9923 (match_operand:V8QI 1 "arith_reg_or_0_operand" "")
9924 (match_operand:V8QI 2 "arith_reg_or_0_operand" "")
9925 (match_operand:DI 3 "arith_reg_operand" "")]
9929 emit_insn (gen_msad_ubq_i (operands[0], operands[3],
9930 operands[1], operands[2]));
9934 (define_insn "msad_ubq_i"
9935 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
9940 (match_operand:DI 1 "arith_reg_operand" "0")
9941 (abs:DI (vec_select:DI
9944 (match_operand:V8QI 2 "arith_reg_or_0_operand" "r"))
9946 (match_operand:V8QI 3 "arith_reg_or_0_operand" "r")))
9947 (parallel [(const_int 0)]))))
9948 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
9949 (zero_extend:V8DI (match_dup 3)))
9950 (parallel [(const_int 1)]))))
9952 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
9953 (zero_extend:V8DI (match_dup 3)))
9954 (parallel [(const_int 2)])))
9955 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
9956 (zero_extend:V8DI (match_dup 3)))
9957 (parallel [(const_int 3)])))))
9960 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
9961 (zero_extend:V8DI (match_dup 3)))
9962 (parallel [(const_int 4)])))
9963 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
9964 (zero_extend:V8DI (match_dup 3)))
9965 (parallel [(const_int 5)]))))
9967 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
9968 (zero_extend:V8DI (match_dup 3)))
9969 (parallel [(const_int 6)])))
9970 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
9971 (zero_extend:V8DI (match_dup 3)))
9972 (parallel [(const_int 7)])))))))]
9974 "msad.ubq %N2, %N3, %0"
9975 [(set_attr "type" "mac_media")])
9977 (define_insn "mshalds_l"
9978 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
9981 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
9982 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
9985 "mshalds.l %1, %2, %0"
9986 [(set_attr "type" "mcmp_media")])
9988 (define_insn "mshalds_w"
9989 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
9992 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
9993 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
9996 "mshalds.w %1, %2, %0"
9997 [(set_attr "type" "mcmp_media")])
9999 (define_insn "ashrv2si3"
10000 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10001 (ashiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
10002 (match_operand:DI 2 "arith_reg_operand" "r")))]
10004 "mshard.l %1, %2, %0"
10005 [(set_attr "type" "arith_media")])
10007 (define_insn "ashrv4hi3"
10008 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10009 (ashiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
10010 (match_operand:DI 2 "arith_reg_operand" "r")))]
10012 "mshard.w %1, %2, %0"
10013 [(set_attr "type" "arith_media")])
10015 (define_insn "mshards_q"
10016 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
10018 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
10019 (match_operand:DI 2 "arith_reg_or_0_operand" "rU"))))]
10021 "mshards.q %1, %N2, %0"
10022 [(set_attr "type" "mcmp_media")])
10024 (define_expand "mshfhi_b"
10025 [(match_operand:V8QI 0 "arith_reg_dest" "")
10026 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rU")
10027 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rU")]
10031 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_b : gen_mshf0_b)
10032 (operands[0], operands[1], operands[2]));
10036 (define_expand "mshflo_b"
10037 [(match_operand:V8QI 0 "arith_reg_dest" "")
10038 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rU")
10039 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rU")]
10043 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_b : gen_mshf4_b)
10044 (operands[0], operands[1], operands[2]));
10048 (define_insn "mshf4_b"
10050 (match_operand:V8QI 0 "arith_reg_dest" "=r")
10052 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rU")
10053 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rU"))
10054 (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13)
10055 (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))]
10057 "* return (TARGET_LITTLE_ENDIAN
10058 ? \"mshfhi.b %N1, %N2, %0\"
10059 : \"mshflo.b %N1, %N2, %0\");"
10060 [(set_attr "type" "arith_media")])
10062 (define_insn "mshf0_b"
10064 (match_operand:V8QI 0 "arith_reg_dest" "=r")
10066 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rU")
10067 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rU"))
10068 (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9)
10069 (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))]
10071 "* return (TARGET_LITTLE_ENDIAN
10072 ? \"mshflo.b %N1, %N2, %0\"
10073 : \"mshfhi.b %N1, %N2, %0\");"
10074 [(set_attr "type" "arith_media")])
10076 (define_expand "mshfhi_l"
10077 [(match_operand:V2SI 0 "arith_reg_dest" "")
10078 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU")
10079 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU")]
10083 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_l : gen_mshf0_l)
10084 (operands[0], operands[1], operands[2]));
10088 (define_expand "mshflo_l"
10089 [(match_operand:V2SI 0 "arith_reg_dest" "")
10090 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU")
10091 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU")]
10095 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_l : gen_mshf4_l)
10096 (operands[0], operands[1], operands[2]));
10100 (define_insn "mshf4_l"
10101 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10103 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU")
10104 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU"))
10105 (parallel [(const_int 1) (const_int 3)])))]
10107 "* return (TARGET_LITTLE_ENDIAN
10108 ? \"mshfhi.l %N1, %N2, %0\"
10109 : \"mshflo.l %N1, %N2, %0\");"
10110 [(set_attr "type" "arith_media")])
10112 (define_insn "mshf0_l"
10113 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10115 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU")
10116 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rU"))
10117 (parallel [(const_int 0) (const_int 2)])))]
10119 "* return (TARGET_LITTLE_ENDIAN
10120 ? \"mshflo.l %N1, %N2, %0\"
10121 : \"mshfhi.l %N1, %N2, %0\");"
10122 [(set_attr "type" "arith_media")])
10124 (define_expand "mshfhi_w"
10125 [(match_operand:V4HI 0 "arith_reg_dest" "")
10126 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU")
10127 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU")]
10131 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_w : gen_mshf0_w)
10132 (operands[0], operands[1], operands[2]));
10136 (define_expand "mshflo_w"
10137 [(match_operand:V4HI 0 "arith_reg_dest" "")
10138 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU")
10139 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU")]
10143 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_w : gen_mshf4_w)
10144 (operands[0], operands[1], operands[2]));
10148 (define_insn "mshf4_w"
10149 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10151 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU")
10152 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))
10153 (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))]
10155 "* return (TARGET_LITTLE_ENDIAN
10156 ? \"mshfhi.w %N1, %N2, %0\"
10157 : \"mshflo.w %N1, %N2, %0\");"
10158 [(set_attr "type" "arith_media")])
10160 (define_insn "mshf0_w"
10161 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10163 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU")
10164 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rU"))
10165 (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))]
10167 "* return (TARGET_LITTLE_ENDIAN
10168 ? \"mshflo.w %N1, %N2, %0\"
10169 : \"mshfhi.w %N1, %N2, %0\");"
10170 [(set_attr "type" "arith_media")])
10172 (define_insn "mshflo_w_x"
10173 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10175 (vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rU")
10176 (match_operand:V2HI 2 "extend_reg_or_0_operand" "rU"))
10177 (parallel [(const_int 0) (const_int 2) (const_int 1) (const_int 3)])))]
10179 "mshflo.w %N1, %N2, %0"
10180 [(set_attr "type" "arith_media")])
10182 /* These are useful to expand ANDs and as combiner patterns. */
10183 (define_insn_and_split "mshfhi_l_di"
10184 [(set (match_operand:DI 0 "arith_reg_dest" "=r,f")
10185 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU,f")
10187 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU,?f")
10188 (const_int -4294967296))))]
10191 mshfhi.l %N1, %N2, %0
10193 "TARGET_SHMEDIA && reload_completed
10194 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
10195 [(set (match_dup 3) (match_dup 4))
10196 (set (match_dup 5) (match_dup 6))]
10199 operands[3] = gen_lowpart (SImode, operands[0]);
10200 operands[4] = gen_highpart (SImode, operands[1]);
10201 operands[5] = gen_highpart (SImode, operands[0]);
10202 operands[6] = gen_highpart (SImode, operands[2]);
10204 [(set_attr "type" "arith_media")])
10206 (define_insn "*mshfhi_l_di_rev"
10207 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10208 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
10209 (const_int -4294967296))
10210 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU")
10213 "mshfhi.l %N2, %N1, %0"
10214 [(set_attr "type" "arith_media")])
10217 [(set (match_operand:DI 0 "arith_reg_dest" "")
10218 (ior:DI (zero_extend:DI (match_operand:SI 1
10219 "extend_reg_or_0_operand" ""))
10220 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "")
10221 (const_int -4294967296))))
10222 (clobber (match_operand:DI 3 "arith_reg_dest" ""))]
10227 emit_insn (gen_ashldi3_media (operands[3],
10228 simplify_gen_subreg (DImode, operands[1],
10231 emit_insn (gen_mshfhi_l_di (operands[0], operands[3], operands[2]));
10235 (define_insn "mshflo_l_di"
10236 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10237 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
10238 (const_int 4294967295))
10239 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU")
10243 "mshflo.l %N1, %N2, %0"
10244 [(set_attr "type" "arith_media")])
10246 (define_insn "*mshflo_l_di_rev"
10247 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10248 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
10250 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU")
10251 (const_int 4294967295))))]
10254 "mshflo.l %N2, %N1, %0"
10255 [(set_attr "type" "arith_media")])
10257 ;; Combiner pattern for trampoline initialization.
10258 (define_insn_and_split "*double_shori"
10259 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10260 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
10262 (match_operand:DI 2 "const_int_operand" "n")))]
10264 && INTVAL (operands[2]) == trunc_int_for_mode (INTVAL (operands[2]), SImode)"
10266 "rtx_equal_p (operands[0], operands[1])"
10270 HOST_WIDE_INT v = INTVAL (operands[2]);
10272 emit_insn (gen_shori_media (operands[0], operands[0],
10273 gen_int_mode (INTVAL (operands[2]) >> 16, HImode)));
10274 emit_insn (gen_shori_media (operands[0], operands[0],
10275 gen_int_mode (v, HImode)));
10280 (define_insn "*mshflo_l_di_x"
10281 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10282 (ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand"
10284 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rU")
10288 "mshflo.l %N1, %N2, %0"
10289 [(set_attr "type" "arith_media")])
10291 (define_insn_and_split "concat_v2sf"
10292 [(set (match_operand:V2SF 0 "register_operand" "=r,f,f?")
10293 ;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rU,0,f")
10294 (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rU,f,f")
10295 (match_operand:SF 2 "register_operand" "rU,f,f")))]
10299 mshflo.l %N1, %N2, %0
10302 "TARGET_SHMEDIA && reload_completed
10303 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
10304 [(set (match_dup 3) (match_dup 1))
10305 (set (match_dup 4) (match_dup 2))]
10308 operands[3] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 0);
10309 operands[4] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 4);
10311 [(set_attr "type" "arith_media")])
10313 (define_insn "*mshflo_l_di_x_rev"
10314 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10315 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rU")
10317 (zero_extend:DI (match_operand:SI 2 "extend_reg_or_0_operand" "rU"))))]
10320 "mshflo.l %N2, %N1, %0"
10321 [(set_attr "type" "arith_media")])
10323 (define_insn "ashlv2si3"
10324 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10325 (ashift:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
10326 (match_operand:DI 2 "arith_reg_operand" "r")))]
10328 "mshlld.l %1, %2, %0"
10329 [(set_attr "type" "arith_media")])
10331 (define_insn "ashlv4hi3"
10332 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10333 (ashift:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
10334 (match_operand:DI 2 "arith_reg_operand" "r")))]
10336 "mshlld.w %1, %2, %0"
10337 [(set_attr "type" "arith_media")])
10339 (define_insn "lshrv2si3"
10340 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10341 (lshiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
10342 (match_operand:DI 2 "arith_reg_operand" "r")))]
10344 "mshlrd.l %1, %2, %0"
10345 [(set_attr "type" "arith_media")])
10347 (define_insn "lshrv4hi3"
10348 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10349 (lshiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
10350 (match_operand:DI 2 "arith_reg_operand" "r")))]
10352 "mshlrd.w %1, %2, %0"
10353 [(set_attr "type" "arith_media")])
10355 (define_insn "subv2si3"
10356 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10357 (minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU")
10358 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
10360 "msub.l %N1, %2, %0"
10361 [(set_attr "type" "arith_media")])
10363 (define_insn "subv4hi3"
10364 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10365 (minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU")
10366 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
10368 "msub.w %N1, %2, %0"
10369 [(set_attr "type" "arith_media")])
10371 (define_insn "sssubv2si3"
10372 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
10373 (ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rU")
10374 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
10376 "msubs.l %N1, %2, %0"
10377 [(set_attr "type" "mcmp_media")])
10379 (define_insn "ussubv8qi3"
10380 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
10381 (us_minus:V8QI (match_operand:V8QI 1 "arith_reg_operand" "r")
10382 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
10384 "msubs.ub %1, %2, %0"
10385 [(set_attr "type" "mcmp_media")])
10387 (define_insn "sssubv4hi3"
10388 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
10389 (ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rU")
10390 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
10392 "msubs.w %N1, %2, %0"
10393 [(set_attr "type" "mcmp_media")])
10395 ;; Floating Point Intrinsics
10397 (define_insn "fcosa_s"
10398 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10399 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
10403 [(set_attr "type" "atrans_media")])
10405 (define_insn "fsina_s"
10406 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10407 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
10411 [(set_attr "type" "atrans_media")])
10413 (define_insn "fipr"
10414 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10415 (plus:SF (plus:SF (vec_select:SF (mult:V4SF (match_operand:V4SF 1
10416 "fp_arith_reg_operand" "f")
10417 (match_operand:V4SF 2
10418 "fp_arith_reg_operand" "f"))
10419 (parallel [(const_int 0)]))
10420 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
10421 (parallel [(const_int 1)])))
10422 (plus:SF (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
10423 (parallel [(const_int 2)]))
10424 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
10425 (parallel [(const_int 3)])))))]
10428 [(set_attr "type" "fparith_media")])
10430 (define_insn "fsrra_s"
10431 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10432 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "f")]
10436 [(set_attr "type" "atrans_media")])
10438 (define_insn "ftrv"
10439 [(set (match_operand:V4SF 0 "fp_arith_reg_operand" "=f")
10443 (vec_select:V4SF (match_operand:V16SF 1 "fp_arith_reg_operand" "f")
10444 (parallel [(const_int 0) (const_int 5)
10445 (const_int 10) (const_int 15)]))
10446 (match_operand:V4SF 2 "fp_arith_reg_operand" "f"))
10448 (vec_select:V4SF (match_dup 1)
10449 (parallel [(const_int 4) (const_int 9)
10450 (const_int 14) (const_int 3)]))
10451 (vec_select:V4SF (match_dup 2)
10452 (parallel [(const_int 1) (const_int 2)
10453 (const_int 3) (const_int 0)]))))
10456 (vec_select:V4SF (match_dup 1)
10457 (parallel [(const_int 8) (const_int 13)
10458 (const_int 2) (const_int 7)]))
10459 (vec_select:V4SF (match_dup 2)
10460 (parallel [(const_int 2) (const_int 3)
10461 (const_int 0) (const_int 1)])))
10463 (vec_select:V4SF (match_dup 1)
10464 (parallel [(const_int 12) (const_int 1)
10465 (const_int 6) (const_int 11)]))
10466 (vec_select:V4SF (match_dup 2)
10467 (parallel [(const_int 3) (const_int 0)
10468 (const_int 1) (const_int 2)]))))))]
10471 [(set_attr "type" "fparith_media")])
10474 [(set (match_operand:QI 0 "arith_reg_dest" "=r")
10475 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
10479 [(set_attr "type" "arith_media")])
10481 (define_insn "nsbsi"
10482 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
10484 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
10488 [(set_attr "type" "arith_media")])
10490 (define_insn "nsbdi"
10491 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10493 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
10497 [(set_attr "type" "arith_media")])
10499 (define_expand "ffsdi2"
10500 [(set (match_operand:DI 0 "arith_reg_dest" "")
10501 (ffs:DI (match_operand:DI 1 "arith_reg_operand" "")))]
10505 rtx scratch = gen_reg_rtx (DImode);
10508 emit_insn (gen_adddi3 (scratch, operands[1], GEN_INT (-1)));
10509 emit_insn (gen_xordi3 (scratch, operands[1], scratch));
10510 emit_insn (gen_lshrdi3_media (scratch, scratch, const1_rtx));
10511 emit_insn (gen_nsbdi (scratch, scratch));
10512 emit_insn (gen_adddi3 (scratch, scratch, GEN_INT (-64)));
10513 emit_insn (gen_movdicc_false (scratch, operands[1], const0_rtx, scratch));
10514 last = emit_insn (gen_subdi3 (operands[0], const0_rtx, scratch));
10516 = gen_rtx_EXPR_LIST (REG_EQUAL,
10517 gen_rtx_FFS (DImode, operands[0]), REG_NOTES (last));
10521 (define_expand "ffssi2"
10522 [(set (match_operand:SI 0 "arith_reg_dest" "")
10523 (ffs:SI (match_operand:SI 1 "arith_reg_operand" "")))]
10527 rtx scratch = gen_reg_rtx (SImode);
10528 rtx discratch = gen_reg_rtx (DImode);
10531 emit_insn (gen_adddi3z_media (discratch, operands[1],
10532 force_reg (SImode, GEN_INT (-1))));
10533 emit_insn (gen_andcdi3 (discratch, discratch,
10534 simplify_gen_subreg (DImode, operands[1],
10536 emit_insn (gen_nsbsi (scratch, discratch));
10537 last = emit_insn (gen_subsi3 (operands[0],
10538 force_reg (SImode, GEN_INT (-64)), scratch));
10540 = gen_rtx_EXPR_LIST (REG_EQUAL,
10541 gen_rtx_FFS (SImode, operands[0]), REG_NOTES (last));
10545 (define_insn "byterev"
10546 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
10547 (vec_select:V8QI (match_operand:V8QI 1 "arith_reg_operand" "r")
10548 (parallel [(const_int 7) (const_int 6) (const_int 5)
10549 (const_int 4) (const_int 3) (const_int 2)
10550 (const_int 1) (const_int 0)])))]
10553 [(set_attr "type" "arith_media")])
10555 ;; The following description models the
10556 ;; SH4 pipeline using the DFA based scheduler.
10557 ;; The DFA based description is better way to model
10558 ;; a superscalar pipeline as compared to function unit
10559 ;; reservation model.
10560 ;; 1. The function unit based model is oriented to describe at most one
10561 ;; unit reservation by each insn. It is difficult to model unit reservations in multiple
10562 ;; pipeline units by same insn. This can be done using DFA based description.
10563 ;; 2. The execution performance of DFA based scheduler does not depend on processor complexity.
10564 ;; 3. Writing all unit reservations for an instruction class is more natural description
10565 ;; of the pipeline and makes interface of the hazard recognizer simpler than the
10566 ;; old function unit based model.
10567 ;; 4. The DFA model is richer and is a part of greater overall framework of RCSP.
10570 ;; Two automata are defined to reduce number of states
10571 ;; which a single large automaton will have.(Factoring)
10573 (define_automaton "inst_pipeline,fpu_pipe")
10575 ;; This unit is basically the decode unit of the processor.
10576 ;; Since SH4 is a dual issue machine,it is as if there are two
10577 ;; units so that any insn can be processed by either one
10578 ;; of the decoding unit.
10580 (define_cpu_unit "pipe_01,pipe_02" "inst_pipeline")
10583 ;; The fixed point arithmetic calculator(?? EX Unit).
10585 (define_cpu_unit "int" "inst_pipeline")
10587 ;; f1_1 and f1_2 are floating point units.Actually there is
10588 ;; a f1 unit which can overlap with other f1 unit but
10589 ;; not another F1 unit.It is as though there were two
10592 (define_cpu_unit "f1_1,f1_2" "fpu_pipe")
10594 ;; The floating point units.
10596 (define_cpu_unit "F1,F2,F3,FS" "fpu_pipe")
10598 ;; This is basically the MA unit of SH4
10599 ;; used in LOAD/STORE pipeline.
10601 (define_cpu_unit "memory" "inst_pipeline")
10603 ;; The address calculator used for branch instructions.
10604 ;; This will be reserved with "issue" of branch instructions
10605 ;; and this is to make sure that no two branch instructions
10606 ;; can be issued in parallel.
10608 (define_cpu_unit "pcr_addrcalc" "inst_pipeline")
10610 ;; ----------------------------------------------------
10611 ;; This reservation is to simplify the dual issue description.
10613 (define_reservation "issue" "pipe_01|pipe_02")
10615 ;; This is to express the locking of D stage.
10617 (define_reservation "d_lock" "pipe_01+pipe_02")
10619 ;; This is to simplify description where F1,F2,FS
10620 ;; are used simultaneously.
10622 (define_reservation "fpu" "F1+F2+FS")
10624 ;; This is to highlight the fact that f1
10625 ;; cannot overlap with F1.
10627 (exclusion_set "f1_1,f1_2" "F1")
10629 ;; Although reg moves have a latency of zero
10630 ;; we need to highlight that they use D stage
10633 (define_insn_reservation "reg_mov" 0
10634 (eq_attr "type" "move,fmove")
10637 ;; Other MT group intructions(1 step operations)
10642 (define_insn_reservation "mt" 1
10643 (eq_attr "insn_class" "mt_group")
10646 ;; Fixed Point Arithmetic Instructions(1 step operations)
10651 (define_insn_reservation "simple_arith" 1
10652 (eq_attr "insn_class" "ex_group")
10655 ;; Load Store instructions. (MOV.[BWL]@(d,GBR)
10660 (define_insn_reservation "load_store" 2
10661 (eq_attr "type" "load,load_si,pcload,pcload_si,store")
10664 ;; Branch (BF,BF/S,BT,BT/S,BRA)
10666 ;; Latency: 2 (or 1) Actually Observed to be 5/7
10668 ;; The latency is 1 when displacement is 0.
10669 ;; This reservation can be further broken into 2
10670 ;; 1. branch_zero : One with latency 1 and in the TEST
10671 ;; part it also checks for 0 (ZERO) displacement
10672 ;; 2. branch: Latency 2.
10674 (define_insn_reservation "branch_zero" 5
10675 (and (eq_attr "type" "cbranch")
10676 (eq_attr "length" "2"))
10677 "(issue+pcr_addrcalc),pcr_addrcalc,nothing")
10679 (define_insn_reservation "branch" 7
10680 (eq_attr "type" "cbranch")
10681 "(issue+pcr_addrcalc),pcr_addrcalc,nothing")
10683 ;; Branch Far (JMP,RTS,BRAF)
10687 ;; Since issue stage (D stage) is blocked for 2nd cycle,
10688 ;; cpu_unit int is reserved since it might be required for far
10689 ;; address calculation.
10691 (define_insn_reservation "branch_far" 12
10692 (and (eq_attr "type" "jump,return")
10693 (eq_attr "length" "6"))
10694 "d_lock*2,int+pcr_addrcalc,pcr_addrcalc")
10700 ;; this instruction can be executed in any of the pipelines
10701 ;; and blocks the pipeline for next 4 stages.
10703 (define_insn_reservation "return_from_exp" 5
10704 (eq_attr "type" "rte")
10705 "(issue+pcr_addrcalc),d_lock*4,int+pcr_addrcalc,nothing")
10712 (define_insn_reservation "ocbwb" 5
10713 (eq_attr "insn_class" "cwb")
10714 "issue,(int+memory),memory*5")
10720 ;; The SX stage is blocked for last 2 cycles.
10722 (define_insn_reservation "lds_to_pr" 3
10723 (eq_attr "type" "prset,call,sfunc")
10724 "(issue+pcr_addrcalc),(issue+int+pcr_addrcalc),(int+pcr_addrcalc)*2")
10730 ;; The SX unit is blocked for last 2 cycles.
10732 (define_insn_reservation "ldsmem_to_pr" 3
10733 (eq_attr "type" "pload")
10734 "(issue+pcr_addrcalc),(issue+int+pcr_addrcalc),(int+memory+pcr_addrcalc),(int+pcr_addrcalc)")
10740 ;; The SX unit in second and third cycles.
10742 (define_insn_reservation "sts_from_pr" 2
10743 (eq_attr "type" "prget")
10744 "(issue+pcr_addrcalc),(pipe_01+int+pcr_addrcalc),(int+pcr_addrcalc),nothing")
10751 (define_insn_reservation "prload_mem" 2
10752 (eq_attr "type" "pstore")
10753 "(issue+pcr_addrcalc),(pipe_01+int+pcr_addrcalc),(int+memory+pcr_addrcalc),memory")
10759 ;; F1 is blocked for last three cycles.
10761 (define_insn_reservation "fpscr_store" 4
10762 (eq_attr "insn_class" "lds_to_fpscr")
10768 ;; Latency to update Rn is 1 and latency to update FPSCR is 4
10770 ;; F1 is blocked for last three cycles.
10772 (define_insn_reservation "fpscr_store_mem" 4
10773 (eq_attr "insn_class" "ldsmem_to_fpscr")
10774 "issue,(int+memory),(F1+memory),F1*2")
10777 ;; Fixed point multiplication (DMULS.L DMULU.L MUL.L MULS.W,MULU.W)
10782 (define_insn_reservation "multi" 4
10783 (eq_attr "type" "smpy,dmpy")
10784 "issue,(issue+int+f1_1),(int+f1_1),(f1_1|f1_2)*2,F2,FS")
10787 ;; Single precision floating point computation FCMP/EQ,
10788 ;; FCP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRVHG, FSCHG
10793 (define_insn_reservation "fp_arith" 4
10794 (eq_attr "type" "fp")
10797 ;; Single Precision FDIV/SQRT
10802 (define_insn_reservation "fp_div" 13
10803 (eq_attr "type" "fdiv")
10804 "issue,F1+F3,F1+F2+F3,F3*7,F1+F3,F2,FS")
10806 ;; Double Precision floating point computation
10807 ;; (FCNVDS, FCNVSD, FLOAT, FTRC)
10809 ;; Latency: (3,4)/5
10812 (define_insn_reservation "dp_float" 5
10813 (eq_attr "type" "dfp_conv")
10814 "issue,F1,F1+F2,F2+FS,FS")
10816 ;; Double-precision floating-point (FADD ,FMUL,FSUB)
10818 ;; Latency: (7,8)/9
10821 (define_insn_reservation "fp_double_arith" 9
10822 (eq_attr "type" "dfp_arith")
10823 "issue,F1,F1+F2,fpu*4,F2+FS,FS")
10825 ;; Double-precision FCMP (FCMP/EQ,FCMP/GT)
10830 (define_insn_reservation "fp_double_cmp" 5
10831 (eq_attr "type" "dfp_cmp")
10832 "issue,(issue+F1),F1+F2,F2+FS,FS")
10834 ;; Double precision FDIV/SQRT
10836 ;; Latency: (24,25)/26
10839 (define_insn_reservation "dp_div" 26
10840 (eq_attr "type" "dfdiv")
10841 "issue,F1+F3,F1+F2+F3,F2+F3+FS,F3*16,F1+F3,F1+F2+F3,fpu+F3,F2+FS,FS")