1 /* Definitions of target machine for GNU compiler for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #define TARGET_VERSION \
25 fputs (" (Hitachi SH)", stderr);
27 /* Generate SDB debugging information. */
29 #define SDB_DEBUGGING_INFO
31 /* Output DBX (stabs) debugging information if doing -gstabs. */
37 #define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__} \
43 #define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
45 #define ASM_SPEC "%{ml:-little} %{mrelax:-relax}"
47 #define LINK_SPEC "%{ml:-m shl} %{mrelax:-relax}"
49 /* We can not debug without a frame pointer. */
50 /* #define CAN_DEBUG_WITHOUT_FP */
52 #define CONDITIONAL_REGISTER_USAGE \
56 for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \
57 fixed_regs[regno] = call_used_regs[regno] = 1; \
59 /* Hitachi saves and restores mac registers on call. */ \
62 call_used_regs[MACH_REG] = 0; \
63 call_used_regs[MACL_REG] = 0; \
66 /* ??? Need to write documentation for all SH options and add it to the
69 /* Run-time compilation parameters selecting different hardware subsets. */
71 extern int target_flags;
72 #define ISIZE_BIT (1<<1)
73 #define DALIGN_BIT (1<<6)
74 #define SH0_BIT (1<<7)
75 #define SH1_BIT (1<<8)
76 #define SH2_BIT (1<<9)
77 #define SH3_BIT (1<<10)
78 #define SH3E_BIT (1<<11)
79 #define SPACE_BIT (1<<13)
80 #define BIGTABLE_BIT (1<<14)
81 #define RELAX_BIT (1<<15)
82 #define HITACHI_BIT (1<<22)
83 #define PADSTRUCT_BIT (1<<28)
84 #define LITTLE_ENDIAN_BIT (1<<29)
86 /* Nonzero if we should dump out instruction size info. */
87 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
89 /* Nonzero to align doubles on 64 bit boundaries. */
90 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
92 /* Nonzero if we should generate code using type 0 insns. */
93 /* ??? Is there such a thing as SH0? If not, we should delete all
95 #define TARGET_SH0 (target_flags & SH0_BIT)
97 /* Nonzero if we should generate code using type 1 insns. */
98 #define TARGET_SH1 (target_flags & SH1_BIT)
100 /* Nonzero if we should generate code using type 2 insns. */
101 #define TARGET_SH2 (target_flags & SH2_BIT)
103 /* Nonzero if we should generate code using type 3 insns. */
104 #define TARGET_SH3 (target_flags & SH3_BIT)
106 /* Nonzero if we should generate code using type 3E insns. */
107 #define TARGET_SH3E (target_flags & SH3E_BIT)
109 /* Nonzero if we should generate smaller code rather than faster code. */
110 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
112 /* Nonzero to use long jump tables. */
113 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
115 /* Nonzero to generate pseudo-ops needed by the assembler and linker
116 to do function call relaxing. */
117 #define TARGET_RELAX (target_flags & RELAX_BIT)
119 /* Nonzero if using Hitachi's calling convention. */
120 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
122 /* Nonzero if padding structures to a multiple of 4 bytes. This is
123 incompatible with Hitachi's compiler, and gives unusual structure layouts
124 which confuse programmers.
125 ??? This option is not useful, but is retained in case there are people
126 who are still relying on it. It may be deleted in the future. */
127 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
129 /* Nonzero if generating code for a little endian SH. */
130 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
132 #define TARGET_SWITCHES \
136 {"3", SH3_BIT|SH2_BIT}, \
137 {"3e", SH3E_BIT|SH3_BIT|SH2_BIT}, \
138 {"b", -LITTLE_ENDIAN_BIT}, \
139 {"bigtable", BIGTABLE_BIT}, \
140 {"dalign", DALIGN_BIT}, \
141 {"hitachi", HITACHI_BIT}, \
142 {"isize", ISIZE_BIT}, \
143 {"l", LITTLE_ENDIAN_BIT}, \
144 {"padstruct", PADSTRUCT_BIT}, \
145 {"relax", RELAX_BIT}, \
146 {"space", SPACE_BIT}, \
147 {"", TARGET_DEFAULT} \
150 #define TARGET_DEFAULT (0)
152 #define OVERRIDE_OPTIONS \
164 /* Never run scheduling before reload, since that can \
165 break global alloc, and generates slower code anyway due \
166 to the pressure on R0. */ \
167 flag_schedule_insns = 0; \
170 /* Target machine storage layout. */
172 /* Define to use software floating point emulator for REAL_ARITHMETIC and
173 decimal <-> binary conversion. */
174 #define REAL_ARITHMETIC
176 /* Define this if most significant bit is lowest numbered
177 in instructions that operate on numbered bit-fields. */
179 #define BITS_BIG_ENDIAN 0
181 /* Define this if most significant byte of a word is the lowest numbered. */
182 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
184 /* Define this if most significant word of a multiword number is the lowest
186 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
188 /* Define this to set the endianness to use in libgcc2.c, which can
189 not depend on target_flags. */
190 #if defined(__LITTLE_ENDIAN__)
191 #define LIBGCC2_WORDS_BIG_ENDIAN 0
193 #define LIBGCC2_WORDS_BIG_ENDIAN 1
196 /* Number of bits in an addressable storage unit. */
197 #define BITS_PER_UNIT 8
199 /* Width in bits of a "word", which is the contents of a machine register.
200 Note that this is not necessarily the width of data type `int';
201 if using 16-bit ints on a 68000, this would still be 32.
202 But on a machine with 16-bit registers, this would be 16. */
203 #define BITS_PER_WORD 32
204 #define MAX_BITS_PER_WORD 32
206 /* Width of a word, in units (bytes). */
207 #define UNITS_PER_WORD 4
209 /* Width in bits of a pointer.
210 See also the macro `Pmode' defined below. */
211 #define POINTER_SIZE 32
213 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
214 #define PARM_BOUNDARY 32
216 /* Boundary (in *bits*) on which stack pointer should be aligned. */
217 #define STACK_BOUNDARY 32
219 /* Allocation boundary (in *bits*) for the code of a function.
220 32 bit alignment is faster, because instructions are always fetched as a
221 pair from a longword boundary. */
222 #define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : 32)
224 /* Alignment of field after `int : 0' in a structure. */
225 #define EMPTY_FIELD_BOUNDARY 32
227 /* No data type wants to be aligned rounder than this. */
228 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
230 /* The best alignment to use in cases where we have a choice. */
231 #define FASTEST_ALIGNMENT 32
233 /* Make strings word-aligned so strcpy from constants will be faster. */
234 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
235 ((TREE_CODE (EXP) == STRING_CST \
236 && (ALIGN) < FASTEST_ALIGNMENT) \
237 ? FASTEST_ALIGNMENT : (ALIGN))
239 /* Make arrays of chars word-aligned for the same reasons. */
240 #define DATA_ALIGNMENT(TYPE, ALIGN) \
241 (TREE_CODE (TYPE) == ARRAY_TYPE \
242 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
243 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
245 /* Number of bits which any structure or union's size must be a
246 multiple of. Each structure or union's size is rounded up to a
248 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
250 /* Set this nonzero if move instructions will actually fail to work
251 when given unaligned data. */
252 #define STRICT_ALIGNMENT 1
254 /* Standard register usage. */
256 /* Register allocation for the Hitachi calling convention:
262 r14 frame pointer/call saved
264 ap arg pointer (doesn't really exist, always eliminated)
265 pr subroutine return address
267 mach multiply/accumulate result, high part
268 macl multiply/accumulate result, low part.
269 fpul fp/int communication register
271 fr1..fr3 scratch floating point registers
273 fr12..fr15 call saved floating point registers */
275 /* Number of actual hardware registers.
276 The hardware registers are assigned numbers for the compiler
277 from 0 to just below FIRST_PSEUDO_REGISTER.
278 All registers that the compiler knows about must be given numbers,
279 even those that are not normally considered general registers. */
287 #define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
289 /* Number 23 is unused. Reserved for future expansion. */
290 #define FIRST_FP_REG 24
291 #define LAST_FP_REG 39
293 #define FIRST_PSEUDO_REGISTER 40
295 /* 1 for registers that have pervasive standard uses
296 and are not available for the register allocator.
298 Mach register is fixed 'cause it's only 10 bits wide for SH1.
299 It is 32 bits wide for SH2. */
301 #define FIXED_REGISTERS \
314 /* 1 for registers not available across function calls.
315 These must include the FIXED_REGISTERS and also any
316 registers that can be used without being saved.
317 The latter must include the registers where values are returned
318 and the register where structure-value addresses are passed.
319 Aside from that, you can include as many other registers as you like. */
321 #define CALL_USED_REGISTERS \
334 /* Return number of consecutive hard regs needed starting at reg REGNO
335 to hold something of mode MODE.
336 This is ordinarily the length in words of a value of mode MODE
337 but can be less for certain modes in special long registers.
339 On the SH regs are UNITS_PER_WORD bits wide. */
341 #define HARD_REGNO_NREGS(REGNO, MODE) \
342 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
344 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
345 We can allow any mode in any general register. The special registers
346 only allow SImode. Don't allow any mode in the PR. */
348 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
349 (SPECIAL_REG (REGNO) ? (MODE) == SImode \
350 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
351 : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG ? (MODE) == SFmode \
352 : (REGNO) == PR_REG ? 0 \
355 /* Value is 1 if it is a good idea to tie two pseudo registers
356 when one has mode MODE1 and one has mode MODE2.
357 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
358 for any hard reg, then this must be 0 for correct output. */
360 #define MODES_TIEABLE_P(MODE1, MODE2) \
361 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
363 /* Specify the registers used for certain standard purposes.
364 The values of these macros are register numbers. */
366 /* Define this if the program counter is overloaded on a register. */
367 /* #define PC_REGNUM 15*/
369 /* Register to use for pushing function arguments. */
370 #define STACK_POINTER_REGNUM 15
372 /* Base register for access to local variables of the function. */
373 #define FRAME_POINTER_REGNUM 14
375 /* Value should be nonzero if functions must have frame pointers.
376 Zero means the frame pointer need not be set up (and parms may be accessed
377 via the stack pointer) in functions that seem suitable. */
379 #define FRAME_POINTER_REQUIRED 0
381 /* Definitions for register eliminations.
383 We have two registers that can be eliminated on the SH. First, the
384 frame pointer register can often be eliminated in favor of the stack
385 pointer register. Secondly, the argument pointer register can always be
386 eliminated; it is replaced with either the stack or frame pointer. */
388 /* This is an array of structures. Each structure initializes one pair
389 of eliminable registers. The "from" register number is given first,
390 followed by "to". Eliminations of the same "from" register are listed
391 in order of preference. */
393 #define ELIMINABLE_REGS \
394 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
395 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
396 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
398 /* Given FROM and TO register numbers, say whether this elimination
400 #define CAN_ELIMINATE(FROM, TO) \
401 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
403 /* Define the offset between two registers, one to be eliminated, and the other
404 its replacement, at the start of a routine. */
406 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
407 OFFSET = initial_elimination_offset (FROM, TO)
409 /* Base register for access to arguments of the function. */
410 #define ARG_POINTER_REGNUM 16
412 /* Register in which the static-chain is passed to a function. */
413 #define STATIC_CHAIN_REGNUM 13
415 /* The register in which a struct value address is passed. */
417 #define STRUCT_VALUE_REGNUM 2
419 /* If the structure value address is not passed in a register, define
420 `STRUCT_VALUE' as an expression returning an RTX for the place
421 where the address is passed. If it returns 0, the address is
422 passed as an "invisible" first argument. */
424 /*#define STRUCT_VALUE ((rtx)0)*/
426 /* Don't default to pcc-struct-return, because we have already specified
427 exactly how to return structures in the RETURN_IN_MEMORY macro. */
429 #define DEFAULT_PCC_STRUCT_RETURN 0
431 /* Define the classes of registers for register constraints in the
432 machine description. Also define ranges of constants.
434 One of the classes must always be named ALL_REGS and include all hard regs.
435 If there is more than one class, another class must be named NO_REGS
436 and contain no registers.
438 The name GENERAL_REGS must be the name of a class (or an alias for
439 another name such as ALL_REGS). This is the class of registers
440 that is allowed by "g" or "r" in a register constraint.
441 Also, registers outside this class are allocated only when
442 instructions express preferences for them.
444 The classes must be numbered in nondecreasing order; that is,
445 a larger-numbered class must never be contained completely
446 in a smaller-numbered class.
448 For any two classes, it is very desirable that there be another
449 class that represents their union. */
451 /* The SH has two sorts of general registers, R0 and the rest. R0 can
452 be used as the destination of some of the arithmetic ops. There are
453 also some special purpose registers; the T bit register, the
454 Procedure Return Register and the Multiply Accumulate Registers. */
471 #define N_REG_CLASSES (int) LIM_REG_CLASSES
473 /* Give names of register classes as strings for dump file. */
474 #define REG_CLASS_NAMES \
488 /* Define which registers fit in which classes.
489 This is an initializer for a vector of HARD_REG_SET
490 of length N_REG_CLASSES. */
492 #define REG_CLASS_CONTENTS \
494 { 0x00000000, 0x00000000 }, /* NO_REGS */ \
495 { 0x00000001, 0x00000000 }, /* R0_REGS */ \
496 { 0x00020000, 0x00000000 }, /* PR_REGS */ \
497 { 0x00040000, 0x00000000 }, /* T_REGS */ \
498 { 0x00300000, 0x00000000 }, /* MAC_REGS */ \
499 { 0x0001FFFF, 0x00000000 }, /* GENERAL_REGS */ \
500 { 0x00400000, 0x00000000 }, /* FPUL_REGS */ \
501 { 0x01000000, 0x00000000 }, /* FP0_REGS */ \
502 { 0xFF000000, 0x000000FF }, /* FP_REGS */ \
503 { 0xFF7FFFFF, 0x000000FF }, /* ALL_REGS */ \
506 /* The same information, inverted:
507 Return the class number of the smallest class containing
508 reg number REGNO. This could be a conditional expression
509 or could index an array. */
511 extern int regno_reg_class[];
512 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
514 /* When defined, the compiler allows registers explicitly used in the
515 rtl to be used as spill registers but prevents the compiler from
516 extending the lifetime of these registers. */
518 #define SMALL_REGISTER_CLASSES
520 /* The order in which register should be allocated. */
521 #define REG_ALLOC_ORDER \
522 { 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14, \
523 24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39, \
524 22,15,16,17,18,19,20,21,23 }
526 /* The class value for index registers, and the one for base regs. */
527 #define INDEX_REG_CLASS R0_REGS
528 #define BASE_REG_CLASS GENERAL_REGS
530 /* Get reg_class from a letter such as appears in the machine
532 extern enum reg_class reg_class_from_letter[];
534 #define REG_CLASS_FROM_LETTER(C) \
535 ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
537 /* The letters I, J, K, L and M in a register constraint string
538 can be used to stand for particular ranges of immediate operands.
539 This macro defines what the ranges are.
540 C is the letter, and VALUE is a constant value.
541 Return 1 if VALUE is in the range specified by C.
542 I: arithmetic operand -127..128, as used in add, sub, etc
543 K: shift operand 1,2,8 or 16
544 L: logical operand 0..255, as used in and, or, etc.
548 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127)
549 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
550 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255)
551 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
552 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
553 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
554 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
555 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
556 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
557 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
558 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
561 /* Similar, but for floating constants, and defining letters G and H.
562 Here VALUE is the CONST_DOUBLE rtx itself. */
564 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
565 ((C) == 'G' ? fp_zero_operand (VALUE) \
566 : (C) == 'H' ? fp_one_operand (VALUE) \
569 /* Given an rtx X being reloaded into a reg required to be
570 in class CLASS, return the class of reg to actually use.
571 In general this is just CLASS; but on some machines
572 in some cases it is preferable to use a more restrictive class. */
574 #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
576 /* Return the maximum number of consecutive registers
577 needed to represent mode MODE in a register of class CLASS.
579 On SH this is the size of MODE in words. */
580 #define CLASS_MAX_NREGS(CLASS, MODE) \
581 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
583 /* Stack layout; function entry, exit and calling. */
585 /* Define the number of registers that can hold parameters.
586 These macros are used only in other macro definitions below. */
588 #define NPARM_REGS(MODE) \
589 ((TARGET_SH3E && ((MODE) == SFmode)) ? 8 : 4)
591 #define FIRST_PARM_REG 4
592 #define FIRST_RET_REG 0
594 #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
595 #define FIRST_FP_RET_REG FIRST_FP_REG
597 /* Define this if pushing a word on the stack
598 makes the stack pointer a smaller address. */
599 #define STACK_GROWS_DOWNWARD
601 /* Define this macro if the addresses of local variable slots are at
602 negative offsets from the frame pointer.
604 The SH only has positive indexes, so grow the frame up. */
605 /* #define FRAME_GROWS_DOWNWARD */
607 /* Offset from the frame pointer to the first local variable slot to
609 #define STARTING_FRAME_OFFSET 0
611 /* If we generate an insn to push BYTES bytes,
612 this says how many the stack pointer really advances by. */
613 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
615 /* Offset of first parameter from the argument pointer register value. */
616 #define FIRST_PARM_OFFSET(FNDECL) 0
618 /* Value is the number of byte of arguments automatically
619 popped when returning from a subroutine call.
620 FUNDECL is the declaration node of the function (as a tree),
621 FUNTYPE is the data type of the function (as a tree),
622 or for a library call it is an identifier node for the subroutine name.
623 SIZE is the number of bytes of arguments passed on the stack.
625 On the SH, the caller does not pop any of its arguments that were passed
627 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
629 /* Some subroutine macros specific to this machine. */
631 #define BASE_RETURN_VALUE_REG(MODE) \
632 ((TARGET_SH3E && ((MODE) == SFmode)) \
636 #define BASE_ARG_REG(MODE) \
637 ((TARGET_SH3E && ((MODE) == SFmode)) \
638 ? FIRST_FP_PARM_REG \
641 /* Define how to find the value returned by a function.
642 VALTYPE is the data type of the value (as a tree).
643 If the precise function being called is known, FUNC is its FUNCTION_DECL;
644 otherwise, FUNC is 0. */
646 #define FUNCTION_VALUE(VALTYPE, FUNC) \
647 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
649 /* Define how to find the value returned by a library function
650 assuming the value has mode MODE. */
651 #define LIBCALL_VALUE(MODE) \
652 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE));
654 /* 1 if N is a possible register number for a function value. */
655 #define FUNCTION_VALUE_REGNO_P(REGNO) \
656 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG))
658 /* 1 if N is a possible register number for function argument passing. */
659 #define FUNCTION_ARG_REGNO_P(REGNO) \
660 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG + 4)) \
662 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG + 8)))
664 /* Define a data type for recording info about an argument list
665 during the scan of that argument list. This data type should
666 hold all necessary information about the function itself
667 and about the args processed so far, enough to enable macros
668 such as FUNCTION_ARG to determine where the next arg should go.
670 On SH, this is a single integer, which is a number of words
671 of arguments scanned so far (including the invisible argument,
672 if any, which holds the structure-value-address).
673 Thus NARGREGS or more means all following args should go on the stack. */
675 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
680 #define CUMULATIVE_ARGS struct sh_args
682 #define GET_SH_ARG_CLASS(MODE) \
683 ((TARGET_SH3E && ((MODE) == SFmode)) ? SH_ARG_FLOAT : SH_ARG_INT)
685 #define ROUND_ADVANCE(SIZE) \
686 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
688 /* Round a register number up to a proper boundary for an arg of mode
691 The SH doesn't care about double alignment, so we only
692 round doubles to even regs when asked to explicitly. */
694 #define ROUND_REG(CUM, MODE) \
695 ((TARGET_ALIGN_DOUBLE \
696 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
697 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
698 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
699 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
701 /* Initialize a variable CUM of type CUMULATIVE_ARGS
702 for a call to a function whose data type is FNTYPE.
703 For a library call, FNTYPE is 0.
705 On SH, the offset always starts at 0: the first parm reg is always
708 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
710 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
711 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
714 /* Update the data in CUM to advance over an argument
715 of mode MODE and data type TYPE.
716 (TYPE is null for libcalls where that information may not be
719 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
720 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] = \
721 (ROUND_REG ((CUM), (MODE)) \
722 + ((MODE) != BLKmode \
723 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
724 : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
726 /* Return boolean indicating arg of mode MODE will be passed in a reg.
727 This macro is only used in this file. */
729 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
730 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \
731 && ((TYPE) == 0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
732 && (! TARGET_SH3E || (ROUND_REG((CUM), (MODE)) + (GET_MODE_SIZE(MODE)/4) <= NPARM_REGS (MODE))))
734 /* Define where to put the arguments to a function.
735 Value is zero to push the argument on the stack,
736 or a hard register in which to store the argument.
738 MODE is the argument's machine mode.
739 TYPE is the data type of the argument (as a tree).
740 This is null for libcalls where that information may
742 CUM is a variable of type CUMULATIVE_ARGS which gives info about
743 the preceding args and about the function being called.
744 NAMED is nonzero if this argument is a named parameter
745 (otherwise it is an extra parameter matching an ellipsis).
747 On SH the first args are normally in registers
748 and the rest are pushed. Any arg that starts within the first
749 NPARM_REGS words is at least partially passed in a register unless
750 its data type forbids. */
752 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
753 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
754 && (NAMED || TARGET_SH3E)) \
755 ? gen_rtx (REG, (MODE), \
756 (BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
759 /* For an arg passed partly in registers and partly in memory,
760 this is the number of registers used.
761 For args passed entirely in registers or entirely in memory, zero.
763 We sometimes split args. */
765 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
766 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
767 && (NAMED || TARGET_SH3E) \
768 && (ROUND_REG ((CUM), (MODE)) \
770 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
771 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
772 - NPARM_REGS (MODE) > 0)) \
773 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
776 extern int current_function_anonymous_args;
778 /* Perform any needed actions needed for a function that is receiving a
779 variable number of arguments. */
781 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
782 current_function_anonymous_args = 1;
784 /* Call the function profiler with a given profile label.
785 We use two .aligns, so as to make sure that both the .long is aligned
786 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
787 from the trapa instruction. */
789 #define FUNCTION_PROFILER(STREAM,LABELNO) \
791 fprintf(STREAM, " .align 2\n"); \
792 fprintf(STREAM, " trapa #33\n"); \
793 fprintf(STREAM, " .align 2\n"); \
794 fprintf(STREAM, " .long LP%d\n", (LABELNO)); \
797 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
798 the stack pointer does not matter. The value is tested only in
799 functions that have frame pointers.
800 No definition is equivalent to always zero. */
802 #define EXIT_IGNORE_STACK 1
804 /* Generate the assembly code for function exit
805 Just dump out any accumulated constant table. */
807 #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue (STREAM, SIZE)
809 /* Output assembler code for a block containing the constant parts
810 of a trampoline, leaving space for the variable parts.
812 On the SH, the trampoline looks like
813 1 0000 D301 mov.l l1,r3
814 2 0002 DD02 mov.l l2,r13
817 5 0008 00000000 l1: .long function
818 6 000c 00000000 l2: .long area */
819 #define TRAMPOLINE_TEMPLATE(FILE) \
821 fprintf ((FILE), " .word 0xd301\n"); \
822 fprintf ((FILE), " .word 0xdd02\n"); \
823 fprintf ((FILE), " .word 0x4d2b\n"); \
824 fprintf ((FILE), " .word 0x200b\n"); \
825 fprintf ((FILE), " .long 0\n"); \
826 fprintf ((FILE), " .long 0\n"); \
829 /* Length in units of the trampoline for entering a nested function. */
830 #define TRAMPOLINE_SIZE 16
832 /* Alignment required for a trampoline in units. */
833 #define TRAMPOLINE_ALIGN 4
835 /* Emit RTL insns to initialize the variable parts of a trampoline.
836 FNADDR is an RTX for the address of the function's pure code.
837 CXT is an RTX for the static chain value for the function. */
839 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
841 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
843 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
847 /* Generate necessary RTL for __builtin_saveregs().
848 ARGLIST is the argument list; see expr.c. */
849 extern struct rtx_def *sh_builtin_saveregs ();
850 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sh_builtin_saveregs (ARGLIST)
852 /* Addressing modes, and classification of registers for them. */
853 #define HAVE_POST_INCREMENT 1
854 /*#define HAVE_PRE_INCREMENT 1*/
855 /*#define HAVE_POST_DECREMENT 1*/
856 #define HAVE_PRE_DECREMENT 1
858 /* Macros to check register numbers against specific register classes. */
860 /* These assume that REGNO is a hard or pseudo reg number.
861 They give nonzero only if REGNO is a hard reg of the suitable class
862 or a pseudo reg currently allocated to a suitable hard reg.
863 Since they use reg_renumber, they are safe only once reg_renumber
864 has been allocated, which happens in local-alloc.c. */
866 #define REGNO_OK_FOR_BASE_P(REGNO) \
867 ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
868 #define REGNO_OK_FOR_INDEX_P(REGNO) \
869 ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
871 /* Maximum number of registers that can appear in a valid memory
874 #define MAX_REGS_PER_ADDRESS 2
876 /* Recognize any constant value that is a valid address. */
878 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
880 /* Nonzero if the constant value X is a legitimate general operand. */
882 /* ??? Should modify this to accept CONST_DOUBLE, and then modify the
883 constant pool table code to fix loads of CONST_DOUBLEs. If that doesn't
884 work well, then we can at least handle simple CONST_DOUBLEs here
887 #define LEGITIMATE_CONSTANT_P(X) \
888 (GET_CODE (X) != CONST_DOUBLE \
889 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X))))
891 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
892 and check its validity for a certain class.
893 We have two alternate definitions for each of them.
894 The usual definition accepts all pseudo regs; the other rejects
895 them unless they have been allocated suitable hard regs.
896 The symbol REG_OK_STRICT causes the latter definition to be used. */
898 #ifndef REG_OK_STRICT
900 /* Nonzero if X is a hard reg that can be used as a base reg
901 or if it is a pseudo reg. */
902 #define REG_OK_FOR_BASE_P(X) \
903 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
905 /* Nonzero if X is a hard reg that can be used as an index
906 or if it is a pseudo reg. */
907 #define REG_OK_FOR_INDEX_P(X) \
908 (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
910 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
911 or if X is a pseudo reg. */
912 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
913 ((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
917 /* Nonzero if X is a hard reg that can be used as a base reg. */
918 #define REG_OK_FOR_BASE_P(X) \
919 REGNO_OK_FOR_BASE_P (REGNO (X))
921 /* Nonzero if X is a hard reg that can be used as an index. */
922 #define REG_OK_FOR_INDEX_P(X) \
923 REGNO_OK_FOR_INDEX_P (REGNO (X))
925 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
926 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
927 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && OFFSET == 0)
931 /* The 'Q' constraint is a pc relative load operand. */
932 #define EXTRA_CONSTRAINT_Q(OP) \
933 (GET_CODE (OP) == MEM && \
934 ((GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
935 || (GET_CODE (XEXP (OP, 0)) == CONST \
936 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS \
937 && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == LABEL_REF \
938 && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT)))
940 #define EXTRA_CONSTRAINT(OP, C) \
941 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
944 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
945 that is a valid memory address for an instruction.
946 The MODE argument is the machine mode for the MEM expression
947 that wants to use this address.
949 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
951 #define MODE_DISP_OK_4(X,MODE) \
952 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
953 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && MODE == SFmode))
954 #define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3)))
956 #define BASE_REGISTER_RTX_P(X) \
957 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
958 || (GET_CODE (X) == SUBREG \
959 && GET_CODE (SUBREG_REG (X)) == REG \
960 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
962 /* Since this must be r0, which is a single register class, we must check
963 SUBREGs more carefully, to be sure that we don't accept one that extends
964 outside the class. */
965 #define INDEX_REGISTER_RTX_P(X) \
966 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
967 || (GET_CODE (X) == SUBREG \
968 && GET_CODE (SUBREG_REG (X)) == REG \
969 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X))))
971 /* Jump to LABEL if X is a valid address RTX. This must also take
972 REG_OK_STRICT into account when deciding about valid registers, but it uses
973 the above macros so we are in luck.
981 /* ??? The SH3e does not have the REG+disp addressing mode when loading values
982 into the FRx registers. We implement this by setting the maximum offset
983 to zero when the value is SFmode. This also restricts loading of SFmode
984 values into the integer registers, but that can't be helped. */
986 /* The SH allows a displacement in a QI or HI amode, but only when the
987 other operand is R0. GCC doesn't handle this very well, so we forgo
990 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
991 DI can be any number 0..60. */
993 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
995 if (GET_CODE (OP) == CONST_INT) \
997 if (MODE_DISP_OK_4 (OP, MODE)) goto LABEL; \
998 if (MODE_DISP_OK_8 (OP, MODE)) goto LABEL; \
1002 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1004 if (BASE_REGISTER_RTX_P (X)) \
1006 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1007 && BASE_REGISTER_RTX_P (XEXP (X, 0))) \
1009 else if (GET_CODE (X) == PLUS) \
1011 rtx xop0 = XEXP (X, 0); \
1012 rtx xop1 = XEXP (X, 1); \
1013 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
1014 GO_IF_LEGITIMATE_INDEX (MODE, xop1, LABEL); \
1015 if (GET_MODE_SIZE (MODE) <= 4) \
1017 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
1019 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
1025 /* Try machine-dependent ways of modifying an illegitimate address
1026 to be legitimate. If we find one, return the new, valid address.
1027 This macro is used in only one place: `memory_address' in explow.c.
1029 OLDX is the address as it was before break_out_memory_refs was called.
1030 In some cases it is useful to look at this to decide what needs to be done.
1032 MODE and WIN are passed so that this macro can use
1033 GO_IF_LEGITIMATE_ADDRESS.
1035 It is always safe for this macro to do nothing. It exists to recognize
1036 opportunities to optimize the output. */
1038 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) ;
1040 /* Go to LABEL if ADDR (a legitimate address expression)
1041 has an effect that depends on the machine mode it is used for. */
1042 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1044 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
1048 /* Specify the machine mode that this machine uses
1049 for the index in the tablejump instruction. */
1050 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
1052 /* Define this if the tablejump instruction expects the table
1053 to contain offsets from the address of the table.
1054 Do not define this if the table should contain absolute addresses. */
1055 #define CASE_VECTOR_PC_RELATIVE
1057 /* Specify the tree operation to be used to convert reals to integers. */
1058 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1060 /* This is the kind of divide that is easiest to do in the general case. */
1061 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1063 /* Since the SH3e has only `float' support, it is desirable to make all
1064 floating point types equivalent to `float'. */
1065 #define DOUBLE_TYPE_SIZE (TARGET_SH3E ? 32 : 64)
1067 /* 'char' is signed by default. */
1068 #define DEFAULT_SIGNED_CHAR 1
1070 /* The type of size_t unsigned int. */
1071 #define SIZE_TYPE "unsigned int"
1073 #define WCHAR_TYPE "short unsigned int"
1074 #define WCHAR_TYPE_SIZE 16
1076 /* Don't cse the address of the function being compiled. */
1077 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
1079 /* Max number of bytes we can move from memory to memory
1080 in one reasonably fast instruction. */
1083 /* Define if operations between registers always perform the operation
1084 on the full register even if a narrower mode is specified. */
1085 #define WORD_REGISTER_OPERATIONS
1087 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1088 will either zero-extend or sign-extend. The value of this macro should
1089 be the code that says which one of the two operations is implicitly
1090 done, NIL if none. */
1091 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
1093 /* Define this if zero-extension is slow (more than one real instruction).
1094 On the SH, it's only one instruction. */
1095 /* #define SLOW_ZERO_EXTEND */
1097 /* Nonzero if access to memory by bytes is slow and undesirable. */
1098 #define SLOW_BYTE_ACCESS 0
1100 /* We assume that the store-condition-codes instructions store 0 for false
1101 and some other value for true. This is the value stored for true. */
1103 #define STORE_FLAG_VALUE 1
1105 /* Immediate shift counts are truncated by the output routines (or was it
1106 the assembler?). Shift counts in a register are truncated by SH. Note
1107 that the native compiler puts too large (> 32) immediate shift counts
1108 into a register and shifts by the register, letting the SH decide what
1109 to do instead of doing that itself. */
1110 /* ??? This is defined, but the library routines in lib1funcs.asm do not
1111 truncate the shift count. This may result in incorrect results for
1112 unusual cases. Truncating the shift counts in the library routines would
1113 make them faster. However, the SH3 has hardware shifts that do not
1114 truncate, so it appears that we need to leave this undefined for correct
1115 SH3 code. We can still using truncation in the library routines though to
1116 make them faster. */
1117 #define SHIFT_COUNT_TRUNCATED 1
1119 /* All integers have the same format so truncation is easy. */
1120 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1122 /* Define this if addresses of constant functions
1123 shouldn't be put through pseudo regs where they can be cse'd.
1124 Desirable on machines where ordinary constants are expensive
1125 but a CALL with constant address is cheap. */
1126 /*#define NO_FUNCTION_CSE 1*/
1128 /* Chars and shorts should be passed as ints. */
1129 #define PROMOTE_PROTOTYPES 1
1131 /* The machine modes of pointers and functions. */
1132 #define Pmode SImode
1133 #define FUNCTION_MODE Pmode
1135 /* The relative costs of various types of constants. Note that cse.c defines
1136 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1138 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1140 if (INTVAL (RTX) == 0) \
1142 else if (CONST_OK_FOR_I (INTVAL (RTX))) \
1144 else if ((OUTER_CODE == AND || OUTER_CODE == IOR || OUTER_CODE == XOR) \
1145 && CONST_OK_FOR_L (INTVAL (RTX))) \
1153 case CONST_DOUBLE: \
1156 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1158 return COSTS_N_INSNS (andcosts (X)); \
1160 return COSTS_N_INSNS (multcosts (X)); \
1164 return COSTS_N_INSNS (shiftcosts (X)) ; \
1169 return COSTS_N_INSNS (20); \
1174 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1175 are actually function calls with some special constraints on arguments
1178 These macros tell reorg that the references to arguments and
1179 register clobbers for insns of type sfunc do not appear to happen
1180 until after the millicode call. This allows reorg to put insns
1181 which set the argument registers into the delay slot of the millicode
1182 call -- thus they act more like traditional CALL_INSNs.
1184 get_attr_type will try to recognize the given insn, so make sure to
1185 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1188 #define INSN_SETS_ARE_DELAYED(X) \
1189 ((GET_CODE (X) == INSN \
1190 && GET_CODE (PATTERN (X)) != SEQUENCE \
1191 && GET_CODE (PATTERN (X)) != USE \
1192 && GET_CODE (PATTERN (X)) != CLOBBER \
1193 && get_attr_type (X) == TYPE_SFUNC))
1195 #define INSN_REFERENCES_ARE_DELAYED(X) \
1196 ((GET_CODE (X) == INSN \
1197 && GET_CODE (PATTERN (X)) != SEQUENCE \
1198 && GET_CODE (PATTERN (X)) != USE \
1199 && GET_CODE (PATTERN (X)) != CLOBBER \
1200 && get_attr_type (X) == TYPE_SFUNC))
1202 /* Compute the cost of an address. For the SH, all valid addresses are
1204 /* ??? Perhaps we should make reg+reg addresses have higher cost because
1205 they add to register pressure on r0. */
1207 #define ADDRESS_COST(RTX) 1
1209 /* Compute extra cost of moving data between one register class
1212 On the SH it is hard to move into the T reg, but simple to load
1215 #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
1216 (((DSTCLASS == T_REGS) || (DSTCLASS == PR_REG)) ? 10 \
1217 : ((DSTCLASS == FP_REGS && SRCCLASS == GENERAL_REGS) \
1218 || (DSTCLASS == GENERAL_REGS && SRCCLASS == FP_REGS)) ? 4 \
1221 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1222 would be so that people would slow memory systems could generate
1223 different code that does fewer memory accesses. */
1225 /* Assembler output control. */
1227 /* A C string constant describing how to begin a comment in the target
1228 assembler language. The compiler assumes that the comment will end at
1229 the end of the line. */
1230 #define ASM_COMMENT_START "!"
1232 /* The text to go at the start of the assembler file. */
1233 #define ASM_FILE_START(STREAM) \
1234 output_file_start (STREAM)
1236 #define ASM_FILE_END(STREAM)
1238 #define ASM_APP_ON ""
1239 #define ASM_APP_OFF ""
1240 #define FILE_ASM_OP "\t.file\n"
1241 #define IDENT_ASM_OP "\t.ident\n"
1242 #define SET_ASM_OP ".set"
1244 /* How to change between sections. */
1246 #define TEXT_SECTION_ASM_OP "\t.text"
1247 #define DATA_SECTION_ASM_OP "\t.data"
1248 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n"
1249 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n"
1250 #define EXTRA_SECTIONS in_ctors, in_dtors
1251 #define EXTRA_SECTION_FUNCTIONS \
1255 if (in_section != in_ctors) \
1257 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1258 in_section = in_ctors; \
1264 if (in_section != in_dtors) \
1266 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1267 in_section = in_dtors; \
1271 /* Define this so that jump tables go in same section as the current function,
1272 which could be text or it could be a user defined section. */
1273 #define JUMP_TABLES_IN_TEXT_SECTION
1275 /* A C statement to output something to the assembler file to switch to section
1276 NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
1277 NULL_TREE. Some target formats do not support arbitrary sections. Do not
1278 define this macro in such cases. */
1280 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME) \
1281 do { fprintf (FILE, ".section\t%s\n", NAME); } while (0)
1283 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
1284 do { ctors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1286 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
1287 do { dtors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1289 #undef DO_GLOBAL_CTORS_BODY
1291 #define DO_GLOBAL_CTORS_BODY \
1293 typedef (*pfunc)(); \
1294 extern pfunc __ctors[]; \
1295 extern pfunc __ctors_end[]; \
1297 for (p = __ctors_end; p > __ctors; ) \
1303 #undef DO_GLOBAL_DTORS_BODY
1304 #define DO_GLOBAL_DTORS_BODY \
1306 typedef (*pfunc)(); \
1307 extern pfunc __dtors[]; \
1308 extern pfunc __dtors_end[]; \
1310 for (p = __dtors; p < __dtors_end; p++) \
1316 #define ASM_OUTPUT_REG_PUSH(file, v) \
1317 fprintf (file, "\tmov.l r%s,-@r15\n", v);
1319 #define ASM_OUTPUT_REG_POP(file, v) \
1320 fprintf (file, "\tmov.l @r15+,r%s\n", v);
1322 /* The assembler's names for the registers. RFP need not always be used as
1323 the Real framepointer; it can also be used as a normal general register.
1324 Note that the name `fp' is horribly misleading since `fp' is in fact only
1325 the argument-and-return-context pointer. */
1326 #define REGISTER_NAMES \
1328 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1329 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1330 "ap", "pr", "t", "gbr", "mach","macl", "fpul", "X", \
1331 "fr0","fr1","fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1332 "fr8","fr9","fr10","fr11","fr12","fr13","fr14","fr15",\
1335 /* DBX register number for a given compiler register number. */
1336 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
1338 #define DBX_REGISTER_NUMBER(REGNO) \
1339 (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO))
1341 /* Output a label definition. */
1342 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1343 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1345 /* This is how to output an assembler line
1346 that says to advance the location counter
1347 to a multiple of 2**LOG bytes. */
1349 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1351 fprintf (FILE, "\t.align %d\n", LOG)
1353 /* Output a function label definition. */
1354 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1355 ASM_OUTPUT_LABEL(STREAM, NAME)
1357 /* Output a globalising directive for a label. */
1358 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1359 (fprintf (STREAM, "\t.global\t"), \
1360 assemble_name (STREAM, NAME), \
1361 fputc ('\n',STREAM))
1363 /* Output a reference to a label. */
1364 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1365 fprintf (STREAM, "_%s", NAME)
1367 /* Make an internal label into a string. */
1368 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1369 sprintf (STRING, "*%s%d", PREFIX, NUM)
1371 /* Output an internal label definition. */
1372 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1373 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1375 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1377 /* Construct a private name. */
1378 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1379 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1380 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1382 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
1383 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1384 fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM);
1386 /* Output a relative address table. */
1388 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1389 if (TARGET_BIGTABLE) \
1390 fprintf (STREAM, "\t.long L%d-L%d\n", VALUE,REL); \
1392 fprintf (STREAM, "\t.word L%d-L%d\n", VALUE,REL); \
1394 /* Output an absolute table element. */
1396 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1397 if (TARGET_BIGTABLE) \
1398 fprintf (STREAM, "\t.long L%d\n", VALUE); \
1400 fprintf (STREAM, "\t.word L%d\n", VALUE); \
1402 /* Output various types of constants. */
1404 /* This is how to output an assembler line defining a `double'. */
1406 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1407 do { char dstr[30]; \
1408 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1409 fprintf (FILE, "\t.double %s\n", dstr); \
1412 /* This is how to output an assembler line defining a `float' constant. */
1413 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1414 do { char dstr[30]; \
1415 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1416 fprintf (FILE, "\t.float %s\n", dstr); \
1419 #define ASM_OUTPUT_INT(STREAM, EXP) \
1420 (fprintf (STREAM, "\t.long\t"), \
1421 output_addr_const (STREAM, (EXP)), \
1422 fputc ('\n', STREAM))
1424 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1425 (fprintf (STREAM, "\t.short\t"), \
1426 output_addr_const (STREAM, (EXP)), \
1427 fputc ('\n', STREAM))
1429 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1430 (fprintf (STREAM, "\t.byte\t"), \
1431 output_addr_const (STREAM, (EXP)), \
1432 fputc ('\n', STREAM))
1434 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1435 fprintf (STREAM, "\t.byte\t%d\n", VALUE) \
1437 /* Align loops and labels after unconditional branches to get faster
1440 #define ASM_OUTPUT_LOOP_ALIGN(FILE) \
1441 if (! TARGET_SMALLCODE) \
1442 ASM_OUTPUT_ALIGN ((FILE), 2)
1444 #define ASM_OUTPUT_ALIGN_CODE(FILE) \
1445 if (! TARGET_SMALLCODE) \
1446 ASM_OUTPUT_ALIGN ((FILE), (TARGET_SH3 || TARGET_SH3E) ? 4 : 2)
1448 /* This is how to output an assembler line
1449 that says to advance the location counter by SIZE bytes. */
1451 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1452 fprintf (FILE, "\t.space %d\n", (SIZE))
1454 /* This says how to output an assembler line
1455 to define a global common symbol. */
1457 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1458 ( fputs ("\t.comm ", (FILE)), \
1459 assemble_name ((FILE), (NAME)), \
1460 fprintf ((FILE), ",%d\n", (SIZE)))
1462 /* This says how to output an assembler line
1463 to define a local common symbol. */
1465 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
1466 ( fputs ("\t.lcomm ", (FILE)), \
1467 assemble_name ((FILE), (NAME)), \
1468 fprintf ((FILE), ",%d\n", (SIZE)))
1470 /* The assembler's parentheses characters. */
1471 #define ASM_OPEN_PAREN "("
1472 #define ASM_CLOSE_PAREN ")"
1474 /* Target characters. */
1475 #define TARGET_BELL 007
1476 #define TARGET_BS 010
1477 #define TARGET_TAB 011
1478 #define TARGET_NEWLINE 012
1479 #define TARGET_VT 013
1480 #define TARGET_FF 014
1481 #define TARGET_CR 015
1483 /* Only perform branch elimination (by making instructions conditional) if
1484 we're optimizing. Otherwise it's of no use anyway. */
1485 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1486 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1488 /* Print operand X (an rtx) in assembler syntax to file FILE.
1489 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1490 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1492 #define PRINT_OPERAND(STREAM, X, CODE) print_operand (STREAM, X, CODE)
1494 /* Print a memory address as an operand to reference that memory location. */
1496 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address (STREAM, X)
1498 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1499 ((CHAR)=='.' || (CHAR) == '#' || (CHAR)=='@')
1501 extern struct rtx_def *sh_compare_op0;
1502 extern struct rtx_def *sh_compare_op1;
1503 extern struct rtx_def *prepare_scc_operands();
1505 /* Which processor to schedule for. The elements of the enumeration must
1506 match exactly the cpu attribute in the sh.md file. */
1508 enum processor_type {
1516 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
1517 extern enum processor_type sh_cpu;
1519 /* Declare functions defined in sh.c and used in templates. */
1521 extern char *output_branch();
1522 extern char *output_shift();
1523 extern char *output_movedouble();
1524 extern char *output_movepcrel();
1525 extern char *output_jump_label_table();
1526 extern char *output_far_jump();
1528 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
1530 /* Generate calls to memcpy, memcmp and memset. */
1532 #define TARGET_MEM_FUNCTIONS
1534 /* Define this macro if you want to implement any pragmas. If defined, it
1535 is a C expression to be executed when #pragma is seen. The
1536 argument FILE is the stdio input stream from which the source
1537 text can be read. CH is the first character after the #pragma. The
1538 result of the expression is the terminating character found
1539 (newline or EOF). */
1540 #define HANDLE_PRAGMA(FILE, NODE) handle_pragma (FILE, NODE)
1542 /* Set when processing a function with pragma interrupt turned on. */
1544 extern int pragma_interrupt;
1546 #define MOVE_RATIO (TARGET_SMALLCODE ? 2 : 16)
1548 /* Instructions with unfilled delay slots take up an extra two bytes for
1549 the nop in the delay slot. Instructions at the start of loops, or
1550 after unconditional branches, may take up extra room when they are
1551 aligned. ??? We would get more accurate results if we did instruction
1552 alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
1553 here is too conservative. */
1555 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1556 if (((GET_CODE (X) == INSN \
1557 && GET_CODE (PATTERN (X)) != SEQUENCE \
1558 && GET_CODE (PATTERN (X)) != USE \
1559 && GET_CODE (PATTERN (X)) != CLOBBER) \
1560 || GET_CODE (X) == CALL_INSN \
1561 || (GET_CODE (X) == JUMP_INSN \
1562 && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \
1563 && GET_CODE (PATTERN (X)) != ADDR_VEC)) \
1564 && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \
1566 if (! TARGET_SMALLCODE) \
1569 for (aip = PREV_INSN (X); aip; aip = PREV_INSN (aip)) \
1571 if (GET_CODE (aip) == BARRIER) \
1573 if (TARGET_SH3 || TARGET_SH3E) \
1579 else if ((GET_CODE (aip) == NOTE \
1580 && NOTE_LINE_NUMBER (aip) == NOTE_INSN_LOOP_BEG)) \
1585 else if (GET_CODE (aip) != NOTE \
1586 && GET_CODE (aip) != CODE_LABEL) \
1591 /* Enable a bug fix for the shorten_branches pass. */
1592 #define SHORTEN_WITH_ADJUST_INSN_LENGTH
1594 /* Define the codes that are matched by predicates in sh.c. */
1595 #define PREDICATE_CODES \
1596 {"arith_reg_operand", {SUBREG, REG}}, \
1597 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1598 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
1599 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
1600 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1601 {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}},
1603 /* Define this macro if it is advisable to hold scalars in registers
1604 in a wider mode than that declared by the program. In such cases,
1605 the value is constrained to be within the bounds of the declared
1606 type, but kept valid in the wider mode. The signedness of the
1607 extension may differ from that of the type.
1609 Leaving the unsignedp unchanged gives better code than always setting it
1610 to 0. This is despite the fact that we have only signed char and short
1611 load instructions. */
1612 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1613 if (GET_MODE_CLASS (MODE) == MODE_INT \
1614 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1617 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
1618 extensions applied to char/short functions arguments. Defining
1619 PROMOTE_FUNCTION_RETURN does the same for function returns. */
1621 #define PROMOTE_FUNCTION_ARGS
1622 #define PROMOTE_FUNCTION_RETURN
1624 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
1625 and poping arguments. However, we do have push/pop instructions, and
1626 rather limited offsets (4 bits) in load/store instructions, so it isn't
1627 clear if this would give better code. If implemented, should check for
1628 compatibility problems. */
1630 /* ??? Define ADJUST_COSTS? */
1632 /* Since the SH architecture lacks negative address offsets,
1633 the givs should be sorted smallest to largest so combine_givs
1634 has maximum opportunity to combine givs. */
1635 #define GIV_SORT_CRITERION(X, Y) \
1636 if (GET_CODE ((X)->add_val) == CONST_INT \
1637 && GET_CODE ((Y)->add_val) == CONST_INT) \
1638 return INTVAL ((X)->add_val) - INTVAL ((Y)->add_val);
1640 /* For the sake of libgcc2.c, indicate target supports atexit. */