1 /* Definitions of target machine for GNU compiler,
3 Copyright (C) 1993, 1994 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com)
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
24 /* Run-time Target Specification. */
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
30 /* Generate SDB debugging information. */
32 #define SDB_DEBUGGING_INFO 1
34 /* Output DBX (stabs) debugging information if doing -gstabs. */
36 #define DBX_DEBUGGING_INFO
38 /* Generate SDB debugging information by default. */
40 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
44 #define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__}"
46 #define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
48 #define ASM_SPEC "%{ml:-little}"
50 #define LINK_SPEC "%{ml:-m shl}"
52 /* Show we can debug even without a frame pointer. */
53 #define CAN_DEBUG_WITHOUT_FP
56 #define CONDITIONAL_REGISTER_USAGE \
57 /* Experimental calling convention with fewer saved registers */ \
60 call_used_regs[8] = 1; \
61 call_used_regs[9] = 1; \
62 call_used_regs[10] = 1; \
63 call_used_regs[11] = 1; \
65 /* Hitachi saves and restores mac registers on call */ \
68 call_used_regs[MACH_REG] = 0; \
69 call_used_regs[MACL_REG] = 0; \
73 /* Run-time compilation parameters selecting different hardware subsets. */
75 extern int target_flags;
76 #define ISIZE_BIT (1<<1)
77 #define FAST_BIT (1<<2)
78 #define MAC_BIT (1<<3)
79 #define RTL_BIT (1<<4)
81 #define DALIGN_BIT (1<<6)
82 #define SH0_BIT (1<<7)
83 #define SH1_BIT (1<<8)
84 #define SH2_BIT (1<<9)
85 #define SH3_BIT (1<<10)
88 #define SPACE_BIT (1<<13)
89 #define BIGTABLE_BIT (1<<14)
90 #define TRYR0_BIT (1<<15)
91 #define NOSAVE_BIT (1<<16)
92 #define SMALLCALL_BIT (1<<17)
93 #define CONSTLEN_2_BIT (1<<20)
94 #define CONSTLEN_3_BIT (1<<21)
95 #define HITACHI_BIT (1<<22)
96 #define PARANOID_BIT (1<<23)
97 #define RETR2_BIT (1<<24)
98 #define CONSTLEN_0_BIT (1<<25)
99 #define BSR_BIT (1<<26)
100 #define SHORTADDR_BIT (1<<27)
101 #define PACKSTRUCT_BIT (1<<28)
102 #define LITTLE_ENDIAN_BIT (1<<29)
104 /* Nonzero if we should generate code using type 0 insns */
105 #define TARGET_SH0 (target_flags & SH0_BIT)
107 /* Nonzero if we should generate code using type 1 insns */
108 #define TARGET_SH1 (target_flags & SH1_BIT)
110 /* Nonzero if we should generate code using type 2 insns */
111 #define TARGET_SH2 (target_flags & SH2_BIT)
113 /* Nonzero if we should generate code using type 3 insns */
114 #define TARGET_SH3 (target_flags & SH3_BIT)
116 /* Nonzero if we should generate faster code rather than smaller code */
117 #define TARGET_FASTCODE (target_flags & FAST_BIT)
119 /* Nonzero if we should generate faster code rather than smaller code */
120 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
122 /* Nonzero if we should dump out instruction size info */
123 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
125 /* Nonzero if we should try to generate mac instructions */
126 #define TARGET_MAC (target_flags & MAC_BIT)
128 /* Nonzero if we should dump the rtl in the assembly file. */
129 #define TARGET_DUMP_RTL (target_flags & RTL_BIT)
131 /* Nonzero if we should dump the rtl somewher else. */
132 #define TARGET_DUMP_R (target_flags & R_BIT)
134 /* Nonzero to align doubles on 64 bit boundaries */
135 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
137 /* Nonzero to use long jump tables */
138 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
140 /* Nonzero if combine dumping wanted */
141 #define TARGET_CDUMP (target_flags & C_BIT)
143 /* Nonzero if trying to use reg+disp for QIs and HIs. This
145 #define TARGET_TRYR0 (target_flags & TRYR0_BIT)
147 /* Nonzero if using no save calling convention */
148 #define TARGET_NOSAVE (target_flags & NOSAVE_BIT)
150 /* Nonzero if using no save calling convention */
151 #define TARGET_SMALLCALL (target_flags & SMALLCALL_BIT)
153 /* Select max size of computed constant code sequences to be 3 insns */
154 #define TARGET_CLEN3 (target_flags & CONSTLEN_3_BIT)
156 /* Select max size of computed constant code sequences to be 0 insns - ie don't do it */
157 #define TARGET_CLEN0 (target_flags & CONSTLEN_0_BIT)
159 /* Nonzero if using Hitachi's calling convention */
160 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
162 #define TARGET_PARANOID (target_flags & PARANOID_BIT)
163 #define TARGET_RETR2 (target_flags & RETR2_BIT)
164 #define TARGET_SHORTADDR (target_flags & SHORTADDR_BIT)
165 #define TARGET_BSR (target_flags & BSR_BIT)
167 /* Nonzero if packing structures as small as they'll go (incompatible with Hitachi's compiler) */
168 #define TARGET_PACKSTRUCT (target_flags & PACKSTRUCT_BIT)
171 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
173 #define TARGET_SWITCHES \
174 { {"0", (SH0_BIT) }, \
178 {"3l", (SH3_BIT|LITTLE_ENDIAN_BIT)}, \
180 {"ac", (MAC_BIT) }, \
181 {"b", (-LITTLE_ENDIAN_BIT) }, \
182 {"bigtable", (BIGTABLE_BIT)}, \
183 {"bsr", (BSR_BIT) }, \
185 {"clen0", (CONSTLEN_0_BIT) }, \
186 {"clen3", (CONSTLEN_3_BIT) }, \
187 {"dalign", (DALIGN_BIT) }, \
188 {"hitachi", (HITACHI_BIT) }, \
189 {"isize", (ISIZE_BIT) }, \
190 {"l", (LITTLE_ENDIAN_BIT) }, \
191 {"nosave", (NOSAVE_BIT) }, \
192 {"packstruct",(PACKSTRUCT_BIT) }, \
193 {"paranoid", (PARANOID_BIT) }, \
195 {"r2", (RETR2_BIT) }, \
196 {"shortaddr", (SHORTADDR_BIT) }, \
197 {"smallcall", (SMALLCALL_BIT) }, \
198 {"space", (SPACE_BIT) }, \
199 {"try-r0", (TRYR0_BIT)}, \
200 {"", TARGET_DEFAULT} \
204 #define TARGET_DEFAULT (FAST_BIT)
207 /* Macro to define table for command options with values. */
208 #define TARGET_OPTIONS \
209 { { "maxsi-", &max_si}, \
210 { "maxhi-", &max_hi} }
213 #define OVERRIDE_OPTIONS \
221 sh_cpu = CPU_SH3|CPU_SH2; \
223 /* We *MUST* always define optimize since we *HAVE* to run \
224 shorten branches to get correct code. */ \
227 flag_delayed_branch = 1; \
228 /* But never run scheduling before reload, since than can \
229 break global alloc, and generates slower code anyway due \
230 to the pressure on R0. */ \
231 flag_schedule_insns = 0; \
233 max_count_si = atoi (max_si); \
235 max_count_si = 1010; \
237 max_count_hi = atoi (max_hi); \
239 max_count_hi = 500; \
241 flag_no_function_cse = 1; \
245 /* Target machine storage Layout. */
247 /* Define to use software floating point emulator for REAL_ARITHMETIC and
248 decimal <-> binary conversion. */
249 #define REAL_ARITHMETIC
251 /* Define this if most significant bit is lowest numbered
252 in instructions that operate on numbered bit-fields. */
254 #define BITS_BIG_ENDIAN 0
257 /* Define this if most significant byte of a word is the lowest numbered. */
258 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
260 /* Define this if most significant word of a multiword number is the lowest
262 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
265 /* Define this to set the endianness to use in libgcc2.c, which can
266 not depend on target_flags. */
267 #if defined(__LITTLE_ENDIAN__)
268 #define LIBGCC2_WORDS_BIG_ENDIAN 0
270 #define LIBGCC2_WORDS_BIG_ENDIAN 1
273 /* Number of bits in an addressable storage unit */
274 #define BITS_PER_UNIT 8
276 /* Width in bits of a "word", which is the contents of a machine register.
277 Note that this is not necessarily the width of data type `int';
278 if using 16-bit ints on a 68000, this would still be 32.
279 But on a machine with 16-bit registers, this would be 16. */
280 #define BITS_PER_WORD 32
281 #define MAX_BITS_PER_WORD 32
283 /* Width of a word, in units (bytes). */
284 #define UNITS_PER_WORD 4
286 /* Width in bits of a pointer.
287 See also the macro `Pmode' defined below. */
288 #define POINTER_SIZE 32
290 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
291 #define PARM_BOUNDARY 32
293 /* Boundary (in *bits*) on which stack pointer should be aligned. */
294 #define STACK_BOUNDARY 32
296 /* Allocation boundary (in *bits*) for the code of a function. */
297 #define FUNCTION_BOUNDARY 16
299 /* Alignment of field after `int : 0' in a structure. */
300 #define EMPTY_FIELD_BOUNDARY 32
302 /* No data type wants to be aligned rounder than this. */
303 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
305 /* The best alignment to use in cases where we have a choice. */
306 #define FASTEST_ALIGNMENT 32
308 /* Make strings word-aligned so strcpy from constants will be faster. */
309 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
310 ((TREE_CODE (EXP) == STRING_CST \
311 && (ALIGN) < FASTEST_ALIGNMENT) \
312 ? FASTEST_ALIGNMENT : (ALIGN))
314 /* Make arrays of chars word-aligned for the same reasons. */
315 #define DATA_ALIGNMENT(TYPE, ALIGN) \
316 (TREE_CODE (TYPE) == ARRAY_TYPE \
317 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
318 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
320 /* Number of bits which any structure or union's size must be a
321 multiple of. Each structure or union's size is rounded up to a
323 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PACKSTRUCT ? 8 : 32)
325 /* Set this nonzero if move instructions will actually fail to work
326 when given unaligned data. */
327 #define STRICT_ALIGNMENT 1
330 /* Standard register usage. */
332 /* Register allocation for the Hitachi calling convention:
338 r14 frame pointer/call saved
340 ap arg pointer (doesn't really exist, always eliminated)
341 pr subroutine return address
343 mach multiply/accumulate result
347 /* Number of actual hardware registers.
348 The hardware registers are assigned numbers for the compiler
349 from 0 to just below FIRST_PSEUDO_REGISTER.
350 All registers that the compiler knows about must be given numbers,
351 even those that are not normally considered general registers. */
360 #define FIRST_PSEUDO_REGISTER 22
362 /* 1 for registers that have pervasive standard uses
363 and are not available for the register allocator.
365 mach register is fixed 'cause it's only 10 bits wide */
374 #define FIXED_REGISTERS \
383 /* 1 for registers not available across function calls.
384 These must include the FIXED_REGISTERS and also any
385 registers that can be used without being saved.
386 The latter must include the registers where values are returned
387 and the register where structure-value addresses are passed.
388 Aside from that, you can include as many other registers as you like. */
397 #define CALL_USED_REGISTERS \
405 /* Return number of consecutive hard regs needed starting at reg REGNO
406 to hold something of mode MODE.
407 This is ordinarily the length in words of a value of mode MODE
408 but can be less for certain modes in special long registers.
410 On the SH regs are UNITS_PER_WORD bits wide; */
412 #define HARD_REGNO_NREGS(REGNO, MODE) \
413 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
415 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
416 We may keep double values in even registers */
418 extern int hard_regno_mode_ok[];
419 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
420 (hard_regno_mode_ok[REGNO] & (1<<(int)MODE))
422 /* Value is 1 if it is a good idea to tie two pseudo registers
423 when one has mode MODE1 and one has mode MODE2.
424 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
425 for any hard reg, then this must be 0 for correct output. */
427 #define MODES_TIEABLE_P(MODE1, MODE2) \
428 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
430 /* Specify the registers used for certain standard purposes.
431 The values of these macros are register numbers. */
433 /* Define this if the program counter is overloaded on a register. */
434 /* #define PC_REGNUM 15*/
436 /* Register to use for pushing function arguments. */
437 #define STACK_POINTER_REGNUM 15
439 /* Base register for access to local variables of the function. */
440 #define FRAME_POINTER_REGNUM 14
442 /* Value should be nonzero if functions must have frame pointers.
443 Zero means the frame pointer need not be set up (and parms may be accessed
444 via the stack pointer) in functions that seem suitable. */
446 #define FRAME_POINTER_REQUIRED 0
448 /* Definitions for register eliminations.
450 We have two registers that can be eliminated on the m88k. First, the
451 frame pointer register can often be eliminated in favor of the stack
452 pointer register. Secondly, the argument pointer register can always be
453 eliminated; it is replaced with either the stack or frame pointer. */
455 /* This is an array of structures. Each structure initializes one pair
456 of eliminable registers. The "from" register number is given first,
457 followed by "to". Eliminations of the same "from" register are listed
458 in order of preference. */
460 /* This is an array of structures. Each structure initializes one pair
461 of eliminable registers. The "from" register number is given first,
462 followed by "to". Eliminations of the same "from" register are listed
463 in order of preference. */
465 #define ELIMINABLE_REGS \
466 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
467 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
468 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
471 /* Given FROM and TO register numbers, say whether this elimination
473 #define CAN_ELIMINATE(FROM, TO) \
474 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
476 /* Define the offset between two registers, one to be eliminated, and the other
477 its replacement, at the start of a routine. */
479 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
480 OFFSET = initial_elimination_offset (FROM, TO)
482 /* Base register for access to arguments of the function. */
483 #define ARG_POINTER_REGNUM 16
485 /* Register in which the static-chain is passed to a function. */
486 #define STATIC_CHAIN_REGNUM 13
488 /* The register in which a struct value address is passed */
490 #define STRUCT_VALUE_REGNUM 2
492 /* If the structure value address is not passed in a register, define
493 `STRUCT_VALUE' as an expression returning an RTX for the place
494 where the address is passed. If it returns 0, the address is
495 passed as an "invisible" first argument. */
497 /*#define STRUCT_VALUE ((rtx)0)*/
500 /* Don't default to pcc-struct-return, because we have already specified
501 exactly how to return structures in the RETURN_IN_MEMORY macro. */
503 #define DEFAULT_PCC_STRUCT_RETURN 0
506 /* Define the classes of registers for register constraints in the
507 machine description. Also define ranges of constants.
509 One of the classes must always be named ALL_REGS and include all hard regs.
510 If there is more than one class, another class must be named NO_REGS
511 and contain no registers.
513 The name GENERAL_REGS must be the name of a class (or an alias for
514 another name such as ALL_REGS). This is the class of registers
515 that is allowed by "g" or "r" in a register constraint.
516 Also, registers outside this class are allocated only when
517 instructions express preferences for them.
519 The classes must be numbered in nondecreasing order; that is,
520 a larger-numbered class must never be contained completely
521 in a smaller-numbered class.
523 For any two classes, it is very desirable that there be another
524 class that represents their union. */
526 /* The SH has two sorts of general registers, R0 and the rest. R0 can
527 be used as the destination of some of the arithmetic ops. There are
528 also some special purpose registers; the T bit register, the
529 Procedure Return Register and the Multipy Accumulate Registers */
543 #define N_REG_CLASSES (int) LIM_REG_CLASSES
545 /* Give names of register classes as strings for dump file. */
546 #define REG_CLASS_NAMES \
557 /* Define which registers fit in which classes.
558 This is an initializer for a vector of HARD_REG_SET
559 of length N_REG_CLASSES. */
561 #define REG_CLASS_CONTENTS \
563 0x000000, /* NO_REGS */ \
564 0x000001, /* R0_REGS */ \
565 0x020000, /* PR_REGS */ \
566 0x040000, /* T_REGS */ \
567 0x300000, /* MAC_REGS */ \
568 0x01FFFF, /* GENERAL_REGS */ \
569 0x37FFFF /* ALL_REGS */ \
572 /* The same information, inverted:
573 Return the class number of the smallest class containing
574 reg number REGNO. This could be a conditional expression
575 or could index an array. */
577 extern int regno_reg_class[];
578 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
580 /* When defined, the compiler allows registers explicitly used in the
581 rtl to be used as spill registers but prevents the compiler from
582 extending the lifetime of these registers. */
584 #define SMALL_REGISTER_CLASSES
586 /* The order in which register should be allocated. */
587 #define REG_ALLOC_ORDER \
588 { 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14,15,16,17,18,19,20,21 }
590 /* The class value for index registers, and the one for base regs. */
591 #define INDEX_REG_CLASS R0_REGS
592 #define BASE_REG_CLASS GENERAL_REGS
594 /* Get reg_class from a letter such as appears in the machine
596 extern enum reg_class reg_class_from_letter[];
598 #define REG_CLASS_FROM_LETTER(C) \
599 ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
602 /* The letters I, J, K, L and M in a register constraint string
603 can be used to stand for particular ranges of immediate operands.
604 This macro defines what the ranges are.
605 C is the letter, and VALUE is a constant value.
606 Return 1 if VALUE is in the range specified by C.
607 I: arithmetic operand -127..128, as used in add, sub, etc
608 K: shift operand 1,2,8 or 16
609 L: logical operand 0..255, as used in and, or, etc.
614 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127)
615 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
616 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255)
617 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
618 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
619 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
620 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
621 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
622 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
623 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
624 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
627 /* Similar, but for floating constants, and defining letters G and H.
628 Here VALUE is the CONST_DOUBLE rtx itself. */
630 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
631 ((C) == 'G' ? CONST_OK_FOR_I (CONST_DOUBLE_HIGH (VALUE)) \
632 && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \
635 /* Given an rtx X being reloaded into a reg required to be
636 in class CLASS, return the class of reg to actually use.
637 In general this is just CLASS; but on some machines
638 in some cases it is preferable to use a more restrictive class. */
640 #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
642 /* Return the register class of a scratch register needed to copy IN into
643 or out of a register in CLASS in MODE. If it can be done directly,
644 NO_REGS is returned. */
647 /* Return the maximum number of consecutive registers
648 needed to represent mode MODE in a register of class CLASS.
650 On SH this is the size of MODE in words */
651 #define CLASS_MAX_NREGS(CLASS, MODE) \
652 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
656 /* Stack layout; function entry, exit and calling. */
658 /* Define the number of register that can hold parameters.
659 These two macros are used only in other macro definitions below. */
661 #define FIRST_PARM_REG 4
662 #define FIRST_RET_REG (TARGET_RETR2 ? 2 : 0)
664 /* Define this if pushing a word on the stack
665 makes the stack pointer a smaller address. */
666 #define STACK_GROWS_DOWNWARD
668 /* Define this macro if the addresses of local variable slots are at
669 negative offsets from the frame pointer.
671 The SH only has positive indexes, so grow the frame up
673 /* #define FRAME_GROWS_DOWNWARD */
675 /* Offset from the frame pointer to the first local variable slot to
677 #define STARTING_FRAME_OFFSET 0
679 /* If we generate an insn to push BYTES bytes,
680 this says how many the stack pointer really advances by. */
681 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
683 /* Offset of first parameter from the argument pointer register value. */
684 #define FIRST_PARM_OFFSET(FNDECL) 0
686 /* Value is the number of byte of arguments automatically
687 popped when returning from a subroutine call.
688 FUNTYPE is the data type of the function (as a tree),
689 or for a library call it is an identifier node for the subroutine name.
690 SIZE is the number of bytes of arguments passed on the stack.
692 On the SH, the caller does not pop any of its arguments that were passed
694 #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
696 /* Define how to find the value returned by a function.
697 VALTYPE is the data type of the value (as a tree).
698 If the precise function being called is known, FUNC is its FUNCTION_DECL;
699 otherwise, FUNC is 0. */
701 #define FUNCTION_VALUE(VALTYPE, FUNC) \
703 TYPE_MODE (VALTYPE) == BLKmode ? SImode : TYPE_MODE (VALTYPE), \
706 /* Define how to find the value returned by a library function
707 assuming the value has mode MODE. */
708 #define LIBCALL_VALUE(MODE) \
709 gen_rtx (REG, MODE, FIRST_RET_REG)
711 /* 1 if N is a possible register number for a function value.
712 On the SH, only r0 can return results. */
713 #define FUNCTION_VALUE_REGNO_P(REGNO) \
714 ((REGNO) == FIRST_RET_REG)
716 /* 1 if N is a possible register number for function argument passing.*/
718 #define FUNCTION_ARG_REGNO_P(REGNO) \
719 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
723 /* Define a data type for recording info about an argument list
724 during the scan of that argument list. This data type should
725 hold all necessary information about the function itself
726 and about the args processed so far, enough to enable macros
727 such as FUNCTION_ARG to determine where the next arg should go.
729 On SH, this is a single integer, which is a number of words
730 of arguments scanned so far (including the invisible argument,
731 if any, which holds the structure-value-address).
732 Thus NARGREGS or more means all following args should go on the stack. */
734 #define CUMULATIVE_ARGS int
736 #define ROUND_ADVANCE(SIZE) \
737 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
739 /* Round a register number up to a proper boundary for an arg of mode
742 The SH doesn't care about double alignment, so we only
743 round doubles to even regs when asked to explicitly. */
745 #define ROUND_REG(X, MODE) \
746 ((TARGET_ALIGN_DOUBLE \
747 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
748 ? ((X) + ((X) & 1)) : (X))
751 /* Initialize a variable CUM of type CUMULATIVE_ARGS
752 for a call to a function whose data type is FNTYPE.
753 For a library call, FNTYPE is 0.
755 On SH, the offset always starts at 0: the first parm reg is always
758 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
761 /* Update the data in CUM to advance over an argument
762 of mode MODE and data type TYPE.
763 (TYPE is null for libcalls where that information may not be
766 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
767 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
768 + ((MODE) != BLKmode \
769 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
770 : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
772 /* Define where to put the arguments to a function.
773 Value is zero to push the argument on the stack,
774 or a hard register in which to store the argument.
776 MODE is the argument's machine mode.
777 TYPE is the data type of the argument (as a tree).
778 This is null for libcalls where that information may
780 CUM is a variable of type CUMULATIVE_ARGS which gives info about
781 the preceding args and about the function being called.
782 NAMED is nonzero if this argument is a named parameter
783 (otherwise it is an extra parameter matching an ellipsis).
785 On SH the first args are normally in registers
786 and the rest are pushed. Any arg that starts within the first
787 NPARM_REGS words is at least partially passed in a register unless
788 its data type forbids. */
791 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
792 sh_function_arg (CUM, MODE, TYPE, NAMED)
794 extern struct rtx_def *sh_function_arg();
796 /* For an arg passed partly in registers and partly in memory,
797 this is the number of registers used.
798 For args passed entirely in registers or entirely in memory, zero.
800 We sometimes split args */
802 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
803 sh_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
805 extern int current_function_anonymous_args;
807 /* Perform any needed actions needed for a function that is receiving a
808 variable number of arguments. */
810 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
811 current_function_anonymous_args = 1;
814 /* Call the function profiler with a given profile label. */
816 #define FUNCTION_PROFILER(STREAM,LABELNO) \
818 fprintf(STREAM, " trapa #5\n"); \
819 fprintf(STREAM, " .align 2\n"); \
820 fprintf(STREAM, " .long LP%d\n", (LABELNO)); \
824 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
825 the stack pointer does not matter. The value is tested only in
826 functions that have frame pointers.
827 No definition is equivalent to always zero. */
829 #define EXIT_IGNORE_STACK 1
831 /* Generate the assembly code for function exit
832 Just dump out any accumulated constant table.*/
834 #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue (STREAM, SIZE)
837 /* Output assembler code for a block containing the constant parts
838 of a trampoline, leaving space for the variable parts.
840 On the SH, the trapoline looks like
841 1 0000 D301 mov.l l1,r3
842 2 0002 DD02 mov.l l2,r13
845 5 0008 00000000 l1: .long function
846 6 000c 00000000 l2: .long area
848 #define TRAMPOLINE_TEMPLATE(FILE) \
850 fprintf ((FILE), " .word 0xd301\n"); \
851 fprintf ((FILE), " .word 0xdd02\n"); \
852 fprintf ((FILE), " .word 0x4d2b\n"); \
853 fprintf ((FILE), " .word 0x200b\n"); \
854 fprintf ((FILE), " .long 0\n"); \
855 fprintf ((FILE), " .long 0\n"); \
858 /* Length in units of the trampoline for entering a nested function. */
859 #define TRAMPOLINE_SIZE 16
861 /* Alignment required for a trampoline in units. */
862 #define TRAMPOLINE_ALIGN 4
864 /* Emit RTL insns to initialize the variable parts of a trampoline.
865 FNADDR is an RTX for the address of the function's pure code.
866 CXT is an RTX for the static chain value for the function. */
868 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
870 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
872 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
877 /* Addressing modes, and classification of registers for them. */
878 #define HAVE_POST_INCREMENT 1
879 /*#define HAVE_PRE_INCREMENT 1*/
880 /*#define HAVE_POST_DECREMENT 1*/
881 #define HAVE_PRE_DECREMENT 1
883 /* Macros to check register numbers against specific register classes. */
885 /* These assume that REGNO is a hard or pseudo reg number.
886 They give nonzero only if REGNO is a hard reg of the suitable class
887 or a pseudo reg currently allocated to a suitable hard reg.
888 Since they use reg_renumber, they are safe only once reg_renumber
889 has been allocated, which happens in local-alloc.c.
893 #define REGNO_OK_FOR_BASE_P(REGNO) \
894 ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
895 #define REGNO_OK_FOR_INDEX_P(REGNO) \
896 ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
898 /* Maximum number of registers that can appear in a valid memory
901 #define MAX_REGS_PER_ADDRESS 2
903 /* Recognize any constant value that is a valid address. */
905 #define CONSTANT_ADDRESS_P(X) \
906 (GET_CODE (X) == LABEL_REF)
908 /* Nonzero if the constant value X is a legitimate general operand. */
910 #define LEGITIMATE_CONSTANT_P(X) \
911 (GET_CODE(X) != CONST_DOUBLE /*&& GET_CODE(X) != LABEL_REF*/)
914 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
915 and check its validity for a certain class.
916 We have two alternate definitions for each of them.
917 The usual definition accepts all pseudo regs; the other rejects
918 them unless they have been allocated suitable hard regs.
919 The symbol REG_OK_STRICT causes the latter definition to be used. */
921 #define MODE_DISP_OK_4(X,MODE) ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<64) && (!(INTVAL(X) &3)))
922 #define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3)))
923 #define MODE_DISP_OK_2(X,MODE) ((GET_MODE_SIZE(MODE)==2) && ((unsigned)INTVAL(X)<32) && TARGET_TRYR0 && (!INTVAL(X) &1))
924 #define MODE_DISP_OK_1(X,MODE) ((GET_MODE_SIZE(MODE)==1) && ((unsigned)INTVAL(X)<16) && TARGET_TRYR0)
926 #ifndef REG_OK_STRICT
929 /* Nonzero if X is a hard reg that can be used as a base reg
930 or if it is a pseudo reg. */
931 #define REG_OK_FOR_BASE_P(X) \
932 (REGNO (X) <= 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
933 /* Nonzero if X is a hard reg that can be used as an index
934 or if it is a pseudo reg. */
936 #define REG_OK_FOR_INDEX_P(X) \
937 (REGNO (X) == 0 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
939 #define REG_OK_FOR_PRE_POST_P(X) \
940 (REG_OK_FOR_BASE_P (X))
943 /* Nonzero if X is a hard reg that can be used as a base reg. */
944 #define REG_OK_FOR_BASE_P(X) \
945 REGNO_OK_FOR_BASE_P (REGNO (X))
947 /* Nonzero if X is a hard reg that can be used as an index. */
948 #define REG_OK_FOR_INDEX_P(X) \
949 REGNO_OK_FOR_INDEX_P (REGNO (X))
951 #define REG_OK_FOR_PRE_POST_P(X) \
952 (REGNO_OK_FOR_BASE_P (REGNO (X)))
955 /* The Q is a pc relative load operand */
956 #define EXTRA_CONSTRAINT_Q(OP) \
957 (GET_CODE (OP) == MEM && \
958 ((GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
959 || (GET_CODE (XEXP (OP, 0)) == CONST \
960 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS \
961 && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == LABEL_REF \
962 && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT)))
964 /* The U is a label ref */
965 #define EXTRA_CONSTRAINT_U(OP) \
966 (GET_CODE (OP) == LABEL_REF)
968 #define IS_INDEX(OP) \
969 ((GET_CODE (OP) == PLUS && \
970 (INDEX_REGISTER_RTX_P (XEXP (OP, 0)) && BASE_REGISTER_RTX_P (XEXP (OP, 1))) || \
971 (INDEX_REGISTER_RTX_P (XEXP (OP, 1)) && BASE_REGISTER_RTX_P (XEXP (OP, 0)))))
975 #define EXTRA_CONSTRAINT(OP, C) \
976 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
977 : (C) == 'U' ? EXTRA_CONSTRAINT_U (OP) \
981 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
982 that is a valid memory address for an instruction.
983 The MODE argument is the machine mode for the MEM expression
984 that wants to use this address.
986 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
988 #define BASE_REGISTER_RTX_P(X) \
989 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
991 #define INDEX_REGISTER_RTX_P(X) \
992 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
995 /* Jump to LABEL if X is a valid address RTX. This must also take
996 REG_OK_STRICT into account when deciding about valid registers, but it uses
997 the above macros so we are in luck.
1006 /* The SH allows a displacement in a QI or HI amode, but only when the
1007 other operand is R0. GCC doesn't handle this very well, so we forgo
1010 A legitimate index for a QI or HI is 0, SI and above can be any
1013 #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
1015 if (GET_CODE (OP) == CONST_INT) \
1017 if (MODE_DISP_OK_4 (OP, MODE)) goto LABEL; \
1018 if (MODE_DISP_OK_8 (OP, MODE)) goto LABEL; \
1019 if (MODE_DISP_OK_2 (OP, MODE)) goto LABEL; \
1020 if (MODE_DISP_OK_1 (OP, MODE)) goto LABEL; \
1025 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1027 if (BASE_REGISTER_RTX_P (X)) \
1029 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1030 && GET_CODE (XEXP (X, 0)) == REG \
1031 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1033 else if (GET_CODE (X) == PLUS) \
1035 rtx xop0 = XEXP(X,0); \
1036 rtx xop1 = XEXP(X,1); \
1037 if (GET_MODE_SIZE(MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
1038 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1039 if (GET_MODE_SIZE(MODE) <= 8 && BASE_REGISTER_RTX_P (xop1)) \
1040 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1041 if (GET_MODE_SIZE(MODE)<= 4) { \
1042 if(BASE_REGISTER_RTX_P(xop1) && \
1043 INDEX_REGISTER_RTX_P(xop0)) goto LABEL; \
1044 if(INDEX_REGISTER_RTX_P(xop1) && \
1045 BASE_REGISTER_RTX_P(xop0)) goto LABEL; \
1048 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1049 && GET_CODE (XEXP (X, 0)) == REG \
1050 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1055 /* Try machine-dependent ways of modifying an illegitimate address
1056 to be legitimate. If we find one, return the new, valid address.
1057 This macro is used in only one place: `memory_address' in explow.c.
1059 OLDX is the address as it was before break_out_memory_refs was called.
1060 In some cases it is useful to look at this to decide what needs to be done.
1062 MODE and WIN are passed so that this macro can use
1063 GO_IF_LEGITIMATE_ADDRESS.
1065 It is always safe for this macro to do nothing. It exists to recognize
1066 opportunities to optimize the output.
1070 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) ;
1072 /* Go to LABEL if ADDR (a legitimate address expression)
1073 has an effect that depends on the machine mode it is used for. */
1074 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1076 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1077 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1081 /* Specify the machine mode that this machine uses
1082 for the index in the tablejump instruction. */
1083 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
1085 /* Define this if the tablejump instruction expects the table
1086 to contain offsets from the address of the table.
1087 Do not define this if the table should contain absolute addresses. */
1088 #define CASE_VECTOR_PC_RELATIVE
1090 /* Specify the tree operation to be used to convert reals to integers. */
1091 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1093 /* This is the kind of divide that is easiest to do in the general case. */
1094 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1096 /* 'char' is signed by default */
1097 #define DEFAULT_SIGNED_CHAR 1
1099 /* The type of size_t unsigned int. */
1100 #define SIZE_TYPE "unsigned int"
1102 #define WCHAR_TYPE "short unsigned int"
1103 #define WCHAR_TYPE_SIZE 16
1105 /* Don't cse the address of the function being compiled. */
1106 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
1108 /* Max number of bytes we can move from memory to memory
1109 in one reasonably fast instruction. */
1112 /* Define if operations between registers always perform the operation
1113 on the full register even if a narrower mode is specified. */
1114 #define WORD_REGISTER_OPERATIONS
1116 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1117 will either zero-extend or sign-extend. The value of this macro should
1118 be the code that says which one of the two operations is implicitly
1119 done, NIL if none. */
1120 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
1122 /* Define this if zero-extension is slow (more than one real instruction).
1123 On the SH, it's only one instruction */
1124 /* #define SLOW_ZERO_EXTEND */
1126 /* Nonzero if access to memory by bytes is slow and undesirable. */
1127 #define SLOW_BYTE_ACCESS 0
1129 /* We assume that the store-condition-codes instructions store 0 for false
1130 and some other value for true. This is the value stored for true. */
1132 #define STORE_FLAG_VALUE 1
1134 /* Immediate shift counts are truncated by the output routines (or was it
1135 the assembler?). Shift counts in a register are truncated by ARM. Note
1136 that the native compiler puts too large (> 32) immediate shift counts
1137 into a register and shifts by the register, letting the ARM decide what
1138 to do instead of doing that itself. */
1139 #define SHIFT_COUNT_TRUNCATED 1
1141 /* All integers have the same format so truncation is easy. */
1142 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1144 /* Define this if addresses of constant functions
1145 shouldn't be put through pseudo regs where they can be cse'd.
1146 Desirable on machines where ordinary constants are expensive
1147 but a CALL with constant address is cheap. */
1148 /*#define NO_FUNCTION_CSE 1*/
1150 /* Chars and shorts should be passed as ints. */
1151 #define PROMOTE_PROTOTYPES 1
1153 /* The machine modes of pointers and functions */
1154 #define Pmode SImode
1155 #define FUNCTION_MODE Pmode
1157 /* The relative costs of various types of constants. Note that cse.c defines
1158 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1160 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1162 if (INTVAL(RTX)==0) return 0; \
1163 if (CONST_OK_FOR_I (INTVAL(RTX))) \
1171 case CONST_DOUBLE: \
1174 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1176 return COSTS_N_INSNS (andcosts (X)); \
1178 return COSTS_N_INSNS (multcosts (X)); \
1181 return COSTS_N_INSNS (shiftcosts (X)) ; \
1186 return COSTS_N_INSNS (20); \
1192 /* The multiply and divide insns on the SH are actually function calls
1193 with some special constraints on arguments and register usage.
1195 These macros tell reorg that the references to arguments and
1196 register clobbers for insns of type sfunc do not appear to happen
1197 until after the millicode call. This allows reorg to put insns
1198 which set the argument registers into the delay slot of the millicode
1199 call -- thus they act more like traditional CALL_INSNs.
1201 get_attr_type will try to recognize the given insn, so make sure to
1202 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1205 #define INSN_SETS_ARE_DELAYED(X) \
1206 ((GET_CODE (X) == INSN \
1207 && GET_CODE (PATTERN (X)) != SEQUENCE \
1208 && GET_CODE (PATTERN (X)) != USE \
1209 && GET_CODE (PATTERN (X)) != CLOBBER \
1210 && get_attr_type (X) == TYPE_SFUNC))
1212 #define INSN_REFERENCES_ARE_DELAYED(X) \
1213 ((GET_CODE (X) == INSN \
1214 && GET_CODE (PATTERN (X)) != SEQUENCE \
1215 && GET_CODE (PATTERN (X)) != USE \
1216 && GET_CODE (PATTERN (X)) != CLOBBER \
1217 && get_attr_type (X) == TYPE_SFUNC))
1219 /* Compute extra cost of moving data between one register class
1222 On the SH it is hard to move into the T reg, but simple to load
1226 #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
1227 (((DSTCLASS == T_REGS) || (DSTCLASS == PR_REG)) ? 10 : 1)
1229 /* Assembler output control */
1231 /* The text to go at the start of the assembler file */
1232 #define ASM_FILE_START(STREAM) \
1233 output_file_start (STREAM, f_options, sizeof f_options / sizeof f_options[0], \
1234 W_options, sizeof W_options / sizeof W_options[0]);
1237 #define ASM_FILE_END(STREAM)
1240 #define ASM_APP_ON ""
1241 #define ASM_APP_OFF ""
1242 #define FILE_ASM_OP "\t.file\n"
1243 #define IDENT_ASM_OP "\t.ident\n"
1245 /* How to change between sections. */
1247 #define TEXT_SECTION_ASM_OP "\t.text"
1248 #define DATA_SECTION_ASM_OP "\t.data"
1249 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n"
1250 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n"
1251 #define INIT_SECTION_ASM_OP "\t.section\t.init\n"
1252 #define EXTRA_SECTIONS in_ctors, in_dtors
1253 #define EXTRA_SECTION_FUNCTIONS \
1257 if (in_section != in_ctors) \
1259 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1260 in_section = in_ctors; \
1266 if (in_section != in_dtors) \
1268 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1269 in_section = in_dtors; \
1273 /* A C statement to output something to the assembler file to switch to section
1274 NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
1275 NULL_TREE. Some target formats do not support arbitrary sections. Do not
1276 define this macro in such cases. */
1278 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME) \
1279 do { fprintf (FILE, ".section\t%s\n", NAME); } while (0)
1281 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
1282 do { ctors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1284 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
1285 do { dtors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1287 #undef DO_GLOBAL_CTORS_BODY
1289 #define DO_GLOBAL_CTORS_BODY \
1291 typedef (*pfunc)(); \
1292 extern pfunc __ctors[]; \
1293 extern pfunc __ctors_end[]; \
1295 for (p = __ctors_end; p > __ctors; ) \
1301 #undef DO_GLOBAL_DTORS_BODY
1302 #define DO_GLOBAL_DTORS_BODY \
1304 typedef (*pfunc)(); \
1305 extern pfunc __dtors[]; \
1306 extern pfunc __dtors_end[]; \
1308 for (p = __dtors; p < __dtors_end; p++) \
1315 #define ASM_OUTPUT_REG_PUSH(file, v) \
1316 fprintf (file, "\tmov.l r%s,-@r15\n", v);
1318 #define ASM_OUTPUT_REG_POP(file, v) \
1319 fprintf (file, "\tmov.l @r15+,r%s\n", v);
1322 /* The assembler's names for the registers. RFP need not always be used as
1323 the Real framepointer; it can also be used as a normal general register.
1324 Note that the name `fp' is horribly misleading since `fp' is in fact only
1325 the argument-and-return-context pointer. */
1326 #define REGISTER_NAMES \
1328 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1329 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1330 "ap", "pr", "t", "gbr", "mach","macl" \
1333 /* DBX register number for a given compiler register number */
1334 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1336 /* Output a label definition. */
1337 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1338 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1341 /* This is how to output an assembler line
1342 that says to advance the location counter
1343 to a multiple of 2**LOG bytes. */
1345 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1347 fprintf (FILE, "\t.align %d\n", LOG)
1349 /* Output a function label definition. */
1350 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1351 ASM_OUTPUT_LABEL(STREAM, NAME)
1353 /* Output a globalising directive for a label. */
1354 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1355 (fprintf (STREAM, "\t.global\t"), \
1356 assemble_name (STREAM, NAME), \
1357 fputc ('\n',STREAM)) \
1359 /* Output a reference to a label. */
1360 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1361 fprintf (STREAM, "_%s", NAME)
1363 /* Make an internal label into a string. */
1364 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1365 sprintf (STRING, "*%s%d", PREFIX, NUM)
1367 /* Output an internal label definition. */
1368 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1369 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1371 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1373 /* Construct a private name. */
1374 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1375 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1376 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1378 /* Jump tables must be 32 bit aligned, no matter the size of the element */
1379 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1380 fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM);
1382 /* Output a relative address table. */
1384 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1385 if (TARGET_BIGTABLE) \
1386 fprintf (STREAM, "\t.long L%d-L%d\n", VALUE,REL); \
1388 fprintf (STREAM, "\t.word L%d-L%d\n", VALUE,REL); \
1390 /* Output an absolute table element */
1392 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1393 if (TARGET_BIGTABLE) \
1394 fprintf (STREAM, "\t.long L%d\n", VALUE); \
1396 fprintf (STREAM, "\t.word L%d\n", VALUE); \
1398 /* Output various types of constants. */
1401 /* This is how to output an assembler line defining a `double' */
1403 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1404 do { char dstr[30]; \
1405 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1406 fprintf (FILE, "\t.double %s\n", dstr); \
1410 /* This is how to output an assembler line defining a `float' constant. */
1411 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1412 do { char dstr[30]; \
1413 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1414 fprintf (FILE, "\t.float %s\n", dstr); \
1417 #define ASM_OUTPUT_INT(STREAM, EXP) \
1418 (fprintf (STREAM, "\t.long\t"), \
1419 output_addr_const (STREAM, (EXP)), \
1420 fputc ('\n', STREAM))
1422 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1423 (fprintf (STREAM, "\t.short\t"), \
1424 output_addr_const (STREAM, (EXP)), \
1425 fputc ('\n', STREAM))
1427 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1428 (fprintf (STREAM, "\t.byte\t"), \
1429 output_addr_const (STREAM, (EXP)), \
1430 fputc ('\n', STREAM))
1432 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1433 fprintf (STREAM, "\t.byte\t%d\n", VALUE) \
1435 /* This is how to output an assembler line
1436 that says to advance the location counter by SIZE bytes. */
1438 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1439 fprintf (FILE, "\t.space %d\n", (SIZE))
1441 /* This says how to output an assembler line
1442 to define a global common symbol. */
1444 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1445 ( fputs ("\t.comm ", (FILE)), \
1446 assemble_name ((FILE), (NAME)), \
1447 fprintf ((FILE), ",%d\n", (SIZE)))
1449 /* This says how to output an assembler line
1450 to define a local common symbol. */
1452 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
1453 ( fputs ("\t.lcomm ", (FILE)), \
1454 assemble_name ((FILE), (NAME)), \
1455 fprintf ((FILE), ",%d\n", (SIZE)))
1458 /* The assembler's parentheses characters. */
1459 #define ASM_OPEN_PAREN "("
1460 #define ASM_CLOSE_PAREN ")"
1462 /* Target characters. */
1463 #define TARGET_BELL 007
1464 #define TARGET_BS 010
1465 #define TARGET_TAB 011
1466 #define TARGET_NEWLINE 012
1467 #define TARGET_VT 013
1468 #define TARGET_FF 014
1469 #define TARGET_CR 015
1472 /* Only perform branch elimination (by making instructions conditional) if
1473 we're optimising. Otherwise it's of no use anyway. */
1474 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1475 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1477 /* Print operand X (an rtx) in assembler syntax to file FILE.
1478 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1479 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1481 #define PRINT_OPERAND(STREAM, X, CODE) print_operand (STREAM, X, CODE)
1483 /* Print a memory address as an operand to reference that memory location. */
1485 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address (STREAM, X)
1487 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1488 ((CHAR)=='.' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR)=='!' || (CHAR)=='@')
1491 extern struct rtx_def *sh_compare_op0;
1492 extern struct rtx_def *sh_compare_op1;
1493 extern struct rtx_def *prepare_scc_operands();
1494 extern struct rtx_def *table_lab;
1497 /* ??? Wrong, this is an incomplete enum type. Fix this to do it the same
1498 way that the mips compiler does this. */
1499 extern enum attr_cpu sh_cpu; /* target cpu */
1501 /* Declare functions defined in sh.c and used in templates. */
1503 extern char *output_branch();
1504 extern char *output_shift();
1505 extern char *output_movedouble();
1506 extern char *output_movepcrel();
1507 extern char *output_jump_label_table();
1508 extern char *output_far_jump();
1511 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
1513 /* Generate calls to memcpy, memcmp and memset. */
1515 #define TARGET_MEM_FUNCTIONS
1517 #define HANDLE_PRAGMA(finput) return handle_pragma (finput)
1519 /* Set when processing a function with pragma interrupt turned on. */
1521 extern int pragma_interrupt;
1522 #define MOVE_RATIO (TARGET_SMALLCODE ? 4 : 16)
1524 extern char *max_si;
1525 extern char *max_hi;
1526 extern int max_count_si;
1527 extern int max_count_hi;
1529 /* Instructions with unfilled delay slots take up an extra two bytes for
1530 the nop in the delay slot. */
1532 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1533 if (((GET_CODE (X) == INSN \
1534 && GET_CODE (PATTERN (X)) != SEQUENCE \
1535 && GET_CODE (PATTERN (X)) != USE \
1536 && GET_CODE (PATTERN (X)) != CLOBBER) \
1537 || GET_CODE (X) == CALL_INSN \
1538 || (GET_CODE (X) == JUMP_INSN \
1539 && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \
1540 && GET_CODE (PATTERN (X)) != ADDR_VEC)) \
1541 && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \
1544 /* Enable a bug fix for the shorten_branches pass. */
1545 #define SHORTEN_WITH_ADJUST_INSN_LENGTH
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