1 /* Definitions of target machine for GNU compiler for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
23 #define TARGET_VERSION \
24 fputs (" (Hitachi SH)", stderr);
26 /* Generate SDB debugging information. */
28 #define SDB_DEBUGGING_INFO
30 /* Output DBX (stabs) debugging information if doing -gstabs. */
32 #define DBX_DEBUGGING_INFO
34 /* Generate SDB debugging information by default. */
36 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
40 #define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__}"
42 #define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
44 #define ASM_SPEC "%{ml:-little}"
46 #define LINK_SPEC "%{ml:-m shl}"
48 /* Show we can debug even without a frame pointer. */
49 #define CAN_DEBUG_WITHOUT_FP
51 #define CONDITIONAL_REGISTER_USAGE \
52 /* Hitachi saves and restores mac registers on call. */ \
55 call_used_regs[MACH_REG] = 0; \
56 call_used_regs[MACL_REG] = 0; \
59 /* Run-time compilation parameters selecting different hardware subsets. */
61 extern int target_flags;
62 #define ISIZE_BIT (1<<1)
63 #define DALIGN_BIT (1<<6)
64 #define SH0_BIT (1<<7)
65 #define SH1_BIT (1<<8)
66 #define SH2_BIT (1<<9)
67 #define SH3_BIT (1<<10)
68 #define SPACE_BIT (1<<13)
69 #define BIGTABLE_BIT (1<<14)
70 #define HITACHI_BIT (1<<22)
71 #define PADSTRUCT_BIT (1<<28)
72 #define LITTLE_ENDIAN_BIT (1<<29)
74 /* Nonzero if we should dump out instruction size info. */
75 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
77 /* Nonzero to align doubles on 64 bit boundaries. */
78 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
80 /* Nonzero if we should generate code using type 0 insns. */
81 /* ??? Is there such a thing as SH0? If not, we should delete all
83 #define TARGET_SH0 (target_flags & SH0_BIT)
85 /* Nonzero if we should generate code using type 1 insns. */
86 #define TARGET_SH1 (target_flags & SH1_BIT)
88 /* Nonzero if we should generate code using type 2 insns. */
89 #define TARGET_SH2 (target_flags & SH2_BIT)
91 /* Nonzero if we should generate code using type 3 insns. */
92 #define TARGET_SH3 (target_flags & SH3_BIT)
94 /* Nonzero if we should generate smaller code rather than faster code. */
95 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
97 /* Nonzero to use long jump tables. */
98 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
100 /* Nonzero if using Hitachi's calling convention. */
101 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
103 /* Nonzero if padding structures to a multiple of 4 bytes. This is
104 incompatible with Hitachi's compiler, and gives unusual structure layouts
105 which confuse programmers.
106 ??? This option is not useful, but is retained in case there are people
107 who are still relying on it. It may be deleted in the future. */
108 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
110 /* Nonzero if generating code for a little endian SH. */
111 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
113 #define TARGET_SWITCHES \
117 {"3", SH3_BIT|SH2_BIT}, \
118 {"3l", SH3_BIT|SH2_BIT|LITTLE_ENDIAN_BIT}, \
119 {"b", -LITTLE_ENDIAN_BIT}, \
120 {"bigtable", BIGTABLE_BIT}, \
121 {"dalign", DALIGN_BIT}, \
122 {"hitachi", HITACHI_BIT}, \
123 {"isize", ISIZE_BIT}, \
124 {"l", LITTLE_ENDIAN_BIT}, \
125 {"padstruct", PADSTRUCT_BIT}, \
126 {"space", SPACE_BIT}, \
127 {"", TARGET_DEFAULT} \
130 #define TARGET_DEFAULT (0)
132 #define OVERRIDE_OPTIONS \
142 /* We *MUST* always define optimize since we *HAVE* to run \
143 shorten branches to get correct code. */ \
144 /* ??? This is obsolete, since now shorten branches is no \
145 longer required by the SH, and is always run once even \
146 when not optimizing. Changing this now might be \
147 confusing though. */ \
149 flag_delayed_branch = 1; \
151 /* But never run scheduling before reload, since that can \
152 break global alloc, and generates slower code anyway due \
153 to the pressure on R0. */ \
154 flag_schedule_insns = 0; \
157 /* Target machine storage layout. */
159 /* Define to use software floating point emulator for REAL_ARITHMETIC and
160 decimal <-> binary conversion. */
161 #define REAL_ARITHMETIC
163 /* Define this if most significant bit is lowest numbered
164 in instructions that operate on numbered bit-fields. */
166 #define BITS_BIG_ENDIAN 0
168 /* Define this if most significant byte of a word is the lowest numbered. */
169 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
171 /* Define this if most significant word of a multiword number is the lowest
173 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
175 /* Define this to set the endianness to use in libgcc2.c, which can
176 not depend on target_flags. */
177 #if defined(__LITTLE_ENDIAN__)
178 #define LIBGCC2_WORDS_BIG_ENDIAN 0
180 #define LIBGCC2_WORDS_BIG_ENDIAN 1
183 /* Number of bits in an addressable storage unit. */
184 #define BITS_PER_UNIT 8
186 /* Width in bits of a "word", which is the contents of a machine register.
187 Note that this is not necessarily the width of data type `int';
188 if using 16-bit ints on a 68000, this would still be 32.
189 But on a machine with 16-bit registers, this would be 16. */
190 #define BITS_PER_WORD 32
191 #define MAX_BITS_PER_WORD 32
193 /* Width of a word, in units (bytes). */
194 #define UNITS_PER_WORD 4
196 /* Width in bits of a pointer.
197 See also the macro `Pmode' defined below. */
198 #define POINTER_SIZE 32
200 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
201 #define PARM_BOUNDARY 32
203 /* Boundary (in *bits*) on which stack pointer should be aligned. */
204 #define STACK_BOUNDARY 32
206 /* Allocation boundary (in *bits*) for the code of a function.
207 32 bit alignment is faster, because instructions are always fetched as a
208 pair from a longword boundary. */
209 #define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : 32)
211 /* Alignment of field after `int : 0' in a structure. */
212 #define EMPTY_FIELD_BOUNDARY 32
214 /* No data type wants to be aligned rounder than this. */
215 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
217 /* The best alignment to use in cases where we have a choice. */
218 #define FASTEST_ALIGNMENT 32
220 /* Make strings word-aligned so strcpy from constants will be faster. */
221 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
222 ((TREE_CODE (EXP) == STRING_CST \
223 && (ALIGN) < FASTEST_ALIGNMENT) \
224 ? FASTEST_ALIGNMENT : (ALIGN))
226 /* Make arrays of chars word-aligned for the same reasons. */
227 #define DATA_ALIGNMENT(TYPE, ALIGN) \
228 (TREE_CODE (TYPE) == ARRAY_TYPE \
229 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
230 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
232 /* Number of bits which any structure or union's size must be a
233 multiple of. Each structure or union's size is rounded up to a
235 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
237 /* Set this nonzero if move instructions will actually fail to work
238 when given unaligned data. */
239 #define STRICT_ALIGNMENT 1
241 /* Standard register usage. */
243 /* Register allocation for the Hitachi calling convention:
249 r14 frame pointer/call saved
251 ap arg pointer (doesn't really exist, always eliminated)
252 pr subroutine return address
254 mach multiply/accumulate result, high part
255 macl multiply/accumulate result, low part. */
257 /* Number of actual hardware registers.
258 The hardware registers are assigned numbers for the compiler
259 from 0 to just below FIRST_PSEUDO_REGISTER.
260 All registers that the compiler knows about must be given numbers,
261 even those that are not normally considered general registers. */
269 #define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
271 #define FIRST_PSEUDO_REGISTER 22
273 /* 1 for registers that have pervasive standard uses
274 and are not available for the register allocator.
276 Mach register is fixed 'cause it's only 10 bits wide for SH1.
277 It is 32 bits wide for SH2. */
279 #define FIXED_REGISTERS \
287 /* 1 for registers not available across function calls.
288 These must include the FIXED_REGISTERS and also any
289 registers that can be used without being saved.
290 The latter must include the registers where values are returned
291 and the register where structure-value addresses are passed.
292 Aside from that, you can include as many other registers as you like. */
294 #define CALL_USED_REGISTERS \
302 /* Return number of consecutive hard regs needed starting at reg REGNO
303 to hold something of mode MODE.
304 This is ordinarily the length in words of a value of mode MODE
305 but can be less for certain modes in special long registers.
307 On the SH regs are UNITS_PER_WORD bits wide. */
309 #define HARD_REGNO_NREGS(REGNO, MODE) \
310 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
312 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
313 We can allow any mode in any general register. The special registers
314 only allow SImode. Don't allow any mode in the PR. */
316 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
317 (SPECIAL_REG (REGNO) ? (MODE) == SImode \
318 : (REGNO) == PR_REG ? 0 \
321 /* Value is 1 if it is a good idea to tie two pseudo registers
322 when one has mode MODE1 and one has mode MODE2.
323 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
324 for any hard reg, then this must be 0 for correct output. */
326 #define MODES_TIEABLE_P(MODE1, MODE2) \
327 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
329 /* Specify the registers used for certain standard purposes.
330 The values of these macros are register numbers. */
332 /* Define this if the program counter is overloaded on a register. */
333 /* #define PC_REGNUM 15*/
335 /* Register to use for pushing function arguments. */
336 #define STACK_POINTER_REGNUM 15
338 /* Base register for access to local variables of the function. */
339 #define FRAME_POINTER_REGNUM 14
341 /* Value should be nonzero if functions must have frame pointers.
342 Zero means the frame pointer need not be set up (and parms may be accessed
343 via the stack pointer) in functions that seem suitable. */
345 #define FRAME_POINTER_REQUIRED 0
347 /* Definitions for register eliminations.
349 We have two registers that can be eliminated on the SH. First, the
350 frame pointer register can often be eliminated in favor of the stack
351 pointer register. Secondly, the argument pointer register can always be
352 eliminated; it is replaced with either the stack or frame pointer. */
354 /* This is an array of structures. Each structure initializes one pair
355 of eliminable registers. The "from" register number is given first,
356 followed by "to". Eliminations of the same "from" register are listed
357 in order of preference. */
359 #define ELIMINABLE_REGS \
360 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
361 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
362 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
364 /* Given FROM and TO register numbers, say whether this elimination
366 #define CAN_ELIMINATE(FROM, TO) \
367 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
369 /* Define the offset between two registers, one to be eliminated, and the other
370 its replacement, at the start of a routine. */
372 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
373 OFFSET = initial_elimination_offset (FROM, TO)
375 /* Base register for access to arguments of the function. */
376 #define ARG_POINTER_REGNUM 16
378 /* Register in which the static-chain is passed to a function. */
379 #define STATIC_CHAIN_REGNUM 13
381 /* The register in which a struct value address is passed. */
383 #define STRUCT_VALUE_REGNUM 2
385 /* If the structure value address is not passed in a register, define
386 `STRUCT_VALUE' as an expression returning an RTX for the place
387 where the address is passed. If it returns 0, the address is
388 passed as an "invisible" first argument. */
390 /*#define STRUCT_VALUE ((rtx)0)*/
392 /* Don't default to pcc-struct-return, because we have already specified
393 exactly how to return structures in the RETURN_IN_MEMORY macro. */
395 #define DEFAULT_PCC_STRUCT_RETURN 0
397 /* Define the classes of registers for register constraints in the
398 machine description. Also define ranges of constants.
400 One of the classes must always be named ALL_REGS and include all hard regs.
401 If there is more than one class, another class must be named NO_REGS
402 and contain no registers.
404 The name GENERAL_REGS must be the name of a class (or an alias for
405 another name such as ALL_REGS). This is the class of registers
406 that is allowed by "g" or "r" in a register constraint.
407 Also, registers outside this class are allocated only when
408 instructions express preferences for them.
410 The classes must be numbered in nondecreasing order; that is,
411 a larger-numbered class must never be contained completely
412 in a smaller-numbered class.
414 For any two classes, it is very desirable that there be another
415 class that represents their union. */
417 /* The SH has two sorts of general registers, R0 and the rest. R0 can
418 be used as the destination of some of the arithmetic ops. There are
419 also some special purpose registers; the T bit register, the
420 Procedure Return Register and the Multipy Accumulate Registers. */
434 #define N_REG_CLASSES (int) LIM_REG_CLASSES
436 /* Give names of register classes as strings for dump file. */
437 #define REG_CLASS_NAMES \
448 /* Define which registers fit in which classes.
449 This is an initializer for a vector of HARD_REG_SET
450 of length N_REG_CLASSES. */
452 #define REG_CLASS_CONTENTS \
454 0x000000, /* NO_REGS */ \
455 0x000001, /* R0_REGS */ \
456 0x020000, /* PR_REGS */ \
457 0x040000, /* T_REGS */ \
458 0x300000, /* MAC_REGS */ \
459 0x01FFFF, /* GENERAL_REGS */ \
460 0x37FFFF /* ALL_REGS */ \
463 /* The same information, inverted:
464 Return the class number of the smallest class containing
465 reg number REGNO. This could be a conditional expression
466 or could index an array. */
468 extern int regno_reg_class[];
469 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
471 /* When defined, the compiler allows registers explicitly used in the
472 rtl to be used as spill registers but prevents the compiler from
473 extending the lifetime of these registers. */
475 #define SMALL_REGISTER_CLASSES
477 /* The order in which register should be allocated. */
478 #define REG_ALLOC_ORDER \
479 { 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14,15,16,17,18,19,20,21 }
481 /* The class value for index registers, and the one for base regs. */
482 #define INDEX_REG_CLASS R0_REGS
483 #define BASE_REG_CLASS GENERAL_REGS
485 /* Get reg_class from a letter such as appears in the machine
487 extern enum reg_class reg_class_from_letter[];
489 #define REG_CLASS_FROM_LETTER(C) \
490 ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
492 /* The letters I, J, K, L and M in a register constraint string
493 can be used to stand for particular ranges of immediate operands.
494 This macro defines what the ranges are.
495 C is the letter, and VALUE is a constant value.
496 Return 1 if VALUE is in the range specified by C.
497 I: arithmetic operand -127..128, as used in add, sub, etc
498 K: shift operand 1,2,8 or 16
499 L: logical operand 0..255, as used in and, or, etc.
503 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127)
504 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
505 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255)
506 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
507 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
508 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
509 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
510 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
511 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
512 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
513 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
516 /* Similar, but for floating constants, and defining letters G and H.
517 Here VALUE is the CONST_DOUBLE rtx itself. */
519 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
521 /* Given an rtx X being reloaded into a reg required to be
522 in class CLASS, return the class of reg to actually use.
523 In general this is just CLASS; but on some machines
524 in some cases it is preferable to use a more restrictive class. */
526 #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
528 /* Return the maximum number of consecutive registers
529 needed to represent mode MODE in a register of class CLASS.
531 On SH this is the size of MODE in words. */
532 #define CLASS_MAX_NREGS(CLASS, MODE) \
533 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
535 /* Stack layout; function entry, exit and calling. */
537 /* Define the number of registers that can hold parameters.
538 These three macros are used only in other macro definitions below. */
540 #define FIRST_PARM_REG 4
541 #define FIRST_RET_REG 0
543 /* Define this if pushing a word on the stack
544 makes the stack pointer a smaller address. */
545 #define STACK_GROWS_DOWNWARD
547 /* Define this macro if the addresses of local variable slots are at
548 negative offsets from the frame pointer.
550 The SH only has positive indexes, so grow the frame up. */
551 /* #define FRAME_GROWS_DOWNWARD */
553 /* Offset from the frame pointer to the first local variable slot to
555 #define STARTING_FRAME_OFFSET 0
557 /* If we generate an insn to push BYTES bytes,
558 this says how many the stack pointer really advances by. */
559 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
561 /* Offset of first parameter from the argument pointer register value. */
562 #define FIRST_PARM_OFFSET(FNDECL) 0
564 /* Value is the number of byte of arguments automatically
565 popped when returning from a subroutine call.
566 FUNDECL is the declaration node of the function (as a tree),
567 FUNTYPE is the data type of the function (as a tree),
568 or for a library call it is an identifier node for the subroutine name.
569 SIZE is the number of bytes of arguments passed on the stack.
571 On the SH, the caller does not pop any of its arguments that were passed
573 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
575 /* Define how to find the value returned by a function.
576 VALTYPE is the data type of the value (as a tree).
577 If the precise function being called is known, FUNC is its FUNCTION_DECL;
578 otherwise, FUNC is 0. */
580 #define FUNCTION_VALUE(VALTYPE, FUNC) \
581 gen_rtx (REG, TYPE_MODE (VALTYPE), FIRST_RET_REG)
583 /* Define how to find the value returned by a library function
584 assuming the value has mode MODE. */
585 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, FIRST_RET_REG)
587 /* 1 if N is a possible register number for a function value.
588 On the SH, only r0 can return results. */
589 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG)
591 /* 1 if N is a possible register number for function argument passing. */
593 #define FUNCTION_ARG_REGNO_P(REGNO) \
594 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
596 /* Define a data type for recording info about an argument list
597 during the scan of that argument list. This data type should
598 hold all necessary information about the function itself
599 and about the args processed so far, enough to enable macros
600 such as FUNCTION_ARG to determine where the next arg should go.
602 On SH, this is a single integer, which is a number of words
603 of arguments scanned so far (including the invisible argument,
604 if any, which holds the structure-value-address).
605 Thus NARGREGS or more means all following args should go on the stack. */
607 #define CUMULATIVE_ARGS int
609 #define ROUND_ADVANCE(SIZE) \
610 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
612 /* Round a register number up to a proper boundary for an arg of mode
615 The SH doesn't care about double alignment, so we only
616 round doubles to even regs when asked to explicitly. */
618 #define ROUND_REG(X, MODE) \
619 ((TARGET_ALIGN_DOUBLE \
620 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
621 ? ((X) + ((X) & 1)) : (X))
623 /* Initialize a variable CUM of type CUMULATIVE_ARGS
624 for a call to a function whose data type is FNTYPE.
625 For a library call, FNTYPE is 0.
627 On SH, the offset always starts at 0: the first parm reg is always
630 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
633 /* Update the data in CUM to advance over an argument
634 of mode MODE and data type TYPE.
635 (TYPE is null for libcalls where that information may not be
638 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
639 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
640 + ((MODE) != BLKmode \
641 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
642 : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
644 /* Define where to put the arguments to a function.
645 Value is zero to push the argument on the stack,
646 or a hard register in which to store the argument.
648 MODE is the argument's machine mode.
649 TYPE is the data type of the argument (as a tree).
650 This is null for libcalls where that information may
652 CUM is a variable of type CUMULATIVE_ARGS which gives info about
653 the preceding args and about the function being called.
654 NAMED is nonzero if this argument is a named parameter
655 (otherwise it is an extra parameter matching an ellipsis).
657 On SH the first args are normally in registers
658 and the rest are pushed. Any arg that starts within the first
659 NPARM_REGS words is at least partially passed in a register unless
660 its data type forbids. */
662 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
663 sh_function_arg (CUM, MODE, TYPE, NAMED)
665 extern struct rtx_def *sh_function_arg();
667 /* For an arg passed partly in registers and partly in memory,
668 this is the number of registers used.
669 For args passed entirely in registers or entirely in memory, zero.
671 We sometimes split args. */
673 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
674 sh_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
676 extern int current_function_anonymous_args;
678 /* Perform any needed actions needed for a function that is receiving a
679 variable number of arguments. */
681 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
682 current_function_anonymous_args = 1;
684 /* Call the function profiler with a given profile label. */
686 #define FUNCTION_PROFILER(STREAM,LABELNO) \
688 fprintf(STREAM, " trapa #5\n"); \
689 fprintf(STREAM, " .align 2\n"); \
690 fprintf(STREAM, " .long LP%d\n", (LABELNO)); \
693 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
694 the stack pointer does not matter. The value is tested only in
695 functions that have frame pointers.
696 No definition is equivalent to always zero. */
698 #define EXIT_IGNORE_STACK 1
700 /* Generate the assembly code for function exit
701 Just dump out any accumulated constant table. */
703 #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue (STREAM, SIZE)
705 /* Output assembler code for a block containing the constant parts
706 of a trampoline, leaving space for the variable parts.
708 On the SH, the trapoline looks like
709 1 0000 D301 mov.l l1,r3
710 2 0002 DD02 mov.l l2,r13
713 5 0008 00000000 l1: .long function
714 6 000c 00000000 l2: .long area */
715 #define TRAMPOLINE_TEMPLATE(FILE) \
717 fprintf ((FILE), " .word 0xd301\n"); \
718 fprintf ((FILE), " .word 0xdd02\n"); \
719 fprintf ((FILE), " .word 0x4d2b\n"); \
720 fprintf ((FILE), " .word 0x200b\n"); \
721 fprintf ((FILE), " .long 0\n"); \
722 fprintf ((FILE), " .long 0\n"); \
725 /* Length in units of the trampoline for entering a nested function. */
726 #define TRAMPOLINE_SIZE 16
728 /* Alignment required for a trampoline in units. */
729 #define TRAMPOLINE_ALIGN 4
731 /* Emit RTL insns to initialize the variable parts of a trampoline.
732 FNADDR is an RTX for the address of the function's pure code.
733 CXT is an RTX for the static chain value for the function. */
735 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
737 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
739 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
743 /* Addressing modes, and classification of registers for them. */
744 #define HAVE_POST_INCREMENT 1
745 /*#define HAVE_PRE_INCREMENT 1*/
746 /*#define HAVE_POST_DECREMENT 1*/
747 #define HAVE_PRE_DECREMENT 1
749 /* Macros to check register numbers against specific register classes. */
751 /* These assume that REGNO is a hard or pseudo reg number.
752 They give nonzero only if REGNO is a hard reg of the suitable class
753 or a pseudo reg currently allocated to a suitable hard reg.
754 Since they use reg_renumber, they are safe only once reg_renumber
755 has been allocated, which happens in local-alloc.c. */
757 #define REGNO_OK_FOR_BASE_P(REGNO) \
758 ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
759 #define REGNO_OK_FOR_INDEX_P(REGNO) \
760 ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
762 /* Maximum number of registers that can appear in a valid memory
765 #define MAX_REGS_PER_ADDRESS 2
767 /* Recognize any constant value that is a valid address. */
769 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
771 /* Nonzero if the constant value X is a legitimate general operand. */
773 /* ??? Should modify this to accept CONST_DOUBLE, and then modify the
774 constant pool table code to fix loads of CONST_DOUBLEs. If that doesn't
775 work well, then we can at least handle simple CONST_DOUBLEs here
777 #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE)
779 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
780 and check its validity for a certain class.
781 We have two alternate definitions for each of them.
782 The usual definition accepts all pseudo regs; the other rejects
783 them unless they have been allocated suitable hard regs.
784 The symbol REG_OK_STRICT causes the latter definition to be used. */
786 #define MODE_DISP_OK_4(X,MODE) ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<64) && (!(INTVAL(X) &3)))
787 #define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3)))
789 #ifndef REG_OK_STRICT
791 /* Nonzero if X is a hard reg that can be used as a base reg
792 or if it is a pseudo reg. */
793 #define REG_OK_FOR_BASE_P(X) \
794 (REGNO (X) <= 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
796 /* Nonzero if X is a hard reg that can be used as an index
797 or if it is a pseudo reg. */
798 #define REG_OK_FOR_INDEX_P(X) \
799 (REGNO (X) == 0 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
803 /* Nonzero if X is a hard reg that can be used as a base reg. */
804 #define REG_OK_FOR_BASE_P(X) \
805 REGNO_OK_FOR_BASE_P (REGNO (X))
807 /* Nonzero if X is a hard reg that can be used as an index. */
808 #define REG_OK_FOR_INDEX_P(X) \
809 REGNO_OK_FOR_INDEX_P (REGNO (X))
813 /* The 'Q' constraint is a pc relative load operand. */
814 #define EXTRA_CONSTRAINT_Q(OP) \
815 (GET_CODE (OP) == MEM && \
816 ((GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
817 || (GET_CODE (XEXP (OP, 0)) == CONST \
818 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS \
819 && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == LABEL_REF \
820 && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT)))
822 #define EXTRA_CONSTRAINT(OP, C) \
823 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
826 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
827 that is a valid memory address for an instruction.
828 The MODE argument is the machine mode for the MEM expression
829 that wants to use this address.
831 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
833 #define BASE_REGISTER_RTX_P(X) \
834 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
835 || (GET_CODE (X) == SUBREG \
836 && GET_CODE (SUBREG_REG (X)) == REG \
837 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
839 #define INDEX_REGISTER_RTX_P(X) \
840 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
841 || (GET_CODE (X) == SUBREG \
842 && GET_CODE (SUBREG_REG (X)) == REG \
843 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
845 /* Jump to LABEL if X is a valid address RTX. This must also take
846 REG_OK_STRICT into account when deciding about valid registers, but it uses
847 the above macros so we are in luck.
855 /* The SH allows a displacement in a QI or HI amode, but only when the
856 other operand is R0. GCC doesn't handle this very well, so we forgo
859 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
860 DI can be any number 0..60. */
862 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
864 if (GET_CODE (OP) == CONST_INT) \
866 if (MODE_DISP_OK_4 (OP, MODE)) goto LABEL; \
867 if (MODE_DISP_OK_8 (OP, MODE)) goto LABEL; \
871 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
873 if (BASE_REGISTER_RTX_P (X)) \
875 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
876 && BASE_REGISTER_RTX_P (XEXP (X, 0))) \
878 else if (GET_CODE (X) == PLUS) \
880 rtx xop0 = XEXP (X, 0); \
881 rtx xop1 = XEXP (X, 1); \
882 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
883 GO_IF_LEGITIMATE_INDEX (MODE, xop1, LABEL); \
884 if (GET_MODE_SIZE (MODE) <= 4) \
886 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
888 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
894 /* Try machine-dependent ways of modifying an illegitimate address
895 to be legitimate. If we find one, return the new, valid address.
896 This macro is used in only one place: `memory_address' in explow.c.
898 OLDX is the address as it was before break_out_memory_refs was called.
899 In some cases it is useful to look at this to decide what needs to be done.
901 MODE and WIN are passed so that this macro can use
902 GO_IF_LEGITIMATE_ADDRESS.
904 It is always safe for this macro to do nothing. It exists to recognize
905 opportunities to optimize the output. */
907 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) ;
909 /* Go to LABEL if ADDR (a legitimate address expression)
910 has an effect that depends on the machine mode it is used for. */
911 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
913 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
917 /* Specify the machine mode that this machine uses
918 for the index in the tablejump instruction. */
919 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
921 /* Define this if the tablejump instruction expects the table
922 to contain offsets from the address of the table.
923 Do not define this if the table should contain absolute addresses. */
924 #define CASE_VECTOR_PC_RELATIVE
926 /* Specify the tree operation to be used to convert reals to integers. */
927 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
929 /* This is the kind of divide that is easiest to do in the general case. */
930 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
932 /* 'char' is signed by default. */
933 #define DEFAULT_SIGNED_CHAR 1
935 /* The type of size_t unsigned int. */
936 #define SIZE_TYPE "unsigned int"
938 #define WCHAR_TYPE "short unsigned int"
939 #define WCHAR_TYPE_SIZE 16
941 /* Don't cse the address of the function being compiled. */
942 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
944 /* Max number of bytes we can move from memory to memory
945 in one reasonably fast instruction. */
948 /* Define if operations between registers always perform the operation
949 on the full register even if a narrower mode is specified. */
950 #define WORD_REGISTER_OPERATIONS
952 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
953 will either zero-extend or sign-extend. The value of this macro should
954 be the code that says which one of the two operations is implicitly
955 done, NIL if none. */
956 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
958 /* Define this if zero-extension is slow (more than one real instruction).
959 On the SH, it's only one instruction. */
960 /* #define SLOW_ZERO_EXTEND */
962 /* Nonzero if access to memory by bytes is slow and undesirable. */
963 #define SLOW_BYTE_ACCESS 0
965 /* We assume that the store-condition-codes instructions store 0 for false
966 and some other value for true. This is the value stored for true. */
968 #define STORE_FLAG_VALUE 1
970 /* Immediate shift counts are truncated by the output routines (or was it
971 the assembler?). Shift counts in a register are truncated by SH. Note
972 that the native compiler puts too large (> 32) immediate shift counts
973 into a register and shifts by the register, letting the SH decide what
974 to do instead of doing that itself. */
975 #define SHIFT_COUNT_TRUNCATED 1
977 /* All integers have the same format so truncation is easy. */
978 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
980 /* Define this if addresses of constant functions
981 shouldn't be put through pseudo regs where they can be cse'd.
982 Desirable on machines where ordinary constants are expensive
983 but a CALL with constant address is cheap. */
984 /*#define NO_FUNCTION_CSE 1*/
986 /* Chars and shorts should be passed as ints. */
987 #define PROMOTE_PROTOTYPES 1
989 /* The machine modes of pointers and functions. */
991 #define FUNCTION_MODE Pmode
993 /* The relative costs of various types of constants. Note that cse.c defines
994 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
996 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
998 if (INTVAL (RTX) == 0) \
1000 else if (CONST_OK_FOR_I (INTVAL (RTX))) \
1002 else if ((OUTER_CODE == AND || OUTER_CODE == IOR || OUTER_CODE == XOR) \
1003 && CONST_OK_FOR_L (INTVAL (RTX))) \
1011 case CONST_DOUBLE: \
1014 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1016 return COSTS_N_INSNS (andcosts (X)); \
1018 return COSTS_N_INSNS (multcosts (X)); \
1022 return COSTS_N_INSNS (shiftcosts (X)) ; \
1027 return COSTS_N_INSNS (20); \
1032 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1033 are actually function calls with some special constraints on arguments
1036 These macros tell reorg that the references to arguments and
1037 register clobbers for insns of type sfunc do not appear to happen
1038 until after the millicode call. This allows reorg to put insns
1039 which set the argument registers into the delay slot of the millicode
1040 call -- thus they act more like traditional CALL_INSNs.
1042 get_attr_type will try to recognize the given insn, so make sure to
1043 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1046 #define INSN_SETS_ARE_DELAYED(X) \
1047 ((GET_CODE (X) == INSN \
1048 && GET_CODE (PATTERN (X)) != SEQUENCE \
1049 && GET_CODE (PATTERN (X)) != USE \
1050 && GET_CODE (PATTERN (X)) != CLOBBER \
1051 && get_attr_type (X) == TYPE_SFUNC))
1053 #define INSN_REFERENCES_ARE_DELAYED(X) \
1054 ((GET_CODE (X) == INSN \
1055 && GET_CODE (PATTERN (X)) != SEQUENCE \
1056 && GET_CODE (PATTERN (X)) != USE \
1057 && GET_CODE (PATTERN (X)) != CLOBBER \
1058 && get_attr_type (X) == TYPE_SFUNC))
1060 /* Compute extra cost of moving data between one register class
1063 On the SH it is hard to move into the T reg, but simple to load
1066 #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
1067 (((DSTCLASS == T_REGS) || (DSTCLASS == PR_REG)) ? 10 : 1)
1069 /* Assembler output control. */
1071 /* The text to go at the start of the assembler file. */
1072 #define ASM_FILE_START(STREAM) \
1073 output_file_start (STREAM, f_options, \
1074 sizeof f_options / sizeof f_options[0], \
1075 W_options, sizeof W_options / sizeof W_options[0]);
1077 #define ASM_FILE_END(STREAM)
1079 #define ASM_APP_ON ""
1080 #define ASM_APP_OFF ""
1081 #define FILE_ASM_OP "\t.file\n"
1082 #define IDENT_ASM_OP "\t.ident\n"
1084 /* How to change between sections. */
1086 #define TEXT_SECTION_ASM_OP "\t.text"
1087 #define DATA_SECTION_ASM_OP "\t.data"
1088 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n"
1089 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n"
1090 #define INIT_SECTION_ASM_OP "\t.section\t.init\n"
1091 #define EXTRA_SECTIONS in_ctors, in_dtors
1092 #define EXTRA_SECTION_FUNCTIONS \
1096 if (in_section != in_ctors) \
1098 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1099 in_section = in_ctors; \
1105 if (in_section != in_dtors) \
1107 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1108 in_section = in_dtors; \
1112 /* A C statement to output something to the assembler file to switch to section
1113 NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
1114 NULL_TREE. Some target formats do not support arbitrary sections. Do not
1115 define this macro in such cases. */
1117 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME) \
1118 do { fprintf (FILE, ".section\t%s\n", NAME); } while (0)
1120 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
1121 do { ctors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1123 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
1124 do { dtors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1126 #undef DO_GLOBAL_CTORS_BODY
1128 #define DO_GLOBAL_CTORS_BODY \
1130 typedef (*pfunc)(); \
1131 extern pfunc __ctors[]; \
1132 extern pfunc __ctors_end[]; \
1134 for (p = __ctors_end; p > __ctors; ) \
1140 #undef DO_GLOBAL_DTORS_BODY
1141 #define DO_GLOBAL_DTORS_BODY \
1143 typedef (*pfunc)(); \
1144 extern pfunc __dtors[]; \
1145 extern pfunc __dtors_end[]; \
1147 for (p = __dtors; p < __dtors_end; p++) \
1153 #define ASM_OUTPUT_REG_PUSH(file, v) \
1154 fprintf (file, "\tmov.l r%s,-@r15\n", v);
1156 #define ASM_OUTPUT_REG_POP(file, v) \
1157 fprintf (file, "\tmov.l @r15+,r%s\n", v);
1159 /* The assembler's names for the registers. RFP need not always be used as
1160 the Real framepointer; it can also be used as a normal general register.
1161 Note that the name `fp' is horribly misleading since `fp' is in fact only
1162 the argument-and-return-context pointer. */
1163 #define REGISTER_NAMES \
1165 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1166 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1167 "ap", "pr", "t", "gbr", "mach","macl" \
1170 /* DBX register number for a given compiler register number. */
1171 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1173 /* Output a label definition. */
1174 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1175 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1177 /* This is how to output an assembler line
1178 that says to advance the location counter
1179 to a multiple of 2**LOG bytes. */
1181 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1183 fprintf (FILE, "\t.align %d\n", LOG)
1185 /* Output a function label definition. */
1186 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1187 ASM_OUTPUT_LABEL(STREAM, NAME)
1189 /* Output a globalising directive for a label. */
1190 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1191 (fprintf (STREAM, "\t.global\t"), \
1192 assemble_name (STREAM, NAME), \
1193 fputc ('\n',STREAM))
1195 /* Output a reference to a label. */
1196 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1197 fprintf (STREAM, "_%s", NAME)
1199 /* Make an internal label into a string. */
1200 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1201 sprintf (STRING, "*%s%d", PREFIX, NUM)
1203 /* Output an internal label definition. */
1204 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1205 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1207 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1209 /* Construct a private name. */
1210 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1211 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1212 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1214 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
1215 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1216 fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM);
1218 /* Output a relative address table. */
1220 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1221 if (TARGET_BIGTABLE) \
1222 fprintf (STREAM, "\t.long L%d-L%d\n", VALUE,REL); \
1224 fprintf (STREAM, "\t.word L%d-L%d\n", VALUE,REL); \
1226 /* Output an absolute table element. */
1228 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1229 if (TARGET_BIGTABLE) \
1230 fprintf (STREAM, "\t.long L%d\n", VALUE); \
1232 fprintf (STREAM, "\t.word L%d\n", VALUE); \
1234 /* Output various types of constants. */
1236 /* This is how to output an assembler line defining a `double'. */
1238 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1239 do { char dstr[30]; \
1240 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1241 fprintf (FILE, "\t.double %s\n", dstr); \
1244 /* This is how to output an assembler line defining a `float' constant. */
1245 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1246 do { char dstr[30]; \
1247 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1248 fprintf (FILE, "\t.float %s\n", dstr); \
1251 #define ASM_OUTPUT_INT(STREAM, EXP) \
1252 (fprintf (STREAM, "\t.long\t"), \
1253 output_addr_const (STREAM, (EXP)), \
1254 fputc ('\n', STREAM))
1256 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1257 (fprintf (STREAM, "\t.short\t"), \
1258 output_addr_const (STREAM, (EXP)), \
1259 fputc ('\n', STREAM))
1261 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1262 (fprintf (STREAM, "\t.byte\t"), \
1263 output_addr_const (STREAM, (EXP)), \
1264 fputc ('\n', STREAM))
1266 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1267 fprintf (STREAM, "\t.byte\t%d\n", VALUE) \
1269 /* This is how to output an assembler line
1270 that says to advance the location counter by SIZE bytes. */
1272 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1273 fprintf (FILE, "\t.space %d\n", (SIZE))
1275 /* This says how to output an assembler line
1276 to define a global common symbol. */
1278 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1279 ( fputs ("\t.comm ", (FILE)), \
1280 assemble_name ((FILE), (NAME)), \
1281 fprintf ((FILE), ",%d\n", (SIZE)))
1283 /* This says how to output an assembler line
1284 to define a local common symbol. */
1286 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
1287 ( fputs ("\t.lcomm ", (FILE)), \
1288 assemble_name ((FILE), (NAME)), \
1289 fprintf ((FILE), ",%d\n", (SIZE)))
1291 /* The assembler's parentheses characters. */
1292 #define ASM_OPEN_PAREN "("
1293 #define ASM_CLOSE_PAREN ")"
1295 /* Target characters. */
1296 #define TARGET_BELL 007
1297 #define TARGET_BS 010
1298 #define TARGET_TAB 011
1299 #define TARGET_NEWLINE 012
1300 #define TARGET_VT 013
1301 #define TARGET_FF 014
1302 #define TARGET_CR 015
1304 /* Only perform branch elimination (by making instructions conditional) if
1305 we're optimizing. Otherwise it's of no use anyway. */
1306 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1307 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1309 /* Print operand X (an rtx) in assembler syntax to file FILE.
1310 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1311 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1313 #define PRINT_OPERAND(STREAM, X, CODE) print_operand (STREAM, X, CODE)
1315 /* Print a memory address as an operand to reference that memory location. */
1317 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address (STREAM, X)
1319 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1320 ((CHAR)=='.' || (CHAR) == '#' || (CHAR)=='@')
1322 extern struct rtx_def *sh_compare_op0;
1323 extern struct rtx_def *sh_compare_op1;
1324 extern struct rtx_def *prepare_scc_operands();
1326 /* Which processor to schedule for. The elements of the enumeration must
1327 match exactly the cpu attribute in the sh.md file. */
1329 enum processor_type {
1336 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
1337 extern enum processor_type sh_cpu;
1339 /* Declare functions defined in sh.c and used in templates. */
1341 extern char *output_branch();
1342 extern char *output_shift();
1343 extern char *output_movedouble();
1344 extern char *output_movepcrel();
1345 extern char *output_jump_label_table();
1346 extern char *output_far_jump();
1348 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
1350 /* Generate calls to memcpy, memcmp and memset. */
1352 #define TARGET_MEM_FUNCTIONS
1354 #define HANDLE_PRAGMA(finput) return handle_pragma (finput)
1356 /* Set when processing a function with pragma interrupt turned on. */
1358 extern int pragma_interrupt;
1360 #define MOVE_RATIO (TARGET_SMALLCODE ? 2 : 16)
1362 /* Instructions with unfilled delay slots take up an extra two bytes for
1363 the nop in the delay slot. */
1365 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1366 if (((GET_CODE (X) == INSN \
1367 && GET_CODE (PATTERN (X)) != SEQUENCE \
1368 && GET_CODE (PATTERN (X)) != USE \
1369 && GET_CODE (PATTERN (X)) != CLOBBER) \
1370 || GET_CODE (X) == CALL_INSN \
1371 || (GET_CODE (X) == JUMP_INSN \
1372 && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \
1373 && GET_CODE (PATTERN (X)) != ADDR_VEC)) \
1374 && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \
1377 /* Enable a bug fix for the shorten_branches pass. */
1378 #define SHORTEN_WITH_ADJUST_INSN_LENGTH
1380 /* Define the codes that are matched by predicates in sh.c. */
1381 #define PREDICATE_CODES \
1382 {"arith_reg_operand", {SUBREG, REG}}, \
1383 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1384 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
1385 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
1386 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1387 {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}},
1389 /* Define this macro if it is advisable to hold scalars in registers
1390 in a wider mode than that declared by the program. In such cases,
1391 the value is constrained to be within the bounds of the declared
1392 type, but kept valid in the wider mode. The signedness of the
1393 extension may differ from that of the type.
1395 Leaving the unsignedp unchanged gives better code than always setting it
1396 to 0. This is despite the fact that we have only signed char and short
1397 load instructions. */
1398 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1399 if (GET_MODE_CLASS (MODE) == MODE_INT \
1400 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1403 /* PROMOTE_FUNCTION_ARGS and PROMOTE_FUNCTION_RETURN appear to have no
1404 effect, because all unprototyped char/shorts are already promoted to
1405 int, and because PROMOTE_PROTOTYPES causes all prototypes char/shorts
1406 to be promoted to it. */
1408 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
1409 and poping arguments. However, we do have push/pop instructions, and
1410 rather limited offsets (4 bits) in load/store instructions, so it isn't
1411 clear if this would give better code. If implemented, should check for
1412 compatibility problems. */
1414 /* ??? Define ADJUST_COSTS? */