1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
35 #define TARGET_CPU_CPP_BUILTINS() \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
43 builtin_define ("__sh1__"); \
46 builtin_define ("__sh2__"); \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
51 case PROCESSOR_SH2A: \
52 builtin_define ("__SH2A__"); \
53 builtin_define (TARGET_SH2A_DOUBLE \
54 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
55 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
56 : "__SH2A_NOFPU__"); \
59 builtin_define ("__sh3__"); \
60 builtin_define ("__SH3__"); \
61 if (TARGET_HARD_SH4) \
62 builtin_define ("__SH4_NOFPU__"); \
64 case PROCESSOR_SH3E: \
65 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
68 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
70 case PROCESSOR_SH4A: \
71 builtin_define ("__SH4A__"); \
72 builtin_define (TARGET_SH4 \
73 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
74 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
79 builtin_define_with_value ("__SH5__", \
80 TARGET_SHMEDIA64 ? "64" : "32", 0); \
81 builtin_define_with_value ("__SHMEDIA__", \
82 TARGET_SHMEDIA ? "1" : "0", 0); \
83 if (! TARGET_FPU_DOUBLE) \
84 builtin_define ("__SH4_NOFPU__"); \
88 builtin_define ("__HITACHI__"); \
89 builtin_define (TARGET_LITTLE_ENDIAN \
90 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
93 builtin_define ("__pic__"); \
94 builtin_define ("__PIC__"); \
98 /* We can not debug without a frame pointer. */
99 /* #define CAN_DEBUG_WITHOUT_FP */
101 #define CONDITIONAL_REGISTER_USAGE do \
104 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
105 if (! VALID_REGISTER_P (regno)) \
106 fixed_regs[regno] = call_used_regs[regno] = 1; \
107 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
109 call_used_regs[FIRST_GENERAL_REG + 8] \
110 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
111 if (TARGET_SHMEDIA) \
113 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
114 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
115 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
118 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
119 /* Renesas saves and restores mac registers on call. */ \
120 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
122 call_used_regs[MACH_REG] = 0; \
123 call_used_regs[MACL_REG] = 0; \
125 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
126 regno <= LAST_FP_REG; regno += 2) \
127 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
128 if (TARGET_SHMEDIA) \
130 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
131 if (! fixed_regs[regno] && call_used_regs[regno]) \
132 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
135 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
136 if (! fixed_regs[regno] && call_used_regs[regno]) \
137 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
140 /* ??? Need to write documentation for all SH options and add it to the
143 /* Run-time compilation parameters selecting different hardware subsets. */
145 extern int target_flags;
146 #define ISIZE_BIT (1<<1)
147 #define DALIGN_BIT (1<<6)
148 #define SH1_BIT (1<<8)
149 #define SH2_BIT (1<<9)
150 #define SH3_BIT (1<<10)
151 #define SH_E_BIT (1<<11)
152 #define HARD_SH4_BIT (1<<5)
153 #define FPU_SINGLE_BIT (1<<7)
154 #define SH4_BIT (1<<12)
155 #define SH4A_BIT (1<<3)
156 #define FMOVD_BIT (1<<4)
157 #define SH5_BIT (1<<0)
158 #define SPACE_BIT (1<<13)
159 #define BIGTABLE_BIT (1<<14)
160 #define RELAX_BIT (1<<15)
161 #define USERMODE_BIT (1<<16)
162 #define HITACHI_BIT (1<<22)
163 #define NOMACSAVE_BIT (1<<23)
164 #define PREFERGOT_BIT (1<<24)
165 #define PADSTRUCT_BIT (1<<28)
166 #define LITTLE_ENDIAN_BIT (1<<29)
167 #define IEEE_BIT (1<<30)
168 #define SAVE_ALL_TR_BIT (1<<2)
169 #define HARD_SH2A_BIT (1<<17)
170 #define HARD_SH2A_DOUBLE_BIT (1<<18)
172 /* Nonzero if this is an ELF target - compile time only */
175 /* Nonzero if we should dump out instruction size info. */
176 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
178 /* Nonzero to align doubles on 64 bit boundaries. */
179 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
181 /* Nonzero if we should generate code using type 1 insns. */
182 #define TARGET_SH1 (target_flags & SH1_BIT)
184 /* Nonzero if we should generate code using type 2 insns. */
185 #define TARGET_SH2 (target_flags & SH2_BIT)
187 /* Nonzero if we should generate code using type 2E insns. */
188 #define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
190 /* Nonzero if we should generate code using type 2A insns. */
191 #define TARGET_SH2A (target_flags & HARD_SH2A_BIT)
192 /* Nonzero if we should generate code using type 2A SF insns. */
193 #define TARGET_SH2A_SINGLE ((target_flags & HARD_SH2A_BIT) && TARGET_SH2E)
194 /* Nonzero if we should generate code using type 2A DF insns. */
195 #define TARGET_SH2A_DOUBLE ((target_flags & HARD_SH2A_DOUBLE_BIT) && TARGET_SH2A)
197 /* Nonzero if we should generate code using type 3 insns. */
198 #define TARGET_SH3 (target_flags & SH3_BIT)
200 /* Nonzero if we should generate code using type 3E insns. */
201 #define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
203 /* Nonzero if the cache line size is 32. */
204 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
206 /* Nonzero if we schedule for a superscalar implementation. */
207 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
209 /* Nonzero if the target has separate instruction and data caches. */
210 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
212 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
213 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
215 /* Nonzero if the default precision of th FPU is single */
216 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
218 /* Nonzero if a double-precision FPU is available. */
219 #define TARGET_FPU_DOUBLE ((target_flags & SH4_BIT) || TARGET_SH2A_DOUBLE)
221 /* Nonzero if an FPU is available. */
222 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
224 /* Nonzero if we should generate code using type 4 insns. */
225 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
227 /* Nonzero if we're generating code for the common subset of
228 instructions present on both SH4a and SH4al-dsp. */
229 #define TARGET_SH4A_ARCH (target_flags & SH4A_BIT)
231 /* Nonzero if we're generating code for SH4a, unless the use of the
232 FPU is disabled (which makes it compatible with SH4al-dsp). */
233 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
235 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
236 #define TARGET_SH5 (target_flags & SH5_BIT)
238 /* Nonzero if we should generate code using the SHcompact instruction
239 set and 32-bit ABI. */
240 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
242 /* Nonzero if we should generate code using the SHmedia instruction
244 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
246 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
248 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
249 && (target_flags & SH_E_BIT))
251 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
253 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
254 && ! (target_flags & SH_E_BIT))
256 /* Nonzero if we should generate code using SHmedia FPU instructions. */
257 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
258 /* Nonzero if we should generate fmovd. */
259 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
261 /* Nonzero if we respect NANs. */
262 #define TARGET_IEEE (target_flags & IEEE_BIT)
264 /* Nonzero if we should generate smaller code rather than faster code. */
265 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
267 /* Nonzero to use long jump tables. */
268 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
270 /* Nonzero to generate pseudo-ops needed by the assembler and linker
271 to do function call relaxing. */
272 #define TARGET_RELAX (target_flags & RELAX_BIT)
274 /* Nonzero if using Renesas's calling convention. */
275 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
277 /* Nonzero if not saving macl/mach when using -mhitachi */
278 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
280 /* Nonzero if padding structures to a multiple of 4 bytes. This is
281 incompatible with Renesas's compiler, and gives unusual structure layouts
282 which confuse programmers.
283 ??? This option is not useful, but is retained in case there are people
284 who are still relying on it. It may be deleted in the future. */
285 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
287 /* Nonzero if generating code for a little endian SH. */
288 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
290 /* Nonzero if we should do everything in userland. */
291 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
293 /* Nonzero if we should prefer @GOT calls when generating PIC. */
294 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
296 #define TARGET_SAVE_ALL_TARGET_REGS (target_flags & SAVE_ALL_TR_BIT)
298 /* This is not used by the SH2E calling convention */
299 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
300 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
301 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
303 #ifndef TARGET_CPU_DEFAULT
304 #define TARGET_CPU_DEFAULT SELECT_SH1
308 #define SUPPORT_SH4_SINGLE
310 #define SUPPORT_SH2A_SINGLE
313 #define SELECT_SH1 (SH1_BIT)
314 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
315 #define SELECT_SH2E (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
316 #define SELECT_SH2A (SH_E_BIT | HARD_SH2A_BIT | HARD_SH2A_DOUBLE_BIT | SH2_BIT | SH1_BIT)
317 #define SELECT_SH2A_NOFPU (HARD_SH2A_BIT | SH2_BIT | SH1_BIT)
318 #define SELECT_SH2A_SINGLE_ONLY (SH_E_BIT | HARD_SH2A_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
319 #define SELECT_SH2A_SINGLE (SH_E_BIT | HARD_SH2A_BIT | FPU_SINGLE_BIT \
320 | HARD_SH2A_DOUBLE_BIT | SH2_BIT | SH1_BIT)
321 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
322 #define SELECT_SH3E (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
323 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
324 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
325 #define SELECT_SH4 (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
326 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
327 #define SELECT_SH4A_NOFPU (SH4A_BIT | SELECT_SH4_NOFPU)
328 #define SELECT_SH4A_SINGLE_ONLY (SH4A_BIT | SELECT_SH4_SINGLE_ONLY)
329 #define SELECT_SH4A (SH4A_BIT | SELECT_SH4)
330 #define SELECT_SH4A_SINGLE (SH4A_BIT | SELECT_SH4_SINGLE)
331 #define SELECT_SH5_64MEDIA (SH5_BIT | SH4_BIT)
332 #define SELECT_SH5_64MEDIA_NOFPU (SH5_BIT)
333 #define SELECT_SH5_32MEDIA (SH5_BIT | SH4_BIT | SH_E_BIT)
334 #define SELECT_SH5_32MEDIA_NOFPU (SH5_BIT | SH_E_BIT)
335 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
336 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
338 /* Disable processor switches for which we have no suitable multilibs. */
340 #define TARGET_SWITCH_SH1
342 #define TARGET_SWITCH_SH2
344 #define TARGET_SWITCH_SH3
345 #ifndef SUPPORT_SH4_NOFPU
346 #define TARGET_SWITCH_SH4_NOFPU
348 #ifndef SUPPORT_SH4A_NOFPU
349 #define TARGET_SWITCH_SH4A_NOFPU
351 #ifndef SUPPORT_SH4AL
352 #define TARGET_SWITCH_SH4AL
354 #ifndef SUPPORT_SH2A_NOFPU
355 #define TARGET_SWITCH_SH2A_NOFPU
362 #define TARGET_SWITCH_SH2E
364 #define TARGET_SWITCH_SH3E
365 #ifndef SUPPORT_SH4_SINGLE_ONLY
366 #define TARGET_SWITCH_SH4_SINGLE_ONLY
368 #ifndef SUPPORT_SH4A_SINGLE_ONLY
369 #define TARGET_SWITCH_SH4A_SINGLE_ONLY
371 #ifndef SUPPORT_SH2A_SINGLE_ONLY
372 #define TARGET_SWITCH_SH2A_SINGLE_ONLY
378 #define TARGET_SWITCH_SH4
380 #define TARGET_SWITCH_SH4A
384 #ifndef SUPPORT_SH4_SINGLE
385 #define TARGET_SWITCH_SH4_SINGLE
386 #ifndef SUPPORT_SH4A_SINGLE
387 #define TARGET_SWITCH_SH4A_SINGLE
392 #define TARGET_SWITCH_SH2A
395 #ifndef SUPPORT_SH2A_SINGLE
396 #define TARGET_SWITCH_SH2A_SINGLE
399 #ifndef SUPPORT_SH5_64MEDIA
400 #define TARGET_SWITCH_SH5_64MEDIA
403 #ifndef SUPPORT_SH5_64MEDIA_NOFPU
404 #define TARGET_SWITCH_SH5_64MEDIA_NOFPU
407 #if !defined(SUPPORT_SH5_32MEDIA) && !defined (SUPPORT_SH5_COMPACT)
408 #define TARGET_SWITCHES_SH5_32MEDIA
411 #if !defined(SUPPORT_SH5_32MEDIA_NOFPU) && !defined (SUPPORT_SH5_COMPACT_NOFPU)
412 #define TARGET_SWITCHES_SH5_32MEDIA_NOFPU
415 /* Reset all target-selection flags. */
416 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
417 | HARD_SH2A_BIT | HARD_SH2A_DOUBLE_BIT \
418 | SH4A_BIT | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
420 #ifndef TARGET_SWITCH_SH1
421 #define TARGET_SWITCH_SH1 \
422 {"1", TARGET_NONE, "" }, \
423 {"1", SELECT_SH1, "Generate SH1 code" },
425 #ifndef TARGET_SWITCH_SH2
426 #define TARGET_SWITCH_SH2 \
427 {"2", TARGET_NONE, "" }, \
428 {"2", SELECT_SH2, "Generate SH2 code" },
430 #ifndef TARGET_SWITCH_SH2E
431 #define TARGET_SWITCH_SH2E \
432 {"2e", TARGET_NONE, "" }, \
433 {"2e", SELECT_SH2E, "Generate SH2e code" },
435 #ifndef TARGET_SWITCH_SH2A
436 #define TARGET_SWITCH_SH2A \
437 {"2a", TARGET_NONE, "" }, \
438 {"2a", SELECT_SH2A, "Generate SH2a code" },
440 #ifndef TARGET_SWITCH_SH2A_SINGLE_ONLY
441 #define TARGET_SWITCH_SH2A_SINGLE_ONLY \
442 {"2a-single-only", TARGET_NONE, "" }, \
443 {"2a-single-only", SELECT_SH2A_SINGLE_ONLY, "Generate only single-precision SH2a code" },
445 #ifndef TARGET_SWITCH_SH2A_SINGLE
446 #define TARGET_SWITCH_SH2A_SINGLE \
447 {"2a-single", TARGET_NONE, "" }, \
448 {"2a-single", SELECT_SH2A_SINGLE, "Generate default single-precision SH2a code" },
450 #ifndef TARGET_SWITCH_SH2A_NOFPU
451 #define TARGET_SWITCH_SH2A_NOFPU \
452 {"2a-nofpu", TARGET_NONE, "" }, \
453 {"2a-nofpu", SELECT_SH2A_NOFPU, "Generate SH2a FPU-less code" },
455 #ifndef TARGET_SWITCH_SH3
456 #define TARGET_SWITCH_SH3 \
457 {"3", TARGET_NONE, "" }, \
458 {"3", SELECT_SH3, "Generate SH3 code" },
460 #ifndef TARGET_SWITCH_SH3E
461 #define TARGET_SWITCH_SH3E \
462 {"3e", TARGET_NONE, "" }, \
463 {"3e", SELECT_SH3E, "Generate SH3e code" },
465 #ifndef TARGET_SWITCH_SH4_SINGLE_ONLY
466 #define TARGET_SWITCH_SH4_SINGLE_ONLY \
467 {"4-single-only", TARGET_NONE, "" }, \
468 {"4-single-only", SELECT_SH4_SINGLE_ONLY, "Generate only single-precision SH4 code" },
470 #ifndef TARGET_SWITCH_SH4_SINGLE
471 #define TARGET_SWITCH_SH4_SINGLE \
472 {"4-single", TARGET_NONE, "" }, \
473 {"4-single", SELECT_SH4_SINGLE, "Generate default single-precision SH4 code" },
475 #ifndef TARGET_SWITCH_SH4_NOFPU
476 #define TARGET_SWITCH_SH4_NOFPU \
477 {"4-nofpu", TARGET_NONE, "" }, \
478 {"4-nofpu", SELECT_SH4_NOFPU, "Generate SH4 FPU-less code" },
480 #ifndef TARGET_SWITCH_SH4
481 #define TARGET_SWITCH_SH4 \
482 {"4", TARGET_NONE, "" }, \
483 {"4", SELECT_SH4, "Generate SH4 code" },
485 #ifndef TARGET_SWITCH_SH4A
486 #define TARGET_SWITCH_SH4A \
487 {"4a", TARGET_NONE, "" }, \
488 {"4a", SELECT_SH4A, "Generate SH4a code" },
490 #ifndef TARGET_SWITCH_SH4A_SINGLE_ONLY
491 #define TARGET_SWITCH_SH4A_SINGLE_ONLY \
492 {"4a-single-only", TARGET_NONE, "" }, \
493 {"4a-single-only", SELECT_SH4A_SINGLE_ONLY, "Generate only single-precision SH4a code" },
495 #ifndef TARGET_SWITCH_SH4A_SINGLE
496 #define TARGET_SWITCH_SH4A_SINGLE \
497 {"4a-single", TARGET_NONE, "" },\
498 {"4a-single", SELECT_SH4A_SINGLE, "Generate default single-precision SH4a code" },
500 #ifndef TARGET_SWITCH_SH4A_NOFPU
501 #define TARGET_SWITCH_SH4A_NOFPU \
502 {"4a-nofpu", TARGET_NONE, "" },\
503 {"4a-nofpu", SELECT_SH4A_NOFPU, "Generate SH4a FPU-less code" },
505 #ifndef TARGET_SWITCH_SH4AL
506 #define TARGET_SWITCH_SH4AL \
507 {"4al", TARGET_NONE, "" },\
508 {"4al", SELECT_SH4A_NOFPU, "Generate SH4al-dsp code" },
510 #ifndef TARGET_SWITCH_SH5_64MEDIA
511 #define TARGET_SWITCH_SH5_64MEDIA \
512 {"5-64media", TARGET_NONE, "" }, \
513 {"5-64media", SELECT_SH5_64MEDIA, "Generate 64-bit SHmedia code" },
515 #ifndef TARGET_SWITCH_SH5_64MEDIA_NOFPU
516 #define TARGET_SWITCH_SH5_64MEDIA_NOFPU \
517 {"5-64media-nofpu", TARGET_NONE, "" }, \
518 {"5-64media-nofpu", SELECT_SH5_64MEDIA_NOFPU, "Generate 64-bit FPU-less SHmedia code" },
520 #ifndef TARGET_SWITCHES_SH5_32MEDIA
521 #define TARGET_SWITCHES_SH5_32MEDIA \
522 {"5-32media", TARGET_NONE, "" }, \
523 {"5-32media", SELECT_SH5_32MEDIA, "Generate 32-bit SHmedia code" }, \
524 {"5-compact", TARGET_NONE, "" }, \
525 {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" },
527 #ifndef TARGET_SWITCHES_SH5_32MEDIA_NOFPU
528 #define TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
529 {"5-32media-nofpu", TARGET_NONE, "" }, \
530 {"5-32media-nofpu", SELECT_SH5_32MEDIA_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
531 {"5-compact-nofpu", TARGET_NONE, "" }, \
532 {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" },
535 #define TARGET_SWITCHES \
536 { TARGET_SWITCH_SH1 \
538 TARGET_SWITCH_SH2A_SINGLE_ONLY \
539 TARGET_SWITCH_SH2A_SINGLE \
540 TARGET_SWITCH_SH2A_NOFPU \
545 TARGET_SWITCH_SH4_SINGLE_ONLY \
546 TARGET_SWITCH_SH4_SINGLE \
547 TARGET_SWITCH_SH4_NOFPU \
549 TARGET_SWITCH_SH4A_SINGLE_ONLY \
550 TARGET_SWITCH_SH4A_SINGLE \
551 TARGET_SWITCH_SH4A_NOFPU \
553 TARGET_SWITCH_SH4AL \
554 TARGET_SWITCH_SH5_64MEDIA \
555 TARGET_SWITCH_SH5_64MEDIA_NOFPU \
556 TARGET_SWITCHES_SH5_32MEDIA \
557 TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
558 {"b", -LITTLE_ENDIAN_BIT, "Generate code in big endian mode" }, \
559 {"bigtable", BIGTABLE_BIT, "Generate 32-bit offsets in switch tables" }, \
560 {"dalign", DALIGN_BIT, "Aligns doubles at 64-bit boundaries" }, \
561 {"fmovd", FMOVD_BIT, "" }, \
562 {"hitachi", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
563 {"renesas", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
564 {"no-renesas",-HITACHI_BIT,"Follow the GCC calling conventions" }, \
565 {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" }, \
566 {"ieee", IEEE_BIT, "Increase the IEEE compliance for floating-point code" }, \
567 {"isize", ISIZE_BIT, "" }, \
568 {"l", LITTLE_ENDIAN_BIT, "Generate code in little endian mode" }, \
569 {"no-ieee", -IEEE_BIT, "" }, \
570 {"padstruct", PADSTRUCT_BIT, "" }, \
571 {"prefergot", PREFERGOT_BIT, "Emit function-calls using global offset table when generating PIC" }, \
572 {"relax", RELAX_BIT, "Shorten address references during linking" }, \
573 {"space", SPACE_BIT, "Deprecated. Use -Os instead" }, \
574 {"usermode", USERMODE_BIT, "Generate library function call to invalidate instruction cache entries after fixing trampoline" }, \
576 {"", TARGET_DEFAULT, "" } \
579 /* This are meant to be redefined in the host dependent files */
580 #define SUBTARGET_SWITCHES
582 /* This defaults us to big-endian. */
583 #ifndef TARGET_ENDIAN_DEFAULT
584 #define TARGET_ENDIAN_DEFAULT 0
587 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
589 #ifndef SH_MULTILIB_CPU_DEFAULT
590 #define SH_MULTILIB_CPU_DEFAULT "m1"
593 #if TARGET_ENDIAN_DEFAULT
594 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
596 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
599 #define CPP_SPEC " %(subtarget_cpp_spec) "
601 #ifndef SUBTARGET_CPP_SPEC
602 #define SUBTARGET_CPP_SPEC ""
605 #ifndef SUBTARGET_EXTRA_SPECS
606 #define SUBTARGET_EXTRA_SPECS
609 #define EXTRA_SPECS \
610 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
611 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
612 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
613 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
614 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
615 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
616 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
617 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
618 SUBTARGET_EXTRA_SPECS
620 #if TARGET_CPU_DEFAULT & HARD_SH4_BIT
621 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
623 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
626 #define SH_ASM_SPEC \
627 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
628 %(subtarget_asm_isa_spec) %{m4al:-dsp}"
630 #define ASM_SPEC SH_ASM_SPEC
632 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
633 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
634 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
636 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
640 #define SUBTARGET_ASM_ISA_SPEC ""
642 #define LINK_EMUL_PREFIX "sh%{ml:l}"
644 #if TARGET_CPU_DEFAULT & SH5_BIT
645 #if TARGET_CPU_DEFAULT & SH_E_BIT
646 #define LINK_DEFAULT_CPU_EMUL "32"
647 #if TARGET_CPU_DEFAULT & SH1_BIT
648 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
650 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
652 #else /* !SH_E_BIT */
653 #define LINK_DEFAULT_CPU_EMUL "64"
654 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
655 #endif /* SH_E_BIT */
656 #define ASM_ISA_DEFAULT_SPEC \
657 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
659 #define LINK_DEFAULT_CPU_EMUL ""
660 #define ASM_ISA_DEFAULT_SPEC ""
663 #define SUBTARGET_LINK_EMUL_SUFFIX ""
664 #define SUBTARGET_LINK_SPEC ""
666 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
667 so that we can undo the damage without code replication. */
668 #define LINK_SPEC SH_LINK_SPEC
670 #define SH_LINK_SPEC "\
671 -m %(link_emul_prefix)\
672 %{m5-compact*|m5-32media*:32}\
674 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
675 %(subtarget_link_emul_suffix) \
676 %{mrelax:-relax} %(subtarget_link_spec)"
678 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
679 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
682 flag_omit_frame_pointer = -1; \
684 target_flags |= SPACE_BIT; \
685 if (TARGET_SHMEDIA && LEVEL > 1) \
687 flag_branch_target_load_optimize = 1; \
689 target_flags |= SAVE_ALL_TR_BIT; \
693 #define ASSEMBLER_DIALECT assembler_dialect
695 extern int assembler_dialect;
697 #define OVERRIDE_OPTIONS \
702 assembler_dialect = 0; \
710 if (TARGET_SH2A_DOUBLE) \
711 target_flags |= FMOVD_BIT; \
719 assembler_dialect = 1; \
722 if (TARGET_SH4A_ARCH) \
724 assembler_dialect = 1; \
730 target_flags |= DALIGN_BIT; \
732 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN)) \
733 target_flags |= FMOVD_BIT; \
734 if (TARGET_SHMEDIA) \
736 /* There are no delay slots on SHmedia. */ \
737 flag_delayed_branch = 0; \
738 /* Relaxation isn't yet supported for SHmedia */ \
739 target_flags &= ~RELAX_BIT; \
741 /* -fprofile-arcs needs a working libgcov . In unified tree \
742 configurations with newlib, this requires to configure with \
743 --with-newlib --with-headers. But there is no way to check \
744 here we have a working libgcov, so just assume that we have. */\
747 warning ("Profiling is not supported on this target."); \
748 profile_flag = profile_arc_flag = 0; \
753 /* Only the sh64-elf assembler fully supports .quad properly. */\
754 targetm.asm_out.aligned_op.di = NULL; \
755 targetm.asm_out.unaligned_op.di = NULL; \
758 reg_class_from_letter['e' - 'a'] = NO_REGS; \
760 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
761 if (! VALID_REGISTER_P (regno)) \
762 sh_register_names[regno][0] = '\0'; \
764 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
765 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
766 sh_additional_register_names[regno][0] = '\0'; \
768 if (flag_omit_frame_pointer < 0) \
770 /* The debugging information is sufficient, \
771 but gdb doesn't implement this yet */ \
773 flag_omit_frame_pointer \
774 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
775 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
777 flag_omit_frame_pointer = 0; \
780 if (flag_pic && ! TARGET_PREFERGOT) \
781 flag_no_function_cse = 1; \
783 if (SMALL_REGISTER_CLASSES) \
785 /* Never run scheduling before reload, since that can \
786 break global alloc, and generates slower code anyway due \
787 to the pressure on R0. */ \
788 /* Enable sched1 for SH4; ready queue will be reordered by \
789 the target hooks when pressure is high. We can not do this for \
790 SH3 and lower as they give spill failures for R0. */ \
791 if (!TARGET_HARD_SH4) \
792 flag_schedule_insns = 0; \
795 if (align_loops == 0) \
796 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
797 if (align_jumps == 0) \
798 align_jumps = 1 << CACHE_LOG; \
799 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
800 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
802 /* Allocation boundary (in *bytes*) for the code of a function. \
803 SH1: 32 bit alignment is faster, because instructions are always \
804 fetched as a pair from a longword boundary. \
805 SH2 .. SH5 : align to cache line start. */ \
806 if (align_functions == 0) \
808 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
809 /* The linker relaxation code breaks when a function contains \
810 alignments that are larger than that at the start of a \
811 compilation unit. */ \
815 = align_loops > align_jumps ? align_loops : align_jumps; \
817 /* Also take possible .long constants / mova tables int account. */\
820 if (align_functions < min_align) \
821 align_functions = min_align; \
825 /* Target machine storage layout. */
827 /* Define this if most significant bit is lowest numbered
828 in instructions that operate on numbered bit-fields. */
830 #define BITS_BIG_ENDIAN 0
832 /* Define this if most significant byte of a word is the lowest numbered. */
833 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
835 /* Define this if most significant word of a multiword number is the lowest
837 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
839 /* Define this to set the endianness to use in libgcc2.c, which can
840 not depend on target_flags. */
841 #if defined(__LITTLE_ENDIAN__)
842 #define LIBGCC2_WORDS_BIG_ENDIAN 0
844 #define LIBGCC2_WORDS_BIG_ENDIAN 1
847 #define MAX_BITS_PER_WORD 64
849 /* Width in bits of an `int'. We want just 32-bits, even if words are
851 #define INT_TYPE_SIZE 32
853 /* Width in bits of a `long'. */
854 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
856 /* Width in bits of a `long long'. */
857 #define LONG_LONG_TYPE_SIZE 64
859 /* Width in bits of a `long double'. */
860 #define LONG_DOUBLE_TYPE_SIZE 64
862 /* Width of a word, in units (bytes). */
863 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
864 #define MIN_UNITS_PER_WORD 4
866 /* Scaling factor for Dwarf data offsets for CFI information.
867 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
868 SHmedia; however, since we do partial register saves for the registers
869 visible to SHcompact, and for target registers for SHMEDIA32, we have
870 to allow saves that are only 4-byte aligned. */
871 #define DWARF_CIE_DATA_ALIGNMENT -4
873 /* Width in bits of a pointer.
874 See also the macro `Pmode' defined below. */
875 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
877 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
878 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
880 /* Boundary (in *bits*) on which stack pointer should be aligned. */
881 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
883 /* The log (base 2) of the cache line size, in bytes. Processors prior to
884 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
885 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
886 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
888 /* ABI given & required minimum allocation boundary (in *bits*) for the
889 code of a function. */
890 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
892 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
893 the vbit must go into the delta field of
894 pointers-to-member-functions. */
895 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
896 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
898 /* Alignment of field after `int : 0' in a structure. */
899 #define EMPTY_FIELD_BOUNDARY 32
901 /* No data type wants to be aligned rounder than this. */
902 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
904 /* The best alignment to use in cases where we have a choice. */
905 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
907 /* Make strings word-aligned so strcpy from constants will be faster. */
908 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
909 ((TREE_CODE (EXP) == STRING_CST \
910 && (ALIGN) < FASTEST_ALIGNMENT) \
911 ? FASTEST_ALIGNMENT : (ALIGN))
913 /* get_mode_alignment assumes complex values are always held in multiple
914 registers, but that is not the case on the SH; CQImode and CHImode are
915 held in a single integer register. SH5 also holds CSImode and SCmode
916 values in integer registers. This is relevant for argument passing on
917 SHcompact as we use a stack temp in order to pass CSImode by reference. */
918 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
919 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
920 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
921 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
924 /* Make arrays of chars word-aligned for the same reasons. */
925 #define DATA_ALIGNMENT(TYPE, ALIGN) \
926 (TREE_CODE (TYPE) == ARRAY_TYPE \
927 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
928 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
930 /* Number of bits which any structure or union's size must be a
931 multiple of. Each structure or union's size is rounded up to a
933 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
935 /* Set this nonzero if move instructions will actually fail to work
936 when given unaligned data. */
937 #define STRICT_ALIGNMENT 1
939 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
940 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
941 barrier_align (LABEL_AFTER_BARRIER)
943 #define LOOP_ALIGN(A_LABEL) \
944 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
945 ? 0 : sh_loop_align (A_LABEL))
947 #define LABEL_ALIGN(A_LABEL) \
949 (PREV_INSN (A_LABEL) \
950 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
951 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
952 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
953 /* explicit alignment insn in constant tables. */ \
954 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
957 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
958 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
960 /* The base two logarithm of the known minimum alignment of an insn length. */
961 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
962 (GET_CODE (A_INSN) == INSN \
963 ? 1 << TARGET_SHMEDIA \
964 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
965 ? 1 << TARGET_SHMEDIA \
968 /* Standard register usage. */
970 /* Register allocation for the Renesas calling convention:
976 r14 frame pointer/call saved
978 ap arg pointer (doesn't really exist, always eliminated)
979 pr subroutine return address
981 mach multiply/accumulate result, high part
982 macl multiply/accumulate result, low part.
983 fpul fp/int communication register
984 rap return address pointer register
986 fr1..fr3 scratch floating point registers
988 fr12..fr15 call saved floating point registers */
990 #define MAX_REGISTER_NAME_LENGTH 5
991 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
993 #define SH_REGISTER_NAMES_INITIALIZER \
995 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
996 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
997 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
998 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
999 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
1000 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
1001 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
1002 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
1003 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1004 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
1005 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
1006 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
1007 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
1008 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
1009 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
1010 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
1011 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
1012 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
1013 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
1017 #define REGNAMES_ARR_INDEX_1(index) \
1018 (sh_register_names[index])
1019 #define REGNAMES_ARR_INDEX_2(index) \
1020 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
1021 #define REGNAMES_ARR_INDEX_4(index) \
1022 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
1023 #define REGNAMES_ARR_INDEX_8(index) \
1024 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
1025 #define REGNAMES_ARR_INDEX_16(index) \
1026 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
1027 #define REGNAMES_ARR_INDEX_32(index) \
1028 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
1029 #define REGNAMES_ARR_INDEX_64(index) \
1030 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
1032 #define REGISTER_NAMES \
1034 REGNAMES_ARR_INDEX_64 (0), \
1035 REGNAMES_ARR_INDEX_64 (64), \
1036 REGNAMES_ARR_INDEX_8 (128), \
1037 REGNAMES_ARR_INDEX_8 (136), \
1038 REGNAMES_ARR_INDEX_8 (144), \
1039 REGNAMES_ARR_INDEX_1 (152) \
1042 #define ADDREGNAMES_SIZE 32
1043 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
1044 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
1045 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
1047 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
1049 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
1050 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
1051 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
1052 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
1055 #define ADDREGNAMES_REGNO(index) \
1056 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
1059 #define ADDREGNAMES_ARR_INDEX_1(index) \
1060 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
1061 #define ADDREGNAMES_ARR_INDEX_2(index) \
1062 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
1063 #define ADDREGNAMES_ARR_INDEX_4(index) \
1064 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
1065 #define ADDREGNAMES_ARR_INDEX_8(index) \
1066 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
1067 #define ADDREGNAMES_ARR_INDEX_16(index) \
1068 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
1069 #define ADDREGNAMES_ARR_INDEX_32(index) \
1070 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
1072 #define ADDITIONAL_REGISTER_NAMES \
1074 ADDREGNAMES_ARR_INDEX_32 (0) \
1077 /* Number of actual hardware registers.
1078 The hardware registers are assigned numbers for the compiler
1079 from 0 to just below FIRST_PSEUDO_REGISTER.
1080 All registers that the compiler knows about must be given numbers,
1081 even those that are not normally considered general registers. */
1083 /* There are many other relevant definitions in sh.md's md_constants. */
1085 #define FIRST_GENERAL_REG R0_REG
1086 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1087 #define FIRST_FP_REG DR0_REG
1088 #define LAST_FP_REG (FIRST_FP_REG + \
1089 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1090 #define FIRST_XD_REG XD0_REG
1091 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1092 #define FIRST_TARGET_REG TR0_REG
1093 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1095 #define GENERAL_REGISTER_P(REGNO) \
1096 IN_RANGE ((REGNO), \
1097 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1098 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1100 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1101 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
1103 #define FP_REGISTER_P(REGNO) \
1104 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1106 #define XD_REGISTER_P(REGNO) \
1107 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1109 #define FP_OR_XD_REGISTER_P(REGNO) \
1110 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1112 #define FP_ANY_REGISTER_P(REGNO) \
1113 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1115 #define SPECIAL_REGISTER_P(REGNO) \
1116 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1117 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1119 #define TARGET_REGISTER_P(REGNO) \
1120 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1122 #define SHMEDIA_REGISTER_P(REGNO) \
1123 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1124 || TARGET_REGISTER_P (REGNO))
1126 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1127 that should be fixed. */
1128 #define VALID_REGISTER_P(REGNO) \
1129 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1130 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1131 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1132 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1134 /* The mode that should be generally used to store a register by
1135 itself in the stack, or to load it back. */
1136 #define REGISTER_NATURAL_MODE(REGNO) \
1137 (FP_REGISTER_P (REGNO) ? SFmode \
1138 : XD_REGISTER_P (REGNO) ? DFmode \
1139 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1143 #define FIRST_PSEUDO_REGISTER 153
1145 /* 1 for registers that have pervasive standard uses
1146 and are not available for the register allocator.
1148 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1149 It is 32 bits wide for SH2. */
1151 #define FIXED_REGISTERS \
1153 /* Regular registers. */ \
1154 0, 0, 0, 0, 0, 0, 0, 0, \
1155 0, 0, 0, 0, 0, 0, 0, 1, \
1156 /* r16 is reserved, r18 is the former pr. */ \
1157 1, 0, 0, 0, 0, 0, 0, 0, \
1158 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1159 /* r26 is a global variable data pointer; r27 is for constants. */ \
1160 1, 1, 1, 1, 0, 0, 0, 0, \
1161 0, 0, 0, 0, 0, 0, 0, 0, \
1162 0, 0, 0, 0, 0, 0, 0, 0, \
1163 0, 0, 0, 0, 0, 0, 0, 0, \
1164 0, 0, 0, 0, 0, 0, 0, 1, \
1165 /* FP registers. */ \
1166 0, 0, 0, 0, 0, 0, 0, 0, \
1167 0, 0, 0, 0, 0, 0, 0, 0, \
1168 0, 0, 0, 0, 0, 0, 0, 0, \
1169 0, 0, 0, 0, 0, 0, 0, 0, \
1170 0, 0, 0, 0, 0, 0, 0, 0, \
1171 0, 0, 0, 0, 0, 0, 0, 0, \
1172 0, 0, 0, 0, 0, 0, 0, 0, \
1173 0, 0, 0, 0, 0, 0, 0, 0, \
1174 /* Branch target registers. */ \
1175 0, 0, 0, 0, 0, 0, 0, 0, \
1176 /* XD registers. */ \
1177 0, 0, 0, 0, 0, 0, 0, 0, \
1178 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1179 1, 1, 1, 1, 1, 1, 0, 1, \
1184 /* 1 for registers not available across function calls.
1185 These must include the FIXED_REGISTERS and also any
1186 registers that can be used without being saved.
1187 The latter must include the registers where values are returned
1188 and the register where structure-value addresses are passed.
1189 Aside from that, you can include as many other registers as you like. */
1191 #define CALL_USED_REGISTERS \
1193 /* Regular registers. */ \
1194 1, 1, 1, 1, 1, 1, 1, 1, \
1195 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1196 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1197 across SH5 function calls. */ \
1198 0, 0, 0, 0, 0, 0, 0, 1, \
1199 1, 1, 1, 1, 1, 1, 1, 1, \
1200 1, 1, 1, 1, 0, 0, 0, 0, \
1201 0, 0, 0, 0, 1, 1, 1, 1, \
1202 1, 1, 1, 1, 0, 0, 0, 0, \
1203 0, 0, 0, 0, 0, 0, 0, 0, \
1204 0, 0, 0, 0, 1, 1, 1, 1, \
1205 /* FP registers. */ \
1206 1, 1, 1, 1, 1, 1, 1, 1, \
1207 1, 1, 1, 1, 0, 0, 0, 0, \
1208 1, 1, 1, 1, 1, 1, 1, 1, \
1209 1, 1, 1, 1, 1, 1, 1, 1, \
1210 1, 1, 1, 1, 0, 0, 0, 0, \
1211 0, 0, 0, 0, 0, 0, 0, 0, \
1212 0, 0, 0, 0, 0, 0, 0, 0, \
1213 0, 0, 0, 0, 0, 0, 0, 0, \
1214 /* Branch target registers. */ \
1215 1, 1, 1, 1, 1, 0, 0, 0, \
1216 /* XD registers. */ \
1217 1, 1, 1, 1, 1, 1, 0, 0, \
1218 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1219 1, 1, 1, 1, 1, 1, 1, 1, \
1224 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1225 across SHcompact function calls. We can't tell whether a called
1226 function is SHmedia or SHcompact, so we assume it may be when
1227 compiling SHmedia code with the 32-bit ABI, since that's the only
1228 ABI that can be linked with SHcompact code. */
1229 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1231 && GET_MODE_SIZE (MODE) > 4 \
1232 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1233 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1234 || TARGET_REGISTER_P (REGNO) \
1235 || (REGNO) == PR_MEDIA_REG))
1237 /* Return number of consecutive hard regs needed starting at reg REGNO
1238 to hold something of mode MODE.
1239 This is ordinarily the length in words of a value of mode MODE
1240 but can be less for certain modes in special long registers.
1242 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1244 #define HARD_REGNO_NREGS(REGNO, MODE) \
1245 (XD_REGISTER_P (REGNO) \
1246 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1247 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1248 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1249 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1251 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1252 We can allow any mode in any general register. The special registers
1253 only allow SImode. Don't allow any mode in the PR. */
1255 /* We cannot hold DCmode values in the XD registers because alter_reg
1256 handles subregs of them incorrectly. We could work around this by
1257 spacing the XD registers like the DR registers, but this would require
1258 additional memory in every compilation to hold larger register vectors.
1259 We could hold SFmode / SCmode values in XD registers, but that
1260 would require a tertiary reload when reloading from / to memory,
1261 and a secondary reload to reload from / to general regs; that
1262 seems to be a loosing proposition. */
1263 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1264 it won't be ferried through GP registers first. */
1265 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1266 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1267 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1268 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1270 : (MODE) == V2SFmode \
1271 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1272 || GENERAL_REGISTER_P (REGNO)) \
1273 : (MODE) == V4SFmode \
1274 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1275 || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
1276 : (MODE) == V16SFmode \
1278 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1279 : (REGNO) == FIRST_XD_REG) \
1280 : FP_REGISTER_P (REGNO) \
1281 ? ((MODE) == SFmode || (MODE) == SImode \
1282 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1283 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1284 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1285 || (MODE) == V2SFmode || (MODE) == TImode))) \
1286 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
1287 : XD_REGISTER_P (REGNO) \
1288 ? (MODE) == DFmode \
1289 : TARGET_REGISTER_P (REGNO) \
1290 ? ((MODE) == DImode || (MODE) == SImode) \
1291 : (REGNO) == PR_REG ? (MODE) == SImode \
1292 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1295 /* Value is 1 if MODE is a supported vector mode. */
1296 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1298 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
1299 || (TARGET_SHMEDIA \
1300 && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
1301 || (MODE) == V2SImode)))
1303 /* Value is 1 if it is a good idea to tie two pseudo registers
1304 when one has mode MODE1 and one has mode MODE2.
1305 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1306 for any hard reg, then this must be 0 for correct output.
1307 That's the case for xd registers: we don't hold SFmode values in
1308 them, so we can't tie an SFmode pseudos with one in another
1309 floating-point mode. */
1311 #define MODES_TIEABLE_P(MODE1, MODE2) \
1312 ((MODE1) == (MODE2) \
1313 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1314 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1315 && (GET_MODE_SIZE (MODE2) <= 4)) \
1316 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1318 /* A C expression that is nonzero if hard register NEW_REG can be
1319 considered for use as a rename register for OLD_REG register */
1321 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1322 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1324 /* Specify the registers used for certain standard purposes.
1325 The values of these macros are register numbers. */
1327 /* Define this if the program counter is overloaded on a register. */
1328 /* #define PC_REGNUM 15*/
1330 /* Register to use for pushing function arguments. */
1331 #define STACK_POINTER_REGNUM SP_REG
1333 /* Base register for access to local variables of the function. */
1334 #define FRAME_POINTER_REGNUM FP_REG
1336 /* Fake register that holds the address on the stack of the
1337 current function's return address. */
1338 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1340 /* Register to hold the addressing base for position independent
1341 code access to data items. */
1342 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1344 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1346 /* Value should be nonzero if functions must have frame pointers.
1347 Zero means the frame pointer need not be set up (and parms may be accessed
1348 via the stack pointer) in functions that seem suitable. */
1350 #define FRAME_POINTER_REQUIRED 0
1352 /* Definitions for register eliminations.
1354 We have three registers that can be eliminated on the SH. First, the
1355 frame pointer register can often be eliminated in favor of the stack
1356 pointer register. Secondly, the argument pointer register can always be
1357 eliminated; it is replaced with either the stack or frame pointer.
1358 Third, there is the return address pointer, which can also be replaced
1359 with either the stack or the frame pointer. */
1361 /* This is an array of structures. Each structure initializes one pair
1362 of eliminable registers. The "from" register number is given first,
1363 followed by "to". Eliminations of the same "from" register are listed
1364 in order of preference. */
1366 /* If you add any registers here that are not actually hard registers,
1367 and that have any alternative of elimination that doesn't always
1368 apply, you need to amend calc_live_regs to exclude it, because
1369 reload spills all eliminable registers where it sees an
1370 can_eliminate == 0 entry, thus making them 'live' .
1371 If you add any hard registers that can be eliminated in different
1372 ways, you have to patch reload to spill them only when all alternatives
1373 of elimination fail. */
1375 #define ELIMINABLE_REGS \
1376 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1377 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1378 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1379 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1380 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1382 /* Given FROM and TO register numbers, say whether this elimination
1384 #define CAN_ELIMINATE(FROM, TO) \
1385 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1387 /* Define the offset between two registers, one to be eliminated, and the other
1388 its replacement, at the start of a routine. */
1390 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1391 OFFSET = initial_elimination_offset ((FROM), (TO))
1393 /* Base register for access to arguments of the function. */
1394 #define ARG_POINTER_REGNUM AP_REG
1396 /* Register in which the static-chain is passed to a function. */
1397 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1399 /* Don't default to pcc-struct-return, because we have already specified
1400 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1403 #define DEFAULT_PCC_STRUCT_RETURN 0
1405 #define SHMEDIA_REGS_STACK_ADJUST() \
1406 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1407 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1408 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1412 /* Define the classes of registers for register constraints in the
1413 machine description. Also define ranges of constants.
1415 One of the classes must always be named ALL_REGS and include all hard regs.
1416 If there is more than one class, another class must be named NO_REGS
1417 and contain no registers.
1419 The name GENERAL_REGS must be the name of a class (or an alias for
1420 another name such as ALL_REGS). This is the class of registers
1421 that is allowed by "g" or "r" in a register constraint.
1422 Also, registers outside this class are allocated only when
1423 instructions express preferences for them.
1425 The classes must be numbered in nondecreasing order; that is,
1426 a larger-numbered class must never be contained completely
1427 in a smaller-numbered class.
1429 For any two classes, it is very desirable that there be another
1430 class that represents their union. */
1432 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1433 be used as the destination of some of the arithmetic ops. There are
1434 also some special purpose registers; the T bit register, the
1435 Procedure Return Register and the Multiply Accumulate Registers. */
1436 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1437 reg_class_subunion. We don't want to have an actual union class
1438 of these, because it would only be used when both classes are calculated
1439 to give the same cost, but there is only one FPUL register.
1440 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1441 applying to the actual instruction alternative considered. E.g., the
1442 y/r alternative of movsi_ie is considered to have no more cost that
1443 the r/r alternative, which is patently untrue. */
1466 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1468 /* Give names of register classes as strings for dump file. */
1469 #define REG_CLASS_NAMES \
1484 "GENERAL_FP_REGS", \
1489 /* Define which registers fit in which classes.
1490 This is an initializer for a vector of HARD_REG_SET
1491 of length N_REG_CLASSES. */
1493 #define REG_CLASS_CONTENTS \
1496 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1498 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1500 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1502 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1504 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1506 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1507 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1508 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1509 /* GENERAL_REGS: */ \
1510 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1512 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1514 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1515 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1516 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1518 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1520 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1521 /* GENERAL_FP_REGS: */ \
1522 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1523 /* TARGET_REGS: */ \
1524 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1526 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1529 /* The same information, inverted:
1530 Return the class number of the smallest class containing
1531 reg number REGNO. This could be a conditional expression
1532 or could index an array. */
1534 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1535 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1537 /* When defined, the compiler allows registers explicitly used in the
1538 rtl to be used as spill registers but prevents the compiler from
1539 extending the lifetime of these registers. */
1541 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1543 /* The order in which register should be allocated. */
1544 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1545 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1546 spilled or used otherwise, we better have the FP_REGS allocated first. */
1547 #define REG_ALLOC_ORDER \
1548 {/* Caller-saved FPRs */ \
1549 65, 66, 67, 68, 69, 70, 71, 64, \
1550 72, 73, 74, 75, 80, 81, 82, 83, \
1551 84, 85, 86, 87, 88, 89, 90, 91, \
1552 92, 93, 94, 95, 96, 97, 98, 99, \
1553 /* Callee-saved FPRs */ \
1554 76, 77, 78, 79,100,101,102,103, \
1555 104,105,106,107,108,109,110,111, \
1556 112,113,114,115,116,117,118,119, \
1557 120,121,122,123,124,125,126,127, \
1558 136,137,138,139,140,141,142,143, \
1560 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1561 1, 2, 3, 7, 6, 5, 4, 0, \
1562 8, 9, 17, 19, 20, 21, 22, 23, \
1563 36, 37, 38, 39, 40, 41, 42, 43, \
1565 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1566 10, 11, 12, 13, 14, 18, \
1567 /* SH5 callee-saved GPRs */ \
1568 28, 29, 30, 31, 32, 33, 34, 35, \
1569 44, 45, 46, 47, 48, 49, 50, 51, \
1570 52, 53, 54, 55, 56, 57, 58, 59, \
1572 /* SH5 branch target registers */ \
1573 128,129,130,131,132,133,134,135, \
1574 /* Fixed registers */ \
1575 15, 16, 24, 25, 26, 27, 63,144, \
1576 145,146,147,148,149,152 }
1578 /* The class value for index registers, and the one for base regs. */
1579 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1580 #define BASE_REG_CLASS GENERAL_REGS
1582 /* Get reg_class from a letter such as appears in the machine
1584 extern enum reg_class reg_class_from_letter[];
1586 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1587 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1588 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1590 /* Overview of uppercase letter constraints:
1591 A: Addresses (constraint len == 3)
1592 Ac4: sh4 cache operations
1593 Ac5: sh5 cache operations
1594 Bxx: miscellaneous constraints
1595 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1597 C: Constants other than only CONST_INT (constraint len == 3)
1598 C16: 16 bit constant, literal or symbolic
1599 Csy: label or symbol
1600 Cpg: non-explicit constants that can be directly loaded into a general
1601 purpose register in PIC code. like 's' except we don't allow
1603 IJKLMNOP: CONT_INT constants
1605 J16: 0xffffffff00000000 | 0x00000000ffffffff
1606 Kxx: unsigned xx bit
1610 Q: pc relative load operand
1611 Rxx: reserved for exotic register classes.
1612 S: extra memory (storage) constraints (constraint len == 3)
1613 Sua: unaligned memory operations
1617 unused CONST_INT constraint letters: LO
1618 unused EXTRA_CONSTRAINT letters: D T U Y */
1620 #if 1 /* check that the transition went well. */
1621 #define CONSTRAINT_LEN(C,STR) \
1622 (((C) == 'L' || (C) == 'O' || (C) == 'D' || (C) == 'T' || (C) == 'U' \
1625 && (((STR)[1] != '0' && (STR)[1] != '1' && (STR)[1] != '2') \
1626 || (STR)[2] < '0' || (STR)[2] > '9')) \
1627 || ((C) == 'B' && ((STR)[1] != 's' || (STR)[2] != 'c')) \
1628 || ((C) == 'J' && ((STR)[1] != '1' || (STR)[2] != '6')) \
1629 || ((C) == 'K' && ((STR)[1] != '0' || (STR)[2] != '8')) \
1630 || ((C) == 'P' && ((STR)[1] != '2' || (STR)[2] != '7'))) \
1632 : ((C) == 'A' || (C) == 'B' || (C) == 'C' \
1633 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1634 || (C) == 'R' || (C) == 'S') \
1636 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1638 #define CONSTRAINT_LEN(C,STR) \
1639 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1640 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1641 || (C) == 'R' || (C) == 'S') \
1642 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1645 /* The letters I, J, K, L and M in a register constraint string
1646 can be used to stand for particular ranges of immediate operands.
1647 This macro defines what the ranges are.
1648 C is the letter, and VALUE is a constant value.
1649 Return 1 if VALUE is in the range specified by C.
1650 I08: arithmetic operand -127..128, as used in add, sub, etc
1651 I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1652 P27: shift operand 1,2,8 or 16
1653 K08: logical operand 0..255, as used in and, or, etc.
1656 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1657 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1660 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1661 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1662 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1663 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1664 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1665 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1666 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1667 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1668 #define CONST_OK_FOR_I20(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -524288 \
1669 && ((HOST_WIDE_INT)(VALUE)) <= 524287 \
1671 #define CONST_OK_FOR_I(VALUE, STR) \
1672 ((STR)[1] == '0' && (STR)[2] == 6 ? CONST_OK_FOR_I06 (VALUE) \
1673 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1674 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1675 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1676 : (STR)[1] == '2' && (STR)[2] == '0' ? CONST_OK_FOR_I20 (VALUE) \
1679 #define CONST_OK_FOR_J16(VALUE) \
1680 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1681 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1682 #define CONST_OK_FOR_J(VALUE, STR) \
1683 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1686 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1687 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1688 #define CONST_OK_FOR_K(VALUE, STR) \
1689 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1691 #define CONST_OK_FOR_P27(VALUE) \
1692 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1693 #define CONST_OK_FOR_P(VALUE, STR) \
1694 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1696 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1697 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1698 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1699 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1700 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1701 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1702 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1703 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1704 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1707 /* Similar, but for floating constants, and defining letters G and H.
1708 Here VALUE is the CONST_DOUBLE rtx itself. */
1710 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1711 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1712 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1715 /* Given an rtx X being reloaded into a reg required to be
1716 in class CLASS, return the class of reg to actually use.
1717 In general this is just CLASS; but on some machines
1718 in some cases it is preferable to use a more restrictive class. */
1720 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1721 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1722 && (GET_CODE (X) == CONST_DOUBLE \
1723 || GET_CODE (X) == SYMBOL_REF) \
1727 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1728 ((((REGCLASS_HAS_FP_REG (CLASS) \
1729 && (GET_CODE (X) == REG \
1730 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1731 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1732 && TARGET_FMOVD)))) \
1733 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1734 && GET_CODE (X) == REG \
1735 && FP_REGISTER_P (REGNO (X)))) \
1736 && ! TARGET_SHMEDIA \
1737 && ((MODE) == SFmode || (MODE) == SImode)) \
1739 : (((CLASS) == FPUL_REGS \
1740 || (REGCLASS_HAS_FP_REG (CLASS) \
1741 && ! TARGET_SHMEDIA && MODE == SImode)) \
1742 && (GET_CODE (X) == MEM \
1743 || (GET_CODE (X) == REG \
1744 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1745 || REGNO (X) == T_REG \
1746 || system_reg_operand (X, VOIDmode))))) \
1748 : ((CLASS) == TARGET_REGS \
1749 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1750 ? ((target_operand ((X), (MODE)) \
1751 && ! target_reg_operand ((X), (MODE))) \
1752 ? NO_REGS : GENERAL_REGS) \
1753 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1754 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1755 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1757 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1758 && TARGET_REGISTER_P (REGNO (X))) \
1759 ? GENERAL_REGS : NO_REGS)
1761 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1762 ((REGCLASS_HAS_FP_REG (CLASS) \
1763 && ! TARGET_SHMEDIA \
1764 && immediate_operand ((X), (MODE)) \
1765 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1766 && (MODE) == SFmode && fldi_ok ())) \
1768 : (CLASS == FPUL_REGS \
1769 && ((GET_CODE (X) == REG \
1770 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1771 || REGNO (X) == T_REG)) \
1772 || GET_CODE (X) == PLUS)) \
1774 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1775 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1778 : (CLASS == FPSCR_REGS \
1779 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1780 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1782 : (REGCLASS_HAS_FP_REG (CLASS) \
1784 && immediate_operand ((X), (MODE)) \
1785 && (X) != CONST0_RTX (GET_MODE (X)) \
1786 && GET_MODE (X) != V4SFmode) \
1788 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1790 /* Return the maximum number of consecutive registers
1791 needed to represent mode MODE in a register of class CLASS.
1793 If TARGET_SHMEDIA, we need two FP registers per word.
1794 Otherwise we will need at most one register per word. */
1795 #define CLASS_MAX_NREGS(CLASS, MODE) \
1797 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1798 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1799 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1801 /* If defined, gives a class of registers that cannot be used as the
1802 operand of a SUBREG that changes the mode of the object illegally. */
1803 /* ??? We need to renumber the internal numbers for the frnn registers
1804 when in little endian in order to allow mode size changes. */
1806 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1807 sh_cannot_change_mode_class (FROM, TO, CLASS)
1809 /* Stack layout; function entry, exit and calling. */
1811 /* Define the number of registers that can hold parameters.
1812 These macros are used only in other macro definitions below. */
1814 #define NPARM_REGS(MODE) \
1815 (TARGET_FPU_ANY && (MODE) == SFmode \
1816 ? (TARGET_SH5 ? 12 : 8) \
1817 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1818 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1819 ? (TARGET_SH5 ? 12 : 8) \
1820 : (TARGET_SH5 ? 8 : 4))
1822 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1823 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1825 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1826 #define FIRST_FP_RET_REG FIRST_FP_REG
1828 /* Define this if pushing a word on the stack
1829 makes the stack pointer a smaller address. */
1830 #define STACK_GROWS_DOWNWARD
1832 /* Define this macro if the addresses of local variable slots are at
1833 negative offsets from the frame pointer.
1835 The SH only has positive indexes, so grow the frame up. */
1836 /* #define FRAME_GROWS_DOWNWARD */
1838 /* Offset from the frame pointer to the first local variable slot to
1840 #define STARTING_FRAME_OFFSET 0
1842 /* If we generate an insn to push BYTES bytes,
1843 this says how many the stack pointer really advances by. */
1844 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1845 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1846 do correct alignment. */
1848 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1851 /* Offset of first parameter from the argument pointer register value. */
1852 #define FIRST_PARM_OFFSET(FNDECL) 0
1854 /* Value is the number of byte of arguments automatically
1855 popped when returning from a subroutine call.
1856 FUNDECL is the declaration node of the function (as a tree),
1857 FUNTYPE is the data type of the function (as a tree),
1858 or for a library call it is an identifier node for the subroutine name.
1859 SIZE is the number of bytes of arguments passed on the stack.
1861 On the SH, the caller does not pop any of its arguments that were passed
1863 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1865 /* Value is the number of bytes of arguments automatically popped when
1866 calling a subroutine.
1867 CUM is the accumulated argument list.
1869 On SHcompact, the call trampoline pops arguments off the stack. */
1870 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1872 /* Some subroutine macros specific to this machine. */
1874 #define BASE_RETURN_VALUE_REG(MODE) \
1875 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1876 ? FIRST_FP_RET_REG \
1877 : TARGET_FPU_ANY && (MODE) == SCmode \
1878 ? FIRST_FP_RET_REG \
1879 : (TARGET_FPU_DOUBLE \
1880 && ((MODE) == DFmode || (MODE) == SFmode \
1881 || (MODE) == DCmode || (MODE) == SCmode )) \
1882 ? FIRST_FP_RET_REG \
1885 #define BASE_ARG_REG(MODE) \
1886 ((TARGET_SH2E && ((MODE) == SFmode)) \
1887 ? FIRST_FP_PARM_REG \
1888 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1889 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1890 ? FIRST_FP_PARM_REG \
1893 /* Define how to find the value returned by a function.
1894 VALTYPE is the data type of the value (as a tree).
1895 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1896 otherwise, FUNC is 0.
1897 For the SH, this is like LIBCALL_VALUE, except that we must change the
1898 mode like PROMOTE_MODE does.
1899 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1900 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1902 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1904 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1905 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1906 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1907 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1908 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1909 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1910 || TREE_CODE (VALTYPE) == REAL_TYPE \
1911 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1912 && sh_promote_prototypes (VALTYPE) \
1913 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1914 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1916 /* Define how to find the value returned by a library function
1917 assuming the value has mode MODE. */
1918 #define LIBCALL_VALUE(MODE) \
1919 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1921 /* 1 if N is a possible register number for a function value. */
1922 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1923 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1924 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1926 /* 1 if N is a possible register number for function argument passing. */
1927 /* ??? There are some callers that pass REGNO as int, and others that pass
1928 it as unsigned. We get warnings unless we do casts everywhere. */
1929 #define FUNCTION_ARG_REGNO_P(REGNO) \
1930 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1931 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1932 || (TARGET_FPU_ANY \
1933 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1934 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1935 + NPARM_REGS (SFmode))))
1937 /* Define a data type for recording info about an argument list
1938 during the scan of that argument list. This data type should
1939 hold all necessary information about the function itself
1940 and about the args processed so far, enough to enable macros
1941 such as FUNCTION_ARG to determine where the next arg should go.
1943 On SH, this is a single integer, which is a number of words
1944 of arguments scanned so far (including the invisible argument,
1945 if any, which holds the structure-value-address).
1946 Thus NARGREGS or more means all following args should go on the stack. */
1948 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1952 /* Nonzero if a prototype is available for the function. */
1954 /* The number of an odd floating-point register, that should be used
1955 for the next argument of type float. */
1956 int free_single_fp_reg;
1957 /* Whether we're processing an outgoing function call. */
1959 /* The number of general-purpose registers that should have been
1960 used to pass partial arguments, that are passed totally on the
1961 stack. On SHcompact, a call trampoline will pop them off the
1962 stack before calling the actual function, and, if the called
1963 function is implemented in SHcompact mode, the incoming arguments
1964 decoder will push such arguments back onto the stack. For
1965 incoming arguments, STACK_REGS also takes into account other
1966 arguments passed by reference, that the decoder will also push
1969 /* The number of general-purpose registers that should have been
1970 used to pass arguments, if the arguments didn't have to be passed
1973 /* Set as by shcompact_byref if the current argument is to be passed
1977 /* call_cookie is a bitmask used by call expanders, as well as
1978 function prologue and epilogues, to allow SHcompact to comply
1979 with the SH5 32-bit ABI, that requires 64-bit registers to be
1980 used even though only the lower 32-bit half is visible in
1981 SHcompact mode. The strategy is to call SHmedia trampolines.
1983 The alternatives for each of the argument-passing registers are
1984 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1985 contents from the address in it; (d) add 8 to it, storing the
1986 result in the next register, then (c); (e) copy it from some
1987 floating-point register,
1989 Regarding copies from floating-point registers, r2 may only be
1990 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1991 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1992 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1993 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1996 The bit mask is structured as follows:
1998 - 1 bit to tell whether to set up a return trampoline.
2000 - 3 bits to count the number consecutive registers to pop off the
2003 - 4 bits for each of r9, r8, r7 and r6.
2005 - 3 bits for each of r5, r4, r3 and r2.
2007 - 3 bits set to 0 (the most significant ones)
2010 1098 7654 3210 9876 5432 1098 7654 3210
2011 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
2012 2223 3344 4555 6666 7777 8888 9999 SSS-
2014 - If F is set, the register must be copied from an FP register,
2015 whose number is encoded in the remaining bits.
2017 - Else, if L is set, the register must be loaded from the address
2018 contained in it. If the P bit is *not* set, the address of the
2019 following dword should be computed first, and stored in the
2022 - Else, if P is set, the register alone should be popped off the
2025 - After all this processing, the number of registers represented
2026 in SSS will be popped off the stack. This is an optimization
2027 for pushing/popping consecutive registers, typically used for
2028 varargs and large arguments partially passed in registers.
2030 - If T is set, a return trampoline will be set up for 64-bit
2031 return values to be split into 2 32-bit registers. */
2032 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
2033 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
2034 #define CALL_COOKIE_STACKSEQ_SHIFT 1
2035 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
2036 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
2037 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
2038 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
2039 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
2040 #define CALL_COOKIE_INT_REG(REG, VAL) \
2041 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
2042 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
2043 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
2046 /* This is set to nonzero when the call in question must use the Renesas ABI,
2047 even without the -mrenesas option. */
2051 #define CUMULATIVE_ARGS struct sh_args
2053 #define GET_SH_ARG_CLASS(MODE) \
2054 ((TARGET_FPU_ANY && (MODE) == SFmode) \
2056 /* There's no mention of complex float types in the SH5 ABI, so we
2057 should presumably handle them as aggregate types. */ \
2058 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
2060 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2061 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
2062 ? SH_ARG_FLOAT : SH_ARG_INT)
2064 #define ROUND_ADVANCE(SIZE) \
2065 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
2067 /* Round a register number up to a proper boundary for an arg of mode
2070 The SH doesn't care about double alignment, so we only
2071 round doubles to even regs when asked to explicitly. */
2073 #define ROUND_REG(CUM, MODE) \
2074 (((TARGET_ALIGN_DOUBLE \
2075 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
2076 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
2077 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
2078 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
2079 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
2080 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
2082 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2083 for a call to a function whose data type is FNTYPE.
2084 For a library call, FNTYPE is 0.
2086 On SH, the offset always starts at 0: the first parm reg is always
2087 the same reg for a given argument class.
2089 For TARGET_HITACHI, the structure value pointer is passed in memory. */
2091 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
2093 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
2094 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
2095 (CUM).renesas_abi = sh_attr_renesas_p (FNTYPE) ? 1 : 0; \
2097 = ((TARGET_HITACHI || (CUM).renesas_abi) && (FNTYPE) \
2098 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
2099 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
2100 (CUM).arg_count[(int) SH_ARG_INT] \
2101 = (TARGET_SH5 && (FNTYPE) \
2102 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
2103 (CUM).free_single_fp_reg = 0; \
2104 (CUM).outgoing = 1; \
2105 (CUM).stack_regs = 0; \
2106 (CUM).byref_regs = 0; \
2109 = (CALL_COOKIE_RET_TRAMP \
2110 (TARGET_SHCOMPACT && (FNTYPE) \
2111 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
2112 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
2113 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
2114 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
2115 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
2117 == FIRST_RET_REG))); \
2120 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
2122 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0, 0); \
2124 = (CALL_COOKIE_RET_TRAMP \
2125 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
2126 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
2129 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
2131 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0, 0); \
2132 (CUM).outgoing = 0; \
2135 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2136 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
2137 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2138 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
2140 /* Return boolean indicating arg of mode MODE will be passed in a reg.
2141 This macro is only used in this file. */
2143 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
2145 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
2146 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
2147 || ! (AGGREGATE_TYPE_P (TYPE) \
2148 || (!TARGET_FPU_ANY \
2149 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2150 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
2151 && ! (CUM).force_mem \
2153 ? ((MODE) == BLKmode \
2154 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2155 + int_size_in_bytes (TYPE)) \
2156 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2157 : ((ROUND_REG((CUM), (MODE)) \
2158 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2159 <= NPARM_REGS (MODE))) \
2160 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
2162 /* By accident we got stuck with passing SCmode on SH4 little endian
2163 in two registers that are nominally successive - which is different from
2164 two single SFmode values, where we take endianness translation into
2165 account. That does not work at all if an odd number of registers is
2166 already in use, so that got fixed, but library functions are still more
2167 likely to use complex numbers without mixing them with SFmode arguments
2168 (which in C would have to be structures), so for the sake of ABI
2169 compatibility the way SCmode values are passed when an even number of
2170 FP registers is in use remains different from a pair of SFmode values for
2173 foo (double); a: fr5,fr4
2174 foo (float a, float b); a: fr5 b: fr4
2175 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2176 this should be the other way round...
2177 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2178 #define FUNCTION_ARG_SCmode_WART 1
2180 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2181 register in SHcompact mode, it must be padded in the most
2182 significant end. This means that passing it by reference wouldn't
2183 pad properly on a big-endian machine. In this particular case, we
2184 pass this argument on the stack, in a way that the call trampoline
2185 will load its value into the appropriate register. */
2186 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2187 ((MODE) == BLKmode \
2188 && TARGET_SHCOMPACT \
2189 && ! TARGET_LITTLE_ENDIAN \
2190 && int_size_in_bytes (TYPE) > 4 \
2191 && int_size_in_bytes (TYPE) < 8)
2193 /* Minimum alignment for an argument to be passed by callee-copy
2194 reference. We need such arguments to be aligned to 8 byte
2195 boundaries, because they'll be loaded using quad loads. */
2196 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2198 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
2200 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
2201 : GET_MODE_ALIGNMENT (MODE)) \
2202 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
2204 /* The SH5 ABI requires floating-point arguments to be passed to
2205 functions without a prototype in both an FP register and a regular
2206 register or the stack. When passing the argument in both FP and
2207 general-purpose registers, list the FP register first. */
2208 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2214 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2215 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2216 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2221 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2222 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2223 + (CUM).arg_count[(int) SH_ARG_INT]) \
2224 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2225 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2228 /* The SH5 ABI requires regular registers or stack slots to be
2229 reserved for floating-point arguments. Registers are taken care of
2230 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2231 Unfortunately, there's no way to just reserve a stack slot, so
2232 we'll end up needlessly storing a copy of the argument in the
2233 stack. For incoming arguments, however, the PARALLEL will be
2234 optimized to the register-only form, and the value in the stack
2235 slot won't be used at all. */
2236 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2237 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2238 ? gen_rtx_REG ((MODE), (REG)) \
2239 : gen_rtx_PARALLEL ((MODE), \
2242 (VOIDmode, NULL_RTX, \
2245 (VOIDmode, gen_rtx_REG ((MODE), \
2249 /* For an arg passed partly in registers and partly in memory,
2250 this is the number of registers used.
2251 For args passed entirely in registers or entirely in memory, zero.
2253 We sometimes split args. */
2255 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2257 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2258 && ! (TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2259 && (ROUND_REG ((CUM), (MODE)) \
2260 + ((MODE) != BLKmode \
2261 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
2262 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
2263 > NPARM_REGS (MODE))) \
2264 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
2265 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
2266 && ! TARGET_SHCOMPACT) \
2267 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
2270 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2272 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2273 || (MODE) == DCmode) \
2274 && ((CUM).arg_count[(int) SH_ARG_INT] \
2275 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2277 /* Perform any needed actions needed for a function that is receiving a
2278 variable number of arguments. */
2280 /* Implement `va_start' for varargs and stdarg. */
2281 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2282 sh_va_start (valist, nextarg)
2284 /* Call the function profiler with a given profile label.
2285 We use two .aligns, so as to make sure that both the .long is aligned
2286 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2287 from the trapa instruction. */
2289 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2291 fprintf((STREAM), "\t.align\t2\n"); \
2292 fprintf((STREAM), "\ttrapa\t#33\n"); \
2293 fprintf((STREAM), "\t.align\t2\n"); \
2294 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2297 /* Define this macro if the code for function profiling should come
2298 before the function prologue. Normally, the profiling code comes
2301 #define PROFILE_BEFORE_PROLOGUE
2303 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2304 the stack pointer does not matter. The value is tested only in
2305 functions that have frame pointers.
2306 No definition is equivalent to always zero. */
2308 #define EXIT_IGNORE_STACK 1
2311 On the SH, the trampoline looks like
2312 2 0002 D202 mov.l l2,r2
2313 1 0000 D301 mov.l l1,r3
2316 5 0008 00000000 l1: .long area
2317 6 000c 00000000 l2: .long function */
2319 /* Length in units of the trampoline for entering a nested function. */
2320 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2322 /* Alignment required for a trampoline in bits . */
2323 #define TRAMPOLINE_ALIGNMENT \
2324 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2325 : TARGET_SHMEDIA ? 256 : 64)
2327 /* Emit RTL insns to initialize the variable parts of a trampoline.
2328 FNADDR is an RTX for the address of the function's pure code.
2329 CXT is an RTX for the static chain value for the function. */
2331 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2332 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2334 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2336 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2338 if (TARGET_SHMEDIA) \
2339 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2340 gen_reg_rtx (Pmode), 0, \
2344 /* A C expression whose value is RTL representing the value of the return
2345 address for the frame COUNT steps up from the current frame.
2346 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2347 can ignore COUNT. */
2349 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2350 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2352 /* A C expression whose value is RTL representing the location of the
2353 incoming return address at the beginning of any function, before the
2354 prologue. This RTL is either a REG, indicating that the return
2355 value is saved in REG, or a MEM representing a location in
2357 #define INCOMING_RETURN_ADDR_RTX \
2358 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2360 /* Addressing modes, and classification of registers for them. */
2361 #define HAVE_POST_INCREMENT TARGET_SH1
2362 #define HAVE_PRE_DECREMENT TARGET_SH1
2364 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2366 #define USE_LOAD_PRE_DECREMENT(mode) 0
2367 #define USE_STORE_POST_INCREMENT(mode) 0
2368 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2371 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2372 < (TARGET_SMALLCODE ? 2 : \
2373 ((ALIGN >= 32) ? 16 : 2)))
2375 /* Macros to check register numbers against specific register classes. */
2377 /* These assume that REGNO is a hard or pseudo reg number.
2378 They give nonzero only if REGNO is a hard reg of the suitable class
2379 or a pseudo reg currently allocated to a suitable hard reg.
2380 Since they use reg_renumber, they are safe only once reg_renumber
2381 has been allocated, which happens in local-alloc.c. */
2383 #define REGNO_OK_FOR_BASE_P(REGNO) \
2384 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2385 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2386 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2388 ? (GENERAL_REGISTER_P (REGNO) \
2389 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2390 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2392 /* Maximum number of registers that can appear in a valid memory
2395 #define MAX_REGS_PER_ADDRESS 2
2397 /* Recognize any constant value that is a valid address. */
2399 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2401 /* Nonzero if the constant value X is a legitimate general operand. */
2403 #define LEGITIMATE_CONSTANT_P(X) \
2405 ? ((GET_MODE (X) != DFmode \
2406 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2407 || (X) == CONST0_RTX (GET_MODE (X)) \
2408 || ! TARGET_SHMEDIA_FPU \
2409 || TARGET_SHMEDIA64) \
2410 : (GET_CODE (X) != CONST_DOUBLE \
2411 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2412 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2414 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2415 and check its validity for a certain class.
2416 We have two alternate definitions for each of them.
2417 The usual definition accepts all pseudo regs; the other rejects
2418 them unless they have been allocated suitable hard regs.
2419 The symbol REG_OK_STRICT causes the latter definition to be used. */
2421 #ifndef REG_OK_STRICT
2423 /* Nonzero if X is a hard reg that can be used as a base reg
2424 or if it is a pseudo reg. */
2425 #define REG_OK_FOR_BASE_P(X) \
2426 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2428 /* Nonzero if X is a hard reg that can be used as an index
2429 or if it is a pseudo reg. */
2430 #define REG_OK_FOR_INDEX_P(X) \
2431 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2432 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2434 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2435 or if X is a pseudo reg. */
2436 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2437 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2438 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2442 /* Nonzero if X is a hard reg that can be used as a base reg. */
2443 #define REG_OK_FOR_BASE_P(X) \
2444 REGNO_OK_FOR_BASE_P (REGNO (X))
2446 /* Nonzero if X is a hard reg that can be used as an index. */
2447 #define REG_OK_FOR_INDEX_P(X) \
2448 REGNO_OK_FOR_INDEX_P (REGNO (X))
2450 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2451 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2452 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2456 /* The 'Q' constraint is a pc relative load operand. */
2457 #define EXTRA_CONSTRAINT_Q(OP) \
2458 (GET_CODE (OP) == MEM \
2459 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2460 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2461 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2462 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2463 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2465 /* Extra address constraints. */
2466 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2468 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2469 operand is not SCRATCH (i.e. REG) then R0 is probably being
2470 used, hence mova is being used, hence do not select this pattern */
2471 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2472 #define EXTRA_CONSTRAINT_B(OP, STR) \
2473 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2476 /* The `C16' constraint is a 16-bit constant, literal or symbolic. */
2477 #define EXTRA_CONSTRAINT_C16(OP) \
2478 (GET_CODE (OP) == CONST \
2479 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2480 && GET_MODE (XEXP ((OP), 0)) == DImode \
2481 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2482 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2483 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2484 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2485 && (MOVI_SHORI_BASE_OPERAND_P \
2486 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2487 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2490 /* Check whether OP is a datalabel unspec. */
2491 #define DATALABEL_REF_NO_CONST_P(OP) \
2492 (GET_CODE (OP) == UNSPEC \
2493 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2494 && XVECLEN ((OP), 0) == 1 \
2495 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2496 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2498 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2500 #define DATALABEL_REF_P(OP) \
2501 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2502 || DATALABEL_REF_NO_CONST_P (OP))
2504 #define GOT_ENTRY_P(OP) \
2505 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2506 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2508 #define GOTPLT_ENTRY_P(OP) \
2509 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2510 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2512 #define UNSPEC_GOTOFF_P(OP) \
2513 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2515 #define GOTOFF_P(OP) \
2516 (GET_CODE (OP) == CONST \
2517 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2518 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2519 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2520 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2522 #define PIC_ADDR_P(OP) \
2523 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2524 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2526 #define PIC_OFFSET_P(OP) \
2528 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2529 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2531 #define PIC_DIRECT_ADDR_P(OP) \
2532 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2534 #define NON_PIC_REFERENCE_P(OP) \
2535 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2536 || DATALABEL_REF_P (OP) \
2537 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2538 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2539 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2540 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2542 #define PIC_REFERENCE_P(OP) \
2543 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2544 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2546 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2548 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2549 || PIC_OFFSET_P (OP)) \
2550 : NON_PIC_REFERENCE_P (OP))
2552 /* The `Csy' constraint is a label or a symbol. */
2553 #define EXTRA_CONSTRAINT_Csy(OP) \
2554 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2556 /* A zero in any shape or form. */
2557 #define EXTRA_CONSTRAINT_Z(OP) \
2558 ((OP) == CONST0_RTX (GET_MODE (OP)))
2560 /* Any vector constant we can handle. */
2561 #define EXTRA_CONSTRAINT_W(OP) \
2562 (GET_CODE (OP) == CONST_VECTOR \
2563 && (sh_rep_vec ((OP), VOIDmode) \
2564 || (HOST_BITS_PER_WIDE_INT >= 64 \
2565 ? sh_const_vec ((OP), VOIDmode) \
2566 : sh_1el_vec ((OP), VOIDmode))))
2568 /* A non-explicit constant that can be loaded directly into a general purpose
2569 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2570 #define EXTRA_CONSTRAINT_Cpg(OP) \
2572 && GET_CODE (OP) != CONST_INT \
2573 && GET_CODE (OP) != CONST_DOUBLE \
2575 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2576 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2577 && GET_CODE (OP) != LABEL_REF)))
2578 #define EXTRA_CONSTRAINT_C(OP, STR) \
2579 ((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
2580 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2581 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2584 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2585 #define EXTRA_CONSTRAINT_Sr0(OP) \
2586 (memory_operand((OP), GET_MODE (OP)) \
2587 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2588 #define EXTRA_CONSTRAINT_Sua(OP) \
2589 (memory_operand((OP), GET_MODE (OP)) \
2590 && GET_CODE (XEXP (OP, 0)) != PLUS)
2591 #define EXTRA_CONSTRAINT_S(OP, STR) \
2592 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2593 : (STR)[1] == 'u' && (STR)[2] == 'a' ? EXTRA_CONSTRAINT_Sua (OP) \
2596 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2597 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2598 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2599 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2600 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2601 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2602 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2603 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2606 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2607 that is a valid memory address for an instruction.
2608 The MODE argument is the machine mode for the MEM expression
2609 that wants to use this address. */
2611 #define MODE_DISP_OK_4(X,MODE) \
2612 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2613 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2615 #define MODE_DISP_OK_8(X,MODE) \
2616 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2617 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2619 #undef MODE_DISP_OK_4
2620 #define MODE_DISP_OK_4(X,MODE) \
2621 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2622 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2623 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2624 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2626 #undef MODE_DISP_OK_8
2627 #define MODE_DISP_OK_8(X,MODE) \
2628 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2629 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2630 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2631 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2633 #define BASE_REGISTER_RTX_P(X) \
2634 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2635 || (GET_CODE (X) == SUBREG \
2636 && GET_CODE (SUBREG_REG (X)) == REG \
2637 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2639 /* Since this must be r0, which is a single register class, we must check
2640 SUBREGs more carefully, to be sure that we don't accept one that extends
2641 outside the class. */
2642 #define INDEX_REGISTER_RTX_P(X) \
2643 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2644 || (GET_CODE (X) == SUBREG \
2645 && GET_CODE (SUBREG_REG (X)) == REG \
2646 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2648 /* Jump to LABEL if X is a valid address RTX. This must also take
2649 REG_OK_STRICT into account when deciding about valid registers, but it uses
2650 the above macros so we are in luck.
2658 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2659 into the FRx registers. We implement this by setting the maximum offset
2660 to zero when the value is SFmode. This also restricts loading of SFmode
2661 values into the integer registers, but that can't be helped. */
2663 /* The SH allows a displacement in a QI or HI amode, but only when the
2664 other operand is R0. GCC doesn't handle this very well, so we forgo
2667 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2668 DI can be any number 0..60. */
2670 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2672 if (GET_CODE (OP) == CONST_INT) \
2674 if (TARGET_SHMEDIA) \
2676 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2677 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2678 && INTVAL (OP) >= -512 * MODE_SIZE \
2679 && INTVAL (OP) < 512 * MODE_SIZE) \
2684 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2685 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2689 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2691 if (BASE_REGISTER_RTX_P (X)) \
2693 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2694 && ! TARGET_SHMEDIA \
2695 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2697 else if (GET_CODE (X) == PLUS \
2698 && ((MODE) != PSImode || reload_completed)) \
2700 rtx xop0 = XEXP ((X), 0); \
2701 rtx xop1 = XEXP ((X), 1); \
2702 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2703 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2704 if (GET_MODE_SIZE (MODE) <= 4 \
2705 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2706 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && MODE == DFmode)) \
2708 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2710 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2716 /* Try machine-dependent ways of modifying an illegitimate address
2717 to be legitimate. If we find one, return the new, valid address.
2718 This macro is used in only one place: `memory_address' in explow.c.
2720 OLDX is the address as it was before break_out_memory_refs was called.
2721 In some cases it is useful to look at this to decide what needs to be done.
2723 MODE and WIN are passed so that this macro can use
2724 GO_IF_LEGITIMATE_ADDRESS.
2726 It is always safe for this macro to do nothing. It exists to recognize
2727 opportunities to optimize the output.
2729 For the SH, if X is almost suitable for indexing, but the offset is
2730 out of range, convert it into a normal form so that cse has a chance
2731 of reducing the number of address registers used. */
2733 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2736 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2737 if (GET_CODE (X) == PLUS \
2738 && (GET_MODE_SIZE (MODE) == 4 \
2739 || GET_MODE_SIZE (MODE) == 8) \
2740 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2741 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2742 && ! TARGET_SHMEDIA \
2743 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2744 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2746 rtx index_rtx = XEXP ((X), 1); \
2747 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2750 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2751 /* On rare occasions, we might get an unaligned pointer \
2752 that is indexed in a way to give an aligned address. \
2753 Therefore, keep the lower two bits in offset_base. */ \
2754 /* Instead of offset_base 128..131 use 124..127, so that \
2755 simple add suffices. */ \
2758 offset_base = ((offset + 4) & ~60) - 4; \
2761 offset_base = offset & ~60; \
2762 /* Sometimes the normal form does not suit DImode. We \
2763 could avoid that by using smaller ranges, but that \
2764 would give less optimized code when SImode is \
2766 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2768 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2769 GEN_INT (offset_base), NULL_RTX, 0, \
2772 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2778 /* A C compound statement that attempts to replace X, which is an address
2779 that needs reloading, with a valid memory address for an operand of
2780 mode MODE. WIN is a C statement label elsewhere in the code.
2782 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2783 of the address. That will allow inheritance of the address reloads. */
2785 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2787 if (GET_CODE (X) == PLUS \
2788 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2789 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2790 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2791 && ! TARGET_SHMEDIA \
2792 && ! (TARGET_SH4 && (MODE) == DFmode) \
2793 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2795 rtx index_rtx = XEXP (X, 1); \
2796 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2799 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2801 push_reload (X, NULL_RTX, &X, NULL, \
2802 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2806 if (TARGET_SH2E && MODE == SFmode) \
2809 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2810 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2814 /* Instead of offset_base 128..131 use 124..127, so that \
2815 simple add suffices. */ \
2818 offset_base = ((offset + 4) & ~60) - 4; \
2821 offset_base = offset & ~60; \
2822 /* Sometimes the normal form does not suit DImode. We \
2823 could avoid that by using smaller ranges, but that \
2824 would give less optimized code when SImode is \
2826 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2828 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2829 GEN_INT (offset_base)); \
2830 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2831 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2832 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2837 /* We must re-recognize what we created before. */ \
2838 else if (GET_CODE (X) == PLUS \
2839 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2840 && GET_CODE (XEXP (X, 0)) == PLUS \
2841 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2842 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2843 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2844 && ! TARGET_SHMEDIA \
2845 && ! (TARGET_SH2E && MODE == SFmode)) \
2847 /* Because this address is so complex, we know it must have \
2848 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2849 it is already unshared, and needs no further unsharing. */ \
2850 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2851 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2856 /* Go to LABEL if ADDR (a legitimate address expression)
2857 has an effect that depends on the machine mode it is used for.
2859 ??? Strictly speaking, we should also include all indexed addressing,
2860 because the index scale factor is the length of the operand.
2861 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2862 high if we did that. So we rely on reload to fix things up. */
2864 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2866 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2870 /* Specify the machine mode that this machine uses
2871 for the index in the tablejump instruction. */
2872 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2874 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2875 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2876 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2877 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2878 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2879 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2882 /* Define as C expression which evaluates to nonzero if the tablejump
2883 instruction expects the table to contain offsets from the address of the
2885 Do not define this if the table should contain absolute addresses. */
2886 #define CASE_VECTOR_PC_RELATIVE 1
2888 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2889 #define FLOAT_TYPE_SIZE 32
2891 /* Since the SH2e has only `float' support, it is desirable to make all
2892 floating point types equivalent to `float'. */
2893 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2895 /* 'char' is signed by default. */
2896 #define DEFAULT_SIGNED_CHAR 1
2898 /* The type of size_t unsigned int. */
2899 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2902 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2904 #define WCHAR_TYPE "short unsigned int"
2905 #define WCHAR_TYPE_SIZE 16
2907 #define SH_ELF_WCHAR_TYPE "long int"
2909 /* Max number of bytes we can move from memory to memory
2910 in one reasonably fast instruction. */
2911 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2913 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2914 MOVE_MAX is not a compile-time constant. */
2915 #define MAX_MOVE_MAX 8
2917 /* Max number of bytes we want move_by_pieces to be able to copy
2919 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2921 /* Define if operations between registers always perform the operation
2922 on the full register even if a narrower mode is specified. */
2923 #define WORD_REGISTER_OPERATIONS
2925 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2926 will either zero-extend or sign-extend. The value of this macro should
2927 be the code that says which one of the two operations is implicitly
2928 done, NIL if none. */
2929 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2930 /* FP registers can load SImode values, but don't implicitly sign-extend
2932 #define LOAD_EXTEND_OP(MODE) \
2933 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2934 : (MODE) != SImode ? SIGN_EXTEND : NIL)
2936 /* Define if loading short immediate values into registers sign extends. */
2937 #define SHORT_IMMEDIATES_SIGN_EXTEND
2939 /* Nonzero if access to memory by bytes is no faster than for words. */
2940 #define SLOW_BYTE_ACCESS 1
2942 /* Immediate shift counts are truncated by the output routines (or was it
2943 the assembler?). Shift counts in a register are truncated by SH. Note
2944 that the native compiler puts too large (> 32) immediate shift counts
2945 into a register and shifts by the register, letting the SH decide what
2946 to do instead of doing that itself. */
2947 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2948 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2949 expects - the sign bit is significant - so it appears that we need to
2950 leave this zero for correct SH3 code. */
2951 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2953 /* All integers have the same format so truncation is easy. */
2954 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2956 /* Define this if addresses of constant functions
2957 shouldn't be put through pseudo regs where they can be cse'd.
2958 Desirable on machines where ordinary constants are expensive
2959 but a CALL with constant address is cheap. */
2960 /*#define NO_FUNCTION_CSE 1*/
2962 /* The machine modes of pointers and functions. */
2963 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2964 #define FUNCTION_MODE Pmode
2966 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2967 are actually function calls with some special constraints on arguments
2970 These macros tell reorg that the references to arguments and
2971 register clobbers for insns of type sfunc do not appear to happen
2972 until after the millicode call. This allows reorg to put insns
2973 which set the argument registers into the delay slot of the millicode
2974 call -- thus they act more like traditional CALL_INSNs.
2976 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2977 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2980 #define INSN_SETS_ARE_DELAYED(X) \
2981 ((GET_CODE (X) == INSN \
2982 && GET_CODE (PATTERN (X)) != SEQUENCE \
2983 && GET_CODE (PATTERN (X)) != USE \
2984 && GET_CODE (PATTERN (X)) != CLOBBER \
2985 && get_attr_is_sfunc (X)))
2987 #define INSN_REFERENCES_ARE_DELAYED(X) \
2988 ((GET_CODE (X) == INSN \
2989 && GET_CODE (PATTERN (X)) != SEQUENCE \
2990 && GET_CODE (PATTERN (X)) != USE \
2991 && GET_CODE (PATTERN (X)) != CLOBBER \
2992 && get_attr_is_sfunc (X)))
2995 /* Position Independent Code. */
2997 /* We can't directly access anything that contains a symbol,
2998 nor can we indirect via the constant pool. */
2999 #define LEGITIMATE_PIC_OPERAND_P(X) \
3000 ((! nonpic_symbol_mentioned_p (X) \
3001 && (GET_CODE (X) != SYMBOL_REF \
3002 || ! CONSTANT_POOL_ADDRESS_P (X) \
3003 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
3004 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
3006 #define SYMBOLIC_CONST_P(X) \
3007 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
3008 && nonpic_symbol_mentioned_p (X))
3010 /* Compute extra cost of moving data between one register class
3013 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
3014 uses this information. Hence, the general register <-> floating point
3015 register information here is not used for SFmode. */
3017 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
3018 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
3019 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
3021 #define REGCLASS_HAS_FP_REG(CLASS) \
3022 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
3023 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
3025 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
3026 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
3028 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
3029 would be so that people with slow memory systems could generate
3030 different code that does fewer memory accesses. */
3032 /* A C expression for the cost of a branch instruction. A value of 1
3033 is the default; other values are interpreted relative to that.
3034 The SH1 does not have delay slots, hence we get a pipeline stall
3035 at every branch. The SH4 is superscalar, so the single delay slot
3036 is not sufficient to keep both pipelines filled. */
3037 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
3039 /* Assembler output control. */
3041 /* A C string constant describing how to begin a comment in the target
3042 assembler language. The compiler assumes that the comment will end at
3043 the end of the line. */
3044 #define ASM_COMMENT_START "!"
3046 #define ASM_APP_ON ""
3047 #define ASM_APP_OFF ""
3048 #define FILE_ASM_OP "\t.file\n"
3049 #define SET_ASM_OP "\t.set\t"
3051 /* How to change between sections. */
3053 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
3054 #define DATA_SECTION_ASM_OP "\t.data"
3056 #if defined CRT_BEGIN || defined CRT_END
3057 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
3058 # undef TEXT_SECTION_ASM_OP
3059 # if __SHMEDIA__ == 1 && __SH5__ == 32
3060 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
3062 # define TEXT_SECTION_ASM_OP "\t.text"
3067 /* If defined, a C expression whose value is a string containing the
3068 assembler operation to identify the following data as
3069 uninitialized global data. If not defined, and neither
3070 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
3071 uninitialized global data will be output in the data section if
3072 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
3074 #ifndef BSS_SECTION_ASM_OP
3075 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
3078 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
3079 separate, explicit argument. If you define this macro, it is used
3080 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
3081 handling the required alignment of the variable. The alignment is
3082 specified as the number of bits.
3084 Try to use function `asm_output_aligned_bss' defined in file
3085 `varasm.c' when defining this macro. */
3086 #ifndef ASM_OUTPUT_ALIGNED_BSS
3087 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
3088 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
3091 /* Define this so that jump tables go in same section as the current function,
3092 which could be text or it could be a user defined section. */
3093 #define JUMP_TABLES_IN_TEXT_SECTION 1
3095 #undef DO_GLOBAL_CTORS_BODY
3096 #define DO_GLOBAL_CTORS_BODY \
3098 typedef (*pfunc)(); \
3099 extern pfunc __ctors[]; \
3100 extern pfunc __ctors_end[]; \
3102 for (p = __ctors_end; p > __ctors; ) \
3108 #undef DO_GLOBAL_DTORS_BODY
3109 #define DO_GLOBAL_DTORS_BODY \
3111 typedef (*pfunc)(); \
3112 extern pfunc __dtors[]; \
3113 extern pfunc __dtors_end[]; \
3115 for (p = __dtors; p < __dtors_end; p++) \
3121 #define ASM_OUTPUT_REG_PUSH(file, v) \
3122 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));
3124 #define ASM_OUTPUT_REG_POP(file, v) \
3125 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
3127 /* DBX register number for a given compiler register number. */
3128 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
3130 /* svr4.h undefines this macro, yet we really want to use the same numbers
3131 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
3132 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
3133 register exists, so we should return -1 for invalid register numbers. */
3134 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
3136 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
3137 used to use the encodings 245..260, but that doesn't make sense:
3138 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
3139 the FP registers stay the same when switching between compact and media
3140 mode. Hence, we also need to use the same dwarf frame columns.
3141 Likewise, we need to support unwind information for SHmedia registers
3142 even in compact code. */
3143 #define SH_DBX_REGISTER_NUMBER(REGNO) \
3144 (IN_RANGE ((REGNO), \
3145 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
3146 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
3147 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
3148 : ((int) (REGNO) >= FIRST_FP_REG \
3150 <= (FIRST_FP_REG + \
3151 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
3152 ? ((unsigned) (REGNO) - FIRST_FP_REG \
3153 + (TARGET_SH5 ? 77 : 25)) \
3154 : XD_REGISTER_P (REGNO) \
3155 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
3156 : TARGET_REGISTER_P (REGNO) \
3157 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
3158 : (REGNO) == PR_REG \
3159 ? (TARGET_SH5 ? 18 : 17) \
3160 : (REGNO) == PR_MEDIA_REG \
3161 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
3162 : (REGNO) == T_REG \
3163 ? (TARGET_SH5 ? 242 : 18) \
3164 : (REGNO) == GBR_REG \
3165 ? (TARGET_SH5 ? 238 : 19) \
3166 : (REGNO) == MACH_REG \
3167 ? (TARGET_SH5 ? 239 : 20) \
3168 : (REGNO) == MACL_REG \
3169 ? (TARGET_SH5 ? 240 : 21) \
3170 : (REGNO) == FPUL_REG \
3171 ? (TARGET_SH5 ? 244 : 23) \
3174 /* This is how to output a reference to a symbol_ref. On SH5,
3175 references to non-code symbols must be preceded by `datalabel'. */
3176 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3179 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3180 fputs ("datalabel ", (FILE)); \
3181 assemble_name ((FILE), XSTR ((SYM), 0)); \
3185 /* This is how to output an assembler line
3186 that says to advance the location counter
3187 to a multiple of 2**LOG bytes. */
3189 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3191 fprintf ((FILE), "\t.align %d\n", (LOG))
3193 /* Globalizing directive for a label. */
3194 #define GLOBAL_ASM_OP "\t.global\t"
3196 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3198 /* Output a relative address table. */
3200 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3201 switch (GET_MODE (BODY)) \
3206 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3210 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3215 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3219 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3224 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3228 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3234 /* Output an absolute table element. */
3236 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3237 if (! optimize || TARGET_BIGTABLE) \
3238 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3240 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3243 /* A C statement to be executed just prior to the output of
3244 assembler code for INSN, to modify the extracted operands so
3245 they will be output differently.
3247 Here the argument OPVEC is the vector containing the operands
3248 extracted from INSN, and NOPERANDS is the number of elements of
3249 the vector which contain meaningful data for this insn.
3250 The contents of this vector are what will be used to convert the insn
3251 template into assembler code, so you can change the assembler output
3252 by changing the contents of the vector. */
3254 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3255 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3257 /* Print operand X (an rtx) in assembler syntax to file FILE.
3258 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3259 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3261 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3263 /* Print a memory address as an operand to reference that memory location. */
3265 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3267 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3268 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3269 || (CHAR) == '$'|| (CHAR) == '\'')
3271 /* Recognize machine-specific patterns that may appear within
3272 constants. Used for PIC-specific UNSPECs. */
3273 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3275 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3277 switch (XINT ((X), 1)) \
3279 case UNSPEC_DATALABEL: \
3280 fputs ("datalabel ", (STREAM)); \
3281 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3284 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3285 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3288 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3289 fputs ("@GOT", (STREAM)); \
3291 case UNSPEC_GOTOFF: \
3292 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3293 fputs ("@GOTOFF", (STREAM)); \
3296 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3297 fputs ("@PLT", (STREAM)); \
3299 case UNSPEC_GOTPLT: \
3300 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3301 fputs ("@GOTPLT", (STREAM)); \
3303 case UNSPEC_DTPOFF: \
3304 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3305 fputs ("@DTPOFF", (STREAM)); \
3307 case UNSPEC_GOTTPOFF: \
3308 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3309 fputs ("@GOTTPOFF", (STREAM)); \
3311 case UNSPEC_TPOFF: \
3312 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3313 fputs ("@TPOFF", (STREAM)); \
3315 case UNSPEC_CALLER: \
3318 /* LPCS stands for Label for PIC Call Site. */ \
3319 ASM_GENERATE_INTERNAL_LABEL \
3320 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3321 assemble_name ((STREAM), name); \
3334 extern struct rtx_def *sh_compare_op0;
3335 extern struct rtx_def *sh_compare_op1;
3337 /* Which processor to schedule for. The elements of the enumeration must
3338 match exactly the cpu attribute in the sh.md file. */
3340 enum processor_type {
3352 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3353 extern enum processor_type sh_cpu;
3355 extern int optimize; /* needed for gen_casesi. */
3357 enum mdep_reorg_phase_e
3359 SH_BEFORE_MDEP_REORG,
3360 SH_INSERT_USES_LABELS,
3361 SH_SHORTEN_BRANCHES0,
3363 SH_SHORTEN_BRANCHES1,
3367 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3369 /* Handle Renesas compiler's pragmas. */
3370 #define REGISTER_TARGET_PRAGMAS() do { \
3371 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3372 c_register_pragma (0, "trapa", sh_pr_trapa); \
3373 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3376 /* Set when processing a function with pragma interrupt turned on. */
3378 extern int pragma_interrupt;
3380 /* Set when processing a function with interrupt attribute. */
3382 extern int current_function_interrupt;
3384 /* Set to an RTX containing the address of the stack to switch to
3385 for interrupt functions. */
3386 extern struct rtx_def *sp_switch;
3388 extern int rtx_equal_function_value_matters;
3391 /* Instructions with unfilled delay slots take up an
3392 extra two bytes for the nop in the delay slot.
3393 sh-dsp parallel processing insns are four bytes long. */
3395 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3396 (LENGTH) += sh_insn_length_adjustment (X);
3398 /* Define the codes that are matched by predicates in sh.c. */
3399 #define PREDICATE_CODES \
3400 {"and_operand", {SUBREG, REG, CONST_INT}}, \
3401 {"any_register_operand", {SUBREG, REG}}, \
3402 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3403 {"arith_reg_dest", {SUBREG, REG}}, \
3404 {"arith_reg_operand", {SUBREG, REG}}, \
3405 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
3406 {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
3407 {"binary_logical_operator", {AND, IOR, XOR}}, \
3408 {"cmpsi_operand", {SUBREG, REG, CONST_INT}}, \
3409 {"commutative_float_operator", {PLUS, MULT}}, \
3410 {"equality_comparison_operator", {EQ,NE}}, \
3411 {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
3412 {"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \
3413 {"fp_arith_reg_operand", {SUBREG, REG}}, \
3414 {"fpscr_operand", {REG}}, \
3415 {"fpul_operand", {REG}}, \
3416 {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \
3417 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
3418 {"general_movdst_operand", {SUBREG, REG, MEM}}, \
3419 {"unaligned_load_operand", {MEM}}, \
3420 {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
3421 {"int_gpr_dest", {SUBREG, REG}}, \
3422 {"inqhi_operand", {TRUNCATE}}, \
3423 {"less_comparison_operator", {LT,LE,LTU,LEU}}, \
3424 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
3425 {"mextr_bit_offset", {CONST_INT}}, \
3426 {"noncommutative_float_operator", {MINUS, DIV}}, \
3427 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
3428 {"sh_register_operand", {REG, SUBREG, CONST_INT}}, \
3429 {"target_reg_operand", {SUBREG, REG}}, \
3430 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
3431 {"trunc_hi_operand", {SUBREG, REG, TRUNCATE}}, \
3432 {"register_operand", {SUBREG, REG}}, \
3433 {"sh_const_vec", {CONST_VECTOR}}, \
3434 {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
3435 {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
3436 {"symbol_ref_operand", {SYMBOL_REF}}, \
3437 {"unary_float_operator", {ABS, NEG, SQRT}}, \
3439 #define SPECIAL_MODE_PREDICATES \
3440 "any_register_operand", \
3442 "trunc_hi_operand", \
3443 /* This line intentionally left blank. */
3445 #define any_register_operand register_operand
3447 /* Define this macro if it is advisable to hold scalars in registers
3448 in a wider mode than that declared by the program. In such cases,
3449 the value is constrained to be within the bounds of the declared
3450 type, but kept valid in the wider mode. The signedness of the
3451 extension may differ from that of the type.
3453 Leaving the unsignedp unchanged gives better code than always setting it
3454 to 0. This is despite the fact that we have only signed char and short
3455 load instructions. */
3456 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3457 if (GET_MODE_CLASS (MODE) == MODE_INT \
3458 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3459 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3460 (MODE) = (TARGET_SH1 ? SImode : DImode);
3462 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3464 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3465 and popping arguments. However, we do have push/pop instructions, and
3466 rather limited offsets (4 bits) in load/store instructions, so it isn't
3467 clear if this would give better code. If implemented, should check for
3468 compatibility problems. */
3470 #define SH_DYNAMIC_SHIFT_COST \
3471 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3474 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3476 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3478 #define ACTUAL_NORMAL_MODE(ENTITY) \
3479 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3481 #define NORMAL_MODE(ENTITY) \
3482 (sh_cfun_interrupt_handler_p () \
3483 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3484 : ACTUAL_NORMAL_MODE (ENTITY))
3486 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3488 #define MODE_EXIT(ENTITY) \
3489 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3491 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3492 && (REGNO) == FPSCR_REG)
3494 #define MODE_NEEDED(ENTITY, INSN) \
3495 (recog_memoized (INSN) >= 0 \
3496 ? get_attr_fp_mode (INSN) \
3499 #define MODE_AFTER(MODE, INSN) \
3501 && recog_memoized (INSN) >= 0 \
3502 && get_attr_fp_set (INSN) != FP_SET_NONE \
3503 ? (int) get_attr_fp_set (INSN) \
3506 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3507 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3509 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3510 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3512 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3513 sh_can_redirect_branch ((INSN), (SEQ))
3515 #define DWARF_FRAME_RETURN_COLUMN \
3516 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3518 #define EH_RETURN_DATA_REGNO(N) \
3519 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3521 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3522 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3524 /* We have to distinguish between code and data, so that we apply
3525 datalabel where and only where appropriate. Use textrel for code. */
3526 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3527 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3528 | ((CODE) ? DW_EH_PE_textrel : flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))
3530 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3531 indirect are handled automatically. */
3532 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3534 if (((ENCODING) & 0x70) == DW_EH_PE_textrel) \
3536 encoding &= ~DW_EH_PE_textrel; \
3537 encoding |= flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr; \
3538 if (GET_CODE (ADDR) != SYMBOL_REF) \
3540 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3545 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3546 /* SH constant pool breaks the devices in crtstuff.c to control section
3547 in where code resides. We have to write it as asm code. */
3548 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3549 asm (SECTION_OP "\n\
3555 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3556 2:\n" TEXT_SECTION_ASM_OP);
3557 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3559 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3560 (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
3561 ? (current_function_is_leaf \
3562 && ! sh_pr_n_sets () \
3563 && ! (TARGET_SHCOMPACT \
3564 && ((current_function_args_info.call_cookie \
3565 & ~ CALL_COOKIE_RET_TRAMP (1)) \
3566 || current_function_has_nonlocal_label)) \
3568 : gen_rtx_MEM (Pmode, return_address_pointer_rtx)) \
3571 #endif /* ! GCC_SH_H */
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