1 /* Definitions of target machine for GNU compiler for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #define TARGET_VERSION \
25 fputs (" (Hitachi SH)", stderr);
27 /* Generate SDB debugging information. */
29 #define SDB_DEBUGGING_INFO
31 /* Output DBX (stabs) debugging information if doing -gstabs. */
33 #define DBX_DEBUGGING_INFO
35 /* Generate SDB debugging information by default. */
37 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
41 #define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__}"
43 #define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
45 #define ASM_SPEC "%{ml:-little}"
47 #define LINK_SPEC "%{ml:-m shl}"
49 /* Show we can debug even without a frame pointer. */
50 #define CAN_DEBUG_WITHOUT_FP
52 #define CONDITIONAL_REGISTER_USAGE \
53 /* Hitachi saves and restores mac registers on call. */ \
56 call_used_regs[MACH_REG] = 0; \
57 call_used_regs[MACL_REG] = 0; \
60 /* ??? Need to write documentation for all SH options and add it to the
63 /* Run-time compilation parameters selecting different hardware subsets. */
65 extern int target_flags;
66 #define ISIZE_BIT (1<<1)
67 #define DALIGN_BIT (1<<6)
68 #define SH0_BIT (1<<7)
69 #define SH1_BIT (1<<8)
70 #define SH2_BIT (1<<9)
71 #define SH3_BIT (1<<10)
72 #define SPACE_BIT (1<<13)
73 #define BIGTABLE_BIT (1<<14)
74 #define HITACHI_BIT (1<<22)
75 #define PADSTRUCT_BIT (1<<28)
76 #define LITTLE_ENDIAN_BIT (1<<29)
78 /* Nonzero if we should dump out instruction size info. */
79 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
81 /* Nonzero to align doubles on 64 bit boundaries. */
82 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
84 /* Nonzero if we should generate code using type 0 insns. */
85 /* ??? Is there such a thing as SH0? If not, we should delete all
87 #define TARGET_SH0 (target_flags & SH0_BIT)
89 /* Nonzero if we should generate code using type 1 insns. */
90 #define TARGET_SH1 (target_flags & SH1_BIT)
92 /* Nonzero if we should generate code using type 2 insns. */
93 #define TARGET_SH2 (target_flags & SH2_BIT)
95 /* Nonzero if we should generate code using type 3 insns. */
96 #define TARGET_SH3 (target_flags & SH3_BIT)
98 /* Nonzero if we should generate smaller code rather than faster code. */
99 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
101 /* Nonzero to use long jump tables. */
102 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
104 /* Nonzero if using Hitachi's calling convention. */
105 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
107 /* Nonzero if padding structures to a multiple of 4 bytes. This is
108 incompatible with Hitachi's compiler, and gives unusual structure layouts
109 which confuse programmers.
110 ??? This option is not useful, but is retained in case there are people
111 who are still relying on it. It may be deleted in the future. */
112 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
114 /* Nonzero if generating code for a little endian SH. */
115 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
117 #define TARGET_SWITCHES \
121 {"3", SH3_BIT|SH2_BIT}, \
122 {"3l", SH3_BIT|SH2_BIT|LITTLE_ENDIAN_BIT}, \
123 {"b", -LITTLE_ENDIAN_BIT}, \
124 {"bigtable", BIGTABLE_BIT}, \
125 {"dalign", DALIGN_BIT}, \
126 {"hitachi", HITACHI_BIT}, \
127 {"isize", ISIZE_BIT}, \
128 {"l", LITTLE_ENDIAN_BIT}, \
129 {"padstruct", PADSTRUCT_BIT}, \
130 {"space", SPACE_BIT}, \
131 {"", TARGET_DEFAULT} \
134 #define TARGET_DEFAULT (0)
136 #define OVERRIDE_OPTIONS \
146 /* We *MUST* always define optimize since we *HAVE* to run \
147 shorten branches to get correct code. */ \
148 /* ??? This is obsolete, since now shorten branches is no \
149 longer required by the SH, and is always run once even \
150 when not optimizing. Changing this now might be \
151 confusing though. */ \
153 flag_delayed_branch = 1; \
155 /* But never run scheduling before reload, since that can \
156 break global alloc, and generates slower code anyway due \
157 to the pressure on R0. */ \
158 flag_schedule_insns = 0; \
161 /* Target machine storage layout. */
163 /* Define to use software floating point emulator for REAL_ARITHMETIC and
164 decimal <-> binary conversion. */
165 #define REAL_ARITHMETIC
167 /* Define this if most significant bit is lowest numbered
168 in instructions that operate on numbered bit-fields. */
170 #define BITS_BIG_ENDIAN 0
172 /* Define this if most significant byte of a word is the lowest numbered. */
173 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
175 /* Define this if most significant word of a multiword number is the lowest
177 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
179 /* Define this to set the endianness to use in libgcc2.c, which can
180 not depend on target_flags. */
181 #if defined(__LITTLE_ENDIAN__)
182 #define LIBGCC2_WORDS_BIG_ENDIAN 0
184 #define LIBGCC2_WORDS_BIG_ENDIAN 1
187 /* Number of bits in an addressable storage unit. */
188 #define BITS_PER_UNIT 8
190 /* Width in bits of a "word", which is the contents of a machine register.
191 Note that this is not necessarily the width of data type `int';
192 if using 16-bit ints on a 68000, this would still be 32.
193 But on a machine with 16-bit registers, this would be 16. */
194 #define BITS_PER_WORD 32
195 #define MAX_BITS_PER_WORD 32
197 /* Width of a word, in units (bytes). */
198 #define UNITS_PER_WORD 4
200 /* Width in bits of a pointer.
201 See also the macro `Pmode' defined below. */
202 #define POINTER_SIZE 32
204 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
205 #define PARM_BOUNDARY 32
207 /* Boundary (in *bits*) on which stack pointer should be aligned. */
208 #define STACK_BOUNDARY 32
210 /* Allocation boundary (in *bits*) for the code of a function.
211 32 bit alignment is faster, because instructions are always fetched as a
212 pair from a longword boundary. */
213 /* ??? Perhaps also define ASM_OUTPUT_ALIGN_CODE and/or ASM_OUTPUT_LOOP_ALIGN
214 so as to align jump targets and/or loops to 4 byte boundaries when not
215 optimizing for space? */
216 #define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : 32)
218 /* Alignment of field after `int : 0' in a structure. */
219 #define EMPTY_FIELD_BOUNDARY 32
221 /* No data type wants to be aligned rounder than this. */
222 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
224 /* The best alignment to use in cases where we have a choice. */
225 #define FASTEST_ALIGNMENT 32
227 /* Make strings word-aligned so strcpy from constants will be faster. */
228 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
229 ((TREE_CODE (EXP) == STRING_CST \
230 && (ALIGN) < FASTEST_ALIGNMENT) \
231 ? FASTEST_ALIGNMENT : (ALIGN))
233 /* Make arrays of chars word-aligned for the same reasons. */
234 #define DATA_ALIGNMENT(TYPE, ALIGN) \
235 (TREE_CODE (TYPE) == ARRAY_TYPE \
236 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
237 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
239 /* Number of bits which any structure or union's size must be a
240 multiple of. Each structure or union's size is rounded up to a
242 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
244 /* Set this nonzero if move instructions will actually fail to work
245 when given unaligned data. */
246 #define STRICT_ALIGNMENT 1
248 /* Standard register usage. */
250 /* Register allocation for the Hitachi calling convention:
256 r14 frame pointer/call saved
258 ap arg pointer (doesn't really exist, always eliminated)
259 pr subroutine return address
261 mach multiply/accumulate result, high part
262 macl multiply/accumulate result, low part. */
264 /* Number of actual hardware registers.
265 The hardware registers are assigned numbers for the compiler
266 from 0 to just below FIRST_PSEUDO_REGISTER.
267 All registers that the compiler knows about must be given numbers,
268 even those that are not normally considered general registers. */
276 #define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
278 #define FIRST_PSEUDO_REGISTER 22
280 /* 1 for registers that have pervasive standard uses
281 and are not available for the register allocator.
283 Mach register is fixed 'cause it's only 10 bits wide for SH1.
284 It is 32 bits wide for SH2. */
286 #define FIXED_REGISTERS \
294 /* 1 for registers not available across function calls.
295 These must include the FIXED_REGISTERS and also any
296 registers that can be used without being saved.
297 The latter must include the registers where values are returned
298 and the register where structure-value addresses are passed.
299 Aside from that, you can include as many other registers as you like. */
301 #define CALL_USED_REGISTERS \
309 /* Return number of consecutive hard regs needed starting at reg REGNO
310 to hold something of mode MODE.
311 This is ordinarily the length in words of a value of mode MODE
312 but can be less for certain modes in special long registers.
314 On the SH regs are UNITS_PER_WORD bits wide. */
316 #define HARD_REGNO_NREGS(REGNO, MODE) \
317 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
319 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
320 We can allow any mode in any general register. The special registers
321 only allow SImode. Don't allow any mode in the PR. */
323 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
324 (SPECIAL_REG (REGNO) ? (MODE) == SImode \
325 : (REGNO) == PR_REG ? 0 \
328 /* Value is 1 if it is a good idea to tie two pseudo registers
329 when one has mode MODE1 and one has mode MODE2.
330 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
331 for any hard reg, then this must be 0 for correct output. */
333 #define MODES_TIEABLE_P(MODE1, MODE2) \
334 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
336 /* Specify the registers used for certain standard purposes.
337 The values of these macros are register numbers. */
339 /* Define this if the program counter is overloaded on a register. */
340 /* #define PC_REGNUM 15*/
342 /* Register to use for pushing function arguments. */
343 #define STACK_POINTER_REGNUM 15
345 /* Base register for access to local variables of the function. */
346 #define FRAME_POINTER_REGNUM 14
348 /* Value should be nonzero if functions must have frame pointers.
349 Zero means the frame pointer need not be set up (and parms may be accessed
350 via the stack pointer) in functions that seem suitable. */
352 #define FRAME_POINTER_REQUIRED 0
354 /* Definitions for register eliminations.
356 We have two registers that can be eliminated on the SH. First, the
357 frame pointer register can often be eliminated in favor of the stack
358 pointer register. Secondly, the argument pointer register can always be
359 eliminated; it is replaced with either the stack or frame pointer. */
361 /* This is an array of structures. Each structure initializes one pair
362 of eliminable registers. The "from" register number is given first,
363 followed by "to". Eliminations of the same "from" register are listed
364 in order of preference. */
366 #define ELIMINABLE_REGS \
367 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
368 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
369 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
371 /* Given FROM and TO register numbers, say whether this elimination
373 #define CAN_ELIMINATE(FROM, TO) \
374 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
376 /* Define the offset between two registers, one to be eliminated, and the other
377 its replacement, at the start of a routine. */
379 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
380 OFFSET = initial_elimination_offset (FROM, TO)
382 /* Base register for access to arguments of the function. */
383 #define ARG_POINTER_REGNUM 16
385 /* Register in which the static-chain is passed to a function. */
386 #define STATIC_CHAIN_REGNUM 13
388 /* The register in which a struct value address is passed. */
390 #define STRUCT_VALUE_REGNUM 2
392 /* If the structure value address is not passed in a register, define
393 `STRUCT_VALUE' as an expression returning an RTX for the place
394 where the address is passed. If it returns 0, the address is
395 passed as an "invisible" first argument. */
397 /*#define STRUCT_VALUE ((rtx)0)*/
399 /* Don't default to pcc-struct-return, because we have already specified
400 exactly how to return structures in the RETURN_IN_MEMORY macro. */
402 #define DEFAULT_PCC_STRUCT_RETURN 0
404 /* Define the classes of registers for register constraints in the
405 machine description. Also define ranges of constants.
407 One of the classes must always be named ALL_REGS and include all hard regs.
408 If there is more than one class, another class must be named NO_REGS
409 and contain no registers.
411 The name GENERAL_REGS must be the name of a class (or an alias for
412 another name such as ALL_REGS). This is the class of registers
413 that is allowed by "g" or "r" in a register constraint.
414 Also, registers outside this class are allocated only when
415 instructions express preferences for them.
417 The classes must be numbered in nondecreasing order; that is,
418 a larger-numbered class must never be contained completely
419 in a smaller-numbered class.
421 For any two classes, it is very desirable that there be another
422 class that represents their union. */
424 /* The SH has two sorts of general registers, R0 and the rest. R0 can
425 be used as the destination of some of the arithmetic ops. There are
426 also some special purpose registers; the T bit register, the
427 Procedure Return Register and the Multiply Accumulate Registers. */
441 #define N_REG_CLASSES (int) LIM_REG_CLASSES
443 /* Give names of register classes as strings for dump file. */
444 #define REG_CLASS_NAMES \
455 /* Define which registers fit in which classes.
456 This is an initializer for a vector of HARD_REG_SET
457 of length N_REG_CLASSES. */
459 #define REG_CLASS_CONTENTS \
461 0x000000, /* NO_REGS */ \
462 0x000001, /* R0_REGS */ \
463 0x020000, /* PR_REGS */ \
464 0x040000, /* T_REGS */ \
465 0x300000, /* MAC_REGS */ \
466 0x01FFFF, /* GENERAL_REGS */ \
467 0x37FFFF /* ALL_REGS */ \
470 /* The same information, inverted:
471 Return the class number of the smallest class containing
472 reg number REGNO. This could be a conditional expression
473 or could index an array. */
475 extern int regno_reg_class[];
476 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
478 /* When defined, the compiler allows registers explicitly used in the
479 rtl to be used as spill registers but prevents the compiler from
480 extending the lifetime of these registers. */
482 #define SMALL_REGISTER_CLASSES
484 /* The order in which register should be allocated. */
485 #define REG_ALLOC_ORDER \
486 { 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14,15,16,17,18,19,20,21 }
488 /* The class value for index registers, and the one for base regs. */
489 #define INDEX_REG_CLASS R0_REGS
490 #define BASE_REG_CLASS GENERAL_REGS
492 /* Get reg_class from a letter such as appears in the machine
494 extern enum reg_class reg_class_from_letter[];
496 #define REG_CLASS_FROM_LETTER(C) \
497 ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
499 /* The letters I, J, K, L and M in a register constraint string
500 can be used to stand for particular ranges of immediate operands.
501 This macro defines what the ranges are.
502 C is the letter, and VALUE is a constant value.
503 Return 1 if VALUE is in the range specified by C.
504 I: arithmetic operand -127..128, as used in add, sub, etc
505 K: shift operand 1,2,8 or 16
506 L: logical operand 0..255, as used in and, or, etc.
510 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127)
511 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
512 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255)
513 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
514 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
515 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
516 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
517 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
518 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
519 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
520 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
523 /* Similar, but for floating constants, and defining letters G and H.
524 Here VALUE is the CONST_DOUBLE rtx itself. */
526 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
528 /* Given an rtx X being reloaded into a reg required to be
529 in class CLASS, return the class of reg to actually use.
530 In general this is just CLASS; but on some machines
531 in some cases it is preferable to use a more restrictive class. */
533 #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
535 /* Return the maximum number of consecutive registers
536 needed to represent mode MODE in a register of class CLASS.
538 On SH this is the size of MODE in words. */
539 #define CLASS_MAX_NREGS(CLASS, MODE) \
540 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
542 /* Stack layout; function entry, exit and calling. */
544 /* Define the number of registers that can hold parameters.
545 These three macros are used only in other macro definitions below. */
547 #define FIRST_PARM_REG 4
548 #define FIRST_RET_REG 0
550 /* Define this if pushing a word on the stack
551 makes the stack pointer a smaller address. */
552 #define STACK_GROWS_DOWNWARD
554 /* Define this macro if the addresses of local variable slots are at
555 negative offsets from the frame pointer.
557 The SH only has positive indexes, so grow the frame up. */
558 /* #define FRAME_GROWS_DOWNWARD */
560 /* Offset from the frame pointer to the first local variable slot to
562 #define STARTING_FRAME_OFFSET 0
564 /* If we generate an insn to push BYTES bytes,
565 this says how many the stack pointer really advances by. */
566 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
568 /* Offset of first parameter from the argument pointer register value. */
569 #define FIRST_PARM_OFFSET(FNDECL) 0
571 /* Value is the number of byte of arguments automatically
572 popped when returning from a subroutine call.
573 FUNDECL is the declaration node of the function (as a tree),
574 FUNTYPE is the data type of the function (as a tree),
575 or for a library call it is an identifier node for the subroutine name.
576 SIZE is the number of bytes of arguments passed on the stack.
578 On the SH, the caller does not pop any of its arguments that were passed
580 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
582 /* Define how to find the value returned by a function.
583 VALTYPE is the data type of the value (as a tree).
584 If the precise function being called is known, FUNC is its FUNCTION_DECL;
585 otherwise, FUNC is 0. */
587 #define FUNCTION_VALUE(VALTYPE, FUNC) \
588 gen_rtx (REG, TYPE_MODE (VALTYPE), FIRST_RET_REG)
590 /* Define how to find the value returned by a library function
591 assuming the value has mode MODE. */
592 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, FIRST_RET_REG)
594 /* 1 if N is a possible register number for a function value.
595 On the SH, only r0 can return results. */
596 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG)
598 /* 1 if N is a possible register number for function argument passing. */
600 #define FUNCTION_ARG_REGNO_P(REGNO) \
601 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
603 /* Define a data type for recording info about an argument list
604 during the scan of that argument list. This data type should
605 hold all necessary information about the function itself
606 and about the args processed so far, enough to enable macros
607 such as FUNCTION_ARG to determine where the next arg should go.
609 On SH, this is a single integer, which is a number of words
610 of arguments scanned so far (including the invisible argument,
611 if any, which holds the structure-value-address).
612 Thus NARGREGS or more means all following args should go on the stack. */
614 #define CUMULATIVE_ARGS int
616 #define ROUND_ADVANCE(SIZE) \
617 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
619 /* Round a register number up to a proper boundary for an arg of mode
622 The SH doesn't care about double alignment, so we only
623 round doubles to even regs when asked to explicitly. */
625 #define ROUND_REG(X, MODE) \
626 ((TARGET_ALIGN_DOUBLE \
627 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
628 ? ((X) + ((X) & 1)) : (X))
630 /* Initialize a variable CUM of type CUMULATIVE_ARGS
631 for a call to a function whose data type is FNTYPE.
632 For a library call, FNTYPE is 0.
634 On SH, the offset always starts at 0: the first parm reg is always
637 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
640 /* Update the data in CUM to advance over an argument
641 of mode MODE and data type TYPE.
642 (TYPE is null for libcalls where that information may not be
645 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
646 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
647 + ((MODE) != BLKmode \
648 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
649 : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
651 /* Define where to put the arguments to a function.
652 Value is zero to push the argument on the stack,
653 or a hard register in which to store the argument.
655 MODE is the argument's machine mode.
656 TYPE is the data type of the argument (as a tree).
657 This is null for libcalls where that information may
659 CUM is a variable of type CUMULATIVE_ARGS which gives info about
660 the preceding args and about the function being called.
661 NAMED is nonzero if this argument is a named parameter
662 (otherwise it is an extra parameter matching an ellipsis).
664 On SH the first args are normally in registers
665 and the rest are pushed. Any arg that starts within the first
666 NPARM_REGS words is at least partially passed in a register unless
667 its data type forbids. */
669 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
670 sh_function_arg (CUM, MODE, TYPE, NAMED)
672 extern struct rtx_def *sh_function_arg();
674 /* For an arg passed partly in registers and partly in memory,
675 this is the number of registers used.
676 For args passed entirely in registers or entirely in memory, zero.
678 We sometimes split args. */
680 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
681 sh_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
683 extern int current_function_anonymous_args;
685 /* Perform any needed actions needed for a function that is receiving a
686 variable number of arguments. */
688 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
689 current_function_anonymous_args = 1;
691 /* Call the function profiler with a given profile label. */
693 #define FUNCTION_PROFILER(STREAM,LABELNO) \
695 fprintf(STREAM, " trapa #5\n"); \
696 fprintf(STREAM, " .align 2\n"); \
697 fprintf(STREAM, " .long LP%d\n", (LABELNO)); \
700 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
701 the stack pointer does not matter. The value is tested only in
702 functions that have frame pointers.
703 No definition is equivalent to always zero. */
705 #define EXIT_IGNORE_STACK 1
707 /* Generate the assembly code for function exit
708 Just dump out any accumulated constant table. */
710 #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue (STREAM, SIZE)
712 /* Output assembler code for a block containing the constant parts
713 of a trampoline, leaving space for the variable parts.
715 On the SH, the trampoline looks like
716 1 0000 D301 mov.l l1,r3
717 2 0002 DD02 mov.l l2,r13
720 5 0008 00000000 l1: .long function
721 6 000c 00000000 l2: .long area */
722 #define TRAMPOLINE_TEMPLATE(FILE) \
724 fprintf ((FILE), " .word 0xd301\n"); \
725 fprintf ((FILE), " .word 0xdd02\n"); \
726 fprintf ((FILE), " .word 0x4d2b\n"); \
727 fprintf ((FILE), " .word 0x200b\n"); \
728 fprintf ((FILE), " .long 0\n"); \
729 fprintf ((FILE), " .long 0\n"); \
732 /* Length in units of the trampoline for entering a nested function. */
733 #define TRAMPOLINE_SIZE 16
735 /* Alignment required for a trampoline in units. */
736 #define TRAMPOLINE_ALIGN 4
738 /* Emit RTL insns to initialize the variable parts of a trampoline.
739 FNADDR is an RTX for the address of the function's pure code.
740 CXT is an RTX for the static chain value for the function. */
742 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
744 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
746 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
750 /* Addressing modes, and classification of registers for them. */
751 #define HAVE_POST_INCREMENT 1
752 /*#define HAVE_PRE_INCREMENT 1*/
753 /*#define HAVE_POST_DECREMENT 1*/
754 #define HAVE_PRE_DECREMENT 1
756 /* Macros to check register numbers against specific register classes. */
758 /* These assume that REGNO is a hard or pseudo reg number.
759 They give nonzero only if REGNO is a hard reg of the suitable class
760 or a pseudo reg currently allocated to a suitable hard reg.
761 Since they use reg_renumber, they are safe only once reg_renumber
762 has been allocated, which happens in local-alloc.c. */
764 #define REGNO_OK_FOR_BASE_P(REGNO) \
765 ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
766 #define REGNO_OK_FOR_INDEX_P(REGNO) \
767 ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
769 /* Maximum number of registers that can appear in a valid memory
772 #define MAX_REGS_PER_ADDRESS 2
774 /* Recognize any constant value that is a valid address. */
776 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
778 /* Nonzero if the constant value X is a legitimate general operand. */
780 /* ??? Should modify this to accept CONST_DOUBLE, and then modify the
781 constant pool table code to fix loads of CONST_DOUBLEs. If that doesn't
782 work well, then we can at least handle simple CONST_DOUBLEs here
784 #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE)
786 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
787 and check its validity for a certain class.
788 We have two alternate definitions for each of them.
789 The usual definition accepts all pseudo regs; the other rejects
790 them unless they have been allocated suitable hard regs.
791 The symbol REG_OK_STRICT causes the latter definition to be used. */
793 #define MODE_DISP_OK_4(X,MODE) ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<64) && (!(INTVAL(X) &3)))
794 #define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3)))
796 #ifndef REG_OK_STRICT
798 /* Nonzero if X is a hard reg that can be used as a base reg
799 or if it is a pseudo reg. */
800 #define REG_OK_FOR_BASE_P(X) \
801 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
803 /* Nonzero if X is a hard reg that can be used as an index
804 or if it is a pseudo reg. */
805 #define REG_OK_FOR_INDEX_P(X) \
806 (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
808 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
809 or if X is a pseudo reg. */
810 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
811 ((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
815 /* Nonzero if X is a hard reg that can be used as a base reg. */
816 #define REG_OK_FOR_BASE_P(X) \
817 REGNO_OK_FOR_BASE_P (REGNO (X))
819 /* Nonzero if X is a hard reg that can be used as an index. */
820 #define REG_OK_FOR_INDEX_P(X) \
821 REGNO_OK_FOR_INDEX_P (REGNO (X))
823 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
824 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
825 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && OFFSET == 0)
829 /* The 'Q' constraint is a pc relative load operand. */
830 #define EXTRA_CONSTRAINT_Q(OP) \
831 (GET_CODE (OP) == MEM && \
832 ((GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
833 || (GET_CODE (XEXP (OP, 0)) == CONST \
834 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS \
835 && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == LABEL_REF \
836 && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT)))
838 #define EXTRA_CONSTRAINT(OP, C) \
839 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
842 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
843 that is a valid memory address for an instruction.
844 The MODE argument is the machine mode for the MEM expression
845 that wants to use this address.
847 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
849 #define BASE_REGISTER_RTX_P(X) \
850 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
851 || (GET_CODE (X) == SUBREG \
852 && GET_CODE (SUBREG_REG (X)) == REG \
853 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
855 /* Since this must be r0, which is a single register class, we must check
856 SUBREGs more carefully, to be sure that we don't accept one that extends
857 outside the class. */
858 #define INDEX_REGISTER_RTX_P(X) \
859 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
860 || (GET_CODE (X) == SUBREG \
861 && GET_CODE (SUBREG_REG (X)) == REG \
862 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X))))
864 /* Jump to LABEL if X is a valid address RTX. This must also take
865 REG_OK_STRICT into account when deciding about valid registers, but it uses
866 the above macros so we are in luck.
874 /* The SH allows a displacement in a QI or HI amode, but only when the
875 other operand is R0. GCC doesn't handle this very well, so we forgo
878 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
879 DI can be any number 0..60. */
881 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
883 if (GET_CODE (OP) == CONST_INT) \
885 if (MODE_DISP_OK_4 (OP, MODE)) goto LABEL; \
886 if (MODE_DISP_OK_8 (OP, MODE)) goto LABEL; \
890 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
892 if (BASE_REGISTER_RTX_P (X)) \
894 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
895 && BASE_REGISTER_RTX_P (XEXP (X, 0))) \
897 else if (GET_CODE (X) == PLUS) \
899 rtx xop0 = XEXP (X, 0); \
900 rtx xop1 = XEXP (X, 1); \
901 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
902 GO_IF_LEGITIMATE_INDEX (MODE, xop1, LABEL); \
903 if (GET_MODE_SIZE (MODE) <= 4) \
905 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
907 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
913 /* Try machine-dependent ways of modifying an illegitimate address
914 to be legitimate. If we find one, return the new, valid address.
915 This macro is used in only one place: `memory_address' in explow.c.
917 OLDX is the address as it was before break_out_memory_refs was called.
918 In some cases it is useful to look at this to decide what needs to be done.
920 MODE and WIN are passed so that this macro can use
921 GO_IF_LEGITIMATE_ADDRESS.
923 It is always safe for this macro to do nothing. It exists to recognize
924 opportunities to optimize the output. */
926 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) ;
928 /* Go to LABEL if ADDR (a legitimate address expression)
929 has an effect that depends on the machine mode it is used for. */
930 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
932 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
936 /* Specify the machine mode that this machine uses
937 for the index in the tablejump instruction. */
938 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
940 /* Define this if the tablejump instruction expects the table
941 to contain offsets from the address of the table.
942 Do not define this if the table should contain absolute addresses. */
943 #define CASE_VECTOR_PC_RELATIVE
945 /* Specify the tree operation to be used to convert reals to integers. */
946 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
948 /* This is the kind of divide that is easiest to do in the general case. */
949 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
951 /* 'char' is signed by default. */
952 #define DEFAULT_SIGNED_CHAR 1
954 /* The type of size_t unsigned int. */
955 #define SIZE_TYPE "unsigned int"
957 #define WCHAR_TYPE "short unsigned int"
958 #define WCHAR_TYPE_SIZE 16
960 /* Don't cse the address of the function being compiled. */
961 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
963 /* Max number of bytes we can move from memory to memory
964 in one reasonably fast instruction. */
967 /* Define if operations between registers always perform the operation
968 on the full register even if a narrower mode is specified. */
969 #define WORD_REGISTER_OPERATIONS
971 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
972 will either zero-extend or sign-extend. The value of this macro should
973 be the code that says which one of the two operations is implicitly
974 done, NIL if none. */
975 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
977 /* Define this if zero-extension is slow (more than one real instruction).
978 On the SH, it's only one instruction. */
979 /* #define SLOW_ZERO_EXTEND */
981 /* Nonzero if access to memory by bytes is slow and undesirable. */
982 #define SLOW_BYTE_ACCESS 0
984 /* We assume that the store-condition-codes instructions store 0 for false
985 and some other value for true. This is the value stored for true. */
987 #define STORE_FLAG_VALUE 1
989 /* Immediate shift counts are truncated by the output routines (or was it
990 the assembler?). Shift counts in a register are truncated by SH. Note
991 that the native compiler puts too large (> 32) immediate shift counts
992 into a register and shifts by the register, letting the SH decide what
993 to do instead of doing that itself. */
994 /* ??? This is defined, but the library routines in lib1funcs.asm do not
995 truncate the shift count. This may result in incorrect results for
996 unusual cases. Truncating the shift counts in the library routines would
997 make them faster. However, the SH3 has hardware shifts that do not
998 truncate, so it appears that we need to leave this undefined for correct
999 SH3 code. We can still using truncation in the library routines though to
1000 make them faster. */
1001 #define SHIFT_COUNT_TRUNCATED 1
1003 /* All integers have the same format so truncation is easy. */
1004 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1006 /* Define this if addresses of constant functions
1007 shouldn't be put through pseudo regs where they can be cse'd.
1008 Desirable on machines where ordinary constants are expensive
1009 but a CALL with constant address is cheap. */
1010 /*#define NO_FUNCTION_CSE 1*/
1012 /* Chars and shorts should be passed as ints. */
1013 #define PROMOTE_PROTOTYPES 1
1015 /* The machine modes of pointers and functions. */
1016 #define Pmode SImode
1017 #define FUNCTION_MODE Pmode
1019 /* The relative costs of various types of constants. Note that cse.c defines
1020 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1022 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1024 if (INTVAL (RTX) == 0) \
1026 else if (CONST_OK_FOR_I (INTVAL (RTX))) \
1028 else if ((OUTER_CODE == AND || OUTER_CODE == IOR || OUTER_CODE == XOR) \
1029 && CONST_OK_FOR_L (INTVAL (RTX))) \
1037 case CONST_DOUBLE: \
1040 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1042 return COSTS_N_INSNS (andcosts (X)); \
1044 return COSTS_N_INSNS (multcosts (X)); \
1048 return COSTS_N_INSNS (shiftcosts (X)) ; \
1053 return COSTS_N_INSNS (20); \
1058 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1059 are actually function calls with some special constraints on arguments
1062 These macros tell reorg that the references to arguments and
1063 register clobbers for insns of type sfunc do not appear to happen
1064 until after the millicode call. This allows reorg to put insns
1065 which set the argument registers into the delay slot of the millicode
1066 call -- thus they act more like traditional CALL_INSNs.
1068 get_attr_type will try to recognize the given insn, so make sure to
1069 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1072 #define INSN_SETS_ARE_DELAYED(X) \
1073 ((GET_CODE (X) == INSN \
1074 && GET_CODE (PATTERN (X)) != SEQUENCE \
1075 && GET_CODE (PATTERN (X)) != USE \
1076 && GET_CODE (PATTERN (X)) != CLOBBER \
1077 && get_attr_type (X) == TYPE_SFUNC))
1079 #define INSN_REFERENCES_ARE_DELAYED(X) \
1080 ((GET_CODE (X) == INSN \
1081 && GET_CODE (PATTERN (X)) != SEQUENCE \
1082 && GET_CODE (PATTERN (X)) != USE \
1083 && GET_CODE (PATTERN (X)) != CLOBBER \
1084 && get_attr_type (X) == TYPE_SFUNC))
1086 /* Compute extra cost of moving data between one register class
1089 On the SH it is hard to move into the T reg, but simple to load
1092 #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
1093 (((DSTCLASS == T_REGS) || (DSTCLASS == PR_REG)) ? 10 : 1)
1095 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1096 would be so that people would slow memory systems could generate
1097 different code that does fewer memory accesses. */
1099 /* Assembler output control. */
1101 /* The text to go at the start of the assembler file. */
1102 #define ASM_FILE_START(STREAM) \
1103 output_file_start (STREAM, f_options, \
1104 sizeof f_options / sizeof f_options[0], \
1105 W_options, sizeof W_options / sizeof W_options[0]);
1107 #define ASM_FILE_END(STREAM)
1109 #define ASM_APP_ON ""
1110 #define ASM_APP_OFF ""
1111 #define FILE_ASM_OP "\t.file\n"
1112 #define IDENT_ASM_OP "\t.ident\n"
1114 /* How to change between sections. */
1116 #define TEXT_SECTION_ASM_OP "\t.text"
1117 #define DATA_SECTION_ASM_OP "\t.data"
1118 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n"
1119 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n"
1120 #define INIT_SECTION_ASM_OP "\t.section\t.init\n"
1121 #define EXTRA_SECTIONS in_ctors, in_dtors
1122 #define EXTRA_SECTION_FUNCTIONS \
1126 if (in_section != in_ctors) \
1128 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1129 in_section = in_ctors; \
1135 if (in_section != in_dtors) \
1137 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1138 in_section = in_dtors; \
1142 /* A C statement to output something to the assembler file to switch to section
1143 NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
1144 NULL_TREE. Some target formats do not support arbitrary sections. Do not
1145 define this macro in such cases. */
1147 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME) \
1148 do { fprintf (FILE, ".section\t%s\n", NAME); } while (0)
1150 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
1151 do { ctors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1153 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
1154 do { dtors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1156 #undef DO_GLOBAL_CTORS_BODY
1158 #define DO_GLOBAL_CTORS_BODY \
1160 typedef (*pfunc)(); \
1161 extern pfunc __ctors[]; \
1162 extern pfunc __ctors_end[]; \
1164 for (p = __ctors_end; p > __ctors; ) \
1170 #undef DO_GLOBAL_DTORS_BODY
1171 #define DO_GLOBAL_DTORS_BODY \
1173 typedef (*pfunc)(); \
1174 extern pfunc __dtors[]; \
1175 extern pfunc __dtors_end[]; \
1177 for (p = __dtors; p < __dtors_end; p++) \
1183 #define ASM_OUTPUT_REG_PUSH(file, v) \
1184 fprintf (file, "\tmov.l r%s,-@r15\n", v);
1186 #define ASM_OUTPUT_REG_POP(file, v) \
1187 fprintf (file, "\tmov.l @r15+,r%s\n", v);
1189 /* The assembler's names for the registers. RFP need not always be used as
1190 the Real framepointer; it can also be used as a normal general register.
1191 Note that the name `fp' is horribly misleading since `fp' is in fact only
1192 the argument-and-return-context pointer. */
1193 #define REGISTER_NAMES \
1195 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1196 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1197 "ap", "pr", "t", "gbr", "mach","macl" \
1200 /* DBX register number for a given compiler register number. */
1201 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1203 /* Output a label definition. */
1204 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1205 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1207 /* This is how to output an assembler line
1208 that says to advance the location counter
1209 to a multiple of 2**LOG bytes. */
1211 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1213 fprintf (FILE, "\t.align %d\n", LOG)
1215 /* Output a function label definition. */
1216 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1217 ASM_OUTPUT_LABEL(STREAM, NAME)
1219 /* Output a globalising directive for a label. */
1220 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1221 (fprintf (STREAM, "\t.global\t"), \
1222 assemble_name (STREAM, NAME), \
1223 fputc ('\n',STREAM))
1225 /* Output a reference to a label. */
1226 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1227 fprintf (STREAM, "_%s", NAME)
1229 /* Make an internal label into a string. */
1230 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1231 sprintf (STRING, "*%s%d", PREFIX, NUM)
1233 /* Output an internal label definition. */
1234 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1235 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1237 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1239 /* Construct a private name. */
1240 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1241 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1242 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1244 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
1245 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1246 fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM);
1248 /* Output a relative address table. */
1250 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1251 if (TARGET_BIGTABLE) \
1252 fprintf (STREAM, "\t.long L%d-L%d\n", VALUE,REL); \
1254 fprintf (STREAM, "\t.word L%d-L%d\n", VALUE,REL); \
1256 /* Output an absolute table element. */
1258 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1259 if (TARGET_BIGTABLE) \
1260 fprintf (STREAM, "\t.long L%d\n", VALUE); \
1262 fprintf (STREAM, "\t.word L%d\n", VALUE); \
1264 /* Output various types of constants. */
1266 /* This is how to output an assembler line defining a `double'. */
1268 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1269 do { char dstr[30]; \
1270 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1271 fprintf (FILE, "\t.double %s\n", dstr); \
1274 /* This is how to output an assembler line defining a `float' constant. */
1275 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1276 do { char dstr[30]; \
1277 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1278 fprintf (FILE, "\t.float %s\n", dstr); \
1281 #define ASM_OUTPUT_INT(STREAM, EXP) \
1282 (fprintf (STREAM, "\t.long\t"), \
1283 output_addr_const (STREAM, (EXP)), \
1284 fputc ('\n', STREAM))
1286 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1287 (fprintf (STREAM, "\t.short\t"), \
1288 output_addr_const (STREAM, (EXP)), \
1289 fputc ('\n', STREAM))
1291 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1292 (fprintf (STREAM, "\t.byte\t"), \
1293 output_addr_const (STREAM, (EXP)), \
1294 fputc ('\n', STREAM))
1296 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1297 fprintf (STREAM, "\t.byte\t%d\n", VALUE) \
1299 /* This is how to output an assembler line
1300 that says to advance the location counter by SIZE bytes. */
1302 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1303 fprintf (FILE, "\t.space %d\n", (SIZE))
1305 /* This says how to output an assembler line
1306 to define a global common symbol. */
1308 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1309 ( fputs ("\t.comm ", (FILE)), \
1310 assemble_name ((FILE), (NAME)), \
1311 fprintf ((FILE), ",%d\n", (SIZE)))
1313 /* This says how to output an assembler line
1314 to define a local common symbol. */
1316 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
1317 ( fputs ("\t.lcomm ", (FILE)), \
1318 assemble_name ((FILE), (NAME)), \
1319 fprintf ((FILE), ",%d\n", (SIZE)))
1321 /* The assembler's parentheses characters. */
1322 #define ASM_OPEN_PAREN "("
1323 #define ASM_CLOSE_PAREN ")"
1325 /* Target characters. */
1326 #define TARGET_BELL 007
1327 #define TARGET_BS 010
1328 #define TARGET_TAB 011
1329 #define TARGET_NEWLINE 012
1330 #define TARGET_VT 013
1331 #define TARGET_FF 014
1332 #define TARGET_CR 015
1334 /* Only perform branch elimination (by making instructions conditional) if
1335 we're optimizing. Otherwise it's of no use anyway. */
1336 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1337 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1339 /* Print operand X (an rtx) in assembler syntax to file FILE.
1340 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1341 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1343 #define PRINT_OPERAND(STREAM, X, CODE) print_operand (STREAM, X, CODE)
1345 /* Print a memory address as an operand to reference that memory location. */
1347 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address (STREAM, X)
1349 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1350 ((CHAR)=='.' || (CHAR) == '#' || (CHAR)=='@')
1352 extern struct rtx_def *sh_compare_op0;
1353 extern struct rtx_def *sh_compare_op1;
1354 extern struct rtx_def *prepare_scc_operands();
1356 /* Which processor to schedule for. The elements of the enumeration must
1357 match exactly the cpu attribute in the sh.md file. */
1359 enum processor_type {
1366 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
1367 extern enum processor_type sh_cpu;
1369 /* Declare functions defined in sh.c and used in templates. */
1371 extern char *output_branch();
1372 extern char *output_shift();
1373 extern char *output_movedouble();
1374 extern char *output_movepcrel();
1375 extern char *output_jump_label_table();
1376 extern char *output_far_jump();
1378 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
1380 /* Generate calls to memcpy, memcmp and memset. */
1382 #define TARGET_MEM_FUNCTIONS
1384 #define HANDLE_PRAGMA(finput) return handle_pragma (finput)
1386 /* Set when processing a function with pragma interrupt turned on. */
1388 extern int pragma_interrupt;
1390 #define MOVE_RATIO (TARGET_SMALLCODE ? 2 : 16)
1392 /* Instructions with unfilled delay slots take up an extra two bytes for
1393 the nop in the delay slot. */
1395 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1396 if (((GET_CODE (X) == INSN \
1397 && GET_CODE (PATTERN (X)) != SEQUENCE \
1398 && GET_CODE (PATTERN (X)) != USE \
1399 && GET_CODE (PATTERN (X)) != CLOBBER) \
1400 || GET_CODE (X) == CALL_INSN \
1401 || (GET_CODE (X) == JUMP_INSN \
1402 && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \
1403 && GET_CODE (PATTERN (X)) != ADDR_VEC)) \
1404 && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \
1407 /* Enable a bug fix for the shorten_branches pass. */
1408 #define SHORTEN_WITH_ADJUST_INSN_LENGTH
1410 /* Define the codes that are matched by predicates in sh.c. */
1411 #define PREDICATE_CODES \
1412 {"arith_reg_operand", {SUBREG, REG}}, \
1413 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1414 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
1415 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
1416 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1417 {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}},
1419 /* Define this macro if it is advisable to hold scalars in registers
1420 in a wider mode than that declared by the program. In such cases,
1421 the value is constrained to be within the bounds of the declared
1422 type, but kept valid in the wider mode. The signedness of the
1423 extension may differ from that of the type.
1425 Leaving the unsignedp unchanged gives better code than always setting it
1426 to 0. This is despite the fact that we have only signed char and short
1427 load instructions. */
1428 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1429 if (GET_MODE_CLASS (MODE) == MODE_INT \
1430 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1433 /* PROMOTE_FUNCTION_ARGS and PROMOTE_FUNCTION_RETURN appear to have no
1434 effect, because all unprototyped char/shorts are already promoted to
1435 int, and because PROMOTE_PROTOTYPES causes all prototypes char/shorts
1436 to be promoted to it. */
1438 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
1439 and poping arguments. However, we do have push/pop instructions, and
1440 rather limited offsets (4 bits) in load/store instructions, so it isn't
1441 clear if this would give better code. If implemented, should check for
1442 compatibility problems. */
1444 /* ??? Define ADJUST_COSTS? */