1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
35 #define TARGET_CPU_CPP_BUILTINS() \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
43 builtin_define ("__sh1__"); \
46 builtin_define ("__sh2__"); \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
52 builtin_define ("__sh3__"); \
53 builtin_define ("__SH3__"); \
54 if (TARGET_HARD_SH4) \
55 builtin_define ("__SH4_NOFPU__"); \
57 case PROCESSOR_SH3E: \
58 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
61 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
65 builtin_define_with_value ("__SH5__", \
66 TARGET_SHMEDIA64 ? "64" : "32", 0); \
67 builtin_define_with_value ("__SHMEDIA__", \
68 TARGET_SHMEDIA ? "1" : "0", 0); \
69 if (! TARGET_FPU_DOUBLE) \
70 builtin_define ("__SH4_NOFPU__"); \
74 builtin_define ("__HITACHI__"); \
75 builtin_define (TARGET_LITTLE_ENDIAN \
76 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
79 builtin_define ("__pic__"); \
80 builtin_define ("__PIC__"); \
84 /* We can not debug without a frame pointer. */
85 /* #define CAN_DEBUG_WITHOUT_FP */
87 #define CONDITIONAL_REGISTER_USAGE do \
90 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
91 if (! VALID_REGISTER_P (regno)) \
92 fixed_regs[regno] = call_used_regs[regno] = 1; \
93 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
95 call_used_regs[FIRST_GENERAL_REG + 8] \
96 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
99 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
100 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
101 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
104 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
105 /* Renesas saves and restores mac registers on call. */ \
106 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
108 call_used_regs[MACH_REG] = 0; \
109 call_used_regs[MACL_REG] = 0; \
111 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
112 regno <= LAST_FP_REG; regno += 2) \
113 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
114 if (TARGET_SHMEDIA) \
116 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
117 if (! fixed_regs[regno] && call_used_regs[regno]) \
118 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
121 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
122 if (! fixed_regs[regno] && call_used_regs[regno]) \
123 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
126 /* ??? Need to write documentation for all SH options and add it to the
129 /* Run-time compilation parameters selecting different hardware subsets. */
131 extern int target_flags;
132 #define ISIZE_BIT (1<<1)
133 #define DALIGN_BIT (1<<6)
134 #define SH1_BIT (1<<8)
135 #define SH2_BIT (1<<9)
136 #define SH3_BIT (1<<10)
137 #define SH_E_BIT (1<<11)
138 #define HARD_SH4_BIT (1<<5)
139 #define FPU_SINGLE_BIT (1<<7)
140 #define SH4_BIT (1<<12)
141 #define FMOVD_BIT (1<<4)
142 #define SH5_BIT (1<<0)
143 #define SPACE_BIT (1<<13)
144 #define BIGTABLE_BIT (1<<14)
145 #define RELAX_BIT (1<<15)
146 #define USERMODE_BIT (1<<16)
147 #define HITACHI_BIT (1<<22)
148 #define NOMACSAVE_BIT (1<<23)
149 #define PREFERGOT_BIT (1<<24)
150 #define PADSTRUCT_BIT (1<<28)
151 #define LITTLE_ENDIAN_BIT (1<<29)
152 #define IEEE_BIT (1<<30)
153 #define SAVE_ALL_TR_BIT (1<<2)
155 /* Nonzero if this is an ELF target - compile time only */
158 /* Nonzero if we should dump out instruction size info. */
159 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
161 /* Nonzero to align doubles on 64 bit boundaries. */
162 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
164 /* Nonzero if we should generate code using type 1 insns. */
165 #define TARGET_SH1 (target_flags & SH1_BIT)
167 /* Nonzero if we should generate code using type 2 insns. */
168 #define TARGET_SH2 (target_flags & SH2_BIT)
170 /* Nonzero if we should generate code using type 2E insns. */
171 #define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
173 /* Nonzero if we should generate code using type 3 insns. */
174 #define TARGET_SH3 (target_flags & SH3_BIT)
176 /* Nonzero if we should generate code using type 3E insns. */
177 #define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
179 /* Nonzero if the cache line size is 32. */
180 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
182 /* Nonzero if we schedule for a superscalar implementation. */
183 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
185 /* Nonzero if the target has separate instruction and data caches. */
186 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
188 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
189 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
191 /* Nonzero if the default precision of th FPU is single */
192 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
194 /* Nonzero if a double-precision FPU is available. */
195 #define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
197 /* Nonzero if an FPU is available. */
198 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
200 /* Nonzero if we should generate code using type 4 insns. */
201 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
203 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
204 #define TARGET_SH5 (target_flags & SH5_BIT)
206 /* Nonzero if we should generate code using the SHcompact instruction
207 set and 32-bit ABI. */
208 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
210 /* Nonzero if we should generate code using the SHmedia instruction
212 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
214 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
216 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
217 && (target_flags & SH_E_BIT))
219 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
221 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
222 && ! (target_flags & SH_E_BIT))
224 /* Nonzero if we should generate code using SHmedia FPU instructions. */
225 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
226 /* Nonzero if we should generate fmovd. */
227 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
229 /* Nonzero if we respect NANs. */
230 #define TARGET_IEEE (target_flags & IEEE_BIT)
232 /* Nonzero if we should generate smaller code rather than faster code. */
233 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
235 /* Nonzero to use long jump tables. */
236 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
238 /* Nonzero to generate pseudo-ops needed by the assembler and linker
239 to do function call relaxing. */
240 #define TARGET_RELAX (target_flags & RELAX_BIT)
242 /* Nonzero if using Renesas's calling convention. */
243 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
245 /* Nonzero if not saving macl/mach when using -mhitachi */
246 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
248 /* Nonzero if padding structures to a multiple of 4 bytes. This is
249 incompatible with Renesas's compiler, and gives unusual structure layouts
250 which confuse programmers.
251 ??? This option is not useful, but is retained in case there are people
252 who are still relying on it. It may be deleted in the future. */
253 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
255 /* Nonzero if generating code for a little endian SH. */
256 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
258 /* Nonzero if we should do everything in userland. */
259 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
261 /* Nonzero if we should prefer @GOT calls when generating PIC. */
262 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
264 #define TARGET_SAVE_ALL_TARGET_REGS (target_flags & SAVE_ALL_TR_BIT)
266 #define SELECT_SH1 (SH1_BIT)
267 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
268 #define SELECT_SH2E (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
269 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
270 #define SELECT_SH3E (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
271 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
272 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
273 #define SELECT_SH4 (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
274 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
275 #define SELECT_SH5_64 (SH5_BIT | SH4_BIT)
276 #define SELECT_SH5_64_NOFPU (SH5_BIT)
277 #define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH_E_BIT)
278 #define SELECT_SH5_32_NOFPU (SH5_BIT | SH_E_BIT)
279 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
280 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
282 /* Reset all target-selection flags. */
283 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
284 | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
286 #define TARGET_SWITCHES \
287 { {"1", TARGET_NONE, "" }, \
288 {"1", SELECT_SH1, "Generate SH1 code" }, \
289 {"2", TARGET_NONE, "" }, \
290 {"2", SELECT_SH2, "Generate SH2 code" }, \
291 {"2e", TARGET_NONE, "" }, \
292 {"2e", SELECT_SH2E, "Generate SH2e code" }, \
293 {"3", TARGET_NONE, "" }, \
294 {"3", SELECT_SH3, "Generate SH3 code" }, \
295 {"3e", TARGET_NONE, "" }, \
296 {"3e", SELECT_SH3E, "Generate SH3e code" }, \
297 {"4-single-only", TARGET_NONE, "" }, \
298 {"4-single-only", SELECT_SH4_SINGLE_ONLY, "Generate only single-precision SH4 code" }, \
299 {"4-single", TARGET_NONE, "" }, \
300 {"4-single", SELECT_SH4_SINGLE, "Generate default single-precision SH4 code" }, \
301 {"4-nofpu", TARGET_NONE, "" }, \
302 {"4-nofpu", SELECT_SH4_NOFPU, "Generate SH4 FPU-less code" }, \
303 {"4", TARGET_NONE, "" }, \
304 {"4", SELECT_SH4, "Generate SH4 code" }, \
305 {"5-64media", TARGET_NONE, "" }, \
306 {"5-64media", SELECT_SH5_64, "Generate 64-bit SHmedia code" }, \
307 {"5-64media-nofpu", TARGET_NONE, "" }, \
308 {"5-64media-nofpu", SELECT_SH5_64_NOFPU, "Generate 64-bit FPU-less SHmedia code" }, \
309 {"5-32media", TARGET_NONE, "" }, \
310 {"5-32media", SELECT_SH5_32, "Generate 32-bit SHmedia code" }, \
311 {"5-32media-nofpu", TARGET_NONE, "" }, \
312 {"5-32media-nofpu", SELECT_SH5_32_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
313 {"5-compact", TARGET_NONE, "" }, \
314 {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" }, \
315 {"5-compact-nofpu", TARGET_NONE, "" }, \
316 {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" }, \
317 {"b", -LITTLE_ENDIAN_BIT, "Generate code in big endian mode" }, \
318 {"bigtable", BIGTABLE_BIT, "Generate 32-bit offsets in switch tables" }, \
319 {"dalign", DALIGN_BIT, "Aligns doubles at 64-bit boundaries" }, \
320 {"fmovd", FMOVD_BIT, "" }, \
321 {"hitachi", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
322 {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" }, \
323 {"ieee", IEEE_BIT, "Increase the IEEE compliance for floating-point code" }, \
324 {"isize", ISIZE_BIT, "" }, \
325 {"l", LITTLE_ENDIAN_BIT, "Generate code in little endian mode" }, \
326 {"no-ieee", -IEEE_BIT, "" }, \
327 {"padstruct", PADSTRUCT_BIT, "" }, \
328 {"prefergot", PREFERGOT_BIT, "Emit function-calls using global offset table when generating PIC" }, \
329 {"relax", RELAX_BIT, "Shorten address references during linking" }, \
330 {"space", SPACE_BIT, "Deprecated. Use -Os instead" }, \
331 {"usermode", USERMODE_BIT, "Generate library function call to invalidate instruction cache entries after fixing trampoline" }, \
333 {"", TARGET_DEFAULT, "" } \
336 /* This are meant to be redefined in the host dependent files */
337 #define SUBTARGET_SWITCHES
339 /* This defaults us to big-endian. */
340 #ifndef TARGET_ENDIAN_DEFAULT
341 #define TARGET_ENDIAN_DEFAULT 0
344 #ifndef TARGET_CPU_DEFAULT
345 #define TARGET_CPU_DEFAULT SELECT_SH1
348 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
350 #define CPP_SPEC " %(subtarget_cpp_spec) "
352 #ifndef SUBTARGET_CPP_SPEC
353 #define SUBTARGET_CPP_SPEC ""
356 #ifndef SUBTARGET_EXTRA_SPECS
357 #define SUBTARGET_EXTRA_SPECS
360 #define EXTRA_SPECS \
361 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
362 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
363 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
364 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
365 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
366 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
367 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
368 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
369 SUBTARGET_EXTRA_SPECS
371 #if TARGET_CPU_DEFAULT & HARD_SH4_BIT
372 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
374 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
377 #define SH_ASM_SPEC \
378 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
379 %(subtarget_asm_isa_spec)"
381 #define ASM_SPEC SH_ASM_SPEC
383 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
384 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
385 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
387 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
391 #define SUBTARGET_ASM_ISA_SPEC ""
393 #define LINK_EMUL_PREFIX "sh%{ml:l}"
395 #if TARGET_CPU_DEFAULT & SH5_BIT
396 #if TARGET_CPU_DEFAULT & SH_E_BIT
397 #define LINK_DEFAULT_CPU_EMUL "32"
399 #define LINK_DEFAULT_CPU_EMUL "64"
400 #endif /* SH_E_BIT */
402 #define LINK_DEFAULT_CPU_EMUL ""
405 #define SUBTARGET_LINK_EMUL_SUFFIX ""
406 #define SUBTARGET_LINK_SPEC ""
408 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
409 so that we can undo the damage without code replication. */
410 #define LINK_SPEC SH_LINK_SPEC
412 #define SH_LINK_SPEC "\
413 -m %(link_emul_prefix)\
414 %{m5-compact*|m5-32media*:32}\
416 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
417 %(subtarget_link_emul_suffix) \
418 %{mrelax:-relax} %(subtarget_link_spec)"
420 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
423 flag_omit_frame_pointer = -1; \
425 target_flags |= SPACE_BIT; \
426 if (TARGET_SHMEDIA && LEVEL > 1) \
428 flag_branch_target_load_optimize = 1; \
430 target_flags |= SAVE_ALL_TR_BIT; \
434 #define ASSEMBLER_DIALECT assembler_dialect
436 extern int assembler_dialect;
438 #define OVERRIDE_OPTIONS \
443 assembler_dialect = 0; \
454 assembler_dialect = 1; \
460 target_flags |= DALIGN_BIT; \
462 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN)) \
463 target_flags |= FMOVD_BIT; \
464 if (TARGET_SHMEDIA) \
466 /* There are no delay slots on SHmedia. */ \
467 flag_delayed_branch = 0; \
468 /* Relaxation isn't yet supported for SHmedia */ \
469 target_flags &= ~RELAX_BIT; \
471 /* -fprofile-arcs needs a working libgcov . In unified tree \
472 configurations with newlib, this requires to configure with \
473 --with-newlib --with-headers. But there is no way to check \
474 here we have a working libgcov, so just assume that we have. */\
477 warning ("Profiling is not supported on this target."); \
478 profile_flag = profile_arc_flag = 0; \
483 /* Only the sh64-elf assembler fully supports .quad properly. */\
484 targetm.asm_out.aligned_op.di = NULL; \
485 targetm.asm_out.unaligned_op.di = NULL; \
488 reg_class_from_letter['e' - 'a'] = NO_REGS; \
490 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
491 if (! VALID_REGISTER_P (regno)) \
492 sh_register_names[regno][0] = '\0'; \
494 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
495 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
496 sh_additional_register_names[regno][0] = '\0'; \
498 if (flag_omit_frame_pointer < 0) \
500 /* The debugging information is sufficient, \
501 but gdb doesn't implement this yet */ \
503 flag_omit_frame_pointer \
504 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
505 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
507 flag_omit_frame_pointer = 0; \
510 if (flag_pic && ! TARGET_PREFERGOT) \
511 flag_no_function_cse = 1; \
513 if (SMALL_REGISTER_CLASSES) \
515 /* Never run scheduling before reload, since that can \
516 break global alloc, and generates slower code anyway due \
517 to the pressure on R0. */ \
518 flag_schedule_insns = 0; \
521 if (align_loops == 0) \
522 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
523 if (align_jumps == 0) \
524 align_jumps = 1 << CACHE_LOG; \
525 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
526 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
528 /* Allocation boundary (in *bytes*) for the code of a function. \
529 SH1: 32 bit alignment is faster, because instructions are always \
530 fetched as a pair from a longword boundary. \
531 SH2 .. SH5 : align to cache line start. */ \
532 if (align_functions == 0) \
534 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
535 /* The linker relaxation code breaks when a function contains \
536 alignments that are larger than that at the start of a \
537 compilation unit. */ \
541 = align_loops > align_jumps ? align_loops : align_jumps; \
543 /* Also take possible .long constants / mova tables int account. */\
546 if (align_functions < min_align) \
547 align_functions = min_align; \
551 /* Target machine storage layout. */
553 /* Define this if most significant bit is lowest numbered
554 in instructions that operate on numbered bit-fields. */
556 #define BITS_BIG_ENDIAN 0
558 /* Define this if most significant byte of a word is the lowest numbered. */
559 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
561 /* Define this if most significant word of a multiword number is the lowest
563 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
565 /* Define this to set the endianness to use in libgcc2.c, which can
566 not depend on target_flags. */
567 #if defined(__LITTLE_ENDIAN__)
568 #define LIBGCC2_WORDS_BIG_ENDIAN 0
570 #define LIBGCC2_WORDS_BIG_ENDIAN 1
573 #define MAX_BITS_PER_WORD 64
575 #define MAX_LONG_TYPE_SIZE MAX_BITS_PER_WORD
577 /* Width in bits of an `int'. We want just 32-bits, even if words are
579 #define INT_TYPE_SIZE 32
581 /* Width in bits of a `long'. */
582 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
584 /* Width in bits of a `long long'. */
585 #define LONG_LONG_TYPE_SIZE 64
587 /* Width in bits of a `long double'. */
588 #define LONG_DOUBLE_TYPE_SIZE 64
590 /* Width of a word, in units (bytes). */
591 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
592 #define MIN_UNITS_PER_WORD 4
594 /* Scaling factor for Dwarf data offsets for CFI information.
595 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
596 SHmedia; however, since we do partial register saves for the registers
597 visible to SHcompact, and for target registers for SHMEDIA32, we have
598 to allow saves that are only 4-byte aligned. */
599 #define DWARF_CIE_DATA_ALIGNMENT -4
601 /* Width in bits of a pointer.
602 See also the macro `Pmode' defined below. */
603 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
605 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
606 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
608 /* Boundary (in *bits*) on which stack pointer should be aligned. */
609 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
611 /* The log (base 2) of the cache line size, in bytes. Processors prior to
612 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
613 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
614 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
616 /* ABI given & required minimum allocation boundary (in *bits*) for the
617 code of a function. */
618 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
620 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
621 the vbit must go into the delta field of
622 pointers-to-member-functions. */
623 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
624 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
626 /* Alignment of field after `int : 0' in a structure. */
627 #define EMPTY_FIELD_BOUNDARY 32
629 /* No data type wants to be aligned rounder than this. */
630 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
632 /* The best alignment to use in cases where we have a choice. */
633 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
635 /* Make strings word-aligned so strcpy from constants will be faster. */
636 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
637 ((TREE_CODE (EXP) == STRING_CST \
638 && (ALIGN) < FASTEST_ALIGNMENT) \
639 ? FASTEST_ALIGNMENT : (ALIGN))
641 /* get_mode_alignment assumes complex values are always held in multiple
642 registers, but that is not the case on the SH; CQImode and CHImode are
643 held in a single integer register. SH5 also holds CSImode and SCmode
644 values in integer registers. This is relevant for argument passing on
645 SHcompact as we use a stack temp in order to pass CSImode by reference. */
646 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
647 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
648 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
649 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
652 /* Make arrays of chars word-aligned for the same reasons. */
653 #define DATA_ALIGNMENT(TYPE, ALIGN) \
654 (TREE_CODE (TYPE) == ARRAY_TYPE \
655 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
656 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
658 /* Number of bits which any structure or union's size must be a
659 multiple of. Each structure or union's size is rounded up to a
661 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
663 /* Set this nonzero if move instructions will actually fail to work
664 when given unaligned data. */
665 #define STRICT_ALIGNMENT 1
667 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
668 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
669 barrier_align (LABEL_AFTER_BARRIER)
671 #define LOOP_ALIGN(A_LABEL) \
672 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
673 ? 0 : sh_loop_align (A_LABEL))
675 #define LABEL_ALIGN(A_LABEL) \
677 (PREV_INSN (A_LABEL) \
678 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
679 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
680 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
681 /* explicit alignment insn in constant tables. */ \
682 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
685 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
686 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
688 /* The base two logarithm of the known minimum alignment of an insn length. */
689 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
690 (GET_CODE (A_INSN) == INSN \
691 ? 1 << TARGET_SHMEDIA \
692 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
693 ? 1 << TARGET_SHMEDIA \
696 /* Standard register usage. */
698 /* Register allocation for the Renesas calling convention:
704 r14 frame pointer/call saved
706 ap arg pointer (doesn't really exist, always eliminated)
707 pr subroutine return address
709 mach multiply/accumulate result, high part
710 macl multiply/accumulate result, low part.
711 fpul fp/int communication register
712 rap return address pointer register
714 fr1..fr3 scratch floating point registers
716 fr12..fr15 call saved floating point registers */
718 #define MAX_REGISTER_NAME_LENGTH 5
719 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
721 #define SH_REGISTER_NAMES_INITIALIZER \
723 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
724 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
725 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
726 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
727 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
728 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
729 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
730 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
731 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
732 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
733 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
734 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
735 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
736 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
737 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
738 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
739 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
740 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
741 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
745 #define DEBUG_REGISTER_NAMES SH_REGISTER_NAMES_INITIALIZER
747 #define REGNAMES_ARR_INDEX_1(index) \
748 (sh_register_names[index])
749 #define REGNAMES_ARR_INDEX_2(index) \
750 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
751 #define REGNAMES_ARR_INDEX_4(index) \
752 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
753 #define REGNAMES_ARR_INDEX_8(index) \
754 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
755 #define REGNAMES_ARR_INDEX_16(index) \
756 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
757 #define REGNAMES_ARR_INDEX_32(index) \
758 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
759 #define REGNAMES_ARR_INDEX_64(index) \
760 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
762 #define REGISTER_NAMES \
764 REGNAMES_ARR_INDEX_64 (0), \
765 REGNAMES_ARR_INDEX_64 (64), \
766 REGNAMES_ARR_INDEX_8 (128), \
767 REGNAMES_ARR_INDEX_8 (136), \
768 REGNAMES_ARR_INDEX_8 (144), \
769 REGNAMES_ARR_INDEX_1 (152) \
772 #define ADDREGNAMES_SIZE 32
773 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
774 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
775 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
777 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
779 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
780 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
781 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
782 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
785 #define ADDREGNAMES_REGNO(index) \
786 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
789 #define ADDREGNAMES_ARR_INDEX_1(index) \
790 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
791 #define ADDREGNAMES_ARR_INDEX_2(index) \
792 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
793 #define ADDREGNAMES_ARR_INDEX_4(index) \
794 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
795 #define ADDREGNAMES_ARR_INDEX_8(index) \
796 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
797 #define ADDREGNAMES_ARR_INDEX_16(index) \
798 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
799 #define ADDREGNAMES_ARR_INDEX_32(index) \
800 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
802 #define ADDITIONAL_REGISTER_NAMES \
804 ADDREGNAMES_ARR_INDEX_32 (0) \
807 /* Number of actual hardware registers.
808 The hardware registers are assigned numbers for the compiler
809 from 0 to just below FIRST_PSEUDO_REGISTER.
810 All registers that the compiler knows about must be given numbers,
811 even those that are not normally considered general registers. */
813 /* There are many other relevant definitions in sh.md's md_constants. */
815 #define FIRST_GENERAL_REG R0_REG
816 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
817 #define FIRST_FP_REG DR0_REG
818 #define LAST_FP_REG (FIRST_FP_REG + \
819 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
820 #define FIRST_XD_REG XD0_REG
821 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
822 #define FIRST_TARGET_REG TR0_REG
823 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
825 #define GENERAL_REGISTER_P(REGNO) \
827 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
828 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
830 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
831 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
833 #define FP_REGISTER_P(REGNO) \
834 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
836 #define XD_REGISTER_P(REGNO) \
837 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
839 #define FP_OR_XD_REGISTER_P(REGNO) \
840 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
842 #define FP_ANY_REGISTER_P(REGNO) \
843 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
845 #define SPECIAL_REGISTER_P(REGNO) \
846 ((REGNO) == GBR_REG || (REGNO) == T_REG \
847 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
849 #define TARGET_REGISTER_P(REGNO) \
850 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
852 #define SHMEDIA_REGISTER_P(REGNO) \
853 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
854 || TARGET_REGISTER_P (REGNO))
856 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
857 that should be fixed. */
858 #define VALID_REGISTER_P(REGNO) \
859 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
860 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
861 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
862 || (TARGET_SH2E && (REGNO) == FPUL_REG))
864 /* The mode that should be generally used to store a register by
865 itself in the stack, or to load it back. */
866 #define REGISTER_NATURAL_MODE(REGNO) \
867 (FP_REGISTER_P (REGNO) ? SFmode \
868 : XD_REGISTER_P (REGNO) ? DFmode \
869 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
873 #define FIRST_PSEUDO_REGISTER 153
875 /* 1 for registers that have pervasive standard uses
876 and are not available for the register allocator.
878 Mach register is fixed 'cause it's only 10 bits wide for SH1.
879 It is 32 bits wide for SH2. */
881 #define FIXED_REGISTERS \
883 /* Regular registers. */ \
884 0, 0, 0, 0, 0, 0, 0, 0, \
885 0, 0, 0, 0, 0, 0, 0, 1, \
886 /* r16 is reserved, r18 is the former pr. */ \
887 1, 0, 0, 0, 0, 0, 0, 0, \
888 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
889 /* r26 is a global variable data pointer; r27 is for constants. */ \
890 1, 1, 1, 1, 0, 0, 0, 0, \
891 0, 0, 0, 0, 0, 0, 0, 0, \
892 0, 0, 0, 0, 0, 0, 0, 0, \
893 0, 0, 0, 0, 0, 0, 0, 0, \
894 0, 0, 0, 0, 0, 0, 0, 1, \
895 /* FP registers. */ \
896 0, 0, 0, 0, 0, 0, 0, 0, \
897 0, 0, 0, 0, 0, 0, 0, 0, \
898 0, 0, 0, 0, 0, 0, 0, 0, \
899 0, 0, 0, 0, 0, 0, 0, 0, \
900 0, 0, 0, 0, 0, 0, 0, 0, \
901 0, 0, 0, 0, 0, 0, 0, 0, \
902 0, 0, 0, 0, 0, 0, 0, 0, \
903 0, 0, 0, 0, 0, 0, 0, 0, \
904 /* Branch target registers. */ \
905 0, 0, 0, 0, 0, 0, 0, 0, \
906 /* XD registers. */ \
907 0, 0, 0, 0, 0, 0, 0, 0, \
908 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
909 1, 1, 1, 1, 1, 1, 0, 1, \
914 /* 1 for registers not available across function calls.
915 These must include the FIXED_REGISTERS and also any
916 registers that can be used without being saved.
917 The latter must include the registers where values are returned
918 and the register where structure-value addresses are passed.
919 Aside from that, you can include as many other registers as you like. */
921 #define CALL_USED_REGISTERS \
923 /* Regular registers. */ \
924 1, 1, 1, 1, 1, 1, 1, 1, \
925 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
926 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
927 across SH5 function calls. */ \
928 0, 0, 0, 0, 0, 0, 0, 1, \
929 1, 1, 0, 1, 1, 1, 1, 1, \
930 1, 1, 1, 1, 0, 0, 0, 0, \
931 0, 0, 0, 0, 1, 1, 1, 1, \
932 1, 1, 1, 1, 0, 0, 0, 0, \
933 0, 0, 0, 0, 0, 0, 0, 0, \
934 0, 0, 0, 0, 1, 1, 1, 1, \
935 /* FP registers. */ \
936 1, 1, 1, 1, 1, 1, 1, 1, \
937 1, 1, 1, 1, 0, 0, 0, 0, \
938 1, 1, 1, 1, 1, 1, 1, 1, \
939 1, 1, 1, 1, 1, 1, 1, 1, \
940 1, 1, 1, 1, 0, 0, 0, 0, \
941 0, 0, 0, 0, 0, 0, 0, 0, \
942 0, 0, 0, 0, 0, 0, 0, 0, \
943 0, 0, 0, 0, 0, 0, 0, 0, \
944 /* Branch target registers. */ \
945 1, 1, 1, 1, 1, 0, 0, 0, \
946 /* XD registers. */ \
947 1, 1, 1, 1, 1, 1, 0, 0, \
948 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
949 1, 1, 0, 1, 1, 1, 1, 1, \
954 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
955 across SHcompact function calls. We can't tell whether a called
956 function is SHmedia or SHcompact, so we assume it may be when
957 compiling SHmedia code with the 32-bit ABI, since that's the only
958 ABI that can be linked with SHcompact code. */
959 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
961 && GET_MODE_SIZE (MODE) > 4 \
962 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
963 && (REGNO) <= FIRST_GENERAL_REG + 15) \
964 || TARGET_REGISTER_P (REGNO) \
965 || (REGNO) == PR_MEDIA_REG))
967 /* Return number of consecutive hard regs needed starting at reg REGNO
968 to hold something of mode MODE.
969 This is ordinarily the length in words of a value of mode MODE
970 but can be less for certain modes in special long registers.
972 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
974 #define HARD_REGNO_NREGS(REGNO, MODE) \
975 (XD_REGISTER_P (REGNO) \
976 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
977 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
978 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
979 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
981 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
982 We can allow any mode in any general register. The special registers
983 only allow SImode. Don't allow any mode in the PR. */
985 /* We cannot hold DCmode values in the XD registers because alter_reg
986 handles subregs of them incorrectly. We could work around this by
987 spacing the XD registers like the DR registers, but this would require
988 additional memory in every compilation to hold larger register vectors.
989 We could hold SFmode / SCmode values in XD registers, but that
990 would require a tertiary reload when reloading from / to memory,
991 and a secondary reload to reload from / to general regs; that
992 seems to be a loosing proposition. */
993 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
994 it won't be ferried through GP registers first. */
995 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
996 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
997 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
998 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1000 : (MODE) == V2SFmode \
1001 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1002 || GENERAL_REGISTER_P (REGNO)) \
1003 : (MODE) == V4SFmode \
1004 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1005 || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
1006 : (MODE) == V16SFmode \
1008 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1009 : (REGNO) == FIRST_XD_REG) \
1010 : FP_REGISTER_P (REGNO) \
1011 ? ((MODE) == SFmode || (MODE) == SImode \
1012 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1013 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
1014 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1015 || (MODE) == V2SFmode || (MODE) == TImode))) \
1016 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
1017 : XD_REGISTER_P (REGNO) \
1018 ? (MODE) == DFmode \
1019 : TARGET_REGISTER_P (REGNO) \
1020 ? ((MODE) == DImode || (MODE) == SImode) \
1021 : (REGNO) == PR_REG ? (MODE) == SImode \
1022 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1025 /* Value is 1 if MODE is a supported vector mode. */
1026 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1028 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
1029 || (TARGET_SHMEDIA \
1030 && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
1031 || (MODE) == V2SImode)))
1033 /* Value is 1 if it is a good idea to tie two pseudo registers
1034 when one has mode MODE1 and one has mode MODE2.
1035 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1036 for any hard reg, then this must be 0 for correct output.
1037 That's the case for xd registers: we don't hold SFmode values in
1038 them, so we can't tie an SFmode pseudos with one in another
1039 floating-point mode. */
1041 #define MODES_TIEABLE_P(MODE1, MODE2) \
1042 ((MODE1) == (MODE2) \
1043 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1044 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1045 && (GET_MODE_SIZE (MODE2) <= 4)) \
1046 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1048 /* A C expression that is nonzero if hard register NEW_REG can be
1049 considered for use as a rename register for OLD_REG register */
1051 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1052 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1054 /* Specify the registers used for certain standard purposes.
1055 The values of these macros are register numbers. */
1057 /* Define this if the program counter is overloaded on a register. */
1058 /* #define PC_REGNUM 15*/
1060 /* Register to use for pushing function arguments. */
1061 #define STACK_POINTER_REGNUM SP_REG
1063 /* Base register for access to local variables of the function. */
1064 #define FRAME_POINTER_REGNUM FP_REG
1066 /* Fake register that holds the address on the stack of the
1067 current function's return address. */
1068 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1070 /* Register to hold the addressing base for position independent
1071 code access to data items. */
1072 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1074 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1076 /* Value should be nonzero if functions must have frame pointers.
1077 Zero means the frame pointer need not be set up (and parms may be accessed
1078 via the stack pointer) in functions that seem suitable. */
1080 #define FRAME_POINTER_REQUIRED 0
1082 /* Definitions for register eliminations.
1084 We have three registers that can be eliminated on the SH. First, the
1085 frame pointer register can often be eliminated in favor of the stack
1086 pointer register. Secondly, the argument pointer register can always be
1087 eliminated; it is replaced with either the stack or frame pointer.
1088 Third, there is the return address pointer, which can also be replaced
1089 with either the stack or the frame pointer. */
1091 /* This is an array of structures. Each structure initializes one pair
1092 of eliminable registers. The "from" register number is given first,
1093 followed by "to". Eliminations of the same "from" register are listed
1094 in order of preference. */
1096 /* If you add any registers here that are not actually hard registers,
1097 and that have any alternative of elimination that doesn't always
1098 apply, you need to amend calc_live_regs to exclude it, because
1099 reload spills all eliminable registers where it sees an
1100 can_eliminate == 0 entry, thus making them 'live' .
1101 If you add any hard registers that can be eliminated in different
1102 ways, you have to patch reload to spill them only when all alternatives
1103 of elimination fail. */
1105 #define ELIMINABLE_REGS \
1106 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1107 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1108 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1109 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1110 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1112 /* Given FROM and TO register numbers, say whether this elimination
1114 #define CAN_ELIMINATE(FROM, TO) \
1115 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1117 /* Define the offset between two registers, one to be eliminated, and the other
1118 its replacement, at the start of a routine. */
1120 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1121 OFFSET = initial_elimination_offset ((FROM), (TO))
1123 /* Base register for access to arguments of the function. */
1124 #define ARG_POINTER_REGNUM AP_REG
1126 /* Register in which the static-chain is passed to a function. */
1127 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1129 /* The register in which a struct value address is passed. */
1131 #define STRUCT_VALUE_REGNUM 2
1133 /* If the structure value address is not passed in a register, define
1134 `STRUCT_VALUE' as an expression returning an RTX for the place
1135 where the address is passed. If it returns 0, the address is
1136 passed as an "invisible" first argument. */
1138 /* The Renesas calling convention doesn't quite fit into this scheme since
1139 the address is passed like an invisible argument, but one that is always
1140 passed in memory. */
1141 #define STRUCT_VALUE \
1142 (TARGET_HITACHI ? 0 : gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM))
1144 #define RETURN_IN_MEMORY(TYPE) \
1146 ? ((TYPE_MODE (TYPE) == BLKmode \
1147 ? (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
1148 : GET_MODE_SIZE (TYPE_MODE (TYPE))) > 8) \
1149 : (TYPE_MODE (TYPE) == BLKmode \
1150 || (TARGET_HITACHI && TREE_CODE (TYPE) == RECORD_TYPE)))
1152 /* Don't default to pcc-struct-return, because we have already specified
1153 exactly how to return structures in the RETURN_IN_MEMORY macro. */
1155 #define DEFAULT_PCC_STRUCT_RETURN 0
1157 #define SHMEDIA_REGS_STACK_ADJUST() \
1158 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1159 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1160 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1164 /* Define the classes of registers for register constraints in the
1165 machine description. Also define ranges of constants.
1167 One of the classes must always be named ALL_REGS and include all hard regs.
1168 If there is more than one class, another class must be named NO_REGS
1169 and contain no registers.
1171 The name GENERAL_REGS must be the name of a class (or an alias for
1172 another name such as ALL_REGS). This is the class of registers
1173 that is allowed by "g" or "r" in a register constraint.
1174 Also, registers outside this class are allocated only when
1175 instructions express preferences for them.
1177 The classes must be numbered in nondecreasing order; that is,
1178 a larger-numbered class must never be contained completely
1179 in a smaller-numbered class.
1181 For any two classes, it is very desirable that there be another
1182 class that represents their union. */
1184 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1185 be used as the destination of some of the arithmetic ops. There are
1186 also some special purpose registers; the T bit register, the
1187 Procedure Return Register and the Multiply Accumulate Registers. */
1188 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1189 reg_class_subunion. We don't want to have an actual union class
1190 of these, because it would only be used when both classes are calculated
1191 to give the same cost, but there is only one FPUL register.
1192 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1193 applying to the actual instruction alternative considered. E.g., the
1194 y/r alternative of movsi_ie is considered to have no more cost that
1195 the r/r alternative, which is patently untrue. */
1218 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1220 /* Give names of register classes as strings for dump file. */
1221 #define REG_CLASS_NAMES \
1236 "GENERAL_FP_REGS", \
1241 /* Define which registers fit in which classes.
1242 This is an initializer for a vector of HARD_REG_SET
1243 of length N_REG_CLASSES. */
1245 #define REG_CLASS_CONTENTS \
1248 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1250 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1252 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1254 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1256 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1258 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1259 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1260 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1261 /* GENERAL_REGS: */ \
1262 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1264 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1266 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1267 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1268 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1270 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1272 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1273 /* GENERAL_FP_REGS: */ \
1274 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1275 /* TARGET_REGS: */ \
1276 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1278 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1281 /* The same information, inverted:
1282 Return the class number of the smallest class containing
1283 reg number REGNO. This could be a conditional expression
1284 or could index an array. */
1286 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1287 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1289 /* When defined, the compiler allows registers explicitly used in the
1290 rtl to be used as spill registers but prevents the compiler from
1291 extending the lifetime of these registers. */
1293 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1295 /* The order in which register should be allocated. */
1296 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1297 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1298 spilled or used otherwise, we better have the FP_REGS allocated first. */
1299 #define REG_ALLOC_ORDER \
1300 {/* Caller-saved FPRs */ \
1301 65, 66, 67, 68, 69, 70, 71, 64, \
1302 72, 73, 74, 75, 80, 81, 82, 83, \
1303 84, 85, 86, 87, 88, 89, 90, 91, \
1304 92, 93, 94, 95, 96, 97, 98, 99, \
1305 /* Callee-saved FPRs */ \
1306 76, 77, 78, 79,100,101,102,103, \
1307 104,105,106,107,108,109,110,111, \
1308 112,113,114,115,116,117,118,119, \
1309 120,121,122,123,124,125,126,127, \
1310 136,137,138,139,140,141,142,143, \
1312 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1313 1, 2, 3, 7, 6, 5, 4, 0, \
1314 8, 9, 17, 19, 20, 21, 22, 23, \
1315 36, 37, 38, 39, 40, 41, 42, 43, \
1317 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1318 10, 11, 12, 13, 14, 18, \
1319 /* SH5 callee-saved GPRs */ \
1320 28, 29, 30, 31, 32, 33, 34, 35, \
1321 44, 45, 46, 47, 48, 49, 50, 51, \
1322 52, 53, 54, 55, 56, 57, 58, 59, \
1324 /* SH5 branch target registers */ \
1325 128,129,130,131,132,133,134,135, \
1326 /* Fixed registers */ \
1327 15, 16, 24, 25, 26, 27, 63,144, \
1328 145,146,147,148,149,152 }
1330 /* The class value for index registers, and the one for base regs. */
1331 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1332 #define BASE_REG_CLASS GENERAL_REGS
1334 /* Get reg_class from a letter such as appears in the machine
1336 extern enum reg_class reg_class_from_letter[];
1338 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1339 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1340 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1342 /* Overview of uppercase letter constraints:
1343 A: Addresses (constraint len == 3)
1344 Ac4: sh4 cache operations
1345 Ac5: sh5 cache operations
1346 Bxx: miscellaneous constraints
1347 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1349 C: Constants other than only CONST_INT (constraint len == 3)
1350 C16: 16 bit constant, literal or symbolic
1351 Csy: label or symbol
1352 Cpg: non-explicit constants that can be directly loaded into a general
1353 purpose register in PIC code. like 's' except we don't allow
1355 IJKLMNOP: CONT_INT constants
1357 J16: 0xffffffff00000000 | 0x00000000ffffffff
1358 Kxx: unsigned xx bit
1362 Q: pc relative load operand
1363 Rxx: reserved for exotic register classes.
1364 S: extra memory (storage) constraints (constraint len == 3)
1365 Sua: unaligned memory operations
1369 unused CONST_INT constraint letters: LO
1370 unused EXTRA_CONSTRAINT letters: D T U Y */
1372 #if 1 /* check that the transition went well. */
1373 #define CONSTRAINT_LEN(C,STR) \
1374 (((C) == 'L' || (C) == 'O' || (C) == 'D' || (C) == 'T' || (C) == 'U' \
1377 && (((STR)[1] != '0' && (STR)[1] != '1') \
1378 || (STR)[2] < '0' || (STR)[2] > '9')) \
1379 || ((C) == 'B' && ((STR)[1] != 's' || (STR)[2] != 'c')) \
1380 || ((C) == 'J' && ((STR)[1] != '1' || (STR)[2] != '6')) \
1381 || ((C) == 'K' && ((STR)[1] != '0' || (STR)[2] != '8')) \
1382 || ((C) == 'P' && ((STR)[1] != '2' || (STR)[2] != '7'))) \
1384 : ((C) == 'A' || (C) == 'B' || (C) == 'C' \
1385 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1386 || (C) == 'R' || (C) == 'S') \
1388 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1390 #define CONSTRAINT_LEN(C,STR) \
1391 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1392 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1393 || (C) == 'R' || (C) == 'S') \
1394 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1397 /* The letters I, J, K, L and M in a register constraint string
1398 can be used to stand for particular ranges of immediate operands.
1399 This macro defines what the ranges are.
1400 C is the letter, and VALUE is a constant value.
1401 Return 1 if VALUE is in the range specified by C.
1402 I08: arithmetic operand -127..128, as used in add, sub, etc
1403 I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1404 P27: shift operand 1,2,8 or 16
1405 K08: logical operand 0..255, as used in and, or, etc.
1408 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1409 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1412 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1413 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1414 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1415 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1416 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1417 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1418 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1419 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1420 #define CONST_OK_FOR_I(VALUE, STR) \
1421 ((STR)[1] == '0' && (STR)[2] == 6 ? CONST_OK_FOR_I06 (VALUE) \
1422 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1423 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1424 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1427 #define CONST_OK_FOR_J16(VALUE) \
1428 (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff \
1429 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1430 #define CONST_OK_FOR_J(VALUE, STR) \
1431 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1434 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1435 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1436 #define CONST_OK_FOR_K(VALUE, STR) \
1437 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1439 #define CONST_OK_FOR_P27(VALUE) \
1440 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1441 #define CONST_OK_FOR_P(VALUE, STR) \
1442 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1444 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1445 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1446 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1447 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1448 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1449 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1450 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1451 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1452 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1455 /* Similar, but for floating constants, and defining letters G and H.
1456 Here VALUE is the CONST_DOUBLE rtx itself. */
1458 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1459 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1460 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1463 /* Given an rtx X being reloaded into a reg required to be
1464 in class CLASS, return the class of reg to actually use.
1465 In general this is just CLASS; but on some machines
1466 in some cases it is preferable to use a more restrictive class. */
1468 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1469 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1470 && (GET_CODE (X) == CONST_DOUBLE \
1471 || GET_CODE (X) == SYMBOL_REF) \
1475 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1476 ((((REGCLASS_HAS_FP_REG (CLASS) \
1477 && (GET_CODE (X) == REG \
1478 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1479 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1480 && TARGET_FMOVD)))) \
1481 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1482 && GET_CODE (X) == REG \
1483 && FP_REGISTER_P (REGNO (X)))) \
1484 && ! TARGET_SHMEDIA \
1485 && ((MODE) == SFmode || (MODE) == SImode)) \
1487 : (((CLASS) == FPUL_REGS \
1488 || (REGCLASS_HAS_FP_REG (CLASS) \
1489 && ! TARGET_SHMEDIA && MODE == SImode)) \
1490 && (GET_CODE (X) == MEM \
1491 || (GET_CODE (X) == REG \
1492 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1493 || REGNO (X) == T_REG \
1494 || system_reg_operand (X, VOIDmode))))) \
1496 : ((CLASS) == TARGET_REGS \
1497 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1498 ? ((target_operand ((X), (MODE)) \
1499 && ! target_reg_operand ((X), (MODE))) \
1500 ? NO_REGS : GENERAL_REGS) \
1501 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1502 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1503 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1505 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1506 && TARGET_REGISTER_P (REGNO (X))) \
1507 ? GENERAL_REGS : NO_REGS)
1509 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1510 ((REGCLASS_HAS_FP_REG (CLASS) \
1511 && ! TARGET_SHMEDIA \
1512 && immediate_operand ((X), (MODE)) \
1513 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1514 && (MODE) == SFmode && fldi_ok ())) \
1516 : (CLASS == FPUL_REGS \
1517 && ((GET_CODE (X) == REG \
1518 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1519 || REGNO (X) == T_REG)) \
1520 || GET_CODE (X) == PLUS)) \
1522 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1523 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1526 : (CLASS == FPSCR_REGS \
1527 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1528 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1530 : (REGCLASS_HAS_FP_REG (CLASS) \
1532 && immediate_operand ((X), (MODE)) \
1533 && (X) != CONST0_RTX (GET_MODE (X)) \
1534 && GET_MODE (X) != V4SFmode) \
1536 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1538 /* Return the maximum number of consecutive registers
1539 needed to represent mode MODE in a register of class CLASS.
1541 If TARGET_SHMEDIA, we need two FP registers per word.
1542 Otherwise we will need at most one register per word. */
1543 #define CLASS_MAX_NREGS(CLASS, MODE) \
1545 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1546 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1547 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1549 /* If defined, gives a class of registers that cannot be used as the
1550 operand of a SUBREG that changes the mode of the object illegally. */
1551 /* ??? We need to renumber the internal numbers for the frnn registers
1552 when in little endian in order to allow mode size changes. */
1554 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1555 sh_cannot_change_mode_class (FROM, TO, CLASS)
1557 /* Stack layout; function entry, exit and calling. */
1559 /* Define the number of registers that can hold parameters.
1560 These macros are used only in other macro definitions below. */
1562 #define NPARM_REGS(MODE) \
1563 (TARGET_FPU_ANY && (MODE) == SFmode \
1564 ? (TARGET_SH5 ? 12 : 8) \
1565 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1566 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1567 ? (TARGET_SH5 ? 12 : 8) \
1568 : (TARGET_SH5 ? 8 : 4))
1570 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1571 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1573 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1574 #define FIRST_FP_RET_REG FIRST_FP_REG
1576 /* Define this if pushing a word on the stack
1577 makes the stack pointer a smaller address. */
1578 #define STACK_GROWS_DOWNWARD
1580 /* Define this macro if the addresses of local variable slots are at
1581 negative offsets from the frame pointer.
1583 The SH only has positive indexes, so grow the frame up. */
1584 /* #define FRAME_GROWS_DOWNWARD */
1586 /* Offset from the frame pointer to the first local variable slot to
1588 #define STARTING_FRAME_OFFSET 0
1590 /* If we generate an insn to push BYTES bytes,
1591 this says how many the stack pointer really advances by. */
1592 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1593 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1594 do correct alignment. */
1596 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1599 /* Offset of first parameter from the argument pointer register value. */
1600 #define FIRST_PARM_OFFSET(FNDECL) 0
1602 /* Value is the number of byte of arguments automatically
1603 popped when returning from a subroutine call.
1604 FUNDECL is the declaration node of the function (as a tree),
1605 FUNTYPE is the data type of the function (as a tree),
1606 or for a library call it is an identifier node for the subroutine name.
1607 SIZE is the number of bytes of arguments passed on the stack.
1609 On the SH, the caller does not pop any of its arguments that were passed
1611 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1613 /* Value is the number of bytes of arguments automatically popped when
1614 calling a subroutine.
1615 CUM is the accumulated argument list.
1617 On SHcompact, the call trampoline pops arguments off the stack. */
1618 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1620 /* Nonzero if we do not know how to pass TYPE solely in registers.
1621 Values that come in registers with inconvenient padding are stored
1622 to memory at the function start. */
1624 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1626 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1627 || TREE_ADDRESSABLE (TYPE)))
1628 /* Some subroutine macros specific to this machine. */
1630 #define BASE_RETURN_VALUE_REG(MODE) \
1631 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1632 ? FIRST_FP_RET_REG \
1633 : TARGET_FPU_ANY && (MODE) == SCmode \
1634 ? FIRST_FP_RET_REG \
1635 : (TARGET_FPU_DOUBLE \
1636 && ((MODE) == DFmode || (MODE) == SFmode \
1637 || (MODE) == DCmode || (MODE) == SCmode )) \
1638 ? FIRST_FP_RET_REG \
1641 #define BASE_ARG_REG(MODE) \
1642 ((TARGET_SH2E && ((MODE) == SFmode)) \
1643 ? FIRST_FP_PARM_REG \
1644 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1645 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1646 ? FIRST_FP_PARM_REG \
1649 /* Define how to find the value returned by a function.
1650 VALTYPE is the data type of the value (as a tree).
1651 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1652 otherwise, FUNC is 0.
1653 For the SH, this is like LIBCALL_VALUE, except that we must change the
1654 mode like PROMOTE_MODE does.
1655 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1656 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1658 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1660 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1661 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1662 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1663 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1664 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1665 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1666 || TREE_CODE (VALTYPE) == REAL_TYPE \
1667 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1668 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1669 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1671 /* Define how to find the value returned by a library function
1672 assuming the value has mode MODE. */
1673 #define LIBCALL_VALUE(MODE) \
1674 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1676 /* 1 if N is a possible register number for a function value. */
1677 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1678 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1679 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1681 /* 1 if N is a possible register number for function argument passing. */
1682 /* ??? There are some callers that pass REGNO as int, and others that pass
1683 it as unsigned. We get warnings unless we do casts everywhere. */
1684 #define FUNCTION_ARG_REGNO_P(REGNO) \
1685 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1686 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1687 || (TARGET_FPU_ANY \
1688 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1689 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1690 + NPARM_REGS (SFmode))))
1692 /* Define a data type for recording info about an argument list
1693 during the scan of that argument list. This data type should
1694 hold all necessary information about the function itself
1695 and about the args processed so far, enough to enable macros
1696 such as FUNCTION_ARG to determine where the next arg should go.
1698 On SH, this is a single integer, which is a number of words
1699 of arguments scanned so far (including the invisible argument,
1700 if any, which holds the structure-value-address).
1701 Thus NARGREGS or more means all following args should go on the stack. */
1703 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1707 /* Nonzero if a prototype is available for the function. */
1709 /* The number of an odd floating-point register, that should be used
1710 for the next argument of type float. */
1711 int free_single_fp_reg;
1712 /* Whether we're processing an outgoing function call. */
1714 /* The number of general-purpose registers that should have been
1715 used to pass partial arguments, that are passed totally on the
1716 stack. On SHcompact, a call trampoline will pop them off the
1717 stack before calling the actual function, and, if the called
1718 function is implemented in SHcompact mode, the incoming arguments
1719 decoder will push such arguments back onto the stack. For
1720 incoming arguments, STACK_REGS also takes into account other
1721 arguments passed by reference, that the decoder will also push
1724 /* The number of general-purpose registers that should have been
1725 used to pass arguments, if the arguments didn't have to be passed
1728 /* Set by SHCOMPACT_BYREF if the current argument is to be passed by
1732 /* call_cookie is a bitmask used by call expanders, as well as
1733 function prologue and epilogues, to allow SHcompact to comply
1734 with the SH5 32-bit ABI, that requires 64-bit registers to be
1735 used even though only the lower 32-bit half is visible in
1736 SHcompact mode. The strategy is to call SHmedia trampolines.
1738 The alternatives for each of the argument-passing registers are
1739 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1740 contents from the address in it; (d) add 8 to it, storing the
1741 result in the next register, then (c); (e) copy it from some
1742 floating-point register,
1744 Regarding copies from floating-point registers, r2 may only be
1745 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1746 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1747 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1748 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1751 The bit mask is structured as follows:
1753 - 1 bit to tell whether to set up a return trampoline.
1755 - 3 bits to count the number consecutive registers to pop off the
1758 - 4 bits for each of r9, r8, r7 and r6.
1760 - 3 bits for each of r5, r4, r3 and r2.
1762 - 3 bits set to 0 (the most significant ones)
1765 1098 7654 3210 9876 5432 1098 7654 3210
1766 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1767 2223 3344 4555 6666 7777 8888 9999 SSS-
1769 - If F is set, the register must be copied from an FP register,
1770 whose number is encoded in the remaining bits.
1772 - Else, if L is set, the register must be loaded from the address
1773 contained in it. If the P bit is *not* set, the address of the
1774 following dword should be computed first, and stored in the
1777 - Else, if P is set, the register alone should be popped off the
1780 - After all this processing, the number of registers represented
1781 in SSS will be popped off the stack. This is an optimization
1782 for pushing/popping consecutive registers, typically used for
1783 varargs and large arguments partially passed in registers.
1785 - If T is set, a return trampoline will be set up for 64-bit
1786 return values to be split into 2 32-bit registers. */
1787 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1788 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1789 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1790 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1791 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1792 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1793 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1794 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1795 #define CALL_COOKIE_INT_REG(REG, VAL) \
1796 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1797 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1798 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1802 #define CUMULATIVE_ARGS struct sh_args
1804 #define GET_SH_ARG_CLASS(MODE) \
1805 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1807 /* There's no mention of complex float types in the SH5 ABI, so we
1808 should presumably handle them as aggregate types. */ \
1809 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1811 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1812 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1813 ? SH_ARG_FLOAT : SH_ARG_INT)
1815 #define ROUND_ADVANCE(SIZE) \
1816 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1818 /* Round a register number up to a proper boundary for an arg of mode
1821 The SH doesn't care about double alignment, so we only
1822 round doubles to even regs when asked to explicitly. */
1824 #define ROUND_REG(CUM, MODE) \
1825 (((TARGET_ALIGN_DOUBLE \
1826 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1827 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1828 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1829 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1830 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1831 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1833 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1834 for a call to a function whose data type is FNTYPE.
1835 For a library call, FNTYPE is 0.
1837 On SH, the offset always starts at 0: the first parm reg is always
1838 the same reg for a given argument class.
1840 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1842 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1844 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1845 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
1847 = (TARGET_HITACHI && FNTYPE \
1848 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1849 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
1850 (CUM).arg_count[(int) SH_ARG_INT] \
1851 = (TARGET_SH5 && (FNTYPE) \
1852 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1853 (CUM).free_single_fp_reg = 0; \
1854 (CUM).outgoing = 1; \
1855 (CUM).stack_regs = 0; \
1856 (CUM).byref_regs = 0; \
1859 = (CALL_COOKIE_RET_TRAMP \
1860 (TARGET_SHCOMPACT && (FNTYPE) \
1861 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
1862 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
1863 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
1864 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
1865 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
1867 == FIRST_RET_REG))); \
1870 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1872 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0); \
1874 = (CALL_COOKIE_RET_TRAMP \
1875 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
1876 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
1879 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1881 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0); \
1882 (CUM).outgoing = 0; \
1885 /* Update the data in CUM to advance over an argument
1886 of mode MODE and data type TYPE.
1887 (TYPE is null for libcalls where that information may not be
1890 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1891 if ((CUM).force_mem) \
1892 (CUM).force_mem = 0; \
1893 else if (TARGET_SH5) \
1895 tree TYPE_ = ((CUM).byref && (TYPE) \
1896 ? TREE_TYPE (TYPE) \
1898 enum machine_mode MODE_ = ((CUM).byref && (TYPE) \
1899 ? TYPE_MODE (TYPE_) \
1901 int dwords = (((CUM).byref \
1903 : (MODE_) == BLKmode \
1904 ? int_size_in_bytes (TYPE_) \
1905 : GET_MODE_SIZE (MODE_)) + 7) / 8; \
1906 int numregs = MIN (dwords, NPARM_REGS (SImode) \
1907 - (CUM).arg_count[(int) SH_ARG_INT]); \
1911 (CUM).arg_count[(int) SH_ARG_INT] += numregs; \
1912 if (TARGET_SHCOMPACT \
1913 && SHCOMPACT_FORCE_ON_STACK (MODE_, TYPE_)) \
1916 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1918 /* N.B. We want this also for outgoing. */\
1919 (CUM).stack_regs += numregs; \
1921 else if ((CUM).byref) \
1923 if (! (CUM).outgoing) \
1924 (CUM).stack_regs += numregs; \
1925 (CUM).byref_regs += numregs; \
1929 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1931 while (--numregs); \
1933 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1936 else if (dwords > numregs) \
1938 int pushregs = numregs; \
1940 if (TARGET_SHCOMPACT) \
1941 (CUM).stack_regs += numregs; \
1942 while (pushregs < NPARM_REGS (SImode) - 1 \
1943 && (CALL_COOKIE_INT_REG_GET \
1944 ((CUM).call_cookie, \
1945 NPARM_REGS (SImode) - pushregs) \
1949 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) \
1953 if (numregs == NPARM_REGS (SImode)) \
1955 |= CALL_COOKIE_INT_REG (0, 1) \
1956 | CALL_COOKIE_STACKSEQ (numregs - 1); \
1959 |= CALL_COOKIE_STACKSEQ (numregs); \
1962 if (GET_SH_ARG_CLASS (MODE_) == SH_ARG_FLOAT \
1963 && ((NAMED) || ! (CUM).prototype_p)) \
1965 if ((MODE_) == SFmode && (CUM).free_single_fp_reg) \
1966 (CUM).free_single_fp_reg = 0; \
1967 else if ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1968 < NPARM_REGS (SFmode)) \
1971 = MIN ((GET_MODE_SIZE (MODE_) + 7) / 8 * 2, \
1972 NPARM_REGS (SFmode) \
1973 - (CUM).arg_count[(int) SH_ARG_FLOAT]); \
1975 (CUM).arg_count[(int) SH_ARG_FLOAT] += numfpregs; \
1977 if (TARGET_SHCOMPACT && ! (CUM).prototype_p) \
1979 if ((CUM).outgoing && numregs > 0) \
1983 |= (CALL_COOKIE_INT_REG \
1984 ((CUM).arg_count[(int) SH_ARG_INT] \
1985 - numregs + ((numfpregs - 2) / 2), \
1986 4 + ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1987 - numfpregs) / 2)); \
1989 while (numfpregs -= 2); \
1991 else if ((MODE_) == SFmode && (NAMED) \
1992 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1993 < NPARM_REGS (SFmode))) \
1994 (CUM).free_single_fp_reg \
1995 = FIRST_FP_PARM_REG - numfpregs \
1996 + (CUM).arg_count[(int) SH_ARG_FLOAT] + 1; \
2000 else if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \
2001 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
2002 = (ROUND_REG ((CUM), (MODE)) \
2003 + ((MODE) == BLKmode \
2004 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
2005 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
2007 /* Return boolean indicating arg of mode MODE will be passed in a reg.
2008 This macro is only used in this file. */
2010 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
2012 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
2013 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
2014 && ! (CUM).force_mem \
2016 ? ((MODE) == BLKmode \
2017 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2018 + int_size_in_bytes (TYPE)) \
2019 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2020 : ((ROUND_REG((CUM), (MODE)) \
2021 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2022 <= NPARM_REGS (MODE))) \
2023 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
2025 /* By accident we got stuck with passing SCmode on SH4 little endian
2026 in two registers that are nominally successive - which is different from
2027 two single SFmode values, where we take endianness translation into
2028 account. That does not work at all if an odd number of registers is
2029 already in use, so that got fixed, but library functions are still more
2030 likely to use complex numbers without mixing them with SFmode arguments
2031 (which in C would have to be structures), so for the sake of ABI
2032 compatibility the way SCmode values are passed when an even number of
2033 FP registers is in use remains different from a pair of SFmode values for
2036 foo (double); a: fr5,fr4
2037 foo (float a, float b); a: fr5 b: fr4
2038 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2039 this should be the other way round...
2040 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2041 #define FUNCTION_ARG_SCmode_WART 1
2043 /* Define where to put the arguments to a function.
2044 Value is zero to push the argument on the stack,
2045 or a hard register in which to store the argument.
2047 MODE is the argument's machine mode.
2048 TYPE is the data type of the argument (as a tree).
2049 This is null for libcalls where that information may
2051 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2052 the preceding args and about the function being called.
2053 NAMED is nonzero if this argument is a named parameter
2054 (otherwise it is an extra parameter matching an ellipsis).
2056 On SH the first args are normally in registers
2057 and the rest are pushed. Any arg that starts within the first
2058 NPARM_REGS words is at least partially passed in a register unless
2059 its data type forbids. */
2061 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2063 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2064 && ((NAMED) || !TARGET_HITACHI)) \
2065 ? (((MODE) == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN \
2066 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG ((CUM), (MODE)) & 1)))\
2067 ? (gen_rtx_PARALLEL \
2071 (gen_rtx_EXPR_LIST \
2073 gen_rtx_REG (SFmode, \
2074 BASE_ARG_REG (MODE) \
2075 + (ROUND_REG ((CUM), (MODE)) ^ 1)), \
2077 (gen_rtx_EXPR_LIST \
2079 gen_rtx_REG (SFmode, \
2080 BASE_ARG_REG (MODE) \
2081 + ((ROUND_REG ((CUM), (MODE)) + 1) ^ 1)), \
2083 : gen_rtx_REG ((MODE), \
2084 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
2085 ^ ((MODE) == SFmode && TARGET_SH4 \
2086 && TARGET_LITTLE_ENDIAN != 0)))) \
2088 ? ((MODE) == VOIDmode && TARGET_SHCOMPACT \
2089 ? GEN_INT ((CUM).call_cookie) \
2090 /* The following test assumes unnamed arguments are promoted to \
2092 : (MODE) == SFmode && (CUM).free_single_fp_reg \
2093 ? SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), (CUM).free_single_fp_reg) \
2094 : (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
2095 && ((NAMED) || ! (CUM).prototype_p) \
2096 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode)) \
2097 ? ((! (CUM).prototype_p && TARGET_SHMEDIA) \
2098 ? SH5_PROTOTYPELESS_FLOAT_ARG ((CUM), (MODE)) \
2099 : SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), \
2101 + (CUM).arg_count[(int) SH_ARG_FLOAT])) \
2102 : ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2103 && (! TARGET_SHCOMPACT \
2104 || (! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
2105 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
2106 (TYPE), (NAMED))))) \
2107 ? gen_rtx_REG ((MODE), (FIRST_PARM_REG \
2108 + (CUM).arg_count[(int) SH_ARG_INT])) \
2112 /* Whether an argument must be passed by reference. On SHcompact, we
2113 pretend arguments wider than 32-bits that would have been passed in
2114 registers are passed by reference, so that an SHmedia trampoline
2115 loads them into the full 64-bits registers. */
2116 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM,MODE,TYPE,NAMED) \
2117 (MUST_PASS_IN_STACK ((MODE), (TYPE)) \
2118 || SHCOMPACT_BYREF ((CUM), (MODE), (TYPE), (NAMED)))
2120 #define SHCOMPACT_BYREF(CUM, MODE, TYPE, NAMED) \
2122 = (TARGET_SHCOMPACT \
2123 && (CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2124 && (! (NAMED) || GET_SH_ARG_CLASS (MODE) == SH_ARG_INT \
2125 || (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
2126 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
2127 >= NPARM_REGS (SFmode)))) \
2128 && ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2129 : GET_MODE_SIZE (MODE)) > 4 \
2130 && ! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
2131 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
2133 ? ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2134 : GET_MODE_SIZE (MODE)) \
2137 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2138 register in SHcompact mode, it must be padded in the most
2139 significant end. This means that passing it by reference wouldn't
2140 pad properly on a big-endian machine. In this particular case, we
2141 pass this argument on the stack, in a way that the call trampoline
2142 will load its value into the appropriate register. */
2143 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2144 ((MODE) == BLKmode \
2145 && TARGET_SHCOMPACT \
2146 && ! TARGET_LITTLE_ENDIAN \
2147 && int_size_in_bytes (TYPE) > 4 \
2148 && int_size_in_bytes (TYPE) < 8)
2150 /* Minimum alignment for an argument to be passed by callee-copy
2151 reference. We need such arguments to be aligned to 8 byte
2152 boundaries, because they'll be loaded using quad loads. */
2153 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2155 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
2157 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
2158 : GET_MODE_ALIGNMENT (MODE)) \
2159 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
2161 /* The SH5 ABI requires floating-point arguments to be passed to
2162 functions without a prototype in both an FP register and a regular
2163 register or the stack. When passing the argument in both FP and
2164 general-purpose registers, list the FP register first. */
2165 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2171 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2172 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2173 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2178 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2179 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2180 + (CUM).arg_count[(int) SH_ARG_INT]) \
2181 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2182 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2185 /* The SH5 ABI requires regular registers or stack slots to be
2186 reserved for floating-point arguments. Registers are taken care of
2187 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2188 Unfortunately, there's no way to just reserve a stack slot, so
2189 we'll end up needlessly storing a copy of the argument in the
2190 stack. For incoming arguments, however, the PARALLEL will be
2191 optimized to the register-only form, and the value in the stack
2192 slot won't be used at all. */
2193 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2194 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2195 ? gen_rtx_REG ((MODE), (REG)) \
2196 : gen_rtx_PARALLEL ((MODE), \
2199 (VOIDmode, NULL_RTX, \
2202 (VOIDmode, gen_rtx_REG ((MODE), \
2206 #define STRICT_ARGUMENT_NAMING TARGET_SH5
2208 #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI && ! TARGET_SH5)
2210 /* For an arg passed partly in registers and partly in memory,
2211 this is the number of registers used.
2212 For args passed entirely in registers or entirely in memory, zero.
2214 We sometimes split args. */
2216 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2218 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2220 && (ROUND_REG ((CUM), (MODE)) \
2221 + ((MODE) != BLKmode \
2222 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
2223 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
2224 > NPARM_REGS (MODE))) \
2225 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
2226 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
2227 && ! TARGET_SHCOMPACT) \
2228 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
2231 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2233 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2234 || (MODE) == DCmode) \
2235 && ((CUM).arg_count[(int) SH_ARG_INT] \
2236 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2238 /* Perform any needed actions needed for a function that is receiving a
2239 variable number of arguments. */
2241 /* We actually emit the code in sh_expand_prologue. We used to use
2242 a static variable to flag that we need to emit this code, but that
2243 doesn't when inlining, when functions are deferred and then emitted
2244 later. Fortunately, we already have two flags that are part of struct
2245 function that tell if a function uses varargs or stdarg. */
2246 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) do \
2247 if (! current_function_stdarg) \
2251 /* Define the `__builtin_va_list' type for the ABI. */
2252 #define BUILD_VA_LIST_TYPE(VALIST) \
2253 (VALIST) = sh_build_va_list ()
2255 /* Implement `va_start' for varargs and stdarg. */
2256 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2257 sh_va_start (valist, nextarg)
2259 /* Implement `va_arg'. */
2260 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2261 sh_va_arg (valist, type)
2263 /* Call the function profiler with a given profile label.
2264 We use two .aligns, so as to make sure that both the .long is aligned
2265 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2266 from the trapa instruction. */
2268 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2270 fprintf((STREAM), "\t.align\t2\n"); \
2271 fprintf((STREAM), "\ttrapa\t#33\n"); \
2272 fprintf((STREAM), "\t.align\t2\n"); \
2273 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2276 /* Define this macro if the code for function profiling should come
2277 before the function prologue. Normally, the profiling code comes
2280 #define PROFILE_BEFORE_PROLOGUE
2282 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2283 the stack pointer does not matter. The value is tested only in
2284 functions that have frame pointers.
2285 No definition is equivalent to always zero. */
2287 #define EXIT_IGNORE_STACK 1
2290 On the SH, the trampoline looks like
2291 2 0002 D202 mov.l l2,r2
2292 1 0000 D301 mov.l l1,r3
2295 5 0008 00000000 l1: .long area
2296 6 000c 00000000 l2: .long function */
2298 /* Length in units of the trampoline for entering a nested function. */
2299 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2301 /* Alignment required for a trampoline in bits . */
2302 #define TRAMPOLINE_ALIGNMENT \
2303 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2304 : TARGET_SHMEDIA ? 256 : 64)
2306 /* Emit RTL insns to initialize the variable parts of a trampoline.
2307 FNADDR is an RTX for the address of the function's pure code.
2308 CXT is an RTX for the static chain value for the function. */
2310 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2311 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2313 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2315 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2317 if (TARGET_SHMEDIA) \
2318 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), GEN_INT (1), \
2319 gen_reg_rtx (Pmode), 0, \
2323 /* A C expression whose value is RTL representing the value of the return
2324 address for the frame COUNT steps up from the current frame.
2325 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2326 can ignore COUNT. */
2328 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2329 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2331 /* A C expression whose value is RTL representing the location of the
2332 incoming return address at the beginning of any function, before the
2333 prologue. This RTL is either a REG, indicating that the return
2334 value is saved in REG, or a MEM representing a location in
2336 #define INCOMING_RETURN_ADDR_RTX \
2337 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2339 /* Generate necessary RTL for __builtin_saveregs(). */
2340 #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
2342 /* Addressing modes, and classification of registers for them. */
2343 #define HAVE_POST_INCREMENT TARGET_SH1
2344 #define HAVE_PRE_DECREMENT TARGET_SH1
2346 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2348 #define USE_LOAD_PRE_DECREMENT(mode) 0
2349 #define USE_STORE_POST_INCREMENT(mode) 0
2350 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2353 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2354 < (TARGET_SMALLCODE ? 2 : \
2355 ((ALIGN >= 32) ? 16 : 2)))
2357 /* Macros to check register numbers against specific register classes. */
2359 /* These assume that REGNO is a hard or pseudo reg number.
2360 They give nonzero only if REGNO is a hard reg of the suitable class
2361 or a pseudo reg currently allocated to a suitable hard reg.
2362 Since they use reg_renumber, they are safe only once reg_renumber
2363 has been allocated, which happens in local-alloc.c. */
2365 #define REGNO_OK_FOR_BASE_P(REGNO) \
2366 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2367 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2368 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2370 ? (GENERAL_REGISTER_P (REGNO) \
2371 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2372 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2374 /* Maximum number of registers that can appear in a valid memory
2377 #define MAX_REGS_PER_ADDRESS 2
2379 /* Recognize any constant value that is a valid address. */
2381 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2383 /* Nonzero if the constant value X is a legitimate general operand. */
2385 #define LEGITIMATE_CONSTANT_P(X) \
2387 ? ((GET_MODE (X) != DFmode \
2388 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2389 || (X) == CONST0_RTX (GET_MODE (X)) \
2390 || ! TARGET_SHMEDIA_FPU \
2391 || TARGET_SHMEDIA64) \
2392 : (GET_CODE (X) != CONST_DOUBLE \
2393 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2394 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2396 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2397 and check its validity for a certain class.
2398 We have two alternate definitions for each of them.
2399 The usual definition accepts all pseudo regs; the other rejects
2400 them unless they have been allocated suitable hard regs.
2401 The symbol REG_OK_STRICT causes the latter definition to be used. */
2403 #ifndef REG_OK_STRICT
2405 /* Nonzero if X is a hard reg that can be used as a base reg
2406 or if it is a pseudo reg. */
2407 #define REG_OK_FOR_BASE_P(X) \
2408 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2410 /* Nonzero if X is a hard reg that can be used as an index
2411 or if it is a pseudo reg. */
2412 #define REG_OK_FOR_INDEX_P(X) \
2413 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2414 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2416 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2417 or if X is a pseudo reg. */
2418 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2419 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2420 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2424 /* Nonzero if X is a hard reg that can be used as a base reg. */
2425 #define REG_OK_FOR_BASE_P(X) \
2426 REGNO_OK_FOR_BASE_P (REGNO (X))
2428 /* Nonzero if X is a hard reg that can be used as an index. */
2429 #define REG_OK_FOR_INDEX_P(X) \
2430 REGNO_OK_FOR_INDEX_P (REGNO (X))
2432 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2433 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2434 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2438 /* The 'Q' constraint is a pc relative load operand. */
2439 #define EXTRA_CONSTRAINT_Q(OP) \
2440 (GET_CODE (OP) == MEM \
2441 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2442 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2443 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2444 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2445 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2447 /* Extra address constraints. */
2448 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2450 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2451 operand is not SCRATCH (i.e. REG) then R0 is probably being
2452 used, hence mova is being used, hence do not select this pattern */
2453 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2454 #define EXTRA_CONSTRAINT_B(OP, STR) \
2455 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2458 /* The `C16' constraint is a 16-bit constant, literal or symbolic. */
2459 #define EXTRA_CONSTRAINT_C16(OP) \
2460 (GET_CODE (OP) == CONST \
2461 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2462 && GET_MODE (XEXP ((OP), 0)) == DImode \
2463 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2464 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2465 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2466 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2467 && (MOVI_SHORI_BASE_OPERAND_P \
2468 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2469 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2472 /* Check whether OP is a datalabel unspec. */
2473 #define DATALABEL_REF_NO_CONST_P(OP) \
2474 (GET_CODE (OP) == UNSPEC \
2475 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2476 && XVECLEN ((OP), 0) == 1 \
2477 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2478 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2480 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2482 #define DATALABEL_REF_P(OP) \
2483 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2484 || DATALABEL_REF_NO_CONST_P (OP))
2486 #define GOT_ENTRY_P(OP) \
2487 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2488 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2490 #define GOTPLT_ENTRY_P(OP) \
2491 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2492 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2494 #define UNSPEC_GOTOFF_P(OP) \
2495 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2497 #define GOTOFF_P(OP) \
2498 (GET_CODE (OP) == CONST \
2499 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2500 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2501 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2502 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2504 #define PIC_ADDR_P(OP) \
2505 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2506 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2508 #define PIC_OFFSET_P(OP) \
2510 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2511 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2513 #define PIC_DIRECT_ADDR_P(OP) \
2514 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2516 #define NON_PIC_REFERENCE_P(OP) \
2517 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2518 || DATALABEL_REF_P (OP) \
2519 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2520 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2521 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2522 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2524 #define PIC_REFERENCE_P(OP) \
2525 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2526 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2528 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2530 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2531 || PIC_OFFSET_P (OP)) \
2532 : NON_PIC_REFERENCE_P (OP))
2534 /* The `Csy' constraint is a label or a symbol. */
2535 #define EXTRA_CONSTRAINT_Csy(OP) \
2536 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2538 /* A zero in any shape or form. */
2539 #define EXTRA_CONSTRAINT_Z(OP) \
2540 ((OP) == CONST0_RTX (GET_MODE (OP)))
2542 /* Any vector constant we can handle. */
2543 #define EXTRA_CONSTRAINT_W(OP) \
2544 (GET_CODE (OP) == CONST_VECTOR \
2545 && (sh_rep_vec ((OP), VOIDmode) \
2546 || (HOST_BITS_PER_WIDE_INT >= 64 \
2547 ? sh_const_vec ((OP), VOIDmode) \
2548 : sh_1el_vec ((OP), VOIDmode))))
2550 /* A non-explicit constant that can be loaded directly into a general purpose
2551 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2552 #define EXTRA_CONSTRAINT_Cpg(OP) \
2554 && GET_CODE (OP) != CONST_INT \
2555 && GET_CODE (OP) != CONST_DOUBLE \
2557 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2558 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2559 && GET_CODE (OP) != LABEL_REF)))
2560 #define EXTRA_CONSTRAINT_C(OP, STR) \
2561 ((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
2562 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2563 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2566 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2567 #define EXTRA_CONSTRAINT_Sr0(OP) \
2568 (memory_operand((OP), GET_MODE (OP)) \
2569 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2570 #define EXTRA_CONSTRAINT_S(OP, STR) \
2571 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2574 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2575 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2576 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2577 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2578 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2579 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2580 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2581 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2584 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2585 that is a valid memory address for an instruction.
2586 The MODE argument is the machine mode for the MEM expression
2587 that wants to use this address. */
2589 #define MODE_DISP_OK_4(X,MODE) \
2590 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2591 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2593 #define MODE_DISP_OK_8(X,MODE) \
2594 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2595 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2597 #define BASE_REGISTER_RTX_P(X) \
2598 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2599 || (GET_CODE (X) == SUBREG \
2600 && GET_CODE (SUBREG_REG (X)) == REG \
2601 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2603 /* Since this must be r0, which is a single register class, we must check
2604 SUBREGs more carefully, to be sure that we don't accept one that extends
2605 outside the class. */
2606 #define INDEX_REGISTER_RTX_P(X) \
2607 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2608 || (GET_CODE (X) == SUBREG \
2609 && GET_CODE (SUBREG_REG (X)) == REG \
2610 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2612 /* Jump to LABEL if X is a valid address RTX. This must also take
2613 REG_OK_STRICT into account when deciding about valid registers, but it uses
2614 the above macros so we are in luck.
2622 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2623 into the FRx registers. We implement this by setting the maximum offset
2624 to zero when the value is SFmode. This also restricts loading of SFmode
2625 values into the integer registers, but that can't be helped. */
2627 /* The SH allows a displacement in a QI or HI amode, but only when the
2628 other operand is R0. GCC doesn't handle this very well, so we forgo
2631 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2632 DI can be any number 0..60. */
2634 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2636 if (GET_CODE (OP) == CONST_INT) \
2638 if (TARGET_SHMEDIA) \
2640 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2641 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2642 && INTVAL (OP) >= -512 * MODE_SIZE \
2643 && INTVAL (OP) < 512 * MODE_SIZE) \
2648 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2649 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2653 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2655 if (BASE_REGISTER_RTX_P (X)) \
2657 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2658 && ! TARGET_SHMEDIA \
2659 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2661 else if (GET_CODE (X) == PLUS \
2662 && ((MODE) != PSImode || reload_completed)) \
2664 rtx xop0 = XEXP ((X), 0); \
2665 rtx xop1 = XEXP ((X), 1); \
2666 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2667 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2668 if (GET_MODE_SIZE (MODE) <= 4 \
2669 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2670 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
2672 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2674 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2680 /* Try machine-dependent ways of modifying an illegitimate address
2681 to be legitimate. If we find one, return the new, valid address.
2682 This macro is used in only one place: `memory_address' in explow.c.
2684 OLDX is the address as it was before break_out_memory_refs was called.
2685 In some cases it is useful to look at this to decide what needs to be done.
2687 MODE and WIN are passed so that this macro can use
2688 GO_IF_LEGITIMATE_ADDRESS.
2690 It is always safe for this macro to do nothing. It exists to recognize
2691 opportunities to optimize the output.
2693 For the SH, if X is almost suitable for indexing, but the offset is
2694 out of range, convert it into a normal form so that cse has a chance
2695 of reducing the number of address registers used. */
2697 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2700 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2701 if (GET_CODE (X) == PLUS \
2702 && (GET_MODE_SIZE (MODE) == 4 \
2703 || GET_MODE_SIZE (MODE) == 8) \
2704 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2705 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2706 && ! TARGET_SHMEDIA \
2707 && ! (TARGET_SH4 && (MODE) == DFmode) \
2708 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2710 rtx index_rtx = XEXP ((X), 1); \
2711 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2714 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2715 /* On rare occasions, we might get an unaligned pointer \
2716 that is indexed in a way to give an aligned address. \
2717 Therefore, keep the lower two bits in offset_base. */ \
2718 /* Instead of offset_base 128..131 use 124..127, so that \
2719 simple add suffices. */ \
2722 offset_base = ((offset + 4) & ~60) - 4; \
2725 offset_base = offset & ~60; \
2726 /* Sometimes the normal form does not suit DImode. We \
2727 could avoid that by using smaller ranges, but that \
2728 would give less optimized code when SImode is \
2730 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2732 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2733 GEN_INT (offset_base), NULL_RTX, 0, \
2736 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2742 /* A C compound statement that attempts to replace X, which is an address
2743 that needs reloading, with a valid memory address for an operand of
2744 mode MODE. WIN is a C statement label elsewhere in the code.
2746 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2747 of the address. That will allow inheritance of the address reloads. */
2749 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2751 if (GET_CODE (X) == PLUS \
2752 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2753 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2754 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2755 && ! TARGET_SHMEDIA \
2756 && ! (TARGET_SH4 && (MODE) == DFmode) \
2757 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2759 rtx index_rtx = XEXP (X, 1); \
2760 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2763 if (TARGET_SH2E && MODE == SFmode) \
2766 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2767 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2771 /* Instead of offset_base 128..131 use 124..127, so that \
2772 simple add suffices. */ \
2775 offset_base = ((offset + 4) & ~60) - 4; \
2778 offset_base = offset & ~60; \
2779 /* Sometimes the normal form does not suit DImode. We \
2780 could avoid that by using smaller ranges, but that \
2781 would give less optimized code when SImode is \
2783 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2785 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2786 GEN_INT (offset_base)); \
2787 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
2788 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2789 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2794 /* We must re-recognize what we created before. */ \
2795 else if (GET_CODE (X) == PLUS \
2796 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2797 && GET_CODE (XEXP (X, 0)) == PLUS \
2798 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2799 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2800 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2801 && ! TARGET_SHMEDIA \
2802 && ! (TARGET_SH2E && MODE == SFmode)) \
2804 /* Because this address is so complex, we know it must have \
2805 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2806 it is already unshared, and needs no further unsharing. */ \
2807 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2808 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2813 /* Go to LABEL if ADDR (a legitimate address expression)
2814 has an effect that depends on the machine mode it is used for.
2816 ??? Strictly speaking, we should also include all indexed addressing,
2817 because the index scale factor is the length of the operand.
2818 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2819 high if we did that. So we rely on reload to fix things up. */
2821 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2823 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2827 /* Specify the machine mode that this machine uses
2828 for the index in the tablejump instruction. */
2829 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2831 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2832 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2833 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2834 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2835 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2836 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2839 /* Define as C expression which evaluates to nonzero if the tablejump
2840 instruction expects the table to contain offsets from the address of the
2842 Do not define this if the table should contain absolute addresses. */
2843 #define CASE_VECTOR_PC_RELATIVE 1
2845 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2846 #define FLOAT_TYPE_SIZE 32
2848 /* Since the SH2e has only `float' support, it is desirable to make all
2849 floating point types equivalent to `float'. */
2850 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4) ? 32 : 64)
2852 /* 'char' is signed by default. */
2853 #define DEFAULT_SIGNED_CHAR 1
2855 /* The type of size_t unsigned int. */
2856 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2859 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2861 #define WCHAR_TYPE "short unsigned int"
2862 #define WCHAR_TYPE_SIZE 16
2864 #define SH_ELF_WCHAR_TYPE "long int"
2866 /* Don't cse the address of the function being compiled. */
2867 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
2869 /* Max number of bytes we can move from memory to memory
2870 in one reasonably fast instruction. */
2871 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2873 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2874 MOVE_MAX is not a compile-time constant. */
2875 #define MAX_MOVE_MAX 8
2877 /* Max number of bytes we want move_by_pieces to be able to copy
2879 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2881 /* Define if operations between registers always perform the operation
2882 on the full register even if a narrower mode is specified. */
2883 #define WORD_REGISTER_OPERATIONS
2885 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2886 will either zero-extend or sign-extend. The value of this macro should
2887 be the code that says which one of the two operations is implicitly
2888 done, NIL if none. */
2889 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2890 /* FP registers can load SImode values, but don't implicitly sign-extend
2892 #define LOAD_EXTEND_OP(MODE) \
2893 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2894 : (MODE) != SImode ? SIGN_EXTEND : NIL)
2896 /* Define if loading short immediate values into registers sign extends. */
2897 #define SHORT_IMMEDIATES_SIGN_EXTEND
2899 /* Nonzero if access to memory by bytes is no faster than for words. */
2900 #define SLOW_BYTE_ACCESS 1
2902 /* Immediate shift counts are truncated by the output routines (or was it
2903 the assembler?). Shift counts in a register are truncated by SH. Note
2904 that the native compiler puts too large (> 32) immediate shift counts
2905 into a register and shifts by the register, letting the SH decide what
2906 to do instead of doing that itself. */
2907 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2908 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2909 expects - the sign bit is significant - so it appears that we need to
2910 leave this zero for correct SH3 code. */
2911 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
2913 /* All integers have the same format so truncation is easy. */
2914 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2916 /* Define this if addresses of constant functions
2917 shouldn't be put through pseudo regs where they can be cse'd.
2918 Desirable on machines where ordinary constants are expensive
2919 but a CALL with constant address is cheap. */
2920 /*#define NO_FUNCTION_CSE 1*/
2922 /* Chars and shorts should be passed as ints. */
2923 #define PROMOTE_PROTOTYPES 1
2925 /* The machine modes of pointers and functions. */
2926 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2927 #define FUNCTION_MODE Pmode
2929 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2930 are actually function calls with some special constraints on arguments
2933 These macros tell reorg that the references to arguments and
2934 register clobbers for insns of type sfunc do not appear to happen
2935 until after the millicode call. This allows reorg to put insns
2936 which set the argument registers into the delay slot of the millicode
2937 call -- thus they act more like traditional CALL_INSNs.
2939 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2940 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2943 #define INSN_SETS_ARE_DELAYED(X) \
2944 ((GET_CODE (X) == INSN \
2945 && GET_CODE (PATTERN (X)) != SEQUENCE \
2946 && GET_CODE (PATTERN (X)) != USE \
2947 && GET_CODE (PATTERN (X)) != CLOBBER \
2948 && get_attr_is_sfunc (X)))
2950 #define INSN_REFERENCES_ARE_DELAYED(X) \
2951 ((GET_CODE (X) == INSN \
2952 && GET_CODE (PATTERN (X)) != SEQUENCE \
2953 && GET_CODE (PATTERN (X)) != USE \
2954 && GET_CODE (PATTERN (X)) != CLOBBER \
2955 && get_attr_is_sfunc (X)))
2958 /* Position Independent Code. */
2960 /* We can't directly access anything that contains a symbol,
2961 nor can we indirect via the constant pool. */
2962 #define LEGITIMATE_PIC_OPERAND_P(X) \
2963 ((! nonpic_symbol_mentioned_p (X) \
2964 && (GET_CODE (X) != SYMBOL_REF \
2965 || ! CONSTANT_POOL_ADDRESS_P (X) \
2966 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2967 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2969 #define SYMBOLIC_CONST_P(X) \
2970 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2971 && nonpic_symbol_mentioned_p (X))
2973 /* Compute extra cost of moving data between one register class
2976 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2977 uses this information. Hence, the general register <-> floating point
2978 register information here is not used for SFmode. */
2980 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2981 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2982 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2984 #define REGCLASS_HAS_FP_REG(CLASS) \
2985 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2986 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2988 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2989 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2991 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2992 would be so that people with slow memory systems could generate
2993 different code that does fewer memory accesses. */
2995 /* A C expression for the cost of a branch instruction. A value of 1
2996 is the default; other values are interpreted relative to that.
2997 The SH1 does not have delay slots, hence we get a pipeline stall
2998 at every branch. The SH4 is superscalar, so the single delay slot
2999 is not sufficient to keep both pipelines filled. */
3000 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
3002 /* Assembler output control. */
3004 /* A C string constant describing how to begin a comment in the target
3005 assembler language. The compiler assumes that the comment will end at
3006 the end of the line. */
3007 #define ASM_COMMENT_START "!"
3009 #define ASM_APP_ON ""
3010 #define ASM_APP_OFF ""
3011 #define FILE_ASM_OP "\t.file\n"
3012 #define SET_ASM_OP "\t.set\t"
3014 /* How to change between sections. */
3016 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
3017 #define DATA_SECTION_ASM_OP "\t.data"
3019 #if defined CRT_BEGIN || defined CRT_END
3020 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
3021 # undef TEXT_SECTION_ASM_OP
3022 # if __SHMEDIA__ == 1 && __SH5__ == 32
3023 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
3025 # define TEXT_SECTION_ASM_OP "\t.text"
3030 /* If defined, a C expression whose value is a string containing the
3031 assembler operation to identify the following data as
3032 uninitialized global data. If not defined, and neither
3033 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
3034 uninitialized global data will be output in the data section if
3035 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
3037 #ifndef BSS_SECTION_ASM_OP
3038 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
3041 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
3042 separate, explicit argument. If you define this macro, it is used
3043 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
3044 handling the required alignment of the variable. The alignment is
3045 specified as the number of bits.
3047 Try to use function `asm_output_aligned_bss' defined in file
3048 `varasm.c' when defining this macro. */
3049 #ifndef ASM_OUTPUT_ALIGNED_BSS
3050 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
3051 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
3054 /* Define this so that jump tables go in same section as the current function,
3055 which could be text or it could be a user defined section. */
3056 #define JUMP_TABLES_IN_TEXT_SECTION 1
3058 #undef DO_GLOBAL_CTORS_BODY
3059 #define DO_GLOBAL_CTORS_BODY \
3061 typedef (*pfunc)(); \
3062 extern pfunc __ctors[]; \
3063 extern pfunc __ctors_end[]; \
3065 for (p = __ctors_end; p > __ctors; ) \
3071 #undef DO_GLOBAL_DTORS_BODY
3072 #define DO_GLOBAL_DTORS_BODY \
3074 typedef (*pfunc)(); \
3075 extern pfunc __dtors[]; \
3076 extern pfunc __dtors_end[]; \
3078 for (p = __dtors; p < __dtors_end; p++) \
3084 #define ASM_OUTPUT_REG_PUSH(file, v) \
3085 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));
3087 #define ASM_OUTPUT_REG_POP(file, v) \
3088 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
3090 /* DBX register number for a given compiler register number. */
3091 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
3093 /* svr4.h undefines this macro, yet we really want to use the same numbers
3094 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
3095 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
3096 register exists, so we should return -1 for invalid register numbers. */
3097 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
3099 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
3100 used to use the encodings 245..260, but that doesn't make sense:
3101 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
3102 the FP registers stay the same when switching between compact and media
3103 mode. Hence, we also need to use the same dwarf frame coloumns.
3104 Likewise, we need to support unwind information for SHmedia registers
3105 even in compact code. */
3106 #define SH_DBX_REGISTER_NUMBER(REGNO) \
3107 (IN_RANGE ((REGNO), \
3108 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
3109 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
3110 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
3111 : ((int) (REGNO) >= FIRST_FP_REG \
3113 <= (FIRST_FP_REG + \
3114 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
3115 ? ((unsigned) (REGNO) - FIRST_FP_REG \
3116 + (TARGET_SH5 ? 77 : 25)) \
3117 : XD_REGISTER_P (REGNO) \
3118 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
3119 : TARGET_REGISTER_P (REGNO) \
3120 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
3121 : (REGNO) == PR_REG \
3122 ? (TARGET_SH5 ? 18 : 17) \
3123 : (REGNO) == PR_MEDIA_REG \
3124 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
3125 : (REGNO) == T_REG \
3126 ? (TARGET_SH5 ? 242 : 18) \
3127 : (REGNO) == GBR_REG \
3128 ? (TARGET_SH5 ? 238 : 19) \
3129 : (REGNO) == MACH_REG \
3130 ? (TARGET_SH5 ? 239 : 20) \
3131 : (REGNO) == MACL_REG \
3132 ? (TARGET_SH5 ? 240 : 21) \
3133 : (REGNO) == FPUL_REG \
3134 ? (TARGET_SH5 ? 244 : 23) \
3137 /* This is how to output a reference to a symbol_ref. On SH5,
3138 references to non-code symbols must be preceded by `datalabel'. */
3139 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3142 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3143 fputs ("datalabel ", (FILE)); \
3144 assemble_name ((FILE), XSTR ((SYM), 0)); \
3148 /* This is how to output an assembler line
3149 that says to advance the location counter
3150 to a multiple of 2**LOG bytes. */
3152 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3154 fprintf ((FILE), "\t.align %d\n", (LOG))
3156 /* Globalizing directive for a label. */
3157 #define GLOBAL_ASM_OP "\t.global\t"
3159 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3161 /* Output a relative address table. */
3163 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3164 switch (GET_MODE (BODY)) \
3169 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3173 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3178 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3182 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3187 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3191 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3197 /* Output an absolute table element. */
3199 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3200 if (! optimize || TARGET_BIGTABLE) \
3201 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3203 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3206 /* A C statement to be executed just prior to the output of
3207 assembler code for INSN, to modify the extracted operands so
3208 they will be output differently.
3210 Here the argument OPVEC is the vector containing the operands
3211 extracted from INSN, and NOPERANDS is the number of elements of
3212 the vector which contain meaningful data for this insn.
3213 The contents of this vector are what will be used to convert the insn
3214 template into assembler code, so you can change the assembler output
3215 by changing the contents of the vector. */
3217 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3218 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3220 /* Print operand X (an rtx) in assembler syntax to file FILE.
3221 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3222 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3224 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3226 /* Print a memory address as an operand to reference that memory location. */
3228 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3230 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3231 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3232 || (CHAR) == '$'|| (CHAR) == '\'')
3234 /* Recognize machine-specific patterns that may appear within
3235 constants. Used for PIC-specific UNSPECs. */
3236 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3238 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3240 switch (XINT ((X), 1)) \
3242 case UNSPEC_DATALABEL: \
3243 fputs ("datalabel ", (STREAM)); \
3244 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3247 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3248 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3251 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3252 fputs ("@GOT", (STREAM)); \
3254 case UNSPEC_GOTOFF: \
3255 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3256 fputs ("@GOTOFF", (STREAM)); \
3259 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3260 fputs ("@PLT", (STREAM)); \
3262 case UNSPEC_GOTPLT: \
3263 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3264 fputs ("@GOTPLT", (STREAM)); \
3266 case UNSPEC_DTPOFF: \
3267 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3268 fputs ("@DTPOFF", (STREAM)); \
3270 case UNSPEC_GOTTPOFF: \
3271 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3272 fputs ("@GOTTPOFF", (STREAM)); \
3274 case UNSPEC_TPOFF: \
3275 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3276 fputs ("@TPOFF", (STREAM)); \
3278 case UNSPEC_CALLER: \
3281 /* LPCS stands for Label for PIC Call Site. */ \
3282 ASM_GENERATE_INTERNAL_LABEL \
3283 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3284 assemble_name ((STREAM), name); \
3297 extern struct rtx_def *sh_compare_op0;
3298 extern struct rtx_def *sh_compare_op1;
3300 /* Which processor to schedule for. The elements of the enumeration must
3301 match exactly the cpu attribute in the sh.md file. */
3303 enum processor_type {
3313 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3314 extern enum processor_type sh_cpu;
3316 extern int optimize; /* needed for gen_casesi. */
3318 enum mdep_reorg_phase_e
3320 SH_BEFORE_MDEP_REORG,
3321 SH_INSERT_USES_LABELS,
3322 SH_SHORTEN_BRANCHES0,
3324 SH_SHORTEN_BRANCHES1,
3328 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3330 /* Generate calls to memcpy, memcmp and memset. */
3332 #define TARGET_MEM_FUNCTIONS
3334 /* Handle Renesas compiler's pragmas. */
3335 #define REGISTER_TARGET_PRAGMAS() do { \
3336 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3337 c_register_pragma (0, "trapa", sh_pr_trapa); \
3338 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3341 /* Set when processing a function with pragma interrupt turned on. */
3343 extern int pragma_interrupt;
3345 /* Set when processing a function with interrupt attribute. */
3347 extern int current_function_interrupt;
3349 /* Set to an RTX containing the address of the stack to switch to
3350 for interrupt functions. */
3351 extern struct rtx_def *sp_switch;
3353 extern int rtx_equal_function_value_matters;
3356 /* Instructions with unfilled delay slots take up an
3357 extra two bytes for the nop in the delay slot.
3358 sh-dsp parallel processing insns are four bytes long. */
3360 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3361 (LENGTH) += sh_insn_length_adjustment (X);
3363 /* Define the codes that are matched by predicates in sh.c. */
3364 #define PREDICATE_CODES \
3365 {"and_operand", {SUBREG, REG, CONST_INT}}, \
3366 {"any_register_operand", {SUBREG, REG}}, \
3367 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3368 {"arith_reg_dest", {SUBREG, REG}}, \
3369 {"arith_reg_operand", {SUBREG, REG}}, \
3370 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
3371 {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
3372 {"binary_logical_operator", {AND, IOR, XOR}}, \
3373 {"commutative_float_operator", {PLUS, MULT}}, \
3374 {"equality_comparison_operator", {EQ,NE}}, \
3375 {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
3376 {"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \
3377 {"fp_arith_reg_operand", {SUBREG, REG}}, \
3378 {"fpscr_operand", {REG}}, \
3379 {"fpul_operand", {REG}}, \
3380 {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \
3381 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
3382 {"general_movdst_operand", {SUBREG, REG, MEM}}, \
3383 {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
3384 {"int_gpr_dest", {SUBREG, REG}}, \
3385 {"inqhi_operand", {TRUNCATE}}, \
3386 {"less_comparison_operator", {LT,LE,LTU,LEU}}, \
3387 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
3388 {"mextr_bit_offset", {CONST_INT}}, \
3389 {"noncommutative_float_operator", {MINUS, DIV}}, \
3390 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
3391 {"sh_register_operand", {REG, SUBREG, CONST_INT}}, \
3392 {"target_reg_operand", {SUBREG, REG}}, \
3393 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
3394 {"trunc_hi_operand", {SUBREG, REG, TRUNCATE}}, \
3395 {"register_operand", {SUBREG, REG}}, \
3396 {"sh_const_vec", {CONST_VECTOR}}, \
3397 {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
3398 {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
3399 {"symbol_ref_operand", {SYMBOL_REF}}, \
3400 {"unary_float_operator", {ABS, NEG, SQRT}}, \
3402 #define SPECIAL_MODE_PREDICATES \
3403 "any_register_operand", \
3405 "trunc_hi_operand", \
3406 /* This line intentionally left blank. */
3408 #define any_register_operand register_operand
3410 /* Define this macro if it is advisable to hold scalars in registers
3411 in a wider mode than that declared by the program. In such cases,
3412 the value is constrained to be within the bounds of the declared
3413 type, but kept valid in the wider mode. The signedness of the
3414 extension may differ from that of the type.
3416 Leaving the unsignedp unchanged gives better code than always setting it
3417 to 0. This is despite the fact that we have only signed char and short
3418 load instructions. */
3419 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3420 if (GET_MODE_CLASS (MODE) == MODE_INT \
3421 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3422 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3423 (MODE) = (TARGET_SH1 ? SImode : DImode);
3425 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
3426 extensions applied to char/short functions arguments. Defining
3427 PROMOTE_FUNCTION_RETURN does the same for function returns. */
3429 #define PROMOTE_FUNCTION_ARGS
3430 #define PROMOTE_FUNCTION_RETURN
3432 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3434 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3435 and poping arguments. However, we do have push/pop instructions, and
3436 rather limited offsets (4 bits) in load/store instructions, so it isn't
3437 clear if this would give better code. If implemented, should check for
3438 compatibility problems. */
3440 #define SH_DYNAMIC_SHIFT_COST \
3441 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3444 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3446 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
3448 #define ACTUAL_NORMAL_MODE(ENTITY) \
3449 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3451 #define NORMAL_MODE(ENTITY) \
3452 (sh_cfun_interrupt_handler_p () \
3453 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3454 : ACTUAL_NORMAL_MODE (ENTITY))
3456 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3457 && (REGNO) == FPSCR_REG)
3459 #define MODE_NEEDED(ENTITY, INSN) \
3460 (recog_memoized (INSN) >= 0 \
3461 ? get_attr_fp_mode (INSN) \
3464 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3465 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3467 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3468 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3470 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3471 sh_can_redirect_branch ((INSN), (SEQ))
3473 #define DWARF_FRAME_RETURN_COLUMN \
3474 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3476 #define EH_RETURN_DATA_REGNO(N) \
3477 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3479 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3480 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3482 /* We have to distinguish between code and data, so that we apply
3483 datalabel where and only where appropriate. Use textrel for code. */
3484 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3485 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3486 | ((CODE) ? DW_EH_PE_textrel : flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))
3488 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3489 indirect are handled automatically. */
3490 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3492 if (((ENCODING) & 0x70) == DW_EH_PE_textrel) \
3494 encoding &= ~DW_EH_PE_textrel; \
3495 encoding |= flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr; \
3496 if (GET_CODE (ADDR) != SYMBOL_REF) \
3498 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3503 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3504 /* SH constant pool breaks the devices in crtstuff.c to control section
3505 in where code resides. We have to write it as asm code. */
3506 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3507 asm (SECTION_OP "\n\
3513 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3514 2:\n" TEXT_SECTION_ASM_OP);
3515 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3517 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3518 (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
3519 ? (current_function_is_leaf \
3520 && ! sh_pr_n_sets () \
3521 && ! (TARGET_SHCOMPACT \
3522 && ((current_function_args_info.call_cookie \
3523 & ~ CALL_COOKIE_RET_TRAMP (1)) \
3524 || current_function_has_nonlocal_label)) \
3526 : gen_rtx_MEM (Pmode, TARGET_SH5 \
3527 ? (plus_constant (arg_pointer_rtx, \
3528 TARGET_SHMEDIA64 ? -8 : -4)) \
3529 : frame_pointer_rtx)) \
3532 #endif /* ! GCC_SH_H */
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