1 /* Definitions of target machine for GNU compiler,
3 Copyright (C) 1993, 1994 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com)
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
24 /* Run-time Target Specification. */
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
30 /* Generate SDB debugging information. */
32 #define SDB_DEBUGGING_INFO 1
34 /* Output DBX (stabs) debugging information if doing -gstabs. */
36 #define DBX_DEBUGGING_INFO
38 /* Generate SDB debugging information by default. */
40 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
44 #define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
46 /* Show we can debug even without a frame pointer. */
47 #define CAN_DEBUG_WITHOUT_FP
50 #define CONDITIONAL_REGISTER_USAGE \
51 /* Experimental calling convention with fewer saved registers */ \
54 call_used_regs[8] = 1; \
55 call_used_regs[9] = 1; \
56 call_used_regs[10] = 1; \
57 call_used_regs[11] = 1; \
59 /* Hitachi saves and restores mac registers on call */ \
62 call_used_regs[MACH_REG] = 0; \
63 call_used_regs[MACL_REG] = 0; \
67 /* Run-time compilation parameters selecting different hardware subsets. */
69 extern int target_flags;
70 #define ISIZE_BIT (1<<1)
71 #define FAST_BIT (1<<2)
72 #define MAC_BIT (1<<3)
73 #define RTL_BIT (1<<4)
75 #define DALIGN_BIT (1<<6)
76 #define SH0_BIT (1<<7)
77 #define SH1_BIT (1<<8)
78 #define SH2_BIT (1<<9)
79 #define SH3_BIT (1<<10)
82 #define SPACE_BIT (1<<13)
83 #define BIGTABLE_BIT (1<<14)
84 #define TRYR0_BIT (1<<15)
85 #define NOSAVE_BIT (1<<16)
86 #define SMALLCALL_BIT (1<<17)
87 #define CONSTLEN_2_BIT (1<<20)
88 #define CONSTLEN_3_BIT (1<<21)
89 #define HITACHI_BIT (1<<22)
90 #define PARANOID_BIT (1<<23)
91 #define RETR2_BIT (1<<24)
92 #define CONSTLEN_0_BIT (1<<25)
93 #define BSR_BIT (1<<26)
94 #define SHORTADDR_BIT (1<<27)
95 #define PACKSTRUCT_BIT (1<<28)
97 /* Nonzero if we should generate code using type 0 insns */
98 #define TARGET_SH0 (target_flags & SH0_BIT)
100 /* Nonzero if we should generate code using type 1 insns */
101 #define TARGET_SH1 (target_flags & SH1_BIT)
103 /* Nonzero if we should generate code using type 2 insns */
104 #define TARGET_SH2 (target_flags & SH2_BIT)
106 /* Nonzero if we should generate code using type 3 insns */
107 #define TARGET_SH3 (target_flags & SH3_BIT)
109 /* Nonzero if we should generate faster code rather than smaller code */
110 #define TARGET_FASTCODE (target_flags & FAST_BIT)
112 /* Nonzero if we should generate faster code rather than smaller code */
113 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
115 /* Nonzero if we should dump out instruction size info */
116 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
118 /* Nonzero if we should try to generate mac instructions */
119 #define TARGET_MAC (target_flags & MAC_BIT)
121 /* Nonzero if we should dump the rtl in the assembly file. */
122 #define TARGET_DUMP_RTL (target_flags & RTL_BIT)
124 /* Nonzero if we should dump the rtl somewher else. */
125 #define TARGET_DUMP_R (target_flags & R_BIT)
127 /* Nonzero to align doubles on 64 bit boundaries */
128 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
130 /* Nonzero to use long jump tables */
131 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
133 /* Nonzero if combine dumping wanted */
134 #define TARGET_CDUMP (target_flags & C_BIT)
136 /* Nonzero if trying to use reg+disp for QIs and HIs. This
138 #define TARGET_TRYR0 (target_flags & TRYR0_BIT)
140 /* Nonzero if using no save calling convention */
141 #define TARGET_NOSAVE (target_flags & NOSAVE_BIT)
143 /* Nonzero if using no save calling convention */
144 #define TARGET_SMALLCALL (target_flags & SMALLCALL_BIT)
146 /* Select max size of computed constant code sequences to be 3 insns */
147 #define TARGET_CLEN3 (target_flags & CONSTLEN_3_BIT)
149 /* Select max size of computed constant code sequences to be 0 insns - ie don't do it */
150 #define TARGET_CLEN0 (target_flags & CONSTLEN_0_BIT)
152 /* Nonzero if using Hitachi's calling convention */
153 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
155 #define TARGET_PARANOID (target_flags & PARANOID_BIT)
156 #define TARGET_RETR2 (target_flags & RETR2_BIT)
157 #define TARGET_SHORTADDR (target_flags & SHORTADDR_BIT)
158 #define TARGET_BSR (target_flags & BSR_BIT)
160 /* Nonzero if packing structures as small as they'll go (incompatible with Hitachi's compiler) */
161 #define TARGET_PACKSTRUCT (target_flags & PACKSTRUCT_BIT)
163 #define TARGET_SWITCHES \
164 { {"isize", ( ISIZE_BIT) }, \
165 {"space", ( SPACE_BIT) }, \
166 {"0", ( SH0_BIT) }, \
167 {"1", ( SH1_BIT) }, \
168 {"2", ( SH2_BIT) }, \
169 {"3", ( SH3_BIT) }, \
170 {"ac", ( MAC_BIT) }, \
171 {"dalign", ( DALIGN_BIT) }, \
173 {"r", ( RTL_BIT) }, \
174 {"bigtable", ( BIGTABLE_BIT)}, \
175 {"try-r0", ( TRYR0_BIT)}, \
177 {"nosave", ( NOSAVE_BIT) }, \
178 {"clen3", ( CONSTLEN_3_BIT) }, \
179 {"clen0", ( CONSTLEN_0_BIT) }, \
180 {"smallcall", ( SMALLCALL_BIT) }, \
181 {"hitachi", ( HITACHI_BIT) }, \
182 {"paranoid", ( PARANOID_BIT) }, \
183 {"r2", ( RETR2_BIT) }, \
184 {"shortaddr", ( SHORTADDR_BIT) }, \
185 {"bsr", ( BSR_BIT) }, \
186 {"packstruct",( PACKSTRUCT_BIT) }, \
187 {"", TARGET_DEFAULT} \
190 #define TARGET_DEFAULT (FAST_BIT)
192 /* Macro to define table for command options with values. */
193 #define TARGET_OPTIONS \
194 { { "maxsi-", &max_si}, \
195 { "maxhi-", &max_hi} }
197 #define OVERRIDE_OPTIONS \
207 /* We *MUST* always define optimize since we *HAVE* to run \
208 shorten branches to get correct code. */ \
211 flag_delayed_branch = 1; \
212 /* But never run scheduling before reload, since than can \
213 break global alloc, and generates slower code anyway due \
214 to the pressure on R0. */ \
215 flag_schedule_insns = 0; \
217 max_count_si = atoi (max_si); \
219 max_count_si = 1010; \
221 max_count_hi = atoi (max_hi); \
223 max_count_hi = 500; \
225 flag_no_function_cse = 1; \
229 /* Target machine storage Layout. */
231 /* Define to use software floating point emulator for REAL_ARITHMETIC and
232 decimal <-> binary conversion. */
233 #define REAL_ARITHMETIC
235 /* Define this if most significant bit is lowest numbered
236 in instructions that operate on numbered bit-fields. */
237 #define BITS_BIG_ENDIAN 0
239 /* Define this if most significant byte of a word is the lowest numbered. */
240 #define BYTES_BIG_ENDIAN 1
242 /* Define this if most significant word of a multiword number is the lowest
244 #define WORDS_BIG_ENDIAN 1
246 /* Number of bits in an addressable storage unit */
247 #define BITS_PER_UNIT 8
249 /* Width in bits of a "word", which is the contents of a machine register.
250 Note that this is not necessarily the width of data type `int';
251 if using 16-bit ints on a 68000, this would still be 32.
252 But on a machine with 16-bit registers, this would be 16. */
253 #define BITS_PER_WORD 32
254 #define MAX_BITS_PER_WORD 32
256 /* Width of a word, in units (bytes). */
257 #define UNITS_PER_WORD 4
259 /* Width in bits of a pointer.
260 See also the macro `Pmode' defined below. */
261 #define POINTER_SIZE 32
263 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
264 #define PARM_BOUNDARY 32
266 /* Boundary (in *bits*) on which stack pointer should be aligned. */
267 #define STACK_BOUNDARY 32
269 /* Allocation boundary (in *bits*) for the code of a function. */
270 #define FUNCTION_BOUNDARY 16
272 /* Alignment of field after `int : 0' in a structure. */
273 #define EMPTY_FIELD_BOUNDARY 32
275 /* No data type wants to be aligned rounder than this. */
276 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
278 /* The best alignment to use in cases where we have a choice. */
279 #define FASTEST_ALIGNMENT 32
281 /* Make strings word-aligned so strcpy from constants will be faster. */
282 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
283 ((TREE_CODE (EXP) == STRING_CST \
284 && (ALIGN) < FASTEST_ALIGNMENT) \
285 ? FASTEST_ALIGNMENT : (ALIGN))
287 /* Make arrays of chars word-aligned for the same reasons. */
288 #define DATA_ALIGNMENT(TYPE, ALIGN) \
289 (TREE_CODE (TYPE) == ARRAY_TYPE \
290 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
291 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
293 /* Number of bits which any structure or union's size must be a
294 multiple of. Each structure or union's size is rounded up to a
296 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PACKSTRUCT ? 8 : 32)
298 /* Set this nonzero if move instructions will actually fail to work
299 when given unaligned data. */
300 #define STRICT_ALIGNMENT 1
303 /* Standard register usage. */
305 /* Register allocation for the Hitachi calling convention:
311 r14 frame pointer/call saved
313 ap arg pointer (doesn't really exist, always eliminated)
314 pr subroutine return address
316 mach multiply/accumulate result
320 /* Number of actual hardware registers.
321 The hardware registers are assigned numbers for the compiler
322 from 0 to just below FIRST_PSEUDO_REGISTER.
323 All registers that the compiler knows about must be given numbers,
324 even those that are not normally considered general registers. */
333 #define FIRST_PSEUDO_REGISTER 22
335 /* 1 for registers that have pervasive standard uses
336 and are not available for the register allocator.
338 mach register is fixed 'cause it's only 10 bits wide */
347 #define FIXED_REGISTERS \
356 /* 1 for registers not available across function calls.
357 These must include the FIXED_REGISTERS and also any
358 registers that can be used without being saved.
359 The latter must include the registers where values are returned
360 and the register where structure-value addresses are passed.
361 Aside from that, you can include as many other registers as you like. */
370 #define CALL_USED_REGISTERS \
378 /* Return number of consecutive hard regs needed starting at reg REGNO
379 to hold something of mode MODE.
380 This is ordinarily the length in words of a value of mode MODE
381 but can be less for certain modes in special long registers.
383 On the SH regs are UNITS_PER_WORD bits wide; */
385 #define HARD_REGNO_NREGS(REGNO, MODE) \
386 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
388 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
389 We may keep double values in even registers */
391 extern int hard_regno_mode_ok[];
392 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
393 (hard_regno_mode_ok[REGNO] & (1<<(int)MODE))
395 /* Value is 1 if it is a good idea to tie two pseudo registers
396 when one has mode MODE1 and one has mode MODE2.
397 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
398 for any hard reg, then this must be 0 for correct output. */
400 #define MODES_TIEABLE_P(MODE1, MODE2) \
401 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
403 /* Specify the registers used for certain standard purposes.
404 The values of these macros are register numbers. */
406 /* Define this if the program counter is overloaded on a register. */
407 /* #define PC_REGNUM 15*/
409 /* Register to use for pushing function arguments. */
410 #define STACK_POINTER_REGNUM 15
412 /* Base register for access to local variables of the function. */
413 #define FRAME_POINTER_REGNUM 14
415 /* Value should be nonzero if functions must have frame pointers.
416 Zero means the frame pointer need not be set up (and parms may be accessed
417 via the stack pointer) in functions that seem suitable. */
419 #define FRAME_POINTER_REQUIRED 0
421 /* Definitions for register eliminations.
423 We have two registers that can be eliminated on the m88k. First, the
424 frame pointer register can often be eliminated in favor of the stack
425 pointer register. Secondly, the argument pointer register can always be
426 eliminated; it is replaced with either the stack or frame pointer. */
428 /* This is an array of structures. Each structure initializes one pair
429 of eliminable registers. The "from" register number is given first,
430 followed by "to". Eliminations of the same "from" register are listed
431 in order of preference. */
433 /* This is an array of structures. Each structure initializes one pair
434 of eliminable registers. The "from" register number is given first,
435 followed by "to". Eliminations of the same "from" register are listed
436 in order of preference. */
438 #define ELIMINABLE_REGS \
439 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
440 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
441 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
444 /* Given FROM and TO register numbers, say whether this elimination
446 #define CAN_ELIMINATE(FROM, TO) \
447 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
449 /* Define the offset between two registers, one to be eliminated, and the other
450 its replacement, at the start of a routine. */
452 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
453 OFFSET = initial_elimination_offset (FROM, TO)
455 /* Base register for access to arguments of the function. */
456 #define ARG_POINTER_REGNUM 16
458 /* Register in which the static-chain is passed to a function. */
459 #define STATIC_CHAIN_REGNUM 13
461 /* The register in which a struct value address is passed */
463 #define STRUCT_VALUE_REGNUM 2
465 /* If the structure value address is not passed in a register, define
466 `STRUCT_VALUE' as an expression returning an RTX for the place
467 where the address is passed. If it returns 0, the address is
468 passed as an "invisible" first argument. */
470 /*#define STRUCT_VALUE ((rtx)0)*/
473 /* Don't default to pcc-struct-return, because we have already specified
474 exactly how to return structures in the RETURN_IN_MEMORY macro. */
476 #define DEFAULT_PCC_STRUCT_RETURN 0
479 /* Define the classes of registers for register constraints in the
480 machine description. Also define ranges of constants.
482 One of the classes must always be named ALL_REGS and include all hard regs.
483 If there is more than one class, another class must be named NO_REGS
484 and contain no registers.
486 The name GENERAL_REGS must be the name of a class (or an alias for
487 another name such as ALL_REGS). This is the class of registers
488 that is allowed by "g" or "r" in a register constraint.
489 Also, registers outside this class are allocated only when
490 instructions express preferences for them.
492 The classes must be numbered in nondecreasing order; that is,
493 a larger-numbered class must never be contained completely
494 in a smaller-numbered class.
496 For any two classes, it is very desirable that there be another
497 class that represents their union. */
499 /* The SH has two sorts of general registers, R0 and the rest. R0 can
500 be used as the destination of some of the arithmetic ops. There are
501 also some special purpose registers; the T bit register, the
502 Procedure Return Register and the Multipy Accumulate Registers */
516 #define N_REG_CLASSES (int) LIM_REG_CLASSES
518 /* Give names of register classes as strings for dump file. */
519 #define REG_CLASS_NAMES \
530 /* Define which registers fit in which classes.
531 This is an initializer for a vector of HARD_REG_SET
532 of length N_REG_CLASSES. */
534 #define REG_CLASS_CONTENTS \
536 0x000000, /* NO_REGS */ \
537 0x000001, /* R0_REGS */ \
538 0x020000, /* PR_REGS */ \
539 0x040000, /* T_REGS */ \
540 0x300000, /* MAC_REGS */ \
541 0x01FFFF, /* GENERAL_REGS */ \
542 0x37FFFF /* ALL_REGS */ \
545 /* The same information, inverted:
546 Return the class number of the smallest class containing
547 reg number REGNO. This could be a conditional expression
548 or could index an array. */
550 extern int regno_reg_class[];
551 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
553 /* When defined, the compiler allows registers explicitly used in the
554 rtl to be used as spill registers but prevents the compiler from
555 extending the lifetime of these registers. */
557 #define SMALL_REGISTER_CLASSES
559 /* The order in which register should be allocated. */
560 #define REG_ALLOC_ORDER \
561 { 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14,15,16,17,18,19,20,21 }
563 /* The class value for index registers, and the one for base regs. */
564 #define INDEX_REG_CLASS R0_REGS
565 #define BASE_REG_CLASS GENERAL_REGS
567 /* Get reg_class from a letter such as appears in the machine
569 extern enum reg_class reg_class_from_letter[];
571 #define REG_CLASS_FROM_LETTER(C) \
572 ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
575 /* The letters I, J, K, L and M in a register constraint string
576 can be used to stand for particular ranges of immediate operands.
577 This macro defines what the ranges are.
578 C is the letter, and VALUE is a constant value.
579 Return 1 if VALUE is in the range specified by C.
580 I: arithmetic operand -127..128, as used in add, sub, etc
581 L: logical operand 0..255, as used in and, or, etc.
582 J: something ok as a move source - so it must be easy to make
585 K: shift operand 1,2,8 or 16 */
588 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127)
589 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255)
590 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
591 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
592 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
593 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
594 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
595 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
596 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
597 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
600 /* Similar, but for floating constants, and defining letters G and H.
601 Here VALUE is the CONST_DOUBLE rtx itself. */
603 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
604 ((C) == 'G' ? CONST_OK_FOR_I (CONST_DOUBLE_HIGH (VALUE)) \
605 && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \
608 /* Given an rtx X being reloaded into a reg required to be
609 in class CLASS, return the class of reg to actually use.
610 In general this is just CLASS; but on some machines
611 in some cases it is preferable to use a more restrictive class. */
613 #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
615 /* Return the register class of a scratch register needed to copy IN into
616 or out of a register in CLASS in MODE. If it can be done directly,
617 NO_REGS is returned. */
620 /* Return the maximum number of consecutive registers
621 needed to represent mode MODE in a register of class CLASS.
623 On SH this is the size of MODE in words */
624 #define CLASS_MAX_NREGS(CLASS, MODE) \
625 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
629 /* Stack layout; function entry, exit and calling. */
631 /* Define the number of register that can hold parameters.
632 These two macros are used only in other macro definitions below. */
634 #define FIRST_PARM_REG 4
635 #define FIRST_RET_REG (TARGET_RETR2 ? 2 : 0)
637 /* Define this if pushing a word on the stack
638 makes the stack pointer a smaller address. */
639 #define STACK_GROWS_DOWNWARD
641 /* Define this macro if the addresses of local variable slots are at
642 negative offsets from the frame pointer.
644 The SH only has positive indexes, so grow the frame up
646 /* #define FRAME_GROWS_DOWNWARD */
648 /* Offset from the frame pointer to the first local variable slot to
650 #define STARTING_FRAME_OFFSET 0
652 /* If we generate an insn to push BYTES bytes,
653 this says how many the stack pointer really advances by. */
654 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
656 /* Offset of first parameter from the argument pointer register value. */
657 #define FIRST_PARM_OFFSET(FNDECL) 0
659 /* Value is the number of byte of arguments automatically
660 popped when returning from a subroutine call.
661 FUNTYPE is the data type of the function (as a tree),
662 or for a library call it is an identifier node for the subroutine name.
663 SIZE is the number of bytes of arguments passed on the stack.
665 On the SH, the caller does not pop any of its arguments that were passed
667 #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
669 /* Define how to find the value returned by a function.
670 VALTYPE is the data type of the value (as a tree).
671 If the precise function being called is known, FUNC is its FUNCTION_DECL;
672 otherwise, FUNC is 0. */
674 #define FUNCTION_VALUE(VALTYPE, FUNC) \
676 TYPE_MODE (VALTYPE) == BLKmode ? SImode : TYPE_MODE (VALTYPE), \
679 /* Define how to find the value returned by a library function
680 assuming the value has mode MODE. */
681 #define LIBCALL_VALUE(MODE) \
682 gen_rtx (REG, MODE, FIRST_RET_REG)
684 /* 1 if N is a possible register number for a function value.
685 On the SH, only r0 can return results. */
686 #define FUNCTION_VALUE_REGNO_P(REGNO) \
687 ((REGNO) == FIRST_RET_REG)
689 /* 1 if N is a possible register number for function argument passing.*/
691 #define FUNCTION_ARG_REGNO_P(REGNO) \
692 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
696 /* Define a data type for recording info about an argument list
697 during the scan of that argument list. This data type should
698 hold all necessary information about the function itself
699 and about the args processed so far, enough to enable macros
700 such as FUNCTION_ARG to determine where the next arg should go.
702 On SH, this is a single integer, which is a number of words
703 of arguments scanned so far (including the invisible argument,
704 if any, which holds the structure-value-address).
705 Thus NARGREGS or more means all following args should go on the stack. */
707 #define CUMULATIVE_ARGS int
709 #define ROUND_ADVANCE(SIZE) \
710 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
712 /* Round a register number up to a proper boundary for an arg of mode
715 The SH doesn't care about double alignment, so we only
716 round doubles to even regs when asked to explicitly. */
718 #define ROUND_REG(X, MODE) \
719 ((TARGET_ALIGN_DOUBLE \
720 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
721 ? ((X) + ((X) & 1)) : (X))
724 /* Initialize a variable CUM of type CUMULATIVE_ARGS
725 for a call to a function whose data type is FNTYPE.
726 For a library call, FNTYPE is 0.
728 On SH, the offset always starts at 0: the first parm reg is always
731 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
734 /* Update the data in CUM to advance over an argument
735 of mode MODE and data type TYPE.
736 (TYPE is null for libcalls where that information may not be
739 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
740 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
741 + ((MODE) != BLKmode \
742 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
743 : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
745 /* Define where to put the arguments to a function.
746 Value is zero to push the argument on the stack,
747 or a hard register in which to store the argument.
749 MODE is the argument's machine mode.
750 TYPE is the data type of the argument (as a tree).
751 This is null for libcalls where that information may
753 CUM is a variable of type CUMULATIVE_ARGS which gives info about
754 the preceding args and about the function being called.
755 NAMED is nonzero if this argument is a named parameter
756 (otherwise it is an extra parameter matching an ellipsis).
758 On SH the first args are normally in registers
759 and the rest are pushed. Any arg that starts within the first
760 NPARM_REGS words is at least partially passed in a register unless
761 its data type forbids. */
764 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
765 sh_function_arg (CUM, MODE, TYPE, NAMED)
767 extern struct rtx_def *sh_function_arg();
769 /* For an arg passed partly in registers and partly in memory,
770 this is the number of registers used.
771 For args passed entirely in registers or entirely in memory, zero.
773 We sometimes split args */
775 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
776 sh_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
778 extern int current_function_anonymous_args;
780 /* Perform any needed actions needed for a function that is receiving a
781 variable number of arguments. */
783 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
784 current_function_anonymous_args = 1;
787 /* Call the function profiler with a given profile label. */
789 #define FUNCTION_PROFILER(STREAM,LABELNO) \
791 fprintf(STREAM, " trapa #5\n"); \
792 fprintf(STREAM, " .align 2\n"); \
793 fprintf(STREAM, " .long LP%d\n", (LABELNO)); \
797 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
798 the stack pointer does not matter. The value is tested only in
799 functions that have frame pointers.
800 No definition is equivalent to always zero. */
802 #define EXIT_IGNORE_STACK 1
804 /* Generate the assembly code for function exit
805 Just dump out any accumulated constant table.*/
807 #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue (STREAM, SIZE)
810 /* Output assembler code for a block containing the constant parts
811 of a trampoline, leaving space for the variable parts.
813 On the SH, the trapoline looks like
814 1 0000 D301 mov.l l1,r3
815 2 0002 DD02 mov.l l2,r13
818 5 0008 00000000 l1: .long function
819 6 000c 00000000 l2: .long area
821 #define TRAMPOLINE_TEMPLATE(FILE) \
823 fprintf ((FILE), " .word 0xd301\n"); \
824 fprintf ((FILE), " .word 0xdd02\n"); \
825 fprintf ((FILE), " .word 0x4d2b\n"); \
826 fprintf ((FILE), " .word 0x200b\n"); \
827 fprintf ((FILE), " .long 0\n"); \
828 fprintf ((FILE), " .long 0\n"); \
831 /* Length in units of the trampoline for entering a nested function. */
832 #define TRAMPOLINE_SIZE 16
834 /* Alignment required for a trampoline in units. */
835 #define TRAMPOLINE_ALIGN 4
837 /* Emit RTL insns to initialize the variable parts of a trampoline.
838 FNADDR is an RTX for the address of the function's pure code.
839 CXT is an RTX for the static chain value for the function. */
841 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
843 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
845 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
850 /* Addressing modes, and classification of registers for them. */
851 #define HAVE_POST_INCREMENT 1
852 /*#define HAVE_PRE_INCREMENT 1*/
853 /*#define HAVE_POST_DECREMENT 1*/
854 #define HAVE_PRE_DECREMENT 1
856 /* Macros to check register numbers against specific register classes. */
858 /* These assume that REGNO is a hard or pseudo reg number.
859 They give nonzero only if REGNO is a hard reg of the suitable class
860 or a pseudo reg currently allocated to a suitable hard reg.
861 Since they use reg_renumber, they are safe only once reg_renumber
862 has been allocated, which happens in local-alloc.c.
866 #define REGNO_OK_FOR_BASE_P(REGNO) \
867 ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
868 #define REGNO_OK_FOR_INDEX_P(REGNO) \
869 ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
871 /* Maximum number of registers that can appear in a valid memory
874 #define MAX_REGS_PER_ADDRESS 2
876 /* Recognize any constant value that is a valid address. */
878 #define CONSTANT_ADDRESS_P(X) \
879 (GET_CODE (X) == LABEL_REF)
881 /* Nonzero if the constant value X is a legitimate general operand. */
883 #define LEGITIMATE_CONSTANT_P(X) \
884 (GET_CODE(X) != CONST_DOUBLE /*&& GET_CODE(X) != LABEL_REF*/)
887 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
888 and check its validity for a certain class.
889 We have two alternate definitions for each of them.
890 The usual definition accepts all pseudo regs; the other rejects
891 them unless they have been allocated suitable hard regs.
892 The symbol REG_OK_STRICT causes the latter definition to be used. */
894 #define MODE_DISP_OK_4(X,MODE) ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<64) && (!(INTVAL(X) &3)))
895 #define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3)))
896 #define MODE_DISP_OK_2(X,MODE) ((GET_MODE_SIZE(MODE)==2) && ((unsigned)INTVAL(X)<32) && TARGET_TRYR0 && (!INTVAL(X) &1))
897 #define MODE_DISP_OK_1(X,MODE) ((GET_MODE_SIZE(MODE)==1) && ((unsigned)INTVAL(X)<16) && TARGET_TRYR0)
899 #ifndef REG_OK_STRICT
902 /* Nonzero if X is a hard reg that can be used as a base reg
903 or if it is a pseudo reg. */
904 #define REG_OK_FOR_BASE_P(X) \
905 (REGNO (X) <= 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
906 /* Nonzero if X is a hard reg that can be used as an index
907 or if it is a pseudo reg. */
909 #define REG_OK_FOR_INDEX_P(X) \
910 (REGNO (X) == 0 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
912 #define REG_OK_FOR_PRE_POST_P(X) \
913 (REG_OK_FOR_BASE_P (X))
916 /* Nonzero if X is a hard reg that can be used as a base reg. */
917 #define REG_OK_FOR_BASE_P(X) \
918 REGNO_OK_FOR_BASE_P (REGNO (X))
920 /* Nonzero if X is a hard reg that can be used as an index. */
921 #define REG_OK_FOR_INDEX_P(X) \
922 REGNO_OK_FOR_INDEX_P (REGNO (X))
924 #define REG_OK_FOR_PRE_POST_P(X) \
925 (REGNO_OK_FOR_BASE_P (REGNO (X)))
928 /* The Q is a pc relative load operand */
929 #define EXTRA_CONSTRAINT_Q(OP) \
930 (GET_CODE (OP) == MEM && \
931 ((GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
932 || (GET_CODE (XEXP (OP, 0)) == CONST \
933 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS \
934 && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == LABEL_REF \
935 && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT)))
937 /* The U is a label ref */
938 #define EXTRA_CONSTRAINT_U(OP) \
939 (GET_CODE (OP) == LABEL_REF)
941 #define IS_INDEX(OP) \
942 ((GET_CODE (OP) == PLUS && \
943 (INDEX_REGISTER_RTX_P (XEXP (OP, 0)) && BASE_REGISTER_RTX_P (XEXP (OP, 1))) || \
944 (INDEX_REGISTER_RTX_P (XEXP (OP, 1)) && BASE_REGISTER_RTX_P (XEXP (OP, 0)))))
948 #define EXTRA_CONSTRAINT(OP, C) \
949 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
950 : (C) == 'U' ? EXTRA_CONSTRAINT_U (OP) \
954 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
955 that is a valid memory address for an instruction.
956 The MODE argument is the machine mode for the MEM expression
957 that wants to use this address.
959 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
961 #define BASE_REGISTER_RTX_P(X) \
962 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
964 #define INDEX_REGISTER_RTX_P(X) \
965 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
968 /* Jump to LABEL if X is a valid address RTX. This must also take
969 REG_OK_STRICT into account when deciding about valid registers, but it uses
970 the above macros so we are in luck.
979 /* The SH allows a displacement in a QI or HI amode, but only when the
980 other operand is R0. GCC doesn't handle this very well, so we forgo
983 A legitimate index for a QI or HI is 0, SI and above can be any
986 #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
988 if (GET_CODE (OP) == CONST_INT) \
990 if (MODE_DISP_OK_4 (OP, MODE)) goto LABEL; \
991 if (MODE_DISP_OK_8 (OP, MODE)) goto LABEL; \
992 if (MODE_DISP_OK_2 (OP, MODE)) goto LABEL; \
993 if (MODE_DISP_OK_1 (OP, MODE)) goto LABEL; \
998 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1000 if (BASE_REGISTER_RTX_P (X)) \
1002 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1003 && GET_CODE (XEXP (X, 0)) == REG \
1004 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1006 else if (GET_CODE (X) == PLUS) \
1008 rtx xop0 = XEXP(X,0); \
1009 rtx xop1 = XEXP(X,1); \
1010 if (GET_MODE_SIZE(MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
1011 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1012 if (GET_MODE_SIZE(MODE) <= 8 && BASE_REGISTER_RTX_P (xop1)) \
1013 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1014 if (GET_MODE_SIZE(MODE)<= 4) { \
1015 if(BASE_REGISTER_RTX_P(xop1) && \
1016 INDEX_REGISTER_RTX_P(xop0)) goto LABEL; \
1017 if(INDEX_REGISTER_RTX_P(xop1) && \
1018 BASE_REGISTER_RTX_P(xop0)) goto LABEL; \
1021 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1022 && GET_CODE (XEXP (X, 0)) == REG \
1023 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1028 /* Try machine-dependent ways of modifying an illegitimate address
1029 to be legitimate. If we find one, return the new, valid address.
1030 This macro is used in only one place: `memory_address' in explow.c.
1032 OLDX is the address as it was before break_out_memory_refs was called.
1033 In some cases it is useful to look at this to decide what needs to be done.
1035 MODE and WIN are passed so that this macro can use
1036 GO_IF_LEGITIMATE_ADDRESS.
1038 It is always safe for this macro to do nothing. It exists to recognize
1039 opportunities to optimize the output.
1043 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) ;
1045 /* Go to LABEL if ADDR (a legitimate address expression)
1046 has an effect that depends on the machine mode it is used for. */
1047 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1049 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1050 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1054 /* Specify the machine mode that this machine uses
1055 for the index in the tablejump instruction. */
1056 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
1058 /* Define this if the tablejump instruction expects the table
1059 to contain offsets from the address of the table.
1060 Do not define this if the table should contain absolute addresses. */
1061 #define CASE_VECTOR_PC_RELATIVE
1063 /* Specify the tree operation to be used to convert reals to integers. */
1064 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1066 /* This is the kind of divide that is easiest to do in the general case. */
1067 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1069 /* 'char' is signed by default */
1070 #define DEFAULT_SIGNED_CHAR 1
1072 /* The type of size_t unsigned int. */
1073 #define SIZE_TYPE "unsigned int"
1075 #define WCHAR_TYPE "short unsigned int"
1076 #define WCHAR_TYPE_SIZE 16
1078 /* Don't cse the address of the function being compiled. */
1079 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
1081 /* Max number of bytes we can move from memory to memory
1082 in one reasonably fast instruction. */
1085 /* Define if operations between registers always perform the operation
1086 on the full register even if a narrower mode is specified. */
1087 #define WORD_REGISTER_OPERATIONS
1089 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1090 will either zero-extend or sign-extend. The value of this macro should
1091 be the code that says which one of the two operations is implicitly
1092 done, NIL if none. */
1093 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
1095 /* Define this if zero-extension is slow (more than one real instruction).
1096 On the SH, it's only one instruction */
1097 /* #define SLOW_ZERO_EXTEND */
1099 /* Nonzero if access to memory by bytes is slow and undesirable. */
1100 #define SLOW_BYTE_ACCESS 0
1102 /* We assume that the store-condition-codes instructions store 0 for false
1103 and some other value for true. This is the value stored for true. */
1105 #define STORE_FLAG_VALUE 1
1107 /* Immediate shift counts are truncated by the output routines (or was it
1108 the assembler?). Shift counts in a register are truncated by ARM. Note
1109 that the native compiler puts too large (> 32) immediate shift counts
1110 into a register and shifts by the register, letting the ARM decide what
1111 to do instead of doing that itself. */
1112 #define SHIFT_COUNT_TRUNCATED 1
1114 /* All integers have the same format so truncation is easy. */
1115 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1117 /* Define this if addresses of constant functions
1118 shouldn't be put through pseudo regs where they can be cse'd.
1119 Desirable on machines where ordinary constants are expensive
1120 but a CALL with constant address is cheap. */
1121 /*#define NO_FUNCTION_CSE 1*/
1123 /* Chars and shorts should be passed as ints. */
1124 #define PROMOTE_PROTOTYPES 1
1126 /* The machine modes of pointers and functions */
1127 #define Pmode SImode
1128 #define FUNCTION_MODE Pmode
1130 /* The relative costs of various types of constants. Note that cse.c defines
1131 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1133 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1135 if (INTVAL(RTX)==0) return 0; \
1136 if (CONST_OK_FOR_I (INTVAL(RTX))) \
1144 case CONST_DOUBLE: \
1147 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1149 return COSTS_N_INSNS (andcosts (X)); \
1151 return COSTS_N_INSNS (multcosts (X)); \
1154 return COSTS_N_INSNS (shiftcosts (X)) ; \
1159 return COSTS_N_INSNS (100); \
1165 /* The multiply and divide insns on the SH are actually function calls
1166 with some special constraints on arguments and register usage.
1168 These macros tell reorg that the references to arguments and
1169 register clobbers for insns of type sfunc do not appear to happen
1170 until after the millicode call. This allows reorg to put insns
1171 which set the argument registers into the delay slot of the millicode
1172 call -- thus they act more like traditional CALL_INSNs.
1174 get_attr_type will try to recognize the given insn, so make sure to
1175 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1178 #define INSN_SETS_ARE_DELAYED(X) \
1179 ((GET_CODE (X) == INSN \
1180 && GET_CODE (PATTERN (X)) != SEQUENCE \
1181 && GET_CODE (PATTERN (X)) != USE \
1182 && GET_CODE (PATTERN (X)) != CLOBBER \
1183 && get_attr_type (X) == TYPE_SFUNC))
1185 #define INSN_REFERENCES_ARE_DELAYED(X) \
1186 ((GET_CODE (X) == INSN \
1187 && GET_CODE (PATTERN (X)) != SEQUENCE \
1188 && GET_CODE (PATTERN (X)) != USE \
1189 && GET_CODE (PATTERN (X)) != CLOBBER \
1190 && get_attr_type (X) == TYPE_SFUNC))
1192 /* Compute extra cost of moving data between one register class
1195 On the SH it is hard to move into the T reg, but simple to load
1199 #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
1200 (((DSTCLASS == T_REGS) || (DSTCLASS == PR_REG)) ? 10 : 1)
1202 /* Assembler output control */
1204 /* The text to go at the start of the assembler file */
1205 #define ASM_FILE_START(STREAM) \
1206 output_file_start (STREAM, f_options, sizeof f_options / sizeof f_options[0], \
1207 W_options, sizeof W_options / sizeof W_options[0]);
1210 #define ASM_FILE_END(STREAM)
1213 #define ASM_APP_ON ""
1214 #define ASM_APP_OFF ""
1215 #define FILE_ASM_OP "\t.file\n"
1216 #define IDENT_ASM_OP "\t.ident\n"
1218 /* How to change between sections. */
1220 #define TEXT_SECTION_ASM_OP "\t.text"
1221 #define DATA_SECTION_ASM_OP "\t.data"
1222 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n"
1223 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n"
1224 #define INIT_SECTION_ASM_OP "\t.section\t.init\n"
1225 #define EXTRA_SECTIONS in_ctors, in_dtors
1226 #define EXTRA_SECTION_FUNCTIONS \
1230 if (in_section != in_ctors) \
1232 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1233 in_section = in_ctors; \
1239 if (in_section != in_dtors) \
1241 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1242 in_section = in_dtors; \
1246 /* A C statement to output something to the assembler file to switch to section
1247 NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
1248 NULL_TREE. Some target formats do not support arbitrary sections. Do not
1249 define this macro in such cases. */
1251 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME) \
1252 do { fprintf (FILE, ".section\t%s\n", NAME); } while (0)
1254 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
1255 do { ctors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1257 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
1258 do { dtors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1260 #undef DO_GLOBAL_CTORS_BODY
1262 #define DO_GLOBAL_CTORS_BODY \
1264 typedef (*pfunc)(); \
1265 extern pfunc __ctors[]; \
1266 extern pfunc __ctors_end[]; \
1268 for (p = __ctors; p < __ctors_end; p++) \
1274 #undef DO_GLOBAL_DTORS_BODY
1275 #define DO_GLOBAL_DTORS_BODY \
1277 typedef (*pfunc)(); \
1278 extern pfunc __dtors[]; \
1279 extern pfunc __dtors_end[]; \
1281 for (p = __dtors; p < __dtors_end; p++) \
1288 #define ASM_OUTPUT_REG_PUSH(file, v) \
1289 fprintf (file, "\tmov.l r%s,-@r15\n", v);
1291 #define ASM_OUTPUT_REG_POP(file, v) \
1292 fprintf (file, "\tmov.l @r15+,r%s\n", v);
1295 /* The assembler's names for the registers. RFP need not always be used as
1296 the Real framepointer; it can also be used as a normal general register.
1297 Note that the name `fp' is horribly misleading since `fp' is in fact only
1298 the argument-and-return-context pointer. */
1299 #define REGISTER_NAMES \
1301 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1302 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1303 "ap", "pr", "t", "gbr", "mach","macl" \
1306 /* DBX register number for a given compiler register number */
1307 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1309 /* Output a label definition. */
1310 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1311 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1314 /* This is how to output an assembler line
1315 that says to advance the location counter
1316 to a multiple of 2**LOG bytes. */
1318 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1320 fprintf (FILE, "\t.align %d\n", LOG)
1322 /* Output a function label definition. */
1323 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1324 ASM_OUTPUT_LABEL(STREAM, NAME)
1326 /* Output a globalising directive for a label. */
1327 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1328 (fprintf (STREAM, "\t.global\t"), \
1329 assemble_name (STREAM, NAME), \
1330 fputc ('\n',STREAM)) \
1332 /* Output a reference to a label. */
1333 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1334 fprintf (STREAM, "_%s", NAME)
1336 /* Make an internal label into a string. */
1337 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1338 sprintf (STRING, "*%s%d", PREFIX, NUM)
1340 /* Output an internal label definition. */
1341 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1342 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1344 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1346 /* Construct a private name. */
1347 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1348 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1349 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1351 /* Jump tables must be 32 bit aligned, no matter the size of the element */
1352 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1353 fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM);
1355 /* Output a relative address table. */
1357 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1358 if (TARGET_BIGTABLE) \
1359 fprintf (STREAM, "\t.long L%d-L%d\n", VALUE,REL); \
1361 fprintf (STREAM, "\t.word L%d-L%d\n", VALUE,REL); \
1363 /* Output an absolute table element */
1365 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1366 if (TARGET_BIGTABLE) \
1367 fprintf (STREAM, "\t.long L%d\n", VALUE); \
1369 fprintf (STREAM, "\t.word L%d\n", VALUE); \
1371 /* Output various types of constants. */
1374 /* This is how to output an assembler line defining a `double' */
1376 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1377 do { char dstr[30]; \
1378 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1379 fprintf (FILE, "\t.double %s\n", dstr); \
1383 /* This is how to output an assembler line defining a `float' constant. */
1384 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1385 do { char dstr[30]; \
1386 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1387 fprintf (FILE, "\t.float %s\n", dstr); \
1390 #define ASM_OUTPUT_INT(STREAM, EXP) \
1391 (fprintf (STREAM, "\t.long\t"), \
1392 output_addr_const (STREAM, (EXP)), \
1393 fputc ('\n', STREAM))
1395 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1396 (fprintf (STREAM, "\t.short\t"), \
1397 output_addr_const (STREAM, (EXP)), \
1398 fputc ('\n', STREAM))
1400 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1401 (fprintf (STREAM, "\t.byte\t"), \
1402 output_addr_const (STREAM, (EXP)), \
1403 fputc ('\n', STREAM))
1405 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1406 fprintf (STREAM, "\t.byte\t%d\n", VALUE) \
1408 /* This is how to output an assembler line
1409 that says to advance the location counter by SIZE bytes. */
1411 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1412 fprintf (FILE, "\t.space %d\n", (SIZE))
1414 /* This says how to output an assembler line
1415 to define a global common symbol. */
1417 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1418 ( fputs ("\t.comm ", (FILE)), \
1419 assemble_name ((FILE), (NAME)), \
1420 fprintf ((FILE), ",%d\n", (SIZE)))
1422 /* This says how to output an assembler line
1423 to define a local common symbol. */
1425 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
1426 ( fputs ("\t.lcomm ", (FILE)), \
1427 assemble_name ((FILE), (NAME)), \
1428 fprintf ((FILE), ",%d\n", (SIZE)))
1431 /* The assembler's parentheses characters. */
1432 #define ASM_OPEN_PAREN "("
1433 #define ASM_CLOSE_PAREN ")"
1435 /* Target characters. */
1436 #define TARGET_BELL 007
1437 #define TARGET_BS 010
1438 #define TARGET_TAB 011
1439 #define TARGET_NEWLINE 012
1440 #define TARGET_VT 013
1441 #define TARGET_FF 014
1442 #define TARGET_CR 015
1445 /* Only perform branch elimination (by making instructions conditional) if
1446 we're optimising. Otherwise it's of no use anyway. */
1447 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1448 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1450 /* Print operand X (an rtx) in assembler syntax to file FILE.
1451 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1452 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1454 #define PRINT_OPERAND(STREAM, X, CODE) print_operand (STREAM, X, CODE)
1456 /* Print a memory address as an operand to reference that memory location. */
1458 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address (STREAM, X)
1460 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1461 ((CHAR)=='.' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR)=='!' || (CHAR)=='@')
1464 extern struct rtx_def *sh_compare_op0;
1465 extern struct rtx_def *sh_compare_op1;
1466 extern struct rtx_def *prepare_scc_operands();
1467 extern struct rtx_def *table_lab;
1470 extern enum attr_cpu sh_cpu; /* target cpu */
1472 /* Declare functions defined in sh.c and used in templates. */
1474 extern char *output_branch();
1475 extern char *output_shift();
1476 extern char *output_movedouble();
1477 extern char *output_movepcrel();
1478 extern char *output_jump_label_table();
1479 extern char *output_far_jump();
1482 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
1484 /* Generate calls to memcpy, memcmp and memset. */
1486 #define TARGET_MEM_FUNCTIONS
1488 #define HANDLE_PRAGMA(finput) return handle_pragma (finput)
1490 /* Set when processing a function with pragma interrupt turned on. */
1492 extern int pragma_interrupt;
1493 #define MOVE_RATIO (TARGET_SMALLCODE ? 4 : 16)