1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
35 #define TARGET_CPU_CPP_BUILTINS() \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
43 builtin_define ("__sh1__"); \
46 builtin_define ("__sh2__"); \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
52 builtin_define ("__sh3__"); \
53 builtin_define ("__SH3__"); \
54 if (TARGET_HARD_SH4) \
55 builtin_define ("__SH4_NOFPU__"); \
57 case PROCESSOR_SH3E: \
58 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
61 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
65 builtin_define_with_value ("__SH5__", \
66 TARGET_SHMEDIA64 ? "64" : "32", 0); \
67 builtin_define_with_value ("__SHMEDIA__", \
68 TARGET_SHMEDIA ? "1" : "0", 0); \
69 if (! TARGET_FPU_DOUBLE) \
70 builtin_define ("__SH4_NOFPU__"); \
74 builtin_define ("__HITACHI__"); \
75 builtin_define (TARGET_LITTLE_ENDIAN \
76 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
79 builtin_define ("__pic__"); \
80 builtin_define ("__PIC__"); \
84 /* We can not debug without a frame pointer. */
85 /* #define CAN_DEBUG_WITHOUT_FP */
87 #define CONDITIONAL_REGISTER_USAGE do \
90 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
91 if (! VALID_REGISTER_P (regno)) \
92 fixed_regs[regno] = call_used_regs[regno] = 1; \
93 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
95 call_used_regs[FIRST_GENERAL_REG + 8] \
96 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
99 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
100 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
101 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
104 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
105 /* Renesas saves and restores mac registers on call. */ \
106 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
108 call_used_regs[MACH_REG] = 0; \
109 call_used_regs[MACL_REG] = 0; \
111 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
112 regno <= LAST_FP_REG; regno += 2) \
113 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
114 if (TARGET_SHMEDIA) \
116 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
117 if (! fixed_regs[regno] && call_used_regs[regno]) \
118 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
121 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
122 if (! fixed_regs[regno] && call_used_regs[regno]) \
123 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
126 /* ??? Need to write documentation for all SH options and add it to the
129 /* Run-time compilation parameters selecting different hardware subsets. */
131 extern int target_flags;
132 #define ISIZE_BIT (1<<1)
133 #define DALIGN_BIT (1<<6)
134 #define SH1_BIT (1<<8)
135 #define SH2_BIT (1<<9)
136 #define SH3_BIT (1<<10)
137 #define SH_E_BIT (1<<11)
138 #define HARD_SH4_BIT (1<<5)
139 #define FPU_SINGLE_BIT (1<<7)
140 #define SH4_BIT (1<<12)
141 #define FMOVD_BIT (1<<4)
142 #define SH5_BIT (1<<0)
143 #define SPACE_BIT (1<<13)
144 #define BIGTABLE_BIT (1<<14)
145 #define RELAX_BIT (1<<15)
146 #define USERMODE_BIT (1<<16)
147 #define HITACHI_BIT (1<<22)
148 #define NOMACSAVE_BIT (1<<23)
149 #define PREFERGOT_BIT (1<<24)
150 #define PADSTRUCT_BIT (1<<28)
151 #define LITTLE_ENDIAN_BIT (1<<29)
152 #define IEEE_BIT (1<<30)
153 #define SAVE_ALL_TR_BIT (1<<2)
155 /* Nonzero if this is an ELF target - compile time only */
158 /* Nonzero if we should dump out instruction size info. */
159 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
161 /* Nonzero to align doubles on 64 bit boundaries. */
162 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
164 /* Nonzero if we should generate code using type 1 insns. */
165 #define TARGET_SH1 (target_flags & SH1_BIT)
167 /* Nonzero if we should generate code using type 2 insns. */
168 #define TARGET_SH2 (target_flags & SH2_BIT)
170 /* Nonzero if we should generate code using type 2E insns. */
171 #define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
173 /* Nonzero if we should generate code using type 3 insns. */
174 #define TARGET_SH3 (target_flags & SH3_BIT)
176 /* Nonzero if we should generate code using type 3E insns. */
177 #define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
179 /* Nonzero if the cache line size is 32. */
180 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
182 /* Nonzero if we schedule for a superscalar implementation. */
183 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
185 /* Nonzero if the target has separate instruction and data caches. */
186 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
188 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
189 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
191 /* Nonzero if the default precision of th FPU is single */
192 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
194 /* Nonzero if a double-precision FPU is available. */
195 #define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
197 /* Nonzero if an FPU is available. */
198 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
200 /* Nonzero if we should generate code using type 4 insns. */
201 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
203 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
204 #define TARGET_SH5 (target_flags & SH5_BIT)
206 /* Nonzero if we should generate code using the SHcompact instruction
207 set and 32-bit ABI. */
208 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
210 /* Nonzero if we should generate code using the SHmedia instruction
212 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
214 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
216 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
217 && (target_flags & SH_E_BIT))
219 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
221 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
222 && ! (target_flags & SH_E_BIT))
224 /* Nonzero if we should generate code using SHmedia FPU instructions. */
225 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
226 /* Nonzero if we should generate fmovd. */
227 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
229 /* Nonzero if we respect NANs. */
230 #define TARGET_IEEE (target_flags & IEEE_BIT)
232 /* Nonzero if we should generate smaller code rather than faster code. */
233 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
235 /* Nonzero to use long jump tables. */
236 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
238 /* Nonzero to generate pseudo-ops needed by the assembler and linker
239 to do function call relaxing. */
240 #define TARGET_RELAX (target_flags & RELAX_BIT)
242 /* Nonzero if using Renesas's calling convention. */
243 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
245 /* Nonzero if not saving macl/mach when using -mhitachi */
246 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
248 /* Nonzero if padding structures to a multiple of 4 bytes. This is
249 incompatible with Renesas's compiler, and gives unusual structure layouts
250 which confuse programmers.
251 ??? This option is not useful, but is retained in case there are people
252 who are still relying on it. It may be deleted in the future. */
253 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
255 /* Nonzero if generating code for a little endian SH. */
256 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
258 /* Nonzero if we should do everything in userland. */
259 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
261 /* Nonzero if we should prefer @GOT calls when generating PIC. */
262 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
264 #define TARGET_SAVE_ALL_TARGET_REGS (target_flags & SAVE_ALL_TR_BIT)
266 /* This is not used by the SH2E calling convention */
267 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
268 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
269 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
271 #ifndef TARGET_CPU_DEFAULT
272 #define TARGET_CPU_DEFAULT SELECT_SH1
276 #define SUPPORT_SH4_SINGLE
279 #define SELECT_SH1 (SH1_BIT)
280 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
281 #define SELECT_SH2E (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
282 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
283 #define SELECT_SH3E (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
284 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
285 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
286 #define SELECT_SH4 (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
287 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
288 #define SELECT_SH5_64MEDIA (SH5_BIT | SH4_BIT)
289 #define SELECT_SH5_64MEDIA_NOFPU (SH5_BIT)
290 #define SELECT_SH5_32MEDIA (SH5_BIT | SH4_BIT | SH_E_BIT)
291 #define SELECT_SH5_32MEDIA_NOFPU (SH5_BIT | SH_E_BIT)
292 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
293 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
295 /* Disable processor switches for which we have no suitable multilibs. */
297 #define TARGET_SWITCH_SH1
299 #define TARGET_SWITCH_SH2
301 #define TARGET_SWITCH_SH3
302 #ifndef SUPPORT_SH4_NOFPU
303 #define TARGET_SWITCH_SH4_NOFPU
310 #define TARGET_SWITCH_SH2E
312 #define TARGET_SWITCH_SH3E
313 #ifndef SUPPORT_SH4_SINGLE_ONLY
314 #define TARGET_SWITCH_SH4_SINGLE_ONLY
320 #define TARGET_SWITCH_SH4
323 #ifndef SUPPORT_SH4_SINGLE
324 #define TARGET_SWITCH_SH4_SINGLE
327 #ifndef SUPPORT_SH5_64MEDIA
328 #define TARGET_SWITCH_SH5_64MEDIA
331 #ifndef SUPPORT_SH5_64MEDIA_NOFPU
332 #define TARGET_SWITCH_SH5_64MEDIA_NOFPU
335 #if !defined(SUPPORT_SH5_32MEDIA) && !defined (SUPPORT_SH5_COMPACT)
336 #define TARGET_SWITCHES_SH5_32MEDIA
339 #if !defined(SUPPORT_SH5_32MEDIA_NOFPU) && !defined (SUPPORT_SH5_COMPACT_NOFPU)
340 #define TARGET_SWITCHES_SH5_32MEDIA_NOFPU
343 /* Reset all target-selection flags. */
344 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
345 | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
347 #ifndef TARGET_SWITCH_SH1
348 #define TARGET_SWITCH_SH1 \
349 {"1", TARGET_NONE, "" }, \
350 {"1", SELECT_SH1, "Generate SH1 code" },
352 #ifndef TARGET_SWITCH_SH2
353 #define TARGET_SWITCH_SH2 \
354 {"2", TARGET_NONE, "" }, \
355 {"2", SELECT_SH2, "Generate SH2 code" },
357 #ifndef TARGET_SWITCH_SH2E
358 #define TARGET_SWITCH_SH2E \
359 {"2e", TARGET_NONE, "" }, \
360 {"2e", SELECT_SH2E, "Generate SH2e code" },
362 #ifndef TARGET_SWITCH_SH3
363 #define TARGET_SWITCH_SH3 \
364 {"3", TARGET_NONE, "" }, \
365 {"3", SELECT_SH3, "Generate SH3 code" },
367 #ifndef TARGET_SWITCH_SH3E
368 #define TARGET_SWITCH_SH3E \
369 {"3e", TARGET_NONE, "" }, \
370 {"3e", SELECT_SH3E, "Generate SH3e code" },
372 #ifndef TARGET_SWITCH_SH4_SINGLE_ONLY
373 #define TARGET_SWITCH_SH4_SINGLE_ONLY \
374 {"4-single-only", TARGET_NONE, "" }, \
375 {"4-single-only", SELECT_SH4_SINGLE_ONLY, "Generate only single-precision SH4 code" },
377 #ifndef TARGET_SWITCH_SH4_SINGLE
378 #define TARGET_SWITCH_SH4_SINGLE \
379 {"4-single", TARGET_NONE, "" }, \
380 {"4-single", SELECT_SH4_SINGLE, "Generate default single-precision SH4 code" },
382 #ifndef TARGET_SWITCH_SH4_NOFPU
383 #define TARGET_SWITCH_SH4_NOFPU \
384 {"4-nofpu", TARGET_NONE, "" }, \
385 {"4-nofpu", SELECT_SH4_NOFPU, "Generate SH4 FPU-less code" },
387 #ifndef TARGET_SWITCH_SH4
388 #define TARGET_SWITCH_SH4 \
389 {"4", TARGET_NONE, "" }, \
390 {"4", SELECT_SH4, "Generate SH4 code" },
392 #ifndef TARGET_SWITCH_SH5_64MEDIA
393 #define TARGET_SWITCH_SH5_64MEDIA \
394 {"5-64media", TARGET_NONE, "" }, \
395 {"5-64media", SELECT_SH5_64MEDIA, "Generate 64-bit SHmedia code" },
397 #ifndef TARGET_SWITCH_SH5_64MEDIA_NOFPU
398 #define TARGET_SWITCH_SH5_64MEDIA_NOFPU \
399 {"5-64media-nofpu", TARGET_NONE, "" }, \
400 {"5-64media-nofpu", SELECT_SH5_64MEDIA_NOFPU, "Generate 64-bit FPU-less SHmedia code" },
402 #ifndef TARGET_SWITCHES_SH5_32MEDIA
403 #define TARGET_SWITCHES_SH5_32MEDIA \
404 {"5-32media", TARGET_NONE, "" }, \
405 {"5-32media", SELECT_SH5_32MEDIA, "Generate 32-bit SHmedia code" }, \
406 {"5-compact", TARGET_NONE, "" }, \
407 {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" },
409 #ifndef TARGET_SWITCHES_SH5_32MEDIA_NOFPU
410 #define TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
411 {"5-32media-nofpu", TARGET_NONE, "" }, \
412 {"5-32media-nofpu", SELECT_SH5_32MEDIA_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
413 {"5-compact-nofpu", TARGET_NONE, "" }, \
414 {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" },
417 #define TARGET_SWITCHES \
418 { TARGET_SWITCH_SH1 \
423 TARGET_SWITCH_SH4_SINGLE_ONLY \
424 TARGET_SWITCH_SH4_SINGLE \
425 TARGET_SWITCH_SH4_NOFPU \
427 TARGET_SWITCH_SH5_64MEDIA \
428 TARGET_SWITCH_SH5_64MEDIA_NOFPU \
429 TARGET_SWITCHES_SH5_32MEDIA \
430 TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
431 {"b", -LITTLE_ENDIAN_BIT, "Generate code in big endian mode" }, \
432 {"bigtable", BIGTABLE_BIT, "Generate 32-bit offsets in switch tables" }, \
433 {"dalign", DALIGN_BIT, "Aligns doubles at 64-bit boundaries" }, \
434 {"fmovd", FMOVD_BIT, "" }, \
435 {"hitachi", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
436 {"renesas", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
437 {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" }, \
438 {"ieee", IEEE_BIT, "Increase the IEEE compliance for floating-point code" }, \
439 {"isize", ISIZE_BIT, "" }, \
440 {"l", LITTLE_ENDIAN_BIT, "Generate code in little endian mode" }, \
441 {"no-ieee", -IEEE_BIT, "" }, \
442 {"padstruct", PADSTRUCT_BIT, "" }, \
443 {"prefergot", PREFERGOT_BIT, "Emit function-calls using global offset table when generating PIC" }, \
444 {"relax", RELAX_BIT, "Shorten address references during linking" }, \
445 {"space", SPACE_BIT, "Deprecated. Use -Os instead" }, \
446 {"usermode", USERMODE_BIT, "Generate library function call to invalidate instruction cache entries after fixing trampoline" }, \
448 {"", TARGET_DEFAULT, "" } \
451 /* This are meant to be redefined in the host dependent files */
452 #define SUBTARGET_SWITCHES
454 /* This defaults us to big-endian. */
455 #ifndef TARGET_ENDIAN_DEFAULT
456 #define TARGET_ENDIAN_DEFAULT 0
459 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
461 #ifndef SH_MULTILIB_CPU_DEFAULT
462 #define SH_MULTILIB_CPU_DEFAULT "m1"
465 #if TARGET_ENDIAN_DEFAULT
466 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
468 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
471 #define CPP_SPEC " %(subtarget_cpp_spec) "
473 #ifndef SUBTARGET_CPP_SPEC
474 #define SUBTARGET_CPP_SPEC ""
477 #ifndef SUBTARGET_EXTRA_SPECS
478 #define SUBTARGET_EXTRA_SPECS
481 #define EXTRA_SPECS \
482 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
483 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
484 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
485 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
486 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
487 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
488 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
489 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
490 SUBTARGET_EXTRA_SPECS
492 #if TARGET_CPU_DEFAULT & HARD_SH4_BIT
493 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
495 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
498 #define SH_ASM_SPEC \
499 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
500 %(subtarget_asm_isa_spec)"
502 #define ASM_SPEC SH_ASM_SPEC
504 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
505 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
506 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
508 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
512 #define SUBTARGET_ASM_ISA_SPEC ""
514 #define LINK_EMUL_PREFIX "sh%{ml:l}"
516 #if TARGET_CPU_DEFAULT & SH5_BIT
517 #if TARGET_CPU_DEFAULT & SH_E_BIT
518 #define LINK_DEFAULT_CPU_EMUL "32"
519 #if TARGET_CPU_DEFAULT & SH1_BIT
520 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
522 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
524 #else /* !SH_E_BIT */
525 #define LINK_DEFAULT_CPU_EMUL "64"
526 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
527 #endif /* SH_E_BIT */
528 #define ASM_ISA_DEFAULT_SPEC \
529 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
531 #define LINK_DEFAULT_CPU_EMUL ""
532 #define ASM_ISA_DEFAULT_SPEC ""
535 #define SUBTARGET_LINK_EMUL_SUFFIX ""
536 #define SUBTARGET_LINK_SPEC ""
538 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
539 so that we can undo the damage without code replication. */
540 #define LINK_SPEC SH_LINK_SPEC
542 #define SH_LINK_SPEC "\
543 -m %(link_emul_prefix)\
544 %{m5-compact*|m5-32media*:32}\
546 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
547 %(subtarget_link_emul_suffix) \
548 %{mrelax:-relax} %(subtarget_link_spec)"
550 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
553 flag_omit_frame_pointer = -1; \
555 target_flags |= SPACE_BIT; \
556 if (TARGET_SHMEDIA && LEVEL > 1) \
558 flag_branch_target_load_optimize = 1; \
560 target_flags |= SAVE_ALL_TR_BIT; \
564 #define ASSEMBLER_DIALECT assembler_dialect
566 extern int assembler_dialect;
568 #define OVERRIDE_OPTIONS \
573 assembler_dialect = 0; \
584 assembler_dialect = 1; \
590 target_flags |= DALIGN_BIT; \
592 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN)) \
593 target_flags |= FMOVD_BIT; \
594 if (TARGET_SHMEDIA) \
596 /* There are no delay slots on SHmedia. */ \
597 flag_delayed_branch = 0; \
598 /* Relaxation isn't yet supported for SHmedia */ \
599 target_flags &= ~RELAX_BIT; \
601 /* -fprofile-arcs needs a working libgcov . In unified tree \
602 configurations with newlib, this requires to configure with \
603 --with-newlib --with-headers. But there is no way to check \
604 here we have a working libgcov, so just assume that we have. */\
607 warning ("Profiling is not supported on this target."); \
608 profile_flag = profile_arc_flag = 0; \
613 /* Only the sh64-elf assembler fully supports .quad properly. */\
614 targetm.asm_out.aligned_op.di = NULL; \
615 targetm.asm_out.unaligned_op.di = NULL; \
618 reg_class_from_letter['e' - 'a'] = NO_REGS; \
620 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
621 if (! VALID_REGISTER_P (regno)) \
622 sh_register_names[regno][0] = '\0'; \
624 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
625 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
626 sh_additional_register_names[regno][0] = '\0'; \
628 if (flag_omit_frame_pointer < 0) \
630 /* The debugging information is sufficient, \
631 but gdb doesn't implement this yet */ \
633 flag_omit_frame_pointer \
634 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
635 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
637 flag_omit_frame_pointer = 0; \
640 if (flag_pic && ! TARGET_PREFERGOT) \
641 flag_no_function_cse = 1; \
643 if (SMALL_REGISTER_CLASSES) \
645 /* Never run scheduling before reload, since that can \
646 break global alloc, and generates slower code anyway due \
647 to the pressure on R0. */ \
648 /* Enable sched1 for SH4; ready queue will be reordered by \
649 the target hooks when pressure is high. We can not do this for \
650 SH3 and lower as they give spill failures for R0. */ \
651 if (!TARGET_HARD_SH4) \
652 flag_schedule_insns = 0; \
655 if (align_loops == 0) \
656 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
657 if (align_jumps == 0) \
658 align_jumps = 1 << CACHE_LOG; \
659 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
660 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
662 /* Allocation boundary (in *bytes*) for the code of a function. \
663 SH1: 32 bit alignment is faster, because instructions are always \
664 fetched as a pair from a longword boundary. \
665 SH2 .. SH5 : align to cache line start. */ \
666 if (align_functions == 0) \
668 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
669 /* The linker relaxation code breaks when a function contains \
670 alignments that are larger than that at the start of a \
671 compilation unit. */ \
675 = align_loops > align_jumps ? align_loops : align_jumps; \
677 /* Also take possible .long constants / mova tables int account. */\
680 if (align_functions < min_align) \
681 align_functions = min_align; \
685 /* Target machine storage layout. */
687 /* Define this if most significant bit is lowest numbered
688 in instructions that operate on numbered bit-fields. */
690 #define BITS_BIG_ENDIAN 0
692 /* Define this if most significant byte of a word is the lowest numbered. */
693 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
695 /* Define this if most significant word of a multiword number is the lowest
697 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
699 /* Define this to set the endianness to use in libgcc2.c, which can
700 not depend on target_flags. */
701 #if defined(__LITTLE_ENDIAN__)
702 #define LIBGCC2_WORDS_BIG_ENDIAN 0
704 #define LIBGCC2_WORDS_BIG_ENDIAN 1
707 #define MAX_BITS_PER_WORD 64
709 /* Width in bits of an `int'. We want just 32-bits, even if words are
711 #define INT_TYPE_SIZE 32
713 /* Width in bits of a `long'. */
714 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
716 /* Width in bits of a `long long'. */
717 #define LONG_LONG_TYPE_SIZE 64
719 /* Width in bits of a `long double'. */
720 #define LONG_DOUBLE_TYPE_SIZE 64
722 /* Width of a word, in units (bytes). */
723 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
724 #define MIN_UNITS_PER_WORD 4
726 /* Scaling factor for Dwarf data offsets for CFI information.
727 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
728 SHmedia; however, since we do partial register saves for the registers
729 visible to SHcompact, and for target registers for SHMEDIA32, we have
730 to allow saves that are only 4-byte aligned. */
731 #define DWARF_CIE_DATA_ALIGNMENT -4
733 /* Width in bits of a pointer.
734 See also the macro `Pmode' defined below. */
735 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
737 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
738 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
740 /* Boundary (in *bits*) on which stack pointer should be aligned. */
741 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
743 /* The log (base 2) of the cache line size, in bytes. Processors prior to
744 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
745 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
746 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
748 /* ABI given & required minimum allocation boundary (in *bits*) for the
749 code of a function. */
750 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
752 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
753 the vbit must go into the delta field of
754 pointers-to-member-functions. */
755 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
756 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
758 /* Alignment of field after `int : 0' in a structure. */
759 #define EMPTY_FIELD_BOUNDARY 32
761 /* No data type wants to be aligned rounder than this. */
762 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
764 /* The best alignment to use in cases where we have a choice. */
765 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
767 /* Make strings word-aligned so strcpy from constants will be faster. */
768 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
769 ((TREE_CODE (EXP) == STRING_CST \
770 && (ALIGN) < FASTEST_ALIGNMENT) \
771 ? FASTEST_ALIGNMENT : (ALIGN))
773 /* get_mode_alignment assumes complex values are always held in multiple
774 registers, but that is not the case on the SH; CQImode and CHImode are
775 held in a single integer register. SH5 also holds CSImode and SCmode
776 values in integer registers. This is relevant for argument passing on
777 SHcompact as we use a stack temp in order to pass CSImode by reference. */
778 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
779 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
780 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
781 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
784 /* Make arrays of chars word-aligned for the same reasons. */
785 #define DATA_ALIGNMENT(TYPE, ALIGN) \
786 (TREE_CODE (TYPE) == ARRAY_TYPE \
787 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
788 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
790 /* Number of bits which any structure or union's size must be a
791 multiple of. Each structure or union's size is rounded up to a
793 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
795 /* Set this nonzero if move instructions will actually fail to work
796 when given unaligned data. */
797 #define STRICT_ALIGNMENT 1
799 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
800 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
801 barrier_align (LABEL_AFTER_BARRIER)
803 #define LOOP_ALIGN(A_LABEL) \
804 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
805 ? 0 : sh_loop_align (A_LABEL))
807 #define LABEL_ALIGN(A_LABEL) \
809 (PREV_INSN (A_LABEL) \
810 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
811 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
812 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
813 /* explicit alignment insn in constant tables. */ \
814 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
817 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
818 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
820 /* The base two logarithm of the known minimum alignment of an insn length. */
821 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
822 (GET_CODE (A_INSN) == INSN \
823 ? 1 << TARGET_SHMEDIA \
824 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
825 ? 1 << TARGET_SHMEDIA \
828 /* Standard register usage. */
830 /* Register allocation for the Renesas calling convention:
836 r14 frame pointer/call saved
838 ap arg pointer (doesn't really exist, always eliminated)
839 pr subroutine return address
841 mach multiply/accumulate result, high part
842 macl multiply/accumulate result, low part.
843 fpul fp/int communication register
844 rap return address pointer register
846 fr1..fr3 scratch floating point registers
848 fr12..fr15 call saved floating point registers */
850 #define MAX_REGISTER_NAME_LENGTH 5
851 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
853 #define SH_REGISTER_NAMES_INITIALIZER \
855 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
856 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
857 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
858 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
859 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
860 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
861 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
862 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
863 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
864 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
865 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
866 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
867 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
868 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
869 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
870 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
871 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
872 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
873 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
877 #define REGNAMES_ARR_INDEX_1(index) \
878 (sh_register_names[index])
879 #define REGNAMES_ARR_INDEX_2(index) \
880 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
881 #define REGNAMES_ARR_INDEX_4(index) \
882 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
883 #define REGNAMES_ARR_INDEX_8(index) \
884 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
885 #define REGNAMES_ARR_INDEX_16(index) \
886 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
887 #define REGNAMES_ARR_INDEX_32(index) \
888 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
889 #define REGNAMES_ARR_INDEX_64(index) \
890 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
892 #define REGISTER_NAMES \
894 REGNAMES_ARR_INDEX_64 (0), \
895 REGNAMES_ARR_INDEX_64 (64), \
896 REGNAMES_ARR_INDEX_8 (128), \
897 REGNAMES_ARR_INDEX_8 (136), \
898 REGNAMES_ARR_INDEX_8 (144), \
899 REGNAMES_ARR_INDEX_1 (152) \
902 #define ADDREGNAMES_SIZE 32
903 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
904 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
905 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
907 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
909 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
910 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
911 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
912 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
915 #define ADDREGNAMES_REGNO(index) \
916 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
919 #define ADDREGNAMES_ARR_INDEX_1(index) \
920 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
921 #define ADDREGNAMES_ARR_INDEX_2(index) \
922 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
923 #define ADDREGNAMES_ARR_INDEX_4(index) \
924 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
925 #define ADDREGNAMES_ARR_INDEX_8(index) \
926 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
927 #define ADDREGNAMES_ARR_INDEX_16(index) \
928 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
929 #define ADDREGNAMES_ARR_INDEX_32(index) \
930 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
932 #define ADDITIONAL_REGISTER_NAMES \
934 ADDREGNAMES_ARR_INDEX_32 (0) \
937 /* Number of actual hardware registers.
938 The hardware registers are assigned numbers for the compiler
939 from 0 to just below FIRST_PSEUDO_REGISTER.
940 All registers that the compiler knows about must be given numbers,
941 even those that are not normally considered general registers. */
943 /* There are many other relevant definitions in sh.md's md_constants. */
945 #define FIRST_GENERAL_REG R0_REG
946 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
947 #define FIRST_FP_REG DR0_REG
948 #define LAST_FP_REG (FIRST_FP_REG + \
949 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
950 #define FIRST_XD_REG XD0_REG
951 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
952 #define FIRST_TARGET_REG TR0_REG
953 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
955 #define GENERAL_REGISTER_P(REGNO) \
957 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
958 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
960 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
961 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
963 #define FP_REGISTER_P(REGNO) \
964 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
966 #define XD_REGISTER_P(REGNO) \
967 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
969 #define FP_OR_XD_REGISTER_P(REGNO) \
970 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
972 #define FP_ANY_REGISTER_P(REGNO) \
973 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
975 #define SPECIAL_REGISTER_P(REGNO) \
976 ((REGNO) == GBR_REG || (REGNO) == T_REG \
977 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
979 #define TARGET_REGISTER_P(REGNO) \
980 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
982 #define SHMEDIA_REGISTER_P(REGNO) \
983 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
984 || TARGET_REGISTER_P (REGNO))
986 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
987 that should be fixed. */
988 #define VALID_REGISTER_P(REGNO) \
989 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
990 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
991 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
992 || (TARGET_SH2E && (REGNO) == FPUL_REG))
994 /* The mode that should be generally used to store a register by
995 itself in the stack, or to load it back. */
996 #define REGISTER_NATURAL_MODE(REGNO) \
997 (FP_REGISTER_P (REGNO) ? SFmode \
998 : XD_REGISTER_P (REGNO) ? DFmode \
999 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1003 #define FIRST_PSEUDO_REGISTER 153
1005 /* 1 for registers that have pervasive standard uses
1006 and are not available for the register allocator.
1008 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1009 It is 32 bits wide for SH2. */
1011 #define FIXED_REGISTERS \
1013 /* Regular registers. */ \
1014 0, 0, 0, 0, 0, 0, 0, 0, \
1015 0, 0, 0, 0, 0, 0, 0, 1, \
1016 /* r16 is reserved, r18 is the former pr. */ \
1017 1, 0, 0, 0, 0, 0, 0, 0, \
1018 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1019 /* r26 is a global variable data pointer; r27 is for constants. */ \
1020 1, 1, 1, 1, 0, 0, 0, 0, \
1021 0, 0, 0, 0, 0, 0, 0, 0, \
1022 0, 0, 0, 0, 0, 0, 0, 0, \
1023 0, 0, 0, 0, 0, 0, 0, 0, \
1024 0, 0, 0, 0, 0, 0, 0, 1, \
1025 /* FP registers. */ \
1026 0, 0, 0, 0, 0, 0, 0, 0, \
1027 0, 0, 0, 0, 0, 0, 0, 0, \
1028 0, 0, 0, 0, 0, 0, 0, 0, \
1029 0, 0, 0, 0, 0, 0, 0, 0, \
1030 0, 0, 0, 0, 0, 0, 0, 0, \
1031 0, 0, 0, 0, 0, 0, 0, 0, \
1032 0, 0, 0, 0, 0, 0, 0, 0, \
1033 0, 0, 0, 0, 0, 0, 0, 0, \
1034 /* Branch target registers. */ \
1035 0, 0, 0, 0, 0, 0, 0, 0, \
1036 /* XD registers. */ \
1037 0, 0, 0, 0, 0, 0, 0, 0, \
1038 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1039 1, 1, 1, 1, 1, 1, 0, 1, \
1044 /* 1 for registers not available across function calls.
1045 These must include the FIXED_REGISTERS and also any
1046 registers that can be used without being saved.
1047 The latter must include the registers where values are returned
1048 and the register where structure-value addresses are passed.
1049 Aside from that, you can include as many other registers as you like. */
1051 #define CALL_USED_REGISTERS \
1053 /* Regular registers. */ \
1054 1, 1, 1, 1, 1, 1, 1, 1, \
1055 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1056 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1057 across SH5 function calls. */ \
1058 0, 0, 0, 0, 0, 0, 0, 1, \
1059 1, 1, 1, 1, 1, 1, 1, 1, \
1060 1, 1, 1, 1, 0, 0, 0, 0, \
1061 0, 0, 0, 0, 1, 1, 1, 1, \
1062 1, 1, 1, 1, 0, 0, 0, 0, \
1063 0, 0, 0, 0, 0, 0, 0, 0, \
1064 0, 0, 0, 0, 1, 1, 1, 1, \
1065 /* FP registers. */ \
1066 1, 1, 1, 1, 1, 1, 1, 1, \
1067 1, 1, 1, 1, 0, 0, 0, 0, \
1068 1, 1, 1, 1, 1, 1, 1, 1, \
1069 1, 1, 1, 1, 1, 1, 1, 1, \
1070 1, 1, 1, 1, 0, 0, 0, 0, \
1071 0, 0, 0, 0, 0, 0, 0, 0, \
1072 0, 0, 0, 0, 0, 0, 0, 0, \
1073 0, 0, 0, 0, 0, 0, 0, 0, \
1074 /* Branch target registers. */ \
1075 1, 1, 1, 1, 1, 0, 0, 0, \
1076 /* XD registers. */ \
1077 1, 1, 1, 1, 1, 1, 0, 0, \
1078 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1079 1, 1, 1, 1, 1, 1, 1, 1, \
1084 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1085 across SHcompact function calls. We can't tell whether a called
1086 function is SHmedia or SHcompact, so we assume it may be when
1087 compiling SHmedia code with the 32-bit ABI, since that's the only
1088 ABI that can be linked with SHcompact code. */
1089 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1091 && GET_MODE_SIZE (MODE) > 4 \
1092 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1093 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1094 || TARGET_REGISTER_P (REGNO) \
1095 || (REGNO) == PR_MEDIA_REG))
1097 /* Return number of consecutive hard regs needed starting at reg REGNO
1098 to hold something of mode MODE.
1099 This is ordinarily the length in words of a value of mode MODE
1100 but can be less for certain modes in special long registers.
1102 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1104 #define HARD_REGNO_NREGS(REGNO, MODE) \
1105 (XD_REGISTER_P (REGNO) \
1106 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1107 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1108 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1109 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1111 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1112 We can allow any mode in any general register. The special registers
1113 only allow SImode. Don't allow any mode in the PR. */
1115 /* We cannot hold DCmode values in the XD registers because alter_reg
1116 handles subregs of them incorrectly. We could work around this by
1117 spacing the XD registers like the DR registers, but this would require
1118 additional memory in every compilation to hold larger register vectors.
1119 We could hold SFmode / SCmode values in XD registers, but that
1120 would require a tertiary reload when reloading from / to memory,
1121 and a secondary reload to reload from / to general regs; that
1122 seems to be a loosing proposition. */
1123 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1124 it won't be ferried through GP registers first. */
1125 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1126 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1127 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1128 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1130 : (MODE) == V2SFmode \
1131 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1132 || GENERAL_REGISTER_P (REGNO)) \
1133 : (MODE) == V4SFmode \
1134 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1135 || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
1136 : (MODE) == V16SFmode \
1138 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1139 : (REGNO) == FIRST_XD_REG) \
1140 : FP_REGISTER_P (REGNO) \
1141 ? ((MODE) == SFmode || (MODE) == SImode \
1142 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1143 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
1144 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1145 || (MODE) == V2SFmode || (MODE) == TImode))) \
1146 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
1147 : XD_REGISTER_P (REGNO) \
1148 ? (MODE) == DFmode \
1149 : TARGET_REGISTER_P (REGNO) \
1150 ? ((MODE) == DImode || (MODE) == SImode) \
1151 : (REGNO) == PR_REG ? (MODE) == SImode \
1152 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1155 /* Value is 1 if MODE is a supported vector mode. */
1156 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1158 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
1159 || (TARGET_SHMEDIA \
1160 && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
1161 || (MODE) == V2SImode)))
1163 /* Value is 1 if it is a good idea to tie two pseudo registers
1164 when one has mode MODE1 and one has mode MODE2.
1165 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1166 for any hard reg, then this must be 0 for correct output.
1167 That's the case for xd registers: we don't hold SFmode values in
1168 them, so we can't tie an SFmode pseudos with one in another
1169 floating-point mode. */
1171 #define MODES_TIEABLE_P(MODE1, MODE2) \
1172 ((MODE1) == (MODE2) \
1173 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1174 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1175 && (GET_MODE_SIZE (MODE2) <= 4)) \
1176 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1178 /* A C expression that is nonzero if hard register NEW_REG can be
1179 considered for use as a rename register for OLD_REG register */
1181 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1182 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1184 /* Specify the registers used for certain standard purposes.
1185 The values of these macros are register numbers. */
1187 /* Define this if the program counter is overloaded on a register. */
1188 /* #define PC_REGNUM 15*/
1190 /* Register to use for pushing function arguments. */
1191 #define STACK_POINTER_REGNUM SP_REG
1193 /* Base register for access to local variables of the function. */
1194 #define FRAME_POINTER_REGNUM FP_REG
1196 /* Fake register that holds the address on the stack of the
1197 current function's return address. */
1198 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1200 /* Register to hold the addressing base for position independent
1201 code access to data items. */
1202 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1204 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1206 /* Value should be nonzero if functions must have frame pointers.
1207 Zero means the frame pointer need not be set up (and parms may be accessed
1208 via the stack pointer) in functions that seem suitable. */
1210 #define FRAME_POINTER_REQUIRED 0
1212 /* Definitions for register eliminations.
1214 We have three registers that can be eliminated on the SH. First, the
1215 frame pointer register can often be eliminated in favor of the stack
1216 pointer register. Secondly, the argument pointer register can always be
1217 eliminated; it is replaced with either the stack or frame pointer.
1218 Third, there is the return address pointer, which can also be replaced
1219 with either the stack or the frame pointer. */
1221 /* This is an array of structures. Each structure initializes one pair
1222 of eliminable registers. The "from" register number is given first,
1223 followed by "to". Eliminations of the same "from" register are listed
1224 in order of preference. */
1226 /* If you add any registers here that are not actually hard registers,
1227 and that have any alternative of elimination that doesn't always
1228 apply, you need to amend calc_live_regs to exclude it, because
1229 reload spills all eliminable registers where it sees an
1230 can_eliminate == 0 entry, thus making them 'live' .
1231 If you add any hard registers that can be eliminated in different
1232 ways, you have to patch reload to spill them only when all alternatives
1233 of elimination fail. */
1235 #define ELIMINABLE_REGS \
1236 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1237 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1238 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1239 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1240 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1242 /* Given FROM and TO register numbers, say whether this elimination
1244 #define CAN_ELIMINATE(FROM, TO) \
1245 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1247 /* Define the offset between two registers, one to be eliminated, and the other
1248 its replacement, at the start of a routine. */
1250 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1251 OFFSET = initial_elimination_offset ((FROM), (TO))
1253 /* Base register for access to arguments of the function. */
1254 #define ARG_POINTER_REGNUM AP_REG
1256 /* Register in which the static-chain is passed to a function. */
1257 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1259 /* Don't default to pcc-struct-return, because we have already specified
1260 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1263 #define DEFAULT_PCC_STRUCT_RETURN 0
1265 #define SHMEDIA_REGS_STACK_ADJUST() \
1266 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1267 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1268 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1272 /* Define the classes of registers for register constraints in the
1273 machine description. Also define ranges of constants.
1275 One of the classes must always be named ALL_REGS and include all hard regs.
1276 If there is more than one class, another class must be named NO_REGS
1277 and contain no registers.
1279 The name GENERAL_REGS must be the name of a class (or an alias for
1280 another name such as ALL_REGS). This is the class of registers
1281 that is allowed by "g" or "r" in a register constraint.
1282 Also, registers outside this class are allocated only when
1283 instructions express preferences for them.
1285 The classes must be numbered in nondecreasing order; that is,
1286 a larger-numbered class must never be contained completely
1287 in a smaller-numbered class.
1289 For any two classes, it is very desirable that there be another
1290 class that represents their union. */
1292 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1293 be used as the destination of some of the arithmetic ops. There are
1294 also some special purpose registers; the T bit register, the
1295 Procedure Return Register and the Multiply Accumulate Registers. */
1296 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1297 reg_class_subunion. We don't want to have an actual union class
1298 of these, because it would only be used when both classes are calculated
1299 to give the same cost, but there is only one FPUL register.
1300 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1301 applying to the actual instruction alternative considered. E.g., the
1302 y/r alternative of movsi_ie is considered to have no more cost that
1303 the r/r alternative, which is patently untrue. */
1326 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1328 /* Give names of register classes as strings for dump file. */
1329 #define REG_CLASS_NAMES \
1344 "GENERAL_FP_REGS", \
1349 /* Define which registers fit in which classes.
1350 This is an initializer for a vector of HARD_REG_SET
1351 of length N_REG_CLASSES. */
1353 #define REG_CLASS_CONTENTS \
1356 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1358 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1360 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1362 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1364 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1366 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1367 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1368 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1369 /* GENERAL_REGS: */ \
1370 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1372 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1374 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1375 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1376 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1378 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1380 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1381 /* GENERAL_FP_REGS: */ \
1382 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1383 /* TARGET_REGS: */ \
1384 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1386 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1389 /* The same information, inverted:
1390 Return the class number of the smallest class containing
1391 reg number REGNO. This could be a conditional expression
1392 or could index an array. */
1394 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1395 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1397 /* When defined, the compiler allows registers explicitly used in the
1398 rtl to be used as spill registers but prevents the compiler from
1399 extending the lifetime of these registers. */
1401 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1403 /* The order in which register should be allocated. */
1404 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1405 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1406 spilled or used otherwise, we better have the FP_REGS allocated first. */
1407 #define REG_ALLOC_ORDER \
1408 {/* Caller-saved FPRs */ \
1409 65, 66, 67, 68, 69, 70, 71, 64, \
1410 72, 73, 74, 75, 80, 81, 82, 83, \
1411 84, 85, 86, 87, 88, 89, 90, 91, \
1412 92, 93, 94, 95, 96, 97, 98, 99, \
1413 /* Callee-saved FPRs */ \
1414 76, 77, 78, 79,100,101,102,103, \
1415 104,105,106,107,108,109,110,111, \
1416 112,113,114,115,116,117,118,119, \
1417 120,121,122,123,124,125,126,127, \
1418 136,137,138,139,140,141,142,143, \
1420 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1421 1, 2, 3, 7, 6, 5, 4, 0, \
1422 8, 9, 17, 19, 20, 21, 22, 23, \
1423 36, 37, 38, 39, 40, 41, 42, 43, \
1425 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1426 10, 11, 12, 13, 14, 18, \
1427 /* SH5 callee-saved GPRs */ \
1428 28, 29, 30, 31, 32, 33, 34, 35, \
1429 44, 45, 46, 47, 48, 49, 50, 51, \
1430 52, 53, 54, 55, 56, 57, 58, 59, \
1432 /* SH5 branch target registers */ \
1433 128,129,130,131,132,133,134,135, \
1434 /* Fixed registers */ \
1435 15, 16, 24, 25, 26, 27, 63,144, \
1436 145,146,147,148,149,152 }
1438 /* The class value for index registers, and the one for base regs. */
1439 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1440 #define BASE_REG_CLASS GENERAL_REGS
1442 /* Get reg_class from a letter such as appears in the machine
1444 extern enum reg_class reg_class_from_letter[];
1446 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1447 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1448 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1450 /* Overview of uppercase letter constraints:
1451 A: Addresses (constraint len == 3)
1452 Ac4: sh4 cache operations
1453 Ac5: sh5 cache operations
1454 Bxx: miscellaneous constraints
1455 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1457 C: Constants other than only CONST_INT (constraint len == 3)
1458 C16: 16 bit constant, literal or symbolic
1459 Csy: label or symbol
1460 Cpg: non-explicit constants that can be directly loaded into a general
1461 purpose register in PIC code. like 's' except we don't allow
1463 IJKLMNOP: CONT_INT constants
1465 J16: 0xffffffff00000000 | 0x00000000ffffffff
1466 Kxx: unsigned xx bit
1470 Q: pc relative load operand
1471 Rxx: reserved for exotic register classes.
1472 S: extra memory (storage) constraints (constraint len == 3)
1473 Sua: unaligned memory operations
1477 unused CONST_INT constraint letters: LO
1478 unused EXTRA_CONSTRAINT letters: D T U Y */
1480 #if 1 /* check that the transition went well. */
1481 #define CONSTRAINT_LEN(C,STR) \
1482 (((C) == 'L' || (C) == 'O' || (C) == 'D' || (C) == 'T' || (C) == 'U' \
1485 && (((STR)[1] != '0' && (STR)[1] != '1') \
1486 || (STR)[2] < '0' || (STR)[2] > '9')) \
1487 || ((C) == 'B' && ((STR)[1] != 's' || (STR)[2] != 'c')) \
1488 || ((C) == 'J' && ((STR)[1] != '1' || (STR)[2] != '6')) \
1489 || ((C) == 'K' && ((STR)[1] != '0' || (STR)[2] != '8')) \
1490 || ((C) == 'P' && ((STR)[1] != '2' || (STR)[2] != '7'))) \
1492 : ((C) == 'A' || (C) == 'B' || (C) == 'C' \
1493 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1494 || (C) == 'R' || (C) == 'S') \
1496 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1498 #define CONSTRAINT_LEN(C,STR) \
1499 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1500 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1501 || (C) == 'R' || (C) == 'S') \
1502 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1505 /* The letters I, J, K, L and M in a register constraint string
1506 can be used to stand for particular ranges of immediate operands.
1507 This macro defines what the ranges are.
1508 C is the letter, and VALUE is a constant value.
1509 Return 1 if VALUE is in the range specified by C.
1510 I08: arithmetic operand -127..128, as used in add, sub, etc
1511 I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1512 P27: shift operand 1,2,8 or 16
1513 K08: logical operand 0..255, as used in and, or, etc.
1516 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1517 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1520 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1521 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1522 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1523 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1524 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1525 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1526 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1527 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1528 #define CONST_OK_FOR_I(VALUE, STR) \
1529 ((STR)[1] == '0' && (STR)[2] == 6 ? CONST_OK_FOR_I06 (VALUE) \
1530 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1531 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1532 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1535 #define CONST_OK_FOR_J16(VALUE) \
1536 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1537 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1538 #define CONST_OK_FOR_J(VALUE, STR) \
1539 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1542 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1543 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1544 #define CONST_OK_FOR_K(VALUE, STR) \
1545 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1547 #define CONST_OK_FOR_P27(VALUE) \
1548 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1549 #define CONST_OK_FOR_P(VALUE, STR) \
1550 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1552 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1553 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1554 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1555 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1556 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1557 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1558 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1559 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1560 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1563 /* Similar, but for floating constants, and defining letters G and H.
1564 Here VALUE is the CONST_DOUBLE rtx itself. */
1566 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1567 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1568 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1571 /* Given an rtx X being reloaded into a reg required to be
1572 in class CLASS, return the class of reg to actually use.
1573 In general this is just CLASS; but on some machines
1574 in some cases it is preferable to use a more restrictive class. */
1576 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1577 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1578 && (GET_CODE (X) == CONST_DOUBLE \
1579 || GET_CODE (X) == SYMBOL_REF) \
1583 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1584 ((((REGCLASS_HAS_FP_REG (CLASS) \
1585 && (GET_CODE (X) == REG \
1586 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1587 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1588 && TARGET_FMOVD)))) \
1589 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1590 && GET_CODE (X) == REG \
1591 && FP_REGISTER_P (REGNO (X)))) \
1592 && ! TARGET_SHMEDIA \
1593 && ((MODE) == SFmode || (MODE) == SImode)) \
1595 : (((CLASS) == FPUL_REGS \
1596 || (REGCLASS_HAS_FP_REG (CLASS) \
1597 && ! TARGET_SHMEDIA && MODE == SImode)) \
1598 && (GET_CODE (X) == MEM \
1599 || (GET_CODE (X) == REG \
1600 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1601 || REGNO (X) == T_REG \
1602 || system_reg_operand (X, VOIDmode))))) \
1604 : ((CLASS) == TARGET_REGS \
1605 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1606 ? ((target_operand ((X), (MODE)) \
1607 && ! target_reg_operand ((X), (MODE))) \
1608 ? NO_REGS : GENERAL_REGS) \
1609 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1610 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1611 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1613 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1614 && TARGET_REGISTER_P (REGNO (X))) \
1615 ? GENERAL_REGS : NO_REGS)
1617 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1618 ((REGCLASS_HAS_FP_REG (CLASS) \
1619 && ! TARGET_SHMEDIA \
1620 && immediate_operand ((X), (MODE)) \
1621 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1622 && (MODE) == SFmode && fldi_ok ())) \
1624 : (CLASS == FPUL_REGS \
1625 && ((GET_CODE (X) == REG \
1626 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1627 || REGNO (X) == T_REG)) \
1628 || GET_CODE (X) == PLUS)) \
1630 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1631 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1634 : (CLASS == FPSCR_REGS \
1635 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1636 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1638 : (REGCLASS_HAS_FP_REG (CLASS) \
1640 && immediate_operand ((X), (MODE)) \
1641 && (X) != CONST0_RTX (GET_MODE (X)) \
1642 && GET_MODE (X) != V4SFmode) \
1644 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1646 /* Return the maximum number of consecutive registers
1647 needed to represent mode MODE in a register of class CLASS.
1649 If TARGET_SHMEDIA, we need two FP registers per word.
1650 Otherwise we will need at most one register per word. */
1651 #define CLASS_MAX_NREGS(CLASS, MODE) \
1653 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1654 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1655 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1657 /* If defined, gives a class of registers that cannot be used as the
1658 operand of a SUBREG that changes the mode of the object illegally. */
1659 /* ??? We need to renumber the internal numbers for the frnn registers
1660 when in little endian in order to allow mode size changes. */
1662 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1663 sh_cannot_change_mode_class (FROM, TO, CLASS)
1665 /* Stack layout; function entry, exit and calling. */
1667 /* Define the number of registers that can hold parameters.
1668 These macros are used only in other macro definitions below. */
1670 #define NPARM_REGS(MODE) \
1671 (TARGET_FPU_ANY && (MODE) == SFmode \
1672 ? (TARGET_SH5 ? 12 : 8) \
1673 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1674 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1675 ? (TARGET_SH5 ? 12 : 8) \
1676 : (TARGET_SH5 ? 8 : 4))
1678 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1679 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1681 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1682 #define FIRST_FP_RET_REG FIRST_FP_REG
1684 /* Define this if pushing a word on the stack
1685 makes the stack pointer a smaller address. */
1686 #define STACK_GROWS_DOWNWARD
1688 /* Define this macro if the addresses of local variable slots are at
1689 negative offsets from the frame pointer.
1691 The SH only has positive indexes, so grow the frame up. */
1692 /* #define FRAME_GROWS_DOWNWARD */
1694 /* Offset from the frame pointer to the first local variable slot to
1696 #define STARTING_FRAME_OFFSET 0
1698 /* If we generate an insn to push BYTES bytes,
1699 this says how many the stack pointer really advances by. */
1700 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1701 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1702 do correct alignment. */
1704 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1707 /* Offset of first parameter from the argument pointer register value. */
1708 #define FIRST_PARM_OFFSET(FNDECL) 0
1710 /* Value is the number of byte of arguments automatically
1711 popped when returning from a subroutine call.
1712 FUNDECL is the declaration node of the function (as a tree),
1713 FUNTYPE is the data type of the function (as a tree),
1714 or for a library call it is an identifier node for the subroutine name.
1715 SIZE is the number of bytes of arguments passed on the stack.
1717 On the SH, the caller does not pop any of its arguments that were passed
1719 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1721 /* Value is the number of bytes of arguments automatically popped when
1722 calling a subroutine.
1723 CUM is the accumulated argument list.
1725 On SHcompact, the call trampoline pops arguments off the stack. */
1726 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1728 /* Some subroutine macros specific to this machine. */
1730 #define BASE_RETURN_VALUE_REG(MODE) \
1731 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1732 ? FIRST_FP_RET_REG \
1733 : TARGET_FPU_ANY && (MODE) == SCmode \
1734 ? FIRST_FP_RET_REG \
1735 : (TARGET_FPU_DOUBLE \
1736 && ((MODE) == DFmode || (MODE) == SFmode \
1737 || (MODE) == DCmode || (MODE) == SCmode )) \
1738 ? FIRST_FP_RET_REG \
1741 #define BASE_ARG_REG(MODE) \
1742 ((TARGET_SH2E && ((MODE) == SFmode)) \
1743 ? FIRST_FP_PARM_REG \
1744 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1745 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1746 ? FIRST_FP_PARM_REG \
1749 /* Define how to find the value returned by a function.
1750 VALTYPE is the data type of the value (as a tree).
1751 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1752 otherwise, FUNC is 0.
1753 For the SH, this is like LIBCALL_VALUE, except that we must change the
1754 mode like PROMOTE_MODE does.
1755 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1756 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1758 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1760 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1761 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1762 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1763 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1764 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1765 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1766 || TREE_CODE (VALTYPE) == REAL_TYPE \
1767 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1768 && sh_promote_prototypes (VALTYPE) \
1769 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1770 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1772 /* Define how to find the value returned by a library function
1773 assuming the value has mode MODE. */
1774 #define LIBCALL_VALUE(MODE) \
1775 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1777 /* 1 if N is a possible register number for a function value. */
1778 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1779 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1780 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1782 /* 1 if N is a possible register number for function argument passing. */
1783 /* ??? There are some callers that pass REGNO as int, and others that pass
1784 it as unsigned. We get warnings unless we do casts everywhere. */
1785 #define FUNCTION_ARG_REGNO_P(REGNO) \
1786 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1787 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1788 || (TARGET_FPU_ANY \
1789 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1790 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1791 + NPARM_REGS (SFmode))))
1793 /* Define a data type for recording info about an argument list
1794 during the scan of that argument list. This data type should
1795 hold all necessary information about the function itself
1796 and about the args processed so far, enough to enable macros
1797 such as FUNCTION_ARG to determine where the next arg should go.
1799 On SH, this is a single integer, which is a number of words
1800 of arguments scanned so far (including the invisible argument,
1801 if any, which holds the structure-value-address).
1802 Thus NARGREGS or more means all following args should go on the stack. */
1804 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1808 /* Nonzero if a prototype is available for the function. */
1810 /* The number of an odd floating-point register, that should be used
1811 for the next argument of type float. */
1812 int free_single_fp_reg;
1813 /* Whether we're processing an outgoing function call. */
1815 /* The number of general-purpose registers that should have been
1816 used to pass partial arguments, that are passed totally on the
1817 stack. On SHcompact, a call trampoline will pop them off the
1818 stack before calling the actual function, and, if the called
1819 function is implemented in SHcompact mode, the incoming arguments
1820 decoder will push such arguments back onto the stack. For
1821 incoming arguments, STACK_REGS also takes into account other
1822 arguments passed by reference, that the decoder will also push
1825 /* The number of general-purpose registers that should have been
1826 used to pass arguments, if the arguments didn't have to be passed
1829 /* Set by SHCOMPACT_BYREF if the current argument is to be passed by
1833 /* call_cookie is a bitmask used by call expanders, as well as
1834 function prologue and epilogues, to allow SHcompact to comply
1835 with the SH5 32-bit ABI, that requires 64-bit registers to be
1836 used even though only the lower 32-bit half is visible in
1837 SHcompact mode. The strategy is to call SHmedia trampolines.
1839 The alternatives for each of the argument-passing registers are
1840 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1841 contents from the address in it; (d) add 8 to it, storing the
1842 result in the next register, then (c); (e) copy it from some
1843 floating-point register,
1845 Regarding copies from floating-point registers, r2 may only be
1846 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1847 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1848 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1849 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1852 The bit mask is structured as follows:
1854 - 1 bit to tell whether to set up a return trampoline.
1856 - 3 bits to count the number consecutive registers to pop off the
1859 - 4 bits for each of r9, r8, r7 and r6.
1861 - 3 bits for each of r5, r4, r3 and r2.
1863 - 3 bits set to 0 (the most significant ones)
1866 1098 7654 3210 9876 5432 1098 7654 3210
1867 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1868 2223 3344 4555 6666 7777 8888 9999 SSS-
1870 - If F is set, the register must be copied from an FP register,
1871 whose number is encoded in the remaining bits.
1873 - Else, if L is set, the register must be loaded from the address
1874 contained in it. If the P bit is *not* set, the address of the
1875 following dword should be computed first, and stored in the
1878 - Else, if P is set, the register alone should be popped off the
1881 - After all this processing, the number of registers represented
1882 in SSS will be popped off the stack. This is an optimization
1883 for pushing/popping consecutive registers, typically used for
1884 varargs and large arguments partially passed in registers.
1886 - If T is set, a return trampoline will be set up for 64-bit
1887 return values to be split into 2 32-bit registers. */
1888 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1889 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1890 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1891 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1892 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1893 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1894 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1895 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1896 #define CALL_COOKIE_INT_REG(REG, VAL) \
1897 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1898 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1899 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1902 /* This is set to nonzero when the call in question must use the Renesas ABI,
1903 even without the -mrenesas option. */
1907 #define CUMULATIVE_ARGS struct sh_args
1909 #define GET_SH_ARG_CLASS(MODE) \
1910 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1912 /* There's no mention of complex float types in the SH5 ABI, so we
1913 should presumably handle them as aggregate types. */ \
1914 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1916 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1917 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1918 ? SH_ARG_FLOAT : SH_ARG_INT)
1920 #define ROUND_ADVANCE(SIZE) \
1921 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1923 /* Round a register number up to a proper boundary for an arg of mode
1926 The SH doesn't care about double alignment, so we only
1927 round doubles to even regs when asked to explicitly. */
1929 #define ROUND_REG(CUM, MODE) \
1930 (((TARGET_ALIGN_DOUBLE \
1931 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1932 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1933 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1934 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1935 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1936 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1938 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1939 for a call to a function whose data type is FNTYPE.
1940 For a library call, FNTYPE is 0.
1942 On SH, the offset always starts at 0: the first parm reg is always
1943 the same reg for a given argument class.
1945 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1947 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1949 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1950 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
1951 (CUM).renesas_abi = sh_attr_renesas_p (FNTYPE) ? 1 : 0; \
1953 = ((TARGET_HITACHI || (CUM).renesas_abi) && (FNTYPE) \
1954 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
1955 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
1956 (CUM).arg_count[(int) SH_ARG_INT] \
1957 = (TARGET_SH5 && (FNTYPE) \
1958 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
1959 (CUM).free_single_fp_reg = 0; \
1960 (CUM).outgoing = 1; \
1961 (CUM).stack_regs = 0; \
1962 (CUM).byref_regs = 0; \
1965 = (CALL_COOKIE_RET_TRAMP \
1966 (TARGET_SHCOMPACT && (FNTYPE) \
1967 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
1968 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
1969 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
1970 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
1971 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
1973 == FIRST_RET_REG))); \
1976 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1978 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0, 0); \
1980 = (CALL_COOKIE_RET_TRAMP \
1981 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
1982 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
1985 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1987 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0, 0); \
1988 (CUM).outgoing = 0; \
1991 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1992 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1993 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1994 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1996 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1997 This macro is only used in this file. */
1999 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
2001 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
2002 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
2003 || ! (AGGREGATE_TYPE_P (TYPE) \
2004 || (!TARGET_FPU_ANY \
2005 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2006 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
2007 && ! (CUM).force_mem \
2009 ? ((MODE) == BLKmode \
2010 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2011 + int_size_in_bytes (TYPE)) \
2012 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2013 : ((ROUND_REG((CUM), (MODE)) \
2014 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2015 <= NPARM_REGS (MODE))) \
2016 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
2018 /* By accident we got stuck with passing SCmode on SH4 little endian
2019 in two registers that are nominally successive - which is different from
2020 two single SFmode values, where we take endianness translation into
2021 account. That does not work at all if an odd number of registers is
2022 already in use, so that got fixed, but library functions are still more
2023 likely to use complex numbers without mixing them with SFmode arguments
2024 (which in C would have to be structures), so for the sake of ABI
2025 compatibility the way SCmode values are passed when an even number of
2026 FP registers is in use remains different from a pair of SFmode values for
2029 foo (double); a: fr5,fr4
2030 foo (float a, float b); a: fr5 b: fr4
2031 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2032 this should be the other way round...
2033 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2034 #define FUNCTION_ARG_SCmode_WART 1
2036 /* Whether an argument must be passed by reference. On SHcompact, we
2037 pretend arguments wider than 32-bits that would have been passed in
2038 registers are passed by reference, so that an SHmedia trampoline
2039 loads them into the full 64-bits registers. */
2040 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM,MODE,TYPE,NAMED) \
2041 (targetm.calls.must_pass_in_stack ((MODE), (TYPE)) \
2042 || SHCOMPACT_BYREF ((CUM), (MODE), (TYPE), (NAMED)))
2044 #define SHCOMPACT_BYREF(CUM, MODE, TYPE, NAMED) \
2046 = (TARGET_SHCOMPACT \
2047 && (CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2048 && (! (NAMED) || GET_SH_ARG_CLASS (MODE) == SH_ARG_INT \
2049 || (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
2050 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
2051 >= NPARM_REGS (SFmode)))) \
2052 && ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2053 : GET_MODE_SIZE (MODE)) > 4 \
2054 && ! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
2055 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
2057 ? ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2058 : GET_MODE_SIZE (MODE)) \
2061 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2062 register in SHcompact mode, it must be padded in the most
2063 significant end. This means that passing it by reference wouldn't
2064 pad properly on a big-endian machine. In this particular case, we
2065 pass this argument on the stack, in a way that the call trampoline
2066 will load its value into the appropriate register. */
2067 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2068 ((MODE) == BLKmode \
2069 && TARGET_SHCOMPACT \
2070 && ! TARGET_LITTLE_ENDIAN \
2071 && int_size_in_bytes (TYPE) > 4 \
2072 && int_size_in_bytes (TYPE) < 8)
2074 /* Minimum alignment for an argument to be passed by callee-copy
2075 reference. We need such arguments to be aligned to 8 byte
2076 boundaries, because they'll be loaded using quad loads. */
2077 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2079 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
2081 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
2082 : GET_MODE_ALIGNMENT (MODE)) \
2083 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
2085 /* The SH5 ABI requires floating-point arguments to be passed to
2086 functions without a prototype in both an FP register and a regular
2087 register or the stack. When passing the argument in both FP and
2088 general-purpose registers, list the FP register first. */
2089 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2095 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2096 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2097 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2102 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2103 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2104 + (CUM).arg_count[(int) SH_ARG_INT]) \
2105 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2106 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2109 /* The SH5 ABI requires regular registers or stack slots to be
2110 reserved for floating-point arguments. Registers are taken care of
2111 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2112 Unfortunately, there's no way to just reserve a stack slot, so
2113 we'll end up needlessly storing a copy of the argument in the
2114 stack. For incoming arguments, however, the PARALLEL will be
2115 optimized to the register-only form, and the value in the stack
2116 slot won't be used at all. */
2117 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2118 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2119 ? gen_rtx_REG ((MODE), (REG)) \
2120 : gen_rtx_PARALLEL ((MODE), \
2123 (VOIDmode, NULL_RTX, \
2126 (VOIDmode, gen_rtx_REG ((MODE), \
2130 /* For an arg passed partly in registers and partly in memory,
2131 this is the number of registers used.
2132 For args passed entirely in registers or entirely in memory, zero.
2134 We sometimes split args. */
2136 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2138 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2140 && (ROUND_REG ((CUM), (MODE)) \
2141 + ((MODE) != BLKmode \
2142 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
2143 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
2144 > NPARM_REGS (MODE))) \
2145 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
2146 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
2147 && ! TARGET_SHCOMPACT) \
2148 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
2151 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2153 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2154 || (MODE) == DCmode) \
2155 && ((CUM).arg_count[(int) SH_ARG_INT] \
2156 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2158 /* Perform any needed actions needed for a function that is receiving a
2159 variable number of arguments. */
2161 /* Implement `va_start' for varargs and stdarg. */
2162 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2163 sh_va_start (valist, nextarg)
2165 /* Call the function profiler with a given profile label.
2166 We use two .aligns, so as to make sure that both the .long is aligned
2167 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2168 from the trapa instruction. */
2170 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2172 fprintf((STREAM), "\t.align\t2\n"); \
2173 fprintf((STREAM), "\ttrapa\t#33\n"); \
2174 fprintf((STREAM), "\t.align\t2\n"); \
2175 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2178 /* Define this macro if the code for function profiling should come
2179 before the function prologue. Normally, the profiling code comes
2182 #define PROFILE_BEFORE_PROLOGUE
2184 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2185 the stack pointer does not matter. The value is tested only in
2186 functions that have frame pointers.
2187 No definition is equivalent to always zero. */
2189 #define EXIT_IGNORE_STACK 1
2192 On the SH, the trampoline looks like
2193 2 0002 D202 mov.l l2,r2
2194 1 0000 D301 mov.l l1,r3
2197 5 0008 00000000 l1: .long area
2198 6 000c 00000000 l2: .long function */
2200 /* Length in units of the trampoline for entering a nested function. */
2201 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2203 /* Alignment required for a trampoline in bits . */
2204 #define TRAMPOLINE_ALIGNMENT \
2205 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2206 : TARGET_SHMEDIA ? 256 : 64)
2208 /* Emit RTL insns to initialize the variable parts of a trampoline.
2209 FNADDR is an RTX for the address of the function's pure code.
2210 CXT is an RTX for the static chain value for the function. */
2212 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2213 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2215 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2217 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2219 if (TARGET_SHMEDIA) \
2220 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2221 gen_reg_rtx (Pmode), 0, \
2225 /* A C expression whose value is RTL representing the value of the return
2226 address for the frame COUNT steps up from the current frame.
2227 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2228 can ignore COUNT. */
2230 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2231 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2233 /* A C expression whose value is RTL representing the location of the
2234 incoming return address at the beginning of any function, before the
2235 prologue. This RTL is either a REG, indicating that the return
2236 value is saved in REG, or a MEM representing a location in
2238 #define INCOMING_RETURN_ADDR_RTX \
2239 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2241 /* Addressing modes, and classification of registers for them. */
2242 #define HAVE_POST_INCREMENT TARGET_SH1
2243 #define HAVE_PRE_DECREMENT TARGET_SH1
2245 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2247 #define USE_LOAD_PRE_DECREMENT(mode) 0
2248 #define USE_STORE_POST_INCREMENT(mode) 0
2249 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2252 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2253 < (TARGET_SMALLCODE ? 2 : \
2254 ((ALIGN >= 32) ? 16 : 2)))
2256 /* Macros to check register numbers against specific register classes. */
2258 /* These assume that REGNO is a hard or pseudo reg number.
2259 They give nonzero only if REGNO is a hard reg of the suitable class
2260 or a pseudo reg currently allocated to a suitable hard reg.
2261 Since they use reg_renumber, they are safe only once reg_renumber
2262 has been allocated, which happens in local-alloc.c. */
2264 #define REGNO_OK_FOR_BASE_P(REGNO) \
2265 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2266 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2267 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2269 ? (GENERAL_REGISTER_P (REGNO) \
2270 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2271 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2273 /* Maximum number of registers that can appear in a valid memory
2276 #define MAX_REGS_PER_ADDRESS 2
2278 /* Recognize any constant value that is a valid address. */
2280 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2282 /* Nonzero if the constant value X is a legitimate general operand. */
2284 #define LEGITIMATE_CONSTANT_P(X) \
2286 ? ((GET_MODE (X) != DFmode \
2287 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2288 || (X) == CONST0_RTX (GET_MODE (X)) \
2289 || ! TARGET_SHMEDIA_FPU \
2290 || TARGET_SHMEDIA64) \
2291 : (GET_CODE (X) != CONST_DOUBLE \
2292 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2293 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2295 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2296 and check its validity for a certain class.
2297 We have two alternate definitions for each of them.
2298 The usual definition accepts all pseudo regs; the other rejects
2299 them unless they have been allocated suitable hard regs.
2300 The symbol REG_OK_STRICT causes the latter definition to be used. */
2302 #ifndef REG_OK_STRICT
2304 /* Nonzero if X is a hard reg that can be used as a base reg
2305 or if it is a pseudo reg. */
2306 #define REG_OK_FOR_BASE_P(X) \
2307 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2309 /* Nonzero if X is a hard reg that can be used as an index
2310 or if it is a pseudo reg. */
2311 #define REG_OK_FOR_INDEX_P(X) \
2312 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2313 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2315 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2316 or if X is a pseudo reg. */
2317 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2318 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2319 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2323 /* Nonzero if X is a hard reg that can be used as a base reg. */
2324 #define REG_OK_FOR_BASE_P(X) \
2325 REGNO_OK_FOR_BASE_P (REGNO (X))
2327 /* Nonzero if X is a hard reg that can be used as an index. */
2328 #define REG_OK_FOR_INDEX_P(X) \
2329 REGNO_OK_FOR_INDEX_P (REGNO (X))
2331 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2332 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2333 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2337 /* The 'Q' constraint is a pc relative load operand. */
2338 #define EXTRA_CONSTRAINT_Q(OP) \
2339 (GET_CODE (OP) == MEM \
2340 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2341 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2342 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2343 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2344 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2346 /* Extra address constraints. */
2347 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2349 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2350 operand is not SCRATCH (i.e. REG) then R0 is probably being
2351 used, hence mova is being used, hence do not select this pattern */
2352 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2353 #define EXTRA_CONSTRAINT_B(OP, STR) \
2354 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2357 /* The `C16' constraint is a 16-bit constant, literal or symbolic. */
2358 #define EXTRA_CONSTRAINT_C16(OP) \
2359 (GET_CODE (OP) == CONST \
2360 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2361 && GET_MODE (XEXP ((OP), 0)) == DImode \
2362 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2363 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2364 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2365 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2366 && (MOVI_SHORI_BASE_OPERAND_P \
2367 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2368 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2371 /* Check whether OP is a datalabel unspec. */
2372 #define DATALABEL_REF_NO_CONST_P(OP) \
2373 (GET_CODE (OP) == UNSPEC \
2374 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2375 && XVECLEN ((OP), 0) == 1 \
2376 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2377 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2379 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2381 #define DATALABEL_REF_P(OP) \
2382 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2383 || DATALABEL_REF_NO_CONST_P (OP))
2385 #define GOT_ENTRY_P(OP) \
2386 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2387 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2389 #define GOTPLT_ENTRY_P(OP) \
2390 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2391 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2393 #define UNSPEC_GOTOFF_P(OP) \
2394 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2396 #define GOTOFF_P(OP) \
2397 (GET_CODE (OP) == CONST \
2398 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2399 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2400 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2401 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2403 #define PIC_ADDR_P(OP) \
2404 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2405 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2407 #define PIC_OFFSET_P(OP) \
2409 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2410 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2412 #define PIC_DIRECT_ADDR_P(OP) \
2413 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2415 #define NON_PIC_REFERENCE_P(OP) \
2416 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2417 || DATALABEL_REF_P (OP) \
2418 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2419 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2420 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2421 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2423 #define PIC_REFERENCE_P(OP) \
2424 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2425 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2427 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2429 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2430 || PIC_OFFSET_P (OP)) \
2431 : NON_PIC_REFERENCE_P (OP))
2433 /* The `Csy' constraint is a label or a symbol. */
2434 #define EXTRA_CONSTRAINT_Csy(OP) \
2435 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2437 /* A zero in any shape or form. */
2438 #define EXTRA_CONSTRAINT_Z(OP) \
2439 ((OP) == CONST0_RTX (GET_MODE (OP)))
2441 /* Any vector constant we can handle. */
2442 #define EXTRA_CONSTRAINT_W(OP) \
2443 (GET_CODE (OP) == CONST_VECTOR \
2444 && (sh_rep_vec ((OP), VOIDmode) \
2445 || (HOST_BITS_PER_WIDE_INT >= 64 \
2446 ? sh_const_vec ((OP), VOIDmode) \
2447 : sh_1el_vec ((OP), VOIDmode))))
2449 /* A non-explicit constant that can be loaded directly into a general purpose
2450 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2451 #define EXTRA_CONSTRAINT_Cpg(OP) \
2453 && GET_CODE (OP) != CONST_INT \
2454 && GET_CODE (OP) != CONST_DOUBLE \
2456 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2457 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2458 && GET_CODE (OP) != LABEL_REF)))
2459 #define EXTRA_CONSTRAINT_C(OP, STR) \
2460 ((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
2461 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2462 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2465 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2466 #define EXTRA_CONSTRAINT_Sr0(OP) \
2467 (memory_operand((OP), GET_MODE (OP)) \
2468 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2469 #define EXTRA_CONSTRAINT_S(OP, STR) \
2470 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2473 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2474 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2475 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2476 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2477 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2478 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2479 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2480 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2483 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2484 that is a valid memory address for an instruction.
2485 The MODE argument is the machine mode for the MEM expression
2486 that wants to use this address. */
2488 #define MODE_DISP_OK_4(X,MODE) \
2489 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2490 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2492 #define MODE_DISP_OK_8(X,MODE) \
2493 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2494 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2496 #define BASE_REGISTER_RTX_P(X) \
2497 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2498 || (GET_CODE (X) == SUBREG \
2499 && GET_CODE (SUBREG_REG (X)) == REG \
2500 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2502 /* Since this must be r0, which is a single register class, we must check
2503 SUBREGs more carefully, to be sure that we don't accept one that extends
2504 outside the class. */
2505 #define INDEX_REGISTER_RTX_P(X) \
2506 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2507 || (GET_CODE (X) == SUBREG \
2508 && GET_CODE (SUBREG_REG (X)) == REG \
2509 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2511 /* Jump to LABEL if X is a valid address RTX. This must also take
2512 REG_OK_STRICT into account when deciding about valid registers, but it uses
2513 the above macros so we are in luck.
2521 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2522 into the FRx registers. We implement this by setting the maximum offset
2523 to zero when the value is SFmode. This also restricts loading of SFmode
2524 values into the integer registers, but that can't be helped. */
2526 /* The SH allows a displacement in a QI or HI amode, but only when the
2527 other operand is R0. GCC doesn't handle this very well, so we forgo
2530 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2531 DI can be any number 0..60. */
2533 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2535 if (GET_CODE (OP) == CONST_INT) \
2537 if (TARGET_SHMEDIA) \
2539 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2540 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2541 && INTVAL (OP) >= -512 * MODE_SIZE \
2542 && INTVAL (OP) < 512 * MODE_SIZE) \
2547 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2548 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2552 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2554 if (BASE_REGISTER_RTX_P (X)) \
2556 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2557 && ! TARGET_SHMEDIA \
2558 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2560 else if (GET_CODE (X) == PLUS \
2561 && ((MODE) != PSImode || reload_completed)) \
2563 rtx xop0 = XEXP ((X), 0); \
2564 rtx xop1 = XEXP ((X), 1); \
2565 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2566 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2567 if (GET_MODE_SIZE (MODE) <= 4 \
2568 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2569 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
2571 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2573 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2579 /* Try machine-dependent ways of modifying an illegitimate address
2580 to be legitimate. If we find one, return the new, valid address.
2581 This macro is used in only one place: `memory_address' in explow.c.
2583 OLDX is the address as it was before break_out_memory_refs was called.
2584 In some cases it is useful to look at this to decide what needs to be done.
2586 MODE and WIN are passed so that this macro can use
2587 GO_IF_LEGITIMATE_ADDRESS.
2589 It is always safe for this macro to do nothing. It exists to recognize
2590 opportunities to optimize the output.
2592 For the SH, if X is almost suitable for indexing, but the offset is
2593 out of range, convert it into a normal form so that cse has a chance
2594 of reducing the number of address registers used. */
2596 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2599 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2600 if (GET_CODE (X) == PLUS \
2601 && (GET_MODE_SIZE (MODE) == 4 \
2602 || GET_MODE_SIZE (MODE) == 8) \
2603 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2604 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2605 && ! TARGET_SHMEDIA \
2606 && ! (TARGET_SH4 && (MODE) == DFmode) \
2607 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2609 rtx index_rtx = XEXP ((X), 1); \
2610 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2613 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2614 /* On rare occasions, we might get an unaligned pointer \
2615 that is indexed in a way to give an aligned address. \
2616 Therefore, keep the lower two bits in offset_base. */ \
2617 /* Instead of offset_base 128..131 use 124..127, so that \
2618 simple add suffices. */ \
2621 offset_base = ((offset + 4) & ~60) - 4; \
2624 offset_base = offset & ~60; \
2625 /* Sometimes the normal form does not suit DImode. We \
2626 could avoid that by using smaller ranges, but that \
2627 would give less optimized code when SImode is \
2629 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2631 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2632 GEN_INT (offset_base), NULL_RTX, 0, \
2635 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2641 /* A C compound statement that attempts to replace X, which is an address
2642 that needs reloading, with a valid memory address for an operand of
2643 mode MODE. WIN is a C statement label elsewhere in the code.
2645 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2646 of the address. That will allow inheritance of the address reloads. */
2648 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2650 if (GET_CODE (X) == PLUS \
2651 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2652 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2653 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2654 && ! TARGET_SHMEDIA \
2655 && ! (TARGET_SH4 && (MODE) == DFmode) \
2656 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2658 rtx index_rtx = XEXP (X, 1); \
2659 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2662 if (TARGET_SH2E && MODE == SFmode) \
2665 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2666 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2670 /* Instead of offset_base 128..131 use 124..127, so that \
2671 simple add suffices. */ \
2674 offset_base = ((offset + 4) & ~60) - 4; \
2677 offset_base = offset & ~60; \
2678 /* Sometimes the normal form does not suit DImode. We \
2679 could avoid that by using smaller ranges, but that \
2680 would give less optimized code when SImode is \
2682 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2684 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2685 GEN_INT (offset_base)); \
2686 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2687 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2688 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2693 /* We must re-recognize what we created before. */ \
2694 else if (GET_CODE (X) == PLUS \
2695 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2696 && GET_CODE (XEXP (X, 0)) == PLUS \
2697 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2698 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2699 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2700 && ! TARGET_SHMEDIA \
2701 && ! (TARGET_SH2E && MODE == SFmode)) \
2703 /* Because this address is so complex, we know it must have \
2704 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2705 it is already unshared, and needs no further unsharing. */ \
2706 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2707 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2712 /* Go to LABEL if ADDR (a legitimate address expression)
2713 has an effect that depends on the machine mode it is used for.
2715 ??? Strictly speaking, we should also include all indexed addressing,
2716 because the index scale factor is the length of the operand.
2717 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2718 high if we did that. So we rely on reload to fix things up. */
2720 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2722 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2726 /* Specify the machine mode that this machine uses
2727 for the index in the tablejump instruction. */
2728 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2730 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2731 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2732 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2733 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2734 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2735 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2738 /* Define as C expression which evaluates to nonzero if the tablejump
2739 instruction expects the table to contain offsets from the address of the
2741 Do not define this if the table should contain absolute addresses. */
2742 #define CASE_VECTOR_PC_RELATIVE 1
2744 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2745 #define FLOAT_TYPE_SIZE 32
2747 /* Since the SH2e has only `float' support, it is desirable to make all
2748 floating point types equivalent to `float'. */
2749 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4) ? 32 : 64)
2751 /* 'char' is signed by default. */
2752 #define DEFAULT_SIGNED_CHAR 1
2754 /* The type of size_t unsigned int. */
2755 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2758 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2760 #define WCHAR_TYPE "short unsigned int"
2761 #define WCHAR_TYPE_SIZE 16
2763 #define SH_ELF_WCHAR_TYPE "long int"
2765 /* Max number of bytes we can move from memory to memory
2766 in one reasonably fast instruction. */
2767 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2769 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2770 MOVE_MAX is not a compile-time constant. */
2771 #define MAX_MOVE_MAX 8
2773 /* Max number of bytes we want move_by_pieces to be able to copy
2775 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2777 /* Define if operations between registers always perform the operation
2778 on the full register even if a narrower mode is specified. */
2779 #define WORD_REGISTER_OPERATIONS
2781 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2782 will either zero-extend or sign-extend. The value of this macro should
2783 be the code that says which one of the two operations is implicitly
2784 done, NIL if none. */
2785 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2786 /* FP registers can load SImode values, but don't implicitly sign-extend
2788 #define LOAD_EXTEND_OP(MODE) \
2789 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2790 : (MODE) != SImode ? SIGN_EXTEND : NIL)
2792 /* Define if loading short immediate values into registers sign extends. */
2793 #define SHORT_IMMEDIATES_SIGN_EXTEND
2795 /* Nonzero if access to memory by bytes is no faster than for words. */
2796 #define SLOW_BYTE_ACCESS 1
2798 /* Immediate shift counts are truncated by the output routines (or was it
2799 the assembler?). Shift counts in a register are truncated by SH. Note
2800 that the native compiler puts too large (> 32) immediate shift counts
2801 into a register and shifts by the register, letting the SH decide what
2802 to do instead of doing that itself. */
2803 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2804 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2805 expects - the sign bit is significant - so it appears that we need to
2806 leave this zero for correct SH3 code. */
2807 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
2809 /* All integers have the same format so truncation is easy. */
2810 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2812 /* Define this if addresses of constant functions
2813 shouldn't be put through pseudo regs where they can be cse'd.
2814 Desirable on machines where ordinary constants are expensive
2815 but a CALL with constant address is cheap. */
2816 /*#define NO_FUNCTION_CSE 1*/
2818 /* The machine modes of pointers and functions. */
2819 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2820 #define FUNCTION_MODE Pmode
2822 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2823 are actually function calls with some special constraints on arguments
2826 These macros tell reorg that the references to arguments and
2827 register clobbers for insns of type sfunc do not appear to happen
2828 until after the millicode call. This allows reorg to put insns
2829 which set the argument registers into the delay slot of the millicode
2830 call -- thus they act more like traditional CALL_INSNs.
2832 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2833 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2836 #define INSN_SETS_ARE_DELAYED(X) \
2837 ((GET_CODE (X) == INSN \
2838 && GET_CODE (PATTERN (X)) != SEQUENCE \
2839 && GET_CODE (PATTERN (X)) != USE \
2840 && GET_CODE (PATTERN (X)) != CLOBBER \
2841 && get_attr_is_sfunc (X)))
2843 #define INSN_REFERENCES_ARE_DELAYED(X) \
2844 ((GET_CODE (X) == INSN \
2845 && GET_CODE (PATTERN (X)) != SEQUENCE \
2846 && GET_CODE (PATTERN (X)) != USE \
2847 && GET_CODE (PATTERN (X)) != CLOBBER \
2848 && get_attr_is_sfunc (X)))
2851 /* Position Independent Code. */
2853 /* We can't directly access anything that contains a symbol,
2854 nor can we indirect via the constant pool. */
2855 #define LEGITIMATE_PIC_OPERAND_P(X) \
2856 ((! nonpic_symbol_mentioned_p (X) \
2857 && (GET_CODE (X) != SYMBOL_REF \
2858 || ! CONSTANT_POOL_ADDRESS_P (X) \
2859 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2860 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2862 #define SYMBOLIC_CONST_P(X) \
2863 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2864 && nonpic_symbol_mentioned_p (X))
2866 /* Compute extra cost of moving data between one register class
2869 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2870 uses this information. Hence, the general register <-> floating point
2871 register information here is not used for SFmode. */
2873 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2874 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2875 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2877 #define REGCLASS_HAS_FP_REG(CLASS) \
2878 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2879 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2881 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2882 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2884 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2885 would be so that people with slow memory systems could generate
2886 different code that does fewer memory accesses. */
2888 /* A C expression for the cost of a branch instruction. A value of 1
2889 is the default; other values are interpreted relative to that.
2890 The SH1 does not have delay slots, hence we get a pipeline stall
2891 at every branch. The SH4 is superscalar, so the single delay slot
2892 is not sufficient to keep both pipelines filled. */
2893 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2895 /* Assembler output control. */
2897 /* A C string constant describing how to begin a comment in the target
2898 assembler language. The compiler assumes that the comment will end at
2899 the end of the line. */
2900 #define ASM_COMMENT_START "!"
2902 #define ASM_APP_ON ""
2903 #define ASM_APP_OFF ""
2904 #define FILE_ASM_OP "\t.file\n"
2905 #define SET_ASM_OP "\t.set\t"
2907 /* How to change between sections. */
2909 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2910 #define DATA_SECTION_ASM_OP "\t.data"
2912 #if defined CRT_BEGIN || defined CRT_END
2913 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2914 # undef TEXT_SECTION_ASM_OP
2915 # if __SHMEDIA__ == 1 && __SH5__ == 32
2916 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2918 # define TEXT_SECTION_ASM_OP "\t.text"
2923 /* If defined, a C expression whose value is a string containing the
2924 assembler operation to identify the following data as
2925 uninitialized global data. If not defined, and neither
2926 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2927 uninitialized global data will be output in the data section if
2928 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2930 #ifndef BSS_SECTION_ASM_OP
2931 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2934 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2935 separate, explicit argument. If you define this macro, it is used
2936 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2937 handling the required alignment of the variable. The alignment is
2938 specified as the number of bits.
2940 Try to use function `asm_output_aligned_bss' defined in file
2941 `varasm.c' when defining this macro. */
2942 #ifndef ASM_OUTPUT_ALIGNED_BSS
2943 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2944 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2947 /* Define this so that jump tables go in same section as the current function,
2948 which could be text or it could be a user defined section. */
2949 #define JUMP_TABLES_IN_TEXT_SECTION 1
2951 #undef DO_GLOBAL_CTORS_BODY
2952 #define DO_GLOBAL_CTORS_BODY \
2954 typedef (*pfunc)(); \
2955 extern pfunc __ctors[]; \
2956 extern pfunc __ctors_end[]; \
2958 for (p = __ctors_end; p > __ctors; ) \
2964 #undef DO_GLOBAL_DTORS_BODY
2965 #define DO_GLOBAL_DTORS_BODY \
2967 typedef (*pfunc)(); \
2968 extern pfunc __dtors[]; \
2969 extern pfunc __dtors_end[]; \
2971 for (p = __dtors; p < __dtors_end; p++) \
2977 #define ASM_OUTPUT_REG_PUSH(file, v) \
2978 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));
2980 #define ASM_OUTPUT_REG_POP(file, v) \
2981 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
2983 /* DBX register number for a given compiler register number. */
2984 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2986 /* svr4.h undefines this macro, yet we really want to use the same numbers
2987 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2988 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2989 register exists, so we should return -1 for invalid register numbers. */
2990 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2992 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2993 used to use the encodings 245..260, but that doesn't make sense:
2994 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2995 the FP registers stay the same when switching between compact and media
2996 mode. Hence, we also need to use the same dwarf frame columns.
2997 Likewise, we need to support unwind information for SHmedia registers
2998 even in compact code. */
2999 #define SH_DBX_REGISTER_NUMBER(REGNO) \
3000 (IN_RANGE ((REGNO), \
3001 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
3002 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
3003 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
3004 : ((int) (REGNO) >= FIRST_FP_REG \
3006 <= (FIRST_FP_REG + \
3007 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
3008 ? ((unsigned) (REGNO) - FIRST_FP_REG \
3009 + (TARGET_SH5 ? 77 : 25)) \
3010 : XD_REGISTER_P (REGNO) \
3011 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
3012 : TARGET_REGISTER_P (REGNO) \
3013 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
3014 : (REGNO) == PR_REG \
3015 ? (TARGET_SH5 ? 18 : 17) \
3016 : (REGNO) == PR_MEDIA_REG \
3017 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
3018 : (REGNO) == T_REG \
3019 ? (TARGET_SH5 ? 242 : 18) \
3020 : (REGNO) == GBR_REG \
3021 ? (TARGET_SH5 ? 238 : 19) \
3022 : (REGNO) == MACH_REG \
3023 ? (TARGET_SH5 ? 239 : 20) \
3024 : (REGNO) == MACL_REG \
3025 ? (TARGET_SH5 ? 240 : 21) \
3026 : (REGNO) == FPUL_REG \
3027 ? (TARGET_SH5 ? 244 : 23) \
3030 /* This is how to output a reference to a symbol_ref. On SH5,
3031 references to non-code symbols must be preceded by `datalabel'. */
3032 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3035 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3036 fputs ("datalabel ", (FILE)); \
3037 assemble_name ((FILE), XSTR ((SYM), 0)); \
3041 /* This is how to output an assembler line
3042 that says to advance the location counter
3043 to a multiple of 2**LOG bytes. */
3045 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3047 fprintf ((FILE), "\t.align %d\n", (LOG))
3049 /* Globalizing directive for a label. */
3050 #define GLOBAL_ASM_OP "\t.global\t"
3052 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3054 /* Output a relative address table. */
3056 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3057 switch (GET_MODE (BODY)) \
3062 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3066 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3071 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3075 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3080 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3084 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3090 /* Output an absolute table element. */
3092 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3093 if (! optimize || TARGET_BIGTABLE) \
3094 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3096 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3099 /* A C statement to be executed just prior to the output of
3100 assembler code for INSN, to modify the extracted operands so
3101 they will be output differently.
3103 Here the argument OPVEC is the vector containing the operands
3104 extracted from INSN, and NOPERANDS is the number of elements of
3105 the vector which contain meaningful data for this insn.
3106 The contents of this vector are what will be used to convert the insn
3107 template into assembler code, so you can change the assembler output
3108 by changing the contents of the vector. */
3110 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3111 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3113 /* Print operand X (an rtx) in assembler syntax to file FILE.
3114 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3115 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3117 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3119 /* Print a memory address as an operand to reference that memory location. */
3121 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3123 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3124 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3125 || (CHAR) == '$'|| (CHAR) == '\'')
3127 /* Recognize machine-specific patterns that may appear within
3128 constants. Used for PIC-specific UNSPECs. */
3129 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3131 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3133 switch (XINT ((X), 1)) \
3135 case UNSPEC_DATALABEL: \
3136 fputs ("datalabel ", (STREAM)); \
3137 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3140 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3141 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3144 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3145 fputs ("@GOT", (STREAM)); \
3147 case UNSPEC_GOTOFF: \
3148 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3149 fputs ("@GOTOFF", (STREAM)); \
3152 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3153 fputs ("@PLT", (STREAM)); \
3155 case UNSPEC_GOTPLT: \
3156 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3157 fputs ("@GOTPLT", (STREAM)); \
3159 case UNSPEC_DTPOFF: \
3160 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3161 fputs ("@DTPOFF", (STREAM)); \
3163 case UNSPEC_GOTTPOFF: \
3164 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3165 fputs ("@GOTTPOFF", (STREAM)); \
3167 case UNSPEC_TPOFF: \
3168 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3169 fputs ("@TPOFF", (STREAM)); \
3171 case UNSPEC_CALLER: \
3174 /* LPCS stands for Label for PIC Call Site. */ \
3175 ASM_GENERATE_INTERNAL_LABEL \
3176 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3177 assemble_name ((STREAM), name); \
3190 extern struct rtx_def *sh_compare_op0;
3191 extern struct rtx_def *sh_compare_op1;
3193 /* Which processor to schedule for. The elements of the enumeration must
3194 match exactly the cpu attribute in the sh.md file. */
3196 enum processor_type {
3206 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3207 extern enum processor_type sh_cpu;
3209 extern int optimize; /* needed for gen_casesi. */
3211 enum mdep_reorg_phase_e
3213 SH_BEFORE_MDEP_REORG,
3214 SH_INSERT_USES_LABELS,
3215 SH_SHORTEN_BRANCHES0,
3217 SH_SHORTEN_BRANCHES1,
3221 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3223 /* Handle Renesas compiler's pragmas. */
3224 #define REGISTER_TARGET_PRAGMAS() do { \
3225 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3226 c_register_pragma (0, "trapa", sh_pr_trapa); \
3227 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3230 /* Set when processing a function with pragma interrupt turned on. */
3232 extern int pragma_interrupt;
3234 /* Set when processing a function with interrupt attribute. */
3236 extern int current_function_interrupt;
3238 /* Set to an RTX containing the address of the stack to switch to
3239 for interrupt functions. */
3240 extern struct rtx_def *sp_switch;
3242 extern int rtx_equal_function_value_matters;
3245 /* Instructions with unfilled delay slots take up an
3246 extra two bytes for the nop in the delay slot.
3247 sh-dsp parallel processing insns are four bytes long. */
3249 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3250 (LENGTH) += sh_insn_length_adjustment (X);
3252 /* Define the codes that are matched by predicates in sh.c. */
3253 #define PREDICATE_CODES \
3254 {"and_operand", {SUBREG, REG, CONST_INT}}, \
3255 {"any_register_operand", {SUBREG, REG}}, \
3256 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3257 {"arith_reg_dest", {SUBREG, REG}}, \
3258 {"arith_reg_operand", {SUBREG, REG}}, \
3259 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
3260 {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
3261 {"binary_logical_operator", {AND, IOR, XOR}}, \
3262 {"cmpsi_operand", {SUBREG, REG, CONST_INT}}, \
3263 {"commutative_float_operator", {PLUS, MULT}}, \
3264 {"equality_comparison_operator", {EQ,NE}}, \
3265 {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
3266 {"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \
3267 {"fp_arith_reg_operand", {SUBREG, REG}}, \
3268 {"fpscr_operand", {REG}}, \
3269 {"fpul_operand", {REG}}, \
3270 {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \
3271 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
3272 {"general_movdst_operand", {SUBREG, REG, MEM}}, \
3273 {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
3274 {"int_gpr_dest", {SUBREG, REG}}, \
3275 {"inqhi_operand", {TRUNCATE}}, \
3276 {"less_comparison_operator", {LT,LE,LTU,LEU}}, \
3277 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
3278 {"mextr_bit_offset", {CONST_INT}}, \
3279 {"noncommutative_float_operator", {MINUS, DIV}}, \
3280 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
3281 {"sh_register_operand", {REG, SUBREG, CONST_INT}}, \
3282 {"target_reg_operand", {SUBREG, REG}}, \
3283 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
3284 {"trunc_hi_operand", {SUBREG, REG, TRUNCATE}}, \
3285 {"register_operand", {SUBREG, REG}}, \
3286 {"sh_const_vec", {CONST_VECTOR}}, \
3287 {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
3288 {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
3289 {"symbol_ref_operand", {SYMBOL_REF}}, \
3290 {"unary_float_operator", {ABS, NEG, SQRT}}, \
3292 #define SPECIAL_MODE_PREDICATES \
3293 "any_register_operand", \
3295 "trunc_hi_operand", \
3296 /* This line intentionally left blank. */
3298 #define any_register_operand register_operand
3300 /* Define this macro if it is advisable to hold scalars in registers
3301 in a wider mode than that declared by the program. In such cases,
3302 the value is constrained to be within the bounds of the declared
3303 type, but kept valid in the wider mode. The signedness of the
3304 extension may differ from that of the type.
3306 Leaving the unsignedp unchanged gives better code than always setting it
3307 to 0. This is despite the fact that we have only signed char and short
3308 load instructions. */
3309 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3310 if (GET_MODE_CLASS (MODE) == MODE_INT \
3311 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3312 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3313 (MODE) = (TARGET_SH1 ? SImode : DImode);
3315 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3317 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3318 and popping arguments. However, we do have push/pop instructions, and
3319 rather limited offsets (4 bits) in load/store instructions, so it isn't
3320 clear if this would give better code. If implemented, should check for
3321 compatibility problems. */
3323 #define SH_DYNAMIC_SHIFT_COST \
3324 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3327 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3329 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
3331 #define ACTUAL_NORMAL_MODE(ENTITY) \
3332 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3334 #define NORMAL_MODE(ENTITY) \
3335 (sh_cfun_interrupt_handler_p () \
3336 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3337 : ACTUAL_NORMAL_MODE (ENTITY))
3339 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3341 #define MODE_EXIT(ENTITY) \
3342 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3344 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3345 && (REGNO) == FPSCR_REG)
3347 #define MODE_NEEDED(ENTITY, INSN) \
3348 (recog_memoized (INSN) >= 0 \
3349 ? get_attr_fp_mode (INSN) \
3352 #define MODE_AFTER(MODE, INSN) \
3354 && recog_memoized (INSN) >= 0 \
3355 && get_attr_fp_set (INSN) != FP_SET_NONE \
3356 ? (int) get_attr_fp_set (INSN) \
3359 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3360 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3362 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3363 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3365 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3366 sh_can_redirect_branch ((INSN), (SEQ))
3368 #define DWARF_FRAME_RETURN_COLUMN \
3369 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3371 #define EH_RETURN_DATA_REGNO(N) \
3372 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3374 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3375 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3377 /* We have to distinguish between code and data, so that we apply
3378 datalabel where and only where appropriate. Use textrel for code. */
3379 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3380 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3381 | ((CODE) ? DW_EH_PE_textrel : flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))
3383 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3384 indirect are handled automatically. */
3385 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3387 if (((ENCODING) & 0x70) == DW_EH_PE_textrel) \
3389 encoding &= ~DW_EH_PE_textrel; \
3390 encoding |= flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr; \
3391 if (GET_CODE (ADDR) != SYMBOL_REF) \
3393 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3398 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3399 /* SH constant pool breaks the devices in crtstuff.c to control section
3400 in where code resides. We have to write it as asm code. */
3401 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3402 asm (SECTION_OP "\n\
3408 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3409 2:\n" TEXT_SECTION_ASM_OP);
3410 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3412 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3413 (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
3414 ? (current_function_is_leaf \
3415 && ! sh_pr_n_sets () \
3416 && ! (TARGET_SHCOMPACT \
3417 && ((current_function_args_info.call_cookie \
3418 & ~ CALL_COOKIE_RET_TRAMP (1)) \
3419 || current_function_has_nonlocal_label)) \
3421 : gen_rtx_MEM (Pmode, return_address_pointer_rtx)) \
3424 #endif /* ! GCC_SH_H */
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