1 /* Definitions of target machine for GNU compiler for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #define TARGET_VERSION \
25 fputs (" (Hitachi SH)", stderr);
27 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
28 include it here, because hconfig.h is also included by gencodes.c . */
29 extern int code_for_indirect_jump_scratch;
31 /* Generate SDB debugging information. */
33 #define SDB_DEBUGGING_INFO
35 /* Output DBX (stabs) debugging information if doing -gstabs. */
41 #define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__} \
46 %{!m1:%{!m2:%{!m3:%{!m3e:-D__sh1__}}}}"
48 #define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
50 #define ASM_SPEC "%{ml:-little} %{mrelax:-relax}"
52 #define LINK_SPEC "%{ml:-m shl} %{mrelax:-relax}"
54 /* We can not debug without a frame pointer. */
55 /* #define CAN_DEBUG_WITHOUT_FP */
57 #define CONDITIONAL_REGISTER_USAGE \
61 for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \
62 fixed_regs[regno] = call_used_regs[regno] = 1; \
63 fixed_regs[FPUL_REG] = call_used_regs[FPUL_REG] = 1; \
65 /* Hitachi saves and restores mac registers on call. */ \
68 call_used_regs[MACH_REG] = 0; \
69 call_used_regs[MACL_REG] = 0; \
72 /* ??? Need to write documentation for all SH options and add it to the
75 /* Run-time compilation parameters selecting different hardware subsets. */
77 extern int target_flags;
78 #define ISIZE_BIT (1<<1)
79 #define DALIGN_BIT (1<<6)
80 #define SH1_BIT (1<<8)
81 #define SH2_BIT (1<<9)
82 #define SH3_BIT (1<<10)
83 #define SH3E_BIT (1<<11)
84 #define SPACE_BIT (1<<13)
85 #define BIGTABLE_BIT (1<<14)
86 #define RELAX_BIT (1<<15)
87 #define HITACHI_BIT (1<<22)
88 #define PADSTRUCT_BIT (1<<28)
89 #define LITTLE_ENDIAN_BIT (1<<29)
90 #define IEEE_BIT (1<<30)
92 /* Nonzero if we should dump out instruction size info. */
93 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
95 /* Nonzero to align doubles on 64 bit boundaries. */
96 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
98 /* Nonzero if we should generate code using type 1 insns. */
99 #define TARGET_SH1 (target_flags & SH1_BIT)
101 /* Nonzero if we should generate code using type 2 insns. */
102 #define TARGET_SH2 (target_flags & SH2_BIT)
104 /* Nonzero if we should generate code using type 3 insns. */
105 #define TARGET_SH3 (target_flags & SH3_BIT)
107 /* Nonzero if we should generate code using type 3E insns. */
108 #define TARGET_SH3E (target_flags & SH3E_BIT)
110 /* Nonzero if we respect NANs. */
111 #define TARGET_IEEE (target_flags & IEEE_BIT)
113 /* Nonzero if we should generate smaller code rather than faster code. */
114 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
116 /* Nonzero to use long jump tables. */
117 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
119 /* Nonzero to generate pseudo-ops needed by the assembler and linker
120 to do function call relaxing. */
121 #define TARGET_RELAX (target_flags & RELAX_BIT)
123 /* Nonzero if using Hitachi's calling convention. */
124 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
126 /* Nonzero if padding structures to a multiple of 4 bytes. This is
127 incompatible with Hitachi's compiler, and gives unusual structure layouts
128 which confuse programmers.
129 ??? This option is not useful, but is retained in case there are people
130 who are still relying on it. It may be deleted in the future. */
131 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
133 /* Nonzero if generating code for a little endian SH. */
134 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
136 #define TARGET_SWITCHES \
139 {"3", SH3_BIT|SH2_BIT}, \
140 {"3e", SH3E_BIT|SH3_BIT|SH2_BIT}, \
141 {"b", -LITTLE_ENDIAN_BIT}, \
142 {"bigtable", BIGTABLE_BIT}, \
143 {"dalign", DALIGN_BIT}, \
144 {"hitachi", HITACHI_BIT}, \
145 {"ieee", IEEE_BIT}, \
146 {"isize", ISIZE_BIT}, \
147 {"l", LITTLE_ENDIAN_BIT}, \
148 {"no-ieee", -IEEE_BIT}, \
149 {"padstruct", PADSTRUCT_BIT}, \
150 {"relax", RELAX_BIT}, \
151 {"space", SPACE_BIT}, \
153 {"", TARGET_DEFAULT} \
156 /* This are meant to be redefined in the host dependent files */
157 #define SUBTARGET_SWITCHES
159 #define TARGET_DEFAULT (0)
161 #define PRESERVE_DEATH_INFO_REGNO_P(regno) (TARGET_RELAX || optimize)
163 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
166 target_flags |= SPACE_BIT; \
169 #define ASSEMBLER_DIALECT 0 /* will allow to distinguish b[tf].s and b[tf]/s . */
170 #define OVERRIDE_OPTIONS \
180 /* Never run scheduling before reload, since that can \
181 break global alloc, and generates slower code anyway due \
182 to the pressure on R0. */ \
183 flag_schedule_insns = 0; \
184 sh_addr_diff_vec_mode = TARGET_BIGTABLE ? SImode : HImode; \
187 /* Target machine storage layout. */
189 /* Define to use software floating point emulator for REAL_ARITHMETIC and
190 decimal <-> binary conversion. */
191 #define REAL_ARITHMETIC
193 /* Define this if most significant bit is lowest numbered
194 in instructions that operate on numbered bit-fields. */
196 #define BITS_BIG_ENDIAN 0
198 /* Define this if most significant byte of a word is the lowest numbered. */
199 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
201 /* Define this if most significant word of a multiword number is the lowest
203 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
205 /* Define this to set the endianness to use in libgcc2.c, which can
206 not depend on target_flags. */
207 #if defined(__LITTLE_ENDIAN__)
208 #define LIBGCC2_WORDS_BIG_ENDIAN 0
210 #define LIBGCC2_WORDS_BIG_ENDIAN 1
213 /* Number of bits in an addressable storage unit. */
214 #define BITS_PER_UNIT 8
216 /* Width in bits of a "word", which is the contents of a machine register.
217 Note that this is not necessarily the width of data type `int';
218 if using 16-bit ints on a 68000, this would still be 32.
219 But on a machine with 16-bit registers, this would be 16. */
220 #define BITS_PER_WORD 32
221 #define MAX_BITS_PER_WORD 32
223 /* Width of a word, in units (bytes). */
224 #define UNITS_PER_WORD 4
226 /* Width in bits of a pointer.
227 See also the macro `Pmode' defined below. */
228 #define POINTER_SIZE 32
230 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
231 #define PARM_BOUNDARY 32
233 /* Boundary (in *bits*) on which stack pointer should be aligned. */
234 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
236 /* The log (base 2) of the cache line size, in bytes. Processors prior to
237 SH3 have no actual cache, but they fetch code in chunks of 4 bytes. */
238 #define CACHE_LOG (TARGET_SH3 ? 4 : 2)
240 /* Allocation boundary (in *bits*) for the code of a function.
241 32 bit alignment is faster, because instructions are always fetched as a
242 pair from a longword boundary. */
243 #define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : (1 << CACHE_LOG) * 8)
245 /* Alignment of field after `int : 0' in a structure. */
246 #define EMPTY_FIELD_BOUNDARY 32
248 /* No data type wants to be aligned rounder than this. */
249 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
251 /* The best alignment to use in cases where we have a choice. */
252 #define FASTEST_ALIGNMENT 32
254 /* Make strings word-aligned so strcpy from constants will be faster. */
255 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
256 ((TREE_CODE (EXP) == STRING_CST \
257 && (ALIGN) < FASTEST_ALIGNMENT) \
258 ? FASTEST_ALIGNMENT : (ALIGN))
260 #ifndef MAX_OFILE_ALIGNMENT
261 #define MAX_OFILE_ALIGNMENT 128
264 /* Make arrays of chars word-aligned for the same reasons. */
265 #define DATA_ALIGNMENT(TYPE, ALIGN) \
266 (TREE_CODE (TYPE) == ARRAY_TYPE \
267 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
268 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
270 /* Number of bits which any structure or union's size must be a
271 multiple of. Each structure or union's size is rounded up to a
273 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
275 /* Set this nonzero if move instructions will actually fail to work
276 when given unaligned data. */
277 #define STRICT_ALIGNMENT 1
279 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
280 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
281 barrier_align (LABEL_AFTER_BARRIER)
283 #define LOOP_ALIGN(A_LABEL) \
284 ((! optimize || TARGET_SMALLCODE) ? 0 : 2)
286 #define LABEL_ALIGN(A_LABEL) \
288 (PREV_INSN (A_LABEL) \
289 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
290 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
291 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == 1) \
292 /* explicit alignment insn in constant tables. */ \
293 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
296 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
297 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
299 /* The base two logarithm of the known minimum alignment of an insn length. */
300 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
301 (GET_CODE (A_INSN) == INSN \
303 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
307 /* Standard register usage. */
309 /* Register allocation for the Hitachi calling convention:
315 r14 frame pointer/call saved
317 ap arg pointer (doesn't really exist, always eliminated)
318 pr subroutine return address
320 mach multiply/accumulate result, high part
321 macl multiply/accumulate result, low part.
322 fpul fp/int communication register
323 rap return address pointer register
325 fr1..fr3 scratch floating point registers
327 fr12..fr15 call saved floating point registers */
329 /* Number of actual hardware registers.
330 The hardware registers are assigned numbers for the compiler
331 from 0 to just below FIRST_PSEUDO_REGISTER.
332 All registers that the compiler knows about must be given numbers,
333 even those that are not normally considered general registers. */
341 #define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
344 #define FIRST_FP_REG 24
345 #define LAST_FP_REG 39
347 #define FIRST_PSEUDO_REGISTER 40
349 /* 1 for registers that have pervasive standard uses
350 and are not available for the register allocator.
352 Mach register is fixed 'cause it's only 10 bits wide for SH1.
353 It is 32 bits wide for SH2. */
355 #define FIXED_REGISTERS \
368 /* 1 for registers not available across function calls.
369 These must include the FIXED_REGISTERS and also any
370 registers that can be used without being saved.
371 The latter must include the registers where values are returned
372 and the register where structure-value addresses are passed.
373 Aside from that, you can include as many other registers as you like. */
375 #define CALL_USED_REGISTERS \
388 /* Return number of consecutive hard regs needed starting at reg REGNO
389 to hold something of mode MODE.
390 This is ordinarily the length in words of a value of mode MODE
391 but can be less for certain modes in special long registers.
393 On the SH regs are UNITS_PER_WORD bits wide. */
395 #define HARD_REGNO_NREGS(REGNO, MODE) \
396 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
398 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
399 We can allow any mode in any general register. The special registers
400 only allow SImode. Don't allow any mode in the PR. */
402 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
403 (SPECIAL_REG (REGNO) ? (MODE) == SImode \
404 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
405 : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG ? (MODE) == SFmode \
406 : (REGNO) == PR_REG ? 0 \
409 /* Value is 1 if it is a good idea to tie two pseudo registers
410 when one has mode MODE1 and one has mode MODE2.
411 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
412 for any hard reg, then this must be 0 for correct output. */
414 #define MODES_TIEABLE_P(MODE1, MODE2) \
415 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
417 /* Specify the registers used for certain standard purposes.
418 The values of these macros are register numbers. */
420 /* Define this if the program counter is overloaded on a register. */
421 /* #define PC_REGNUM 15*/
423 /* Register to use for pushing function arguments. */
424 #define STACK_POINTER_REGNUM 15
426 /* Base register for access to local variables of the function. */
427 #define FRAME_POINTER_REGNUM 14
429 /* Fake register that holds the address on the stack of the
430 current function's return address. */
431 #define RETURN_ADDRESS_POINTER_REGNUM 23
433 /* Value should be nonzero if functions must have frame pointers.
434 Zero means the frame pointer need not be set up (and parms may be accessed
435 via the stack pointer) in functions that seem suitable. */
437 #define FRAME_POINTER_REQUIRED 0
439 /* Definitions for register eliminations.
441 We have three registers that can be eliminated on the SH. First, the
442 frame pointer register can often be eliminated in favor of the stack
443 pointer register. Secondly, the argument pointer register can always be
444 eliminated; it is replaced with either the stack or frame pointer.
445 Third, there is the return address pointer, which can also be replaced
446 with either the stack or the frame pointer. */
448 /* This is an array of structures. Each structure initializes one pair
449 of eliminable registers. The "from" register number is given first,
450 followed by "to". Eliminations of the same "from" register are listed
451 in order of preference. */
453 /* If you add any registers here that are not actually hard registers,
454 and that have any alternative of elimination that doesn't always
455 apply, you need to amend calc_live_regs to exclude it, because
456 reload spills all eliminable registers where it sees an
457 can_eliminate == 0 entry, thus making them 'live' .
458 If you add any hard registers that can be eliminated in different
459 ways, you have to patch reload to spill them only when all alternatives
460 of elimination fail. */
462 #define ELIMINABLE_REGS \
463 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
464 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
465 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
466 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
467 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
469 /* Given FROM and TO register numbers, say whether this elimination
471 #define CAN_ELIMINATE(FROM, TO) \
472 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
474 /* Define the offset between two registers, one to be eliminated, and the other
475 its replacement, at the start of a routine. */
477 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
478 OFFSET = initial_elimination_offset ((FROM), (TO))
480 /* Base register for access to arguments of the function. */
481 #define ARG_POINTER_REGNUM 16
483 /* Register in which the static-chain is passed to a function. */
484 #define STATIC_CHAIN_REGNUM 13
486 /* The register in which a struct value address is passed. */
488 #define STRUCT_VALUE_REGNUM 2
490 /* If the structure value address is not passed in a register, define
491 `STRUCT_VALUE' as an expression returning an RTX for the place
492 where the address is passed. If it returns 0, the address is
493 passed as an "invisible" first argument. */
495 /*#define STRUCT_VALUE ((rtx)0)*/
497 /* Don't default to pcc-struct-return, because we have already specified
498 exactly how to return structures in the RETURN_IN_MEMORY macro. */
500 #define DEFAULT_PCC_STRUCT_RETURN 0
502 /* Define the classes of registers for register constraints in the
503 machine description. Also define ranges of constants.
505 One of the classes must always be named ALL_REGS and include all hard regs.
506 If there is more than one class, another class must be named NO_REGS
507 and contain no registers.
509 The name GENERAL_REGS must be the name of a class (or an alias for
510 another name such as ALL_REGS). This is the class of registers
511 that is allowed by "g" or "r" in a register constraint.
512 Also, registers outside this class are allocated only when
513 instructions express preferences for them.
515 The classes must be numbered in nondecreasing order; that is,
516 a larger-numbered class must never be contained completely
517 in a smaller-numbered class.
519 For any two classes, it is very desirable that there be another
520 class that represents their union. */
522 /* The SH has two sorts of general registers, R0 and the rest. R0 can
523 be used as the destination of some of the arithmetic ops. There are
524 also some special purpose registers; the T bit register, the
525 Procedure Return Register and the Multiply Accumulate Registers. */
526 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
527 reg_class_subunion. We don't want to have an actual union class
528 of these, because it would only be used when both classes are calculated
529 to give the same cost, but there is only one FPUL register.
530 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
531 applying to the actual instruction alternative considered. E.g., the
532 y/r alternative of movsi_ie is considered to have no more cost that
533 the r/r alternative, which is patently untrue. */
551 #define N_REG_CLASSES (int) LIM_REG_CLASSES
553 /* Give names of register classes as strings for dump file. */
554 #define REG_CLASS_NAMES \
569 /* Define which registers fit in which classes.
570 This is an initializer for a vector of HARD_REG_SET
571 of length N_REG_CLASSES. */
573 #define REG_CLASS_CONTENTS \
575 { 0x00000000, 0x00000000 }, /* NO_REGS */ \
576 { 0x00000001, 0x00000000 }, /* R0_REGS */ \
577 { 0x00020000, 0x00000000 }, /* PR_REGS */ \
578 { 0x00040000, 0x00000000 }, /* T_REGS */ \
579 { 0x00300000, 0x00000000 }, /* MAC_REGS */ \
580 { 0x00400000, 0x00000000 }, /* FPUL_REGS */ \
581 { 0x0081FFFF, 0x00000000 }, /* GENERAL_REGS */ \
582 { 0x01000000, 0x00000000 }, /* FP0_REGS */ \
583 { 0xFF000000, 0x000000FF }, /* FP_REGS */ \
584 { 0xFF81FFFF, 0x000000FF }, /* GENERAL_FP_REGS */ \
585 { 0xFFFFFFFF, 0x000000FF }, /* ALL_REGS */ \
588 /* The same information, inverted:
589 Return the class number of the smallest class containing
590 reg number REGNO. This could be a conditional expression
591 or could index an array. */
593 extern int regno_reg_class[];
594 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
596 /* When defined, the compiler allows registers explicitly used in the
597 rtl to be used as spill registers but prevents the compiler from
598 extending the lifetime of these registers. */
600 #define SMALL_REGISTER_CLASSES 1
602 /* The order in which register should be allocated. */
603 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
604 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
605 spilled or used otherwise, we better have the FP_REGS allocated first. */
606 #define REG_ALLOC_ORDER \
607 { 25,26,27,28,29,30,31,24,32,33,34,35,36,37,38,39, \
608 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14, \
609 22,15,16,17,18,19,20,21,23 }
611 /* The class value for index registers, and the one for base regs. */
612 #define INDEX_REG_CLASS R0_REGS
613 #define BASE_REG_CLASS GENERAL_REGS
615 /* Get reg_class from a letter such as appears in the machine
617 extern enum reg_class reg_class_from_letter[];
619 #define REG_CLASS_FROM_LETTER(C) \
620 ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
622 /* The letters I, J, K, L and M in a register constraint string
623 can be used to stand for particular ranges of immediate operands.
624 This macro defines what the ranges are.
625 C is the letter, and VALUE is a constant value.
626 Return 1 if VALUE is in the range specified by C.
627 I: arithmetic operand -127..128, as used in add, sub, etc
628 K: shift operand 1,2,8 or 16
629 L: logical operand 0..255, as used in and, or, etc.
633 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127)
634 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
635 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255)
636 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
637 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
638 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
639 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
640 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
641 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
642 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
643 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
646 /* Similar, but for floating constants, and defining letters G and H.
647 Here VALUE is the CONST_DOUBLE rtx itself. */
649 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
650 ((C) == 'G' ? fp_zero_operand (VALUE) \
651 : (C) == 'H' ? fp_one_operand (VALUE) \
654 /* Given an rtx X being reloaded into a reg required to be
655 in class CLASS, return the class of reg to actually use.
656 In general this is just CLASS; but on some machines
657 in some cases it is preferable to use a more restrictive class. */
659 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
661 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
662 ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS) \
663 && (GET_CODE (X) == REG && REGNO (X) <= AP_REG)) \
664 || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \
665 && GET_CODE (X) == REG \
666 && REGNO (X) >= FIRST_FP_REG && REGNO (X) <= LAST_FP_REG)) \
669 : ((CLASS) == FPUL_REGS \
670 && (GET_CODE (X) == MEM \
671 || GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER))\
673 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
674 && GET_CODE (X) == REG && REGNO (X) > 15 \
675 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
676 ? GENERAL_REGS : NO_REGS)
678 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
679 ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS) \
680 && immediate_operand ((X), (MODE)) \
681 && ! (fp_zero_operand (X) || fp_one_operand (X))) \
682 ? R0_REGS : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
684 /* Return the maximum number of consecutive registers
685 needed to represent mode MODE in a register of class CLASS.
687 On SH this is the size of MODE in words. */
688 #define CLASS_MAX_NREGS(CLASS, MODE) \
689 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
691 /* Stack layout; function entry, exit and calling. */
693 /* Define the number of registers that can hold parameters.
694 These macros are used only in other macro definitions below. */
696 #define NPARM_REGS(MODE) \
697 (TARGET_SH3E && (MODE) == SFmode \
701 #define FIRST_PARM_REG 4
702 #define FIRST_RET_REG 0
704 #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
705 #define FIRST_FP_RET_REG FIRST_FP_REG
707 /* Define this if pushing a word on the stack
708 makes the stack pointer a smaller address. */
709 #define STACK_GROWS_DOWNWARD
711 /* Define this macro if the addresses of local variable slots are at
712 negative offsets from the frame pointer.
714 The SH only has positive indexes, so grow the frame up. */
715 /* #define FRAME_GROWS_DOWNWARD */
717 /* Offset from the frame pointer to the first local variable slot to
719 #define STARTING_FRAME_OFFSET 0
721 /* If we generate an insn to push BYTES bytes,
722 this says how many the stack pointer really advances by. */
723 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
724 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
725 do correct alignment. */
727 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
730 /* Offset of first parameter from the argument pointer register value. */
731 #define FIRST_PARM_OFFSET(FNDECL) 0
733 /* Value is the number of byte of arguments automatically
734 popped when returning from a subroutine call.
735 FUNDECL is the declaration node of the function (as a tree),
736 FUNTYPE is the data type of the function (as a tree),
737 or for a library call it is an identifier node for the subroutine name.
738 SIZE is the number of bytes of arguments passed on the stack.
740 On the SH, the caller does not pop any of its arguments that were passed
742 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
744 /* Nonzero if we do not know how to pass TYPE solely in registers.
745 Values that come in registers with inconvenient padding are stored
746 to memory at the function start. */
748 #define MUST_PASS_IN_STACK(MODE,TYPE) \
750 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
751 || TREE_ADDRESSABLE (TYPE)))
752 /* Some subroutine macros specific to this machine. */
754 #define BASE_RETURN_VALUE_REG(MODE) \
755 ((TARGET_SH3E && ((MODE) == SFmode)) \
759 #define BASE_ARG_REG(MODE) \
760 ((TARGET_SH3E && ((MODE) == SFmode)) \
761 ? FIRST_FP_PARM_REG \
764 /* Define how to find the value returned by a function.
765 VALTYPE is the data type of the value (as a tree).
766 If the precise function being called is known, FUNC is its FUNCTION_DECL;
767 otherwise, FUNC is 0. */
769 #define FUNCTION_VALUE(VALTYPE, FUNC) \
770 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
772 /* Define how to find the value returned by a library function
773 assuming the value has mode MODE. */
774 #define LIBCALL_VALUE(MODE) \
775 gen_rtx (REG, (MODE), BASE_RETURN_VALUE_REG (MODE));
777 /* 1 if N is a possible register number for a function value. */
778 #define FUNCTION_VALUE_REGNO_P(REGNO) \
779 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG))
781 /* 1 if N is a possible register number for function argument passing. */
782 #define FUNCTION_ARG_REGNO_P(REGNO) \
783 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG + 4)) \
785 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG + 8)))
787 /* Define a data type for recording info about an argument list
788 during the scan of that argument list. This data type should
789 hold all necessary information about the function itself
790 and about the args processed so far, enough to enable macros
791 such as FUNCTION_ARG to determine where the next arg should go.
793 On SH, this is a single integer, which is a number of words
794 of arguments scanned so far (including the invisible argument,
795 if any, which holds the structure-value-address).
796 Thus NARGREGS or more means all following args should go on the stack. */
798 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
803 #define CUMULATIVE_ARGS struct sh_args
805 #define GET_SH_ARG_CLASS(MODE) \
806 ((TARGET_SH3E && ((MODE) == SFmode)) ? SH_ARG_FLOAT : SH_ARG_INT)
808 #define ROUND_ADVANCE(SIZE) \
809 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
811 /* Round a register number up to a proper boundary for an arg of mode
814 The SH doesn't care about double alignment, so we only
815 round doubles to even regs when asked to explicitly. */
817 #define ROUND_REG(CUM, MODE) \
818 ((TARGET_ALIGN_DOUBLE \
819 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
820 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
821 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
822 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
824 /* Initialize a variable CUM of type CUMULATIVE_ARGS
825 for a call to a function whose data type is FNTYPE.
826 For a library call, FNTYPE is 0.
828 On SH, the offset always starts at 0: the first parm reg is always
829 the same reg for a given argument class. */
831 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
833 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
834 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
837 /* Update the data in CUM to advance over an argument
838 of mode MODE and data type TYPE.
839 (TYPE is null for libcalls where that information may not be
842 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
843 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] = \
844 (ROUND_REG ((CUM), (MODE)) \
845 + ((MODE) != BLKmode \
846 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
847 : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
849 /* Return boolean indicating arg of mode MODE will be passed in a reg.
850 This macro is only used in this file. */
852 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
853 (((TYPE) == 0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
855 ? ((MODE) == BLKmode \
856 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
857 + int_size_in_bytes (TYPE)) \
858 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
859 : ((ROUND_REG((CUM), (MODE)) \
860 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
861 <= NPARM_REGS (MODE))) \
862 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
864 /* Define where to put the arguments to a function.
865 Value is zero to push the argument on the stack,
866 or a hard register in which to store the argument.
868 MODE is the argument's machine mode.
869 TYPE is the data type of the argument (as a tree).
870 This is null for libcalls where that information may
872 CUM is a variable of type CUMULATIVE_ARGS which gives info about
873 the preceding args and about the function being called.
874 NAMED is nonzero if this argument is a named parameter
875 (otherwise it is an extra parameter matching an ellipsis).
877 On SH the first args are normally in registers
878 and the rest are pushed. Any arg that starts within the first
879 NPARM_REGS words is at least partially passed in a register unless
880 its data type forbids. */
882 extern int current_function_varargs;
884 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
885 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
886 && ((NAMED) || TARGET_SH3E || ! current_function_varargs)) \
887 ? gen_rtx (REG, (MODE), \
888 (BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
891 /* For an arg passed partly in registers and partly in memory,
892 this is the number of registers used.
893 For args passed entirely in registers or entirely in memory, zero.
895 We sometimes split args. */
897 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
898 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
899 && (ROUND_REG ((CUM), (MODE)) \
901 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
902 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
903 - NPARM_REGS (MODE) > 0)) \
904 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
907 extern int current_function_anonymous_args;
909 /* Perform any needed actions needed for a function that is receiving a
910 variable number of arguments. */
912 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
913 current_function_anonymous_args = 1;
915 /* Call the function profiler with a given profile label.
916 We use two .aligns, so as to make sure that both the .long is aligned
917 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
918 from the trapa instruction. */
920 #define FUNCTION_PROFILER(STREAM,LABELNO) \
922 fprintf((STREAM), "\t.align\t2\n"); \
923 fprintf((STREAM), "\ttrapa\t#33\n"); \
924 fprintf((STREAM), "\t.align\t2\n"); \
925 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
928 /* Define this macro if the code for function profiling should come
929 before the function prologue. Normally, the profiling code comes
932 #define PROFILE_BEFORE_PROLOGUE
934 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
935 the stack pointer does not matter. The value is tested only in
936 functions that have frame pointers.
937 No definition is equivalent to always zero. */
939 #define EXIT_IGNORE_STACK 1
941 /* Generate the assembly code for function exit
942 Just dump out any accumulated constant table. */
944 #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue ((STREAM), (SIZE))
947 On the SH, the trampoline looks like
948 2 0002 DD02 mov.l l2,r13
949 1 0000 D301 mov.l l1,r3
952 5 0008 00000000 l1: .long function
953 6 000c 00000000 l2: .long area */
955 /* Length in units of the trampoline for entering a nested function. */
956 #define TRAMPOLINE_SIZE 16
958 /* Alignment required for a trampoline in bits . */
959 #define TRAMPOLINE_ALIGNMENT \
960 ((CACHE_LOG < 3 || TARGET_SMALLCODE) ? 32 : 64) \
962 /* Emit RTL insns to initialize the variable parts of a trampoline.
963 FNADDR is an RTX for the address of the function's pure code.
964 CXT is an RTX for the static chain value for the function. */
966 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
968 emit_move_insn (gen_rtx (MEM, SImode, (TRAMP)), \
969 GEN_INT (TARGET_LITTLE_ENDIAN ? 0xd301dd02 : 0xdd02d301));\
970 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 4)), \
971 GEN_INT (TARGET_LITTLE_ENDIAN ? 0x00094d2b : 0x4d2b0009));\
972 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
974 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
978 /* A C expression whose value is RTL representing the value of the return
979 address for the frame COUNT steps up from the current frame.
980 FRAMEADDR is already the frame pointer of the COUNT frame, so we
983 #define RETURN_ADDR_RTX(COUNT, FRAME) \
985 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM)) \
988 /* Generate necessary RTL for __builtin_saveregs().
989 ARGLIST is the argument list; see expr.c. */
990 extern struct rtx_def *sh_builtin_saveregs ();
991 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sh_builtin_saveregs (ARGLIST)
993 /* Addressing modes, and classification of registers for them. */
994 #define HAVE_POST_INCREMENT 1
995 /*#define HAVE_PRE_INCREMENT 1*/
996 /*#define HAVE_POST_DECREMENT 1*/
997 #define HAVE_PRE_DECREMENT 1
999 /* Macros to check register numbers against specific register classes. */
1001 /* These assume that REGNO is a hard or pseudo reg number.
1002 They give nonzero only if REGNO is a hard reg of the suitable class
1003 or a pseudo reg currently allocated to a suitable hard reg.
1004 Since they use reg_renumber, they are safe only once reg_renumber
1005 has been allocated, which happens in local-alloc.c. */
1007 #define REGNO_OK_FOR_BASE_P(REGNO) \
1008 ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
1009 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1010 ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
1012 /* Maximum number of registers that can appear in a valid memory
1015 #define MAX_REGS_PER_ADDRESS 2
1017 /* Recognize any constant value that is a valid address. */
1019 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1021 /* Nonzero if the constant value X is a legitimate general operand. */
1023 #define LEGITIMATE_CONSTANT_P(X) \
1024 (GET_CODE (X) != CONST_DOUBLE \
1025 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
1026 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X))))
1028 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1029 and check its validity for a certain class.
1030 We have two alternate definitions for each of them.
1031 The usual definition accepts all pseudo regs; the other rejects
1032 them unless they have been allocated suitable hard regs.
1033 The symbol REG_OK_STRICT causes the latter definition to be used. */
1035 #ifndef REG_OK_STRICT
1037 /* Nonzero if X is a hard reg that can be used as a base reg
1038 or if it is a pseudo reg. */
1039 #define REG_OK_FOR_BASE_P(X) \
1040 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1042 /* Nonzero if X is a hard reg that can be used as an index
1043 or if it is a pseudo reg. */
1044 #define REG_OK_FOR_INDEX_P(X) \
1045 (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1047 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
1048 or if X is a pseudo reg. */
1049 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
1050 ((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1054 /* Nonzero if X is a hard reg that can be used as a base reg. */
1055 #define REG_OK_FOR_BASE_P(X) \
1056 REGNO_OK_FOR_BASE_P (REGNO (X))
1058 /* Nonzero if X is a hard reg that can be used as an index. */
1059 #define REG_OK_FOR_INDEX_P(X) \
1060 REGNO_OK_FOR_INDEX_P (REGNO (X))
1062 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
1063 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
1064 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
1068 /* The 'Q' constraint is a pc relative load operand. */
1069 #define EXTRA_CONSTRAINT_Q(OP) \
1070 (GET_CODE (OP) == MEM && \
1071 ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
1072 || (GET_CODE (XEXP ((OP), 0)) == CONST \
1073 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
1074 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
1075 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
1077 #define EXTRA_CONSTRAINT(OP, C) \
1078 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
1081 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1082 that is a valid memory address for an instruction.
1083 The MODE argument is the machine mode for the MEM expression
1084 that wants to use this address.
1086 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1088 #define MODE_DISP_OK_4(X,MODE) \
1089 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
1090 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode))
1091 #define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3)))
1093 #define BASE_REGISTER_RTX_P(X) \
1094 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1095 || (GET_CODE (X) == SUBREG \
1096 && GET_CODE (SUBREG_REG (X)) == REG \
1097 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1099 /* Since this must be r0, which is a single register class, we must check
1100 SUBREGs more carefully, to be sure that we don't accept one that extends
1101 outside the class. */
1102 #define INDEX_REGISTER_RTX_P(X) \
1103 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1104 || (GET_CODE (X) == SUBREG \
1105 && GET_CODE (SUBREG_REG (X)) == REG \
1106 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X))))
1108 /* Jump to LABEL if X is a valid address RTX. This must also take
1109 REG_OK_STRICT into account when deciding about valid registers, but it uses
1110 the above macros so we are in luck.
1118 /* ??? The SH3e does not have the REG+disp addressing mode when loading values
1119 into the FRx registers. We implement this by setting the maximum offset
1120 to zero when the value is SFmode. This also restricts loading of SFmode
1121 values into the integer registers, but that can't be helped. */
1123 /* The SH allows a displacement in a QI or HI amode, but only when the
1124 other operand is R0. GCC doesn't handle this very well, so we forgo
1127 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
1128 DI can be any number 0..60. */
1130 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
1132 if (GET_CODE (OP) == CONST_INT) \
1134 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
1135 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
1139 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1141 if (BASE_REGISTER_RTX_P (X)) \
1143 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1144 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
1146 else if (GET_CODE (X) == PLUS && MODE != PSImode) \
1148 rtx xop0 = XEXP ((X), 0); \
1149 rtx xop1 = XEXP ((X), 1); \
1150 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
1151 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
1152 if (GET_MODE_SIZE (MODE) <= 4) \
1154 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
1156 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
1162 /* Try machine-dependent ways of modifying an illegitimate address
1163 to be legitimate. If we find one, return the new, valid address.
1164 This macro is used in only one place: `memory_address' in explow.c.
1166 OLDX is the address as it was before break_out_memory_refs was called.
1167 In some cases it is useful to look at this to decide what needs to be done.
1169 MODE and WIN are passed so that this macro can use
1170 GO_IF_LEGITIMATE_ADDRESS.
1172 It is always safe for this macro to do nothing. It exists to recognize
1173 opportunities to optimize the output.
1175 For the SH, if X is almost suitable for indexing, but the offset is
1176 out of range, convert it into a normal form so that cse has a chance
1177 of reducing the number of address registers used. */
1179 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1181 if (GET_CODE (X) == PLUS \
1182 && (GET_MODE_SIZE (MODE) == 4 \
1183 || GET_MODE_SIZE (MODE) == 8) \
1184 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
1185 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
1186 && ! (TARGET_SH3E && (MODE) == SFmode)) \
1188 rtx index_rtx = XEXP ((X), 1); \
1189 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
1192 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
1193 /* On rare occasions, we might get an unaligned pointer \
1194 that is indexed in a way to give an aligned address. \
1195 Therefore, keep the lower two bits in offset_base. */ \
1196 /* Instead of offset_base 128..131 use 124..127, so that \
1197 simple add suffices. */ \
1200 offset_base = ((offset + 4) & ~60) - 4; \
1203 offset_base = offset & ~60; \
1204 /* Sometimes the normal form does not suit DImode. We \
1205 could avoid that by using smaller ranges, but that \
1206 would give less optimized code when SImode is \
1208 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
1210 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
1211 GEN_INT (offset_base), NULL_RTX, 0, \
1214 (X) = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base)); \
1220 /* A C compound statement that attempts to replace X, which is an address
1221 that needs reloading, with a valid memory address for an operand of
1222 mode MODE. WIN is a C statement label elsewhere in the code.
1224 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
1225 of the address. That will allow inheritance of the address reloads. */
1227 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1229 if (GET_CODE (X) == PLUS \
1230 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
1231 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1232 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1233 && ! (TARGET_SH3E && MODE == SFmode)) \
1235 rtx index_rtx = XEXP (X, 1); \
1236 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
1239 /* Instead of offset_base 128..131 use 124..127, so that \
1240 simple add suffices. */ \
1243 offset_base = ((offset + 4) & ~60) - 4; \
1246 offset_base = offset & ~60; \
1247 /* Sometimes the normal form does not suit DImode. We \
1248 could avoid that by using smaller ranges, but that \
1249 would give less optimized code when SImode is \
1251 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
1253 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1254 GEN_INT (offset_base)); \
1255 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
1256 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1257 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
1262 /* We must re-recognize what we created before. */ \
1263 else if (GET_CODE (X) == PLUS \
1264 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
1265 && GET_CODE (XEXP (X, 0)) == PLUS \
1266 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1267 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
1268 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1269 && ! (TARGET_SH3E && MODE == SFmode)) \
1271 /* Because this address is so complex, we know it must have \
1272 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
1273 it is already unshared, and needs no further unsharing. */ \
1274 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL_PTR, \
1275 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
1280 /* Go to LABEL if ADDR (a legitimate address expression)
1281 has an effect that depends on the machine mode it is used for.
1283 ??? Strictly speaking, we should also include all indexed addressing,
1284 because the index scale factor is the length of the operand.
1285 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
1286 high if we did that. So we rely on reload to fix things up. */
1288 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1290 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
1294 /* Specify the machine mode that this machine uses
1295 for the index in the tablejump instruction. */
1296 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
1298 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1299 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1300 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1301 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1302 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1303 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1306 /* Define as C expression which evaluates to nonzero if the tablejump
1307 instruction expects the table to contain offsets from the address of the
1309 Do not define this if the table should contain absolute addresses. */
1310 #define CASE_VECTOR_PC_RELATIVE 1
1312 /* Specify the tree operation to be used to convert reals to integers. */
1313 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1315 /* This is the kind of divide that is easiest to do in the general case. */
1316 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1318 /* Since the SH3e has only `float' support, it is desirable to make all
1319 floating point types equivalent to `float'. */
1320 #define DOUBLE_TYPE_SIZE (TARGET_SH3E ? 32 : 64)
1322 /* 'char' is signed by default. */
1323 #define DEFAULT_SIGNED_CHAR 1
1325 /* The type of size_t unsigned int. */
1326 #define SIZE_TYPE "unsigned int"
1328 #define WCHAR_TYPE "short unsigned int"
1329 #define WCHAR_TYPE_SIZE 16
1331 /* Don't cse the address of the function being compiled. */
1332 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
1334 /* Max number of bytes we can move from memory to memory
1335 in one reasonably fast instruction. */
1338 /* Define if operations between registers always perform the operation
1339 on the full register even if a narrower mode is specified. */
1340 #define WORD_REGISTER_OPERATIONS
1342 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1343 will either zero-extend or sign-extend. The value of this macro should
1344 be the code that says which one of the two operations is implicitly
1345 done, NIL if none. */
1346 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
1348 /* Define if loading short immediate values into registers sign extends. */
1349 #define SHORT_IMMEDIATES_SIGN_EXTEND
1351 /* Define this if zero-extension is slow (more than one real instruction).
1352 On the SH, it's only one instruction. */
1353 /* #define SLOW_ZERO_EXTEND */
1355 /* Nonzero if access to memory by bytes is slow and undesirable. */
1356 #define SLOW_BYTE_ACCESS 0
1358 /* We assume that the store-condition-codes instructions store 0 for false
1359 and some other value for true. This is the value stored for true. */
1361 #define STORE_FLAG_VALUE 1
1363 /* Immediate shift counts are truncated by the output routines (or was it
1364 the assembler?). Shift counts in a register are truncated by SH. Note
1365 that the native compiler puts too large (> 32) immediate shift counts
1366 into a register and shifts by the register, letting the SH decide what
1367 to do instead of doing that itself. */
1368 /* ??? The library routines in lib1funcs.asm truncate the shift count.
1369 However, the SH3 has hardware shifts that do not truncate exactly as gcc
1370 expects - the sign bit is significant - so it appears that we need to
1371 leave this zero for correct SH3 code. */
1372 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
1374 /* All integers have the same format so truncation is easy. */
1375 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1377 /* Define this if addresses of constant functions
1378 shouldn't be put through pseudo regs where they can be cse'd.
1379 Desirable on machines where ordinary constants are expensive
1380 but a CALL with constant address is cheap. */
1381 /*#define NO_FUNCTION_CSE 1*/
1383 /* Chars and shorts should be passed as ints. */
1384 #define PROMOTE_PROTOTYPES 1
1386 /* The machine modes of pointers and functions. */
1387 #define Pmode SImode
1388 #define FUNCTION_MODE Pmode
1390 /* The relative costs of various types of constants. Note that cse.c defines
1391 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1393 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1395 if (INTVAL (RTX) == 0) \
1397 else if (CONST_OK_FOR_I (INTVAL (RTX))) \
1399 else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \
1400 && CONST_OK_FOR_L (INTVAL (RTX))) \
1408 case CONST_DOUBLE: \
1411 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1413 return COSTS_N_INSNS (andcosts (X)); \
1415 return COSTS_N_INSNS (multcosts (X)); \
1419 return COSTS_N_INSNS (shiftcosts (X)) ; \
1424 return COSTS_N_INSNS (20); \
1429 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1430 are actually function calls with some special constraints on arguments
1433 These macros tell reorg that the references to arguments and
1434 register clobbers for insns of type sfunc do not appear to happen
1435 until after the millicode call. This allows reorg to put insns
1436 which set the argument registers into the delay slot of the millicode
1437 call -- thus they act more like traditional CALL_INSNs.
1439 get_attr_type will try to recognize the given insn, so make sure to
1440 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1443 #define INSN_SETS_ARE_DELAYED(X) \
1444 ((GET_CODE (X) == INSN \
1445 && GET_CODE (PATTERN (X)) != SEQUENCE \
1446 && GET_CODE (PATTERN (X)) != USE \
1447 && GET_CODE (PATTERN (X)) != CLOBBER \
1448 && get_attr_type (X) == TYPE_SFUNC))
1450 #define INSN_REFERENCES_ARE_DELAYED(X) \
1451 ((GET_CODE (X) == INSN \
1452 && GET_CODE (PATTERN (X)) != SEQUENCE \
1453 && GET_CODE (PATTERN (X)) != USE \
1454 && GET_CODE (PATTERN (X)) != CLOBBER \
1455 && get_attr_type (X) == TYPE_SFUNC))
1457 /* Compute the cost of an address. For the SH, all valid addresses are
1459 /* ??? Perhaps we should make reg+reg addresses have higher cost because
1460 they add to register pressure on r0. */
1462 #define ADDRESS_COST(RTX) 1
1464 /* Compute extra cost of moving data between one register class
1467 #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
1468 ((DSTCLASS) == PR_REG ? 10 \
1469 : (((DSTCLASS) == FP_REGS && (SRCCLASS) == GENERAL_REGS) \
1470 || ((DSTCLASS) == GENERAL_REGS && (SRCCLASS) == FP_REGS)) ? 4 \
1473 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1474 would be so that people would slow memory systems could generate
1475 different code that does fewer memory accesses. */
1477 /* Assembler output control. */
1479 /* A C string constant describing how to begin a comment in the target
1480 assembler language. The compiler assumes that the comment will end at
1481 the end of the line. */
1482 #define ASM_COMMENT_START "!"
1484 /* The text to go at the start of the assembler file. */
1485 #define ASM_FILE_START(STREAM) \
1486 output_file_start (STREAM)
1488 #define ASM_FILE_END(STREAM)
1490 #define ASM_APP_ON ""
1491 #define ASM_APP_OFF ""
1492 #define FILE_ASM_OP "\t.file\n"
1493 #define IDENT_ASM_OP "\t.ident\n"
1494 #define SET_ASM_OP ".set"
1496 /* How to change between sections. */
1498 #define TEXT_SECTION_ASM_OP "\t.text"
1499 #define DATA_SECTION_ASM_OP "\t.data"
1500 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n"
1501 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n"
1502 #define EXTRA_SECTIONS in_ctors, in_dtors
1503 #define EXTRA_SECTION_FUNCTIONS \
1507 if (in_section != in_ctors) \
1509 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1510 in_section = in_ctors; \
1516 if (in_section != in_dtors) \
1518 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1519 in_section = in_dtors; \
1523 /* Define this so that jump tables go in same section as the current function,
1524 which could be text or it could be a user defined section. */
1525 #define JUMP_TABLES_IN_TEXT_SECTION 1
1527 /* A C statement to output something to the assembler file to switch to section
1528 NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
1529 NULL_TREE. Some target formats do not support arbitrary sections. Do not
1530 define this macro in such cases. */
1532 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
1533 do { fprintf (FILE, ".section\t%s\n", NAME); } while (0)
1535 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
1536 do { ctors_section(); asm_fprintf((FILE),"\t.long\t%U%s\n", (NAME)); } while (0)
1538 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
1539 do { dtors_section(); asm_fprintf((FILE),"\t.long\t%U%s\n", (NAME)); } while (0)
1541 #undef DO_GLOBAL_CTORS_BODY
1543 #define DO_GLOBAL_CTORS_BODY \
1545 typedef (*pfunc)(); \
1546 extern pfunc __ctors[]; \
1547 extern pfunc __ctors_end[]; \
1549 for (p = __ctors_end; p > __ctors; ) \
1555 #undef DO_GLOBAL_DTORS_BODY
1556 #define DO_GLOBAL_DTORS_BODY \
1558 typedef (*pfunc)(); \
1559 extern pfunc __dtors[]; \
1560 extern pfunc __dtors_end[]; \
1562 for (p = __dtors; p < __dtors_end; p++) \
1568 #define ASM_OUTPUT_REG_PUSH(file, v) \
1569 fprintf ((file), "\tmov.l\tr%s,-@r15\n", (v));
1571 #define ASM_OUTPUT_REG_POP(file, v) \
1572 fprintf ((file), "\tmov.l\t@r15+,r%s\n", (v));
1574 /* The assembler's names for the registers. RFP need not always be used as
1575 the Real framepointer; it can also be used as a normal general register.
1576 Note that the name `fp' is horribly misleading since `fp' is in fact only
1577 the argument-and-return-context pointer. */
1578 #define REGISTER_NAMES \
1580 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1581 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1582 "ap", "pr", "t", "gbr", "mach","macl", "fpul","rap", \
1583 "fr0","fr1","fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1584 "fr8","fr9","fr10","fr11","fr12","fr13","fr14","fr15",\
1587 /* DBX register number for a given compiler register number. */
1588 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
1590 #define DBX_REGISTER_NUMBER(REGNO) \
1591 (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO))
1593 /* Output a label definition. */
1594 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1595 do { assemble_name ((FILE), (NAME)); fputs (":\n", (FILE)); } while (0)
1597 /* This is how to output an assembler line
1598 that says to advance the location counter
1599 to a multiple of 2**LOG bytes. */
1601 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1603 fprintf ((FILE), "\t.align %d\n", (LOG))
1605 /* Output a function label definition. */
1606 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1607 ASM_OUTPUT_LABEL((STREAM), (NAME))
1609 /* Output a globalising directive for a label. */
1610 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1611 (fprintf ((STREAM), "\t.global\t"), \
1612 assemble_name ((STREAM), (NAME)), \
1613 fputc ('\n', (STREAM)))
1615 /* The prefix to add to user-visible assembler symbols. */
1617 #define USER_LABEL_PREFIX "_"
1619 /* The prefix to add to an internally generated label. */
1621 #define LOCAL_LABEL_PREFIX ""
1623 /* Make an internal label into a string. */
1624 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1625 sprintf ((STRING), "*%s%s%d", LOCAL_LABEL_PREFIX, (PREFIX), (NUM))
1627 /* Output an internal label definition. */
1628 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1629 asm_fprintf ((FILE), "%L%s%d:\n", (PREFIX), (NUM))
1631 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1633 /* Construct a private name. */
1634 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1635 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1636 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1638 /* Output a relative address table. */
1640 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
1641 switch (GET_MODE (BODY)) \
1644 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1647 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1650 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1654 /* Output an absolute table element. */
1656 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1657 if (TARGET_BIGTABLE) \
1658 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
1660 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); \
1662 /* Output various types of constants. */
1664 /* This is how to output an assembler line defining a `double'. */
1666 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1667 do { char dstr[30]; \
1668 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1669 fprintf ((FILE), "\t.double %s\n", dstr); \
1672 /* This is how to output an assembler line defining a `float' constant. */
1673 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1674 do { char dstr[30]; \
1675 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1676 fprintf ((FILE), "\t.float %s\n", dstr); \
1679 #define ASM_OUTPUT_INT(STREAM, EXP) \
1680 (fprintf ((STREAM), "\t.long\t"), \
1681 output_addr_const ((STREAM), (EXP)), \
1682 fputc ('\n', (STREAM)))
1684 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1685 (fprintf ((STREAM), "\t.short\t"), \
1686 output_addr_const ((STREAM), (EXP)), \
1687 fputc ('\n', (STREAM)))
1689 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1690 (fprintf ((STREAM), "\t.byte\t"), \
1691 output_addr_const ((STREAM), (EXP)), \
1692 fputc ('\n', (STREAM)))
1694 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1695 fprintf ((STREAM), "\t.byte\t%d\n", (VALUE)) \
1697 /* The next two are used for debug info when compiling with -gdwarf. */
1698 #define UNALIGNED_SHORT_ASM_OP ".uaword"
1699 #define UNALIGNED_INT_ASM_OP ".ualong"
1701 /* Loop alignment is now done in machine_dependent_reorg, so that
1702 branch shortening can know about it. */
1704 /* This is how to output an assembler line
1705 that says to advance the location counter by SIZE bytes. */
1707 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1708 fprintf ((FILE), "\t.space %d\n", (SIZE))
1710 /* This says how to output an assembler line
1711 to define a global common symbol. */
1713 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1714 ( fputs ("\t.comm ", (FILE)), \
1715 assemble_name ((FILE), (NAME)), \
1716 fprintf ((FILE), ",%d\n", (SIZE)))
1718 /* This says how to output an assembler line
1719 to define a local common symbol. */
1721 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1722 ( fputs ("\t.lcomm ", (FILE)), \
1723 assemble_name ((FILE), (NAME)), \
1724 fprintf ((FILE), ",%d\n", (SIZE)))
1726 /* The assembler's parentheses characters. */
1727 #define ASM_OPEN_PAREN "("
1728 #define ASM_CLOSE_PAREN ")"
1730 /* Target characters. */
1731 #define TARGET_BELL 007
1732 #define TARGET_BS 010
1733 #define TARGET_TAB 011
1734 #define TARGET_NEWLINE 012
1735 #define TARGET_VT 013
1736 #define TARGET_FF 014
1737 #define TARGET_CR 015
1739 /* A C statement to be executed just prior to the output of
1740 assembler code for INSN, to modify the extracted operands so
1741 they will be output differently.
1743 Here the argument OPVEC is the vector containing the operands
1744 extracted from INSN, and NOPERANDS is the number of elements of
1745 the vector which contain meaningful data for this insn.
1746 The contents of this vector are what will be used to convert the insn
1747 template into assembler code, so you can change the assembler output
1748 by changing the contents of the vector. */
1750 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1751 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
1753 /* Print operand X (an rtx) in assembler syntax to file FILE.
1754 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1755 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1757 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
1759 /* Print a memory address as an operand to reference that memory location. */
1761 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
1763 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1764 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
1767 extern struct rtx_def *sh_compare_op0;
1768 extern struct rtx_def *sh_compare_op1;
1769 extern struct rtx_def *prepare_scc_operands();
1771 /* Which processor to schedule for. The elements of the enumeration must
1772 match exactly the cpu attribute in the sh.md file. */
1774 enum processor_type {
1781 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
1782 extern enum processor_type sh_cpu;
1784 extern enum machine_mode sh_addr_diff_vec_mode;
1786 extern int optimize; /* needed for gen_casesi. */
1788 /* Declare functions defined in sh.c and used in templates. */
1790 extern char *output_branch();
1791 extern char *output_ieee_ccmpeq();
1792 extern char *output_branchy_insn();
1793 extern char *output_shift();
1794 extern char *output_movedouble();
1795 extern char *output_movepcrel();
1796 extern char *output_jump_label_table();
1797 extern char *output_far_jump();
1799 enum mdep_reorg_phase_e
1801 SH_BEFORE_MDEP_REORG,
1802 SH_INSERT_USES_LABELS,
1803 SH_SHORTEN_BRANCHES0,
1805 SH_SHORTEN_BRANCHES1,
1809 extern enum mdep_reorg_phase_e mdep_reorg_phase;
1811 void machine_dependent_reorg ();
1812 struct rtx_def *sfunc_uses_reg ();
1813 int barrier_align ();
1815 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
1817 /* Generate calls to memcpy, memcmp and memset. */
1819 #define TARGET_MEM_FUNCTIONS
1821 /* Define this macro if you want to implement any pragmas. If defined, it
1822 is a C expression to be executed when #pragma is seen. The
1823 argument FILE is the stdio input stream from which the source
1824 text can be read. CH is the first character after the #pragma. The
1825 result of the expression is the terminating character found
1826 (newline or EOF). */
1827 #define HANDLE_PRAGMA(FILE, NODE) handle_pragma ((FILE), (NODE))
1829 /* Set when processing a function with pragma interrupt turned on. */
1831 extern int pragma_interrupt;
1833 /* Set to an RTX containing the address of the stack to switch to
1834 for interrupt functions. */
1835 extern struct rtx_def *sp_switch;
1837 /* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
1838 is a valid machine specific attribute for DECL.
1839 The attributes in ATTRIBUTES have previously been assigned to DECL. */
1840 extern int sh_valid_machine_decl_attribute ();
1841 #define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
1842 sh_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
1845 #define MOVE_RATIO (TARGET_SMALLCODE ? 2 : 16)
1847 /* Instructions with unfilled delay slots take up an extra two bytes for
1848 the nop in the delay slot. */
1850 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1851 if (((GET_CODE (X) == INSN \
1852 && GET_CODE (PATTERN (X)) != USE \
1853 && GET_CODE (PATTERN (X)) != CLOBBER) \
1854 || GET_CODE (X) == CALL_INSN \
1855 || (GET_CODE (X) == JUMP_INSN \
1856 && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \
1857 && GET_CODE (PATTERN (X)) != ADDR_VEC)) \
1858 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (X)))) != SEQUENCE \
1859 && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \
1862 /* Define the codes that are matched by predicates in sh.c. */
1863 #define PREDICATE_CODES \
1864 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1865 {"arith_reg_operand", {SUBREG, REG}}, \
1866 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
1867 {"braf_label_ref_operand", {LABEL_REF}}, \
1868 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1869 {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1870 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
1871 {"register_operand", {SUBREG, REG}},
1873 /* Define this macro if it is advisable to hold scalars in registers
1874 in a wider mode than that declared by the program. In such cases,
1875 the value is constrained to be within the bounds of the declared
1876 type, but kept valid in the wider mode. The signedness of the
1877 extension may differ from that of the type.
1879 Leaving the unsignedp unchanged gives better code than always setting it
1880 to 0. This is despite the fact that we have only signed char and short
1881 load instructions. */
1882 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1883 if (GET_MODE_CLASS (MODE) == MODE_INT \
1884 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1887 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
1888 extensions applied to char/short functions arguments. Defining
1889 PROMOTE_FUNCTION_RETURN does the same for function returns. */
1891 #define PROMOTE_FUNCTION_ARGS
1892 #define PROMOTE_FUNCTION_RETURN
1894 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
1895 and poping arguments. However, we do have push/pop instructions, and
1896 rather limited offsets (4 bits) in load/store instructions, so it isn't
1897 clear if this would give better code. If implemented, should check for
1898 compatibility problems. */
1900 /* A C statement (sans semicolon) to update the integer variable COST
1901 based on the relationship between INSN that is dependent on
1902 DEP_INSN through the dependence LINK. The default is to make no
1903 adjustment to COST. This can be used for example to specify to
1904 the scheduler that an output- or anti-dependence does not incur
1905 the same cost as a data-dependence. */
1907 #define ADJUST_COST(insn,link,dep_insn,cost) \
1911 if (GET_CODE(insn) == CALL_INSN) \
1913 /* The only input for a call that is timing-critical is the \
1914 function's address. */ \
1915 rtx call = PATTERN (insn); \
1917 if (GET_CODE (call) == PARALLEL) \
1918 call = XVECEXP (call, 0 ,0); \
1919 if (GET_CODE (call) == SET) \
1920 call = SET_SRC (call); \
1921 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM \
1922 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)) \
1925 /* All sfunc calls are parallels with at least four components. \
1926 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */ \
1927 else if (GET_CODE (PATTERN (insn)) == PARALLEL \
1928 && XVECLEN (PATTERN (insn), 0) >= 4 \
1929 && (reg = sfunc_uses_reg (insn))) \
1931 /* Likewise, the most timing critical input for an sfuncs call \
1932 is the function address. However, sfuncs typically start \
1933 using their arguments pretty quickly. \
1934 Assume a four cycle delay before they are needed. */ \
1935 if (! reg_set_p (reg, dep_insn)) \
1938 /* Adjust load_si / pcload_si type insns latency. Use the known \
1939 nominal latency and form of the insn to speed up the check. */ \
1940 else if (cost == 3 \
1941 && GET_CODE (PATTERN (dep_insn)) == SET \
1942 /* Latency for dmpy type insns is also 3, so check the that \
1943 it's actually a move insn. */ \
1944 && general_movsrc_operand (SET_SRC (PATTERN (dep_insn)), SImode))\
1948 /* For the sake of libgcc2.c, indicate target supports atexit. */
1951 #define SH_DYNAMIC_SHIFT_COST (TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
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