1 /* Output routines for GCC for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
28 #include "insn-config.h"
36 #include "hard-reg-set.h"
38 #include "insn-attr.h"
42 #include "integrate.h"
45 #include "target-def.h"
47 #include "langhooks.h"
49 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
51 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
52 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
54 /* These are some macros to abstract register modes. */
55 #define CONST_OK_FOR_ADD(size) \
56 (TARGET_SHMEDIA ? CONST_OK_FOR_P (size) : CONST_OK_FOR_I (size))
57 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
58 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
59 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
61 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
62 int current_function_interrupt;
64 /* ??? The pragma interrupt support will not work for SH3. */
65 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
66 output code for the next function appropriate for an interrupt handler. */
69 /* This is set by the trap_exit attribute for functions. It specifies
70 a trap number to be used in a trapa instruction at function exit
71 (instead of an rte instruction). */
74 /* This is used by the sp_switch attribute for functions. It specifies
75 a variable holding the address of the stack the interrupt function
76 should switch to/from at entry/exit. */
79 /* This is set by #pragma trapa, and is similar to the above, except that
80 the compiler doesn't emit code to preserve all registers. */
81 static int pragma_trapa;
83 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
84 which has a separate set of low regs for User and Supervisor modes.
85 This should only be used for the lowest level of interrupts. Higher levels
86 of interrupts must save the registers in case they themselves are
88 int pragma_nosave_low_regs;
90 /* This is used for communication between SETUP_INCOMING_VARARGS and
91 sh_expand_prologue. */
92 int current_function_anonymous_args;
94 /* Global variables for machine-dependent things. */
96 /* Which cpu are we scheduling for. */
97 enum processor_type sh_cpu;
99 /* Saved operands from the last compare to use when we generate an scc
105 /* Provides the class number of the smallest class containing
108 int regno_reg_class[FIRST_PSEUDO_REGISTER] =
110 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
111 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
112 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
113 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
114 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
127 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
128 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
129 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
130 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
143 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
144 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
145 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
146 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
147 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
151 char sh_register_names[FIRST_PSEUDO_REGISTER] \
152 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
154 char sh_additional_register_names[ADDREGNAMES_SIZE] \
155 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
156 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
158 /* Provide reg_class from a letter such as appears in the machine
159 description. *: target independently reserved letter.
160 reg_class_from_letter['e' - 'a'] is set to NO_REGS for TARGET_FMOVD. */
162 enum reg_class reg_class_from_letter[] =
164 /* a */ ALL_REGS, /* b */ TARGET_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
165 /* e */ FP_REGS, /* f */ FP_REGS, /* g **/ NO_REGS, /* h */ NO_REGS,
166 /* i **/ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
167 /* m **/ NO_REGS, /* n **/ NO_REGS, /* o **/ NO_REGS, /* p **/ NO_REGS,
168 /* q */ NO_REGS, /* r **/ NO_REGS, /* s **/ NO_REGS, /* t */ T_REGS,
169 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
170 /* y */ FPUL_REGS, /* z */ R0_REGS
173 int assembler_dialect;
175 static void split_branches PARAMS ((rtx));
176 static int branch_dest PARAMS ((rtx));
177 static void force_into PARAMS ((rtx, rtx));
178 static void print_slot PARAMS ((rtx));
179 static rtx add_constant PARAMS ((rtx, enum machine_mode, rtx));
180 static void dump_table PARAMS ((rtx));
181 static int hi_const PARAMS ((rtx));
182 static int broken_move PARAMS ((rtx));
183 static int mova_p PARAMS ((rtx));
184 static rtx find_barrier PARAMS ((int, rtx, rtx));
185 static int noncall_uses_reg PARAMS ((rtx, rtx, rtx *));
186 static rtx gen_block_redirect PARAMS ((rtx, int, int));
187 static void output_stack_adjust PARAMS ((int, rtx, int, rtx (*) (rtx)));
188 static rtx frame_insn PARAMS ((rtx));
189 static rtx push PARAMS ((int));
190 static void pop PARAMS ((int));
191 static void push_regs PARAMS ((HOST_WIDE_INT *));
192 static void calc_live_regs PARAMS ((int *, HOST_WIDE_INT *));
193 static void mark_use PARAMS ((rtx, rtx *));
194 static HOST_WIDE_INT rounded_frame_size PARAMS ((int));
195 static rtx mark_constant_pool_use PARAMS ((rtx));
196 const struct attribute_spec sh_attribute_table[];
197 static tree sh_handle_interrupt_handler_attribute PARAMS ((tree *, tree, tree, int, bool *));
198 static tree sh_handle_sp_switch_attribute PARAMS ((tree *, tree, tree, int, bool *));
199 static tree sh_handle_trap_exit_attribute PARAMS ((tree *, tree, tree, int, bool *));
200 static void sh_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
201 static void sh_insert_attributes PARAMS ((tree, tree *));
202 static int sh_adjust_cost PARAMS ((rtx, rtx, rtx, int));
203 static int sh_use_dfa_interface PARAMS ((void));
204 static int sh_issue_rate PARAMS ((void));
205 static bool sh_function_ok_for_sibcall PARAMS ((tree, tree));
207 static bool sh_cannot_modify_jumps_p PARAMS ((void));
208 static bool sh_ms_bitfield_layout_p PARAMS ((tree));
210 static void sh_encode_section_info PARAMS ((tree, int));
211 static const char *sh_strip_name_encoding PARAMS ((const char *));
212 static void sh_init_builtins PARAMS ((void));
213 static void sh_media_init_builtins PARAMS ((void));
214 static rtx sh_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int));
215 static int flow_dependent_p PARAMS ((rtx, rtx));
216 static void flow_dependent_p_1 PARAMS ((rtx, rtx, void *));
217 static int shiftcosts PARAMS ((rtx));
218 static int andcosts PARAMS ((rtx));
219 static int addsubcosts PARAMS ((rtx));
220 static int multcosts PARAMS ((rtx));
221 static bool unspec_caller_rtx_p PARAMS ((rtx));
222 static bool sh_cannot_copy_insn_p PARAMS ((rtx));
223 static bool sh_rtx_costs PARAMS ((rtx, int, int, int *));
224 static int sh_address_cost PARAMS ((rtx));
226 /* Initialize the GCC target structure. */
227 #undef TARGET_ATTRIBUTE_TABLE
228 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
230 /* The next two are used for debug info when compiling with -gdwarf. */
231 #undef TARGET_ASM_UNALIGNED_HI_OP
232 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
233 #undef TARGET_ASM_UNALIGNED_SI_OP
234 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
236 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
237 #undef TARGET_ASM_UNALIGNED_DI_OP
238 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
239 #undef TARGET_ASM_ALIGNED_DI_OP
240 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
242 #undef TARGET_ASM_FUNCTION_EPILOGUE
243 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
245 #undef TARGET_INSERT_ATTRIBUTES
246 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
248 #undef TARGET_SCHED_ADJUST_COST
249 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
251 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
252 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
254 #undef TARGET_SCHED_ISSUE_RATE
255 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
257 #undef TARGET_CANNOT_MODIFY_JUMPS_P
258 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
260 #undef TARGET_MS_BITFIELD_LAYOUT_P
261 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
263 #undef TARGET_ENCODE_SECTION_INFO
264 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
265 #undef TARGET_STRIP_NAME_ENCODING
266 #define TARGET_STRIP_NAME_ENCODING sh_strip_name_encoding
268 #undef TARGET_INIT_BUILTINS
269 #define TARGET_INIT_BUILTINS sh_init_builtins
270 #undef TARGET_EXPAND_BUILTIN
271 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
273 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
274 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
276 #undef TARGET_CANNOT_COPY_INSN_P
277 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
278 #undef TARGET_RTX_COSTS
279 #define TARGET_RTX_COSTS sh_rtx_costs
280 #undef TARGET_ADDRESS_COST
281 #define TARGET_ADDRESS_COST sh_address_cost
284 #undef TARGET_HAVE_TLS
285 #define TARGET_HAVE_TLS true
288 struct gcc_target targetm = TARGET_INITIALIZER;
290 /* Print the operand address in x to the stream. */
293 print_operand_address (stream, x)
297 switch (GET_CODE (x))
301 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
306 rtx base = XEXP (x, 0);
307 rtx index = XEXP (x, 1);
309 switch (GET_CODE (index))
312 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
313 reg_names[true_regnum (base)]);
319 int base_num = true_regnum (base);
320 int index_num = true_regnum (index);
322 fprintf (stream, "@(r0,%s)",
323 reg_names[MAX (base_num, index_num)]);
335 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
339 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
343 x = mark_constant_pool_use (x);
344 output_addr_const (stream, x);
349 /* Print operand x (an rtx) in assembler syntax to file stream
350 according to modifier code.
352 '.' print a .s if insn needs delay slot
353 ',' print LOCAL_LABEL_PREFIX
354 '@' print trap, rte or rts depending upon pragma interruptness
355 '#' output a nop if there is nothing to put in the delay slot
356 ''' print likelyhood suffix (/u for unlikely).
357 'O' print a constant without the #
358 'R' print the LSW of a dp value - changes if in little endian
359 'S' print the MSW of a dp value - changes if in little endian
360 'T' print the next word of a dp value - same as 'R' in big endian mode.
361 'M' print an `x' if `m' will print `base,index'.
362 'N' print 'r63' if the operand is (const_int 0).
363 'm' print a pair `base,offset' or `base,index', for LD and ST.
364 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
365 'o' output an operator. */
368 print_operand (stream, x, code)
377 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
378 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
379 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
382 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
386 fprintf (stream, "trapa #%d", trap_exit);
387 else if (sh_cfun_interrupt_handler_p ())
388 fprintf (stream, "rte");
390 fprintf (stream, "rts");
393 /* Output a nop if there's nothing in the delay slot. */
394 if (dbr_sequence_length () == 0)
395 fprintf (stream, "\n\tnop");
399 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
401 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
402 fputs ("/u", stream);
406 x = mark_constant_pool_use (x);
407 output_addr_const (stream, x);
410 fputs (reg_names[REGNO (x) + LSW], (stream));
413 fputs (reg_names[REGNO (x) + MSW], (stream));
416 /* Next word of a double. */
417 switch (GET_CODE (x))
420 fputs (reg_names[REGNO (x) + 1], (stream));
423 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
424 && GET_CODE (XEXP (x, 0)) != POST_INC)
425 x = adjust_address (x, SImode, 4);
426 print_operand_address (stream, XEXP (x, 0));
433 switch (GET_CODE (x))
435 case PLUS: fputs ("add", stream); break;
436 case MINUS: fputs ("sub", stream); break;
437 case MULT: fputs ("mul", stream); break;
438 case DIV: fputs ("div", stream); break;
439 case EQ: fputs ("eq", stream); break;
440 case NE: fputs ("ne", stream); break;
441 case GT: case LT: fputs ("gt", stream); break;
442 case GE: case LE: fputs ("ge", stream); break;
443 case GTU: case LTU: fputs ("gtu", stream); break;
444 case GEU: case LEU: fputs ("geu", stream); break;
450 if (GET_CODE (x) == MEM
451 && GET_CODE (XEXP (x, 0)) == PLUS
452 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
453 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
458 if (GET_CODE (x) != MEM)
461 switch (GET_CODE (x))
465 print_operand (stream, x, 0);
466 fputs (", 0", stream);
470 print_operand (stream, XEXP (x, 0), 0);
471 fputs (", ", stream);
472 print_operand (stream, XEXP (x, 1), 0);
481 if (x == CONST0_RTX (GET_MODE (x)))
483 fprintf ((stream), "r63");
488 if (GET_CODE (x) == CONST_INT)
490 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
497 switch (GET_CODE (x))
499 /* FIXME: We need this on SHmedia32 because reload generates
500 some sign-extended HI or QI loads into DImode registers
501 but, because Pmode is SImode, the address ends up with a
502 subreg:SI of the DImode register. Maybe reload should be
503 fixed so as to apply alter_subreg to such loads? */
505 if (SUBREG_BYTE (x) != 0
506 || GET_CODE (SUBREG_REG (x)) != REG)
513 if (FP_REGISTER_P (REGNO (x))
514 && GET_MODE (x) == V16SFmode)
515 fprintf ((stream), "mtrx%s", reg_names[REGNO (x)] + 2);
516 else if (FP_REGISTER_P (REGNO (x))
517 && GET_MODE (x) == V4SFmode)
518 fprintf ((stream), "fv%s", reg_names[REGNO (x)] + 2);
519 else if (GET_CODE (x) == REG
520 && GET_MODE (x) == V2SFmode)
521 fprintf ((stream), "fp%s", reg_names[REGNO (x)] + 2);
522 else if (FP_REGISTER_P (REGNO (x))
523 && GET_MODE_SIZE (GET_MODE (x)) > 4)
524 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
526 fputs (reg_names[REGNO (x)], (stream));
530 output_address (XEXP (x, 0));
535 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
536 && GET_MODE (XEXP (x, 0)) == DImode
537 && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE
538 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)
540 rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0);
543 if (GET_CODE (val) == ASHIFTRT)
546 if (GET_CODE (XEXP (val, 0)) == CONST)
548 output_addr_const (stream, XEXP (val, 0));
549 if (GET_CODE (XEXP (val, 0)) == CONST)
551 fputs (" >> ", stream);
552 output_addr_const (stream, XEXP (val, 1));
557 if (GET_CODE (val) == CONST)
559 output_addr_const (stream, val);
560 if (GET_CODE (val) == CONST)
563 fputs (" & 65535)", stream);
571 output_addr_const (stream, x);
578 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
580 force_into (value, target)
583 value = force_operand (value, target);
584 if (! rtx_equal_p (value, target))
585 emit_insn (gen_move_insn (target, value));
588 /* Emit code to perform a block move. Choose the best method.
590 OPERANDS[0] is the destination.
591 OPERANDS[1] is the source.
592 OPERANDS[2] is the size.
593 OPERANDS[3] is the alignment safe to use. */
596 expand_block_move (operands)
599 int align = INTVAL (operands[3]);
600 int constp = (GET_CODE (operands[2]) == CONST_INT);
601 int bytes = (constp ? INTVAL (operands[2]) : 0);
603 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
604 alignment, or if it isn't a multiple of 4 bytes, then fail. */
605 if (! constp || align < 4 || (bytes % 4 != 0))
612 else if (bytes == 12)
617 rtx r4 = gen_rtx (REG, SImode, 4);
618 rtx r5 = gen_rtx (REG, SImode, 5);
620 entry_name = get_identifier ("__movstrSI12_i4");
622 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
623 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
624 force_into (XEXP (operands[0], 0), r4);
625 force_into (XEXP (operands[1], 0), r5);
626 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
629 else if (! TARGET_SMALLCODE)
635 rtx r4 = gen_rtx (REG, SImode, 4);
636 rtx r5 = gen_rtx (REG, SImode, 5);
637 rtx r6 = gen_rtx (REG, SImode, 6);
639 entry_name = get_identifier (bytes & 4
641 : "__movstr_i4_even");
642 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
643 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
644 force_into (XEXP (operands[0], 0), r4);
645 force_into (XEXP (operands[1], 0), r5);
648 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
649 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
661 rtx r4 = gen_rtx_REG (SImode, 4);
662 rtx r5 = gen_rtx_REG (SImode, 5);
664 sprintf (entry, "__movstrSI%d", bytes);
665 entry_name = get_identifier (entry);
666 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
667 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
668 force_into (XEXP (operands[0], 0), r4);
669 force_into (XEXP (operands[1], 0), r5);
670 emit_insn (gen_block_move_real (func_addr_rtx));
674 /* This is the same number of bytes as a memcpy call, but to a different
675 less common function name, so this will occasionally use more space. */
676 if (! TARGET_SMALLCODE)
681 int final_switch, while_loop;
682 rtx r4 = gen_rtx_REG (SImode, 4);
683 rtx r5 = gen_rtx_REG (SImode, 5);
684 rtx r6 = gen_rtx_REG (SImode, 6);
686 entry_name = get_identifier ("__movstr");
687 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
688 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
689 force_into (XEXP (operands[0], 0), r4);
690 force_into (XEXP (operands[1], 0), r5);
692 /* r6 controls the size of the move. 16 is decremented from it
693 for each 64 bytes moved. Then the negative bit left over is used
694 as an index into a list of move instructions. e.g., a 72 byte move
695 would be set up with size(r6) = 14, for one iteration through the
696 big while loop, and a switch of -2 for the last part. */
698 final_switch = 16 - ((bytes / 4) % 16);
699 while_loop = ((bytes / 4) / 16 - 1) * 16;
700 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
701 emit_insn (gen_block_lump_real (func_addr_rtx));
708 /* Prepare operands for a move define_expand; specifically, one of the
709 operands must be in a register. */
712 prepare_move_operands (operands, mode)
714 enum machine_mode mode;
716 if ((mode == SImode || mode == DImode)
718 && ! ((mode == Pmode || mode == ptr_mode)
719 && tls_symbolic_operand (operands[1], Pmode) != 0))
722 if (SYMBOLIC_CONST_P (operands[1]))
724 if (GET_CODE (operands[0]) == MEM)
725 operands[1] = force_reg (Pmode, operands[1]);
726 else if (TARGET_SHMEDIA
727 && GET_CODE (operands[1]) == LABEL_REF
728 && target_reg_operand (operands[0], mode))
732 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
733 operands[1] = legitimize_pic_address (operands[1], mode, temp);
736 else if (GET_CODE (operands[1]) == CONST
737 && GET_CODE (XEXP (operands[1], 0)) == PLUS
738 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
740 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
741 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
743 operands[1] = expand_binop (mode, add_optab, temp,
744 XEXP (XEXP (operands[1], 0), 1),
745 no_new_pseudos ? temp
746 : gen_reg_rtx (Pmode),
751 if (! reload_in_progress && ! reload_completed)
753 /* Copy the source to a register if both operands aren't registers. */
754 if (! register_operand (operands[0], mode)
755 && ! sh_register_operand (operands[1], mode))
756 operands[1] = copy_to_mode_reg (mode, operands[1]);
758 /* This case can happen while generating code to move the result
759 of a library call to the target. Reject `st r0,@(rX,rY)' because
760 reload will fail to find a spill register for rX, since r0 is already
761 being used for the source. */
762 else if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 0
763 && GET_CODE (operands[0]) == MEM
764 && GET_CODE (XEXP (operands[0], 0)) == PLUS
765 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
766 operands[1] = copy_to_mode_reg (mode, operands[1]);
769 if (mode == Pmode || mode == ptr_mode)
772 enum tls_model tls_kind;
776 if ((tls_kind = tls_symbolic_operand (op1, Pmode)))
778 rtx tga_op1, tga_ret, tmp, tmp2;
783 case TLS_MODEL_GLOBAL_DYNAMIC:
784 tga_ret = gen_rtx_REG (Pmode, R0_REG);
785 emit_insn (gen_tls_global_dynamic (tga_ret, op1));
789 case TLS_MODEL_LOCAL_DYNAMIC:
790 tga_ret = gen_rtx_REG (Pmode, R0_REG);
791 emit_insn (gen_tls_local_dynamic (tga_ret, op1));
793 tmp = gen_reg_rtx (Pmode);
794 emit_move_insn (tmp, tga_ret);
796 if (register_operand (op0, Pmode))
799 tmp2 = gen_reg_rtx (Pmode);
801 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
805 case TLS_MODEL_INITIAL_EXEC:
807 emit_insn (gen_GOTaddr2picreg ());
808 tga_op1 = gen_reg_rtx (Pmode);
809 tmp = gen_sym2GOTTPOFF (op1);
810 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
814 case TLS_MODEL_LOCAL_EXEC:
815 tmp2 = gen_reg_rtx (Pmode);
816 emit_insn (gen_load_gbr (tmp2));
817 tmp = gen_reg_rtx (Pmode);
818 emit_insn (gen_symTPOFF2reg (tmp, op1));
819 RTX_UNCHANGING_P (tmp) = 1;
821 if (register_operand (op0, Pmode))
824 op1 = gen_reg_rtx (Pmode);
826 emit_insn (gen_addsi3 (op1, tmp, tmp2));
839 /* Prepare the operands for an scc instruction; make sure that the
840 compare has been done. */
842 prepare_scc_operands (code)
845 rtx t_reg = gen_rtx_REG (SImode, T_REG);
846 enum rtx_code oldcode = code;
847 enum machine_mode mode;
849 /* First need a compare insn. */
853 /* It isn't possible to handle this case. */
872 rtx tmp = sh_compare_op0;
873 sh_compare_op0 = sh_compare_op1;
874 sh_compare_op1 = tmp;
877 mode = GET_MODE (sh_compare_op0);
878 if (mode == VOIDmode)
879 mode = GET_MODE (sh_compare_op1);
881 sh_compare_op0 = force_reg (mode, sh_compare_op0);
882 if ((code != EQ && code != NE
883 && (sh_compare_op1 != const0_rtx
884 || code == GTU || code == GEU || code == LTU || code == LEU))
885 || (mode == DImode && sh_compare_op1 != const0_rtx)
886 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
887 sh_compare_op1 = force_reg (mode, sh_compare_op1);
889 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
890 (mode == SFmode ? emit_sf_insn : emit_df_insn)
891 (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
892 gen_rtx (SET, VOIDmode, t_reg,
893 gen_rtx (code, SImode,
894 sh_compare_op0, sh_compare_op1)),
895 gen_rtx (USE, VOIDmode, get_fpscr_rtx ()))));
897 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
898 gen_rtx (code, SImode, sh_compare_op0,
904 /* Called from the md file, set up the operands of a compare instruction. */
907 from_compare (operands, code)
911 enum machine_mode mode = GET_MODE (sh_compare_op0);
913 if (mode == VOIDmode)
914 mode = GET_MODE (sh_compare_op1);
917 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
919 /* Force args into regs, since we can't use constants here. */
920 sh_compare_op0 = force_reg (mode, sh_compare_op0);
921 if (sh_compare_op1 != const0_rtx
922 || code == GTU || code == GEU
923 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
924 sh_compare_op1 = force_reg (mode, sh_compare_op1);
926 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
928 from_compare (operands, GT);
929 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
932 insn = gen_rtx_SET (VOIDmode,
933 gen_rtx_REG (SImode, T_REG),
934 gen_rtx (code, SImode, sh_compare_op0,
936 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
938 insn = gen_rtx (PARALLEL, VOIDmode,
940 gen_rtx (USE, VOIDmode, get_fpscr_rtx ())));
941 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
947 /* Functions to output assembly code. */
949 /* Return a sequence of instructions to perform DI or DF move.
951 Since the SH cannot move a DI or DF in one instruction, we have
952 to take care when we see overlapping source and dest registers. */
955 output_movedouble (insn, operands, mode)
956 rtx insn ATTRIBUTE_UNUSED;
958 enum machine_mode mode;
960 rtx dst = operands[0];
961 rtx src = operands[1];
963 if (GET_CODE (dst) == MEM
964 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
965 return "mov.l %T1,%0\n\tmov.l %1,%0";
967 if (register_operand (dst, mode)
968 && register_operand (src, mode))
970 if (REGNO (src) == MACH_REG)
971 return "sts mach,%S0\n\tsts macl,%R0";
973 /* When mov.d r1,r2 do r2->r3 then r1->r2;
974 when mov.d r1,r0 do r1->r0 then r2->r1. */
976 if (REGNO (src) + 1 == REGNO (dst))
977 return "mov %T1,%T0\n\tmov %1,%0";
979 return "mov %1,%0\n\tmov %T1,%T0";
981 else if (GET_CODE (src) == CONST_INT)
983 if (INTVAL (src) < 0)
984 output_asm_insn ("mov #-1,%S0", operands);
986 output_asm_insn ("mov #0,%S0", operands);
990 else if (GET_CODE (src) == MEM)
993 int dreg = REGNO (dst);
994 rtx inside = XEXP (src, 0);
996 if (GET_CODE (inside) == REG)
997 ptrreg = REGNO (inside);
998 else if (GET_CODE (inside) == SUBREG)
999 ptrreg = subreg_regno (inside);
1000 else if (GET_CODE (inside) == PLUS)
1002 ptrreg = REGNO (XEXP (inside, 0));
1003 /* ??? A r0+REG address shouldn't be possible here, because it isn't
1004 an offsettable address. Unfortunately, offsettable addresses use
1005 QImode to check the offset, and a QImode offsettable address
1006 requires r0 for the other operand, which is not currently
1007 supported, so we can't use the 'o' constraint.
1008 Thus we must check for and handle r0+REG addresses here.
1009 We punt for now, since this is likely very rare. */
1010 if (GET_CODE (XEXP (inside, 1)) == REG)
1013 else if (GET_CODE (inside) == LABEL_REF)
1014 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
1015 else if (GET_CODE (inside) == POST_INC)
1016 return "mov.l %1,%0\n\tmov.l %1,%T0";
1020 /* Work out the safe way to copy. Copy into the second half first. */
1022 return "mov.l %T1,%T0\n\tmov.l %1,%0";
1025 return "mov.l %1,%0\n\tmov.l %T1,%T0";
1028 /* Print an instruction which would have gone into a delay slot after
1029 another instruction, but couldn't because the other instruction expanded
1030 into a sequence where putting the slot insn at the end wouldn't work. */
1036 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
1038 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
1042 output_far_jump (insn, op)
1046 struct { rtx lab, reg, op; } this;
1047 rtx braf_base_lab = NULL_RTX;
1050 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
1052 this.lab = gen_label_rtx ();
1056 && offset - get_attr_length (insn) <= 32766)
1059 jump = "mov.w %O0,%1; braf %1";
1067 jump = "mov.l %O0,%1; braf %1";
1069 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1072 jump = "mov.l %O0,%1; jmp @%1";
1074 /* If we have a scratch register available, use it. */
1075 if (GET_CODE (PREV_INSN (insn)) == INSN
1076 && INSN_CODE (PREV_INSN (insn)) == CODE_FOR_indirect_jump_scratch)
1078 this.reg = SET_DEST (PATTERN (PREV_INSN (insn)));
1079 if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2)
1080 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1081 output_asm_insn (jump, &this.lab);
1082 if (dbr_sequence_length ())
1083 print_slot (final_sequence);
1085 output_asm_insn ("nop", 0);
1089 /* Output the delay slot insn first if any. */
1090 if (dbr_sequence_length ())
1091 print_slot (final_sequence);
1093 this.reg = gen_rtx_REG (SImode, 13);
1094 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1095 Fortunately, MACL is fixed and call-clobbered, and we never
1096 need its value across jumps, so save r13 in it instead of in
1099 output_asm_insn ("lds r13, macl", 0);
1101 output_asm_insn ("mov.l r13,@-r15", 0);
1102 output_asm_insn (jump, &this.lab);
1104 output_asm_insn ("sts macl, r13", 0);
1106 output_asm_insn ("mov.l @r15+,r13", 0);
1108 if (far && flag_pic && TARGET_SH2)
1110 braf_base_lab = gen_label_rtx ();
1111 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1112 CODE_LABEL_NUMBER (braf_base_lab));
1115 output_asm_insn (".align 2", 0);
1116 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
1118 if (far && flag_pic)
1121 this.lab = braf_base_lab;
1122 output_asm_insn (".long %O2-%O0", &this.lab);
1125 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
1129 /* Local label counter, used for constants in the pool and inside
1130 pattern branches. */
1132 static int lf = 100;
1134 /* Output code for ordinary branches. */
1137 output_branch (logic, insn, operands)
1142 switch (get_attr_length (insn))
1145 /* This can happen if filling the delay slot has caused a forward
1146 branch to exceed its range (we could reverse it, but only
1147 when we know we won't overextend other branches; this should
1148 best be handled by relaxation).
1149 It can also happen when other condbranches hoist delay slot insn
1150 from their destination, thus leading to code size increase.
1151 But the branch will still be in the range -4092..+4098 bytes. */
1156 /* The call to print_slot will clobber the operands. */
1157 rtx op0 = operands[0];
1159 /* If the instruction in the delay slot is annulled (true), then
1160 there is no delay slot where we can put it now. The only safe
1161 place for it is after the label. final will do that by default. */
1164 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1166 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
1167 ASSEMBLER_DIALECT ? "/" : ".", label);
1168 print_slot (final_sequence);
1171 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
1173 output_asm_insn ("bra\t%l0", &op0);
1174 fprintf (asm_out_file, "\tnop\n");
1175 (*targetm.asm_out.internal_label)(asm_out_file, "LF", label);
1179 /* When relaxing, handle this like a short branch. The linker
1180 will fix it up if it still doesn't fit after relaxation. */
1182 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
1184 /* These are for SH2e, in which we have to account for the
1185 extra nop because of the hardware bug in annulled branches. */
1192 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1194 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
1196 ASSEMBLER_DIALECT ? "/" : ".", label);
1197 fprintf (asm_out_file, "\tnop\n");
1198 output_asm_insn ("bra\t%l0", operands);
1199 fprintf (asm_out_file, "\tnop\n");
1200 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
1204 /* When relaxing, fall through. */
1209 sprintf (buffer, "b%s%ss\t%%l0",
1211 ASSEMBLER_DIALECT ? "/" : ".");
1212 output_asm_insn (buffer, &operands[0]);
1217 /* There should be no longer branches now - that would
1218 indicate that something has destroyed the branches set
1219 up in machine_dependent_reorg. */
1225 output_branchy_insn (code, template, insn, operands)
1227 const char *template;
1231 rtx next_insn = NEXT_INSN (insn);
1233 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
1235 rtx src = SET_SRC (PATTERN (next_insn));
1236 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
1238 /* Following branch not taken */
1239 operands[9] = gen_label_rtx ();
1240 emit_label_after (operands[9], next_insn);
1241 INSN_ADDRESSES_NEW (operands[9],
1242 INSN_ADDRESSES (INSN_UID (next_insn))
1243 + get_attr_length (next_insn));
1248 int offset = (branch_dest (next_insn)
1249 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
1250 if (offset >= -252 && offset <= 258)
1252 if (GET_CODE (src) == IF_THEN_ELSE)
1254 src = XEXP (src, 1);
1260 operands[9] = gen_label_rtx ();
1261 emit_label_after (operands[9], insn);
1262 INSN_ADDRESSES_NEW (operands[9],
1263 INSN_ADDRESSES (INSN_UID (insn))
1264 + get_attr_length (insn));
1269 output_ieee_ccmpeq (insn, operands)
1270 rtx insn, *operands;
1272 return output_branchy_insn (NE, "bt\t%l9\\;fcmp/eq\t%1,%0", insn, operands);
1275 /* Output to FILE the start of the assembler file. */
1278 output_file_start (file)
1281 output_file_directive (file, main_input_filename);
1283 /* Switch to the data section so that the coffsem symbol
1284 isn't in the text section. */
1287 if (TARGET_LITTLE_ENDIAN)
1288 fprintf (file, "\t.little\n");
1290 if (TARGET_SHCOMPACT)
1291 fprintf (file, "\t.mode\tSHcompact\n");
1292 else if (TARGET_SHMEDIA)
1293 fprintf (file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1294 TARGET_SHMEDIA64 ? 64 : 32);
1297 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
1300 unspec_caller_rtx_p (pat)
1303 switch (GET_CODE (pat))
1306 return unspec_caller_rtx_p (XEXP (pat, 0));
1309 if (unspec_caller_rtx_p (XEXP (pat, 0)))
1311 return unspec_caller_rtx_p (XEXP (pat, 1));
1313 if (XINT (pat, 1) == UNSPEC_CALLER)
1322 /* Indicate that INSN cannot be duplicated. This is true for insn
1323 that generates an unique label. */
1326 sh_cannot_copy_insn_p (insn)
1331 if (!reload_completed || !flag_pic)
1334 if (GET_CODE (insn) != INSN)
1336 if (asm_noperands (insn) >= 0)
1339 pat = PATTERN (insn);
1340 if (GET_CODE (pat) != SET)
1342 pat = SET_SRC (pat);
1344 if (unspec_caller_rtx_p (pat))
1350 /* Actual number of instructions used to make a shift by N. */
1351 static const char ashiftrt_insns[] =
1352 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1354 /* Left shift and logical right shift are the same. */
1355 static const char shift_insns[] =
1356 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1358 /* Individual shift amounts needed to get the above length sequences.
1359 One bit right shifts clobber the T bit, so when possible, put one bit
1360 shifts in the middle of the sequence, so the ends are eligible for
1361 branch delay slots. */
1362 static const short shift_amounts[32][5] = {
1363 {0}, {1}, {2}, {2, 1},
1364 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1365 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1366 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1367 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1368 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1369 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1370 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1372 /* Likewise, but for shift amounts < 16, up to three highmost bits
1373 might be clobbered. This is typically used when combined with some
1374 kind of sign or zero extension. */
1376 static const char ext_shift_insns[] =
1377 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1379 static const short ext_shift_amounts[32][4] = {
1380 {0}, {1}, {2}, {2, 1},
1381 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1382 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1383 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1384 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1385 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1386 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1387 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1389 /* Assuming we have a value that has been sign-extended by at least one bit,
1390 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1391 to shift it by N without data loss, and quicker than by other means? */
1392 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1394 /* This is used in length attributes in sh.md to help compute the length
1395 of arbitrary constant shift instructions. */
1398 shift_insns_rtx (insn)
1401 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1402 int shift_count = INTVAL (XEXP (set_src, 1));
1403 enum rtx_code shift_code = GET_CODE (set_src);
1408 return ashiftrt_insns[shift_count];
1411 return shift_insns[shift_count];
1417 /* Return the cost of a shift. */
1428 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
1430 if (GET_MODE (x) == DImode
1431 && GET_CODE (XEXP (x, 1)) == CONST_INT
1432 && INTVAL (XEXP (x, 1)) == 1)
1435 /* Everything else is invalid, because there is no pattern for it. */
1438 /* If shift by a non constant, then this will be expensive. */
1439 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1440 return SH_DYNAMIC_SHIFT_COST;
1442 value = INTVAL (XEXP (x, 1));
1444 /* Otherwise, return the true cost in instructions. */
1445 if (GET_CODE (x) == ASHIFTRT)
1447 int cost = ashiftrt_insns[value];
1448 /* If SH3, then we put the constant in a reg and use shad. */
1449 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
1450 cost = 1 + SH_DYNAMIC_SHIFT_COST;
1454 return shift_insns[value];
1457 /* Return the cost of an AND operation. */
1465 /* Anding with a register is a single cycle and instruction. */
1466 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1469 i = INTVAL (XEXP (x, 1));
1473 if ((GET_CODE (XEXP (x, 1)) == CONST_INT
1474 && CONST_OK_FOR_J (INTVAL (XEXP (x, 1))))
1475 || EXTRA_CONSTRAINT_S (XEXP (x, 1)))
1481 /* These constants are single cycle extu.[bw] instructions. */
1482 if (i == 0xff || i == 0xffff)
1484 /* Constants that can be used in an and immediate instruction is a single
1485 cycle, but this requires r0, so make it a little more expensive. */
1486 if (CONST_OK_FOR_L (i))
1488 /* Constants that can be loaded with a mov immediate and an and.
1489 This case is probably unnecessary. */
1490 if (CONST_OK_FOR_I (i))
1492 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1493 This case is probably unnecessary. */
1497 /* Return the cost of an addition or a subtraction. */
1503 /* Adding a register is a single cycle insn. */
1504 if (GET_CODE (XEXP (x, 1)) == REG
1505 || GET_CODE (XEXP (x, 1)) == SUBREG)
1508 /* Likewise for small constants. */
1509 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1510 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
1514 switch (GET_CODE (XEXP (x, 1)))
1519 return TARGET_SHMEDIA64 ? 5 : 3;
1522 if (CONST_OK_FOR_J (INTVAL (XEXP (x, 1))))
1524 else if (CONST_OK_FOR_J (INTVAL (XEXP (x, 1)) >> 16))
1526 else if (CONST_OK_FOR_J ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
1534 /* Any other constant requires a 2 cycle pc-relative load plus an
1539 /* Return the cost of a multiply. */
1542 rtx x ATTRIBUTE_UNUSED;
1549 /* We have a mul insn, so we can never take more than the mul and the
1550 read of the mac reg, but count more because of the latency and extra
1552 if (TARGET_SMALLCODE)
1557 /* If we're aiming at small code, then just count the number of
1558 insns in a multiply call sequence. */
1559 if (TARGET_SMALLCODE)
1562 /* Otherwise count all the insns in the routine we'd be calling too. */
1566 /* Compute a (partial) cost for rtx X. Return true if the complete
1567 cost has been computed, and false if subexpressions should be
1568 scanned. In either case, *TOTAL contains the cost result. */
1571 sh_rtx_costs (x, code, outer_code, total)
1573 int code, outer_code, *total;
1580 if (INTVAL (x) == 0)
1582 else if (outer_code == AND && and_operand ((x), DImode))
1584 else if ((outer_code == IOR || outer_code == XOR
1585 || outer_code == PLUS)
1586 && CONST_OK_FOR_P (INTVAL (x)))
1588 else if (CONST_OK_FOR_J (INTVAL (x)))
1589 *total = COSTS_N_INSNS (outer_code != SET);
1590 else if (CONST_OK_FOR_J (INTVAL (x) >> 16))
1591 *total = COSTS_N_INSNS (2);
1592 else if (CONST_OK_FOR_J ((INTVAL (x) >> 16) >> 16))
1593 *total = COSTS_N_INSNS (3);
1595 *total = COSTS_N_INSNS (4);
1598 if (CONST_OK_FOR_I (INTVAL (x)))
1600 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
1601 && CONST_OK_FOR_L (INTVAL (x)))
1610 if (TARGET_SHMEDIA64)
1611 *total = COSTS_N_INSNS (4);
1612 else if (TARGET_SHMEDIA32)
1613 *total = COSTS_N_INSNS (2);
1620 *total = COSTS_N_INSNS (4);
1626 *total = COSTS_N_INSNS (addsubcosts (x));
1630 *total = COSTS_N_INSNS (andcosts (x));
1634 *total = COSTS_N_INSNS (multcosts (x));
1640 *total = COSTS_N_INSNS (shiftcosts (x));
1647 *total = COSTS_N_INSNS (20);
1660 /* Compute the cost of an address. For the SH, all valid addresses are
1661 the same cost. Use a slightly higher cost for reg + reg addressing,
1662 since it increases pressure on r0. */
1668 return (GET_CODE (X) == PLUS
1669 && ! CONSTANT_P (XEXP (X, 1))
1670 && ! TARGET_SHMEDIA ? 1 : 0);
1673 /* Code to expand a shift. */
1676 gen_ashift (type, n, reg)
1681 /* Negative values here come from the shift_amounts array. */
1694 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
1698 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
1700 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
1703 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
1708 /* Same for HImode */
1711 gen_ashift_hi (type, n, reg)
1716 /* Negative values here come from the shift_amounts array. */
1730 /* We don't have HImode right shift operations because using the
1731 ordinary 32 bit shift instructions for that doesn't generate proper
1732 zero/sign extension.
1733 gen_ashift_hi is only called in contexts where we know that the
1734 sign extension works out correctly. */
1737 if (GET_CODE (reg) == SUBREG)
1739 offset = SUBREG_BYTE (reg);
1740 reg = SUBREG_REG (reg);
1742 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
1746 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
1751 /* Output RTL to split a constant shift into its component SH constant
1752 shift instructions. */
1755 gen_shifty_op (code, operands)
1759 int value = INTVAL (operands[2]);
1762 /* Truncate the shift count in case it is out of bounds. */
1763 value = value & 0x1f;
1767 if (code == LSHIFTRT)
1769 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1770 emit_insn (gen_movt (operands[0]));
1773 else if (code == ASHIFT)
1775 /* There is a two instruction sequence for 31 bit left shifts,
1776 but it requires r0. */
1777 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
1779 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
1780 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1785 else if (value == 0)
1787 /* This can happen when not optimizing. We must output something here
1788 to prevent the compiler from aborting in final.c after the try_split
1790 emit_insn (gen_nop ());
1794 max = shift_insns[value];
1795 for (i = 0; i < max; i++)
1796 gen_ashift (code, shift_amounts[value][i], operands[0]);
1799 /* Same as above, but optimized for values where the topmost bits don't
1803 gen_shifty_hi_op (code, operands)
1807 int value = INTVAL (operands[2]);
1809 void (*gen_fun) PARAMS ((int, int, rtx));
1811 /* This operation is used by and_shl for SImode values with a few
1812 high bits known to be cleared. */
1816 emit_insn (gen_nop ());
1820 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
1823 max = ext_shift_insns[value];
1824 for (i = 0; i < max; i++)
1825 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1828 /* When shifting right, emit the shifts in reverse order, so that
1829 solitary negative values come first. */
1830 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
1831 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1834 /* Output RTL for an arithmetic right shift. */
1836 /* ??? Rewrite to use super-optimizer sequences. */
1839 expand_ashiftrt (operands)
1850 if (GET_CODE (operands[2]) != CONST_INT)
1852 rtx count = copy_to_mode_reg (SImode, operands[2]);
1853 emit_insn (gen_negsi2 (count, count));
1854 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1857 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
1858 > 1 + SH_DYNAMIC_SHIFT_COST)
1861 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
1862 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1866 if (GET_CODE (operands[2]) != CONST_INT)
1869 value = INTVAL (operands[2]) & 31;
1873 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
1876 else if (value >= 16 && value <= 19)
1878 wrk = gen_reg_rtx (SImode);
1879 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
1882 gen_ashift (ASHIFTRT, 1, wrk);
1883 emit_move_insn (operands[0], wrk);
1886 /* Expand a short sequence inline, longer call a magic routine. */
1887 else if (value <= 5)
1889 wrk = gen_reg_rtx (SImode);
1890 emit_move_insn (wrk, operands[1]);
1892 gen_ashift (ASHIFTRT, 1, wrk);
1893 emit_move_insn (operands[0], wrk);
1897 wrk = gen_reg_rtx (Pmode);
1899 /* Load the value into an arg reg and call a helper. */
1900 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1901 sprintf (func, "__ashiftrt_r4_%d", value);
1902 func_name = get_identifier (func);
1903 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (func_name));
1904 emit_move_insn (wrk, sym);
1905 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
1906 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
1911 sh_dynamicalize_shift_p (count)
1914 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
1917 /* Try to find a good way to implement the combiner pattern
1918 [(set (match_operand:SI 0 "register_operand" "r")
1919 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1920 (match_operand:SI 2 "const_int_operand" "n"))
1921 (match_operand:SI 3 "const_int_operand" "n"))) .
1922 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1923 return 0 for simple right / left or left/right shift combination.
1924 return 1 for a combination of shifts with zero_extend.
1925 return 2 for a combination of shifts with an AND that needs r0.
1926 return 3 for a combination of shifts with an AND that needs an extra
1927 scratch register, when the three highmost bits of the AND mask are clear.
1928 return 4 for a combination of shifts with an AND that needs an extra
1929 scratch register, when any of the three highmost bits of the AND mask
1931 If ATTRP is set, store an initial right shift width in ATTRP[0],
1932 and the instruction length in ATTRP[1] . These values are not valid
1934 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1935 shift_amounts for the last shift value that is to be used before the
1938 shl_and_kind (left_rtx, mask_rtx, attrp)
1939 rtx left_rtx, mask_rtx;
1942 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
1943 int left = INTVAL (left_rtx), right;
1945 int cost, best_cost = 10000;
1946 int best_right = 0, best_len = 0;
1950 if (left < 0 || left > 31)
1952 if (GET_CODE (mask_rtx) == CONST_INT)
1953 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
1955 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
1956 /* Can this be expressed as a right shift / left shift pair ? */
1957 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
1958 right = exact_log2 (lsb);
1959 mask2 = ~(mask + lsb - 1);
1960 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
1961 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1963 best_cost = shift_insns[right] + shift_insns[right + left];
1964 /* mask has no trailing zeroes <==> ! right */
1965 else if (! right && mask2 == ~(lsb2 - 1))
1967 int late_right = exact_log2 (lsb2);
1968 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
1970 /* Try to use zero extend */
1971 if (mask2 == ~(lsb2 - 1))
1975 for (width = 8; width <= 16; width += 8)
1977 /* Can we zero-extend right away? */
1978 if (lsb2 == (unsigned HOST_WIDE_INT)1 << width)
1981 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
1982 if (cost < best_cost)
1993 /* ??? Could try to put zero extend into initial right shift,
1994 or even shift a bit left before the right shift. */
1995 /* Determine value of first part of left shift, to get to the
1996 zero extend cut-off point. */
1997 first = width - exact_log2 (lsb2) + right;
1998 if (first >= 0 && right + left - first >= 0)
2000 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
2001 + ext_shift_insns[right + left - first];
2002 if (cost < best_cost)
2014 /* Try to use r0 AND pattern */
2015 for (i = 0; i <= 2; i++)
2019 if (! CONST_OK_FOR_L (mask >> i))
2021 cost = (i != 0) + 2 + ext_shift_insns[left + i];
2022 if (cost < best_cost)
2027 best_len = cost - 1;
2030 /* Try to use a scratch register to hold the AND operand. */
2031 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT)3 << 30)) == 0;
2032 for (i = 0; i <= 2; i++)
2036 cost = (i != 0) + (CONST_OK_FOR_I (mask >> i) ? 2 : 3)
2037 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
2038 if (cost < best_cost)
2043 best_len = cost - 1 - ! CONST_OK_FOR_I (mask >> i);
2049 attrp[0] = best_right;
2050 attrp[1] = best_len;
2055 /* This is used in length attributes of the unnamed instructions
2056 corresponding to shl_and_kind return values of 1 and 2. */
2058 shl_and_length (insn)
2061 rtx set_src, left_rtx, mask_rtx;
2064 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2065 left_rtx = XEXP (XEXP (set_src, 0), 1);
2066 mask_rtx = XEXP (set_src, 1);
2067 shl_and_kind (left_rtx, mask_rtx, attributes);
2068 return attributes[1];
2071 /* This is used in length attribute of the and_shl_scratch instruction. */
2074 shl_and_scr_length (insn)
2077 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2078 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
2079 rtx op = XEXP (set_src, 0);
2080 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
2081 op = XEXP (XEXP (op, 0), 0);
2082 return len + shift_insns[INTVAL (XEXP (op, 1))];
2085 /* Generating rtl? */
2086 extern int rtx_equal_function_value_matters;
2088 /* Generate rtl for instructions for which shl_and_kind advised a particular
2089 method of generating them, i.e. returned zero. */
2092 gen_shl_and (dest, left_rtx, mask_rtx, source)
2093 rtx dest, left_rtx, mask_rtx, source;
2096 unsigned HOST_WIDE_INT mask;
2097 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
2098 int right, total_shift;
2099 void (*shift_gen_fun) PARAMS ((int, rtx*)) = gen_shifty_hi_op;
2101 right = attributes[0];
2102 total_shift = INTVAL (left_rtx) + right;
2103 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
2110 int first = attributes[2];
2115 emit_insn ((mask << right) <= 0xff
2116 ? gen_zero_extendqisi2(dest,
2117 gen_lowpart (QImode, source))
2118 : gen_zero_extendhisi2(dest,
2119 gen_lowpart (HImode, source)));
2123 emit_insn (gen_movsi (dest, source));
2127 operands[2] = GEN_INT (right);
2128 gen_shifty_hi_op (LSHIFTRT, operands);
2132 operands[2] = GEN_INT (first);
2133 gen_shifty_hi_op (ASHIFT, operands);
2134 total_shift -= first;
2138 emit_insn (mask <= 0xff
2139 ? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest))
2140 : gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest)));
2141 if (total_shift > 0)
2143 operands[2] = GEN_INT (total_shift);
2144 gen_shifty_hi_op (ASHIFT, operands);
2149 shift_gen_fun = gen_shifty_op;
2151 /* If the topmost bit that matters is set, set the topmost bits
2152 that don't matter. This way, we might be able to get a shorter
2154 if (mask & ((HOST_WIDE_INT)1 << (31 - total_shift)))
2155 mask |= (HOST_WIDE_INT)~0 << (31 - total_shift);
2157 /* Don't expand fine-grained when combining, because that will
2158 make the pattern fail. */
2159 if (rtx_equal_function_value_matters
2160 || reload_in_progress || reload_completed)
2164 /* Cases 3 and 4 should be handled by this split
2165 only while combining */
2170 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
2173 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
2178 operands[2] = GEN_INT (total_shift);
2179 shift_gen_fun (ASHIFT, operands);
2186 if (kind != 4 && total_shift < 16)
2188 neg = -ext_shift_amounts[total_shift][1];
2190 neg -= ext_shift_amounts[total_shift][2];
2194 emit_insn (gen_and_shl_scratch (dest, source,
2197 GEN_INT (total_shift + neg),
2199 emit_insn (gen_movsi (dest, dest));
2206 /* Try to find a good way to implement the combiner pattern
2207 [(set (match_operand:SI 0 "register_operand" "=r")
2208 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2209 (match_operand:SI 2 "const_int_operand" "n")
2210 (match_operand:SI 3 "const_int_operand" "n")
2212 (clobber (reg:SI T_REG))]
2213 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
2214 return 0 for simple left / right shift combination.
2215 return 1 for left shift / 8 bit sign extend / left shift.
2216 return 2 for left shift / 16 bit sign extend / left shift.
2217 return 3 for left shift / 8 bit sign extend / shift / sign extend.
2218 return 4 for left shift / 16 bit sign extend / shift / sign extend.
2219 return 5 for left shift / 16 bit sign extend / right shift
2220 return 6 for < 8 bit sign extend / left shift.
2221 return 7 for < 8 bit sign extend / left shift / single right shift.
2222 If COSTP is nonzero, assign the calculated cost to *COSTP. */
2225 shl_sext_kind (left_rtx, size_rtx, costp)
2226 rtx left_rtx, size_rtx;
2229 int left, size, insize, ext;
2230 int cost = 0, best_cost;
2233 left = INTVAL (left_rtx);
2234 size = INTVAL (size_rtx);
2235 insize = size - left;
2238 /* Default to left / right shift. */
2240 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
2243 /* 16 bit shift / sign extend / 16 bit shift */
2244 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
2245 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
2246 below, by alternative 3 or something even better. */
2247 if (cost < best_cost)
2253 /* Try a plain sign extend between two shifts. */
2254 for (ext = 16; ext >= insize; ext -= 8)
2258 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
2259 if (cost < best_cost)
2261 kind = ext / (unsigned) 8;
2265 /* Check if we can do a sloppy shift with a final signed shift
2266 restoring the sign. */
2267 if (EXT_SHIFT_SIGNED (size - ext))
2268 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
2269 /* If not, maybe it's still cheaper to do the second shift sloppy,
2270 and do a final sign extend? */
2271 else if (size <= 16)
2272 cost = ext_shift_insns[ext - insize] + 1
2273 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
2276 if (cost < best_cost)
2278 kind = ext / (unsigned) 8 + 2;
2282 /* Check if we can sign extend in r0 */
2285 cost = 3 + shift_insns[left];
2286 if (cost < best_cost)
2291 /* Try the same with a final signed shift. */
2294 cost = 3 + ext_shift_insns[left + 1] + 1;
2295 if (cost < best_cost)
2304 /* Try to use a dynamic shift. */
2305 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
2306 if (cost < best_cost)
2317 /* Function to be used in the length attribute of the instructions
2318 implementing this pattern. */
2321 shl_sext_length (insn)
2324 rtx set_src, left_rtx, size_rtx;
2327 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2328 left_rtx = XEXP (XEXP (set_src, 0), 1);
2329 size_rtx = XEXP (set_src, 1);
2330 shl_sext_kind (left_rtx, size_rtx, &cost);
2334 /* Generate rtl for this pattern */
2337 gen_shl_sext (dest, left_rtx, size_rtx, source)
2338 rtx dest, left_rtx, size_rtx, source;
2341 int left, size, insize, cost;
2344 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
2345 left = INTVAL (left_rtx);
2346 size = INTVAL (size_rtx);
2347 insize = size - left;
2355 int ext = kind & 1 ? 8 : 16;
2356 int shift2 = size - ext;
2358 /* Don't expand fine-grained when combining, because that will
2359 make the pattern fail. */
2360 if (! rtx_equal_function_value_matters
2361 && ! reload_in_progress && ! reload_completed)
2363 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2364 emit_insn (gen_movsi (dest, source));
2368 emit_insn (gen_movsi (dest, source));
2372 operands[2] = GEN_INT (ext - insize);
2373 gen_shifty_hi_op (ASHIFT, operands);
2376 ? gen_extendqisi2(dest, gen_lowpart (QImode, dest))
2377 : gen_extendhisi2(dest, gen_lowpart (HImode, dest)));
2382 operands[2] = GEN_INT (shift2);
2383 gen_shifty_op (ASHIFT, operands);
2390 if (EXT_SHIFT_SIGNED (shift2))
2392 operands[2] = GEN_INT (shift2 + 1);
2393 gen_shifty_op (ASHIFT, operands);
2394 operands[2] = GEN_INT (1);
2395 gen_shifty_op (ASHIFTRT, operands);
2398 operands[2] = GEN_INT (shift2);
2399 gen_shifty_hi_op (ASHIFT, operands);
2403 operands[2] = GEN_INT (-shift2);
2404 gen_shifty_hi_op (LSHIFTRT, operands);
2406 emit_insn (size <= 8
2407 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
2408 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2415 if (! rtx_equal_function_value_matters
2416 && ! reload_in_progress && ! reload_completed)
2417 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2421 operands[2] = GEN_INT (16 - insize);
2422 gen_shifty_hi_op (ASHIFT, operands);
2423 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2425 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2427 gen_ashift (ASHIFTRT, 1, dest);
2432 /* Don't expand fine-grained when combining, because that will
2433 make the pattern fail. */
2434 if (! rtx_equal_function_value_matters
2435 && ! reload_in_progress && ! reload_completed)
2437 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2438 emit_insn (gen_movsi (dest, source));
2441 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
2442 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
2443 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
2445 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
2446 gen_shifty_op (ASHIFT, operands);
2448 emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
2456 /* Prefix a symbol_ref name with "datalabel". */
2459 gen_datalabel_ref (sym)
2462 if (GET_CODE (sym) == LABEL_REF)
2463 return gen_rtx_CONST (GET_MODE (sym),
2464 gen_rtx_UNSPEC (GET_MODE (sym),
2468 if (GET_CODE (sym) != SYMBOL_REF)
2471 XSTR (sym, 0) = concat (SH_DATALABEL_ENCODING, XSTR (sym, 0), NULL);
2477 /* The SH cannot load a large constant into a register, constants have to
2478 come from a pc relative load. The reference of a pc relative load
2479 instruction must be less than 1k infront of the instruction. This
2480 means that we often have to dump a constant inside a function, and
2481 generate code to branch around it.
2483 It is important to minimize this, since the branches will slow things
2484 down and make things bigger.
2486 Worst case code looks like:
2504 We fix this by performing a scan before scheduling, which notices which
2505 instructions need to have their operands fetched from the constant table
2506 and builds the table.
2510 scan, find an instruction which needs a pcrel move. Look forward, find the
2511 last barrier which is within MAX_COUNT bytes of the requirement.
2512 If there isn't one, make one. Process all the instructions between
2513 the find and the barrier.
2515 In the above example, we can tell that L3 is within 1k of L1, so
2516 the first move can be shrunk from the 3 insn+constant sequence into
2517 just 1 insn, and the constant moved to L3 to make:
2528 Then the second move becomes the target for the shortening process. */
2532 rtx value; /* Value in table. */
2533 rtx label; /* Label of value. */
2534 rtx wend; /* End of window. */
2535 enum machine_mode mode; /* Mode of value. */
2537 /* True if this constant is accessed as part of a post-increment
2538 sequence. Note that HImode constants are never accessed in this way. */
2539 bool part_of_sequence_p;
2542 /* The maximum number of constants that can fit into one pool, since
2543 the pc relative range is 0...1020 bytes and constants are at least 4
2546 #define MAX_POOL_SIZE (1020/4)
2547 static pool_node pool_vector[MAX_POOL_SIZE];
2548 static int pool_size;
2549 static rtx pool_window_label;
2550 static int pool_window_last;
2552 /* ??? If we need a constant in HImode which is the truncated value of a
2553 constant we need in SImode, we could combine the two entries thus saving
2554 two bytes. Is this common enough to be worth the effort of implementing
2557 /* ??? This stuff should be done at the same time that we shorten branches.
2558 As it is now, we must assume that all branches are the maximum size, and
2559 this causes us to almost always output constant pools sooner than
2562 /* Add a constant to the pool and return its label. */
2565 add_constant (x, mode, last_value)
2567 enum machine_mode mode;
2571 rtx lab, new, ref, newref;
2573 /* First see if we've already got it. */
2574 for (i = 0; i < pool_size; i++)
2576 if (x->code == pool_vector[i].value->code
2577 && mode == pool_vector[i].mode)
2579 if (x->code == CODE_LABEL)
2581 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
2584 if (rtx_equal_p (x, pool_vector[i].value))
2589 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
2591 new = gen_label_rtx ();
2592 LABEL_REFS (new) = pool_vector[i].label;
2593 pool_vector[i].label = lab = new;
2595 if (lab && pool_window_label)
2597 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2598 ref = pool_vector[pool_window_last].wend;
2599 LABEL_NEXTREF (newref) = ref;
2600 pool_vector[pool_window_last].wend = newref;
2603 pool_window_label = new;
2604 pool_window_last = i;
2610 /* Need a new one. */
2611 pool_vector[pool_size].value = x;
2612 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
2615 pool_vector[pool_size - 1].part_of_sequence_p = true;
2618 lab = gen_label_rtx ();
2619 pool_vector[pool_size].mode = mode;
2620 pool_vector[pool_size].label = lab;
2621 pool_vector[pool_size].wend = NULL_RTX;
2622 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
2623 if (lab && pool_window_label)
2625 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2626 ref = pool_vector[pool_window_last].wend;
2627 LABEL_NEXTREF (newref) = ref;
2628 pool_vector[pool_window_last].wend = newref;
2631 pool_window_label = lab;
2632 pool_window_last = pool_size;
2637 /* Output the literal table. */
2648 /* Do two passes, first time dump out the HI sized constants. */
2650 for (i = 0; i < pool_size; i++)
2652 pool_node *p = &pool_vector[i];
2654 if (p->mode == HImode)
2658 scan = emit_insn_after (gen_align_2 (), scan);
2661 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2662 scan = emit_label_after (lab, scan);
2663 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
2665 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2667 lab = XEXP (ref, 0);
2668 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2671 else if (p->mode == DFmode)
2677 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
2679 rtx align_insn = NULL_RTX;
2681 scan = emit_label_after (gen_label_rtx (), scan);
2682 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2685 for (i = 0; i < pool_size; i++)
2687 pool_node *p = &pool_vector[i];
2695 if (align_insn && !p->part_of_sequence_p)
2697 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2698 emit_label_before (lab, align_insn);
2699 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
2701 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2703 lab = XEXP (ref, 0);
2704 emit_insn_before (gen_consttable_window_end (lab),
2707 delete_insn (align_insn);
2708 align_insn = NULL_RTX;
2713 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2714 scan = emit_label_after (lab, scan);
2715 scan = emit_insn_after (gen_consttable_4 (p->value,
2717 need_align = ! need_align;
2723 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2728 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2729 scan = emit_label_after (lab, scan);
2730 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2738 if (p->mode != HImode)
2740 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2742 lab = XEXP (ref, 0);
2743 scan = emit_insn_after (gen_consttable_window_end (lab),
2752 for (i = 0; i < pool_size; i++)
2754 pool_node *p = &pool_vector[i];
2765 scan = emit_label_after (gen_label_rtx (), scan);
2766 scan = emit_insn_after (gen_align_4 (), scan);
2768 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2769 scan = emit_label_after (lab, scan);
2770 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
2778 scan = emit_label_after (gen_label_rtx (), scan);
2779 scan = emit_insn_after (gen_align_4 (), scan);
2781 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2782 scan = emit_label_after (lab, scan);
2783 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2791 if (p->mode != HImode)
2793 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2795 lab = XEXP (ref, 0);
2796 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2801 scan = emit_insn_after (gen_consttable_end (), scan);
2802 scan = emit_barrier_after (scan);
2804 pool_window_label = NULL_RTX;
2805 pool_window_last = 0;
2808 /* Return nonzero if constant would be an ok source for a
2809 mov.w instead of a mov.l. */
2815 return (GET_CODE (src) == CONST_INT
2816 && INTVAL (src) >= -32768
2817 && INTVAL (src) <= 32767);
2820 /* Nonzero if the insn is a move instruction which needs to be fixed. */
2822 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2823 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
2824 need to fix it if the input value is CONST_OK_FOR_I. */
2830 if (GET_CODE (insn) == INSN)
2832 rtx pat = PATTERN (insn);
2833 if (GET_CODE (pat) == PARALLEL)
2834 pat = XVECEXP (pat, 0, 0);
2835 if (GET_CODE (pat) == SET
2836 /* We can load any 8 bit value if we don't care what the high
2837 order bits end up as. */
2838 && GET_MODE (SET_DEST (pat)) != QImode
2839 && (CONSTANT_P (SET_SRC (pat))
2840 /* Match mova_const. */
2841 || (GET_CODE (SET_SRC (pat)) == UNSPEC
2842 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
2843 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
2845 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
2846 && (fp_zero_operand (SET_SRC (pat))
2847 || fp_one_operand (SET_SRC (pat)))
2848 /* ??? If this is a -m4 or -m4-single compilation, in general
2849 we don't know the current setting of fpscr, so disable fldi.
2850 There is an exception if this was a register-register move
2851 before reload - and hence it was ascertained that we have
2852 single precision setting - and in a post-reload optimization
2853 we changed this to do a constant load. In that case
2854 we don't have an r0 clobber, hence we must use fldi. */
2855 && (! TARGET_SH4 || TARGET_FMOVD
2856 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
2858 && GET_CODE (SET_DEST (pat)) == REG
2859 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
2860 && (GET_CODE (SET_SRC (pat)) != CONST_INT
2861 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat)))))
2872 return (GET_CODE (insn) == INSN
2873 && GET_CODE (PATTERN (insn)) == SET
2874 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
2875 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
2876 /* Don't match mova_const. */
2877 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn)), 0, 0)) == LABEL_REF);
2880 /* Find the last barrier from insn FROM which is close enough to hold the
2881 constant pool. If we can't find one, then create one near the end of
2885 find_barrier (num_mova, mova, from)
2896 int leading_mova = num_mova;
2897 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
2901 /* For HImode: range is 510, add 4 because pc counts from address of
2902 second instruction after this one, subtract 2 for the jump instruction
2903 that we may need to emit before the table, subtract 2 for the instruction
2904 that fills the jump delay slot (in very rare cases, reorg will take an
2905 instruction from after the constant pool or will leave the delay slot
2906 empty). This gives 510.
2907 For SImode: range is 1020, add 4 because pc counts from address of
2908 second instruction after this one, subtract 2 in case pc is 2 byte
2909 aligned, subtract 2 for the jump instruction that we may need to emit
2910 before the table, subtract 2 for the instruction that fills the jump
2911 delay slot. This gives 1018. */
2913 /* The branch will always be shortened now that the reference address for
2914 forward branches is the successor address, thus we need no longer make
2915 adjustments to the [sh]i_limit for -O0. */
2920 while (from && count_si < si_limit && count_hi < hi_limit)
2922 int inc = get_attr_length (from);
2925 if (GET_CODE (from) == CODE_LABEL)
2928 new_align = 1 << label_to_alignment (from);
2929 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
2930 new_align = 1 << barrier_align (from);
2936 if (GET_CODE (from) == BARRIER)
2939 found_barrier = from;
2941 /* If we are at the end of the function, or in front of an alignment
2942 instruction, we need not insert an extra alignment. We prefer
2943 this kind of barrier. */
2944 if (barrier_align (from) > 2)
2945 good_barrier = from;
2948 if (broken_move (from))
2951 enum machine_mode mode;
2953 pat = PATTERN (from);
2954 if (GET_CODE (pat) == PARALLEL)
2955 pat = XVECEXP (pat, 0, 0);
2956 src = SET_SRC (pat);
2957 dst = SET_DEST (pat);
2958 mode = GET_MODE (dst);
2960 /* We must explicitly check the mode, because sometimes the
2961 front end will generate code to load unsigned constants into
2962 HImode targets without properly sign extending them. */
2964 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
2967 /* We put the short constants before the long constants, so
2968 we must count the length of short constants in the range
2969 for the long constants. */
2970 /* ??? This isn't optimal, but is easy to do. */
2975 /* We dump DF/DI constants before SF/SI ones, because
2976 the limit is the same, but the alignment requirements
2977 are higher. We may waste up to 4 additional bytes
2978 for alignment, and the DF/DI constant may have
2979 another SF/SI constant placed before it. */
2980 if (TARGET_SHCOMPACT
2982 && (mode == DFmode || mode == DImode))
2987 while (si_align > 2 && found_si + si_align - 2 > count_si)
2989 if (found_si > count_si)
2990 count_si = found_si;
2991 found_si += GET_MODE_SIZE (mode);
2993 si_limit -= GET_MODE_SIZE (mode);
2996 /* See the code in machine_dependent_reorg, which has a similar if
2997 statement that generates a new mova insn in many cases. */
2998 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
3008 barrier_before_mova = good_barrier ? good_barrier : found_barrier;
3010 if (found_si > count_si)
3011 count_si = found_si;
3013 else if (GET_CODE (from) == JUMP_INSN
3014 && (GET_CODE (PATTERN (from)) == ADDR_VEC
3015 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
3019 if (barrier_align (next_real_insn (from)) == CACHE_LOG)
3021 /* We have just passed the barrier in front of the
3022 ADDR_DIFF_VEC, which is stored in found_barrier. Since
3023 the ADDR_DIFF_VEC is accessed as data, just like our pool
3024 constants, this is a good opportunity to accommodate what
3025 we have gathered so far.
3026 If we waited any longer, we could end up at a barrier in
3027 front of code, which gives worse cache usage for separated
3028 instruction / data caches. */
3029 good_barrier = found_barrier;
3034 rtx body = PATTERN (from);
3035 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
3038 /* For the SH1, we generate alignments even after jumps-around-jumps. */
3039 else if (GET_CODE (from) == JUMP_INSN
3041 && ! TARGET_SMALLCODE)
3047 if (new_align > si_align)
3049 si_limit -= (count_si - 1) & (new_align - si_align);
3050 si_align = new_align;
3052 count_si = (count_si + new_align - 1) & -new_align;
3057 if (new_align > hi_align)
3059 hi_limit -= (count_hi - 1) & (new_align - hi_align);
3060 hi_align = new_align;
3062 count_hi = (count_hi + new_align - 1) & -new_align;
3064 from = NEXT_INSN (from);
3071 /* Try as we might, the leading mova is out of range. Change
3072 it into a load (which will become a pcload) and retry. */
3073 SET_SRC (PATTERN (mova)) = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3074 INSN_CODE (mova) = -1;
3075 return find_barrier (0, 0, mova);
3079 /* Insert the constant pool table before the mova instruction,
3080 to prevent the mova label reference from going out of range. */
3082 good_barrier = found_barrier = barrier_before_mova;
3088 if (good_barrier && next_real_insn (found_barrier))
3089 found_barrier = good_barrier;
3093 /* We didn't find a barrier in time to dump our stuff,
3094 so we'll make one. */
3095 rtx label = gen_label_rtx ();
3097 /* If we exceeded the range, then we must back up over the last
3098 instruction we looked at. Otherwise, we just need to undo the
3099 NEXT_INSN at the end of the loop. */
3100 if (count_hi > hi_limit || count_si > si_limit)
3101 from = PREV_INSN (PREV_INSN (from));
3103 from = PREV_INSN (from);
3105 /* Walk back to be just before any jump or label.
3106 Putting it before a label reduces the number of times the branch
3107 around the constant pool table will be hit. Putting it before
3108 a jump makes it more likely that the bra delay slot will be
3110 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
3111 || GET_CODE (from) == CODE_LABEL)
3112 from = PREV_INSN (from);
3114 from = emit_jump_insn_after (gen_jump (label), from);
3115 JUMP_LABEL (from) = label;
3116 LABEL_NUSES (label) = 1;
3117 found_barrier = emit_barrier_after (from);
3118 emit_label_after (label, found_barrier);
3121 return found_barrier;
3124 /* If the instruction INSN is implemented by a special function, and we can
3125 positively find the register that is used to call the sfunc, and this
3126 register is not used anywhere else in this instruction - except as the
3127 destination of a set, return this register; else, return 0. */
3129 sfunc_uses_reg (insn)
3133 rtx pattern, part, reg_part, reg;
3135 if (GET_CODE (insn) != INSN)
3137 pattern = PATTERN (insn);
3138 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
3141 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
3143 part = XVECEXP (pattern, 0, i);
3144 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
3149 reg = XEXP (reg_part, 0);
3150 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
3152 part = XVECEXP (pattern, 0, i);
3153 if (part == reg_part || GET_CODE (part) == CLOBBER)
3155 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
3156 && GET_CODE (SET_DEST (part)) == REG)
3157 ? SET_SRC (part) : part)))
3163 /* See if the only way in which INSN uses REG is by calling it, or by
3164 setting it while calling it. Set *SET to a SET rtx if the register
3168 noncall_uses_reg (reg, insn, set)
3177 reg2 = sfunc_uses_reg (insn);
3178 if (reg2 && REGNO (reg2) == REGNO (reg))
3180 pattern = single_set (insn);
3182 && GET_CODE (SET_DEST (pattern)) == REG
3183 && REGNO (reg) == REGNO (SET_DEST (pattern)))
3187 if (GET_CODE (insn) != CALL_INSN)
3189 /* We don't use rtx_equal_p because we don't care if the mode is
3191 pattern = single_set (insn);
3193 && GET_CODE (SET_DEST (pattern)) == REG
3194 && REGNO (reg) == REGNO (SET_DEST (pattern)))
3200 par = PATTERN (insn);
3201 if (GET_CODE (par) == PARALLEL)
3202 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
3204 part = XVECEXP (par, 0, i);
3205 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
3208 return reg_mentioned_p (reg, SET_SRC (pattern));
3214 pattern = PATTERN (insn);
3216 if (GET_CODE (pattern) == PARALLEL)
3220 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
3221 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
3223 pattern = XVECEXP (pattern, 0, 0);
3226 if (GET_CODE (pattern) == SET)
3228 if (reg_mentioned_p (reg, SET_DEST (pattern)))
3230 /* We don't use rtx_equal_p, because we don't care if the
3231 mode is different. */
3232 if (GET_CODE (SET_DEST (pattern)) != REG
3233 || REGNO (reg) != REGNO (SET_DEST (pattern)))
3239 pattern = SET_SRC (pattern);
3242 if (GET_CODE (pattern) != CALL
3243 || GET_CODE (XEXP (pattern, 0)) != MEM
3244 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
3250 /* Given a X, a pattern of an insn or a part of it, return a mask of used
3251 general registers. Bits 0..15 mean that the respective registers
3252 are used as inputs in the instruction. Bits 16..31 mean that the
3253 registers 0..15, respectively, are used as outputs, or are clobbered.
3254 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
3256 regs_used (x, is_dest)
3265 code = GET_CODE (x);
3270 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3271 << (REGNO (x) + is_dest));
3275 rtx y = SUBREG_REG (x);
3277 if (GET_CODE (y) != REG)
3280 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3282 subreg_regno_offset (REGNO (y),
3285 GET_MODE (x)) + is_dest));
3289 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
3291 /* If there was a return value, it must have been indicated with USE. */
3306 fmt = GET_RTX_FORMAT (code);
3308 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3313 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3314 used |= regs_used (XVECEXP (x, i, j), is_dest);
3316 else if (fmt[i] == 'e')
3317 used |= regs_used (XEXP (x, i), is_dest);
3322 /* Create an instruction that prevents redirection of a conditional branch
3323 to the destination of the JUMP with address ADDR.
3324 If the branch needs to be implemented as an indirect jump, try to find
3325 a scratch register for it.
3326 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
3327 If any preceding insn that doesn't fit into a delay slot is good enough,
3328 pass 1. Pass 2 if a definite blocking insn is needed.
3329 -1 is used internally to avoid deep recursion.
3330 If a blocking instruction is made or recognized, return it. */
3333 gen_block_redirect (jump, addr, need_block)
3335 int addr, need_block;
3338 rtx prev = prev_nonnote_insn (jump);
3341 /* First, check if we already have an instruction that satisfies our need. */
3342 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
3344 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
3346 if (GET_CODE (PATTERN (prev)) == USE
3347 || GET_CODE (PATTERN (prev)) == CLOBBER
3348 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3350 else if ((need_block &= ~1) < 0)
3352 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
3355 /* We can't use JUMP_LABEL here because it might be undefined
3356 when not optimizing. */
3357 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
3358 /* If the branch is out of range, try to find a scratch register for it. */
3360 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3364 /* Don't look for the stack pointer as a scratch register,
3365 it would cause trouble if an interrupt occurred. */
3366 unsigned try = 0x7fff, used;
3367 int jump_left = flag_expensive_optimizations + 1;
3369 /* It is likely that the most recent eligible instruction is wanted for
3370 the delay slot. Therefore, find out which registers it uses, and
3371 try to avoid using them. */
3373 for (scan = jump; (scan = PREV_INSN (scan)); )
3377 if (INSN_DELETED_P (scan))
3379 code = GET_CODE (scan);
3380 if (code == CODE_LABEL || code == JUMP_INSN)
3383 && GET_CODE (PATTERN (scan)) != USE
3384 && GET_CODE (PATTERN (scan)) != CLOBBER
3385 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
3387 try &= ~regs_used (PATTERN (scan), 0);
3391 for (used = dead = 0, scan = JUMP_LABEL (jump);
3392 (scan = NEXT_INSN (scan)); )
3396 if (INSN_DELETED_P (scan))
3398 code = GET_CODE (scan);
3399 if (GET_RTX_CLASS (code) == 'i')
3401 used |= regs_used (PATTERN (scan), 0);
3402 if (code == CALL_INSN)
3403 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
3404 dead |= (used >> 16) & ~used;
3410 if (code == JUMP_INSN)
3412 if (jump_left-- && simplejump_p (scan))
3413 scan = JUMP_LABEL (scan);
3419 /* Mask out the stack pointer again, in case it was
3420 the only 'free' register we have found. */
3423 /* If the immediate destination is still in range, check for possible
3424 threading with a jump beyond the delay slot insn.
3425 Don't check if we are called recursively; the jump has been or will be
3426 checked in a different invocation then. */
3428 else if (optimize && need_block >= 0)
3430 rtx next = next_active_insn (next_active_insn (dest));
3431 if (next && GET_CODE (next) == JUMP_INSN
3432 && GET_CODE (PATTERN (next)) == SET
3433 && recog_memoized (next) == CODE_FOR_jump)
3435 dest = JUMP_LABEL (next);
3437 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3439 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
3445 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
3447 /* It would be nice if we could convert the jump into an indirect
3448 jump / far branch right now, and thus exposing all constituent
3449 instructions to further optimization. However, reorg uses
3450 simplejump_p to determine if there is an unconditional jump where
3451 it should try to schedule instructions from the target of the
3452 branch; simplejump_p fails for indirect jumps even if they have
3454 rtx insn = emit_insn_before (gen_indirect_jump_scratch
3455 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
3457 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
3460 else if (need_block)
3461 /* We can't use JUMP_LABEL here because it might be undefined
3462 when not optimizing. */
3463 return emit_insn_before (gen_block_branch_redirect
3464 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
3469 #define CONDJUMP_MIN -252
3470 #define CONDJUMP_MAX 262
3473 /* A label (to be placed) in front of the jump
3474 that jumps to our ultimate destination. */
3476 /* Where we are going to insert it if we cannot move the jump any farther,
3477 or the jump itself if we have picked up an existing jump. */
3479 /* The ultimate destination. */
3481 struct far_branch *prev;
3482 /* If the branch has already been created, its address;
3483 else the address of its first prospective user. */
3487 static void gen_far_branch PARAMS ((struct far_branch *));
3488 enum mdep_reorg_phase_e mdep_reorg_phase;
3491 struct far_branch *bp;
3493 rtx insn = bp->insert_place;
3495 rtx label = gen_label_rtx ();
3497 emit_label_after (label, insn);
3500 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
3501 LABEL_NUSES (bp->far_label)++;
3504 jump = emit_jump_insn_after (gen_return (), insn);
3505 /* Emit a barrier so that reorg knows that any following instructions
3506 are not reachable via a fall-through path.
3507 But don't do this when not optimizing, since we wouldn't supress the
3508 alignment for the barrier then, and could end up with out-of-range
3509 pc-relative loads. */
3511 emit_barrier_after (jump);
3512 emit_label_after (bp->near_label, insn);
3513 JUMP_LABEL (jump) = bp->far_label;
3514 if (! invert_jump (insn, label, 1))
3517 (gen_stuff_delay_slot
3518 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
3519 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
3521 /* Prevent reorg from undoing our splits. */
3522 gen_block_redirect (jump, bp->address += 2, 2);
3525 /* Fix up ADDR_DIFF_VECs. */
3527 fixup_addr_diff_vecs (first)
3532 for (insn = first; insn; insn = NEXT_INSN (insn))
3534 rtx vec_lab, pat, prev, prevpat, x, braf_label;
3536 if (GET_CODE (insn) != JUMP_INSN
3537 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
3539 pat = PATTERN (insn);
3540 vec_lab = XEXP (XEXP (pat, 0), 0);
3542 /* Search the matching casesi_jump_2. */
3543 for (prev = vec_lab; ; prev = PREV_INSN (prev))
3545 if (GET_CODE (prev) != JUMP_INSN)
3547 prevpat = PATTERN (prev);
3548 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
3550 x = XVECEXP (prevpat, 0, 1);
3551 if (GET_CODE (x) != USE)
3554 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
3558 /* Emit the reference label of the braf where it belongs, right after
3559 the casesi_jump_2 (i.e. braf). */
3560 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
3561 emit_label_after (braf_label, prev);
3563 /* Fix up the ADDR_DIF_VEC to be relative
3564 to the reference address of the braf. */
3565 XEXP (XEXP (pat, 0), 0) = braf_label;
3569 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3570 a barrier. Return the base 2 logarithm of the desired alignment. */
3572 barrier_align (barrier_or_label)
3573 rtx barrier_or_label;
3575 rtx next = next_real_insn (barrier_or_label), pat, prev;
3576 int slot, credit, jump_to_next = 0;
3581 pat = PATTERN (next);
3583 if (GET_CODE (pat) == ADDR_DIFF_VEC)
3586 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
3587 /* This is a barrier in front of a constant table. */
3590 prev = prev_real_insn (barrier_or_label);
3591 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
3593 pat = PATTERN (prev);
3594 /* If this is a very small table, we want to keep the alignment after
3595 the table to the minimum for proper code alignment. */
3596 return ((TARGET_SMALLCODE
3597 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
3598 <= (unsigned)1 << (CACHE_LOG - 2)))
3599 ? 1 << TARGET_SHMEDIA : CACHE_LOG);
3602 if (TARGET_SMALLCODE)
3605 if (! TARGET_SH2 || ! optimize)
3608 /* When fixing up pcloads, a constant table might be inserted just before
3609 the basic block that ends with the barrier. Thus, we can't trust the
3610 instruction lengths before that. */
3611 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
3613 /* Check if there is an immediately preceding branch to the insn beyond
3614 the barrier. We must weight the cost of discarding useful information
3615 from the current cache line when executing this branch and there is
3616 an alignment, against that of fetching unneeded insn in front of the
3617 branch target when there is no alignment. */
3619 /* There are two delay_slot cases to consider. One is the simple case
3620 where the preceding branch is to the insn beyond the barrier (simple
3621 delay slot filling), and the other is where the preceding branch has
3622 a delay slot that is a duplicate of the insn after the barrier
3623 (fill_eager_delay_slots) and the branch is to the insn after the insn
3624 after the barrier. */
3626 /* PREV is presumed to be the JUMP_INSN for the barrier under
3627 investigation. Skip to the insn before it. */
3628 prev = prev_real_insn (prev);
3630 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
3631 credit >= 0 && prev && GET_CODE (prev) == INSN;
3632 prev = prev_real_insn (prev))
3635 if (GET_CODE (PATTERN (prev)) == USE
3636 || GET_CODE (PATTERN (prev)) == CLOBBER)
3638 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
3640 prev = XVECEXP (PATTERN (prev), 0, 1);
3641 if (INSN_UID (prev) == INSN_UID (next))
3643 /* Delay slot was filled with insn at jump target. */
3650 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3652 credit -= get_attr_length (prev);
3655 && GET_CODE (prev) == JUMP_INSN
3656 && JUMP_LABEL (prev))
3660 || next_real_insn (JUMP_LABEL (prev)) == next
3661 /* If relax_delay_slots() decides NEXT was redundant
3662 with some previous instruction, it will have
3663 redirected PREV's jump to the following insn. */
3664 || JUMP_LABEL (prev) == next_nonnote_insn (next)
3665 /* There is no upper bound on redundant instructions
3666 that might have been skipped, but we must not put an
3667 alignment where none had been before. */
3668 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
3670 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
3671 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch))))
3673 rtx pat = PATTERN (prev);
3674 if (GET_CODE (pat) == PARALLEL)
3675 pat = XVECEXP (pat, 0, 0);
3676 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
3685 /* If we are inside a phony loop, almost any kind of label can turn up as the
3686 first one in the loop. Aligning a braf label causes incorrect switch
3687 destination addresses; we can detect braf labels because they are
3688 followed by a BARRIER.
3689 Applying loop alignment to small constant or switch tables is a waste
3690 of space, so we suppress this too. */
3692 sh_loop_align (label)
3698 next = next_nonnote_insn (next);
3699 while (next && GET_CODE (next) == CODE_LABEL);
3703 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
3704 || recog_memoized (next) == CODE_FOR_consttable_2)
3713 /* Exported to toplev.c.
3715 Do a final pass over the function, just before delayed branch
3719 machine_dependent_reorg (first)
3722 rtx insn, mova = NULL_RTX;
3724 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
3725 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
3727 /* We must split call insns before introducing `mova's. If we're
3728 optimizing, they'll have already been split. Otherwise, make
3729 sure we don't split them too late. */
3731 split_all_insns_noflow ();
3736 /* If relaxing, generate pseudo-ops to associate function calls with
3737 the symbols they call. It does no harm to not generate these
3738 pseudo-ops. However, when we can generate them, it enables to
3739 linker to potentially relax the jsr to a bsr, and eliminate the
3740 register load and, possibly, the constant pool entry. */
3742 mdep_reorg_phase = SH_INSERT_USES_LABELS;
3745 /* Remove all REG_LABEL notes. We want to use them for our own
3746 purposes. This works because none of the remaining passes
3747 need to look at them.
3749 ??? But it may break in the future. We should use a machine
3750 dependent REG_NOTE, or some other approach entirely. */
3751 for (insn = first; insn; insn = NEXT_INSN (insn))
3757 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
3758 remove_note (insn, note);
3762 for (insn = first; insn; insn = NEXT_INSN (insn))
3764 rtx pattern, reg, link, set, scan, dies, label;
3765 int rescan = 0, foundinsn = 0;
3767 if (GET_CODE (insn) == CALL_INSN)
3769 pattern = PATTERN (insn);
3771 if (GET_CODE (pattern) == PARALLEL)
3772 pattern = XVECEXP (pattern, 0, 0);
3773 if (GET_CODE (pattern) == SET)
3774 pattern = SET_SRC (pattern);
3776 if (GET_CODE (pattern) != CALL
3777 || GET_CODE (XEXP (pattern, 0)) != MEM)
3780 reg = XEXP (XEXP (pattern, 0), 0);
3784 reg = sfunc_uses_reg (insn);
3789 if (GET_CODE (reg) != REG)
3792 /* This is a function call via REG. If the only uses of REG
3793 between the time that it is set and the time that it dies
3794 are in function calls, then we can associate all the
3795 function calls with the setting of REG. */
3797 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
3799 if (REG_NOTE_KIND (link) != 0)
3801 set = single_set (XEXP (link, 0));
3802 if (set && rtx_equal_p (reg, SET_DEST (set)))
3804 link = XEXP (link, 0);
3811 /* ??? Sometimes global register allocation will have
3812 deleted the insn pointed to by LOG_LINKS. Try
3813 scanning backward to find where the register is set. */
3814 for (scan = PREV_INSN (insn);
3815 scan && GET_CODE (scan) != CODE_LABEL;
3816 scan = PREV_INSN (scan))
3818 if (! INSN_P (scan))
3821 if (! reg_mentioned_p (reg, scan))
3824 if (noncall_uses_reg (reg, scan, &set))
3838 /* The register is set at LINK. */
3840 /* We can only optimize the function call if the register is
3841 being set to a symbol. In theory, we could sometimes
3842 optimize calls to a constant location, but the assembler
3843 and linker do not support that at present. */
3844 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
3845 && GET_CODE (SET_SRC (set)) != LABEL_REF)
3848 /* Scan forward from LINK to the place where REG dies, and
3849 make sure that the only insns which use REG are
3850 themselves function calls. */
3852 /* ??? This doesn't work for call targets that were allocated
3853 by reload, since there may not be a REG_DEAD note for the
3857 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
3861 /* Don't try to trace forward past a CODE_LABEL if we haven't
3862 seen INSN yet. Ordinarily, we will only find the setting insn
3863 in LOG_LINKS if it is in the same basic block. However,
3864 cross-jumping can insert code labels in between the load and
3865 the call, and can result in situations where a single call
3866 insn may have two targets depending on where we came from. */
3868 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
3871 if (! INSN_P (scan))
3874 /* Don't try to trace forward past a JUMP. To optimize
3875 safely, we would have to check that all the
3876 instructions at the jump destination did not use REG. */
3878 if (GET_CODE (scan) == JUMP_INSN)
3881 if (! reg_mentioned_p (reg, scan))
3884 if (noncall_uses_reg (reg, scan, &scanset))
3891 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
3893 /* There is a function call to this register other
3894 than the one we are checking. If we optimize
3895 this call, we need to rescan again below. */
3899 /* ??? We shouldn't have to worry about SCANSET here.
3900 We should just be able to check for a REG_DEAD note
3901 on a function call. However, the REG_DEAD notes are
3902 apparently not dependable around libcalls; c-torture
3903 execute/920501-2 is a test case. If SCANSET is set,
3904 then this insn sets the register, so it must have
3905 died earlier. Unfortunately, this will only handle
3906 the cases in which the register is, in fact, set in a
3909 /* ??? We shouldn't have to use FOUNDINSN here.
3910 However, the LOG_LINKS fields are apparently not
3911 entirely reliable around libcalls;
3912 newlib/libm/math/e_pow.c is a test case. Sometimes
3913 an insn will appear in LOG_LINKS even though it is
3914 not the most recent insn which sets the register. */
3918 || find_reg_note (scan, REG_DEAD, reg)))
3927 /* Either there was a branch, or some insn used REG
3928 other than as a function call address. */
3932 /* Create a code label, and put it in a REG_LABEL note on
3933 the insn which sets the register, and on each call insn
3934 which uses the register. In final_prescan_insn we look
3935 for the REG_LABEL notes, and output the appropriate label
3938 label = gen_label_rtx ();
3939 REG_NOTES (link) = gen_rtx_INSN_LIST (REG_LABEL, label,
3941 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, label,
3950 scan = NEXT_INSN (scan);
3952 && ((GET_CODE (scan) == CALL_INSN
3953 && reg_mentioned_p (reg, scan))
3954 || ((reg2 = sfunc_uses_reg (scan))
3955 && REGNO (reg2) == REGNO (reg))))
3957 = gen_rtx_INSN_LIST (REG_LABEL, label, REG_NOTES (scan));
3959 while (scan != dies);
3965 fixup_addr_diff_vecs (first);
3969 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
3970 shorten_branches (first);
3972 /* Scan the function looking for move instructions which have to be
3973 changed to pc-relative loads and insert the literal tables. */
3975 mdep_reorg_phase = SH_FIXUP_PCLOAD;
3976 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
3983 else if (GET_CODE (insn) == JUMP_INSN
3984 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3992 /* Some code might have been inserted between the mova and
3993 its ADDR_DIFF_VEC. Check if the mova is still in range. */
3994 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
3995 total += get_attr_length (scan);
3997 /* range of mova is 1020, add 4 because pc counts from address of
3998 second instruction after this one, subtract 2 in case pc is 2
3999 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
4000 cancels out with alignment effects of the mova itself. */
4003 /* Change the mova into a load, and restart scanning
4004 there. broken_move will then return true for mova. */
4005 SET_SRC (PATTERN (mova))
4006 = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4007 INSN_CODE (mova) = -1;
4011 if (broken_move (insn))
4014 /* Scan ahead looking for a barrier to stick the constant table
4016 rtx barrier = find_barrier (num_mova, mova, insn);
4017 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
4019 if (num_mova && ! mova_p (mova))
4021 /* find_barrier had to change the first mova into a
4022 pcload; thus, we have to start with this new pcload. */
4026 /* Now find all the moves between the points and modify them. */
4027 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
4029 if (GET_CODE (scan) == CODE_LABEL)
4031 if (broken_move (scan))
4033 rtx *patp = &PATTERN (scan), pat = *patp;
4037 enum machine_mode mode;
4039 if (GET_CODE (pat) == PARALLEL)
4040 patp = &XVECEXP (pat, 0, 0), pat = *patp;
4041 src = SET_SRC (pat);
4042 dst = SET_DEST (pat);
4043 mode = GET_MODE (dst);
4045 if (mode == SImode && hi_const (src)
4046 && REGNO (dst) != FPUL_REG)
4051 while (GET_CODE (dst) == SUBREG)
4053 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
4054 GET_MODE (SUBREG_REG (dst)),
4057 dst = SUBREG_REG (dst);
4059 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
4062 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
4064 /* This must be an insn that clobbers r0. */
4065 rtx clobber = XVECEXP (PATTERN (scan), 0,
4066 XVECLEN (PATTERN (scan), 0) - 1);
4068 if (GET_CODE (clobber) != CLOBBER
4069 || ! rtx_equal_p (XEXP (clobber, 0), r0_rtx))
4073 && reg_set_between_p (r0_rtx, last_float_move, scan))
4077 && GET_MODE_SIZE (mode) != 4
4078 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
4080 lab = add_constant (src, mode, last_float);
4082 emit_insn_before (gen_mova (lab), scan);
4085 /* There will be a REG_UNUSED note for r0 on
4086 LAST_FLOAT_MOVE; we have to change it to REG_INC,
4087 lest reorg:mark_target_live_regs will not
4088 consider r0 to be used, and we end up with delay
4089 slot insn in front of SCAN that clobbers r0. */
4091 = find_regno_note (last_float_move, REG_UNUSED, 0);
4093 /* If we are not optimizing, then there may not be
4096 PUT_MODE (note, REG_INC);
4098 *last_float_addr = r0_inc_rtx;
4100 last_float_move = scan;
4102 newsrc = gen_rtx (MEM, mode,
4103 (((TARGET_SH4 && ! TARGET_FMOVD)
4104 || REGNO (dst) == FPUL_REG)
4107 last_float_addr = &XEXP (newsrc, 0);
4109 /* Remove the clobber of r0. */
4110 XEXP (clobber, 0) = gen_rtx_SCRATCH (Pmode);
4111 RTX_UNCHANGING_P (newsrc) = 1;
4113 /* This is a mova needing a label. Create it. */
4114 else if (GET_CODE (src) == UNSPEC
4115 && XINT (src, 1) == UNSPEC_MOVA
4116 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
4118 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
4119 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
4120 newsrc = gen_rtx_UNSPEC (SImode,
4121 gen_rtvec (1, newsrc),
4126 lab = add_constant (src, mode, 0);
4127 newsrc = gen_rtx_MEM (mode,
4128 gen_rtx_LABEL_REF (VOIDmode, lab));
4129 RTX_UNCHANGING_P (newsrc) = 1;
4131 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
4132 INSN_CODE (scan) = -1;
4135 dump_table (barrier);
4140 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
4141 INSN_ADDRESSES_FREE ();
4142 split_branches (first);
4144 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
4145 also has an effect on the register that holds the address of the sfunc.
4146 Insert an extra dummy insn in front of each sfunc that pretends to
4147 use this register. */
4148 if (flag_delayed_branch)
4150 for (insn = first; insn; insn = NEXT_INSN (insn))
4152 rtx reg = sfunc_uses_reg (insn);
4156 emit_insn_before (gen_use_sfunc_addr (reg), insn);
4160 /* fpscr is not actually a user variable, but we pretend it is for the
4161 sake of the previous optimization passes, since we want it handled like
4162 one. However, we don't have any debugging information for it, so turn
4163 it into a non-user variable now. */
4165 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
4167 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
4171 get_dest_uid (label, max_uid)
4175 rtx dest = next_real_insn (label);
4178 /* This can happen for an undefined label. */
4180 dest_uid = INSN_UID (dest);
4181 /* If this is a newly created branch redirection blocking instruction,
4182 we cannot index the branch_uid or insn_addresses arrays with its
4183 uid. But then, we won't need to, because the actual destination is
4184 the following branch. */
4185 while (dest_uid >= max_uid)
4187 dest = NEXT_INSN (dest);
4188 dest_uid = INSN_UID (dest);
4190 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
4195 /* Split condbranches that are out of range. Also add clobbers for
4196 scratch registers that are needed in far jumps.
4197 We do this before delay slot scheduling, so that it can take our
4198 newly created instructions into account. It also allows us to
4199 find branches with common targets more easily. */
4202 split_branches (first)
4206 struct far_branch **uid_branch, *far_branch_list = 0;
4207 int max_uid = get_max_uid ();
4209 /* Find out which branches are out of range. */
4210 shorten_branches (first);
4212 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
4213 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
4215 for (insn = first; insn; insn = NEXT_INSN (insn))
4216 if (! INSN_P (insn))
4218 else if (INSN_DELETED_P (insn))
4220 /* Shorten_branches would split this instruction again,
4221 so transform it into a note. */
4222 PUT_CODE (insn, NOTE);
4223 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4224 NOTE_SOURCE_FILE (insn) = 0;
4226 else if (GET_CODE (insn) == JUMP_INSN
4227 /* Don't mess with ADDR_DIFF_VEC */
4228 && (GET_CODE (PATTERN (insn)) == SET
4229 || GET_CODE (PATTERN (insn)) == RETURN))
4231 enum attr_type type = get_attr_type (insn);
4232 if (type == TYPE_CBRANCH)
4236 if (get_attr_length (insn) > 4)
4238 rtx src = SET_SRC (PATTERN (insn));
4239 rtx olabel = XEXP (XEXP (src, 1), 0);
4240 int addr = INSN_ADDRESSES (INSN_UID (insn));
4242 int dest_uid = get_dest_uid (olabel, max_uid);
4243 struct far_branch *bp = uid_branch[dest_uid];
4245 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
4246 the label if the LABEL_NUSES count drops to zero. There is
4247 always a jump_optimize pass that sets these values, but it
4248 proceeds to delete unreferenced code, and then if not
4249 optimizing, to un-delete the deleted instructions, thus
4250 leaving labels with too low uses counts. */
4253 JUMP_LABEL (insn) = olabel;
4254 LABEL_NUSES (olabel)++;
4258 bp = (struct far_branch *) alloca (sizeof *bp);
4259 uid_branch[dest_uid] = bp;
4260 bp->prev = far_branch_list;
4261 far_branch_list = bp;
4263 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
4264 LABEL_NUSES (bp->far_label)++;
4268 label = bp->near_label;
4269 if (! label && bp->address - addr >= CONDJUMP_MIN)
4271 rtx block = bp->insert_place;
4273 if (GET_CODE (PATTERN (block)) == RETURN)
4274 block = PREV_INSN (block);
4276 block = gen_block_redirect (block,
4278 label = emit_label_after (gen_label_rtx (),
4280 bp->near_label = label;
4282 else if (label && ! NEXT_INSN (label))
4284 if (addr + 2 - bp->address <= CONDJUMP_MAX)
4285 bp->insert_place = insn;
4287 gen_far_branch (bp);
4291 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
4293 bp->near_label = label = gen_label_rtx ();
4294 bp->insert_place = insn;
4297 if (! redirect_jump (insn, label, 1))
4302 /* get_attr_length (insn) == 2 */
4303 /* Check if we have a pattern where reorg wants to redirect
4304 the branch to a label from an unconditional branch that
4306 /* We can't use JUMP_LABEL here because it might be undefined
4307 when not optimizing. */
4308 /* A syntax error might cause beyond to be NULL_RTX. */
4310 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
4314 && (GET_CODE (beyond) == JUMP_INSN
4315 || ((beyond = next_active_insn (beyond))
4316 && GET_CODE (beyond) == JUMP_INSN))
4317 && GET_CODE (PATTERN (beyond)) == SET
4318 && recog_memoized (beyond) == CODE_FOR_jump
4320 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
4321 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4323 gen_block_redirect (beyond,
4324 INSN_ADDRESSES (INSN_UID (beyond)), 1);
4327 next = next_active_insn (insn);
4329 if ((GET_CODE (next) == JUMP_INSN
4330 || GET_CODE (next = next_active_insn (next)) == JUMP_INSN)
4331 && GET_CODE (PATTERN (next)) == SET
4332 && recog_memoized (next) == CODE_FOR_jump
4334 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
4335 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4337 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
4339 else if (type == TYPE_JUMP || type == TYPE_RETURN)
4341 int addr = INSN_ADDRESSES (INSN_UID (insn));
4344 struct far_branch *bp;
4346 if (type == TYPE_JUMP)
4348 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
4349 dest_uid = get_dest_uid (far_label, max_uid);
4352 /* Parse errors can lead to labels outside
4354 if (! NEXT_INSN (far_label))
4359 JUMP_LABEL (insn) = far_label;
4360 LABEL_NUSES (far_label)++;
4362 redirect_jump (insn, NULL_RTX, 1);
4366 bp = uid_branch[dest_uid];
4369 bp = (struct far_branch *) alloca (sizeof *bp);
4370 uid_branch[dest_uid] = bp;
4371 bp->prev = far_branch_list;
4372 far_branch_list = bp;
4374 bp->far_label = far_label;
4376 LABEL_NUSES (far_label)++;
4378 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
4379 if (addr - bp->address <= CONDJUMP_MAX)
4380 emit_label_after (bp->near_label, PREV_INSN (insn));
4383 gen_far_branch (bp);
4389 bp->insert_place = insn;
4391 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
4393 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
4396 /* Generate all pending far branches,
4397 and free our references to the far labels. */
4398 while (far_branch_list)
4400 if (far_branch_list->near_label
4401 && ! NEXT_INSN (far_branch_list->near_label))
4402 gen_far_branch (far_branch_list);
4404 && far_branch_list->far_label
4405 && ! --LABEL_NUSES (far_branch_list->far_label))
4406 delete_insn (far_branch_list->far_label);
4407 far_branch_list = far_branch_list->prev;
4410 /* Instruction length information is no longer valid due to the new
4411 instructions that have been generated. */
4412 init_insn_lengths ();
4415 /* Dump out instruction addresses, which is useful for debugging the
4416 constant pool table stuff.
4418 If relaxing, output the label and pseudo-ops used to link together
4419 calls and the instruction which set the registers. */
4421 /* ??? This is unnecessary, and probably should be deleted. This makes
4422 the insn_addresses declaration above unnecessary. */
4424 /* ??? The addresses printed by this routine for insns are nonsense for
4425 insns which are inside of a sequence where none of the inner insns have
4426 variable length. This is because the second pass of shorten_branches
4427 does not bother to update them. */
4430 final_prescan_insn (insn, opvec, noperands)
4432 rtx *opvec ATTRIBUTE_UNUSED;
4433 int noperands ATTRIBUTE_UNUSED;
4435 if (TARGET_DUMPISIZE)
4436 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
4442 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
4447 pattern = PATTERN (insn);
4448 if (GET_CODE (pattern) == PARALLEL)
4449 pattern = XVECEXP (pattern, 0, 0);
4450 if (GET_CODE (pattern) == CALL
4451 || (GET_CODE (pattern) == SET
4452 && (GET_CODE (SET_SRC (pattern)) == CALL
4453 || get_attr_type (insn) == TYPE_SFUNC)))
4454 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
4455 CODE_LABEL_NUMBER (XEXP (note, 0)));
4456 else if (GET_CODE (pattern) == SET)
4457 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4458 CODE_LABEL_NUMBER (XEXP (note, 0)));
4465 /* Dump out any constants accumulated in the final pass. These will
4469 output_jump_label_table ()
4475 fprintf (asm_out_file, "\t.align 2\n");
4476 for (i = 0; i < pool_size; i++)
4478 pool_node *p = &pool_vector[i];
4480 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4481 CODE_LABEL_NUMBER (p->label));
4482 output_asm_insn (".long %O0", &p->value);
4490 /* A full frame looks like:
4494 [ if current_function_anonymous_args
4507 local-0 <- fp points here. */
4509 /* Number of bytes pushed for anonymous args, used to pass information
4510 between expand_prologue and expand_epilogue. */
4512 static int extra_push;
4514 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register
4515 to be adjusted, and TEMP, if nonnegative, holds the register number
4516 of a general register that we may clobber. */
4519 output_stack_adjust (size, reg, temp, emit_fn)
4523 rtx (*emit_fn) PARAMS ((rtx));
4527 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4532 if (CONST_OK_FOR_ADD (size))
4533 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
4534 /* Try to do it with two partial adjustments; however, we must make
4535 sure that the stack is properly aligned at all times, in case
4536 an interrupt occurs between the two partial adjustments. */
4537 else if (CONST_OK_FOR_ADD (size / 2 & -align)
4538 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
4540 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
4541 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
4548 /* If TEMP is invalid, we could temporarily save a general
4549 register to MACL. However, there is currently no need
4550 to handle this case, so just abort when we see it. */
4553 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
4555 /* If SIZE is negative, subtract the positive value.
4556 This sometimes allows a constant pool entry to be shared
4557 between prologue and epilogue code. */
4560 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
4561 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
4565 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
4566 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
4568 if (emit_fn == frame_insn)
4570 = (gen_rtx_EXPR_LIST
4571 (REG_FRAME_RELATED_EXPR,
4572 gen_rtx_SET (VOIDmode, reg,
4573 gen_rtx_PLUS (SImode, reg, GEN_INT (size))),
4584 RTX_FRAME_RELATED_P (x) = 1;
4588 /* Output RTL to push register RN onto the stack. */
4596 x = gen_push_fpul ();
4597 else if (rn == FPSCR_REG)
4598 x = gen_push_fpscr ();
4599 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4600 && FP_OR_XD_REGISTER_P (rn))
4602 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4604 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
4606 else if (TARGET_SH2E && FP_REGISTER_P (rn))
4607 x = gen_push_e (gen_rtx_REG (SFmode, rn));
4609 x = gen_push (gen_rtx_REG (SImode, rn));
4613 = gen_rtx_EXPR_LIST (REG_INC,
4614 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4618 /* Output RTL to pop register RN from the stack. */
4626 x = gen_pop_fpul ();
4627 else if (rn == FPSCR_REG)
4628 x = gen_pop_fpscr ();
4629 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4630 && FP_OR_XD_REGISTER_P (rn))
4632 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4634 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
4636 else if (TARGET_SH2E && FP_REGISTER_P (rn))
4637 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
4639 x = gen_pop (gen_rtx_REG (SImode, rn));
4643 = gen_rtx_EXPR_LIST (REG_INC,
4644 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4647 /* Generate code to push the regs specified in the mask. */
4651 HOST_WIDE_INT *mask;
4655 /* Push PR last; this gives better latencies after the prologue, and
4656 candidates for the return delay slot when there are no general
4657 registers pushed. */
4658 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4659 if (i != PR_REG && mask[i / 32] & (1 << (i % 32)))
4661 if (mask[PR_REG / 32] & (1 << (PR_REG % 32)))
4665 /* Work out the registers which need to be saved, both as a mask and a
4666 count of saved words.
4668 If doing a pragma interrupt function, then push all regs used by the
4669 function, and if we call another function (we can tell by looking at PR),
4670 make sure that all the regs it clobbers are safe too. */
4673 calc_live_regs (count_ptr, live_regs_mask)
4675 HOST_WIDE_INT *live_regs_mask;
4679 int interrupt_handler;
4682 interrupt_handler = sh_cfun_interrupt_handler_p ();
4684 for (count = 0; 32 * count < FIRST_PSEUDO_REGISTER; count++)
4685 live_regs_mask[count] = 0;
4686 /* If we can save a lot of saves by switching to double mode, do that. */
4687 if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE)
4688 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
4689 if (regs_ever_live[reg] && regs_ever_live[reg+1]
4690 && (! call_used_regs[reg] || (interrupt_handler && ! pragma_trapa))
4693 target_flags &= ~FPU_SINGLE_BIT;
4696 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
4697 knows how to use it. That means the pseudo originally allocated for
4698 the initial value can become the PR_MEDIA_REG hard register, as seen for
4699 execute/20010122-1.c:test9. */
4701 pr_live = regs_ever_live[PR_MEDIA_REG];
4704 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
4705 pr_live = (pr_initial
4706 ? (GET_CODE (pr_initial) != REG
4707 || REGNO (pr_initial) != (PR_REG))
4708 : regs_ever_live[PR_REG]);
4710 /* Force PR to be live if the prologue has to call the SHmedia
4711 argument decoder or register saver. */
4712 if (TARGET_SHCOMPACT
4713 && ((current_function_args_info.call_cookie
4714 & ~ CALL_COOKIE_RET_TRAMP (1))
4715 || current_function_has_nonlocal_label))
4717 for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--)
4719 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
4721 : (interrupt_handler && ! pragma_trapa)
4722 ? (/* Need to save all the regs ever live. */
4723 (regs_ever_live[reg]
4724 || (call_used_regs[reg]
4725 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
4727 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
4728 && reg != RETURN_ADDRESS_POINTER_REGNUM
4729 && reg != T_REG && reg != GBR_REG
4730 /* Push fpscr only on targets which have FPU */
4731 && (reg != FPSCR_REG || TARGET_FPU_ANY))
4732 : (/* Only push those regs which are used and need to be saved. */
4735 && current_function_args_info.call_cookie
4736 && reg == PIC_OFFSET_TABLE_REGNUM)
4737 || (regs_ever_live[reg] && ! call_used_regs[reg])
4738 || (current_function_calls_eh_return
4739 && (reg == EH_RETURN_DATA_REGNO (0)
4740 || reg == EH_RETURN_DATA_REGNO (1)
4741 || reg == EH_RETURN_DATA_REGNO (2)
4742 || reg == EH_RETURN_DATA_REGNO (3)))))
4744 live_regs_mask[reg / 32] |= 1 << (reg % 32);
4745 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4747 if ((TARGET_SH4 || TARGET_SH5) && TARGET_FMOVD
4748 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
4750 if (FP_REGISTER_P (reg))
4752 if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
4754 live_regs_mask[(reg ^ 1) / 32] |= 1 << ((reg ^ 1) % 32);
4755 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
4758 else if (XD_REGISTER_P (reg))
4760 /* Must switch to double mode to access these registers. */
4761 target_flags &= ~FPU_SINGLE_BIT;
4770 /* Code to generate prologue and epilogue sequences */
4772 /* PUSHED is the number of bytes that are being pushed on the
4773 stack for register saves. Return the frame size, padded
4774 appropriately so that the stack stays properly aligned. */
4775 static HOST_WIDE_INT
4776 rounded_frame_size (pushed)
4779 HOST_WIDE_INT size = get_frame_size ();
4780 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4782 return ((size + pushed + align - 1) & -align) - pushed;
4785 /* Choose a call-clobbered target-branch register that remains
4786 unchanged along the whole function. We set it up as the return
4787 value in the prologue. */
4789 sh_media_register_for_return ()
4794 if (! current_function_is_leaf)
4797 tr0_used = flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
4799 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
4800 if (call_used_regs[regno] && ! regs_ever_live[regno])
4807 sh_expand_prologue ()
4809 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
4812 int save_flags = target_flags;
4814 current_function_interrupt = sh_cfun_interrupt_handler_p ();
4816 /* We have pretend args if we had an object sent partially in registers
4817 and partially on the stack, e.g. a large structure. */
4818 output_stack_adjust (-current_function_pretend_args_size
4819 - current_function_args_info.stack_regs * 8,
4820 stack_pointer_rtx, TARGET_SH5 ? 0 : 1, frame_insn);
4824 if (TARGET_SHCOMPACT && flag_pic && current_function_args_info.call_cookie)
4825 /* We're going to use the PIC register to load the address of the
4826 incoming-argument decoder and/or of the return trampoline from
4827 the GOT, so make sure the PIC register is preserved and
4829 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
4831 if (TARGET_SHCOMPACT
4832 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
4836 /* First, make all registers with incoming arguments that will
4837 be pushed onto the stack live, so that register renaming
4838 doesn't overwrite them. */
4839 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
4840 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info.call_cookie)
4841 >= NPARM_REGS (SImode) - reg)
4842 for (; reg < NPARM_REGS (SImode); reg++)
4843 emit_insn (gen_shcompact_preserve_incoming_args
4844 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
4845 else if (CALL_COOKIE_INT_REG_GET
4846 (current_function_args_info.call_cookie, reg) == 1)
4847 emit_insn (gen_shcompact_preserve_incoming_args
4848 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
4850 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
4852 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
4853 GEN_INT (current_function_args_info.call_cookie));
4854 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
4855 gen_rtx_REG (SImode, R0_REG));
4857 else if (TARGET_SHMEDIA)
4859 int tr = sh_media_register_for_return ();
4863 rtx insn = emit_move_insn (gen_rtx_REG (DImode, tr),
4864 gen_rtx_REG (DImode, PR_MEDIA_REG));
4866 /* If this function only exits with sibcalls, this copy
4867 will be flagged as dead. */
4868 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
4874 /* Emit the code for SETUP_VARARGS. */
4875 if (current_function_stdarg)
4877 /* This is not used by the SH2E calling convention */
4878 if (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 && ! TARGET_HITACHI)
4880 /* Push arg regs as if they'd been provided by caller in stack. */
4881 for (i = 0; i < NPARM_REGS(SImode); i++)
4883 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
4886 if (i >= (NPARM_REGS(SImode)
4887 - current_function_args_info.arg_count[(int) SH_ARG_INT]
4891 RTX_FRAME_RELATED_P (insn) = 0;
4897 /* If we're supposed to switch stacks at function entry, do so now. */
4899 emit_insn (gen_sp_switch_1 ());
4901 calc_live_regs (&d, live_regs_mask);
4902 /* ??? Maybe we could save some switching if we can move a mode switch
4903 that already happens to be at the function start into the prologue. */
4904 if (target_flags != save_flags)
4905 emit_insn (gen_toggle_sz ());
4912 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
4913 int offset_in_r0 = -1;
4916 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
4917 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
4918 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
4920 offset = d + d_rounding;
4921 output_stack_adjust (-offset, stack_pointer_rtx, 1, frame_insn);
4923 /* We loop twice: first, we save 8-byte aligned registers in the
4924 higher addresses, that are known to be aligned. Then, we
4925 proceed to saving 32-bit registers that don't need 8-byte
4927 /* Note that if you change this code in a way that affects where
4928 the return register is saved, you have to update not only
4929 sh_expand_epilogue, but also sh_set_return_address. */
4930 for (align = 1; align >= 0; align--)
4931 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
4932 if (live_regs_mask[i/32] & (1 << (i % 32)))
4934 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
4936 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
4938 if (mode == SFmode && (i % 2) == 1
4939 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
4940 && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
4947 /* If we're doing the aligned pass and this is not aligned,
4948 or we're doing the unaligned pass and this is aligned,
4950 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
4954 offset -= GET_MODE_SIZE (mode);
4956 reg_rtx = gen_rtx_REG (mode, reg);
4958 mem_rtx = gen_rtx_MEM (mode,
4959 gen_rtx_PLUS (Pmode,
4963 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
4969 if (HAVE_PRE_DECREMENT
4970 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
4971 || mem_rtx == NULL_RTX
4972 || i == PR_REG || SPECIAL_REGISTER_P (i)))
4974 pre_dec = gen_rtx_MEM (mode,
4975 gen_rtx_PRE_DEC (Pmode, r0));
4977 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
4986 offset += GET_MODE_SIZE (mode);
4990 if (mem_rtx != NULL_RTX)
4993 if (offset_in_r0 == -1)
4995 emit_move_insn (r0, GEN_INT (offset));
4996 offset_in_r0 = offset;
4998 else if (offset != offset_in_r0)
5003 GEN_INT (offset - offset_in_r0)));
5004 offset_in_r0 += offset - offset_in_r0;
5007 if (pre_dec != NULL_RTX)
5013 (Pmode, r0, stack_pointer_rtx));
5017 offset -= GET_MODE_SIZE (mode);
5018 offset_in_r0 -= GET_MODE_SIZE (mode);
5023 mem_rtx = gen_rtx_MEM (mode, r0);
5025 mem_rtx = gen_rtx_MEM (mode,
5026 gen_rtx_PLUS (Pmode,
5030 /* We must not use an r0-based address for target-branch
5031 registers or for special registers without pre-dec
5032 memory addresses, since we store their values in r0
5034 if (TARGET_REGISTER_P (i)
5035 || ((i == PR_REG || SPECIAL_REGISTER_P (i))
5036 && mem_rtx != pre_dec))
5040 if (TARGET_REGISTER_P (i)
5041 || ((i == PR_REG || SPECIAL_REGISTER_P (i))
5042 && mem_rtx != pre_dec))
5044 rtx r0mode = gen_rtx_REG (GET_MODE (reg_rtx), R0_REG);
5046 emit_move_insn (r0mode, reg_rtx);
5054 emit_move_insn (mem_rtx, reg_rtx);
5057 if (offset != d_rounding)
5061 push_regs (live_regs_mask);
5063 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5065 rtx insn = get_last_insn ();
5066 rtx last = emit_insn (gen_GOTaddr2picreg ());
5068 /* Mark these insns as possibly dead. Sometimes, flow2 may
5069 delete all uses of the PIC register. In this case, let it
5070 delete the initialization too. */
5073 insn = NEXT_INSN (insn);
5075 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5079 while (insn != last);
5082 if (SHMEDIA_REGS_STACK_ADJUST ())
5084 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5085 gen_rtx_SYMBOL_REF (Pmode,
5087 ? "__GCC_push_shmedia_regs"
5088 : "__GCC_push_shmedia_regs_nofpu"));
5089 /* This must NOT go through the PLT, otherwise mach and macl
5090 may be clobbered. */
5091 emit_insn (gen_shmedia_save_restore_regs_compact
5092 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
5095 if (target_flags != save_flags)
5097 rtx insn = emit_insn (gen_toggle_sz ());
5099 /* If we're lucky, a mode switch in the function body will
5100 overwrite fpscr, turning this insn dead. Tell flow this
5101 insn is ok to delete. */
5102 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5107 target_flags = save_flags;
5109 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
5110 stack_pointer_rtx, TARGET_SH5 ? 0 : 1, frame_insn);
5112 if (frame_pointer_needed)
5113 frame_insn (GEN_MOV (frame_pointer_rtx, stack_pointer_rtx));
5115 if (TARGET_SHCOMPACT
5116 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
5118 /* This must NOT go through the PLT, otherwise mach and macl
5119 may be clobbered. */
5120 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5121 gen_rtx_SYMBOL_REF (Pmode,
5122 "__GCC_shcompact_incoming_args"));
5123 emit_insn (gen_shcompact_incoming_args ());
5128 sh_expand_epilogue ()
5130 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
5134 int save_flags = target_flags;
5137 calc_live_regs (&d, live_regs_mask);
5139 if (TARGET_SH5 && d % (STACK_BOUNDARY / BITS_PER_UNIT))
5140 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5141 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
5143 frame_size = rounded_frame_size (d) - d_rounding;
5145 if (frame_pointer_needed)
5147 output_stack_adjust (frame_size, frame_pointer_rtx, 7, emit_insn);
5149 /* We must avoid moving the stack pointer adjustment past code
5150 which reads from the local frame, else an interrupt could
5151 occur after the SP adjustment and clobber data in the local
5153 emit_insn (gen_blockage ());
5154 emit_insn (GEN_MOV (stack_pointer_rtx, frame_pointer_rtx));
5156 else if (frame_size)
5158 /* We must avoid moving the stack pointer adjustment past code
5159 which reads from the local frame, else an interrupt could
5160 occur after the SP adjustment and clobber data in the local
5162 emit_insn (gen_blockage ());
5163 output_stack_adjust (frame_size, stack_pointer_rtx, 7, emit_insn);
5166 if (SHMEDIA_REGS_STACK_ADJUST ())
5168 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5169 gen_rtx_SYMBOL_REF (Pmode,
5171 ? "__GCC_pop_shmedia_regs"
5172 : "__GCC_pop_shmedia_regs_nofpu"));
5173 /* This must NOT go through the PLT, otherwise mach and macl
5174 may be clobbered. */
5175 emit_insn (gen_shmedia_save_restore_regs_compact
5176 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
5179 /* Pop all the registers. */
5181 if (target_flags != save_flags)
5182 emit_insn (gen_toggle_sz ());
5185 int offset = d_rounding;
5186 int offset_in_r0 = -1;
5189 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
5191 /* We loop twice: first, we save 8-byte aligned registers in the
5192 higher addresses, that are known to be aligned. Then, we
5193 proceed to saving 32-bit registers that don't need 8-byte
5195 for (align = 0; align <= 1; align++)
5196 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5197 if (live_regs_mask[i/32] & (1 << (i % 32)))
5199 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5201 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
5203 if (mode == SFmode && (i % 2) == 0
5204 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5205 && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
5211 /* If we're doing the aligned pass and this is not aligned,
5212 or we're doing the unaligned pass and this is aligned,
5214 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
5218 reg_rtx = gen_rtx_REG (mode, reg);
5220 mem_rtx = gen_rtx_MEM (mode,
5221 gen_rtx_PLUS (Pmode,
5225 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
5231 if (HAVE_POST_INCREMENT
5232 && (offset == offset_in_r0
5233 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
5234 && mem_rtx == NULL_RTX)
5235 || i == PR_REG || SPECIAL_REGISTER_P (i)))
5237 post_inc = gen_rtx_MEM (mode,
5238 gen_rtx_POST_INC (Pmode, r0));
5240 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
5243 post_inc = NULL_RTX;
5252 if (mem_rtx != NULL_RTX)
5255 if (offset_in_r0 == -1)
5257 emit_move_insn (r0, GEN_INT (offset));
5258 offset_in_r0 = offset;
5260 else if (offset != offset_in_r0)
5265 GEN_INT (offset - offset_in_r0)));
5266 offset_in_r0 += offset - offset_in_r0;
5269 if (post_inc != NULL_RTX)
5275 (Pmode, r0, stack_pointer_rtx));
5281 offset_in_r0 += GET_MODE_SIZE (mode);
5284 mem_rtx = gen_rtx_MEM (mode, r0);
5286 mem_rtx = gen_rtx_MEM (mode,
5287 gen_rtx_PLUS (Pmode,
5291 if ((i == PR_REG || SPECIAL_REGISTER_P (i))
5292 && mem_rtx != post_inc)
5296 if ((i == PR_REG || SPECIAL_REGISTER_P (i))
5297 && mem_rtx != post_inc)
5299 insn = emit_move_insn (r0, mem_rtx);
5302 else if (TARGET_REGISTER_P (i))
5304 rtx r1 = gen_rtx_REG (mode, R1_REG);
5306 insn = emit_move_insn (r1, mem_rtx);
5310 insn = emit_move_insn (reg_rtx, mem_rtx);
5312 offset += GET_MODE_SIZE (mode);
5315 if (offset != d + d_rounding)
5322 if (live_regs_mask[PR_REG / 32] & (1 << (PR_REG % 32)))
5324 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5326 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
5328 if (j != PR_REG && live_regs_mask[j / 32] & (1 << (j % 32)))
5332 if (target_flags != save_flags)
5333 emit_insn (gen_toggle_sz ());
5334 target_flags = save_flags;
5336 output_stack_adjust (extra_push + current_function_pretend_args_size
5338 + current_function_args_info.stack_regs * 8,
5339 stack_pointer_rtx, 7, emit_insn);
5341 if (current_function_calls_eh_return)
5342 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
5343 EH_RETURN_STACKADJ_RTX));
5345 /* Switch back to the normal stack if necessary. */
5347 emit_insn (gen_sp_switch_2 ());
5349 /* Tell flow the insn that pops PR isn't dead. */
5350 /* PR_REG will never be live in SHmedia mode, and we don't need to
5351 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
5352 by the return pattern. */
5353 if (live_regs_mask[PR_REG / 32] & (1 << (PR_REG % 32)))
5354 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
5357 static int sh_need_epilogue_known = 0;
5362 if (! sh_need_epilogue_known)
5367 sh_expand_epilogue ();
5368 epilogue = get_insns ();
5370 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
5372 return sh_need_epilogue_known > 0;
5375 /* Emit code to change the current function's return address to RA.
5376 TEMP is available as a scratch register, if needed. */
5379 sh_set_return_address (ra, tmp)
5382 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
5385 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
5388 calc_live_regs (&d, live_regs_mask);
5390 /* If pr_reg isn't life, we can set it (or the register given in
5391 sh_media_register_for_return) directly. */
5392 if ((live_regs_mask[pr_reg / 32] & (1 << (pr_reg % 32))) == 0)
5398 int rr_regno = sh_media_register_for_return ();
5403 rr = gen_rtx_REG (DImode, rr_regno);
5406 rr = gen_rtx_REG (SImode, pr_reg);
5408 emit_insn (GEN_MOV (rr, ra));
5409 /* Tell flow the register for return isn't dead. */
5410 emit_insn (gen_rtx_USE (VOIDmode, rr));
5420 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
5421 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5422 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
5426 /* We loop twice: first, we save 8-byte aligned registers in the
5427 higher addresses, that are known to be aligned. Then, we
5428 proceed to saving 32-bit registers that don't need 8-byte
5430 for (align = 0; align <= 1; align++)
5431 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5432 if (live_regs_mask[i/32] & (1 << (i % 32)))
5434 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5436 if (mode == SFmode && (i % 2) == 0
5437 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5438 && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
5444 /* If we're doing the aligned pass and this is not aligned,
5445 or we're doing the unaligned pass and this is aligned,
5447 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
5454 offset += GET_MODE_SIZE (mode);
5457 /* We can't find pr register. */
5461 pr_offset = (rounded_frame_size (d) - d_rounding + offset
5462 + SHMEDIA_REGS_STACK_ADJUST ());
5465 pr_offset = rounded_frame_size (d) - d_rounding;
5467 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
5468 emit_insn (GEN_ADD3 (tmp, tmp, frame_pointer_rtx));
5470 tmp = gen_rtx_MEM (Pmode, tmp);
5471 emit_insn (GEN_MOV (tmp, ra));
5474 /* Clear variables at function end. */
5477 sh_output_function_epilogue (file, size)
5478 FILE *file ATTRIBUTE_UNUSED;
5479 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
5481 trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
5482 sh_need_epilogue_known = 0;
5483 sp_switch = NULL_RTX;
5487 sh_builtin_saveregs ()
5489 /* First unnamed integer register. */
5490 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
5491 /* Number of integer registers we need to save. */
5492 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
5493 /* First unnamed SFmode float reg */
5494 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
5495 /* Number of SFmode float regs to save. */
5496 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
5499 HOST_WIDE_INT alias_set;
5505 int pushregs = n_intregs;
5507 while (pushregs < NPARM_REGS (SImode) - 1
5508 && (CALL_COOKIE_INT_REG_GET
5509 (current_function_args_info.call_cookie,
5510 NPARM_REGS (SImode) - pushregs)
5513 current_function_args_info.call_cookie
5514 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
5519 if (pushregs == NPARM_REGS (SImode))
5520 current_function_args_info.call_cookie
5521 |= (CALL_COOKIE_INT_REG (0, 1)
5522 | CALL_COOKIE_STACKSEQ (pushregs - 1));
5524 current_function_args_info.call_cookie
5525 |= CALL_COOKIE_STACKSEQ (pushregs);
5527 current_function_pretend_args_size += 8 * n_intregs;
5529 if (TARGET_SHCOMPACT)
5533 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
5535 error ("__builtin_saveregs not supported by this subtarget");
5542 /* Allocate block of memory for the regs. */
5543 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
5544 Or can assign_stack_local accept a 0 SIZE argument? */
5545 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
5548 regbuf = gen_rtx_MEM (BLKmode,
5549 gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
5550 else if (n_floatregs & 1)
5554 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
5555 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
5556 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
5557 regbuf = change_address (regbuf, BLKmode, addr);
5560 regbuf = assign_stack_local (BLKmode, bufsize, 0);
5561 alias_set = get_varargs_alias_set ();
5562 set_mem_alias_set (regbuf, alias_set);
5565 This is optimized to only save the regs that are necessary. Explicitly
5566 named args need not be saved. */
5568 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
5569 adjust_address (regbuf, BLKmode,
5570 n_floatregs * UNITS_PER_WORD),
5571 n_intregs, n_intregs * UNITS_PER_WORD);
5574 /* Return the address of the regbuf. */
5575 return XEXP (regbuf, 0);
5578 This is optimized to only save the regs that are necessary. Explicitly
5579 named args need not be saved.
5580 We explicitly build a pointer to the buffer because it halves the insn
5581 count when not optimizing (otherwise the pointer is built for each reg
5583 We emit the moves in reverse order so that we can use predecrement. */
5585 fpregs = gen_reg_rtx (Pmode);
5586 emit_move_insn (fpregs, XEXP (regbuf, 0));
5587 emit_insn (gen_addsi3 (fpregs, fpregs,
5588 GEN_INT (n_floatregs * UNITS_PER_WORD)));
5592 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
5594 emit_insn (gen_addsi3 (fpregs, fpregs,
5595 GEN_INT (-2 * UNITS_PER_WORD)));
5596 mem = gen_rtx_MEM (DFmode, fpregs);
5597 set_mem_alias_set (mem, alias_set);
5598 emit_move_insn (mem,
5599 gen_rtx (REG, DFmode, BASE_ARG_REG (DFmode) + regno));
5601 regno = first_floatreg;
5604 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5605 mem = gen_rtx_MEM (SFmode, fpregs);
5606 set_mem_alias_set (mem, alias_set);
5607 emit_move_insn (mem,
5608 gen_rtx (REG, SFmode, BASE_ARG_REG (SFmode) + regno
5609 - (TARGET_LITTLE_ENDIAN != 0)));
5613 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
5617 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5618 mem = gen_rtx_MEM (SFmode, fpregs);
5619 set_mem_alias_set (mem, alias_set);
5620 emit_move_insn (mem,
5621 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
5624 /* Return the address of the regbuf. */
5625 return XEXP (regbuf, 0);
5628 /* Define the `__builtin_va_list' type for the ABI. */
5633 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5636 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4) || TARGET_HITACHI)
5637 return ptr_type_node;
5639 record = make_node (RECORD_TYPE);
5641 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
5643 f_next_o_limit = build_decl (FIELD_DECL,
5644 get_identifier ("__va_next_o_limit"),
5646 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
5648 f_next_fp_limit = build_decl (FIELD_DECL,
5649 get_identifier ("__va_next_fp_limit"),
5651 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
5654 DECL_FIELD_CONTEXT (f_next_o) = record;
5655 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
5656 DECL_FIELD_CONTEXT (f_next_fp) = record;
5657 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
5658 DECL_FIELD_CONTEXT (f_next_stack) = record;
5660 TYPE_FIELDS (record) = f_next_o;
5661 TREE_CHAIN (f_next_o) = f_next_o_limit;
5662 TREE_CHAIN (f_next_o_limit) = f_next_fp;
5663 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
5664 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
5666 layout_type (record);
5671 /* Implement `va_start' for varargs and stdarg. */
5674 sh_va_start (valist, nextarg)
5678 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5679 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
5685 expand_builtin_saveregs ();
5686 std_expand_builtin_va_start (valist, nextarg);
5690 if ((! TARGET_SH2E && ! TARGET_SH4) || TARGET_HITACHI)
5692 std_expand_builtin_va_start (valist, nextarg);
5696 f_next_o = TYPE_FIELDS (va_list_type_node);
5697 f_next_o_limit = TREE_CHAIN (f_next_o);
5698 f_next_fp = TREE_CHAIN (f_next_o_limit);
5699 f_next_fp_limit = TREE_CHAIN (f_next_fp);
5700 f_next_stack = TREE_CHAIN (f_next_fp_limit);
5702 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
5703 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
5704 valist, f_next_o_limit);
5705 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp);
5706 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
5707 valist, f_next_fp_limit);
5708 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
5709 valist, f_next_stack);
5711 /* Call __builtin_saveregs. */
5712 u = make_tree (ptr_type_node, expand_builtin_saveregs ());
5713 t = build (MODIFY_EXPR, ptr_type_node, next_fp, u);
5714 TREE_SIDE_EFFECTS (t) = 1;
5715 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5717 nfp = current_function_args_info.arg_count[SH_ARG_FLOAT];
5722 u = fold (build (PLUS_EXPR, ptr_type_node, u,
5723 build_int_2 (UNITS_PER_WORD * nfp, 0)));
5724 t = build (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
5725 TREE_SIDE_EFFECTS (t) = 1;
5726 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5728 t = build (MODIFY_EXPR, ptr_type_node, next_o, u);
5729 TREE_SIDE_EFFECTS (t) = 1;
5730 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5732 nint = current_function_args_info.arg_count[SH_ARG_INT];
5737 u = fold (build (PLUS_EXPR, ptr_type_node, u,
5738 build_int_2 (UNITS_PER_WORD * nint, 0)));
5739 t = build (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
5740 TREE_SIDE_EFFECTS (t) = 1;
5741 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5743 u = make_tree (ptr_type_node, nextarg);
5744 t = build (MODIFY_EXPR, ptr_type_node, next_stack, u);
5745 TREE_SIDE_EFFECTS (t) = 1;
5746 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5749 /* Implement `va_arg'. */
5752 sh_va_arg (valist, type)
5755 HOST_WIDE_INT size, rsize;
5756 tree tmp, pptr_type_node;
5759 int pass_by_ref = MUST_PASS_IN_STACK (TYPE_MODE (type), type);
5761 size = int_size_in_bytes (type);
5762 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5763 pptr_type_node = build_pointer_type (ptr_type_node);
5766 type = build_pointer_type (type);
5768 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4) && ! TARGET_HITACHI)
5770 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5771 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
5773 rtx lab_false, lab_over;
5775 f_next_o = TYPE_FIELDS (va_list_type_node);
5776 f_next_o_limit = TREE_CHAIN (f_next_o);
5777 f_next_fp = TREE_CHAIN (f_next_o_limit);
5778 f_next_fp_limit = TREE_CHAIN (f_next_fp);
5779 f_next_stack = TREE_CHAIN (f_next_fp_limit);
5781 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
5782 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
5783 valist, f_next_o_limit);
5784 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp),
5786 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
5787 valist, f_next_fp_limit);
5788 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
5789 valist, f_next_stack);
5793 pass_as_float = ((TREE_CODE (type) == REAL_TYPE && size <= 8)
5794 || (TREE_CODE (type) == COMPLEX_TYPE
5795 && TREE_CODE (TREE_TYPE (type)) == REAL_TYPE
5800 pass_as_float = (TREE_CODE (type) == REAL_TYPE && size == 4);
5803 addr_rtx = gen_reg_rtx (Pmode);
5804 lab_false = gen_label_rtx ();
5805 lab_over = gen_label_rtx ();
5810 = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
5811 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
5813 emit_cmp_and_jump_insns (expand_expr (next_fp, NULL_RTX, Pmode,
5815 expand_expr (next_fp_limit, NULL_RTX,
5816 Pmode, EXPAND_NORMAL),
5817 GE, const1_rtx, Pmode, 1, lab_false);
5819 if (TYPE_ALIGN (type) > BITS_PER_WORD
5820 || (((TREE_CODE (type) == REAL_TYPE && size == 8) || size == 16)
5821 && (n_floatregs & 1)))
5823 tmp = build (BIT_AND_EXPR, ptr_type_node, next_fp,
5824 build_int_2 (UNITS_PER_WORD, 0));
5825 tmp = build (PLUS_EXPR, ptr_type_node, next_fp, tmp);
5826 tmp = build (MODIFY_EXPR, ptr_type_node, next_fp, tmp);
5827 TREE_SIDE_EFFECTS (tmp) = 1;
5828 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
5831 tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp);
5832 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5834 emit_move_insn (addr_rtx, r);
5836 emit_jump_insn (gen_jump (lab_over));
5838 emit_label (lab_false);
5840 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
5841 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5843 emit_move_insn (addr_rtx, r);
5847 tmp = build (PLUS_EXPR, ptr_type_node, next_o,
5848 build_int_2 (rsize, 0));
5850 emit_cmp_and_jump_insns (expand_expr (tmp, NULL_RTX, Pmode,
5852 expand_expr (next_o_limit, NULL_RTX,
5853 Pmode, EXPAND_NORMAL),
5854 GT, const1_rtx, Pmode, 1, lab_false);
5856 tmp = build1 (ADDR_EXPR, pptr_type_node, next_o);
5857 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5859 emit_move_insn (addr_rtx, r);
5861 emit_jump_insn (gen_jump (lab_over));
5863 emit_label (lab_false);
5865 if (size > 4 && ! TARGET_SH4)
5867 tmp = build (MODIFY_EXPR, ptr_type_node, next_o, next_o_limit);
5868 TREE_SIDE_EFFECTS (tmp) = 1;
5869 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
5872 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
5873 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5875 emit_move_insn (addr_rtx, r);
5878 emit_label (lab_over);
5880 tmp = make_tree (pptr_type_node, addr_rtx);
5881 valist = build1 (INDIRECT_REF, ptr_type_node, tmp);
5884 /* ??? In va-sh.h, there had been code to make values larger than
5885 size 8 indirect. This does not match the FUNCTION_ARG macros. */
5887 result = std_expand_builtin_va_arg (valist, type);
5890 #ifdef POINTERS_EXTEND_UNSIGNED
5891 if (GET_MODE (addr) != Pmode)
5892 addr = convert_memory_address (Pmode, result);
5894 result = gen_rtx_MEM (ptr_mode, force_reg (Pmode, result));
5895 set_mem_alias_set (result, get_varargs_alias_set ());
5897 /* ??? expand_builtin_va_arg will also set the alias set of the dereferenced
5898 argument to the varargs alias set. */
5902 /* Define the offset between two registers, one to be eliminated, and
5903 the other its replacement, at the start of a routine. */
5906 initial_elimination_offset (from, to)
5911 int regs_saved_rounding = 0;
5912 int total_saved_regs_space;
5913 int total_auto_space;
5914 int save_flags = target_flags;
5917 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
5918 calc_live_regs (®s_saved, live_regs_mask);
5919 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
5920 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
5921 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5922 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
5924 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
5925 copy_flags = target_flags;
5926 target_flags = save_flags;
5928 total_saved_regs_space = regs_saved + regs_saved_rounding;
5930 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
5931 return total_saved_regs_space + total_auto_space
5932 + current_function_args_info.byref_regs * 8;
5934 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
5935 return total_saved_regs_space + total_auto_space
5936 + current_function_args_info.byref_regs * 8;
5938 /* Initial gap between fp and sp is 0. */
5939 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
5942 if (from == RETURN_ADDRESS_POINTER_REGNUM
5943 && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
5947 int i, n = total_saved_regs_space;
5949 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
5951 n += total_auto_space;
5953 /* If it wasn't saved, there's not much we can do. */
5954 if ((live_regs_mask[pr_reg / 32] & (1 << (pr_reg % 32))) == 0)
5957 target_flags = copy_flags;
5959 /* We loop twice: first, check 8-byte aligned registers,
5960 that are stored in the higher addresses, that are known
5961 to be aligned. Then, check 32-bit registers that don't
5962 need 8-byte alignment. */
5963 for (align = 1; align >= 0; align--)
5964 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
5965 if (live_regs_mask[i/32] & (1 << (i % 32)))
5967 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5969 if (mode == SFmode && (i % 2) == 1
5970 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5971 && (live_regs_mask[(i ^ 1) / 32]
5972 & (1 << ((i ^ 1) % 32))))
5978 /* If we're doing the aligned pass and this is not aligned,
5979 or we're doing the unaligned pass and this is aligned,
5981 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
5985 n -= GET_MODE_SIZE (mode);
5989 target_flags = save_flags;
5997 return total_auto_space;
6003 /* Handle machine specific pragmas to be semi-compatible with Hitachi
6007 sh_pr_interrupt (pfile)
6008 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
6010 pragma_interrupt = 1;
6015 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
6017 pragma_interrupt = pragma_trapa = 1;
6021 sh_pr_nosave_low_regs (pfile)
6022 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
6024 pragma_nosave_low_regs = 1;
6027 /* Generate 'handle_interrupt' attribute for decls */
6030 sh_insert_attributes (node, attributes)
6034 if (! pragma_interrupt
6035 || TREE_CODE (node) != FUNCTION_DECL)
6038 /* We are only interested in fields. */
6039 if (TREE_CODE_CLASS (TREE_CODE (node)) != 'd')
6042 /* Add a 'handle_interrupt' attribute. */
6043 * attributes = tree_cons (get_identifier ("interrupt_handler"), NULL, * attributes);
6048 /* Supported attributes:
6050 interrupt_handler -- specifies this function is an interrupt handler.
6052 sp_switch -- specifies an alternate stack for an interrupt handler
6055 trap_exit -- use a trapa to exit an interrupt function instead of
6056 an rte instruction. */
6058 const struct attribute_spec sh_attribute_table[] =
6060 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6061 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
6062 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
6063 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
6064 { NULL, 0, 0, false, false, false, NULL }
6067 /* Handle an "interrupt_handler" attribute; arguments as in
6068 struct attribute_spec.handler. */
6070 sh_handle_interrupt_handler_attribute (node, name, args, flags, no_add_attrs)
6073 tree args ATTRIBUTE_UNUSED;
6074 int flags ATTRIBUTE_UNUSED;
6077 if (TREE_CODE (*node) != FUNCTION_DECL)
6079 warning ("`%s' attribute only applies to functions",
6080 IDENTIFIER_POINTER (name));
6081 *no_add_attrs = true;
6083 else if (TARGET_SHCOMPACT)
6085 error ("attribute interrupt_handler is not compatible with -m5-compact");
6086 *no_add_attrs = true;
6092 /* Handle an "sp_switch" attribute; arguments as in
6093 struct attribute_spec.handler. */
6095 sh_handle_sp_switch_attribute (node, name, args, flags, no_add_attrs)
6099 int flags ATTRIBUTE_UNUSED;
6102 if (TREE_CODE (*node) != FUNCTION_DECL)
6104 warning ("`%s' attribute only applies to functions",
6105 IDENTIFIER_POINTER (name));
6106 *no_add_attrs = true;
6108 else if (!pragma_interrupt)
6110 /* The sp_switch attribute only has meaning for interrupt functions. */
6111 warning ("`%s' attribute only applies to interrupt functions",
6112 IDENTIFIER_POINTER (name));
6113 *no_add_attrs = true;
6115 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
6117 /* The argument must be a constant string. */
6118 warning ("`%s' attribute argument not a string constant",
6119 IDENTIFIER_POINTER (name));
6120 *no_add_attrs = true;
6124 sp_switch = gen_rtx_SYMBOL_REF (VOIDmode,
6125 TREE_STRING_POINTER (TREE_VALUE (args)));
6131 /* Handle an "trap_exit" attribute; arguments as in
6132 struct attribute_spec.handler. */
6134 sh_handle_trap_exit_attribute (node, name, args, flags, no_add_attrs)
6138 int flags ATTRIBUTE_UNUSED;
6141 if (TREE_CODE (*node) != FUNCTION_DECL)
6143 warning ("`%s' attribute only applies to functions",
6144 IDENTIFIER_POINTER (name));
6145 *no_add_attrs = true;
6147 else if (!pragma_interrupt)
6149 /* The trap_exit attribute only has meaning for interrupt functions. */
6150 warning ("`%s' attribute only applies to interrupt functions",
6151 IDENTIFIER_POINTER (name));
6152 *no_add_attrs = true;
6154 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
6156 /* The argument must be a constant integer. */
6157 warning ("`%s' attribute argument not an integer constant",
6158 IDENTIFIER_POINTER (name));
6159 *no_add_attrs = true;
6163 trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args));
6170 sh_cfun_interrupt_handler_p ()
6172 return (lookup_attribute ("interrupt_handler",
6173 DECL_ATTRIBUTES (current_function_decl))
6177 /* Predicates used by the templates. */
6179 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
6180 Used only in general_movsrc_operand. */
6183 system_reg_operand (op, mode)
6185 enum machine_mode mode ATTRIBUTE_UNUSED;
6197 /* Returns 1 if OP can be source of a simple move operation.
6198 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
6199 invalid as are subregs of system registers. */
6202 general_movsrc_operand (op, mode)
6204 enum machine_mode mode;
6206 if (GET_CODE (op) == MEM)
6208 rtx inside = XEXP (op, 0);
6209 if (GET_CODE (inside) == CONST)
6210 inside = XEXP (inside, 0);
6212 if (GET_CODE (inside) == LABEL_REF)
6215 if (GET_CODE (inside) == PLUS
6216 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
6217 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
6220 /* Only post inc allowed. */
6221 if (GET_CODE (inside) == PRE_DEC)
6225 if ((mode == QImode || mode == HImode)
6226 && (GET_CODE (op) == SUBREG
6227 && GET_CODE (XEXP (op, 0)) == REG
6228 && system_reg_operand (XEXP (op, 0), mode)))
6231 return general_operand (op, mode);
6234 /* Returns 1 if OP can be a destination of a move.
6235 Same as general_operand, but no preinc allowed. */
6238 general_movdst_operand (op, mode)
6240 enum machine_mode mode;
6242 /* Only pre dec allowed. */
6243 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
6246 return general_operand (op, mode);
6249 /* Returns 1 if OP is a normal arithmetic register. */
6252 arith_reg_operand (op, mode)
6254 enum machine_mode mode;
6256 if (register_operand (op, mode))
6260 if (GET_CODE (op) == REG)
6262 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
6263 regno = REGNO (SUBREG_REG (op));
6267 return (regno != T_REG && regno != PR_REG
6268 && ! TARGET_REGISTER_P (regno)
6269 && (regno != FPUL_REG || TARGET_SH4)
6270 && regno != MACH_REG && regno != MACL_REG);
6275 /* Like above, but for DImode destinations: forbid paradoxical DImode subregs,
6276 because this would lead to missing sign extensions when truncating from
6277 DImode to SImode. */
6279 arith_reg_dest (op, mode)
6281 enum machine_mode mode;
6283 if (mode == DImode && GET_CODE (op) == SUBREG
6284 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
6286 return arith_reg_operand (op, mode);
6290 int_gpr_dest (op, mode)
6292 enum machine_mode mode ATTRIBUTE_UNUSED;
6294 enum machine_mode op_mode = GET_MODE (op);
6296 if (GET_MODE_CLASS (op_mode) != MODE_INT
6297 || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
6299 if (! reload_completed)
6301 return true_regnum (op) <= LAST_GENERAL_REG;
6305 fp_arith_reg_operand (op, mode)
6307 enum machine_mode mode;
6309 if (register_operand (op, mode))
6313 if (GET_CODE (op) == REG)
6315 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
6316 regno = REGNO (SUBREG_REG (op));
6320 return (regno >= FIRST_PSEUDO_REGISTER
6321 || FP_REGISTER_P (regno));
6326 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
6329 arith_operand (op, mode)
6331 enum machine_mode mode;
6333 if (arith_reg_operand (op, mode))
6338 /* FIXME: We should be checking whether the CONST_INT fits in a
6339 CONST_OK_FOR_J here, but this causes reload_cse to crash when
6340 attempting to transform a sequence of two 64-bit sets of the
6341 same register from literal constants into a set and an add,
6342 when the difference is too wide for an add. */
6343 if (GET_CODE (op) == CONST_INT
6344 || EXTRA_CONSTRAINT_S (op))
6349 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
6355 /* Returns 1 if OP is a valid source operand for a compare insn. */
6358 arith_reg_or_0_operand (op, mode)
6360 enum machine_mode mode;
6362 if (arith_reg_operand (op, mode))
6365 if (EXTRA_CONSTRAINT_U (op))
6371 /* Return 1 if OP is a valid source operand for an SHmedia operation
6372 that takes either a register or a 6-bit immediate. */
6375 shmedia_6bit_operand (op, mode)
6377 enum machine_mode mode;
6379 return (arith_reg_operand (op, mode)
6380 || (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op))));
6383 /* Returns 1 if OP is a valid source operand for a logical operation. */
6386 logical_operand (op, mode)
6388 enum machine_mode mode;
6390 if (arith_reg_operand (op, mode))
6395 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_P (INTVAL (op)))
6400 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
6407 and_operand (op, mode)
6409 enum machine_mode mode;
6411 if (logical_operand (op, mode))
6414 /* Check mshflo.l / mshflhi.l opportunities. */
6417 && GET_CODE (op) == CONST_INT
6418 && (INTVAL (op) == (unsigned) 0xffffffff
6419 || INTVAL (op) == (HOST_WIDE_INT) -1 << 32))
6425 /* Nonzero if OP is a floating point value with value 0.0. */
6428 fp_zero_operand (op)
6433 if (GET_MODE (op) != SFmode)
6436 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
6437 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
6440 /* Nonzero if OP is a floating point value with value 1.0. */
6448 if (GET_MODE (op) != SFmode)
6451 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
6452 return REAL_VALUES_EQUAL (r, dconst1);
6455 /* For -m4 and -m4-single-only, mode switching is used. If we are
6456 compiling without -mfmovd, movsf_ie isn't taken into account for
6457 mode switching. We could check in machine_dependent_reorg for
6458 cases where we know we are in single precision mode, but there is
6459 interface to find that out during reload, so we must avoid
6460 choosing an fldi alternative during reload and thus failing to
6461 allocate a scratch register for the constant loading. */
6465 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
6469 tertiary_reload_operand (op, mode)
6471 enum machine_mode mode ATTRIBUTE_UNUSED;
6473 enum rtx_code code = GET_CODE (op);
6474 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
6478 fpscr_operand (op, mode)
6480 enum machine_mode mode ATTRIBUTE_UNUSED;
6482 return (GET_CODE (op) == REG && REGNO (op) == FPSCR_REG
6483 && GET_MODE (op) == PSImode);
6487 fpul_operand (op, mode)
6489 enum machine_mode mode;
6492 return fp_arith_reg_operand (op, mode);
6494 return (GET_CODE (op) == REG
6495 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
6496 && GET_MODE (op) == mode);
6500 symbol_ref_operand (op, mode)
6502 enum machine_mode mode ATTRIBUTE_UNUSED;
6504 return (GET_CODE (op) == SYMBOL_REF);
6507 /* Return the TLS type for TLS symbols, 0 for otherwise. */
6509 tls_symbolic_operand (op, mode)
6511 enum machine_mode mode ATTRIBUTE_UNUSED;
6515 if (GET_CODE (op) != SYMBOL_REF)
6519 STRIP_DATALABEL_ENCODING(str, str);
6520 if (! TLS_SYMNAME_P (str))
6526 return TLS_MODEL_GLOBAL_DYNAMIC;
6528 return TLS_MODEL_LOCAL_DYNAMIC;
6530 return TLS_MODEL_INITIAL_EXEC;
6532 return TLS_MODEL_LOCAL_EXEC;
6538 commutative_float_operator (op, mode)
6540 enum machine_mode mode;
6542 if (GET_MODE (op) != mode)
6544 switch (GET_CODE (op))
6556 noncommutative_float_operator (op, mode)
6558 enum machine_mode mode;
6560 if (GET_MODE (op) != mode)
6562 switch (GET_CODE (op))
6574 unary_float_operator (op, mode)
6576 enum machine_mode mode;
6578 if (GET_MODE (op) != mode)
6580 switch (GET_CODE (op))
6593 binary_float_operator (op, mode)
6595 enum machine_mode mode;
6597 if (GET_MODE (op) != mode)
6599 switch (GET_CODE (op))
6613 binary_logical_operator (op, mode)
6615 enum machine_mode mode;
6617 if (GET_MODE (op) != mode)
6619 switch (GET_CODE (op))
6632 equality_comparison_operator (op, mode)
6634 enum machine_mode mode;
6636 return ((mode == VOIDmode || GET_MODE (op) == mode)
6637 && (GET_CODE (op) == EQ || GET_CODE (op) == NE));
6640 int greater_comparison_operator (op, mode)
6642 enum machine_mode mode;
6644 if (mode != VOIDmode && GET_MODE (op) == mode)
6646 switch (GET_CODE (op))
6658 int less_comparison_operator (op, mode)
6660 enum machine_mode mode;
6662 if (mode != VOIDmode && GET_MODE (op) == mode)
6664 switch (GET_CODE (op))
6676 /* Accept pseudos and branch target registers. */
6678 target_reg_operand (op, mode)
6680 enum machine_mode mode;
6683 || GET_MODE (op) != DImode)
6686 if (GET_CODE (op) == SUBREG)
6689 if (GET_CODE (op) != REG)
6692 /* We must protect ourselves from matching pseudos that are virtual
6693 register, because they will eventually be replaced with hardware
6694 registers that aren't branch-target registers. */
6695 if (REGNO (op) > LAST_VIRTUAL_REGISTER
6696 || TARGET_REGISTER_P (REGNO (op)))
6702 /* Same as target_reg_operand, except that label_refs and symbol_refs
6703 are accepted before reload. */
6705 target_operand (op, mode)
6707 enum machine_mode mode;
6712 if ((GET_MODE (op) == DImode || GET_MODE (op) == VOIDmode)
6713 && EXTRA_CONSTRAINT_T (op))
6714 return ! reload_completed;
6716 return target_reg_operand (op, mode);
6720 mextr_bit_offset (op, mode)
6722 enum machine_mode mode ATTRIBUTE_UNUSED;
6726 if (GET_CODE (op) != CONST_INT)
6729 return i >= 1*8 && i <= 7*8 && (i & 7) == 0;
6733 extend_reg_operand (op, mode)
6735 enum machine_mode mode;
6737 return (GET_CODE (op) == TRUNCATE
6739 : arith_reg_operand) (op, mode);
6743 trunc_hi_operand (op, mode)
6745 enum machine_mode mode;
6747 enum machine_mode op_mode = GET_MODE (op);
6749 if (op_mode != SImode && op_mode != DImode
6750 && op_mode != V4HImode && op_mode != V2SImode)
6752 return extend_reg_operand (op, mode);
6756 extend_reg_or_0_operand (op, mode)
6758 enum machine_mode mode;
6760 return (GET_CODE (op) == TRUNCATE
6762 : arith_reg_or_0_operand) (op, mode);
6766 general_extend_operand (op, mode)
6768 enum machine_mode mode;
6770 return (GET_CODE (op) == TRUNCATE
6772 : nonimmediate_operand) (op, mode);
6776 inqhi_operand (op, mode)
6778 enum machine_mode mode;
6780 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
6783 /* Can't use true_regnum here because copy_cost wants to know about
6784 SECONDARY_INPUT_RELOAD_CLASS. */
6785 return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op));
6789 sh_rep_vec (v, mode)
6791 enum machine_mode mode;
6796 if ((GET_CODE (v) != CONST_VECTOR && GET_CODE (v) != PARALLEL)
6797 || (GET_MODE (v) != mode && mode != VOIDmode))
6799 i = XVECLEN (v, 0) - 2;
6800 x = XVECEXP (v, 0, i + 1);
6801 if (GET_MODE_UNIT_SIZE (mode) == 1)
6803 y = XVECEXP (v, 0, i);
6804 for (i -= 2 ; i >= 0; i -= 2)
6805 if (! rtx_equal_p (XVECEXP (v, 0, i + 1), x)
6806 || ! rtx_equal_p (XVECEXP (v, 0, i), y))
6811 if (XVECEXP (v, 0, i) != x)
6816 /* Determine if V is a constant vector matching MODE with only one element
6817 that is not a sign extension. Two byte-sized elements count as one. */
6819 sh_1el_vec (v, mode)
6821 enum machine_mode mode;
6824 int i, last, least, sign_ix;
6827 if (GET_CODE (v) != CONST_VECTOR
6828 || (GET_MODE (v) != mode && mode != VOIDmode))
6830 /* Determine numbers of last and of least significant elements. */
6831 last = XVECLEN (v, 0) - 1;
6832 least = TARGET_LITTLE_ENDIAN ? 0 : last;
6833 if (GET_CODE (XVECEXP (v, 0, least)) != CONST_INT)
6836 if (GET_MODE_UNIT_SIZE (mode) == 1)
6837 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
6838 if (GET_CODE (XVECEXP (v, 0, sign_ix)) != CONST_INT)
6840 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (v));
6841 sign = (INTVAL (XVECEXP (v, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
6842 ? constm1_rtx : const0_rtx);
6843 i = XVECLEN (v, 0) - 1;
6845 if (i != least && i != sign_ix && XVECEXP (v, 0, i) != sign)
6852 sh_const_vec (v, mode)
6854 enum machine_mode mode;
6858 if (GET_CODE (v) != CONST_VECTOR
6859 || (GET_MODE (v) != mode && mode != VOIDmode))
6861 i = XVECLEN (v, 0) - 1;
6863 if (GET_CODE (XVECEXP (v, 0, i)) != CONST_INT)
6868 /* Return the destination address of a branch. */
6871 branch_dest (branch)
6874 rtx dest = SET_SRC (PATTERN (branch));
6877 if (GET_CODE (dest) == IF_THEN_ELSE)
6878 dest = XEXP (dest, 1);
6879 dest = XEXP (dest, 0);
6880 dest_uid = INSN_UID (dest);
6881 return INSN_ADDRESSES (dest_uid);
6884 /* Return nonzero if REG is not used after INSN.
6885 We assume REG is a reload reg, and therefore does
6886 not live past labels. It may live past calls or jumps though. */
6888 reg_unused_after (reg, insn)
6895 /* If the reg is set by this instruction, then it is safe for our
6896 case. Disregard the case where this is a store to memory, since
6897 we are checking a register used in the store address. */
6898 set = single_set (insn);
6899 if (set && GET_CODE (SET_DEST (set)) != MEM
6900 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6903 while ((insn = NEXT_INSN (insn)))
6905 code = GET_CODE (insn);
6908 /* If this is a label that existed before reload, then the register
6909 if dead here. However, if this is a label added by reorg, then
6910 the register may still be live here. We can't tell the difference,
6911 so we just ignore labels completely. */
6912 if (code == CODE_LABEL)
6917 if (code == JUMP_INSN)
6920 /* If this is a sequence, we must handle them all at once.
6921 We could have for instance a call that sets the target register,
6922 and an insn in a delay slot that uses the register. In this case,
6923 we must return 0. */
6924 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
6929 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
6931 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
6932 rtx set = single_set (this_insn);
6934 if (GET_CODE (this_insn) == CALL_INSN)
6936 else if (GET_CODE (this_insn) == JUMP_INSN)
6938 if (INSN_ANNULLED_BRANCH_P (this_insn))
6943 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
6945 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6947 if (GET_CODE (SET_DEST (set)) != MEM)
6953 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
6958 else if (code == JUMP_INSN)
6961 else if (GET_RTX_CLASS (code) == 'i')
6963 rtx set = single_set (insn);
6965 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
6967 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6968 return GET_CODE (SET_DEST (set)) != MEM;
6969 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
6973 if (code == CALL_INSN && call_used_regs[REGNO (reg)])
6981 static GTY(()) rtx fpscr_rtx;
6987 fpscr_rtx = gen_rtx (REG, PSImode, FPSCR_REG);
6988 REG_USERVAR_P (fpscr_rtx) = 1;
6989 mark_user_reg (fpscr_rtx);
6991 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
6992 mark_user_reg (fpscr_rtx);
7011 expand_sf_unop (fun, operands)
7012 rtx (*fun) PARAMS ((rtx, rtx, rtx));
7015 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
7019 expand_sf_binop (fun, operands)
7020 rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx));
7023 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
7028 expand_df_unop (fun, operands)
7029 rtx (*fun) PARAMS ((rtx, rtx, rtx));
7032 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
7036 expand_df_binop (fun, operands)
7037 rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx));
7040 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
7044 /* ??? gcc does flow analysis strictly after common subexpression
7045 elimination. As a result, common subexpression elimination fails
7046 when there are some intervening statements setting the same register.
7047 If we did nothing about this, this would hurt the precision switching
7048 for SH4 badly. There is some cse after reload, but it is unable to
7049 undo the extra register pressure from the unused instructions, and
7050 it cannot remove auto-increment loads.
7052 A C code example that shows this flow/cse weakness for (at least) SH
7053 and sparc (as of gcc ss-970706) is this:
7067 So we add another pass before common subexpression elimination, to
7068 remove assignments that are dead due to a following assignment in the
7069 same basic block. */
7072 mark_use (x, reg_set_block)
7073 rtx x, *reg_set_block;
7079 code = GET_CODE (x);
7084 int regno = REGNO (x);
7085 int nregs = (regno < FIRST_PSEUDO_REGISTER
7086 ? HARD_REGNO_NREGS (regno, GET_MODE (x))
7090 reg_set_block[regno + nregs - 1] = 0;
7097 rtx dest = SET_DEST (x);
7099 if (GET_CODE (dest) == SUBREG)
7100 dest = SUBREG_REG (dest);
7101 if (GET_CODE (dest) != REG)
7102 mark_use (dest, reg_set_block);
7103 mark_use (SET_SRC (x), reg_set_block);
7110 const char *fmt = GET_RTX_FORMAT (code);
7112 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7115 mark_use (XEXP (x, i), reg_set_block);
7116 else if (fmt[i] == 'E')
7117 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7118 mark_use (XVECEXP (x, i, j), reg_set_block);
7125 static rtx get_free_reg PARAMS ((HARD_REG_SET));
7127 /* This function returns a register to use to load the address to load
7128 the fpscr from. Currently it always returns r1 or r7, but when we are
7129 able to use pseudo registers after combine, or have a better mechanism
7130 for choosing a register, it should be done here. */
7131 /* REGS_LIVE is the liveness information for the point for which we
7132 need this allocation. In some bare-bones exit blocks, r1 is live at the
7133 start. We can even have all of r0..r3 being live:
7134 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
7135 INSN before which new insns are placed with will clobber the register
7136 we return. If a basic block consists only of setting the return value
7137 register to a pseudo and using that register, the return value is not
7138 live before or after this block, yet we we'll insert our insns right in
7142 get_free_reg (regs_live)
7143 HARD_REG_SET regs_live;
7145 if (! TEST_HARD_REG_BIT (regs_live, 1))
7146 return gen_rtx_REG (Pmode, 1);
7148 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
7149 there shouldn't be anything but a jump before the function end. */
7150 if (! TEST_HARD_REG_BIT (regs_live, 7))
7151 return gen_rtx_REG (Pmode, 7);
7156 /* This function will set the fpscr from memory.
7157 MODE is the mode we are setting it to. */
7159 fpscr_set_from_mem (mode, regs_live)
7161 HARD_REG_SET regs_live;
7163 enum attr_fp_mode fp_mode = mode;
7164 rtx addr_reg = get_free_reg (regs_live);
7166 if (fp_mode == (enum attr_fp_mode) NORMAL_MODE (FP_MODE))
7167 emit_insn (gen_fpu_switch1 (addr_reg));
7169 emit_insn (gen_fpu_switch0 (addr_reg));
7172 /* Is the given character a logical line separator for the assembler? */
7173 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
7174 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
7178 sh_insn_length_adjustment (insn)
7181 /* Instructions with unfilled delay slots take up an extra two bytes for
7182 the nop in the delay slot. */
7183 if (((GET_CODE (insn) == INSN
7184 && GET_CODE (PATTERN (insn)) != USE
7185 && GET_CODE (PATTERN (insn)) != CLOBBER)
7186 || GET_CODE (insn) == CALL_INSN
7187 || (GET_CODE (insn) == JUMP_INSN
7188 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
7189 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
7190 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
7191 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
7194 /* SH2e has a bug that prevents the use of annulled branches, so if
7195 the delay slot is not filled, we'll have to put a NOP in it. */
7196 if (sh_cpu == CPU_SH2E
7197 && GET_CODE (insn) == JUMP_INSN
7198 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
7199 && GET_CODE (PATTERN (insn)) != ADDR_VEC
7200 && get_attr_type (insn) == TYPE_CBRANCH
7201 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
7204 /* sh-dsp parallel processing insn take four bytes instead of two. */
7206 if (GET_CODE (insn) == INSN)
7209 rtx body = PATTERN (insn);
7210 const char *template;
7212 int maybe_label = 1;
7214 if (GET_CODE (body) == ASM_INPUT)
7215 template = XSTR (body, 0);
7216 else if (asm_noperands (body) >= 0)
7218 = decode_asm_operands (body, NULL, NULL, NULL, NULL);
7227 while (c == ' ' || c == '\t');
7228 /* all sh-dsp parallel-processing insns start with p.
7229 The only non-ppi sh insn starting with p is pref.
7230 The only ppi starting with pr is prnd. */
7231 if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2))
7233 /* The repeat pseudo-insn expands two three insns, a total of
7234 six bytes in size. */
7235 else if ((c == 'r' || c == 'R')
7236 && ! strncasecmp ("epeat", template, 5))
7238 while (c && c != '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c))
7240 /* If this is a label, it is obviously not a ppi insn. */
7241 if (c == ':' && maybe_label)
7246 else if (c == '\'' || c == '"')
7251 maybe_label = c != ':';
7259 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
7260 isn't protected by a PIC unspec. */
7262 nonpic_symbol_mentioned_p (x)
7265 register const char *fmt;
7268 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
7269 || GET_CODE (x) == PC)
7272 /* We don't want to look into the possible MEM location of a
7273 CONST_DOUBLE, since we're not going to use it, in general. */
7274 if (GET_CODE (x) == CONST_DOUBLE)
7277 if (GET_CODE (x) == UNSPEC
7278 && (XINT (x, 1) == UNSPEC_PIC
7279 || XINT (x, 1) == UNSPEC_GOT
7280 || XINT (x, 1) == UNSPEC_GOTOFF
7281 || XINT (x, 1) == UNSPEC_GOTPLT
7282 || XINT (x, 1) == UNSPEC_GOTTPOFF
7283 || XINT (x, 1) == UNSPEC_DTPOFF
7284 || XINT (x, 1) == UNSPEC_PLT))
7287 fmt = GET_RTX_FORMAT (GET_CODE (x));
7288 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
7294 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7295 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
7298 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
7305 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
7306 @GOTOFF in `reg'. */
7308 legitimize_pic_address (orig, mode, reg)
7310 enum machine_mode mode ATTRIBUTE_UNUSED;
7313 if (tls_symbolic_operand (orig, Pmode))
7316 if (GET_CODE (orig) == LABEL_REF
7317 || (GET_CODE (orig) == SYMBOL_REF
7318 && (CONSTANT_POOL_ADDRESS_P (orig)
7319 /* SYMBOL_REF_FLAG is set on static symbols. */
7320 || SYMBOL_REF_FLAG (orig))))
7323 reg = gen_reg_rtx (Pmode);
7325 emit_insn (gen_symGOTOFF2reg (reg, orig));
7328 else if (GET_CODE (orig) == SYMBOL_REF)
7331 reg = gen_reg_rtx (Pmode);
7333 emit_insn (gen_symGOT2reg (reg, orig));
7339 /* Mark the use of a constant in the literal table. If the constant
7340 has multiple labels, make it unique. */
7342 mark_constant_pool_use (x)
7345 rtx insn, lab, pattern;
7350 switch (GET_CODE (x))
7360 /* Get the first label in the list of labels for the same constant
7361 and delete another labels in the list. */
7363 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
7365 if (GET_CODE (insn) != CODE_LABEL
7366 || LABEL_REFS (insn) != NEXT_INSN (insn))
7371 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
7372 INSN_DELETED_P (insn) = 1;
7374 /* Mark constants in a window. */
7375 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
7377 if (GET_CODE (insn) != INSN)
7380 pattern = PATTERN (insn);
7381 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
7384 switch (XINT (pattern, 1))
7386 case UNSPECV_CONST2:
7387 case UNSPECV_CONST4:
7388 case UNSPECV_CONST8:
7389 XVECEXP (pattern, 0, 1) = const1_rtx;
7391 case UNSPECV_WINDOW_END:
7392 if (XVECEXP (pattern, 0, 0) == x)
7395 case UNSPECV_CONST_END:
7405 /* Return true if it's possible to redirect BRANCH1 to the destination
7406 of an unconditional jump BRANCH2. We only want to do this if the
7407 resulting branch will have a short displacement. */
7409 sh_can_redirect_branch (branch1, branch2)
7413 if (flag_expensive_optimizations && simplejump_p (branch2))
7415 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
7419 for (distance = 0, insn = NEXT_INSN (branch1);
7420 insn && distance < 256;
7421 insn = PREV_INSN (insn))
7426 distance += get_attr_length (insn);
7428 for (distance = 0, insn = NEXT_INSN (branch1);
7429 insn && distance < 256;
7430 insn = NEXT_INSN (insn))
7435 distance += get_attr_length (insn);
7441 /* Return nonzero if register old_reg can be renamed to register new_reg. */
7443 sh_hard_regno_rename_ok (old_reg, new_reg)
7444 unsigned int old_reg ATTRIBUTE_UNUSED;
7445 unsigned int new_reg;
7448 /* Interrupt functions can only use registers that have already been
7449 saved by the prologue, even if they would normally be
7452 if (sh_cfun_interrupt_handler_p () && !regs_ever_live[new_reg])
7458 /* Function to update the integer COST
7459 based on the relationship between INSN that is dependent on
7460 DEP_INSN through the dependence LINK. The default is to make no
7461 adjustment to COST. This can be used for example to specify to
7462 the scheduler that an output- or anti-dependence does not incur
7463 the same cost as a data-dependence. The return value should be
7464 the new value for COST. */
7466 sh_adjust_cost (insn, link, dep_insn, cost)
7468 rtx link ATTRIBUTE_UNUSED;
7476 /* On SHmedia, if the dependence is an anti-dependence or
7477 output-dependence, there is no cost. */
7478 if (REG_NOTE_KIND (link) != 0)
7481 if (get_attr_is_mac_media (insn)
7482 && get_attr_is_mac_media (dep_insn))
7485 else if (REG_NOTE_KIND (link) == 0)
7487 enum attr_type dep_type, type;
7489 if (recog_memoized (insn) < 0
7490 || recog_memoized (dep_insn) < 0)
7493 dep_type = get_attr_type (dep_insn);
7494 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
7496 if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
7497 && (type = get_attr_type (insn)) != TYPE_CALL
7498 && type != TYPE_SFUNC)
7501 /* The only input for a call that is timing-critical is the
7502 function's address. */
7503 if (GET_CODE(insn) == CALL_INSN)
7505 rtx call = PATTERN (insn);
7507 if (GET_CODE (call) == PARALLEL)
7508 call = XVECEXP (call, 0 ,0);
7509 if (GET_CODE (call) == SET)
7510 call = SET_SRC (call);
7511 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
7512 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))
7515 /* Likewise, the most timing critical input for an sfuncs call
7516 is the function address. However, sfuncs typically start
7517 using their arguments pretty quickly.
7518 Assume a four cycle delay before they are needed. */
7519 /* All sfunc calls are parallels with at least four components.
7520 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
7521 else if (GET_CODE (PATTERN (insn)) == PARALLEL
7522 && XVECLEN (PATTERN (insn), 0) >= 4
7523 && (reg = sfunc_uses_reg (insn)))
7525 if (! reg_set_p (reg, dep_insn))
7528 /* When the preceding instruction loads the shift amount of
7529 the following SHAD/SHLD, the latency of the load is increased
7532 && get_attr_type (insn) == TYPE_DYN_SHIFT
7533 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
7534 && reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
7535 XEXP (SET_SRC (single_set(insn)),
7538 /* When an LS group instruction with a latency of less than
7539 3 cycles is followed by a double-precision floating-point
7540 instruction, FIPR, or FTRV, the latency of the first
7541 instruction is increased to 3 cycles. */
7543 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
7544 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
7546 /* The lsw register of a double-precision computation is ready one
7548 else if (reload_completed
7549 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
7550 && (use_pat = single_set (insn))
7551 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
7555 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
7556 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
7559 /* An anti-dependence penalty of two applies if the first insn is a double
7560 precision fadd / fsub / fmul. */
7561 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI
7562 && recog_memoized (dep_insn) >= 0
7563 && get_attr_type (dep_insn) == TYPE_DFP_ARITH
7564 /* A lot of alleged anti-flow dependences are fake,
7565 so check this one is real. */
7566 && flow_dependent_p (dep_insn, insn))
7573 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
7574 if DEP_INSN is anti-flow dependent on INSN. */
7576 flow_dependent_p (insn, dep_insn)
7579 rtx tmp = PATTERN (insn);
7581 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
7582 return tmp == NULL_RTX;
7585 /* A helper function for flow_dependent_p called through note_stores. */
7587 flow_dependent_p_1 (x, pat, data)
7589 rtx pat ATTRIBUTE_UNUSED;
7592 rtx * pinsn = (rtx *) data;
7594 if (*pinsn && reg_referenced_p (x, *pinsn))
7598 /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
7599 'special function' patterns (type sfunc) that clobber pr, but that
7600 do not look like function calls to leaf_function_p. Hence we must
7601 do this extra check. */
7605 return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
7608 /* This Function returns nonzero if the DFA based scheduler interface
7609 is to be used. At present this is supported for the SH4 only. */
7611 sh_use_dfa_interface()
7613 if (TARGET_HARD_SH4)
7619 /* This function returns "2" to indicate dual issue for the SH4
7620 processor. To be used by the DFA pipeline description. */
7624 if (TARGET_SUPERSCALAR)
7630 /* SHmedia requires registers for branches, so we can't generate new
7631 branches past reload. */
7633 sh_cannot_modify_jumps_p ()
7635 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
7639 sh_ms_bitfield_layout_p (record_type)
7640 tree record_type ATTRIBUTE_UNUSED;
7645 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
7646 may access it using GOTOFF instead of GOT. */
7649 sh_encode_section_info (decl, first)
7656 rtl = DECL_RTL (decl);
7658 rtl = TREE_CST_RTL (decl);
7659 if (GET_CODE (rtl) != MEM)
7661 symbol = XEXP (rtl, 0);
7662 if (GET_CODE (symbol) != SYMBOL_REF)
7666 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
7668 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL (decl))
7670 const char *symbol_str, *orig_str;
7672 enum tls_model kind;
7677 orig_str = XSTR (symbol, 0);
7678 is_local = (*targetm.binds_local_p) (decl);
7683 kind = TLS_MODEL_LOCAL_EXEC;
7685 kind = TLS_MODEL_INITIAL_EXEC;
7688 kind = TLS_MODEL_LOCAL_DYNAMIC;
7690 kind = TLS_MODEL_GLOBAL_DYNAMIC;
7691 if (kind < flag_tls_default)
7692 kind = flag_tls_default;
7694 STRIP_DATALABEL_ENCODING (symbol_str, orig_str);
7695 dlen = symbol_str - orig_str;
7697 encoding = " GLil"[kind];
7698 if (TLS_SYMNAME_P (symbol_str))
7700 if (encoding == symbol_str[1])
7702 /* Handle the changes from initial-exec to local-exec and
7703 from global-dynamic to local-dynamic. */
7704 if ((encoding == 'l' && symbol_str[1] == 'i')
7705 || (encoding == 'L' && symbol_str[1] == 'G'))
7711 len = strlen (symbol_str);
7712 newstr = alloca (dlen + len + 3);
7714 memcpy (newstr, orig_str, dlen);
7715 newstr[dlen + 0] = SH_TLS_ENCODING[0];
7716 newstr[dlen + 1] = encoding;
7717 memcpy (newstr + dlen + 2, symbol_str, len + 1);
7719 XSTR (symbol, 0) = ggc_alloc_string (newstr, dlen + len + 2);
7722 if (TARGET_SH5 && first && TREE_CODE (decl) != FUNCTION_DECL)
7723 XEXP (rtl, 0) = gen_datalabel_ref (symbol);
7726 /* Undo the effects of the above. */
7729 sh_strip_name_encoding (str)
7732 STRIP_DATALABEL_ENCODING (str, str);
7733 STRIP_TLS_ENCODING (str, str);
7740 On the SH1..SH4, the trampoline looks like
7741 2 0002 D202 mov.l l2,r2
7742 1 0000 D301 mov.l l1,r3
7745 5 0008 00000000 l1: .long area
7746 6 000c 00000000 l2: .long function
7748 SH5 (compact) uses r1 instead of r3 for the static chain. */
7751 /* Emit RTL insns to initialize the variable parts of a trampoline.
7752 FNADDR is an RTX for the address of the function's pure code.
7753 CXT is an RTX for the static chain value for the function. */
7756 sh_initialize_trampoline (tramp, fnaddr, cxt)
7757 rtx tramp, fnaddr, cxt;
7759 if (TARGET_SHMEDIA64)
7764 rtx movi1 = GEN_INT (0xcc000010);
7765 rtx shori1 = GEN_INT (0xc8000010);
7768 /* The following trampoline works within a +- 128 KB range for cxt:
7769 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
7770 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
7771 gettr tr1,r1; blink tr0,r63 */
7772 /* Address rounding makes it hard to compute the exact bounds of the
7773 offset for this trampoline, but we have a rather generous offset
7774 range, so frame_offset should do fine as an upper bound. */
7775 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
7777 /* ??? could optimize this trampoline initialization
7778 by writing DImode words with two insns each. */
7779 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
7780 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
7781 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
7782 insn = gen_rtx_AND (DImode, insn, mask);
7783 /* Or in ptb/u .,tr1 pattern */
7784 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
7785 insn = force_operand (insn, NULL_RTX);
7786 insn = gen_lowpart (SImode, insn);
7787 emit_move_insn (gen_rtx_MEM (SImode, tramp), insn);
7788 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
7789 insn = gen_rtx_AND (DImode, insn, mask);
7790 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
7791 insn = gen_lowpart (SImode, insn);
7792 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), insn);
7793 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
7794 insn = gen_rtx_AND (DImode, insn, mask);
7795 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
7796 insn = gen_lowpart (SImode, insn);
7797 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), insn);
7798 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
7799 insn = gen_rtx_AND (DImode, insn, mask);
7800 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
7801 insn = gen_lowpart (SImode, insn);
7802 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7804 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
7805 insn = gen_rtx_AND (DImode, insn, mask);
7806 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
7807 insn = gen_lowpart (SImode, insn);
7808 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 16)),
7810 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 20)),
7811 GEN_INT (0x6bf10600));
7812 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 24)),
7813 GEN_INT (0x4415fc10));
7814 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 28)),
7815 GEN_INT (0x4401fff0));
7816 emit_insn (gen_ic_invalidate_line (tramp));
7819 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
7820 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
7822 tramp_templ = gen_datalabel_ref (tramp_templ);
7823 dst = gen_rtx_MEM (BLKmode, tramp);
7824 src = gen_rtx_MEM (BLKmode, tramp_templ);
7825 set_mem_align (dst, 256);
7826 set_mem_align (src, 64);
7827 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
7829 emit_move_insn (gen_rtx_MEM (Pmode, plus_constant (tramp, fixed_len)),
7831 emit_move_insn (gen_rtx_MEM (Pmode,
7832 plus_constant (tramp,
7834 + GET_MODE_SIZE (Pmode))),
7836 emit_insn (gen_ic_invalidate_line (tramp));
7839 else if (TARGET_SHMEDIA)
7841 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
7842 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
7843 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
7844 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
7845 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
7846 rotated 10 right, and higher 16 bit of every 32 selected. */
7848 = force_reg (V2HImode, (simplify_gen_subreg
7849 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
7850 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
7851 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
7853 tramp = force_reg (Pmode, tramp);
7854 fnaddr = force_reg (SImode, fnaddr);
7855 cxt = force_reg (SImode, cxt);
7856 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
7857 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
7859 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
7860 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
7861 emit_insn (gen_ashldi3_media (quad0, quad0, GEN_INT (2)));
7862 emit_move_insn (gen_rtx_MEM (DImode, tramp), quad0);
7863 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
7864 gen_rtx_SUBREG (V2HImode, cxt, 0),
7866 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
7867 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
7868 emit_insn (gen_ashldi3_media (cxtload, cxtload, GEN_INT (2)));
7869 if (TARGET_LITTLE_ENDIAN)
7871 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
7872 emit_insn (gen_mextr4 (quad2, cxtload, blink));
7876 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
7877 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
7879 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 8)), quad1);
7880 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), quad2);
7881 emit_insn (gen_ic_invalidate_line (tramp));
7884 else if (TARGET_SHCOMPACT)
7886 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
7889 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7890 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
7892 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7893 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
7895 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7897 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7901 if (TARGET_USERMODE)
7902 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__ic_invalidate"),
7903 0, VOIDmode, 1, tramp, SImode);
7905 emit_insn (gen_ic_invalidate_line (tramp));
7909 /* FIXME: This is overly conservative. A SHcompact function that
7910 receives arguments ``by reference'' will have them stored in its
7911 own stack frame, so it must not pass pointers or references to
7912 these arguments to other functions by means of sibling calls. */
7914 sh_function_ok_for_sibcall (decl, exp)
7916 tree exp ATTRIBUTE_UNUSED;
7919 && (! TARGET_SHCOMPACT
7920 || current_function_args_info.stack_regs == 0));
7923 /* Machine specific built-in functions. */
7925 struct builtin_description
7927 const enum insn_code icode;
7928 const char *const name;
7932 /* describe number and signedness of arguments; arg[0] == result
7933 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
7934 static const char signature_args[][4] =
7936 #define SH_BLTIN_V2SI2 0
7938 #define SH_BLTIN_V4HI2 1
7940 #define SH_BLTIN_V2SI3 2
7942 #define SH_BLTIN_V4HI3 3
7944 #define SH_BLTIN_V8QI3 4
7946 #define SH_BLTIN_MAC_HISI 5
7948 #define SH_BLTIN_SH_HI 6
7950 #define SH_BLTIN_SH_SI 7
7952 #define SH_BLTIN_V4HI2V2SI 8
7954 #define SH_BLTIN_V4HI2V8QI 9
7956 #define SH_BLTIN_SISF 10
7958 #define SH_BLTIN_LDUA_L 11
7960 #define SH_BLTIN_LDUA_Q 12
7962 #define SH_BLTIN_STUA_L 13
7964 #define SH_BLTIN_STUA_Q 14
7966 #define SH_BLTIN_UDI 15
7968 #define SH_BLTIN_NUM_SHARED_SIGNATURES 16
7969 #define SH_BLTIN_2 16
7970 #define SH_BLTIN_SU 16
7972 #define SH_BLTIN_3 17
7973 #define SH_BLTIN_SUS 17
7975 #define SH_BLTIN_PSSV 18
7977 #define SH_BLTIN_XXUU 19
7978 #define SH_BLTIN_UUUU 19
7980 #define SH_BLTIN_PV 20
7983 /* mcmv: operands considered unsigned. */
7984 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
7985 /* mperm: control value considered unsigned int. */
7986 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
7987 /* mshards_q: returns signed short. */
7988 /* nsb: takes long long arg, returns unsigned char. */
7989 static const struct builtin_description bdesc[] =
7991 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
7992 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
7993 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
7994 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
7995 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
7996 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
7997 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
7999 { CODE_FOR_alloco32, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
8000 { CODE_FOR_alloco64, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
8002 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
8003 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
8004 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
8005 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
8006 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
8007 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
8008 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
8009 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
8010 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
8011 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
8012 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_UDI },
8013 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_UDI },
8014 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_UDI },
8015 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_UDI },
8016 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_UDI },
8017 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_UDI },
8018 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_UDI },
8019 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
8020 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
8021 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
8022 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
8023 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
8024 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
8025 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
8026 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
8027 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
8028 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
8029 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
8030 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
8031 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
8032 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
8033 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
8034 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
8035 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
8036 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
8037 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
8038 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
8039 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
8040 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
8041 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
8042 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
8043 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
8044 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
8045 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
8046 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
8047 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
8048 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
8049 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
8050 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
8051 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
8052 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
8053 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
8054 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
8055 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
8057 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
8058 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
8059 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
8060 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
8061 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
8062 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
8063 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
8064 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
8065 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
8066 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
8067 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
8068 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
8069 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
8070 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
8071 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
8072 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
8074 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
8075 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
8077 { CODE_FOR_prefetch32,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
8078 { CODE_FOR_prefetch64,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV }
8083 sh_media_init_builtins ()
8085 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
8086 const struct builtin_description *d;
8088 memset (shared, 0, sizeof shared);
8089 for (d = bdesc; d - bdesc < (int) (sizeof bdesc / sizeof bdesc[0]); d++)
8091 tree type, arg_type;
8092 int signature = d->signature;
8095 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
8096 type = shared[signature];
8099 int has_result = signature_args[signature][0] != 0;
8101 if (signature_args[signature][1] == 8
8102 && (insn_data[d->icode].operand[has_result].mode != Pmode))
8104 if (! TARGET_FPU_ANY
8105 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
8107 type = void_list_node;
8110 int arg = signature_args[signature][i];
8111 int opno = i - 1 + has_result;
8114 arg_type = ptr_type_node;
8116 arg_type = ((*lang_hooks.types.type_for_mode)
8117 (insn_data[d->icode].operand[opno].mode,
8122 arg_type = void_type_node;
8125 type = tree_cons (NULL_TREE, arg_type, type);
8127 type = build_function_type (arg_type, type);
8128 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
8129 shared[signature] = type;
8131 builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
8140 sh_media_init_builtins ();
8143 /* Expand an expression EXP that calls a built-in function,
8144 with result going to TARGET if that's convenient
8145 (and in mode MODE if that's convenient).
8146 SUBTARGET may be used as the target for computing one of EXP's operands.
8147 IGNORE is nonzero if the value is to be ignored. */
8150 sh_expand_builtin (exp, target, subtarget, mode, ignore)
8153 rtx subtarget ATTRIBUTE_UNUSED;
8154 enum machine_mode mode ATTRIBUTE_UNUSED;
8157 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8158 tree arglist = TREE_OPERAND (exp, 1);
8159 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8160 const struct builtin_description *d = &bdesc[fcode];
8161 enum insn_code icode = d->icode;
8162 int signature = d->signature;
8163 enum machine_mode tmode = VOIDmode;
8168 if (signature_args[signature][0])
8173 tmode = insn_data[icode].operand[0].mode;
8175 || GET_MODE (target) != tmode
8176 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8177 target = gen_reg_rtx (tmode);
8183 for (i = 1; i <= 3; i++, nop++)
8186 enum machine_mode opmode, argmode;
8188 if (! signature_args[signature][i])
8190 arg = TREE_VALUE (arglist);
8191 if (arg == error_mark_node)
8193 arglist = TREE_CHAIN (arglist);
8194 opmode = insn_data[icode].operand[nop].mode;
8195 argmode = TYPE_MODE (TREE_TYPE (arg));
8196 if (argmode != opmode)
8197 arg = build1 (NOP_EXPR,
8198 (*lang_hooks.types.type_for_mode) (opmode, 0), arg);
8199 op[nop] = expand_expr (arg, NULL_RTX, opmode, 0);
8200 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
8201 op[nop] = copy_to_mode_reg (opmode, op[nop]);
8207 pat = (*insn_data[d->icode].genfun) (op[0]);
8210 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
8213 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
8216 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
8228 sh_expand_unop_v2sf (code, op0, op1)
8232 rtx sel0 = const0_rtx;
8233 rtx sel1 = const1_rtx;
8234 rtx (*fn) PARAMS ((rtx, rtx, rtx, rtx, rtx)) = gen_unary_sf_op;
8235 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
8237 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
8238 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
8242 sh_expand_binop_v2sf (code, op0, op1, op2)
8246 rtx sel0 = const0_rtx;
8247 rtx sel1 = const1_rtx;
8248 rtx (*fn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx))
8250 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
8252 emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0, sel1));
8253 emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1, sel0));
8256 /* Return the class of registers for which a mode change from FROM to TO
8259 sh_cannot_change_mode_class (from, to, class)
8260 enum machine_mode from, to;
8261 enum reg_class class;
8263 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
8265 if (TARGET_LITTLE_ENDIAN)
8267 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
8268 return reg_classes_intersect_p (DF_REGS, class);
8272 if (GET_MODE_SIZE (from) < 8)
8273 return reg_classes_intersect_p (DF_HI_REGS, class);
8280 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
8281 that label is used. */
8284 sh_mark_label (address, nuses)
8288 if (GOTOFF_P (address))
8290 /* Extract the label or symbol. */
8291 address = XEXP (address, 0);
8292 if (GET_CODE (address) == PLUS)
8293 address = XEXP (address, 0);
8294 address = XVECEXP (address, 0, 0);
8296 if (GET_CODE (address) == LABEL_REF
8297 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
8298 LABEL_NUSES (XEXP (address, 0)) += nuses;
8301 /* Compute extra cost of moving data between one register class
8304 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
8305 uses this information. Hence, the general register <-> floating point
8306 register information here is not used for SFmode. */
8309 sh_register_move_cost (mode, srcclass, dstclass)
8310 enum machine_mode mode;
8311 enum reg_class srcclass, dstclass;
8313 if (dstclass == T_REGS || dstclass == PR_REGS)
8316 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
8317 && REGCLASS_HAS_FP_REG (srcclass)
8318 && REGCLASS_HAS_FP_REG (dstclass))
8321 if ((REGCLASS_HAS_FP_REG (dstclass)
8322 && REGCLASS_HAS_GENERAL_REG (srcclass))
8323 || (REGCLASS_HAS_GENERAL_REG (dstclass)
8324 && REGCLASS_HAS_FP_REG (srcclass)))
8325 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
8326 * ((GET_MODE_SIZE (mode) + 7) / 8U));
8328 if ((dstclass == FPUL_REGS
8329 && REGCLASS_HAS_GENERAL_REG (srcclass))
8330 || (srcclass == FPUL_REGS
8331 && REGCLASS_HAS_GENERAL_REG (dstclass)))
8334 if ((dstclass == FPUL_REGS
8335 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
8336 || (srcclass == FPUL_REGS
8337 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
8340 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
8341 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
8344 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
8345 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
8350 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
8351 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
8352 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
8354 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
8357 /* Like register_operand, but take into account that SHMEDIA can use
8358 the constant zero like a general register. */
8360 sh_register_operand (op, mode)
8362 enum machine_mode mode;
8364 if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
8366 return register_operand (op, mode);