1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "insn-config.h"
35 #include "hard-reg-set.h"
37 #include "insn-attr.h"
40 #include "integrate.h"
44 #include "target-def.h"
46 #include "langhooks.h"
47 #include "basic-block.h"
49 #include "cfglayout.h"
51 #include "sched-int.h"
55 #include "alloc-pool.h"
56 #include "tm-constrs.h"
59 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
61 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
62 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
64 /* These are some macros to abstract register modes. */
65 #define CONST_OK_FOR_ADD(size) \
66 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
67 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
68 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
69 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
71 /* Used to simplify the logic below. Find the attributes wherever
73 #define SH_ATTRIBUTES(decl) \
74 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
75 : DECL_ATTRIBUTES (decl) \
76 ? (DECL_ATTRIBUTES (decl)) \
77 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
79 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
80 int current_function_interrupt;
82 tree sh_deferred_function_attributes;
83 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
85 /* Global variables for machine-dependent things. */
87 /* Which cpu are we scheduling for. */
88 enum processor_type sh_cpu;
90 /* Definitions used in ready queue reordering for first scheduling pass. */
92 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
93 static short *regmode_weight[2];
95 /* Total SFmode and SImode weights of scheduled insns. */
96 static int curr_regmode_pressure[2];
98 /* Number of r0 life regions. */
99 static int r0_life_regions;
101 /* If true, skip cycles for Q -> R movement. */
102 static int skip_cycles = 0;
104 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
105 and returned from sh_reorder2. */
106 static short cached_can_issue_more;
108 /* Provides the class number of the smallest class containing
111 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
113 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
114 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
130 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
146 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
147 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
148 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
149 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
150 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
151 GENERAL_REGS, GENERAL_REGS,
154 char sh_register_names[FIRST_PSEUDO_REGISTER] \
155 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
157 char sh_additional_register_names[ADDREGNAMES_SIZE] \
158 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
159 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
161 int assembler_dialect;
163 static bool shmedia_space_reserved_for_target_registers;
165 static bool sh_handle_option (size_t, const char *, int);
166 static void split_branches (rtx);
167 static int branch_dest (rtx);
168 static void force_into (rtx, rtx);
169 static void print_slot (rtx);
170 static rtx add_constant (rtx, enum machine_mode, rtx);
171 static void dump_table (rtx, rtx);
172 static int hi_const (rtx);
173 static int broken_move (rtx);
174 static int mova_p (rtx);
175 static rtx find_barrier (int, rtx, rtx);
176 static int noncall_uses_reg (rtx, rtx, rtx *);
177 static rtx gen_block_redirect (rtx, int, int);
178 static void sh_reorg (void);
179 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
180 static rtx frame_insn (rtx);
181 static rtx push (int);
182 static void pop (int);
183 static void push_regs (HARD_REG_SET *, int);
184 static int calc_live_regs (HARD_REG_SET *);
185 static HOST_WIDE_INT rounded_frame_size (int);
186 static rtx mark_constant_pool_use (rtx);
187 const struct attribute_spec sh_attribute_table[];
188 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
189 static tree sh_handle_resbank_handler_attribute (tree *, tree,
191 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
193 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
194 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
195 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
196 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
197 static void sh_insert_attributes (tree, tree *);
198 static const char *sh_check_pch_target_flags (int);
199 static int sh_adjust_cost (rtx, rtx, rtx, int);
200 static int sh_issue_rate (void);
201 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
202 static short find_set_regmode_weight (rtx, enum machine_mode);
203 static short find_insn_regmode_weight (rtx, enum machine_mode);
204 static void find_regmode_weight (basic_block, enum machine_mode);
205 static int find_r0_life_regions (basic_block);
206 static void sh_md_init_global (FILE *, int, int);
207 static void sh_md_finish_global (FILE *, int);
208 static int rank_for_reorder (const void *, const void *);
209 static void swap_reorder (rtx *, int);
210 static void ready_reorder (rtx *, int);
211 static short high_pressure (enum machine_mode);
212 static int sh_reorder (FILE *, int, rtx *, int *, int);
213 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
214 static void sh_md_init (FILE *, int, int);
215 static int sh_variable_issue (FILE *, int, rtx, int);
217 static bool sh_function_ok_for_sibcall (tree, tree);
219 static bool sh_cannot_modify_jumps_p (void);
220 static enum reg_class sh_target_reg_class (void);
221 static bool sh_optimize_target_register_callee_saved (bool);
222 static bool sh_ms_bitfield_layout_p (const_tree);
224 static void sh_init_builtins (void);
225 static void sh_media_init_builtins (void);
226 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
227 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
228 static void sh_file_start (void);
229 static int flow_dependent_p (rtx, rtx);
230 static void flow_dependent_p_1 (rtx, const_rtx, void *);
231 static int shiftcosts (rtx);
232 static int andcosts (rtx);
233 static int addsubcosts (rtx);
234 static int multcosts (rtx);
235 static bool unspec_caller_rtx_p (rtx);
236 static bool sh_cannot_copy_insn_p (rtx);
237 static bool sh_rtx_costs (rtx, int, int, int *, bool);
238 static int sh_address_cost (rtx, bool);
239 static int sh_pr_n_sets (void);
240 static rtx sh_allocate_initial_value (rtx);
241 static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);
242 static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
243 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
244 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
245 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
246 static int scavenge_reg (HARD_REG_SET *s);
247 struct save_schedule_s;
248 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
249 struct save_schedule_s *, int);
251 static rtx sh_struct_value_rtx (tree, int);
252 static bool sh_return_in_memory (const_tree, const_tree);
253 static rtx sh_builtin_saveregs (void);
254 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
255 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
256 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
257 static tree sh_build_builtin_va_list (void);
258 static void sh_va_start (tree, rtx);
259 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
260 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
262 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
264 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
266 static bool sh_scalar_mode_supported_p (enum machine_mode);
267 static int sh_dwarf_calling_convention (const_tree);
268 static void sh_encode_section_info (tree, rtx, int);
269 static int sh2a_function_vector_p (tree);
272 /* Initialize the GCC target structure. */
273 #undef TARGET_ATTRIBUTE_TABLE
274 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
276 /* The next two are used for debug info when compiling with -gdwarf. */
277 #undef TARGET_ASM_UNALIGNED_HI_OP
278 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
279 #undef TARGET_ASM_UNALIGNED_SI_OP
280 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
282 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
283 #undef TARGET_ASM_UNALIGNED_DI_OP
284 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
285 #undef TARGET_ASM_ALIGNED_DI_OP
286 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
288 #undef TARGET_ASM_FUNCTION_EPILOGUE
289 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
291 #undef TARGET_ASM_OUTPUT_MI_THUNK
292 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
294 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
295 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
297 #undef TARGET_ASM_FILE_START
298 #define TARGET_ASM_FILE_START sh_file_start
299 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
300 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
302 #undef TARGET_DEFAULT_TARGET_FLAGS
303 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
304 #undef TARGET_HANDLE_OPTION
305 #define TARGET_HANDLE_OPTION sh_handle_option
307 #undef TARGET_INSERT_ATTRIBUTES
308 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
310 #undef TARGET_SCHED_ADJUST_COST
311 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
313 #undef TARGET_SCHED_ISSUE_RATE
314 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
316 /* The next 5 hooks have been implemented for reenabling sched1. With the
317 help of these macros we are limiting the movement of insns in sched1 to
318 reduce the register pressure. The overall idea is to keep count of SImode
319 and SFmode regs required by already scheduled insns. When these counts
320 cross some threshold values; give priority to insns that free registers.
321 The insn that frees registers is most likely to be the insn with lowest
322 LUID (original insn order); but such an insn might be there in the stalled
323 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
324 upto a max of 8 cycles so that such insns may move from Q -> R.
326 The description of the hooks are as below:
328 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
329 scheduler; it is called inside the sched_init function just after
330 find_insn_reg_weights function call. It is used to calculate the SImode
331 and SFmode weights of insns of basic blocks; much similar to what
332 find_insn_reg_weights does.
333 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
335 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
336 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
339 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
340 high; reorder the ready queue so that the insn with lowest LUID will be
343 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
344 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
346 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
347 can be returned from TARGET_SCHED_REORDER2.
349 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
351 #undef TARGET_SCHED_DFA_NEW_CYCLE
352 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
354 #undef TARGET_SCHED_INIT_GLOBAL
355 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
357 #undef TARGET_SCHED_FINISH_GLOBAL
358 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
360 #undef TARGET_SCHED_VARIABLE_ISSUE
361 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
363 #undef TARGET_SCHED_REORDER
364 #define TARGET_SCHED_REORDER sh_reorder
366 #undef TARGET_SCHED_REORDER2
367 #define TARGET_SCHED_REORDER2 sh_reorder2
369 #undef TARGET_SCHED_INIT
370 #define TARGET_SCHED_INIT sh_md_init
372 #undef TARGET_LEGITIMIZE_ADDRESS
373 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
375 #undef TARGET_CANNOT_MODIFY_JUMPS_P
376 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
377 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
378 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
379 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
380 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
381 sh_optimize_target_register_callee_saved
383 #undef TARGET_MS_BITFIELD_LAYOUT_P
384 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
386 #undef TARGET_INIT_BUILTINS
387 #define TARGET_INIT_BUILTINS sh_init_builtins
388 #undef TARGET_EXPAND_BUILTIN
389 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
391 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
392 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
394 #undef TARGET_CANNOT_COPY_INSN_P
395 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
396 #undef TARGET_RTX_COSTS
397 #define TARGET_RTX_COSTS sh_rtx_costs
398 #undef TARGET_ADDRESS_COST
399 #define TARGET_ADDRESS_COST sh_address_cost
400 #undef TARGET_ALLOCATE_INITIAL_VALUE
401 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
403 #undef TARGET_MACHINE_DEPENDENT_REORG
404 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
406 #undef TARGET_DWARF_REGISTER_SPAN
407 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
410 #undef TARGET_HAVE_TLS
411 #define TARGET_HAVE_TLS true
414 #undef TARGET_PROMOTE_PROTOTYPES
415 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
416 #undef TARGET_PROMOTE_FUNCTION_ARGS
417 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
418 #undef TARGET_PROMOTE_FUNCTION_RETURN
419 #define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
421 #undef TARGET_STRUCT_VALUE_RTX
422 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
423 #undef TARGET_RETURN_IN_MEMORY
424 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
426 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
427 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
428 #undef TARGET_SETUP_INCOMING_VARARGS
429 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
430 #undef TARGET_STRICT_ARGUMENT_NAMING
431 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
432 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
433 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
434 #undef TARGET_MUST_PASS_IN_STACK
435 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
436 #undef TARGET_PASS_BY_REFERENCE
437 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
438 #undef TARGET_CALLEE_COPIES
439 #define TARGET_CALLEE_COPIES sh_callee_copies
440 #undef TARGET_ARG_PARTIAL_BYTES
441 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
443 #undef TARGET_BUILD_BUILTIN_VA_LIST
444 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
445 #undef TARGET_EXPAND_BUILTIN_VA_START
446 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
447 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
448 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
450 #undef TARGET_SCALAR_MODE_SUPPORTED_P
451 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
452 #undef TARGET_VECTOR_MODE_SUPPORTED_P
453 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
455 #undef TARGET_CHECK_PCH_TARGET_FLAGS
456 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
458 #undef TARGET_DWARF_CALLING_CONVENTION
459 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
461 /* Return regmode weight for insn. */
462 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
464 /* Return current register pressure for regmode. */
465 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
467 #undef TARGET_ENCODE_SECTION_INFO
468 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
472 #undef TARGET_ENCODE_SECTION_INFO
473 #define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
474 #undef TARGET_STRIP_NAME_ENCODING
475 #define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
476 #undef TARGET_CXX_IMPORT_EXPORT_CLASS
477 #define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
481 #undef TARGET_SECONDARY_RELOAD
482 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
484 #undef TARGET_LEGITIMATE_ADDRESS_P
485 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
487 /* Machine-specific symbol_ref flags. */
488 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
490 struct gcc_target targetm = TARGET_INITIALIZER;
492 /* Implement TARGET_HANDLE_OPTION. */
495 sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
496 int value ATTRIBUTE_UNUSED)
501 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
505 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
509 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
513 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
517 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
520 case OPT_m2a_single_only:
521 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
525 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
529 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
533 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
540 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
544 case OPT_m4_100_nofpu:
545 case OPT_m4_200_nofpu:
546 case OPT_m4_300_nofpu:
550 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
554 case OPT_m4_100_single:
555 case OPT_m4_200_single:
556 case OPT_m4_300_single:
557 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
560 case OPT_m4_single_only:
561 case OPT_m4_100_single_only:
562 case OPT_m4_200_single_only:
563 case OPT_m4_300_single_only:
564 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
568 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
573 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
577 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
580 case OPT_m4a_single_only:
581 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
585 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
588 case OPT_m5_32media_nofpu:
589 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
593 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
596 case OPT_m5_64media_nofpu:
597 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
601 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
604 case OPT_m5_compact_nofpu:
605 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
613 /* Print the operand address in x to the stream. */
616 print_operand_address (FILE *stream, rtx x)
618 switch (GET_CODE (x))
622 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
627 rtx base = XEXP (x, 0);
628 rtx index = XEXP (x, 1);
630 switch (GET_CODE (index))
633 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
634 reg_names[true_regnum (base)]);
640 int base_num = true_regnum (base);
641 int index_num = true_regnum (index);
643 fprintf (stream, "@(r0,%s)",
644 reg_names[MAX (base_num, index_num)]);
655 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
659 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
663 x = mark_constant_pool_use (x);
664 output_addr_const (stream, x);
669 /* Print operand x (an rtx) in assembler syntax to file stream
670 according to modifier code.
672 '.' print a .s if insn needs delay slot
673 ',' print LOCAL_LABEL_PREFIX
674 '@' print trap, rte or rts depending upon pragma interruptness
675 '#' output a nop if there is nothing to put in the delay slot
676 ''' print likelihood suffix (/u for unlikely).
677 '>' print branch target if -fverbose-asm
678 'O' print a constant without the #
679 'R' print the LSW of a dp value - changes if in little endian
680 'S' print the MSW of a dp value - changes if in little endian
681 'T' print the next word of a dp value - same as 'R' in big endian mode.
682 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
683 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
684 'N' print 'r63' if the operand is (const_int 0).
685 'd' print a V2SF reg as dN instead of fpN.
686 'm' print a pair `base,offset' or `base,index', for LD and ST.
687 'U' Likewise for {LD,ST}{HI,LO}.
688 'V' print the position of a single bit set.
689 'W' print the position of a single bit cleared.
690 't' print a memory address which is a register.
691 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
692 'o' output an operator. */
695 print_operand (FILE *stream, rtx x, int code)
698 enum machine_mode mode;
706 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
707 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
708 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
711 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
714 trapa_attr = lookup_attribute ("trap_exit",
715 DECL_ATTRIBUTES (current_function_decl));
717 fprintf (stream, "trapa #%ld",
718 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
719 else if (sh_cfun_interrupt_handler_p ())
721 if (sh_cfun_resbank_handler_p ())
722 fprintf (stream, "resbank\n");
723 fprintf (stream, "rte");
726 fprintf (stream, "rts");
729 /* Output a nop if there's nothing in the delay slot. */
730 if (dbr_sequence_length () == 0)
731 fprintf (stream, "\n\tnop");
735 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
737 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
738 fputs ("/u", stream);
742 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
744 fputs ("\t! target: ", stream);
745 output_addr_const (stream, JUMP_LABEL (current_output_insn));
749 x = mark_constant_pool_use (x);
750 output_addr_const (stream, x);
752 /* N.B.: %R / %S / %T adjust memory addresses by four.
753 For SHMEDIA, that means they can be used to access the first and
754 second 32 bit part of a 64 bit (or larger) value that
755 might be held in floating point registers or memory.
756 While they can be used to access 64 bit parts of a larger value
757 held in general purpose registers, that won't work with memory -
758 neither for fp registers, since the frxx names are used. */
760 if (REG_P (x) || GET_CODE (x) == SUBREG)
762 regno = true_regnum (x);
763 regno += FP_REGISTER_P (regno) ? 1 : LSW;
764 fputs (reg_names[regno], (stream));
768 x = adjust_address (x, SImode, 4 * LSW);
769 print_operand_address (stream, XEXP (x, 0));
776 if (mode == VOIDmode)
778 if (GET_MODE_SIZE (mode) >= 8)
779 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
781 print_operand (stream, sub, 0);
783 output_operand_lossage ("invalid operand to %%R");
787 if (REG_P (x) || GET_CODE (x) == SUBREG)
789 regno = true_regnum (x);
790 regno += FP_REGISTER_P (regno) ? 0 : MSW;
791 fputs (reg_names[regno], (stream));
795 x = adjust_address (x, SImode, 4 * MSW);
796 print_operand_address (stream, XEXP (x, 0));
803 if (mode == VOIDmode)
805 if (GET_MODE_SIZE (mode) >= 8)
806 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
808 print_operand (stream, sub, 0);
810 output_operand_lossage ("invalid operand to %%S");
814 /* Next word of a double. */
815 switch (GET_CODE (x))
818 fputs (reg_names[REGNO (x) + 1], (stream));
821 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
822 && GET_CODE (XEXP (x, 0)) != POST_INC)
823 x = adjust_address (x, SImode, 4);
824 print_operand_address (stream, XEXP (x, 0));
832 gcc_assert (GET_CODE (x) == MEM);
834 switch (GET_CODE (x))
838 print_operand (stream, x, 0);
846 switch (GET_CODE (x))
848 case PLUS: fputs ("add", stream); break;
849 case MINUS: fputs ("sub", stream); break;
850 case MULT: fputs ("mul", stream); break;
851 case DIV: fputs ("div", stream); break;
852 case EQ: fputs ("eq", stream); break;
853 case NE: fputs ("ne", stream); break;
854 case GT: case LT: fputs ("gt", stream); break;
855 case GE: case LE: fputs ("ge", stream); break;
856 case GTU: case LTU: fputs ("gtu", stream); break;
857 case GEU: case LEU: fputs ("geu", stream); break;
865 if (GET_CODE (x) == MEM
866 && GET_CODE (XEXP (x, 0)) == PLUS
867 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
868 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
873 if (GET_CODE (x) == MEM)
875 switch (GET_MODE (x))
877 case QImode: fputs (".b", stream); break;
878 case HImode: fputs (".w", stream); break;
879 case SImode: fputs (".l", stream); break;
880 case SFmode: fputs (".s", stream); break;
881 case DFmode: fputs (".d", stream); break;
882 default: gcc_unreachable ();
889 gcc_assert (GET_CODE (x) == MEM);
893 switch (GET_CODE (x))
897 print_operand (stream, x, 0);
898 fputs (", 0", stream);
902 print_operand (stream, XEXP (x, 0), 0);
903 fputs (", ", stream);
904 print_operand (stream, XEXP (x, 1), 0);
914 int num = exact_log2 (INTVAL (x));
915 gcc_assert (num >= 0);
916 fprintf (stream, "#%d", num);
922 int num = exact_log2 (~INTVAL (x));
923 gcc_assert (num >= 0);
924 fprintf (stream, "#%d", num);
929 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == V2SFmode);
931 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
935 if (x == CONST0_RTX (GET_MODE (x)))
937 fprintf ((stream), "r63");
942 if (GET_CODE (x) == CONST_INT)
944 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
954 switch (GET_CODE (x))
958 rtx inner = XEXP (x, 0);
960 enum machine_mode inner_mode;
962 /* We might see SUBREGs with vector mode registers inside. */
963 if (GET_CODE (inner) == SUBREG
964 && (GET_MODE_SIZE (GET_MODE (inner))
965 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
966 && subreg_lowpart_p (inner))
967 inner = SUBREG_REG (inner);
968 if (GET_CODE (inner) == CONST_INT)
970 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
973 inner_mode = GET_MODE (inner);
974 if (GET_CODE (inner) == SUBREG
975 && (GET_MODE_SIZE (GET_MODE (inner))
976 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
977 && GET_CODE (SUBREG_REG (inner)) == REG)
979 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
980 GET_MODE (SUBREG_REG (inner)),
983 inner = SUBREG_REG (inner);
985 if (GET_CODE (inner) != REG || GET_MODE_SIZE (inner_mode) > 8)
987 /* Floating point register pairs are always big endian;
988 general purpose registers are 64 bit wide. */
989 regno = REGNO (inner);
990 regno = (HARD_REGNO_NREGS (regno, inner_mode)
991 - HARD_REGNO_NREGS (regno, mode))
999 /* FIXME: We need this on SHmedia32 because reload generates
1000 some sign-extended HI or QI loads into DImode registers
1001 but, because Pmode is SImode, the address ends up with a
1002 subreg:SI of the DImode register. Maybe reload should be
1003 fixed so as to apply alter_subreg to such loads? */
1005 gcc_assert (trapping_target_operand (x, VOIDmode));
1006 x = XEXP (XEXP (x, 2), 0);
1007 goto default_output;
1009 gcc_assert (SUBREG_BYTE (x) == 0
1010 && GET_CODE (SUBREG_REG (x)) == REG);
1018 if (FP_REGISTER_P (regno)
1019 && mode == V16SFmode)
1020 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1021 else if (FP_REGISTER_P (REGNO (x))
1022 && mode == V4SFmode)
1023 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1024 else if (GET_CODE (x) == REG
1025 && mode == V2SFmode)
1026 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1027 else if (FP_REGISTER_P (REGNO (x))
1028 && GET_MODE_SIZE (mode) > 4)
1029 fprintf ((stream), "d%s", reg_names[regno] + 1);
1031 fputs (reg_names[regno], (stream));
1035 output_address (XEXP (x, 0));
1040 fputc ('#', stream);
1041 output_addr_const (stream, x);
1049 /* Encode symbol attributes of a SYMBOL_REF into its
1050 SYMBOL_REF_FLAGS. */
1052 sh_encode_section_info (tree decl, rtx rtl, int first)
1054 default_encode_section_info (decl, rtl, first);
1056 if (TREE_CODE (decl) == FUNCTION_DECL
1057 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1058 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1061 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1063 force_into (rtx value, rtx target)
1065 value = force_operand (value, target);
1066 if (! rtx_equal_p (value, target))
1067 emit_insn (gen_move_insn (target, value));
1070 /* Emit code to perform a block move. Choose the best method.
1072 OPERANDS[0] is the destination.
1073 OPERANDS[1] is the source.
1074 OPERANDS[2] is the size.
1075 OPERANDS[3] is the alignment safe to use. */
1078 expand_block_move (rtx *operands)
1080 int align = INTVAL (operands[3]);
1081 int constp = (GET_CODE (operands[2]) == CONST_INT);
1082 int bytes = (constp ? INTVAL (operands[2]) : 0);
1087 /* If we could use mov.l to move words and dest is word-aligned, we
1088 can use movua.l for loads and still generate a relatively short
1089 and efficient sequence. */
1090 if (TARGET_SH4A_ARCH && align < 4
1091 && MEM_ALIGN (operands[0]) >= 32
1092 && can_move_by_pieces (bytes, 32))
1094 rtx dest = copy_rtx (operands[0]);
1095 rtx src = copy_rtx (operands[1]);
1096 /* We could use different pseudos for each copied word, but
1097 since movua can only load into r0, it's kind of
1099 rtx temp = gen_reg_rtx (SImode);
1100 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1103 while (copied + 4 <= bytes)
1105 rtx to = adjust_address (dest, SImode, copied);
1106 rtx from = adjust_automodify_address (src, BLKmode,
1109 set_mem_size (from, GEN_INT (4));
1110 emit_insn (gen_movua (temp, from));
1111 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1112 emit_move_insn (to, temp);
1117 move_by_pieces (adjust_address (dest, BLKmode, copied),
1118 adjust_automodify_address (src, BLKmode,
1120 bytes - copied, align, 0);
1125 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1126 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1127 if (align < 4 || (bytes % 4 != 0))
1130 if (TARGET_HARD_SH4)
1134 else if (bytes == 12)
1136 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1137 rtx r4 = gen_rtx_REG (SImode, 4);
1138 rtx r5 = gen_rtx_REG (SImode, 5);
1140 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1141 force_into (XEXP (operands[0], 0), r4);
1142 force_into (XEXP (operands[1], 0), r5);
1143 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1146 else if (! TARGET_SMALLCODE)
1148 const char *entry_name;
1149 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1151 rtx r4 = gen_rtx_REG (SImode, 4);
1152 rtx r5 = gen_rtx_REG (SImode, 5);
1153 rtx r6 = gen_rtx_REG (SImode, 6);
1155 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1156 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1157 force_into (XEXP (operands[0], 0), r4);
1158 force_into (XEXP (operands[1], 0), r5);
1160 dwords = bytes >> 3;
1161 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1162 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1171 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1172 rtx r4 = gen_rtx_REG (SImode, 4);
1173 rtx r5 = gen_rtx_REG (SImode, 5);
1175 sprintf (entry, "__movmemSI%d", bytes);
1176 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1177 force_into (XEXP (operands[0], 0), r4);
1178 force_into (XEXP (operands[1], 0), r5);
1179 emit_insn (gen_block_move_real (func_addr_rtx));
1183 /* This is the same number of bytes as a memcpy call, but to a different
1184 less common function name, so this will occasionally use more space. */
1185 if (! TARGET_SMALLCODE)
1187 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1188 int final_switch, while_loop;
1189 rtx r4 = gen_rtx_REG (SImode, 4);
1190 rtx r5 = gen_rtx_REG (SImode, 5);
1191 rtx r6 = gen_rtx_REG (SImode, 6);
1193 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1194 force_into (XEXP (operands[0], 0), r4);
1195 force_into (XEXP (operands[1], 0), r5);
1197 /* r6 controls the size of the move. 16 is decremented from it
1198 for each 64 bytes moved. Then the negative bit left over is used
1199 as an index into a list of move instructions. e.g., a 72 byte move
1200 would be set up with size(r6) = 14, for one iteration through the
1201 big while loop, and a switch of -2 for the last part. */
1203 final_switch = 16 - ((bytes / 4) % 16);
1204 while_loop = ((bytes / 4) / 16 - 1) * 16;
1205 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1206 emit_insn (gen_block_lump_real (func_addr_rtx));
1213 /* Prepare operands for a move define_expand; specifically, one of the
1214 operands must be in a register. */
1217 prepare_move_operands (rtx operands[], enum machine_mode mode)
1219 if ((mode == SImode || mode == DImode)
1221 && ! ((mode == Pmode || mode == ptr_mode)
1222 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1225 if (SYMBOLIC_CONST_P (operands[1]))
1227 if (GET_CODE (operands[0]) == MEM)
1228 operands[1] = force_reg (Pmode, operands[1]);
1229 else if (TARGET_SHMEDIA
1230 && GET_CODE (operands[1]) == LABEL_REF
1231 && target_reg_operand (operands[0], mode))
1235 temp = (!can_create_pseudo_p ()
1237 : gen_reg_rtx (Pmode));
1238 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1241 else if (GET_CODE (operands[1]) == CONST
1242 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1243 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1245 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1246 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1248 operands[1] = expand_binop (mode, add_optab, temp,
1249 XEXP (XEXP (operands[1], 0), 1),
1250 (!can_create_pseudo_p ()
1252 : gen_reg_rtx (Pmode)),
1253 0, OPTAB_LIB_WIDEN);
1257 if (! reload_in_progress && ! reload_completed)
1259 /* Copy the source to a register if both operands aren't registers. */
1260 if (! register_operand (operands[0], mode)
1261 && ! sh_register_operand (operands[1], mode))
1262 operands[1] = copy_to_mode_reg (mode, operands[1]);
1264 if (GET_CODE (operands[0]) == MEM && ! memory_operand (operands[0], mode))
1266 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1267 except that we can't use that function because it is static. */
1268 rtx new_rtx = change_address (operands[0], mode, 0);
1269 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1270 operands[0] = new_rtx;
1273 /* This case can happen while generating code to move the result
1274 of a library call to the target. Reject `st r0,@(rX,rY)' because
1275 reload will fail to find a spill register for rX, since r0 is already
1276 being used for the source. */
1278 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1279 && GET_CODE (operands[0]) == MEM
1280 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1281 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
1282 operands[1] = copy_to_mode_reg (mode, operands[1]);
1285 if (mode == Pmode || mode == ptr_mode)
1288 enum tls_model tls_kind;
1292 if (GET_CODE (op1) == CONST
1293 && GET_CODE (XEXP (op1, 0)) == PLUS
1294 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1297 opc = XEXP (XEXP (op1, 0), 1);
1298 op1 = XEXP (XEXP (op1, 0), 0);
1303 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1305 rtx tga_op1, tga_ret, tmp, tmp2;
1309 case TLS_MODEL_GLOBAL_DYNAMIC:
1310 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1311 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1315 case TLS_MODEL_LOCAL_DYNAMIC:
1316 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1317 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1319 tmp = gen_reg_rtx (Pmode);
1320 emit_move_insn (tmp, tga_ret);
1322 if (register_operand (op0, Pmode))
1325 tmp2 = gen_reg_rtx (Pmode);
1327 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1331 case TLS_MODEL_INITIAL_EXEC:
1334 /* Don't schedule insns for getting GOT address when
1335 the first scheduling is enabled, to avoid spill
1337 if (flag_schedule_insns)
1338 emit_insn (gen_blockage ());
1339 emit_insn (gen_GOTaddr2picreg ());
1340 emit_use (gen_rtx_REG (SImode, PIC_REG));
1341 if (flag_schedule_insns)
1342 emit_insn (gen_blockage ());
1344 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1345 tmp = gen_sym2GOTTPOFF (op1);
1346 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1350 case TLS_MODEL_LOCAL_EXEC:
1351 tmp2 = gen_reg_rtx (Pmode);
1352 emit_insn (gen_load_gbr (tmp2));
1353 tmp = gen_reg_rtx (Pmode);
1354 emit_insn (gen_symTPOFF2reg (tmp, op1));
1356 if (register_operand (op0, Pmode))
1359 op1 = gen_reg_rtx (Pmode);
1361 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1368 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1377 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1378 enum rtx_code comparison)
1381 rtx scratch = NULL_RTX;
1383 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1384 comparison = GET_CODE (operands[0]);
1386 scratch = operands[4];
1387 if (GET_CODE (operands[1]) == CONST_INT
1388 && GET_CODE (operands[2]) != CONST_INT)
1390 rtx tmp = operands[1];
1392 operands[1] = operands[2];
1394 comparison = swap_condition (comparison);
1396 if (GET_CODE (operands[2]) == CONST_INT)
1398 HOST_WIDE_INT val = INTVAL (operands[2]);
1399 if ((val == -1 || val == -0x81)
1400 && (comparison == GT || comparison == LE))
1402 comparison = (comparison == GT) ? GE : LT;
1403 operands[2] = gen_int_mode (val + 1, mode);
1405 else if ((val == 1 || val == 0x80)
1406 && (comparison == GE || comparison == LT))
1408 comparison = (comparison == GE) ? GT : LE;
1409 operands[2] = gen_int_mode (val - 1, mode);
1411 else if (val == 1 && (comparison == GEU || comparison == LTU))
1413 comparison = (comparison == GEU) ? NE : EQ;
1414 operands[2] = CONST0_RTX (mode);
1416 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1418 comparison = (comparison == GEU) ? GTU : LEU;
1419 operands[2] = gen_int_mode (val - 1, mode);
1421 else if (val == 0 && (comparison == GTU || comparison == LEU))
1422 comparison = (comparison == GTU) ? NE : EQ;
1423 else if (mode == SImode
1424 && ((val == 0x7fffffff
1425 && (comparison == GTU || comparison == LEU))
1426 || ((unsigned HOST_WIDE_INT) val
1427 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1428 && (comparison == GEU || comparison == LTU))))
1430 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1431 operands[2] = CONST0_RTX (mode);
1435 if (can_create_pseudo_p ())
1436 operands[1] = force_reg (mode, op1);
1437 /* When we are handling DImode comparisons, we want to keep constants so
1438 that we can optimize the component comparisons; however, memory loads
1439 are better issued as a whole so that they can be scheduled well.
1440 SImode equality comparisons allow I08 constants, but only when they
1441 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1442 into a register, that register might as well be r0, and we allow the
1443 constant. If it is already in a register, this is likely to be
1444 allocated to a different hard register, thus we load the constant into
1445 a register unless it is zero. */
1446 if (!REG_P (operands[2])
1447 && (GET_CODE (operands[2]) != CONST_INT
1448 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1449 && ((comparison != EQ && comparison != NE)
1450 || (REG_P (op1) && REGNO (op1) != R0_REG)
1451 || !satisfies_constraint_I08 (operands[2])))))
1453 if (scratch && GET_MODE (scratch) == mode)
1455 emit_move_insn (scratch, operands[2]);
1456 operands[2] = scratch;
1458 else if (can_create_pseudo_p ())
1459 operands[2] = force_reg (mode, operands[2]);
1465 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1467 rtx (*branch_expander) (rtx) = gen_branch_true;
1470 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1473 case NE: case LT: case LE: case LTU: case LEU:
1474 comparison = reverse_condition (comparison);
1475 branch_expander = gen_branch_false;
1478 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1479 gen_rtx_fmt_ee (comparison, SImode,
1480 operands[1], operands[2])));
1481 jump = emit_jump_insn (branch_expander (operands[3]));
1482 if (probability >= 0)
1483 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
1487 /* ??? How should we distribute probabilities when more than one branch
1488 is generated. So far we only have soem ad-hoc observations:
1489 - If the operands are random, they are likely to differ in both parts.
1490 - If comparing items in a hash chain, the operands are random or equal;
1491 operation should be EQ or NE.
1492 - If items are searched in an ordered tree from the root, we can expect
1493 the highpart to be unequal about half of the time; operation should be
1494 an inequality comparison, operands non-constant, and overall probability
1495 about 50%. Likewise for quicksort.
1496 - Range checks will be often made against constants. Even if we assume for
1497 simplicity an even distribution of the non-constant operand over a
1498 sub-range here, the same probability could be generated with differently
1499 wide sub-ranges - as long as the ratio of the part of the subrange that
1500 is before the threshold to the part that comes after the threshold stays
1501 the same. Thus, we can't really tell anything here;
1502 assuming random distribution is at least simple.
1506 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1508 enum rtx_code msw_taken, msw_skip, lsw_taken;
1509 rtx skip_label = NULL_RTX;
1510 rtx op1h, op1l, op2h, op2l;
1513 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1514 rtx scratch = operands[4];
1516 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1517 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1518 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1519 op1l = gen_lowpart (SImode, operands[1]);
1520 op2l = gen_lowpart (SImode, operands[2]);
1521 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
1522 prob = split_branch_probability;
1523 rev_prob = REG_BR_PROB_BASE - prob;
1526 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1527 That costs 1 cycle more when the first branch can be predicted taken,
1528 but saves us mispredicts because only one branch needs prediction.
1529 It also enables generating the cmpeqdi_t-1 pattern. */
1531 if (TARGET_CMPEQDI_T)
1533 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1534 emit_jump_insn (gen_branch_true (operands[3]));
1541 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1543 msw_skip_prob = rev_prob;
1544 if (REG_BR_PROB_BASE <= 65535)
1545 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1548 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1552 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1553 / ((HOST_WIDEST_INT) prob << 32)))
1559 if (TARGET_CMPEQDI_T)
1561 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1562 emit_jump_insn (gen_branch_false (operands[3]));
1566 msw_taken_prob = prob;
1571 msw_taken = comparison;
1572 if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1)
1574 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1575 msw_skip = swap_condition (msw_taken);
1579 if (op2l == CONST0_RTX (SImode))
1580 msw_taken = comparison;
1583 msw_taken = comparison == GE ? GT : GTU;
1584 msw_skip = swap_condition (msw_taken);
1589 msw_taken = comparison;
1590 if (op2l == CONST0_RTX (SImode))
1592 msw_skip = swap_condition (msw_taken);
1596 if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1)
1597 msw_taken = comparison;
1601 if (comparison == LE)
1603 else if (op2h != CONST0_RTX (SImode))
1607 msw_skip = swap_condition (msw_taken);
1610 default: return false;
1612 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
1613 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1614 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
1615 if (comparison != EQ && comparison != NE && num_branches > 1)
1617 if (!CONSTANT_P (operands[2])
1618 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1619 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1621 msw_taken_prob = prob / 2U;
1623 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1624 lsw_taken_prob = prob;
1628 msw_taken_prob = prob;
1629 msw_skip_prob = REG_BR_PROB_BASE;
1630 /* ??? If we have a constant op2h, should we use that when
1631 calculating lsw_taken_prob? */
1632 lsw_taken_prob = prob;
1637 operands[4] = NULL_RTX;
1638 if (reload_completed
1639 && ! arith_reg_or_0_operand (op2h, SImode)
1640 && (true_regnum (op1h) || (comparison != EQ && comparison != NE))
1641 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
1642 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
1644 emit_move_insn (scratch, operands[2]);
1645 operands[2] = scratch;
1647 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1648 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
1649 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1651 rtx taken_label = operands[3];
1653 /* Operands were possibly modified, but msw_skip doesn't expect this.
1654 Always use the original ones. */
1655 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1661 operands[3] = skip_label = gen_label_rtx ();
1662 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
1663 operands[3] = taken_label;
1667 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
1669 if (reload_completed
1670 && ! arith_reg_or_0_operand (op2l, SImode)
1671 && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE)))
1673 emit_move_insn (scratch, operands[2]);
1674 operands[2] = scratch;
1676 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
1678 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1679 emit_label (skip_label);
1683 /* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
1686 sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
1688 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1690 insn = gen_rtx_PARALLEL (VOIDmode,
1692 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
1693 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1699 /* Prepare the operands for an scc instruction; make sure that the
1700 compare has been done and the result is in T_REG. */
1702 sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
1704 rtx t_reg = gen_rtx_REG (SImode, T_REG);
1705 enum rtx_code oldcode = code;
1706 enum machine_mode mode;
1708 /* First need a compare insn. */
1712 /* It isn't possible to handle this case. */
1729 if (code != oldcode)
1736 mode = GET_MODE (op0);
1737 if (mode == VOIDmode)
1738 mode = GET_MODE (op1);
1740 op0 = force_reg (mode, op0);
1741 if ((code != EQ && code != NE
1742 && (op1 != const0_rtx
1743 || code == GTU || code == GEU || code == LTU || code == LEU))
1744 || (mode == DImode && op1 != const0_rtx)
1745 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1746 op1 = force_reg (mode, op1);
1748 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode, t_reg,
1749 gen_rtx_fmt_ee (code, SImode, op0, op1)),
1754 sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
1757 rtx target = gen_reg_rtx (SImode);
1760 gcc_assert (TARGET_SHMEDIA);
1769 tmp = gen_rtx_fmt_ee (code, SImode, op0, op1);
1770 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
1780 tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1);
1781 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
1799 rtx t2 = gen_reg_rtx (DImode);
1800 emit_insn (gen_extendsidi2 (t2, target));
1804 return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx);
1807 /* Called from the md file, set up the operands of a compare instruction. */
1810 sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
1812 enum rtx_code code = GET_CODE (operands[0]);
1813 enum rtx_code branch_code;
1814 rtx op0 = operands[1];
1815 rtx op1 = operands[2];
1817 bool need_ccmpeq = false;
1819 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
1821 op0 = force_reg (mode, op0);
1822 op1 = force_reg (mode, op1);
1826 if (code != EQ || mode == DImode)
1828 /* Force args into regs, since we can't use constants here. */
1829 op0 = force_reg (mode, op0);
1830 if (op1 != const0_rtx || code == GTU || code == GEU)
1831 op1 = force_reg (mode, op1);
1835 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1838 || (code == LE && TARGET_IEEE && TARGET_SH2E)
1839 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
1841 tem = op0, op0 = op1, op1 = tem;
1842 code = swap_condition (code);
1845 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
1848 gcc_assert (TARGET_IEEE && TARGET_SH2E);
1853 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
1854 to EQ/GT respectively. */
1855 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
1872 branch_code = reverse_condition (code);
1878 insn = gen_rtx_SET (VOIDmode,
1879 gen_rtx_REG (SImode, T_REG),
1880 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
1882 sh_emit_set_t_insn (insn, mode);
1884 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
1886 if (branch_code == code)
1887 emit_jump_insn (gen_branch_true (operands[3]));
1889 emit_jump_insn (gen_branch_false (operands[3]));
1893 sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
1895 enum rtx_code code = GET_CODE (operands[1]);
1896 rtx op0 = operands[2];
1897 rtx op1 = operands[3];
1899 bool invert = false;
1902 op0 = force_reg (mode, op0);
1903 if ((code != EQ && code != NE
1904 && (op1 != const0_rtx
1905 || code == GTU || code == GEU || code == LTU || code == LEU))
1906 || (mode == DImode && op1 != const0_rtx)
1907 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1908 op1 = force_reg (mode, op1);
1910 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1912 if (code == LT || code == LE)
1914 code = swap_condition (code);
1915 tem = op0, op0 = op1, op1 = tem;
1921 lab = gen_label_rtx ();
1922 sh_emit_scc_to_t (EQ, op0, op1);
1923 emit_jump_insn (gen_branch_true (lab));
1940 sh_emit_scc_to_t (code, op0, op1);
1944 emit_insn (gen_movnegt (operands[0]));
1946 emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
1949 /* Functions to output assembly code. */
1951 /* Return a sequence of instructions to perform DI or DF move.
1953 Since the SH cannot move a DI or DF in one instruction, we have
1954 to take care when we see overlapping source and dest registers. */
1957 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1958 enum machine_mode mode)
1960 rtx dst = operands[0];
1961 rtx src = operands[1];
1963 if (GET_CODE (dst) == MEM
1964 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
1965 return "mov.l %T1,%0\n\tmov.l %1,%0";
1967 if (register_operand (dst, mode)
1968 && register_operand (src, mode))
1970 if (REGNO (src) == MACH_REG)
1971 return "sts mach,%S0\n\tsts macl,%R0";
1973 /* When mov.d r1,r2 do r2->r3 then r1->r2;
1974 when mov.d r1,r0 do r1->r0 then r2->r1. */
1976 if (REGNO (src) + 1 == REGNO (dst))
1977 return "mov %T1,%T0\n\tmov %1,%0";
1979 return "mov %1,%0\n\tmov %T1,%T0";
1981 else if (GET_CODE (src) == CONST_INT)
1983 if (INTVAL (src) < 0)
1984 output_asm_insn ("mov #-1,%S0", operands);
1986 output_asm_insn ("mov #0,%S0", operands);
1988 return "mov %1,%R0";
1990 else if (GET_CODE (src) == MEM)
1993 int dreg = REGNO (dst);
1994 rtx inside = XEXP (src, 0);
1996 switch (GET_CODE (inside))
1999 ptrreg = REGNO (inside);
2003 ptrreg = subreg_regno (inside);
2007 ptrreg = REGNO (XEXP (inside, 0));
2008 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2009 an offsettable address. Unfortunately, offsettable addresses use
2010 QImode to check the offset, and a QImode offsettable address
2011 requires r0 for the other operand, which is not currently
2012 supported, so we can't use the 'o' constraint.
2013 Thus we must check for and handle r0+REG addresses here.
2014 We punt for now, since this is likely very rare. */
2015 gcc_assert (GET_CODE (XEXP (inside, 1)) != REG);
2019 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2021 return "mov.l %1,%0\n\tmov.l %1,%T0";
2026 /* Work out the safe way to copy. Copy into the second half first. */
2028 return "mov.l %T1,%T0\n\tmov.l %1,%0";
2031 return "mov.l %1,%0\n\tmov.l %T1,%T0";
2034 /* Print an instruction which would have gone into a delay slot after
2035 another instruction, but couldn't because the other instruction expanded
2036 into a sequence where putting the slot insn at the end wouldn't work. */
2039 print_slot (rtx insn)
2041 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
2043 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
2047 output_far_jump (rtx insn, rtx op)
2049 struct { rtx lab, reg, op; } this_jmp;
2050 rtx braf_base_lab = NULL_RTX;
2053 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2056 this_jmp.lab = gen_label_rtx ();
2060 && offset - get_attr_length (insn) <= 32766)
2063 jump = "mov.w %O0,%1; braf %1";
2071 jump = "mov.l %O0,%1; braf %1";
2073 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2076 jump = "mov.l %O0,%1; jmp @%1";
2078 /* If we have a scratch register available, use it. */
2079 if (GET_CODE ((prev = prev_nonnote_insn (insn))) == INSN
2080 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2082 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2083 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
2084 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
2085 output_asm_insn (jump, &this_jmp.lab);
2086 if (dbr_sequence_length ())
2087 print_slot (final_sequence);
2089 output_asm_insn ("nop", 0);
2093 /* Output the delay slot insn first if any. */
2094 if (dbr_sequence_length ())
2095 print_slot (final_sequence);
2097 this_jmp.reg = gen_rtx_REG (SImode, 13);
2098 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2099 Fortunately, MACL is fixed and call-clobbered, and we never
2100 need its value across jumps, so save r13 in it instead of in
2103 output_asm_insn ("lds r13, macl", 0);
2105 output_asm_insn ("mov.l r13,@-r15", 0);
2106 output_asm_insn (jump, &this_jmp.lab);
2108 output_asm_insn ("sts macl, r13", 0);
2110 output_asm_insn ("mov.l @r15+,r13", 0);
2112 if (far && flag_pic && TARGET_SH2)
2114 braf_base_lab = gen_label_rtx ();
2115 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2116 CODE_LABEL_NUMBER (braf_base_lab));
2119 output_asm_insn (".align 2", 0);
2120 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2122 if (far && flag_pic)
2125 this_jmp.lab = braf_base_lab;
2126 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
2129 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2133 /* Local label counter, used for constants in the pool and inside
2134 pattern branches. */
2136 static int lf = 100;
2138 /* Output code for ordinary branches. */
2141 output_branch (int logic, rtx insn, rtx *operands)
2143 switch (get_attr_length (insn))
2146 /* This can happen if filling the delay slot has caused a forward
2147 branch to exceed its range (we could reverse it, but only
2148 when we know we won't overextend other branches; this should
2149 best be handled by relaxation).
2150 It can also happen when other condbranches hoist delay slot insn
2151 from their destination, thus leading to code size increase.
2152 But the branch will still be in the range -4092..+4098 bytes. */
2157 /* The call to print_slot will clobber the operands. */
2158 rtx op0 = operands[0];
2160 /* If the instruction in the delay slot is annulled (true), then
2161 there is no delay slot where we can put it now. The only safe
2162 place for it is after the label. final will do that by default. */
2165 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2166 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2168 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2169 ASSEMBLER_DIALECT ? "/" : ".", label);
2170 print_slot (final_sequence);
2173 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2175 output_asm_insn ("bra\t%l0", &op0);
2176 fprintf (asm_out_file, "\tnop\n");
2177 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2181 /* When relaxing, handle this like a short branch. The linker
2182 will fix it up if it still doesn't fit after relaxation. */
2184 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2186 /* These are for SH2e, in which we have to account for the
2187 extra nop because of the hardware bug in annulled branches. */
2193 gcc_assert (!final_sequence
2194 || !(INSN_ANNULLED_BRANCH_P
2195 (XVECEXP (final_sequence, 0, 0))));
2196 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2198 ASSEMBLER_DIALECT ? "/" : ".", label);
2199 fprintf (asm_out_file, "\tnop\n");
2200 output_asm_insn ("bra\t%l0", operands);
2201 fprintf (asm_out_file, "\tnop\n");
2202 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2206 /* When relaxing, fall through. */
2211 sprintf (buffer, "b%s%ss\t%%l0",
2213 ASSEMBLER_DIALECT ? "/" : ".");
2214 output_asm_insn (buffer, &operands[0]);
2219 /* There should be no longer branches now - that would
2220 indicate that something has destroyed the branches set
2221 up in machine_dependent_reorg. */
2226 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2227 fill in operands 9 as a label to the successor insn.
2228 We try to use jump threading where possible.
2229 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2230 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2231 follow jmp and bt, if the address is in range. */
2233 output_branchy_insn (enum rtx_code code, const char *templ,
2234 rtx insn, rtx *operands)
2236 rtx next_insn = NEXT_INSN (insn);
2238 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
2240 rtx src = SET_SRC (PATTERN (next_insn));
2241 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2243 /* Following branch not taken */
2244 operands[9] = gen_label_rtx ();
2245 emit_label_after (operands[9], next_insn);
2246 INSN_ADDRESSES_NEW (operands[9],
2247 INSN_ADDRESSES (INSN_UID (next_insn))
2248 + get_attr_length (next_insn));
2253 int offset = (branch_dest (next_insn)
2254 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2255 if (offset >= -252 && offset <= 258)
2257 if (GET_CODE (src) == IF_THEN_ELSE)
2259 src = XEXP (src, 1);
2265 operands[9] = gen_label_rtx ();
2266 emit_label_after (operands[9], insn);
2267 INSN_ADDRESSES_NEW (operands[9],
2268 INSN_ADDRESSES (INSN_UID (insn))
2269 + get_attr_length (insn));
2274 output_ieee_ccmpeq (rtx insn, rtx *operands)
2276 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2280 /* Output the start of the assembler file. */
2283 sh_file_start (void)
2285 default_file_start ();
2288 /* Declare the .directive section before it is used. */
2289 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2290 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2294 /* We need to show the text section with the proper
2295 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2296 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2297 will complain. We can teach GAS specifically about the
2298 default attributes for our choice of text section, but
2299 then we would have to change GAS again if/when we change
2300 the text section name. */
2301 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2303 /* Switch to the data section so that the coffsem symbol
2304 isn't in the text section. */
2305 switch_to_section (data_section);
2307 if (TARGET_LITTLE_ENDIAN)
2308 fputs ("\t.little\n", asm_out_file);
2312 if (TARGET_SHCOMPACT)
2313 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2314 else if (TARGET_SHMEDIA)
2315 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2316 TARGET_SHMEDIA64 ? 64 : 32);
2320 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2323 unspec_caller_rtx_p (rtx pat)
2328 split_const (pat, &base, &offset);
2329 if (GET_CODE (base) == UNSPEC)
2331 if (XINT (base, 1) == UNSPEC_CALLER)
2333 for (i = 0; i < XVECLEN (base, 0); i++)
2334 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2340 /* Indicate that INSN cannot be duplicated. This is true for insn
2341 that generates a unique label. */
2344 sh_cannot_copy_insn_p (rtx insn)
2348 if (!reload_completed || !flag_pic)
2351 if (GET_CODE (insn) != INSN)
2353 if (asm_noperands (insn) >= 0)
2356 pat = PATTERN (insn);
2357 if (GET_CODE (pat) != SET)
2359 pat = SET_SRC (pat);
2361 if (unspec_caller_rtx_p (pat))
2367 /* Actual number of instructions used to make a shift by N. */
2368 static const char ashiftrt_insns[] =
2369 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2371 /* Left shift and logical right shift are the same. */
2372 static const char shift_insns[] =
2373 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2375 /* Individual shift amounts needed to get the above length sequences.
2376 One bit right shifts clobber the T bit, so when possible, put one bit
2377 shifts in the middle of the sequence, so the ends are eligible for
2378 branch delay slots. */
2379 static const short shift_amounts[32][5] = {
2380 {0}, {1}, {2}, {2, 1},
2381 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2382 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2383 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2384 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2385 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2386 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2387 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2389 /* Likewise, but for shift amounts < 16, up to three highmost bits
2390 might be clobbered. This is typically used when combined with some
2391 kind of sign or zero extension. */
2393 static const char ext_shift_insns[] =
2394 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2396 static const short ext_shift_amounts[32][4] = {
2397 {0}, {1}, {2}, {2, 1},
2398 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2399 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2400 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2401 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2402 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2403 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2404 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2406 /* Assuming we have a value that has been sign-extended by at least one bit,
2407 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2408 to shift it by N without data loss, and quicker than by other means? */
2409 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2411 /* This is used in length attributes in sh.md to help compute the length
2412 of arbitrary constant shift instructions. */
2415 shift_insns_rtx (rtx insn)
2417 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2418 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
2419 enum rtx_code shift_code = GET_CODE (set_src);
2424 return ashiftrt_insns[shift_count];
2427 return shift_insns[shift_count];
2433 /* Return the cost of a shift. */
2443 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2445 if (GET_MODE (x) == DImode
2446 && GET_CODE (XEXP (x, 1)) == CONST_INT
2447 && INTVAL (XEXP (x, 1)) == 1)
2450 /* Everything else is invalid, because there is no pattern for it. */
2453 /* If shift by a non constant, then this will be expensive. */
2454 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2455 return SH_DYNAMIC_SHIFT_COST;
2457 /* Otherwise, return the true cost in instructions. Cope with out of range
2458 shift counts more or less arbitrarily. */
2459 value = INTVAL (XEXP (x, 1)) & 31;
2461 if (GET_CODE (x) == ASHIFTRT)
2463 int cost = ashiftrt_insns[value];
2464 /* If SH3, then we put the constant in a reg and use shad. */
2465 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2466 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2470 return shift_insns[value];
2473 /* Return the cost of an AND operation. */
2480 /* Anding with a register is a single cycle and instruction. */
2481 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2484 i = INTVAL (XEXP (x, 1));
2488 if (satisfies_constraint_I10 (XEXP (x, 1))
2489 || satisfies_constraint_J16 (XEXP (x, 1)))
2492 return 1 + rtx_cost (XEXP (x, 1), AND, !optimize_size);
2495 /* These constants are single cycle extu.[bw] instructions. */
2496 if (i == 0xff || i == 0xffff)
2498 /* Constants that can be used in an and immediate instruction in a single
2499 cycle, but this requires r0, so make it a little more expensive. */
2500 if (CONST_OK_FOR_K08 (i))
2502 /* Constants that can be loaded with a mov immediate and an and.
2503 This case is probably unnecessary. */
2504 if (CONST_OK_FOR_I08 (i))
2506 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2507 This case is probably unnecessary. */
2511 /* Return the cost of an addition or a subtraction. */
2516 /* Adding a register is a single cycle insn. */
2517 if (GET_CODE (XEXP (x, 1)) == REG
2518 || GET_CODE (XEXP (x, 1)) == SUBREG)
2521 /* Likewise for small constants. */
2522 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2523 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2527 switch (GET_CODE (XEXP (x, 1)))
2532 return TARGET_SHMEDIA64 ? 5 : 3;
2535 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2537 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2539 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2547 /* Any other constant requires a 2 cycle pc-relative load plus an
2552 /* Return the cost of a multiply. */
2554 multcosts (rtx x ATTRIBUTE_UNUSED)
2556 if (sh_multcost >= 0)
2559 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2560 accept constants. Ideally, we would use a cost of one or two and
2561 add the cost of the operand, but disregard the latter when inside loops
2562 and loop invariant code motion is still to follow.
2563 Using a multiply first and splitting it later if it's a loss
2564 doesn't work because of different sign / zero extension semantics
2565 of multiplies vs. shifts. */
2566 return TARGET_SMALLCODE ? 2 : 3;
2570 /* We have a mul insn, so we can never take more than the mul and the
2571 read of the mac reg, but count more because of the latency and extra
2573 if (TARGET_SMALLCODE)
2578 /* If we're aiming at small code, then just count the number of
2579 insns in a multiply call sequence. */
2580 if (TARGET_SMALLCODE)
2583 /* Otherwise count all the insns in the routine we'd be calling too. */
2587 /* Compute a (partial) cost for rtx X. Return true if the complete
2588 cost has been computed, and false if subexpressions should be
2589 scanned. In either case, *TOTAL contains the cost result. */
2592 sh_rtx_costs (rtx x, int code, int outer_code, int *total,
2593 bool speed ATTRIBUTE_UNUSED)
2600 if (INTVAL (x) == 0)
2602 else if (outer_code == AND && and_operand ((x), DImode))
2604 else if ((outer_code == IOR || outer_code == XOR
2605 || outer_code == PLUS)
2606 && CONST_OK_FOR_I10 (INTVAL (x)))
2608 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2609 *total = COSTS_N_INSNS (outer_code != SET);
2610 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2611 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2612 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2613 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2615 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2618 if (CONST_OK_FOR_I08 (INTVAL (x)))
2620 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2621 && CONST_OK_FOR_K08 (INTVAL (x)))
2623 /* prepare_cmp_insn will force costly constants int registers before
2624 the cbranch[sd]i4 patterns can see them, so preserve potentially
2625 interesting ones not covered by I08 above. */
2626 else if (outer_code == COMPARE
2627 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2628 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2629 || INTVAL (x) == 0x7fffffff
2630 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2639 if (TARGET_SHMEDIA64)
2640 *total = COSTS_N_INSNS (4);
2641 else if (TARGET_SHMEDIA32)
2642 *total = COSTS_N_INSNS (2);
2649 *total = COSTS_N_INSNS (4);
2650 /* prepare_cmp_insn will force costly constants int registers before
2651 the cbranchdi4 pattern can see them, so preserve potentially
2652 interesting ones. */
2653 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
2659 if (x == CONST0_RTX (GET_MODE (x)))
2661 else if (sh_1el_vec (x, VOIDmode))
2662 *total = outer_code != SET;
2663 if (sh_rep_vec (x, VOIDmode))
2664 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2665 + (outer_code != SET));
2666 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2671 *total = COSTS_N_INSNS (addsubcosts (x));
2675 *total = COSTS_N_INSNS (andcosts (x));
2679 *total = COSTS_N_INSNS (multcosts (x));
2685 *total = COSTS_N_INSNS (shiftcosts (x));
2692 *total = COSTS_N_INSNS (20);
2696 if (sh_1el_vec (x, VOIDmode))
2697 *total = outer_code != SET;
2698 if (sh_rep_vec (x, VOIDmode))
2699 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2700 + (outer_code != SET));
2701 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2714 /* Compute the cost of an address. For the SH, all valid addresses are
2715 the same cost. Use a slightly higher cost for reg + reg addressing,
2716 since it increases pressure on r0. */
2719 sh_address_cost (rtx X,
2720 bool speed ATTRIBUTE_UNUSED)
2722 return (GET_CODE (X) == PLUS
2723 && ! CONSTANT_P (XEXP (X, 1))
2724 && ! TARGET_SHMEDIA ? 1 : 0);
2727 /* Code to expand a shift. */
2730 gen_ashift (int type, int n, rtx reg)
2732 /* Negative values here come from the shift_amounts array. */
2745 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
2749 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
2751 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
2754 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
2759 /* Same for HImode */
2762 gen_ashift_hi (int type, int n, rtx reg)
2764 /* Negative values here come from the shift_amounts array. */
2778 /* We don't have HImode right shift operations because using the
2779 ordinary 32 bit shift instructions for that doesn't generate proper
2780 zero/sign extension.
2781 gen_ashift_hi is only called in contexts where we know that the
2782 sign extension works out correctly. */
2785 if (GET_CODE (reg) == SUBREG)
2787 offset = SUBREG_BYTE (reg);
2788 reg = SUBREG_REG (reg);
2790 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
2794 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
2799 /* Output RTL to split a constant shift into its component SH constant
2800 shift instructions. */
2803 gen_shifty_op (int code, rtx *operands)
2805 int value = INTVAL (operands[2]);
2808 /* Truncate the shift count in case it is out of bounds. */
2813 if (code == LSHIFTRT)
2815 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2816 emit_insn (gen_movt (operands[0]));
2819 else if (code == ASHIFT)
2821 /* There is a two instruction sequence for 31 bit left shifts,
2822 but it requires r0. */
2823 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
2825 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
2826 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2831 else if (value == 0)
2833 /* This can happen even when optimizing, if there were subregs before
2834 reload. Don't output a nop here, as this is never optimized away;
2835 use a no-op move instead. */
2836 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
2840 max = shift_insns[value];
2841 for (i = 0; i < max; i++)
2842 gen_ashift (code, shift_amounts[value][i], operands[0]);
2845 /* Same as above, but optimized for values where the topmost bits don't
2849 gen_shifty_hi_op (int code, rtx *operands)
2851 int value = INTVAL (operands[2]);
2853 void (*gen_fun) (int, int, rtx);
2855 /* This operation is used by and_shl for SImode values with a few
2856 high bits known to be cleared. */
2860 emit_insn (gen_nop ());
2864 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
2867 max = ext_shift_insns[value];
2868 for (i = 0; i < max; i++)
2869 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2872 /* When shifting right, emit the shifts in reverse order, so that
2873 solitary negative values come first. */
2874 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
2875 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2878 /* Output RTL for an arithmetic right shift. */
2880 /* ??? Rewrite to use super-optimizer sequences. */
2883 expand_ashiftrt (rtx *operands)
2891 if (GET_CODE (operands[2]) != CONST_INT)
2893 rtx count = copy_to_mode_reg (SImode, operands[2]);
2894 emit_insn (gen_negsi2 (count, count));
2895 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2898 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
2899 > 1 + SH_DYNAMIC_SHIFT_COST)
2902 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
2903 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2907 if (GET_CODE (operands[2]) != CONST_INT)
2910 value = INTVAL (operands[2]) & 31;
2914 /* If we are called from abs expansion, arrange things so that we
2915 we can use a single MT instruction that doesn't clobber the source,
2916 if LICM can hoist out the load of the constant zero. */
2917 if (currently_expanding_to_rtl)
2919 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
2921 emit_insn (gen_mov_neg_si_t (operands[0]));
2924 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
2927 else if (value >= 16 && value <= 19)
2929 wrk = gen_reg_rtx (SImode);
2930 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
2933 gen_ashift (ASHIFTRT, 1, wrk);
2934 emit_move_insn (operands[0], wrk);
2937 /* Expand a short sequence inline, longer call a magic routine. */
2938 else if (value <= 5)
2940 wrk = gen_reg_rtx (SImode);
2941 emit_move_insn (wrk, operands[1]);
2943 gen_ashift (ASHIFTRT, 1, wrk);
2944 emit_move_insn (operands[0], wrk);
2948 wrk = gen_reg_rtx (Pmode);
2950 /* Load the value into an arg reg and call a helper. */
2951 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2952 sprintf (func, "__ashiftrt_r4_%d", value);
2953 function_symbol (wrk, func, SFUNC_STATIC);
2954 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
2955 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
2960 sh_dynamicalize_shift_p (rtx count)
2962 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
2965 /* Try to find a good way to implement the combiner pattern
2966 [(set (match_operand:SI 0 "register_operand" "r")
2967 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2968 (match_operand:SI 2 "const_int_operand" "n"))
2969 (match_operand:SI 3 "const_int_operand" "n"))) .
2970 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
2971 return 0 for simple right / left or left/right shift combination.
2972 return 1 for a combination of shifts with zero_extend.
2973 return 2 for a combination of shifts with an AND that needs r0.
2974 return 3 for a combination of shifts with an AND that needs an extra
2975 scratch register, when the three highmost bits of the AND mask are clear.
2976 return 4 for a combination of shifts with an AND that needs an extra
2977 scratch register, when any of the three highmost bits of the AND mask
2979 If ATTRP is set, store an initial right shift width in ATTRP[0],
2980 and the instruction length in ATTRP[1] . These values are not valid
2982 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
2983 shift_amounts for the last shift value that is to be used before the
2986 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
2988 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
2989 int left = INTVAL (left_rtx), right;
2991 int cost, best_cost = 10000;
2992 int best_right = 0, best_len = 0;
2996 if (left < 0 || left > 31)
2998 if (GET_CODE (mask_rtx) == CONST_INT)
2999 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3001 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
3002 /* Can this be expressed as a right shift / left shift pair? */
3003 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3004 right = exact_log2 (lsb);
3005 mask2 = ~(mask + lsb - 1);
3006 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3007 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3009 best_cost = shift_insns[right] + shift_insns[right + left];
3010 /* mask has no trailing zeroes <==> ! right */
3011 else if (! right && mask2 == ~(lsb2 - 1))
3013 int late_right = exact_log2 (lsb2);
3014 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
3016 /* Try to use zero extend. */
3017 if (mask2 == ~(lsb2 - 1))
3021 for (width = 8; width <= 16; width += 8)
3023 /* Can we zero-extend right away? */
3024 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
3027 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
3028 if (cost < best_cost)
3039 /* ??? Could try to put zero extend into initial right shift,
3040 or even shift a bit left before the right shift. */
3041 /* Determine value of first part of left shift, to get to the
3042 zero extend cut-off point. */
3043 first = width - exact_log2 (lsb2) + right;
3044 if (first >= 0 && right + left - first >= 0)
3046 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
3047 + ext_shift_insns[right + left - first];
3048 if (cost < best_cost)
3060 /* Try to use r0 AND pattern */
3061 for (i = 0; i <= 2; i++)
3065 if (! CONST_OK_FOR_K08 (mask >> i))
3067 cost = (i != 0) + 2 + ext_shift_insns[left + i];
3068 if (cost < best_cost)
3073 best_len = cost - 1;
3076 /* Try to use a scratch register to hold the AND operand. */
3077 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
3078 for (i = 0; i <= 2; i++)
3082 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
3083 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
3084 if (cost < best_cost)
3089 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
3095 attrp[0] = best_right;
3096 attrp[1] = best_len;
3101 /* This is used in length attributes of the unnamed instructions
3102 corresponding to shl_and_kind return values of 1 and 2. */
3104 shl_and_length (rtx insn)
3106 rtx set_src, left_rtx, mask_rtx;
3109 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3110 left_rtx = XEXP (XEXP (set_src, 0), 1);
3111 mask_rtx = XEXP (set_src, 1);
3112 shl_and_kind (left_rtx, mask_rtx, attributes);
3113 return attributes[1];
3116 /* This is used in length attribute of the and_shl_scratch instruction. */
3119 shl_and_scr_length (rtx insn)
3121 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3122 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
3123 rtx op = XEXP (set_src, 0);
3124 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
3125 op = XEXP (XEXP (op, 0), 0);
3126 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
3129 /* Generate rtl for instructions for which shl_and_kind advised a particular
3130 method of generating them, i.e. returned zero. */
3133 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
3136 unsigned HOST_WIDE_INT mask;
3137 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3138 int right, total_shift;
3139 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
3141 right = attributes[0];
3142 total_shift = INTVAL (left_rtx) + right;
3143 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3150 int first = attributes[2];
3155 emit_insn ((mask << right) <= 0xff
3156 ? gen_zero_extendqisi2 (dest,
3157 gen_lowpart (QImode, source))
3158 : gen_zero_extendhisi2 (dest,
3159 gen_lowpart (HImode, source)));
3163 emit_insn (gen_movsi (dest, source));
3167 operands[2] = GEN_INT (right);
3168 gen_shifty_hi_op (LSHIFTRT, operands);
3172 operands[2] = GEN_INT (first);
3173 gen_shifty_hi_op (ASHIFT, operands);
3174 total_shift -= first;
3178 emit_insn (mask <= 0xff
3179 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3180 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3181 if (total_shift > 0)
3183 operands[2] = GEN_INT (total_shift);
3184 gen_shifty_hi_op (ASHIFT, operands);
3189 shift_gen_fun = gen_shifty_op;
3191 /* If the topmost bit that matters is set, set the topmost bits
3192 that don't matter. This way, we might be able to get a shorter
3194 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3195 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3197 /* Don't expand fine-grained when combining, because that will
3198 make the pattern fail. */
3199 if (currently_expanding_to_rtl
3200 || reload_in_progress || reload_completed)
3204 /* Cases 3 and 4 should be handled by this split
3205 only while combining */
3206 gcc_assert (kind <= 2);
3209 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3212 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3217 operands[2] = GEN_INT (total_shift);
3218 shift_gen_fun (ASHIFT, operands);
3225 if (kind != 4 && total_shift < 16)
3227 neg = -ext_shift_amounts[total_shift][1];
3229 neg -= ext_shift_amounts[total_shift][2];
3233 emit_insn (gen_and_shl_scratch (dest, source,
3236 GEN_INT (total_shift + neg),
3238 emit_insn (gen_movsi (dest, dest));
3245 /* Try to find a good way to implement the combiner pattern
3246 [(set (match_operand:SI 0 "register_operand" "=r")
3247 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3248 (match_operand:SI 2 "const_int_operand" "n")
3249 (match_operand:SI 3 "const_int_operand" "n")
3251 (clobber (reg:SI T_REG))]
3252 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3253 return 0 for simple left / right shift combination.
3254 return 1 for left shift / 8 bit sign extend / left shift.
3255 return 2 for left shift / 16 bit sign extend / left shift.
3256 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3257 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3258 return 5 for left shift / 16 bit sign extend / right shift
3259 return 6 for < 8 bit sign extend / left shift.
3260 return 7 for < 8 bit sign extend / left shift / single right shift.
3261 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3264 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3266 int left, size, insize, ext;
3267 int cost = 0, best_cost;
3270 left = INTVAL (left_rtx);
3271 size = INTVAL (size_rtx);
3272 insize = size - left;
3273 gcc_assert (insize > 0);
3274 /* Default to left / right shift. */
3276 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3279 /* 16 bit shift / sign extend / 16 bit shift */
3280 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3281 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3282 below, by alternative 3 or something even better. */
3283 if (cost < best_cost)
3289 /* Try a plain sign extend between two shifts. */
3290 for (ext = 16; ext >= insize; ext -= 8)
3294 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3295 if (cost < best_cost)
3297 kind = ext / (unsigned) 8;
3301 /* Check if we can do a sloppy shift with a final signed shift
3302 restoring the sign. */
3303 if (EXT_SHIFT_SIGNED (size - ext))
3304 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3305 /* If not, maybe it's still cheaper to do the second shift sloppy,
3306 and do a final sign extend? */
3307 else if (size <= 16)
3308 cost = ext_shift_insns[ext - insize] + 1
3309 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3312 if (cost < best_cost)
3314 kind = ext / (unsigned) 8 + 2;
3318 /* Check if we can sign extend in r0 */
3321 cost = 3 + shift_insns[left];
3322 if (cost < best_cost)
3327 /* Try the same with a final signed shift. */
3330 cost = 3 + ext_shift_insns[left + 1] + 1;
3331 if (cost < best_cost)
3340 /* Try to use a dynamic shift. */
3341 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3342 if (cost < best_cost)
3353 /* Function to be used in the length attribute of the instructions
3354 implementing this pattern. */
3357 shl_sext_length (rtx insn)
3359 rtx set_src, left_rtx, size_rtx;
3362 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3363 left_rtx = XEXP (XEXP (set_src, 0), 1);
3364 size_rtx = XEXP (set_src, 1);
3365 shl_sext_kind (left_rtx, size_rtx, &cost);
3369 /* Generate rtl for this pattern */
3372 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3375 int left, size, insize, cost;
3378 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3379 left = INTVAL (left_rtx);
3380 size = INTVAL (size_rtx);
3381 insize = size - left;
3389 int ext = kind & 1 ? 8 : 16;
3390 int shift2 = size - ext;
3392 /* Don't expand fine-grained when combining, because that will
3393 make the pattern fail. */
3394 if (! currently_expanding_to_rtl
3395 && ! reload_in_progress && ! reload_completed)
3397 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3398 emit_insn (gen_movsi (dest, source));
3402 emit_insn (gen_movsi (dest, source));
3406 operands[2] = GEN_INT (ext - insize);
3407 gen_shifty_hi_op (ASHIFT, operands);
3410 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3411 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3416 operands[2] = GEN_INT (shift2);
3417 gen_shifty_op (ASHIFT, operands);
3424 if (EXT_SHIFT_SIGNED (shift2))
3426 operands[2] = GEN_INT (shift2 + 1);
3427 gen_shifty_op (ASHIFT, operands);
3428 operands[2] = const1_rtx;
3429 gen_shifty_op (ASHIFTRT, operands);
3432 operands[2] = GEN_INT (shift2);
3433 gen_shifty_hi_op (ASHIFT, operands);
3437 operands[2] = GEN_INT (-shift2);
3438 gen_shifty_hi_op (LSHIFTRT, operands);
3440 emit_insn (size <= 8
3441 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3442 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3449 if (! currently_expanding_to_rtl
3450 && ! reload_in_progress && ! reload_completed)
3451 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3455 operands[2] = GEN_INT (16 - insize);
3456 gen_shifty_hi_op (ASHIFT, operands);
3457 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3459 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3461 gen_ashift (ASHIFTRT, 1, dest);
3466 /* Don't expand fine-grained when combining, because that will
3467 make the pattern fail. */
3468 if (! currently_expanding_to_rtl
3469 && ! reload_in_progress && ! reload_completed)
3471 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3472 emit_insn (gen_movsi (dest, source));
3475 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3476 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3477 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3479 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3480 gen_shifty_op (ASHIFT, operands);
3482 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3490 /* Prefix a symbol_ref name with "datalabel". */
3493 gen_datalabel_ref (rtx sym)
3497 if (GET_CODE (sym) == LABEL_REF)
3498 return gen_rtx_CONST (GET_MODE (sym),
3499 gen_rtx_UNSPEC (GET_MODE (sym),
3503 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3505 str = XSTR (sym, 0);
3506 /* Share all SYMBOL_REF strings with the same value - that is important
3508 str = IDENTIFIER_POINTER (get_identifier (str));
3509 XSTR (sym, 0) = str;
3515 static alloc_pool label_ref_list_pool;
3517 typedef struct label_ref_list_d
3520 struct label_ref_list_d *next;
3521 } *label_ref_list_t;
3523 /* The SH cannot load a large constant into a register, constants have to
3524 come from a pc relative load. The reference of a pc relative load
3525 instruction must be less than 1k in front of the instruction. This
3526 means that we often have to dump a constant inside a function, and
3527 generate code to branch around it.
3529 It is important to minimize this, since the branches will slow things
3530 down and make things bigger.
3532 Worst case code looks like:
3550 We fix this by performing a scan before scheduling, which notices which
3551 instructions need to have their operands fetched from the constant table
3552 and builds the table.
3556 scan, find an instruction which needs a pcrel move. Look forward, find the
3557 last barrier which is within MAX_COUNT bytes of the requirement.
3558 If there isn't one, make one. Process all the instructions between
3559 the find and the barrier.
3561 In the above example, we can tell that L3 is within 1k of L1, so
3562 the first move can be shrunk from the 3 insn+constant sequence into
3563 just 1 insn, and the constant moved to L3 to make:
3574 Then the second move becomes the target for the shortening process. */
3578 rtx value; /* Value in table. */
3579 rtx label; /* Label of value. */
3580 label_ref_list_t wend; /* End of window. */
3581 enum machine_mode mode; /* Mode of value. */
3583 /* True if this constant is accessed as part of a post-increment
3584 sequence. Note that HImode constants are never accessed in this way. */
3585 bool part_of_sequence_p;
3588 /* The maximum number of constants that can fit into one pool, since
3589 constants in the range 0..510 are at least 2 bytes long, and in the
3590 range from there to 1018 at least 4 bytes. */
3592 #define MAX_POOL_SIZE 372
3593 static pool_node pool_vector[MAX_POOL_SIZE];
3594 static int pool_size;
3595 static rtx pool_window_label;
3596 static int pool_window_last;
3598 static int max_labelno_before_reorg;
3600 /* ??? If we need a constant in HImode which is the truncated value of a
3601 constant we need in SImode, we could combine the two entries thus saving
3602 two bytes. Is this common enough to be worth the effort of implementing
3605 /* ??? This stuff should be done at the same time that we shorten branches.
3606 As it is now, we must assume that all branches are the maximum size, and
3607 this causes us to almost always output constant pools sooner than
3610 /* Add a constant to the pool and return its label. */
3613 add_constant (rtx x, enum machine_mode mode, rtx last_value)
3617 label_ref_list_t ref, newref;
3619 /* First see if we've already got it. */
3620 for (i = 0; i < pool_size; i++)
3622 if (x->code == pool_vector[i].value->code
3623 && mode == pool_vector[i].mode)
3625 if (x->code == CODE_LABEL)
3627 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3630 if (rtx_equal_p (x, pool_vector[i].value))
3635 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3637 new_rtx = gen_label_rtx ();
3638 LABEL_REFS (new_rtx) = pool_vector[i].label;
3639 pool_vector[i].label = lab = new_rtx;
3641 if (lab && pool_window_label)
3643 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3644 newref->label = pool_window_label;
3645 ref = pool_vector[pool_window_last].wend;
3647 pool_vector[pool_window_last].wend = newref;
3650 pool_window_label = new_rtx;
3651 pool_window_last = i;
3657 /* Need a new one. */
3658 pool_vector[pool_size].value = x;
3659 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3662 pool_vector[pool_size - 1].part_of_sequence_p = true;
3665 lab = gen_label_rtx ();
3666 pool_vector[pool_size].mode = mode;
3667 pool_vector[pool_size].label = lab;
3668 pool_vector[pool_size].wend = NULL;
3669 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
3670 if (lab && pool_window_label)
3672 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3673 newref->label = pool_window_label;
3674 ref = pool_vector[pool_window_last].wend;
3676 pool_vector[pool_window_last].wend = newref;
3679 pool_window_label = lab;
3680 pool_window_last = pool_size;
3685 /* Output the literal table. START, if nonzero, is the first instruction
3686 this table is needed for, and also indicates that there is at least one
3687 casesi_worker_2 instruction; We have to emit the operand3 labels from
3688 these insns at a 4-byte aligned position. BARRIER is the barrier
3689 after which we are to place the table. */
3692 dump_table (rtx start, rtx barrier)
3698 label_ref_list_t ref;
3701 /* Do two passes, first time dump out the HI sized constants. */
3703 for (i = 0; i < pool_size; i++)
3705 pool_node *p = &pool_vector[i];
3707 if (p->mode == HImode)
3711 scan = emit_insn_after (gen_align_2 (), scan);
3714 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3715 scan = emit_label_after (lab, scan);
3716 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
3718 for (ref = p->wend; ref; ref = ref->next)
3721 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3724 else if (p->mode == DFmode)
3732 scan = emit_insn_after (gen_align_4 (), scan);
3734 for (; start != barrier; start = NEXT_INSN (start))
3735 if (GET_CODE (start) == INSN
3736 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
3738 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
3739 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
3741 scan = emit_label_after (lab, scan);
3744 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
3746 rtx align_insn = NULL_RTX;
3748 scan = emit_label_after (gen_label_rtx (), scan);
3749 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3752 for (i = 0; i < pool_size; i++)
3754 pool_node *p = &pool_vector[i];
3762 if (align_insn && !p->part_of_sequence_p)
3764 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3765 emit_label_before (lab, align_insn);
3766 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
3768 for (ref = p->wend; ref; ref = ref->next)
3771 emit_insn_before (gen_consttable_window_end (lab),
3774 delete_insn (align_insn);
3775 align_insn = NULL_RTX;
3780 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3781 scan = emit_label_after (lab, scan);
3782 scan = emit_insn_after (gen_consttable_4 (p->value,
3784 need_align = ! need_align;
3790 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3795 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3796 scan = emit_label_after (lab, scan);
3797 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3804 if (p->mode != HImode)
3806 for (ref = p->wend; ref; ref = ref->next)
3809 scan = emit_insn_after (gen_consttable_window_end (lab),
3818 for (i = 0; i < pool_size; i++)
3820 pool_node *p = &pool_vector[i];
3831 scan = emit_label_after (gen_label_rtx (), scan);
3832 scan = emit_insn_after (gen_align_4 (), scan);
3834 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3835 scan = emit_label_after (lab, scan);
3836 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
3844 scan = emit_label_after (gen_label_rtx (), scan);
3845 scan = emit_insn_after (gen_align_4 (), scan);
3847 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3848 scan = emit_label_after (lab, scan);
3849 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3856 if (p->mode != HImode)
3858 for (ref = p->wend; ref; ref = ref->next)
3861 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3866 scan = emit_insn_after (gen_consttable_end (), scan);
3867 scan = emit_barrier_after (scan);
3869 pool_window_label = NULL_RTX;
3870 pool_window_last = 0;
3873 /* Return nonzero if constant would be an ok source for a
3874 mov.w instead of a mov.l. */
3879 return (GET_CODE (src) == CONST_INT
3880 && INTVAL (src) >= -32768
3881 && INTVAL (src) <= 32767);
3884 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
3886 /* Nonzero if the insn is a move instruction which needs to be fixed. */
3888 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
3889 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
3890 need to fix it if the input value is CONST_OK_FOR_I08. */
3893 broken_move (rtx insn)
3895 if (GET_CODE (insn) == INSN)
3897 rtx pat = PATTERN (insn);
3898 if (GET_CODE (pat) == PARALLEL)
3899 pat = XVECEXP (pat, 0, 0);
3900 if (GET_CODE (pat) == SET
3901 /* We can load any 8-bit value if we don't care what the high
3902 order bits end up as. */
3903 && GET_MODE (SET_DEST (pat)) != QImode
3904 && (CONSTANT_P (SET_SRC (pat))
3905 /* Match mova_const. */
3906 || (GET_CODE (SET_SRC (pat)) == UNSPEC
3907 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
3908 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
3910 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
3911 && (fp_zero_operand (SET_SRC (pat))
3912 || fp_one_operand (SET_SRC (pat)))
3913 /* ??? If this is a -m4 or -m4-single compilation, in general
3914 we don't know the current setting of fpscr, so disable fldi.
3915 There is an exception if this was a register-register move
3916 before reload - and hence it was ascertained that we have
3917 single precision setting - and in a post-reload optimization
3918 we changed this to do a constant load. In that case
3919 we don't have an r0 clobber, hence we must use fldi. */
3920 && (! TARGET_SH4 || TARGET_FMOVD
3921 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
3923 && GET_CODE (SET_DEST (pat)) == REG
3924 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
3926 && GET_MODE (SET_DEST (pat)) == SImode
3927 && (satisfies_constraint_I20 (SET_SRC (pat))
3928 || satisfies_constraint_I28 (SET_SRC (pat))))
3929 && ! satisfies_constraint_I08 (SET_SRC (pat)))
3939 return (GET_CODE (insn) == INSN
3940 && GET_CODE (PATTERN (insn)) == SET
3941 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
3942 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
3943 /* Don't match mova_const. */
3944 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
3947 /* Fix up a mova from a switch that went out of range. */
3949 fixup_mova (rtx mova)
3951 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
3954 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
3955 INSN_CODE (mova) = -1;
3960 rtx lab = gen_label_rtx ();
3961 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
3965 worker = NEXT_INSN (worker);
3967 && GET_CODE (worker) != CODE_LABEL
3968 && GET_CODE (worker) != JUMP_INSN);
3969 } while (GET_CODE (worker) == NOTE
3970 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
3971 wpat = PATTERN (worker);
3972 wpat0 = XVECEXP (wpat, 0, 0);
3973 wpat1 = XVECEXP (wpat, 0, 1);
3974 wsrc = SET_SRC (wpat0);
3975 PATTERN (worker) = (gen_casesi_worker_2
3976 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
3977 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
3979 INSN_CODE (worker) = -1;
3980 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3981 base = gen_rtx_LABEL_REF (Pmode, lab);
3982 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
3983 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
3984 INSN_CODE (mova) = -1;
3988 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
3989 *num_mova, and check if the new mova is not nested within the first one.
3990 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
3991 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
3993 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
3995 int n_addr = 0; /* Initialization to shut up spurious warning. */
3996 int f_target, n_target = 0; /* Likewise. */
4000 /* If NEW_MOVA has no address yet, it will be handled later. */
4001 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4004 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4005 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4006 if (n_addr > n_target || n_addr + 1022 < n_target)
4008 /* Change the mova into a load.
4009 broken_move will then return true for it. */
4010 fixup_mova (new_mova);
4016 *first_mova = new_mova;
4021 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4026 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4027 > n_target - n_addr)
4029 fixup_mova (*first_mova);
4034 fixup_mova (new_mova);
4039 /* Find the last barrier from insn FROM which is close enough to hold the
4040 constant pool. If we can't find one, then create one near the end of
4044 find_barrier (int num_mova, rtx mova, rtx from)
4053 int leading_mova = num_mova;
4054 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
4059 /* For HImode: range is 510, add 4 because pc counts from address of
4060 second instruction after this one, subtract 2 for the jump instruction
4061 that we may need to emit before the table, subtract 2 for the instruction
4062 that fills the jump delay slot (in very rare cases, reorg will take an
4063 instruction from after the constant pool or will leave the delay slot
4064 empty). This gives 510.
4065 For SImode: range is 1020, add 4 because pc counts from address of
4066 second instruction after this one, subtract 2 in case pc is 2 byte
4067 aligned, subtract 2 for the jump instruction that we may need to emit
4068 before the table, subtract 2 for the instruction that fills the jump
4069 delay slot. This gives 1018. */
4071 /* The branch will always be shortened now that the reference address for
4072 forward branches is the successor address, thus we need no longer make
4073 adjustments to the [sh]i_limit for -O0. */
4078 while (from && count_si < si_limit && count_hi < hi_limit)
4080 int inc = get_attr_length (from);
4083 /* If this is a label that existed at the time of the compute_alignments
4084 call, determine the alignment. N.B. When find_barrier recurses for
4085 an out-of-reach mova, we might see labels at the start of previously
4086 inserted constant tables. */
4087 if (GET_CODE (from) == CODE_LABEL
4088 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
4091 new_align = 1 << label_to_alignment (from);
4092 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
4093 new_align = 1 << barrier_align (from);
4098 /* In case we are scanning a constant table because of recursion, check
4099 for explicit alignments. If the table is long, we might be forced
4100 to emit the new table in front of it; the length of the alignment
4101 might be the last straw. */
4102 else if (GET_CODE (from) == INSN
4103 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4104 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4105 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4106 /* When we find the end of a constant table, paste the new constant
4107 at the end. That is better than putting it in front because
4108 this way, we don't need extra alignment for adding a 4-byte-aligned
4109 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4110 else if (GET_CODE (from) == INSN
4111 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4112 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4115 if (GET_CODE (from) == BARRIER)
4119 found_barrier = from;
4121 /* If we are at the end of the function, or in front of an alignment
4122 instruction, we need not insert an extra alignment. We prefer
4123 this kind of barrier. */
4124 if (barrier_align (from) > 2)
4125 good_barrier = from;
4127 /* If we are at the end of a hot/cold block, dump the constants
4129 next = NEXT_INSN (from);
4132 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4136 if (broken_move (from))
4139 enum machine_mode mode;
4141 pat = PATTERN (from);
4142 if (GET_CODE (pat) == PARALLEL)
4143 pat = XVECEXP (pat, 0, 0);
4144 src = SET_SRC (pat);
4145 dst = SET_DEST (pat);
4146 mode = GET_MODE (dst);
4148 /* We must explicitly check the mode, because sometimes the
4149 front end will generate code to load unsigned constants into
4150 HImode targets without properly sign extending them. */
4152 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
4155 /* We put the short constants before the long constants, so
4156 we must count the length of short constants in the range
4157 for the long constants. */
4158 /* ??? This isn't optimal, but is easy to do. */
4163 /* We dump DF/DI constants before SF/SI ones, because
4164 the limit is the same, but the alignment requirements
4165 are higher. We may waste up to 4 additional bytes
4166 for alignment, and the DF/DI constant may have
4167 another SF/SI constant placed before it. */
4168 if (TARGET_SHCOMPACT
4170 && (mode == DFmode || mode == DImode))
4175 while (si_align > 2 && found_si + si_align - 2 > count_si)
4177 if (found_si > count_si)
4178 count_si = found_si;
4179 found_si += GET_MODE_SIZE (mode);
4181 si_limit -= GET_MODE_SIZE (mode);
4187 switch (untangle_mova (&num_mova, &mova, from))
4189 case 0: return find_barrier (0, 0, mova);
4194 = good_barrier ? good_barrier : found_barrier;
4198 if (found_si > count_si)
4199 count_si = found_si;
4201 else if (GET_CODE (from) == JUMP_INSN
4202 && (GET_CODE (PATTERN (from)) == ADDR_VEC
4203 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
4205 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4207 && (prev_nonnote_insn (from)
4208 == XEXP (MOVA_LABELREF (mova), 0))))
4210 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4212 /* We have just passed the barrier in front of the
4213 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4214 the ADDR_DIFF_VEC is accessed as data, just like our pool
4215 constants, this is a good opportunity to accommodate what
4216 we have gathered so far.
4217 If we waited any longer, we could end up at a barrier in
4218 front of code, which gives worse cache usage for separated
4219 instruction / data caches. */
4220 good_barrier = found_barrier;
4225 rtx body = PATTERN (from);
4226 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4229 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4230 else if (GET_CODE (from) == JUMP_INSN
4232 && ! TARGET_SMALLCODE)
4238 if (new_align > si_align)
4240 si_limit -= (count_si - 1) & (new_align - si_align);
4241 si_align = new_align;
4243 count_si = (count_si + new_align - 1) & -new_align;
4248 if (new_align > hi_align)
4250 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4251 hi_align = new_align;
4253 count_hi = (count_hi + new_align - 1) & -new_align;
4255 from = NEXT_INSN (from);
4262 /* Try as we might, the leading mova is out of range. Change
4263 it into a load (which will become a pcload) and retry. */
4265 return find_barrier (0, 0, mova);
4269 /* Insert the constant pool table before the mova instruction,
4270 to prevent the mova label reference from going out of range. */
4272 good_barrier = found_barrier = barrier_before_mova;
4278 if (good_barrier && next_real_insn (found_barrier))
4279 found_barrier = good_barrier;
4283 /* We didn't find a barrier in time to dump our stuff,
4284 so we'll make one. */
4285 rtx label = gen_label_rtx ();
4287 /* If we exceeded the range, then we must back up over the last
4288 instruction we looked at. Otherwise, we just need to undo the
4289 NEXT_INSN at the end of the loop. */
4290 if (PREV_INSN (from) != orig
4291 && (count_hi > hi_limit || count_si > si_limit))
4292 from = PREV_INSN (PREV_INSN (from));
4294 from = PREV_INSN (from);
4296 /* Walk back to be just before any jump or label.
4297 Putting it before a label reduces the number of times the branch
4298 around the constant pool table will be hit. Putting it before
4299 a jump makes it more likely that the bra delay slot will be
4301 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
4302 || GET_CODE (from) == CODE_LABEL)
4303 from = PREV_INSN (from);
4305 from = emit_jump_insn_after (gen_jump (label), from);
4306 JUMP_LABEL (from) = label;
4307 LABEL_NUSES (label) = 1;
4308 found_barrier = emit_barrier_after (from);
4309 emit_label_after (label, found_barrier);
4312 return found_barrier;
4315 /* If the instruction INSN is implemented by a special function, and we can
4316 positively find the register that is used to call the sfunc, and this
4317 register is not used anywhere else in this instruction - except as the
4318 destination of a set, return this register; else, return 0. */
4320 sfunc_uses_reg (rtx insn)
4323 rtx pattern, part, reg_part, reg;
4325 if (GET_CODE (insn) != INSN)
4327 pattern = PATTERN (insn);
4328 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4331 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4333 part = XVECEXP (pattern, 0, i);
4334 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4339 reg = XEXP (reg_part, 0);
4340 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4342 part = XVECEXP (pattern, 0, i);
4343 if (part == reg_part || GET_CODE (part) == CLOBBER)
4345 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4346 && GET_CODE (SET_DEST (part)) == REG)
4347 ? SET_SRC (part) : part)))
4353 /* See if the only way in which INSN uses REG is by calling it, or by
4354 setting it while calling it. Set *SET to a SET rtx if the register
4358 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4364 reg2 = sfunc_uses_reg (insn);
4365 if (reg2 && REGNO (reg2) == REGNO (reg))
4367 pattern = single_set (insn);
4369 && GET_CODE (SET_DEST (pattern)) == REG
4370 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4374 if (GET_CODE (insn) != CALL_INSN)
4376 /* We don't use rtx_equal_p because we don't care if the mode is
4378 pattern = single_set (insn);
4380 && GET_CODE (SET_DEST (pattern)) == REG
4381 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4387 par = PATTERN (insn);
4388 if (GET_CODE (par) == PARALLEL)
4389 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4391 part = XVECEXP (par, 0, i);
4392 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4395 return reg_mentioned_p (reg, SET_SRC (pattern));
4401 pattern = PATTERN (insn);
4403 if (GET_CODE (pattern) == PARALLEL)
4407 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4408 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4410 pattern = XVECEXP (pattern, 0, 0);
4413 if (GET_CODE (pattern) == SET)
4415 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4417 /* We don't use rtx_equal_p, because we don't care if the
4418 mode is different. */
4419 if (GET_CODE (SET_DEST (pattern)) != REG
4420 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4426 pattern = SET_SRC (pattern);
4429 if (GET_CODE (pattern) != CALL
4430 || GET_CODE (XEXP (pattern, 0)) != MEM
4431 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4437 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4438 general registers. Bits 0..15 mean that the respective registers
4439 are used as inputs in the instruction. Bits 16..31 mean that the
4440 registers 0..15, respectively, are used as outputs, or are clobbered.
4441 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4443 regs_used (rtx x, int is_dest)
4451 code = GET_CODE (x);
4456 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4457 << (REGNO (x) + is_dest));
4461 rtx y = SUBREG_REG (x);
4463 if (GET_CODE (y) != REG)
4466 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4468 subreg_regno_offset (REGNO (y),
4471 GET_MODE (x)) + is_dest));
4475 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4477 /* If there was a return value, it must have been indicated with USE. */
4492 fmt = GET_RTX_FORMAT (code);
4494 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4499 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4500 used |= regs_used (XVECEXP (x, i, j), is_dest);
4502 else if (fmt[i] == 'e')
4503 used |= regs_used (XEXP (x, i), is_dest);
4508 /* Create an instruction that prevents redirection of a conditional branch
4509 to the destination of the JUMP with address ADDR.
4510 If the branch needs to be implemented as an indirect jump, try to find
4511 a scratch register for it.
4512 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4513 If any preceding insn that doesn't fit into a delay slot is good enough,
4514 pass 1. Pass 2 if a definite blocking insn is needed.
4515 -1 is used internally to avoid deep recursion.
4516 If a blocking instruction is made or recognized, return it. */
4519 gen_block_redirect (rtx jump, int addr, int need_block)
4522 rtx prev = prev_nonnote_insn (jump);
4525 /* First, check if we already have an instruction that satisfies our need. */
4526 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
4528 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4530 if (GET_CODE (PATTERN (prev)) == USE
4531 || GET_CODE (PATTERN (prev)) == CLOBBER
4532 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4534 else if ((need_block &= ~1) < 0)
4536 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4539 if (GET_CODE (PATTERN (jump)) == RETURN)
4543 /* Reorg even does nasty things with return insns that cause branches
4544 to go out of range - see find_end_label and callers. */
4545 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4547 /* We can't use JUMP_LABEL here because it might be undefined
4548 when not optimizing. */
4549 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4550 /* If the branch is out of range, try to find a scratch register for it. */
4552 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4556 /* Don't look for the stack pointer as a scratch register,
4557 it would cause trouble if an interrupt occurred. */
4558 unsigned attempt = 0x7fff, used;
4559 int jump_left = flag_expensive_optimizations + 1;
4561 /* It is likely that the most recent eligible instruction is wanted for
4562 the delay slot. Therefore, find out which registers it uses, and
4563 try to avoid using them. */
4565 for (scan = jump; (scan = PREV_INSN (scan)); )
4569 if (INSN_DELETED_P (scan))
4571 code = GET_CODE (scan);
4572 if (code == CODE_LABEL || code == JUMP_INSN)
4575 && GET_CODE (PATTERN (scan)) != USE
4576 && GET_CODE (PATTERN (scan)) != CLOBBER
4577 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4579 attempt &= ~regs_used (PATTERN (scan), 0);
4583 for (used = dead = 0, scan = JUMP_LABEL (jump);
4584 (scan = NEXT_INSN (scan)); )
4588 if (INSN_DELETED_P (scan))
4590 code = GET_CODE (scan);
4593 used |= regs_used (PATTERN (scan), 0);
4594 if (code == CALL_INSN)
4595 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4596 dead |= (used >> 16) & ~used;
4602 if (code == JUMP_INSN)
4604 if (jump_left-- && simplejump_p (scan))
4605 scan = JUMP_LABEL (scan);
4611 /* Mask out the stack pointer again, in case it was
4612 the only 'free' register we have found. */
4615 /* If the immediate destination is still in range, check for possible
4616 threading with a jump beyond the delay slot insn.
4617 Don't check if we are called recursively; the jump has been or will be
4618 checked in a different invocation then. */
4620 else if (optimize && need_block >= 0)
4622 rtx next = next_active_insn (next_active_insn (dest));
4623 if (next && GET_CODE (next) == JUMP_INSN
4624 && GET_CODE (PATTERN (next)) == SET
4625 && recog_memoized (next) == CODE_FOR_jump_compact)
4627 dest = JUMP_LABEL (next);
4629 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4631 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
4637 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
4639 /* It would be nice if we could convert the jump into an indirect
4640 jump / far branch right now, and thus exposing all constituent
4641 instructions to further optimization. However, reorg uses
4642 simplejump_p to determine if there is an unconditional jump where
4643 it should try to schedule instructions from the target of the
4644 branch; simplejump_p fails for indirect jumps even if they have
4646 rtx insn = emit_insn_before (gen_indirect_jump_scratch
4647 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
4649 /* ??? We would like this to have the scope of the jump, but that
4650 scope will change when a delay slot insn of an inner scope is added.
4651 Hence, after delay slot scheduling, we'll have to expect
4652 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
4655 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
4656 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
4659 else if (need_block)
4660 /* We can't use JUMP_LABEL here because it might be undefined
4661 when not optimizing. */
4662 return emit_insn_before (gen_block_branch_redirect
4663 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
4668 #define CONDJUMP_MIN -252
4669 #define CONDJUMP_MAX 262
4672 /* A label (to be placed) in front of the jump
4673 that jumps to our ultimate destination. */
4675 /* Where we are going to insert it if we cannot move the jump any farther,
4676 or the jump itself if we have picked up an existing jump. */
4678 /* The ultimate destination. */
4680 struct far_branch *prev;
4681 /* If the branch has already been created, its address;
4682 else the address of its first prospective user. */
4686 static void gen_far_branch (struct far_branch *);
4687 enum mdep_reorg_phase_e mdep_reorg_phase;
4689 gen_far_branch (struct far_branch *bp)
4691 rtx insn = bp->insert_place;
4693 rtx label = gen_label_rtx ();
4696 emit_label_after (label, insn);
4699 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
4700 LABEL_NUSES (bp->far_label)++;
4703 jump = emit_jump_insn_after (gen_return (), insn);
4704 /* Emit a barrier so that reorg knows that any following instructions
4705 are not reachable via a fall-through path.
4706 But don't do this when not optimizing, since we wouldn't suppress the
4707 alignment for the barrier then, and could end up with out-of-range
4708 pc-relative loads. */
4710 emit_barrier_after (jump);
4711 emit_label_after (bp->near_label, insn);
4712 JUMP_LABEL (jump) = bp->far_label;
4713 ok = invert_jump (insn, label, 1);
4716 /* If we are branching around a jump (rather than a return), prevent
4717 reorg from using an insn from the jump target as the delay slot insn -
4718 when reorg did this, it pessimized code (we rather hide the delay slot)
4719 and it could cause branches to go out of range. */
4722 (gen_stuff_delay_slot
4723 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
4724 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
4726 /* Prevent reorg from undoing our splits. */
4727 gen_block_redirect (jump, bp->address += 2, 2);
4730 /* Fix up ADDR_DIFF_VECs. */
4732 fixup_addr_diff_vecs (rtx first)
4736 for (insn = first; insn; insn = NEXT_INSN (insn))
4738 rtx vec_lab, pat, prev, prevpat, x, braf_label;
4740 if (GET_CODE (insn) != JUMP_INSN
4741 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
4743 pat = PATTERN (insn);
4744 vec_lab = XEXP (XEXP (pat, 0), 0);
4746 /* Search the matching casesi_jump_2. */
4747 for (prev = vec_lab; ; prev = PREV_INSN (prev))
4749 if (GET_CODE (prev) != JUMP_INSN)
4751 prevpat = PATTERN (prev);
4752 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
4754 x = XVECEXP (prevpat, 0, 1);
4755 if (GET_CODE (x) != USE)
4758 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
4761 /* FIXME: This is a bug in the optimizer, but it seems harmless
4762 to just avoid panicing. */
4766 /* Emit the reference label of the braf where it belongs, right after
4767 the casesi_jump_2 (i.e. braf). */
4768 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
4769 emit_label_after (braf_label, prev);
4771 /* Fix up the ADDR_DIF_VEC to be relative
4772 to the reference address of the braf. */
4773 XEXP (XEXP (pat, 0), 0) = braf_label;
4777 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
4778 a barrier. Return the base 2 logarithm of the desired alignment. */
4780 barrier_align (rtx barrier_or_label)
4782 rtx next = next_real_insn (barrier_or_label), pat, prev;
4783 int slot, credit, jump_to_next = 0;
4788 pat = PATTERN (next);
4790 if (GET_CODE (pat) == ADDR_DIFF_VEC)
4793 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
4794 /* This is a barrier in front of a constant table. */
4797 prev = prev_real_insn (barrier_or_label);
4798 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
4800 pat = PATTERN (prev);
4801 /* If this is a very small table, we want to keep the alignment after
4802 the table to the minimum for proper code alignment. */
4803 return ((TARGET_SMALLCODE
4804 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
4805 <= (unsigned) 1 << (CACHE_LOG - 2)))
4806 ? 1 << TARGET_SHMEDIA : align_jumps_log);
4809 if (TARGET_SMALLCODE)
4812 if (! TARGET_SH2 || ! optimize)
4813 return align_jumps_log;
4815 /* When fixing up pcloads, a constant table might be inserted just before
4816 the basic block that ends with the barrier. Thus, we can't trust the
4817 instruction lengths before that. */
4818 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
4820 /* Check if there is an immediately preceding branch to the insn beyond
4821 the barrier. We must weight the cost of discarding useful information
4822 from the current cache line when executing this branch and there is
4823 an alignment, against that of fetching unneeded insn in front of the
4824 branch target when there is no alignment. */
4826 /* There are two delay_slot cases to consider. One is the simple case
4827 where the preceding branch is to the insn beyond the barrier (simple
4828 delay slot filling), and the other is where the preceding branch has
4829 a delay slot that is a duplicate of the insn after the barrier
4830 (fill_eager_delay_slots) and the branch is to the insn after the insn
4831 after the barrier. */
4833 /* PREV is presumed to be the JUMP_INSN for the barrier under
4834 investigation. Skip to the insn before it. */
4835 prev = prev_real_insn (prev);
4837 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
4838 credit >= 0 && prev && GET_CODE (prev) == INSN;
4839 prev = prev_real_insn (prev))
4842 if (GET_CODE (PATTERN (prev)) == USE
4843 || GET_CODE (PATTERN (prev)) == CLOBBER)
4845 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
4847 prev = XVECEXP (PATTERN (prev), 0, 1);
4848 if (INSN_UID (prev) == INSN_UID (next))
4850 /* Delay slot was filled with insn at jump target. */
4857 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4859 credit -= get_attr_length (prev);
4862 && GET_CODE (prev) == JUMP_INSN
4863 && JUMP_LABEL (prev))
4867 || next_real_insn (JUMP_LABEL (prev)) == next
4868 /* If relax_delay_slots() decides NEXT was redundant
4869 with some previous instruction, it will have
4870 redirected PREV's jump to the following insn. */
4871 || JUMP_LABEL (prev) == next_nonnote_insn (next)
4872 /* There is no upper bound on redundant instructions
4873 that might have been skipped, but we must not put an
4874 alignment where none had been before. */
4875 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
4877 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
4878 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
4879 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
4881 rtx pat = PATTERN (prev);
4882 if (GET_CODE (pat) == PARALLEL)
4883 pat = XVECEXP (pat, 0, 0);
4884 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
4890 return align_jumps_log;
4893 /* If we are inside a phony loop, almost any kind of label can turn up as the
4894 first one in the loop. Aligning a braf label causes incorrect switch
4895 destination addresses; we can detect braf labels because they are
4896 followed by a BARRIER.
4897 Applying loop alignment to small constant or switch tables is a waste
4898 of space, so we suppress this too. */
4900 sh_loop_align (rtx label)
4905 next = next_nonnote_insn (next);
4906 while (next && GET_CODE (next) == CODE_LABEL);
4910 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
4911 || recog_memoized (next) == CODE_FOR_consttable_2)
4914 return align_loops_log;
4917 /* Do a final pass over the function, just before delayed branch
4923 rtx first, insn, mova = NULL_RTX;
4925 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
4926 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
4928 first = get_insns ();
4929 max_labelno_before_reorg = max_label_num ();
4931 /* We must split call insns before introducing `mova's. If we're
4932 optimizing, they'll have already been split. Otherwise, make
4933 sure we don't split them too late. */
4935 split_all_insns_noflow ();
4940 /* If relaxing, generate pseudo-ops to associate function calls with
4941 the symbols they call. It does no harm to not generate these
4942 pseudo-ops. However, when we can generate them, it enables to
4943 linker to potentially relax the jsr to a bsr, and eliminate the
4944 register load and, possibly, the constant pool entry. */
4946 mdep_reorg_phase = SH_INSERT_USES_LABELS;
4949 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
4950 own purposes. This works because none of the remaining passes
4951 need to look at them.
4953 ??? But it may break in the future. We should use a machine
4954 dependent REG_NOTE, or some other approach entirely. */
4955 for (insn = first; insn; insn = NEXT_INSN (insn))
4961 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
4963 remove_note (insn, note);
4967 for (insn = first; insn; insn = NEXT_INSN (insn))
4969 rtx pattern, reg, link, set, scan, dies, label;
4970 int rescan = 0, foundinsn = 0;
4972 if (GET_CODE (insn) == CALL_INSN)
4974 pattern = PATTERN (insn);
4976 if (GET_CODE (pattern) == PARALLEL)
4977 pattern = XVECEXP (pattern, 0, 0);
4978 if (GET_CODE (pattern) == SET)
4979 pattern = SET_SRC (pattern);
4981 if (GET_CODE (pattern) != CALL
4982 || GET_CODE (XEXP (pattern, 0)) != MEM)
4985 reg = XEXP (XEXP (pattern, 0), 0);
4989 reg = sfunc_uses_reg (insn);
4994 if (GET_CODE (reg) != REG)
4997 /* Try scanning backward to find where the register is set. */
4999 for (scan = PREV_INSN (insn);
5000 scan && GET_CODE (scan) != CODE_LABEL;
5001 scan = PREV_INSN (scan))
5003 if (! INSN_P (scan))
5006 if (! reg_mentioned_p (reg, scan))
5009 if (noncall_uses_reg (reg, scan, &set))
5022 /* The register is set at LINK. */
5024 /* We can only optimize the function call if the register is
5025 being set to a symbol. In theory, we could sometimes
5026 optimize calls to a constant location, but the assembler
5027 and linker do not support that at present. */
5028 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5029 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5032 /* Scan forward from LINK to the place where REG dies, and
5033 make sure that the only insns which use REG are
5034 themselves function calls. */
5036 /* ??? This doesn't work for call targets that were allocated
5037 by reload, since there may not be a REG_DEAD note for the
5041 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5045 /* Don't try to trace forward past a CODE_LABEL if we haven't
5046 seen INSN yet. Ordinarily, we will only find the setting insn
5047 if it is in the same basic block. However,
5048 cross-jumping can insert code labels in between the load and
5049 the call, and can result in situations where a single call
5050 insn may have two targets depending on where we came from. */
5052 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
5055 if (! INSN_P (scan))
5058 /* Don't try to trace forward past a JUMP. To optimize
5059 safely, we would have to check that all the
5060 instructions at the jump destination did not use REG. */
5062 if (GET_CODE (scan) == JUMP_INSN)
5065 if (! reg_mentioned_p (reg, scan))
5068 if (noncall_uses_reg (reg, scan, &scanset))
5075 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
5077 /* There is a function call to this register other
5078 than the one we are checking. If we optimize
5079 this call, we need to rescan again below. */
5083 /* ??? We shouldn't have to worry about SCANSET here.
5084 We should just be able to check for a REG_DEAD note
5085 on a function call. However, the REG_DEAD notes are
5086 apparently not dependable around libcalls; c-torture
5087 execute/920501-2 is a test case. If SCANSET is set,
5088 then this insn sets the register, so it must have
5089 died earlier. Unfortunately, this will only handle
5090 the cases in which the register is, in fact, set in a
5093 /* ??? We shouldn't have to use FOUNDINSN here.
5094 This dates back to when we used LOG_LINKS to find
5095 the most recent insn which sets the register. */
5099 || find_reg_note (scan, REG_DEAD, reg)))
5108 /* Either there was a branch, or some insn used REG
5109 other than as a function call address. */
5113 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5114 on the insn which sets the register, and on each call insn
5115 which uses the register. In final_prescan_insn we look for
5116 the REG_LABEL_OPERAND notes, and output the appropriate label
5119 label = gen_label_rtx ();
5120 add_reg_note (link, REG_LABEL_OPERAND, label);
5121 add_reg_note (insn, REG_LABEL_OPERAND, label);
5129 scan = NEXT_INSN (scan);
5131 && ((GET_CODE (scan) == CALL_INSN
5132 && reg_mentioned_p (reg, scan))
5133 || ((reg2 = sfunc_uses_reg (scan))
5134 && REGNO (reg2) == REGNO (reg))))
5135 add_reg_note (scan, REG_LABEL_OPERAND, label);
5137 while (scan != dies);
5143 fixup_addr_diff_vecs (first);
5147 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5148 shorten_branches (first);
5151 /* Scan the function looking for move instructions which have to be
5152 changed to pc-relative loads and insert the literal tables. */
5153 label_ref_list_pool = create_alloc_pool ("label references list",
5154 sizeof (struct label_ref_list_d),
5156 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5157 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
5161 /* ??? basic block reordering can move a switch table dispatch
5162 below the switch table. Check if that has happened.
5163 We only have the addresses available when optimizing; but then,
5164 this check shouldn't be needed when not optimizing. */
5165 if (!untangle_mova (&num_mova, &mova, insn))
5171 else if (GET_CODE (insn) == JUMP_INSN
5172 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5174 /* ??? loop invariant motion can also move a mova out of a
5175 loop. Since loop does this code motion anyway, maybe we
5176 should wrap UNSPEC_MOVA into a CONST, so that reload can
5179 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5180 || (prev_nonnote_insn (insn)
5181 == XEXP (MOVA_LABELREF (mova), 0))))
5188 /* Some code might have been inserted between the mova and
5189 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5190 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5191 total += get_attr_length (scan);
5193 /* range of mova is 1020, add 4 because pc counts from address of
5194 second instruction after this one, subtract 2 in case pc is 2
5195 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5196 cancels out with alignment effects of the mova itself. */
5199 /* Change the mova into a load, and restart scanning
5200 there. broken_move will then return true for mova. */
5205 if (broken_move (insn)
5206 || (GET_CODE (insn) == INSN
5207 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5210 /* Scan ahead looking for a barrier to stick the constant table
5212 rtx barrier = find_barrier (num_mova, mova, insn);
5213 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5214 int need_aligned_label = 0;
5216 if (num_mova && ! mova_p (mova))
5218 /* find_barrier had to change the first mova into a
5219 pcload; thus, we have to start with this new pcload. */
5223 /* Now find all the moves between the points and modify them. */
5224 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5226 if (GET_CODE (scan) == CODE_LABEL)
5228 if (GET_CODE (scan) == INSN
5229 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5230 need_aligned_label = 1;
5231 if (broken_move (scan))
5233 rtx *patp = &PATTERN (scan), pat = *patp;
5237 enum machine_mode mode;
5239 if (GET_CODE (pat) == PARALLEL)
5240 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5241 src = SET_SRC (pat);
5242 dst = SET_DEST (pat);
5243 mode = GET_MODE (dst);
5245 if (mode == SImode && hi_const (src)
5246 && REGNO (dst) != FPUL_REG)
5251 while (GET_CODE (dst) == SUBREG)
5253 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5254 GET_MODE (SUBREG_REG (dst)),
5257 dst = SUBREG_REG (dst);
5259 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5261 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
5263 /* This must be an insn that clobbers r0. */
5264 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5265 XVECLEN (PATTERN (scan), 0)
5267 rtx clobber = *clobberp;
5269 gcc_assert (GET_CODE (clobber) == CLOBBER
5270 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5273 && reg_set_between_p (r0_rtx, last_float_move, scan))
5277 && GET_MODE_SIZE (mode) != 4
5278 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5280 lab = add_constant (src, mode, last_float);
5282 emit_insn_before (gen_mova (lab), scan);
5285 /* There will be a REG_UNUSED note for r0 on
5286 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5287 lest reorg:mark_target_live_regs will not
5288 consider r0 to be used, and we end up with delay
5289 slot insn in front of SCAN that clobbers r0. */
5291 = find_regno_note (last_float_move, REG_UNUSED, 0);
5293 /* If we are not optimizing, then there may not be
5296 PUT_REG_NOTE_KIND (note, REG_INC);
5298 *last_float_addr = r0_inc_rtx;
5300 last_float_move = scan;
5302 newsrc = gen_const_mem (mode,
5303 (((TARGET_SH4 && ! TARGET_FMOVD)
5304 || REGNO (dst) == FPUL_REG)
5307 last_float_addr = &XEXP (newsrc, 0);
5309 /* Remove the clobber of r0. */
5310 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5311 gen_rtx_SCRATCH (Pmode));
5313 /* This is a mova needing a label. Create it. */
5314 else if (GET_CODE (src) == UNSPEC
5315 && XINT (src, 1) == UNSPEC_MOVA
5316 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5318 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5319 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5320 newsrc = gen_rtx_UNSPEC (SImode,
5321 gen_rtvec (1, newsrc),
5326 lab = add_constant (src, mode, 0);
5327 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5328 newsrc = gen_const_mem (mode, newsrc);
5330 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5331 INSN_CODE (scan) = -1;
5334 dump_table (need_aligned_label ? insn : 0, barrier);
5338 free_alloc_pool (label_ref_list_pool);
5339 for (insn = first; insn; insn = NEXT_INSN (insn))
5340 PUT_MODE (insn, VOIDmode);
5342 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5343 INSN_ADDRESSES_FREE ();
5344 split_branches (first);
5346 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5347 also has an effect on the register that holds the address of the sfunc.
5348 Insert an extra dummy insn in front of each sfunc that pretends to
5349 use this register. */
5350 if (flag_delayed_branch)
5352 for (insn = first; insn; insn = NEXT_INSN (insn))
5354 rtx reg = sfunc_uses_reg (insn);
5358 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5362 /* fpscr is not actually a user variable, but we pretend it is for the
5363 sake of the previous optimization passes, since we want it handled like
5364 one. However, we don't have any debugging information for it, so turn
5365 it into a non-user variable now. */
5367 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5369 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5373 get_dest_uid (rtx label, int max_uid)
5375 rtx dest = next_real_insn (label);
5378 /* This can happen for an undefined label. */
5380 dest_uid = INSN_UID (dest);
5381 /* If this is a newly created branch redirection blocking instruction,
5382 we cannot index the branch_uid or insn_addresses arrays with its
5383 uid. But then, we won't need to, because the actual destination is
5384 the following branch. */
5385 while (dest_uid >= max_uid)
5387 dest = NEXT_INSN (dest);
5388 dest_uid = INSN_UID (dest);
5390 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
5395 /* Split condbranches that are out of range. Also add clobbers for
5396 scratch registers that are needed in far jumps.
5397 We do this before delay slot scheduling, so that it can take our
5398 newly created instructions into account. It also allows us to
5399 find branches with common targets more easily. */
5402 split_branches (rtx first)
5405 struct far_branch **uid_branch, *far_branch_list = 0;
5406 int max_uid = get_max_uid ();
5409 /* Find out which branches are out of range. */
5410 shorten_branches (first);
5412 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5413 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5415 for (insn = first; insn; insn = NEXT_INSN (insn))
5416 if (! INSN_P (insn))
5418 else if (INSN_DELETED_P (insn))
5420 /* Shorten_branches would split this instruction again,
5421 so transform it into a note. */
5422 SET_INSN_DELETED (insn);
5424 else if (GET_CODE (insn) == JUMP_INSN
5425 /* Don't mess with ADDR_DIFF_VEC */
5426 && (GET_CODE (PATTERN (insn)) == SET
5427 || GET_CODE (PATTERN (insn)) == RETURN))
5429 enum attr_type type = get_attr_type (insn);
5430 if (type == TYPE_CBRANCH)
5434 if (get_attr_length (insn) > 4)
5436 rtx src = SET_SRC (PATTERN (insn));
5437 rtx olabel = XEXP (XEXP (src, 1), 0);
5438 int addr = INSN_ADDRESSES (INSN_UID (insn));
5440 int dest_uid = get_dest_uid (olabel, max_uid);
5441 struct far_branch *bp = uid_branch[dest_uid];
5443 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5444 the label if the LABEL_NUSES count drops to zero. There is
5445 always a jump_optimize pass that sets these values, but it
5446 proceeds to delete unreferenced code, and then if not
5447 optimizing, to un-delete the deleted instructions, thus
5448 leaving labels with too low uses counts. */
5451 JUMP_LABEL (insn) = olabel;
5452 LABEL_NUSES (olabel)++;
5456 bp = (struct far_branch *) alloca (sizeof *bp);
5457 uid_branch[dest_uid] = bp;
5458 bp->prev = far_branch_list;
5459 far_branch_list = bp;
5461 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5462 LABEL_NUSES (bp->far_label)++;
5466 label = bp->near_label;
5467 if (! label && bp->address - addr >= CONDJUMP_MIN)
5469 rtx block = bp->insert_place;
5471 if (GET_CODE (PATTERN (block)) == RETURN)
5472 block = PREV_INSN (block);
5474 block = gen_block_redirect (block,
5476 label = emit_label_after (gen_label_rtx (),
5478 bp->near_label = label;
5480 else if (label && ! NEXT_INSN (label))
5482 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5483 bp->insert_place = insn;
5485 gen_far_branch (bp);
5489 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5491 bp->near_label = label = gen_label_rtx ();
5492 bp->insert_place = insn;
5495 ok = redirect_jump (insn, label, 0);
5500 /* get_attr_length (insn) == 2 */
5501 /* Check if we have a pattern where reorg wants to redirect
5502 the branch to a label from an unconditional branch that
5504 /* We can't use JUMP_LABEL here because it might be undefined
5505 when not optimizing. */
5506 /* A syntax error might cause beyond to be NULL_RTX. */
5508 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5512 && (GET_CODE (beyond) == JUMP_INSN
5513 || ((beyond = next_active_insn (beyond))
5514 && GET_CODE (beyond) == JUMP_INSN))
5515 && GET_CODE (PATTERN (beyond)) == SET
5516 && recog_memoized (beyond) == CODE_FOR_jump_compact
5518 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5519 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5521 gen_block_redirect (beyond,
5522 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5525 next = next_active_insn (insn);
5527 if ((GET_CODE (next) == JUMP_INSN
5528 || ((next = next_active_insn (next))
5529 && GET_CODE (next) == JUMP_INSN))
5530 && GET_CODE (PATTERN (next)) == SET
5531 && recog_memoized (next) == CODE_FOR_jump_compact
5533 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5534 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5536 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5538 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5540 int addr = INSN_ADDRESSES (INSN_UID (insn));
5543 struct far_branch *bp;
5545 if (type == TYPE_JUMP)
5547 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5548 dest_uid = get_dest_uid (far_label, max_uid);
5551 /* Parse errors can lead to labels outside
5553 if (! NEXT_INSN (far_label))
5558 JUMP_LABEL (insn) = far_label;
5559 LABEL_NUSES (far_label)++;
5561 redirect_jump (insn, NULL_RTX, 1);
5565 bp = uid_branch[dest_uid];
5568 bp = (struct far_branch *) alloca (sizeof *bp);
5569 uid_branch[dest_uid] = bp;
5570 bp->prev = far_branch_list;
5571 far_branch_list = bp;
5573 bp->far_label = far_label;
5575 LABEL_NUSES (far_label)++;
5577 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5578 if (addr - bp->address <= CONDJUMP_MAX)
5579 emit_label_after (bp->near_label, PREV_INSN (insn));
5582 gen_far_branch (bp);
5588 bp->insert_place = insn;
5590 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5592 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5595 /* Generate all pending far branches,
5596 and free our references to the far labels. */
5597 while (far_branch_list)
5599 if (far_branch_list->near_label
5600 && ! NEXT_INSN (far_branch_list->near_label))
5601 gen_far_branch (far_branch_list);
5603 && far_branch_list->far_label
5604 && ! --LABEL_NUSES (far_branch_list->far_label))
5605 delete_insn (far_branch_list->far_label);
5606 far_branch_list = far_branch_list->prev;
5609 /* Instruction length information is no longer valid due to the new
5610 instructions that have been generated. */
5611 init_insn_lengths ();
5614 /* Dump out instruction addresses, which is useful for debugging the
5615 constant pool table stuff.
5617 If relaxing, output the label and pseudo-ops used to link together
5618 calls and the instruction which set the registers. */
5620 /* ??? The addresses printed by this routine for insns are nonsense for
5621 insns which are inside of a sequence where none of the inner insns have
5622 variable length. This is because the second pass of shorten_branches
5623 does not bother to update them. */
5626 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
5627 int noperands ATTRIBUTE_UNUSED)
5629 if (TARGET_DUMPISIZE)
5630 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
5636 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
5641 pattern = PATTERN (insn);
5642 if (GET_CODE (pattern) == PARALLEL)
5643 pattern = XVECEXP (pattern, 0, 0);
5644 switch (GET_CODE (pattern))
5647 if (GET_CODE (SET_SRC (pattern)) != CALL
5648 && get_attr_type (insn) != TYPE_SFUNC)
5650 targetm.asm_out.internal_label
5651 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
5654 /* else FALLTHROUGH */
5656 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
5657 CODE_LABEL_NUMBER (XEXP (note, 0)));
5667 /* Dump out any constants accumulated in the final pass. These will
5671 output_jump_label_table (void)
5677 fprintf (asm_out_file, "\t.align 2\n");
5678 for (i = 0; i < pool_size; i++)
5680 pool_node *p = &pool_vector[i];
5682 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5683 CODE_LABEL_NUMBER (p->label));
5684 output_asm_insn (".long %O0", &p->value);
5692 /* A full frame looks like:
5696 [ if current_function_anonymous_args
5709 local-0 <- fp points here. */
5711 /* Number of bytes pushed for anonymous args, used to pass information
5712 between expand_prologue and expand_epilogue. */
5714 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
5715 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
5716 for an epilogue and a negative value means that it's for a sibcall
5717 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
5718 all the registers that are about to be restored, and hence dead. */
5721 output_stack_adjust (int size, rtx reg, int epilogue_p,
5722 HARD_REG_SET *live_regs_mask)
5724 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
5727 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
5729 /* This test is bogus, as output_stack_adjust is used to re-align the
5732 gcc_assert (!(size % align));
5735 if (CONST_OK_FOR_ADD (size))
5736 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
5737 /* Try to do it with two partial adjustments; however, we must make
5738 sure that the stack is properly aligned at all times, in case
5739 an interrupt occurs between the two partial adjustments. */
5740 else if (CONST_OK_FOR_ADD (size / 2 & -align)
5741 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
5743 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
5744 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
5750 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
5753 /* If TEMP is invalid, we could temporarily save a general
5754 register to MACL. However, there is currently no need
5755 to handle this case, so just die when we see it. */
5757 || current_function_interrupt
5758 || ! call_really_used_regs[temp] || fixed_regs[temp])
5760 if (temp < 0 && ! current_function_interrupt
5761 && (TARGET_SHMEDIA || epilogue_p >= 0))
5764 COPY_HARD_REG_SET (temps, call_used_reg_set);
5765 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
5769 if (crtl->return_rtx)
5771 enum machine_mode mode;
5772 mode = GET_MODE (crtl->return_rtx);
5773 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
5774 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
5776 for (i = 0; i < nreg; i++)
5777 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
5778 if (crtl->calls_eh_return)
5780 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
5781 for (i = 0; i <= 3; i++)
5782 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
5785 if (TARGET_SHMEDIA && epilogue_p < 0)
5786 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
5787 CLEAR_HARD_REG_BIT (temps, i);
5788 if (epilogue_p <= 0)
5790 for (i = FIRST_PARM_REG;
5791 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
5792 CLEAR_HARD_REG_BIT (temps, i);
5793 if (cfun->static_chain_decl != NULL)
5794 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
5796 temp = scavenge_reg (&temps);
5798 if (temp < 0 && live_regs_mask)
5802 COPY_HARD_REG_SET (temps, *live_regs_mask);
5803 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
5804 temp = scavenge_reg (&temps);
5808 rtx adj_reg, tmp_reg, mem;
5810 /* If we reached here, the most likely case is the (sibcall)
5811 epilogue for non SHmedia. Put a special push/pop sequence
5812 for such case as the last resort. This looks lengthy but
5813 would not be problem because it seems to be very
5816 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
5819 /* ??? There is still the slight possibility that r4 or
5820 r5 have been reserved as fixed registers or assigned
5821 as global registers, and they change during an
5822 interrupt. There are possible ways to handle this:
5824 - If we are adjusting the frame pointer (r14), we can do
5825 with a single temp register and an ordinary push / pop
5827 - Grab any call-used or call-saved registers (i.e. not
5828 fixed or globals) for the temps we need. We might
5829 also grab r14 if we are adjusting the stack pointer.
5830 If we can't find enough available registers, issue
5831 a diagnostic and die - the user must have reserved
5832 way too many registers.
5833 But since all this is rather unlikely to happen and
5834 would require extra testing, we just die if r4 / r5
5835 are not available. */
5836 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
5837 && !global_regs[4] && !global_regs[5]);
5839 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
5840 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
5841 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
5842 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
5843 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
5844 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5845 emit_move_insn (mem, tmp_reg);
5846 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
5847 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5848 emit_move_insn (mem, tmp_reg);
5849 emit_move_insn (reg, adj_reg);
5850 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5851 emit_move_insn (adj_reg, mem);
5852 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5853 emit_move_insn (tmp_reg, mem);
5854 /* Tell flow the insns that pop r4/r5 aren't dead. */
5859 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
5861 /* If SIZE is negative, subtract the positive value.
5862 This sometimes allows a constant pool entry to be shared
5863 between prologue and epilogue code. */
5866 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
5867 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
5871 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
5872 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
5875 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
5876 gen_rtx_SET (VOIDmode, reg,
5877 gen_rtx_PLUS (SImode, reg,
5887 RTX_FRAME_RELATED_P (x) = 1;
5891 /* Output RTL to push register RN onto the stack. */
5898 x = gen_push_fpul ();
5899 else if (rn == FPSCR_REG)
5900 x = gen_push_fpscr ();
5901 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5902 && FP_OR_XD_REGISTER_P (rn))
5904 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5906 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
5908 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5909 x = gen_push_e (gen_rtx_REG (SFmode, rn));
5911 x = gen_push (gen_rtx_REG (SImode, rn));
5914 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
5918 /* Output RTL to pop register RN from the stack. */
5925 x = gen_pop_fpul ();
5926 else if (rn == FPSCR_REG)
5927 x = gen_pop_fpscr ();
5928 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5929 && FP_OR_XD_REGISTER_P (rn))
5931 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5933 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
5935 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5936 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
5938 x = gen_pop (gen_rtx_REG (SImode, rn));
5941 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
5944 /* Generate code to push the regs specified in the mask. */
5947 push_regs (HARD_REG_SET *mask, int interrupt_handler)
5949 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
5952 /* Push PR last; this gives better latencies after the prologue, and
5953 candidates for the return delay slot when there are no general
5954 registers pushed. */
5955 for (; i < FIRST_PSEUDO_REGISTER; i++)
5957 /* If this is an interrupt handler, and the SZ bit varies,
5958 and we have to push any floating point register, we need
5959 to switch to the correct precision first. */
5960 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
5961 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
5963 HARD_REG_SET unsaved;
5966 COMPL_HARD_REG_SET (unsaved, *mask);
5967 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
5971 && (i != FPSCR_REG || ! skip_fpscr)
5972 && TEST_HARD_REG_BIT (*mask, i))
5974 /* If the ISR has RESBANK attribute assigned, don't push any of
5975 the following registers - R0-R14, MACH, MACL and GBR. */
5976 if (! (sh_cfun_resbank_handler_p ()
5977 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
5985 /* Push banked registers last to improve delay slot opportunities. */
5986 if (interrupt_handler)
5987 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
5988 if (TEST_HARD_REG_BIT (*mask, i))
5991 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
5992 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
5996 /* Calculate how much extra space is needed to save all callee-saved
5998 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6001 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
6004 int stack_space = 0;
6005 int interrupt_handler = sh_cfun_interrupt_handler_p ();
6007 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6008 if ((! call_really_used_regs[reg] || interrupt_handler)
6009 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6010 /* Leave space to save this target register on the stack,
6011 in case target register allocation wants to use it. */
6012 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6016 /* Decide whether we should reserve space for callee-save target registers,
6017 in case target register allocation wants to use them. REGS_SAVED is
6018 the space, in bytes, that is already required for register saves.
6019 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6022 shmedia_reserve_space_for_target_registers_p (int regs_saved,
6023 HARD_REG_SET *live_regs_mask)
6027 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
6030 /* Decide how much space to reserve for callee-save target registers
6031 in case target register allocation wants to use them.
6032 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6035 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
6037 if (shmedia_space_reserved_for_target_registers)
6038 return shmedia_target_regs_stack_space (live_regs_mask);
6043 /* Work out the registers which need to be saved, both as a mask and a
6044 count of saved words. Return the count.
6046 If doing a pragma interrupt function, then push all regs used by the
6047 function, and if we call another function (we can tell by looking at PR),
6048 make sure that all the regs it clobbers are safe too. */
6051 calc_live_regs (HARD_REG_SET *live_regs_mask)
6056 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6057 bool nosave_low_regs;
6058 int pr_live, has_call;
6060 attrs = DECL_ATTRIBUTES (current_function_decl);
6061 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6062 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6063 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6064 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
6066 CLEAR_HARD_REG_SET (*live_regs_mask);
6067 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
6068 && df_regs_ever_live_p (FPSCR_REG))
6069 target_flags &= ~MASK_FPU_SINGLE;
6070 /* If we can save a lot of saves by switching to double mode, do that. */
6071 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
6072 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6073 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
6074 && (! call_really_used_regs[reg]
6075 || interrupt_handler)
6078 target_flags &= ~MASK_FPU_SINGLE;
6081 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6082 knows how to use it. That means the pseudo originally allocated for
6083 the initial value can become the PR_MEDIA_REG hard register, as seen for
6084 execute/20010122-1.c:test9. */
6086 /* ??? this function is called from initial_elimination_offset, hence we
6087 can't use the result of sh_media_register_for_return here. */
6088 pr_live = sh_pr_n_sets ();
6091 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
6092 pr_live = (pr_initial
6093 ? (GET_CODE (pr_initial) != REG
6094 || REGNO (pr_initial) != (PR_REG))
6095 : df_regs_ever_live_p (PR_REG));
6096 /* For Shcompact, if not optimizing, we end up with a memory reference
6097 using the return address pointer for __builtin_return_address even
6098 though there is no actual need to put the PR register on the stack. */
6099 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
6101 /* Force PR to be live if the prologue has to call the SHmedia
6102 argument decoder or register saver. */
6103 if (TARGET_SHCOMPACT
6104 && ((crtl->args.info.call_cookie
6105 & ~ CALL_COOKIE_RET_TRAMP (1))
6106 || crtl->saves_all_registers))
6108 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
6109 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
6111 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
6114 ? (/* Need to save all the regs ever live. */
6115 (df_regs_ever_live_p (reg)
6116 || (call_really_used_regs[reg]
6117 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
6118 || reg == PIC_OFFSET_TABLE_REGNUM)
6120 || (TARGET_SHMEDIA && has_call
6121 && REGISTER_NATURAL_MODE (reg) == SImode
6122 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
6123 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
6124 && reg != RETURN_ADDRESS_POINTER_REGNUM
6125 && reg != T_REG && reg != GBR_REG
6126 /* Push fpscr only on targets which have FPU */
6127 && (reg != FPSCR_REG || TARGET_FPU_ANY))
6128 : (/* Only push those regs which are used and need to be saved. */
6131 && crtl->args.info.call_cookie
6132 && reg == PIC_OFFSET_TABLE_REGNUM)
6133 || (df_regs_ever_live_p (reg)
6134 && ((!call_really_used_regs[reg]
6135 && !(reg != PIC_OFFSET_TABLE_REGNUM
6136 && fixed_regs[reg] && call_used_regs[reg]))
6137 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
6138 || (crtl->calls_eh_return
6139 && (reg == EH_RETURN_DATA_REGNO (0)
6140 || reg == EH_RETURN_DATA_REGNO (1)
6141 || reg == EH_RETURN_DATA_REGNO (2)
6142 || reg == EH_RETURN_DATA_REGNO (3)))
6143 || ((reg == MACL_REG || reg == MACH_REG)
6144 && df_regs_ever_live_p (reg)
6145 && sh_cfun_attr_renesas_p ())
6148 SET_HARD_REG_BIT (*live_regs_mask, reg);
6149 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6151 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
6152 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
6154 if (FP_REGISTER_P (reg))
6156 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
6158 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
6159 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
6162 else if (XD_REGISTER_P (reg))
6164 /* Must switch to double mode to access these registers. */
6165 target_flags &= ~MASK_FPU_SINGLE;
6169 if (nosave_low_regs && reg == R8_REG)
6172 /* If we have a target register optimization pass after prologue / epilogue
6173 threading, we need to assume all target registers will be live even if
6175 if (flag_branch_target_load_optimize2
6176 && TARGET_SAVE_ALL_TARGET_REGS
6177 && shmedia_space_reserved_for_target_registers)
6178 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6179 if ((! call_really_used_regs[reg] || interrupt_handler)
6180 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6182 SET_HARD_REG_BIT (*live_regs_mask, reg);
6183 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6185 /* If this is an interrupt handler, we don't have any call-clobbered
6186 registers we can conveniently use for target register save/restore.
6187 Make sure we save at least one general purpose register when we need
6188 to save target registers. */
6189 if (interrupt_handler
6190 && hard_reg_set_intersect_p (*live_regs_mask,
6191 reg_class_contents[TARGET_REGS])
6192 && ! hard_reg_set_intersect_p (*live_regs_mask,
6193 reg_class_contents[GENERAL_REGS]))
6195 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6196 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6202 /* Code to generate prologue and epilogue sequences */
6204 /* PUSHED is the number of bytes that are being pushed on the
6205 stack for register saves. Return the frame size, padded
6206 appropriately so that the stack stays properly aligned. */
6207 static HOST_WIDE_INT
6208 rounded_frame_size (int pushed)
6210 HOST_WIDE_INT size = get_frame_size ();
6211 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6213 return ((size + pushed + align - 1) & -align) - pushed;
6216 /* Choose a call-clobbered target-branch register that remains
6217 unchanged along the whole function. We set it up as the return
6218 value in the prologue. */
6220 sh_media_register_for_return (void)
6225 if (! current_function_is_leaf)
6227 if (lookup_attribute ("interrupt_handler",
6228 DECL_ATTRIBUTES (current_function_decl)))
6230 if (sh_cfun_interrupt_handler_p ())
6233 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6235 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6236 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6242 /* The maximum registers we need to save are:
6243 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6244 - 32 floating point registers (for each pair, we save none,
6245 one single precision value, or a double precision value).
6246 - 8 target registers
6247 - add 1 entry for a delimiter. */
6248 #define MAX_SAVED_REGS (62+32+8)
6250 typedef struct save_entry_s
6259 /* There will be a delimiter entry with VOIDmode both at the start and the
6260 end of a filled in schedule. The end delimiter has the offset of the
6261 save with the smallest (i.e. most negative) offset. */
6262 typedef struct save_schedule_s
6264 save_entry entries[MAX_SAVED_REGS + 2];
6265 int temps[MAX_TEMPS+1];
6268 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6269 use reverse order. Returns the last entry written to (not counting
6270 the delimiter). OFFSET_BASE is a number to be added to all offset
6274 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6278 save_entry *entry = schedule->entries;
6282 if (! current_function_interrupt)
6283 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6284 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6285 && ! FUNCTION_ARG_REGNO_P (i)
6286 && i != FIRST_RET_REG
6287 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6288 && ! (crtl->calls_eh_return
6289 && (i == EH_RETURN_STACKADJ_REGNO
6290 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6291 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6292 schedule->temps[tmpx++] = i;
6294 entry->mode = VOIDmode;
6295 entry->offset = offset_base;
6297 /* We loop twice: first, we save 8-byte aligned registers in the
6298 higher addresses, that are known to be aligned. Then, we
6299 proceed to saving 32-bit registers that don't need 8-byte
6301 If this is an interrupt function, all registers that need saving
6302 need to be saved in full. moreover, we need to postpone saving
6303 target registers till we have saved some general purpose registers
6304 we can then use as scratch registers. */
6305 offset = offset_base;
6306 for (align = 1; align >= 0; align--)
6308 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6309 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6311 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6314 if (current_function_interrupt)
6316 if (TARGET_REGISTER_P (i))
6318 if (GENERAL_REGISTER_P (i))
6321 if (mode == SFmode && (i % 2) == 1
6322 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6323 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6330 /* If we're doing the aligned pass and this is not aligned,
6331 or we're doing the unaligned pass and this is aligned,
6333 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6337 if (current_function_interrupt
6338 && GENERAL_REGISTER_P (i)
6339 && tmpx < MAX_TEMPS)
6340 schedule->temps[tmpx++] = i;
6342 offset -= GET_MODE_SIZE (mode);
6345 entry->offset = offset;
6348 if (align && current_function_interrupt)
6349 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6350 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6352 offset -= GET_MODE_SIZE (DImode);
6354 entry->mode = DImode;
6355 entry->offset = offset;
6360 entry->mode = VOIDmode;
6361 entry->offset = offset;
6362 schedule->temps[tmpx] = -1;
6367 sh_expand_prologue (void)
6369 HARD_REG_SET live_regs_mask;
6372 int save_flags = target_flags;
6375 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6377 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6379 /* We have pretend args if we had an object sent partially in registers
6380 and partially on the stack, e.g. a large structure. */
6381 pretend_args = crtl->args.pretend_args_size;
6382 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6383 && (NPARM_REGS(SImode)
6384 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
6386 output_stack_adjust (-pretend_args
6387 - crtl->args.info.stack_regs * 8,
6388 stack_pointer_rtx, 0, NULL);
6390 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
6391 /* We're going to use the PIC register to load the address of the
6392 incoming-argument decoder and/or of the return trampoline from
6393 the GOT, so make sure the PIC register is preserved and
6395 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6397 if (TARGET_SHCOMPACT
6398 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6402 /* First, make all registers with incoming arguments that will
6403 be pushed onto the stack live, so that register renaming
6404 doesn't overwrite them. */
6405 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6406 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
6407 >= NPARM_REGS (SImode) - reg)
6408 for (; reg < NPARM_REGS (SImode); reg++)
6409 emit_insn (gen_shcompact_preserve_incoming_args
6410 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6411 else if (CALL_COOKIE_INT_REG_GET
6412 (crtl->args.info.call_cookie, reg) == 1)
6413 emit_insn (gen_shcompact_preserve_incoming_args
6414 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6416 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6418 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6419 GEN_INT (crtl->args.info.call_cookie));
6420 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6421 gen_rtx_REG (SImode, R0_REG));
6423 else if (TARGET_SHMEDIA)
6425 int tr = sh_media_register_for_return ();
6428 emit_move_insn (gen_rtx_REG (DImode, tr),
6429 gen_rtx_REG (DImode, PR_MEDIA_REG));
6432 /* Emit the code for SETUP_VARARGS. */
6435 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6437 /* Push arg regs as if they'd been provided by caller in stack. */
6438 for (i = 0; i < NPARM_REGS(SImode); i++)
6440 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6443 if (i >= (NPARM_REGS(SImode)
6444 - crtl->args.info.arg_count[(int) SH_ARG_INT]
6452 /* If we're supposed to switch stacks at function entry, do so now. */
6455 /* The argument specifies a variable holding the address of the
6456 stack the interrupt function should switch to/from at entry/exit. */
6458 = ggc_strdup (TREE_STRING_POINTER (TREE_VALUE (sp_switch_attr)));
6459 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6461 emit_insn (gen_sp_switch_1 (sp_switch));
6464 d = calc_live_regs (&live_regs_mask);
6465 /* ??? Maybe we could save some switching if we can move a mode switch
6466 that already happens to be at the function start into the prologue. */
6467 if (target_flags != save_flags && ! current_function_interrupt)
6468 emit_insn (gen_toggle_sz ());
6472 int offset_base, offset;
6474 int offset_in_r0 = -1;
6476 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6477 int total_size, save_size;
6478 save_schedule schedule;
6482 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6483 && ! current_function_interrupt)
6484 r0 = gen_rtx_REG (Pmode, R0_REG);
6486 /* D is the actual number of bytes that we need for saving registers,
6487 however, in initial_elimination_offset we have committed to using
6488 an additional TREGS_SPACE amount of bytes - in order to keep both
6489 addresses to arguments supplied by the caller and local variables
6490 valid, we must keep this gap. Place it between the incoming
6491 arguments and the actually saved registers in a bid to optimize
6492 locality of reference. */
6493 total_size = d + tregs_space;
6494 total_size += rounded_frame_size (total_size);
6495 save_size = total_size - rounded_frame_size (d);
6496 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6497 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6498 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6500 /* If adjusting the stack in a single step costs nothing extra, do so.
6501 I.e. either if a single addi is enough, or we need a movi anyway,
6502 and we don't exceed the maximum offset range (the test for the
6503 latter is conservative for simplicity). */
6505 && (CONST_OK_FOR_I10 (-total_size)
6506 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6507 && total_size <= 2044)))
6508 d_rounding = total_size - save_size;
6510 offset_base = d + d_rounding;
6512 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
6515 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6516 tmp_pnt = schedule.temps;
6517 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6519 enum machine_mode mode = (enum machine_mode) entry->mode;
6520 unsigned int reg = entry->reg;
6521 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
6524 offset = entry->offset;
6526 reg_rtx = gen_rtx_REG (mode, reg);
6528 mem_rtx = gen_frame_mem (mode,
6529 gen_rtx_PLUS (Pmode,
6533 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
6539 if (HAVE_PRE_DECREMENT
6540 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6541 || mem_rtx == NULL_RTX
6542 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6544 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
6546 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
6551 offset += GET_MODE_SIZE (mode);
6555 if (mem_rtx != NULL_RTX)
6558 if (offset_in_r0 == -1)
6560 emit_move_insn (r0, GEN_INT (offset));
6561 offset_in_r0 = offset;
6563 else if (offset != offset_in_r0)
6568 GEN_INT (offset - offset_in_r0)));
6569 offset_in_r0 += offset - offset_in_r0;
6572 if (pre_dec != NULL_RTX)
6578 (Pmode, r0, stack_pointer_rtx));
6582 offset -= GET_MODE_SIZE (mode);
6583 offset_in_r0 -= GET_MODE_SIZE (mode);
6588 mem_rtx = gen_frame_mem (mode, r0);
6590 mem_rtx = gen_frame_mem (mode,
6591 gen_rtx_PLUS (Pmode,
6595 /* We must not use an r0-based address for target-branch
6596 registers or for special registers without pre-dec
6597 memory addresses, since we store their values in r0
6599 gcc_assert (!TARGET_REGISTER_P (reg)
6600 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6601 || mem_rtx == pre_dec));
6604 orig_reg_rtx = reg_rtx;
6605 if (TARGET_REGISTER_P (reg)
6606 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6607 && mem_rtx != pre_dec))
6609 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
6611 emit_move_insn (tmp_reg, reg_rtx);
6613 if (REGNO (tmp_reg) == R0_REG)
6617 gcc_assert (!refers_to_regno_p
6618 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
6621 if (*++tmp_pnt <= 0)
6622 tmp_pnt = schedule.temps;
6629 /* Mark as interesting for dwarf cfi generator */
6630 insn = emit_move_insn (mem_rtx, reg_rtx);
6631 RTX_FRAME_RELATED_P (insn) = 1;
6632 /* If we use an intermediate register for the save, we can't
6633 describe this exactly in cfi as a copy of the to-be-saved
6634 register into the temporary register and then the temporary
6635 register on the stack, because the temporary register can
6636 have a different natural size than the to-be-saved register.
6637 Thus, we gloss over the intermediate copy and pretend we do
6638 a direct save from the to-be-saved register. */
6639 if (REGNO (reg_rtx) != reg)
6643 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
6644 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6647 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
6649 rtx reg_rtx = gen_rtx_REG (mode, reg);
6651 rtx mem_rtx = gen_frame_mem (mode,
6652 gen_rtx_PLUS (Pmode,
6656 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
6657 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6662 gcc_assert (entry->offset == d_rounding);
6665 push_regs (&live_regs_mask, current_function_interrupt);
6667 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
6668 emit_insn (gen_GOTaddr2picreg ());
6670 if (SHMEDIA_REGS_STACK_ADJUST ())
6672 /* This must NOT go through the PLT, otherwise mach and macl
6673 may be clobbered. */
6674 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6676 ? "__GCC_push_shmedia_regs"
6677 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
6678 emit_insn (gen_shmedia_save_restore_regs_compact
6679 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
6682 if (target_flags != save_flags && ! current_function_interrupt)
6683 emit_insn (gen_toggle_sz ());
6685 target_flags = save_flags;
6687 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
6688 stack_pointer_rtx, 0, NULL);
6690 if (frame_pointer_needed)
6691 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
6693 if (TARGET_SHCOMPACT
6694 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6696 /* This must NOT go through the PLT, otherwise mach and macl
6697 may be clobbered. */
6698 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6699 "__GCC_shcompact_incoming_args", SFUNC_GOT);
6700 emit_insn (gen_shcompact_incoming_args ());
6705 sh_expand_epilogue (bool sibcall_p)
6707 HARD_REG_SET live_regs_mask;
6711 int save_flags = target_flags;
6712 int frame_size, save_size;
6713 int fpscr_deferred = 0;
6714 int e = sibcall_p ? -1 : 1;
6716 d = calc_live_regs (&live_regs_mask);
6719 frame_size = rounded_frame_size (d);
6723 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6725 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
6726 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6727 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
6729 total_size = d + tregs_space;
6730 total_size += rounded_frame_size (total_size);
6731 save_size = total_size - frame_size;
6733 /* If adjusting the stack in a single step costs nothing extra, do so.
6734 I.e. either if a single addi is enough, or we need a movi anyway,
6735 and we don't exceed the maximum offset range (the test for the
6736 latter is conservative for simplicity). */
6738 && ! frame_pointer_needed
6739 && (CONST_OK_FOR_I10 (total_size)
6740 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
6741 && total_size <= 2044)))
6742 d_rounding = frame_size;
6744 frame_size -= d_rounding;
6747 if (frame_pointer_needed)
6749 /* We must avoid scheduling the epilogue with previous basic blocks
6750 when exception handling is enabled. See PR/18032. */
6751 if (flag_exceptions)
6752 emit_insn (gen_blockage ());
6753 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
6756 /* We must avoid moving the stack pointer adjustment past code
6757 which reads from the local frame, else an interrupt could
6758 occur after the SP adjustment and clobber data in the local
6760 emit_insn (gen_blockage ());
6761 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
6763 else if (frame_size)
6765 /* We must avoid moving the stack pointer adjustment past code
6766 which reads from the local frame, else an interrupt could
6767 occur after the SP adjustment and clobber data in the local
6769 emit_insn (gen_blockage ());
6770 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
6773 if (SHMEDIA_REGS_STACK_ADJUST ())
6775 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6777 ? "__GCC_pop_shmedia_regs"
6778 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
6779 /* This must NOT go through the PLT, otherwise mach and macl
6780 may be clobbered. */
6781 emit_insn (gen_shmedia_save_restore_regs_compact
6782 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
6785 /* Pop all the registers. */
6787 if (target_flags != save_flags && ! current_function_interrupt)
6788 emit_insn (gen_toggle_sz ());
6791 int offset_base, offset;
6792 int offset_in_r0 = -1;
6794 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
6795 save_schedule schedule;
6799 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
6800 offset_base = -entry[1].offset + d_rounding;
6801 tmp_pnt = schedule.temps;
6802 for (; entry->mode != VOIDmode; entry--)
6804 enum machine_mode mode = (enum machine_mode) entry->mode;
6805 int reg = entry->reg;
6806 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
6808 offset = offset_base + entry->offset;
6809 reg_rtx = gen_rtx_REG (mode, reg);
6811 mem_rtx = gen_frame_mem (mode,
6812 gen_rtx_PLUS (Pmode,
6816 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
6819 if (HAVE_POST_INCREMENT
6820 && (offset == offset_in_r0
6821 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
6822 && mem_rtx == NULL_RTX)
6823 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6825 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
6827 if (!memory_address_p (mode, XEXP (post_inc, 0)))
6828 post_inc = NULL_RTX;
6833 if (mem_rtx != NULL_RTX)
6836 if (offset_in_r0 == -1)
6838 emit_move_insn (r0, GEN_INT (offset));
6839 offset_in_r0 = offset;
6841 else if (offset != offset_in_r0)
6846 GEN_INT (offset - offset_in_r0)));
6847 offset_in_r0 += offset - offset_in_r0;
6850 if (post_inc != NULL_RTX)
6856 (Pmode, r0, stack_pointer_rtx));
6862 offset_in_r0 += GET_MODE_SIZE (mode);
6865 mem_rtx = gen_frame_mem (mode, r0);
6867 mem_rtx = gen_frame_mem (mode,
6868 gen_rtx_PLUS (Pmode,
6872 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6873 || mem_rtx == post_inc);
6876 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6877 && mem_rtx != post_inc)
6879 insn = emit_move_insn (r0, mem_rtx);
6882 else if (TARGET_REGISTER_P (reg))
6884 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
6886 /* Give the scheduler a bit of freedom by using up to
6887 MAX_TEMPS registers in a round-robin fashion. */
6888 insn = emit_move_insn (tmp_reg, mem_rtx);
6891 tmp_pnt = schedule.temps;
6894 insn = emit_move_insn (reg_rtx, mem_rtx);
6897 gcc_assert (entry->offset + offset_base == d + d_rounding);
6899 else /* ! TARGET_SH5 */
6904 /* For an ISR with RESBANK attribute assigned, don't pop PR
6906 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
6907 && !sh_cfun_resbank_handler_p ())
6909 if (!frame_pointer_needed)
6910 emit_insn (gen_blockage ());
6914 /* Banked registers are poped first to avoid being scheduled in the
6915 delay slot. RTE switches banks before the ds instruction. */
6916 if (current_function_interrupt)
6918 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6919 if (TEST_HARD_REG_BIT (live_regs_mask, i))
6920 pop (LAST_BANKED_REG - i);
6922 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
6925 last_reg = FIRST_PSEUDO_REGISTER;
6927 for (i = 0; i < last_reg; i++)
6929 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
6931 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
6932 && hard_reg_set_intersect_p (live_regs_mask,
6933 reg_class_contents[DF_REGS]))
6935 /* For an ISR with RESBANK attribute assigned, don't pop
6936 following registers, R0-R14, MACH, MACL and GBR. */
6937 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
6938 && ! (sh_cfun_resbank_handler_p ()
6939 && ((j >= FIRST_GENERAL_REG
6940 && j < LAST_GENERAL_REG)
6946 if (j == FIRST_FP_REG && fpscr_deferred)
6950 if (target_flags != save_flags && ! current_function_interrupt)
6951 emit_insn (gen_toggle_sz ());
6952 target_flags = save_flags;
6954 output_stack_adjust (crtl->args.pretend_args_size
6955 + save_size + d_rounding
6956 + crtl->args.info.stack_regs * 8,
6957 stack_pointer_rtx, e, NULL);
6959 if (crtl->calls_eh_return)
6960 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
6961 EH_RETURN_STACKADJ_RTX));
6963 /* Switch back to the normal stack if necessary. */
6964 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
6965 emit_insn (gen_sp_switch_2 ());
6967 /* Tell flow the insn that pops PR isn't dead. */
6968 /* PR_REG will never be live in SHmedia mode, and we don't need to
6969 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
6970 by the return pattern. */
6971 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
6972 emit_use (gen_rtx_REG (SImode, PR_REG));
6975 static int sh_need_epilogue_known = 0;
6978 sh_need_epilogue (void)
6980 if (! sh_need_epilogue_known)
6985 sh_expand_epilogue (0);
6986 epilogue = get_insns ();
6988 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
6990 return sh_need_epilogue_known > 0;
6993 /* Emit code to change the current function's return address to RA.
6994 TEMP is available as a scratch register, if needed. */
6997 sh_set_return_address (rtx ra, rtx tmp)
6999 HARD_REG_SET live_regs_mask;
7001 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7004 d = calc_live_regs (&live_regs_mask);
7006 /* If pr_reg isn't life, we can set it (or the register given in
7007 sh_media_register_for_return) directly. */
7008 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7014 int rr_regno = sh_media_register_for_return ();
7019 rr = gen_rtx_REG (DImode, rr_regno);
7022 rr = gen_rtx_REG (SImode, pr_reg);
7024 emit_insn (GEN_MOV (rr, ra));
7025 /* Tell flow the register for return isn't dead. */
7033 save_schedule schedule;
7036 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
7037 offset = entry[1].offset;
7038 for (; entry->mode != VOIDmode; entry--)
7039 if (entry->reg == pr_reg)
7042 /* We can't find pr register. */
7046 offset = entry->offset - offset;
7047 pr_offset = (rounded_frame_size (d) + offset
7048 + SHMEDIA_REGS_STACK_ADJUST ());
7051 pr_offset = rounded_frame_size (d);
7053 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7054 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7056 tmp = gen_frame_mem (Pmode, tmp);
7057 emit_insn (GEN_MOV (tmp, ra));
7058 /* Tell this store isn't dead. */
7062 /* Clear variables at function end. */
7065 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7066 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7068 sh_need_epilogue_known = 0;
7072 sh_builtin_saveregs (void)
7074 /* First unnamed integer register. */
7075 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
7076 /* Number of integer registers we need to save. */
7077 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7078 /* First unnamed SFmode float reg */
7079 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
7080 /* Number of SFmode float regs to save. */
7081 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
7084 alias_set_type alias_set;
7090 int pushregs = n_intregs;
7092 while (pushregs < NPARM_REGS (SImode) - 1
7093 && (CALL_COOKIE_INT_REG_GET
7094 (crtl->args.info.call_cookie,
7095 NPARM_REGS (SImode) - pushregs)
7098 crtl->args.info.call_cookie
7099 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7104 if (pushregs == NPARM_REGS (SImode))
7105 crtl->args.info.call_cookie
7106 |= (CALL_COOKIE_INT_REG (0, 1)
7107 | CALL_COOKIE_STACKSEQ (pushregs - 1));
7109 crtl->args.info.call_cookie
7110 |= CALL_COOKIE_STACKSEQ (pushregs);
7112 crtl->args.pretend_args_size += 8 * n_intregs;
7114 if (TARGET_SHCOMPACT)
7118 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
7120 error ("__builtin_saveregs not supported by this subtarget");
7127 /* Allocate block of memory for the regs. */
7128 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7129 Or can assign_stack_local accept a 0 SIZE argument? */
7130 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7133 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
7134 else if (n_floatregs & 1)
7138 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7139 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7140 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7141 regbuf = change_address (regbuf, BLKmode, addr);
7143 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7147 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7148 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7149 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7150 emit_insn (gen_andsi3 (addr, addr, mask));
7151 regbuf = change_address (regbuf, BLKmode, addr);
7154 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7155 alias_set = get_varargs_alias_set ();
7156 set_mem_alias_set (regbuf, alias_set);
7159 This is optimized to only save the regs that are necessary. Explicitly
7160 named args need not be saved. */
7162 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7163 adjust_address (regbuf, BLKmode,
7164 n_floatregs * UNITS_PER_WORD),
7168 /* Return the address of the regbuf. */
7169 return XEXP (regbuf, 0);
7172 This is optimized to only save the regs that are necessary. Explicitly
7173 named args need not be saved.
7174 We explicitly build a pointer to the buffer because it halves the insn
7175 count when not optimizing (otherwise the pointer is built for each reg
7177 We emit the moves in reverse order so that we can use predecrement. */
7179 fpregs = copy_to_mode_reg (Pmode,
7180 plus_constant (XEXP (regbuf, 0),
7181 n_floatregs * UNITS_PER_WORD));
7182 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7185 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7187 emit_insn (gen_addsi3 (fpregs, fpregs,
7188 GEN_INT (-2 * UNITS_PER_WORD)));
7189 mem = change_address (regbuf, DFmode, fpregs);
7190 emit_move_insn (mem,
7191 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7193 regno = first_floatreg;
7196 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7197 mem = change_address (regbuf, SFmode, fpregs);
7198 emit_move_insn (mem,
7199 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7200 - (TARGET_LITTLE_ENDIAN != 0)));
7204 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7208 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7209 mem = change_address (regbuf, SFmode, fpregs);
7210 emit_move_insn (mem,
7211 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7214 /* Return the address of the regbuf. */
7215 return XEXP (regbuf, 0);
7218 /* Define the `__builtin_va_list' type for the ABI. */
7221 sh_build_builtin_va_list (void)
7223 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7226 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7227 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7228 return ptr_type_node;
7230 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7232 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
7234 f_next_o_limit = build_decl (FIELD_DECL,
7235 get_identifier ("__va_next_o_limit"),
7237 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
7239 f_next_fp_limit = build_decl (FIELD_DECL,
7240 get_identifier ("__va_next_fp_limit"),
7242 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
7245 DECL_FIELD_CONTEXT (f_next_o) = record;
7246 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7247 DECL_FIELD_CONTEXT (f_next_fp) = record;
7248 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7249 DECL_FIELD_CONTEXT (f_next_stack) = record;
7251 TYPE_FIELDS (record) = f_next_o;
7252 TREE_CHAIN (f_next_o) = f_next_o_limit;
7253 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7254 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7255 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7257 layout_type (record);
7262 /* Implement `va_start' for varargs and stdarg. */
7265 sh_va_start (tree valist, rtx nextarg)
7267 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7268 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7274 expand_builtin_saveregs ();
7275 std_expand_builtin_va_start (valist, nextarg);
7279 if ((! TARGET_SH2E && ! TARGET_SH4)
7280 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7282 std_expand_builtin_va_start (valist, nextarg);
7286 f_next_o = TYPE_FIELDS (va_list_type_node);
7287 f_next_o_limit = TREE_CHAIN (f_next_o);
7288 f_next_fp = TREE_CHAIN (f_next_o_limit);
7289 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7290 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7292 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7294 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7295 valist, f_next_o_limit, NULL_TREE);
7296 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7298 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7299 valist, f_next_fp_limit, NULL_TREE);
7300 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7301 valist, f_next_stack, NULL_TREE);
7303 /* Call __builtin_saveregs. */
7304 u = make_tree (sizetype, expand_builtin_saveregs ());
7305 u = fold_convert (ptr_type_node, u);
7306 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7307 TREE_SIDE_EFFECTS (t) = 1;
7308 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7310 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7315 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7316 size_int (UNITS_PER_WORD * nfp));
7317 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7318 TREE_SIDE_EFFECTS (t) = 1;
7319 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7321 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7322 TREE_SIDE_EFFECTS (t) = 1;
7323 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7325 nint = crtl->args.info.arg_count[SH_ARG_INT];
7330 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7331 size_int (UNITS_PER_WORD * nint));
7332 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7333 TREE_SIDE_EFFECTS (t) = 1;
7334 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7336 u = make_tree (ptr_type_node, nextarg);
7337 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7338 TREE_SIDE_EFFECTS (t) = 1;
7339 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7342 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7343 member, return it. */
7345 find_sole_member (tree type)
7347 tree field, member = NULL_TREE;
7349 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7351 if (TREE_CODE (field) != FIELD_DECL)
7353 if (!DECL_SIZE (field))
7355 if (integer_zerop (DECL_SIZE (field)))
7363 /* Implement `va_arg'. */
7366 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7367 gimple_seq *post_p ATTRIBUTE_UNUSED)
7369 HOST_WIDE_INT size, rsize;
7370 tree tmp, pptr_type_node;
7371 tree addr, lab_over = NULL, result = NULL;
7372 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7376 type = build_pointer_type (type);
7378 size = int_size_in_bytes (type);
7379 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7380 pptr_type_node = build_pointer_type (ptr_type_node);
7382 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7383 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7385 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7386 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7391 f_next_o = TYPE_FIELDS (va_list_type_node);
7392 f_next_o_limit = TREE_CHAIN (f_next_o);
7393 f_next_fp = TREE_CHAIN (f_next_o_limit);
7394 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7395 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7397 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7399 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7400 valist, f_next_o_limit, NULL_TREE);
7401 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7402 valist, f_next_fp, NULL_TREE);
7403 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7404 valist, f_next_fp_limit, NULL_TREE);
7405 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7406 valist, f_next_stack, NULL_TREE);
7408 /* Structures with a single member with a distinct mode are passed
7409 like their member. This is relevant if the latter has a REAL_TYPE
7410 or COMPLEX_TYPE type. */
7412 while (TREE_CODE (eff_type) == RECORD_TYPE
7413 && (member = find_sole_member (eff_type))
7414 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7415 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7416 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7418 tree field_type = TREE_TYPE (member);
7420 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7421 eff_type = field_type;
7424 gcc_assert ((TYPE_ALIGN (eff_type)
7425 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7426 || (TYPE_ALIGN (eff_type)
7427 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7432 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7434 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7435 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7436 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7441 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7444 addr = create_tmp_var (pptr_type_node, NULL);
7445 lab_false = create_artificial_label ();
7446 lab_over = create_artificial_label ();
7448 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
7452 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7454 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7456 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
7457 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7459 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
7460 tmp = next_fp_limit;
7461 if (size > 4 && !is_double)
7462 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp),
7463 unshare_expr (tmp), size_int (4 - size));
7464 tmp = build2 (GE_EXPR, boolean_type_node,
7465 unshare_expr (next_fp_tmp), unshare_expr (tmp));
7466 cmp = build3 (COND_EXPR, void_type_node, tmp,
7467 build1 (GOTO_EXPR, void_type_node,
7468 unshare_expr (lab_false)), NULL_TREE);
7470 gimplify_and_add (cmp, pre_p);
7472 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7473 || (is_double || size == 16))
7475 tmp = fold_convert (sizetype, next_fp_tmp);
7476 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7477 size_int (UNITS_PER_WORD));
7478 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7479 unshare_expr (next_fp_tmp), tmp);
7480 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
7483 gimplify_and_add (cmp, pre_p);
7485 #ifdef FUNCTION_ARG_SCmode_WART
7486 if (TYPE_MODE (eff_type) == SCmode
7487 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7489 tree subtype = TREE_TYPE (eff_type);
7493 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7494 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7497 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7498 real = get_initialized_tmp_var (real, pre_p, NULL);
7500 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
7501 if (type != eff_type)
7502 result = build1 (VIEW_CONVERT_EXPR, type, result);
7503 result = get_initialized_tmp_var (result, pre_p, NULL);
7505 #endif /* FUNCTION_ARG_SCmode_WART */
7507 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7508 gimplify_and_add (tmp, pre_p);
7510 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7511 gimplify_and_add (tmp, pre_p);
7513 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7514 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7515 gimplify_assign (unshare_expr (next_fp_tmp),
7516 unshare_expr (valist), pre_p);
7518 gimplify_assign (unshare_expr (valist),
7519 unshare_expr (next_fp_tmp), post_p);
7520 valist = next_fp_tmp;
7524 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7525 unshare_expr (next_o), size_int (rsize));
7526 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
7527 unshare_expr (next_o_limit));
7528 tmp = build3 (COND_EXPR, void_type_node, tmp,
7529 build1 (GOTO_EXPR, void_type_node,
7530 unshare_expr (lab_false)),
7532 gimplify_and_add (tmp, pre_p);
7534 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
7535 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7537 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7538 gimplify_and_add (tmp, pre_p);
7540 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7541 gimplify_and_add (tmp, pre_p);
7543 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7544 gimplify_assign (unshare_expr (next_o),
7545 unshare_expr (next_o_limit), pre_p);
7547 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7548 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7553 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7554 gimplify_and_add (tmp, pre_p);
7558 /* ??? In va-sh.h, there had been code to make values larger than
7559 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7561 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7564 gimplify_assign (result, tmp, pre_p);
7566 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7567 gimplify_and_add (tmp, pre_p);
7573 result = build_va_arg_indirect_ref (result);
7578 /* 64 bit floating points memory transfers are paired single precision loads
7579 or store. So DWARF information needs fixing in little endian (unless
7580 PR=SZ=1 in FPSCR). */
7582 sh_dwarf_register_span (rtx reg)
7584 unsigned regno = REGNO (reg);
7586 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
7590 gen_rtx_PARALLEL (VOIDmode,
7592 gen_rtx_REG (SFmode,
7593 DBX_REGISTER_NUMBER (regno+1)),
7594 gen_rtx_REG (SFmode,
7595 DBX_REGISTER_NUMBER (regno))));
7599 sh_promote_prototypes (const_tree type)
7605 return ! sh_attr_renesas_p (type);
7608 /* Whether an argument must be passed by reference. On SHcompact, we
7609 pretend arguments wider than 32-bits that would have been passed in
7610 registers are passed by reference, so that an SHmedia trampoline
7611 loads them into the full 64-bits registers. */
7614 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
7615 const_tree type, bool named)
7617 unsigned HOST_WIDE_INT size;
7620 size = int_size_in_bytes (type);
7622 size = GET_MODE_SIZE (mode);
7624 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
7626 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
7627 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
7628 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
7630 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
7631 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7638 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7639 const_tree type, bool named)
7641 if (targetm.calls.must_pass_in_stack (mode, type))
7644 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7645 wants to know about pass-by-reference semantics for incoming
7650 if (TARGET_SHCOMPACT)
7652 cum->byref = shcompact_byref (cum, mode, type, named);
7653 return cum->byref != 0;
7660 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7661 const_tree type, bool named ATTRIBUTE_UNUSED)
7663 /* ??? How can it possibly be correct to return true only on the
7664 caller side of the equation? Is there someplace else in the
7665 sh backend that's magically producing the copies? */
7666 return (cum->outgoing
7667 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
7668 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
7672 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7673 tree type, bool named ATTRIBUTE_UNUSED)
7678 && PASS_IN_REG_P (*cum, mode, type)
7679 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7680 && (ROUND_REG (*cum, mode)
7682 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
7683 : ROUND_ADVANCE (int_size_in_bytes (type)))
7684 > NPARM_REGS (mode)))
7685 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
7687 else if (!TARGET_SHCOMPACT
7688 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7689 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
7691 return words * UNITS_PER_WORD;
7695 /* Define where to put the arguments to a function.
7696 Value is zero to push the argument on the stack,
7697 or a hard register in which to store the argument.
7699 MODE is the argument's machine mode.
7700 TYPE is the data type of the argument (as a tree).
7701 This is null for libcalls where that information may
7703 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7704 the preceding args and about the function being called.
7705 NAMED is nonzero if this argument is a named parameter
7706 (otherwise it is an extra parameter matching an ellipsis).
7708 On SH the first args are normally in registers
7709 and the rest are pushed. Any arg that starts within the first
7710 NPARM_REGS words is at least partially passed in a register unless
7711 its data type forbids. */
7715 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7716 tree type, int named)
7718 if (! TARGET_SH5 && mode == VOIDmode)
7719 return GEN_INT (ca->renesas_abi ? 1 : 0);
7722 && PASS_IN_REG_P (*ca, mode, type)
7723 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
7727 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
7728 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
7730 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
7731 gen_rtx_REG (SFmode,
7733 + (ROUND_REG (*ca, mode) ^ 1)),
7735 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
7736 gen_rtx_REG (SFmode,
7738 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
7740 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
7743 /* If the alignment of a DF value causes an SF register to be
7744 skipped, we will use that skipped register for the next SF
7746 if ((TARGET_HITACHI || ca->renesas_abi)
7747 && ca->free_single_fp_reg
7749 return gen_rtx_REG (mode, ca->free_single_fp_reg);
7751 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
7752 ^ (mode == SFmode && TARGET_SH4
7753 && TARGET_LITTLE_ENDIAN != 0
7754 && ! TARGET_HITACHI && ! ca->renesas_abi);
7755 return gen_rtx_REG (mode, regno);
7761 if (mode == VOIDmode && TARGET_SHCOMPACT)
7762 return GEN_INT (ca->call_cookie);
7764 /* The following test assumes unnamed arguments are promoted to
7766 if (mode == SFmode && ca->free_single_fp_reg)
7767 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
7769 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
7770 && (named || ! ca->prototype_p)
7771 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
7773 if (! ca->prototype_p && TARGET_SHMEDIA)
7774 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
7776 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
7778 + ca->arg_count[(int) SH_ARG_FLOAT]);
7781 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
7782 && (! TARGET_SHCOMPACT
7783 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
7784 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
7787 return gen_rtx_REG (mode, (FIRST_PARM_REG
7788 + ca->arg_count[(int) SH_ARG_INT]));
7797 /* Update the data in CUM to advance over an argument
7798 of mode MODE and data type TYPE.
7799 (TYPE is null for libcalls where that information may not be
7803 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7804 tree type, int named)
7808 else if (TARGET_SH5)
7810 tree type2 = (ca->byref && type
7813 enum machine_mode mode2 = (ca->byref && type
7816 int dwords = ((ca->byref
7819 ? int_size_in_bytes (type2)
7820 : GET_MODE_SIZE (mode2)) + 7) / 8;
7821 int numregs = MIN (dwords, NPARM_REGS (SImode)
7822 - ca->arg_count[(int) SH_ARG_INT]);
7826 ca->arg_count[(int) SH_ARG_INT] += numregs;
7827 if (TARGET_SHCOMPACT
7828 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
7831 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7833 /* N.B. We want this also for outgoing. */
7834 ca->stack_regs += numregs;
7839 ca->stack_regs += numregs;
7840 ca->byref_regs += numregs;
7844 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7848 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7851 else if (dwords > numregs)
7853 int pushregs = numregs;
7855 if (TARGET_SHCOMPACT)
7856 ca->stack_regs += numregs;
7857 while (pushregs < NPARM_REGS (SImode) - 1
7858 && (CALL_COOKIE_INT_REG_GET
7860 NPARM_REGS (SImode) - pushregs)
7864 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7868 if (numregs == NPARM_REGS (SImode))
7870 |= CALL_COOKIE_INT_REG (0, 1)
7871 | CALL_COOKIE_STACKSEQ (numregs - 1);
7874 |= CALL_COOKIE_STACKSEQ (numregs);
7877 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
7878 && (named || ! ca->prototype_p))
7880 if (mode2 == SFmode && ca->free_single_fp_reg)
7881 ca->free_single_fp_reg = 0;
7882 else if (ca->arg_count[(int) SH_ARG_FLOAT]
7883 < NPARM_REGS (SFmode))
7886 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
7888 - ca->arg_count[(int) SH_ARG_FLOAT]);
7890 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
7892 if (TARGET_SHCOMPACT && ! ca->prototype_p)
7894 if (ca->outgoing && numregs > 0)
7898 |= (CALL_COOKIE_INT_REG
7899 (ca->arg_count[(int) SH_ARG_INT]
7900 - numregs + ((numfpregs - 2) / 2),
7901 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
7904 while (numfpregs -= 2);
7906 else if (mode2 == SFmode && (named)
7907 && (ca->arg_count[(int) SH_ARG_FLOAT]
7908 < NPARM_REGS (SFmode)))
7909 ca->free_single_fp_reg
7910 = FIRST_FP_PARM_REG - numfpregs
7911 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
7917 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
7919 /* Note that we've used the skipped register. */
7920 if (mode == SFmode && ca->free_single_fp_reg)
7922 ca->free_single_fp_reg = 0;
7925 /* When we have a DF after an SF, there's an SF register that get
7926 skipped in order to align the DF value. We note this skipped
7927 register, because the next SF value will use it, and not the
7928 SF that follows the DF. */
7930 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
7932 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
7933 + BASE_ARG_REG (mode));
7937 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
7938 || PASS_IN_REG_P (*ca, mode, type))
7939 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
7940 = (ROUND_REG (*ca, mode)
7942 ? ROUND_ADVANCE (int_size_in_bytes (type))
7943 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
7946 /* The Renesas calling convention doesn't quite fit into this scheme since
7947 the address is passed like an invisible argument, but one that is always
7948 passed in memory. */
7950 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
7952 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7954 return gen_rtx_REG (Pmode, 2);
7957 /* Worker function for TARGET_RETURN_IN_MEMORY. */
7960 sh_return_in_memory (const_tree type, const_tree fndecl)
7964 if (TYPE_MODE (type) == BLKmode)
7965 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
7967 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
7971 return (TYPE_MODE (type) == BLKmode
7972 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7973 && TREE_CODE (type) == RECORD_TYPE));
7977 /* We actually emit the code in sh_expand_prologue. We used to use
7978 a static variable to flag that we need to emit this code, but that
7979 doesn't when inlining, when functions are deferred and then emitted
7980 later. Fortunately, we already have two flags that are part of struct
7981 function that tell if a function uses varargs or stdarg. */
7983 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
7984 enum machine_mode mode,
7986 int *pretend_arg_size,
7987 int second_time ATTRIBUTE_UNUSED)
7989 gcc_assert (cfun->stdarg);
7990 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
7992 int named_parm_regs, anon_parm_regs;
7994 named_parm_regs = (ROUND_REG (*ca, mode)
7996 ? ROUND_ADVANCE (int_size_in_bytes (type))
7997 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
7998 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
7999 if (anon_parm_regs > 0)
8000 *pretend_arg_size = anon_parm_regs * 4;
8005 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
8011 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
8013 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
8017 /* Define the offset between two registers, one to be eliminated, and
8018 the other its replacement, at the start of a routine. */
8021 initial_elimination_offset (int from, int to)
8024 int regs_saved_rounding = 0;
8025 int total_saved_regs_space;
8026 int total_auto_space;
8027 int save_flags = target_flags;
8029 HARD_REG_SET live_regs_mask;
8031 shmedia_space_reserved_for_target_registers = false;
8032 regs_saved = calc_live_regs (&live_regs_mask);
8033 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
8035 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
8037 shmedia_space_reserved_for_target_registers = true;
8038 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
8041 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
8042 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8043 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
8045 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8046 copy_flags = target_flags;
8047 target_flags = save_flags;
8049 total_saved_regs_space = regs_saved + regs_saved_rounding;
8051 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8052 return total_saved_regs_space + total_auto_space
8053 + crtl->args.info.byref_regs * 8;
8055 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8056 return total_saved_regs_space + total_auto_space
8057 + crtl->args.info.byref_regs * 8;
8059 /* Initial gap between fp and sp is 0. */
8060 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8063 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8064 return rounded_frame_size (0);
8066 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8067 return rounded_frame_size (0);
8069 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
8070 && (to == HARD_FRAME_POINTER_REGNUM
8071 || to == STACK_POINTER_REGNUM));
8074 int n = total_saved_regs_space;
8075 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
8076 save_schedule schedule;
8079 n += total_auto_space;
8081 /* If it wasn't saved, there's not much we can do. */
8082 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
8085 target_flags = copy_flags;
8087 sh5_schedule_saves (&live_regs_mask, &schedule, n);
8088 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
8089 if (entry->reg == pr_reg)
8091 target_flags = save_flags;
8092 return entry->offset;
8097 return total_auto_space;
8100 /* Parse the -mfixed-range= option string. */
8102 sh_fix_range (const char *const_str)
8105 char *str, *dash, *comma;
8107 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8108 REG2 are either register names or register numbers. The effect
8109 of this option is to mark the registers in the range from REG1 to
8110 REG2 as ``fixed'' so they won't be used by the compiler. */
8112 i = strlen (const_str);
8113 str = (char *) alloca (i + 1);
8114 memcpy (str, const_str, i + 1);
8118 dash = strchr (str, '-');
8121 warning (0, "value of -mfixed-range must have form REG1-REG2");
8125 comma = strchr (dash + 1, ',');
8129 first = decode_reg_name (str);
8132 warning (0, "unknown register name: %s", str);
8136 last = decode_reg_name (dash + 1);
8139 warning (0, "unknown register name: %s", dash + 1);
8147 warning (0, "%s-%s is an empty range", str, dash + 1);
8151 for (i = first; i <= last; ++i)
8152 fixed_regs[i] = call_used_regs[i] = 1;
8162 /* Insert any deferred function attributes from earlier pragmas. */
8164 sh_insert_attributes (tree node, tree *attributes)
8168 if (TREE_CODE (node) != FUNCTION_DECL)
8171 /* We are only interested in fields. */
8175 /* Append the attributes to the deferred attributes. */
8176 *sh_deferred_function_attributes_tail = *attributes;
8177 attrs = sh_deferred_function_attributes;
8181 /* Some attributes imply or require the interrupt attribute. */
8182 if (!lookup_attribute ("interrupt_handler", attrs)
8183 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8185 /* If we have a trapa_handler, but no interrupt_handler attribute,
8186 insert an interrupt_handler attribute. */
8187 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8188 /* We can't use sh_pr_interrupt here because that's not in the
8191 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8192 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8193 if the interrupt attribute is missing, we ignore the attribute
8195 else if (lookup_attribute ("sp_switch", attrs)
8196 || lookup_attribute ("trap_exit", attrs)
8197 || lookup_attribute ("nosave_low_regs", attrs)
8198 || lookup_attribute ("resbank", attrs))
8202 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8204 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8205 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8206 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8207 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8208 warning (OPT_Wattributes,
8209 "%qE attribute only applies to interrupt functions",
8210 TREE_PURPOSE (attrs));
8213 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8215 tail = &TREE_CHAIN (*tail);
8218 attrs = *attributes;
8222 /* Install the processed list. */
8223 *attributes = attrs;
8225 /* Clear deferred attributes. */
8226 sh_deferred_function_attributes = NULL_TREE;
8227 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8232 /* Supported attributes:
8234 interrupt_handler -- specifies this function is an interrupt handler.
8236 trapa_handler - like above, but don't save all registers.
8238 sp_switch -- specifies an alternate stack for an interrupt handler
8241 trap_exit -- use a trapa to exit an interrupt function instead of
8244 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8245 This is useful on the SH3 and upwards,
8246 which has a separate set of low regs for User and Supervisor modes.
8247 This should only be used for the lowest level of interrupts. Higher levels
8248 of interrupts must save the registers in case they themselves are
8251 renesas -- use Renesas calling/layout conventions (functions and
8254 resbank -- In case of an ISR, use a register bank to save registers
8255 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8258 const struct attribute_spec sh_attribute_table[] =
8260 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8261 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8262 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
8263 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
8264 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
8265 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8266 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8267 { "resbank", 0, 0, true, false, false, sh_handle_resbank_handler_attribute },
8268 { "function_vector", 1, 1, true, false, false, sh2a_handle_function_vector_handler_attribute },
8270 /* Symbian support adds three new attributes:
8271 dllexport - for exporting a function/variable that will live in a dll
8272 dllimport - for importing a function/variable from a dll
8274 Microsoft allows multiple declspecs in one __declspec, separating
8275 them with spaces. We do NOT support this. Instead, use __declspec
8277 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8278 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8280 { NULL, 0, 0, false, false, false, NULL }
8283 /* Handle a 'resbank' attribute. */
8285 sh_handle_resbank_handler_attribute (tree * node, tree name,
8286 tree args ATTRIBUTE_UNUSED,
8287 int flags ATTRIBUTE_UNUSED,
8288 bool * no_add_attrs)
8292 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8294 *no_add_attrs = true;
8296 if (TREE_CODE (*node) != FUNCTION_DECL)
8298 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8300 *no_add_attrs = true;
8306 /* Handle an "interrupt_handler" attribute; arguments as in
8307 struct attribute_spec.handler. */
8309 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8310 tree args ATTRIBUTE_UNUSED,
8311 int flags ATTRIBUTE_UNUSED,
8314 if (TREE_CODE (*node) != FUNCTION_DECL)
8316 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8318 *no_add_attrs = true;
8320 else if (TARGET_SHCOMPACT)
8322 error ("attribute interrupt_handler is not compatible with -m5-compact");
8323 *no_add_attrs = true;
8329 /* Handle an 'function_vector' attribute; arguments as in
8330 struct attribute_spec.handler. */
8332 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8333 tree args ATTRIBUTE_UNUSED,
8334 int flags ATTRIBUTE_UNUSED,
8335 bool * no_add_attrs)
8339 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8341 *no_add_attrs = true;
8343 else if (TREE_CODE (*node) != FUNCTION_DECL)
8345 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8347 *no_add_attrs = true;
8349 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8351 /* The argument must be a constant integer. */
8352 warning (OPT_Wattributes,
8353 "%qE attribute argument not an integer constant",
8355 *no_add_attrs = true;
8357 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8359 /* The argument value must be between 0 to 255. */
8360 warning (OPT_Wattributes,
8361 "%qE attribute argument should be between 0 to 255",
8363 *no_add_attrs = true;
8368 /* Returns 1 if current function has been assigned the attribute
8369 'function_vector'. */
8371 sh2a_is_function_vector_call (rtx x)
8373 if (GET_CODE (x) == SYMBOL_REF
8374 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8376 tree tr = SYMBOL_REF_DECL (x);
8378 if (sh2a_function_vector_p (tr))
8385 /* Returns the function vector number, if the the attribute
8386 'function_vector' is assigned, otherwise returns zero. */
8388 sh2a_get_function_vector_number (rtx x)
8393 if ((GET_CODE (x) == SYMBOL_REF)
8394 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8396 t = SYMBOL_REF_DECL (x);
8398 if (TREE_CODE (t) != FUNCTION_DECL)
8401 list = SH_ATTRIBUTES (t);
8404 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8406 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8410 list = TREE_CHAIN (list);
8419 /* Handle an "sp_switch" attribute; arguments as in
8420 struct attribute_spec.handler. */
8422 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8423 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8425 if (TREE_CODE (*node) != FUNCTION_DECL)
8427 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8429 *no_add_attrs = true;
8431 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8433 /* The argument must be a constant string. */
8434 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
8436 *no_add_attrs = true;
8442 /* Handle an "trap_exit" attribute; arguments as in
8443 struct attribute_spec.handler. */
8445 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8446 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8448 if (TREE_CODE (*node) != FUNCTION_DECL)
8450 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8452 *no_add_attrs = true;
8454 /* The argument specifies a trap number to be used in a trapa instruction
8455 at function exit (instead of an rte instruction). */
8456 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8458 /* The argument must be a constant integer. */
8459 warning (OPT_Wattributes, "%qE attribute argument not an "
8460 "integer constant", name);
8461 *no_add_attrs = true;
8468 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8469 tree name ATTRIBUTE_UNUSED,
8470 tree args ATTRIBUTE_UNUSED,
8471 int flags ATTRIBUTE_UNUSED,
8472 bool *no_add_attrs ATTRIBUTE_UNUSED)
8477 /* True if __attribute__((renesas)) or -mrenesas. */
8479 sh_attr_renesas_p (const_tree td)
8486 td = TREE_TYPE (td);
8487 if (td == error_mark_node)
8489 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8493 /* True if __attribute__((renesas)) or -mrenesas, for the current
8496 sh_cfun_attr_renesas_p (void)
8498 return sh_attr_renesas_p (current_function_decl);
8502 sh_cfun_interrupt_handler_p (void)
8504 return (lookup_attribute ("interrupt_handler",
8505 DECL_ATTRIBUTES (current_function_decl))
8509 /* Returns 1 if FUNC has been assigned the attribute
8510 "function_vector". */
8512 sh2a_function_vector_p (tree func)
8515 if (TREE_CODE (func) != FUNCTION_DECL)
8518 list = SH_ATTRIBUTES (func);
8521 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8524 list = TREE_CHAIN (list);
8529 /* Returns TRUE if given tree has the "resbank" attribute. */
8532 sh_cfun_resbank_handler_p (void)
8534 return ((lookup_attribute ("resbank",
8535 DECL_ATTRIBUTES (current_function_decl))
8537 && (lookup_attribute ("interrupt_handler",
8538 DECL_ATTRIBUTES (current_function_decl))
8539 != NULL_TREE) && TARGET_SH2A);
8542 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8545 sh_check_pch_target_flags (int old_flags)
8547 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8548 | MASK_SH_E | MASK_HARD_SH4
8549 | MASK_FPU_SINGLE | MASK_SH4))
8550 return _("created and used with different architectures / ABIs");
8551 if ((old_flags ^ target_flags) & MASK_HITACHI)
8552 return _("created and used with different ABIs");
8553 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8554 return _("created and used with different endianness");
8558 /* Predicates used by the templates. */
8560 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
8561 Used only in general_movsrc_operand. */
8564 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8576 /* Nonzero if OP is a floating point value with value 0.0. */
8579 fp_zero_operand (rtx op)
8583 if (GET_MODE (op) != SFmode)
8586 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8587 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
8590 /* Nonzero if OP is a floating point value with value 1.0. */
8593 fp_one_operand (rtx op)
8597 if (GET_MODE (op) != SFmode)
8600 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8601 return REAL_VALUES_EQUAL (r, dconst1);
8604 /* For -m4 and -m4-single-only, mode switching is used. If we are
8605 compiling without -mfmovd, movsf_ie isn't taken into account for
8606 mode switching. We could check in machine_dependent_reorg for
8607 cases where we know we are in single precision mode, but there is
8608 interface to find that out during reload, so we must avoid
8609 choosing an fldi alternative during reload and thus failing to
8610 allocate a scratch register for the constant loading. */
8614 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
8618 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8620 enum rtx_code code = GET_CODE (op);
8621 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
8624 /* Return the TLS type for TLS symbols, 0 for otherwise. */
8626 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8628 if (GET_CODE (op) != SYMBOL_REF)
8629 return TLS_MODEL_NONE;
8630 return SYMBOL_REF_TLS_MODEL (op);
8633 /* Return the destination address of a branch. */
8636 branch_dest (rtx branch)
8638 rtx dest = SET_SRC (PATTERN (branch));
8641 if (GET_CODE (dest) == IF_THEN_ELSE)
8642 dest = XEXP (dest, 1);
8643 dest = XEXP (dest, 0);
8644 dest_uid = INSN_UID (dest);
8645 return INSN_ADDRESSES (dest_uid);
8648 /* Return nonzero if REG is not used after INSN.
8649 We assume REG is a reload reg, and therefore does
8650 not live past labels. It may live past calls or jumps though. */
8652 reg_unused_after (rtx reg, rtx insn)
8657 /* If the reg is set by this instruction, then it is safe for our
8658 case. Disregard the case where this is a store to memory, since
8659 we are checking a register used in the store address. */
8660 set = single_set (insn);
8661 if (set && GET_CODE (SET_DEST (set)) != MEM
8662 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8665 while ((insn = NEXT_INSN (insn)))
8671 code = GET_CODE (insn);
8674 /* If this is a label that existed before reload, then the register
8675 if dead here. However, if this is a label added by reorg, then
8676 the register may still be live here. We can't tell the difference,
8677 so we just ignore labels completely. */
8678 if (code == CODE_LABEL)
8683 if (code == JUMP_INSN)
8686 /* If this is a sequence, we must handle them all at once.
8687 We could have for instance a call that sets the target register,
8688 and an insn in a delay slot that uses the register. In this case,
8689 we must return 0. */
8690 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
8695 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8697 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
8698 rtx set = single_set (this_insn);
8700 if (GET_CODE (this_insn) == CALL_INSN)
8702 else if (GET_CODE (this_insn) == JUMP_INSN)
8704 if (INSN_ANNULLED_BRANCH_P (this_insn))
8709 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8711 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8713 if (GET_CODE (SET_DEST (set)) != MEM)
8719 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
8724 else if (code == JUMP_INSN)
8728 set = single_set (insn);
8729 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8731 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8732 return GET_CODE (SET_DEST (set)) != MEM;
8733 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
8736 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
8744 static GTY(()) rtx fpscr_rtx;
8746 get_fpscr_rtx (void)
8750 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
8751 REG_USERVAR_P (fpscr_rtx) = 1;
8752 mark_user_reg (fpscr_rtx);
8754 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
8755 mark_user_reg (fpscr_rtx);
8759 static GTY(()) tree fpscr_values;
8762 emit_fpu_switch (rtx scratch, int index)
8766 if (fpscr_values == NULL)
8770 t = build_index_type (integer_one_node);
8771 t = build_array_type (integer_type_node, t);
8772 t = build_decl (VAR_DECL, get_identifier ("__fpscr_values"), t);
8773 DECL_ARTIFICIAL (t) = 1;
8774 DECL_IGNORED_P (t) = 1;
8775 DECL_EXTERNAL (t) = 1;
8776 TREE_STATIC (t) = 1;
8777 TREE_PUBLIC (t) = 1;
8783 src = DECL_RTL (fpscr_values);
8784 if (!can_create_pseudo_p ())
8786 emit_move_insn (scratch, XEXP (src, 0));
8788 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
8789 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
8792 src = adjust_address (src, PSImode, index * 4);
8794 dst = get_fpscr_rtx ();
8795 emit_move_insn (dst, src);
8799 emit_sf_insn (rtx pat)
8805 emit_df_insn (rtx pat)
8811 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8813 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8817 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8819 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
8824 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8826 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8830 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8832 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
8836 static rtx get_free_reg (HARD_REG_SET);
8838 /* This function returns a register to use to load the address to load
8839 the fpscr from. Currently it always returns r1 or r7, but when we are
8840 able to use pseudo registers after combine, or have a better mechanism
8841 for choosing a register, it should be done here. */
8842 /* REGS_LIVE is the liveness information for the point for which we
8843 need this allocation. In some bare-bones exit blocks, r1 is live at the
8844 start. We can even have all of r0..r3 being live:
8845 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
8846 INSN before which new insns are placed with will clobber the register
8847 we return. If a basic block consists only of setting the return value
8848 register to a pseudo and using that register, the return value is not
8849 live before or after this block, yet we we'll insert our insns right in
8853 get_free_reg (HARD_REG_SET regs_live)
8855 if (! TEST_HARD_REG_BIT (regs_live, 1))
8856 return gen_rtx_REG (Pmode, 1);
8858 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
8859 there shouldn't be anything but a jump before the function end. */
8860 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
8861 return gen_rtx_REG (Pmode, 7);
8864 /* This function will set the fpscr from memory.
8865 MODE is the mode we are setting it to. */
8867 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
8869 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
8870 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
8873 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
8874 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
8877 /* Is the given character a logical line separator for the assembler? */
8878 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
8879 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
8883 sh_insn_length_adjustment (rtx insn)
8885 /* Instructions with unfilled delay slots take up an extra two bytes for
8886 the nop in the delay slot. */
8887 if (((GET_CODE (insn) == INSN
8888 && GET_CODE (PATTERN (insn)) != USE
8889 && GET_CODE (PATTERN (insn)) != CLOBBER)
8890 || GET_CODE (insn) == CALL_INSN
8891 || (GET_CODE (insn) == JUMP_INSN
8892 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8893 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
8894 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
8895 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
8898 /* SH2e has a bug that prevents the use of annulled branches, so if
8899 the delay slot is not filled, we'll have to put a NOP in it. */
8900 if (sh_cpu_attr == CPU_SH2E
8901 && GET_CODE (insn) == JUMP_INSN
8902 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8903 && GET_CODE (PATTERN (insn)) != ADDR_VEC
8904 && get_attr_type (insn) == TYPE_CBRANCH
8905 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
8908 /* sh-dsp parallel processing insn take four bytes instead of two. */
8910 if (GET_CODE (insn) == INSN)
8913 rtx body = PATTERN (insn);
8916 int maybe_label = 1;
8918 if (GET_CODE (body) == ASM_INPUT)
8919 templ = XSTR (body, 0);
8920 else if (asm_noperands (body) >= 0)
8922 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
8931 while (c == ' ' || c == '\t');
8932 /* all sh-dsp parallel-processing insns start with p.
8933 The only non-ppi sh insn starting with p is pref.
8934 The only ppi starting with pr is prnd. */
8935 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
8937 /* The repeat pseudo-insn expands two three insns, a total of
8938 six bytes in size. */
8939 else if ((c == 'r' || c == 'R')
8940 && ! strncasecmp ("epeat", templ, 5))
8942 while (c && c != '\n'
8943 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
8945 /* If this is a label, it is obviously not a ppi insn. */
8946 if (c == ':' && maybe_label)
8951 else if (c == '\'' || c == '"')
8956 maybe_label = c != ':';
8964 /* Return TRUE for a valid displacement for the REG+disp addressing
8967 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
8968 into the FRx registers. We implement this by setting the maximum offset
8969 to zero when the value is SFmode. This also restricts loading of SFmode
8970 values into the integer registers, but that can't be helped. */
8972 /* The SH allows a displacement in a QI or HI amode, but only when the
8973 other operand is R0. GCC doesn't handle this very well, so we forgot
8976 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
8977 DI can be any number 0..60. */
8980 sh_legitimate_index_p (enum machine_mode mode, rtx op)
8982 if (GET_CODE (op) == CONST_INT)
8988 /* Check if this the address of an unaligned load / store. */
8989 if (mode == VOIDmode)
8990 return CONST_OK_FOR_I06 (INTVAL (op));
8992 size = GET_MODE_SIZE (mode);
8993 return (!(INTVAL (op) & (size - 1))
8994 && INTVAL (op) >= -512 * size
8995 && INTVAL (op) < 512 * size);
9000 if (GET_MODE_SIZE (mode) == 1
9001 && (unsigned) INTVAL (op) < 4096)
9005 if ((GET_MODE_SIZE (mode) == 4
9006 && (unsigned) INTVAL (op) < 64
9007 && !(INTVAL (op) & 3)
9008 && !(TARGET_SH2E && mode == SFmode))
9009 || (GET_MODE_SIZE (mode) == 4
9010 && (unsigned) INTVAL (op) < 16383
9011 && !(INTVAL (op) & 3) && TARGET_SH2A))
9014 if ((GET_MODE_SIZE (mode) == 8
9015 && (unsigned) INTVAL (op) < 60
9016 && !(INTVAL (op) & 3)
9017 && !((TARGET_SH4 || TARGET_SH2A) && mode == DFmode))
9018 || ((GET_MODE_SIZE (mode)==8)
9019 && (unsigned) INTVAL (op) < 8192
9020 && !(INTVAL (op) & (TARGET_SH2A_DOUBLE ? 7 : 3))
9021 && (TARGET_SH2A && mode == DFmode)))
9028 /* Recognize an RTL expression that is a valid memory address for
9030 The MODE argument is the machine mode for the MEM expression
9031 that wants to use this address.
9039 sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9041 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9043 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9045 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9047 else if (GET_CODE (x) == PLUS
9048 && (mode != PSImode || reload_completed))
9050 rtx xop0 = XEXP (x, 0);
9051 rtx xop1 = XEXP (x, 1);
9053 if (GET_MODE_SIZE (mode) <= 8
9054 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9055 && sh_legitimate_index_p (mode, xop1))
9058 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode
9059 || ((xop0 == stack_pointer_rtx
9060 || xop0 == hard_frame_pointer_rtx)
9061 && REG_P (xop1) && REGNO (xop1) == R0_REG)
9062 || ((xop1 == stack_pointer_rtx
9063 || xop1 == hard_frame_pointer_rtx)
9064 && REG_P (xop0) && REGNO (xop0) == R0_REG))
9065 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4)
9066 || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8)
9067 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
9068 && TARGET_FMOVD && mode == DFmode)))
9070 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9071 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9073 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9074 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9082 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9083 isn't protected by a PIC unspec. */
9085 nonpic_symbol_mentioned_p (rtx x)
9087 register const char *fmt;
9090 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9091 || GET_CODE (x) == PC)
9094 /* We don't want to look into the possible MEM location of a
9095 CONST_DOUBLE, since we're not going to use it, in general. */
9096 if (GET_CODE (x) == CONST_DOUBLE)
9099 if (GET_CODE (x) == UNSPEC
9100 && (XINT (x, 1) == UNSPEC_PIC
9101 || XINT (x, 1) == UNSPEC_GOT
9102 || XINT (x, 1) == UNSPEC_GOTOFF
9103 || XINT (x, 1) == UNSPEC_GOTPLT
9104 || XINT (x, 1) == UNSPEC_GOTTPOFF
9105 || XINT (x, 1) == UNSPEC_DTPOFF
9106 || XINT (x, 1) == UNSPEC_PLT
9107 || XINT (x, 1) == UNSPEC_SYMOFF
9108 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
9111 fmt = GET_RTX_FORMAT (GET_CODE (x));
9112 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9118 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9119 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9122 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9129 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9130 @GOTOFF in `reg'. */
9132 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
9135 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
9138 if (GET_CODE (orig) == LABEL_REF
9139 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
9142 reg = gen_reg_rtx (Pmode);
9144 emit_insn (gen_symGOTOFF2reg (reg, orig));
9147 else if (GET_CODE (orig) == SYMBOL_REF)
9150 reg = gen_reg_rtx (Pmode);
9152 emit_insn (gen_symGOT2reg (reg, orig));
9158 /* Try machine-dependent ways of modifying an illegitimate address
9159 to be legitimate. If we find one, return the new, valid address.
9160 Otherwise, return X.
9162 For the SH, if X is almost suitable for indexing, but the offset is
9163 out of range, convert it into a normal form so that CSE has a chance
9164 of reducing the number of address registers used. */
9167 sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
9170 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9172 if (GET_CODE (x) == PLUS
9173 && (GET_MODE_SIZE (mode) == 4
9174 || GET_MODE_SIZE (mode) == 8)
9175 && GET_CODE (XEXP (x, 1)) == CONST_INT
9176 && BASE_REGISTER_RTX_P (XEXP (x, 0))
9178 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
9179 && ! (TARGET_SH2E && mode == SFmode))
9181 rtx index_rtx = XEXP (x, 1);
9182 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9185 /* On rare occasions, we might get an unaligned pointer
9186 that is indexed in a way to give an aligned address.
9187 Therefore, keep the lower two bits in offset_base. */
9188 /* Instead of offset_base 128..131 use 124..127, so that
9189 simple add suffices. */
9191 offset_base = ((offset + 4) & ~60) - 4;
9193 offset_base = offset & ~60;
9195 /* Sometimes the normal form does not suit DImode. We
9196 could avoid that by using smaller ranges, but that
9197 would give less optimized code when SImode is
9199 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9201 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9202 GEN_INT (offset_base), NULL_RTX, 0,
9205 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9212 /* Mark the use of a constant in the literal table. If the constant
9213 has multiple labels, make it unique. */
9215 mark_constant_pool_use (rtx x)
9217 rtx insn, lab, pattern;
9222 switch (GET_CODE (x))
9232 /* Get the first label in the list of labels for the same constant
9233 and delete another labels in the list. */
9235 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
9237 if (GET_CODE (insn) != CODE_LABEL
9238 || LABEL_REFS (insn) != NEXT_INSN (insn))
9243 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
9244 INSN_DELETED_P (insn) = 1;
9246 /* Mark constants in a window. */
9247 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
9249 if (GET_CODE (insn) != INSN)
9252 pattern = PATTERN (insn);
9253 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
9256 switch (XINT (pattern, 1))
9258 case UNSPECV_CONST2:
9259 case UNSPECV_CONST4:
9260 case UNSPECV_CONST8:
9261 XVECEXP (pattern, 0, 1) = const1_rtx;
9263 case UNSPECV_WINDOW_END:
9264 if (XVECEXP (pattern, 0, 0) == x)
9267 case UNSPECV_CONST_END:
9277 /* Return true if it's possible to redirect BRANCH1 to the destination
9278 of an unconditional jump BRANCH2. We only want to do this if the
9279 resulting branch will have a short displacement. */
9281 sh_can_redirect_branch (rtx branch1, rtx branch2)
9283 if (flag_expensive_optimizations && simplejump_p (branch2))
9285 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
9289 for (distance = 0, insn = NEXT_INSN (branch1);
9290 insn && distance < 256;
9291 insn = PREV_INSN (insn))
9296 distance += get_attr_length (insn);
9298 for (distance = 0, insn = NEXT_INSN (branch1);
9299 insn && distance < 256;
9300 insn = NEXT_INSN (insn))
9305 distance += get_attr_length (insn);
9311 /* Return nonzero if register old_reg can be renamed to register new_reg. */
9313 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
9314 unsigned int new_reg)
9316 /* Interrupt functions can only use registers that have already been
9317 saved by the prologue, even if they would normally be
9320 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
9326 /* Function to update the integer COST
9327 based on the relationship between INSN that is dependent on
9328 DEP_INSN through the dependence LINK. The default is to make no
9329 adjustment to COST. This can be used for example to specify to
9330 the scheduler that an output- or anti-dependence does not incur
9331 the same cost as a data-dependence. The return value should be
9332 the new value for COST. */
9334 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
9340 /* On SHmedia, if the dependence is an anti-dependence or
9341 output-dependence, there is no cost. */
9342 if (REG_NOTE_KIND (link) != 0)
9344 /* However, dependencies between target register loads and
9345 uses of the register in a subsequent block that are separated
9346 by a conditional branch are not modelled - we have to do with
9347 the anti-dependency between the target register load and the
9348 conditional branch that ends the current block. */
9349 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
9350 && GET_CODE (PATTERN (dep_insn)) == SET
9351 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
9352 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
9353 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
9355 int orig_cost = cost;
9356 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
9357 rtx target = ((! note
9358 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
9359 ? insn : JUMP_LABEL (insn));
9360 /* On the likely path, the branch costs 1, on the unlikely path,
9364 target = next_active_insn (target);
9365 while (target && ! flow_dependent_p (target, dep_insn)
9367 /* If two branches are executed in immediate succession, with the
9368 first branch properly predicted, this causes a stall at the
9369 second branch, hence we won't need the target for the
9370 second branch for two cycles after the launch of the first
9372 if (cost > orig_cost - 2)
9373 cost = orig_cost - 2;
9379 else if (get_attr_is_mac_media (insn)
9380 && get_attr_is_mac_media (dep_insn))
9383 else if (! reload_completed
9384 && GET_CODE (PATTERN (insn)) == SET
9385 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
9386 && GET_CODE (PATTERN (dep_insn)) == SET
9387 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
9390 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
9391 that is needed at the target. */
9392 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
9393 && ! flow_dependent_p (insn, dep_insn))
9396 else if (REG_NOTE_KIND (link) == 0)
9398 enum attr_type type;
9401 if (recog_memoized (insn) < 0
9402 || recog_memoized (dep_insn) < 0)
9405 dep_set = single_set (dep_insn);
9407 /* The latency that we specify in the scheduling description refers
9408 to the actual output, not to an auto-increment register; for that,
9409 the latency is one. */
9410 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9412 rtx set = single_set (insn);
9415 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9416 && (!MEM_P (SET_DEST (set))
9417 || !reg_mentioned_p (SET_DEST (dep_set),
9418 XEXP (SET_DEST (set), 0))))
9421 /* The only input for a call that is timing-critical is the
9422 function's address. */
9423 if (GET_CODE (insn) == CALL_INSN)
9425 rtx call = PATTERN (insn);
9427 if (GET_CODE (call) == PARALLEL)
9428 call = XVECEXP (call, 0 ,0);
9429 if (GET_CODE (call) == SET)
9430 call = SET_SRC (call);
9431 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
9432 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9433 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9434 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9435 cost -= TARGET_SH4_300 ? 3 : 6;
9437 /* Likewise, the most timing critical input for an sfuncs call
9438 is the function address. However, sfuncs typically start
9439 using their arguments pretty quickly.
9440 Assume a four cycle delay for SH4 before they are needed.
9441 Cached ST40-300 calls are quicker, so assume only a one
9443 ??? Maybe we should encode the delays till input registers
9444 are needed by sfuncs into the sfunc call insn. */
9445 /* All sfunc calls are parallels with at least four components.
9446 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9447 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9448 && XVECLEN (PATTERN (insn), 0) >= 4
9449 && (reg = sfunc_uses_reg (insn)))
9451 if (! reg_set_p (reg, dep_insn))
9452 cost -= TARGET_SH4_300 ? 1 : 4;
9454 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9456 enum attr_type dep_type = get_attr_type (dep_insn);
9458 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9460 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9461 && (type = get_attr_type (insn)) != TYPE_CALL
9462 && type != TYPE_SFUNC)
9464 /* When the preceding instruction loads the shift amount of
9465 the following SHAD/SHLD, the latency of the load is increased
9467 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9468 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
9469 && reg_overlap_mentioned_p (SET_DEST (dep_set),
9470 XEXP (SET_SRC (single_set (insn)),
9473 /* When an LS group instruction with a latency of less than
9474 3 cycles is followed by a double-precision floating-point
9475 instruction, FIPR, or FTRV, the latency of the first
9476 instruction is increased to 3 cycles. */
9478 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9479 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9481 /* The lsw register of a double-precision computation is ready one
9483 else if (reload_completed
9484 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9485 && (use_pat = single_set (insn))
9486 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9490 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9491 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9494 else if (TARGET_SH4_300)
9496 /* Stores need their input register two cycles later. */
9497 if (dep_set && cost >= 1
9498 && ((type = get_attr_type (insn)) == TYPE_STORE
9499 || type == TYPE_PSTORE
9500 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9502 rtx set = single_set (insn);
9504 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9505 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9508 /* But don't reduce the cost below 1 if the address depends
9509 on a side effect of dep_insn. */
9511 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9517 /* An anti-dependence penalty of two applies if the first insn is a double
9518 precision fadd / fsub / fmul. */
9519 else if (!TARGET_SH4_300
9520 && REG_NOTE_KIND (link) == REG_DEP_ANTI
9521 && recog_memoized (dep_insn) >= 0
9522 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9523 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9524 /* A lot of alleged anti-flow dependences are fake,
9525 so check this one is real. */
9526 && flow_dependent_p (dep_insn, insn))
9532 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9533 if DEP_INSN is anti-flow dependent on INSN. */
9535 flow_dependent_p (rtx insn, rtx dep_insn)
9537 rtx tmp = PATTERN (insn);
9539 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9540 return tmp == NULL_RTX;
9543 /* A helper function for flow_dependent_p called through note_stores. */
9545 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9547 rtx * pinsn = (rtx *) data;
9549 if (*pinsn && reg_referenced_p (x, *pinsn))
9553 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9554 'special function' patterns (type sfunc) that clobber pr, but that
9555 do not look like function calls to leaf_function_p. Hence we must
9556 do this extra check. */
9560 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9563 /* Return where to allocate pseudo for a given hard register initial
9566 sh_allocate_initial_value (rtx hard_reg)
9570 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
9572 if (current_function_is_leaf
9573 && ! sh_pr_n_sets ()
9574 && ! (TARGET_SHCOMPACT
9575 && ((crtl->args.info.call_cookie
9576 & ~ CALL_COOKIE_RET_TRAMP (1))
9577 || crtl->saves_all_registers)))
9580 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
9588 /* This function returns "2" to indicate dual issue for the SH4
9589 processor. To be used by the DFA pipeline description. */
9591 sh_issue_rate (void)
9593 if (TARGET_SUPERSCALAR)
9599 /* Functions for ready queue reordering for sched1. */
9601 /* Get weight for mode for a set x. */
9603 find_set_regmode_weight (rtx x, enum machine_mode mode)
9605 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9607 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9609 if (GET_CODE (SET_DEST (x)) == REG)
9611 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9621 /* Get regmode weight for insn. */
9623 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
9625 short reg_weight = 0;
9628 /* Increment weight for each register born here. */
9630 reg_weight += find_set_regmode_weight (x, mode);
9631 if (GET_CODE (x) == PARALLEL)
9634 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9636 x = XVECEXP (PATTERN (insn), 0, j);
9637 reg_weight += find_set_regmode_weight (x, mode);
9640 /* Decrement weight for each register that dies here. */
9641 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9643 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9645 rtx note = XEXP (x, 0);
9646 if (GET_CODE (note) == REG && GET_MODE (note) == mode)
9653 /* Calculate regmode weights for all insns of a basic block. */
9655 find_regmode_weight (basic_block b, enum machine_mode mode)
9657 rtx insn, next_tail, head, tail;
9659 get_ebb_head_tail (b, b, &head, &tail);
9660 next_tail = NEXT_INSN (tail);
9662 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9664 /* Handle register life information. */
9669 INSN_REGMODE_WEIGHT (insn, mode) =
9670 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
9671 else if (mode == SImode)
9672 INSN_REGMODE_WEIGHT (insn, mode) =
9673 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
9677 /* Comparison function for ready queue sorting. */
9679 rank_for_reorder (const void *x, const void *y)
9681 rtx tmp = *(const rtx *) y;
9682 rtx tmp2 = *(const rtx *) x;
9684 /* The insn in a schedule group should be issued the first. */
9685 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
9686 return SCHED_GROUP_P (tmp2) ? 1 : -1;
9688 /* If insns are equally good, sort by INSN_LUID (original insn order), This
9689 minimizes instruction movement, thus minimizing sched's effect on
9690 register pressure. */
9691 return INSN_LUID (tmp) - INSN_LUID (tmp2);
9694 /* Resort the array A in which only element at index N may be out of order. */
9696 swap_reorder (rtx *a, int n)
9698 rtx insn = a[n - 1];
9701 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
9709 #define SCHED_REORDER(READY, N_READY) \
9712 if ((N_READY) == 2) \
9713 swap_reorder (READY, N_READY); \
9714 else if ((N_READY) > 2) \
9715 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
9719 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
9722 ready_reorder (rtx *ready, int nready)
9724 SCHED_REORDER (ready, nready);
9727 /* Count life regions of r0 for a block. */
9729 find_r0_life_regions (basic_block b)
9738 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
9751 r0_reg = gen_rtx_REG (SImode, R0_REG);
9756 if (find_regno_note (insn, REG_DEAD, R0_REG))
9762 && (pset = single_set (insn))
9763 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
9764 && !find_regno_note (insn, REG_UNUSED, R0_REG))
9772 insn = NEXT_INSN (insn);
9777 /* Calculate regmode weights for all insns of all basic block. */
9779 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
9780 int verbose ATTRIBUTE_UNUSED,
9785 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
9786 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
9787 r0_life_regions = 0;
9789 FOR_EACH_BB_REVERSE (b)
9791 find_regmode_weight (b, SImode);
9792 find_regmode_weight (b, SFmode);
9793 if (!reload_completed)
9794 r0_life_regions += find_r0_life_regions (b);
9797 CURR_REGMODE_PRESSURE (SImode) = 0;
9798 CURR_REGMODE_PRESSURE (SFmode) = 0;
9804 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
9805 int verbose ATTRIBUTE_UNUSED)
9807 if (regmode_weight[0])
9809 free (regmode_weight[0]);
9810 regmode_weight[0] = NULL;
9812 if (regmode_weight[1])
9814 free (regmode_weight[1]);
9815 regmode_weight[1] = NULL;
9819 /* The scalar modes supported differs from the default version in TImode
9820 for 32-bit SHMEDIA. */
9822 sh_scalar_mode_supported_p (enum machine_mode mode)
9824 if (TARGET_SHMEDIA32 && mode == TImode)
9827 return default_scalar_mode_supported_p (mode);
9830 /* Cache the can_issue_more so that we can return it from reorder2. Also,
9831 keep count of register pressures on SImode and SFmode. */
9833 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
9834 int sched_verbose ATTRIBUTE_UNUSED,
9838 if (GET_CODE (PATTERN (insn)) != USE
9839 && GET_CODE (PATTERN (insn)) != CLOBBER)
9840 cached_can_issue_more = can_issue_more - 1;
9842 cached_can_issue_more = can_issue_more;
9844 if (reload_completed)
9845 return cached_can_issue_more;
9847 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
9848 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
9850 return cached_can_issue_more;
9854 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
9855 int verbose ATTRIBUTE_UNUSED,
9856 int veclen ATTRIBUTE_UNUSED)
9858 CURR_REGMODE_PRESSURE (SImode) = 0;
9859 CURR_REGMODE_PRESSURE (SFmode) = 0;
9862 /* Some magic numbers. */
9863 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9864 functions that already have high pressure on r0. */
9865 #define R0_MAX_LIFE_REGIONS 2
9866 /* Register Pressure thresholds for SImode and SFmode registers. */
9867 #define SIMODE_MAX_WEIGHT 5
9868 #define SFMODE_MAX_WEIGHT 10
9870 /* Return true if the pressure is high for MODE. */
9872 high_pressure (enum machine_mode mode)
9874 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9875 functions that already have high pressure on r0. */
9876 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
9880 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
9882 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
9885 /* Reorder ready queue if register pressure is high. */
9887 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
9888 int sched_verbose ATTRIBUTE_UNUSED,
9891 int clock_var ATTRIBUTE_UNUSED)
9893 if (reload_completed)
9894 return sh_issue_rate ();
9896 if (high_pressure (SFmode) || high_pressure (SImode))
9898 ready_reorder (ready, *n_readyp);
9901 return sh_issue_rate ();
9904 /* Skip cycles if the current register pressure is high. */
9906 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
9907 int sched_verbose ATTRIBUTE_UNUSED,
9908 rtx *ready ATTRIBUTE_UNUSED,
9909 int *n_readyp ATTRIBUTE_UNUSED,
9910 int clock_var ATTRIBUTE_UNUSED)
9912 if (reload_completed)
9913 return cached_can_issue_more;
9915 if (high_pressure(SFmode) || high_pressure (SImode))
9918 return cached_can_issue_more;
9921 /* Skip cycles without sorting the ready queue. This will move insn from
9922 Q->R. If this is the last cycle we are skipping; allow sorting of ready
9923 queue by sh_reorder. */
9925 /* Generally, skipping these many cycles are sufficient for all insns to move
9930 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
9931 int sched_verbose ATTRIBUTE_UNUSED,
9932 rtx insn ATTRIBUTE_UNUSED,
9937 if (reload_completed)
9942 if ((clock_var - last_clock_var) < MAX_SKIPS)
9947 /* If this is the last cycle we are skipping, allow reordering of R. */
9948 if ((clock_var - last_clock_var) == MAX_SKIPS)
9960 /* SHmedia requires registers for branches, so we can't generate new
9961 branches past reload. */
9963 sh_cannot_modify_jumps_p (void)
9965 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
9968 static enum reg_class
9969 sh_target_reg_class (void)
9971 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
9975 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
9982 if (! shmedia_space_reserved_for_target_registers)
9984 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
9986 if (calc_live_regs (&dummy) >= 6 * 8)
9992 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
9994 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
9998 On the SH1..SH4, the trampoline looks like
9999 2 0002 D202 mov.l l2,r2
10000 1 0000 D301 mov.l l1,r3
10001 3 0004 422B jmp @r2
10003 5 0008 00000000 l1: .long area
10004 6 000c 00000000 l2: .long function
10006 SH5 (compact) uses r1 instead of r3 for the static chain. */
10009 /* Emit RTL insns to initialize the variable parts of a trampoline.
10010 FNADDR is an RTX for the address of the function's pure code.
10011 CXT is an RTX for the static chain value for the function. */
10014 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
10016 rtx tramp_mem = gen_frame_mem (BLKmode, tramp);
10018 if (TARGET_SHMEDIA64)
10023 rtx movi1 = GEN_INT (0xcc000010);
10024 rtx shori1 = GEN_INT (0xc8000010);
10027 /* The following trampoline works within a +- 128 KB range for cxt:
10028 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10029 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10030 gettr tr1,r1; blink tr0,r63 */
10031 /* Address rounding makes it hard to compute the exact bounds of the
10032 offset for this trampoline, but we have a rather generous offset
10033 range, so frame_offset should do fine as an upper bound. */
10034 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
10036 /* ??? could optimize this trampoline initialization
10037 by writing DImode words with two insns each. */
10038 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
10039 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
10040 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
10041 insn = gen_rtx_AND (DImode, insn, mask);
10042 /* Or in ptb/u .,tr1 pattern */
10043 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
10044 insn = force_operand (insn, NULL_RTX);
10045 insn = gen_lowpart (SImode, insn);
10046 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
10047 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
10048 insn = gen_rtx_AND (DImode, insn, mask);
10049 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
10050 insn = gen_lowpart (SImode, insn);
10051 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
10052 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
10053 insn = gen_rtx_AND (DImode, insn, mask);
10054 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10055 insn = gen_lowpart (SImode, insn);
10056 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
10057 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
10058 insn = gen_rtx_AND (DImode, insn, mask);
10059 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10060 insn = gen_lowpart (SImode, insn);
10061 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
10062 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
10063 insn = gen_rtx_AND (DImode, insn, mask);
10064 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10065 insn = gen_lowpart (SImode, insn);
10066 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
10067 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
10068 GEN_INT (0x6bf10600));
10069 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
10070 GEN_INT (0x4415fc10));
10071 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
10072 GEN_INT (0x4401fff0));
10073 emit_insn (gen_ic_invalidate_line (tramp));
10076 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
10077 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
10079 tramp_templ = gen_datalabel_ref (tramp_templ);
10081 src = gen_const_mem (BLKmode, tramp_templ);
10082 set_mem_align (dst, 256);
10083 set_mem_align (src, 64);
10084 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
10086 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
10087 emit_move_insn (adjust_address (tramp_mem, Pmode,
10088 fixed_len + GET_MODE_SIZE (Pmode)),
10090 emit_insn (gen_ic_invalidate_line (tramp));
10093 else if (TARGET_SHMEDIA)
10095 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10096 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10097 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
10098 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
10099 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
10100 rotated 10 right, and higher 16 bit of every 32 selected. */
10102 = force_reg (V2HImode, (simplify_gen_subreg
10103 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
10104 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
10105 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
10107 tramp = force_reg (Pmode, tramp);
10108 fnaddr = force_reg (SImode, fnaddr);
10109 cxt = force_reg (SImode, cxt);
10110 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
10111 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
10113 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
10114 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10115 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
10116 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
10117 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
10118 gen_rtx_SUBREG (V2HImode, cxt, 0),
10120 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
10121 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10122 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
10123 if (TARGET_LITTLE_ENDIAN)
10125 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
10126 emit_insn (gen_mextr4 (quad2, cxtload, blink));
10130 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
10131 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
10133 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
10134 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
10135 emit_insn (gen_ic_invalidate_line (tramp));
10138 else if (TARGET_SHCOMPACT)
10140 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
10143 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
10144 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
10146 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
10147 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
10149 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
10150 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
10151 if (TARGET_HARVARD)
10153 if (!TARGET_INLINE_IC_INVALIDATE
10154 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
10155 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10156 FUNCTION_ORDINARY),
10157 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
10159 emit_insn (gen_ic_invalidate_line (tramp));
10163 /* FIXME: This is overly conservative. A SHcompact function that
10164 receives arguments ``by reference'' will have them stored in its
10165 own stack frame, so it must not pass pointers or references to
10166 these arguments to other functions by means of sibling calls. */
10167 /* If PIC, we cannot make sibling calls to global functions
10168 because the PLT requires r12 to be live. */
10170 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10173 && (! TARGET_SHCOMPACT
10174 || crtl->args.info.stack_regs == 0)
10175 && ! sh_cfun_interrupt_handler_p ()
10177 || (decl && ! TREE_PUBLIC (decl))
10178 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
10181 /* Machine specific built-in functions. */
10183 struct builtin_description
10185 const enum insn_code icode;
10186 const char *const name;
10190 /* describe number and signedness of arguments; arg[0] == result
10191 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
10192 /* 9: 64-bit pointer, 10: 32-bit pointer */
10193 static const char signature_args[][4] =
10195 #define SH_BLTIN_V2SI2 0
10197 #define SH_BLTIN_V4HI2 1
10199 #define SH_BLTIN_V2SI3 2
10201 #define SH_BLTIN_V4HI3 3
10203 #define SH_BLTIN_V8QI3 4
10205 #define SH_BLTIN_MAC_HISI 5
10207 #define SH_BLTIN_SH_HI 6
10209 #define SH_BLTIN_SH_SI 7
10211 #define SH_BLTIN_V4HI2V2SI 8
10213 #define SH_BLTIN_V4HI2V8QI 9
10215 #define SH_BLTIN_SISF 10
10217 #define SH_BLTIN_LDUA_L 11
10219 #define SH_BLTIN_LDUA_Q 12
10221 #define SH_BLTIN_STUA_L 13
10223 #define SH_BLTIN_STUA_Q 14
10225 #define SH_BLTIN_LDUA_L64 15
10227 #define SH_BLTIN_LDUA_Q64 16
10229 #define SH_BLTIN_STUA_L64 17
10231 #define SH_BLTIN_STUA_Q64 18
10233 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10234 #define SH_BLTIN_2 19
10235 #define SH_BLTIN_SU 19
10237 #define SH_BLTIN_3 20
10238 #define SH_BLTIN_SUS 20
10240 #define SH_BLTIN_PSSV 21
10242 #define SH_BLTIN_XXUU 22
10243 #define SH_BLTIN_UUUU 22
10245 #define SH_BLTIN_PV 23
10248 /* mcmv: operands considered unsigned. */
10249 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
10250 /* mperm: control value considered unsigned int. */
10251 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
10252 /* mshards_q: returns signed short. */
10253 /* nsb: takes long long arg, returns unsigned char. */
10254 static const struct builtin_description bdesc[] =
10256 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
10257 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
10258 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
10259 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
10260 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
10261 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
10262 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
10263 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
10264 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
10265 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
10266 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
10267 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
10268 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
10269 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
10270 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
10271 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
10272 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
10273 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
10274 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 },
10275 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 },
10276 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 },
10277 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 },
10278 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 },
10279 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 },
10280 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 },
10281 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
10282 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
10283 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
10284 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
10285 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
10286 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
10287 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
10288 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
10289 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
10290 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
10291 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
10292 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
10293 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
10294 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
10295 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
10296 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
10297 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
10298 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
10299 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
10300 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
10301 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
10302 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
10303 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
10304 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
10305 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
10306 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
10307 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
10308 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
10309 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
10310 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
10311 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
10312 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
10313 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
10314 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
10315 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
10316 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
10317 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 },
10318 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 },
10319 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 },
10320 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
10321 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
10322 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
10323 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
10324 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
10325 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
10326 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
10327 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
10328 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
10329 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 },
10330 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 },
10331 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 },
10332 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 },
10333 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 },
10334 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 },
10335 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 },
10336 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 },
10337 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
10338 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
10339 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
10343 sh_media_init_builtins (void)
10345 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
10346 const struct builtin_description *d;
10348 memset (shared, 0, sizeof shared);
10349 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
10351 tree type, arg_type = 0;
10352 int signature = d->signature;
10355 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
10356 type = shared[signature];
10359 int has_result = signature_args[signature][0] != 0;
10361 if ((signature_args[signature][1] & 8)
10362 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
10363 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
10365 if (! TARGET_FPU_ANY
10366 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
10368 type = void_list_node;
10371 int arg = signature_args[signature][i];
10372 int opno = i - 1 + has_result;
10375 arg_type = ptr_type_node;
10377 arg_type = (*lang_hooks.types.type_for_mode)
10378 (insn_data[d->icode].operand[opno].mode,
10383 arg_type = void_type_node;
10386 type = tree_cons (NULL_TREE, arg_type, type);
10388 type = build_function_type (arg_type, type);
10389 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10390 shared[signature] = type;
10392 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10397 /* Implements target hook vector_mode_supported_p. */
10399 sh_vector_mode_supported_p (enum machine_mode mode)
10402 && ((mode == V2SFmode)
10403 || (mode == V4SFmode)
10404 || (mode == V16SFmode)))
10407 else if (TARGET_SHMEDIA
10408 && ((mode == V8QImode)
10409 || (mode == V2HImode)
10410 || (mode == V4HImode)
10411 || (mode == V2SImode)))
10417 /* Implements target hook dwarf_calling_convention. Return an enum
10418 of dwarf_calling_convention. */
10420 sh_dwarf_calling_convention (const_tree func)
10422 if (sh_attr_renesas_p (func))
10423 return DW_CC_GNU_renesas_sh;
10425 return DW_CC_normal;
10429 sh_init_builtins (void)
10431 if (TARGET_SHMEDIA)
10432 sh_media_init_builtins ();
10435 /* Expand an expression EXP that calls a built-in function,
10436 with result going to TARGET if that's convenient
10437 (and in mode MODE if that's convenient).
10438 SUBTARGET may be used as the target for computing one of EXP's operands.
10439 IGNORE is nonzero if the value is to be ignored. */
10442 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10443 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
10445 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10446 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10447 const struct builtin_description *d = &bdesc[fcode];
10448 enum insn_code icode = d->icode;
10449 int signature = d->signature;
10450 enum machine_mode tmode = VOIDmode;
10455 if (signature_args[signature][0])
10460 tmode = insn_data[icode].operand[0].mode;
10462 || GET_MODE (target) != tmode
10463 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10464 target = gen_reg_rtx (tmode);
10465 op[nop++] = target;
10470 for (i = 1; i <= 3; i++, nop++)
10473 enum machine_mode opmode, argmode;
10476 if (! signature_args[signature][i])
10478 arg = CALL_EXPR_ARG (exp, i - 1);
10479 if (arg == error_mark_node)
10481 if (signature_args[signature][i] & 8)
10484 optype = ptr_type_node;
10488 opmode = insn_data[icode].operand[nop].mode;
10489 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10491 argmode = TYPE_MODE (TREE_TYPE (arg));
10492 if (argmode != opmode)
10493 arg = build1 (NOP_EXPR, optype, arg);
10494 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
10495 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10496 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10502 pat = (*insn_data[d->icode].genfun) (op[0]);
10505 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10508 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10511 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10514 gcc_unreachable ();
10523 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
10525 rtx sel0 = const0_rtx;
10526 rtx sel1 = const1_rtx;
10527 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
10528 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
10530 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
10531 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
10535 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
10537 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
10539 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
10540 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
10543 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
10544 We can allow any mode in any general register. The special registers
10545 only allow SImode. Don't allow any mode in the PR.
10547 We cannot hold DCmode values in the XD registers because alter_reg
10548 handles subregs of them incorrectly. We could work around this by
10549 spacing the XD registers like the DR registers, but this would require
10550 additional memory in every compilation to hold larger register vectors.
10551 We could hold SFmode / SCmode values in XD registers, but that
10552 would require a tertiary reload when reloading from / to memory,
10553 and a secondary reload to reload from / to general regs; that
10554 seems to be a loosing proposition.
10556 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
10557 it won't be ferried through GP registers first. */
10560 sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
10562 if (SPECIAL_REGISTER_P (regno))
10563 return mode == SImode;
10565 if (regno == FPUL_REG)
10566 return (mode == SImode || mode == SFmode);
10568 if (FP_REGISTER_P (regno) && mode == SFmode)
10571 if (mode == V2SFmode)
10573 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
10574 || GENERAL_REGISTER_P (regno)))
10580 if (mode == V4SFmode)
10582 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
10583 || GENERAL_REGISTER_P (regno))
10589 if (mode == V16SFmode)
10591 if (TARGET_SHMEDIA)
10593 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
10599 return regno == FIRST_XD_REG;
10602 if (FP_REGISTER_P (regno))
10606 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
10607 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
10610 && (mode == DFmode || mode == DImode
10611 || mode == V2SFmode || mode == TImode)))
10612 && ((regno - FIRST_FP_REG) & 1) == 0)
10613 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
10614 && ((regno - FIRST_FP_REG) & 3) == 0))
10620 if (XD_REGISTER_P (regno))
10621 return mode == DFmode;
10623 if (TARGET_REGISTER_P (regno))
10624 return (mode == DImode || mode == SImode || mode == PDImode);
10626 if (regno == PR_REG)
10627 return mode == SImode;
10629 if (regno == FPSCR_REG)
10630 return mode == PSImode;
10632 /* FIXME. This works around PR target/37633 for -O0. */
10633 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
10635 unsigned int n = GET_MODE_SIZE (mode) / 8;
10637 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
10638 && regno <= FIRST_GENERAL_REG + 14)
10645 /* Return the class of registers for which a mode change from FROM to TO
10648 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
10649 enum reg_class rclass)
10651 /* We want to enable the use of SUBREGs as a means to
10652 VEC_SELECT a single element of a vector. */
10653 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
10654 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
10656 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10658 if (TARGET_LITTLE_ENDIAN)
10660 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
10661 return reg_classes_intersect_p (DF_REGS, rclass);
10665 if (GET_MODE_SIZE (from) < 8)
10666 return reg_classes_intersect_p (DF_HI_REGS, rclass);
10673 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10674 that label is used. */
10677 sh_mark_label (rtx address, int nuses)
10679 if (GOTOFF_P (address))
10681 /* Extract the label or symbol. */
10682 address = XEXP (address, 0);
10683 if (GET_CODE (address) == PLUS)
10684 address = XEXP (address, 0);
10685 address = XVECEXP (address, 0, 0);
10687 if (GET_CODE (address) == LABEL_REF
10688 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
10689 LABEL_NUSES (XEXP (address, 0)) += nuses;
10692 /* Compute extra cost of moving data between one register class
10695 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10696 uses this information. Hence, the general register <-> floating point
10697 register information here is not used for SFmode. */
10700 sh_register_move_cost (enum machine_mode mode,
10701 enum reg_class srcclass, enum reg_class dstclass)
10703 if (dstclass == T_REGS || dstclass == PR_REGS)
10706 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
10709 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
10710 && REGCLASS_HAS_FP_REG (srcclass)
10711 && REGCLASS_HAS_FP_REG (dstclass))
10714 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
10715 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
10717 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
10718 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
10721 if ((REGCLASS_HAS_FP_REG (dstclass)
10722 && REGCLASS_HAS_GENERAL_REG (srcclass))
10723 || (REGCLASS_HAS_GENERAL_REG (dstclass)
10724 && REGCLASS_HAS_FP_REG (srcclass)))
10725 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
10726 * ((GET_MODE_SIZE (mode) + 7) / 8U));
10728 if ((dstclass == FPUL_REGS
10729 && REGCLASS_HAS_GENERAL_REG (srcclass))
10730 || (srcclass == FPUL_REGS
10731 && REGCLASS_HAS_GENERAL_REG (dstclass)))
10734 if ((dstclass == FPUL_REGS
10735 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
10736 || (srcclass == FPUL_REGS
10737 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
10740 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10741 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10744 /* ??? ptabs faults on (value & 0x3) == 0x3 */
10746 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
10748 if (sh_gettrcost >= 0)
10749 return sh_gettrcost;
10750 else if (!TARGET_PT_FIXED)
10754 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10755 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10760 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
10761 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
10762 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
10764 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
10767 static rtx emit_load_ptr (rtx, rtx);
10770 emit_load_ptr (rtx reg, rtx addr)
10772 rtx mem = gen_const_mem (ptr_mode, addr);
10774 if (Pmode != ptr_mode)
10775 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
10776 return emit_move_insn (reg, mem);
10780 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
10781 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10784 CUMULATIVE_ARGS cum;
10785 int structure_value_byref = 0;
10786 rtx this_rtx, this_value, sibcall, insns, funexp;
10787 tree funtype = TREE_TYPE (function);
10788 int simple_add = CONST_OK_FOR_ADD (delta);
10790 rtx scratch0, scratch1, scratch2;
10793 reload_completed = 1;
10794 epilogue_completed = 1;
10795 current_function_uses_only_leaf_regs = 1;
10797 emit_note (NOTE_INSN_PROLOGUE_END);
10799 /* Find the "this" pointer. We have such a wide range of ABIs for the
10800 SH that it's best to do this completely machine independently.
10801 "this" is passed as first argument, unless a structure return pointer
10802 comes first, in which case "this" comes second. */
10803 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
10804 #ifndef PCC_STATIC_STRUCT_RETURN
10805 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10806 structure_value_byref = 1;
10807 #endif /* not PCC_STATIC_STRUCT_RETURN */
10808 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
10810 tree ptype = build_pointer_type (TREE_TYPE (funtype));
10812 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
10814 this_rtx = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
10816 /* For SHcompact, we only have r0 for a scratch register: r1 is the
10817 static chain pointer (even if you can't have nested virtual functions
10818 right now, someone might implement them sometime), and the rest of the
10819 registers are used for argument passing, are callee-saved, or reserved. */
10820 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
10821 -ffixed-reg has been used. */
10822 if (! call_used_regs[0] || fixed_regs[0])
10823 error ("r0 needs to be available as a call-clobbered register");
10824 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
10827 if (call_used_regs[1] && ! fixed_regs[1])
10828 scratch1 = gen_rtx_REG (ptr_mode, 1);
10829 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
10830 pointing where to return struct values. */
10831 if (call_used_regs[3] && ! fixed_regs[3])
10832 scratch2 = gen_rtx_REG (Pmode, 3);
10834 else if (TARGET_SHMEDIA)
10836 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
10837 if (i != REGNO (scratch0) &&
10838 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
10840 scratch1 = gen_rtx_REG (ptr_mode, i);
10843 if (scratch1 == scratch0)
10844 error ("Need a second call-clobbered general purpose register");
10845 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
10846 if (call_used_regs[i] && ! fixed_regs[i])
10848 scratch2 = gen_rtx_REG (Pmode, i);
10851 if (scratch2 == scratch0)
10852 error ("Need a call-clobbered target register");
10855 this_value = plus_constant (this_rtx, delta);
10857 && (simple_add || scratch0 != scratch1)
10858 && strict_memory_address_p (ptr_mode, this_value))
10860 emit_load_ptr (scratch0, this_value);
10865 ; /* Do nothing. */
10866 else if (simple_add)
10867 emit_move_insn (this_rtx, this_value);
10870 emit_move_insn (scratch1, GEN_INT (delta));
10871 emit_insn (gen_add2_insn (this_rtx, scratch1));
10879 emit_load_ptr (scratch0, this_rtx);
10881 offset_addr = plus_constant (scratch0, vcall_offset);
10882 if (strict_memory_address_p (ptr_mode, offset_addr))
10883 ; /* Do nothing. */
10884 else if (! TARGET_SH5 && scratch0 != scratch1)
10886 /* scratch0 != scratch1, and we have indexed loads. Get better
10887 schedule by loading the offset into r1 and using an indexed
10888 load - then the load of r1 can issue before the load from
10889 (this_rtx + delta) finishes. */
10890 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10891 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
10893 else if (CONST_OK_FOR_ADD (vcall_offset))
10895 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
10896 offset_addr = scratch0;
10898 else if (scratch0 != scratch1)
10900 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10901 emit_insn (gen_add2_insn (scratch0, scratch1));
10902 offset_addr = scratch0;
10905 gcc_unreachable (); /* FIXME */
10906 emit_load_ptr (scratch0, offset_addr);
10908 if (Pmode != ptr_mode)
10909 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
10910 emit_insn (gen_add2_insn (this_rtx, scratch0));
10913 /* Generate a tail call to the target function. */
10914 if (! TREE_USED (function))
10916 assemble_external (function);
10917 TREE_USED (function) = 1;
10919 funexp = XEXP (DECL_RTL (function), 0);
10920 /* If the function is overridden, so is the thunk, hence we don't
10921 need GOT addressing even if this is a public symbol. */
10923 if (TARGET_SH1 && ! flag_weak)
10924 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
10927 if (TARGET_SH2 && flag_pic)
10929 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
10930 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
10934 if (TARGET_SHMEDIA && flag_pic)
10936 funexp = gen_sym2PIC (funexp);
10937 PUT_MODE (funexp, Pmode);
10939 emit_move_insn (scratch2, funexp);
10940 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
10941 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
10943 sibcall = emit_call_insn (sibcall);
10944 SIBLING_CALL_P (sibcall) = 1;
10945 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
10948 /* Run just enough of rest_of_compilation to do scheduling and get
10949 the insns emitted. Note that use_thunk calls
10950 assemble_start_function and assemble_end_function. */
10952 insn_locators_alloc ();
10953 insns = get_insns ();
10959 split_all_insns_noflow ();
10964 if (optimize > 0 && flag_delayed_branch)
10965 dbr_schedule (insns);
10967 shorten_branches (insns);
10968 final_start_function (insns, file, 1);
10969 final (insns, file, 1);
10970 final_end_function ();
10971 free_after_compilation (cfun);
10973 reload_completed = 0;
10974 epilogue_completed = 0;
10978 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
10982 /* If this is not an ordinary function, the name usually comes from a
10983 string literal or an sprintf buffer. Make sure we use the same
10984 string consistently, so that cse will be able to unify address loads. */
10985 if (kind != FUNCTION_ORDINARY)
10986 name = IDENTIFIER_POINTER (get_identifier (name));
10987 sym = gen_rtx_SYMBOL_REF (Pmode, name);
10988 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
10992 case FUNCTION_ORDINARY:
10996 rtx reg = target ? target : gen_reg_rtx (Pmode);
10998 emit_insn (gen_symGOT2reg (reg, sym));
11004 /* ??? To allow cse to work, we use GOTOFF relocations.
11005 we could add combiner patterns to transform this into
11006 straight pc-relative calls with sym2PIC / bsrf when
11007 label load and function call are still 1:1 and in the
11008 same basic block during combine. */
11009 rtx reg = target ? target : gen_reg_rtx (Pmode);
11011 emit_insn (gen_symGOTOFF2reg (reg, sym));
11016 if (target && sym != target)
11018 emit_move_insn (target, sym);
11024 /* Find the number of a general purpose register in S. */
11026 scavenge_reg (HARD_REG_SET *s)
11029 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11030 if (TEST_HARD_REG_BIT (*s, r))
11036 sh_get_pr_initial_val (void)
11040 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11041 PR register on SHcompact, because it might be clobbered by the prologue.
11042 We check first if that is known to be the case. */
11043 if (TARGET_SHCOMPACT
11044 && ((crtl->args.info.call_cookie
11045 & ~ CALL_COOKIE_RET_TRAMP (1))
11046 || crtl->saves_all_registers))
11047 return gen_frame_mem (SImode, return_address_pointer_rtx);
11049 /* If we haven't finished rtl generation, there might be a nonlocal label
11050 that we haven't seen yet.
11051 ??? get_hard_reg_initial_val fails if it is called after register
11052 allocation has started, unless it has been called before for the
11053 same register. And even then, we end in trouble if we didn't use
11054 the register in the same basic block before. So call
11055 get_hard_reg_initial_val now and wrap it in an unspec if we might
11056 need to replace it. */
11057 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11058 combine can put the pseudo returned by get_hard_reg_initial_val into
11059 instructions that need a general purpose registers, which will fail to
11060 be recognized when the pseudo becomes allocated to PR. */
11062 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
11064 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11069 sh_expand_t_scc (rtx operands[])
11071 enum rtx_code code = GET_CODE (operands[1]);
11072 rtx target = operands[0];
11073 rtx op0 = operands[2];
11074 rtx op1 = operands[3];
11075 rtx result = target;
11078 if (GET_CODE (op0) != REG || REGNO (op0) != T_REG
11079 || GET_CODE (op1) != CONST_INT)
11081 if (GET_CODE (result) != REG)
11082 result = gen_reg_rtx (SImode);
11083 val = INTVAL (op1);
11084 if ((code == EQ && val == 1) || (code == NE && val == 0))
11085 emit_insn (gen_movt (result));
11086 else if (TARGET_SH2A && ((code == EQ && val == 0)
11087 || (code == NE && val == 1)))
11088 emit_insn (gen_movrt (result));
11089 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11091 emit_clobber (result);
11092 emit_insn (gen_subc (result, result, result));
11093 emit_insn (gen_addsi3 (result, result, const1_rtx));
11095 else if (code == EQ || code == NE)
11096 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11099 if (result != target)
11100 emit_move_insn (target, result);
11104 /* INSN is an sfunc; return the rtx that describes the address used. */
11106 extract_sfunc_addr (rtx insn)
11108 rtx pattern, part = NULL_RTX;
11111 pattern = PATTERN (insn);
11112 len = XVECLEN (pattern, 0);
11113 for (i = 0; i < len; i++)
11115 part = XVECEXP (pattern, 0, i);
11116 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
11117 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
11118 return XEXP (part, 0);
11120 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
11121 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
11124 /* Verify that the register in use_sfunc_addr still agrees with the address
11125 used in the sfunc. This prevents fill_slots_from_thread from changing
11127 INSN is the use_sfunc_addr instruction, and REG is the register it
11130 check_use_sfunc_addr (rtx insn, rtx reg)
11132 /* Search for the sfunc. It should really come right after INSN. */
11133 while ((insn = NEXT_INSN (insn)))
11135 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN)
11137 if (! INSN_P (insn))
11140 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11141 insn = XVECEXP (PATTERN (insn), 0, 0);
11142 if (GET_CODE (PATTERN (insn)) != PARALLEL
11143 || get_attr_type (insn) != TYPE_SFUNC)
11145 return rtx_equal_p (extract_sfunc_addr (insn), reg);
11147 gcc_unreachable ();
11150 /* This function returns a constant rtx that represents pi / 2**15 in
11151 SFmode. it's used to scale SFmode angles, in radians, to a
11152 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11153 maps to 0x10000). */
11155 static GTY(()) rtx sh_fsca_sf2int_rtx;
11158 sh_fsca_sf2int (void)
11160 if (! sh_fsca_sf2int_rtx)
11162 REAL_VALUE_TYPE rv;
11164 real_from_string (&rv, "10430.378350470453");
11165 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
11168 return sh_fsca_sf2int_rtx;
11171 /* This function returns a constant rtx that represents pi / 2**15 in
11172 DFmode. it's used to scale DFmode angles, in radians, to a
11173 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11174 maps to 0x10000). */
11176 static GTY(()) rtx sh_fsca_df2int_rtx;
11179 sh_fsca_df2int (void)
11181 if (! sh_fsca_df2int_rtx)
11183 REAL_VALUE_TYPE rv;
11185 real_from_string (&rv, "10430.378350470453");
11186 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
11189 return sh_fsca_df2int_rtx;
11192 /* This function returns a constant rtx that represents 2**15 / pi in
11193 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
11194 of a full circle back to a SFmode value, i.e., 0x10000 maps to
11197 static GTY(()) rtx sh_fsca_int2sf_rtx;
11200 sh_fsca_int2sf (void)
11202 if (! sh_fsca_int2sf_rtx)
11204 REAL_VALUE_TYPE rv;
11206 real_from_string (&rv, "9.587379924285257e-5");
11207 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
11210 return sh_fsca_int2sf_rtx;
11213 /* Initialize the CUMULATIVE_ARGS structure. */
11216 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
11218 rtx libname ATTRIBUTE_UNUSED,
11220 signed int n_named_args,
11221 enum machine_mode mode)
11223 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
11224 pcum->free_single_fp_reg = 0;
11225 pcum->stack_regs = 0;
11226 pcum->byref_regs = 0;
11228 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
11230 /* XXX - Should we check TARGET_HITACHI here ??? */
11231 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
11235 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
11236 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
11237 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
11238 pcum->arg_count [(int) SH_ARG_INT]
11239 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
11242 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11243 && pcum->arg_count [(int) SH_ARG_INT] == 0
11244 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
11245 ? int_size_in_bytes (TREE_TYPE (fntype))
11246 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
11247 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
11248 == FIRST_RET_REG));
11252 pcum->arg_count [(int) SH_ARG_INT] = 0;
11253 pcum->prototype_p = FALSE;
11254 if (mode != VOIDmode)
11256 pcum->call_cookie =
11257 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11258 && GET_MODE_SIZE (mode) > 4
11259 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
11261 /* If the default ABI is the Renesas ABI then all library
11262 calls must assume that the library will be using the
11263 Renesas ABI. So if the function would return its result
11264 in memory then we must force the address of this memory
11265 block onto the stack. Ideally we would like to call
11266 targetm.calls.return_in_memory() here but we do not have
11267 the TYPE or the FNDECL available so we synthesize the
11268 contents of that function as best we can. */
11270 (TARGET_DEFAULT & MASK_HITACHI)
11271 && (mode == BLKmode
11272 || (GET_MODE_SIZE (mode) > 4
11273 && !(mode == DFmode
11274 && TARGET_FPU_DOUBLE)));
11278 pcum->call_cookie = 0;
11279 pcum->force_mem = FALSE;
11284 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
11285 not enter into CONST_DOUBLE for the replace.
11287 Note that copying is not done so X must not be shared unless all copies
11288 are to be modified.
11290 This is like replace_rtx, except that we operate on N_REPLACEMENTS
11291 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
11292 replacements[n*2+1] - and that we take mode changes into account.
11294 If a replacement is ambiguous, return NULL_RTX.
11296 If MODIFY is zero, don't modify any rtl in place,
11297 just return zero or nonzero for failure / success. */
11300 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
11305 /* The following prevents loops occurrence when we change MEM in
11306 CONST_DOUBLE onto the same CONST_DOUBLE. */
11307 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
11310 for (i = n_replacements - 1; i >= 0 ; i--)
11311 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
11312 return replacements[i*2+1];
11314 /* Allow this function to make replacements in EXPR_LISTs. */
11318 if (GET_CODE (x) == SUBREG)
11320 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
11321 n_replacements, modify);
11323 if (GET_CODE (new_rtx) == CONST_INT)
11325 x = simplify_subreg (GET_MODE (x), new_rtx,
11326 GET_MODE (SUBREG_REG (x)),
11332 SUBREG_REG (x) = new_rtx;
11336 else if (GET_CODE (x) == REG)
11338 unsigned regno = REGNO (x);
11339 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
11340 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11341 rtx result = NULL_RTX;
11343 for (i = n_replacements - 1; i >= 0; i--)
11345 rtx from = replacements[i*2];
11346 rtx to = replacements[i*2+1];
11347 unsigned from_regno, from_nregs, to_regno, new_regno;
11349 if (GET_CODE (from) != REG)
11351 from_regno = REGNO (from);
11352 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
11353 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
11354 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
11356 if (regno < from_regno
11357 || regno + nregs > from_regno + nregs
11358 || GET_CODE (to) != REG
11361 to_regno = REGNO (to);
11362 if (to_regno < FIRST_PSEUDO_REGISTER)
11364 new_regno = regno + to_regno - from_regno;
11365 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
11368 result = gen_rtx_REG (GET_MODE (x), new_regno);
11370 else if (GET_MODE (x) <= GET_MODE (to))
11371 result = gen_lowpart_common (GET_MODE (x), to);
11373 result = gen_lowpart_SUBREG (GET_MODE (x), to);
11376 return result ? result : x;
11378 else if (GET_CODE (x) == ZERO_EXTEND)
11380 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
11381 n_replacements, modify);
11383 if (GET_CODE (new_rtx) == CONST_INT)
11385 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
11386 new_rtx, GET_MODE (XEXP (x, 0)));
11391 XEXP (x, 0) = new_rtx;
11396 fmt = GET_RTX_FORMAT (GET_CODE (x));
11397 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
11403 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
11404 n_replacements, modify);
11408 XEXP (x, i) = new_rtx;
11410 else if (fmt[i] == 'E')
11411 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11413 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
11414 n_replacements, modify);
11418 XVECEXP (x, i, j) = new_rtx;
11426 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
11428 enum rtx_code code = TRUNCATE;
11430 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
11432 rtx inner = XEXP (x, 0);
11433 enum machine_mode inner_mode = GET_MODE (inner);
11435 if (inner_mode == mode)
11437 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
11439 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
11440 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
11442 code = GET_CODE (x);
11446 return gen_rtx_fmt_e (code, mode, x);
11449 /* called via for_each_rtx after reload, to clean up truncates of
11450 registers that span multiple actual hard registers. */
11452 shmedia_cleanup_truncate (rtx *p, void *n_changes)
11456 if (GET_CODE (x) != TRUNCATE)
11459 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && GET_CODE (reg) == REG)
11461 enum machine_mode reg_mode = GET_MODE (reg);
11462 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
11463 subreg_lowpart_offset (DImode, reg_mode));
11464 *(int*) n_changes += 1;
11470 /* Load and store depend on the highpart of the address. However,
11471 set_attr_alternative does not give well-defined results before reload,
11472 so we must look at the rtl ourselves to see if any of the feeding
11473 registers is used in a memref. */
11475 /* Called by sh_contains_memref_p via for_each_rtx. */
11477 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
11479 return (GET_CODE (*loc) == MEM);
11482 /* Return nonzero iff INSN contains a MEM. */
11484 sh_contains_memref_p (rtx insn)
11486 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
11489 /* Return nonzero iff INSN loads a banked register. */
11491 sh_loads_bankedreg_p (rtx insn)
11493 if (GET_CODE (PATTERN (insn)) == SET)
11495 rtx op = SET_DEST (PATTERN(insn));
11496 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11503 /* FNADDR is the MEM expression from a call expander. Return an address
11504 to use in an SHmedia insn pattern. */
11506 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
11510 fnaddr = XEXP (fnaddr, 0);
11511 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
11512 if (flag_pic && is_sym)
11514 if (! SYMBOL_REF_LOCAL_P (fnaddr))
11516 rtx reg = gen_reg_rtx (Pmode);
11518 /* We must not use GOTPLT for sibcalls, because PIC_REG
11519 must be restored before the PLT code gets to run. */
11521 emit_insn (gen_symGOT2reg (reg, fnaddr));
11523 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
11528 fnaddr = gen_sym2PIC (fnaddr);
11529 PUT_MODE (fnaddr, Pmode);
11532 /* If ptabs might trap, make this visible to the rest of the compiler.
11533 We generally assume that symbols pertain to valid locations, but
11534 it is possible to generate invalid symbols with asm or linker tricks.
11535 In a list of functions where each returns its successor, an invalid
11536 symbol might denote an empty list. */
11537 if (!TARGET_PT_FIXED
11538 && (!is_sym || TARGET_INVALID_SYMBOLS)
11539 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
11541 rtx tr = gen_reg_rtx (PDImode);
11543 emit_insn (gen_ptabs (tr, fnaddr));
11546 else if (! target_reg_operand (fnaddr, Pmode))
11547 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
11552 sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
11553 enum machine_mode mode, secondary_reload_info *sri)
11557 if (REGCLASS_HAS_FP_REG (rclass)
11558 && ! TARGET_SHMEDIA
11559 && immediate_operand ((x), mode)
11560 && ! ((fp_zero_operand (x) || fp_one_operand (x))
11561 && mode == SFmode && fldi_ok ()))
11565 sri->icode = CODE_FOR_reload_insf__frn;
11568 sri->icode = CODE_FOR_reload_indf__frn;
11571 /* ??? If we knew that we are in the appropriate mode -
11572 single precision - we could use a reload pattern directly. */
11577 if (rclass == FPUL_REGS
11578 && ((GET_CODE (x) == REG
11579 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11580 || REGNO (x) == T_REG))
11581 || GET_CODE (x) == PLUS))
11582 return GENERAL_REGS;
11583 if (rclass == FPUL_REGS && immediate_operand (x, mode))
11585 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
11586 return GENERAL_REGS;
11587 else if (mode == SFmode)
11589 sri->icode = CODE_FOR_reload_insi__i_fpul;
11592 if (rclass == FPSCR_REGS
11593 && ((GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11594 || (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PLUS)))
11595 return GENERAL_REGS;
11596 if (REGCLASS_HAS_FP_REG (rclass)
11598 && immediate_operand (x, mode)
11599 && x != CONST0_RTX (GET_MODE (x))
11600 && GET_MODE (x) != V4SFmode)
11601 return GENERAL_REGS;
11602 if ((mode == QImode || mode == HImode)
11603 && TARGET_SHMEDIA && inqhi_operand (x, mode))
11605 sri->icode = ((mode == QImode)
11606 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
11609 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
11610 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
11611 return TARGET_REGS;
11612 } /* end of input-only processing. */
11614 if (((REGCLASS_HAS_FP_REG (rclass)
11615 && (GET_CODE (x) == REG
11616 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11617 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11618 && TARGET_FMOVD))))
11619 || (REGCLASS_HAS_GENERAL_REG (rclass)
11620 && GET_CODE (x) == REG
11621 && FP_REGISTER_P (REGNO (x))))
11622 && ! TARGET_SHMEDIA
11623 && (mode == SFmode || mode == SImode))
11625 if ((rclass == FPUL_REGS
11626 || (REGCLASS_HAS_FP_REG (rclass)
11627 && ! TARGET_SHMEDIA && mode == SImode))
11628 && (GET_CODE (x) == MEM
11629 || (GET_CODE (x) == REG
11630 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11631 || REGNO (x) == T_REG
11632 || system_reg_operand (x, VOIDmode)))))
11634 if (rclass == FPUL_REGS)
11635 return GENERAL_REGS;
11638 if ((rclass == TARGET_REGS
11639 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
11640 && !satisfies_constraint_Csy (x)
11641 && (GET_CODE (x) != REG || ! GENERAL_REGISTER_P (REGNO (x))))
11642 return GENERAL_REGS;
11643 if ((rclass == MAC_REGS || rclass == PR_REGS)
11644 && GET_CODE (x) == REG && ! GENERAL_REGISTER_P (REGNO (x))
11645 && rclass != REGNO_REG_CLASS (REGNO (x)))
11646 return GENERAL_REGS;
11647 if (rclass != GENERAL_REGS && GET_CODE (x) == REG
11648 && TARGET_REGISTER_P (REGNO (x)))
11649 return GENERAL_REGS;
11653 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;