1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
28 #include "insn-config.h"
36 #include "hard-reg-set.h"
38 #include "insn-attr.h"
42 #include "integrate.h"
45 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
54 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
56 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
57 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
59 /* These are some macros to abstract register modes. */
60 #define CONST_OK_FOR_ADD(size) \
61 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
62 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
63 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
64 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
66 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
67 int current_function_interrupt;
69 /* ??? The pragma interrupt support will not work for SH3. */
70 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
71 output code for the next function appropriate for an interrupt handler. */
74 /* This is set by the trap_exit attribute for functions. It specifies
75 a trap number to be used in a trapa instruction at function exit
76 (instead of an rte instruction). */
79 /* This is used by the sp_switch attribute for functions. It specifies
80 a variable holding the address of the stack the interrupt function
81 should switch to/from at entry/exit. */
84 /* This is set by #pragma trapa, and is similar to the above, except that
85 the compiler doesn't emit code to preserve all registers. */
86 static int pragma_trapa;
88 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
89 which has a separate set of low regs for User and Supervisor modes.
90 This should only be used for the lowest level of interrupts. Higher levels
91 of interrupts must save the registers in case they themselves are
93 int pragma_nosave_low_regs;
95 /* This is used for communication between SETUP_INCOMING_VARARGS and
96 sh_expand_prologue. */
97 int current_function_anonymous_args;
99 /* Global variables for machine-dependent things. */
101 /* Which cpu are we scheduling for. */
102 enum processor_type sh_cpu;
104 /* Saved operands from the last compare to use when we generate an scc
110 /* Provides the class number of the smallest class containing
113 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
115 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
131 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
147 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
148 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
149 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
150 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
151 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
152 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
156 char sh_register_names[FIRST_PSEUDO_REGISTER] \
157 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
159 char sh_additional_register_names[ADDREGNAMES_SIZE] \
160 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
161 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
163 /* Provide reg_class from a letter such as appears in the machine
164 description. *: target independently reserved letter.
165 reg_class_from_letter['e' - 'a'] is set to NO_REGS for TARGET_FMOVD. */
167 enum reg_class reg_class_from_letter[] =
169 /* a */ ALL_REGS, /* b */ TARGET_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
170 /* e */ FP_REGS, /* f */ FP_REGS, /* g **/ NO_REGS, /* h */ NO_REGS,
171 /* i **/ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
172 /* m **/ NO_REGS, /* n **/ NO_REGS, /* o **/ NO_REGS, /* p **/ NO_REGS,
173 /* q */ NO_REGS, /* r **/ NO_REGS, /* s **/ NO_REGS, /* t */ T_REGS,
174 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
175 /* y */ FPUL_REGS, /* z */ R0_REGS
178 int assembler_dialect;
180 static bool shmedia_space_reserved_for_target_registers;
182 static void split_branches (rtx);
183 static int branch_dest (rtx);
184 static void force_into (rtx, rtx);
185 static void print_slot (rtx);
186 static rtx add_constant (rtx, enum machine_mode, rtx);
187 static void dump_table (rtx);
188 static int hi_const (rtx);
189 static int broken_move (rtx);
190 static int mova_p (rtx);
191 static rtx find_barrier (int, rtx, rtx);
192 static int noncall_uses_reg (rtx, rtx, rtx *);
193 static rtx gen_block_redirect (rtx, int, int);
194 static void sh_reorg (void);
195 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
196 static rtx frame_insn (rtx);
197 static rtx push (int);
198 static void pop (int);
199 static void push_regs (HARD_REG_SET *, int);
200 static int calc_live_regs (HARD_REG_SET *);
201 static void mark_use (rtx, rtx *);
202 static HOST_WIDE_INT rounded_frame_size (int);
203 static rtx mark_constant_pool_use (rtx);
204 const struct attribute_spec sh_attribute_table[];
205 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
206 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
207 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
208 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
209 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
210 static void sh_insert_attributes (tree, tree *);
211 static int sh_adjust_cost (rtx, rtx, rtx, int);
212 static int sh_use_dfa_interface (void);
213 static int sh_issue_rate (void);
214 static bool sh_function_ok_for_sibcall (tree, tree);
216 static bool sh_cannot_modify_jumps_p (void);
217 static int sh_target_reg_class (void);
218 static bool sh_optimize_target_register_callee_saved (bool);
219 static bool sh_ms_bitfield_layout_p (tree);
221 static void sh_init_builtins (void);
222 static void sh_media_init_builtins (void);
223 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
224 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
225 static void sh_file_start (void);
226 static int flow_dependent_p (rtx, rtx);
227 static void flow_dependent_p_1 (rtx, rtx, void *);
228 static int shiftcosts (rtx);
229 static int andcosts (rtx);
230 static int addsubcosts (rtx);
231 static int multcosts (rtx);
232 static bool unspec_caller_rtx_p (rtx);
233 static bool sh_cannot_copy_insn_p (rtx);
234 static bool sh_rtx_costs (rtx, int, int, int *);
235 static int sh_address_cost (rtx);
236 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
237 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
238 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
239 static int scavenge_reg (HARD_REG_SET *s);
240 struct save_schedule_s;
241 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
242 struct save_schedule_s *, int);
244 static bool sh_promote_prototypes (tree);
245 static rtx sh_struct_value_rtx (tree, int);
246 static bool sh_return_in_memory (tree, tree);
247 static rtx sh_builtin_saveregs (void);
248 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
249 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
250 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
251 static tree sh_build_builtin_va_list (void);
254 /* Initialize the GCC target structure. */
255 #undef TARGET_ATTRIBUTE_TABLE
256 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
258 /* The next two are used for debug info when compiling with -gdwarf. */
259 #undef TARGET_ASM_UNALIGNED_HI_OP
260 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
261 #undef TARGET_ASM_UNALIGNED_SI_OP
262 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
264 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
265 #undef TARGET_ASM_UNALIGNED_DI_OP
266 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
267 #undef TARGET_ASM_ALIGNED_DI_OP
268 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
270 #undef TARGET_ASM_FUNCTION_EPILOGUE
271 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
273 #undef TARGET_ASM_OUTPUT_MI_THUNK
274 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
276 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
277 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
279 #undef TARGET_ASM_FILE_START
280 #define TARGET_ASM_FILE_START sh_file_start
281 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
282 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
284 #undef TARGET_INSERT_ATTRIBUTES
285 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
287 #undef TARGET_SCHED_ADJUST_COST
288 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
290 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
291 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
293 #undef TARGET_SCHED_ISSUE_RATE
294 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
296 #undef TARGET_CANNOT_MODIFY_JUMPS_P
297 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
298 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
299 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
300 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
301 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
302 sh_optimize_target_register_callee_saved
304 #undef TARGET_MS_BITFIELD_LAYOUT_P
305 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
307 #undef TARGET_INIT_BUILTINS
308 #define TARGET_INIT_BUILTINS sh_init_builtins
309 #undef TARGET_EXPAND_BUILTIN
310 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
312 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
313 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
315 #undef TARGET_CANNOT_COPY_INSN_P
316 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
317 #undef TARGET_RTX_COSTS
318 #define TARGET_RTX_COSTS sh_rtx_costs
319 #undef TARGET_ADDRESS_COST
320 #define TARGET_ADDRESS_COST sh_address_cost
322 #undef TARGET_MACHINE_DEPENDENT_REORG
323 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
326 #undef TARGET_HAVE_TLS
327 #define TARGET_HAVE_TLS true
330 #undef TARGET_PROMOTE_PROTOTYPES
331 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
332 #undef TARGET_PROMOTE_FUNCTION_ARGS
333 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
334 #undef TARGET_PROMOTE_FUNCTION_RETURN
335 #define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
337 #undef TARGET_STRUCT_VALUE_RTX
338 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
339 #undef TARGET_RETURN_IN_MEMORY
340 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
342 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
343 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
344 #undef TARGET_SETUP_INCOMING_VARARGS
345 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
346 #undef TARGET_STRICT_ARGUMENT_NAMING
347 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
348 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
349 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
351 #undef TARGET_BUILD_BUILTIN_VA_LIST
352 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
354 #undef TARGET_PCH_VALID_P
355 #define TARGET_PCH_VALID_P sh_pch_valid_p
357 struct gcc_target targetm = TARGET_INITIALIZER;
359 /* Print the operand address in x to the stream. */
362 print_operand_address (FILE *stream, rtx x)
364 switch (GET_CODE (x))
368 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
373 rtx base = XEXP (x, 0);
374 rtx index = XEXP (x, 1);
376 switch (GET_CODE (index))
379 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
380 reg_names[true_regnum (base)]);
386 int base_num = true_regnum (base);
387 int index_num = true_regnum (index);
389 fprintf (stream, "@(r0,%s)",
390 reg_names[MAX (base_num, index_num)]);
402 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
406 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
410 x = mark_constant_pool_use (x);
411 output_addr_const (stream, x);
416 /* Print operand x (an rtx) in assembler syntax to file stream
417 according to modifier code.
419 '.' print a .s if insn needs delay slot
420 ',' print LOCAL_LABEL_PREFIX
421 '@' print trap, rte or rts depending upon pragma interruptness
422 '#' output a nop if there is nothing to put in the delay slot
423 ''' print likelihood suffix (/u for unlikely).
424 'O' print a constant without the #
425 'R' print the LSW of a dp value - changes if in little endian
426 'S' print the MSW of a dp value - changes if in little endian
427 'T' print the next word of a dp value - same as 'R' in big endian mode.
428 'M' print an `x' if `m' will print `base,index'.
429 'N' print 'r63' if the operand is (const_int 0).
430 'm' print a pair `base,offset' or `base,index', for LD and ST.
431 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
432 'o' output an operator. */
435 print_operand (FILE *stream, rtx x, int code)
441 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
442 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
443 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
446 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
450 fprintf (stream, "trapa #%d", trap_exit);
451 else if (sh_cfun_interrupt_handler_p ())
452 fprintf (stream, "rte");
454 fprintf (stream, "rts");
457 /* Output a nop if there's nothing in the delay slot. */
458 if (dbr_sequence_length () == 0)
459 fprintf (stream, "\n\tnop");
463 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
465 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
466 fputs ("/u", stream);
470 x = mark_constant_pool_use (x);
471 output_addr_const (stream, x);
474 fputs (reg_names[REGNO (x) + LSW], (stream));
477 fputs (reg_names[REGNO (x) + MSW], (stream));
480 /* Next word of a double. */
481 switch (GET_CODE (x))
484 fputs (reg_names[REGNO (x) + 1], (stream));
487 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
488 && GET_CODE (XEXP (x, 0)) != POST_INC)
489 x = adjust_address (x, SImode, 4);
490 print_operand_address (stream, XEXP (x, 0));
497 switch (GET_CODE (x))
499 case PLUS: fputs ("add", stream); break;
500 case MINUS: fputs ("sub", stream); break;
501 case MULT: fputs ("mul", stream); break;
502 case DIV: fputs ("div", stream); break;
503 case EQ: fputs ("eq", stream); break;
504 case NE: fputs ("ne", stream); break;
505 case GT: case LT: fputs ("gt", stream); break;
506 case GE: case LE: fputs ("ge", stream); break;
507 case GTU: case LTU: fputs ("gtu", stream); break;
508 case GEU: case LEU: fputs ("geu", stream); break;
514 if (GET_CODE (x) == MEM
515 && GET_CODE (XEXP (x, 0)) == PLUS
516 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
517 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
522 if (GET_CODE (x) != MEM)
525 switch (GET_CODE (x))
529 print_operand (stream, x, 0);
530 fputs (", 0", stream);
534 print_operand (stream, XEXP (x, 0), 0);
535 fputs (", ", stream);
536 print_operand (stream, XEXP (x, 1), 0);
545 if (x == CONST0_RTX (GET_MODE (x)))
547 fprintf ((stream), "r63");
552 if (GET_CODE (x) == CONST_INT)
554 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
561 switch (GET_CODE (x))
563 /* FIXME: We need this on SHmedia32 because reload generates
564 some sign-extended HI or QI loads into DImode registers
565 but, because Pmode is SImode, the address ends up with a
566 subreg:SI of the DImode register. Maybe reload should be
567 fixed so as to apply alter_subreg to such loads? */
569 if (SUBREG_BYTE (x) != 0
570 || GET_CODE (SUBREG_REG (x)) != REG)
577 if (FP_REGISTER_P (REGNO (x))
578 && GET_MODE (x) == V16SFmode)
579 fprintf ((stream), "mtrx%s", reg_names[REGNO (x)] + 2);
580 else if (FP_REGISTER_P (REGNO (x))
581 && GET_MODE (x) == V4SFmode)
582 fprintf ((stream), "fv%s", reg_names[REGNO (x)] + 2);
583 else if (GET_CODE (x) == REG
584 && GET_MODE (x) == V2SFmode)
585 fprintf ((stream), "fp%s", reg_names[REGNO (x)] + 2);
586 else if (FP_REGISTER_P (REGNO (x))
587 && GET_MODE_SIZE (GET_MODE (x)) > 4)
588 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
590 fputs (reg_names[REGNO (x)], (stream));
594 output_address (XEXP (x, 0));
599 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
600 && GET_MODE (XEXP (x, 0)) == DImode
601 && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE
602 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)
604 rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0);
607 if (GET_CODE (val) == ASHIFTRT)
610 if (GET_CODE (XEXP (val, 0)) == CONST)
612 output_addr_const (stream, XEXP (val, 0));
613 if (GET_CODE (XEXP (val, 0)) == CONST)
615 fputs (" >> ", stream);
616 output_addr_const (stream, XEXP (val, 1));
621 if (GET_CODE (val) == CONST)
623 output_addr_const (stream, val);
624 if (GET_CODE (val) == CONST)
627 fputs (" & 65535)", stream);
635 output_addr_const (stream, x);
642 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
644 force_into (rtx value, rtx target)
646 value = force_operand (value, target);
647 if (! rtx_equal_p (value, target))
648 emit_insn (gen_move_insn (target, value));
651 /* Emit code to perform a block move. Choose the best method.
653 OPERANDS[0] is the destination.
654 OPERANDS[1] is the source.
655 OPERANDS[2] is the size.
656 OPERANDS[3] is the alignment safe to use. */
659 expand_block_move (rtx *operands)
661 int align = INTVAL (operands[3]);
662 int constp = (GET_CODE (operands[2]) == CONST_INT);
663 int bytes = (constp ? INTVAL (operands[2]) : 0);
665 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
666 alignment, or if it isn't a multiple of 4 bytes, then fail. */
667 if (! constp || align < 4 || (bytes % 4 != 0))
674 else if (bytes == 12)
679 rtx r4 = gen_rtx (REG, SImode, 4);
680 rtx r5 = gen_rtx (REG, SImode, 5);
682 entry_name = get_identifier ("__movstrSI12_i4");
684 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
685 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
686 force_into (XEXP (operands[0], 0), r4);
687 force_into (XEXP (operands[1], 0), r5);
688 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
691 else if (! TARGET_SMALLCODE)
697 rtx r4 = gen_rtx (REG, SImode, 4);
698 rtx r5 = gen_rtx (REG, SImode, 5);
699 rtx r6 = gen_rtx (REG, SImode, 6);
701 entry_name = get_identifier (bytes & 4
703 : "__movstr_i4_even");
704 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
705 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
706 force_into (XEXP (operands[0], 0), r4);
707 force_into (XEXP (operands[1], 0), r5);
710 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
711 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
723 rtx r4 = gen_rtx_REG (SImode, 4);
724 rtx r5 = gen_rtx_REG (SImode, 5);
726 sprintf (entry, "__movstrSI%d", bytes);
727 entry_name = get_identifier (entry);
728 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
729 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
730 force_into (XEXP (operands[0], 0), r4);
731 force_into (XEXP (operands[1], 0), r5);
732 emit_insn (gen_block_move_real (func_addr_rtx));
736 /* This is the same number of bytes as a memcpy call, but to a different
737 less common function name, so this will occasionally use more space. */
738 if (! TARGET_SMALLCODE)
743 int final_switch, while_loop;
744 rtx r4 = gen_rtx_REG (SImode, 4);
745 rtx r5 = gen_rtx_REG (SImode, 5);
746 rtx r6 = gen_rtx_REG (SImode, 6);
748 entry_name = get_identifier ("__movstr");
749 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
750 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
751 force_into (XEXP (operands[0], 0), r4);
752 force_into (XEXP (operands[1], 0), r5);
754 /* r6 controls the size of the move. 16 is decremented from it
755 for each 64 bytes moved. Then the negative bit left over is used
756 as an index into a list of move instructions. e.g., a 72 byte move
757 would be set up with size(r6) = 14, for one iteration through the
758 big while loop, and a switch of -2 for the last part. */
760 final_switch = 16 - ((bytes / 4) % 16);
761 while_loop = ((bytes / 4) / 16 - 1) * 16;
762 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
763 emit_insn (gen_block_lump_real (func_addr_rtx));
770 /* Prepare operands for a move define_expand; specifically, one of the
771 operands must be in a register. */
774 prepare_move_operands (rtx operands[], enum machine_mode mode)
776 if ((mode == SImode || mode == DImode)
778 && ! ((mode == Pmode || mode == ptr_mode)
779 && tls_symbolic_operand (operands[1], Pmode) != 0))
782 if (SYMBOLIC_CONST_P (operands[1]))
784 if (GET_CODE (operands[0]) == MEM)
785 operands[1] = force_reg (Pmode, operands[1]);
786 else if (TARGET_SHMEDIA
787 && GET_CODE (operands[1]) == LABEL_REF
788 && target_reg_operand (operands[0], mode))
792 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
793 operands[1] = legitimize_pic_address (operands[1], mode, temp);
796 else if (GET_CODE (operands[1]) == CONST
797 && GET_CODE (XEXP (operands[1], 0)) == PLUS
798 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
800 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
801 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
803 operands[1] = expand_binop (mode, add_optab, temp,
804 XEXP (XEXP (operands[1], 0), 1),
805 no_new_pseudos ? temp
806 : gen_reg_rtx (Pmode),
811 if (! reload_in_progress && ! reload_completed)
813 /* Copy the source to a register if both operands aren't registers. */
814 if (! register_operand (operands[0], mode)
815 && ! sh_register_operand (operands[1], mode))
816 operands[1] = copy_to_mode_reg (mode, operands[1]);
818 if (GET_CODE (operands[0]) == MEM && ! memory_operand (operands[0], mode))
820 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
821 except that we can't use that function because it is static. */
822 rtx new = change_address (operands[0], mode, 0);
823 MEM_COPY_ATTRIBUTES (new, operands[0]);
827 /* This case can happen while generating code to move the result
828 of a library call to the target. Reject `st r0,@(rX,rY)' because
829 reload will fail to find a spill register for rX, since r0 is already
830 being used for the source. */
831 else if (refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
832 && GET_CODE (operands[0]) == MEM
833 && GET_CODE (XEXP (operands[0], 0)) == PLUS
834 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
835 operands[1] = copy_to_mode_reg (mode, operands[1]);
838 if (mode == Pmode || mode == ptr_mode)
841 enum tls_model tls_kind;
845 if ((tls_kind = tls_symbolic_operand (op1, Pmode)))
847 rtx tga_op1, tga_ret, tmp, tmp2;
852 case TLS_MODEL_GLOBAL_DYNAMIC:
853 tga_ret = gen_rtx_REG (Pmode, R0_REG);
854 emit_insn (gen_tls_global_dynamic (tga_ret, op1));
858 case TLS_MODEL_LOCAL_DYNAMIC:
859 tga_ret = gen_rtx_REG (Pmode, R0_REG);
860 emit_insn (gen_tls_local_dynamic (tga_ret, op1));
862 tmp = gen_reg_rtx (Pmode);
863 emit_move_insn (tmp, tga_ret);
865 if (register_operand (op0, Pmode))
868 tmp2 = gen_reg_rtx (Pmode);
870 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
874 case TLS_MODEL_INITIAL_EXEC:
876 emit_insn (gen_GOTaddr2picreg ());
877 tga_op1 = gen_reg_rtx (Pmode);
878 tmp = gen_sym2GOTTPOFF (op1);
879 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
883 case TLS_MODEL_LOCAL_EXEC:
884 tmp2 = gen_reg_rtx (Pmode);
885 emit_insn (gen_load_gbr (tmp2));
886 tmp = gen_reg_rtx (Pmode);
887 emit_insn (gen_symTPOFF2reg (tmp, op1));
888 RTX_UNCHANGING_P (tmp) = 1;
890 if (register_operand (op0, Pmode))
893 op1 = gen_reg_rtx (Pmode);
895 emit_insn (gen_addsi3 (op1, tmp, tmp2));
908 /* Prepare the operands for an scc instruction; make sure that the
909 compare has been done. */
911 prepare_scc_operands (enum rtx_code code)
913 rtx t_reg = gen_rtx_REG (SImode, T_REG);
914 enum rtx_code oldcode = code;
915 enum machine_mode mode;
917 /* First need a compare insn. */
921 /* It isn't possible to handle this case. */
940 rtx tmp = sh_compare_op0;
941 sh_compare_op0 = sh_compare_op1;
942 sh_compare_op1 = tmp;
945 mode = GET_MODE (sh_compare_op0);
946 if (mode == VOIDmode)
947 mode = GET_MODE (sh_compare_op1);
949 sh_compare_op0 = force_reg (mode, sh_compare_op0);
950 if ((code != EQ && code != NE
951 && (sh_compare_op1 != const0_rtx
952 || code == GTU || code == GEU || code == LTU || code == LEU))
953 || (mode == DImode && sh_compare_op1 != const0_rtx)
954 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
955 sh_compare_op1 = force_reg (mode, sh_compare_op1);
957 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
958 (mode == SFmode ? emit_sf_insn : emit_df_insn)
959 (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
960 gen_rtx (SET, VOIDmode, t_reg,
961 gen_rtx (code, SImode,
962 sh_compare_op0, sh_compare_op1)),
963 gen_rtx (USE, VOIDmode, get_fpscr_rtx ()))));
965 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
966 gen_rtx (code, SImode, sh_compare_op0,
972 /* Called from the md file, set up the operands of a compare instruction. */
975 from_compare (rtx *operands, int code)
977 enum machine_mode mode = GET_MODE (sh_compare_op0);
979 if (mode == VOIDmode)
980 mode = GET_MODE (sh_compare_op1);
983 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
985 /* Force args into regs, since we can't use constants here. */
986 sh_compare_op0 = force_reg (mode, sh_compare_op0);
987 if (sh_compare_op1 != const0_rtx
988 || code == GTU || code == GEU
989 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
990 sh_compare_op1 = force_reg (mode, sh_compare_op1);
992 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
994 from_compare (operands, GT);
995 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
998 insn = gen_rtx_SET (VOIDmode,
999 gen_rtx_REG (SImode, T_REG),
1000 gen_rtx (code, SImode, sh_compare_op0,
1002 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
1004 insn = gen_rtx (PARALLEL, VOIDmode,
1006 gen_rtx (USE, VOIDmode, get_fpscr_rtx ())));
1007 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1013 /* Functions to output assembly code. */
1015 /* Return a sequence of instructions to perform DI or DF move.
1017 Since the SH cannot move a DI or DF in one instruction, we have
1018 to take care when we see overlapping source and dest registers. */
1021 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1022 enum machine_mode mode)
1024 rtx dst = operands[0];
1025 rtx src = operands[1];
1027 if (GET_CODE (dst) == MEM
1028 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
1029 return "mov.l %T1,%0\n\tmov.l %1,%0";
1031 if (register_operand (dst, mode)
1032 && register_operand (src, mode))
1034 if (REGNO (src) == MACH_REG)
1035 return "sts mach,%S0\n\tsts macl,%R0";
1037 /* When mov.d r1,r2 do r2->r3 then r1->r2;
1038 when mov.d r1,r0 do r1->r0 then r2->r1. */
1040 if (REGNO (src) + 1 == REGNO (dst))
1041 return "mov %T1,%T0\n\tmov %1,%0";
1043 return "mov %1,%0\n\tmov %T1,%T0";
1045 else if (GET_CODE (src) == CONST_INT)
1047 if (INTVAL (src) < 0)
1048 output_asm_insn ("mov #-1,%S0", operands);
1050 output_asm_insn ("mov #0,%S0", operands);
1052 return "mov %1,%R0";
1054 else if (GET_CODE (src) == MEM)
1057 int dreg = REGNO (dst);
1058 rtx inside = XEXP (src, 0);
1060 if (GET_CODE (inside) == REG)
1061 ptrreg = REGNO (inside);
1062 else if (GET_CODE (inside) == SUBREG)
1063 ptrreg = subreg_regno (inside);
1064 else if (GET_CODE (inside) == PLUS)
1066 ptrreg = REGNO (XEXP (inside, 0));
1067 /* ??? A r0+REG address shouldn't be possible here, because it isn't
1068 an offsettable address. Unfortunately, offsettable addresses use
1069 QImode to check the offset, and a QImode offsettable address
1070 requires r0 for the other operand, which is not currently
1071 supported, so we can't use the 'o' constraint.
1072 Thus we must check for and handle r0+REG addresses here.
1073 We punt for now, since this is likely very rare. */
1074 if (GET_CODE (XEXP (inside, 1)) == REG)
1077 else if (GET_CODE (inside) == LABEL_REF)
1078 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
1079 else if (GET_CODE (inside) == POST_INC)
1080 return "mov.l %1,%0\n\tmov.l %1,%T0";
1084 /* Work out the safe way to copy. Copy into the second half first. */
1086 return "mov.l %T1,%T0\n\tmov.l %1,%0";
1089 return "mov.l %1,%0\n\tmov.l %T1,%T0";
1092 /* Print an instruction which would have gone into a delay slot after
1093 another instruction, but couldn't because the other instruction expanded
1094 into a sequence where putting the slot insn at the end wouldn't work. */
1097 print_slot (rtx insn)
1099 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1, NULL);
1101 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
1105 output_far_jump (rtx insn, rtx op)
1107 struct { rtx lab, reg, op; } this;
1108 rtx braf_base_lab = NULL_RTX;
1111 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
1114 this.lab = gen_label_rtx ();
1118 && offset - get_attr_length (insn) <= 32766)
1121 jump = "mov.w %O0,%1; braf %1";
1129 jump = "mov.l %O0,%1; braf %1";
1131 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1134 jump = "mov.l %O0,%1; jmp @%1";
1136 /* If we have a scratch register available, use it. */
1137 if (GET_CODE ((prev = prev_nonnote_insn (insn))) == INSN
1138 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
1140 this.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
1141 if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2)
1142 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1143 output_asm_insn (jump, &this.lab);
1144 if (dbr_sequence_length ())
1145 print_slot (final_sequence);
1147 output_asm_insn ("nop", 0);
1151 /* Output the delay slot insn first if any. */
1152 if (dbr_sequence_length ())
1153 print_slot (final_sequence);
1155 this.reg = gen_rtx_REG (SImode, 13);
1156 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1157 Fortunately, MACL is fixed and call-clobbered, and we never
1158 need its value across jumps, so save r13 in it instead of in
1161 output_asm_insn ("lds r13, macl", 0);
1163 output_asm_insn ("mov.l r13,@-r15", 0);
1164 output_asm_insn (jump, &this.lab);
1166 output_asm_insn ("sts macl, r13", 0);
1168 output_asm_insn ("mov.l @r15+,r13", 0);
1170 if (far && flag_pic && TARGET_SH2)
1172 braf_base_lab = gen_label_rtx ();
1173 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1174 CODE_LABEL_NUMBER (braf_base_lab));
1177 output_asm_insn (".align 2", 0);
1178 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
1180 if (far && flag_pic)
1183 this.lab = braf_base_lab;
1184 output_asm_insn (".long %O2-%O0", &this.lab);
1187 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
1191 /* Local label counter, used for constants in the pool and inside
1192 pattern branches. */
1194 static int lf = 100;
1196 /* Output code for ordinary branches. */
1199 output_branch (int logic, rtx insn, rtx *operands)
1201 switch (get_attr_length (insn))
1204 /* This can happen if filling the delay slot has caused a forward
1205 branch to exceed its range (we could reverse it, but only
1206 when we know we won't overextend other branches; this should
1207 best be handled by relaxation).
1208 It can also happen when other condbranches hoist delay slot insn
1209 from their destination, thus leading to code size increase.
1210 But the branch will still be in the range -4092..+4098 bytes. */
1215 /* The call to print_slot will clobber the operands. */
1216 rtx op0 = operands[0];
1218 /* If the instruction in the delay slot is annulled (true), then
1219 there is no delay slot where we can put it now. The only safe
1220 place for it is after the label. final will do that by default. */
1223 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1225 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
1226 ASSEMBLER_DIALECT ? "/" : ".", label);
1227 print_slot (final_sequence);
1230 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
1232 output_asm_insn ("bra\t%l0", &op0);
1233 fprintf (asm_out_file, "\tnop\n");
1234 (*targetm.asm_out.internal_label)(asm_out_file, "LF", label);
1238 /* When relaxing, handle this like a short branch. The linker
1239 will fix it up if it still doesn't fit after relaxation. */
1241 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
1243 /* These are for SH2e, in which we have to account for the
1244 extra nop because of the hardware bug in annulled branches. */
1251 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1253 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
1255 ASSEMBLER_DIALECT ? "/" : ".", label);
1256 fprintf (asm_out_file, "\tnop\n");
1257 output_asm_insn ("bra\t%l0", operands);
1258 fprintf (asm_out_file, "\tnop\n");
1259 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
1263 /* When relaxing, fall through. */
1268 sprintf (buffer, "b%s%ss\t%%l0",
1270 ASSEMBLER_DIALECT ? "/" : ".");
1271 output_asm_insn (buffer, &operands[0]);
1276 /* There should be no longer branches now - that would
1277 indicate that something has destroyed the branches set
1278 up in machine_dependent_reorg. */
1284 output_branchy_insn (enum rtx_code code, const char *template,
1285 rtx insn, rtx *operands)
1287 rtx next_insn = NEXT_INSN (insn);
1289 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
1291 rtx src = SET_SRC (PATTERN (next_insn));
1292 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
1294 /* Following branch not taken */
1295 operands[9] = gen_label_rtx ();
1296 emit_label_after (operands[9], next_insn);
1297 INSN_ADDRESSES_NEW (operands[9],
1298 INSN_ADDRESSES (INSN_UID (next_insn))
1299 + get_attr_length (next_insn));
1304 int offset = (branch_dest (next_insn)
1305 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
1306 if (offset >= -252 && offset <= 258)
1308 if (GET_CODE (src) == IF_THEN_ELSE)
1310 src = XEXP (src, 1);
1316 operands[9] = gen_label_rtx ();
1317 emit_label_after (operands[9], insn);
1318 INSN_ADDRESSES_NEW (operands[9],
1319 INSN_ADDRESSES (INSN_UID (insn))
1320 + get_attr_length (insn));
1325 output_ieee_ccmpeq (rtx insn, rtx *operands)
1327 return output_branchy_insn (NE, "bt\t%l9\\;fcmp/eq\t%1,%0", insn, operands);
1330 /* Output the start of the assembler file. */
1333 sh_file_start (void)
1335 default_file_start ();
1338 /* We need to show the text section with the proper
1339 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
1340 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
1341 will complain. We can teach GAS specifically about the
1342 default attributes for our choice of text section, but
1343 then we would have to change GAS again if/when we change
1344 the text section name. */
1345 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
1347 /* Switch to the data section so that the coffsem symbol
1348 isn't in the text section. */
1351 if (TARGET_LITTLE_ENDIAN)
1352 fputs ("\t.little\n", asm_out_file);
1356 if (TARGET_SHCOMPACT)
1357 fputs ("\t.mode\tSHcompact\n", asm_out_file);
1358 else if (TARGET_SHMEDIA)
1359 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1360 TARGET_SHMEDIA64 ? 64 : 32);
1364 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
1367 unspec_caller_rtx_p (rtx pat)
1369 switch (GET_CODE (pat))
1372 return unspec_caller_rtx_p (XEXP (pat, 0));
1375 if (unspec_caller_rtx_p (XEXP (pat, 0)))
1377 return unspec_caller_rtx_p (XEXP (pat, 1));
1379 if (XINT (pat, 1) == UNSPEC_CALLER)
1388 /* Indicate that INSN cannot be duplicated. This is true for insn
1389 that generates an unique label. */
1392 sh_cannot_copy_insn_p (rtx insn)
1396 if (!reload_completed || !flag_pic)
1399 if (GET_CODE (insn) != INSN)
1401 if (asm_noperands (insn) >= 0)
1404 pat = PATTERN (insn);
1405 if (GET_CODE (pat) != SET)
1407 pat = SET_SRC (pat);
1409 if (unspec_caller_rtx_p (pat))
1415 /* Actual number of instructions used to make a shift by N. */
1416 static const char ashiftrt_insns[] =
1417 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1419 /* Left shift and logical right shift are the same. */
1420 static const char shift_insns[] =
1421 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1423 /* Individual shift amounts needed to get the above length sequences.
1424 One bit right shifts clobber the T bit, so when possible, put one bit
1425 shifts in the middle of the sequence, so the ends are eligible for
1426 branch delay slots. */
1427 static const short shift_amounts[32][5] = {
1428 {0}, {1}, {2}, {2, 1},
1429 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1430 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1431 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1432 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1433 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1434 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1435 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1437 /* Likewise, but for shift amounts < 16, up to three highmost bits
1438 might be clobbered. This is typically used when combined with some
1439 kind of sign or zero extension. */
1441 static const char ext_shift_insns[] =
1442 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1444 static const short ext_shift_amounts[32][4] = {
1445 {0}, {1}, {2}, {2, 1},
1446 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1447 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1448 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1449 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1450 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1451 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1452 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1454 /* Assuming we have a value that has been sign-extended by at least one bit,
1455 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1456 to shift it by N without data loss, and quicker than by other means? */
1457 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1459 /* This is used in length attributes in sh.md to help compute the length
1460 of arbitrary constant shift instructions. */
1463 shift_insns_rtx (rtx insn)
1465 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1466 int shift_count = INTVAL (XEXP (set_src, 1));
1467 enum rtx_code shift_code = GET_CODE (set_src);
1472 return ashiftrt_insns[shift_count];
1475 return shift_insns[shift_count];
1481 /* Return the cost of a shift. */
1491 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
1493 if (GET_MODE (x) == DImode
1494 && GET_CODE (XEXP (x, 1)) == CONST_INT
1495 && INTVAL (XEXP (x, 1)) == 1)
1498 /* Everything else is invalid, because there is no pattern for it. */
1501 /* If shift by a non constant, then this will be expensive. */
1502 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1503 return SH_DYNAMIC_SHIFT_COST;
1505 value = INTVAL (XEXP (x, 1));
1507 /* Otherwise, return the true cost in instructions. */
1508 if (GET_CODE (x) == ASHIFTRT)
1510 int cost = ashiftrt_insns[value];
1511 /* If SH3, then we put the constant in a reg and use shad. */
1512 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
1513 cost = 1 + SH_DYNAMIC_SHIFT_COST;
1517 return shift_insns[value];
1520 /* Return the cost of an AND operation. */
1527 /* Anding with a register is a single cycle and instruction. */
1528 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1531 i = INTVAL (XEXP (x, 1));
1535 if ((GET_CODE (XEXP (x, 1)) == CONST_INT
1536 && CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
1537 || EXTRA_CONSTRAINT_C16 (XEXP (x, 1)))
1543 /* These constants are single cycle extu.[bw] instructions. */
1544 if (i == 0xff || i == 0xffff)
1546 /* Constants that can be used in an and immediate instruction in a single
1547 cycle, but this requires r0, so make it a little more expensive. */
1548 if (CONST_OK_FOR_K08 (i))
1550 /* Constants that can be loaded with a mov immediate and an and.
1551 This case is probably unnecessary. */
1552 if (CONST_OK_FOR_I08 (i))
1554 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1555 This case is probably unnecessary. */
1559 /* Return the cost of an addition or a subtraction. */
1564 /* Adding a register is a single cycle insn. */
1565 if (GET_CODE (XEXP (x, 1)) == REG
1566 || GET_CODE (XEXP (x, 1)) == SUBREG)
1569 /* Likewise for small constants. */
1570 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1571 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
1575 switch (GET_CODE (XEXP (x, 1)))
1580 return TARGET_SHMEDIA64 ? 5 : 3;
1583 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
1585 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
1587 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
1595 /* Any other constant requires a 2 cycle pc-relative load plus an
1600 /* Return the cost of a multiply. */
1602 multcosts (rtx x ATTRIBUTE_UNUSED)
1609 /* We have a mul insn, so we can never take more than the mul and the
1610 read of the mac reg, but count more because of the latency and extra
1612 if (TARGET_SMALLCODE)
1617 /* If we're aiming at small code, then just count the number of
1618 insns in a multiply call sequence. */
1619 if (TARGET_SMALLCODE)
1622 /* Otherwise count all the insns in the routine we'd be calling too. */
1626 /* Compute a (partial) cost for rtx X. Return true if the complete
1627 cost has been computed, and false if subexpressions should be
1628 scanned. In either case, *TOTAL contains the cost result. */
1631 sh_rtx_costs (rtx x, int code, int outer_code, int *total)
1638 if (INTVAL (x) == 0)
1640 else if (outer_code == AND && and_operand ((x), DImode))
1642 else if ((outer_code == IOR || outer_code == XOR
1643 || outer_code == PLUS)
1644 && CONST_OK_FOR_I10 (INTVAL (x)))
1646 else if (CONST_OK_FOR_I16 (INTVAL (x)))
1647 *total = COSTS_N_INSNS (outer_code != SET);
1648 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
1649 *total = COSTS_N_INSNS (2);
1650 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
1651 *total = COSTS_N_INSNS (3);
1653 *total = COSTS_N_INSNS (4);
1656 if (CONST_OK_FOR_I08 (INTVAL (x)))
1658 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
1659 && CONST_OK_FOR_K08 (INTVAL (x)))
1668 if (TARGET_SHMEDIA64)
1669 *total = COSTS_N_INSNS (4);
1670 else if (TARGET_SHMEDIA32)
1671 *total = COSTS_N_INSNS (2);
1678 *total = COSTS_N_INSNS (4);
1684 *total = COSTS_N_INSNS (addsubcosts (x));
1688 *total = COSTS_N_INSNS (andcosts (x));
1692 *total = COSTS_N_INSNS (multcosts (x));
1698 *total = COSTS_N_INSNS (shiftcosts (x));
1705 *total = COSTS_N_INSNS (20);
1718 /* Compute the cost of an address. For the SH, all valid addresses are
1719 the same cost. Use a slightly higher cost for reg + reg addressing,
1720 since it increases pressure on r0. */
1723 sh_address_cost (rtx X)
1725 return (GET_CODE (X) == PLUS
1726 && ! CONSTANT_P (XEXP (X, 1))
1727 && ! TARGET_SHMEDIA ? 1 : 0);
1730 /* Code to expand a shift. */
1733 gen_ashift (int type, int n, rtx reg)
1735 /* Negative values here come from the shift_amounts array. */
1748 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
1752 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
1754 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
1757 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
1762 /* Same for HImode */
1765 gen_ashift_hi (int type, int n, rtx reg)
1767 /* Negative values here come from the shift_amounts array. */
1781 /* We don't have HImode right shift operations because using the
1782 ordinary 32 bit shift instructions for that doesn't generate proper
1783 zero/sign extension.
1784 gen_ashift_hi is only called in contexts where we know that the
1785 sign extension works out correctly. */
1788 if (GET_CODE (reg) == SUBREG)
1790 offset = SUBREG_BYTE (reg);
1791 reg = SUBREG_REG (reg);
1793 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
1797 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
1802 /* Output RTL to split a constant shift into its component SH constant
1803 shift instructions. */
1806 gen_shifty_op (int code, rtx *operands)
1808 int value = INTVAL (operands[2]);
1811 /* Truncate the shift count in case it is out of bounds. */
1812 value = value & 0x1f;
1816 if (code == LSHIFTRT)
1818 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1819 emit_insn (gen_movt (operands[0]));
1822 else if (code == ASHIFT)
1824 /* There is a two instruction sequence for 31 bit left shifts,
1825 but it requires r0. */
1826 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
1828 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
1829 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1834 else if (value == 0)
1836 /* This can happen when not optimizing. We must output something here
1837 to prevent the compiler from aborting in final.c after the try_split
1839 emit_insn (gen_nop ());
1843 max = shift_insns[value];
1844 for (i = 0; i < max; i++)
1845 gen_ashift (code, shift_amounts[value][i], operands[0]);
1848 /* Same as above, but optimized for values where the topmost bits don't
1852 gen_shifty_hi_op (int code, rtx *operands)
1854 int value = INTVAL (operands[2]);
1856 void (*gen_fun) (int, int, rtx);
1858 /* This operation is used by and_shl for SImode values with a few
1859 high bits known to be cleared. */
1863 emit_insn (gen_nop ());
1867 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
1870 max = ext_shift_insns[value];
1871 for (i = 0; i < max; i++)
1872 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1875 /* When shifting right, emit the shifts in reverse order, so that
1876 solitary negative values come first. */
1877 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
1878 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1881 /* Output RTL for an arithmetic right shift. */
1883 /* ??? Rewrite to use super-optimizer sequences. */
1886 expand_ashiftrt (rtx *operands)
1896 if (GET_CODE (operands[2]) != CONST_INT)
1898 rtx count = copy_to_mode_reg (SImode, operands[2]);
1899 emit_insn (gen_negsi2 (count, count));
1900 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1903 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
1904 > 1 + SH_DYNAMIC_SHIFT_COST)
1907 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
1908 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1912 if (GET_CODE (operands[2]) != CONST_INT)
1915 value = INTVAL (operands[2]) & 31;
1919 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
1922 else if (value >= 16 && value <= 19)
1924 wrk = gen_reg_rtx (SImode);
1925 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
1928 gen_ashift (ASHIFTRT, 1, wrk);
1929 emit_move_insn (operands[0], wrk);
1932 /* Expand a short sequence inline, longer call a magic routine. */
1933 else if (value <= 5)
1935 wrk = gen_reg_rtx (SImode);
1936 emit_move_insn (wrk, operands[1]);
1938 gen_ashift (ASHIFTRT, 1, wrk);
1939 emit_move_insn (operands[0], wrk);
1943 wrk = gen_reg_rtx (Pmode);
1945 /* Load the value into an arg reg and call a helper. */
1946 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1947 sprintf (func, "__ashiftrt_r4_%d", value);
1948 func_name = get_identifier (func);
1949 sym = function_symbol (IDENTIFIER_POINTER (func_name));
1950 emit_move_insn (wrk, sym);
1951 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
1952 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
1957 sh_dynamicalize_shift_p (rtx count)
1959 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
1962 /* Try to find a good way to implement the combiner pattern
1963 [(set (match_operand:SI 0 "register_operand" "r")
1964 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1965 (match_operand:SI 2 "const_int_operand" "n"))
1966 (match_operand:SI 3 "const_int_operand" "n"))) .
1967 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1968 return 0 for simple right / left or left/right shift combination.
1969 return 1 for a combination of shifts with zero_extend.
1970 return 2 for a combination of shifts with an AND that needs r0.
1971 return 3 for a combination of shifts with an AND that needs an extra
1972 scratch register, when the three highmost bits of the AND mask are clear.
1973 return 4 for a combination of shifts with an AND that needs an extra
1974 scratch register, when any of the three highmost bits of the AND mask
1976 If ATTRP is set, store an initial right shift width in ATTRP[0],
1977 and the instruction length in ATTRP[1] . These values are not valid
1979 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1980 shift_amounts for the last shift value that is to be used before the
1983 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
1985 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
1986 int left = INTVAL (left_rtx), right;
1988 int cost, best_cost = 10000;
1989 int best_right = 0, best_len = 0;
1993 if (left < 0 || left > 31)
1995 if (GET_CODE (mask_rtx) == CONST_INT)
1996 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
1998 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
1999 /* Can this be expressed as a right shift / left shift pair ? */
2000 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
2001 right = exact_log2 (lsb);
2002 mask2 = ~(mask + lsb - 1);
2003 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
2004 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
2006 best_cost = shift_insns[right] + shift_insns[right + left];
2007 /* mask has no trailing zeroes <==> ! right */
2008 else if (! right && mask2 == ~(lsb2 - 1))
2010 int late_right = exact_log2 (lsb2);
2011 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
2013 /* Try to use zero extend */
2014 if (mask2 == ~(lsb2 - 1))
2018 for (width = 8; width <= 16; width += 8)
2020 /* Can we zero-extend right away? */
2021 if (lsb2 == (unsigned HOST_WIDE_INT)1 << width)
2024 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
2025 if (cost < best_cost)
2036 /* ??? Could try to put zero extend into initial right shift,
2037 or even shift a bit left before the right shift. */
2038 /* Determine value of first part of left shift, to get to the
2039 zero extend cut-off point. */
2040 first = width - exact_log2 (lsb2) + right;
2041 if (first >= 0 && right + left - first >= 0)
2043 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
2044 + ext_shift_insns[right + left - first];
2045 if (cost < best_cost)
2057 /* Try to use r0 AND pattern */
2058 for (i = 0; i <= 2; i++)
2062 if (! CONST_OK_FOR_K08 (mask >> i))
2064 cost = (i != 0) + 2 + ext_shift_insns[left + i];
2065 if (cost < best_cost)
2070 best_len = cost - 1;
2073 /* Try to use a scratch register to hold the AND operand. */
2074 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT)3 << 30)) == 0;
2075 for (i = 0; i <= 2; i++)
2079 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
2080 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
2081 if (cost < best_cost)
2086 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
2092 attrp[0] = best_right;
2093 attrp[1] = best_len;
2098 /* This is used in length attributes of the unnamed instructions
2099 corresponding to shl_and_kind return values of 1 and 2. */
2101 shl_and_length (rtx insn)
2103 rtx set_src, left_rtx, mask_rtx;
2106 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2107 left_rtx = XEXP (XEXP (set_src, 0), 1);
2108 mask_rtx = XEXP (set_src, 1);
2109 shl_and_kind (left_rtx, mask_rtx, attributes);
2110 return attributes[1];
2113 /* This is used in length attribute of the and_shl_scratch instruction. */
2116 shl_and_scr_length (rtx insn)
2118 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2119 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
2120 rtx op = XEXP (set_src, 0);
2121 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
2122 op = XEXP (XEXP (op, 0), 0);
2123 return len + shift_insns[INTVAL (XEXP (op, 1))];
2126 /* Generating rtl? */
2127 extern int rtx_equal_function_value_matters;
2129 /* Generate rtl for instructions for which shl_and_kind advised a particular
2130 method of generating them, i.e. returned zero. */
2133 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
2136 unsigned HOST_WIDE_INT mask;
2137 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
2138 int right, total_shift;
2139 void (*shift_gen_fun) (int, rtx*) = gen_shifty_hi_op;
2141 right = attributes[0];
2142 total_shift = INTVAL (left_rtx) + right;
2143 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
2150 int first = attributes[2];
2155 emit_insn ((mask << right) <= 0xff
2156 ? gen_zero_extendqisi2(dest,
2157 gen_lowpart (QImode, source))
2158 : gen_zero_extendhisi2(dest,
2159 gen_lowpart (HImode, source)));
2163 emit_insn (gen_movsi (dest, source));
2167 operands[2] = GEN_INT (right);
2168 gen_shifty_hi_op (LSHIFTRT, operands);
2172 operands[2] = GEN_INT (first);
2173 gen_shifty_hi_op (ASHIFT, operands);
2174 total_shift -= first;
2178 emit_insn (mask <= 0xff
2179 ? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest))
2180 : gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest)));
2181 if (total_shift > 0)
2183 operands[2] = GEN_INT (total_shift);
2184 gen_shifty_hi_op (ASHIFT, operands);
2189 shift_gen_fun = gen_shifty_op;
2191 /* If the topmost bit that matters is set, set the topmost bits
2192 that don't matter. This way, we might be able to get a shorter
2194 if (mask & ((HOST_WIDE_INT)1 << (31 - total_shift)))
2195 mask |= (HOST_WIDE_INT)~0 << (31 - total_shift);
2197 /* Don't expand fine-grained when combining, because that will
2198 make the pattern fail. */
2199 if (rtx_equal_function_value_matters
2200 || reload_in_progress || reload_completed)
2204 /* Cases 3 and 4 should be handled by this split
2205 only while combining */
2210 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
2213 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
2218 operands[2] = GEN_INT (total_shift);
2219 shift_gen_fun (ASHIFT, operands);
2226 if (kind != 4 && total_shift < 16)
2228 neg = -ext_shift_amounts[total_shift][1];
2230 neg -= ext_shift_amounts[total_shift][2];
2234 emit_insn (gen_and_shl_scratch (dest, source,
2237 GEN_INT (total_shift + neg),
2239 emit_insn (gen_movsi (dest, dest));
2246 /* Try to find a good way to implement the combiner pattern
2247 [(set (match_operand:SI 0 "register_operand" "=r")
2248 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2249 (match_operand:SI 2 "const_int_operand" "n")
2250 (match_operand:SI 3 "const_int_operand" "n")
2252 (clobber (reg:SI T_REG))]
2253 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
2254 return 0 for simple left / right shift combination.
2255 return 1 for left shift / 8 bit sign extend / left shift.
2256 return 2 for left shift / 16 bit sign extend / left shift.
2257 return 3 for left shift / 8 bit sign extend / shift / sign extend.
2258 return 4 for left shift / 16 bit sign extend / shift / sign extend.
2259 return 5 for left shift / 16 bit sign extend / right shift
2260 return 6 for < 8 bit sign extend / left shift.
2261 return 7 for < 8 bit sign extend / left shift / single right shift.
2262 If COSTP is nonzero, assign the calculated cost to *COSTP. */
2265 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
2267 int left, size, insize, ext;
2268 int cost = 0, best_cost;
2271 left = INTVAL (left_rtx);
2272 size = INTVAL (size_rtx);
2273 insize = size - left;
2276 /* Default to left / right shift. */
2278 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
2281 /* 16 bit shift / sign extend / 16 bit shift */
2282 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
2283 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
2284 below, by alternative 3 or something even better. */
2285 if (cost < best_cost)
2291 /* Try a plain sign extend between two shifts. */
2292 for (ext = 16; ext >= insize; ext -= 8)
2296 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
2297 if (cost < best_cost)
2299 kind = ext / (unsigned) 8;
2303 /* Check if we can do a sloppy shift with a final signed shift
2304 restoring the sign. */
2305 if (EXT_SHIFT_SIGNED (size - ext))
2306 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
2307 /* If not, maybe it's still cheaper to do the second shift sloppy,
2308 and do a final sign extend? */
2309 else if (size <= 16)
2310 cost = ext_shift_insns[ext - insize] + 1
2311 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
2314 if (cost < best_cost)
2316 kind = ext / (unsigned) 8 + 2;
2320 /* Check if we can sign extend in r0 */
2323 cost = 3 + shift_insns[left];
2324 if (cost < best_cost)
2329 /* Try the same with a final signed shift. */
2332 cost = 3 + ext_shift_insns[left + 1] + 1;
2333 if (cost < best_cost)
2342 /* Try to use a dynamic shift. */
2343 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
2344 if (cost < best_cost)
2355 /* Function to be used in the length attribute of the instructions
2356 implementing this pattern. */
2359 shl_sext_length (rtx insn)
2361 rtx set_src, left_rtx, size_rtx;
2364 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2365 left_rtx = XEXP (XEXP (set_src, 0), 1);
2366 size_rtx = XEXP (set_src, 1);
2367 shl_sext_kind (left_rtx, size_rtx, &cost);
2371 /* Generate rtl for this pattern */
2374 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
2377 int left, size, insize, cost;
2380 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
2381 left = INTVAL (left_rtx);
2382 size = INTVAL (size_rtx);
2383 insize = size - left;
2391 int ext = kind & 1 ? 8 : 16;
2392 int shift2 = size - ext;
2394 /* Don't expand fine-grained when combining, because that will
2395 make the pattern fail. */
2396 if (! rtx_equal_function_value_matters
2397 && ! reload_in_progress && ! reload_completed)
2399 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2400 emit_insn (gen_movsi (dest, source));
2404 emit_insn (gen_movsi (dest, source));
2408 operands[2] = GEN_INT (ext - insize);
2409 gen_shifty_hi_op (ASHIFT, operands);
2412 ? gen_extendqisi2(dest, gen_lowpart (QImode, dest))
2413 : gen_extendhisi2(dest, gen_lowpart (HImode, dest)));
2418 operands[2] = GEN_INT (shift2);
2419 gen_shifty_op (ASHIFT, operands);
2426 if (EXT_SHIFT_SIGNED (shift2))
2428 operands[2] = GEN_INT (shift2 + 1);
2429 gen_shifty_op (ASHIFT, operands);
2430 operands[2] = GEN_INT (1);
2431 gen_shifty_op (ASHIFTRT, operands);
2434 operands[2] = GEN_INT (shift2);
2435 gen_shifty_hi_op (ASHIFT, operands);
2439 operands[2] = GEN_INT (-shift2);
2440 gen_shifty_hi_op (LSHIFTRT, operands);
2442 emit_insn (size <= 8
2443 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
2444 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2451 if (! rtx_equal_function_value_matters
2452 && ! reload_in_progress && ! reload_completed)
2453 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2457 operands[2] = GEN_INT (16 - insize);
2458 gen_shifty_hi_op (ASHIFT, operands);
2459 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2461 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2463 gen_ashift (ASHIFTRT, 1, dest);
2468 /* Don't expand fine-grained when combining, because that will
2469 make the pattern fail. */
2470 if (! rtx_equal_function_value_matters
2471 && ! reload_in_progress && ! reload_completed)
2473 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2474 emit_insn (gen_movsi (dest, source));
2477 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
2478 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
2479 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
2481 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
2482 gen_shifty_op (ASHIFT, operands);
2484 emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
2492 /* Prefix a symbol_ref name with "datalabel". */
2495 gen_datalabel_ref (rtx sym)
2497 if (GET_CODE (sym) == LABEL_REF)
2498 return gen_rtx_CONST (GET_MODE (sym),
2499 gen_rtx_UNSPEC (GET_MODE (sym),
2503 if (GET_CODE (sym) != SYMBOL_REF)
2510 /* The SH cannot load a large constant into a register, constants have to
2511 come from a pc relative load. The reference of a pc relative load
2512 instruction must be less than 1k infront of the instruction. This
2513 means that we often have to dump a constant inside a function, and
2514 generate code to branch around it.
2516 It is important to minimize this, since the branches will slow things
2517 down and make things bigger.
2519 Worst case code looks like:
2537 We fix this by performing a scan before scheduling, which notices which
2538 instructions need to have their operands fetched from the constant table
2539 and builds the table.
2543 scan, find an instruction which needs a pcrel move. Look forward, find the
2544 last barrier which is within MAX_COUNT bytes of the requirement.
2545 If there isn't one, make one. Process all the instructions between
2546 the find and the barrier.
2548 In the above example, we can tell that L3 is within 1k of L1, so
2549 the first move can be shrunk from the 3 insn+constant sequence into
2550 just 1 insn, and the constant moved to L3 to make:
2561 Then the second move becomes the target for the shortening process. */
2565 rtx value; /* Value in table. */
2566 rtx label; /* Label of value. */
2567 rtx wend; /* End of window. */
2568 enum machine_mode mode; /* Mode of value. */
2570 /* True if this constant is accessed as part of a post-increment
2571 sequence. Note that HImode constants are never accessed in this way. */
2572 bool part_of_sequence_p;
2575 /* The maximum number of constants that can fit into one pool, since
2576 the pc relative range is 0...1020 bytes and constants are at least 4
2579 #define MAX_POOL_SIZE (1020/4)
2580 static pool_node pool_vector[MAX_POOL_SIZE];
2581 static int pool_size;
2582 static rtx pool_window_label;
2583 static int pool_window_last;
2585 /* ??? If we need a constant in HImode which is the truncated value of a
2586 constant we need in SImode, we could combine the two entries thus saving
2587 two bytes. Is this common enough to be worth the effort of implementing
2590 /* ??? This stuff should be done at the same time that we shorten branches.
2591 As it is now, we must assume that all branches are the maximum size, and
2592 this causes us to almost always output constant pools sooner than
2595 /* Add a constant to the pool and return its label. */
2598 add_constant (rtx x, enum machine_mode mode, rtx last_value)
2601 rtx lab, new, ref, newref;
2603 /* First see if we've already got it. */
2604 for (i = 0; i < pool_size; i++)
2606 if (x->code == pool_vector[i].value->code
2607 && mode == pool_vector[i].mode)
2609 if (x->code == CODE_LABEL)
2611 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
2614 if (rtx_equal_p (x, pool_vector[i].value))
2619 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
2621 new = gen_label_rtx ();
2622 LABEL_REFS (new) = pool_vector[i].label;
2623 pool_vector[i].label = lab = new;
2625 if (lab && pool_window_label)
2627 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2628 ref = pool_vector[pool_window_last].wend;
2629 LABEL_NEXTREF (newref) = ref;
2630 pool_vector[pool_window_last].wend = newref;
2633 pool_window_label = new;
2634 pool_window_last = i;
2640 /* Need a new one. */
2641 pool_vector[pool_size].value = x;
2642 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
2645 pool_vector[pool_size - 1].part_of_sequence_p = true;
2648 lab = gen_label_rtx ();
2649 pool_vector[pool_size].mode = mode;
2650 pool_vector[pool_size].label = lab;
2651 pool_vector[pool_size].wend = NULL_RTX;
2652 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
2653 if (lab && pool_window_label)
2655 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2656 ref = pool_vector[pool_window_last].wend;
2657 LABEL_NEXTREF (newref) = ref;
2658 pool_vector[pool_window_last].wend = newref;
2661 pool_window_label = lab;
2662 pool_window_last = pool_size;
2667 /* Output the literal table. */
2670 dump_table (rtx scan)
2677 /* Do two passes, first time dump out the HI sized constants. */
2679 for (i = 0; i < pool_size; i++)
2681 pool_node *p = &pool_vector[i];
2683 if (p->mode == HImode)
2687 scan = emit_insn_after (gen_align_2 (), scan);
2690 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2691 scan = emit_label_after (lab, scan);
2692 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
2694 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2696 lab = XEXP (ref, 0);
2697 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2700 else if (p->mode == DFmode)
2706 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
2708 rtx align_insn = NULL_RTX;
2710 scan = emit_label_after (gen_label_rtx (), scan);
2711 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2714 for (i = 0; i < pool_size; i++)
2716 pool_node *p = &pool_vector[i];
2724 if (align_insn && !p->part_of_sequence_p)
2726 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2727 emit_label_before (lab, align_insn);
2728 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
2730 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2732 lab = XEXP (ref, 0);
2733 emit_insn_before (gen_consttable_window_end (lab),
2736 delete_insn (align_insn);
2737 align_insn = NULL_RTX;
2742 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2743 scan = emit_label_after (lab, scan);
2744 scan = emit_insn_after (gen_consttable_4 (p->value,
2746 need_align = ! need_align;
2752 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2757 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2758 scan = emit_label_after (lab, scan);
2759 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2767 if (p->mode != HImode)
2769 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2771 lab = XEXP (ref, 0);
2772 scan = emit_insn_after (gen_consttable_window_end (lab),
2781 for (i = 0; i < pool_size; i++)
2783 pool_node *p = &pool_vector[i];
2794 scan = emit_label_after (gen_label_rtx (), scan);
2795 scan = emit_insn_after (gen_align_4 (), scan);
2797 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2798 scan = emit_label_after (lab, scan);
2799 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
2807 scan = emit_label_after (gen_label_rtx (), scan);
2808 scan = emit_insn_after (gen_align_4 (), scan);
2810 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2811 scan = emit_label_after (lab, scan);
2812 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2820 if (p->mode != HImode)
2822 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2824 lab = XEXP (ref, 0);
2825 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2830 scan = emit_insn_after (gen_consttable_end (), scan);
2831 scan = emit_barrier_after (scan);
2833 pool_window_label = NULL_RTX;
2834 pool_window_last = 0;
2837 /* Return nonzero if constant would be an ok source for a
2838 mov.w instead of a mov.l. */
2843 return (GET_CODE (src) == CONST_INT
2844 && INTVAL (src) >= -32768
2845 && INTVAL (src) <= 32767);
2848 /* Nonzero if the insn is a move instruction which needs to be fixed. */
2850 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2851 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
2852 need to fix it if the input value is CONST_OK_FOR_I08. */
2855 broken_move (rtx insn)
2857 if (GET_CODE (insn) == INSN)
2859 rtx pat = PATTERN (insn);
2860 if (GET_CODE (pat) == PARALLEL)
2861 pat = XVECEXP (pat, 0, 0);
2862 if (GET_CODE (pat) == SET
2863 /* We can load any 8 bit value if we don't care what the high
2864 order bits end up as. */
2865 && GET_MODE (SET_DEST (pat)) != QImode
2866 && (CONSTANT_P (SET_SRC (pat))
2867 /* Match mova_const. */
2868 || (GET_CODE (SET_SRC (pat)) == UNSPEC
2869 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
2870 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
2872 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
2873 && (fp_zero_operand (SET_SRC (pat))
2874 || fp_one_operand (SET_SRC (pat)))
2875 /* ??? If this is a -m4 or -m4-single compilation, in general
2876 we don't know the current setting of fpscr, so disable fldi.
2877 There is an exception if this was a register-register move
2878 before reload - and hence it was ascertained that we have
2879 single precision setting - and in a post-reload optimization
2880 we changed this to do a constant load. In that case
2881 we don't have an r0 clobber, hence we must use fldi. */
2882 && (! TARGET_SH4 || TARGET_FMOVD
2883 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
2885 && GET_CODE (SET_DEST (pat)) == REG
2886 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
2887 && (GET_CODE (SET_SRC (pat)) != CONST_INT
2888 || ! CONST_OK_FOR_I08 (INTVAL (SET_SRC (pat)))))
2898 return (GET_CODE (insn) == INSN
2899 && GET_CODE (PATTERN (insn)) == SET
2900 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
2901 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
2902 /* Don't match mova_const. */
2903 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn)), 0, 0)) == LABEL_REF);
2906 /* Find the last barrier from insn FROM which is close enough to hold the
2907 constant pool. If we can't find one, then create one near the end of
2911 find_barrier (int num_mova, rtx mova, rtx from)
2920 int leading_mova = num_mova;
2921 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
2925 /* For HImode: range is 510, add 4 because pc counts from address of
2926 second instruction after this one, subtract 2 for the jump instruction
2927 that we may need to emit before the table, subtract 2 for the instruction
2928 that fills the jump delay slot (in very rare cases, reorg will take an
2929 instruction from after the constant pool or will leave the delay slot
2930 empty). This gives 510.
2931 For SImode: range is 1020, add 4 because pc counts from address of
2932 second instruction after this one, subtract 2 in case pc is 2 byte
2933 aligned, subtract 2 for the jump instruction that we may need to emit
2934 before the table, subtract 2 for the instruction that fills the jump
2935 delay slot. This gives 1018. */
2937 /* The branch will always be shortened now that the reference address for
2938 forward branches is the successor address, thus we need no longer make
2939 adjustments to the [sh]i_limit for -O0. */
2944 while (from && count_si < si_limit && count_hi < hi_limit)
2946 int inc = get_attr_length (from);
2949 if (GET_CODE (from) == CODE_LABEL)
2952 new_align = 1 << label_to_alignment (from);
2953 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
2954 new_align = 1 << barrier_align (from);
2960 if (GET_CODE (from) == BARRIER)
2963 found_barrier = from;
2965 /* If we are at the end of the function, or in front of an alignment
2966 instruction, we need not insert an extra alignment. We prefer
2967 this kind of barrier. */
2968 if (barrier_align (from) > 2)
2969 good_barrier = from;
2972 if (broken_move (from))
2975 enum machine_mode mode;
2977 pat = PATTERN (from);
2978 if (GET_CODE (pat) == PARALLEL)
2979 pat = XVECEXP (pat, 0, 0);
2980 src = SET_SRC (pat);
2981 dst = SET_DEST (pat);
2982 mode = GET_MODE (dst);
2984 /* We must explicitly check the mode, because sometimes the
2985 front end will generate code to load unsigned constants into
2986 HImode targets without properly sign extending them. */
2988 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
2991 /* We put the short constants before the long constants, so
2992 we must count the length of short constants in the range
2993 for the long constants. */
2994 /* ??? This isn't optimal, but is easy to do. */
2999 /* We dump DF/DI constants before SF/SI ones, because
3000 the limit is the same, but the alignment requirements
3001 are higher. We may waste up to 4 additional bytes
3002 for alignment, and the DF/DI constant may have
3003 another SF/SI constant placed before it. */
3004 if (TARGET_SHCOMPACT
3006 && (mode == DFmode || mode == DImode))
3011 while (si_align > 2 && found_si + si_align - 2 > count_si)
3013 if (found_si > count_si)
3014 count_si = found_si;
3015 found_si += GET_MODE_SIZE (mode);
3017 si_limit -= GET_MODE_SIZE (mode);
3020 /* See the code in machine_dependent_reorg, which has a similar if
3021 statement that generates a new mova insn in many cases. */
3022 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
3032 barrier_before_mova = good_barrier ? good_barrier : found_barrier;
3034 if (found_si > count_si)
3035 count_si = found_si;
3037 else if (GET_CODE (from) == JUMP_INSN
3038 && (GET_CODE (PATTERN (from)) == ADDR_VEC
3039 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
3043 if (barrier_align (next_real_insn (from)) == align_jumps_log)
3045 /* We have just passed the barrier in front of the
3046 ADDR_DIFF_VEC, which is stored in found_barrier. Since
3047 the ADDR_DIFF_VEC is accessed as data, just like our pool
3048 constants, this is a good opportunity to accommodate what
3049 we have gathered so far.
3050 If we waited any longer, we could end up at a barrier in
3051 front of code, which gives worse cache usage for separated
3052 instruction / data caches. */
3053 good_barrier = found_barrier;
3058 rtx body = PATTERN (from);
3059 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
3062 /* For the SH1, we generate alignments even after jumps-around-jumps. */
3063 else if (GET_CODE (from) == JUMP_INSN
3065 && ! TARGET_SMALLCODE)
3071 if (new_align > si_align)
3073 si_limit -= (count_si - 1) & (new_align - si_align);
3074 si_align = new_align;
3076 count_si = (count_si + new_align - 1) & -new_align;
3081 if (new_align > hi_align)
3083 hi_limit -= (count_hi - 1) & (new_align - hi_align);
3084 hi_align = new_align;
3086 count_hi = (count_hi + new_align - 1) & -new_align;
3088 from = NEXT_INSN (from);
3095 /* Try as we might, the leading mova is out of range. Change
3096 it into a load (which will become a pcload) and retry. */
3097 SET_SRC (PATTERN (mova)) = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3098 INSN_CODE (mova) = -1;
3099 return find_barrier (0, 0, mova);
3103 /* Insert the constant pool table before the mova instruction,
3104 to prevent the mova label reference from going out of range. */
3106 good_barrier = found_barrier = barrier_before_mova;
3112 if (good_barrier && next_real_insn (found_barrier))
3113 found_barrier = good_barrier;
3117 /* We didn't find a barrier in time to dump our stuff,
3118 so we'll make one. */
3119 rtx label = gen_label_rtx ();
3121 /* If we exceeded the range, then we must back up over the last
3122 instruction we looked at. Otherwise, we just need to undo the
3123 NEXT_INSN at the end of the loop. */
3124 if (count_hi > hi_limit || count_si > si_limit)
3125 from = PREV_INSN (PREV_INSN (from));
3127 from = PREV_INSN (from);
3129 /* Walk back to be just before any jump or label.
3130 Putting it before a label reduces the number of times the branch
3131 around the constant pool table will be hit. Putting it before
3132 a jump makes it more likely that the bra delay slot will be
3134 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
3135 || GET_CODE (from) == CODE_LABEL)
3136 from = PREV_INSN (from);
3138 from = emit_jump_insn_after (gen_jump (label), from);
3139 JUMP_LABEL (from) = label;
3140 LABEL_NUSES (label) = 1;
3141 found_barrier = emit_barrier_after (from);
3142 emit_label_after (label, found_barrier);
3145 return found_barrier;
3148 /* If the instruction INSN is implemented by a special function, and we can
3149 positively find the register that is used to call the sfunc, and this
3150 register is not used anywhere else in this instruction - except as the
3151 destination of a set, return this register; else, return 0. */
3153 sfunc_uses_reg (rtx insn)
3156 rtx pattern, part, reg_part, reg;
3158 if (GET_CODE (insn) != INSN)
3160 pattern = PATTERN (insn);
3161 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
3164 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
3166 part = XVECEXP (pattern, 0, i);
3167 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
3172 reg = XEXP (reg_part, 0);
3173 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
3175 part = XVECEXP (pattern, 0, i);
3176 if (part == reg_part || GET_CODE (part) == CLOBBER)
3178 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
3179 && GET_CODE (SET_DEST (part)) == REG)
3180 ? SET_SRC (part) : part)))
3186 /* See if the only way in which INSN uses REG is by calling it, or by
3187 setting it while calling it. Set *SET to a SET rtx if the register
3191 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
3197 reg2 = sfunc_uses_reg (insn);
3198 if (reg2 && REGNO (reg2) == REGNO (reg))
3200 pattern = single_set (insn);
3202 && GET_CODE (SET_DEST (pattern)) == REG
3203 && REGNO (reg) == REGNO (SET_DEST (pattern)))
3207 if (GET_CODE (insn) != CALL_INSN)
3209 /* We don't use rtx_equal_p because we don't care if the mode is
3211 pattern = single_set (insn);
3213 && GET_CODE (SET_DEST (pattern)) == REG
3214 && REGNO (reg) == REGNO (SET_DEST (pattern)))
3220 par = PATTERN (insn);
3221 if (GET_CODE (par) == PARALLEL)
3222 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
3224 part = XVECEXP (par, 0, i);
3225 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
3228 return reg_mentioned_p (reg, SET_SRC (pattern));
3234 pattern = PATTERN (insn);
3236 if (GET_CODE (pattern) == PARALLEL)
3240 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
3241 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
3243 pattern = XVECEXP (pattern, 0, 0);
3246 if (GET_CODE (pattern) == SET)
3248 if (reg_mentioned_p (reg, SET_DEST (pattern)))
3250 /* We don't use rtx_equal_p, because we don't care if the
3251 mode is different. */
3252 if (GET_CODE (SET_DEST (pattern)) != REG
3253 || REGNO (reg) != REGNO (SET_DEST (pattern)))
3259 pattern = SET_SRC (pattern);
3262 if (GET_CODE (pattern) != CALL
3263 || GET_CODE (XEXP (pattern, 0)) != MEM
3264 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
3270 /* Given a X, a pattern of an insn or a part of it, return a mask of used
3271 general registers. Bits 0..15 mean that the respective registers
3272 are used as inputs in the instruction. Bits 16..31 mean that the
3273 registers 0..15, respectively, are used as outputs, or are clobbered.
3274 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
3276 regs_used (rtx x, int is_dest)
3284 code = GET_CODE (x);
3289 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3290 << (REGNO (x) + is_dest));
3294 rtx y = SUBREG_REG (x);
3296 if (GET_CODE (y) != REG)
3299 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3301 subreg_regno_offset (REGNO (y),
3304 GET_MODE (x)) + is_dest));
3308 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
3310 /* If there was a return value, it must have been indicated with USE. */
3325 fmt = GET_RTX_FORMAT (code);
3327 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3332 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3333 used |= regs_used (XVECEXP (x, i, j), is_dest);
3335 else if (fmt[i] == 'e')
3336 used |= regs_used (XEXP (x, i), is_dest);
3341 /* Create an instruction that prevents redirection of a conditional branch
3342 to the destination of the JUMP with address ADDR.
3343 If the branch needs to be implemented as an indirect jump, try to find
3344 a scratch register for it.
3345 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
3346 If any preceding insn that doesn't fit into a delay slot is good enough,
3347 pass 1. Pass 2 if a definite blocking insn is needed.
3348 -1 is used internally to avoid deep recursion.
3349 If a blocking instruction is made or recognized, return it. */
3352 gen_block_redirect (rtx jump, int addr, int need_block)
3355 rtx prev = prev_nonnote_insn (jump);
3358 /* First, check if we already have an instruction that satisfies our need. */
3359 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
3361 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
3363 if (GET_CODE (PATTERN (prev)) == USE
3364 || GET_CODE (PATTERN (prev)) == CLOBBER
3365 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3367 else if ((need_block &= ~1) < 0)
3369 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
3372 if (GET_CODE (PATTERN (jump)) == RETURN)
3376 /* Reorg even does nasty things with return insns that cause branches
3377 to go out of range - see find_end_label and callers. */
3378 return emit_insn_before (gen_block_branch_redirect (GEN_INT (0)) , jump);
3380 /* We can't use JUMP_LABEL here because it might be undefined
3381 when not optimizing. */
3382 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
3383 /* If the branch is out of range, try to find a scratch register for it. */
3385 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3389 /* Don't look for the stack pointer as a scratch register,
3390 it would cause trouble if an interrupt occurred. */
3391 unsigned try = 0x7fff, used;
3392 int jump_left = flag_expensive_optimizations + 1;
3394 /* It is likely that the most recent eligible instruction is wanted for
3395 the delay slot. Therefore, find out which registers it uses, and
3396 try to avoid using them. */
3398 for (scan = jump; (scan = PREV_INSN (scan)); )
3402 if (INSN_DELETED_P (scan))
3404 code = GET_CODE (scan);
3405 if (code == CODE_LABEL || code == JUMP_INSN)
3408 && GET_CODE (PATTERN (scan)) != USE
3409 && GET_CODE (PATTERN (scan)) != CLOBBER
3410 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
3412 try &= ~regs_used (PATTERN (scan), 0);
3416 for (used = dead = 0, scan = JUMP_LABEL (jump);
3417 (scan = NEXT_INSN (scan)); )
3421 if (INSN_DELETED_P (scan))
3423 code = GET_CODE (scan);
3424 if (GET_RTX_CLASS (code) == 'i')
3426 used |= regs_used (PATTERN (scan), 0);
3427 if (code == CALL_INSN)
3428 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
3429 dead |= (used >> 16) & ~used;
3435 if (code == JUMP_INSN)
3437 if (jump_left-- && simplejump_p (scan))
3438 scan = JUMP_LABEL (scan);
3444 /* Mask out the stack pointer again, in case it was
3445 the only 'free' register we have found. */
3448 /* If the immediate destination is still in range, check for possible
3449 threading with a jump beyond the delay slot insn.
3450 Don't check if we are called recursively; the jump has been or will be
3451 checked in a different invocation then. */
3453 else if (optimize && need_block >= 0)
3455 rtx next = next_active_insn (next_active_insn (dest));
3456 if (next && GET_CODE (next) == JUMP_INSN
3457 && GET_CODE (PATTERN (next)) == SET
3458 && recog_memoized (next) == CODE_FOR_jump_compact)
3460 dest = JUMP_LABEL (next);
3462 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3464 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
3470 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
3472 /* It would be nice if we could convert the jump into an indirect
3473 jump / far branch right now, and thus exposing all constituent
3474 instructions to further optimization. However, reorg uses
3475 simplejump_p to determine if there is an unconditional jump where
3476 it should try to schedule instructions from the target of the
3477 branch; simplejump_p fails for indirect jumps even if they have
3479 rtx insn = emit_insn_before (gen_indirect_jump_scratch
3480 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
3482 /* ??? We would like this to have the scope of the jump, but that
3483 scope will change when a delay slot insn of an inner scope is added.
3484 Hence, after delay slot scheduling, we'll have to expect
3485 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
3488 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
3489 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
3492 else if (need_block)
3493 /* We can't use JUMP_LABEL here because it might be undefined
3494 when not optimizing. */
3495 return emit_insn_before (gen_block_branch_redirect
3496 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
3501 #define CONDJUMP_MIN -252
3502 #define CONDJUMP_MAX 262
3505 /* A label (to be placed) in front of the jump
3506 that jumps to our ultimate destination. */
3508 /* Where we are going to insert it if we cannot move the jump any farther,
3509 or the jump itself if we have picked up an existing jump. */
3511 /* The ultimate destination. */
3513 struct far_branch *prev;
3514 /* If the branch has already been created, its address;
3515 else the address of its first prospective user. */
3519 static void gen_far_branch (struct far_branch *);
3520 enum mdep_reorg_phase_e mdep_reorg_phase;
3522 gen_far_branch (struct far_branch *bp)
3524 rtx insn = bp->insert_place;
3526 rtx label = gen_label_rtx ();
3528 emit_label_after (label, insn);
3531 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
3532 LABEL_NUSES (bp->far_label)++;
3535 jump = emit_jump_insn_after (gen_return (), insn);
3536 /* Emit a barrier so that reorg knows that any following instructions
3537 are not reachable via a fall-through path.
3538 But don't do this when not optimizing, since we wouldn't suppress the
3539 alignment for the barrier then, and could end up with out-of-range
3540 pc-relative loads. */
3542 emit_barrier_after (jump);
3543 emit_label_after (bp->near_label, insn);
3544 JUMP_LABEL (jump) = bp->far_label;
3545 if (! invert_jump (insn, label, 1))
3547 /* If we are branching around a jump (rather than a return), prevent
3548 reorg from using an insn from the jump target as the delay slot insn -
3549 when reorg did this, it pessimized code (we rather hide the delay slot)
3550 and it could cause branches to go out of range. */
3553 (gen_stuff_delay_slot
3554 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
3555 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
3557 /* Prevent reorg from undoing our splits. */
3558 gen_block_redirect (jump, bp->address += 2, 2);
3561 /* Fix up ADDR_DIFF_VECs. */
3563 fixup_addr_diff_vecs (rtx first)
3567 for (insn = first; insn; insn = NEXT_INSN (insn))
3569 rtx vec_lab, pat, prev, prevpat, x, braf_label;
3571 if (GET_CODE (insn) != JUMP_INSN
3572 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
3574 pat = PATTERN (insn);
3575 vec_lab = XEXP (XEXP (pat, 0), 0);
3577 /* Search the matching casesi_jump_2. */
3578 for (prev = vec_lab; ; prev = PREV_INSN (prev))
3580 if (GET_CODE (prev) != JUMP_INSN)
3582 prevpat = PATTERN (prev);
3583 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
3585 x = XVECEXP (prevpat, 0, 1);
3586 if (GET_CODE (x) != USE)
3589 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
3593 /* Emit the reference label of the braf where it belongs, right after
3594 the casesi_jump_2 (i.e. braf). */
3595 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
3596 emit_label_after (braf_label, prev);
3598 /* Fix up the ADDR_DIF_VEC to be relative
3599 to the reference address of the braf. */
3600 XEXP (XEXP (pat, 0), 0) = braf_label;
3604 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3605 a barrier. Return the base 2 logarithm of the desired alignment. */
3607 barrier_align (rtx barrier_or_label)
3609 rtx next = next_real_insn (barrier_or_label), pat, prev;
3610 int slot, credit, jump_to_next = 0;
3615 pat = PATTERN (next);
3617 if (GET_CODE (pat) == ADDR_DIFF_VEC)
3620 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
3621 /* This is a barrier in front of a constant table. */
3624 prev = prev_real_insn (barrier_or_label);
3625 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
3627 pat = PATTERN (prev);
3628 /* If this is a very small table, we want to keep the alignment after
3629 the table to the minimum for proper code alignment. */
3630 return ((TARGET_SMALLCODE
3631 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
3632 <= (unsigned)1 << (CACHE_LOG - 2)))
3633 ? 1 << TARGET_SHMEDIA : align_jumps_log);
3636 if (TARGET_SMALLCODE)
3639 if (! TARGET_SH2 || ! optimize)
3640 return align_jumps_log;
3642 /* When fixing up pcloads, a constant table might be inserted just before
3643 the basic block that ends with the barrier. Thus, we can't trust the
3644 instruction lengths before that. */
3645 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
3647 /* Check if there is an immediately preceding branch to the insn beyond
3648 the barrier. We must weight the cost of discarding useful information
3649 from the current cache line when executing this branch and there is
3650 an alignment, against that of fetching unneeded insn in front of the
3651 branch target when there is no alignment. */
3653 /* There are two delay_slot cases to consider. One is the simple case
3654 where the preceding branch is to the insn beyond the barrier (simple
3655 delay slot filling), and the other is where the preceding branch has
3656 a delay slot that is a duplicate of the insn after the barrier
3657 (fill_eager_delay_slots) and the branch is to the insn after the insn
3658 after the barrier. */
3660 /* PREV is presumed to be the JUMP_INSN for the barrier under
3661 investigation. Skip to the insn before it. */
3662 prev = prev_real_insn (prev);
3664 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
3665 credit >= 0 && prev && GET_CODE (prev) == INSN;
3666 prev = prev_real_insn (prev))
3669 if (GET_CODE (PATTERN (prev)) == USE
3670 || GET_CODE (PATTERN (prev)) == CLOBBER)
3672 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
3674 prev = XVECEXP (PATTERN (prev), 0, 1);
3675 if (INSN_UID (prev) == INSN_UID (next))
3677 /* Delay slot was filled with insn at jump target. */
3684 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3686 credit -= get_attr_length (prev);
3689 && GET_CODE (prev) == JUMP_INSN
3690 && JUMP_LABEL (prev))
3694 || next_real_insn (JUMP_LABEL (prev)) == next
3695 /* If relax_delay_slots() decides NEXT was redundant
3696 with some previous instruction, it will have
3697 redirected PREV's jump to the following insn. */
3698 || JUMP_LABEL (prev) == next_nonnote_insn (next)
3699 /* There is no upper bound on redundant instructions
3700 that might have been skipped, but we must not put an
3701 alignment where none had been before. */
3702 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
3704 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
3705 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
3706 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
3708 rtx pat = PATTERN (prev);
3709 if (GET_CODE (pat) == PARALLEL)
3710 pat = XVECEXP (pat, 0, 0);
3711 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
3717 return align_jumps_log;
3720 /* If we are inside a phony loop, almost any kind of label can turn up as the
3721 first one in the loop. Aligning a braf label causes incorrect switch
3722 destination addresses; we can detect braf labels because they are
3723 followed by a BARRIER.
3724 Applying loop alignment to small constant or switch tables is a waste
3725 of space, so we suppress this too. */
3727 sh_loop_align (rtx label)
3732 next = next_nonnote_insn (next);
3733 while (next && GET_CODE (next) == CODE_LABEL);
3737 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
3738 || recog_memoized (next) == CODE_FOR_consttable_2)
3741 return align_loops_log;
3744 /* Do a final pass over the function, just before delayed branch
3750 rtx first, insn, mova = NULL_RTX;
3752 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
3753 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
3755 first = get_insns ();
3757 /* We must split call insns before introducing `mova's. If we're
3758 optimizing, they'll have already been split. Otherwise, make
3759 sure we don't split them too late. */
3761 split_all_insns_noflow ();
3766 /* If relaxing, generate pseudo-ops to associate function calls with
3767 the symbols they call. It does no harm to not generate these
3768 pseudo-ops. However, when we can generate them, it enables to
3769 linker to potentially relax the jsr to a bsr, and eliminate the
3770 register load and, possibly, the constant pool entry. */
3772 mdep_reorg_phase = SH_INSERT_USES_LABELS;
3775 /* Remove all REG_LABEL notes. We want to use them for our own
3776 purposes. This works because none of the remaining passes
3777 need to look at them.
3779 ??? But it may break in the future. We should use a machine
3780 dependent REG_NOTE, or some other approach entirely. */
3781 for (insn = first; insn; insn = NEXT_INSN (insn))
3787 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
3788 remove_note (insn, note);
3792 for (insn = first; insn; insn = NEXT_INSN (insn))
3794 rtx pattern, reg, link, set, scan, dies, label;
3795 int rescan = 0, foundinsn = 0;
3797 if (GET_CODE (insn) == CALL_INSN)
3799 pattern = PATTERN (insn);
3801 if (GET_CODE (pattern) == PARALLEL)
3802 pattern = XVECEXP (pattern, 0, 0);
3803 if (GET_CODE (pattern) == SET)
3804 pattern = SET_SRC (pattern);
3806 if (GET_CODE (pattern) != CALL
3807 || GET_CODE (XEXP (pattern, 0)) != MEM)
3810 reg = XEXP (XEXP (pattern, 0), 0);
3814 reg = sfunc_uses_reg (insn);
3819 if (GET_CODE (reg) != REG)
3822 /* This is a function call via REG. If the only uses of REG
3823 between the time that it is set and the time that it dies
3824 are in function calls, then we can associate all the
3825 function calls with the setting of REG. */
3827 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
3829 if (REG_NOTE_KIND (link) != 0)
3831 set = single_set (XEXP (link, 0));
3832 if (set && rtx_equal_p (reg, SET_DEST (set)))
3834 link = XEXP (link, 0);
3841 /* ??? Sometimes global register allocation will have
3842 deleted the insn pointed to by LOG_LINKS. Try
3843 scanning backward to find where the register is set. */
3844 for (scan = PREV_INSN (insn);
3845 scan && GET_CODE (scan) != CODE_LABEL;
3846 scan = PREV_INSN (scan))
3848 if (! INSN_P (scan))
3851 if (! reg_mentioned_p (reg, scan))
3854 if (noncall_uses_reg (reg, scan, &set))
3868 /* The register is set at LINK. */
3870 /* We can only optimize the function call if the register is
3871 being set to a symbol. In theory, we could sometimes
3872 optimize calls to a constant location, but the assembler
3873 and linker do not support that at present. */
3874 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
3875 && GET_CODE (SET_SRC (set)) != LABEL_REF)
3878 /* Scan forward from LINK to the place where REG dies, and
3879 make sure that the only insns which use REG are
3880 themselves function calls. */
3882 /* ??? This doesn't work for call targets that were allocated
3883 by reload, since there may not be a REG_DEAD note for the
3887 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
3891 /* Don't try to trace forward past a CODE_LABEL if we haven't
3892 seen INSN yet. Ordinarily, we will only find the setting insn
3893 in LOG_LINKS if it is in the same basic block. However,
3894 cross-jumping can insert code labels in between the load and
3895 the call, and can result in situations where a single call
3896 insn may have two targets depending on where we came from. */
3898 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
3901 if (! INSN_P (scan))
3904 /* Don't try to trace forward past a JUMP. To optimize
3905 safely, we would have to check that all the
3906 instructions at the jump destination did not use REG. */
3908 if (GET_CODE (scan) == JUMP_INSN)
3911 if (! reg_mentioned_p (reg, scan))
3914 if (noncall_uses_reg (reg, scan, &scanset))
3921 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
3923 /* There is a function call to this register other
3924 than the one we are checking. If we optimize
3925 this call, we need to rescan again below. */
3929 /* ??? We shouldn't have to worry about SCANSET here.
3930 We should just be able to check for a REG_DEAD note
3931 on a function call. However, the REG_DEAD notes are
3932 apparently not dependable around libcalls; c-torture
3933 execute/920501-2 is a test case. If SCANSET is set,
3934 then this insn sets the register, so it must have
3935 died earlier. Unfortunately, this will only handle
3936 the cases in which the register is, in fact, set in a
3939 /* ??? We shouldn't have to use FOUNDINSN here.
3940 However, the LOG_LINKS fields are apparently not
3941 entirely reliable around libcalls;
3942 newlib/libm/math/e_pow.c is a test case. Sometimes
3943 an insn will appear in LOG_LINKS even though it is
3944 not the most recent insn which sets the register. */
3948 || find_reg_note (scan, REG_DEAD, reg)))
3957 /* Either there was a branch, or some insn used REG
3958 other than as a function call address. */
3962 /* Create a code label, and put it in a REG_LABEL note on
3963 the insn which sets the register, and on each call insn
3964 which uses the register. In final_prescan_insn we look
3965 for the REG_LABEL notes, and output the appropriate label
3968 label = gen_label_rtx ();
3969 REG_NOTES (link) = gen_rtx_INSN_LIST (REG_LABEL, label,
3971 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, label,
3980 scan = NEXT_INSN (scan);
3982 && ((GET_CODE (scan) == CALL_INSN
3983 && reg_mentioned_p (reg, scan))
3984 || ((reg2 = sfunc_uses_reg (scan))
3985 && REGNO (reg2) == REGNO (reg))))
3987 = gen_rtx_INSN_LIST (REG_LABEL, label, REG_NOTES (scan));
3989 while (scan != dies);
3995 fixup_addr_diff_vecs (first);
3999 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
4000 shorten_branches (first);
4002 /* Scan the function looking for move instructions which have to be
4003 changed to pc-relative loads and insert the literal tables. */
4005 mdep_reorg_phase = SH_FIXUP_PCLOAD;
4006 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
4013 else if (GET_CODE (insn) == JUMP_INSN
4014 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
4022 /* Some code might have been inserted between the mova and
4023 its ADDR_DIFF_VEC. Check if the mova is still in range. */
4024 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
4025 total += get_attr_length (scan);
4027 /* range of mova is 1020, add 4 because pc counts from address of
4028 second instruction after this one, subtract 2 in case pc is 2
4029 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
4030 cancels out with alignment effects of the mova itself. */
4033 /* Change the mova into a load, and restart scanning
4034 there. broken_move will then return true for mova. */
4035 SET_SRC (PATTERN (mova))
4036 = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4037 INSN_CODE (mova) = -1;
4041 if (broken_move (insn))
4044 /* Scan ahead looking for a barrier to stick the constant table
4046 rtx barrier = find_barrier (num_mova, mova, insn);
4047 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
4049 if (num_mova && ! mova_p (mova))
4051 /* find_barrier had to change the first mova into a
4052 pcload; thus, we have to start with this new pcload. */
4056 /* Now find all the moves between the points and modify them. */
4057 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
4059 if (GET_CODE (scan) == CODE_LABEL)
4061 if (broken_move (scan))
4063 rtx *patp = &PATTERN (scan), pat = *patp;
4067 enum machine_mode mode;
4069 if (GET_CODE (pat) == PARALLEL)
4070 patp = &XVECEXP (pat, 0, 0), pat = *patp;
4071 src = SET_SRC (pat);
4072 dst = SET_DEST (pat);
4073 mode = GET_MODE (dst);
4075 if (mode == SImode && hi_const (src)
4076 && REGNO (dst) != FPUL_REG)
4081 while (GET_CODE (dst) == SUBREG)
4083 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
4084 GET_MODE (SUBREG_REG (dst)),
4087 dst = SUBREG_REG (dst);
4089 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
4092 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
4094 /* This must be an insn that clobbers r0. */
4095 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
4096 XVECLEN (PATTERN (scan), 0)
4098 rtx clobber = *clobberp;
4100 if (GET_CODE (clobber) != CLOBBER
4101 || ! rtx_equal_p (XEXP (clobber, 0), r0_rtx))
4105 && reg_set_between_p (r0_rtx, last_float_move, scan))
4109 && GET_MODE_SIZE (mode) != 4
4110 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
4112 lab = add_constant (src, mode, last_float);
4114 emit_insn_before (gen_mova (lab), scan);
4117 /* There will be a REG_UNUSED note for r0 on
4118 LAST_FLOAT_MOVE; we have to change it to REG_INC,
4119 lest reorg:mark_target_live_regs will not
4120 consider r0 to be used, and we end up with delay
4121 slot insn in front of SCAN that clobbers r0. */
4123 = find_regno_note (last_float_move, REG_UNUSED, 0);
4125 /* If we are not optimizing, then there may not be
4128 PUT_MODE (note, REG_INC);
4130 *last_float_addr = r0_inc_rtx;
4132 last_float_move = scan;
4134 newsrc = gen_rtx (MEM, mode,
4135 (((TARGET_SH4 && ! TARGET_FMOVD)
4136 || REGNO (dst) == FPUL_REG)
4139 last_float_addr = &XEXP (newsrc, 0);
4141 /* Remove the clobber of r0. */
4142 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
4143 gen_rtx_SCRATCH (Pmode));
4144 RTX_UNCHANGING_P (newsrc) = 1;
4146 /* This is a mova needing a label. Create it. */
4147 else if (GET_CODE (src) == UNSPEC
4148 && XINT (src, 1) == UNSPEC_MOVA
4149 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
4151 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
4152 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
4153 newsrc = gen_rtx_UNSPEC (SImode,
4154 gen_rtvec (1, newsrc),
4159 lab = add_constant (src, mode, 0);
4160 newsrc = gen_rtx_MEM (mode,
4161 gen_rtx_LABEL_REF (VOIDmode, lab));
4162 RTX_UNCHANGING_P (newsrc) = 1;
4164 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
4165 INSN_CODE (scan) = -1;
4168 dump_table (barrier);
4173 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
4174 INSN_ADDRESSES_FREE ();
4175 split_branches (first);
4177 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
4178 also has an effect on the register that holds the address of the sfunc.
4179 Insert an extra dummy insn in front of each sfunc that pretends to
4180 use this register. */
4181 if (flag_delayed_branch)
4183 for (insn = first; insn; insn = NEXT_INSN (insn))
4185 rtx reg = sfunc_uses_reg (insn);
4189 emit_insn_before (gen_use_sfunc_addr (reg), insn);
4193 /* fpscr is not actually a user variable, but we pretend it is for the
4194 sake of the previous optimization passes, since we want it handled like
4195 one. However, we don't have any debugging information for it, so turn
4196 it into a non-user variable now. */
4198 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
4200 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
4204 get_dest_uid (rtx label, int max_uid)
4206 rtx dest = next_real_insn (label);
4209 /* This can happen for an undefined label. */
4211 dest_uid = INSN_UID (dest);
4212 /* If this is a newly created branch redirection blocking instruction,
4213 we cannot index the branch_uid or insn_addresses arrays with its
4214 uid. But then, we won't need to, because the actual destination is
4215 the following branch. */
4216 while (dest_uid >= max_uid)
4218 dest = NEXT_INSN (dest);
4219 dest_uid = INSN_UID (dest);
4221 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
4226 /* Split condbranches that are out of range. Also add clobbers for
4227 scratch registers that are needed in far jumps.
4228 We do this before delay slot scheduling, so that it can take our
4229 newly created instructions into account. It also allows us to
4230 find branches with common targets more easily. */
4233 split_branches (rtx first)
4236 struct far_branch **uid_branch, *far_branch_list = 0;
4237 int max_uid = get_max_uid ();
4239 /* Find out which branches are out of range. */
4240 shorten_branches (first);
4242 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
4243 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
4245 for (insn = first; insn; insn = NEXT_INSN (insn))
4246 if (! INSN_P (insn))
4248 else if (INSN_DELETED_P (insn))
4250 /* Shorten_branches would split this instruction again,
4251 so transform it into a note. */
4252 PUT_CODE (insn, NOTE);
4253 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4254 NOTE_SOURCE_FILE (insn) = 0;
4256 else if (GET_CODE (insn) == JUMP_INSN
4257 /* Don't mess with ADDR_DIFF_VEC */
4258 && (GET_CODE (PATTERN (insn)) == SET
4259 || GET_CODE (PATTERN (insn)) == RETURN))
4261 enum attr_type type = get_attr_type (insn);
4262 if (type == TYPE_CBRANCH)
4266 if (get_attr_length (insn) > 4)
4268 rtx src = SET_SRC (PATTERN (insn));
4269 rtx olabel = XEXP (XEXP (src, 1), 0);
4270 int addr = INSN_ADDRESSES (INSN_UID (insn));
4272 int dest_uid = get_dest_uid (olabel, max_uid);
4273 struct far_branch *bp = uid_branch[dest_uid];
4275 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
4276 the label if the LABEL_NUSES count drops to zero. There is
4277 always a jump_optimize pass that sets these values, but it
4278 proceeds to delete unreferenced code, and then if not
4279 optimizing, to un-delete the deleted instructions, thus
4280 leaving labels with too low uses counts. */
4283 JUMP_LABEL (insn) = olabel;
4284 LABEL_NUSES (olabel)++;
4288 bp = (struct far_branch *) alloca (sizeof *bp);
4289 uid_branch[dest_uid] = bp;
4290 bp->prev = far_branch_list;
4291 far_branch_list = bp;
4293 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
4294 LABEL_NUSES (bp->far_label)++;
4298 label = bp->near_label;
4299 if (! label && bp->address - addr >= CONDJUMP_MIN)
4301 rtx block = bp->insert_place;
4303 if (GET_CODE (PATTERN (block)) == RETURN)
4304 block = PREV_INSN (block);
4306 block = gen_block_redirect (block,
4308 label = emit_label_after (gen_label_rtx (),
4310 bp->near_label = label;
4312 else if (label && ! NEXT_INSN (label))
4314 if (addr + 2 - bp->address <= CONDJUMP_MAX)
4315 bp->insert_place = insn;
4317 gen_far_branch (bp);
4321 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
4323 bp->near_label = label = gen_label_rtx ();
4324 bp->insert_place = insn;
4327 if (! redirect_jump (insn, label, 1))
4332 /* get_attr_length (insn) == 2 */
4333 /* Check if we have a pattern where reorg wants to redirect
4334 the branch to a label from an unconditional branch that
4336 /* We can't use JUMP_LABEL here because it might be undefined
4337 when not optimizing. */
4338 /* A syntax error might cause beyond to be NULL_RTX. */
4340 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
4344 && (GET_CODE (beyond) == JUMP_INSN
4345 || ((beyond = next_active_insn (beyond))
4346 && GET_CODE (beyond) == JUMP_INSN))
4347 && GET_CODE (PATTERN (beyond)) == SET
4348 && recog_memoized (beyond) == CODE_FOR_jump_compact
4350 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
4351 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4353 gen_block_redirect (beyond,
4354 INSN_ADDRESSES (INSN_UID (beyond)), 1);
4357 next = next_active_insn (insn);
4359 if ((GET_CODE (next) == JUMP_INSN
4360 || GET_CODE (next = next_active_insn (next)) == JUMP_INSN)
4361 && GET_CODE (PATTERN (next)) == SET
4362 && recog_memoized (next) == CODE_FOR_jump_compact
4364 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
4365 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4367 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
4369 else if (type == TYPE_JUMP || type == TYPE_RETURN)
4371 int addr = INSN_ADDRESSES (INSN_UID (insn));
4374 struct far_branch *bp;
4376 if (type == TYPE_JUMP)
4378 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
4379 dest_uid = get_dest_uid (far_label, max_uid);
4382 /* Parse errors can lead to labels outside
4384 if (! NEXT_INSN (far_label))
4389 JUMP_LABEL (insn) = far_label;
4390 LABEL_NUSES (far_label)++;
4392 redirect_jump (insn, NULL_RTX, 1);
4396 bp = uid_branch[dest_uid];
4399 bp = (struct far_branch *) alloca (sizeof *bp);
4400 uid_branch[dest_uid] = bp;
4401 bp->prev = far_branch_list;
4402 far_branch_list = bp;
4404 bp->far_label = far_label;
4406 LABEL_NUSES (far_label)++;
4408 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
4409 if (addr - bp->address <= CONDJUMP_MAX)
4410 emit_label_after (bp->near_label, PREV_INSN (insn));
4413 gen_far_branch (bp);
4419 bp->insert_place = insn;
4421 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
4423 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
4426 /* Generate all pending far branches,
4427 and free our references to the far labels. */
4428 while (far_branch_list)
4430 if (far_branch_list->near_label
4431 && ! NEXT_INSN (far_branch_list->near_label))
4432 gen_far_branch (far_branch_list);
4434 && far_branch_list->far_label
4435 && ! --LABEL_NUSES (far_branch_list->far_label))
4436 delete_insn (far_branch_list->far_label);
4437 far_branch_list = far_branch_list->prev;
4440 /* Instruction length information is no longer valid due to the new
4441 instructions that have been generated. */
4442 init_insn_lengths ();
4445 /* Dump out instruction addresses, which is useful for debugging the
4446 constant pool table stuff.
4448 If relaxing, output the label and pseudo-ops used to link together
4449 calls and the instruction which set the registers. */
4451 /* ??? The addresses printed by this routine for insns are nonsense for
4452 insns which are inside of a sequence where none of the inner insns have
4453 variable length. This is because the second pass of shorten_branches
4454 does not bother to update them. */
4457 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
4458 int noperands ATTRIBUTE_UNUSED)
4460 if (TARGET_DUMPISIZE)
4461 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
4467 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
4472 pattern = PATTERN (insn);
4473 if (GET_CODE (pattern) == PARALLEL)
4474 pattern = XVECEXP (pattern, 0, 0);
4475 if (GET_CODE (pattern) == CALL
4476 || (GET_CODE (pattern) == SET
4477 && (GET_CODE (SET_SRC (pattern)) == CALL
4478 || get_attr_type (insn) == TYPE_SFUNC)))
4479 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
4480 CODE_LABEL_NUMBER (XEXP (note, 0)));
4481 else if (GET_CODE (pattern) == SET)
4482 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4483 CODE_LABEL_NUMBER (XEXP (note, 0)));
4490 /* Dump out any constants accumulated in the final pass. These will
4494 output_jump_label_table (void)
4500 fprintf (asm_out_file, "\t.align 2\n");
4501 for (i = 0; i < pool_size; i++)
4503 pool_node *p = &pool_vector[i];
4505 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4506 CODE_LABEL_NUMBER (p->label));
4507 output_asm_insn (".long %O0", &p->value);
4515 /* A full frame looks like:
4519 [ if current_function_anonymous_args
4532 local-0 <- fp points here. */
4534 /* Number of bytes pushed for anonymous args, used to pass information
4535 between expand_prologue and expand_epilogue. */
4537 static int extra_push;
4539 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
4540 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
4541 for an epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET
4542 of all the registers that are about to be restored, and hence dead. */
4545 output_stack_adjust (int size, rtx reg, int epilogue_p,
4546 HARD_REG_SET *live_regs_mask)
4548 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
4551 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4556 if (CONST_OK_FOR_ADD (size))
4557 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
4558 /* Try to do it with two partial adjustments; however, we must make
4559 sure that the stack is properly aligned at all times, in case
4560 an interrupt occurs between the two partial adjustments. */
4561 else if (CONST_OK_FOR_ADD (size / 2 & -align)
4562 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
4564 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
4565 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
4571 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
4574 /* If TEMP is invalid, we could temporarily save a general
4575 register to MACL. However, there is currently no need
4576 to handle this case, so just abort when we see it. */
4577 if (current_function_interrupt
4578 || ! call_used_regs[temp] || fixed_regs[temp])
4580 if (temp < 0 && ! current_function_interrupt)
4583 COPY_HARD_REG_SET (temps, call_used_reg_set);
4584 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
4587 for (i = 0; i < HARD_REGNO_NREGS (FIRST_RET_REG, DImode); i++)
4588 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
4589 if (current_function_calls_eh_return)
4591 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
4592 for (i = 0; i <= 3; i++)
4593 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
4598 for (i = FIRST_PARM_REG;
4599 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
4600 CLEAR_HARD_REG_BIT (temps, i);
4601 if (current_function_needs_context)
4602 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
4604 temp = scavenge_reg (&temps);
4606 if (temp < 0 && live_regs_mask)
4607 temp = scavenge_reg (live_regs_mask);
4610 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
4612 /* If SIZE is negative, subtract the positive value.
4613 This sometimes allows a constant pool entry to be shared
4614 between prologue and epilogue code. */
4617 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
4618 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
4622 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
4623 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
4627 = (gen_rtx_EXPR_LIST
4628 (REG_FRAME_RELATED_EXPR,
4629 gen_rtx_SET (VOIDmode, reg,
4630 gen_rtx_PLUS (SImode, reg, GEN_INT (size))),
4640 RTX_FRAME_RELATED_P (x) = 1;
4644 /* Output RTL to push register RN onto the stack. */
4651 x = gen_push_fpul ();
4652 else if (rn == FPSCR_REG)
4653 x = gen_push_fpscr ();
4654 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4655 && FP_OR_XD_REGISTER_P (rn))
4657 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4659 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
4661 else if (TARGET_SH2E && FP_REGISTER_P (rn))
4662 x = gen_push_e (gen_rtx_REG (SFmode, rn));
4664 x = gen_push (gen_rtx_REG (SImode, rn));
4668 = gen_rtx_EXPR_LIST (REG_INC,
4669 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4673 /* Output RTL to pop register RN from the stack. */
4680 x = gen_pop_fpul ();
4681 else if (rn == FPSCR_REG)
4682 x = gen_pop_fpscr ();
4683 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4684 && FP_OR_XD_REGISTER_P (rn))
4686 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4688 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
4690 else if (TARGET_SH2E && FP_REGISTER_P (rn))
4691 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
4693 x = gen_pop (gen_rtx_REG (SImode, rn));
4697 = gen_rtx_EXPR_LIST (REG_INC,
4698 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4701 /* Generate code to push the regs specified in the mask. */
4704 push_regs (HARD_REG_SET *mask, int interrupt_handler)
4709 /* Push PR last; this gives better latencies after the prologue, and
4710 candidates for the return delay slot when there are no general
4711 registers pushed. */
4712 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4714 /* If this is an interrupt handler, and the SZ bit varies,
4715 and we have to push any floating point register, we need
4716 to switch to the correct precision first. */
4717 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
4718 && hard_regs_intersect_p (mask, ®_class_contents[DF_REGS]))
4720 HARD_REG_SET unsaved;
4723 COMPL_HARD_REG_SET(unsaved, *mask);
4724 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
4728 && (i != FPSCR_REG || ! skip_fpscr)
4729 && TEST_HARD_REG_BIT (*mask, i))
4732 if (TEST_HARD_REG_BIT (*mask, PR_REG))
4736 /* Calculate how much extra space is needed to save all callee-saved
4738 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4741 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
4744 int stack_space = 0;
4745 int interrupt_handler = sh_cfun_interrupt_handler_p ();
4747 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
4748 if ((! call_used_regs[reg] || interrupt_handler)
4749 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
4750 /* Leave space to save this target register on the stack,
4751 in case target register allocation wants to use it. */
4752 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4756 /* Decide whether we should reserve space for callee-save target registers,
4757 in case target register allocation wants to use them. REGS_SAVED is
4758 the space, in bytes, that is already required for register saves.
4759 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4762 shmedia_reserve_space_for_target_registers_p (int regs_saved,
4763 HARD_REG_SET *live_regs_mask)
4767 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
4770 /* Decide how much space to reserve for callee-save target registers
4771 in case target register allocation wants to use them.
4772 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4775 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
4777 if (shmedia_space_reserved_for_target_registers)
4778 return shmedia_target_regs_stack_space (live_regs_mask);
4783 /* Work out the registers which need to be saved, both as a mask and a
4784 count of saved words. Return the count.
4786 If doing a pragma interrupt function, then push all regs used by the
4787 function, and if we call another function (we can tell by looking at PR),
4788 make sure that all the regs it clobbers are safe too. */
4791 calc_live_regs (HARD_REG_SET *live_regs_mask)
4795 int interrupt_handler;
4796 int pr_live, has_call;
4798 interrupt_handler = sh_cfun_interrupt_handler_p ();
4800 CLEAR_HARD_REG_SET (*live_regs_mask);
4801 if (TARGET_SH4 && TARGET_FMOVD && interrupt_handler
4802 && regs_ever_live[FPSCR_REG])
4803 target_flags &= ~FPU_SINGLE_BIT;
4804 /* If we can save a lot of saves by switching to double mode, do that. */
4805 else if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE)
4806 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
4807 if (regs_ever_live[reg] && regs_ever_live[reg+1]
4808 && (! call_used_regs[reg] || (interrupt_handler && ! pragma_trapa))
4811 target_flags &= ~FPU_SINGLE_BIT;
4814 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
4815 knows how to use it. That means the pseudo originally allocated for
4816 the initial value can become the PR_MEDIA_REG hard register, as seen for
4817 execute/20010122-1.c:test9. */
4819 /* ??? this function is called from initial_elimination_offset, hence we
4820 can't use the result of sh_media_register_for_return here. */
4821 pr_live = sh_pr_n_sets ();
4824 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
4825 pr_live = (pr_initial
4826 ? (GET_CODE (pr_initial) != REG
4827 || REGNO (pr_initial) != (PR_REG))
4828 : regs_ever_live[PR_REG]);
4829 /* For Shcompact, if not optimizing, we end up with a memory reference
4830 using the return address pointer for __builtin_return_address even
4831 though there is no actual need to put the PR register on the stack. */
4832 pr_live |= regs_ever_live[RETURN_ADDRESS_POINTER_REGNUM];
4834 /* Force PR to be live if the prologue has to call the SHmedia
4835 argument decoder or register saver. */
4836 if (TARGET_SHCOMPACT
4837 && ((current_function_args_info.call_cookie
4838 & ~ CALL_COOKIE_RET_TRAMP (1))
4839 || current_function_has_nonlocal_label))
4841 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
4842 for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--)
4844 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
4846 : (interrupt_handler && ! pragma_trapa)
4847 ? (/* Need to save all the regs ever live. */
4848 (regs_ever_live[reg]
4849 || (call_used_regs[reg]
4850 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
4852 || (has_call && REGISTER_NATURAL_MODE (reg) == SImode
4853 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
4854 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
4855 && reg != RETURN_ADDRESS_POINTER_REGNUM
4856 && reg != T_REG && reg != GBR_REG
4857 /* Push fpscr only on targets which have FPU */
4858 && (reg != FPSCR_REG || TARGET_FPU_ANY))
4859 : (/* Only push those regs which are used and need to be saved. */
4862 && current_function_args_info.call_cookie
4863 && reg == (int) PIC_OFFSET_TABLE_REGNUM)
4864 || (regs_ever_live[reg] && ! call_used_regs[reg])
4865 || (current_function_calls_eh_return
4866 && (reg == (int) EH_RETURN_DATA_REGNO (0)
4867 || reg == (int) EH_RETURN_DATA_REGNO (1)
4868 || reg == (int) EH_RETURN_DATA_REGNO (2)
4869 || reg == (int) EH_RETURN_DATA_REGNO (3)))
4870 || ((reg == MACL_REG || reg == MACH_REG)
4871 && regs_ever_live[reg]
4872 && sh_cfun_attr_renesas_p ())
4875 SET_HARD_REG_BIT (*live_regs_mask, reg);
4876 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4878 if ((TARGET_SH4 || TARGET_SH5) && TARGET_FMOVD
4879 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
4881 if (FP_REGISTER_P (reg))
4883 if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
4885 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
4886 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
4889 else if (XD_REGISTER_P (reg))
4891 /* Must switch to double mode to access these registers. */
4892 target_flags &= ~FPU_SINGLE_BIT;
4897 /* If we have a target register optimization pass after prologue / epilogue
4898 threading, we need to assume all target registers will be live even if
4900 if (flag_branch_target_load_optimize2
4901 && TARGET_SAVE_ALL_TARGET_REGS
4902 && shmedia_space_reserved_for_target_registers)
4903 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
4904 if ((! call_used_regs[reg] || interrupt_handler)
4905 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
4907 SET_HARD_REG_BIT (*live_regs_mask, reg);
4908 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4910 /* If this is an interrupt handler, we don't have any call-clobbered
4911 registers we can conveniently use for target register save/restore.
4912 Make sure we save at least one general purpose register when we need
4913 to save target registers. */
4914 if (interrupt_handler
4915 && hard_regs_intersect_p (live_regs_mask,
4916 ®_class_contents[TARGET_REGS])
4917 && ! hard_regs_intersect_p (live_regs_mask,
4918 ®_class_contents[GENERAL_REGS]))
4920 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
4921 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
4927 /* Code to generate prologue and epilogue sequences */
4929 /* PUSHED is the number of bytes that are being pushed on the
4930 stack for register saves. Return the frame size, padded
4931 appropriately so that the stack stays properly aligned. */
4932 static HOST_WIDE_INT
4933 rounded_frame_size (int pushed)
4935 HOST_WIDE_INT size = get_frame_size ();
4936 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4938 return ((size + pushed + align - 1) & -align) - pushed;
4941 /* Choose a call-clobbered target-branch register that remains
4942 unchanged along the whole function. We set it up as the return
4943 value in the prologue. */
4945 sh_media_register_for_return (void)
4950 if (! current_function_is_leaf)
4952 if (lookup_attribute ("interrupt_handler",
4953 DECL_ATTRIBUTES (current_function_decl)))
4956 tr0_used = flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
4958 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
4959 if (call_used_regs[regno] && ! regs_ever_live[regno])
4965 /* The maximum registers we need to save are:
4966 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
4967 - 32 floating point registers (for each pair, we save none,
4968 one single precision value, or a double precision value).
4969 - 8 target registers
4970 - add 1 entry for a delimiter. */
4971 #define MAX_SAVED_REGS (62+32+8)
4973 typedef struct save_entry_s
4982 /* There will be a delimiter entry with VOIDmode both at the start and the
4983 end of a filled in schedule. The end delimiter has the offset of the
4984 save with the smallest (i.e. most negative) offset. */
4985 typedef struct save_schedule_s
4987 save_entry entries[MAX_SAVED_REGS + 2];
4988 int temps[MAX_TEMPS+1];
4991 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
4992 use reverse order. Returns the last entry written to (not counting
4993 the delimiter). OFFSET_BASE is a number to be added to all offset
4997 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
5001 save_entry *entry = schedule->entries;
5005 if (! current_function_interrupt)
5006 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
5007 if (call_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
5008 && ! FUNCTION_ARG_REGNO_P (i)
5009 && i != FIRST_RET_REG
5010 && ! (current_function_needs_context && i == STATIC_CHAIN_REGNUM)
5011 && ! (current_function_calls_eh_return
5012 && (i == EH_RETURN_STACKADJ_REGNO
5013 || ((unsigned)i <= EH_RETURN_DATA_REGNO (0)
5014 && (unsigned)i >= EH_RETURN_DATA_REGNO (3)))))
5015 schedule->temps[tmpx++] = i;
5017 entry->mode = VOIDmode;
5018 entry->offset = offset_base;
5020 /* We loop twice: first, we save 8-byte aligned registers in the
5021 higher addresses, that are known to be aligned. Then, we
5022 proceed to saving 32-bit registers that don't need 8-byte
5024 If this is an interrupt function, all registers that need saving
5025 need to be saved in full. moreover, we need to postpone saving
5026 target registers till we have saved some general purpose registers
5027 we can then use as scratch registers. */
5028 offset = offset_base;
5029 for (align = 1; align >= 0; align--)
5031 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
5032 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
5034 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5037 if (current_function_interrupt)
5039 if (TARGET_REGISTER_P (i))
5041 if (GENERAL_REGISTER_P (i))
5044 if (mode == SFmode && (i % 2) == 1
5045 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5046 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
5053 /* If we're doing the aligned pass and this is not aligned,
5054 or we're doing the unaligned pass and this is aligned,
5056 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
5060 if (current_function_interrupt
5061 && GENERAL_REGISTER_P (i)
5062 && tmpx < MAX_TEMPS)
5063 schedule->temps[tmpx++] = i;
5065 offset -= GET_MODE_SIZE (mode);
5068 entry->offset = offset;
5071 if (align && current_function_interrupt)
5072 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
5073 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
5075 offset -= GET_MODE_SIZE (DImode);
5077 entry->mode = DImode;
5078 entry->offset = offset;
5083 entry->mode = VOIDmode;
5084 entry->offset = offset;
5085 schedule->temps[tmpx] = -1;
5090 sh_expand_prologue (void)
5092 HARD_REG_SET live_regs_mask;
5095 int save_flags = target_flags;
5097 current_function_interrupt = sh_cfun_interrupt_handler_p ();
5099 /* We have pretend args if we had an object sent partially in registers
5100 and partially on the stack, e.g. a large structure. */
5101 output_stack_adjust (-current_function_pretend_args_size
5102 - current_function_args_info.stack_regs * 8,
5103 stack_pointer_rtx, 0, NULL);
5107 if (TARGET_SHCOMPACT && flag_pic && current_function_args_info.call_cookie)
5108 /* We're going to use the PIC register to load the address of the
5109 incoming-argument decoder and/or of the return trampoline from
5110 the GOT, so make sure the PIC register is preserved and
5112 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
5114 if (TARGET_SHCOMPACT
5115 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
5119 /* First, make all registers with incoming arguments that will
5120 be pushed onto the stack live, so that register renaming
5121 doesn't overwrite them. */
5122 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
5123 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info.call_cookie)
5124 >= NPARM_REGS (SImode) - reg)
5125 for (; reg < NPARM_REGS (SImode); reg++)
5126 emit_insn (gen_shcompact_preserve_incoming_args
5127 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
5128 else if (CALL_COOKIE_INT_REG_GET
5129 (current_function_args_info.call_cookie, reg) == 1)
5130 emit_insn (gen_shcompact_preserve_incoming_args
5131 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
5133 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
5135 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
5136 GEN_INT (current_function_args_info.call_cookie));
5137 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
5138 gen_rtx_REG (SImode, R0_REG));
5140 else if (TARGET_SHMEDIA)
5142 int tr = sh_media_register_for_return ();
5146 rtx insn = emit_move_insn (gen_rtx_REG (DImode, tr),
5147 gen_rtx_REG (DImode, PR_MEDIA_REG));
5149 /* ??? We should suppress saving pr when we don't need it, but this
5150 is tricky because of builtin_return_address. */
5152 /* If this function only exits with sibcalls, this copy
5153 will be flagged as dead. */
5154 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5160 /* Emit the code for SETUP_VARARGS. */
5161 if (current_function_stdarg)
5163 /* This is not used by the SH2E calling convention */
5164 if (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5
5165 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
5167 /* Push arg regs as if they'd been provided by caller in stack. */
5168 for (i = 0; i < NPARM_REGS(SImode); i++)
5170 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
5173 if (i >= (NPARM_REGS(SImode)
5174 - current_function_args_info.arg_count[(int) SH_ARG_INT]
5178 RTX_FRAME_RELATED_P (insn) = 0;
5184 /* If we're supposed to switch stacks at function entry, do so now. */
5186 emit_insn (gen_sp_switch_1 ());
5188 d = calc_live_regs (&live_regs_mask);
5189 /* ??? Maybe we could save some switching if we can move a mode switch
5190 that already happens to be at the function start into the prologue. */
5191 if (target_flags != save_flags && ! current_function_interrupt)
5192 emit_insn (gen_toggle_sz ());
5196 int offset_base, offset;
5198 int offset_in_r0 = -1;
5200 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
5201 int total_size, save_size;
5202 save_schedule schedule;
5206 if (call_used_regs[R0_REG] && ! fixed_regs[R0_REG]
5207 && ! current_function_interrupt)
5208 r0 = gen_rtx_REG (Pmode, R0_REG);
5210 /* D is the actual number of bytes that we need for saving registers,
5211 however, in initial_elimination_offset we have committed to using
5212 an additional TREGS_SPACE amount of bytes - in order to keep both
5213 addresses to arguments supplied by the caller and local variables
5214 valid, we must keep this gap. Place it between the incoming
5215 arguments and the actually saved registers in a bid to optimize
5216 locality of reference. */
5217 total_size = d + tregs_space;
5218 total_size += rounded_frame_size (total_size);
5219 save_size = total_size - rounded_frame_size (d);
5220 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
5221 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5222 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
5224 /* If adjusting the stack in a single step costs nothing extra, do so.
5225 I.e. either if a single addi is enough, or we need a movi anyway,
5226 and we don't exceed the maximum offset range (the test for the
5227 latter is conservative for simplicity). */
5229 && (CONST_OK_FOR_I10 (-total_size)
5230 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
5231 && total_size <= 2044)))
5232 d_rounding = total_size - save_size;
5234 offset_base = d + d_rounding;
5236 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
5239 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
5240 tmp_pnt = schedule.temps;
5241 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
5243 enum machine_mode mode = entry->mode;
5244 int reg = entry->reg;
5245 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
5247 offset = entry->offset;
5249 reg_rtx = gen_rtx_REG (mode, reg);
5251 mem_rtx = gen_rtx_MEM (mode,
5252 gen_rtx_PLUS (Pmode,
5256 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
5264 if (HAVE_PRE_DECREMENT
5265 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
5266 || mem_rtx == NULL_RTX
5267 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
5269 pre_dec = gen_rtx_MEM (mode,
5270 gen_rtx_PRE_DEC (Pmode, r0));
5272 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
5281 offset += GET_MODE_SIZE (mode);
5285 if (mem_rtx != NULL_RTX)
5288 if (offset_in_r0 == -1)
5290 emit_move_insn (r0, GEN_INT (offset));
5291 offset_in_r0 = offset;
5293 else if (offset != offset_in_r0)
5298 GEN_INT (offset - offset_in_r0)));
5299 offset_in_r0 += offset - offset_in_r0;
5302 if (pre_dec != NULL_RTX)
5308 (Pmode, r0, stack_pointer_rtx));
5312 offset -= GET_MODE_SIZE (mode);
5313 offset_in_r0 -= GET_MODE_SIZE (mode);
5318 mem_rtx = gen_rtx_MEM (mode, r0);
5320 mem_rtx = gen_rtx_MEM (mode,
5321 gen_rtx_PLUS (Pmode,
5325 /* We must not use an r0-based address for target-branch
5326 registers or for special registers without pre-dec
5327 memory addresses, since we store their values in r0
5329 if (TARGET_REGISTER_P (reg)
5330 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5331 && mem_rtx != pre_dec))
5335 if (TARGET_REGISTER_P (reg)
5336 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5337 && mem_rtx != pre_dec))
5339 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
5341 emit_move_insn (tmp_reg, reg_rtx);
5343 if (REGNO (tmp_reg) == R0_REG)
5347 if (refers_to_regno_p (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0))
5351 if (*++tmp_pnt <= 0)
5352 tmp_pnt = schedule.temps;
5359 /* Mark as interesting for dwarf cfi generator */
5360 insn = emit_move_insn (mem_rtx, reg_rtx);
5361 RTX_FRAME_RELATED_P (insn) = 1;
5363 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
5365 rtx reg_rtx = gen_rtx_REG (mode, reg);
5367 rtx mem_rtx = gen_rtx_MEM (mode,
5368 gen_rtx_PLUS (Pmode,
5372 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
5373 note_rtx = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set,
5375 REG_NOTES (insn) = note_rtx;
5380 if (entry->offset != d_rounding)
5384 push_regs (&live_regs_mask, current_function_interrupt);
5386 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5388 rtx insn = get_last_insn ();
5389 rtx last = emit_insn (gen_GOTaddr2picreg ());
5391 /* Mark these insns as possibly dead. Sometimes, flow2 may
5392 delete all uses of the PIC register. In this case, let it
5393 delete the initialization too. */
5396 insn = NEXT_INSN (insn);
5398 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5402 while (insn != last);
5405 if (SHMEDIA_REGS_STACK_ADJUST ())
5407 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5408 function_symbol (TARGET_FPU_ANY
5409 ? "__GCC_push_shmedia_regs"
5410 : "__GCC_push_shmedia_regs_nofpu"));
5411 /* This must NOT go through the PLT, otherwise mach and macl
5412 may be clobbered. */
5413 emit_insn (gen_shmedia_save_restore_regs_compact
5414 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
5417 if (target_flags != save_flags && ! current_function_interrupt)
5419 rtx insn = emit_insn (gen_toggle_sz ());
5421 /* If we're lucky, a mode switch in the function body will
5422 overwrite fpscr, turning this insn dead. Tell flow this
5423 insn is ok to delete. */
5424 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5429 target_flags = save_flags;
5431 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
5432 stack_pointer_rtx, 0, NULL);
5434 if (frame_pointer_needed)
5435 frame_insn (GEN_MOV (frame_pointer_rtx, stack_pointer_rtx));
5437 if (TARGET_SHCOMPACT
5438 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
5440 /* This must NOT go through the PLT, otherwise mach and macl
5441 may be clobbered. */
5442 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5443 function_symbol ("__GCC_shcompact_incoming_args"));
5444 emit_insn (gen_shcompact_incoming_args ());
5449 sh_expand_epilogue (void)
5451 HARD_REG_SET live_regs_mask;
5455 int save_flags = target_flags;
5456 int frame_size, save_size;
5457 int fpscr_deferred = 0;
5459 d = calc_live_regs (&live_regs_mask);
5462 frame_size = rounded_frame_size (d);
5466 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
5468 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
5469 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5470 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
5472 total_size = d + tregs_space;
5473 total_size += rounded_frame_size (total_size);
5474 save_size = total_size - frame_size;
5476 /* If adjusting the stack in a single step costs nothing extra, do so.
5477 I.e. either if a single addi is enough, or we need a movi anyway,
5478 and we don't exceed the maximum offset range (the test for the
5479 latter is conservative for simplicity). */
5481 && ! frame_pointer_needed
5482 && (CONST_OK_FOR_I10 (total_size)
5483 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
5484 && total_size <= 2044)))
5485 d_rounding = frame_size;
5487 frame_size -= d_rounding;
5490 if (frame_pointer_needed)
5492 output_stack_adjust (frame_size, frame_pointer_rtx, 1, &live_regs_mask);
5494 /* We must avoid moving the stack pointer adjustment past code
5495 which reads from the local frame, else an interrupt could
5496 occur after the SP adjustment and clobber data in the local
5498 emit_insn (gen_blockage ());
5499 emit_insn (GEN_MOV (stack_pointer_rtx, frame_pointer_rtx));
5501 else if (frame_size)
5503 /* We must avoid moving the stack pointer adjustment past code
5504 which reads from the local frame, else an interrupt could
5505 occur after the SP adjustment and clobber data in the local
5507 emit_insn (gen_blockage ());
5508 output_stack_adjust (frame_size, stack_pointer_rtx, 1, &live_regs_mask);
5511 if (SHMEDIA_REGS_STACK_ADJUST ())
5513 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5514 function_symbol (TARGET_FPU_ANY
5515 ? "__GCC_pop_shmedia_regs"
5516 : "__GCC_pop_shmedia_regs_nofpu"));
5517 /* This must NOT go through the PLT, otherwise mach and macl
5518 may be clobbered. */
5519 emit_insn (gen_shmedia_save_restore_regs_compact
5520 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
5523 /* Pop all the registers. */
5525 if (target_flags != save_flags && ! current_function_interrupt)
5526 emit_insn (gen_toggle_sz ());
5529 int offset_base, offset;
5530 int offset_in_r0 = -1;
5532 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
5533 save_schedule schedule;
5537 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
5538 offset_base = -entry[1].offset + d_rounding;
5539 tmp_pnt = schedule.temps;
5540 for (; entry->mode != VOIDmode; entry--)
5542 enum machine_mode mode = entry->mode;
5543 int reg = entry->reg;
5544 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
5546 offset = offset_base + entry->offset;
5547 reg_rtx = gen_rtx_REG (mode, reg);
5549 mem_rtx = gen_rtx_MEM (mode,
5550 gen_rtx_PLUS (Pmode,
5554 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
5560 if (HAVE_POST_INCREMENT
5561 && (offset == offset_in_r0
5562 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
5563 && mem_rtx == NULL_RTX)
5564 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
5566 post_inc = gen_rtx_MEM (mode,
5567 gen_rtx_POST_INC (Pmode, r0));
5569 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
5572 post_inc = NULL_RTX;
5581 if (mem_rtx != NULL_RTX)
5584 if (offset_in_r0 == -1)
5586 emit_move_insn (r0, GEN_INT (offset));
5587 offset_in_r0 = offset;
5589 else if (offset != offset_in_r0)
5594 GEN_INT (offset - offset_in_r0)));
5595 offset_in_r0 += offset - offset_in_r0;
5598 if (post_inc != NULL_RTX)
5604 (Pmode, r0, stack_pointer_rtx));
5610 offset_in_r0 += GET_MODE_SIZE (mode);
5613 mem_rtx = gen_rtx_MEM (mode, r0);
5615 mem_rtx = gen_rtx_MEM (mode,
5616 gen_rtx_PLUS (Pmode,
5620 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5621 && mem_rtx != post_inc)
5625 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5626 && mem_rtx != post_inc)
5628 insn = emit_move_insn (r0, mem_rtx);
5631 else if (TARGET_REGISTER_P (reg))
5633 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
5635 /* Give the scheduler a bit of freedom by using up to
5636 MAX_TEMPS registers in a round-robin fashion. */
5637 insn = emit_move_insn (tmp_reg, mem_rtx);
5640 tmp_pnt = schedule.temps;
5643 insn = emit_move_insn (reg_rtx, mem_rtx);
5644 if (reg == PR_MEDIA_REG && sh_media_register_for_return () >= 0)
5645 /* This is dead, unless we return with a sibcall. */
5646 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5651 if (entry->offset + offset_base != d + d_rounding)
5654 else /* ! TARGET_SH5 */
5657 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
5659 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5661 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
5663 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
5664 && hard_regs_intersect_p (&live_regs_mask,
5665 ®_class_contents[DF_REGS]))
5667 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j))
5669 if (j == FIRST_FP_REG && fpscr_deferred)
5674 if (target_flags != save_flags && ! current_function_interrupt)
5675 emit_insn (gen_toggle_sz ());
5676 target_flags = save_flags;
5678 output_stack_adjust (extra_push + current_function_pretend_args_size
5679 + save_size + d_rounding
5680 + current_function_args_info.stack_regs * 8,
5681 stack_pointer_rtx, 1, NULL);
5683 if (current_function_calls_eh_return)
5684 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
5685 EH_RETURN_STACKADJ_RTX));
5687 /* Switch back to the normal stack if necessary. */
5689 emit_insn (gen_sp_switch_2 ());
5691 /* Tell flow the insn that pops PR isn't dead. */
5692 /* PR_REG will never be live in SHmedia mode, and we don't need to
5693 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
5694 by the return pattern. */
5695 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
5696 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
5699 static int sh_need_epilogue_known = 0;
5702 sh_need_epilogue (void)
5704 if (! sh_need_epilogue_known)
5709 sh_expand_epilogue ();
5710 epilogue = get_insns ();
5712 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
5714 return sh_need_epilogue_known > 0;
5717 /* Emit code to change the current function's return address to RA.
5718 TEMP is available as a scratch register, if needed. */
5721 sh_set_return_address (rtx ra, rtx tmp)
5723 HARD_REG_SET live_regs_mask;
5725 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
5728 d = calc_live_regs (&live_regs_mask);
5730 /* If pr_reg isn't life, we can set it (or the register given in
5731 sh_media_register_for_return) directly. */
5732 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
5738 int rr_regno = sh_media_register_for_return ();
5743 rr = gen_rtx_REG (DImode, rr_regno);
5746 rr = gen_rtx_REG (SImode, pr_reg);
5748 emit_insn (GEN_MOV (rr, ra));
5749 /* Tell flow the register for return isn't dead. */
5750 emit_insn (gen_rtx_USE (VOIDmode, rr));
5757 save_schedule schedule;
5760 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
5761 offset = entry[1].offset;
5762 for (; entry->mode != VOIDmode; entry--)
5763 if (entry->reg == pr_reg)
5766 /* We can't find pr register. */
5770 offset = entry->offset - offset;
5771 pr_offset = (rounded_frame_size (d) + offset
5772 + SHMEDIA_REGS_STACK_ADJUST ());
5775 pr_offset = rounded_frame_size (d);
5777 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
5778 emit_insn (GEN_ADD3 (tmp, tmp, frame_pointer_rtx));
5780 tmp = gen_rtx_MEM (Pmode, tmp);
5781 emit_insn (GEN_MOV (tmp, ra));
5784 /* Clear variables at function end. */
5787 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
5788 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5790 trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
5791 sh_need_epilogue_known = 0;
5792 sp_switch = NULL_RTX;
5796 sh_builtin_saveregs (void)
5798 /* First unnamed integer register. */
5799 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
5800 /* Number of integer registers we need to save. */
5801 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
5802 /* First unnamed SFmode float reg */
5803 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
5804 /* Number of SFmode float regs to save. */
5805 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
5808 HOST_WIDE_INT alias_set;
5814 int pushregs = n_intregs;
5816 while (pushregs < NPARM_REGS (SImode) - 1
5817 && (CALL_COOKIE_INT_REG_GET
5818 (current_function_args_info.call_cookie,
5819 NPARM_REGS (SImode) - pushregs)
5822 current_function_args_info.call_cookie
5823 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
5828 if (pushregs == NPARM_REGS (SImode))
5829 current_function_args_info.call_cookie
5830 |= (CALL_COOKIE_INT_REG (0, 1)
5831 | CALL_COOKIE_STACKSEQ (pushregs - 1));
5833 current_function_args_info.call_cookie
5834 |= CALL_COOKIE_STACKSEQ (pushregs);
5836 current_function_pretend_args_size += 8 * n_intregs;
5838 if (TARGET_SHCOMPACT)
5842 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
5844 error ("__builtin_saveregs not supported by this subtarget");
5851 /* Allocate block of memory for the regs. */
5852 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
5853 Or can assign_stack_local accept a 0 SIZE argument? */
5854 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
5857 regbuf = gen_rtx_MEM (BLKmode,
5858 gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
5859 else if (n_floatregs & 1)
5863 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
5864 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
5865 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
5866 regbuf = change_address (regbuf, BLKmode, addr);
5869 regbuf = assign_stack_local (BLKmode, bufsize, 0);
5870 alias_set = get_varargs_alias_set ();
5871 set_mem_alias_set (regbuf, alias_set);
5874 This is optimized to only save the regs that are necessary. Explicitly
5875 named args need not be saved. */
5877 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
5878 adjust_address (regbuf, BLKmode,
5879 n_floatregs * UNITS_PER_WORD),
5883 /* Return the address of the regbuf. */
5884 return XEXP (regbuf, 0);
5887 This is optimized to only save the regs that are necessary. Explicitly
5888 named args need not be saved.
5889 We explicitly build a pointer to the buffer because it halves the insn
5890 count when not optimizing (otherwise the pointer is built for each reg
5892 We emit the moves in reverse order so that we can use predecrement. */
5894 fpregs = gen_reg_rtx (Pmode);
5895 emit_move_insn (fpregs, XEXP (regbuf, 0));
5896 emit_insn (gen_addsi3 (fpregs, fpregs,
5897 GEN_INT (n_floatregs * UNITS_PER_WORD)));
5901 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
5903 emit_insn (gen_addsi3 (fpregs, fpregs,
5904 GEN_INT (-2 * UNITS_PER_WORD)));
5905 mem = gen_rtx_MEM (DFmode, fpregs);
5906 set_mem_alias_set (mem, alias_set);
5907 emit_move_insn (mem,
5908 gen_rtx (REG, DFmode, BASE_ARG_REG (DFmode) + regno));
5910 regno = first_floatreg;
5913 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5914 mem = gen_rtx_MEM (SFmode, fpregs);
5915 set_mem_alias_set (mem, alias_set);
5916 emit_move_insn (mem,
5917 gen_rtx (REG, SFmode, BASE_ARG_REG (SFmode) + regno
5918 - (TARGET_LITTLE_ENDIAN != 0)));
5922 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
5926 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5927 mem = gen_rtx_MEM (SFmode, fpregs);
5928 set_mem_alias_set (mem, alias_set);
5929 emit_move_insn (mem,
5930 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
5933 /* Return the address of the regbuf. */
5934 return XEXP (regbuf, 0);
5937 /* Define the `__builtin_va_list' type for the ABI. */
5940 sh_build_builtin_va_list (void)
5942 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5945 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
5946 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
5947 return ptr_type_node;
5949 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5951 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
5953 f_next_o_limit = build_decl (FIELD_DECL,
5954 get_identifier ("__va_next_o_limit"),
5956 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
5958 f_next_fp_limit = build_decl (FIELD_DECL,
5959 get_identifier ("__va_next_fp_limit"),
5961 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
5964 DECL_FIELD_CONTEXT (f_next_o) = record;
5965 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
5966 DECL_FIELD_CONTEXT (f_next_fp) = record;
5967 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
5968 DECL_FIELD_CONTEXT (f_next_stack) = record;
5970 TYPE_FIELDS (record) = f_next_o;
5971 TREE_CHAIN (f_next_o) = f_next_o_limit;
5972 TREE_CHAIN (f_next_o_limit) = f_next_fp;
5973 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
5974 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
5976 layout_type (record);
5981 /* Implement `va_start' for varargs and stdarg. */
5984 sh_va_start (tree valist, rtx nextarg)
5986 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5987 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
5993 expand_builtin_saveregs ();
5994 std_expand_builtin_va_start (valist, nextarg);
5998 if ((! TARGET_SH2E && ! TARGET_SH4)
5999 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
6001 std_expand_builtin_va_start (valist, nextarg);
6005 f_next_o = TYPE_FIELDS (va_list_type_node);
6006 f_next_o_limit = TREE_CHAIN (f_next_o);
6007 f_next_fp = TREE_CHAIN (f_next_o_limit);
6008 f_next_fp_limit = TREE_CHAIN (f_next_fp);
6009 f_next_stack = TREE_CHAIN (f_next_fp_limit);
6011 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
6012 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
6013 valist, f_next_o_limit);
6014 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp);
6015 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
6016 valist, f_next_fp_limit);
6017 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
6018 valist, f_next_stack);
6020 /* Call __builtin_saveregs. */
6021 u = make_tree (ptr_type_node, expand_builtin_saveregs ());
6022 t = build (MODIFY_EXPR, ptr_type_node, next_fp, u);
6023 TREE_SIDE_EFFECTS (t) = 1;
6024 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6026 nfp = current_function_args_info.arg_count[SH_ARG_FLOAT];
6031 u = fold (build (PLUS_EXPR, ptr_type_node, u,
6032 build_int_2 (UNITS_PER_WORD * nfp, 0)));
6033 t = build (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
6034 TREE_SIDE_EFFECTS (t) = 1;
6035 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6037 t = build (MODIFY_EXPR, ptr_type_node, next_o, u);
6038 TREE_SIDE_EFFECTS (t) = 1;
6039 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6041 nint = current_function_args_info.arg_count[SH_ARG_INT];
6046 u = fold (build (PLUS_EXPR, ptr_type_node, u,
6047 build_int_2 (UNITS_PER_WORD * nint, 0)));
6048 t = build (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
6049 TREE_SIDE_EFFECTS (t) = 1;
6050 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6052 u = make_tree (ptr_type_node, nextarg);
6053 t = build (MODIFY_EXPR, ptr_type_node, next_stack, u);
6054 TREE_SIDE_EFFECTS (t) = 1;
6055 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6058 /* Implement `va_arg'. */
6061 sh_va_arg (tree valist, tree type)
6063 HOST_WIDE_INT size, rsize;
6064 tree tmp, pptr_type_node;
6066 rtx result_ptr, result = NULL_RTX;
6067 int pass_by_ref = MUST_PASS_IN_STACK (TYPE_MODE (type), type);
6070 size = int_size_in_bytes (type);
6071 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6072 pptr_type_node = build_pointer_type (ptr_type_node);
6075 type = build_pointer_type (type);
6077 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
6078 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
6080 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
6081 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
6085 f_next_o = TYPE_FIELDS (va_list_type_node);
6086 f_next_o_limit = TREE_CHAIN (f_next_o);
6087 f_next_fp = TREE_CHAIN (f_next_o_limit);
6088 f_next_fp_limit = TREE_CHAIN (f_next_fp);
6089 f_next_stack = TREE_CHAIN (f_next_fp_limit);
6091 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
6092 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
6093 valist, f_next_o_limit);
6094 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp),
6096 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
6097 valist, f_next_fp_limit);
6098 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
6099 valist, f_next_stack);
6101 /* Structures with a single member with a distinct mode are passed
6102 like their member. This is relevant if the latter has a REAL_TYPE
6103 or COMPLEX_TYPE type. */
6104 if (TREE_CODE (type) == RECORD_TYPE
6105 && TYPE_FIELDS (type)
6106 && TREE_CODE (TYPE_FIELDS (type)) == FIELD_DECL
6107 && (TREE_CODE (TREE_TYPE (TYPE_FIELDS (type))) == REAL_TYPE
6108 || TREE_CODE (TREE_TYPE (TYPE_FIELDS (type))) == COMPLEX_TYPE)
6109 && TREE_CHAIN (TYPE_FIELDS (type)) == NULL_TREE)
6110 type = TREE_TYPE (TYPE_FIELDS (type));
6113 pass_as_float = ((TREE_CODE (type) == REAL_TYPE && size <= 8)
6114 || (TREE_CODE (type) == COMPLEX_TYPE
6115 && TREE_CODE (TREE_TYPE (type)) == REAL_TYPE
6120 pass_as_float = (TREE_CODE (type) == REAL_TYPE && size == 4);
6123 addr_rtx = gen_reg_rtx (Pmode);
6124 lab_false = gen_label_rtx ();
6125 lab_over = gen_label_rtx ();
6127 tmp = make_tree (pptr_type_node, addr_rtx);
6128 valist = build1 (INDIRECT_REF, ptr_type_node, tmp);
6133 = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
6134 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
6136 emit_cmp_and_jump_insns (expand_expr (next_fp, NULL_RTX, Pmode,
6138 expand_expr (next_fp_limit, NULL_RTX,
6139 Pmode, EXPAND_NORMAL),
6140 GE, const1_rtx, Pmode, 1, lab_false);
6142 if (TYPE_ALIGN (type) > BITS_PER_WORD
6143 || (((TREE_CODE (type) == REAL_TYPE && size == 8) || size == 16)
6144 && (n_floatregs & 1)))
6146 tmp = build (BIT_AND_EXPR, ptr_type_node, next_fp,
6147 build_int_2 (UNITS_PER_WORD, 0));
6148 tmp = build (PLUS_EXPR, ptr_type_node, next_fp, tmp);
6149 tmp = build (MODIFY_EXPR, ptr_type_node, next_fp, tmp);
6150 TREE_SIDE_EFFECTS (tmp) = 1;
6151 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
6154 tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp);
6155 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6157 emit_move_insn (addr_rtx, r);
6159 #ifdef FUNCTION_ARG_SCmode_WART
6160 if (TYPE_MODE (type) == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
6162 rtx addr, real, imag, result_value, slot;
6163 tree subtype = TREE_TYPE (type);
6165 addr = std_expand_builtin_va_arg (valist, subtype);
6166 #ifdef POINTERS_EXTEND_UNSIGNED
6167 if (GET_MODE (addr) != Pmode)
6168 addr = convert_memory_address (Pmode, addr);
6170 imag = gen_rtx_MEM (TYPE_MODE (type), addr);
6171 set_mem_alias_set (imag, get_varargs_alias_set ());
6173 addr = std_expand_builtin_va_arg (valist, subtype);
6174 #ifdef POINTERS_EXTEND_UNSIGNED
6175 if (GET_MODE (addr) != Pmode)
6176 addr = convert_memory_address (Pmode, addr);
6178 real = gen_rtx_MEM (TYPE_MODE (type), addr);
6179 set_mem_alias_set (real, get_varargs_alias_set ());
6181 result_value = gen_rtx_CONCAT (SCmode, real, imag);
6182 /* ??? this interface is stupid - why require a pointer? */
6183 result = gen_reg_rtx (Pmode);
6184 slot = assign_stack_temp (SCmode, 8, 0);
6185 emit_move_insn (slot, result_value);
6186 emit_move_insn (result, XEXP (slot, 0));
6188 #endif /* FUNCTION_ARG_SCmode_WART */
6190 emit_jump_insn (gen_jump (lab_over));
6192 emit_label (lab_false);
6194 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
6195 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6197 emit_move_insn (addr_rtx, r);
6201 tmp = build (PLUS_EXPR, ptr_type_node, next_o,
6202 build_int_2 (rsize, 0));
6204 emit_cmp_and_jump_insns (expand_expr (tmp, NULL_RTX, Pmode,
6206 expand_expr (next_o_limit, NULL_RTX,
6207 Pmode, EXPAND_NORMAL),
6208 GT, const1_rtx, Pmode, 1, lab_false);
6210 tmp = build1 (ADDR_EXPR, pptr_type_node, next_o);
6211 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6213 emit_move_insn (addr_rtx, r);
6215 emit_jump_insn (gen_jump (lab_over));
6217 emit_label (lab_false);
6219 if (size > 4 && ! TARGET_SH4)
6221 tmp = build (MODIFY_EXPR, ptr_type_node, next_o, next_o_limit);
6222 TREE_SIDE_EFFECTS (tmp) = 1;
6223 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
6226 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
6227 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6229 emit_move_insn (addr_rtx, r);
6233 emit_label (lab_over);
6236 /* ??? In va-sh.h, there had been code to make values larger than
6237 size 8 indirect. This does not match the FUNCTION_ARG macros. */
6239 result_ptr = std_expand_builtin_va_arg (valist, type);
6242 emit_move_insn (result, result_ptr);
6243 emit_label (lab_over);
6246 result = result_ptr;
6250 #ifdef POINTERS_EXTEND_UNSIGNED
6251 if (GET_MODE (addr) != Pmode)
6252 addr = convert_memory_address (Pmode, result);
6254 result = gen_rtx_MEM (ptr_mode, force_reg (Pmode, result));
6255 set_mem_alias_set (result, get_varargs_alias_set ());
6257 /* ??? expand_builtin_va_arg will also set the alias set of the dereferenced
6258 argument to the varargs alias set. */
6263 sh_promote_prototypes (tree type)
6269 return ! sh_attr_renesas_p (type);
6272 /* Define where to put the arguments to a function.
6273 Value is zero to push the argument on the stack,
6274 or a hard register in which to store the argument.
6276 MODE is the argument's machine mode.
6277 TYPE is the data type of the argument (as a tree).
6278 This is null for libcalls where that information may
6280 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6281 the preceding args and about the function being called.
6282 NAMED is nonzero if this argument is a named parameter
6283 (otherwise it is an extra parameter matching an ellipsis).
6285 On SH the first args are normally in registers
6286 and the rest are pushed. Any arg that starts within the first
6287 NPARM_REGS words is at least partially passed in a register unless
6288 its data type forbids. */
6292 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
6293 tree type, int named)
6295 if (! TARGET_SH5 && mode == VOIDmode)
6296 return GEN_INT (ca->renesas_abi ? 1 : 0);
6299 && PASS_IN_REG_P (*ca, mode, type)
6300 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
6304 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
6305 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
6307 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
6308 gen_rtx_REG (SFmode,
6310 + (ROUND_REG (*ca, mode) ^ 1)),
6312 rtx r2 = gen_rtx_EXPR_LIST(VOIDmode,
6313 gen_rtx_REG (SFmode,
6315 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
6317 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
6320 /* If the alignment of a DF value causes an SF register to be
6321 skipped, we will use that skipped register for the next SF
6323 if ((TARGET_HITACHI || ca->renesas_abi)
6324 && ca->free_single_fp_reg
6326 return gen_rtx_REG (mode, ca->free_single_fp_reg);
6328 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
6329 ^ (mode == SFmode && TARGET_SH4
6330 && TARGET_LITTLE_ENDIAN != 0
6331 && ! TARGET_HITACHI && ! ca->renesas_abi);
6332 return gen_rtx_REG (mode, regno);
6338 if (mode == VOIDmode && TARGET_SHCOMPACT)
6339 return GEN_INT (ca->call_cookie);
6341 /* The following test assumes unnamed arguments are promoted to
6343 if (mode == SFmode && ca->free_single_fp_reg)
6344 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
6346 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
6347 && (named || ! ca->prototype_p)
6348 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
6350 if (! ca->prototype_p && TARGET_SHMEDIA)
6351 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
6353 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
6355 + ca->arg_count[(int) SH_ARG_FLOAT]);
6358 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
6359 && (! TARGET_SHCOMPACT
6360 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
6361 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
6364 return gen_rtx_REG (mode, (FIRST_PARM_REG
6365 + ca->arg_count[(int) SH_ARG_INT]));
6374 /* Update the data in CUM to advance over an argument
6375 of mode MODE and data type TYPE.
6376 (TYPE is null for libcalls where that information may not be
6380 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
6381 tree type, int named)
6385 else if (TARGET_SH5)
6387 tree type2 = (ca->byref && type
6390 enum machine_mode mode2 = (ca->byref && type
6393 int dwords = ((ca->byref
6396 ? int_size_in_bytes (type2)
6397 : GET_MODE_SIZE (mode2)) + 7) / 8;
6398 int numregs = MIN (dwords, NPARM_REGS (SImode)
6399 - ca->arg_count[(int) SH_ARG_INT]);
6403 ca->arg_count[(int) SH_ARG_INT] += numregs;
6404 if (TARGET_SHCOMPACT
6405 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
6408 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
6410 /* N.B. We want this also for outgoing. */
6411 ca->stack_regs += numregs;
6416 ca->stack_regs += numregs;
6417 ca->byref_regs += numregs;
6421 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
6425 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
6428 else if (dwords > numregs)
6430 int pushregs = numregs;
6432 if (TARGET_SHCOMPACT)
6433 ca->stack_regs += numregs;
6434 while (pushregs < NPARM_REGS (SImode) - 1
6435 && (CALL_COOKIE_INT_REG_GET
6437 NPARM_REGS (SImode) - pushregs)
6441 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
6445 if (numregs == NPARM_REGS (SImode))
6447 |= CALL_COOKIE_INT_REG (0, 1)
6448 | CALL_COOKIE_STACKSEQ (numregs - 1);
6451 |= CALL_COOKIE_STACKSEQ (numregs);
6454 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
6455 && (named || ! ca->prototype_p))
6457 if (mode2 == SFmode && ca->free_single_fp_reg)
6458 ca->free_single_fp_reg = 0;
6459 else if (ca->arg_count[(int) SH_ARG_FLOAT]
6460 < NPARM_REGS (SFmode))
6463 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
6465 - ca->arg_count[(int) SH_ARG_FLOAT]);
6467 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
6469 if (TARGET_SHCOMPACT && ! ca->prototype_p)
6471 if (ca->outgoing && numregs > 0)
6475 |= (CALL_COOKIE_INT_REG
6476 (ca->arg_count[(int) SH_ARG_INT]
6477 - numregs + ((numfpregs - 2) / 2),
6478 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
6481 while (numfpregs -= 2);
6483 else if (mode2 == SFmode && (named)
6484 && (ca->arg_count[(int) SH_ARG_FLOAT]
6485 < NPARM_REGS (SFmode)))
6486 ca->free_single_fp_reg
6487 = FIRST_FP_PARM_REG - numfpregs
6488 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
6494 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
6496 /* Note that we've used the skipped register. */
6497 if (mode == SFmode && ca->free_single_fp_reg)
6499 ca->free_single_fp_reg = 0;
6502 /* When we have a DF after an SF, there's an SF register that get
6503 skipped in order to align the DF value. We note this skipped
6504 register, because the next SF value will use it, and not the
6505 SF that follows the DF. */
6507 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
6509 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
6510 + BASE_ARG_REG (mode));
6514 if (! (TARGET_SH4 || ca->renesas_abi)
6515 || PASS_IN_REG_P (*ca, mode, type))
6516 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
6517 = (ROUND_REG (*ca, mode)
6519 ? ROUND_ADVANCE (int_size_in_bytes (type))
6520 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
6523 /* If the structure value address is not passed in a register, define
6524 `STRUCT_VALUE' as an expression returning an RTX for the place
6525 where the address is passed. If it returns 0, the address is
6526 passed as an "invisible" first argument. */
6527 /* The Renesas calling convention doesn't quite fit into this scheme since
6528 the address is passed like an invisible argument, but one that is always
6529 passed in memory. */
6531 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
6533 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
6535 return gen_rtx_REG (Pmode, 2);
6539 sh_return_in_memory (tree type, tree fndecl)
6543 if (TYPE_MODE (type) == BLKmode)
6544 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
6546 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
6550 return (TYPE_MODE (type) == BLKmode
6551 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
6552 && TREE_CODE (type) == RECORD_TYPE));
6556 /* We actually emit the code in sh_expand_prologue. We used to use
6557 a static variable to flag that we need to emit this code, but that
6558 doesn't when inlining, when functions are deferred and then emitted
6559 later. Fortunately, we already have two flags that are part of struct
6560 function that tell if a function uses varargs or stdarg. */
6562 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
6563 enum machine_mode mode ATTRIBUTE_UNUSED,
6564 tree type ATTRIBUTE_UNUSED,
6565 int *pretend_arg_size ATTRIBUTE_UNUSED,
6566 int second_time ATTRIBUTE_UNUSED)
6568 if (! current_function_stdarg)
6573 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
6579 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
6581 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
6585 /* Define the offset between two registers, one to be eliminated, and
6586 the other its replacement, at the start of a routine. */
6589 initial_elimination_offset (int from, int to)
6592 int regs_saved_rounding = 0;
6593 int total_saved_regs_space;
6594 int total_auto_space;
6595 int save_flags = target_flags;
6597 HARD_REG_SET live_regs_mask;
6599 shmedia_space_reserved_for_target_registers = false;
6600 regs_saved = calc_live_regs (&live_regs_mask);
6601 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
6603 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
6605 shmedia_space_reserved_for_target_registers = true;
6606 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
6609 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
6610 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6611 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
6613 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
6614 copy_flags = target_flags;
6615 target_flags = save_flags;
6617 total_saved_regs_space = regs_saved + regs_saved_rounding;
6619 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
6620 return total_saved_regs_space + total_auto_space
6621 + current_function_args_info.byref_regs * 8;
6623 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
6624 return total_saved_regs_space + total_auto_space
6625 + current_function_args_info.byref_regs * 8;
6627 /* Initial gap between fp and sp is 0. */
6628 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
6631 if (from == RETURN_ADDRESS_POINTER_REGNUM
6632 && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
6636 int n = total_saved_regs_space;
6637 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
6638 save_schedule schedule;
6641 n += total_auto_space;
6643 /* If it wasn't saved, there's not much we can do. */
6644 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
6647 target_flags = copy_flags;
6649 sh5_schedule_saves (&live_regs_mask, &schedule, n);
6650 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6651 if (entry->reg == pr_reg)
6653 target_flags = save_flags;
6654 return entry->offset;
6659 return total_auto_space;
6665 /* Handle machine specific pragmas to be semi-compatible with Renesas
6669 sh_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
6671 pragma_interrupt = 1;
6675 sh_pr_trapa (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
6677 pragma_interrupt = pragma_trapa = 1;
6681 sh_pr_nosave_low_regs (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
6683 pragma_nosave_low_regs = 1;
6686 /* Generate 'handle_interrupt' attribute for decls */
6689 sh_insert_attributes (tree node, tree *attributes)
6691 if (! pragma_interrupt
6692 || TREE_CODE (node) != FUNCTION_DECL)
6695 /* We are only interested in fields. */
6696 if (TREE_CODE_CLASS (TREE_CODE (node)) != 'd')
6699 /* Add a 'handle_interrupt' attribute. */
6700 * attributes = tree_cons (get_identifier ("interrupt_handler"), NULL, * attributes);
6705 /* Supported attributes:
6707 interrupt_handler -- specifies this function is an interrupt handler.
6709 sp_switch -- specifies an alternate stack for an interrupt handler
6712 trap_exit -- use a trapa to exit an interrupt function instead of
6715 renesas -- use Renesas calling/layout conventions (functions and
6720 const struct attribute_spec sh_attribute_table[] =
6722 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6723 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
6724 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
6725 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
6726 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
6727 { NULL, 0, 0, false, false, false, NULL }
6730 /* Handle an "interrupt_handler" attribute; arguments as in
6731 struct attribute_spec.handler. */
6733 sh_handle_interrupt_handler_attribute (tree *node, tree name,
6734 tree args ATTRIBUTE_UNUSED,
6735 int flags ATTRIBUTE_UNUSED,
6738 if (TREE_CODE (*node) != FUNCTION_DECL)
6740 warning ("`%s' attribute only applies to functions",
6741 IDENTIFIER_POINTER (name));
6742 *no_add_attrs = true;
6744 else if (TARGET_SHCOMPACT)
6746 error ("attribute interrupt_handler is not compatible with -m5-compact");
6747 *no_add_attrs = true;
6753 /* Handle an "sp_switch" attribute; arguments as in
6754 struct attribute_spec.handler. */
6756 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
6757 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
6759 if (TREE_CODE (*node) != FUNCTION_DECL)
6761 warning ("`%s' attribute only applies to functions",
6762 IDENTIFIER_POINTER (name));
6763 *no_add_attrs = true;
6765 else if (!pragma_interrupt)
6767 /* The sp_switch attribute only has meaning for interrupt functions. */
6768 warning ("`%s' attribute only applies to interrupt functions",
6769 IDENTIFIER_POINTER (name));
6770 *no_add_attrs = true;
6772 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
6774 /* The argument must be a constant string. */
6775 warning ("`%s' attribute argument not a string constant",
6776 IDENTIFIER_POINTER (name));
6777 *no_add_attrs = true;
6781 const char *s = ggc_strdup (TREE_STRING_POINTER (TREE_VALUE (args)));
6782 sp_switch = gen_rtx_SYMBOL_REF (VOIDmode, s);
6788 /* Handle an "trap_exit" attribute; arguments as in
6789 struct attribute_spec.handler. */
6791 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
6792 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
6794 if (TREE_CODE (*node) != FUNCTION_DECL)
6796 warning ("`%s' attribute only applies to functions",
6797 IDENTIFIER_POINTER (name));
6798 *no_add_attrs = true;
6800 else if (!pragma_interrupt)
6802 /* The trap_exit attribute only has meaning for interrupt functions. */
6803 warning ("`%s' attribute only applies to interrupt functions",
6804 IDENTIFIER_POINTER (name));
6805 *no_add_attrs = true;
6807 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
6809 /* The argument must be a constant integer. */
6810 warning ("`%s' attribute argument not an integer constant",
6811 IDENTIFIER_POINTER (name));
6812 *no_add_attrs = true;
6816 trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args));
6823 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
6824 tree name ATTRIBUTE_UNUSED,
6825 tree args ATTRIBUTE_UNUSED,
6826 int flags ATTRIBUTE_UNUSED,
6827 bool *no_add_attrs ATTRIBUTE_UNUSED)
6832 /* True if __attribute__((renesas)) or -mrenesas. */
6834 sh_attr_renesas_p (tree td)
6841 td = TREE_TYPE (td);
6842 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
6846 /* True if __attribute__((renesas)) or -mrenesas, for the current
6849 sh_cfun_attr_renesas_p (void)
6851 return sh_attr_renesas_p (current_function_decl);
6855 sh_cfun_interrupt_handler_p (void)
6857 return (lookup_attribute ("interrupt_handler",
6858 DECL_ATTRIBUTES (current_function_decl))
6862 /* ??? target_switches in toplev.c is static, hence we have to duplicate it. */
6865 const char *const name;
6867 const char *const description;
6869 sh_target_switches[] = TARGET_SWITCHES;
6870 #define target_switches sh_target_switches
6872 /* Like default_pch_valid_p, but take flag_mask into account. */
6874 sh_pch_valid_p (const void *data_p, size_t len)
6876 const char *data = (const char *)data_p;
6877 const char *flag_that_differs = NULL;
6881 = (SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | HARD_SH4_BIT | FPU_SINGLE_BIT
6882 | SH4_BIT | HITACHI_BIT | LITTLE_ENDIAN_BIT);
6884 /* -fpic and -fpie also usually make a PCH invalid. */
6885 if (data[0] != flag_pic)
6886 return _("created and used with different settings of -fpic");
6887 if (data[1] != flag_pie)
6888 return _("created and used with different settings of -fpie");
6891 /* Check target_flags. */
6892 memcpy (&old_flags, data, sizeof (target_flags));
6893 if (((old_flags ^ target_flags) & flag_mask) != 0)
6895 for (i = 0; i < ARRAY_SIZE (target_switches); i++)
6899 bits = target_switches[i].value;
6903 if ((target_flags & bits) != (old_flags & bits))
6905 flag_that_differs = target_switches[i].name;
6911 data += sizeof (target_flags);
6912 len -= sizeof (target_flags);
6914 /* Check string options. */
6915 #ifdef TARGET_OPTIONS
6916 for (i = 0; i < ARRAY_SIZE (target_options); i++)
6918 const char *str = *target_options[i].variable;
6922 l = strlen (str) + 1;
6923 if (len < l || memcmp (data, str, l) != 0)
6925 flag_that_differs = target_options[i].prefix;
6938 asprintf (&r, _("created and used with differing settings of `-m%s'"),
6941 return _("out of memory");
6946 /* Predicates used by the templates. */
6948 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
6949 Used only in general_movsrc_operand. */
6952 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
6964 /* Returns 1 if OP can be source of a simple move operation.
6965 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
6966 invalid as are subregs of system registers. */
6969 general_movsrc_operand (rtx op, enum machine_mode mode)
6971 if (GET_CODE (op) == MEM)
6973 rtx inside = XEXP (op, 0);
6974 if (GET_CODE (inside) == CONST)
6975 inside = XEXP (inside, 0);
6977 if (GET_CODE (inside) == LABEL_REF)
6980 if (GET_CODE (inside) == PLUS
6981 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
6982 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
6985 /* Only post inc allowed. */
6986 if (GET_CODE (inside) == PRE_DEC)
6990 if ((mode == QImode || mode == HImode)
6991 && (GET_CODE (op) == SUBREG
6992 && GET_CODE (XEXP (op, 0)) == REG
6993 && system_reg_operand (XEXP (op, 0), mode)))
6996 return general_operand (op, mode);
6999 /* Returns 1 if OP can be a destination of a move.
7000 Same as general_operand, but no preinc allowed. */
7003 general_movdst_operand (rtx op, enum machine_mode mode)
7005 /* Only pre dec allowed. */
7006 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
7009 return general_operand (op, mode);
7012 /* Returns 1 if OP is a normal arithmetic register. */
7015 arith_reg_operand (rtx op, enum machine_mode mode)
7017 if (register_operand (op, mode))
7021 if (GET_CODE (op) == REG)
7023 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
7024 regno = REGNO (SUBREG_REG (op));
7028 return (regno != T_REG && regno != PR_REG
7029 && ! TARGET_REGISTER_P (regno)
7030 && (regno != FPUL_REG || TARGET_SH4)
7031 && regno != MACH_REG && regno != MACL_REG);
7036 /* Like above, but for DImode destinations: forbid paradoxical DImode subregs,
7037 because this would lead to missing sign extensions when truncating from
7038 DImode to SImode. */
7040 arith_reg_dest (rtx op, enum machine_mode mode)
7042 if (mode == DImode && GET_CODE (op) == SUBREG
7043 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
7045 return arith_reg_operand (op, mode);
7049 int_gpr_dest (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7051 enum machine_mode op_mode = GET_MODE (op);
7053 if (GET_MODE_CLASS (op_mode) != MODE_INT
7054 || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
7056 if (! reload_completed)
7058 return true_regnum (op) <= LAST_GENERAL_REG;
7062 fp_arith_reg_operand (rtx op, enum machine_mode mode)
7064 if (register_operand (op, mode))
7068 if (GET_CODE (op) == REG)
7070 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
7071 regno = REGNO (SUBREG_REG (op));
7075 return (regno >= FIRST_PSEUDO_REGISTER
7076 || FP_REGISTER_P (regno));
7081 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
7084 arith_operand (rtx op, enum machine_mode mode)
7086 if (arith_reg_operand (op, mode))
7091 /* FIXME: We should be checking whether the CONST_INT fits in a
7092 CONST_OK_FOR_I16 here, but this causes reload_cse to crash when
7093 attempting to transform a sequence of two 64-bit sets of the
7094 same register from literal constants into a set and an add,
7095 when the difference is too wide for an add. */
7096 if (GET_CODE (op) == CONST_INT
7097 || EXTRA_CONSTRAINT_C16 (op))
7102 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (op)))
7108 /* Returns 1 if OP is a valid source operand for a compare insn. */
7111 arith_reg_or_0_operand (rtx op, enum machine_mode mode)
7113 if (arith_reg_operand (op, mode))
7116 if (EXTRA_CONSTRAINT_Z (op))
7122 /* Return 1 if OP is a valid source operand for an SHmedia operation
7123 that takes either a register or a 6-bit immediate. */
7126 shmedia_6bit_operand (rtx op, enum machine_mode mode)
7128 return (arith_reg_operand (op, mode)
7129 || (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I06 (INTVAL (op))));
7132 /* Returns 1 if OP is a valid source operand for a logical operation. */
7135 logical_operand (rtx op, enum machine_mode mode)
7137 if (arith_reg_operand (op, mode))
7142 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I10 (INTVAL (op)))
7147 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K08 (INTVAL (op)))
7154 and_operand (rtx op, enum machine_mode mode)
7156 if (logical_operand (op, mode))
7159 /* Check mshflo.l / mshflhi.l opportunities. */
7162 && GET_CODE (op) == CONST_INT
7163 && CONST_OK_FOR_J16 (INTVAL (op)))
7169 /* Nonzero if OP is a floating point value with value 0.0. */
7172 fp_zero_operand (rtx op)
7176 if (GET_MODE (op) != SFmode)
7179 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
7180 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
7183 /* Nonzero if OP is a floating point value with value 1.0. */
7186 fp_one_operand (rtx op)
7190 if (GET_MODE (op) != SFmode)
7193 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
7194 return REAL_VALUES_EQUAL (r, dconst1);
7197 /* For -m4 and -m4-single-only, mode switching is used. If we are
7198 compiling without -mfmovd, movsf_ie isn't taken into account for
7199 mode switching. We could check in machine_dependent_reorg for
7200 cases where we know we are in single precision mode, but there is
7201 interface to find that out during reload, so we must avoid
7202 choosing an fldi alternative during reload and thus failing to
7203 allocate a scratch register for the constant loading. */
7207 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
7211 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7213 enum rtx_code code = GET_CODE (op);
7214 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
7218 fpscr_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7220 return (GET_CODE (op) == REG && REGNO (op) == FPSCR_REG
7221 && GET_MODE (op) == PSImode);
7225 fpul_operand (rtx op, enum machine_mode mode)
7228 return fp_arith_reg_operand (op, mode);
7230 return (GET_CODE (op) == REG
7231 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
7232 && GET_MODE (op) == mode);
7236 symbol_ref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7238 return (GET_CODE (op) == SYMBOL_REF);
7241 /* Return the TLS type for TLS symbols, 0 for otherwise. */
7243 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7245 if (GET_CODE (op) != SYMBOL_REF)
7247 return SYMBOL_REF_TLS_MODEL (op);
7251 commutative_float_operator (rtx op, enum machine_mode mode)
7253 if (GET_MODE (op) != mode)
7255 switch (GET_CODE (op))
7267 noncommutative_float_operator (rtx op, enum machine_mode mode)
7269 if (GET_MODE (op) != mode)
7271 switch (GET_CODE (op))
7283 unary_float_operator (rtx op, enum machine_mode mode)
7285 if (GET_MODE (op) != mode)
7287 switch (GET_CODE (op))
7300 binary_float_operator (rtx op, enum machine_mode mode)
7302 if (GET_MODE (op) != mode)
7304 switch (GET_CODE (op))
7318 binary_logical_operator (rtx op, enum machine_mode mode)
7320 if (GET_MODE (op) != mode)
7322 switch (GET_CODE (op))
7335 equality_comparison_operator (rtx op, enum machine_mode mode)
7337 return ((mode == VOIDmode || GET_MODE (op) == mode)
7338 && (GET_CODE (op) == EQ || GET_CODE (op) == NE));
7341 int greater_comparison_operator (rtx op, enum machine_mode mode)
7343 if (mode != VOIDmode && GET_MODE (op) == mode)
7345 switch (GET_CODE (op))
7357 int less_comparison_operator (rtx op, enum machine_mode mode)
7359 if (mode != VOIDmode && GET_MODE (op) == mode)
7361 switch (GET_CODE (op))
7373 /* Accept pseudos and branch target registers. */
7375 target_reg_operand (rtx op, enum machine_mode mode)
7378 || GET_MODE (op) != DImode)
7381 if (GET_CODE (op) == SUBREG)
7384 if (GET_CODE (op) != REG)
7387 /* We must protect ourselves from matching pseudos that are virtual
7388 register, because they will eventually be replaced with hardware
7389 registers that aren't branch-target registers. */
7390 if (REGNO (op) > LAST_VIRTUAL_REGISTER
7391 || TARGET_REGISTER_P (REGNO (op)))
7397 /* Same as target_reg_operand, except that label_refs and symbol_refs
7398 are accepted before reload. */
7400 target_operand (rtx op, enum machine_mode mode)
7405 if ((GET_MODE (op) == DImode || GET_MODE (op) == VOIDmode)
7406 && EXTRA_CONSTRAINT_Csy (op))
7407 return ! reload_completed;
7409 return target_reg_operand (op, mode);
7413 mextr_bit_offset (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7417 if (GET_CODE (op) != CONST_INT)
7420 return i >= 1*8 && i <= 7*8 && (i & 7) == 0;
7424 extend_reg_operand (rtx op, enum machine_mode mode)
7426 return (GET_CODE (op) == TRUNCATE
7428 : arith_reg_operand) (op, mode);
7432 trunc_hi_operand (rtx op, enum machine_mode mode)
7434 enum machine_mode op_mode = GET_MODE (op);
7436 if (op_mode != SImode && op_mode != DImode
7437 && op_mode != V4HImode && op_mode != V2SImode)
7439 return extend_reg_operand (op, mode);
7443 extend_reg_or_0_operand (rtx op, enum machine_mode mode)
7445 return (GET_CODE (op) == TRUNCATE
7447 : arith_reg_or_0_operand) (op, mode);
7451 general_extend_operand (rtx op, enum machine_mode mode)
7453 return (GET_CODE (op) == TRUNCATE
7455 : nonimmediate_operand) (op, mode);
7459 inqhi_operand (rtx op, enum machine_mode mode)
7461 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
7464 /* Can't use true_regnum here because copy_cost wants to know about
7465 SECONDARY_INPUT_RELOAD_CLASS. */
7466 return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op));
7470 sh_rep_vec (rtx v, enum machine_mode mode)
7475 if ((GET_CODE (v) != CONST_VECTOR && GET_CODE (v) != PARALLEL)
7476 || (GET_MODE (v) != mode && mode != VOIDmode))
7478 i = XVECLEN (v, 0) - 2;
7479 x = XVECEXP (v, 0, i + 1);
7480 if (GET_MODE_UNIT_SIZE (mode) == 1)
7482 y = XVECEXP (v, 0, i);
7483 for (i -= 2 ; i >= 0; i -= 2)
7484 if (! rtx_equal_p (XVECEXP (v, 0, i + 1), x)
7485 || ! rtx_equal_p (XVECEXP (v, 0, i), y))
7490 if (XVECEXP (v, 0, i) != x)
7495 /* Determine if V is a constant vector matching MODE with only one element
7496 that is not a sign extension. Two byte-sized elements count as one. */
7498 sh_1el_vec (rtx v, enum machine_mode mode)
7501 int i, last, least, sign_ix;
7504 if (GET_CODE (v) != CONST_VECTOR
7505 || (GET_MODE (v) != mode && mode != VOIDmode))
7507 /* Determine numbers of last and of least significant elements. */
7508 last = XVECLEN (v, 0) - 1;
7509 least = TARGET_LITTLE_ENDIAN ? 0 : last;
7510 if (GET_CODE (XVECEXP (v, 0, least)) != CONST_INT)
7513 if (GET_MODE_UNIT_SIZE (mode) == 1)
7514 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
7515 if (GET_CODE (XVECEXP (v, 0, sign_ix)) != CONST_INT)
7517 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (v));
7518 sign = (INTVAL (XVECEXP (v, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
7519 ? constm1_rtx : const0_rtx);
7520 i = XVECLEN (v, 0) - 1;
7522 if (i != least && i != sign_ix && XVECEXP (v, 0, i) != sign)
7529 sh_const_vec (rtx v, enum machine_mode mode)
7533 if (GET_CODE (v) != CONST_VECTOR
7534 || (GET_MODE (v) != mode && mode != VOIDmode))
7536 i = XVECLEN (v, 0) - 1;
7538 if (GET_CODE (XVECEXP (v, 0, i)) != CONST_INT)
7543 /* Return the destination address of a branch. */
7546 branch_dest (rtx branch)
7548 rtx dest = SET_SRC (PATTERN (branch));
7551 if (GET_CODE (dest) == IF_THEN_ELSE)
7552 dest = XEXP (dest, 1);
7553 dest = XEXP (dest, 0);
7554 dest_uid = INSN_UID (dest);
7555 return INSN_ADDRESSES (dest_uid);
7558 /* Return nonzero if REG is not used after INSN.
7559 We assume REG is a reload reg, and therefore does
7560 not live past labels. It may live past calls or jumps though. */
7562 reg_unused_after (rtx reg, rtx insn)
7567 /* If the reg is set by this instruction, then it is safe for our
7568 case. Disregard the case where this is a store to memory, since
7569 we are checking a register used in the store address. */
7570 set = single_set (insn);
7571 if (set && GET_CODE (SET_DEST (set)) != MEM
7572 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7575 while ((insn = NEXT_INSN (insn)))
7577 code = GET_CODE (insn);
7580 /* If this is a label that existed before reload, then the register
7581 if dead here. However, if this is a label added by reorg, then
7582 the register may still be live here. We can't tell the difference,
7583 so we just ignore labels completely. */
7584 if (code == CODE_LABEL)
7589 if (code == JUMP_INSN)
7592 /* If this is a sequence, we must handle them all at once.
7593 We could have for instance a call that sets the target register,
7594 and an insn in a delay slot that uses the register. In this case,
7595 we must return 0. */
7596 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
7601 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7603 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
7604 rtx set = single_set (this_insn);
7606 if (GET_CODE (this_insn) == CALL_INSN)
7608 else if (GET_CODE (this_insn) == JUMP_INSN)
7610 if (INSN_ANNULLED_BRANCH_P (this_insn))
7615 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
7617 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7619 if (GET_CODE (SET_DEST (set)) != MEM)
7625 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
7630 else if (code == JUMP_INSN)
7633 else if (GET_RTX_CLASS (code) == 'i')
7635 rtx set = single_set (insn);
7637 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
7639 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7640 return GET_CODE (SET_DEST (set)) != MEM;
7641 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
7645 if (code == CALL_INSN && call_used_regs[REGNO (reg)])
7653 static GTY(()) rtx fpscr_rtx;
7655 get_fpscr_rtx (void)
7659 fpscr_rtx = gen_rtx (REG, PSImode, FPSCR_REG);
7660 REG_USERVAR_P (fpscr_rtx) = 1;
7661 mark_user_reg (fpscr_rtx);
7663 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
7664 mark_user_reg (fpscr_rtx);
7669 emit_sf_insn (rtx pat)
7675 emit_df_insn (rtx pat)
7681 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
7683 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
7687 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
7689 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
7694 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
7696 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
7700 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
7702 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
7706 /* ??? gcc does flow analysis strictly after common subexpression
7707 elimination. As a result, common subexpression elimination fails
7708 when there are some intervening statements setting the same register.
7709 If we did nothing about this, this would hurt the precision switching
7710 for SH4 badly. There is some cse after reload, but it is unable to
7711 undo the extra register pressure from the unused instructions, and
7712 it cannot remove auto-increment loads.
7714 A C code example that shows this flow/cse weakness for (at least) SH
7715 and sparc (as of gcc ss-970706) is this:
7729 So we add another pass before common subexpression elimination, to
7730 remove assignments that are dead due to a following assignment in the
7731 same basic block. */
7734 mark_use (rtx x, rtx *reg_set_block)
7740 code = GET_CODE (x);
7745 int regno = REGNO (x);
7746 int nregs = (regno < FIRST_PSEUDO_REGISTER
7747 ? HARD_REGNO_NREGS (regno, GET_MODE (x))
7751 reg_set_block[regno + nregs - 1] = 0;
7758 rtx dest = SET_DEST (x);
7760 if (GET_CODE (dest) == SUBREG)
7761 dest = SUBREG_REG (dest);
7762 if (GET_CODE (dest) != REG)
7763 mark_use (dest, reg_set_block);
7764 mark_use (SET_SRC (x), reg_set_block);
7771 const char *fmt = GET_RTX_FORMAT (code);
7773 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7776 mark_use (XEXP (x, i), reg_set_block);
7777 else if (fmt[i] == 'E')
7778 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7779 mark_use (XVECEXP (x, i, j), reg_set_block);
7786 static rtx get_free_reg (HARD_REG_SET);
7788 /* This function returns a register to use to load the address to load
7789 the fpscr from. Currently it always returns r1 or r7, but when we are
7790 able to use pseudo registers after combine, or have a better mechanism
7791 for choosing a register, it should be done here. */
7792 /* REGS_LIVE is the liveness information for the point for which we
7793 need this allocation. In some bare-bones exit blocks, r1 is live at the
7794 start. We can even have all of r0..r3 being live:
7795 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
7796 INSN before which new insns are placed with will clobber the register
7797 we return. If a basic block consists only of setting the return value
7798 register to a pseudo and using that register, the return value is not
7799 live before or after this block, yet we we'll insert our insns right in
7803 get_free_reg (HARD_REG_SET regs_live)
7805 if (! TEST_HARD_REG_BIT (regs_live, 1))
7806 return gen_rtx_REG (Pmode, 1);
7808 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
7809 there shouldn't be anything but a jump before the function end. */
7810 if (! TEST_HARD_REG_BIT (regs_live, 7))
7811 return gen_rtx_REG (Pmode, 7);
7816 /* This function will set the fpscr from memory.
7817 MODE is the mode we are setting it to. */
7819 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
7821 enum attr_fp_mode fp_mode = mode;
7822 rtx addr_reg = get_free_reg (regs_live);
7824 if (fp_mode == (enum attr_fp_mode) ACTUAL_NORMAL_MODE (FP_MODE))
7825 emit_insn (gen_fpu_switch1 (addr_reg));
7827 emit_insn (gen_fpu_switch0 (addr_reg));
7830 /* Is the given character a logical line separator for the assembler? */
7831 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
7832 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
7836 sh_insn_length_adjustment (rtx insn)
7838 /* Instructions with unfilled delay slots take up an extra two bytes for
7839 the nop in the delay slot. */
7840 if (((GET_CODE (insn) == INSN
7841 && GET_CODE (PATTERN (insn)) != USE
7842 && GET_CODE (PATTERN (insn)) != CLOBBER)
7843 || GET_CODE (insn) == CALL_INSN
7844 || (GET_CODE (insn) == JUMP_INSN
7845 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
7846 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
7847 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
7848 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
7851 /* SH2e has a bug that prevents the use of annulled branches, so if
7852 the delay slot is not filled, we'll have to put a NOP in it. */
7853 if (sh_cpu == CPU_SH2E
7854 && GET_CODE (insn) == JUMP_INSN
7855 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
7856 && GET_CODE (PATTERN (insn)) != ADDR_VEC
7857 && get_attr_type (insn) == TYPE_CBRANCH
7858 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
7861 /* sh-dsp parallel processing insn take four bytes instead of two. */
7863 if (GET_CODE (insn) == INSN)
7866 rtx body = PATTERN (insn);
7867 const char *template;
7869 int maybe_label = 1;
7871 if (GET_CODE (body) == ASM_INPUT)
7872 template = XSTR (body, 0);
7873 else if (asm_noperands (body) >= 0)
7875 = decode_asm_operands (body, NULL, NULL, NULL, NULL);
7884 while (c == ' ' || c == '\t');
7885 /* all sh-dsp parallel-processing insns start with p.
7886 The only non-ppi sh insn starting with p is pref.
7887 The only ppi starting with pr is prnd. */
7888 if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2))
7890 /* The repeat pseudo-insn expands two three insns, a total of
7891 six bytes in size. */
7892 else if ((c == 'r' || c == 'R')
7893 && ! strncasecmp ("epeat", template, 5))
7895 while (c && c != '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c))
7897 /* If this is a label, it is obviously not a ppi insn. */
7898 if (c == ':' && maybe_label)
7903 else if (c == '\'' || c == '"')
7908 maybe_label = c != ':';
7916 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
7917 isn't protected by a PIC unspec. */
7919 nonpic_symbol_mentioned_p (rtx x)
7921 register const char *fmt;
7924 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
7925 || GET_CODE (x) == PC)
7928 /* We don't want to look into the possible MEM location of a
7929 CONST_DOUBLE, since we're not going to use it, in general. */
7930 if (GET_CODE (x) == CONST_DOUBLE)
7933 if (GET_CODE (x) == UNSPEC
7934 && (XINT (x, 1) == UNSPEC_PIC
7935 || XINT (x, 1) == UNSPEC_GOT
7936 || XINT (x, 1) == UNSPEC_GOTOFF
7937 || XINT (x, 1) == UNSPEC_GOTPLT
7938 || XINT (x, 1) == UNSPEC_GOTTPOFF
7939 || XINT (x, 1) == UNSPEC_DTPOFF
7940 || XINT (x, 1) == UNSPEC_PLT))
7943 fmt = GET_RTX_FORMAT (GET_CODE (x));
7944 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
7950 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7951 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
7954 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
7961 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
7962 @GOTOFF in `reg'. */
7964 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
7967 if (tls_symbolic_operand (orig, Pmode))
7970 if (GET_CODE (orig) == LABEL_REF
7971 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
7974 reg = gen_reg_rtx (Pmode);
7976 emit_insn (gen_symGOTOFF2reg (reg, orig));
7979 else if (GET_CODE (orig) == SYMBOL_REF)
7982 reg = gen_reg_rtx (Pmode);
7984 emit_insn (gen_symGOT2reg (reg, orig));
7990 /* Mark the use of a constant in the literal table. If the constant
7991 has multiple labels, make it unique. */
7993 mark_constant_pool_use (rtx x)
7995 rtx insn, lab, pattern;
8000 switch (GET_CODE (x))
8010 /* Get the first label in the list of labels for the same constant
8011 and delete another labels in the list. */
8013 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
8015 if (GET_CODE (insn) != CODE_LABEL
8016 || LABEL_REFS (insn) != NEXT_INSN (insn))
8021 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
8022 INSN_DELETED_P (insn) = 1;
8024 /* Mark constants in a window. */
8025 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
8027 if (GET_CODE (insn) != INSN)
8030 pattern = PATTERN (insn);
8031 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
8034 switch (XINT (pattern, 1))
8036 case UNSPECV_CONST2:
8037 case UNSPECV_CONST4:
8038 case UNSPECV_CONST8:
8039 XVECEXP (pattern, 0, 1) = const1_rtx;
8041 case UNSPECV_WINDOW_END:
8042 if (XVECEXP (pattern, 0, 0) == x)
8045 case UNSPECV_CONST_END:
8055 /* Return true if it's possible to redirect BRANCH1 to the destination
8056 of an unconditional jump BRANCH2. We only want to do this if the
8057 resulting branch will have a short displacement. */
8059 sh_can_redirect_branch (rtx branch1, rtx branch2)
8061 if (flag_expensive_optimizations && simplejump_p (branch2))
8063 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
8067 for (distance = 0, insn = NEXT_INSN (branch1);
8068 insn && distance < 256;
8069 insn = PREV_INSN (insn))
8074 distance += get_attr_length (insn);
8076 for (distance = 0, insn = NEXT_INSN (branch1);
8077 insn && distance < 256;
8078 insn = NEXT_INSN (insn))
8083 distance += get_attr_length (insn);
8089 /* Return nonzero if register old_reg can be renamed to register new_reg. */
8091 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
8092 unsigned int new_reg)
8095 /* Interrupt functions can only use registers that have already been
8096 saved by the prologue, even if they would normally be
8099 if (sh_cfun_interrupt_handler_p () && !regs_ever_live[new_reg])
8105 /* Function to update the integer COST
8106 based on the relationship between INSN that is dependent on
8107 DEP_INSN through the dependence LINK. The default is to make no
8108 adjustment to COST. This can be used for example to specify to
8109 the scheduler that an output- or anti-dependence does not incur
8110 the same cost as a data-dependence. The return value should be
8111 the new value for COST. */
8113 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
8119 /* On SHmedia, if the dependence is an anti-dependence or
8120 output-dependence, there is no cost. */
8121 if (REG_NOTE_KIND (link) != 0)
8124 if (get_attr_is_mac_media (insn)
8125 && get_attr_is_mac_media (dep_insn))
8128 else if (REG_NOTE_KIND (link) == 0)
8130 enum attr_type dep_type, type;
8132 if (recog_memoized (insn) < 0
8133 || recog_memoized (dep_insn) < 0)
8136 dep_type = get_attr_type (dep_insn);
8137 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
8139 if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
8140 && (type = get_attr_type (insn)) != TYPE_CALL
8141 && type != TYPE_SFUNC)
8144 /* The only input for a call that is timing-critical is the
8145 function's address. */
8146 if (GET_CODE(insn) == CALL_INSN)
8148 rtx call = PATTERN (insn);
8150 if (GET_CODE (call) == PARALLEL)
8151 call = XVECEXP (call, 0 ,0);
8152 if (GET_CODE (call) == SET)
8153 call = SET_SRC (call);
8154 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
8155 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))
8158 /* Likewise, the most timing critical input for an sfuncs call
8159 is the function address. However, sfuncs typically start
8160 using their arguments pretty quickly.
8161 Assume a four cycle delay before they are needed. */
8162 /* All sfunc calls are parallels with at least four components.
8163 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
8164 else if (GET_CODE (PATTERN (insn)) == PARALLEL
8165 && XVECLEN (PATTERN (insn), 0) >= 4
8166 && (reg = sfunc_uses_reg (insn)))
8168 if (! reg_set_p (reg, dep_insn))
8171 /* When the preceding instruction loads the shift amount of
8172 the following SHAD/SHLD, the latency of the load is increased
8175 && get_attr_type (insn) == TYPE_DYN_SHIFT
8176 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
8177 && reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
8178 XEXP (SET_SRC (single_set(insn)),
8181 /* When an LS group instruction with a latency of less than
8182 3 cycles is followed by a double-precision floating-point
8183 instruction, FIPR, or FTRV, the latency of the first
8184 instruction is increased to 3 cycles. */
8186 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
8187 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
8189 /* The lsw register of a double-precision computation is ready one
8191 else if (reload_completed
8192 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
8193 && (use_pat = single_set (insn))
8194 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
8198 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
8199 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
8202 /* An anti-dependence penalty of two applies if the first insn is a double
8203 precision fadd / fsub / fmul. */
8204 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI
8205 && recog_memoized (dep_insn) >= 0
8206 && get_attr_type (dep_insn) == TYPE_DFP_ARITH
8207 /* A lot of alleged anti-flow dependences are fake,
8208 so check this one is real. */
8209 && flow_dependent_p (dep_insn, insn))
8216 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
8217 if DEP_INSN is anti-flow dependent on INSN. */
8219 flow_dependent_p (rtx insn, rtx dep_insn)
8221 rtx tmp = PATTERN (insn);
8223 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
8224 return tmp == NULL_RTX;
8227 /* A helper function for flow_dependent_p called through note_stores. */
8229 flow_dependent_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8231 rtx * pinsn = (rtx *) data;
8233 if (*pinsn && reg_referenced_p (x, *pinsn))
8237 /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
8238 'special function' patterns (type sfunc) that clobber pr, but that
8239 do not look like function calls to leaf_function_p. Hence we must
8240 do this extra check. */
8244 return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
8247 /* This Function returns nonzero if the DFA based scheduler interface
8248 is to be used. At present this is supported for the SH4 only. */
8250 sh_use_dfa_interface(void)
8252 if (TARGET_HARD_SH4)
8258 /* This function returns "2" to indicate dual issue for the SH4
8259 processor. To be used by the DFA pipeline description. */
8263 if (TARGET_SUPERSCALAR)
8269 /* SHmedia requires registers for branches, so we can't generate new
8270 branches past reload. */
8272 sh_cannot_modify_jumps_p (void)
8274 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
8278 sh_target_reg_class (void)
8280 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
8284 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
8286 return (shmedia_space_reserved_for_target_registers
8287 && (! after_prologue_epilogue_gen || TARGET_SAVE_ALL_TARGET_REGS));
8291 sh_ms_bitfield_layout_p (record_type)
8292 tree record_type ATTRIBUTE_UNUSED;
8294 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
8298 On the SH1..SH4, the trampoline looks like
8299 2 0002 D202 mov.l l2,r2
8300 1 0000 D301 mov.l l1,r3
8303 5 0008 00000000 l1: .long area
8304 6 000c 00000000 l2: .long function
8306 SH5 (compact) uses r1 instead of r3 for the static chain. */
8309 /* Emit RTL insns to initialize the variable parts of a trampoline.
8310 FNADDR is an RTX for the address of the function's pure code.
8311 CXT is an RTX for the static chain value for the function. */
8314 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
8316 if (TARGET_SHMEDIA64)
8321 rtx movi1 = GEN_INT (0xcc000010);
8322 rtx shori1 = GEN_INT (0xc8000010);
8325 /* The following trampoline works within a +- 128 KB range for cxt:
8326 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
8327 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
8328 gettr tr1,r1; blink tr0,r63 */
8329 /* Address rounding makes it hard to compute the exact bounds of the
8330 offset for this trampoline, but we have a rather generous offset
8331 range, so frame_offset should do fine as an upper bound. */
8332 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
8334 /* ??? could optimize this trampoline initialization
8335 by writing DImode words with two insns each. */
8336 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
8337 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
8338 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
8339 insn = gen_rtx_AND (DImode, insn, mask);
8340 /* Or in ptb/u .,tr1 pattern */
8341 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
8342 insn = force_operand (insn, NULL_RTX);
8343 insn = gen_lowpart (SImode, insn);
8344 emit_move_insn (gen_rtx_MEM (SImode, tramp), insn);
8345 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
8346 insn = gen_rtx_AND (DImode, insn, mask);
8347 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
8348 insn = gen_lowpart (SImode, insn);
8349 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), insn);
8350 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
8351 insn = gen_rtx_AND (DImode, insn, mask);
8352 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8353 insn = gen_lowpart (SImode, insn);
8354 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), insn);
8355 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
8356 insn = gen_rtx_AND (DImode, insn, mask);
8357 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8358 insn = gen_lowpart (SImode, insn);
8359 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
8361 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
8362 insn = gen_rtx_AND (DImode, insn, mask);
8363 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8364 insn = gen_lowpart (SImode, insn);
8365 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 16)),
8367 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 20)),
8368 GEN_INT (0x6bf10600));
8369 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 24)),
8370 GEN_INT (0x4415fc10));
8371 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 28)),
8372 GEN_INT (0x4401fff0));
8373 emit_insn (gen_ic_invalidate_line (tramp));
8376 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
8377 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
8379 tramp_templ = gen_datalabel_ref (tramp_templ);
8380 dst = gen_rtx_MEM (BLKmode, tramp);
8381 src = gen_rtx_MEM (BLKmode, tramp_templ);
8382 set_mem_align (dst, 256);
8383 set_mem_align (src, 64);
8384 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
8386 emit_move_insn (gen_rtx_MEM (Pmode, plus_constant (tramp, fixed_len)),
8388 emit_move_insn (gen_rtx_MEM (Pmode,
8389 plus_constant (tramp,
8391 + GET_MODE_SIZE (Pmode))),
8393 emit_insn (gen_ic_invalidate_line (tramp));
8396 else if (TARGET_SHMEDIA)
8398 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
8399 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
8400 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
8401 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
8402 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
8403 rotated 10 right, and higher 16 bit of every 32 selected. */
8405 = force_reg (V2HImode, (simplify_gen_subreg
8406 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
8407 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
8408 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
8410 tramp = force_reg (Pmode, tramp);
8411 fnaddr = force_reg (SImode, fnaddr);
8412 cxt = force_reg (SImode, cxt);
8413 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
8414 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
8416 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
8417 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
8418 emit_insn (gen_ashldi3_media (quad0, quad0, GEN_INT (2)));
8419 emit_move_insn (gen_rtx_MEM (DImode, tramp), quad0);
8420 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
8421 gen_rtx_SUBREG (V2HImode, cxt, 0),
8423 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
8424 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
8425 emit_insn (gen_ashldi3_media (cxtload, cxtload, GEN_INT (2)));
8426 if (TARGET_LITTLE_ENDIAN)
8428 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
8429 emit_insn (gen_mextr4 (quad2, cxtload, blink));
8433 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
8434 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
8436 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 8)), quad1);
8437 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), quad2);
8438 emit_insn (gen_ic_invalidate_line (tramp));
8441 else if (TARGET_SHCOMPACT)
8443 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
8446 emit_move_insn (gen_rtx_MEM (SImode, tramp),
8447 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
8449 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
8450 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
8452 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
8454 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
8458 if (TARGET_USERMODE)
8459 emit_library_call (function_symbol ("__ic_invalidate"),
8460 0, VOIDmode, 1, tramp, SImode);
8462 emit_insn (gen_ic_invalidate_line (tramp));
8466 /* FIXME: This is overly conservative. A SHcompact function that
8467 receives arguments ``by reference'' will have them stored in its
8468 own stack frame, so it must not pass pointers or references to
8469 these arguments to other functions by means of sibling calls. */
8471 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8474 && (! TARGET_SHCOMPACT
8475 || current_function_args_info.stack_regs == 0)
8476 && ! sh_cfun_interrupt_handler_p ());
8479 /* Machine specific built-in functions. */
8481 struct builtin_description
8483 const enum insn_code icode;
8484 const char *const name;
8488 /* describe number and signedness of arguments; arg[0] == result
8489 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
8490 static const char signature_args[][4] =
8492 #define SH_BLTIN_V2SI2 0
8494 #define SH_BLTIN_V4HI2 1
8496 #define SH_BLTIN_V2SI3 2
8498 #define SH_BLTIN_V4HI3 3
8500 #define SH_BLTIN_V8QI3 4
8502 #define SH_BLTIN_MAC_HISI 5
8504 #define SH_BLTIN_SH_HI 6
8506 #define SH_BLTIN_SH_SI 7
8508 #define SH_BLTIN_V4HI2V2SI 8
8510 #define SH_BLTIN_V4HI2V8QI 9
8512 #define SH_BLTIN_SISF 10
8514 #define SH_BLTIN_LDUA_L 11
8516 #define SH_BLTIN_LDUA_Q 12
8518 #define SH_BLTIN_STUA_L 13
8520 #define SH_BLTIN_STUA_Q 14
8522 #define SH_BLTIN_UDI 15
8524 #define SH_BLTIN_NUM_SHARED_SIGNATURES 16
8525 #define SH_BLTIN_2 16
8526 #define SH_BLTIN_SU 16
8528 #define SH_BLTIN_3 17
8529 #define SH_BLTIN_SUS 17
8531 #define SH_BLTIN_PSSV 18
8533 #define SH_BLTIN_XXUU 19
8534 #define SH_BLTIN_UUUU 19
8536 #define SH_BLTIN_PV 20
8539 /* mcmv: operands considered unsigned. */
8540 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
8541 /* mperm: control value considered unsigned int. */
8542 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
8543 /* mshards_q: returns signed short. */
8544 /* nsb: takes long long arg, returns unsigned char. */
8545 static const struct builtin_description bdesc[] =
8547 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
8548 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
8549 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
8550 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
8551 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
8552 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
8553 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
8555 { CODE_FOR_alloco32, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
8556 { CODE_FOR_alloco64, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
8558 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
8559 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
8560 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
8561 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
8562 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
8563 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
8564 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
8565 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
8566 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
8567 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
8568 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_UDI },
8569 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_UDI },
8570 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_UDI },
8571 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_UDI },
8572 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_UDI },
8573 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_UDI },
8574 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_UDI },
8575 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
8576 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
8577 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
8578 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
8579 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
8580 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
8581 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
8582 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
8583 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
8584 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
8585 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
8586 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
8587 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
8588 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
8589 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
8590 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
8591 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
8592 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
8593 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
8594 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
8595 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
8596 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
8597 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
8598 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
8599 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
8600 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
8601 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
8602 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
8603 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
8604 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
8605 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
8606 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
8607 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
8608 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
8609 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
8610 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
8611 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
8613 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
8614 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
8615 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
8616 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
8617 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
8618 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
8619 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
8620 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
8621 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
8622 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
8623 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
8624 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
8625 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
8626 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
8627 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
8628 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
8630 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
8631 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
8633 { CODE_FOR_prefetch32,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
8634 { CODE_FOR_prefetch64,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV }
8639 sh_media_init_builtins (void)
8641 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
8642 const struct builtin_description *d;
8644 memset (shared, 0, sizeof shared);
8645 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
8647 tree type, arg_type;
8648 int signature = d->signature;
8651 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
8652 type = shared[signature];
8655 int has_result = signature_args[signature][0] != 0;
8657 if (signature_args[signature][1] == 8
8658 && (insn_data[d->icode].operand[has_result].mode != Pmode))
8660 if (! TARGET_FPU_ANY
8661 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
8663 type = void_list_node;
8666 int arg = signature_args[signature][i];
8667 int opno = i - 1 + has_result;
8670 arg_type = ptr_type_node;
8672 arg_type = ((*lang_hooks.types.type_for_mode)
8673 (insn_data[d->icode].operand[opno].mode,
8678 arg_type = void_type_node;
8681 type = tree_cons (NULL_TREE, arg_type, type);
8683 type = build_function_type (arg_type, type);
8684 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
8685 shared[signature] = type;
8687 builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
8693 sh_init_builtins (void)
8696 sh_media_init_builtins ();
8699 /* Expand an expression EXP that calls a built-in function,
8700 with result going to TARGET if that's convenient
8701 (and in mode MODE if that's convenient).
8702 SUBTARGET may be used as the target for computing one of EXP's operands.
8703 IGNORE is nonzero if the value is to be ignored. */
8706 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8707 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
8709 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8710 tree arglist = TREE_OPERAND (exp, 1);
8711 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8712 const struct builtin_description *d = &bdesc[fcode];
8713 enum insn_code icode = d->icode;
8714 int signature = d->signature;
8715 enum machine_mode tmode = VOIDmode;
8720 if (signature_args[signature][0])
8725 tmode = insn_data[icode].operand[0].mode;
8727 || GET_MODE (target) != tmode
8728 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8729 target = gen_reg_rtx (tmode);
8735 for (i = 1; i <= 3; i++, nop++)
8738 enum machine_mode opmode, argmode;
8740 if (! signature_args[signature][i])
8742 arg = TREE_VALUE (arglist);
8743 if (arg == error_mark_node)
8745 arglist = TREE_CHAIN (arglist);
8746 opmode = insn_data[icode].operand[nop].mode;
8747 argmode = TYPE_MODE (TREE_TYPE (arg));
8748 if (argmode != opmode)
8749 arg = build1 (NOP_EXPR,
8750 (*lang_hooks.types.type_for_mode) (opmode, 0), arg);
8751 op[nop] = expand_expr (arg, NULL_RTX, opmode, 0);
8752 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
8753 op[nop] = copy_to_mode_reg (opmode, op[nop]);
8759 pat = (*insn_data[d->icode].genfun) (op[0]);
8762 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
8765 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
8768 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
8780 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
8782 rtx sel0 = const0_rtx;
8783 rtx sel1 = const1_rtx;
8784 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
8785 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
8787 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
8788 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
8792 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
8794 rtx sel0 = const0_rtx;
8795 rtx sel1 = const1_rtx;
8796 rtx (*fn) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx)
8798 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
8800 emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0, sel1));
8801 emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1, sel0));
8804 /* Return the class of registers for which a mode change from FROM to TO
8807 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
8808 enum reg_class class)
8810 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
8812 if (TARGET_LITTLE_ENDIAN)
8814 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
8815 return reg_classes_intersect_p (DF_REGS, class);
8819 if (GET_MODE_SIZE (from) < 8)
8820 return reg_classes_intersect_p (DF_HI_REGS, class);
8827 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
8828 that label is used. */
8831 sh_mark_label (rtx address, int nuses)
8833 if (GOTOFF_P (address))
8835 /* Extract the label or symbol. */
8836 address = XEXP (address, 0);
8837 if (GET_CODE (address) == PLUS)
8838 address = XEXP (address, 0);
8839 address = XVECEXP (address, 0, 0);
8841 if (GET_CODE (address) == LABEL_REF
8842 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
8843 LABEL_NUSES (XEXP (address, 0)) += nuses;
8846 /* Compute extra cost of moving data between one register class
8849 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
8850 uses this information. Hence, the general register <-> floating point
8851 register information here is not used for SFmode. */
8854 sh_register_move_cost (enum machine_mode mode,
8855 enum reg_class srcclass, enum reg_class dstclass)
8857 if (dstclass == T_REGS || dstclass == PR_REGS)
8860 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
8863 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
8864 && REGCLASS_HAS_FP_REG (srcclass)
8865 && REGCLASS_HAS_FP_REG (dstclass))
8868 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
8869 || (dstclass== MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
8872 if ((REGCLASS_HAS_FP_REG (dstclass)
8873 && REGCLASS_HAS_GENERAL_REG (srcclass))
8874 || (REGCLASS_HAS_GENERAL_REG (dstclass)
8875 && REGCLASS_HAS_FP_REG (srcclass)))
8876 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
8877 * ((GET_MODE_SIZE (mode) + 7) / 8U));
8879 if ((dstclass == FPUL_REGS
8880 && REGCLASS_HAS_GENERAL_REG (srcclass))
8881 || (srcclass == FPUL_REGS
8882 && REGCLASS_HAS_GENERAL_REG (dstclass)))
8885 if ((dstclass == FPUL_REGS
8886 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
8887 || (srcclass == FPUL_REGS
8888 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
8891 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
8892 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
8895 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
8896 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
8901 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
8902 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
8903 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
8905 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
8908 /* Like register_operand, but take into account that SHMEDIA can use
8909 the constant zero like a general register. */
8911 sh_register_operand (rtx op, enum machine_mode mode)
8913 if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
8915 return register_operand (op, mode);
8919 cmpsi_operand (rtx op, enum machine_mode mode)
8921 if (GET_CODE (op) == REG && REGNO (op) == T_REG
8922 && GET_MODE (op) == SImode)
8924 return arith_operand (op, mode);
8927 static rtx emit_load_ptr (rtx, rtx);
8930 emit_load_ptr (rtx reg, rtx addr)
8932 rtx mem = gen_rtx_MEM (ptr_mode, addr);
8934 if (Pmode != ptr_mode)
8935 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
8936 return emit_move_insn (reg, mem);
8940 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8941 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8944 CUMULATIVE_ARGS cum;
8945 int structure_value_byref = 0;
8946 rtx this, this_value, sibcall, insns, funexp;
8947 tree funtype = TREE_TYPE (function);
8948 int simple_add = CONST_OK_FOR_ADD (delta);
8950 rtx scratch0, scratch1, scratch2;
8952 reload_completed = 1;
8953 epilogue_completed = 1;
8955 current_function_uses_only_leaf_regs = 1;
8957 emit_note (NOTE_INSN_PROLOGUE_END);
8959 /* Find the "this" pointer. We have such a wide range of ABIs for the
8960 SH that it's best to do this completely machine independently.
8961 "this" is passed as first argument, unless a structure return pointer
8962 comes first, in which case "this" comes second. */
8963 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0);
8964 #ifndef PCC_STATIC_STRUCT_RETURN
8965 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8966 structure_value_byref = 1;
8967 #endif /* not PCC_STATIC_STRUCT_RETURN */
8968 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
8970 tree ptype = build_pointer_type (TREE_TYPE (funtype));
8972 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
8974 this = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
8976 /* For SHcompact, we only have r0 for a scratch register: r1 is the
8977 static chain pointer (even if you can't have nested virtual functions
8978 right now, someone might implement them sometime), and the rest of the
8979 registers are used for argument passing, are callee-saved, or reserved. */
8980 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
8983 scratch1 = gen_rtx_REG (ptr_mode, 1);
8984 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
8985 pointing where to return struct values. */
8986 scratch2 = gen_rtx_REG (Pmode, 3);
8988 else if (TARGET_SHMEDIA)
8990 scratch1 = gen_rtx_REG (ptr_mode, 21);
8991 scratch2 = gen_rtx_REG (Pmode, TR0_REG);
8994 this_value = plus_constant (this, delta);
8996 && (simple_add || scratch0 != scratch1)
8997 && strict_memory_address_p (ptr_mode, this_value))
8999 emit_load_ptr (scratch0, this_value);
9005 else if (simple_add)
9006 emit_move_insn (this, this_value);
9009 emit_move_insn (scratch1, GEN_INT (delta));
9010 emit_insn (gen_add2_insn (this, scratch1));
9018 emit_load_ptr (scratch0, this);
9020 offset_addr = plus_constant (scratch0, vcall_offset);
9021 if (strict_memory_address_p (ptr_mode, offset_addr))
9023 else if (! TARGET_SH5)
9025 /* scratch0 != scratch1, and we have indexed loads. Get better
9026 schedule by loading the offset into r1 and using an indexed
9027 load - then the load of r1 can issue before the load from
9028 (this + delta) finishes. */
9029 emit_move_insn (scratch1, GEN_INT (vcall_offset));
9030 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
9032 else if (CONST_OK_FOR_ADD (vcall_offset))
9034 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
9035 offset_addr = scratch0;
9037 else if (scratch0 != scratch1)
9039 emit_move_insn (scratch1, GEN_INT (vcall_offset));
9040 emit_insn (gen_add2_insn (scratch0, scratch1));
9041 offset_addr = scratch0;
9044 abort (); /* FIXME */
9045 emit_load_ptr (scratch0, offset_addr);
9047 if (Pmode != ptr_mode)
9048 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
9049 emit_insn (gen_add2_insn (this, scratch0));
9052 /* Generate a tail call to the target function. */
9053 if (! TREE_USED (function))
9055 assemble_external (function);
9056 TREE_USED (function) = 1;
9058 funexp = XEXP (DECL_RTL (function), 0);
9059 emit_move_insn (scratch2, funexp);
9060 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
9061 sibcall = emit_call_insn (gen_sibcall (funexp, const0_rtx, NULL_RTX));
9062 SIBLING_CALL_P (sibcall) = 1;
9063 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this);
9066 /* Run just enough of rest_of_compilation to do scheduling and get
9067 the insns emitted. Note that use_thunk calls
9068 assemble_start_function and assemble_end_function. */
9070 insn_locators_initialize ();
9071 insns = get_insns ();
9073 if (optimize > 0 && flag_schedule_insns_after_reload)
9076 find_basic_blocks (insns, max_reg_num (), rtl_dump_file);
9077 life_analysis (insns, rtl_dump_file, PROP_FINAL);
9079 split_all_insns (1);
9081 schedule_insns (rtl_dump_file);
9086 if (optimize > 0 && flag_delayed_branch)
9087 dbr_schedule (insns, rtl_dump_file);
9088 shorten_branches (insns);
9089 final_start_function (insns, file, 1);
9090 final (insns, file, 1, 0);
9091 final_end_function ();
9093 if (optimize > 0 && flag_schedule_insns_after_reload)
9095 /* Release all memory allocated by flow. */
9096 free_basic_block_vars (0);
9098 /* Release all memory held by regsets now. */
9099 regset_release_memory ();
9102 reload_completed = 0;
9103 epilogue_completed = 0;
9108 function_symbol (const char *name)
9110 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
9111 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
9115 /* Find the number of a general purpose register in S. */
9117 scavenge_reg (HARD_REG_SET *s)
9120 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
9121 if (TEST_HARD_REG_BIT (*s, r))
9127 sh_get_pr_initial_val (void)
9131 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
9132 PR register on SHcompact, because it might be clobbered by the prologue.
9133 We check first if that is known to be the case. */
9134 if (TARGET_SHCOMPACT
9135 && ((current_function_args_info.call_cookie
9136 & ~ CALL_COOKIE_RET_TRAMP (1))
9137 || current_function_has_nonlocal_label))
9138 return gen_rtx_MEM (SImode, return_address_pointer_rtx);
9140 /* If we haven't finished rtl generation, there might be a nonlocal label
9141 that we haven't seen yet.
9142 ??? get_hard_reg_initial_val fails if it is called while no_new_pseudos
9143 is set, unless it has been called before for the same register. And even
9144 then, we end in trouble if we didn't use the register in the same
9145 basic block before. So call get_hard_reg_initial_val now and wrap it
9146 in an unspec if we might need to replace it. */
9147 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
9148 combine can put the pseudo returned by get_hard_reg_initial_val into
9149 instructions that need a general purpose registers, which will fail to
9150 be recognized when the pseudo becomes allocated to PR. */
9152 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9154 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
9159 sh_expand_t_scc (enum rtx_code code, rtx target)
9161 rtx result = target;
9164 if (GET_CODE (sh_compare_op0) != REG || REGNO (sh_compare_op0) != T_REG
9165 || GET_CODE (sh_compare_op1) != CONST_INT)
9167 if (GET_CODE (result) != REG)
9168 result = gen_reg_rtx (SImode);
9169 val = INTVAL (sh_compare_op1);
9170 if ((code == EQ && val == 1) || (code == NE && val == 0))
9171 emit_insn (gen_movt (result));
9172 else if ((code == EQ && val == 0) || (code == NE && val == 1))
9174 emit_insn (gen_rtx_CLOBBER (VOIDmode, result));
9175 emit_insn (gen_subc (result, result, result));
9176 emit_insn (gen_addsi3 (result, result, GEN_INT (1)));
9178 else if (code == EQ || code == NE)
9179 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
9182 if (result != target)
9183 emit_move_insn (target, result);
9187 /* INSN is an sfunc; return the rtx that describes the address used. */
9189 extract_sfunc_addr (rtx insn)
9191 rtx pattern, part = NULL_RTX;
9194 pattern = PATTERN (insn);
9195 len = XVECLEN (pattern, 0);
9196 for (i = 0; i < len; i++)
9198 part = XVECEXP (pattern, 0, i);
9199 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
9200 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
9201 return XEXP (part, 0);
9203 if (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE)
9204 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
9208 /* Verify that the register in use_sfunc_addr still agrees with the address
9209 used in the sfunc. This prevents fill_slots_from_thread from changing
9211 INSN is the use_sfunc_addr instruction, and REG is the register it
9214 check_use_sfunc_addr (rtx insn, rtx reg)
9216 /* Search for the sfunc. It should really come right after INSN. */
9217 while ((insn = NEXT_INSN (insn)))
9219 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN)
9221 if (! INSN_P (insn))
9224 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
9225 insn = XVECEXP (PATTERN (insn), 0, 0);
9226 if (GET_CODE (PATTERN (insn)) != PARALLEL
9227 || get_attr_type (insn) != TYPE_SFUNC)
9229 return rtx_equal_p (extract_sfunc_addr (insn), reg);