1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "insn-config.h"
35 #include "hard-reg-set.h"
37 #include "insn-attr.h"
40 #include "integrate.h"
44 #include "target-def.h"
46 #include "langhooks.h"
47 #include "basic-block.h"
49 #include "cfglayout.h"
51 #include "sched-int.h"
56 #include "alloc-pool.h"
57 #include "tm-constrs.h"
60 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
62 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
63 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
65 /* These are some macros to abstract register modes. */
66 #define CONST_OK_FOR_ADD(size) \
67 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
68 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
69 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
70 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
72 /* Used to simplify the logic below. Find the attributes wherever
74 #define SH_ATTRIBUTES(decl) \
75 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
76 : DECL_ATTRIBUTES (decl) \
77 ? (DECL_ATTRIBUTES (decl)) \
78 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
80 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
81 int current_function_interrupt;
83 tree sh_deferred_function_attributes;
84 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
86 /* Global variables for machine-dependent things. */
88 /* Which cpu are we scheduling for. */
89 enum processor_type sh_cpu;
91 /* Definitions used in ready queue reordering for first scheduling pass. */
93 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
94 static short *regmode_weight[2];
96 /* Total SFmode and SImode weights of scheduled insns. */
97 static int curr_regmode_pressure[2];
99 /* Number of r0 life regions. */
100 static int r0_life_regions;
102 /* If true, skip cycles for Q -> R movement. */
103 static int skip_cycles = 0;
105 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
106 and returned from sh_reorder2. */
107 static short cached_can_issue_more;
109 /* Provides the class number of the smallest class containing
112 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
114 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
147 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
148 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
149 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
150 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
151 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
152 GENERAL_REGS, GENERAL_REGS,
155 char sh_register_names[FIRST_PSEUDO_REGISTER] \
156 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
158 char sh_additional_register_names[ADDREGNAMES_SIZE] \
159 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
160 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
162 int assembler_dialect;
164 static bool shmedia_space_reserved_for_target_registers;
166 static bool sh_handle_option (size_t, const char *, int);
167 static void split_branches (rtx);
168 static int branch_dest (rtx);
169 static void force_into (rtx, rtx);
170 static void print_slot (rtx);
171 static rtx add_constant (rtx, enum machine_mode, rtx);
172 static void dump_table (rtx, rtx);
173 static int hi_const (rtx);
174 static int broken_move (rtx);
175 static int mova_p (rtx);
176 static rtx find_barrier (int, rtx, rtx);
177 static int noncall_uses_reg (rtx, rtx, rtx *);
178 static rtx gen_block_redirect (rtx, int, int);
179 static void sh_reorg (void);
180 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
181 static rtx frame_insn (rtx);
182 static rtx push (int);
183 static void pop (int);
184 static void push_regs (HARD_REG_SET *, int);
185 static int calc_live_regs (HARD_REG_SET *);
186 static HOST_WIDE_INT rounded_frame_size (int);
187 static rtx mark_constant_pool_use (rtx);
188 EXPORTED_CONST struct attribute_spec sh_attribute_table[];
189 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
190 static tree sh_handle_resbank_handler_attribute (tree *, tree,
192 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
194 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
195 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
196 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
197 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
198 static void sh_insert_attributes (tree, tree *);
199 static const char *sh_check_pch_target_flags (int);
200 static int sh_adjust_cost (rtx, rtx, rtx, int);
201 static int sh_issue_rate (void);
202 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
203 static short find_set_regmode_weight (rtx, enum machine_mode);
204 static short find_insn_regmode_weight (rtx, enum machine_mode);
205 static void find_regmode_weight (basic_block, enum machine_mode);
206 static int find_r0_life_regions (basic_block);
207 static void sh_md_init_global (FILE *, int, int);
208 static void sh_md_finish_global (FILE *, int);
209 static int rank_for_reorder (const void *, const void *);
210 static void swap_reorder (rtx *, int);
211 static void ready_reorder (rtx *, int);
212 static short high_pressure (enum machine_mode);
213 static int sh_reorder (FILE *, int, rtx *, int *, int);
214 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
215 static void sh_md_init (FILE *, int, int);
216 static int sh_variable_issue (FILE *, int, rtx, int);
218 static bool sh_function_ok_for_sibcall (tree, tree);
220 static bool sh_cannot_modify_jumps_p (void);
221 static enum reg_class sh_target_reg_class (void);
222 static bool sh_optimize_target_register_callee_saved (bool);
223 static bool sh_ms_bitfield_layout_p (const_tree);
225 static void sh_init_builtins (void);
226 static void sh_media_init_builtins (void);
227 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
228 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
229 static void sh_file_start (void);
230 static int flow_dependent_p (rtx, rtx);
231 static void flow_dependent_p_1 (rtx, const_rtx, void *);
232 static int shiftcosts (rtx);
233 static int andcosts (rtx);
234 static int addsubcosts (rtx);
235 static int multcosts (rtx);
236 static bool unspec_caller_rtx_p (rtx);
237 static bool sh_cannot_copy_insn_p (rtx);
238 static bool sh_rtx_costs (rtx, int, int, int *, bool);
239 static int sh_address_cost (rtx, bool);
240 static int sh_pr_n_sets (void);
241 static rtx sh_allocate_initial_value (rtx);
242 static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);
243 static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
244 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
245 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
246 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
247 static int scavenge_reg (HARD_REG_SET *s);
248 struct save_schedule_s;
249 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
250 struct save_schedule_s *, int);
252 static rtx sh_struct_value_rtx (tree, int);
253 static bool sh_return_in_memory (const_tree, const_tree);
254 static rtx sh_builtin_saveregs (void);
255 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
256 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
257 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
258 static tree sh_build_builtin_va_list (void);
259 static void sh_va_start (tree, rtx);
260 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
261 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
263 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
265 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
267 static bool sh_scalar_mode_supported_p (enum machine_mode);
268 static int sh_dwarf_calling_convention (const_tree);
269 static void sh_encode_section_info (tree, rtx, int);
270 static int sh2a_function_vector_p (tree);
273 /* Initialize the GCC target structure. */
274 #undef TARGET_ATTRIBUTE_TABLE
275 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
277 /* The next two are used for debug info when compiling with -gdwarf. */
278 #undef TARGET_ASM_UNALIGNED_HI_OP
279 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
280 #undef TARGET_ASM_UNALIGNED_SI_OP
281 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
283 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
284 #undef TARGET_ASM_UNALIGNED_DI_OP
285 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
286 #undef TARGET_ASM_ALIGNED_DI_OP
287 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
289 #undef TARGET_ASM_FUNCTION_EPILOGUE
290 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
292 #undef TARGET_ASM_OUTPUT_MI_THUNK
293 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
295 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
296 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
298 #undef TARGET_ASM_FILE_START
299 #define TARGET_ASM_FILE_START sh_file_start
300 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
301 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
303 #undef TARGET_DEFAULT_TARGET_FLAGS
304 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
305 #undef TARGET_HANDLE_OPTION
306 #define TARGET_HANDLE_OPTION sh_handle_option
308 #undef TARGET_INSERT_ATTRIBUTES
309 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
311 #undef TARGET_SCHED_ADJUST_COST
312 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
314 #undef TARGET_SCHED_ISSUE_RATE
315 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
317 /* The next 5 hooks have been implemented for reenabling sched1. With the
318 help of these macros we are limiting the movement of insns in sched1 to
319 reduce the register pressure. The overall idea is to keep count of SImode
320 and SFmode regs required by already scheduled insns. When these counts
321 cross some threshold values; give priority to insns that free registers.
322 The insn that frees registers is most likely to be the insn with lowest
323 LUID (original insn order); but such an insn might be there in the stalled
324 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
325 upto a max of 8 cycles so that such insns may move from Q -> R.
327 The description of the hooks are as below:
329 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
330 scheduler; it is called inside the sched_init function just after
331 find_insn_reg_weights function call. It is used to calculate the SImode
332 and SFmode weights of insns of basic blocks; much similar to what
333 find_insn_reg_weights does.
334 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
336 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
337 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
340 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
341 high; reorder the ready queue so that the insn with lowest LUID will be
344 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
345 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
347 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
348 can be returned from TARGET_SCHED_REORDER2.
350 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
352 #undef TARGET_SCHED_DFA_NEW_CYCLE
353 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
355 #undef TARGET_SCHED_INIT_GLOBAL
356 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
358 #undef TARGET_SCHED_FINISH_GLOBAL
359 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
361 #undef TARGET_SCHED_VARIABLE_ISSUE
362 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
364 #undef TARGET_SCHED_REORDER
365 #define TARGET_SCHED_REORDER sh_reorder
367 #undef TARGET_SCHED_REORDER2
368 #define TARGET_SCHED_REORDER2 sh_reorder2
370 #undef TARGET_SCHED_INIT
371 #define TARGET_SCHED_INIT sh_md_init
373 #undef TARGET_LEGITIMIZE_ADDRESS
374 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
376 #undef TARGET_CANNOT_MODIFY_JUMPS_P
377 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
378 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
379 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
380 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
381 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
382 sh_optimize_target_register_callee_saved
384 #undef TARGET_MS_BITFIELD_LAYOUT_P
385 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
387 #undef TARGET_INIT_BUILTINS
388 #define TARGET_INIT_BUILTINS sh_init_builtins
389 #undef TARGET_EXPAND_BUILTIN
390 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
392 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
393 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
395 #undef TARGET_CANNOT_COPY_INSN_P
396 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
397 #undef TARGET_RTX_COSTS
398 #define TARGET_RTX_COSTS sh_rtx_costs
399 #undef TARGET_ADDRESS_COST
400 #define TARGET_ADDRESS_COST sh_address_cost
401 #undef TARGET_ALLOCATE_INITIAL_VALUE
402 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
404 #undef TARGET_MACHINE_DEPENDENT_REORG
405 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
407 #undef TARGET_DWARF_REGISTER_SPAN
408 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
411 #undef TARGET_HAVE_TLS
412 #define TARGET_HAVE_TLS true
415 #undef TARGET_PROMOTE_PROTOTYPES
416 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
417 #undef TARGET_PROMOTE_FUNCTION_ARGS
418 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
419 #undef TARGET_PROMOTE_FUNCTION_RETURN
420 #define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
422 #undef TARGET_STRUCT_VALUE_RTX
423 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
424 #undef TARGET_RETURN_IN_MEMORY
425 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
427 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
428 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
429 #undef TARGET_SETUP_INCOMING_VARARGS
430 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
431 #undef TARGET_STRICT_ARGUMENT_NAMING
432 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
433 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
434 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
435 #undef TARGET_MUST_PASS_IN_STACK
436 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
437 #undef TARGET_PASS_BY_REFERENCE
438 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
439 #undef TARGET_CALLEE_COPIES
440 #define TARGET_CALLEE_COPIES sh_callee_copies
441 #undef TARGET_ARG_PARTIAL_BYTES
442 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
444 #undef TARGET_BUILD_BUILTIN_VA_LIST
445 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
446 #undef TARGET_EXPAND_BUILTIN_VA_START
447 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
448 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
449 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
451 #undef TARGET_SCALAR_MODE_SUPPORTED_P
452 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
453 #undef TARGET_VECTOR_MODE_SUPPORTED_P
454 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
456 #undef TARGET_CHECK_PCH_TARGET_FLAGS
457 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
459 #undef TARGET_DWARF_CALLING_CONVENTION
460 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
462 /* Return regmode weight for insn. */
463 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
465 /* Return current register pressure for regmode. */
466 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
468 #undef TARGET_ENCODE_SECTION_INFO
469 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
473 #undef TARGET_ENCODE_SECTION_INFO
474 #define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
475 #undef TARGET_STRIP_NAME_ENCODING
476 #define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
477 #undef TARGET_CXX_IMPORT_EXPORT_CLASS
478 #define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
482 #undef TARGET_SECONDARY_RELOAD
483 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
485 #undef TARGET_LEGITIMATE_ADDRESS_P
486 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
488 /* Machine-specific symbol_ref flags. */
489 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
491 struct gcc_target targetm = TARGET_INITIALIZER;
493 /* Implement TARGET_HANDLE_OPTION. */
496 sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
497 int value ATTRIBUTE_UNUSED)
502 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
506 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
510 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
514 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
518 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
521 case OPT_m2a_single_only:
522 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
526 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
530 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
534 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
541 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
545 case OPT_m4_100_nofpu:
546 case OPT_m4_200_nofpu:
547 case OPT_m4_300_nofpu:
551 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
555 case OPT_m4_100_single:
556 case OPT_m4_200_single:
557 case OPT_m4_300_single:
558 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
561 case OPT_m4_single_only:
562 case OPT_m4_100_single_only:
563 case OPT_m4_200_single_only:
564 case OPT_m4_300_single_only:
565 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
569 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
574 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
578 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
581 case OPT_m4a_single_only:
582 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
586 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
589 case OPT_m5_32media_nofpu:
590 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
594 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
597 case OPT_m5_64media_nofpu:
598 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
602 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
605 case OPT_m5_compact_nofpu:
606 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
614 /* Set default optimization options. */
616 sh_optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
620 flag_omit_frame_pointer = 2;
622 sh_div_str = "inv:minlat";
626 target_flags |= MASK_SMALLCODE;
627 sh_div_str = SH_DIV_STR_FOR_SIZE ;
630 TARGET_CBRANCHDI4 = 1;
631 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options
632 haven't been parsed yet, hence we'd read only the default.
633 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so
634 it's OK to always set flag_branch_target_load_optimize. */
637 flag_branch_target_load_optimize = 1;
639 target_flags |= MASK_SAVE_ALL_TARGET_REGS;
641 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE
642 here, so leave it to OVERRIDE_OPTIONS to set
643 flag_finite_math_only. We set it to 2 here so we know if the user
644 explicitly requested this to be on or off. */
645 flag_finite_math_only = 2;
646 /* If flag_schedule_insns is 1, we set it to 2 here so we know if
647 the user explicitly requested this to be on or off. */
648 if (flag_schedule_insns > 0)
649 flag_schedule_insns = 2;
651 set_param_value ("simultaneous-prefetches", 2);
654 /* Implement OVERRIDE_OPTIONS macro. Validate and override various
655 options, and do some machine dependent initialization. */
657 sh_override_options (void)
661 SUBTARGET_OVERRIDE_OPTIONS;
662 if (flag_finite_math_only == 2)
663 flag_finite_math_only
664 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;
665 if (TARGET_SH2E && !flag_finite_math_only)
666 target_flags |= MASK_IEEE;
667 sh_cpu = PROCESSOR_SH1;
668 assembler_dialect = 0;
670 sh_cpu = PROCESSOR_SH2;
672 sh_cpu = PROCESSOR_SH2E;
675 sh_cpu = PROCESSOR_SH2A;
676 if (TARGET_SH2A_DOUBLE)
677 target_flags |= MASK_FMOVD;
680 sh_cpu = PROCESSOR_SH3;
682 sh_cpu = PROCESSOR_SH3E;
685 assembler_dialect = 1;
686 sh_cpu = PROCESSOR_SH4;
688 if (TARGET_SH4A_ARCH)
690 assembler_dialect = 1;
691 sh_cpu = PROCESSOR_SH4A;
695 sh_cpu = PROCESSOR_SH5;
696 target_flags |= MASK_ALIGN_DOUBLE;
697 if (TARGET_SHMEDIA_FPU)
698 target_flags |= MASK_FMOVD;
701 /* There are no delay slots on SHmedia. */
702 flag_delayed_branch = 0;
703 /* Relaxation isn't yet supported for SHmedia */
704 target_flags &= ~MASK_RELAX;
705 /* After reload, if conversion does little good but can cause
707 - find_if_block doesn't do anything for SH because we don't
708 have conditional execution patterns. (We use conditional
709 move patterns, which are handled differently, and only
711 - find_cond_trap doesn't do anything for the SH because we
712 don't have conditional traps.
713 - find_if_case_1 uses redirect_edge_and_branch_force in
714 the only path that does an optimization, and this causes
715 an ICE when branch targets are in registers.
716 - find_if_case_2 doesn't do anything for the SHmedia after
717 reload except when it can redirect a tablejump - and
718 that's rather rare. */
719 flag_if_conversion2 = 0;
720 if (! strcmp (sh_div_str, "call"))
721 sh_div_strategy = SH_DIV_CALL;
722 else if (! strcmp (sh_div_str, "call2"))
723 sh_div_strategy = SH_DIV_CALL2;
724 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)
725 sh_div_strategy = SH_DIV_FP;
726 else if (! strcmp (sh_div_str, "inv"))
727 sh_div_strategy = SH_DIV_INV;
728 else if (! strcmp (sh_div_str, "inv:minlat"))
729 sh_div_strategy = SH_DIV_INV_MINLAT;
730 else if (! strcmp (sh_div_str, "inv20u"))
731 sh_div_strategy = SH_DIV_INV20U;
732 else if (! strcmp (sh_div_str, "inv20l"))
733 sh_div_strategy = SH_DIV_INV20L;
734 else if (! strcmp (sh_div_str, "inv:call2"))
735 sh_div_strategy = SH_DIV_INV_CALL2;
736 else if (! strcmp (sh_div_str, "inv:call"))
737 sh_div_strategy = SH_DIV_INV_CALL;
738 else if (! strcmp (sh_div_str, "inv:fp"))
741 sh_div_strategy = SH_DIV_INV_FP;
743 sh_div_strategy = SH_DIV_INV;
745 TARGET_CBRANCHDI4 = 0;
746 /* Assembler CFI isn't yet fully supported for SHmedia. */
747 flag_dwarf2_cfi_asm = 0;
752 /* Only the sh64-elf assembler fully supports .quad properly. */
753 targetm.asm_out.aligned_op.di = NULL;
754 targetm.asm_out.unaligned_op.di = NULL;
758 if (! strcmp (sh_div_str, "call-div1"))
759 sh_div_strategy = SH_DIV_CALL_DIV1;
760 else if (! strcmp (sh_div_str, "call-fp")
761 && (TARGET_FPU_DOUBLE
762 || (TARGET_HARD_SH4 && TARGET_SH2E)
763 || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))
764 sh_div_strategy = SH_DIV_CALL_FP;
765 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2)
766 sh_div_strategy = SH_DIV_CALL_TABLE;
768 /* Pick one that makes most sense for the target in general.
769 It is not much good to use different functions depending
770 on -Os, since then we'll end up with two different functions
771 when some of the code is compiled for size, and some for
774 /* SH4 tends to emphasize speed. */
776 sh_div_strategy = SH_DIV_CALL_TABLE;
777 /* These have their own way of doing things. */
778 else if (TARGET_SH2A)
779 sh_div_strategy = SH_DIV_INTRINSIC;
780 /* ??? Should we use the integer SHmedia function instead? */
781 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)
782 sh_div_strategy = SH_DIV_CALL_FP;
783 /* SH1 .. SH3 cores often go into small-footprint systems, so
784 default to the smallest implementation available. */
785 else if (TARGET_SH2) /* ??? EXPERIMENTAL */
786 sh_div_strategy = SH_DIV_CALL_TABLE;
788 sh_div_strategy = SH_DIV_CALL_DIV1;
791 TARGET_PRETEND_CMOVE = 0;
792 if (sh_divsi3_libfunc[0])
793 ; /* User supplied - leave it alone. */
794 else if (TARGET_DIVIDE_CALL_FP)
795 sh_divsi3_libfunc = "__sdivsi3_i4";
796 else if (TARGET_DIVIDE_CALL_TABLE)
797 sh_divsi3_libfunc = "__sdivsi3_i4i";
799 sh_divsi3_libfunc = "__sdivsi3_1";
801 sh_divsi3_libfunc = "__sdivsi3";
802 if (sh_branch_cost == -1)
804 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1;
806 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
807 if (! VALID_REGISTER_P (regno))
808 sh_register_names[regno][0] = '\0';
810 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
811 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
812 sh_additional_register_names[regno][0] = '\0';
814 if (flag_omit_frame_pointer == 2)
816 /* The debugging information is sufficient,
817 but gdb doesn't implement this yet */
819 flag_omit_frame_pointer
820 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);
822 flag_omit_frame_pointer = 0;
825 if ((flag_pic && ! TARGET_PREFERGOT)
826 || (TARGET_SHMEDIA && !TARGET_PT_FIXED))
827 flag_no_function_cse = 1;
829 if (SMALL_REGISTER_CLASSES)
831 /* Never run scheduling before reload, since that can
832 break global alloc, and generates slower code anyway due
833 to the pressure on R0. */
834 /* Enable sched1 for SH4 if the user explicitly requests.
835 When sched1 is enabled, the ready queue will be reordered by
836 the target hooks if pressure is high. We can not do this for
837 PIC, SH3 and lower as they give spill failures for R0. */
838 if (!TARGET_HARD_SH4 || flag_pic)
839 flag_schedule_insns = 0;
840 /* ??? Current exception handling places basic block boundaries
841 after call_insns. It causes the high pressure on R0 and gives
842 spill failures for R0 in reload. See PR 22553 and the thread
844 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
845 else if (flag_exceptions)
847 if (flag_schedule_insns == 1)
848 warning (0, "ignoring -fschedule-insns because of exception handling bug");
849 flag_schedule_insns = 0;
851 else if (flag_schedule_insns == 2)
852 flag_schedule_insns = 0;
855 if (align_loops == 0)
856 align_loops = 1 << (TARGET_SH5 ? 3 : 2);
857 if (align_jumps == 0)
858 align_jumps = 1 << CACHE_LOG;
859 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))
860 align_jumps = TARGET_SHMEDIA ? 4 : 2;
862 /* Allocation boundary (in *bytes*) for the code of a function.
863 SH1: 32 bit alignment is faster, because instructions are always
864 fetched as a pair from a longword boundary.
865 SH2 .. SH5 : align to cache line start. */
866 if (align_functions == 0)
868 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);
869 /* The linker relaxation code breaks when a function contains
870 alignments that are larger than that at the start of a
875 = align_loops > align_jumps ? align_loops : align_jumps;
877 /* Also take possible .long constants / mova tables int account. */
880 if (align_functions < min_align)
881 align_functions = min_align;
884 if (sh_fixed_range_str)
885 sh_fix_range (sh_fixed_range_str);
888 /* Print the operand address in x to the stream. */
891 print_operand_address (FILE *stream, rtx x)
893 switch (GET_CODE (x))
897 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
902 rtx base = XEXP (x, 0);
903 rtx index = XEXP (x, 1);
905 switch (GET_CODE (index))
908 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
909 reg_names[true_regnum (base)]);
915 int base_num = true_regnum (base);
916 int index_num = true_regnum (index);
918 fprintf (stream, "@(r0,%s)",
919 reg_names[MAX (base_num, index_num)]);
930 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
934 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
938 x = mark_constant_pool_use (x);
939 output_addr_const (stream, x);
944 /* Print operand x (an rtx) in assembler syntax to file stream
945 according to modifier code.
947 '.' print a .s if insn needs delay slot
948 ',' print LOCAL_LABEL_PREFIX
949 '@' print trap, rte or rts depending upon pragma interruptness
950 '#' output a nop if there is nothing to put in the delay slot
951 ''' print likelihood suffix (/u for unlikely).
952 '>' print branch target if -fverbose-asm
953 'O' print a constant without the #
954 'R' print the LSW of a dp value - changes if in little endian
955 'S' print the MSW of a dp value - changes if in little endian
956 'T' print the next word of a dp value - same as 'R' in big endian mode.
957 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
958 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
959 'N' print 'r63' if the operand is (const_int 0).
960 'd' print a V2SF reg as dN instead of fpN.
961 'm' print a pair `base,offset' or `base,index', for LD and ST.
962 'U' Likewise for {LD,ST}{HI,LO}.
963 'V' print the position of a single bit set.
964 'W' print the position of a single bit cleared.
965 't' print a memory address which is a register.
966 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
967 'o' output an operator. */
970 print_operand (FILE *stream, rtx x, int code)
973 enum machine_mode mode;
981 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
982 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
983 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
986 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
989 trapa_attr = lookup_attribute ("trap_exit",
990 DECL_ATTRIBUTES (current_function_decl));
992 fprintf (stream, "trapa #%ld",
993 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
994 else if (sh_cfun_interrupt_handler_p ())
996 if (sh_cfun_resbank_handler_p ())
997 fprintf (stream, "resbank\n");
998 fprintf (stream, "rte");
1001 fprintf (stream, "rts");
1004 /* Output a nop if there's nothing in the delay slot. */
1005 if (dbr_sequence_length () == 0)
1006 fprintf (stream, "\n\tnop");
1010 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
1012 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
1013 fputs ("/u", stream);
1017 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
1019 fputs ("\t! target: ", stream);
1020 output_addr_const (stream, JUMP_LABEL (current_output_insn));
1024 x = mark_constant_pool_use (x);
1025 output_addr_const (stream, x);
1027 /* N.B.: %R / %S / %T adjust memory addresses by four.
1028 For SHMEDIA, that means they can be used to access the first and
1029 second 32 bit part of a 64 bit (or larger) value that
1030 might be held in floating point registers or memory.
1031 While they can be used to access 64 bit parts of a larger value
1032 held in general purpose registers, that won't work with memory -
1033 neither for fp registers, since the frxx names are used. */
1035 if (REG_P (x) || GET_CODE (x) == SUBREG)
1037 regno = true_regnum (x);
1038 regno += FP_REGISTER_P (regno) ? 1 : LSW;
1039 fputs (reg_names[regno], (stream));
1043 x = adjust_address (x, SImode, 4 * LSW);
1044 print_operand_address (stream, XEXP (x, 0));
1050 mode = GET_MODE (x);
1051 if (mode == VOIDmode)
1053 if (GET_MODE_SIZE (mode) >= 8)
1054 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
1056 print_operand (stream, sub, 0);
1058 output_operand_lossage ("invalid operand to %%R");
1062 if (REG_P (x) || GET_CODE (x) == SUBREG)
1064 regno = true_regnum (x);
1065 regno += FP_REGISTER_P (regno) ? 0 : MSW;
1066 fputs (reg_names[regno], (stream));
1070 x = adjust_address (x, SImode, 4 * MSW);
1071 print_operand_address (stream, XEXP (x, 0));
1077 mode = GET_MODE (x);
1078 if (mode == VOIDmode)
1080 if (GET_MODE_SIZE (mode) >= 8)
1081 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
1083 print_operand (stream, sub, 0);
1085 output_operand_lossage ("invalid operand to %%S");
1089 /* Next word of a double. */
1090 switch (GET_CODE (x))
1093 fputs (reg_names[REGNO (x) + 1], (stream));
1096 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
1097 && GET_CODE (XEXP (x, 0)) != POST_INC)
1098 x = adjust_address (x, SImode, 4);
1099 print_operand_address (stream, XEXP (x, 0));
1107 gcc_assert (MEM_P (x));
1109 switch (GET_CODE (x))
1113 print_operand (stream, x, 0);
1121 switch (GET_CODE (x))
1123 case PLUS: fputs ("add", stream); break;
1124 case MINUS: fputs ("sub", stream); break;
1125 case MULT: fputs ("mul", stream); break;
1126 case DIV: fputs ("div", stream); break;
1127 case EQ: fputs ("eq", stream); break;
1128 case NE: fputs ("ne", stream); break;
1129 case GT: case LT: fputs ("gt", stream); break;
1130 case GE: case LE: fputs ("ge", stream); break;
1131 case GTU: case LTU: fputs ("gtu", stream); break;
1132 case GEU: case LEU: fputs ("geu", stream); break;
1141 && GET_CODE (XEXP (x, 0)) == PLUS
1142 && (REG_P (XEXP (XEXP (x, 0), 1))
1143 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
1144 fputc ('x', stream);
1150 switch (GET_MODE (x))
1152 case QImode: fputs (".b", stream); break;
1153 case HImode: fputs (".w", stream); break;
1154 case SImode: fputs (".l", stream); break;
1155 case SFmode: fputs (".s", stream); break;
1156 case DFmode: fputs (".d", stream); break;
1157 default: gcc_unreachable ();
1164 gcc_assert (MEM_P (x));
1168 switch (GET_CODE (x))
1172 print_operand (stream, x, 0);
1173 fputs (", 0", stream);
1177 print_operand (stream, XEXP (x, 0), 0);
1178 fputs (", ", stream);
1179 print_operand (stream, XEXP (x, 1), 0);
1189 int num = exact_log2 (INTVAL (x));
1190 gcc_assert (num >= 0);
1191 fprintf (stream, "#%d", num);
1197 int num = exact_log2 (~INTVAL (x));
1198 gcc_assert (num >= 0);
1199 fprintf (stream, "#%d", num);
1204 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
1206 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1210 if (x == CONST0_RTX (GET_MODE (x)))
1212 fprintf ((stream), "r63");
1215 goto default_output;
1217 if (CONST_INT_P (x))
1219 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
1227 mode = GET_MODE (x);
1229 switch (GET_CODE (x))
1233 rtx inner = XEXP (x, 0);
1235 enum machine_mode inner_mode;
1237 /* We might see SUBREGs with vector mode registers inside. */
1238 if (GET_CODE (inner) == SUBREG
1239 && (GET_MODE_SIZE (GET_MODE (inner))
1240 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1241 && subreg_lowpart_p (inner))
1242 inner = SUBREG_REG (inner);
1243 if (CONST_INT_P (inner))
1245 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
1246 goto default_output;
1248 inner_mode = GET_MODE (inner);
1249 if (GET_CODE (inner) == SUBREG
1250 && (GET_MODE_SIZE (GET_MODE (inner))
1251 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1252 && REG_P (SUBREG_REG (inner)))
1254 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
1255 GET_MODE (SUBREG_REG (inner)),
1256 SUBREG_BYTE (inner),
1258 inner = SUBREG_REG (inner);
1260 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
1262 /* Floating point register pairs are always big endian;
1263 general purpose registers are 64 bit wide. */
1264 regno = REGNO (inner);
1265 regno = (HARD_REGNO_NREGS (regno, inner_mode)
1266 - HARD_REGNO_NREGS (regno, mode))
1274 /* FIXME: We need this on SHmedia32 because reload generates
1275 some sign-extended HI or QI loads into DImode registers
1276 but, because Pmode is SImode, the address ends up with a
1277 subreg:SI of the DImode register. Maybe reload should be
1278 fixed so as to apply alter_subreg to such loads? */
1280 gcc_assert (trapping_target_operand (x, VOIDmode));
1281 x = XEXP (XEXP (x, 2), 0);
1282 goto default_output;
1284 gcc_assert (SUBREG_BYTE (x) == 0
1285 && REG_P (SUBREG_REG (x)));
1293 if (FP_REGISTER_P (regno)
1294 && mode == V16SFmode)
1295 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1296 else if (FP_REGISTER_P (REGNO (x))
1297 && mode == V4SFmode)
1298 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1300 && mode == V2SFmode)
1301 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1302 else if (FP_REGISTER_P (REGNO (x))
1303 && GET_MODE_SIZE (mode) > 4)
1304 fprintf ((stream), "d%s", reg_names[regno] + 1);
1306 fputs (reg_names[regno], (stream));
1310 output_address (XEXP (x, 0));
1315 fputc ('#', stream);
1316 output_addr_const (stream, x);
1324 /* Encode symbol attributes of a SYMBOL_REF into its
1325 SYMBOL_REF_FLAGS. */
1327 sh_encode_section_info (tree decl, rtx rtl, int first)
1329 default_encode_section_info (decl, rtl, first);
1331 if (TREE_CODE (decl) == FUNCTION_DECL
1332 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1333 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1336 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1338 force_into (rtx value, rtx target)
1340 value = force_operand (value, target);
1341 if (! rtx_equal_p (value, target))
1342 emit_insn (gen_move_insn (target, value));
1345 /* Emit code to perform a block move. Choose the best method.
1347 OPERANDS[0] is the destination.
1348 OPERANDS[1] is the source.
1349 OPERANDS[2] is the size.
1350 OPERANDS[3] is the alignment safe to use. */
1353 expand_block_move (rtx *operands)
1355 int align = INTVAL (operands[3]);
1356 int constp = (CONST_INT_P (operands[2]));
1357 int bytes = (constp ? INTVAL (operands[2]) : 0);
1362 /* If we could use mov.l to move words and dest is word-aligned, we
1363 can use movua.l for loads and still generate a relatively short
1364 and efficient sequence. */
1365 if (TARGET_SH4A_ARCH && align < 4
1366 && MEM_ALIGN (operands[0]) >= 32
1367 && can_move_by_pieces (bytes, 32))
1369 rtx dest = copy_rtx (operands[0]);
1370 rtx src = copy_rtx (operands[1]);
1371 /* We could use different pseudos for each copied word, but
1372 since movua can only load into r0, it's kind of
1374 rtx temp = gen_reg_rtx (SImode);
1375 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1378 while (copied + 4 <= bytes)
1380 rtx to = adjust_address (dest, SImode, copied);
1381 rtx from = adjust_automodify_address (src, BLKmode,
1384 set_mem_size (from, GEN_INT (4));
1385 emit_insn (gen_movua (temp, from));
1386 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1387 emit_move_insn (to, temp);
1392 move_by_pieces (adjust_address (dest, BLKmode, copied),
1393 adjust_automodify_address (src, BLKmode,
1395 bytes - copied, align, 0);
1400 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1401 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1402 if (align < 4 || (bytes % 4 != 0))
1405 if (TARGET_HARD_SH4)
1409 else if (bytes == 12)
1411 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1412 rtx r4 = gen_rtx_REG (SImode, 4);
1413 rtx r5 = gen_rtx_REG (SImode, 5);
1415 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1416 force_into (XEXP (operands[0], 0), r4);
1417 force_into (XEXP (operands[1], 0), r5);
1418 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1421 else if (! TARGET_SMALLCODE)
1423 const char *entry_name;
1424 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1426 rtx r4 = gen_rtx_REG (SImode, 4);
1427 rtx r5 = gen_rtx_REG (SImode, 5);
1428 rtx r6 = gen_rtx_REG (SImode, 6);
1430 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1431 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1432 force_into (XEXP (operands[0], 0), r4);
1433 force_into (XEXP (operands[1], 0), r5);
1435 dwords = bytes >> 3;
1436 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1437 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1446 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1447 rtx r4 = gen_rtx_REG (SImode, 4);
1448 rtx r5 = gen_rtx_REG (SImode, 5);
1450 sprintf (entry, "__movmemSI%d", bytes);
1451 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1452 force_into (XEXP (operands[0], 0), r4);
1453 force_into (XEXP (operands[1], 0), r5);
1454 emit_insn (gen_block_move_real (func_addr_rtx));
1458 /* This is the same number of bytes as a memcpy call, but to a different
1459 less common function name, so this will occasionally use more space. */
1460 if (! TARGET_SMALLCODE)
1462 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1463 int final_switch, while_loop;
1464 rtx r4 = gen_rtx_REG (SImode, 4);
1465 rtx r5 = gen_rtx_REG (SImode, 5);
1466 rtx r6 = gen_rtx_REG (SImode, 6);
1468 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1469 force_into (XEXP (operands[0], 0), r4);
1470 force_into (XEXP (operands[1], 0), r5);
1472 /* r6 controls the size of the move. 16 is decremented from it
1473 for each 64 bytes moved. Then the negative bit left over is used
1474 as an index into a list of move instructions. e.g., a 72 byte move
1475 would be set up with size(r6) = 14, for one iteration through the
1476 big while loop, and a switch of -2 for the last part. */
1478 final_switch = 16 - ((bytes / 4) % 16);
1479 while_loop = ((bytes / 4) / 16 - 1) * 16;
1480 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1481 emit_insn (gen_block_lump_real (func_addr_rtx));
1488 /* Prepare operands for a move define_expand; specifically, one of the
1489 operands must be in a register. */
1492 prepare_move_operands (rtx operands[], enum machine_mode mode)
1494 if ((mode == SImode || mode == DImode)
1496 && ! ((mode == Pmode || mode == ptr_mode)
1497 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1500 if (SYMBOLIC_CONST_P (operands[1]))
1502 if (MEM_P (operands[0]))
1503 operands[1] = force_reg (Pmode, operands[1]);
1504 else if (TARGET_SHMEDIA
1505 && GET_CODE (operands[1]) == LABEL_REF
1506 && target_reg_operand (operands[0], mode))
1510 temp = (!can_create_pseudo_p ()
1512 : gen_reg_rtx (Pmode));
1513 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1516 else if (GET_CODE (operands[1]) == CONST
1517 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1518 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1520 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1521 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1523 operands[1] = expand_binop (mode, add_optab, temp,
1524 XEXP (XEXP (operands[1], 0), 1),
1525 (!can_create_pseudo_p ()
1527 : gen_reg_rtx (Pmode)),
1528 0, OPTAB_LIB_WIDEN);
1532 if (! reload_in_progress && ! reload_completed)
1534 /* Copy the source to a register if both operands aren't registers. */
1535 if (! register_operand (operands[0], mode)
1536 && ! sh_register_operand (operands[1], mode))
1537 operands[1] = copy_to_mode_reg (mode, operands[1]);
1539 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
1541 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1542 except that we can't use that function because it is static. */
1543 rtx new_rtx = change_address (operands[0], mode, 0);
1544 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1545 operands[0] = new_rtx;
1548 /* This case can happen while generating code to move the result
1549 of a library call to the target. Reject `st r0,@(rX,rY)' because
1550 reload will fail to find a spill register for rX, since r0 is already
1551 being used for the source. */
1553 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1554 && MEM_P (operands[0])
1555 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1556 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
1557 operands[1] = copy_to_mode_reg (mode, operands[1]);
1560 if (mode == Pmode || mode == ptr_mode)
1563 enum tls_model tls_kind;
1567 if (GET_CODE (op1) == CONST
1568 && GET_CODE (XEXP (op1, 0)) == PLUS
1569 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1572 opc = XEXP (XEXP (op1, 0), 1);
1573 op1 = XEXP (XEXP (op1, 0), 0);
1578 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1580 rtx tga_op1, tga_ret, tmp, tmp2;
1584 case TLS_MODEL_GLOBAL_DYNAMIC:
1585 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1586 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1590 case TLS_MODEL_LOCAL_DYNAMIC:
1591 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1592 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1594 tmp = gen_reg_rtx (Pmode);
1595 emit_move_insn (tmp, tga_ret);
1597 if (register_operand (op0, Pmode))
1600 tmp2 = gen_reg_rtx (Pmode);
1602 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1606 case TLS_MODEL_INITIAL_EXEC:
1609 /* Don't schedule insns for getting GOT address when
1610 the first scheduling is enabled, to avoid spill
1612 if (flag_schedule_insns)
1613 emit_insn (gen_blockage ());
1614 emit_insn (gen_GOTaddr2picreg ());
1615 emit_use (gen_rtx_REG (SImode, PIC_REG));
1616 if (flag_schedule_insns)
1617 emit_insn (gen_blockage ());
1619 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1620 tmp = gen_sym2GOTTPOFF (op1);
1621 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1625 case TLS_MODEL_LOCAL_EXEC:
1626 tmp2 = gen_reg_rtx (Pmode);
1627 emit_insn (gen_load_gbr (tmp2));
1628 tmp = gen_reg_rtx (Pmode);
1629 emit_insn (gen_symTPOFF2reg (tmp, op1));
1631 if (register_operand (op0, Pmode))
1634 op1 = gen_reg_rtx (Pmode);
1636 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1643 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1652 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1653 enum rtx_code comparison)
1656 rtx scratch = NULL_RTX;
1658 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1659 comparison = GET_CODE (operands[0]);
1661 scratch = operands[4];
1662 if (CONST_INT_P (operands[1])
1663 && !CONST_INT_P (operands[2]))
1665 rtx tmp = operands[1];
1667 operands[1] = operands[2];
1669 comparison = swap_condition (comparison);
1671 if (CONST_INT_P (operands[2]))
1673 HOST_WIDE_INT val = INTVAL (operands[2]);
1674 if ((val == -1 || val == -0x81)
1675 && (comparison == GT || comparison == LE))
1677 comparison = (comparison == GT) ? GE : LT;
1678 operands[2] = gen_int_mode (val + 1, mode);
1680 else if ((val == 1 || val == 0x80)
1681 && (comparison == GE || comparison == LT))
1683 comparison = (comparison == GE) ? GT : LE;
1684 operands[2] = gen_int_mode (val - 1, mode);
1686 else if (val == 1 && (comparison == GEU || comparison == LTU))
1688 comparison = (comparison == GEU) ? NE : EQ;
1689 operands[2] = CONST0_RTX (mode);
1691 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1693 comparison = (comparison == GEU) ? GTU : LEU;
1694 operands[2] = gen_int_mode (val - 1, mode);
1696 else if (val == 0 && (comparison == GTU || comparison == LEU))
1697 comparison = (comparison == GTU) ? NE : EQ;
1698 else if (mode == SImode
1699 && ((val == 0x7fffffff
1700 && (comparison == GTU || comparison == LEU))
1701 || ((unsigned HOST_WIDE_INT) val
1702 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1703 && (comparison == GEU || comparison == LTU))))
1705 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1706 operands[2] = CONST0_RTX (mode);
1710 if (can_create_pseudo_p ())
1711 operands[1] = force_reg (mode, op1);
1712 /* When we are handling DImode comparisons, we want to keep constants so
1713 that we can optimize the component comparisons; however, memory loads
1714 are better issued as a whole so that they can be scheduled well.
1715 SImode equality comparisons allow I08 constants, but only when they
1716 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1717 into a register, that register might as well be r0, and we allow the
1718 constant. If it is already in a register, this is likely to be
1719 allocated to a different hard register, thus we load the constant into
1720 a register unless it is zero. */
1721 if (!REG_P (operands[2])
1722 && (!CONST_INT_P (operands[2])
1723 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1724 && ((comparison != EQ && comparison != NE)
1725 || (REG_P (op1) && REGNO (op1) != R0_REG)
1726 || !satisfies_constraint_I08 (operands[2])))))
1728 if (scratch && GET_MODE (scratch) == mode)
1730 emit_move_insn (scratch, operands[2]);
1731 operands[2] = scratch;
1733 else if (can_create_pseudo_p ())
1734 operands[2] = force_reg (mode, operands[2]);
1740 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1742 rtx (*branch_expander) (rtx) = gen_branch_true;
1745 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1748 case NE: case LT: case LE: case LTU: case LEU:
1749 comparison = reverse_condition (comparison);
1750 branch_expander = gen_branch_false;
1753 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1754 gen_rtx_fmt_ee (comparison, SImode,
1755 operands[1], operands[2])));
1756 jump = emit_jump_insn (branch_expander (operands[3]));
1757 if (probability >= 0)
1758 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
1762 /* ??? How should we distribute probabilities when more than one branch
1763 is generated. So far we only have soem ad-hoc observations:
1764 - If the operands are random, they are likely to differ in both parts.
1765 - If comparing items in a hash chain, the operands are random or equal;
1766 operation should be EQ or NE.
1767 - If items are searched in an ordered tree from the root, we can expect
1768 the highpart to be unequal about half of the time; operation should be
1769 an inequality comparison, operands non-constant, and overall probability
1770 about 50%. Likewise for quicksort.
1771 - Range checks will be often made against constants. Even if we assume for
1772 simplicity an even distribution of the non-constant operand over a
1773 sub-range here, the same probability could be generated with differently
1774 wide sub-ranges - as long as the ratio of the part of the subrange that
1775 is before the threshold to the part that comes after the threshold stays
1776 the same. Thus, we can't really tell anything here;
1777 assuming random distribution is at least simple.
1781 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1783 enum rtx_code msw_taken, msw_skip, lsw_taken;
1784 rtx skip_label = NULL_RTX;
1785 rtx op1h, op1l, op2h, op2l;
1788 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1789 rtx scratch = operands[4];
1791 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1792 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1793 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1794 op1l = gen_lowpart (SImode, operands[1]);
1795 op2l = gen_lowpart (SImode, operands[2]);
1796 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
1797 prob = split_branch_probability;
1798 rev_prob = REG_BR_PROB_BASE - prob;
1801 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1802 That costs 1 cycle more when the first branch can be predicted taken,
1803 but saves us mispredicts because only one branch needs prediction.
1804 It also enables generating the cmpeqdi_t-1 pattern. */
1806 if (TARGET_CMPEQDI_T)
1808 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1809 emit_jump_insn (gen_branch_true (operands[3]));
1816 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1818 msw_skip_prob = rev_prob;
1819 if (REG_BR_PROB_BASE <= 65535)
1820 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1823 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1827 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1828 / ((HOST_WIDEST_INT) prob << 32)))
1834 if (TARGET_CMPEQDI_T)
1836 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1837 emit_jump_insn (gen_branch_false (operands[3]));
1841 msw_taken_prob = prob;
1846 msw_taken = comparison;
1847 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1849 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1850 msw_skip = swap_condition (msw_taken);
1854 if (op2l == CONST0_RTX (SImode))
1855 msw_taken = comparison;
1858 msw_taken = comparison == GE ? GT : GTU;
1859 msw_skip = swap_condition (msw_taken);
1864 msw_taken = comparison;
1865 if (op2l == CONST0_RTX (SImode))
1867 msw_skip = swap_condition (msw_taken);
1871 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1872 msw_taken = comparison;
1876 if (comparison == LE)
1878 else if (op2h != CONST0_RTX (SImode))
1882 msw_skip = swap_condition (msw_taken);
1885 default: return false;
1887 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
1888 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1889 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
1890 if (comparison != EQ && comparison != NE && num_branches > 1)
1892 if (!CONSTANT_P (operands[2])
1893 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1894 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1896 msw_taken_prob = prob / 2U;
1898 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1899 lsw_taken_prob = prob;
1903 msw_taken_prob = prob;
1904 msw_skip_prob = REG_BR_PROB_BASE;
1905 /* ??? If we have a constant op2h, should we use that when
1906 calculating lsw_taken_prob? */
1907 lsw_taken_prob = prob;
1912 operands[4] = NULL_RTX;
1913 if (reload_completed
1914 && ! arith_reg_or_0_operand (op2h, SImode)
1915 && (true_regnum (op1h) || (comparison != EQ && comparison != NE))
1916 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
1917 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
1919 emit_move_insn (scratch, operands[2]);
1920 operands[2] = scratch;
1922 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1923 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
1924 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1926 rtx taken_label = operands[3];
1928 /* Operands were possibly modified, but msw_skip doesn't expect this.
1929 Always use the original ones. */
1930 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1936 operands[3] = skip_label = gen_label_rtx ();
1937 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
1938 operands[3] = taken_label;
1942 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
1944 if (reload_completed
1945 && ! arith_reg_or_0_operand (op2l, SImode)
1946 && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE)))
1948 emit_move_insn (scratch, operands[2]);
1949 operands[2] = scratch;
1951 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
1953 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1954 emit_label (skip_label);
1958 /* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
1961 sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
1963 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1965 insn = gen_rtx_PARALLEL (VOIDmode,
1967 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
1968 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1974 /* Prepare the operands for an scc instruction; make sure that the
1975 compare has been done and the result is in T_REG. */
1977 sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
1979 rtx t_reg = gen_rtx_REG (SImode, T_REG);
1980 enum rtx_code oldcode = code;
1981 enum machine_mode mode;
1983 /* First need a compare insn. */
1987 /* It isn't possible to handle this case. */
2004 if (code != oldcode)
2011 mode = GET_MODE (op0);
2012 if (mode == VOIDmode)
2013 mode = GET_MODE (op1);
2015 op0 = force_reg (mode, op0);
2016 if ((code != EQ && code != NE
2017 && (op1 != const0_rtx
2018 || code == GTU || code == GEU || code == LTU || code == LEU))
2019 || (mode == DImode && op1 != const0_rtx)
2020 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2021 op1 = force_reg (mode, op1);
2023 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode, t_reg,
2024 gen_rtx_fmt_ee (code, SImode, op0, op1)),
2029 sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
2032 rtx target = gen_reg_rtx (SImode);
2035 gcc_assert (TARGET_SHMEDIA);
2044 tmp = gen_rtx_fmt_ee (code, SImode, op0, op1);
2045 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2055 tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1);
2056 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2074 rtx t2 = gen_reg_rtx (DImode);
2075 emit_insn (gen_extendsidi2 (t2, target));
2079 return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx);
2082 /* Called from the md file, set up the operands of a compare instruction. */
2085 sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
2087 enum rtx_code code = GET_CODE (operands[0]);
2088 enum rtx_code branch_code;
2089 rtx op0 = operands[1];
2090 rtx op1 = operands[2];
2092 bool need_ccmpeq = false;
2094 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
2096 op0 = force_reg (mode, op0);
2097 op1 = force_reg (mode, op1);
2101 if (code != EQ || mode == DImode)
2103 /* Force args into regs, since we can't use constants here. */
2104 op0 = force_reg (mode, op0);
2105 if (op1 != const0_rtx || code == GTU || code == GEU)
2106 op1 = force_reg (mode, op1);
2110 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2113 || (code == LE && TARGET_IEEE && TARGET_SH2E)
2114 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
2116 tem = op0, op0 = op1, op1 = tem;
2117 code = swap_condition (code);
2120 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2123 gcc_assert (TARGET_IEEE && TARGET_SH2E);
2128 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2129 to EQ/GT respectively. */
2130 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
2147 branch_code = reverse_condition (code);
2153 insn = gen_rtx_SET (VOIDmode,
2154 gen_rtx_REG (SImode, T_REG),
2155 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
2157 sh_emit_set_t_insn (insn, mode);
2159 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
2161 if (branch_code == code)
2162 emit_jump_insn (gen_branch_true (operands[3]));
2164 emit_jump_insn (gen_branch_false (operands[3]));
2168 sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
2170 enum rtx_code code = GET_CODE (operands[1]);
2171 rtx op0 = operands[2];
2172 rtx op1 = operands[3];
2174 bool invert = false;
2177 op0 = force_reg (mode, op0);
2178 if ((code != EQ && code != NE
2179 && (op1 != const0_rtx
2180 || code == GTU || code == GEU || code == LTU || code == LEU))
2181 || (mode == DImode && op1 != const0_rtx)
2182 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2183 op1 = force_reg (mode, op1);
2185 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2187 if (code == LT || code == LE)
2189 code = swap_condition (code);
2190 tem = op0, op0 = op1, op1 = tem;
2196 lab = gen_label_rtx ();
2197 sh_emit_scc_to_t (EQ, op0, op1);
2198 emit_jump_insn (gen_branch_true (lab));
2215 sh_emit_scc_to_t (code, op0, op1);
2219 emit_insn (gen_movnegt (operands[0]));
2221 emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
2224 /* Functions to output assembly code. */
2226 /* Return a sequence of instructions to perform DI or DF move.
2228 Since the SH cannot move a DI or DF in one instruction, we have
2229 to take care when we see overlapping source and dest registers. */
2232 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
2233 enum machine_mode mode)
2235 rtx dst = operands[0];
2236 rtx src = operands[1];
2239 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
2240 return "mov.l %T1,%0\n\tmov.l %1,%0";
2242 if (register_operand (dst, mode)
2243 && register_operand (src, mode))
2245 if (REGNO (src) == MACH_REG)
2246 return "sts mach,%S0\n\tsts macl,%R0";
2248 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2249 when mov.d r1,r0 do r1->r0 then r2->r1. */
2251 if (REGNO (src) + 1 == REGNO (dst))
2252 return "mov %T1,%T0\n\tmov %1,%0";
2254 return "mov %1,%0\n\tmov %T1,%T0";
2256 else if (CONST_INT_P (src))
2258 if (INTVAL (src) < 0)
2259 output_asm_insn ("mov #-1,%S0", operands);
2261 output_asm_insn ("mov #0,%S0", operands);
2263 return "mov %1,%R0";
2265 else if (MEM_P (src))
2268 int dreg = REGNO (dst);
2269 rtx inside = XEXP (src, 0);
2271 switch (GET_CODE (inside))
2274 ptrreg = REGNO (inside);
2278 ptrreg = subreg_regno (inside);
2282 ptrreg = REGNO (XEXP (inside, 0));
2283 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2284 an offsettable address. Unfortunately, offsettable addresses use
2285 QImode to check the offset, and a QImode offsettable address
2286 requires r0 for the other operand, which is not currently
2287 supported, so we can't use the 'o' constraint.
2288 Thus we must check for and handle r0+REG addresses here.
2289 We punt for now, since this is likely very rare. */
2290 gcc_assert (!REG_P (XEXP (inside, 1)));
2294 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2296 return "mov.l %1,%0\n\tmov.l %1,%T0";
2301 /* Work out the safe way to copy. Copy into the second half first. */
2303 return "mov.l %T1,%T0\n\tmov.l %1,%0";
2306 return "mov.l %1,%0\n\tmov.l %T1,%T0";
2309 /* Print an instruction which would have gone into a delay slot after
2310 another instruction, but couldn't because the other instruction expanded
2311 into a sequence where putting the slot insn at the end wouldn't work. */
2314 print_slot (rtx insn)
2316 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
2318 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
2322 output_far_jump (rtx insn, rtx op)
2324 struct { rtx lab, reg, op; } this_jmp;
2325 rtx braf_base_lab = NULL_RTX;
2328 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2331 this_jmp.lab = gen_label_rtx ();
2335 && offset - get_attr_length (insn) <= 32766)
2338 jump = "mov.w %O0,%1; braf %1";
2346 jump = "mov.l %O0,%1; braf %1";
2348 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2351 jump = "mov.l %O0,%1; jmp @%1";
2353 /* If we have a scratch register available, use it. */
2354 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
2355 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2357 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2358 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
2359 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
2360 output_asm_insn (jump, &this_jmp.lab);
2361 if (dbr_sequence_length ())
2362 print_slot (final_sequence);
2364 output_asm_insn ("nop", 0);
2368 /* Output the delay slot insn first if any. */
2369 if (dbr_sequence_length ())
2370 print_slot (final_sequence);
2372 this_jmp.reg = gen_rtx_REG (SImode, 13);
2373 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2374 Fortunately, MACL is fixed and call-clobbered, and we never
2375 need its value across jumps, so save r13 in it instead of in
2378 output_asm_insn ("lds r13, macl", 0);
2380 output_asm_insn ("mov.l r13,@-r15", 0);
2381 output_asm_insn (jump, &this_jmp.lab);
2383 output_asm_insn ("sts macl, r13", 0);
2385 output_asm_insn ("mov.l @r15+,r13", 0);
2387 if (far && flag_pic && TARGET_SH2)
2389 braf_base_lab = gen_label_rtx ();
2390 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2391 CODE_LABEL_NUMBER (braf_base_lab));
2394 output_asm_insn (".align 2", 0);
2395 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2397 if (far && flag_pic)
2400 this_jmp.lab = braf_base_lab;
2401 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
2404 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2408 /* Local label counter, used for constants in the pool and inside
2409 pattern branches. */
2411 static int lf = 100;
2413 /* Output code for ordinary branches. */
2416 output_branch (int logic, rtx insn, rtx *operands)
2418 switch (get_attr_length (insn))
2421 /* This can happen if filling the delay slot has caused a forward
2422 branch to exceed its range (we could reverse it, but only
2423 when we know we won't overextend other branches; this should
2424 best be handled by relaxation).
2425 It can also happen when other condbranches hoist delay slot insn
2426 from their destination, thus leading to code size increase.
2427 But the branch will still be in the range -4092..+4098 bytes. */
2432 /* The call to print_slot will clobber the operands. */
2433 rtx op0 = operands[0];
2435 /* If the instruction in the delay slot is annulled (true), then
2436 there is no delay slot where we can put it now. The only safe
2437 place for it is after the label. final will do that by default. */
2440 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2441 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2443 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2444 ASSEMBLER_DIALECT ? "/" : ".", label);
2445 print_slot (final_sequence);
2448 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2450 output_asm_insn ("bra\t%l0", &op0);
2451 fprintf (asm_out_file, "\tnop\n");
2452 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2456 /* When relaxing, handle this like a short branch. The linker
2457 will fix it up if it still doesn't fit after relaxation. */
2459 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2461 /* These are for SH2e, in which we have to account for the
2462 extra nop because of the hardware bug in annulled branches. */
2468 gcc_assert (!final_sequence
2469 || !(INSN_ANNULLED_BRANCH_P
2470 (XVECEXP (final_sequence, 0, 0))));
2471 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2473 ASSEMBLER_DIALECT ? "/" : ".", label);
2474 fprintf (asm_out_file, "\tnop\n");
2475 output_asm_insn ("bra\t%l0", operands);
2476 fprintf (asm_out_file, "\tnop\n");
2477 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2481 /* When relaxing, fall through. */
2486 sprintf (buffer, "b%s%ss\t%%l0",
2488 ASSEMBLER_DIALECT ? "/" : ".");
2489 output_asm_insn (buffer, &operands[0]);
2494 /* There should be no longer branches now - that would
2495 indicate that something has destroyed the branches set
2496 up in machine_dependent_reorg. */
2501 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2502 fill in operands 9 as a label to the successor insn.
2503 We try to use jump threading where possible.
2504 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2505 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2506 follow jmp and bt, if the address is in range. */
2508 output_branchy_insn (enum rtx_code code, const char *templ,
2509 rtx insn, rtx *operands)
2511 rtx next_insn = NEXT_INSN (insn);
2513 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
2515 rtx src = SET_SRC (PATTERN (next_insn));
2516 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2518 /* Following branch not taken */
2519 operands[9] = gen_label_rtx ();
2520 emit_label_after (operands[9], next_insn);
2521 INSN_ADDRESSES_NEW (operands[9],
2522 INSN_ADDRESSES (INSN_UID (next_insn))
2523 + get_attr_length (next_insn));
2528 int offset = (branch_dest (next_insn)
2529 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2530 if (offset >= -252 && offset <= 258)
2532 if (GET_CODE (src) == IF_THEN_ELSE)
2534 src = XEXP (src, 1);
2540 operands[9] = gen_label_rtx ();
2541 emit_label_after (operands[9], insn);
2542 INSN_ADDRESSES_NEW (operands[9],
2543 INSN_ADDRESSES (INSN_UID (insn))
2544 + get_attr_length (insn));
2549 output_ieee_ccmpeq (rtx insn, rtx *operands)
2551 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2555 /* Output the start of the assembler file. */
2558 sh_file_start (void)
2560 default_file_start ();
2563 /* Declare the .directive section before it is used. */
2564 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2565 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2569 /* We need to show the text section with the proper
2570 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2571 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2572 will complain. We can teach GAS specifically about the
2573 default attributes for our choice of text section, but
2574 then we would have to change GAS again if/when we change
2575 the text section name. */
2576 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2578 /* Switch to the data section so that the coffsem symbol
2579 isn't in the text section. */
2580 switch_to_section (data_section);
2582 if (TARGET_LITTLE_ENDIAN)
2583 fputs ("\t.little\n", asm_out_file);
2587 if (TARGET_SHCOMPACT)
2588 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2589 else if (TARGET_SHMEDIA)
2590 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2591 TARGET_SHMEDIA64 ? 64 : 32);
2595 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2598 unspec_caller_rtx_p (rtx pat)
2603 split_const (pat, &base, &offset);
2604 if (GET_CODE (base) == UNSPEC)
2606 if (XINT (base, 1) == UNSPEC_CALLER)
2608 for (i = 0; i < XVECLEN (base, 0); i++)
2609 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2615 /* Indicate that INSN cannot be duplicated. This is true for insn
2616 that generates a unique label. */
2619 sh_cannot_copy_insn_p (rtx insn)
2623 if (!reload_completed || !flag_pic)
2626 if (!NONJUMP_INSN_P (insn))
2628 if (asm_noperands (insn) >= 0)
2631 pat = PATTERN (insn);
2632 if (GET_CODE (pat) != SET)
2634 pat = SET_SRC (pat);
2636 if (unspec_caller_rtx_p (pat))
2642 /* Actual number of instructions used to make a shift by N. */
2643 static const char ashiftrt_insns[] =
2644 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2646 /* Left shift and logical right shift are the same. */
2647 static const char shift_insns[] =
2648 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2650 /* Individual shift amounts needed to get the above length sequences.
2651 One bit right shifts clobber the T bit, so when possible, put one bit
2652 shifts in the middle of the sequence, so the ends are eligible for
2653 branch delay slots. */
2654 static const short shift_amounts[32][5] = {
2655 {0}, {1}, {2}, {2, 1},
2656 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2657 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2658 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2659 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2660 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2661 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2662 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2664 /* Likewise, but for shift amounts < 16, up to three highmost bits
2665 might be clobbered. This is typically used when combined with some
2666 kind of sign or zero extension. */
2668 static const char ext_shift_insns[] =
2669 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2671 static const short ext_shift_amounts[32][4] = {
2672 {0}, {1}, {2}, {2, 1},
2673 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2674 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2675 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2676 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2677 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2678 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2679 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2681 /* Assuming we have a value that has been sign-extended by at least one bit,
2682 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2683 to shift it by N without data loss, and quicker than by other means? */
2684 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2686 /* This is used in length attributes in sh.md to help compute the length
2687 of arbitrary constant shift instructions. */
2690 shift_insns_rtx (rtx insn)
2692 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2693 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
2694 enum rtx_code shift_code = GET_CODE (set_src);
2699 return ashiftrt_insns[shift_count];
2702 return shift_insns[shift_count];
2708 /* Return the cost of a shift. */
2718 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2720 if (GET_MODE (x) == DImode
2721 && CONST_INT_P (XEXP (x, 1))
2722 && INTVAL (XEXP (x, 1)) == 1)
2725 /* Everything else is invalid, because there is no pattern for it. */
2728 /* If shift by a non constant, then this will be expensive. */
2729 if (!CONST_INT_P (XEXP (x, 1)))
2730 return SH_DYNAMIC_SHIFT_COST;
2732 /* Otherwise, return the true cost in instructions. Cope with out of range
2733 shift counts more or less arbitrarily. */
2734 value = INTVAL (XEXP (x, 1)) & 31;
2736 if (GET_CODE (x) == ASHIFTRT)
2738 int cost = ashiftrt_insns[value];
2739 /* If SH3, then we put the constant in a reg and use shad. */
2740 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2741 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2745 return shift_insns[value];
2748 /* Return the cost of an AND operation. */
2755 /* Anding with a register is a single cycle and instruction. */
2756 if (!CONST_INT_P (XEXP (x, 1)))
2759 i = INTVAL (XEXP (x, 1));
2763 if (satisfies_constraint_I10 (XEXP (x, 1))
2764 || satisfies_constraint_J16 (XEXP (x, 1)))
2767 return 1 + rtx_cost (XEXP (x, 1), AND, !optimize_size);
2770 /* These constants are single cycle extu.[bw] instructions. */
2771 if (i == 0xff || i == 0xffff)
2773 /* Constants that can be used in an and immediate instruction in a single
2774 cycle, but this requires r0, so make it a little more expensive. */
2775 if (CONST_OK_FOR_K08 (i))
2777 /* Constants that can be loaded with a mov immediate and an and.
2778 This case is probably unnecessary. */
2779 if (CONST_OK_FOR_I08 (i))
2781 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2782 This case is probably unnecessary. */
2786 /* Return the cost of an addition or a subtraction. */
2791 /* Adding a register is a single cycle insn. */
2792 if (REG_P (XEXP (x, 1))
2793 || GET_CODE (XEXP (x, 1)) == SUBREG)
2796 /* Likewise for small constants. */
2797 if (CONST_INT_P (XEXP (x, 1))
2798 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2802 switch (GET_CODE (XEXP (x, 1)))
2807 return TARGET_SHMEDIA64 ? 5 : 3;
2810 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2812 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2814 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2822 /* Any other constant requires a 2 cycle pc-relative load plus an
2827 /* Return the cost of a multiply. */
2829 multcosts (rtx x ATTRIBUTE_UNUSED)
2831 if (sh_multcost >= 0)
2834 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2835 accept constants. Ideally, we would use a cost of one or two and
2836 add the cost of the operand, but disregard the latter when inside loops
2837 and loop invariant code motion is still to follow.
2838 Using a multiply first and splitting it later if it's a loss
2839 doesn't work because of different sign / zero extension semantics
2840 of multiplies vs. shifts. */
2841 return TARGET_SMALLCODE ? 2 : 3;
2845 /* We have a mul insn, so we can never take more than the mul and the
2846 read of the mac reg, but count more because of the latency and extra
2848 if (TARGET_SMALLCODE)
2853 /* If we're aiming at small code, then just count the number of
2854 insns in a multiply call sequence. */
2855 if (TARGET_SMALLCODE)
2858 /* Otherwise count all the insns in the routine we'd be calling too. */
2862 /* Compute a (partial) cost for rtx X. Return true if the complete
2863 cost has been computed, and false if subexpressions should be
2864 scanned. In either case, *TOTAL contains the cost result. */
2867 sh_rtx_costs (rtx x, int code, int outer_code, int *total,
2868 bool speed ATTRIBUTE_UNUSED)
2875 if (INTVAL (x) == 0)
2877 else if (outer_code == AND && and_operand ((x), DImode))
2879 else if ((outer_code == IOR || outer_code == XOR
2880 || outer_code == PLUS)
2881 && CONST_OK_FOR_I10 (INTVAL (x)))
2883 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2884 *total = COSTS_N_INSNS (outer_code != SET);
2885 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2886 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2887 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2888 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2890 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2893 if (CONST_OK_FOR_I08 (INTVAL (x)))
2895 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2896 && CONST_OK_FOR_K08 (INTVAL (x)))
2898 /* prepare_cmp_insn will force costly constants int registers before
2899 the cbranch[sd]i4 patterns can see them, so preserve potentially
2900 interesting ones not covered by I08 above. */
2901 else if (outer_code == COMPARE
2902 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2903 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2904 || INTVAL (x) == 0x7fffffff
2905 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2914 if (TARGET_SHMEDIA64)
2915 *total = COSTS_N_INSNS (4);
2916 else if (TARGET_SHMEDIA32)
2917 *total = COSTS_N_INSNS (2);
2924 *total = COSTS_N_INSNS (4);
2925 /* prepare_cmp_insn will force costly constants int registers before
2926 the cbranchdi4 pattern can see them, so preserve potentially
2927 interesting ones. */
2928 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
2934 if (x == CONST0_RTX (GET_MODE (x)))
2936 else if (sh_1el_vec (x, VOIDmode))
2937 *total = outer_code != SET;
2938 if (sh_rep_vec (x, VOIDmode))
2939 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2940 + (outer_code != SET));
2941 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2946 *total = COSTS_N_INSNS (addsubcosts (x));
2950 *total = COSTS_N_INSNS (andcosts (x));
2954 *total = COSTS_N_INSNS (multcosts (x));
2960 *total = COSTS_N_INSNS (shiftcosts (x));
2967 *total = COSTS_N_INSNS (20);
2971 if (sh_1el_vec (x, VOIDmode))
2972 *total = outer_code != SET;
2973 if (sh_rep_vec (x, VOIDmode))
2974 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2975 + (outer_code != SET));
2976 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2989 /* Compute the cost of an address. For the SH, all valid addresses are
2990 the same cost. Use a slightly higher cost for reg + reg addressing,
2991 since it increases pressure on r0. */
2994 sh_address_cost (rtx X,
2995 bool speed ATTRIBUTE_UNUSED)
2997 return (GET_CODE (X) == PLUS
2998 && ! CONSTANT_P (XEXP (X, 1))
2999 && ! TARGET_SHMEDIA ? 1 : 0);
3002 /* Code to expand a shift. */
3005 gen_ashift (int type, int n, rtx reg)
3007 /* Negative values here come from the shift_amounts array. */
3020 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
3024 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
3026 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
3029 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
3034 /* Same for HImode */
3037 gen_ashift_hi (int type, int n, rtx reg)
3039 /* Negative values here come from the shift_amounts array. */
3053 /* We don't have HImode right shift operations because using the
3054 ordinary 32 bit shift instructions for that doesn't generate proper
3055 zero/sign extension.
3056 gen_ashift_hi is only called in contexts where we know that the
3057 sign extension works out correctly. */
3060 if (GET_CODE (reg) == SUBREG)
3062 offset = SUBREG_BYTE (reg);
3063 reg = SUBREG_REG (reg);
3065 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
3069 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
3074 /* Output RTL to split a constant shift into its component SH constant
3075 shift instructions. */
3078 gen_shifty_op (int code, rtx *operands)
3080 int value = INTVAL (operands[2]);
3083 /* Truncate the shift count in case it is out of bounds. */
3088 if (code == LSHIFTRT)
3090 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3091 emit_insn (gen_movt (operands[0]));
3094 else if (code == ASHIFT)
3096 /* There is a two instruction sequence for 31 bit left shifts,
3097 but it requires r0. */
3098 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
3100 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
3101 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3106 else if (value == 0)
3108 /* This can happen even when optimizing, if there were subregs before
3109 reload. Don't output a nop here, as this is never optimized away;
3110 use a no-op move instead. */
3111 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
3115 max = shift_insns[value];
3116 for (i = 0; i < max; i++)
3117 gen_ashift (code, shift_amounts[value][i], operands[0]);
3120 /* Same as above, but optimized for values where the topmost bits don't
3124 gen_shifty_hi_op (int code, rtx *operands)
3126 int value = INTVAL (operands[2]);
3128 void (*gen_fun) (int, int, rtx);
3130 /* This operation is used by and_shl for SImode values with a few
3131 high bits known to be cleared. */
3135 emit_insn (gen_nop ());
3139 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
3142 max = ext_shift_insns[value];
3143 for (i = 0; i < max; i++)
3144 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3147 /* When shifting right, emit the shifts in reverse order, so that
3148 solitary negative values come first. */
3149 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
3150 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3153 /* Output RTL for an arithmetic right shift. */
3155 /* ??? Rewrite to use super-optimizer sequences. */
3158 expand_ashiftrt (rtx *operands)
3166 if (!CONST_INT_P (operands[2]))
3168 rtx count = copy_to_mode_reg (SImode, operands[2]);
3169 emit_insn (gen_negsi2 (count, count));
3170 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3173 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
3174 > 1 + SH_DYNAMIC_SHIFT_COST)
3177 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
3178 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3182 if (!CONST_INT_P (operands[2]))
3185 value = INTVAL (operands[2]) & 31;
3189 /* If we are called from abs expansion, arrange things so that we
3190 we can use a single MT instruction that doesn't clobber the source,
3191 if LICM can hoist out the load of the constant zero. */
3192 if (currently_expanding_to_rtl)
3194 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
3196 emit_insn (gen_mov_neg_si_t (operands[0]));
3199 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
3202 else if (value >= 16 && value <= 19)
3204 wrk = gen_reg_rtx (SImode);
3205 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
3208 gen_ashift (ASHIFTRT, 1, wrk);
3209 emit_move_insn (operands[0], wrk);
3212 /* Expand a short sequence inline, longer call a magic routine. */
3213 else if (value <= 5)
3215 wrk = gen_reg_rtx (SImode);
3216 emit_move_insn (wrk, operands[1]);
3218 gen_ashift (ASHIFTRT, 1, wrk);
3219 emit_move_insn (operands[0], wrk);
3223 wrk = gen_reg_rtx (Pmode);
3225 /* Load the value into an arg reg and call a helper. */
3226 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
3227 sprintf (func, "__ashiftrt_r4_%d", value);
3228 function_symbol (wrk, func, SFUNC_STATIC);
3229 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
3230 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
3235 sh_dynamicalize_shift_p (rtx count)
3237 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
3240 /* Try to find a good way to implement the combiner pattern
3241 [(set (match_operand:SI 0 "register_operand" "r")
3242 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3243 (match_operand:SI 2 "const_int_operand" "n"))
3244 (match_operand:SI 3 "const_int_operand" "n"))) .
3245 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3246 return 0 for simple right / left or left/right shift combination.
3247 return 1 for a combination of shifts with zero_extend.
3248 return 2 for a combination of shifts with an AND that needs r0.
3249 return 3 for a combination of shifts with an AND that needs an extra
3250 scratch register, when the three highmost bits of the AND mask are clear.
3251 return 4 for a combination of shifts with an AND that needs an extra
3252 scratch register, when any of the three highmost bits of the AND mask
3254 If ATTRP is set, store an initial right shift width in ATTRP[0],
3255 and the instruction length in ATTRP[1] . These values are not valid
3257 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3258 shift_amounts for the last shift value that is to be used before the
3261 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
3263 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
3264 int left = INTVAL (left_rtx), right;
3266 int cost, best_cost = 10000;
3267 int best_right = 0, best_len = 0;
3271 if (left < 0 || left > 31)
3273 if (CONST_INT_P (mask_rtx))
3274 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3276 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
3277 /* Can this be expressed as a right shift / left shift pair? */
3278 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3279 right = exact_log2 (lsb);
3280 mask2 = ~(mask + lsb - 1);
3281 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3282 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3284 best_cost = shift_insns[right] + shift_insns[right + left];
3285 /* mask has no trailing zeroes <==> ! right */
3286 else if (! right && mask2 == ~(lsb2 - 1))
3288 int late_right = exact_log2 (lsb2);
3289 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
3291 /* Try to use zero extend. */
3292 if (mask2 == ~(lsb2 - 1))
3296 for (width = 8; width <= 16; width += 8)
3298 /* Can we zero-extend right away? */
3299 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
3302 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
3303 if (cost < best_cost)
3314 /* ??? Could try to put zero extend into initial right shift,
3315 or even shift a bit left before the right shift. */
3316 /* Determine value of first part of left shift, to get to the
3317 zero extend cut-off point. */
3318 first = width - exact_log2 (lsb2) + right;
3319 if (first >= 0 && right + left - first >= 0)
3321 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
3322 + ext_shift_insns[right + left - first];
3323 if (cost < best_cost)
3335 /* Try to use r0 AND pattern */
3336 for (i = 0; i <= 2; i++)
3340 if (! CONST_OK_FOR_K08 (mask >> i))
3342 cost = (i != 0) + 2 + ext_shift_insns[left + i];
3343 if (cost < best_cost)
3348 best_len = cost - 1;
3351 /* Try to use a scratch register to hold the AND operand. */
3352 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
3353 for (i = 0; i <= 2; i++)
3357 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
3358 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
3359 if (cost < best_cost)
3364 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
3370 attrp[0] = best_right;
3371 attrp[1] = best_len;
3376 /* This is used in length attributes of the unnamed instructions
3377 corresponding to shl_and_kind return values of 1 and 2. */
3379 shl_and_length (rtx insn)
3381 rtx set_src, left_rtx, mask_rtx;
3384 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3385 left_rtx = XEXP (XEXP (set_src, 0), 1);
3386 mask_rtx = XEXP (set_src, 1);
3387 shl_and_kind (left_rtx, mask_rtx, attributes);
3388 return attributes[1];
3391 /* This is used in length attribute of the and_shl_scratch instruction. */
3394 shl_and_scr_length (rtx insn)
3396 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3397 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
3398 rtx op = XEXP (set_src, 0);
3399 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
3400 op = XEXP (XEXP (op, 0), 0);
3401 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
3404 /* Generate rtl for instructions for which shl_and_kind advised a particular
3405 method of generating them, i.e. returned zero. */
3408 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
3411 unsigned HOST_WIDE_INT mask;
3412 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3413 int right, total_shift;
3414 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
3416 right = attributes[0];
3417 total_shift = INTVAL (left_rtx) + right;
3418 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3425 int first = attributes[2];
3430 emit_insn ((mask << right) <= 0xff
3431 ? gen_zero_extendqisi2 (dest,
3432 gen_lowpart (QImode, source))
3433 : gen_zero_extendhisi2 (dest,
3434 gen_lowpart (HImode, source)));
3438 emit_insn (gen_movsi (dest, source));
3442 operands[2] = GEN_INT (right);
3443 gen_shifty_hi_op (LSHIFTRT, operands);
3447 operands[2] = GEN_INT (first);
3448 gen_shifty_hi_op (ASHIFT, operands);
3449 total_shift -= first;
3453 emit_insn (mask <= 0xff
3454 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3455 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3456 if (total_shift > 0)
3458 operands[2] = GEN_INT (total_shift);
3459 gen_shifty_hi_op (ASHIFT, operands);
3464 shift_gen_fun = gen_shifty_op;
3466 /* If the topmost bit that matters is set, set the topmost bits
3467 that don't matter. This way, we might be able to get a shorter
3469 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3470 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3472 /* Don't expand fine-grained when combining, because that will
3473 make the pattern fail. */
3474 if (currently_expanding_to_rtl
3475 || reload_in_progress || reload_completed)
3479 /* Cases 3 and 4 should be handled by this split
3480 only while combining */
3481 gcc_assert (kind <= 2);
3484 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3487 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3492 operands[2] = GEN_INT (total_shift);
3493 shift_gen_fun (ASHIFT, operands);
3500 if (kind != 4 && total_shift < 16)
3502 neg = -ext_shift_amounts[total_shift][1];
3504 neg -= ext_shift_amounts[total_shift][2];
3508 emit_insn (gen_and_shl_scratch (dest, source,
3511 GEN_INT (total_shift + neg),
3513 emit_insn (gen_movsi (dest, dest));
3520 /* Try to find a good way to implement the combiner pattern
3521 [(set (match_operand:SI 0 "register_operand" "=r")
3522 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3523 (match_operand:SI 2 "const_int_operand" "n")
3524 (match_operand:SI 3 "const_int_operand" "n")
3526 (clobber (reg:SI T_REG))]
3527 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3528 return 0 for simple left / right shift combination.
3529 return 1 for left shift / 8 bit sign extend / left shift.
3530 return 2 for left shift / 16 bit sign extend / left shift.
3531 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3532 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3533 return 5 for left shift / 16 bit sign extend / right shift
3534 return 6 for < 8 bit sign extend / left shift.
3535 return 7 for < 8 bit sign extend / left shift / single right shift.
3536 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3539 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3541 int left, size, insize, ext;
3542 int cost = 0, best_cost;
3545 left = INTVAL (left_rtx);
3546 size = INTVAL (size_rtx);
3547 insize = size - left;
3548 gcc_assert (insize > 0);
3549 /* Default to left / right shift. */
3551 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3554 /* 16 bit shift / sign extend / 16 bit shift */
3555 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3556 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3557 below, by alternative 3 or something even better. */
3558 if (cost < best_cost)
3564 /* Try a plain sign extend between two shifts. */
3565 for (ext = 16; ext >= insize; ext -= 8)
3569 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3570 if (cost < best_cost)
3572 kind = ext / (unsigned) 8;
3576 /* Check if we can do a sloppy shift with a final signed shift
3577 restoring the sign. */
3578 if (EXT_SHIFT_SIGNED (size - ext))
3579 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3580 /* If not, maybe it's still cheaper to do the second shift sloppy,
3581 and do a final sign extend? */
3582 else if (size <= 16)
3583 cost = ext_shift_insns[ext - insize] + 1
3584 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3587 if (cost < best_cost)
3589 kind = ext / (unsigned) 8 + 2;
3593 /* Check if we can sign extend in r0 */
3596 cost = 3 + shift_insns[left];
3597 if (cost < best_cost)
3602 /* Try the same with a final signed shift. */
3605 cost = 3 + ext_shift_insns[left + 1] + 1;
3606 if (cost < best_cost)
3615 /* Try to use a dynamic shift. */
3616 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3617 if (cost < best_cost)
3628 /* Function to be used in the length attribute of the instructions
3629 implementing this pattern. */
3632 shl_sext_length (rtx insn)
3634 rtx set_src, left_rtx, size_rtx;
3637 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3638 left_rtx = XEXP (XEXP (set_src, 0), 1);
3639 size_rtx = XEXP (set_src, 1);
3640 shl_sext_kind (left_rtx, size_rtx, &cost);
3644 /* Generate rtl for this pattern */
3647 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3650 int left, size, insize, cost;
3653 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3654 left = INTVAL (left_rtx);
3655 size = INTVAL (size_rtx);
3656 insize = size - left;
3664 int ext = kind & 1 ? 8 : 16;
3665 int shift2 = size - ext;
3667 /* Don't expand fine-grained when combining, because that will
3668 make the pattern fail. */
3669 if (! currently_expanding_to_rtl
3670 && ! reload_in_progress && ! reload_completed)
3672 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3673 emit_insn (gen_movsi (dest, source));
3677 emit_insn (gen_movsi (dest, source));
3681 operands[2] = GEN_INT (ext - insize);
3682 gen_shifty_hi_op (ASHIFT, operands);
3685 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3686 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3691 operands[2] = GEN_INT (shift2);
3692 gen_shifty_op (ASHIFT, operands);
3699 if (EXT_SHIFT_SIGNED (shift2))
3701 operands[2] = GEN_INT (shift2 + 1);
3702 gen_shifty_op (ASHIFT, operands);
3703 operands[2] = const1_rtx;
3704 gen_shifty_op (ASHIFTRT, operands);
3707 operands[2] = GEN_INT (shift2);
3708 gen_shifty_hi_op (ASHIFT, operands);
3712 operands[2] = GEN_INT (-shift2);
3713 gen_shifty_hi_op (LSHIFTRT, operands);
3715 emit_insn (size <= 8
3716 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3717 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3724 if (! currently_expanding_to_rtl
3725 && ! reload_in_progress && ! reload_completed)
3726 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3730 operands[2] = GEN_INT (16 - insize);
3731 gen_shifty_hi_op (ASHIFT, operands);
3732 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3734 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3736 gen_ashift (ASHIFTRT, 1, dest);
3741 /* Don't expand fine-grained when combining, because that will
3742 make the pattern fail. */
3743 if (! currently_expanding_to_rtl
3744 && ! reload_in_progress && ! reload_completed)
3746 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3747 emit_insn (gen_movsi (dest, source));
3750 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3751 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3752 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3754 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3755 gen_shifty_op (ASHIFT, operands);
3757 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3765 /* Prefix a symbol_ref name with "datalabel". */
3768 gen_datalabel_ref (rtx sym)
3772 if (GET_CODE (sym) == LABEL_REF)
3773 return gen_rtx_CONST (GET_MODE (sym),
3774 gen_rtx_UNSPEC (GET_MODE (sym),
3778 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3780 str = XSTR (sym, 0);
3781 /* Share all SYMBOL_REF strings with the same value - that is important
3783 str = IDENTIFIER_POINTER (get_identifier (str));
3784 XSTR (sym, 0) = str;
3790 static alloc_pool label_ref_list_pool;
3792 typedef struct label_ref_list_d
3795 struct label_ref_list_d *next;
3796 } *label_ref_list_t;
3798 /* The SH cannot load a large constant into a register, constants have to
3799 come from a pc relative load. The reference of a pc relative load
3800 instruction must be less than 1k in front of the instruction. This
3801 means that we often have to dump a constant inside a function, and
3802 generate code to branch around it.
3804 It is important to minimize this, since the branches will slow things
3805 down and make things bigger.
3807 Worst case code looks like:
3825 We fix this by performing a scan before scheduling, which notices which
3826 instructions need to have their operands fetched from the constant table
3827 and builds the table.
3831 scan, find an instruction which needs a pcrel move. Look forward, find the
3832 last barrier which is within MAX_COUNT bytes of the requirement.
3833 If there isn't one, make one. Process all the instructions between
3834 the find and the barrier.
3836 In the above example, we can tell that L3 is within 1k of L1, so
3837 the first move can be shrunk from the 3 insn+constant sequence into
3838 just 1 insn, and the constant moved to L3 to make:
3849 Then the second move becomes the target for the shortening process. */
3853 rtx value; /* Value in table. */
3854 rtx label; /* Label of value. */
3855 label_ref_list_t wend; /* End of window. */
3856 enum machine_mode mode; /* Mode of value. */
3858 /* True if this constant is accessed as part of a post-increment
3859 sequence. Note that HImode constants are never accessed in this way. */
3860 bool part_of_sequence_p;
3863 /* The maximum number of constants that can fit into one pool, since
3864 constants in the range 0..510 are at least 2 bytes long, and in the
3865 range from there to 1018 at least 4 bytes. */
3867 #define MAX_POOL_SIZE 372
3868 static pool_node pool_vector[MAX_POOL_SIZE];
3869 static int pool_size;
3870 static rtx pool_window_label;
3871 static int pool_window_last;
3873 static int max_labelno_before_reorg;
3875 /* ??? If we need a constant in HImode which is the truncated value of a
3876 constant we need in SImode, we could combine the two entries thus saving
3877 two bytes. Is this common enough to be worth the effort of implementing
3880 /* ??? This stuff should be done at the same time that we shorten branches.
3881 As it is now, we must assume that all branches are the maximum size, and
3882 this causes us to almost always output constant pools sooner than
3885 /* Add a constant to the pool and return its label. */
3888 add_constant (rtx x, enum machine_mode mode, rtx last_value)
3892 label_ref_list_t ref, newref;
3894 /* First see if we've already got it. */
3895 for (i = 0; i < pool_size; i++)
3897 if (x->code == pool_vector[i].value->code
3898 && mode == pool_vector[i].mode)
3900 if (x->code == CODE_LABEL)
3902 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3905 if (rtx_equal_p (x, pool_vector[i].value))
3910 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3912 new_rtx = gen_label_rtx ();
3913 LABEL_REFS (new_rtx) = pool_vector[i].label;
3914 pool_vector[i].label = lab = new_rtx;
3916 if (lab && pool_window_label)
3918 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3919 newref->label = pool_window_label;
3920 ref = pool_vector[pool_window_last].wend;
3922 pool_vector[pool_window_last].wend = newref;
3925 pool_window_label = new_rtx;
3926 pool_window_last = i;
3932 /* Need a new one. */
3933 pool_vector[pool_size].value = x;
3934 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3937 pool_vector[pool_size - 1].part_of_sequence_p = true;
3940 lab = gen_label_rtx ();
3941 pool_vector[pool_size].mode = mode;
3942 pool_vector[pool_size].label = lab;
3943 pool_vector[pool_size].wend = NULL;
3944 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
3945 if (lab && pool_window_label)
3947 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3948 newref->label = pool_window_label;
3949 ref = pool_vector[pool_window_last].wend;
3951 pool_vector[pool_window_last].wend = newref;
3954 pool_window_label = lab;
3955 pool_window_last = pool_size;
3960 /* Output the literal table. START, if nonzero, is the first instruction
3961 this table is needed for, and also indicates that there is at least one
3962 casesi_worker_2 instruction; We have to emit the operand3 labels from
3963 these insns at a 4-byte aligned position. BARRIER is the barrier
3964 after which we are to place the table. */
3967 dump_table (rtx start, rtx barrier)
3973 label_ref_list_t ref;
3976 /* Do two passes, first time dump out the HI sized constants. */
3978 for (i = 0; i < pool_size; i++)
3980 pool_node *p = &pool_vector[i];
3982 if (p->mode == HImode)
3986 scan = emit_insn_after (gen_align_2 (), scan);
3989 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3990 scan = emit_label_after (lab, scan);
3991 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
3993 for (ref = p->wend; ref; ref = ref->next)
3996 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3999 else if (p->mode == DFmode)
4007 scan = emit_insn_after (gen_align_4 (), scan);
4009 for (; start != barrier; start = NEXT_INSN (start))
4010 if (NONJUMP_INSN_P (start)
4011 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
4013 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
4014 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
4016 scan = emit_label_after (lab, scan);
4019 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
4021 rtx align_insn = NULL_RTX;
4023 scan = emit_label_after (gen_label_rtx (), scan);
4024 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4027 for (i = 0; i < pool_size; i++)
4029 pool_node *p = &pool_vector[i];
4037 if (align_insn && !p->part_of_sequence_p)
4039 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4040 emit_label_before (lab, align_insn);
4041 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
4043 for (ref = p->wend; ref; ref = ref->next)
4046 emit_insn_before (gen_consttable_window_end (lab),
4049 delete_insn (align_insn);
4050 align_insn = NULL_RTX;
4055 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4056 scan = emit_label_after (lab, scan);
4057 scan = emit_insn_after (gen_consttable_4 (p->value,
4059 need_align = ! need_align;
4065 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4070 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4071 scan = emit_label_after (lab, scan);
4072 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4079 if (p->mode != HImode)
4081 for (ref = p->wend; ref; ref = ref->next)
4084 scan = emit_insn_after (gen_consttable_window_end (lab),
4093 for (i = 0; i < pool_size; i++)
4095 pool_node *p = &pool_vector[i];
4106 scan = emit_label_after (gen_label_rtx (), scan);
4107 scan = emit_insn_after (gen_align_4 (), scan);
4109 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4110 scan = emit_label_after (lab, scan);
4111 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
4119 scan = emit_label_after (gen_label_rtx (), scan);
4120 scan = emit_insn_after (gen_align_4 (), scan);
4122 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4123 scan = emit_label_after (lab, scan);
4124 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4131 if (p->mode != HImode)
4133 for (ref = p->wend; ref; ref = ref->next)
4136 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4141 scan = emit_insn_after (gen_consttable_end (), scan);
4142 scan = emit_barrier_after (scan);
4144 pool_window_label = NULL_RTX;
4145 pool_window_last = 0;
4148 /* Return nonzero if constant would be an ok source for a
4149 mov.w instead of a mov.l. */
4154 return (CONST_INT_P (src)
4155 && INTVAL (src) >= -32768
4156 && INTVAL (src) <= 32767);
4159 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4161 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4163 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4164 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4165 need to fix it if the input value is CONST_OK_FOR_I08. */
4168 broken_move (rtx insn)
4170 if (NONJUMP_INSN_P (insn))
4172 rtx pat = PATTERN (insn);
4173 if (GET_CODE (pat) == PARALLEL)
4174 pat = XVECEXP (pat, 0, 0);
4175 if (GET_CODE (pat) == SET
4176 /* We can load any 8-bit value if we don't care what the high
4177 order bits end up as. */
4178 && GET_MODE (SET_DEST (pat)) != QImode
4179 && (CONSTANT_P (SET_SRC (pat))
4180 /* Match mova_const. */
4181 || (GET_CODE (SET_SRC (pat)) == UNSPEC
4182 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
4183 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
4185 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
4186 && (fp_zero_operand (SET_SRC (pat))
4187 || fp_one_operand (SET_SRC (pat)))
4188 /* ??? If this is a -m4 or -m4-single compilation, in general
4189 we don't know the current setting of fpscr, so disable fldi.
4190 There is an exception if this was a register-register move
4191 before reload - and hence it was ascertained that we have
4192 single precision setting - and in a post-reload optimization
4193 we changed this to do a constant load. In that case
4194 we don't have an r0 clobber, hence we must use fldi. */
4195 && (! TARGET_SH4 || TARGET_FMOVD
4196 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
4198 && REG_P (SET_DEST (pat))
4199 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
4201 && GET_MODE (SET_DEST (pat)) == SImode
4202 && (satisfies_constraint_I20 (SET_SRC (pat))
4203 || satisfies_constraint_I28 (SET_SRC (pat))))
4204 && ! satisfies_constraint_I08 (SET_SRC (pat)))
4214 return (NONJUMP_INSN_P (insn)
4215 && GET_CODE (PATTERN (insn)) == SET
4216 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
4217 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
4218 /* Don't match mova_const. */
4219 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
4222 /* Fix up a mova from a switch that went out of range. */
4224 fixup_mova (rtx mova)
4226 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
4229 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
4230 INSN_CODE (mova) = -1;
4235 rtx lab = gen_label_rtx ();
4236 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
4240 worker = NEXT_INSN (worker);
4242 && !LABEL_P (worker)
4243 && !JUMP_P (worker));
4244 } while (NOTE_P (worker)
4245 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
4246 wpat = PATTERN (worker);
4247 wpat0 = XVECEXP (wpat, 0, 0);
4248 wpat1 = XVECEXP (wpat, 0, 1);
4249 wsrc = SET_SRC (wpat0);
4250 PATTERN (worker) = (gen_casesi_worker_2
4251 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
4252 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
4254 INSN_CODE (worker) = -1;
4255 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4256 base = gen_rtx_LABEL_REF (Pmode, lab);
4257 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
4258 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
4259 INSN_CODE (mova) = -1;
4263 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4264 *num_mova, and check if the new mova is not nested within the first one.
4265 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4266 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4268 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
4270 int n_addr = 0; /* Initialization to shut up spurious warning. */
4271 int f_target, n_target = 0; /* Likewise. */
4275 /* If NEW_MOVA has no address yet, it will be handled later. */
4276 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4279 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4280 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4281 if (n_addr > n_target || n_addr + 1022 < n_target)
4283 /* Change the mova into a load.
4284 broken_move will then return true for it. */
4285 fixup_mova (new_mova);
4291 *first_mova = new_mova;
4296 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4301 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4302 > n_target - n_addr)
4304 fixup_mova (*first_mova);
4309 fixup_mova (new_mova);
4314 /* Find the last barrier from insn FROM which is close enough to hold the
4315 constant pool. If we can't find one, then create one near the end of
4319 find_barrier (int num_mova, rtx mova, rtx from)
4328 int leading_mova = num_mova;
4329 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
4334 /* For HImode: range is 510, add 4 because pc counts from address of
4335 second instruction after this one, subtract 2 for the jump instruction
4336 that we may need to emit before the table, subtract 2 for the instruction
4337 that fills the jump delay slot (in very rare cases, reorg will take an
4338 instruction from after the constant pool or will leave the delay slot
4339 empty). This gives 510.
4340 For SImode: range is 1020, add 4 because pc counts from address of
4341 second instruction after this one, subtract 2 in case pc is 2 byte
4342 aligned, subtract 2 for the jump instruction that we may need to emit
4343 before the table, subtract 2 for the instruction that fills the jump
4344 delay slot. This gives 1018. */
4346 /* The branch will always be shortened now that the reference address for
4347 forward branches is the successor address, thus we need no longer make
4348 adjustments to the [sh]i_limit for -O0. */
4353 while (from && count_si < si_limit && count_hi < hi_limit)
4355 int inc = get_attr_length (from);
4358 /* If this is a label that existed at the time of the compute_alignments
4359 call, determine the alignment. N.B. When find_barrier recurses for
4360 an out-of-reach mova, we might see labels at the start of previously
4361 inserted constant tables. */
4363 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
4366 new_align = 1 << label_to_alignment (from);
4367 else if (BARRIER_P (prev_nonnote_insn (from)))
4368 new_align = 1 << barrier_align (from);
4373 /* In case we are scanning a constant table because of recursion, check
4374 for explicit alignments. If the table is long, we might be forced
4375 to emit the new table in front of it; the length of the alignment
4376 might be the last straw. */
4377 else if (NONJUMP_INSN_P (from)
4378 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4379 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4380 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4381 /* When we find the end of a constant table, paste the new constant
4382 at the end. That is better than putting it in front because
4383 this way, we don't need extra alignment for adding a 4-byte-aligned
4384 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4385 else if (NONJUMP_INSN_P (from)
4386 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4387 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4390 if (BARRIER_P (from))
4394 found_barrier = from;
4396 /* If we are at the end of the function, or in front of an alignment
4397 instruction, we need not insert an extra alignment. We prefer
4398 this kind of barrier. */
4399 if (barrier_align (from) > 2)
4400 good_barrier = from;
4402 /* If we are at the end of a hot/cold block, dump the constants
4404 next = NEXT_INSN (from);
4407 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4411 if (broken_move (from))
4414 enum machine_mode mode;
4416 pat = PATTERN (from);
4417 if (GET_CODE (pat) == PARALLEL)
4418 pat = XVECEXP (pat, 0, 0);
4419 src = SET_SRC (pat);
4420 dst = SET_DEST (pat);
4421 mode = GET_MODE (dst);
4423 /* We must explicitly check the mode, because sometimes the
4424 front end will generate code to load unsigned constants into
4425 HImode targets without properly sign extending them. */
4427 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
4430 /* We put the short constants before the long constants, so
4431 we must count the length of short constants in the range
4432 for the long constants. */
4433 /* ??? This isn't optimal, but is easy to do. */
4438 /* We dump DF/DI constants before SF/SI ones, because
4439 the limit is the same, but the alignment requirements
4440 are higher. We may waste up to 4 additional bytes
4441 for alignment, and the DF/DI constant may have
4442 another SF/SI constant placed before it. */
4443 if (TARGET_SHCOMPACT
4445 && (mode == DFmode || mode == DImode))
4450 while (si_align > 2 && found_si + si_align - 2 > count_si)
4452 if (found_si > count_si)
4453 count_si = found_si;
4454 found_si += GET_MODE_SIZE (mode);
4456 si_limit -= GET_MODE_SIZE (mode);
4462 switch (untangle_mova (&num_mova, &mova, from))
4464 case 0: return find_barrier (0, 0, mova);
4469 = good_barrier ? good_barrier : found_barrier;
4473 if (found_si > count_si)
4474 count_si = found_si;
4476 else if (JUMP_TABLE_DATA_P (from))
4478 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4480 && (prev_nonnote_insn (from)
4481 == XEXP (MOVA_LABELREF (mova), 0))))
4483 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4485 /* We have just passed the barrier in front of the
4486 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4487 the ADDR_DIFF_VEC is accessed as data, just like our pool
4488 constants, this is a good opportunity to accommodate what
4489 we have gathered so far.
4490 If we waited any longer, we could end up at a barrier in
4491 front of code, which gives worse cache usage for separated
4492 instruction / data caches. */
4493 good_barrier = found_barrier;
4498 rtx body = PATTERN (from);
4499 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4502 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4503 else if (JUMP_P (from)
4505 && ! TARGET_SMALLCODE)
4511 if (new_align > si_align)
4513 si_limit -= (count_si - 1) & (new_align - si_align);
4514 si_align = new_align;
4516 count_si = (count_si + new_align - 1) & -new_align;
4521 if (new_align > hi_align)
4523 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4524 hi_align = new_align;
4526 count_hi = (count_hi + new_align - 1) & -new_align;
4528 from = NEXT_INSN (from);
4535 /* Try as we might, the leading mova is out of range. Change
4536 it into a load (which will become a pcload) and retry. */
4538 return find_barrier (0, 0, mova);
4542 /* Insert the constant pool table before the mova instruction,
4543 to prevent the mova label reference from going out of range. */
4545 good_barrier = found_barrier = barrier_before_mova;
4551 if (good_barrier && next_real_insn (found_barrier))
4552 found_barrier = good_barrier;
4556 /* We didn't find a barrier in time to dump our stuff,
4557 so we'll make one. */
4558 rtx label = gen_label_rtx ();
4560 /* If we exceeded the range, then we must back up over the last
4561 instruction we looked at. Otherwise, we just need to undo the
4562 NEXT_INSN at the end of the loop. */
4563 if (PREV_INSN (from) != orig
4564 && (count_hi > hi_limit || count_si > si_limit))
4565 from = PREV_INSN (PREV_INSN (from));
4567 from = PREV_INSN (from);
4569 /* Walk back to be just before any jump or label.
4570 Putting it before a label reduces the number of times the branch
4571 around the constant pool table will be hit. Putting it before
4572 a jump makes it more likely that the bra delay slot will be
4574 while (NOTE_P (from) || JUMP_P (from)
4576 from = PREV_INSN (from);
4578 from = emit_jump_insn_after (gen_jump (label), from);
4579 JUMP_LABEL (from) = label;
4580 LABEL_NUSES (label) = 1;
4581 found_barrier = emit_barrier_after (from);
4582 emit_label_after (label, found_barrier);
4585 return found_barrier;
4588 /* If the instruction INSN is implemented by a special function, and we can
4589 positively find the register that is used to call the sfunc, and this
4590 register is not used anywhere else in this instruction - except as the
4591 destination of a set, return this register; else, return 0. */
4593 sfunc_uses_reg (rtx insn)
4596 rtx pattern, part, reg_part, reg;
4598 if (!NONJUMP_INSN_P (insn))
4600 pattern = PATTERN (insn);
4601 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4604 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4606 part = XVECEXP (pattern, 0, i);
4607 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4612 reg = XEXP (reg_part, 0);
4613 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4615 part = XVECEXP (pattern, 0, i);
4616 if (part == reg_part || GET_CODE (part) == CLOBBER)
4618 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4619 && REG_P (SET_DEST (part)))
4620 ? SET_SRC (part) : part)))
4626 /* See if the only way in which INSN uses REG is by calling it, or by
4627 setting it while calling it. Set *SET to a SET rtx if the register
4631 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4637 reg2 = sfunc_uses_reg (insn);
4638 if (reg2 && REGNO (reg2) == REGNO (reg))
4640 pattern = single_set (insn);
4642 && REG_P (SET_DEST (pattern))
4643 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4649 /* We don't use rtx_equal_p because we don't care if the mode is
4651 pattern = single_set (insn);
4653 && REG_P (SET_DEST (pattern))
4654 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4660 par = PATTERN (insn);
4661 if (GET_CODE (par) == PARALLEL)
4662 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4664 part = XVECEXP (par, 0, i);
4665 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4668 return reg_mentioned_p (reg, SET_SRC (pattern));
4674 pattern = PATTERN (insn);
4676 if (GET_CODE (pattern) == PARALLEL)
4680 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4681 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4683 pattern = XVECEXP (pattern, 0, 0);
4686 if (GET_CODE (pattern) == SET)
4688 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4690 /* We don't use rtx_equal_p, because we don't care if the
4691 mode is different. */
4692 if (!REG_P (SET_DEST (pattern))
4693 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4699 pattern = SET_SRC (pattern);
4702 if (GET_CODE (pattern) != CALL
4703 || !MEM_P (XEXP (pattern, 0))
4704 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4710 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4711 general registers. Bits 0..15 mean that the respective registers
4712 are used as inputs in the instruction. Bits 16..31 mean that the
4713 registers 0..15, respectively, are used as outputs, or are clobbered.
4714 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4716 regs_used (rtx x, int is_dest)
4724 code = GET_CODE (x);
4729 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4730 << (REGNO (x) + is_dest));
4734 rtx y = SUBREG_REG (x);
4739 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4741 subreg_regno_offset (REGNO (y),
4744 GET_MODE (x)) + is_dest));
4748 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4750 /* If there was a return value, it must have been indicated with USE. */
4765 fmt = GET_RTX_FORMAT (code);
4767 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4772 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4773 used |= regs_used (XVECEXP (x, i, j), is_dest);
4775 else if (fmt[i] == 'e')
4776 used |= regs_used (XEXP (x, i), is_dest);
4781 /* Create an instruction that prevents redirection of a conditional branch
4782 to the destination of the JUMP with address ADDR.
4783 If the branch needs to be implemented as an indirect jump, try to find
4784 a scratch register for it.
4785 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4786 If any preceding insn that doesn't fit into a delay slot is good enough,
4787 pass 1. Pass 2 if a definite blocking insn is needed.
4788 -1 is used internally to avoid deep recursion.
4789 If a blocking instruction is made or recognized, return it. */
4792 gen_block_redirect (rtx jump, int addr, int need_block)
4795 rtx prev = prev_nonnote_insn (jump);
4798 /* First, check if we already have an instruction that satisfies our need. */
4799 if (prev && NONJUMP_INSN_P (prev) && ! INSN_DELETED_P (prev))
4801 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4803 if (GET_CODE (PATTERN (prev)) == USE
4804 || GET_CODE (PATTERN (prev)) == CLOBBER
4805 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4807 else if ((need_block &= ~1) < 0)
4809 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4812 if (GET_CODE (PATTERN (jump)) == RETURN)
4816 /* Reorg even does nasty things with return insns that cause branches
4817 to go out of range - see find_end_label and callers. */
4818 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4820 /* We can't use JUMP_LABEL here because it might be undefined
4821 when not optimizing. */
4822 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4823 /* If the branch is out of range, try to find a scratch register for it. */
4825 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4829 /* Don't look for the stack pointer as a scratch register,
4830 it would cause trouble if an interrupt occurred. */
4831 unsigned attempt = 0x7fff, used;
4832 int jump_left = flag_expensive_optimizations + 1;
4834 /* It is likely that the most recent eligible instruction is wanted for
4835 the delay slot. Therefore, find out which registers it uses, and
4836 try to avoid using them. */
4838 for (scan = jump; (scan = PREV_INSN (scan)); )
4842 if (INSN_DELETED_P (scan))
4844 code = GET_CODE (scan);
4845 if (code == CODE_LABEL || code == JUMP_INSN)
4848 && GET_CODE (PATTERN (scan)) != USE
4849 && GET_CODE (PATTERN (scan)) != CLOBBER
4850 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4852 attempt &= ~regs_used (PATTERN (scan), 0);
4856 for (used = dead = 0, scan = JUMP_LABEL (jump);
4857 (scan = NEXT_INSN (scan)); )
4861 if (INSN_DELETED_P (scan))
4863 code = GET_CODE (scan);
4866 used |= regs_used (PATTERN (scan), 0);
4867 if (code == CALL_INSN)
4868 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4869 dead |= (used >> 16) & ~used;
4875 if (code == JUMP_INSN)
4877 if (jump_left-- && simplejump_p (scan))
4878 scan = JUMP_LABEL (scan);
4884 /* Mask out the stack pointer again, in case it was
4885 the only 'free' register we have found. */
4888 /* If the immediate destination is still in range, check for possible
4889 threading with a jump beyond the delay slot insn.
4890 Don't check if we are called recursively; the jump has been or will be
4891 checked in a different invocation then. */
4893 else if (optimize && need_block >= 0)
4895 rtx next = next_active_insn (next_active_insn (dest));
4896 if (next && JUMP_P (next)
4897 && GET_CODE (PATTERN (next)) == SET
4898 && recog_memoized (next) == CODE_FOR_jump_compact)
4900 dest = JUMP_LABEL (next);
4902 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4904 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
4910 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
4912 /* It would be nice if we could convert the jump into an indirect
4913 jump / far branch right now, and thus exposing all constituent
4914 instructions to further optimization. However, reorg uses
4915 simplejump_p to determine if there is an unconditional jump where
4916 it should try to schedule instructions from the target of the
4917 branch; simplejump_p fails for indirect jumps even if they have
4919 rtx insn = emit_insn_before (gen_indirect_jump_scratch
4920 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
4922 /* ??? We would like this to have the scope of the jump, but that
4923 scope will change when a delay slot insn of an inner scope is added.
4924 Hence, after delay slot scheduling, we'll have to expect
4925 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
4928 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
4929 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
4932 else if (need_block)
4933 /* We can't use JUMP_LABEL here because it might be undefined
4934 when not optimizing. */
4935 return emit_insn_before (gen_block_branch_redirect
4936 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
4941 #define CONDJUMP_MIN -252
4942 #define CONDJUMP_MAX 262
4945 /* A label (to be placed) in front of the jump
4946 that jumps to our ultimate destination. */
4948 /* Where we are going to insert it if we cannot move the jump any farther,
4949 or the jump itself if we have picked up an existing jump. */
4951 /* The ultimate destination. */
4953 struct far_branch *prev;
4954 /* If the branch has already been created, its address;
4955 else the address of its first prospective user. */
4959 static void gen_far_branch (struct far_branch *);
4960 enum mdep_reorg_phase_e mdep_reorg_phase;
4962 gen_far_branch (struct far_branch *bp)
4964 rtx insn = bp->insert_place;
4966 rtx label = gen_label_rtx ();
4969 emit_label_after (label, insn);
4972 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
4973 LABEL_NUSES (bp->far_label)++;
4976 jump = emit_jump_insn_after (gen_return (), insn);
4977 /* Emit a barrier so that reorg knows that any following instructions
4978 are not reachable via a fall-through path.
4979 But don't do this when not optimizing, since we wouldn't suppress the
4980 alignment for the barrier then, and could end up with out-of-range
4981 pc-relative loads. */
4983 emit_barrier_after (jump);
4984 emit_label_after (bp->near_label, insn);
4985 JUMP_LABEL (jump) = bp->far_label;
4986 ok = invert_jump (insn, label, 1);
4989 /* If we are branching around a jump (rather than a return), prevent
4990 reorg from using an insn from the jump target as the delay slot insn -
4991 when reorg did this, it pessimized code (we rather hide the delay slot)
4992 and it could cause branches to go out of range. */
4995 (gen_stuff_delay_slot
4996 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
4997 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
4999 /* Prevent reorg from undoing our splits. */
5000 gen_block_redirect (jump, bp->address += 2, 2);
5003 /* Fix up ADDR_DIFF_VECs. */
5005 fixup_addr_diff_vecs (rtx first)
5009 for (insn = first; insn; insn = NEXT_INSN (insn))
5011 rtx vec_lab, pat, prev, prevpat, x, braf_label;
5014 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
5016 pat = PATTERN (insn);
5017 vec_lab = XEXP (XEXP (pat, 0), 0);
5019 /* Search the matching casesi_jump_2. */
5020 for (prev = vec_lab; ; prev = PREV_INSN (prev))
5024 prevpat = PATTERN (prev);
5025 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
5027 x = XVECEXP (prevpat, 0, 1);
5028 if (GET_CODE (x) != USE)
5031 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
5034 /* FIXME: This is a bug in the optimizer, but it seems harmless
5035 to just avoid panicing. */
5039 /* Emit the reference label of the braf where it belongs, right after
5040 the casesi_jump_2 (i.e. braf). */
5041 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
5042 emit_label_after (braf_label, prev);
5044 /* Fix up the ADDR_DIF_VEC to be relative
5045 to the reference address of the braf. */
5046 XEXP (XEXP (pat, 0), 0) = braf_label;
5050 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5051 a barrier. Return the base 2 logarithm of the desired alignment. */
5053 barrier_align (rtx barrier_or_label)
5055 rtx next = next_real_insn (barrier_or_label), pat, prev;
5056 int slot, credit, jump_to_next = 0;
5061 pat = PATTERN (next);
5063 if (GET_CODE (pat) == ADDR_DIFF_VEC)
5066 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
5067 /* This is a barrier in front of a constant table. */
5070 prev = prev_real_insn (barrier_or_label);
5071 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
5073 pat = PATTERN (prev);
5074 /* If this is a very small table, we want to keep the alignment after
5075 the table to the minimum for proper code alignment. */
5076 return ((TARGET_SMALLCODE
5077 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
5078 <= (unsigned) 1 << (CACHE_LOG - 2)))
5079 ? 1 << TARGET_SHMEDIA : align_jumps_log);
5082 if (TARGET_SMALLCODE)
5085 if (! TARGET_SH2 || ! optimize)
5086 return align_jumps_log;
5088 /* When fixing up pcloads, a constant table might be inserted just before
5089 the basic block that ends with the barrier. Thus, we can't trust the
5090 instruction lengths before that. */
5091 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
5093 /* Check if there is an immediately preceding branch to the insn beyond
5094 the barrier. We must weight the cost of discarding useful information
5095 from the current cache line when executing this branch and there is
5096 an alignment, against that of fetching unneeded insn in front of the
5097 branch target when there is no alignment. */
5099 /* There are two delay_slot cases to consider. One is the simple case
5100 where the preceding branch is to the insn beyond the barrier (simple
5101 delay slot filling), and the other is where the preceding branch has
5102 a delay slot that is a duplicate of the insn after the barrier
5103 (fill_eager_delay_slots) and the branch is to the insn after the insn
5104 after the barrier. */
5106 /* PREV is presumed to be the JUMP_INSN for the barrier under
5107 investigation. Skip to the insn before it. */
5108 prev = prev_real_insn (prev);
5110 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
5111 credit >= 0 && prev && NONJUMP_INSN_P (prev);
5112 prev = prev_real_insn (prev))
5115 if (GET_CODE (PATTERN (prev)) == USE
5116 || GET_CODE (PATTERN (prev)) == CLOBBER)
5118 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
5120 prev = XVECEXP (PATTERN (prev), 0, 1);
5121 if (INSN_UID (prev) == INSN_UID (next))
5123 /* Delay slot was filled with insn at jump target. */
5130 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5132 credit -= get_attr_length (prev);
5136 && JUMP_LABEL (prev))
5140 || next_real_insn (JUMP_LABEL (prev)) == next
5141 /* If relax_delay_slots() decides NEXT was redundant
5142 with some previous instruction, it will have
5143 redirected PREV's jump to the following insn. */
5144 || JUMP_LABEL (prev) == next_nonnote_insn (next)
5145 /* There is no upper bound on redundant instructions
5146 that might have been skipped, but we must not put an
5147 alignment where none had been before. */
5148 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
5150 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
5151 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
5152 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
5154 rtx pat = PATTERN (prev);
5155 if (GET_CODE (pat) == PARALLEL)
5156 pat = XVECEXP (pat, 0, 0);
5157 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
5163 return align_jumps_log;
5166 /* If we are inside a phony loop, almost any kind of label can turn up as the
5167 first one in the loop. Aligning a braf label causes incorrect switch
5168 destination addresses; we can detect braf labels because they are
5169 followed by a BARRIER.
5170 Applying loop alignment to small constant or switch tables is a waste
5171 of space, so we suppress this too. */
5173 sh_loop_align (rtx label)
5178 next = next_nonnote_insn (next);
5179 while (next && LABEL_P (next));
5183 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
5184 || recog_memoized (next) == CODE_FOR_consttable_2)
5187 return align_loops_log;
5190 /* Do a final pass over the function, just before delayed branch
5196 rtx first, insn, mova = NULL_RTX;
5198 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
5199 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
5201 first = get_insns ();
5202 max_labelno_before_reorg = max_label_num ();
5204 /* We must split call insns before introducing `mova's. If we're
5205 optimizing, they'll have already been split. Otherwise, make
5206 sure we don't split them too late. */
5208 split_all_insns_noflow ();
5213 /* If relaxing, generate pseudo-ops to associate function calls with
5214 the symbols they call. It does no harm to not generate these
5215 pseudo-ops. However, when we can generate them, it enables to
5216 linker to potentially relax the jsr to a bsr, and eliminate the
5217 register load and, possibly, the constant pool entry. */
5219 mdep_reorg_phase = SH_INSERT_USES_LABELS;
5222 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5223 own purposes. This works because none of the remaining passes
5224 need to look at them.
5226 ??? But it may break in the future. We should use a machine
5227 dependent REG_NOTE, or some other approach entirely. */
5228 for (insn = first; insn; insn = NEXT_INSN (insn))
5234 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
5236 remove_note (insn, note);
5240 for (insn = first; insn; insn = NEXT_INSN (insn))
5242 rtx pattern, reg, link, set, scan, dies, label;
5243 int rescan = 0, foundinsn = 0;
5247 pattern = PATTERN (insn);
5249 if (GET_CODE (pattern) == PARALLEL)
5250 pattern = XVECEXP (pattern, 0, 0);
5251 if (GET_CODE (pattern) == SET)
5252 pattern = SET_SRC (pattern);
5254 if (GET_CODE (pattern) != CALL
5255 || !MEM_P (XEXP (pattern, 0)))
5258 reg = XEXP (XEXP (pattern, 0), 0);
5262 reg = sfunc_uses_reg (insn);
5270 /* Try scanning backward to find where the register is set. */
5272 for (scan = PREV_INSN (insn);
5273 scan && !LABEL_P (scan);
5274 scan = PREV_INSN (scan))
5276 if (! INSN_P (scan))
5279 if (! reg_mentioned_p (reg, scan))
5282 if (noncall_uses_reg (reg, scan, &set))
5295 /* The register is set at LINK. */
5297 /* We can only optimize the function call if the register is
5298 being set to a symbol. In theory, we could sometimes
5299 optimize calls to a constant location, but the assembler
5300 and linker do not support that at present. */
5301 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5302 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5305 /* Scan forward from LINK to the place where REG dies, and
5306 make sure that the only insns which use REG are
5307 themselves function calls. */
5309 /* ??? This doesn't work for call targets that were allocated
5310 by reload, since there may not be a REG_DEAD note for the
5314 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5318 /* Don't try to trace forward past a CODE_LABEL if we haven't
5319 seen INSN yet. Ordinarily, we will only find the setting insn
5320 if it is in the same basic block. However,
5321 cross-jumping can insert code labels in between the load and
5322 the call, and can result in situations where a single call
5323 insn may have two targets depending on where we came from. */
5325 if (LABEL_P (scan) && ! foundinsn)
5328 if (! INSN_P (scan))
5331 /* Don't try to trace forward past a JUMP. To optimize
5332 safely, we would have to check that all the
5333 instructions at the jump destination did not use REG. */
5338 if (! reg_mentioned_p (reg, scan))
5341 if (noncall_uses_reg (reg, scan, &scanset))
5348 && (CALL_P (scan) || sfunc_uses_reg (scan)))
5350 /* There is a function call to this register other
5351 than the one we are checking. If we optimize
5352 this call, we need to rescan again below. */
5356 /* ??? We shouldn't have to worry about SCANSET here.
5357 We should just be able to check for a REG_DEAD note
5358 on a function call. However, the REG_DEAD notes are
5359 apparently not dependable around libcalls; c-torture
5360 execute/920501-2 is a test case. If SCANSET is set,
5361 then this insn sets the register, so it must have
5362 died earlier. Unfortunately, this will only handle
5363 the cases in which the register is, in fact, set in a
5366 /* ??? We shouldn't have to use FOUNDINSN here.
5367 This dates back to when we used LOG_LINKS to find
5368 the most recent insn which sets the register. */
5372 || find_reg_note (scan, REG_DEAD, reg)))
5381 /* Either there was a branch, or some insn used REG
5382 other than as a function call address. */
5386 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5387 on the insn which sets the register, and on each call insn
5388 which uses the register. In final_prescan_insn we look for
5389 the REG_LABEL_OPERAND notes, and output the appropriate label
5392 label = gen_label_rtx ();
5393 add_reg_note (link, REG_LABEL_OPERAND, label);
5394 add_reg_note (insn, REG_LABEL_OPERAND, label);
5402 scan = NEXT_INSN (scan);
5405 && reg_mentioned_p (reg, scan))
5406 || ((reg2 = sfunc_uses_reg (scan))
5407 && REGNO (reg2) == REGNO (reg))))
5408 add_reg_note (scan, REG_LABEL_OPERAND, label);
5410 while (scan != dies);
5416 fixup_addr_diff_vecs (first);
5420 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5421 shorten_branches (first);
5424 /* Scan the function looking for move instructions which have to be
5425 changed to pc-relative loads and insert the literal tables. */
5426 label_ref_list_pool = create_alloc_pool ("label references list",
5427 sizeof (struct label_ref_list_d),
5429 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5430 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
5434 /* ??? basic block reordering can move a switch table dispatch
5435 below the switch table. Check if that has happened.
5436 We only have the addresses available when optimizing; but then,
5437 this check shouldn't be needed when not optimizing. */
5438 if (!untangle_mova (&num_mova, &mova, insn))
5444 else if (JUMP_P (insn)
5445 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5447 /* ??? loop invariant motion can also move a mova out of a
5448 loop. Since loop does this code motion anyway, maybe we
5449 should wrap UNSPEC_MOVA into a CONST, so that reload can
5452 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5453 || (prev_nonnote_insn (insn)
5454 == XEXP (MOVA_LABELREF (mova), 0))))
5461 /* Some code might have been inserted between the mova and
5462 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5463 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5464 total += get_attr_length (scan);
5466 /* range of mova is 1020, add 4 because pc counts from address of
5467 second instruction after this one, subtract 2 in case pc is 2
5468 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5469 cancels out with alignment effects of the mova itself. */
5472 /* Change the mova into a load, and restart scanning
5473 there. broken_move will then return true for mova. */
5478 if (broken_move (insn)
5479 || (NONJUMP_INSN_P (insn)
5480 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5483 /* Scan ahead looking for a barrier to stick the constant table
5485 rtx barrier = find_barrier (num_mova, mova, insn);
5486 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5487 int need_aligned_label = 0;
5489 if (num_mova && ! mova_p (mova))
5491 /* find_barrier had to change the first mova into a
5492 pcload; thus, we have to start with this new pcload. */
5496 /* Now find all the moves between the points and modify them. */
5497 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5501 if (NONJUMP_INSN_P (scan)
5502 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5503 need_aligned_label = 1;
5504 if (broken_move (scan))
5506 rtx *patp = &PATTERN (scan), pat = *patp;
5510 enum machine_mode mode;
5512 if (GET_CODE (pat) == PARALLEL)
5513 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5514 src = SET_SRC (pat);
5515 dst = SET_DEST (pat);
5516 mode = GET_MODE (dst);
5518 if (mode == SImode && hi_const (src)
5519 && REGNO (dst) != FPUL_REG)
5524 while (GET_CODE (dst) == SUBREG)
5526 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5527 GET_MODE (SUBREG_REG (dst)),
5530 dst = SUBREG_REG (dst);
5532 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5534 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
5536 /* This must be an insn that clobbers r0. */
5537 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5538 XVECLEN (PATTERN (scan), 0)
5540 rtx clobber = *clobberp;
5542 gcc_assert (GET_CODE (clobber) == CLOBBER
5543 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5546 && reg_set_between_p (r0_rtx, last_float_move, scan))
5550 && GET_MODE_SIZE (mode) != 4
5551 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5553 lab = add_constant (src, mode, last_float);
5555 emit_insn_before (gen_mova (lab), scan);
5558 /* There will be a REG_UNUSED note for r0 on
5559 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5560 lest reorg:mark_target_live_regs will not
5561 consider r0 to be used, and we end up with delay
5562 slot insn in front of SCAN that clobbers r0. */
5564 = find_regno_note (last_float_move, REG_UNUSED, 0);
5566 /* If we are not optimizing, then there may not be
5569 PUT_REG_NOTE_KIND (note, REG_INC);
5571 *last_float_addr = r0_inc_rtx;
5573 last_float_move = scan;
5575 newsrc = gen_const_mem (mode,
5576 (((TARGET_SH4 && ! TARGET_FMOVD)
5577 || REGNO (dst) == FPUL_REG)
5580 last_float_addr = &XEXP (newsrc, 0);
5582 /* Remove the clobber of r0. */
5583 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5584 gen_rtx_SCRATCH (Pmode));
5586 /* This is a mova needing a label. Create it. */
5587 else if (GET_CODE (src) == UNSPEC
5588 && XINT (src, 1) == UNSPEC_MOVA
5589 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5591 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5592 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5593 newsrc = gen_rtx_UNSPEC (SImode,
5594 gen_rtvec (1, newsrc),
5599 lab = add_constant (src, mode, 0);
5600 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5601 newsrc = gen_const_mem (mode, newsrc);
5603 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5604 INSN_CODE (scan) = -1;
5607 dump_table (need_aligned_label ? insn : 0, barrier);
5611 free_alloc_pool (label_ref_list_pool);
5612 for (insn = first; insn; insn = NEXT_INSN (insn))
5613 PUT_MODE (insn, VOIDmode);
5615 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5616 INSN_ADDRESSES_FREE ();
5617 split_branches (first);
5619 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5620 also has an effect on the register that holds the address of the sfunc.
5621 Insert an extra dummy insn in front of each sfunc that pretends to
5622 use this register. */
5623 if (flag_delayed_branch)
5625 for (insn = first; insn; insn = NEXT_INSN (insn))
5627 rtx reg = sfunc_uses_reg (insn);
5631 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5635 /* fpscr is not actually a user variable, but we pretend it is for the
5636 sake of the previous optimization passes, since we want it handled like
5637 one. However, we don't have any debugging information for it, so turn
5638 it into a non-user variable now. */
5640 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5642 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5646 get_dest_uid (rtx label, int max_uid)
5648 rtx dest = next_real_insn (label);
5651 /* This can happen for an undefined label. */
5653 dest_uid = INSN_UID (dest);
5654 /* If this is a newly created branch redirection blocking instruction,
5655 we cannot index the branch_uid or insn_addresses arrays with its
5656 uid. But then, we won't need to, because the actual destination is
5657 the following branch. */
5658 while (dest_uid >= max_uid)
5660 dest = NEXT_INSN (dest);
5661 dest_uid = INSN_UID (dest);
5663 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
5668 /* Split condbranches that are out of range. Also add clobbers for
5669 scratch registers that are needed in far jumps.
5670 We do this before delay slot scheduling, so that it can take our
5671 newly created instructions into account. It also allows us to
5672 find branches with common targets more easily. */
5675 split_branches (rtx first)
5678 struct far_branch **uid_branch, *far_branch_list = 0;
5679 int max_uid = get_max_uid ();
5682 /* Find out which branches are out of range. */
5683 shorten_branches (first);
5685 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5686 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5688 for (insn = first; insn; insn = NEXT_INSN (insn))
5689 if (! INSN_P (insn))
5691 else if (INSN_DELETED_P (insn))
5693 /* Shorten_branches would split this instruction again,
5694 so transform it into a note. */
5695 SET_INSN_DELETED (insn);
5697 else if (JUMP_P (insn)
5698 /* Don't mess with ADDR_DIFF_VEC */
5699 && (GET_CODE (PATTERN (insn)) == SET
5700 || GET_CODE (PATTERN (insn)) == RETURN))
5702 enum attr_type type = get_attr_type (insn);
5703 if (type == TYPE_CBRANCH)
5707 if (get_attr_length (insn) > 4)
5709 rtx src = SET_SRC (PATTERN (insn));
5710 rtx olabel = XEXP (XEXP (src, 1), 0);
5711 int addr = INSN_ADDRESSES (INSN_UID (insn));
5713 int dest_uid = get_dest_uid (olabel, max_uid);
5714 struct far_branch *bp = uid_branch[dest_uid];
5716 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5717 the label if the LABEL_NUSES count drops to zero. There is
5718 always a jump_optimize pass that sets these values, but it
5719 proceeds to delete unreferenced code, and then if not
5720 optimizing, to un-delete the deleted instructions, thus
5721 leaving labels with too low uses counts. */
5724 JUMP_LABEL (insn) = olabel;
5725 LABEL_NUSES (olabel)++;
5729 bp = (struct far_branch *) alloca (sizeof *bp);
5730 uid_branch[dest_uid] = bp;
5731 bp->prev = far_branch_list;
5732 far_branch_list = bp;
5734 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5735 LABEL_NUSES (bp->far_label)++;
5739 label = bp->near_label;
5740 if (! label && bp->address - addr >= CONDJUMP_MIN)
5742 rtx block = bp->insert_place;
5744 if (GET_CODE (PATTERN (block)) == RETURN)
5745 block = PREV_INSN (block);
5747 block = gen_block_redirect (block,
5749 label = emit_label_after (gen_label_rtx (),
5751 bp->near_label = label;
5753 else if (label && ! NEXT_INSN (label))
5755 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5756 bp->insert_place = insn;
5758 gen_far_branch (bp);
5762 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5764 bp->near_label = label = gen_label_rtx ();
5765 bp->insert_place = insn;
5768 ok = redirect_jump (insn, label, 0);
5773 /* get_attr_length (insn) == 2 */
5774 /* Check if we have a pattern where reorg wants to redirect
5775 the branch to a label from an unconditional branch that
5777 /* We can't use JUMP_LABEL here because it might be undefined
5778 when not optimizing. */
5779 /* A syntax error might cause beyond to be NULL_RTX. */
5781 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5786 || ((beyond = next_active_insn (beyond))
5787 && JUMP_P (beyond)))
5788 && GET_CODE (PATTERN (beyond)) == SET
5789 && recog_memoized (beyond) == CODE_FOR_jump_compact
5791 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5792 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5794 gen_block_redirect (beyond,
5795 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5798 next = next_active_insn (insn);
5801 || ((next = next_active_insn (next))
5803 && GET_CODE (PATTERN (next)) == SET
5804 && recog_memoized (next) == CODE_FOR_jump_compact
5806 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5807 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5809 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5811 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5813 int addr = INSN_ADDRESSES (INSN_UID (insn));
5816 struct far_branch *bp;
5818 if (type == TYPE_JUMP)
5820 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5821 dest_uid = get_dest_uid (far_label, max_uid);
5824 /* Parse errors can lead to labels outside
5826 if (! NEXT_INSN (far_label))
5831 JUMP_LABEL (insn) = far_label;
5832 LABEL_NUSES (far_label)++;
5834 redirect_jump (insn, NULL_RTX, 1);
5838 bp = uid_branch[dest_uid];
5841 bp = (struct far_branch *) alloca (sizeof *bp);
5842 uid_branch[dest_uid] = bp;
5843 bp->prev = far_branch_list;
5844 far_branch_list = bp;
5846 bp->far_label = far_label;
5848 LABEL_NUSES (far_label)++;
5850 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5851 if (addr - bp->address <= CONDJUMP_MAX)
5852 emit_label_after (bp->near_label, PREV_INSN (insn));
5855 gen_far_branch (bp);
5861 bp->insert_place = insn;
5863 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5865 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5868 /* Generate all pending far branches,
5869 and free our references to the far labels. */
5870 while (far_branch_list)
5872 if (far_branch_list->near_label
5873 && ! NEXT_INSN (far_branch_list->near_label))
5874 gen_far_branch (far_branch_list);
5876 && far_branch_list->far_label
5877 && ! --LABEL_NUSES (far_branch_list->far_label))
5878 delete_insn (far_branch_list->far_label);
5879 far_branch_list = far_branch_list->prev;
5882 /* Instruction length information is no longer valid due to the new
5883 instructions that have been generated. */
5884 init_insn_lengths ();
5887 /* Dump out instruction addresses, which is useful for debugging the
5888 constant pool table stuff.
5890 If relaxing, output the label and pseudo-ops used to link together
5891 calls and the instruction which set the registers. */
5893 /* ??? The addresses printed by this routine for insns are nonsense for
5894 insns which are inside of a sequence where none of the inner insns have
5895 variable length. This is because the second pass of shorten_branches
5896 does not bother to update them. */
5899 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
5900 int noperands ATTRIBUTE_UNUSED)
5902 if (TARGET_DUMPISIZE)
5903 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
5909 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
5914 pattern = PATTERN (insn);
5915 if (GET_CODE (pattern) == PARALLEL)
5916 pattern = XVECEXP (pattern, 0, 0);
5917 switch (GET_CODE (pattern))
5920 if (GET_CODE (SET_SRC (pattern)) != CALL
5921 && get_attr_type (insn) != TYPE_SFUNC)
5923 targetm.asm_out.internal_label
5924 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
5927 /* else FALLTHROUGH */
5929 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
5930 CODE_LABEL_NUMBER (XEXP (note, 0)));
5940 /* Dump out any constants accumulated in the final pass. These will
5944 output_jump_label_table (void)
5950 fprintf (asm_out_file, "\t.align 2\n");
5951 for (i = 0; i < pool_size; i++)
5953 pool_node *p = &pool_vector[i];
5955 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5956 CODE_LABEL_NUMBER (p->label));
5957 output_asm_insn (".long %O0", &p->value);
5965 /* A full frame looks like:
5969 [ if current_function_anonymous_args
5982 local-0 <- fp points here. */
5984 /* Number of bytes pushed for anonymous args, used to pass information
5985 between expand_prologue and expand_epilogue. */
5987 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
5988 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
5989 for an epilogue and a negative value means that it's for a sibcall
5990 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
5991 all the registers that are about to be restored, and hence dead. */
5994 output_stack_adjust (int size, rtx reg, int epilogue_p,
5995 HARD_REG_SET *live_regs_mask)
5997 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
6000 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6002 /* This test is bogus, as output_stack_adjust is used to re-align the
6005 gcc_assert (!(size % align));
6008 if (CONST_OK_FOR_ADD (size))
6009 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
6010 /* Try to do it with two partial adjustments; however, we must make
6011 sure that the stack is properly aligned at all times, in case
6012 an interrupt occurs between the two partial adjustments. */
6013 else if (CONST_OK_FOR_ADD (size / 2 & -align)
6014 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
6016 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
6017 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
6023 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
6026 /* If TEMP is invalid, we could temporarily save a general
6027 register to MACL. However, there is currently no need
6028 to handle this case, so just die when we see it. */
6030 || current_function_interrupt
6031 || ! call_really_used_regs[temp] || fixed_regs[temp])
6033 if (temp < 0 && ! current_function_interrupt
6034 && (TARGET_SHMEDIA || epilogue_p >= 0))
6037 COPY_HARD_REG_SET (temps, call_used_reg_set);
6038 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
6042 if (crtl->return_rtx)
6044 enum machine_mode mode;
6045 mode = GET_MODE (crtl->return_rtx);
6046 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
6047 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
6049 for (i = 0; i < nreg; i++)
6050 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
6051 if (crtl->calls_eh_return)
6053 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
6054 for (i = 0; i <= 3; i++)
6055 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
6058 if (TARGET_SHMEDIA && epilogue_p < 0)
6059 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
6060 CLEAR_HARD_REG_BIT (temps, i);
6061 if (epilogue_p <= 0)
6063 for (i = FIRST_PARM_REG;
6064 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
6065 CLEAR_HARD_REG_BIT (temps, i);
6066 if (cfun->static_chain_decl != NULL)
6067 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
6069 temp = scavenge_reg (&temps);
6071 if (temp < 0 && live_regs_mask)
6075 COPY_HARD_REG_SET (temps, *live_regs_mask);
6076 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
6077 temp = scavenge_reg (&temps);
6081 rtx adj_reg, tmp_reg, mem;
6083 /* If we reached here, the most likely case is the (sibcall)
6084 epilogue for non SHmedia. Put a special push/pop sequence
6085 for such case as the last resort. This looks lengthy but
6086 would not be problem because it seems to be very
6089 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
6092 /* ??? There is still the slight possibility that r4 or
6093 r5 have been reserved as fixed registers or assigned
6094 as global registers, and they change during an
6095 interrupt. There are possible ways to handle this:
6097 - If we are adjusting the frame pointer (r14), we can do
6098 with a single temp register and an ordinary push / pop
6100 - Grab any call-used or call-saved registers (i.e. not
6101 fixed or globals) for the temps we need. We might
6102 also grab r14 if we are adjusting the stack pointer.
6103 If we can't find enough available registers, issue
6104 a diagnostic and die - the user must have reserved
6105 way too many registers.
6106 But since all this is rather unlikely to happen and
6107 would require extra testing, we just die if r4 / r5
6108 are not available. */
6109 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
6110 && !global_regs[4] && !global_regs[5]);
6112 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
6113 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
6114 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
6115 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
6116 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
6117 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6118 emit_move_insn (mem, tmp_reg);
6119 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
6120 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6121 emit_move_insn (mem, tmp_reg);
6122 emit_move_insn (reg, adj_reg);
6123 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6124 emit_move_insn (adj_reg, mem);
6125 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6126 emit_move_insn (tmp_reg, mem);
6127 /* Tell flow the insns that pop r4/r5 aren't dead. */
6132 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
6134 /* If SIZE is negative, subtract the positive value.
6135 This sometimes allows a constant pool entry to be shared
6136 between prologue and epilogue code. */
6139 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
6140 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
6144 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
6145 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
6148 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
6149 gen_rtx_SET (VOIDmode, reg,
6150 gen_rtx_PLUS (SImode, reg,
6160 RTX_FRAME_RELATED_P (x) = 1;
6164 /* Output RTL to push register RN onto the stack. */
6171 x = gen_push_fpul ();
6172 else if (rn == FPSCR_REG)
6173 x = gen_push_fpscr ();
6174 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6175 && FP_OR_XD_REGISTER_P (rn))
6177 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6179 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
6181 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6182 x = gen_push_e (gen_rtx_REG (SFmode, rn));
6184 x = gen_push (gen_rtx_REG (SImode, rn));
6187 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6191 /* Output RTL to pop register RN from the stack. */
6198 x = gen_pop_fpul ();
6199 else if (rn == FPSCR_REG)
6200 x = gen_pop_fpscr ();
6201 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6202 && FP_OR_XD_REGISTER_P (rn))
6204 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6206 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
6208 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6209 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
6211 x = gen_pop (gen_rtx_REG (SImode, rn));
6214 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6217 /* Generate code to push the regs specified in the mask. */
6220 push_regs (HARD_REG_SET *mask, int interrupt_handler)
6222 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
6225 /* Push PR last; this gives better latencies after the prologue, and
6226 candidates for the return delay slot when there are no general
6227 registers pushed. */
6228 for (; i < FIRST_PSEUDO_REGISTER; i++)
6230 /* If this is an interrupt handler, and the SZ bit varies,
6231 and we have to push any floating point register, we need
6232 to switch to the correct precision first. */
6233 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
6234 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
6236 HARD_REG_SET unsaved;
6239 COMPL_HARD_REG_SET (unsaved, *mask);
6240 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
6244 && (i != FPSCR_REG || ! skip_fpscr)
6245 && TEST_HARD_REG_BIT (*mask, i))
6247 /* If the ISR has RESBANK attribute assigned, don't push any of
6248 the following registers - R0-R14, MACH, MACL and GBR. */
6249 if (! (sh_cfun_resbank_handler_p ()
6250 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
6258 /* Push banked registers last to improve delay slot opportunities. */
6259 if (interrupt_handler)
6260 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6261 if (TEST_HARD_REG_BIT (*mask, i))
6264 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6265 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
6269 /* Calculate how much extra space is needed to save all callee-saved
6271 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6274 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
6277 int stack_space = 0;
6278 int interrupt_handler = sh_cfun_interrupt_handler_p ();
6280 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6281 if ((! call_really_used_regs[reg] || interrupt_handler)
6282 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6283 /* Leave space to save this target register on the stack,
6284 in case target register allocation wants to use it. */
6285 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6289 /* Decide whether we should reserve space for callee-save target registers,
6290 in case target register allocation wants to use them. REGS_SAVED is
6291 the space, in bytes, that is already required for register saves.
6292 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6295 shmedia_reserve_space_for_target_registers_p (int regs_saved,
6296 HARD_REG_SET *live_regs_mask)
6300 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
6303 /* Decide how much space to reserve for callee-save target registers
6304 in case target register allocation wants to use them.
6305 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6308 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
6310 if (shmedia_space_reserved_for_target_registers)
6311 return shmedia_target_regs_stack_space (live_regs_mask);
6316 /* Work out the registers which need to be saved, both as a mask and a
6317 count of saved words. Return the count.
6319 If doing a pragma interrupt function, then push all regs used by the
6320 function, and if we call another function (we can tell by looking at PR),
6321 make sure that all the regs it clobbers are safe too. */
6324 calc_live_regs (HARD_REG_SET *live_regs_mask)
6329 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6330 bool nosave_low_regs;
6331 int pr_live, has_call;
6333 attrs = DECL_ATTRIBUTES (current_function_decl);
6334 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6335 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6336 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6337 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
6339 CLEAR_HARD_REG_SET (*live_regs_mask);
6340 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
6341 && df_regs_ever_live_p (FPSCR_REG))
6342 target_flags &= ~MASK_FPU_SINGLE;
6343 /* If we can save a lot of saves by switching to double mode, do that. */
6344 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
6345 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6346 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
6347 && (! call_really_used_regs[reg]
6348 || interrupt_handler)
6351 target_flags &= ~MASK_FPU_SINGLE;
6354 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6355 knows how to use it. That means the pseudo originally allocated for
6356 the initial value can become the PR_MEDIA_REG hard register, as seen for
6357 execute/20010122-1.c:test9. */
6359 /* ??? this function is called from initial_elimination_offset, hence we
6360 can't use the result of sh_media_register_for_return here. */
6361 pr_live = sh_pr_n_sets ();
6364 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
6365 pr_live = (pr_initial
6366 ? (!REG_P (pr_initial)
6367 || REGNO (pr_initial) != (PR_REG))
6368 : df_regs_ever_live_p (PR_REG));
6369 /* For Shcompact, if not optimizing, we end up with a memory reference
6370 using the return address pointer for __builtin_return_address even
6371 though there is no actual need to put the PR register on the stack. */
6372 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
6374 /* Force PR to be live if the prologue has to call the SHmedia
6375 argument decoder or register saver. */
6376 if (TARGET_SHCOMPACT
6377 && ((crtl->args.info.call_cookie
6378 & ~ CALL_COOKIE_RET_TRAMP (1))
6379 || crtl->saves_all_registers))
6381 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
6382 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
6384 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
6387 ? (/* Need to save all the regs ever live. */
6388 (df_regs_ever_live_p (reg)
6389 || (call_really_used_regs[reg]
6390 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
6391 || reg == PIC_OFFSET_TABLE_REGNUM)
6393 || (TARGET_SHMEDIA && has_call
6394 && REGISTER_NATURAL_MODE (reg) == SImode
6395 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
6396 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
6397 && reg != RETURN_ADDRESS_POINTER_REGNUM
6398 && reg != T_REG && reg != GBR_REG
6399 /* Push fpscr only on targets which have FPU */
6400 && (reg != FPSCR_REG || TARGET_FPU_ANY))
6401 : (/* Only push those regs which are used and need to be saved. */
6404 && crtl->args.info.call_cookie
6405 && reg == PIC_OFFSET_TABLE_REGNUM)
6406 || (df_regs_ever_live_p (reg)
6407 && ((!call_really_used_regs[reg]
6408 && !(reg != PIC_OFFSET_TABLE_REGNUM
6409 && fixed_regs[reg] && call_used_regs[reg]))
6410 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
6411 || (crtl->calls_eh_return
6412 && (reg == EH_RETURN_DATA_REGNO (0)
6413 || reg == EH_RETURN_DATA_REGNO (1)
6414 || reg == EH_RETURN_DATA_REGNO (2)
6415 || reg == EH_RETURN_DATA_REGNO (3)))
6416 || ((reg == MACL_REG || reg == MACH_REG)
6417 && df_regs_ever_live_p (reg)
6418 && sh_cfun_attr_renesas_p ())
6421 SET_HARD_REG_BIT (*live_regs_mask, reg);
6422 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6424 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
6425 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
6427 if (FP_REGISTER_P (reg))
6429 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
6431 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
6432 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
6435 else if (XD_REGISTER_P (reg))
6437 /* Must switch to double mode to access these registers. */
6438 target_flags &= ~MASK_FPU_SINGLE;
6442 if (nosave_low_regs && reg == R8_REG)
6445 /* If we have a target register optimization pass after prologue / epilogue
6446 threading, we need to assume all target registers will be live even if
6448 if (flag_branch_target_load_optimize2
6449 && TARGET_SAVE_ALL_TARGET_REGS
6450 && shmedia_space_reserved_for_target_registers)
6451 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6452 if ((! call_really_used_regs[reg] || interrupt_handler)
6453 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6455 SET_HARD_REG_BIT (*live_regs_mask, reg);
6456 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6458 /* If this is an interrupt handler, we don't have any call-clobbered
6459 registers we can conveniently use for target register save/restore.
6460 Make sure we save at least one general purpose register when we need
6461 to save target registers. */
6462 if (interrupt_handler
6463 && hard_reg_set_intersect_p (*live_regs_mask,
6464 reg_class_contents[TARGET_REGS])
6465 && ! hard_reg_set_intersect_p (*live_regs_mask,
6466 reg_class_contents[GENERAL_REGS]))
6468 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6469 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6475 /* Code to generate prologue and epilogue sequences */
6477 /* PUSHED is the number of bytes that are being pushed on the
6478 stack for register saves. Return the frame size, padded
6479 appropriately so that the stack stays properly aligned. */
6480 static HOST_WIDE_INT
6481 rounded_frame_size (int pushed)
6483 HOST_WIDE_INT size = get_frame_size ();
6484 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6486 return ((size + pushed + align - 1) & -align) - pushed;
6489 /* Choose a call-clobbered target-branch register that remains
6490 unchanged along the whole function. We set it up as the return
6491 value in the prologue. */
6493 sh_media_register_for_return (void)
6498 if (! current_function_is_leaf)
6500 if (lookup_attribute ("interrupt_handler",
6501 DECL_ATTRIBUTES (current_function_decl)))
6503 if (sh_cfun_interrupt_handler_p ())
6506 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6508 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6509 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6515 /* The maximum registers we need to save are:
6516 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6517 - 32 floating point registers (for each pair, we save none,
6518 one single precision value, or a double precision value).
6519 - 8 target registers
6520 - add 1 entry for a delimiter. */
6521 #define MAX_SAVED_REGS (62+32+8)
6523 typedef struct save_entry_s
6532 /* There will be a delimiter entry with VOIDmode both at the start and the
6533 end of a filled in schedule. The end delimiter has the offset of the
6534 save with the smallest (i.e. most negative) offset. */
6535 typedef struct save_schedule_s
6537 save_entry entries[MAX_SAVED_REGS + 2];
6538 int temps[MAX_TEMPS+1];
6541 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6542 use reverse order. Returns the last entry written to (not counting
6543 the delimiter). OFFSET_BASE is a number to be added to all offset
6547 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6551 save_entry *entry = schedule->entries;
6555 if (! current_function_interrupt)
6556 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6557 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6558 && ! FUNCTION_ARG_REGNO_P (i)
6559 && i != FIRST_RET_REG
6560 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6561 && ! (crtl->calls_eh_return
6562 && (i == EH_RETURN_STACKADJ_REGNO
6563 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6564 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6565 schedule->temps[tmpx++] = i;
6567 entry->mode = VOIDmode;
6568 entry->offset = offset_base;
6570 /* We loop twice: first, we save 8-byte aligned registers in the
6571 higher addresses, that are known to be aligned. Then, we
6572 proceed to saving 32-bit registers that don't need 8-byte
6574 If this is an interrupt function, all registers that need saving
6575 need to be saved in full. moreover, we need to postpone saving
6576 target registers till we have saved some general purpose registers
6577 we can then use as scratch registers. */
6578 offset = offset_base;
6579 for (align = 1; align >= 0; align--)
6581 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6582 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6584 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6587 if (current_function_interrupt)
6589 if (TARGET_REGISTER_P (i))
6591 if (GENERAL_REGISTER_P (i))
6594 if (mode == SFmode && (i % 2) == 1
6595 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6596 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6603 /* If we're doing the aligned pass and this is not aligned,
6604 or we're doing the unaligned pass and this is aligned,
6606 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6610 if (current_function_interrupt
6611 && GENERAL_REGISTER_P (i)
6612 && tmpx < MAX_TEMPS)
6613 schedule->temps[tmpx++] = i;
6615 offset -= GET_MODE_SIZE (mode);
6618 entry->offset = offset;
6621 if (align && current_function_interrupt)
6622 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6623 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6625 offset -= GET_MODE_SIZE (DImode);
6627 entry->mode = DImode;
6628 entry->offset = offset;
6633 entry->mode = VOIDmode;
6634 entry->offset = offset;
6635 schedule->temps[tmpx] = -1;
6640 sh_expand_prologue (void)
6642 HARD_REG_SET live_regs_mask;
6645 int save_flags = target_flags;
6648 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6650 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6652 /* We have pretend args if we had an object sent partially in registers
6653 and partially on the stack, e.g. a large structure. */
6654 pretend_args = crtl->args.pretend_args_size;
6655 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6656 && (NPARM_REGS(SImode)
6657 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
6659 output_stack_adjust (-pretend_args
6660 - crtl->args.info.stack_regs * 8,
6661 stack_pointer_rtx, 0, NULL);
6663 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
6664 /* We're going to use the PIC register to load the address of the
6665 incoming-argument decoder and/or of the return trampoline from
6666 the GOT, so make sure the PIC register is preserved and
6668 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6670 if (TARGET_SHCOMPACT
6671 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6675 /* First, make all registers with incoming arguments that will
6676 be pushed onto the stack live, so that register renaming
6677 doesn't overwrite them. */
6678 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6679 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
6680 >= NPARM_REGS (SImode) - reg)
6681 for (; reg < NPARM_REGS (SImode); reg++)
6682 emit_insn (gen_shcompact_preserve_incoming_args
6683 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6684 else if (CALL_COOKIE_INT_REG_GET
6685 (crtl->args.info.call_cookie, reg) == 1)
6686 emit_insn (gen_shcompact_preserve_incoming_args
6687 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6689 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6691 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6692 GEN_INT (crtl->args.info.call_cookie));
6693 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6694 gen_rtx_REG (SImode, R0_REG));
6696 else if (TARGET_SHMEDIA)
6698 int tr = sh_media_register_for_return ();
6701 emit_move_insn (gen_rtx_REG (DImode, tr),
6702 gen_rtx_REG (DImode, PR_MEDIA_REG));
6705 /* Emit the code for SETUP_VARARGS. */
6708 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6710 /* Push arg regs as if they'd been provided by caller in stack. */
6711 for (i = 0; i < NPARM_REGS(SImode); i++)
6713 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6716 if (i >= (NPARM_REGS(SImode)
6717 - crtl->args.info.arg_count[(int) SH_ARG_INT]
6725 /* If we're supposed to switch stacks at function entry, do so now. */
6728 /* The argument specifies a variable holding the address of the
6729 stack the interrupt function should switch to/from at entry/exit. */
6731 = ggc_strdup (TREE_STRING_POINTER (TREE_VALUE (sp_switch_attr)));
6732 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6734 emit_insn (gen_sp_switch_1 (sp_switch));
6737 d = calc_live_regs (&live_regs_mask);
6738 /* ??? Maybe we could save some switching if we can move a mode switch
6739 that already happens to be at the function start into the prologue. */
6740 if (target_flags != save_flags && ! current_function_interrupt)
6741 emit_insn (gen_toggle_sz ());
6745 int offset_base, offset;
6747 int offset_in_r0 = -1;
6749 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6750 int total_size, save_size;
6751 save_schedule schedule;
6755 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6756 && ! current_function_interrupt)
6757 r0 = gen_rtx_REG (Pmode, R0_REG);
6759 /* D is the actual number of bytes that we need for saving registers,
6760 however, in initial_elimination_offset we have committed to using
6761 an additional TREGS_SPACE amount of bytes - in order to keep both
6762 addresses to arguments supplied by the caller and local variables
6763 valid, we must keep this gap. Place it between the incoming
6764 arguments and the actually saved registers in a bid to optimize
6765 locality of reference. */
6766 total_size = d + tregs_space;
6767 total_size += rounded_frame_size (total_size);
6768 save_size = total_size - rounded_frame_size (d);
6769 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6770 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6771 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6773 /* If adjusting the stack in a single step costs nothing extra, do so.
6774 I.e. either if a single addi is enough, or we need a movi anyway,
6775 and we don't exceed the maximum offset range (the test for the
6776 latter is conservative for simplicity). */
6778 && (CONST_OK_FOR_I10 (-total_size)
6779 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6780 && total_size <= 2044)))
6781 d_rounding = total_size - save_size;
6783 offset_base = d + d_rounding;
6785 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
6788 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6789 tmp_pnt = schedule.temps;
6790 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6792 enum machine_mode mode = (enum machine_mode) entry->mode;
6793 unsigned int reg = entry->reg;
6794 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
6797 offset = entry->offset;
6799 reg_rtx = gen_rtx_REG (mode, reg);
6801 mem_rtx = gen_frame_mem (mode,
6802 gen_rtx_PLUS (Pmode,
6806 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
6812 if (HAVE_PRE_DECREMENT
6813 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6814 || mem_rtx == NULL_RTX
6815 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6817 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
6819 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
6824 offset += GET_MODE_SIZE (mode);
6828 if (mem_rtx != NULL_RTX)
6831 if (offset_in_r0 == -1)
6833 emit_move_insn (r0, GEN_INT (offset));
6834 offset_in_r0 = offset;
6836 else if (offset != offset_in_r0)
6841 GEN_INT (offset - offset_in_r0)));
6842 offset_in_r0 += offset - offset_in_r0;
6845 if (pre_dec != NULL_RTX)
6851 (Pmode, r0, stack_pointer_rtx));
6855 offset -= GET_MODE_SIZE (mode);
6856 offset_in_r0 -= GET_MODE_SIZE (mode);
6861 mem_rtx = gen_frame_mem (mode, r0);
6863 mem_rtx = gen_frame_mem (mode,
6864 gen_rtx_PLUS (Pmode,
6868 /* We must not use an r0-based address for target-branch
6869 registers or for special registers without pre-dec
6870 memory addresses, since we store their values in r0
6872 gcc_assert (!TARGET_REGISTER_P (reg)
6873 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6874 || mem_rtx == pre_dec));
6877 orig_reg_rtx = reg_rtx;
6878 if (TARGET_REGISTER_P (reg)
6879 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6880 && mem_rtx != pre_dec))
6882 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
6884 emit_move_insn (tmp_reg, reg_rtx);
6886 if (REGNO (tmp_reg) == R0_REG)
6890 gcc_assert (!refers_to_regno_p
6891 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
6894 if (*++tmp_pnt <= 0)
6895 tmp_pnt = schedule.temps;
6902 /* Mark as interesting for dwarf cfi generator */
6903 insn = emit_move_insn (mem_rtx, reg_rtx);
6904 RTX_FRAME_RELATED_P (insn) = 1;
6905 /* If we use an intermediate register for the save, we can't
6906 describe this exactly in cfi as a copy of the to-be-saved
6907 register into the temporary register and then the temporary
6908 register on the stack, because the temporary register can
6909 have a different natural size than the to-be-saved register.
6910 Thus, we gloss over the intermediate copy and pretend we do
6911 a direct save from the to-be-saved register. */
6912 if (REGNO (reg_rtx) != reg)
6916 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
6917 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6920 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
6922 rtx reg_rtx = gen_rtx_REG (mode, reg);
6924 rtx mem_rtx = gen_frame_mem (mode,
6925 gen_rtx_PLUS (Pmode,
6929 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
6930 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6935 gcc_assert (entry->offset == d_rounding);
6938 push_regs (&live_regs_mask, current_function_interrupt);
6940 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
6941 emit_insn (gen_GOTaddr2picreg ());
6943 if (SHMEDIA_REGS_STACK_ADJUST ())
6945 /* This must NOT go through the PLT, otherwise mach and macl
6946 may be clobbered. */
6947 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6949 ? "__GCC_push_shmedia_regs"
6950 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
6951 emit_insn (gen_shmedia_save_restore_regs_compact
6952 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
6955 if (target_flags != save_flags && ! current_function_interrupt)
6956 emit_insn (gen_toggle_sz ());
6958 target_flags = save_flags;
6960 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
6961 stack_pointer_rtx, 0, NULL);
6963 if (frame_pointer_needed)
6964 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
6966 if (TARGET_SHCOMPACT
6967 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6969 /* This must NOT go through the PLT, otherwise mach and macl
6970 may be clobbered. */
6971 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6972 "__GCC_shcompact_incoming_args", SFUNC_GOT);
6973 emit_insn (gen_shcompact_incoming_args ());
6978 sh_expand_epilogue (bool sibcall_p)
6980 HARD_REG_SET live_regs_mask;
6984 int save_flags = target_flags;
6985 int frame_size, save_size;
6986 int fpscr_deferred = 0;
6987 int e = sibcall_p ? -1 : 1;
6989 d = calc_live_regs (&live_regs_mask);
6992 frame_size = rounded_frame_size (d);
6996 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6998 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
6999 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7000 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
7002 total_size = d + tregs_space;
7003 total_size += rounded_frame_size (total_size);
7004 save_size = total_size - frame_size;
7006 /* If adjusting the stack in a single step costs nothing extra, do so.
7007 I.e. either if a single addi is enough, or we need a movi anyway,
7008 and we don't exceed the maximum offset range (the test for the
7009 latter is conservative for simplicity). */
7011 && ! frame_pointer_needed
7012 && (CONST_OK_FOR_I10 (total_size)
7013 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
7014 && total_size <= 2044)))
7015 d_rounding = frame_size;
7017 frame_size -= d_rounding;
7020 if (frame_pointer_needed)
7022 /* We must avoid scheduling the epilogue with previous basic blocks.
7023 See PR/18032 and PR/40313. */
7024 emit_insn (gen_blockage ());
7025 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
7028 /* We must avoid moving the stack pointer adjustment past code
7029 which reads from the local frame, else an interrupt could
7030 occur after the SP adjustment and clobber data in the local
7032 emit_insn (gen_blockage ());
7033 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
7035 else if (frame_size)
7037 /* We must avoid moving the stack pointer adjustment past code
7038 which reads from the local frame, else an interrupt could
7039 occur after the SP adjustment and clobber data in the local
7041 emit_insn (gen_blockage ());
7042 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
7045 if (SHMEDIA_REGS_STACK_ADJUST ())
7047 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7049 ? "__GCC_pop_shmedia_regs"
7050 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
7051 /* This must NOT go through the PLT, otherwise mach and macl
7052 may be clobbered. */
7053 emit_insn (gen_shmedia_save_restore_regs_compact
7054 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
7057 /* Pop all the registers. */
7059 if (target_flags != save_flags && ! current_function_interrupt)
7060 emit_insn (gen_toggle_sz ());
7063 int offset_base, offset;
7064 int offset_in_r0 = -1;
7066 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
7067 save_schedule schedule;
7071 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
7072 offset_base = -entry[1].offset + d_rounding;
7073 tmp_pnt = schedule.temps;
7074 for (; entry->mode != VOIDmode; entry--)
7076 enum machine_mode mode = (enum machine_mode) entry->mode;
7077 int reg = entry->reg;
7078 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
7080 offset = offset_base + entry->offset;
7081 reg_rtx = gen_rtx_REG (mode, reg);
7083 mem_rtx = gen_frame_mem (mode,
7084 gen_rtx_PLUS (Pmode,
7088 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7091 if (HAVE_POST_INCREMENT
7092 && (offset == offset_in_r0
7093 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
7094 && mem_rtx == NULL_RTX)
7095 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7097 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
7099 if (!memory_address_p (mode, XEXP (post_inc, 0)))
7100 post_inc = NULL_RTX;
7105 if (mem_rtx != NULL_RTX)
7108 if (offset_in_r0 == -1)
7110 emit_move_insn (r0, GEN_INT (offset));
7111 offset_in_r0 = offset;
7113 else if (offset != offset_in_r0)
7118 GEN_INT (offset - offset_in_r0)));
7119 offset_in_r0 += offset - offset_in_r0;
7122 if (post_inc != NULL_RTX)
7128 (Pmode, r0, stack_pointer_rtx));
7134 offset_in_r0 += GET_MODE_SIZE (mode);
7137 mem_rtx = gen_frame_mem (mode, r0);
7139 mem_rtx = gen_frame_mem (mode,
7140 gen_rtx_PLUS (Pmode,
7144 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7145 || mem_rtx == post_inc);
7148 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7149 && mem_rtx != post_inc)
7151 insn = emit_move_insn (r0, mem_rtx);
7154 else if (TARGET_REGISTER_P (reg))
7156 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
7158 /* Give the scheduler a bit of freedom by using up to
7159 MAX_TEMPS registers in a round-robin fashion. */
7160 insn = emit_move_insn (tmp_reg, mem_rtx);
7163 tmp_pnt = schedule.temps;
7166 insn = emit_move_insn (reg_rtx, mem_rtx);
7169 gcc_assert (entry->offset + offset_base == d + d_rounding);
7171 else /* ! TARGET_SH5 */
7176 /* For an ISR with RESBANK attribute assigned, don't pop PR
7178 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
7179 && !sh_cfun_resbank_handler_p ())
7181 if (!frame_pointer_needed)
7182 emit_insn (gen_blockage ());
7186 /* Banked registers are poped first to avoid being scheduled in the
7187 delay slot. RTE switches banks before the ds instruction. */
7188 if (current_function_interrupt)
7190 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
7191 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7192 pop (LAST_BANKED_REG - i);
7194 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
7197 last_reg = FIRST_PSEUDO_REGISTER;
7199 for (i = 0; i < last_reg; i++)
7201 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
7203 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
7204 && hard_reg_set_intersect_p (live_regs_mask,
7205 reg_class_contents[DF_REGS]))
7207 /* For an ISR with RESBANK attribute assigned, don't pop
7208 following registers, R0-R14, MACH, MACL and GBR. */
7209 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
7210 && ! (sh_cfun_resbank_handler_p ()
7211 && ((j >= FIRST_GENERAL_REG
7212 && j < LAST_GENERAL_REG)
7218 if (j == FIRST_FP_REG && fpscr_deferred)
7222 if (target_flags != save_flags && ! current_function_interrupt)
7223 emit_insn (gen_toggle_sz ());
7224 target_flags = save_flags;
7226 output_stack_adjust (crtl->args.pretend_args_size
7227 + save_size + d_rounding
7228 + crtl->args.info.stack_regs * 8,
7229 stack_pointer_rtx, e, NULL);
7231 if (crtl->calls_eh_return)
7232 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
7233 EH_RETURN_STACKADJ_RTX));
7235 /* Switch back to the normal stack if necessary. */
7236 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
7237 emit_insn (gen_sp_switch_2 ());
7239 /* Tell flow the insn that pops PR isn't dead. */
7240 /* PR_REG will never be live in SHmedia mode, and we don't need to
7241 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
7242 by the return pattern. */
7243 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
7244 emit_use (gen_rtx_REG (SImode, PR_REG));
7247 static int sh_need_epilogue_known = 0;
7250 sh_need_epilogue (void)
7252 if (! sh_need_epilogue_known)
7257 sh_expand_epilogue (0);
7258 epilogue = get_insns ();
7260 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
7262 return sh_need_epilogue_known > 0;
7265 /* Emit code to change the current function's return address to RA.
7266 TEMP is available as a scratch register, if needed. */
7269 sh_set_return_address (rtx ra, rtx tmp)
7271 HARD_REG_SET live_regs_mask;
7273 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7276 d = calc_live_regs (&live_regs_mask);
7278 /* If pr_reg isn't life, we can set it (or the register given in
7279 sh_media_register_for_return) directly. */
7280 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7286 int rr_regno = sh_media_register_for_return ();
7291 rr = gen_rtx_REG (DImode, rr_regno);
7294 rr = gen_rtx_REG (SImode, pr_reg);
7296 emit_insn (GEN_MOV (rr, ra));
7297 /* Tell flow the register for return isn't dead. */
7305 save_schedule schedule;
7308 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
7309 offset = entry[1].offset;
7310 for (; entry->mode != VOIDmode; entry--)
7311 if (entry->reg == pr_reg)
7314 /* We can't find pr register. */
7318 offset = entry->offset - offset;
7319 pr_offset = (rounded_frame_size (d) + offset
7320 + SHMEDIA_REGS_STACK_ADJUST ());
7323 pr_offset = rounded_frame_size (d);
7325 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7326 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7328 tmp = gen_frame_mem (Pmode, tmp);
7329 emit_insn (GEN_MOV (tmp, ra));
7330 /* Tell this store isn't dead. */
7334 /* Clear variables at function end. */
7337 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7338 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7340 sh_need_epilogue_known = 0;
7344 sh_builtin_saveregs (void)
7346 /* First unnamed integer register. */
7347 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
7348 /* Number of integer registers we need to save. */
7349 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7350 /* First unnamed SFmode float reg */
7351 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
7352 /* Number of SFmode float regs to save. */
7353 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
7356 alias_set_type alias_set;
7362 int pushregs = n_intregs;
7364 while (pushregs < NPARM_REGS (SImode) - 1
7365 && (CALL_COOKIE_INT_REG_GET
7366 (crtl->args.info.call_cookie,
7367 NPARM_REGS (SImode) - pushregs)
7370 crtl->args.info.call_cookie
7371 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7376 if (pushregs == NPARM_REGS (SImode))
7377 crtl->args.info.call_cookie
7378 |= (CALL_COOKIE_INT_REG (0, 1)
7379 | CALL_COOKIE_STACKSEQ (pushregs - 1));
7381 crtl->args.info.call_cookie
7382 |= CALL_COOKIE_STACKSEQ (pushregs);
7384 crtl->args.pretend_args_size += 8 * n_intregs;
7386 if (TARGET_SHCOMPACT)
7390 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
7392 error ("__builtin_saveregs not supported by this subtarget");
7399 /* Allocate block of memory for the regs. */
7400 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7401 Or can assign_stack_local accept a 0 SIZE argument? */
7402 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7405 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
7406 else if (n_floatregs & 1)
7410 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7411 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7412 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7413 regbuf = change_address (regbuf, BLKmode, addr);
7415 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7419 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7420 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7421 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7422 emit_insn (gen_andsi3 (addr, addr, mask));
7423 regbuf = change_address (regbuf, BLKmode, addr);
7426 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7427 alias_set = get_varargs_alias_set ();
7428 set_mem_alias_set (regbuf, alias_set);
7431 This is optimized to only save the regs that are necessary. Explicitly
7432 named args need not be saved. */
7434 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7435 adjust_address (regbuf, BLKmode,
7436 n_floatregs * UNITS_PER_WORD),
7440 /* Return the address of the regbuf. */
7441 return XEXP (regbuf, 0);
7444 This is optimized to only save the regs that are necessary. Explicitly
7445 named args need not be saved.
7446 We explicitly build a pointer to the buffer because it halves the insn
7447 count when not optimizing (otherwise the pointer is built for each reg
7449 We emit the moves in reverse order so that we can use predecrement. */
7451 fpregs = copy_to_mode_reg (Pmode,
7452 plus_constant (XEXP (regbuf, 0),
7453 n_floatregs * UNITS_PER_WORD));
7454 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7457 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7459 emit_insn (gen_addsi3 (fpregs, fpregs,
7460 GEN_INT (-2 * UNITS_PER_WORD)));
7461 mem = change_address (regbuf, DFmode, fpregs);
7462 emit_move_insn (mem,
7463 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7465 regno = first_floatreg;
7468 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7469 mem = change_address (regbuf, SFmode, fpregs);
7470 emit_move_insn (mem,
7471 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7472 - (TARGET_LITTLE_ENDIAN != 0)));
7476 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7480 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7481 mem = change_address (regbuf, SFmode, fpregs);
7482 emit_move_insn (mem,
7483 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7486 /* Return the address of the regbuf. */
7487 return XEXP (regbuf, 0);
7490 /* Define the `__builtin_va_list' type for the ABI. */
7493 sh_build_builtin_va_list (void)
7495 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7498 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7499 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7500 return ptr_type_node;
7502 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7504 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
7506 f_next_o_limit = build_decl (FIELD_DECL,
7507 get_identifier ("__va_next_o_limit"),
7509 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
7511 f_next_fp_limit = build_decl (FIELD_DECL,
7512 get_identifier ("__va_next_fp_limit"),
7514 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
7517 DECL_FIELD_CONTEXT (f_next_o) = record;
7518 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7519 DECL_FIELD_CONTEXT (f_next_fp) = record;
7520 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7521 DECL_FIELD_CONTEXT (f_next_stack) = record;
7523 TYPE_FIELDS (record) = f_next_o;
7524 TREE_CHAIN (f_next_o) = f_next_o_limit;
7525 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7526 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7527 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7529 layout_type (record);
7534 /* Implement `va_start' for varargs and stdarg. */
7537 sh_va_start (tree valist, rtx nextarg)
7539 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7540 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7546 expand_builtin_saveregs ();
7547 std_expand_builtin_va_start (valist, nextarg);
7551 if ((! TARGET_SH2E && ! TARGET_SH4)
7552 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7554 std_expand_builtin_va_start (valist, nextarg);
7558 f_next_o = TYPE_FIELDS (va_list_type_node);
7559 f_next_o_limit = TREE_CHAIN (f_next_o);
7560 f_next_fp = TREE_CHAIN (f_next_o_limit);
7561 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7562 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7564 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7566 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7567 valist, f_next_o_limit, NULL_TREE);
7568 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7570 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7571 valist, f_next_fp_limit, NULL_TREE);
7572 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7573 valist, f_next_stack, NULL_TREE);
7575 /* Call __builtin_saveregs. */
7576 u = make_tree (sizetype, expand_builtin_saveregs ());
7577 u = fold_convert (ptr_type_node, u);
7578 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7579 TREE_SIDE_EFFECTS (t) = 1;
7580 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7582 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7587 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7588 size_int (UNITS_PER_WORD * nfp));
7589 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7590 TREE_SIDE_EFFECTS (t) = 1;
7591 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7593 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7594 TREE_SIDE_EFFECTS (t) = 1;
7595 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7597 nint = crtl->args.info.arg_count[SH_ARG_INT];
7602 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7603 size_int (UNITS_PER_WORD * nint));
7604 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7605 TREE_SIDE_EFFECTS (t) = 1;
7606 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7608 u = make_tree (ptr_type_node, nextarg);
7609 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7610 TREE_SIDE_EFFECTS (t) = 1;
7611 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7614 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7615 member, return it. */
7617 find_sole_member (tree type)
7619 tree field, member = NULL_TREE;
7621 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7623 if (TREE_CODE (field) != FIELD_DECL)
7625 if (!DECL_SIZE (field))
7627 if (integer_zerop (DECL_SIZE (field)))
7635 /* Implement `va_arg'. */
7638 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7639 gimple_seq *post_p ATTRIBUTE_UNUSED)
7641 HOST_WIDE_INT size, rsize;
7642 tree tmp, pptr_type_node;
7643 tree addr, lab_over = NULL, result = NULL;
7644 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7648 type = build_pointer_type (type);
7650 size = int_size_in_bytes (type);
7651 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7652 pptr_type_node = build_pointer_type (ptr_type_node);
7654 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7655 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7657 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7658 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7663 f_next_o = TYPE_FIELDS (va_list_type_node);
7664 f_next_o_limit = TREE_CHAIN (f_next_o);
7665 f_next_fp = TREE_CHAIN (f_next_o_limit);
7666 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7667 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7669 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7671 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7672 valist, f_next_o_limit, NULL_TREE);
7673 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7674 valist, f_next_fp, NULL_TREE);
7675 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7676 valist, f_next_fp_limit, NULL_TREE);
7677 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7678 valist, f_next_stack, NULL_TREE);
7680 /* Structures with a single member with a distinct mode are passed
7681 like their member. This is relevant if the latter has a REAL_TYPE
7682 or COMPLEX_TYPE type. */
7684 while (TREE_CODE (eff_type) == RECORD_TYPE
7685 && (member = find_sole_member (eff_type))
7686 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7687 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7688 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7690 tree field_type = TREE_TYPE (member);
7692 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7693 eff_type = field_type;
7696 gcc_assert ((TYPE_ALIGN (eff_type)
7697 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7698 || (TYPE_ALIGN (eff_type)
7699 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7704 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7706 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7707 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7708 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7713 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7716 addr = create_tmp_var (pptr_type_node, NULL);
7717 lab_false = create_artificial_label ();
7718 lab_over = create_artificial_label ();
7720 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
7724 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7726 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7728 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
7729 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7731 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
7732 tmp = next_fp_limit;
7733 if (size > 4 && !is_double)
7734 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp),
7735 unshare_expr (tmp), size_int (4 - size));
7736 tmp = build2 (GE_EXPR, boolean_type_node,
7737 unshare_expr (next_fp_tmp), unshare_expr (tmp));
7738 cmp = build3 (COND_EXPR, void_type_node, tmp,
7739 build1 (GOTO_EXPR, void_type_node,
7740 unshare_expr (lab_false)), NULL_TREE);
7742 gimplify_and_add (cmp, pre_p);
7744 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7745 || (is_double || size == 16))
7747 tmp = fold_convert (sizetype, next_fp_tmp);
7748 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7749 size_int (UNITS_PER_WORD));
7750 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7751 unshare_expr (next_fp_tmp), tmp);
7752 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
7755 gimplify_and_add (cmp, pre_p);
7757 #ifdef FUNCTION_ARG_SCmode_WART
7758 if (TYPE_MODE (eff_type) == SCmode
7759 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7761 tree subtype = TREE_TYPE (eff_type);
7765 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7766 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7769 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7770 real = get_initialized_tmp_var (real, pre_p, NULL);
7772 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
7773 if (type != eff_type)
7774 result = build1 (VIEW_CONVERT_EXPR, type, result);
7775 result = get_initialized_tmp_var (result, pre_p, NULL);
7777 #endif /* FUNCTION_ARG_SCmode_WART */
7779 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7780 gimplify_and_add (tmp, pre_p);
7782 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7783 gimplify_and_add (tmp, pre_p);
7785 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7786 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7787 gimplify_assign (unshare_expr (next_fp_tmp),
7788 unshare_expr (valist), pre_p);
7790 gimplify_assign (unshare_expr (valist),
7791 unshare_expr (next_fp_tmp), post_p);
7792 valist = next_fp_tmp;
7796 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7797 unshare_expr (next_o), size_int (rsize));
7798 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
7799 unshare_expr (next_o_limit));
7800 tmp = build3 (COND_EXPR, void_type_node, tmp,
7801 build1 (GOTO_EXPR, void_type_node,
7802 unshare_expr (lab_false)),
7804 gimplify_and_add (tmp, pre_p);
7806 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
7807 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7809 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7810 gimplify_and_add (tmp, pre_p);
7812 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7813 gimplify_and_add (tmp, pre_p);
7815 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7816 gimplify_assign (unshare_expr (next_o),
7817 unshare_expr (next_o_limit), pre_p);
7819 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7820 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7825 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7826 gimplify_and_add (tmp, pre_p);
7830 /* ??? In va-sh.h, there had been code to make values larger than
7831 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7833 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7836 gimplify_assign (result, tmp, pre_p);
7838 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7839 gimplify_and_add (tmp, pre_p);
7845 result = build_va_arg_indirect_ref (result);
7850 /* 64 bit floating points memory transfers are paired single precision loads
7851 or store. So DWARF information needs fixing in little endian (unless
7852 PR=SZ=1 in FPSCR). */
7854 sh_dwarf_register_span (rtx reg)
7856 unsigned regno = REGNO (reg);
7858 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
7862 gen_rtx_PARALLEL (VOIDmode,
7864 gen_rtx_REG (SFmode,
7865 DBX_REGISTER_NUMBER (regno+1)),
7866 gen_rtx_REG (SFmode,
7867 DBX_REGISTER_NUMBER (regno))));
7871 sh_promote_prototypes (const_tree type)
7877 return ! sh_attr_renesas_p (type);
7880 /* Whether an argument must be passed by reference. On SHcompact, we
7881 pretend arguments wider than 32-bits that would have been passed in
7882 registers are passed by reference, so that an SHmedia trampoline
7883 loads them into the full 64-bits registers. */
7886 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
7887 const_tree type, bool named)
7889 unsigned HOST_WIDE_INT size;
7892 size = int_size_in_bytes (type);
7894 size = GET_MODE_SIZE (mode);
7896 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
7898 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
7899 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
7900 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
7902 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
7903 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7910 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7911 const_tree type, bool named)
7913 if (targetm.calls.must_pass_in_stack (mode, type))
7916 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7917 wants to know about pass-by-reference semantics for incoming
7922 if (TARGET_SHCOMPACT)
7924 cum->byref = shcompact_byref (cum, mode, type, named);
7925 return cum->byref != 0;
7932 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7933 const_tree type, bool named ATTRIBUTE_UNUSED)
7935 /* ??? How can it possibly be correct to return true only on the
7936 caller side of the equation? Is there someplace else in the
7937 sh backend that's magically producing the copies? */
7938 return (cum->outgoing
7939 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
7940 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
7944 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7945 tree type, bool named ATTRIBUTE_UNUSED)
7950 && PASS_IN_REG_P (*cum, mode, type)
7951 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7952 && (ROUND_REG (*cum, mode)
7954 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
7955 : ROUND_ADVANCE (int_size_in_bytes (type)))
7956 > NPARM_REGS (mode)))
7957 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
7959 else if (!TARGET_SHCOMPACT
7960 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7961 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
7963 return words * UNITS_PER_WORD;
7967 /* Define where to put the arguments to a function.
7968 Value is zero to push the argument on the stack,
7969 or a hard register in which to store the argument.
7971 MODE is the argument's machine mode.
7972 TYPE is the data type of the argument (as a tree).
7973 This is null for libcalls where that information may
7975 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7976 the preceding args and about the function being called.
7977 NAMED is nonzero if this argument is a named parameter
7978 (otherwise it is an extra parameter matching an ellipsis).
7980 On SH the first args are normally in registers
7981 and the rest are pushed. Any arg that starts within the first
7982 NPARM_REGS words is at least partially passed in a register unless
7983 its data type forbids. */
7987 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7988 tree type, int named)
7990 if (! TARGET_SH5 && mode == VOIDmode)
7991 return GEN_INT (ca->renesas_abi ? 1 : 0);
7994 && PASS_IN_REG_P (*ca, mode, type)
7995 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
7999 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
8000 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
8002 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
8003 gen_rtx_REG (SFmode,
8005 + (ROUND_REG (*ca, mode) ^ 1)),
8007 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
8008 gen_rtx_REG (SFmode,
8010 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
8012 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
8015 /* If the alignment of a DF value causes an SF register to be
8016 skipped, we will use that skipped register for the next SF
8018 if ((TARGET_HITACHI || ca->renesas_abi)
8019 && ca->free_single_fp_reg
8021 return gen_rtx_REG (mode, ca->free_single_fp_reg);
8023 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
8024 ^ (mode == SFmode && TARGET_SH4
8025 && TARGET_LITTLE_ENDIAN != 0
8026 && ! TARGET_HITACHI && ! ca->renesas_abi);
8027 return gen_rtx_REG (mode, regno);
8033 if (mode == VOIDmode && TARGET_SHCOMPACT)
8034 return GEN_INT (ca->call_cookie);
8036 /* The following test assumes unnamed arguments are promoted to
8038 if (mode == SFmode && ca->free_single_fp_reg)
8039 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
8041 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
8042 && (named || ! ca->prototype_p)
8043 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
8045 if (! ca->prototype_p && TARGET_SHMEDIA)
8046 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
8048 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
8050 + ca->arg_count[(int) SH_ARG_FLOAT]);
8053 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
8054 && (! TARGET_SHCOMPACT
8055 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
8056 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
8059 return gen_rtx_REG (mode, (FIRST_PARM_REG
8060 + ca->arg_count[(int) SH_ARG_INT]));
8069 /* Update the data in CUM to advance over an argument
8070 of mode MODE and data type TYPE.
8071 (TYPE is null for libcalls where that information may not be
8075 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8076 tree type, int named)
8080 else if (TARGET_SH5)
8082 tree type2 = (ca->byref && type
8085 enum machine_mode mode2 = (ca->byref && type
8088 int dwords = ((ca->byref
8091 ? int_size_in_bytes (type2)
8092 : GET_MODE_SIZE (mode2)) + 7) / 8;
8093 int numregs = MIN (dwords, NPARM_REGS (SImode)
8094 - ca->arg_count[(int) SH_ARG_INT]);
8098 ca->arg_count[(int) SH_ARG_INT] += numregs;
8099 if (TARGET_SHCOMPACT
8100 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
8103 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8105 /* N.B. We want this also for outgoing. */
8106 ca->stack_regs += numregs;
8111 ca->stack_regs += numregs;
8112 ca->byref_regs += numregs;
8116 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8120 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8123 else if (dwords > numregs)
8125 int pushregs = numregs;
8127 if (TARGET_SHCOMPACT)
8128 ca->stack_regs += numregs;
8129 while (pushregs < NPARM_REGS (SImode) - 1
8130 && (CALL_COOKIE_INT_REG_GET
8132 NPARM_REGS (SImode) - pushregs)
8136 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
8140 if (numregs == NPARM_REGS (SImode))
8142 |= CALL_COOKIE_INT_REG (0, 1)
8143 | CALL_COOKIE_STACKSEQ (numregs - 1);
8146 |= CALL_COOKIE_STACKSEQ (numregs);
8149 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
8150 && (named || ! ca->prototype_p))
8152 if (mode2 == SFmode && ca->free_single_fp_reg)
8153 ca->free_single_fp_reg = 0;
8154 else if (ca->arg_count[(int) SH_ARG_FLOAT]
8155 < NPARM_REGS (SFmode))
8158 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
8160 - ca->arg_count[(int) SH_ARG_FLOAT]);
8162 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
8164 if (TARGET_SHCOMPACT && ! ca->prototype_p)
8166 if (ca->outgoing && numregs > 0)
8170 |= (CALL_COOKIE_INT_REG
8171 (ca->arg_count[(int) SH_ARG_INT]
8172 - numregs + ((numfpregs - 2) / 2),
8173 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
8176 while (numfpregs -= 2);
8178 else if (mode2 == SFmode && (named)
8179 && (ca->arg_count[(int) SH_ARG_FLOAT]
8180 < NPARM_REGS (SFmode)))
8181 ca->free_single_fp_reg
8182 = FIRST_FP_PARM_REG - numfpregs
8183 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
8189 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
8191 /* Note that we've used the skipped register. */
8192 if (mode == SFmode && ca->free_single_fp_reg)
8194 ca->free_single_fp_reg = 0;
8197 /* When we have a DF after an SF, there's an SF register that get
8198 skipped in order to align the DF value. We note this skipped
8199 register, because the next SF value will use it, and not the
8200 SF that follows the DF. */
8202 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
8204 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
8205 + BASE_ARG_REG (mode));
8209 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
8210 || PASS_IN_REG_P (*ca, mode, type))
8211 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
8212 = (ROUND_REG (*ca, mode)
8214 ? ROUND_ADVANCE (int_size_in_bytes (type))
8215 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
8218 /* The Renesas calling convention doesn't quite fit into this scheme since
8219 the address is passed like an invisible argument, but one that is always
8220 passed in memory. */
8222 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
8224 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8226 return gen_rtx_REG (Pmode, 2);
8229 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8232 sh_return_in_memory (const_tree type, const_tree fndecl)
8236 if (TYPE_MODE (type) == BLKmode)
8237 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
8239 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
8243 return (TYPE_MODE (type) == BLKmode
8244 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8245 && TREE_CODE (type) == RECORD_TYPE));
8249 /* We actually emit the code in sh_expand_prologue. We used to use
8250 a static variable to flag that we need to emit this code, but that
8251 doesn't when inlining, when functions are deferred and then emitted
8252 later. Fortunately, we already have two flags that are part of struct
8253 function that tell if a function uses varargs or stdarg. */
8255 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
8256 enum machine_mode mode,
8258 int *pretend_arg_size,
8259 int second_time ATTRIBUTE_UNUSED)
8261 gcc_assert (cfun->stdarg);
8262 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8264 int named_parm_regs, anon_parm_regs;
8266 named_parm_regs = (ROUND_REG (*ca, mode)
8268 ? ROUND_ADVANCE (int_size_in_bytes (type))
8269 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
8270 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
8271 if (anon_parm_regs > 0)
8272 *pretend_arg_size = anon_parm_regs * 4;
8277 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
8283 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
8285 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
8289 /* Define the offset between two registers, one to be eliminated, and
8290 the other its replacement, at the start of a routine. */
8293 initial_elimination_offset (int from, int to)
8296 int regs_saved_rounding = 0;
8297 int total_saved_regs_space;
8298 int total_auto_space;
8299 int save_flags = target_flags;
8301 HARD_REG_SET live_regs_mask;
8303 shmedia_space_reserved_for_target_registers = false;
8304 regs_saved = calc_live_regs (&live_regs_mask);
8305 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
8307 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
8309 shmedia_space_reserved_for_target_registers = true;
8310 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
8313 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
8314 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8315 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
8317 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8318 copy_flags = target_flags;
8319 target_flags = save_flags;
8321 total_saved_regs_space = regs_saved + regs_saved_rounding;
8323 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8324 return total_saved_regs_space + total_auto_space
8325 + crtl->args.info.byref_regs * 8;
8327 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8328 return total_saved_regs_space + total_auto_space
8329 + crtl->args.info.byref_regs * 8;
8331 /* Initial gap between fp and sp is 0. */
8332 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8335 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8336 return rounded_frame_size (0);
8338 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8339 return rounded_frame_size (0);
8341 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
8342 && (to == HARD_FRAME_POINTER_REGNUM
8343 || to == STACK_POINTER_REGNUM));
8346 int n = total_saved_regs_space;
8347 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
8348 save_schedule schedule;
8351 n += total_auto_space;
8353 /* If it wasn't saved, there's not much we can do. */
8354 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
8357 target_flags = copy_flags;
8359 sh5_schedule_saves (&live_regs_mask, &schedule, n);
8360 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
8361 if (entry->reg == pr_reg)
8363 target_flags = save_flags;
8364 return entry->offset;
8369 return total_auto_space;
8372 /* Parse the -mfixed-range= option string. */
8374 sh_fix_range (const char *const_str)
8377 char *str, *dash, *comma;
8379 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8380 REG2 are either register names or register numbers. The effect
8381 of this option is to mark the registers in the range from REG1 to
8382 REG2 as ``fixed'' so they won't be used by the compiler. */
8384 i = strlen (const_str);
8385 str = (char *) alloca (i + 1);
8386 memcpy (str, const_str, i + 1);
8390 dash = strchr (str, '-');
8393 warning (0, "value of -mfixed-range must have form REG1-REG2");
8397 comma = strchr (dash + 1, ',');
8401 first = decode_reg_name (str);
8404 warning (0, "unknown register name: %s", str);
8408 last = decode_reg_name (dash + 1);
8411 warning (0, "unknown register name: %s", dash + 1);
8419 warning (0, "%s-%s is an empty range", str, dash + 1);
8423 for (i = first; i <= last; ++i)
8424 fixed_regs[i] = call_used_regs[i] = 1;
8434 /* Insert any deferred function attributes from earlier pragmas. */
8436 sh_insert_attributes (tree node, tree *attributes)
8440 if (TREE_CODE (node) != FUNCTION_DECL)
8443 /* We are only interested in fields. */
8447 /* Append the attributes to the deferred attributes. */
8448 *sh_deferred_function_attributes_tail = *attributes;
8449 attrs = sh_deferred_function_attributes;
8453 /* Some attributes imply or require the interrupt attribute. */
8454 if (!lookup_attribute ("interrupt_handler", attrs)
8455 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8457 /* If we have a trapa_handler, but no interrupt_handler attribute,
8458 insert an interrupt_handler attribute. */
8459 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8460 /* We can't use sh_pr_interrupt here because that's not in the
8463 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8464 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8465 if the interrupt attribute is missing, we ignore the attribute
8467 else if (lookup_attribute ("sp_switch", attrs)
8468 || lookup_attribute ("trap_exit", attrs)
8469 || lookup_attribute ("nosave_low_regs", attrs)
8470 || lookup_attribute ("resbank", attrs))
8474 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8476 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8477 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8478 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8479 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8480 warning (OPT_Wattributes,
8481 "%qE attribute only applies to interrupt functions",
8482 TREE_PURPOSE (attrs));
8485 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8487 tail = &TREE_CHAIN (*tail);
8490 attrs = *attributes;
8494 /* Install the processed list. */
8495 *attributes = attrs;
8497 /* Clear deferred attributes. */
8498 sh_deferred_function_attributes = NULL_TREE;
8499 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8504 /* Supported attributes:
8506 interrupt_handler -- specifies this function is an interrupt handler.
8508 trapa_handler - like above, but don't save all registers.
8510 sp_switch -- specifies an alternate stack for an interrupt handler
8513 trap_exit -- use a trapa to exit an interrupt function instead of
8516 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8517 This is useful on the SH3 and upwards,
8518 which has a separate set of low regs for User and Supervisor modes.
8519 This should only be used for the lowest level of interrupts. Higher levels
8520 of interrupts must save the registers in case they themselves are
8523 renesas -- use Renesas calling/layout conventions (functions and
8526 resbank -- In case of an ISR, use a register bank to save registers
8527 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8530 const struct attribute_spec sh_attribute_table[] =
8532 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8533 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8534 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
8535 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
8536 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
8537 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8538 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8539 { "resbank", 0, 0, true, false, false, sh_handle_resbank_handler_attribute },
8540 { "function_vector", 1, 1, true, false, false, sh2a_handle_function_vector_handler_attribute },
8542 /* Symbian support adds three new attributes:
8543 dllexport - for exporting a function/variable that will live in a dll
8544 dllimport - for importing a function/variable from a dll
8546 Microsoft allows multiple declspecs in one __declspec, separating
8547 them with spaces. We do NOT support this. Instead, use __declspec
8549 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8550 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8552 { NULL, 0, 0, false, false, false, NULL }
8555 /* Handle a 'resbank' attribute. */
8557 sh_handle_resbank_handler_attribute (tree * node, tree name,
8558 tree args ATTRIBUTE_UNUSED,
8559 int flags ATTRIBUTE_UNUSED,
8560 bool * no_add_attrs)
8564 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8566 *no_add_attrs = true;
8568 if (TREE_CODE (*node) != FUNCTION_DECL)
8570 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8572 *no_add_attrs = true;
8578 /* Handle an "interrupt_handler" attribute; arguments as in
8579 struct attribute_spec.handler. */
8581 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8582 tree args ATTRIBUTE_UNUSED,
8583 int flags ATTRIBUTE_UNUSED,
8586 if (TREE_CODE (*node) != FUNCTION_DECL)
8588 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8590 *no_add_attrs = true;
8592 else if (TARGET_SHCOMPACT)
8594 error ("attribute interrupt_handler is not compatible with -m5-compact");
8595 *no_add_attrs = true;
8601 /* Handle an 'function_vector' attribute; arguments as in
8602 struct attribute_spec.handler. */
8604 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8605 tree args ATTRIBUTE_UNUSED,
8606 int flags ATTRIBUTE_UNUSED,
8607 bool * no_add_attrs)
8611 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8613 *no_add_attrs = true;
8615 else if (TREE_CODE (*node) != FUNCTION_DECL)
8617 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8619 *no_add_attrs = true;
8621 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8623 /* The argument must be a constant integer. */
8624 warning (OPT_Wattributes,
8625 "%qE attribute argument not an integer constant",
8627 *no_add_attrs = true;
8629 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8631 /* The argument value must be between 0 to 255. */
8632 warning (OPT_Wattributes,
8633 "%qE attribute argument should be between 0 to 255",
8635 *no_add_attrs = true;
8640 /* Returns 1 if current function has been assigned the attribute
8641 'function_vector'. */
8643 sh2a_is_function_vector_call (rtx x)
8645 if (GET_CODE (x) == SYMBOL_REF
8646 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8648 tree tr = SYMBOL_REF_DECL (x);
8650 if (sh2a_function_vector_p (tr))
8657 /* Returns the function vector number, if the the attribute
8658 'function_vector' is assigned, otherwise returns zero. */
8660 sh2a_get_function_vector_number (rtx x)
8665 if ((GET_CODE (x) == SYMBOL_REF)
8666 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8668 t = SYMBOL_REF_DECL (x);
8670 if (TREE_CODE (t) != FUNCTION_DECL)
8673 list = SH_ATTRIBUTES (t);
8676 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8678 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8682 list = TREE_CHAIN (list);
8691 /* Handle an "sp_switch" attribute; arguments as in
8692 struct attribute_spec.handler. */
8694 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8695 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8697 if (TREE_CODE (*node) != FUNCTION_DECL)
8699 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8701 *no_add_attrs = true;
8703 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8705 /* The argument must be a constant string. */
8706 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
8708 *no_add_attrs = true;
8714 /* Handle an "trap_exit" attribute; arguments as in
8715 struct attribute_spec.handler. */
8717 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8718 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8720 if (TREE_CODE (*node) != FUNCTION_DECL)
8722 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8724 *no_add_attrs = true;
8726 /* The argument specifies a trap number to be used in a trapa instruction
8727 at function exit (instead of an rte instruction). */
8728 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8730 /* The argument must be a constant integer. */
8731 warning (OPT_Wattributes, "%qE attribute argument not an "
8732 "integer constant", name);
8733 *no_add_attrs = true;
8740 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8741 tree name ATTRIBUTE_UNUSED,
8742 tree args ATTRIBUTE_UNUSED,
8743 int flags ATTRIBUTE_UNUSED,
8744 bool *no_add_attrs ATTRIBUTE_UNUSED)
8749 /* True if __attribute__((renesas)) or -mrenesas. */
8751 sh_attr_renesas_p (const_tree td)
8758 td = TREE_TYPE (td);
8759 if (td == error_mark_node)
8761 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8765 /* True if __attribute__((renesas)) or -mrenesas, for the current
8768 sh_cfun_attr_renesas_p (void)
8770 return sh_attr_renesas_p (current_function_decl);
8774 sh_cfun_interrupt_handler_p (void)
8776 return (lookup_attribute ("interrupt_handler",
8777 DECL_ATTRIBUTES (current_function_decl))
8781 /* Returns 1 if FUNC has been assigned the attribute
8782 "function_vector". */
8784 sh2a_function_vector_p (tree func)
8787 if (TREE_CODE (func) != FUNCTION_DECL)
8790 list = SH_ATTRIBUTES (func);
8793 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8796 list = TREE_CHAIN (list);
8801 /* Returns TRUE if given tree has the "resbank" attribute. */
8804 sh_cfun_resbank_handler_p (void)
8806 return ((lookup_attribute ("resbank",
8807 DECL_ATTRIBUTES (current_function_decl))
8809 && (lookup_attribute ("interrupt_handler",
8810 DECL_ATTRIBUTES (current_function_decl))
8811 != NULL_TREE) && TARGET_SH2A);
8814 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8817 sh_check_pch_target_flags (int old_flags)
8819 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8820 | MASK_SH_E | MASK_HARD_SH4
8821 | MASK_FPU_SINGLE | MASK_SH4))
8822 return _("created and used with different architectures / ABIs");
8823 if ((old_flags ^ target_flags) & MASK_HITACHI)
8824 return _("created and used with different ABIs");
8825 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8826 return _("created and used with different endianness");
8830 /* Predicates used by the templates. */
8832 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
8833 Used only in general_movsrc_operand. */
8836 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8848 /* Nonzero if OP is a floating point value with value 0.0. */
8851 fp_zero_operand (rtx op)
8855 if (GET_MODE (op) != SFmode)
8858 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8859 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
8862 /* Nonzero if OP is a floating point value with value 1.0. */
8865 fp_one_operand (rtx op)
8869 if (GET_MODE (op) != SFmode)
8872 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8873 return REAL_VALUES_EQUAL (r, dconst1);
8876 /* For -m4 and -m4-single-only, mode switching is used. If we are
8877 compiling without -mfmovd, movsf_ie isn't taken into account for
8878 mode switching. We could check in machine_dependent_reorg for
8879 cases where we know we are in single precision mode, but there is
8880 interface to find that out during reload, so we must avoid
8881 choosing an fldi alternative during reload and thus failing to
8882 allocate a scratch register for the constant loading. */
8886 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
8890 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8892 enum rtx_code code = GET_CODE (op);
8893 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
8896 /* Return the TLS type for TLS symbols, 0 for otherwise. */
8898 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8900 if (GET_CODE (op) != SYMBOL_REF)
8901 return TLS_MODEL_NONE;
8902 return SYMBOL_REF_TLS_MODEL (op);
8905 /* Return the destination address of a branch. */
8908 branch_dest (rtx branch)
8910 rtx dest = SET_SRC (PATTERN (branch));
8913 if (GET_CODE (dest) == IF_THEN_ELSE)
8914 dest = XEXP (dest, 1);
8915 dest = XEXP (dest, 0);
8916 dest_uid = INSN_UID (dest);
8917 return INSN_ADDRESSES (dest_uid);
8920 /* Return nonzero if REG is not used after INSN.
8921 We assume REG is a reload reg, and therefore does
8922 not live past labels. It may live past calls or jumps though. */
8924 reg_unused_after (rtx reg, rtx insn)
8929 /* If the reg is set by this instruction, then it is safe for our
8930 case. Disregard the case where this is a store to memory, since
8931 we are checking a register used in the store address. */
8932 set = single_set (insn);
8933 if (set && !MEM_P (SET_DEST (set))
8934 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8937 while ((insn = NEXT_INSN (insn)))
8943 code = GET_CODE (insn);
8946 /* If this is a label that existed before reload, then the register
8947 if dead here. However, if this is a label added by reorg, then
8948 the register may still be live here. We can't tell the difference,
8949 so we just ignore labels completely. */
8950 if (code == CODE_LABEL)
8955 if (code == JUMP_INSN)
8958 /* If this is a sequence, we must handle them all at once.
8959 We could have for instance a call that sets the target register,
8960 and an insn in a delay slot that uses the register. In this case,
8961 we must return 0. */
8962 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
8967 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8969 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
8970 rtx set = single_set (this_insn);
8972 if (CALL_P (this_insn))
8974 else if (JUMP_P (this_insn))
8976 if (INSN_ANNULLED_BRANCH_P (this_insn))
8981 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8983 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8985 if (!MEM_P (SET_DEST (set)))
8991 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
8996 else if (code == JUMP_INSN)
9000 set = single_set (insn);
9001 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9003 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9004 return !MEM_P (SET_DEST (set));
9005 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9008 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
9016 static GTY(()) rtx fpscr_rtx;
9018 get_fpscr_rtx (void)
9022 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
9023 REG_USERVAR_P (fpscr_rtx) = 1;
9024 mark_user_reg (fpscr_rtx);
9026 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
9027 mark_user_reg (fpscr_rtx);
9031 static GTY(()) tree fpscr_values;
9034 emit_fpu_switch (rtx scratch, int index)
9038 if (fpscr_values == NULL)
9042 t = build_index_type (integer_one_node);
9043 t = build_array_type (integer_type_node, t);
9044 t = build_decl (VAR_DECL, get_identifier ("__fpscr_values"), t);
9045 DECL_ARTIFICIAL (t) = 1;
9046 DECL_IGNORED_P (t) = 1;
9047 DECL_EXTERNAL (t) = 1;
9048 TREE_STATIC (t) = 1;
9049 TREE_PUBLIC (t) = 1;
9055 src = DECL_RTL (fpscr_values);
9056 if (!can_create_pseudo_p ())
9058 emit_move_insn (scratch, XEXP (src, 0));
9060 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
9061 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
9064 src = adjust_address (src, PSImode, index * 4);
9066 dst = get_fpscr_rtx ();
9067 emit_move_insn (dst, src);
9071 emit_sf_insn (rtx pat)
9077 emit_df_insn (rtx pat)
9083 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9085 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9089 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9091 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
9096 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9098 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9102 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9104 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
9108 static rtx get_free_reg (HARD_REG_SET);
9110 /* This function returns a register to use to load the address to load
9111 the fpscr from. Currently it always returns r1 or r7, but when we are
9112 able to use pseudo registers after combine, or have a better mechanism
9113 for choosing a register, it should be done here. */
9114 /* REGS_LIVE is the liveness information for the point for which we
9115 need this allocation. In some bare-bones exit blocks, r1 is live at the
9116 start. We can even have all of r0..r3 being live:
9117 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
9118 INSN before which new insns are placed with will clobber the register
9119 we return. If a basic block consists only of setting the return value
9120 register to a pseudo and using that register, the return value is not
9121 live before or after this block, yet we we'll insert our insns right in
9125 get_free_reg (HARD_REG_SET regs_live)
9127 if (! TEST_HARD_REG_BIT (regs_live, 1))
9128 return gen_rtx_REG (Pmode, 1);
9130 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
9131 there shouldn't be anything but a jump before the function end. */
9132 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
9133 return gen_rtx_REG (Pmode, 7);
9136 /* This function will set the fpscr from memory.
9137 MODE is the mode we are setting it to. */
9139 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
9141 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
9142 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
9145 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
9146 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
9149 /* Is the given character a logical line separator for the assembler? */
9150 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
9151 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
9155 sh_insn_length_adjustment (rtx insn)
9157 /* Instructions with unfilled delay slots take up an extra two bytes for
9158 the nop in the delay slot. */
9159 if (((NONJUMP_INSN_P (insn)
9160 && GET_CODE (PATTERN (insn)) != USE
9161 && GET_CODE (PATTERN (insn)) != CLOBBER)
9164 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9165 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
9166 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
9167 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
9170 /* SH2e has a bug that prevents the use of annulled branches, so if
9171 the delay slot is not filled, we'll have to put a NOP in it. */
9172 if (sh_cpu_attr == CPU_SH2E
9174 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9175 && GET_CODE (PATTERN (insn)) != ADDR_VEC
9176 && get_attr_type (insn) == TYPE_CBRANCH
9177 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
9180 /* sh-dsp parallel processing insn take four bytes instead of two. */
9182 if (NONJUMP_INSN_P (insn))
9185 rtx body = PATTERN (insn);
9188 int maybe_label = 1;
9190 if (GET_CODE (body) == ASM_INPUT)
9191 templ = XSTR (body, 0);
9192 else if (asm_noperands (body) >= 0)
9194 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
9203 while (c == ' ' || c == '\t');
9204 /* all sh-dsp parallel-processing insns start with p.
9205 The only non-ppi sh insn starting with p is pref.
9206 The only ppi starting with pr is prnd. */
9207 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
9209 /* The repeat pseudo-insn expands two three insns, a total of
9210 six bytes in size. */
9211 else if ((c == 'r' || c == 'R')
9212 && ! strncasecmp ("epeat", templ, 5))
9214 while (c && c != '\n'
9215 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
9217 /* If this is a label, it is obviously not a ppi insn. */
9218 if (c == ':' && maybe_label)
9223 else if (c == '\'' || c == '"')
9228 maybe_label = c != ':';
9236 /* Return TRUE for a valid displacement for the REG+disp addressing
9239 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
9240 into the FRx registers. We implement this by setting the maximum offset
9241 to zero when the value is SFmode. This also restricts loading of SFmode
9242 values into the integer registers, but that can't be helped. */
9244 /* The SH allows a displacement in a QI or HI amode, but only when the
9245 other operand is R0. GCC doesn't handle this very well, so we forgot
9248 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
9249 DI can be any number 0..60. */
9252 sh_legitimate_index_p (enum machine_mode mode, rtx op)
9254 if (CONST_INT_P (op))
9260 /* Check if this the address of an unaligned load / store. */
9261 if (mode == VOIDmode)
9262 return CONST_OK_FOR_I06 (INTVAL (op));
9264 size = GET_MODE_SIZE (mode);
9265 return (!(INTVAL (op) & (size - 1))
9266 && INTVAL (op) >= -512 * size
9267 && INTVAL (op) < 512 * size);
9272 if (GET_MODE_SIZE (mode) == 1
9273 && (unsigned) INTVAL (op) < 4096)
9277 if ((GET_MODE_SIZE (mode) == 4
9278 && (unsigned) INTVAL (op) < 64
9279 && !(INTVAL (op) & 3)
9280 && !(TARGET_SH2E && mode == SFmode))
9281 || (GET_MODE_SIZE (mode) == 4
9282 && (unsigned) INTVAL (op) < 16383
9283 && !(INTVAL (op) & 3) && TARGET_SH2A))
9286 if ((GET_MODE_SIZE (mode) == 8
9287 && (unsigned) INTVAL (op) < 60
9288 && !(INTVAL (op) & 3)
9289 && !((TARGET_SH4 || TARGET_SH2A) && mode == DFmode))
9290 || ((GET_MODE_SIZE (mode)==8)
9291 && (unsigned) INTVAL (op) < 8192
9292 && !(INTVAL (op) & (TARGET_SH2A_DOUBLE ? 7 : 3))
9293 && (TARGET_SH2A && mode == DFmode)))
9300 /* Recognize an RTL expression that is a valid memory address for
9302 The MODE argument is the machine mode for the MEM expression
9303 that wants to use this address.
9311 sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9313 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9315 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9317 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9319 else if (GET_CODE (x) == PLUS
9320 && (mode != PSImode || reload_completed))
9322 rtx xop0 = XEXP (x, 0);
9323 rtx xop1 = XEXP (x, 1);
9325 if (GET_MODE_SIZE (mode) <= 8
9326 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9327 && sh_legitimate_index_p (mode, xop1))
9330 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode
9331 || ((xop0 == stack_pointer_rtx
9332 || xop0 == hard_frame_pointer_rtx)
9333 && REG_P (xop1) && REGNO (xop1) == R0_REG)
9334 || ((xop1 == stack_pointer_rtx
9335 || xop1 == hard_frame_pointer_rtx)
9336 && REG_P (xop0) && REGNO (xop0) == R0_REG))
9337 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4)
9338 || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8)
9339 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
9340 && TARGET_FMOVD && mode == DFmode)))
9342 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9343 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9345 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9346 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9354 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9355 isn't protected by a PIC unspec. */
9357 nonpic_symbol_mentioned_p (rtx x)
9359 register const char *fmt;
9362 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9363 || GET_CODE (x) == PC)
9366 /* We don't want to look into the possible MEM location of a
9367 CONST_DOUBLE, since we're not going to use it, in general. */
9368 if (GET_CODE (x) == CONST_DOUBLE)
9371 if (GET_CODE (x) == UNSPEC
9372 && (XINT (x, 1) == UNSPEC_PIC
9373 || XINT (x, 1) == UNSPEC_GOT
9374 || XINT (x, 1) == UNSPEC_GOTOFF
9375 || XINT (x, 1) == UNSPEC_GOTPLT
9376 || XINT (x, 1) == UNSPEC_GOTTPOFF
9377 || XINT (x, 1) == UNSPEC_DTPOFF
9378 || XINT (x, 1) == UNSPEC_PLT
9379 || XINT (x, 1) == UNSPEC_SYMOFF
9380 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
9383 fmt = GET_RTX_FORMAT (GET_CODE (x));
9384 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9390 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9391 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9394 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9401 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9402 @GOTOFF in `reg'. */
9404 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
9407 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
9410 if (GET_CODE (orig) == LABEL_REF
9411 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
9414 reg = gen_reg_rtx (Pmode);
9416 emit_insn (gen_symGOTOFF2reg (reg, orig));
9419 else if (GET_CODE (orig) == SYMBOL_REF)
9422 reg = gen_reg_rtx (Pmode);
9424 emit_insn (gen_symGOT2reg (reg, orig));
9430 /* Try machine-dependent ways of modifying an illegitimate address
9431 to be legitimate. If we find one, return the new, valid address.
9432 Otherwise, return X.
9434 For the SH, if X is almost suitable for indexing, but the offset is
9435 out of range, convert it into a normal form so that CSE has a chance
9436 of reducing the number of address registers used. */
9439 sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
9442 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9444 if (GET_CODE (x) == PLUS
9445 && (GET_MODE_SIZE (mode) == 4
9446 || GET_MODE_SIZE (mode) == 8)
9447 && CONST_INT_P (XEXP (x, 1))
9448 && BASE_REGISTER_RTX_P (XEXP (x, 0))
9450 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
9451 && ! (TARGET_SH2E && mode == SFmode))
9453 rtx index_rtx = XEXP (x, 1);
9454 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9457 /* On rare occasions, we might get an unaligned pointer
9458 that is indexed in a way to give an aligned address.
9459 Therefore, keep the lower two bits in offset_base. */
9460 /* Instead of offset_base 128..131 use 124..127, so that
9461 simple add suffices. */
9463 offset_base = ((offset + 4) & ~60) - 4;
9465 offset_base = offset & ~60;
9467 /* Sometimes the normal form does not suit DImode. We
9468 could avoid that by using smaller ranges, but that
9469 would give less optimized code when SImode is
9471 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9473 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9474 GEN_INT (offset_base), NULL_RTX, 0,
9477 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9484 /* Mark the use of a constant in the literal table. If the constant
9485 has multiple labels, make it unique. */
9487 mark_constant_pool_use (rtx x)
9489 rtx insn, lab, pattern;
9494 switch (GET_CODE (x))
9504 /* Get the first label in the list of labels for the same constant
9505 and delete another labels in the list. */
9507 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
9510 || LABEL_REFS (insn) != NEXT_INSN (insn))
9515 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
9516 INSN_DELETED_P (insn) = 1;
9518 /* Mark constants in a window. */
9519 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
9521 if (!NONJUMP_INSN_P (insn))
9524 pattern = PATTERN (insn);
9525 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
9528 switch (XINT (pattern, 1))
9530 case UNSPECV_CONST2:
9531 case UNSPECV_CONST4:
9532 case UNSPECV_CONST8:
9533 XVECEXP (pattern, 0, 1) = const1_rtx;
9535 case UNSPECV_WINDOW_END:
9536 if (XVECEXP (pattern, 0, 0) == x)
9539 case UNSPECV_CONST_END:
9549 /* Return true if it's possible to redirect BRANCH1 to the destination
9550 of an unconditional jump BRANCH2. We only want to do this if the
9551 resulting branch will have a short displacement. */
9553 sh_can_redirect_branch (rtx branch1, rtx branch2)
9555 if (flag_expensive_optimizations && simplejump_p (branch2))
9557 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
9561 for (distance = 0, insn = NEXT_INSN (branch1);
9562 insn && distance < 256;
9563 insn = PREV_INSN (insn))
9568 distance += get_attr_length (insn);
9570 for (distance = 0, insn = NEXT_INSN (branch1);
9571 insn && distance < 256;
9572 insn = NEXT_INSN (insn))
9577 distance += get_attr_length (insn);
9583 /* Return nonzero if register old_reg can be renamed to register new_reg. */
9585 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
9586 unsigned int new_reg)
9588 /* Interrupt functions can only use registers that have already been
9589 saved by the prologue, even if they would normally be
9592 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
9598 /* Function to update the integer COST
9599 based on the relationship between INSN that is dependent on
9600 DEP_INSN through the dependence LINK. The default is to make no
9601 adjustment to COST. This can be used for example to specify to
9602 the scheduler that an output- or anti-dependence does not incur
9603 the same cost as a data-dependence. The return value should be
9604 the new value for COST. */
9606 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
9612 /* On SHmedia, if the dependence is an anti-dependence or
9613 output-dependence, there is no cost. */
9614 if (REG_NOTE_KIND (link) != 0)
9616 /* However, dependencies between target register loads and
9617 uses of the register in a subsequent block that are separated
9618 by a conditional branch are not modelled - we have to do with
9619 the anti-dependency between the target register load and the
9620 conditional branch that ends the current block. */
9621 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
9622 && GET_CODE (PATTERN (dep_insn)) == SET
9623 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
9624 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
9625 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
9627 int orig_cost = cost;
9628 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
9629 rtx target = ((! note
9630 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
9631 ? insn : JUMP_LABEL (insn));
9632 /* On the likely path, the branch costs 1, on the unlikely path,
9636 target = next_active_insn (target);
9637 while (target && ! flow_dependent_p (target, dep_insn)
9639 /* If two branches are executed in immediate succession, with the
9640 first branch properly predicted, this causes a stall at the
9641 second branch, hence we won't need the target for the
9642 second branch for two cycles after the launch of the first
9644 if (cost > orig_cost - 2)
9645 cost = orig_cost - 2;
9651 else if (get_attr_is_mac_media (insn)
9652 && get_attr_is_mac_media (dep_insn))
9655 else if (! reload_completed
9656 && GET_CODE (PATTERN (insn)) == SET
9657 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
9658 && GET_CODE (PATTERN (dep_insn)) == SET
9659 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
9662 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
9663 that is needed at the target. */
9664 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
9665 && ! flow_dependent_p (insn, dep_insn))
9668 else if (REG_NOTE_KIND (link) == 0)
9670 enum attr_type type;
9673 if (recog_memoized (insn) < 0
9674 || recog_memoized (dep_insn) < 0)
9677 dep_set = single_set (dep_insn);
9679 /* The latency that we specify in the scheduling description refers
9680 to the actual output, not to an auto-increment register; for that,
9681 the latency is one. */
9682 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9684 rtx set = single_set (insn);
9687 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9688 && (!MEM_P (SET_DEST (set))
9689 || !reg_mentioned_p (SET_DEST (dep_set),
9690 XEXP (SET_DEST (set), 0))))
9693 /* The only input for a call that is timing-critical is the
9694 function's address. */
9697 rtx call = PATTERN (insn);
9699 if (GET_CODE (call) == PARALLEL)
9700 call = XVECEXP (call, 0 ,0);
9701 if (GET_CODE (call) == SET)
9702 call = SET_SRC (call);
9703 if (GET_CODE (call) == CALL && MEM_P (XEXP (call, 0))
9704 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9705 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9706 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9707 cost -= TARGET_SH4_300 ? 3 : 6;
9709 /* Likewise, the most timing critical input for an sfuncs call
9710 is the function address. However, sfuncs typically start
9711 using their arguments pretty quickly.
9712 Assume a four cycle delay for SH4 before they are needed.
9713 Cached ST40-300 calls are quicker, so assume only a one
9715 ??? Maybe we should encode the delays till input registers
9716 are needed by sfuncs into the sfunc call insn. */
9717 /* All sfunc calls are parallels with at least four components.
9718 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9719 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9720 && XVECLEN (PATTERN (insn), 0) >= 4
9721 && (reg = sfunc_uses_reg (insn)))
9723 if (! reg_set_p (reg, dep_insn))
9724 cost -= TARGET_SH4_300 ? 1 : 4;
9726 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9728 enum attr_type dep_type = get_attr_type (dep_insn);
9730 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9732 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9733 && (type = get_attr_type (insn)) != TYPE_CALL
9734 && type != TYPE_SFUNC)
9736 /* When the preceding instruction loads the shift amount of
9737 the following SHAD/SHLD, the latency of the load is increased
9739 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9740 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
9741 && reg_overlap_mentioned_p (SET_DEST (dep_set),
9742 XEXP (SET_SRC (single_set (insn)),
9745 /* When an LS group instruction with a latency of less than
9746 3 cycles is followed by a double-precision floating-point
9747 instruction, FIPR, or FTRV, the latency of the first
9748 instruction is increased to 3 cycles. */
9750 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9751 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9753 /* The lsw register of a double-precision computation is ready one
9755 else if (reload_completed
9756 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9757 && (use_pat = single_set (insn))
9758 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9762 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9763 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9766 else if (TARGET_SH4_300)
9768 /* Stores need their input register two cycles later. */
9769 if (dep_set && cost >= 1
9770 && ((type = get_attr_type (insn)) == TYPE_STORE
9771 || type == TYPE_PSTORE
9772 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9774 rtx set = single_set (insn);
9776 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9777 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9780 /* But don't reduce the cost below 1 if the address depends
9781 on a side effect of dep_insn. */
9783 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9789 /* An anti-dependence penalty of two applies if the first insn is a double
9790 precision fadd / fsub / fmul. */
9791 else if (!TARGET_SH4_300
9792 && REG_NOTE_KIND (link) == REG_DEP_ANTI
9793 && recog_memoized (dep_insn) >= 0
9794 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9795 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9796 /* A lot of alleged anti-flow dependences are fake,
9797 so check this one is real. */
9798 && flow_dependent_p (dep_insn, insn))
9804 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9805 if DEP_INSN is anti-flow dependent on INSN. */
9807 flow_dependent_p (rtx insn, rtx dep_insn)
9809 rtx tmp = PATTERN (insn);
9811 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9812 return tmp == NULL_RTX;
9815 /* A helper function for flow_dependent_p called through note_stores. */
9817 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9819 rtx * pinsn = (rtx *) data;
9821 if (*pinsn && reg_referenced_p (x, *pinsn))
9825 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9826 'special function' patterns (type sfunc) that clobber pr, but that
9827 do not look like function calls to leaf_function_p. Hence we must
9828 do this extra check. */
9832 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9835 /* Return where to allocate pseudo for a given hard register initial
9838 sh_allocate_initial_value (rtx hard_reg)
9842 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
9844 if (current_function_is_leaf
9845 && ! sh_pr_n_sets ()
9846 && ! (TARGET_SHCOMPACT
9847 && ((crtl->args.info.call_cookie
9848 & ~ CALL_COOKIE_RET_TRAMP (1))
9849 || crtl->saves_all_registers)))
9852 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
9860 /* This function returns "2" to indicate dual issue for the SH4
9861 processor. To be used by the DFA pipeline description. */
9863 sh_issue_rate (void)
9865 if (TARGET_SUPERSCALAR)
9871 /* Functions for ready queue reordering for sched1. */
9873 /* Get weight for mode for a set x. */
9875 find_set_regmode_weight (rtx x, enum machine_mode mode)
9877 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9879 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9881 if (REG_P (SET_DEST (x)))
9883 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9893 /* Get regmode weight for insn. */
9895 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
9897 short reg_weight = 0;
9900 /* Increment weight for each register born here. */
9902 reg_weight += find_set_regmode_weight (x, mode);
9903 if (GET_CODE (x) == PARALLEL)
9906 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9908 x = XVECEXP (PATTERN (insn), 0, j);
9909 reg_weight += find_set_regmode_weight (x, mode);
9912 /* Decrement weight for each register that dies here. */
9913 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9915 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9917 rtx note = XEXP (x, 0);
9918 if (REG_P (note) && GET_MODE (note) == mode)
9925 /* Calculate regmode weights for all insns of a basic block. */
9927 find_regmode_weight (basic_block b, enum machine_mode mode)
9929 rtx insn, next_tail, head, tail;
9931 get_ebb_head_tail (b, b, &head, &tail);
9932 next_tail = NEXT_INSN (tail);
9934 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9936 /* Handle register life information. */
9941 INSN_REGMODE_WEIGHT (insn, mode) =
9942 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
9943 else if (mode == SImode)
9944 INSN_REGMODE_WEIGHT (insn, mode) =
9945 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
9949 /* Comparison function for ready queue sorting. */
9951 rank_for_reorder (const void *x, const void *y)
9953 rtx tmp = *(const rtx *) y;
9954 rtx tmp2 = *(const rtx *) x;
9956 /* The insn in a schedule group should be issued the first. */
9957 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
9958 return SCHED_GROUP_P (tmp2) ? 1 : -1;
9960 /* If insns are equally good, sort by INSN_LUID (original insn order), This
9961 minimizes instruction movement, thus minimizing sched's effect on
9962 register pressure. */
9963 return INSN_LUID (tmp) - INSN_LUID (tmp2);
9966 /* Resort the array A in which only element at index N may be out of order. */
9968 swap_reorder (rtx *a, int n)
9970 rtx insn = a[n - 1];
9973 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
9981 #define SCHED_REORDER(READY, N_READY) \
9984 if ((N_READY) == 2) \
9985 swap_reorder (READY, N_READY); \
9986 else if ((N_READY) > 2) \
9987 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
9991 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
9994 ready_reorder (rtx *ready, int nready)
9996 SCHED_REORDER (ready, nready);
9999 /* Count life regions of r0 for a block. */
10001 find_r0_life_regions (basic_block b)
10010 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
10021 insn = BB_HEAD (b);
10023 r0_reg = gen_rtx_REG (SImode, R0_REG);
10028 if (find_regno_note (insn, REG_DEAD, R0_REG))
10034 && (pset = single_set (insn))
10035 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
10036 && !find_regno_note (insn, REG_UNUSED, R0_REG))
10044 insn = NEXT_INSN (insn);
10046 return set - death;
10049 /* Calculate regmode weights for all insns of all basic block. */
10051 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
10052 int verbose ATTRIBUTE_UNUSED,
10057 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
10058 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
10059 r0_life_regions = 0;
10061 FOR_EACH_BB_REVERSE (b)
10063 find_regmode_weight (b, SImode);
10064 find_regmode_weight (b, SFmode);
10065 if (!reload_completed)
10066 r0_life_regions += find_r0_life_regions (b);
10069 CURR_REGMODE_PRESSURE (SImode) = 0;
10070 CURR_REGMODE_PRESSURE (SFmode) = 0;
10076 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
10077 int verbose ATTRIBUTE_UNUSED)
10079 if (regmode_weight[0])
10081 free (regmode_weight[0]);
10082 regmode_weight[0] = NULL;
10084 if (regmode_weight[1])
10086 free (regmode_weight[1]);
10087 regmode_weight[1] = NULL;
10091 /* The scalar modes supported differs from the default version in TImode
10092 for 32-bit SHMEDIA. */
10094 sh_scalar_mode_supported_p (enum machine_mode mode)
10096 if (TARGET_SHMEDIA32 && mode == TImode)
10099 return default_scalar_mode_supported_p (mode);
10102 /* Cache the can_issue_more so that we can return it from reorder2. Also,
10103 keep count of register pressures on SImode and SFmode. */
10105 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
10106 int sched_verbose ATTRIBUTE_UNUSED,
10108 int can_issue_more)
10110 if (GET_CODE (PATTERN (insn)) != USE
10111 && GET_CODE (PATTERN (insn)) != CLOBBER)
10112 cached_can_issue_more = can_issue_more - 1;
10114 cached_can_issue_more = can_issue_more;
10116 if (reload_completed)
10117 return cached_can_issue_more;
10119 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
10120 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
10122 return cached_can_issue_more;
10126 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
10127 int verbose ATTRIBUTE_UNUSED,
10128 int veclen ATTRIBUTE_UNUSED)
10130 CURR_REGMODE_PRESSURE (SImode) = 0;
10131 CURR_REGMODE_PRESSURE (SFmode) = 0;
10134 /* Some magic numbers. */
10135 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10136 functions that already have high pressure on r0. */
10137 #define R0_MAX_LIFE_REGIONS 2
10138 /* Register Pressure thresholds for SImode and SFmode registers. */
10139 #define SIMODE_MAX_WEIGHT 5
10140 #define SFMODE_MAX_WEIGHT 10
10142 /* Return true if the pressure is high for MODE. */
10144 high_pressure (enum machine_mode mode)
10146 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10147 functions that already have high pressure on r0. */
10148 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
10151 if (mode == SFmode)
10152 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
10154 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
10157 /* Reorder ready queue if register pressure is high. */
10159 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
10160 int sched_verbose ATTRIBUTE_UNUSED,
10163 int clock_var ATTRIBUTE_UNUSED)
10165 if (reload_completed)
10166 return sh_issue_rate ();
10168 if (high_pressure (SFmode) || high_pressure (SImode))
10170 ready_reorder (ready, *n_readyp);
10173 return sh_issue_rate ();
10176 /* Skip cycles if the current register pressure is high. */
10178 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
10179 int sched_verbose ATTRIBUTE_UNUSED,
10180 rtx *ready ATTRIBUTE_UNUSED,
10181 int *n_readyp ATTRIBUTE_UNUSED,
10182 int clock_var ATTRIBUTE_UNUSED)
10184 if (reload_completed)
10185 return cached_can_issue_more;
10187 if (high_pressure(SFmode) || high_pressure (SImode))
10190 return cached_can_issue_more;
10193 /* Skip cycles without sorting the ready queue. This will move insn from
10194 Q->R. If this is the last cycle we are skipping; allow sorting of ready
10195 queue by sh_reorder. */
10197 /* Generally, skipping these many cycles are sufficient for all insns to move
10199 #define MAX_SKIPS 8
10202 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
10203 int sched_verbose ATTRIBUTE_UNUSED,
10204 rtx insn ATTRIBUTE_UNUSED,
10205 int last_clock_var,
10209 if (reload_completed)
10214 if ((clock_var - last_clock_var) < MAX_SKIPS)
10219 /* If this is the last cycle we are skipping, allow reordering of R. */
10220 if ((clock_var - last_clock_var) == MAX_SKIPS)
10232 /* SHmedia requires registers for branches, so we can't generate new
10233 branches past reload. */
10235 sh_cannot_modify_jumps_p (void)
10237 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
10240 static enum reg_class
10241 sh_target_reg_class (void)
10243 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
10247 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
10249 HARD_REG_SET dummy;
10254 if (! shmedia_space_reserved_for_target_registers)
10256 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
10258 if (calc_live_regs (&dummy) >= 6 * 8)
10264 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
10266 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
10270 On the SH1..SH4, the trampoline looks like
10271 2 0002 D202 mov.l l2,r2
10272 1 0000 D301 mov.l l1,r3
10273 3 0004 422B jmp @r2
10275 5 0008 00000000 l1: .long area
10276 6 000c 00000000 l2: .long function
10278 SH5 (compact) uses r1 instead of r3 for the static chain. */
10281 /* Emit RTL insns to initialize the variable parts of a trampoline.
10282 FNADDR is an RTX for the address of the function's pure code.
10283 CXT is an RTX for the static chain value for the function. */
10286 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
10288 rtx tramp_mem = gen_frame_mem (BLKmode, tramp);
10290 if (TARGET_SHMEDIA64)
10295 rtx movi1 = GEN_INT (0xcc000010);
10296 rtx shori1 = GEN_INT (0xc8000010);
10299 /* The following trampoline works within a +- 128 KB range for cxt:
10300 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10301 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10302 gettr tr1,r1; blink tr0,r63 */
10303 /* Address rounding makes it hard to compute the exact bounds of the
10304 offset for this trampoline, but we have a rather generous offset
10305 range, so frame_offset should do fine as an upper bound. */
10306 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
10308 /* ??? could optimize this trampoline initialization
10309 by writing DImode words with two insns each. */
10310 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
10311 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
10312 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
10313 insn = gen_rtx_AND (DImode, insn, mask);
10314 /* Or in ptb/u .,tr1 pattern */
10315 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
10316 insn = force_operand (insn, NULL_RTX);
10317 insn = gen_lowpart (SImode, insn);
10318 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
10319 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
10320 insn = gen_rtx_AND (DImode, insn, mask);
10321 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
10322 insn = gen_lowpart (SImode, insn);
10323 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
10324 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
10325 insn = gen_rtx_AND (DImode, insn, mask);
10326 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10327 insn = gen_lowpart (SImode, insn);
10328 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
10329 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
10330 insn = gen_rtx_AND (DImode, insn, mask);
10331 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10332 insn = gen_lowpart (SImode, insn);
10333 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
10334 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
10335 insn = gen_rtx_AND (DImode, insn, mask);
10336 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10337 insn = gen_lowpart (SImode, insn);
10338 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
10339 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
10340 GEN_INT (0x6bf10600));
10341 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
10342 GEN_INT (0x4415fc10));
10343 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
10344 GEN_INT (0x4401fff0));
10345 emit_insn (gen_ic_invalidate_line (tramp));
10348 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
10349 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
10351 tramp_templ = gen_datalabel_ref (tramp_templ);
10353 src = gen_const_mem (BLKmode, tramp_templ);
10354 set_mem_align (dst, 256);
10355 set_mem_align (src, 64);
10356 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
10358 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
10359 emit_move_insn (adjust_address (tramp_mem, Pmode,
10360 fixed_len + GET_MODE_SIZE (Pmode)),
10362 emit_insn (gen_ic_invalidate_line (tramp));
10365 else if (TARGET_SHMEDIA)
10367 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10368 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10369 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
10370 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
10371 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
10372 rotated 10 right, and higher 16 bit of every 32 selected. */
10374 = force_reg (V2HImode, (simplify_gen_subreg
10375 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
10376 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
10377 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
10379 tramp = force_reg (Pmode, tramp);
10380 fnaddr = force_reg (SImode, fnaddr);
10381 cxt = force_reg (SImode, cxt);
10382 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
10383 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
10385 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
10386 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10387 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
10388 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
10389 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
10390 gen_rtx_SUBREG (V2HImode, cxt, 0),
10392 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
10393 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10394 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
10395 if (TARGET_LITTLE_ENDIAN)
10397 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
10398 emit_insn (gen_mextr4 (quad2, cxtload, blink));
10402 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
10403 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
10405 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
10406 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
10407 emit_insn (gen_ic_invalidate_line (tramp));
10410 else if (TARGET_SHCOMPACT)
10412 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
10415 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
10416 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
10418 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
10419 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
10421 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
10422 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
10423 if (TARGET_HARVARD)
10425 if (!TARGET_INLINE_IC_INVALIDATE
10426 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
10427 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10428 FUNCTION_ORDINARY),
10429 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
10431 emit_insn (gen_ic_invalidate_line (tramp));
10435 /* FIXME: This is overly conservative. A SHcompact function that
10436 receives arguments ``by reference'' will have them stored in its
10437 own stack frame, so it must not pass pointers or references to
10438 these arguments to other functions by means of sibling calls. */
10439 /* If PIC, we cannot make sibling calls to global functions
10440 because the PLT requires r12 to be live. */
10442 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10445 && (! TARGET_SHCOMPACT
10446 || crtl->args.info.stack_regs == 0)
10447 && ! sh_cfun_interrupt_handler_p ()
10449 || (decl && ! TREE_PUBLIC (decl))
10450 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
10453 /* Machine specific built-in functions. */
10455 struct builtin_description
10457 const enum insn_code icode;
10458 const char *const name;
10462 /* describe number and signedness of arguments; arg[0] == result
10463 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
10464 /* 9: 64-bit pointer, 10: 32-bit pointer */
10465 static const char signature_args[][4] =
10467 #define SH_BLTIN_V2SI2 0
10469 #define SH_BLTIN_V4HI2 1
10471 #define SH_BLTIN_V2SI3 2
10473 #define SH_BLTIN_V4HI3 3
10475 #define SH_BLTIN_V8QI3 4
10477 #define SH_BLTIN_MAC_HISI 5
10479 #define SH_BLTIN_SH_HI 6
10481 #define SH_BLTIN_SH_SI 7
10483 #define SH_BLTIN_V4HI2V2SI 8
10485 #define SH_BLTIN_V4HI2V8QI 9
10487 #define SH_BLTIN_SISF 10
10489 #define SH_BLTIN_LDUA_L 11
10491 #define SH_BLTIN_LDUA_Q 12
10493 #define SH_BLTIN_STUA_L 13
10495 #define SH_BLTIN_STUA_Q 14
10497 #define SH_BLTIN_LDUA_L64 15
10499 #define SH_BLTIN_LDUA_Q64 16
10501 #define SH_BLTIN_STUA_L64 17
10503 #define SH_BLTIN_STUA_Q64 18
10505 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10506 #define SH_BLTIN_2 19
10507 #define SH_BLTIN_SU 19
10509 #define SH_BLTIN_3 20
10510 #define SH_BLTIN_SUS 20
10512 #define SH_BLTIN_PSSV 21
10514 #define SH_BLTIN_XXUU 22
10515 #define SH_BLTIN_UUUU 22
10517 #define SH_BLTIN_PV 23
10520 /* mcmv: operands considered unsigned. */
10521 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
10522 /* mperm: control value considered unsigned int. */
10523 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
10524 /* mshards_q: returns signed short. */
10525 /* nsb: takes long long arg, returns unsigned char. */
10526 static const struct builtin_description bdesc[] =
10528 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
10529 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
10530 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
10531 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
10532 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
10533 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
10534 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
10535 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
10536 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
10537 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
10538 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
10539 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
10540 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
10541 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
10542 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
10543 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
10544 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
10545 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
10546 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 },
10547 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 },
10548 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 },
10549 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 },
10550 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 },
10551 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 },
10552 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 },
10553 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
10554 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
10555 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
10556 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
10557 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
10558 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
10559 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
10560 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
10561 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
10562 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
10563 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
10564 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
10565 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
10566 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
10567 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
10568 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
10569 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
10570 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
10571 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
10572 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
10573 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
10574 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
10575 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
10576 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
10577 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
10578 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
10579 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
10580 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
10581 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
10582 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
10583 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
10584 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
10585 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
10586 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
10587 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
10588 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
10589 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 },
10590 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 },
10591 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 },
10592 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
10593 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
10594 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
10595 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
10596 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
10597 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
10598 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
10599 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
10600 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
10601 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 },
10602 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 },
10603 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 },
10604 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 },
10605 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 },
10606 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 },
10607 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 },
10608 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 },
10609 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
10610 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
10611 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
10615 sh_media_init_builtins (void)
10617 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
10618 const struct builtin_description *d;
10620 memset (shared, 0, sizeof shared);
10621 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
10623 tree type, arg_type = 0;
10624 int signature = d->signature;
10627 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
10628 type = shared[signature];
10631 int has_result = signature_args[signature][0] != 0;
10633 if ((signature_args[signature][1] & 8)
10634 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
10635 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
10637 if (! TARGET_FPU_ANY
10638 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
10640 type = void_list_node;
10643 int arg = signature_args[signature][i];
10644 int opno = i - 1 + has_result;
10647 arg_type = ptr_type_node;
10649 arg_type = (*lang_hooks.types.type_for_mode)
10650 (insn_data[d->icode].operand[opno].mode,
10655 arg_type = void_type_node;
10658 type = tree_cons (NULL_TREE, arg_type, type);
10660 type = build_function_type (arg_type, type);
10661 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10662 shared[signature] = type;
10664 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10669 /* Implements target hook vector_mode_supported_p. */
10671 sh_vector_mode_supported_p (enum machine_mode mode)
10674 && ((mode == V2SFmode)
10675 || (mode == V4SFmode)
10676 || (mode == V16SFmode)))
10679 else if (TARGET_SHMEDIA
10680 && ((mode == V8QImode)
10681 || (mode == V2HImode)
10682 || (mode == V4HImode)
10683 || (mode == V2SImode)))
10689 /* Implements target hook dwarf_calling_convention. Return an enum
10690 of dwarf_calling_convention. */
10692 sh_dwarf_calling_convention (const_tree func)
10694 if (sh_attr_renesas_p (func))
10695 return DW_CC_GNU_renesas_sh;
10697 return DW_CC_normal;
10701 sh_init_builtins (void)
10703 if (TARGET_SHMEDIA)
10704 sh_media_init_builtins ();
10707 /* Expand an expression EXP that calls a built-in function,
10708 with result going to TARGET if that's convenient
10709 (and in mode MODE if that's convenient).
10710 SUBTARGET may be used as the target for computing one of EXP's operands.
10711 IGNORE is nonzero if the value is to be ignored. */
10714 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10715 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
10717 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10718 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10719 const struct builtin_description *d = &bdesc[fcode];
10720 enum insn_code icode = d->icode;
10721 int signature = d->signature;
10722 enum machine_mode tmode = VOIDmode;
10727 if (signature_args[signature][0])
10732 tmode = insn_data[icode].operand[0].mode;
10734 || GET_MODE (target) != tmode
10735 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10736 target = gen_reg_rtx (tmode);
10737 op[nop++] = target;
10742 for (i = 1; i <= 3; i++, nop++)
10745 enum machine_mode opmode, argmode;
10748 if (! signature_args[signature][i])
10750 arg = CALL_EXPR_ARG (exp, i - 1);
10751 if (arg == error_mark_node)
10753 if (signature_args[signature][i] & 8)
10756 optype = ptr_type_node;
10760 opmode = insn_data[icode].operand[nop].mode;
10761 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10763 argmode = TYPE_MODE (TREE_TYPE (arg));
10764 if (argmode != opmode)
10765 arg = build1 (NOP_EXPR, optype, arg);
10766 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
10767 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10768 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10774 pat = (*insn_data[d->icode].genfun) (op[0]);
10777 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10780 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10783 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10786 gcc_unreachable ();
10795 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
10797 rtx sel0 = const0_rtx;
10798 rtx sel1 = const1_rtx;
10799 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
10800 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
10802 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
10803 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
10807 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
10809 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
10811 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
10812 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
10815 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
10816 We can allow any mode in any general register. The special registers
10817 only allow SImode. Don't allow any mode in the PR.
10819 We cannot hold DCmode values in the XD registers because alter_reg
10820 handles subregs of them incorrectly. We could work around this by
10821 spacing the XD registers like the DR registers, but this would require
10822 additional memory in every compilation to hold larger register vectors.
10823 We could hold SFmode / SCmode values in XD registers, but that
10824 would require a tertiary reload when reloading from / to memory,
10825 and a secondary reload to reload from / to general regs; that
10826 seems to be a loosing proposition.
10828 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
10829 it won't be ferried through GP registers first. */
10832 sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
10834 if (SPECIAL_REGISTER_P (regno))
10835 return mode == SImode;
10837 if (regno == FPUL_REG)
10838 return (mode == SImode || mode == SFmode);
10840 if (FP_REGISTER_P (regno) && mode == SFmode)
10843 if (mode == V2SFmode)
10845 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
10846 || GENERAL_REGISTER_P (regno)))
10852 if (mode == V4SFmode)
10854 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
10855 || GENERAL_REGISTER_P (regno))
10861 if (mode == V16SFmode)
10863 if (TARGET_SHMEDIA)
10865 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
10871 return regno == FIRST_XD_REG;
10874 if (FP_REGISTER_P (regno))
10878 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
10879 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
10882 && (mode == DFmode || mode == DImode
10883 || mode == V2SFmode || mode == TImode)))
10884 && ((regno - FIRST_FP_REG) & 1) == 0)
10885 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
10886 && ((regno - FIRST_FP_REG) & 3) == 0))
10892 if (XD_REGISTER_P (regno))
10893 return mode == DFmode;
10895 if (TARGET_REGISTER_P (regno))
10896 return (mode == DImode || mode == SImode || mode == PDImode);
10898 if (regno == PR_REG)
10899 return mode == SImode;
10901 if (regno == FPSCR_REG)
10902 return mode == PSImode;
10904 /* FIXME. This works around PR target/37633 for -O0. */
10905 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
10907 unsigned int n = GET_MODE_SIZE (mode) / 8;
10909 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
10910 && regno <= FIRST_GENERAL_REG + 14)
10917 /* Return the class of registers for which a mode change from FROM to TO
10920 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
10921 enum reg_class rclass)
10923 /* We want to enable the use of SUBREGs as a means to
10924 VEC_SELECT a single element of a vector. */
10925 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
10926 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
10928 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10930 if (TARGET_LITTLE_ENDIAN)
10932 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
10933 return reg_classes_intersect_p (DF_REGS, rclass);
10937 if (GET_MODE_SIZE (from) < 8)
10938 return reg_classes_intersect_p (DF_HI_REGS, rclass);
10945 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10946 that label is used. */
10949 sh_mark_label (rtx address, int nuses)
10951 if (GOTOFF_P (address))
10953 /* Extract the label or symbol. */
10954 address = XEXP (address, 0);
10955 if (GET_CODE (address) == PLUS)
10956 address = XEXP (address, 0);
10957 address = XVECEXP (address, 0, 0);
10959 if (GET_CODE (address) == LABEL_REF
10960 && LABEL_P (XEXP (address, 0)))
10961 LABEL_NUSES (XEXP (address, 0)) += nuses;
10964 /* Compute extra cost of moving data between one register class
10967 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10968 uses this information. Hence, the general register <-> floating point
10969 register information here is not used for SFmode. */
10972 sh_register_move_cost (enum machine_mode mode,
10973 enum reg_class srcclass, enum reg_class dstclass)
10975 if (dstclass == T_REGS || dstclass == PR_REGS)
10978 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
10981 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
10982 && REGCLASS_HAS_FP_REG (srcclass)
10983 && REGCLASS_HAS_FP_REG (dstclass))
10986 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
10987 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
10989 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
10990 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
10993 if ((REGCLASS_HAS_FP_REG (dstclass)
10994 && REGCLASS_HAS_GENERAL_REG (srcclass))
10995 || (REGCLASS_HAS_GENERAL_REG (dstclass)
10996 && REGCLASS_HAS_FP_REG (srcclass)))
10997 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
10998 * ((GET_MODE_SIZE (mode) + 7) / 8U));
11000 if ((dstclass == FPUL_REGS
11001 && REGCLASS_HAS_GENERAL_REG (srcclass))
11002 || (srcclass == FPUL_REGS
11003 && REGCLASS_HAS_GENERAL_REG (dstclass)))
11006 if ((dstclass == FPUL_REGS
11007 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
11008 || (srcclass == FPUL_REGS
11009 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
11012 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11013 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11016 /* ??? ptabs faults on (value & 0x3) == 0x3 */
11018 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
11020 if (sh_gettrcost >= 0)
11021 return sh_gettrcost;
11022 else if (!TARGET_PT_FIXED)
11026 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11027 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11032 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
11033 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
11034 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
11036 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
11039 static rtx emit_load_ptr (rtx, rtx);
11042 emit_load_ptr (rtx reg, rtx addr)
11044 rtx mem = gen_const_mem (ptr_mode, addr);
11046 if (Pmode != ptr_mode)
11047 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
11048 return emit_move_insn (reg, mem);
11052 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11053 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11056 CUMULATIVE_ARGS cum;
11057 int structure_value_byref = 0;
11058 rtx this_rtx, this_value, sibcall, insns, funexp;
11059 tree funtype = TREE_TYPE (function);
11060 int simple_add = CONST_OK_FOR_ADD (delta);
11062 rtx scratch0, scratch1, scratch2;
11065 reload_completed = 1;
11066 epilogue_completed = 1;
11067 current_function_uses_only_leaf_regs = 1;
11069 emit_note (NOTE_INSN_PROLOGUE_END);
11071 /* Find the "this" pointer. We have such a wide range of ABIs for the
11072 SH that it's best to do this completely machine independently.
11073 "this" is passed as first argument, unless a structure return pointer
11074 comes first, in which case "this" comes second. */
11075 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
11076 #ifndef PCC_STATIC_STRUCT_RETURN
11077 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11078 structure_value_byref = 1;
11079 #endif /* not PCC_STATIC_STRUCT_RETURN */
11080 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
11082 tree ptype = build_pointer_type (TREE_TYPE (funtype));
11084 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
11086 this_rtx = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
11088 /* For SHcompact, we only have r0 for a scratch register: r1 is the
11089 static chain pointer (even if you can't have nested virtual functions
11090 right now, someone might implement them sometime), and the rest of the
11091 registers are used for argument passing, are callee-saved, or reserved. */
11092 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
11093 -ffixed-reg has been used. */
11094 if (! call_used_regs[0] || fixed_regs[0])
11095 error ("r0 needs to be available as a call-clobbered register");
11096 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
11099 if (call_used_regs[1] && ! fixed_regs[1])
11100 scratch1 = gen_rtx_REG (ptr_mode, 1);
11101 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
11102 pointing where to return struct values. */
11103 if (call_used_regs[3] && ! fixed_regs[3])
11104 scratch2 = gen_rtx_REG (Pmode, 3);
11106 else if (TARGET_SHMEDIA)
11108 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
11109 if (i != REGNO (scratch0) &&
11110 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
11112 scratch1 = gen_rtx_REG (ptr_mode, i);
11115 if (scratch1 == scratch0)
11116 error ("Need a second call-clobbered general purpose register");
11117 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
11118 if (call_used_regs[i] && ! fixed_regs[i])
11120 scratch2 = gen_rtx_REG (Pmode, i);
11123 if (scratch2 == scratch0)
11124 error ("Need a call-clobbered target register");
11127 this_value = plus_constant (this_rtx, delta);
11129 && (simple_add || scratch0 != scratch1)
11130 && strict_memory_address_p (ptr_mode, this_value))
11132 emit_load_ptr (scratch0, this_value);
11137 ; /* Do nothing. */
11138 else if (simple_add)
11139 emit_move_insn (this_rtx, this_value);
11142 emit_move_insn (scratch1, GEN_INT (delta));
11143 emit_insn (gen_add2_insn (this_rtx, scratch1));
11151 emit_load_ptr (scratch0, this_rtx);
11153 offset_addr = plus_constant (scratch0, vcall_offset);
11154 if (strict_memory_address_p (ptr_mode, offset_addr))
11155 ; /* Do nothing. */
11156 else if (! TARGET_SH5 && scratch0 != scratch1)
11158 /* scratch0 != scratch1, and we have indexed loads. Get better
11159 schedule by loading the offset into r1 and using an indexed
11160 load - then the load of r1 can issue before the load from
11161 (this_rtx + delta) finishes. */
11162 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11163 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
11165 else if (CONST_OK_FOR_ADD (vcall_offset))
11167 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
11168 offset_addr = scratch0;
11170 else if (scratch0 != scratch1)
11172 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11173 emit_insn (gen_add2_insn (scratch0, scratch1));
11174 offset_addr = scratch0;
11177 gcc_unreachable (); /* FIXME */
11178 emit_load_ptr (scratch0, offset_addr);
11180 if (Pmode != ptr_mode)
11181 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
11182 emit_insn (gen_add2_insn (this_rtx, scratch0));
11185 /* Generate a tail call to the target function. */
11186 if (! TREE_USED (function))
11188 assemble_external (function);
11189 TREE_USED (function) = 1;
11191 funexp = XEXP (DECL_RTL (function), 0);
11192 /* If the function is overridden, so is the thunk, hence we don't
11193 need GOT addressing even if this is a public symbol. */
11195 if (TARGET_SH1 && ! flag_weak)
11196 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
11199 if (TARGET_SH2 && flag_pic)
11201 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
11202 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
11206 if (TARGET_SHMEDIA && flag_pic)
11208 funexp = gen_sym2PIC (funexp);
11209 PUT_MODE (funexp, Pmode);
11211 emit_move_insn (scratch2, funexp);
11212 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
11213 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
11215 sibcall = emit_call_insn (sibcall);
11216 SIBLING_CALL_P (sibcall) = 1;
11217 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
11220 /* Run just enough of rest_of_compilation to do scheduling and get
11221 the insns emitted. Note that use_thunk calls
11222 assemble_start_function and assemble_end_function. */
11224 insn_locators_alloc ();
11225 insns = get_insns ();
11231 split_all_insns_noflow ();
11236 if (optimize > 0 && flag_delayed_branch)
11237 dbr_schedule (insns);
11239 shorten_branches (insns);
11240 final_start_function (insns, file, 1);
11241 final (insns, file, 1);
11242 final_end_function ();
11243 free_after_compilation (cfun);
11245 reload_completed = 0;
11246 epilogue_completed = 0;
11250 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
11254 /* If this is not an ordinary function, the name usually comes from a
11255 string literal or an sprintf buffer. Make sure we use the same
11256 string consistently, so that cse will be able to unify address loads. */
11257 if (kind != FUNCTION_ORDINARY)
11258 name = IDENTIFIER_POINTER (get_identifier (name));
11259 sym = gen_rtx_SYMBOL_REF (Pmode, name);
11260 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
11264 case FUNCTION_ORDINARY:
11268 rtx reg = target ? target : gen_reg_rtx (Pmode);
11270 emit_insn (gen_symGOT2reg (reg, sym));
11276 /* ??? To allow cse to work, we use GOTOFF relocations.
11277 we could add combiner patterns to transform this into
11278 straight pc-relative calls with sym2PIC / bsrf when
11279 label load and function call are still 1:1 and in the
11280 same basic block during combine. */
11281 rtx reg = target ? target : gen_reg_rtx (Pmode);
11283 emit_insn (gen_symGOTOFF2reg (reg, sym));
11288 if (target && sym != target)
11290 emit_move_insn (target, sym);
11296 /* Find the number of a general purpose register in S. */
11298 scavenge_reg (HARD_REG_SET *s)
11301 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11302 if (TEST_HARD_REG_BIT (*s, r))
11308 sh_get_pr_initial_val (void)
11312 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11313 PR register on SHcompact, because it might be clobbered by the prologue.
11314 We check first if that is known to be the case. */
11315 if (TARGET_SHCOMPACT
11316 && ((crtl->args.info.call_cookie
11317 & ~ CALL_COOKIE_RET_TRAMP (1))
11318 || crtl->saves_all_registers))
11319 return gen_frame_mem (SImode, return_address_pointer_rtx);
11321 /* If we haven't finished rtl generation, there might be a nonlocal label
11322 that we haven't seen yet.
11323 ??? get_hard_reg_initial_val fails if it is called after register
11324 allocation has started, unless it has been called before for the
11325 same register. And even then, we end in trouble if we didn't use
11326 the register in the same basic block before. So call
11327 get_hard_reg_initial_val now and wrap it in an unspec if we might
11328 need to replace it. */
11329 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11330 combine can put the pseudo returned by get_hard_reg_initial_val into
11331 instructions that need a general purpose registers, which will fail to
11332 be recognized when the pseudo becomes allocated to PR. */
11334 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
11336 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11341 sh_expand_t_scc (rtx operands[])
11343 enum rtx_code code = GET_CODE (operands[1]);
11344 rtx target = operands[0];
11345 rtx op0 = operands[2];
11346 rtx op1 = operands[3];
11347 rtx result = target;
11350 if (!REG_P (op0) || REGNO (op0) != T_REG
11351 || !CONST_INT_P (op1))
11353 if (!REG_P (result))
11354 result = gen_reg_rtx (SImode);
11355 val = INTVAL (op1);
11356 if ((code == EQ && val == 1) || (code == NE && val == 0))
11357 emit_insn (gen_movt (result));
11358 else if (TARGET_SH2A && ((code == EQ && val == 0)
11359 || (code == NE && val == 1)))
11360 emit_insn (gen_xorsi3_movrt (result));
11361 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11363 emit_clobber (result);
11364 emit_insn (gen_subc (result, result, result));
11365 emit_insn (gen_addsi3 (result, result, const1_rtx));
11367 else if (code == EQ || code == NE)
11368 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11371 if (result != target)
11372 emit_move_insn (target, result);
11376 /* INSN is an sfunc; return the rtx that describes the address used. */
11378 extract_sfunc_addr (rtx insn)
11380 rtx pattern, part = NULL_RTX;
11383 pattern = PATTERN (insn);
11384 len = XVECLEN (pattern, 0);
11385 for (i = 0; i < len; i++)
11387 part = XVECEXP (pattern, 0, i);
11388 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
11389 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
11390 return XEXP (part, 0);
11392 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
11393 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
11396 /* Verify that the register in use_sfunc_addr still agrees with the address
11397 used in the sfunc. This prevents fill_slots_from_thread from changing
11399 INSN is the use_sfunc_addr instruction, and REG is the register it
11402 check_use_sfunc_addr (rtx insn, rtx reg)
11404 /* Search for the sfunc. It should really come right after INSN. */
11405 while ((insn = NEXT_INSN (insn)))
11407 if (LABEL_P (insn) || JUMP_P (insn))
11409 if (! INSN_P (insn))
11412 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11413 insn = XVECEXP (PATTERN (insn), 0, 0);
11414 if (GET_CODE (PATTERN (insn)) != PARALLEL
11415 || get_attr_type (insn) != TYPE_SFUNC)
11417 return rtx_equal_p (extract_sfunc_addr (insn), reg);
11419 gcc_unreachable ();
11422 /* This function returns a constant rtx that represents pi / 2**15 in
11423 SFmode. it's used to scale SFmode angles, in radians, to a
11424 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11425 maps to 0x10000). */
11427 static GTY(()) rtx sh_fsca_sf2int_rtx;
11430 sh_fsca_sf2int (void)
11432 if (! sh_fsca_sf2int_rtx)
11434 REAL_VALUE_TYPE rv;
11436 real_from_string (&rv, "10430.378350470453");
11437 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
11440 return sh_fsca_sf2int_rtx;
11443 /* This function returns a constant rtx that represents pi / 2**15 in
11444 DFmode. it's used to scale DFmode angles, in radians, to a
11445 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11446 maps to 0x10000). */
11448 static GTY(()) rtx sh_fsca_df2int_rtx;
11451 sh_fsca_df2int (void)
11453 if (! sh_fsca_df2int_rtx)
11455 REAL_VALUE_TYPE rv;
11457 real_from_string (&rv, "10430.378350470453");
11458 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
11461 return sh_fsca_df2int_rtx;
11464 /* This function returns a constant rtx that represents 2**15 / pi in
11465 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
11466 of a full circle back to a SFmode value, i.e., 0x10000 maps to
11469 static GTY(()) rtx sh_fsca_int2sf_rtx;
11472 sh_fsca_int2sf (void)
11474 if (! sh_fsca_int2sf_rtx)
11476 REAL_VALUE_TYPE rv;
11478 real_from_string (&rv, "9.587379924285257e-5");
11479 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
11482 return sh_fsca_int2sf_rtx;
11485 /* Initialize the CUMULATIVE_ARGS structure. */
11488 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
11490 rtx libname ATTRIBUTE_UNUSED,
11492 signed int n_named_args,
11493 enum machine_mode mode)
11495 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
11496 pcum->free_single_fp_reg = 0;
11497 pcum->stack_regs = 0;
11498 pcum->byref_regs = 0;
11500 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
11502 /* XXX - Should we check TARGET_HITACHI here ??? */
11503 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
11507 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
11508 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
11509 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
11510 pcum->arg_count [(int) SH_ARG_INT]
11511 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
11514 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11515 && pcum->arg_count [(int) SH_ARG_INT] == 0
11516 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
11517 ? int_size_in_bytes (TREE_TYPE (fntype))
11518 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
11519 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
11520 == FIRST_RET_REG));
11524 pcum->arg_count [(int) SH_ARG_INT] = 0;
11525 pcum->prototype_p = FALSE;
11526 if (mode != VOIDmode)
11528 pcum->call_cookie =
11529 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11530 && GET_MODE_SIZE (mode) > 4
11531 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
11533 /* If the default ABI is the Renesas ABI then all library
11534 calls must assume that the library will be using the
11535 Renesas ABI. So if the function would return its result
11536 in memory then we must force the address of this memory
11537 block onto the stack. Ideally we would like to call
11538 targetm.calls.return_in_memory() here but we do not have
11539 the TYPE or the FNDECL available so we synthesize the
11540 contents of that function as best we can. */
11542 (TARGET_DEFAULT & MASK_HITACHI)
11543 && (mode == BLKmode
11544 || (GET_MODE_SIZE (mode) > 4
11545 && !(mode == DFmode
11546 && TARGET_FPU_DOUBLE)));
11550 pcum->call_cookie = 0;
11551 pcum->force_mem = FALSE;
11556 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
11557 not enter into CONST_DOUBLE for the replace.
11559 Note that copying is not done so X must not be shared unless all copies
11560 are to be modified.
11562 This is like replace_rtx, except that we operate on N_REPLACEMENTS
11563 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
11564 replacements[n*2+1] - and that we take mode changes into account.
11566 If a replacement is ambiguous, return NULL_RTX.
11568 If MODIFY is zero, don't modify any rtl in place,
11569 just return zero or nonzero for failure / success. */
11572 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
11577 /* The following prevents loops occurrence when we change MEM in
11578 CONST_DOUBLE onto the same CONST_DOUBLE. */
11579 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
11582 for (i = n_replacements - 1; i >= 0 ; i--)
11583 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
11584 return replacements[i*2+1];
11586 /* Allow this function to make replacements in EXPR_LISTs. */
11590 if (GET_CODE (x) == SUBREG)
11592 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
11593 n_replacements, modify);
11595 if (CONST_INT_P (new_rtx))
11597 x = simplify_subreg (GET_MODE (x), new_rtx,
11598 GET_MODE (SUBREG_REG (x)),
11604 SUBREG_REG (x) = new_rtx;
11608 else if (REG_P (x))
11610 unsigned regno = REGNO (x);
11611 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
11612 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11613 rtx result = NULL_RTX;
11615 for (i = n_replacements - 1; i >= 0; i--)
11617 rtx from = replacements[i*2];
11618 rtx to = replacements[i*2+1];
11619 unsigned from_regno, from_nregs, to_regno, new_regno;
11623 from_regno = REGNO (from);
11624 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
11625 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
11626 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
11628 if (regno < from_regno
11629 || regno + nregs > from_regno + nregs
11633 to_regno = REGNO (to);
11634 if (to_regno < FIRST_PSEUDO_REGISTER)
11636 new_regno = regno + to_regno - from_regno;
11637 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
11640 result = gen_rtx_REG (GET_MODE (x), new_regno);
11642 else if (GET_MODE (x) <= GET_MODE (to))
11643 result = gen_lowpart_common (GET_MODE (x), to);
11645 result = gen_lowpart_SUBREG (GET_MODE (x), to);
11648 return result ? result : x;
11650 else if (GET_CODE (x) == ZERO_EXTEND)
11652 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
11653 n_replacements, modify);
11655 if (CONST_INT_P (new_rtx))
11657 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
11658 new_rtx, GET_MODE (XEXP (x, 0)));
11663 XEXP (x, 0) = new_rtx;
11668 fmt = GET_RTX_FORMAT (GET_CODE (x));
11669 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
11675 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
11676 n_replacements, modify);
11680 XEXP (x, i) = new_rtx;
11682 else if (fmt[i] == 'E')
11683 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11685 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
11686 n_replacements, modify);
11690 XVECEXP (x, i, j) = new_rtx;
11698 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
11700 enum rtx_code code = TRUNCATE;
11702 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
11704 rtx inner = XEXP (x, 0);
11705 enum machine_mode inner_mode = GET_MODE (inner);
11707 if (inner_mode == mode)
11709 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
11711 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
11712 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
11714 code = GET_CODE (x);
11718 return gen_rtx_fmt_e (code, mode, x);
11721 /* called via for_each_rtx after reload, to clean up truncates of
11722 registers that span multiple actual hard registers. */
11724 shmedia_cleanup_truncate (rtx *p, void *n_changes)
11728 if (GET_CODE (x) != TRUNCATE)
11731 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && REG_P (reg))
11733 enum machine_mode reg_mode = GET_MODE (reg);
11734 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
11735 subreg_lowpart_offset (DImode, reg_mode));
11736 *(int*) n_changes += 1;
11742 /* Load and store depend on the highpart of the address. However,
11743 set_attr_alternative does not give well-defined results before reload,
11744 so we must look at the rtl ourselves to see if any of the feeding
11745 registers is used in a memref. */
11747 /* Called by sh_contains_memref_p via for_each_rtx. */
11749 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
11751 return (MEM_P (*loc));
11754 /* Return nonzero iff INSN contains a MEM. */
11756 sh_contains_memref_p (rtx insn)
11758 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
11761 /* Return nonzero iff INSN loads a banked register. */
11763 sh_loads_bankedreg_p (rtx insn)
11765 if (GET_CODE (PATTERN (insn)) == SET)
11767 rtx op = SET_DEST (PATTERN(insn));
11768 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11775 /* FNADDR is the MEM expression from a call expander. Return an address
11776 to use in an SHmedia insn pattern. */
11778 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
11782 fnaddr = XEXP (fnaddr, 0);
11783 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
11784 if (flag_pic && is_sym)
11786 if (! SYMBOL_REF_LOCAL_P (fnaddr))
11788 rtx reg = gen_reg_rtx (Pmode);
11790 /* We must not use GOTPLT for sibcalls, because PIC_REG
11791 must be restored before the PLT code gets to run. */
11793 emit_insn (gen_symGOT2reg (reg, fnaddr));
11795 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
11800 fnaddr = gen_sym2PIC (fnaddr);
11801 PUT_MODE (fnaddr, Pmode);
11804 /* If ptabs might trap, make this visible to the rest of the compiler.
11805 We generally assume that symbols pertain to valid locations, but
11806 it is possible to generate invalid symbols with asm or linker tricks.
11807 In a list of functions where each returns its successor, an invalid
11808 symbol might denote an empty list. */
11809 if (!TARGET_PT_FIXED
11810 && (!is_sym || TARGET_INVALID_SYMBOLS)
11811 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
11813 rtx tr = gen_reg_rtx (PDImode);
11815 emit_insn (gen_ptabs (tr, fnaddr));
11818 else if (! target_reg_operand (fnaddr, Pmode))
11819 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
11824 sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
11825 enum machine_mode mode, secondary_reload_info *sri)
11829 if (REGCLASS_HAS_FP_REG (rclass)
11830 && ! TARGET_SHMEDIA
11831 && immediate_operand ((x), mode)
11832 && ! ((fp_zero_operand (x) || fp_one_operand (x))
11833 && mode == SFmode && fldi_ok ()))
11837 sri->icode = CODE_FOR_reload_insf__frn;
11840 sri->icode = CODE_FOR_reload_indf__frn;
11843 /* ??? If we knew that we are in the appropriate mode -
11844 single precision - we could use a reload pattern directly. */
11849 if (rclass == FPUL_REGS
11851 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11852 || REGNO (x) == T_REG))
11853 || GET_CODE (x) == PLUS))
11854 return GENERAL_REGS;
11855 if (rclass == FPUL_REGS && immediate_operand (x, mode))
11857 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
11858 return GENERAL_REGS;
11859 else if (mode == SFmode)
11861 sri->icode = CODE_FOR_reload_insi__i_fpul;
11864 if (rclass == FPSCR_REGS
11865 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11866 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
11867 return GENERAL_REGS;
11868 if (REGCLASS_HAS_FP_REG (rclass)
11870 && immediate_operand (x, mode)
11871 && x != CONST0_RTX (GET_MODE (x))
11872 && GET_MODE (x) != V4SFmode)
11873 return GENERAL_REGS;
11874 if ((mode == QImode || mode == HImode)
11875 && TARGET_SHMEDIA && inqhi_operand (x, mode))
11877 sri->icode = ((mode == QImode)
11878 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
11881 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
11882 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
11883 return TARGET_REGS;
11884 } /* end of input-only processing. */
11886 if (((REGCLASS_HAS_FP_REG (rclass)
11888 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11889 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11890 && TARGET_FMOVD))))
11891 || (REGCLASS_HAS_GENERAL_REG (rclass)
11893 && FP_REGISTER_P (REGNO (x))))
11894 && ! TARGET_SHMEDIA
11895 && (mode == SFmode || mode == SImode))
11897 if ((rclass == FPUL_REGS
11898 || (REGCLASS_HAS_FP_REG (rclass)
11899 && ! TARGET_SHMEDIA && mode == SImode))
11902 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11903 || REGNO (x) == T_REG
11904 || system_reg_operand (x, VOIDmode)))))
11906 if (rclass == FPUL_REGS)
11907 return GENERAL_REGS;
11910 if ((rclass == TARGET_REGS
11911 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
11912 && !satisfies_constraint_Csy (x)
11913 && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
11914 return GENERAL_REGS;
11915 if ((rclass == MAC_REGS || rclass == PR_REGS)
11916 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
11917 && rclass != REGNO_REG_CLASS (REGNO (x)))
11918 return GENERAL_REGS;
11919 if (rclass != GENERAL_REGS && REG_P (x)
11920 && TARGET_REGISTER_P (REGNO (x)))
11921 return GENERAL_REGS;
11925 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;