1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "insn-config.h"
35 #include "hard-reg-set.h"
37 #include "insn-attr.h"
41 #include "integrate.h"
45 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
52 #include "sched-int.h"
56 #include "alloc-pool.h"
57 #include "tm-constrs.h"
60 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
62 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
63 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
65 /* These are some macros to abstract register modes. */
66 #define CONST_OK_FOR_ADD(size) \
67 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
68 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
69 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
70 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
72 /* Used to simplify the logic below. Find the attributes wherever
74 #define SH_ATTRIBUTES(decl) \
75 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
76 : DECL_ATTRIBUTES (decl) \
77 ? (DECL_ATTRIBUTES (decl)) \
78 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
80 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
81 int current_function_interrupt;
83 tree sh_deferred_function_attributes;
84 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
86 /* Global variables for machine-dependent things. */
88 /* Which cpu are we scheduling for. */
89 enum processor_type sh_cpu;
91 /* Definitions used in ready queue reordering for first scheduling pass. */
93 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
94 static short *regmode_weight[2];
96 /* Total SFmode and SImode weights of scheduled insns. */
97 static int curr_regmode_pressure[2];
99 /* Number of r0 life regions. */
100 static int r0_life_regions;
102 /* If true, skip cycles for Q -> R movement. */
103 static int skip_cycles = 0;
105 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
106 and returned from sh_reorder2. */
107 static short cached_can_issue_more;
109 /* Saved operands from the last compare to use when we generate an scc
115 /* Provides the class number of the smallest class containing
118 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
120 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
131 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
132 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
133 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
135 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
136 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
147 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
148 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
149 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
152 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
153 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
154 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
155 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
156 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
157 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
158 GENERAL_REGS, GENERAL_REGS,
161 char sh_register_names[FIRST_PSEUDO_REGISTER] \
162 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
164 char sh_additional_register_names[ADDREGNAMES_SIZE] \
165 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
166 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
168 int assembler_dialect;
170 static bool shmedia_space_reserved_for_target_registers;
172 static bool sh_handle_option (size_t, const char *, int);
173 static void split_branches (rtx);
174 static int branch_dest (rtx);
175 static void force_into (rtx, rtx);
176 static void print_slot (rtx);
177 static rtx add_constant (rtx, enum machine_mode, rtx);
178 static void dump_table (rtx, rtx);
179 static int hi_const (rtx);
180 static int broken_move (rtx);
181 static int mova_p (rtx);
182 static rtx find_barrier (int, rtx, rtx);
183 static int noncall_uses_reg (rtx, rtx, rtx *);
184 static rtx gen_block_redirect (rtx, int, int);
185 static void sh_reorg (void);
186 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
187 static rtx frame_insn (rtx);
188 static rtx push (int);
189 static void pop (int);
190 static void push_regs (HARD_REG_SET *, int);
191 static int calc_live_regs (HARD_REG_SET *);
192 static HOST_WIDE_INT rounded_frame_size (int);
193 static rtx mark_constant_pool_use (rtx);
194 const struct attribute_spec sh_attribute_table[];
195 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
196 static tree sh_handle_resbank_handler_attribute (tree *, tree,
198 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
200 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
201 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
202 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
203 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
204 static void sh_insert_attributes (tree, tree *);
205 static const char *sh_check_pch_target_flags (int);
206 static int sh_adjust_cost (rtx, rtx, rtx, int);
207 static int sh_issue_rate (void);
208 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
209 static short find_set_regmode_weight (rtx, enum machine_mode);
210 static short find_insn_regmode_weight (rtx, enum machine_mode);
211 static void find_regmode_weight (basic_block, enum machine_mode);
212 static int find_r0_life_regions (basic_block);
213 static void sh_md_init_global (FILE *, int, int);
214 static void sh_md_finish_global (FILE *, int);
215 static int rank_for_reorder (const void *, const void *);
216 static void swap_reorder (rtx *, int);
217 static void ready_reorder (rtx *, int);
218 static short high_pressure (enum machine_mode);
219 static int sh_reorder (FILE *, int, rtx *, int *, int);
220 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
221 static void sh_md_init (FILE *, int, int);
222 static int sh_variable_issue (FILE *, int, rtx, int);
224 static bool sh_function_ok_for_sibcall (tree, tree);
226 static bool sh_cannot_modify_jumps_p (void);
227 static int sh_target_reg_class (void);
228 static bool sh_optimize_target_register_callee_saved (bool);
229 static bool sh_ms_bitfield_layout_p (const_tree);
231 static void sh_init_builtins (void);
232 static void sh_media_init_builtins (void);
233 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
234 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
235 static void sh_file_start (void);
236 static int flow_dependent_p (rtx, rtx);
237 static void flow_dependent_p_1 (rtx, const_rtx, void *);
238 static int shiftcosts (rtx);
239 static int andcosts (rtx);
240 static int addsubcosts (rtx);
241 static int multcosts (rtx);
242 static bool unspec_caller_rtx_p (rtx);
243 static bool sh_cannot_copy_insn_p (rtx);
244 static bool sh_rtx_costs (rtx, int, int, int *, bool);
245 static int sh_address_cost (rtx, bool);
246 static int sh_pr_n_sets (void);
247 static rtx sh_allocate_initial_value (rtx);
248 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
249 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
250 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
251 static int scavenge_reg (HARD_REG_SET *s);
252 struct save_schedule_s;
253 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
254 struct save_schedule_s *, int);
256 static rtx sh_struct_value_rtx (tree, int);
257 static bool sh_return_in_memory (const_tree, const_tree);
258 static rtx sh_builtin_saveregs (void);
259 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
260 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
261 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
262 static tree sh_build_builtin_va_list (void);
263 static void sh_va_start (tree, rtx);
264 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
265 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
267 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
269 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
271 static bool sh_scalar_mode_supported_p (enum machine_mode);
272 static int sh_dwarf_calling_convention (const_tree);
273 static void sh_encode_section_info (tree, rtx, int);
274 static int sh2a_function_vector_p (tree);
277 /* Initialize the GCC target structure. */
278 #undef TARGET_ATTRIBUTE_TABLE
279 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
281 /* The next two are used for debug info when compiling with -gdwarf. */
282 #undef TARGET_ASM_UNALIGNED_HI_OP
283 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
284 #undef TARGET_ASM_UNALIGNED_SI_OP
285 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
287 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
288 #undef TARGET_ASM_UNALIGNED_DI_OP
289 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
290 #undef TARGET_ASM_ALIGNED_DI_OP
291 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
293 #undef TARGET_ASM_FUNCTION_EPILOGUE
294 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
296 #undef TARGET_ASM_OUTPUT_MI_THUNK
297 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
299 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
300 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
302 #undef TARGET_ASM_FILE_START
303 #define TARGET_ASM_FILE_START sh_file_start
304 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
305 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
307 #undef TARGET_DEFAULT_TARGET_FLAGS
308 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
309 #undef TARGET_HANDLE_OPTION
310 #define TARGET_HANDLE_OPTION sh_handle_option
312 #undef TARGET_INSERT_ATTRIBUTES
313 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
315 #undef TARGET_SCHED_ADJUST_COST
316 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
318 #undef TARGET_SCHED_ISSUE_RATE
319 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
321 /* The next 5 hooks have been implemented for reenabling sched1. With the
322 help of these macros we are limiting the movement of insns in sched1 to
323 reduce the register pressure. The overall idea is to keep count of SImode
324 and SFmode regs required by already scheduled insns. When these counts
325 cross some threshold values; give priority to insns that free registers.
326 The insn that frees registers is most likely to be the insn with lowest
327 LUID (original insn order); but such an insn might be there in the stalled
328 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
329 upto a max of 8 cycles so that such insns may move from Q -> R.
331 The description of the hooks are as below:
333 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
334 scheduler; it is called inside the sched_init function just after
335 find_insn_reg_weights function call. It is used to calculate the SImode
336 and SFmode weights of insns of basic blocks; much similar to what
337 find_insn_reg_weights does.
338 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
340 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
341 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
344 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
345 high; reorder the ready queue so that the insn with lowest LUID will be
348 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
349 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
351 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
352 can be returned from TARGET_SCHED_REORDER2.
354 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
356 #undef TARGET_SCHED_DFA_NEW_CYCLE
357 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
359 #undef TARGET_SCHED_INIT_GLOBAL
360 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
362 #undef TARGET_SCHED_FINISH_GLOBAL
363 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
365 #undef TARGET_SCHED_VARIABLE_ISSUE
366 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
368 #undef TARGET_SCHED_REORDER
369 #define TARGET_SCHED_REORDER sh_reorder
371 #undef TARGET_SCHED_REORDER2
372 #define TARGET_SCHED_REORDER2 sh_reorder2
374 #undef TARGET_SCHED_INIT
375 #define TARGET_SCHED_INIT sh_md_init
377 #undef TARGET_CANNOT_MODIFY_JUMPS_P
378 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
379 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
380 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
381 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
382 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
383 sh_optimize_target_register_callee_saved
385 #undef TARGET_MS_BITFIELD_LAYOUT_P
386 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
388 #undef TARGET_INIT_BUILTINS
389 #define TARGET_INIT_BUILTINS sh_init_builtins
390 #undef TARGET_EXPAND_BUILTIN
391 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
393 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
394 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
396 #undef TARGET_CANNOT_COPY_INSN_P
397 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
398 #undef TARGET_RTX_COSTS
399 #define TARGET_RTX_COSTS sh_rtx_costs
400 #undef TARGET_ADDRESS_COST
401 #define TARGET_ADDRESS_COST sh_address_cost
402 #undef TARGET_ALLOCATE_INITIAL_VALUE
403 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
405 #undef TARGET_MACHINE_DEPENDENT_REORG
406 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
408 #undef TARGET_DWARF_REGISTER_SPAN
409 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
412 #undef TARGET_HAVE_TLS
413 #define TARGET_HAVE_TLS true
416 #undef TARGET_PROMOTE_PROTOTYPES
417 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
418 #undef TARGET_PROMOTE_FUNCTION_ARGS
419 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
420 #undef TARGET_PROMOTE_FUNCTION_RETURN
421 #define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
423 #undef TARGET_STRUCT_VALUE_RTX
424 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
425 #undef TARGET_RETURN_IN_MEMORY
426 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
428 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
429 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
430 #undef TARGET_SETUP_INCOMING_VARARGS
431 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
432 #undef TARGET_STRICT_ARGUMENT_NAMING
433 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
434 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
435 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
436 #undef TARGET_MUST_PASS_IN_STACK
437 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
438 #undef TARGET_PASS_BY_REFERENCE
439 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
440 #undef TARGET_CALLEE_COPIES
441 #define TARGET_CALLEE_COPIES sh_callee_copies
442 #undef TARGET_ARG_PARTIAL_BYTES
443 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
445 #undef TARGET_BUILD_BUILTIN_VA_LIST
446 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
447 #undef TARGET_EXPAND_BUILTIN_VA_START
448 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
449 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
450 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
452 #undef TARGET_SCALAR_MODE_SUPPORTED_P
453 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
454 #undef TARGET_VECTOR_MODE_SUPPORTED_P
455 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
457 #undef TARGET_CHECK_PCH_TARGET_FLAGS
458 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
460 #undef TARGET_DWARF_CALLING_CONVENTION
461 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
463 /* Return regmode weight for insn. */
464 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
466 /* Return current register pressure for regmode. */
467 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
469 #undef TARGET_ENCODE_SECTION_INFO
470 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
474 #undef TARGET_ENCODE_SECTION_INFO
475 #define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
476 #undef TARGET_STRIP_NAME_ENCODING
477 #define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
478 #undef TARGET_CXX_IMPORT_EXPORT_CLASS
479 #define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
483 #undef TARGET_SECONDARY_RELOAD
484 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
486 /* Machine-specific symbol_ref flags. */
487 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
489 struct gcc_target targetm = TARGET_INITIALIZER;
491 /* Implement TARGET_HANDLE_OPTION. */
494 sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
495 int value ATTRIBUTE_UNUSED)
500 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
504 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
508 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
512 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
516 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
519 case OPT_m2a_single_only:
520 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
524 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
528 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
532 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
539 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
543 case OPT_m4_100_nofpu:
544 case OPT_m4_200_nofpu:
545 case OPT_m4_300_nofpu:
549 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
553 case OPT_m4_100_single:
554 case OPT_m4_200_single:
555 case OPT_m4_300_single:
556 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
559 case OPT_m4_single_only:
560 case OPT_m4_100_single_only:
561 case OPT_m4_200_single_only:
562 case OPT_m4_300_single_only:
563 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
567 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
572 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
576 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
579 case OPT_m4a_single_only:
580 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
584 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
587 case OPT_m5_32media_nofpu:
588 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
592 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
595 case OPT_m5_64media_nofpu:
596 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
600 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
603 case OPT_m5_compact_nofpu:
604 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
612 /* Print the operand address in x to the stream. */
615 print_operand_address (FILE *stream, rtx x)
617 switch (GET_CODE (x))
621 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
626 rtx base = XEXP (x, 0);
627 rtx index = XEXP (x, 1);
629 switch (GET_CODE (index))
632 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
633 reg_names[true_regnum (base)]);
639 int base_num = true_regnum (base);
640 int index_num = true_regnum (index);
642 fprintf (stream, "@(r0,%s)",
643 reg_names[MAX (base_num, index_num)]);
654 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
658 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
662 x = mark_constant_pool_use (x);
663 output_addr_const (stream, x);
668 /* Print operand x (an rtx) in assembler syntax to file stream
669 according to modifier code.
671 '.' print a .s if insn needs delay slot
672 ',' print LOCAL_LABEL_PREFIX
673 '@' print trap, rte or rts depending upon pragma interruptness
674 '#' output a nop if there is nothing to put in the delay slot
675 ''' print likelihood suffix (/u for unlikely).
676 '>' print branch target if -fverbose-asm
677 'O' print a constant without the #
678 'R' print the LSW of a dp value - changes if in little endian
679 'S' print the MSW of a dp value - changes if in little endian
680 'T' print the next word of a dp value - same as 'R' in big endian mode.
681 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
682 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
683 'N' print 'r63' if the operand is (const_int 0).
684 'd' print a V2SF reg as dN instead of fpN.
685 'm' print a pair `base,offset' or `base,index', for LD and ST.
686 'U' Likewise for {LD,ST}{HI,LO}.
687 'V' print the position of a single bit set.
688 'W' print the position of a single bit cleared.
689 't' print a memory address which is a register.
690 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
691 'o' output an operator. */
694 print_operand (FILE *stream, rtx x, int code)
697 enum machine_mode mode;
705 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
706 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
707 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
710 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
713 trapa_attr = lookup_attribute ("trap_exit",
714 DECL_ATTRIBUTES (current_function_decl));
716 fprintf (stream, "trapa #%ld",
717 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
718 else if (sh_cfun_interrupt_handler_p ())
720 if (sh_cfun_resbank_handler_p ())
721 fprintf (stream, "resbank\n");
722 fprintf (stream, "rte");
725 fprintf (stream, "rts");
728 /* Output a nop if there's nothing in the delay slot. */
729 if (dbr_sequence_length () == 0)
730 fprintf (stream, "\n\tnop");
734 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
736 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
737 fputs ("/u", stream);
741 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
743 fputs ("\t! target: ", stream);
744 output_addr_const (stream, JUMP_LABEL (current_output_insn));
748 x = mark_constant_pool_use (x);
749 output_addr_const (stream, x);
751 /* N.B.: %R / %S / %T adjust memory addresses by four.
752 For SHMEDIA, that means they can be used to access the first and
753 second 32 bit part of a 64 bit (or larger) value that
754 might be held in floating point registers or memory.
755 While they can be used to access 64 bit parts of a larger value
756 held in general purpose registers, that won't work with memory -
757 neither for fp registers, since the frxx names are used. */
759 if (REG_P (x) || GET_CODE (x) == SUBREG)
761 regno = true_regnum (x);
762 regno += FP_REGISTER_P (regno) ? 1 : LSW;
763 fputs (reg_names[regno], (stream));
767 x = adjust_address (x, SImode, 4 * LSW);
768 print_operand_address (stream, XEXP (x, 0));
775 if (mode == VOIDmode)
777 if (GET_MODE_SIZE (mode) >= 8)
778 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
780 print_operand (stream, sub, 0);
782 output_operand_lossage ("invalid operand to %%R");
786 if (REG_P (x) || GET_CODE (x) == SUBREG)
788 regno = true_regnum (x);
789 regno += FP_REGISTER_P (regno) ? 0 : MSW;
790 fputs (reg_names[regno], (stream));
794 x = adjust_address (x, SImode, 4 * MSW);
795 print_operand_address (stream, XEXP (x, 0));
802 if (mode == VOIDmode)
804 if (GET_MODE_SIZE (mode) >= 8)
805 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
807 print_operand (stream, sub, 0);
809 output_operand_lossage ("invalid operand to %%S");
813 /* Next word of a double. */
814 switch (GET_CODE (x))
817 fputs (reg_names[REGNO (x) + 1], (stream));
820 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
821 && GET_CODE (XEXP (x, 0)) != POST_INC)
822 x = adjust_address (x, SImode, 4);
823 print_operand_address (stream, XEXP (x, 0));
831 gcc_assert (GET_CODE (x) == MEM);
833 switch (GET_CODE (x))
837 print_operand (stream, x, 0);
845 switch (GET_CODE (x))
847 case PLUS: fputs ("add", stream); break;
848 case MINUS: fputs ("sub", stream); break;
849 case MULT: fputs ("mul", stream); break;
850 case DIV: fputs ("div", stream); break;
851 case EQ: fputs ("eq", stream); break;
852 case NE: fputs ("ne", stream); break;
853 case GT: case LT: fputs ("gt", stream); break;
854 case GE: case LE: fputs ("ge", stream); break;
855 case GTU: case LTU: fputs ("gtu", stream); break;
856 case GEU: case LEU: fputs ("geu", stream); break;
864 if (GET_CODE (x) == MEM
865 && GET_CODE (XEXP (x, 0)) == PLUS
866 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
867 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
872 if (GET_CODE (x) == MEM)
874 switch (GET_MODE (x))
876 case QImode: fputs (".b", stream); break;
877 case HImode: fputs (".w", stream); break;
878 case SImode: fputs (".l", stream); break;
879 case SFmode: fputs (".s", stream); break;
880 case DFmode: fputs (".d", stream); break;
881 default: gcc_unreachable ();
888 gcc_assert (GET_CODE (x) == MEM);
892 switch (GET_CODE (x))
896 print_operand (stream, x, 0);
897 fputs (", 0", stream);
901 print_operand (stream, XEXP (x, 0), 0);
902 fputs (", ", stream);
903 print_operand (stream, XEXP (x, 1), 0);
913 int num = exact_log2 (INTVAL (x));
914 gcc_assert (num >= 0);
915 fprintf (stream, "#%d", num);
921 int num = exact_log2 (~INTVAL (x));
922 gcc_assert (num >= 0);
923 fprintf (stream, "#%d", num);
928 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == V2SFmode);
930 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
934 if (x == CONST0_RTX (GET_MODE (x)))
936 fprintf ((stream), "r63");
941 if (GET_CODE (x) == CONST_INT)
943 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
953 switch (GET_CODE (x))
957 rtx inner = XEXP (x, 0);
959 enum machine_mode inner_mode;
961 /* We might see SUBREGs with vector mode registers inside. */
962 if (GET_CODE (inner) == SUBREG
963 && (GET_MODE_SIZE (GET_MODE (inner))
964 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
965 && subreg_lowpart_p (inner))
966 inner = SUBREG_REG (inner);
967 if (GET_CODE (inner) == CONST_INT)
969 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
972 inner_mode = GET_MODE (inner);
973 if (GET_CODE (inner) == SUBREG
974 && (GET_MODE_SIZE (GET_MODE (inner))
975 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
976 && GET_CODE (SUBREG_REG (inner)) == REG)
978 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
979 GET_MODE (SUBREG_REG (inner)),
982 inner = SUBREG_REG (inner);
984 if (GET_CODE (inner) != REG || GET_MODE_SIZE (inner_mode) > 8)
986 /* Floating point register pairs are always big endian;
987 general purpose registers are 64 bit wide. */
988 regno = REGNO (inner);
989 regno = (HARD_REGNO_NREGS (regno, inner_mode)
990 - HARD_REGNO_NREGS (regno, mode))
998 /* FIXME: We need this on SHmedia32 because reload generates
999 some sign-extended HI or QI loads into DImode registers
1000 but, because Pmode is SImode, the address ends up with a
1001 subreg:SI of the DImode register. Maybe reload should be
1002 fixed so as to apply alter_subreg to such loads? */
1004 gcc_assert (trapping_target_operand (x, VOIDmode));
1005 x = XEXP (XEXP (x, 2), 0);
1006 goto default_output;
1008 gcc_assert (SUBREG_BYTE (x) == 0
1009 && GET_CODE (SUBREG_REG (x)) == REG);
1017 if (FP_REGISTER_P (regno)
1018 && mode == V16SFmode)
1019 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1020 else if (FP_REGISTER_P (REGNO (x))
1021 && mode == V4SFmode)
1022 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1023 else if (GET_CODE (x) == REG
1024 && mode == V2SFmode)
1025 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1026 else if (FP_REGISTER_P (REGNO (x))
1027 && GET_MODE_SIZE (mode) > 4)
1028 fprintf ((stream), "d%s", reg_names[regno] + 1);
1030 fputs (reg_names[regno], (stream));
1034 output_address (XEXP (x, 0));
1039 fputc ('#', stream);
1040 output_addr_const (stream, x);
1048 /* Encode symbol attributes of a SYMBOL_REF into its
1049 SYMBOL_REF_FLAGS. */
1051 sh_encode_section_info (tree decl, rtx rtl, int first)
1053 default_encode_section_info (decl, rtl, first);
1055 if (TREE_CODE (decl) == FUNCTION_DECL
1056 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1057 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1060 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1062 force_into (rtx value, rtx target)
1064 value = force_operand (value, target);
1065 if (! rtx_equal_p (value, target))
1066 emit_insn (gen_move_insn (target, value));
1069 /* Emit code to perform a block move. Choose the best method.
1071 OPERANDS[0] is the destination.
1072 OPERANDS[1] is the source.
1073 OPERANDS[2] is the size.
1074 OPERANDS[3] is the alignment safe to use. */
1077 expand_block_move (rtx *operands)
1079 int align = INTVAL (operands[3]);
1080 int constp = (GET_CODE (operands[2]) == CONST_INT);
1081 int bytes = (constp ? INTVAL (operands[2]) : 0);
1086 /* If we could use mov.l to move words and dest is word-aligned, we
1087 can use movua.l for loads and still generate a relatively short
1088 and efficient sequence. */
1089 if (TARGET_SH4A_ARCH && align < 4
1090 && MEM_ALIGN (operands[0]) >= 32
1091 && can_move_by_pieces (bytes, 32))
1093 rtx dest = copy_rtx (operands[0]);
1094 rtx src = copy_rtx (operands[1]);
1095 /* We could use different pseudos for each copied word, but
1096 since movua can only load into r0, it's kind of
1098 rtx temp = gen_reg_rtx (SImode);
1099 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1102 while (copied + 4 <= bytes)
1104 rtx to = adjust_address (dest, SImode, copied);
1105 rtx from = adjust_automodify_address (src, BLKmode,
1108 set_mem_size (from, GEN_INT (4));
1109 emit_insn (gen_movua (temp, from));
1110 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1111 emit_move_insn (to, temp);
1116 move_by_pieces (adjust_address (dest, BLKmode, copied),
1117 adjust_automodify_address (src, BLKmode,
1119 bytes - copied, align, 0);
1124 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1125 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1126 if (align < 4 || (bytes % 4 != 0))
1129 if (TARGET_HARD_SH4)
1133 else if (bytes == 12)
1135 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1136 rtx r4 = gen_rtx_REG (SImode, 4);
1137 rtx r5 = gen_rtx_REG (SImode, 5);
1139 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1140 force_into (XEXP (operands[0], 0), r4);
1141 force_into (XEXP (operands[1], 0), r5);
1142 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1145 else if (! TARGET_SMALLCODE)
1147 const char *entry_name;
1148 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1150 rtx r4 = gen_rtx_REG (SImode, 4);
1151 rtx r5 = gen_rtx_REG (SImode, 5);
1152 rtx r6 = gen_rtx_REG (SImode, 6);
1154 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1155 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1156 force_into (XEXP (operands[0], 0), r4);
1157 force_into (XEXP (operands[1], 0), r5);
1159 dwords = bytes >> 3;
1160 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1161 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1170 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1171 rtx r4 = gen_rtx_REG (SImode, 4);
1172 rtx r5 = gen_rtx_REG (SImode, 5);
1174 sprintf (entry, "__movmemSI%d", bytes);
1175 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1176 force_into (XEXP (operands[0], 0), r4);
1177 force_into (XEXP (operands[1], 0), r5);
1178 emit_insn (gen_block_move_real (func_addr_rtx));
1182 /* This is the same number of bytes as a memcpy call, but to a different
1183 less common function name, so this will occasionally use more space. */
1184 if (! TARGET_SMALLCODE)
1186 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1187 int final_switch, while_loop;
1188 rtx r4 = gen_rtx_REG (SImode, 4);
1189 rtx r5 = gen_rtx_REG (SImode, 5);
1190 rtx r6 = gen_rtx_REG (SImode, 6);
1192 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1193 force_into (XEXP (operands[0], 0), r4);
1194 force_into (XEXP (operands[1], 0), r5);
1196 /* r6 controls the size of the move. 16 is decremented from it
1197 for each 64 bytes moved. Then the negative bit left over is used
1198 as an index into a list of move instructions. e.g., a 72 byte move
1199 would be set up with size(r6) = 14, for one iteration through the
1200 big while loop, and a switch of -2 for the last part. */
1202 final_switch = 16 - ((bytes / 4) % 16);
1203 while_loop = ((bytes / 4) / 16 - 1) * 16;
1204 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1205 emit_insn (gen_block_lump_real (func_addr_rtx));
1212 /* Prepare operands for a move define_expand; specifically, one of the
1213 operands must be in a register. */
1216 prepare_move_operands (rtx operands[], enum machine_mode mode)
1218 if ((mode == SImode || mode == DImode)
1220 && ! ((mode == Pmode || mode == ptr_mode)
1221 && tls_symbolic_operand (operands[1], Pmode) != 0))
1224 if (SYMBOLIC_CONST_P (operands[1]))
1226 if (GET_CODE (operands[0]) == MEM)
1227 operands[1] = force_reg (Pmode, operands[1]);
1228 else if (TARGET_SHMEDIA
1229 && GET_CODE (operands[1]) == LABEL_REF
1230 && target_reg_operand (operands[0], mode))
1234 temp = (!can_create_pseudo_p ()
1236 : gen_reg_rtx (Pmode));
1237 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1240 else if (GET_CODE (operands[1]) == CONST
1241 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1242 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1244 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1245 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1247 operands[1] = expand_binop (mode, add_optab, temp,
1248 XEXP (XEXP (operands[1], 0), 1),
1249 (!can_create_pseudo_p ()
1251 : gen_reg_rtx (Pmode)),
1252 0, OPTAB_LIB_WIDEN);
1256 if (! reload_in_progress && ! reload_completed)
1258 /* Copy the source to a register if both operands aren't registers. */
1259 if (! register_operand (operands[0], mode)
1260 && ! sh_register_operand (operands[1], mode))
1261 operands[1] = copy_to_mode_reg (mode, operands[1]);
1263 if (GET_CODE (operands[0]) == MEM && ! memory_operand (operands[0], mode))
1265 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1266 except that we can't use that function because it is static. */
1267 rtx new_rtx = change_address (operands[0], mode, 0);
1268 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1269 operands[0] = new_rtx;
1272 /* This case can happen while generating code to move the result
1273 of a library call to the target. Reject `st r0,@(rX,rY)' because
1274 reload will fail to find a spill register for rX, since r0 is already
1275 being used for the source. */
1277 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1278 && GET_CODE (operands[0]) == MEM
1279 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1280 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
1281 operands[1] = copy_to_mode_reg (mode, operands[1]);
1284 if (mode == Pmode || mode == ptr_mode)
1287 enum tls_model tls_kind;
1291 if (GET_CODE (op1) == CONST
1292 && GET_CODE (XEXP (op1, 0)) == PLUS
1293 && tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode))
1295 opc = XEXP (XEXP (op1, 0), 1);
1296 op1 = XEXP (XEXP (op1, 0), 0);
1301 if ((tls_kind = tls_symbolic_operand (op1, Pmode)))
1303 rtx tga_op1, tga_ret, tmp, tmp2;
1307 case TLS_MODEL_GLOBAL_DYNAMIC:
1308 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1309 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1313 case TLS_MODEL_LOCAL_DYNAMIC:
1314 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1315 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1317 tmp = gen_reg_rtx (Pmode);
1318 emit_move_insn (tmp, tga_ret);
1320 if (register_operand (op0, Pmode))
1323 tmp2 = gen_reg_rtx (Pmode);
1325 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1329 case TLS_MODEL_INITIAL_EXEC:
1332 /* Don't schedule insns for getting GOT address when
1333 the first scheduling is enabled, to avoid spill
1335 if (flag_schedule_insns)
1336 emit_insn (gen_blockage ());
1337 emit_insn (gen_GOTaddr2picreg ());
1338 emit_use (gen_rtx_REG (SImode, PIC_REG));
1339 if (flag_schedule_insns)
1340 emit_insn (gen_blockage ());
1342 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1343 tmp = gen_sym2GOTTPOFF (op1);
1344 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1348 case TLS_MODEL_LOCAL_EXEC:
1349 tmp2 = gen_reg_rtx (Pmode);
1350 emit_insn (gen_load_gbr (tmp2));
1351 tmp = gen_reg_rtx (Pmode);
1352 emit_insn (gen_symTPOFF2reg (tmp, op1));
1354 if (register_operand (op0, Pmode))
1357 op1 = gen_reg_rtx (Pmode);
1359 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1366 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1375 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1376 enum rtx_code comparison)
1379 rtx scratch = NULL_RTX;
1381 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1382 comparison = GET_CODE (operands[0]);
1384 scratch = operands[4];
1385 if (GET_CODE (operands[1]) == CONST_INT
1386 && GET_CODE (operands[2]) != CONST_INT)
1388 rtx tmp = operands[1];
1390 operands[1] = operands[2];
1392 comparison = swap_condition (comparison);
1394 if (GET_CODE (operands[2]) == CONST_INT)
1396 HOST_WIDE_INT val = INTVAL (operands[2]);
1397 if ((val == -1 || val == -0x81)
1398 && (comparison == GT || comparison == LE))
1400 comparison = (comparison == GT) ? GE : LT;
1401 operands[2] = gen_int_mode (val + 1, mode);
1403 else if ((val == 1 || val == 0x80)
1404 && (comparison == GE || comparison == LT))
1406 comparison = (comparison == GE) ? GT : LE;
1407 operands[2] = gen_int_mode (val - 1, mode);
1409 else if (val == 1 && (comparison == GEU || comparison == LTU))
1411 comparison = (comparison == GEU) ? NE : EQ;
1412 operands[2] = CONST0_RTX (mode);
1414 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1416 comparison = (comparison == GEU) ? GTU : LEU;
1417 operands[2] = gen_int_mode (val - 1, mode);
1419 else if (val == 0 && (comparison == GTU || comparison == LEU))
1420 comparison = (comparison == GTU) ? NE : EQ;
1421 else if (mode == SImode
1422 && ((val == 0x7fffffff
1423 && (comparison == GTU || comparison == LEU))
1424 || ((unsigned HOST_WIDE_INT) val
1425 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1426 && (comparison == GEU || comparison == LTU))))
1428 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1429 operands[2] = CONST0_RTX (mode);
1433 if (can_create_pseudo_p ())
1434 operands[1] = force_reg (mode, op1);
1435 /* When we are handling DImode comparisons, we want to keep constants so
1436 that we can optimize the component comparisons; however, memory loads
1437 are better issued as a whole so that they can be scheduled well.
1438 SImode equality comparisons allow I08 constants, but only when they
1439 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1440 into a register, that register might as well be r0, and we allow the
1441 constant. If it is already in a register, this is likely to be
1442 allocated to a different hard register, thus we load the constant into
1443 a register unless it is zero. */
1444 if (!REG_P (operands[2])
1445 && (GET_CODE (operands[2]) != CONST_INT
1446 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1447 && ((comparison != EQ && comparison != NE)
1448 || (REG_P (op1) && REGNO (op1) != R0_REG)
1449 || !satisfies_constraint_I08 (operands[2])))))
1451 if (scratch && GET_MODE (scratch) == mode)
1453 emit_move_insn (scratch, operands[2]);
1454 operands[2] = scratch;
1456 else if (can_create_pseudo_p ())
1457 operands[2] = force_reg (mode, operands[2]);
1463 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1465 rtx (*branch_expander) (rtx) = gen_branch_true;
1468 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1471 case NE: case LT: case LE: case LTU: case LEU:
1472 comparison = reverse_condition (comparison);
1473 branch_expander = gen_branch_false;
1476 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1477 gen_rtx_fmt_ee (comparison, SImode,
1478 operands[1], operands[2])));
1479 jump = emit_jump_insn (branch_expander (operands[3]));
1480 if (probability >= 0)
1481 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
1485 /* ??? How should we distribute probabilities when more than one branch
1486 is generated. So far we only have soem ad-hoc observations:
1487 - If the operands are random, they are likely to differ in both parts.
1488 - If comparing items in a hash chain, the operands are random or equal;
1489 operation should be EQ or NE.
1490 - If items are searched in an ordered tree from the root, we can expect
1491 the highpart to be unequal about half of the time; operation should be
1492 an inequality comparison, operands non-constant, and overall probability
1493 about 50%. Likewise for quicksort.
1494 - Range checks will be often made against constants. Even if we assume for
1495 simplicity an even distribution of the non-constant operand over a
1496 sub-range here, the same probability could be generated with differently
1497 wide sub-ranges - as long as the ratio of the part of the subrange that
1498 is before the threshold to the part that comes after the threshold stays
1499 the same. Thus, we can't really tell anything here;
1500 assuming random distribution is at least simple.
1504 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1506 enum rtx_code msw_taken, msw_skip, lsw_taken;
1507 rtx skip_label = NULL_RTX;
1508 rtx op1h, op1l, op2h, op2l;
1511 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1512 rtx scratch = operands[4];
1514 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1515 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1516 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1517 op1l = gen_lowpart (SImode, operands[1]);
1518 op2l = gen_lowpart (SImode, operands[2]);
1519 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
1520 prob = split_branch_probability;
1521 rev_prob = REG_BR_PROB_BASE - prob;
1524 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1525 That costs 1 cycle more when the first branch can be predicted taken,
1526 but saves us mispredicts because only one branch needs prediction.
1527 It also enables generating the cmpeqdi_t-1 pattern. */
1529 if (TARGET_CMPEQDI_T)
1531 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1532 emit_jump_insn (gen_branch_true (operands[3]));
1539 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1541 msw_skip_prob = rev_prob;
1542 if (REG_BR_PROB_BASE <= 65535)
1543 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1546 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1550 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1551 / ((HOST_WIDEST_INT) prob << 32)))
1557 if (TARGET_CMPEQDI_T)
1559 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1560 emit_jump_insn (gen_branch_false (operands[3]));
1564 msw_taken_prob = prob;
1569 msw_taken = comparison;
1570 if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1)
1572 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1573 msw_skip = swap_condition (msw_taken);
1577 if (op2l == CONST0_RTX (SImode))
1578 msw_taken = comparison;
1581 msw_taken = comparison == GE ? GT : GTU;
1582 msw_skip = swap_condition (msw_taken);
1587 msw_taken = comparison;
1588 if (op2l == CONST0_RTX (SImode))
1590 msw_skip = swap_condition (msw_taken);
1594 if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1)
1595 msw_taken = comparison;
1599 if (comparison == LE)
1601 else if (op2h != CONST0_RTX (SImode))
1605 msw_skip = swap_condition (msw_taken);
1608 default: return false;
1610 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
1611 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1612 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
1613 if (comparison != EQ && comparison != NE && num_branches > 1)
1615 if (!CONSTANT_P (operands[2])
1616 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1617 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1619 msw_taken_prob = prob / 2U;
1621 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1622 lsw_taken_prob = prob;
1626 msw_taken_prob = prob;
1627 msw_skip_prob = REG_BR_PROB_BASE;
1628 /* ??? If we have a constant op2h, should we use that when
1629 calculating lsw_taken_prob? */
1630 lsw_taken_prob = prob;
1635 operands[4] = NULL_RTX;
1636 if (reload_completed
1637 && ! arith_reg_or_0_operand (op2h, SImode) && true_regnum (op1h)
1638 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
1639 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
1641 emit_move_insn (scratch, operands[2]);
1642 operands[2] = scratch;
1644 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1645 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
1646 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1648 rtx taken_label = operands[3];
1650 /* Operands were possibly modified, but msw_skip doesn't expect this.
1651 Always use the original ones. */
1652 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1658 operands[3] = skip_label = gen_label_rtx ();
1659 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
1660 operands[3] = taken_label;
1664 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
1666 if (reload_completed
1667 && ! arith_reg_or_0_operand (op2l, SImode) && true_regnum (op1l))
1668 operands[4] = scratch;
1669 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
1671 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1672 emit_label (skip_label);
1676 /* Prepare the operands for an scc instruction; make sure that the
1677 compare has been done. */
1679 prepare_scc_operands (enum rtx_code code)
1681 rtx t_reg = gen_rtx_REG (SImode, T_REG);
1682 enum rtx_code oldcode = code;
1683 enum machine_mode mode;
1685 /* First need a compare insn. */
1689 /* It isn't possible to handle this case. */
1706 if (code != oldcode)
1708 rtx tmp = sh_compare_op0;
1709 sh_compare_op0 = sh_compare_op1;
1710 sh_compare_op1 = tmp;
1713 mode = GET_MODE (sh_compare_op0);
1714 if (mode == VOIDmode)
1715 mode = GET_MODE (sh_compare_op1);
1717 sh_compare_op0 = force_reg (mode, sh_compare_op0);
1718 if ((code != EQ && code != NE
1719 && (sh_compare_op1 != const0_rtx
1720 || code == GTU || code == GEU || code == LTU || code == LEU))
1721 || (mode == DImode && sh_compare_op1 != const0_rtx)
1722 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1723 sh_compare_op1 = force_reg (mode, sh_compare_op1);
1725 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1726 (mode == SFmode ? emit_sf_insn : emit_df_insn)
1727 (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
1728 gen_rtx_SET (VOIDmode, t_reg,
1729 gen_rtx_fmt_ee (code, SImode,
1730 sh_compare_op0, sh_compare_op1)),
1731 gen_rtx_USE (VOIDmode, get_fpscr_rtx ()))));
1733 emit_insn (gen_rtx_SET (VOIDmode, t_reg,
1734 gen_rtx_fmt_ee (code, SImode,
1735 sh_compare_op0, sh_compare_op1)));
1740 /* Called from the md file, set up the operands of a compare instruction. */
1743 from_compare (rtx *operands, int code)
1745 enum machine_mode mode = GET_MODE (sh_compare_op0);
1747 if (mode == VOIDmode)
1748 mode = GET_MODE (sh_compare_op1);
1751 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1753 /* Force args into regs, since we can't use constants here. */
1754 sh_compare_op0 = force_reg (mode, sh_compare_op0);
1755 if (sh_compare_op1 != const0_rtx
1756 || code == GTU || code == GEU
1757 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1758 sh_compare_op1 = force_reg (mode, sh_compare_op1);
1760 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
1762 from_compare (operands, GT);
1763 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
1766 insn = gen_rtx_SET (VOIDmode,
1767 gen_rtx_REG (SImode, T_REG),
1768 gen_rtx_fmt_ee ((enum rtx_code) code, SImode,
1769 sh_compare_op0, sh_compare_op1));
1770 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1772 insn = gen_rtx_PARALLEL (VOIDmode,
1774 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
1775 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1781 /* Functions to output assembly code. */
1783 /* Return a sequence of instructions to perform DI or DF move.
1785 Since the SH cannot move a DI or DF in one instruction, we have
1786 to take care when we see overlapping source and dest registers. */
1789 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1790 enum machine_mode mode)
1792 rtx dst = operands[0];
1793 rtx src = operands[1];
1795 if (GET_CODE (dst) == MEM
1796 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
1797 return "mov.l %T1,%0\n\tmov.l %1,%0";
1799 if (register_operand (dst, mode)
1800 && register_operand (src, mode))
1802 if (REGNO (src) == MACH_REG)
1803 return "sts mach,%S0\n\tsts macl,%R0";
1805 /* When mov.d r1,r2 do r2->r3 then r1->r2;
1806 when mov.d r1,r0 do r1->r0 then r2->r1. */
1808 if (REGNO (src) + 1 == REGNO (dst))
1809 return "mov %T1,%T0\n\tmov %1,%0";
1811 return "mov %1,%0\n\tmov %T1,%T0";
1813 else if (GET_CODE (src) == CONST_INT)
1815 if (INTVAL (src) < 0)
1816 output_asm_insn ("mov #-1,%S0", operands);
1818 output_asm_insn ("mov #0,%S0", operands);
1820 return "mov %1,%R0";
1822 else if (GET_CODE (src) == MEM)
1825 int dreg = REGNO (dst);
1826 rtx inside = XEXP (src, 0);
1828 switch (GET_CODE (inside))
1831 ptrreg = REGNO (inside);
1835 ptrreg = subreg_regno (inside);
1839 ptrreg = REGNO (XEXP (inside, 0));
1840 /* ??? A r0+REG address shouldn't be possible here, because it isn't
1841 an offsettable address. Unfortunately, offsettable addresses use
1842 QImode to check the offset, and a QImode offsettable address
1843 requires r0 for the other operand, which is not currently
1844 supported, so we can't use the 'o' constraint.
1845 Thus we must check for and handle r0+REG addresses here.
1846 We punt for now, since this is likely very rare. */
1847 gcc_assert (GET_CODE (XEXP (inside, 1)) != REG);
1851 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
1853 return "mov.l %1,%0\n\tmov.l %1,%T0";
1858 /* Work out the safe way to copy. Copy into the second half first. */
1860 return "mov.l %T1,%T0\n\tmov.l %1,%0";
1863 return "mov.l %1,%0\n\tmov.l %T1,%T0";
1866 /* Print an instruction which would have gone into a delay slot after
1867 another instruction, but couldn't because the other instruction expanded
1868 into a sequence where putting the slot insn at the end wouldn't work. */
1871 print_slot (rtx insn)
1873 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
1875 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
1879 output_far_jump (rtx insn, rtx op)
1881 struct { rtx lab, reg, op; } this_jmp;
1882 rtx braf_base_lab = NULL_RTX;
1885 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
1888 this_jmp.lab = gen_label_rtx ();
1892 && offset - get_attr_length (insn) <= 32766)
1895 jump = "mov.w %O0,%1; braf %1";
1903 jump = "mov.l %O0,%1; braf %1";
1905 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1908 jump = "mov.l %O0,%1; jmp @%1";
1910 /* If we have a scratch register available, use it. */
1911 if (GET_CODE ((prev = prev_nonnote_insn (insn))) == INSN
1912 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
1914 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
1915 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
1916 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1917 output_asm_insn (jump, &this_jmp.lab);
1918 if (dbr_sequence_length ())
1919 print_slot (final_sequence);
1921 output_asm_insn ("nop", 0);
1925 /* Output the delay slot insn first if any. */
1926 if (dbr_sequence_length ())
1927 print_slot (final_sequence);
1929 this_jmp.reg = gen_rtx_REG (SImode, 13);
1930 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1931 Fortunately, MACL is fixed and call-clobbered, and we never
1932 need its value across jumps, so save r13 in it instead of in
1935 output_asm_insn ("lds r13, macl", 0);
1937 output_asm_insn ("mov.l r13,@-r15", 0);
1938 output_asm_insn (jump, &this_jmp.lab);
1940 output_asm_insn ("sts macl, r13", 0);
1942 output_asm_insn ("mov.l @r15+,r13", 0);
1944 if (far && flag_pic && TARGET_SH2)
1946 braf_base_lab = gen_label_rtx ();
1947 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1948 CODE_LABEL_NUMBER (braf_base_lab));
1951 output_asm_insn (".align 2", 0);
1952 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
1954 if (far && flag_pic)
1957 this_jmp.lab = braf_base_lab;
1958 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
1961 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
1965 /* Local label counter, used for constants in the pool and inside
1966 pattern branches. */
1968 static int lf = 100;
1970 /* Output code for ordinary branches. */
1973 output_branch (int logic, rtx insn, rtx *operands)
1975 switch (get_attr_length (insn))
1978 /* This can happen if filling the delay slot has caused a forward
1979 branch to exceed its range (we could reverse it, but only
1980 when we know we won't overextend other branches; this should
1981 best be handled by relaxation).
1982 It can also happen when other condbranches hoist delay slot insn
1983 from their destination, thus leading to code size increase.
1984 But the branch will still be in the range -4092..+4098 bytes. */
1989 /* The call to print_slot will clobber the operands. */
1990 rtx op0 = operands[0];
1992 /* If the instruction in the delay slot is annulled (true), then
1993 there is no delay slot where we can put it now. The only safe
1994 place for it is after the label. final will do that by default. */
1997 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
1998 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2000 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2001 ASSEMBLER_DIALECT ? "/" : ".", label);
2002 print_slot (final_sequence);
2005 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2007 output_asm_insn ("bra\t%l0", &op0);
2008 fprintf (asm_out_file, "\tnop\n");
2009 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2013 /* When relaxing, handle this like a short branch. The linker
2014 will fix it up if it still doesn't fit after relaxation. */
2016 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2018 /* These are for SH2e, in which we have to account for the
2019 extra nop because of the hardware bug in annulled branches. */
2025 gcc_assert (!final_sequence
2026 || !(INSN_ANNULLED_BRANCH_P
2027 (XVECEXP (final_sequence, 0, 0))));
2028 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2030 ASSEMBLER_DIALECT ? "/" : ".", label);
2031 fprintf (asm_out_file, "\tnop\n");
2032 output_asm_insn ("bra\t%l0", operands);
2033 fprintf (asm_out_file, "\tnop\n");
2034 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2038 /* When relaxing, fall through. */
2043 sprintf (buffer, "b%s%ss\t%%l0",
2045 ASSEMBLER_DIALECT ? "/" : ".");
2046 output_asm_insn (buffer, &operands[0]);
2051 /* There should be no longer branches now - that would
2052 indicate that something has destroyed the branches set
2053 up in machine_dependent_reorg. */
2058 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2059 fill in operands 9 as a label to the successor insn.
2060 We try to use jump threading where possible.
2061 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2062 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2063 follow jmp and bt, if the address is in range. */
2065 output_branchy_insn (enum rtx_code code, const char *templ,
2066 rtx insn, rtx *operands)
2068 rtx next_insn = NEXT_INSN (insn);
2070 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
2072 rtx src = SET_SRC (PATTERN (next_insn));
2073 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2075 /* Following branch not taken */
2076 operands[9] = gen_label_rtx ();
2077 emit_label_after (operands[9], next_insn);
2078 INSN_ADDRESSES_NEW (operands[9],
2079 INSN_ADDRESSES (INSN_UID (next_insn))
2080 + get_attr_length (next_insn));
2085 int offset = (branch_dest (next_insn)
2086 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2087 if (offset >= -252 && offset <= 258)
2089 if (GET_CODE (src) == IF_THEN_ELSE)
2091 src = XEXP (src, 1);
2097 operands[9] = gen_label_rtx ();
2098 emit_label_after (operands[9], insn);
2099 INSN_ADDRESSES_NEW (operands[9],
2100 INSN_ADDRESSES (INSN_UID (insn))
2101 + get_attr_length (insn));
2106 output_ieee_ccmpeq (rtx insn, rtx *operands)
2108 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2112 /* Output the start of the assembler file. */
2115 sh_file_start (void)
2117 default_file_start ();
2120 /* Declare the .directive section before it is used. */
2121 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2122 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2126 /* We need to show the text section with the proper
2127 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2128 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2129 will complain. We can teach GAS specifically about the
2130 default attributes for our choice of text section, but
2131 then we would have to change GAS again if/when we change
2132 the text section name. */
2133 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2135 /* Switch to the data section so that the coffsem symbol
2136 isn't in the text section. */
2137 switch_to_section (data_section);
2139 if (TARGET_LITTLE_ENDIAN)
2140 fputs ("\t.little\n", asm_out_file);
2144 if (TARGET_SHCOMPACT)
2145 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2146 else if (TARGET_SHMEDIA)
2147 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2148 TARGET_SHMEDIA64 ? 64 : 32);
2152 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2155 unspec_caller_rtx_p (rtx pat)
2160 split_const (pat, &base, &offset);
2161 if (GET_CODE (base) == UNSPEC)
2163 if (XINT (base, 1) == UNSPEC_CALLER)
2165 for (i = 0; i < XVECLEN (base, 0); i++)
2166 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2172 /* Indicate that INSN cannot be duplicated. This is true for insn
2173 that generates a unique label. */
2176 sh_cannot_copy_insn_p (rtx insn)
2180 if (!reload_completed || !flag_pic)
2183 if (GET_CODE (insn) != INSN)
2185 if (asm_noperands (insn) >= 0)
2188 pat = PATTERN (insn);
2189 if (GET_CODE (pat) != SET)
2191 pat = SET_SRC (pat);
2193 if (unspec_caller_rtx_p (pat))
2199 /* Actual number of instructions used to make a shift by N. */
2200 static const char ashiftrt_insns[] =
2201 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2203 /* Left shift and logical right shift are the same. */
2204 static const char shift_insns[] =
2205 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2207 /* Individual shift amounts needed to get the above length sequences.
2208 One bit right shifts clobber the T bit, so when possible, put one bit
2209 shifts in the middle of the sequence, so the ends are eligible for
2210 branch delay slots. */
2211 static const short shift_amounts[32][5] = {
2212 {0}, {1}, {2}, {2, 1},
2213 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2214 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2215 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2216 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2217 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2218 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2219 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2221 /* Likewise, but for shift amounts < 16, up to three highmost bits
2222 might be clobbered. This is typically used when combined with some
2223 kind of sign or zero extension. */
2225 static const char ext_shift_insns[] =
2226 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2228 static const short ext_shift_amounts[32][4] = {
2229 {0}, {1}, {2}, {2, 1},
2230 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2231 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2232 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2233 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2234 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2235 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2236 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2238 /* Assuming we have a value that has been sign-extended by at least one bit,
2239 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2240 to shift it by N without data loss, and quicker than by other means? */
2241 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2243 /* This is used in length attributes in sh.md to help compute the length
2244 of arbitrary constant shift instructions. */
2247 shift_insns_rtx (rtx insn)
2249 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2250 int shift_count = INTVAL (XEXP (set_src, 1));
2251 enum rtx_code shift_code = GET_CODE (set_src);
2256 return ashiftrt_insns[shift_count];
2259 return shift_insns[shift_count];
2265 /* Return the cost of a shift. */
2275 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2277 if (GET_MODE (x) == DImode
2278 && GET_CODE (XEXP (x, 1)) == CONST_INT
2279 && INTVAL (XEXP (x, 1)) == 1)
2282 /* Everything else is invalid, because there is no pattern for it. */
2285 /* If shift by a non constant, then this will be expensive. */
2286 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2287 return SH_DYNAMIC_SHIFT_COST;
2289 value = INTVAL (XEXP (x, 1));
2291 /* Otherwise, return the true cost in instructions. */
2292 if (GET_CODE (x) == ASHIFTRT)
2294 int cost = ashiftrt_insns[value];
2295 /* If SH3, then we put the constant in a reg and use shad. */
2296 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2297 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2301 return shift_insns[value];
2304 /* Return the cost of an AND operation. */
2311 /* Anding with a register is a single cycle and instruction. */
2312 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2315 i = INTVAL (XEXP (x, 1));
2319 if (satisfies_constraint_I10 (XEXP (x, 1))
2320 || satisfies_constraint_J16 (XEXP (x, 1)))
2323 return 1 + rtx_cost (XEXP (x, 1), AND, !optimize_size);
2326 /* These constants are single cycle extu.[bw] instructions. */
2327 if (i == 0xff || i == 0xffff)
2329 /* Constants that can be used in an and immediate instruction in a single
2330 cycle, but this requires r0, so make it a little more expensive. */
2331 if (CONST_OK_FOR_K08 (i))
2333 /* Constants that can be loaded with a mov immediate and an and.
2334 This case is probably unnecessary. */
2335 if (CONST_OK_FOR_I08 (i))
2337 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2338 This case is probably unnecessary. */
2342 /* Return the cost of an addition or a subtraction. */
2347 /* Adding a register is a single cycle insn. */
2348 if (GET_CODE (XEXP (x, 1)) == REG
2349 || GET_CODE (XEXP (x, 1)) == SUBREG)
2352 /* Likewise for small constants. */
2353 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2354 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2358 switch (GET_CODE (XEXP (x, 1)))
2363 return TARGET_SHMEDIA64 ? 5 : 3;
2366 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2368 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2370 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2378 /* Any other constant requires a 2 cycle pc-relative load plus an
2383 /* Return the cost of a multiply. */
2385 multcosts (rtx x ATTRIBUTE_UNUSED)
2387 if (sh_multcost >= 0)
2390 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2391 accept constants. Ideally, we would use a cost of one or two and
2392 add the cost of the operand, but disregard the latter when inside loops
2393 and loop invariant code motion is still to follow.
2394 Using a multiply first and splitting it later if it's a loss
2395 doesn't work because of different sign / zero extension semantics
2396 of multiplies vs. shifts. */
2397 return TARGET_SMALLCODE ? 2 : 3;
2401 /* We have a mul insn, so we can never take more than the mul and the
2402 read of the mac reg, but count more because of the latency and extra
2404 if (TARGET_SMALLCODE)
2409 /* If we're aiming at small code, then just count the number of
2410 insns in a multiply call sequence. */
2411 if (TARGET_SMALLCODE)
2414 /* Otherwise count all the insns in the routine we'd be calling too. */
2418 /* Compute a (partial) cost for rtx X. Return true if the complete
2419 cost has been computed, and false if subexpressions should be
2420 scanned. In either case, *TOTAL contains the cost result. */
2423 sh_rtx_costs (rtx x, int code, int outer_code, int *total,
2424 bool speed ATTRIBUTE_UNUSED)
2431 if (INTVAL (x) == 0)
2433 else if (outer_code == AND && and_operand ((x), DImode))
2435 else if ((outer_code == IOR || outer_code == XOR
2436 || outer_code == PLUS)
2437 && CONST_OK_FOR_I10 (INTVAL (x)))
2439 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2440 *total = COSTS_N_INSNS (outer_code != SET);
2441 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2442 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2443 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2444 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2446 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2449 if (CONST_OK_FOR_I08 (INTVAL (x)))
2451 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2452 && CONST_OK_FOR_K08 (INTVAL (x)))
2454 /* prepare_cmp_insn will force costly constants int registers before
2455 the cbranch[sd]i4 patterns can see them, so preserve potentially
2456 interesting ones not covered by I08 above. */
2457 else if (outer_code == COMPARE
2458 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2459 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2460 || INTVAL (x) == 0x7fffffff
2461 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2470 if (TARGET_SHMEDIA64)
2471 *total = COSTS_N_INSNS (4);
2472 else if (TARGET_SHMEDIA32)
2473 *total = COSTS_N_INSNS (2);
2480 *total = COSTS_N_INSNS (4);
2481 /* prepare_cmp_insn will force costly constants int registers before
2482 the cbranchdi4 pattern can see them, so preserve potentially
2483 interesting ones. */
2484 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
2490 if (x == CONST0_RTX (GET_MODE (x)))
2492 else if (sh_1el_vec (x, VOIDmode))
2493 *total = outer_code != SET;
2494 if (sh_rep_vec (x, VOIDmode))
2495 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2496 + (outer_code != SET));
2497 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2502 *total = COSTS_N_INSNS (addsubcosts (x));
2506 *total = COSTS_N_INSNS (andcosts (x));
2510 *total = COSTS_N_INSNS (multcosts (x));
2516 *total = COSTS_N_INSNS (shiftcosts (x));
2523 *total = COSTS_N_INSNS (20);
2527 if (sh_1el_vec (x, VOIDmode))
2528 *total = outer_code != SET;
2529 if (sh_rep_vec (x, VOIDmode))
2530 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2531 + (outer_code != SET));
2532 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2545 /* Compute the cost of an address. For the SH, all valid addresses are
2546 the same cost. Use a slightly higher cost for reg + reg addressing,
2547 since it increases pressure on r0. */
2550 sh_address_cost (rtx X,
2551 bool speed ATTRIBUTE_UNUSED)
2553 return (GET_CODE (X) == PLUS
2554 && ! CONSTANT_P (XEXP (X, 1))
2555 && ! TARGET_SHMEDIA ? 1 : 0);
2558 /* Code to expand a shift. */
2561 gen_ashift (int type, int n, rtx reg)
2563 /* Negative values here come from the shift_amounts array. */
2576 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
2580 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
2582 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
2585 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
2590 /* Same for HImode */
2593 gen_ashift_hi (int type, int n, rtx reg)
2595 /* Negative values here come from the shift_amounts array. */
2609 /* We don't have HImode right shift operations because using the
2610 ordinary 32 bit shift instructions for that doesn't generate proper
2611 zero/sign extension.
2612 gen_ashift_hi is only called in contexts where we know that the
2613 sign extension works out correctly. */
2616 if (GET_CODE (reg) == SUBREG)
2618 offset = SUBREG_BYTE (reg);
2619 reg = SUBREG_REG (reg);
2621 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
2625 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
2630 /* Output RTL to split a constant shift into its component SH constant
2631 shift instructions. */
2634 gen_shifty_op (int code, rtx *operands)
2636 int value = INTVAL (operands[2]);
2639 /* Truncate the shift count in case it is out of bounds. */
2640 value = value & 0x1f;
2644 if (code == LSHIFTRT)
2646 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2647 emit_insn (gen_movt (operands[0]));
2650 else if (code == ASHIFT)
2652 /* There is a two instruction sequence for 31 bit left shifts,
2653 but it requires r0. */
2654 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
2656 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
2657 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2662 else if (value == 0)
2664 /* This can happen even when optimizing, if there were subregs before
2665 reload. Don't output a nop here, as this is never optimized away;
2666 use a no-op move instead. */
2667 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
2671 max = shift_insns[value];
2672 for (i = 0; i < max; i++)
2673 gen_ashift (code, shift_amounts[value][i], operands[0]);
2676 /* Same as above, but optimized for values where the topmost bits don't
2680 gen_shifty_hi_op (int code, rtx *operands)
2682 int value = INTVAL (operands[2]);
2684 void (*gen_fun) (int, int, rtx);
2686 /* This operation is used by and_shl for SImode values with a few
2687 high bits known to be cleared. */
2691 emit_insn (gen_nop ());
2695 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
2698 max = ext_shift_insns[value];
2699 for (i = 0; i < max; i++)
2700 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2703 /* When shifting right, emit the shifts in reverse order, so that
2704 solitary negative values come first. */
2705 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
2706 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2709 /* Output RTL for an arithmetic right shift. */
2711 /* ??? Rewrite to use super-optimizer sequences. */
2714 expand_ashiftrt (rtx *operands)
2722 if (GET_CODE (operands[2]) != CONST_INT)
2724 rtx count = copy_to_mode_reg (SImode, operands[2]);
2725 emit_insn (gen_negsi2 (count, count));
2726 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2729 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
2730 > 1 + SH_DYNAMIC_SHIFT_COST)
2733 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
2734 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2738 if (GET_CODE (operands[2]) != CONST_INT)
2741 value = INTVAL (operands[2]) & 31;
2745 /* If we are called from abs expansion, arrange things so that we
2746 we can use a single MT instruction that doesn't clobber the source,
2747 if LICM can hoist out the load of the constant zero. */
2748 if (currently_expanding_to_rtl)
2750 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
2752 emit_insn (gen_mov_neg_si_t (operands[0]));
2755 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
2758 else if (value >= 16 && value <= 19)
2760 wrk = gen_reg_rtx (SImode);
2761 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
2764 gen_ashift (ASHIFTRT, 1, wrk);
2765 emit_move_insn (operands[0], wrk);
2768 /* Expand a short sequence inline, longer call a magic routine. */
2769 else if (value <= 5)
2771 wrk = gen_reg_rtx (SImode);
2772 emit_move_insn (wrk, operands[1]);
2774 gen_ashift (ASHIFTRT, 1, wrk);
2775 emit_move_insn (operands[0], wrk);
2779 wrk = gen_reg_rtx (Pmode);
2781 /* Load the value into an arg reg and call a helper. */
2782 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2783 sprintf (func, "__ashiftrt_r4_%d", value);
2784 function_symbol (wrk, func, SFUNC_STATIC);
2785 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
2786 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
2791 sh_dynamicalize_shift_p (rtx count)
2793 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
2796 /* Try to find a good way to implement the combiner pattern
2797 [(set (match_operand:SI 0 "register_operand" "r")
2798 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2799 (match_operand:SI 2 "const_int_operand" "n"))
2800 (match_operand:SI 3 "const_int_operand" "n"))) .
2801 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
2802 return 0 for simple right / left or left/right shift combination.
2803 return 1 for a combination of shifts with zero_extend.
2804 return 2 for a combination of shifts with an AND that needs r0.
2805 return 3 for a combination of shifts with an AND that needs an extra
2806 scratch register, when the three highmost bits of the AND mask are clear.
2807 return 4 for a combination of shifts with an AND that needs an extra
2808 scratch register, when any of the three highmost bits of the AND mask
2810 If ATTRP is set, store an initial right shift width in ATTRP[0],
2811 and the instruction length in ATTRP[1] . These values are not valid
2813 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
2814 shift_amounts for the last shift value that is to be used before the
2817 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
2819 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
2820 int left = INTVAL (left_rtx), right;
2822 int cost, best_cost = 10000;
2823 int best_right = 0, best_len = 0;
2827 if (left < 0 || left > 31)
2829 if (GET_CODE (mask_rtx) == CONST_INT)
2830 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
2832 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
2833 /* Can this be expressed as a right shift / left shift pair? */
2834 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
2835 right = exact_log2 (lsb);
2836 mask2 = ~(mask + lsb - 1);
2837 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
2838 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
2840 best_cost = shift_insns[right] + shift_insns[right + left];
2841 /* mask has no trailing zeroes <==> ! right */
2842 else if (! right && mask2 == ~(lsb2 - 1))
2844 int late_right = exact_log2 (lsb2);
2845 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
2847 /* Try to use zero extend. */
2848 if (mask2 == ~(lsb2 - 1))
2852 for (width = 8; width <= 16; width += 8)
2854 /* Can we zero-extend right away? */
2855 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
2858 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
2859 if (cost < best_cost)
2870 /* ??? Could try to put zero extend into initial right shift,
2871 or even shift a bit left before the right shift. */
2872 /* Determine value of first part of left shift, to get to the
2873 zero extend cut-off point. */
2874 first = width - exact_log2 (lsb2) + right;
2875 if (first >= 0 && right + left - first >= 0)
2877 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
2878 + ext_shift_insns[right + left - first];
2879 if (cost < best_cost)
2891 /* Try to use r0 AND pattern */
2892 for (i = 0; i <= 2; i++)
2896 if (! CONST_OK_FOR_K08 (mask >> i))
2898 cost = (i != 0) + 2 + ext_shift_insns[left + i];
2899 if (cost < best_cost)
2904 best_len = cost - 1;
2907 /* Try to use a scratch register to hold the AND operand. */
2908 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
2909 for (i = 0; i <= 2; i++)
2913 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
2914 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
2915 if (cost < best_cost)
2920 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
2926 attrp[0] = best_right;
2927 attrp[1] = best_len;
2932 /* This is used in length attributes of the unnamed instructions
2933 corresponding to shl_and_kind return values of 1 and 2. */
2935 shl_and_length (rtx insn)
2937 rtx set_src, left_rtx, mask_rtx;
2940 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2941 left_rtx = XEXP (XEXP (set_src, 0), 1);
2942 mask_rtx = XEXP (set_src, 1);
2943 shl_and_kind (left_rtx, mask_rtx, attributes);
2944 return attributes[1];
2947 /* This is used in length attribute of the and_shl_scratch instruction. */
2950 shl_and_scr_length (rtx insn)
2952 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2953 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
2954 rtx op = XEXP (set_src, 0);
2955 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
2956 op = XEXP (XEXP (op, 0), 0);
2957 return len + shift_insns[INTVAL (XEXP (op, 1))];
2960 /* Generate rtl for instructions for which shl_and_kind advised a particular
2961 method of generating them, i.e. returned zero. */
2964 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
2967 unsigned HOST_WIDE_INT mask;
2968 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
2969 int right, total_shift;
2970 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
2972 right = attributes[0];
2973 total_shift = INTVAL (left_rtx) + right;
2974 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
2981 int first = attributes[2];
2986 emit_insn ((mask << right) <= 0xff
2987 ? gen_zero_extendqisi2 (dest,
2988 gen_lowpart (QImode, source))
2989 : gen_zero_extendhisi2 (dest,
2990 gen_lowpart (HImode, source)));
2994 emit_insn (gen_movsi (dest, source));
2998 operands[2] = GEN_INT (right);
2999 gen_shifty_hi_op (LSHIFTRT, operands);
3003 operands[2] = GEN_INT (first);
3004 gen_shifty_hi_op (ASHIFT, operands);
3005 total_shift -= first;
3009 emit_insn (mask <= 0xff
3010 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3011 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3012 if (total_shift > 0)
3014 operands[2] = GEN_INT (total_shift);
3015 gen_shifty_hi_op (ASHIFT, operands);
3020 shift_gen_fun = gen_shifty_op;
3022 /* If the topmost bit that matters is set, set the topmost bits
3023 that don't matter. This way, we might be able to get a shorter
3025 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3026 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3028 /* Don't expand fine-grained when combining, because that will
3029 make the pattern fail. */
3030 if (currently_expanding_to_rtl
3031 || reload_in_progress || reload_completed)
3035 /* Cases 3 and 4 should be handled by this split
3036 only while combining */
3037 gcc_assert (kind <= 2);
3040 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3043 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3048 operands[2] = GEN_INT (total_shift);
3049 shift_gen_fun (ASHIFT, operands);
3056 if (kind != 4 && total_shift < 16)
3058 neg = -ext_shift_amounts[total_shift][1];
3060 neg -= ext_shift_amounts[total_shift][2];
3064 emit_insn (gen_and_shl_scratch (dest, source,
3067 GEN_INT (total_shift + neg),
3069 emit_insn (gen_movsi (dest, dest));
3076 /* Try to find a good way to implement the combiner pattern
3077 [(set (match_operand:SI 0 "register_operand" "=r")
3078 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3079 (match_operand:SI 2 "const_int_operand" "n")
3080 (match_operand:SI 3 "const_int_operand" "n")
3082 (clobber (reg:SI T_REG))]
3083 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3084 return 0 for simple left / right shift combination.
3085 return 1 for left shift / 8 bit sign extend / left shift.
3086 return 2 for left shift / 16 bit sign extend / left shift.
3087 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3088 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3089 return 5 for left shift / 16 bit sign extend / right shift
3090 return 6 for < 8 bit sign extend / left shift.
3091 return 7 for < 8 bit sign extend / left shift / single right shift.
3092 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3095 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3097 int left, size, insize, ext;
3098 int cost = 0, best_cost;
3101 left = INTVAL (left_rtx);
3102 size = INTVAL (size_rtx);
3103 insize = size - left;
3104 gcc_assert (insize > 0);
3105 /* Default to left / right shift. */
3107 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3110 /* 16 bit shift / sign extend / 16 bit shift */
3111 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3112 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3113 below, by alternative 3 or something even better. */
3114 if (cost < best_cost)
3120 /* Try a plain sign extend between two shifts. */
3121 for (ext = 16; ext >= insize; ext -= 8)
3125 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3126 if (cost < best_cost)
3128 kind = ext / (unsigned) 8;
3132 /* Check if we can do a sloppy shift with a final signed shift
3133 restoring the sign. */
3134 if (EXT_SHIFT_SIGNED (size - ext))
3135 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3136 /* If not, maybe it's still cheaper to do the second shift sloppy,
3137 and do a final sign extend? */
3138 else if (size <= 16)
3139 cost = ext_shift_insns[ext - insize] + 1
3140 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3143 if (cost < best_cost)
3145 kind = ext / (unsigned) 8 + 2;
3149 /* Check if we can sign extend in r0 */
3152 cost = 3 + shift_insns[left];
3153 if (cost < best_cost)
3158 /* Try the same with a final signed shift. */
3161 cost = 3 + ext_shift_insns[left + 1] + 1;
3162 if (cost < best_cost)
3171 /* Try to use a dynamic shift. */
3172 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3173 if (cost < best_cost)
3184 /* Function to be used in the length attribute of the instructions
3185 implementing this pattern. */
3188 shl_sext_length (rtx insn)
3190 rtx set_src, left_rtx, size_rtx;
3193 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3194 left_rtx = XEXP (XEXP (set_src, 0), 1);
3195 size_rtx = XEXP (set_src, 1);
3196 shl_sext_kind (left_rtx, size_rtx, &cost);
3200 /* Generate rtl for this pattern */
3203 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3206 int left, size, insize, cost;
3209 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3210 left = INTVAL (left_rtx);
3211 size = INTVAL (size_rtx);
3212 insize = size - left;
3220 int ext = kind & 1 ? 8 : 16;
3221 int shift2 = size - ext;
3223 /* Don't expand fine-grained when combining, because that will
3224 make the pattern fail. */
3225 if (! currently_expanding_to_rtl
3226 && ! reload_in_progress && ! reload_completed)
3228 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3229 emit_insn (gen_movsi (dest, source));
3233 emit_insn (gen_movsi (dest, source));
3237 operands[2] = GEN_INT (ext - insize);
3238 gen_shifty_hi_op (ASHIFT, operands);
3241 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3242 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3247 operands[2] = GEN_INT (shift2);
3248 gen_shifty_op (ASHIFT, operands);
3255 if (EXT_SHIFT_SIGNED (shift2))
3257 operands[2] = GEN_INT (shift2 + 1);
3258 gen_shifty_op (ASHIFT, operands);
3259 operands[2] = const1_rtx;
3260 gen_shifty_op (ASHIFTRT, operands);
3263 operands[2] = GEN_INT (shift2);
3264 gen_shifty_hi_op (ASHIFT, operands);
3268 operands[2] = GEN_INT (-shift2);
3269 gen_shifty_hi_op (LSHIFTRT, operands);
3271 emit_insn (size <= 8
3272 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3273 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3280 if (! currently_expanding_to_rtl
3281 && ! reload_in_progress && ! reload_completed)
3282 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3286 operands[2] = GEN_INT (16 - insize);
3287 gen_shifty_hi_op (ASHIFT, operands);
3288 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3290 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3292 gen_ashift (ASHIFTRT, 1, dest);
3297 /* Don't expand fine-grained when combining, because that will
3298 make the pattern fail. */
3299 if (! currently_expanding_to_rtl
3300 && ! reload_in_progress && ! reload_completed)
3302 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3303 emit_insn (gen_movsi (dest, source));
3306 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3307 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3308 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3310 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3311 gen_shifty_op (ASHIFT, operands);
3313 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3321 /* Prefix a symbol_ref name with "datalabel". */
3324 gen_datalabel_ref (rtx sym)
3328 if (GET_CODE (sym) == LABEL_REF)
3329 return gen_rtx_CONST (GET_MODE (sym),
3330 gen_rtx_UNSPEC (GET_MODE (sym),
3334 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3336 str = XSTR (sym, 0);
3337 /* Share all SYMBOL_REF strings with the same value - that is important
3339 str = IDENTIFIER_POINTER (get_identifier (str));
3340 XSTR (sym, 0) = str;
3346 static alloc_pool label_ref_list_pool;
3348 typedef struct label_ref_list_d
3351 struct label_ref_list_d *next;
3352 } *label_ref_list_t;
3354 /* The SH cannot load a large constant into a register, constants have to
3355 come from a pc relative load. The reference of a pc relative load
3356 instruction must be less than 1k in front of the instruction. This
3357 means that we often have to dump a constant inside a function, and
3358 generate code to branch around it.
3360 It is important to minimize this, since the branches will slow things
3361 down and make things bigger.
3363 Worst case code looks like:
3381 We fix this by performing a scan before scheduling, which notices which
3382 instructions need to have their operands fetched from the constant table
3383 and builds the table.
3387 scan, find an instruction which needs a pcrel move. Look forward, find the
3388 last barrier which is within MAX_COUNT bytes of the requirement.
3389 If there isn't one, make one. Process all the instructions between
3390 the find and the barrier.
3392 In the above example, we can tell that L3 is within 1k of L1, so
3393 the first move can be shrunk from the 3 insn+constant sequence into
3394 just 1 insn, and the constant moved to L3 to make:
3405 Then the second move becomes the target for the shortening process. */
3409 rtx value; /* Value in table. */
3410 rtx label; /* Label of value. */
3411 label_ref_list_t wend; /* End of window. */
3412 enum machine_mode mode; /* Mode of value. */
3414 /* True if this constant is accessed as part of a post-increment
3415 sequence. Note that HImode constants are never accessed in this way. */
3416 bool part_of_sequence_p;
3419 /* The maximum number of constants that can fit into one pool, since
3420 constants in the range 0..510 are at least 2 bytes long, and in the
3421 range from there to 1018 at least 4 bytes. */
3423 #define MAX_POOL_SIZE 372
3424 static pool_node pool_vector[MAX_POOL_SIZE];
3425 static int pool_size;
3426 static rtx pool_window_label;
3427 static int pool_window_last;
3429 static int max_labelno_before_reorg;
3431 /* ??? If we need a constant in HImode which is the truncated value of a
3432 constant we need in SImode, we could combine the two entries thus saving
3433 two bytes. Is this common enough to be worth the effort of implementing
3436 /* ??? This stuff should be done at the same time that we shorten branches.
3437 As it is now, we must assume that all branches are the maximum size, and
3438 this causes us to almost always output constant pools sooner than
3441 /* Add a constant to the pool and return its label. */
3444 add_constant (rtx x, enum machine_mode mode, rtx last_value)
3448 label_ref_list_t ref, newref;
3450 /* First see if we've already got it. */
3451 for (i = 0; i < pool_size; i++)
3453 if (x->code == pool_vector[i].value->code
3454 && mode == pool_vector[i].mode)
3456 if (x->code == CODE_LABEL)
3458 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3461 if (rtx_equal_p (x, pool_vector[i].value))
3466 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3468 new_rtx = gen_label_rtx ();
3469 LABEL_REFS (new_rtx) = pool_vector[i].label;
3470 pool_vector[i].label = lab = new_rtx;
3472 if (lab && pool_window_label)
3474 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3475 newref->label = pool_window_label;
3476 ref = pool_vector[pool_window_last].wend;
3478 pool_vector[pool_window_last].wend = newref;
3481 pool_window_label = new_rtx;
3482 pool_window_last = i;
3488 /* Need a new one. */
3489 pool_vector[pool_size].value = x;
3490 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3493 pool_vector[pool_size - 1].part_of_sequence_p = true;
3496 lab = gen_label_rtx ();
3497 pool_vector[pool_size].mode = mode;
3498 pool_vector[pool_size].label = lab;
3499 pool_vector[pool_size].wend = NULL;
3500 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
3501 if (lab && pool_window_label)
3503 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3504 newref->label = pool_window_label;
3505 ref = pool_vector[pool_window_last].wend;
3507 pool_vector[pool_window_last].wend = newref;
3510 pool_window_label = lab;
3511 pool_window_last = pool_size;
3516 /* Output the literal table. START, if nonzero, is the first instruction
3517 this table is needed for, and also indicates that there is at least one
3518 casesi_worker_2 instruction; We have to emit the operand3 labels from
3519 these insns at a 4-byte aligned position. BARRIER is the barrier
3520 after which we are to place the table. */
3523 dump_table (rtx start, rtx barrier)
3529 label_ref_list_t ref;
3532 /* Do two passes, first time dump out the HI sized constants. */
3534 for (i = 0; i < pool_size; i++)
3536 pool_node *p = &pool_vector[i];
3538 if (p->mode == HImode)
3542 scan = emit_insn_after (gen_align_2 (), scan);
3545 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3546 scan = emit_label_after (lab, scan);
3547 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
3549 for (ref = p->wend; ref; ref = ref->next)
3552 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3555 else if (p->mode == DFmode)
3563 scan = emit_insn_after (gen_align_4 (), scan);
3565 for (; start != barrier; start = NEXT_INSN (start))
3566 if (GET_CODE (start) == INSN
3567 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
3569 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
3570 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
3572 scan = emit_label_after (lab, scan);
3575 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
3577 rtx align_insn = NULL_RTX;
3579 scan = emit_label_after (gen_label_rtx (), scan);
3580 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3583 for (i = 0; i < pool_size; i++)
3585 pool_node *p = &pool_vector[i];
3593 if (align_insn && !p->part_of_sequence_p)
3595 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3596 emit_label_before (lab, align_insn);
3597 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
3599 for (ref = p->wend; ref; ref = ref->next)
3602 emit_insn_before (gen_consttable_window_end (lab),
3605 delete_insn (align_insn);
3606 align_insn = NULL_RTX;
3611 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3612 scan = emit_label_after (lab, scan);
3613 scan = emit_insn_after (gen_consttable_4 (p->value,
3615 need_align = ! need_align;
3621 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3626 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3627 scan = emit_label_after (lab, scan);
3628 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3635 if (p->mode != HImode)
3637 for (ref = p->wend; ref; ref = ref->next)
3640 scan = emit_insn_after (gen_consttable_window_end (lab),
3649 for (i = 0; i < pool_size; i++)
3651 pool_node *p = &pool_vector[i];
3662 scan = emit_label_after (gen_label_rtx (), scan);
3663 scan = emit_insn_after (gen_align_4 (), scan);
3665 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3666 scan = emit_label_after (lab, scan);
3667 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
3675 scan = emit_label_after (gen_label_rtx (), scan);
3676 scan = emit_insn_after (gen_align_4 (), scan);
3678 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3679 scan = emit_label_after (lab, scan);
3680 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3687 if (p->mode != HImode)
3689 for (ref = p->wend; ref; ref = ref->next)
3692 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3697 scan = emit_insn_after (gen_consttable_end (), scan);
3698 scan = emit_barrier_after (scan);
3700 pool_window_label = NULL_RTX;
3701 pool_window_last = 0;
3704 /* Return nonzero if constant would be an ok source for a
3705 mov.w instead of a mov.l. */
3710 return (GET_CODE (src) == CONST_INT
3711 && INTVAL (src) >= -32768
3712 && INTVAL (src) <= 32767);
3715 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
3717 /* Nonzero if the insn is a move instruction which needs to be fixed. */
3719 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
3720 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
3721 need to fix it if the input value is CONST_OK_FOR_I08. */
3724 broken_move (rtx insn)
3726 if (GET_CODE (insn) == INSN)
3728 rtx pat = PATTERN (insn);
3729 if (GET_CODE (pat) == PARALLEL)
3730 pat = XVECEXP (pat, 0, 0);
3731 if (GET_CODE (pat) == SET
3732 /* We can load any 8-bit value if we don't care what the high
3733 order bits end up as. */
3734 && GET_MODE (SET_DEST (pat)) != QImode
3735 && (CONSTANT_P (SET_SRC (pat))
3736 /* Match mova_const. */
3737 || (GET_CODE (SET_SRC (pat)) == UNSPEC
3738 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
3739 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
3741 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
3742 && (fp_zero_operand (SET_SRC (pat))
3743 || fp_one_operand (SET_SRC (pat)))
3744 /* ??? If this is a -m4 or -m4-single compilation, in general
3745 we don't know the current setting of fpscr, so disable fldi.
3746 There is an exception if this was a register-register move
3747 before reload - and hence it was ascertained that we have
3748 single precision setting - and in a post-reload optimization
3749 we changed this to do a constant load. In that case
3750 we don't have an r0 clobber, hence we must use fldi. */
3751 && (! TARGET_SH4 || TARGET_FMOVD
3752 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
3754 && GET_CODE (SET_DEST (pat)) == REG
3755 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
3757 && GET_MODE (SET_DEST (pat)) == SImode
3758 && (satisfies_constraint_I20 (SET_SRC (pat))
3759 || satisfies_constraint_I28 (SET_SRC (pat))))
3760 && ! satisfies_constraint_I08 (SET_SRC (pat)))
3770 return (GET_CODE (insn) == INSN
3771 && GET_CODE (PATTERN (insn)) == SET
3772 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
3773 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
3774 /* Don't match mova_const. */
3775 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
3778 /* Fix up a mova from a switch that went out of range. */
3780 fixup_mova (rtx mova)
3782 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
3785 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
3786 INSN_CODE (mova) = -1;
3791 rtx lab = gen_label_rtx ();
3792 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
3796 worker = NEXT_INSN (worker);
3798 && GET_CODE (worker) != CODE_LABEL
3799 && GET_CODE (worker) != JUMP_INSN);
3800 } while (GET_CODE (worker) == NOTE
3801 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
3802 wpat = PATTERN (worker);
3803 wpat0 = XVECEXP (wpat, 0, 0);
3804 wpat1 = XVECEXP (wpat, 0, 1);
3805 wsrc = SET_SRC (wpat0);
3806 PATTERN (worker) = (gen_casesi_worker_2
3807 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
3808 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
3810 INSN_CODE (worker) = -1;
3811 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3812 base = gen_rtx_LABEL_REF (Pmode, lab);
3813 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
3814 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
3815 INSN_CODE (mova) = -1;
3819 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
3820 *num_mova, and check if the new mova is not nested within the first one.
3821 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
3822 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
3824 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
3826 int n_addr = 0; /* Initialization to shut up spurious warning. */
3827 int f_target, n_target = 0; /* Likewise. */
3831 /* If NEW_MOVA has no address yet, it will be handled later. */
3832 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
3835 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
3836 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
3837 if (n_addr > n_target || n_addr + 1022 < n_target)
3839 /* Change the mova into a load.
3840 broken_move will then return true for it. */
3841 fixup_mova (new_mova);
3847 *first_mova = new_mova;
3852 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
3857 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
3858 > n_target - n_addr)
3860 fixup_mova (*first_mova);
3865 fixup_mova (new_mova);
3870 /* Find the last barrier from insn FROM which is close enough to hold the
3871 constant pool. If we can't find one, then create one near the end of
3875 find_barrier (int num_mova, rtx mova, rtx from)
3884 int leading_mova = num_mova;
3885 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
3890 /* For HImode: range is 510, add 4 because pc counts from address of
3891 second instruction after this one, subtract 2 for the jump instruction
3892 that we may need to emit before the table, subtract 2 for the instruction
3893 that fills the jump delay slot (in very rare cases, reorg will take an
3894 instruction from after the constant pool or will leave the delay slot
3895 empty). This gives 510.
3896 For SImode: range is 1020, add 4 because pc counts from address of
3897 second instruction after this one, subtract 2 in case pc is 2 byte
3898 aligned, subtract 2 for the jump instruction that we may need to emit
3899 before the table, subtract 2 for the instruction that fills the jump
3900 delay slot. This gives 1018. */
3902 /* The branch will always be shortened now that the reference address for
3903 forward branches is the successor address, thus we need no longer make
3904 adjustments to the [sh]i_limit for -O0. */
3909 while (from && count_si < si_limit && count_hi < hi_limit)
3911 int inc = get_attr_length (from);
3914 /* If this is a label that existed at the time of the compute_alignments
3915 call, determine the alignment. N.B. When find_barrier recurses for
3916 an out-of-reach mova, we might see labels at the start of previously
3917 inserted constant tables. */
3918 if (GET_CODE (from) == CODE_LABEL
3919 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
3922 new_align = 1 << label_to_alignment (from);
3923 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
3924 new_align = 1 << barrier_align (from);
3929 /* In case we are scanning a constant table because of recursion, check
3930 for explicit alignments. If the table is long, we might be forced
3931 to emit the new table in front of it; the length of the alignment
3932 might be the last straw. */
3933 else if (GET_CODE (from) == INSN
3934 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
3935 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
3936 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
3937 /* When we find the end of a constant table, paste the new constant
3938 at the end. That is better than putting it in front because
3939 this way, we don't need extra alignment for adding a 4-byte-aligned
3940 mov(a) label to a 2/4 or 8/4 byte aligned table. */
3941 else if (GET_CODE (from) == INSN
3942 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
3943 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
3946 if (GET_CODE (from) == BARRIER)
3950 found_barrier = from;
3952 /* If we are at the end of the function, or in front of an alignment
3953 instruction, we need not insert an extra alignment. We prefer
3954 this kind of barrier. */
3955 if (barrier_align (from) > 2)
3956 good_barrier = from;
3958 /* If we are at the end of a hot/cold block, dump the constants
3960 next = NEXT_INSN (from);
3963 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
3967 if (broken_move (from))
3970 enum machine_mode mode;
3972 pat = PATTERN (from);
3973 if (GET_CODE (pat) == PARALLEL)
3974 pat = XVECEXP (pat, 0, 0);
3975 src = SET_SRC (pat);
3976 dst = SET_DEST (pat);
3977 mode = GET_MODE (dst);
3979 /* We must explicitly check the mode, because sometimes the
3980 front end will generate code to load unsigned constants into
3981 HImode targets without properly sign extending them. */
3983 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
3986 /* We put the short constants before the long constants, so
3987 we must count the length of short constants in the range
3988 for the long constants. */
3989 /* ??? This isn't optimal, but is easy to do. */
3994 /* We dump DF/DI constants before SF/SI ones, because
3995 the limit is the same, but the alignment requirements
3996 are higher. We may waste up to 4 additional bytes
3997 for alignment, and the DF/DI constant may have
3998 another SF/SI constant placed before it. */
3999 if (TARGET_SHCOMPACT
4001 && (mode == DFmode || mode == DImode))
4006 while (si_align > 2 && found_si + si_align - 2 > count_si)
4008 if (found_si > count_si)
4009 count_si = found_si;
4010 found_si += GET_MODE_SIZE (mode);
4012 si_limit -= GET_MODE_SIZE (mode);
4018 switch (untangle_mova (&num_mova, &mova, from))
4020 case 0: return find_barrier (0, 0, mova);
4025 = good_barrier ? good_barrier : found_barrier;
4029 if (found_si > count_si)
4030 count_si = found_si;
4032 else if (GET_CODE (from) == JUMP_INSN
4033 && (GET_CODE (PATTERN (from)) == ADDR_VEC
4034 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
4036 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4038 && (prev_nonnote_insn (from)
4039 == XEXP (MOVA_LABELREF (mova), 0))))
4041 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4043 /* We have just passed the barrier in front of the
4044 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4045 the ADDR_DIFF_VEC is accessed as data, just like our pool
4046 constants, this is a good opportunity to accommodate what
4047 we have gathered so far.
4048 If we waited any longer, we could end up at a barrier in
4049 front of code, which gives worse cache usage for separated
4050 instruction / data caches. */
4051 good_barrier = found_barrier;
4056 rtx body = PATTERN (from);
4057 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4060 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4061 else if (GET_CODE (from) == JUMP_INSN
4063 && ! TARGET_SMALLCODE)
4069 if (new_align > si_align)
4071 si_limit -= (count_si - 1) & (new_align - si_align);
4072 si_align = new_align;
4074 count_si = (count_si + new_align - 1) & -new_align;
4079 if (new_align > hi_align)
4081 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4082 hi_align = new_align;
4084 count_hi = (count_hi + new_align - 1) & -new_align;
4086 from = NEXT_INSN (from);
4093 /* Try as we might, the leading mova is out of range. Change
4094 it into a load (which will become a pcload) and retry. */
4096 return find_barrier (0, 0, mova);
4100 /* Insert the constant pool table before the mova instruction,
4101 to prevent the mova label reference from going out of range. */
4103 good_barrier = found_barrier = barrier_before_mova;
4109 if (good_barrier && next_real_insn (found_barrier))
4110 found_barrier = good_barrier;
4114 /* We didn't find a barrier in time to dump our stuff,
4115 so we'll make one. */
4116 rtx label = gen_label_rtx ();
4118 /* If we exceeded the range, then we must back up over the last
4119 instruction we looked at. Otherwise, we just need to undo the
4120 NEXT_INSN at the end of the loop. */
4121 if (PREV_INSN (from) != orig
4122 && (count_hi > hi_limit || count_si > si_limit))
4123 from = PREV_INSN (PREV_INSN (from));
4125 from = PREV_INSN (from);
4127 /* Walk back to be just before any jump or label.
4128 Putting it before a label reduces the number of times the branch
4129 around the constant pool table will be hit. Putting it before
4130 a jump makes it more likely that the bra delay slot will be
4132 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
4133 || GET_CODE (from) == CODE_LABEL)
4134 from = PREV_INSN (from);
4136 from = emit_jump_insn_after (gen_jump (label), from);
4137 JUMP_LABEL (from) = label;
4138 LABEL_NUSES (label) = 1;
4139 found_barrier = emit_barrier_after (from);
4140 emit_label_after (label, found_barrier);
4143 return found_barrier;
4146 /* If the instruction INSN is implemented by a special function, and we can
4147 positively find the register that is used to call the sfunc, and this
4148 register is not used anywhere else in this instruction - except as the
4149 destination of a set, return this register; else, return 0. */
4151 sfunc_uses_reg (rtx insn)
4154 rtx pattern, part, reg_part, reg;
4156 if (GET_CODE (insn) != INSN)
4158 pattern = PATTERN (insn);
4159 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4162 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4164 part = XVECEXP (pattern, 0, i);
4165 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4170 reg = XEXP (reg_part, 0);
4171 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4173 part = XVECEXP (pattern, 0, i);
4174 if (part == reg_part || GET_CODE (part) == CLOBBER)
4176 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4177 && GET_CODE (SET_DEST (part)) == REG)
4178 ? SET_SRC (part) : part)))
4184 /* See if the only way in which INSN uses REG is by calling it, or by
4185 setting it while calling it. Set *SET to a SET rtx if the register
4189 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4195 reg2 = sfunc_uses_reg (insn);
4196 if (reg2 && REGNO (reg2) == REGNO (reg))
4198 pattern = single_set (insn);
4200 && GET_CODE (SET_DEST (pattern)) == REG
4201 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4205 if (GET_CODE (insn) != CALL_INSN)
4207 /* We don't use rtx_equal_p because we don't care if the mode is
4209 pattern = single_set (insn);
4211 && GET_CODE (SET_DEST (pattern)) == REG
4212 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4218 par = PATTERN (insn);
4219 if (GET_CODE (par) == PARALLEL)
4220 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4222 part = XVECEXP (par, 0, i);
4223 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4226 return reg_mentioned_p (reg, SET_SRC (pattern));
4232 pattern = PATTERN (insn);
4234 if (GET_CODE (pattern) == PARALLEL)
4238 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4239 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4241 pattern = XVECEXP (pattern, 0, 0);
4244 if (GET_CODE (pattern) == SET)
4246 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4248 /* We don't use rtx_equal_p, because we don't care if the
4249 mode is different. */
4250 if (GET_CODE (SET_DEST (pattern)) != REG
4251 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4257 pattern = SET_SRC (pattern);
4260 if (GET_CODE (pattern) != CALL
4261 || GET_CODE (XEXP (pattern, 0)) != MEM
4262 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4268 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4269 general registers. Bits 0..15 mean that the respective registers
4270 are used as inputs in the instruction. Bits 16..31 mean that the
4271 registers 0..15, respectively, are used as outputs, or are clobbered.
4272 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4274 regs_used (rtx x, int is_dest)
4282 code = GET_CODE (x);
4287 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4288 << (REGNO (x) + is_dest));
4292 rtx y = SUBREG_REG (x);
4294 if (GET_CODE (y) != REG)
4297 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4299 subreg_regno_offset (REGNO (y),
4302 GET_MODE (x)) + is_dest));
4306 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4308 /* If there was a return value, it must have been indicated with USE. */
4323 fmt = GET_RTX_FORMAT (code);
4325 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4330 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4331 used |= regs_used (XVECEXP (x, i, j), is_dest);
4333 else if (fmt[i] == 'e')
4334 used |= regs_used (XEXP (x, i), is_dest);
4339 /* Create an instruction that prevents redirection of a conditional branch
4340 to the destination of the JUMP with address ADDR.
4341 If the branch needs to be implemented as an indirect jump, try to find
4342 a scratch register for it.
4343 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4344 If any preceding insn that doesn't fit into a delay slot is good enough,
4345 pass 1. Pass 2 if a definite blocking insn is needed.
4346 -1 is used internally to avoid deep recursion.
4347 If a blocking instruction is made or recognized, return it. */
4350 gen_block_redirect (rtx jump, int addr, int need_block)
4353 rtx prev = prev_nonnote_insn (jump);
4356 /* First, check if we already have an instruction that satisfies our need. */
4357 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
4359 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4361 if (GET_CODE (PATTERN (prev)) == USE
4362 || GET_CODE (PATTERN (prev)) == CLOBBER
4363 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4365 else if ((need_block &= ~1) < 0)
4367 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4370 if (GET_CODE (PATTERN (jump)) == RETURN)
4374 /* Reorg even does nasty things with return insns that cause branches
4375 to go out of range - see find_end_label and callers. */
4376 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4378 /* We can't use JUMP_LABEL here because it might be undefined
4379 when not optimizing. */
4380 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4381 /* If the branch is out of range, try to find a scratch register for it. */
4383 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4387 /* Don't look for the stack pointer as a scratch register,
4388 it would cause trouble if an interrupt occurred. */
4389 unsigned attempt = 0x7fff, used;
4390 int jump_left = flag_expensive_optimizations + 1;
4392 /* It is likely that the most recent eligible instruction is wanted for
4393 the delay slot. Therefore, find out which registers it uses, and
4394 try to avoid using them. */
4396 for (scan = jump; (scan = PREV_INSN (scan)); )
4400 if (INSN_DELETED_P (scan))
4402 code = GET_CODE (scan);
4403 if (code == CODE_LABEL || code == JUMP_INSN)
4406 && GET_CODE (PATTERN (scan)) != USE
4407 && GET_CODE (PATTERN (scan)) != CLOBBER
4408 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4410 attempt &= ~regs_used (PATTERN (scan), 0);
4414 for (used = dead = 0, scan = JUMP_LABEL (jump);
4415 (scan = NEXT_INSN (scan)); )
4419 if (INSN_DELETED_P (scan))
4421 code = GET_CODE (scan);
4424 used |= regs_used (PATTERN (scan), 0);
4425 if (code == CALL_INSN)
4426 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4427 dead |= (used >> 16) & ~used;
4433 if (code == JUMP_INSN)
4435 if (jump_left-- && simplejump_p (scan))
4436 scan = JUMP_LABEL (scan);
4442 /* Mask out the stack pointer again, in case it was
4443 the only 'free' register we have found. */
4446 /* If the immediate destination is still in range, check for possible
4447 threading with a jump beyond the delay slot insn.
4448 Don't check if we are called recursively; the jump has been or will be
4449 checked in a different invocation then. */
4451 else if (optimize && need_block >= 0)
4453 rtx next = next_active_insn (next_active_insn (dest));
4454 if (next && GET_CODE (next) == JUMP_INSN
4455 && GET_CODE (PATTERN (next)) == SET
4456 && recog_memoized (next) == CODE_FOR_jump_compact)
4458 dest = JUMP_LABEL (next);
4460 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4462 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
4468 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
4470 /* It would be nice if we could convert the jump into an indirect
4471 jump / far branch right now, and thus exposing all constituent
4472 instructions to further optimization. However, reorg uses
4473 simplejump_p to determine if there is an unconditional jump where
4474 it should try to schedule instructions from the target of the
4475 branch; simplejump_p fails for indirect jumps even if they have
4477 rtx insn = emit_insn_before (gen_indirect_jump_scratch
4478 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
4480 /* ??? We would like this to have the scope of the jump, but that
4481 scope will change when a delay slot insn of an inner scope is added.
4482 Hence, after delay slot scheduling, we'll have to expect
4483 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
4486 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
4487 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
4490 else if (need_block)
4491 /* We can't use JUMP_LABEL here because it might be undefined
4492 when not optimizing. */
4493 return emit_insn_before (gen_block_branch_redirect
4494 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
4499 #define CONDJUMP_MIN -252
4500 #define CONDJUMP_MAX 262
4503 /* A label (to be placed) in front of the jump
4504 that jumps to our ultimate destination. */
4506 /* Where we are going to insert it if we cannot move the jump any farther,
4507 or the jump itself if we have picked up an existing jump. */
4509 /* The ultimate destination. */
4511 struct far_branch *prev;
4512 /* If the branch has already been created, its address;
4513 else the address of its first prospective user. */
4517 static void gen_far_branch (struct far_branch *);
4518 enum mdep_reorg_phase_e mdep_reorg_phase;
4520 gen_far_branch (struct far_branch *bp)
4522 rtx insn = bp->insert_place;
4524 rtx label = gen_label_rtx ();
4527 emit_label_after (label, insn);
4530 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
4531 LABEL_NUSES (bp->far_label)++;
4534 jump = emit_jump_insn_after (gen_return (), insn);
4535 /* Emit a barrier so that reorg knows that any following instructions
4536 are not reachable via a fall-through path.
4537 But don't do this when not optimizing, since we wouldn't suppress the
4538 alignment for the barrier then, and could end up with out-of-range
4539 pc-relative loads. */
4541 emit_barrier_after (jump);
4542 emit_label_after (bp->near_label, insn);
4543 JUMP_LABEL (jump) = bp->far_label;
4544 ok = invert_jump (insn, label, 1);
4547 /* If we are branching around a jump (rather than a return), prevent
4548 reorg from using an insn from the jump target as the delay slot insn -
4549 when reorg did this, it pessimized code (we rather hide the delay slot)
4550 and it could cause branches to go out of range. */
4553 (gen_stuff_delay_slot
4554 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
4555 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
4557 /* Prevent reorg from undoing our splits. */
4558 gen_block_redirect (jump, bp->address += 2, 2);
4561 /* Fix up ADDR_DIFF_VECs. */
4563 fixup_addr_diff_vecs (rtx first)
4567 for (insn = first; insn; insn = NEXT_INSN (insn))
4569 rtx vec_lab, pat, prev, prevpat, x, braf_label;
4571 if (GET_CODE (insn) != JUMP_INSN
4572 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
4574 pat = PATTERN (insn);
4575 vec_lab = XEXP (XEXP (pat, 0), 0);
4577 /* Search the matching casesi_jump_2. */
4578 for (prev = vec_lab; ; prev = PREV_INSN (prev))
4580 if (GET_CODE (prev) != JUMP_INSN)
4582 prevpat = PATTERN (prev);
4583 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
4585 x = XVECEXP (prevpat, 0, 1);
4586 if (GET_CODE (x) != USE)
4589 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
4592 /* FIXME: This is a bug in the optimizer, but it seems harmless
4593 to just avoid panicing. */
4597 /* Emit the reference label of the braf where it belongs, right after
4598 the casesi_jump_2 (i.e. braf). */
4599 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
4600 emit_label_after (braf_label, prev);
4602 /* Fix up the ADDR_DIF_VEC to be relative
4603 to the reference address of the braf. */
4604 XEXP (XEXP (pat, 0), 0) = braf_label;
4608 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
4609 a barrier. Return the base 2 logarithm of the desired alignment. */
4611 barrier_align (rtx barrier_or_label)
4613 rtx next = next_real_insn (barrier_or_label), pat, prev;
4614 int slot, credit, jump_to_next = 0;
4619 pat = PATTERN (next);
4621 if (GET_CODE (pat) == ADDR_DIFF_VEC)
4624 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
4625 /* This is a barrier in front of a constant table. */
4628 prev = prev_real_insn (barrier_or_label);
4629 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
4631 pat = PATTERN (prev);
4632 /* If this is a very small table, we want to keep the alignment after
4633 the table to the minimum for proper code alignment. */
4634 return ((TARGET_SMALLCODE
4635 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
4636 <= (unsigned) 1 << (CACHE_LOG - 2)))
4637 ? 1 << TARGET_SHMEDIA : align_jumps_log);
4640 if (TARGET_SMALLCODE)
4643 if (! TARGET_SH2 || ! optimize)
4644 return align_jumps_log;
4646 /* When fixing up pcloads, a constant table might be inserted just before
4647 the basic block that ends with the barrier. Thus, we can't trust the
4648 instruction lengths before that. */
4649 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
4651 /* Check if there is an immediately preceding branch to the insn beyond
4652 the barrier. We must weight the cost of discarding useful information
4653 from the current cache line when executing this branch and there is
4654 an alignment, against that of fetching unneeded insn in front of the
4655 branch target when there is no alignment. */
4657 /* There are two delay_slot cases to consider. One is the simple case
4658 where the preceding branch is to the insn beyond the barrier (simple
4659 delay slot filling), and the other is where the preceding branch has
4660 a delay slot that is a duplicate of the insn after the barrier
4661 (fill_eager_delay_slots) and the branch is to the insn after the insn
4662 after the barrier. */
4664 /* PREV is presumed to be the JUMP_INSN for the barrier under
4665 investigation. Skip to the insn before it. */
4666 prev = prev_real_insn (prev);
4668 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
4669 credit >= 0 && prev && GET_CODE (prev) == INSN;
4670 prev = prev_real_insn (prev))
4673 if (GET_CODE (PATTERN (prev)) == USE
4674 || GET_CODE (PATTERN (prev)) == CLOBBER)
4676 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
4678 prev = XVECEXP (PATTERN (prev), 0, 1);
4679 if (INSN_UID (prev) == INSN_UID (next))
4681 /* Delay slot was filled with insn at jump target. */
4688 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4690 credit -= get_attr_length (prev);
4693 && GET_CODE (prev) == JUMP_INSN
4694 && JUMP_LABEL (prev))
4698 || next_real_insn (JUMP_LABEL (prev)) == next
4699 /* If relax_delay_slots() decides NEXT was redundant
4700 with some previous instruction, it will have
4701 redirected PREV's jump to the following insn. */
4702 || JUMP_LABEL (prev) == next_nonnote_insn (next)
4703 /* There is no upper bound on redundant instructions
4704 that might have been skipped, but we must not put an
4705 alignment where none had been before. */
4706 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
4708 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
4709 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
4710 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
4712 rtx pat = PATTERN (prev);
4713 if (GET_CODE (pat) == PARALLEL)
4714 pat = XVECEXP (pat, 0, 0);
4715 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
4721 return align_jumps_log;
4724 /* If we are inside a phony loop, almost any kind of label can turn up as the
4725 first one in the loop. Aligning a braf label causes incorrect switch
4726 destination addresses; we can detect braf labels because they are
4727 followed by a BARRIER.
4728 Applying loop alignment to small constant or switch tables is a waste
4729 of space, so we suppress this too. */
4731 sh_loop_align (rtx label)
4736 next = next_nonnote_insn (next);
4737 while (next && GET_CODE (next) == CODE_LABEL);
4741 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
4742 || recog_memoized (next) == CODE_FOR_consttable_2)
4745 return align_loops_log;
4748 /* Do a final pass over the function, just before delayed branch
4754 rtx first, insn, mova = NULL_RTX;
4756 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
4757 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
4759 first = get_insns ();
4760 max_labelno_before_reorg = max_label_num ();
4762 /* We must split call insns before introducing `mova's. If we're
4763 optimizing, they'll have already been split. Otherwise, make
4764 sure we don't split them too late. */
4766 split_all_insns_noflow ();
4771 /* If relaxing, generate pseudo-ops to associate function calls with
4772 the symbols they call. It does no harm to not generate these
4773 pseudo-ops. However, when we can generate them, it enables to
4774 linker to potentially relax the jsr to a bsr, and eliminate the
4775 register load and, possibly, the constant pool entry. */
4777 mdep_reorg_phase = SH_INSERT_USES_LABELS;
4780 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
4781 own purposes. This works because none of the remaining passes
4782 need to look at them.
4784 ??? But it may break in the future. We should use a machine
4785 dependent REG_NOTE, or some other approach entirely. */
4786 for (insn = first; insn; insn = NEXT_INSN (insn))
4792 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
4794 remove_note (insn, note);
4798 for (insn = first; insn; insn = NEXT_INSN (insn))
4800 rtx pattern, reg, link, set, scan, dies, label;
4801 int rescan = 0, foundinsn = 0;
4803 if (GET_CODE (insn) == CALL_INSN)
4805 pattern = PATTERN (insn);
4807 if (GET_CODE (pattern) == PARALLEL)
4808 pattern = XVECEXP (pattern, 0, 0);
4809 if (GET_CODE (pattern) == SET)
4810 pattern = SET_SRC (pattern);
4812 if (GET_CODE (pattern) != CALL
4813 || GET_CODE (XEXP (pattern, 0)) != MEM)
4816 reg = XEXP (XEXP (pattern, 0), 0);
4820 reg = sfunc_uses_reg (insn);
4825 if (GET_CODE (reg) != REG)
4828 /* Try scanning backward to find where the register is set. */
4830 for (scan = PREV_INSN (insn);
4831 scan && GET_CODE (scan) != CODE_LABEL;
4832 scan = PREV_INSN (scan))
4834 if (! INSN_P (scan))
4837 if (! reg_mentioned_p (reg, scan))
4840 if (noncall_uses_reg (reg, scan, &set))
4853 /* The register is set at LINK. */
4855 /* We can only optimize the function call if the register is
4856 being set to a symbol. In theory, we could sometimes
4857 optimize calls to a constant location, but the assembler
4858 and linker do not support that at present. */
4859 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
4860 && GET_CODE (SET_SRC (set)) != LABEL_REF)
4863 /* Scan forward from LINK to the place where REG dies, and
4864 make sure that the only insns which use REG are
4865 themselves function calls. */
4867 /* ??? This doesn't work for call targets that were allocated
4868 by reload, since there may not be a REG_DEAD note for the
4872 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
4876 /* Don't try to trace forward past a CODE_LABEL if we haven't
4877 seen INSN yet. Ordinarily, we will only find the setting insn
4878 if it is in the same basic block. However,
4879 cross-jumping can insert code labels in between the load and
4880 the call, and can result in situations where a single call
4881 insn may have two targets depending on where we came from. */
4883 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
4886 if (! INSN_P (scan))
4889 /* Don't try to trace forward past a JUMP. To optimize
4890 safely, we would have to check that all the
4891 instructions at the jump destination did not use REG. */
4893 if (GET_CODE (scan) == JUMP_INSN)
4896 if (! reg_mentioned_p (reg, scan))
4899 if (noncall_uses_reg (reg, scan, &scanset))
4906 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
4908 /* There is a function call to this register other
4909 than the one we are checking. If we optimize
4910 this call, we need to rescan again below. */
4914 /* ??? We shouldn't have to worry about SCANSET here.
4915 We should just be able to check for a REG_DEAD note
4916 on a function call. However, the REG_DEAD notes are
4917 apparently not dependable around libcalls; c-torture
4918 execute/920501-2 is a test case. If SCANSET is set,
4919 then this insn sets the register, so it must have
4920 died earlier. Unfortunately, this will only handle
4921 the cases in which the register is, in fact, set in a
4924 /* ??? We shouldn't have to use FOUNDINSN here.
4925 This dates back to when we used LOG_LINKS to find
4926 the most recent insn which sets the register. */
4930 || find_reg_note (scan, REG_DEAD, reg)))
4939 /* Either there was a branch, or some insn used REG
4940 other than as a function call address. */
4944 /* Create a code label, and put it in a REG_LABEL_OPERAND note
4945 on the insn which sets the register, and on each call insn
4946 which uses the register. In final_prescan_insn we look for
4947 the REG_LABEL_OPERAND notes, and output the appropriate label
4950 label = gen_label_rtx ();
4951 add_reg_note (link, REG_LABEL_OPERAND, label);
4952 add_reg_note (insn, REG_LABEL_OPERAND, label);
4960 scan = NEXT_INSN (scan);
4962 && ((GET_CODE (scan) == CALL_INSN
4963 && reg_mentioned_p (reg, scan))
4964 || ((reg2 = sfunc_uses_reg (scan))
4965 && REGNO (reg2) == REGNO (reg))))
4966 add_reg_note (scan, REG_LABEL_OPERAND, label);
4968 while (scan != dies);
4974 fixup_addr_diff_vecs (first);
4978 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
4979 shorten_branches (first);
4982 /* Scan the function looking for move instructions which have to be
4983 changed to pc-relative loads and insert the literal tables. */
4984 label_ref_list_pool = create_alloc_pool ("label references list",
4985 sizeof (struct label_ref_list_d),
4987 mdep_reorg_phase = SH_FIXUP_PCLOAD;
4988 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
4992 /* ??? basic block reordering can move a switch table dispatch
4993 below the switch table. Check if that has happened.
4994 We only have the addresses available when optimizing; but then,
4995 this check shouldn't be needed when not optimizing. */
4996 if (!untangle_mova (&num_mova, &mova, insn))
5002 else if (GET_CODE (insn) == JUMP_INSN
5003 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5005 /* ??? loop invariant motion can also move a mova out of a
5006 loop. Since loop does this code motion anyway, maybe we
5007 should wrap UNSPEC_MOVA into a CONST, so that reload can
5010 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5011 || (prev_nonnote_insn (insn)
5012 == XEXP (MOVA_LABELREF (mova), 0))))
5019 /* Some code might have been inserted between the mova and
5020 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5021 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5022 total += get_attr_length (scan);
5024 /* range of mova is 1020, add 4 because pc counts from address of
5025 second instruction after this one, subtract 2 in case pc is 2
5026 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5027 cancels out with alignment effects of the mova itself. */
5030 /* Change the mova into a load, and restart scanning
5031 there. broken_move will then return true for mova. */
5036 if (broken_move (insn)
5037 || (GET_CODE (insn) == INSN
5038 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5041 /* Scan ahead looking for a barrier to stick the constant table
5043 rtx barrier = find_barrier (num_mova, mova, insn);
5044 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5045 int need_aligned_label = 0;
5047 if (num_mova && ! mova_p (mova))
5049 /* find_barrier had to change the first mova into a
5050 pcload; thus, we have to start with this new pcload. */
5054 /* Now find all the moves between the points and modify them. */
5055 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5057 if (GET_CODE (scan) == CODE_LABEL)
5059 if (GET_CODE (scan) == INSN
5060 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5061 need_aligned_label = 1;
5062 if (broken_move (scan))
5064 rtx *patp = &PATTERN (scan), pat = *patp;
5068 enum machine_mode mode;
5070 if (GET_CODE (pat) == PARALLEL)
5071 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5072 src = SET_SRC (pat);
5073 dst = SET_DEST (pat);
5074 mode = GET_MODE (dst);
5076 if (mode == SImode && hi_const (src)
5077 && REGNO (dst) != FPUL_REG)
5082 while (GET_CODE (dst) == SUBREG)
5084 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5085 GET_MODE (SUBREG_REG (dst)),
5088 dst = SUBREG_REG (dst);
5090 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5092 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
5094 /* This must be an insn that clobbers r0. */
5095 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5096 XVECLEN (PATTERN (scan), 0)
5098 rtx clobber = *clobberp;
5100 gcc_assert (GET_CODE (clobber) == CLOBBER
5101 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5104 && reg_set_between_p (r0_rtx, last_float_move, scan))
5108 && GET_MODE_SIZE (mode) != 4
5109 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5111 lab = add_constant (src, mode, last_float);
5113 emit_insn_before (gen_mova (lab), scan);
5116 /* There will be a REG_UNUSED note for r0 on
5117 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5118 lest reorg:mark_target_live_regs will not
5119 consider r0 to be used, and we end up with delay
5120 slot insn in front of SCAN that clobbers r0. */
5122 = find_regno_note (last_float_move, REG_UNUSED, 0);
5124 /* If we are not optimizing, then there may not be
5127 PUT_MODE (note, REG_INC);
5129 *last_float_addr = r0_inc_rtx;
5131 last_float_move = scan;
5133 newsrc = gen_const_mem (mode,
5134 (((TARGET_SH4 && ! TARGET_FMOVD)
5135 || REGNO (dst) == FPUL_REG)
5138 last_float_addr = &XEXP (newsrc, 0);
5140 /* Remove the clobber of r0. */
5141 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5142 gen_rtx_SCRATCH (Pmode));
5144 /* This is a mova needing a label. Create it. */
5145 else if (GET_CODE (src) == UNSPEC
5146 && XINT (src, 1) == UNSPEC_MOVA
5147 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5149 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5150 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5151 newsrc = gen_rtx_UNSPEC (SImode,
5152 gen_rtvec (1, newsrc),
5157 lab = add_constant (src, mode, 0);
5158 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5159 newsrc = gen_const_mem (mode, newsrc);
5161 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5162 INSN_CODE (scan) = -1;
5165 dump_table (need_aligned_label ? insn : 0, barrier);
5169 free_alloc_pool (label_ref_list_pool);
5170 for (insn = first; insn; insn = NEXT_INSN (insn))
5171 PUT_MODE (insn, VOIDmode);
5173 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5174 INSN_ADDRESSES_FREE ();
5175 split_branches (first);
5177 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5178 also has an effect on the register that holds the address of the sfunc.
5179 Insert an extra dummy insn in front of each sfunc that pretends to
5180 use this register. */
5181 if (flag_delayed_branch)
5183 for (insn = first; insn; insn = NEXT_INSN (insn))
5185 rtx reg = sfunc_uses_reg (insn);
5189 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5193 /* fpscr is not actually a user variable, but we pretend it is for the
5194 sake of the previous optimization passes, since we want it handled like
5195 one. However, we don't have any debugging information for it, so turn
5196 it into a non-user variable now. */
5198 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5200 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5204 get_dest_uid (rtx label, int max_uid)
5206 rtx dest = next_real_insn (label);
5209 /* This can happen for an undefined label. */
5211 dest_uid = INSN_UID (dest);
5212 /* If this is a newly created branch redirection blocking instruction,
5213 we cannot index the branch_uid or insn_addresses arrays with its
5214 uid. But then, we won't need to, because the actual destination is
5215 the following branch. */
5216 while (dest_uid >= max_uid)
5218 dest = NEXT_INSN (dest);
5219 dest_uid = INSN_UID (dest);
5221 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
5226 /* Split condbranches that are out of range. Also add clobbers for
5227 scratch registers that are needed in far jumps.
5228 We do this before delay slot scheduling, so that it can take our
5229 newly created instructions into account. It also allows us to
5230 find branches with common targets more easily. */
5233 split_branches (rtx first)
5236 struct far_branch **uid_branch, *far_branch_list = 0;
5237 int max_uid = get_max_uid ();
5240 /* Find out which branches are out of range. */
5241 shorten_branches (first);
5243 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5244 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5246 for (insn = first; insn; insn = NEXT_INSN (insn))
5247 if (! INSN_P (insn))
5249 else if (INSN_DELETED_P (insn))
5251 /* Shorten_branches would split this instruction again,
5252 so transform it into a note. */
5253 SET_INSN_DELETED (insn);
5255 else if (GET_CODE (insn) == JUMP_INSN
5256 /* Don't mess with ADDR_DIFF_VEC */
5257 && (GET_CODE (PATTERN (insn)) == SET
5258 || GET_CODE (PATTERN (insn)) == RETURN))
5260 enum attr_type type = get_attr_type (insn);
5261 if (type == TYPE_CBRANCH)
5265 if (get_attr_length (insn) > 4)
5267 rtx src = SET_SRC (PATTERN (insn));
5268 rtx olabel = XEXP (XEXP (src, 1), 0);
5269 int addr = INSN_ADDRESSES (INSN_UID (insn));
5271 int dest_uid = get_dest_uid (olabel, max_uid);
5272 struct far_branch *bp = uid_branch[dest_uid];
5274 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5275 the label if the LABEL_NUSES count drops to zero. There is
5276 always a jump_optimize pass that sets these values, but it
5277 proceeds to delete unreferenced code, and then if not
5278 optimizing, to un-delete the deleted instructions, thus
5279 leaving labels with too low uses counts. */
5282 JUMP_LABEL (insn) = olabel;
5283 LABEL_NUSES (olabel)++;
5287 bp = (struct far_branch *) alloca (sizeof *bp);
5288 uid_branch[dest_uid] = bp;
5289 bp->prev = far_branch_list;
5290 far_branch_list = bp;
5292 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5293 LABEL_NUSES (bp->far_label)++;
5297 label = bp->near_label;
5298 if (! label && bp->address - addr >= CONDJUMP_MIN)
5300 rtx block = bp->insert_place;
5302 if (GET_CODE (PATTERN (block)) == RETURN)
5303 block = PREV_INSN (block);
5305 block = gen_block_redirect (block,
5307 label = emit_label_after (gen_label_rtx (),
5309 bp->near_label = label;
5311 else if (label && ! NEXT_INSN (label))
5313 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5314 bp->insert_place = insn;
5316 gen_far_branch (bp);
5320 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5322 bp->near_label = label = gen_label_rtx ();
5323 bp->insert_place = insn;
5326 ok = redirect_jump (insn, label, 0);
5331 /* get_attr_length (insn) == 2 */
5332 /* Check if we have a pattern where reorg wants to redirect
5333 the branch to a label from an unconditional branch that
5335 /* We can't use JUMP_LABEL here because it might be undefined
5336 when not optimizing. */
5337 /* A syntax error might cause beyond to be NULL_RTX. */
5339 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5343 && (GET_CODE (beyond) == JUMP_INSN
5344 || ((beyond = next_active_insn (beyond))
5345 && GET_CODE (beyond) == JUMP_INSN))
5346 && GET_CODE (PATTERN (beyond)) == SET
5347 && recog_memoized (beyond) == CODE_FOR_jump_compact
5349 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5350 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5352 gen_block_redirect (beyond,
5353 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5356 next = next_active_insn (insn);
5358 if ((GET_CODE (next) == JUMP_INSN
5359 || ((next = next_active_insn (next))
5360 && GET_CODE (next) == JUMP_INSN))
5361 && GET_CODE (PATTERN (next)) == SET
5362 && recog_memoized (next) == CODE_FOR_jump_compact
5364 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5365 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5367 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5369 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5371 int addr = INSN_ADDRESSES (INSN_UID (insn));
5374 struct far_branch *bp;
5376 if (type == TYPE_JUMP)
5378 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5379 dest_uid = get_dest_uid (far_label, max_uid);
5382 /* Parse errors can lead to labels outside
5384 if (! NEXT_INSN (far_label))
5389 JUMP_LABEL (insn) = far_label;
5390 LABEL_NUSES (far_label)++;
5392 redirect_jump (insn, NULL_RTX, 1);
5396 bp = uid_branch[dest_uid];
5399 bp = (struct far_branch *) alloca (sizeof *bp);
5400 uid_branch[dest_uid] = bp;
5401 bp->prev = far_branch_list;
5402 far_branch_list = bp;
5404 bp->far_label = far_label;
5406 LABEL_NUSES (far_label)++;
5408 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5409 if (addr - bp->address <= CONDJUMP_MAX)
5410 emit_label_after (bp->near_label, PREV_INSN (insn));
5413 gen_far_branch (bp);
5419 bp->insert_place = insn;
5421 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5423 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5426 /* Generate all pending far branches,
5427 and free our references to the far labels. */
5428 while (far_branch_list)
5430 if (far_branch_list->near_label
5431 && ! NEXT_INSN (far_branch_list->near_label))
5432 gen_far_branch (far_branch_list);
5434 && far_branch_list->far_label
5435 && ! --LABEL_NUSES (far_branch_list->far_label))
5436 delete_insn (far_branch_list->far_label);
5437 far_branch_list = far_branch_list->prev;
5440 /* Instruction length information is no longer valid due to the new
5441 instructions that have been generated. */
5442 init_insn_lengths ();
5445 /* Dump out instruction addresses, which is useful for debugging the
5446 constant pool table stuff.
5448 If relaxing, output the label and pseudo-ops used to link together
5449 calls and the instruction which set the registers. */
5451 /* ??? The addresses printed by this routine for insns are nonsense for
5452 insns which are inside of a sequence where none of the inner insns have
5453 variable length. This is because the second pass of shorten_branches
5454 does not bother to update them. */
5457 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
5458 int noperands ATTRIBUTE_UNUSED)
5460 if (TARGET_DUMPISIZE)
5461 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
5467 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
5472 pattern = PATTERN (insn);
5473 if (GET_CODE (pattern) == PARALLEL)
5474 pattern = XVECEXP (pattern, 0, 0);
5475 switch (GET_CODE (pattern))
5478 if (GET_CODE (SET_SRC (pattern)) != CALL
5479 && get_attr_type (insn) != TYPE_SFUNC)
5481 targetm.asm_out.internal_label
5482 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
5485 /* else FALLTHROUGH */
5487 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
5488 CODE_LABEL_NUMBER (XEXP (note, 0)));
5498 /* Dump out any constants accumulated in the final pass. These will
5502 output_jump_label_table (void)
5508 fprintf (asm_out_file, "\t.align 2\n");
5509 for (i = 0; i < pool_size; i++)
5511 pool_node *p = &pool_vector[i];
5513 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5514 CODE_LABEL_NUMBER (p->label));
5515 output_asm_insn (".long %O0", &p->value);
5523 /* A full frame looks like:
5527 [ if current_function_anonymous_args
5540 local-0 <- fp points here. */
5542 /* Number of bytes pushed for anonymous args, used to pass information
5543 between expand_prologue and expand_epilogue. */
5545 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
5546 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
5547 for an epilogue and a negative value means that it's for a sibcall
5548 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
5549 all the registers that are about to be restored, and hence dead. */
5552 output_stack_adjust (int size, rtx reg, int epilogue_p,
5553 HARD_REG_SET *live_regs_mask)
5555 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
5558 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
5560 /* This test is bogus, as output_stack_adjust is used to re-align the
5563 gcc_assert (!(size % align));
5566 if (CONST_OK_FOR_ADD (size))
5567 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
5568 /* Try to do it with two partial adjustments; however, we must make
5569 sure that the stack is properly aligned at all times, in case
5570 an interrupt occurs between the two partial adjustments. */
5571 else if (CONST_OK_FOR_ADD (size / 2 & -align)
5572 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
5574 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
5575 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
5581 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
5584 /* If TEMP is invalid, we could temporarily save a general
5585 register to MACL. However, there is currently no need
5586 to handle this case, so just die when we see it. */
5588 || current_function_interrupt
5589 || ! call_really_used_regs[temp] || fixed_regs[temp])
5591 if (temp < 0 && ! current_function_interrupt
5592 && (TARGET_SHMEDIA || epilogue_p >= 0))
5595 COPY_HARD_REG_SET (temps, call_used_reg_set);
5596 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
5600 if (crtl->return_rtx)
5602 enum machine_mode mode;
5603 mode = GET_MODE (crtl->return_rtx);
5604 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
5605 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
5607 for (i = 0; i < nreg; i++)
5608 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
5609 if (crtl->calls_eh_return)
5611 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
5612 for (i = 0; i <= 3; i++)
5613 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
5616 if (TARGET_SHMEDIA && epilogue_p < 0)
5617 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
5618 CLEAR_HARD_REG_BIT (temps, i);
5619 if (epilogue_p <= 0)
5621 for (i = FIRST_PARM_REG;
5622 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
5623 CLEAR_HARD_REG_BIT (temps, i);
5624 if (cfun->static_chain_decl != NULL)
5625 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
5627 temp = scavenge_reg (&temps);
5629 if (temp < 0 && live_regs_mask)
5633 COPY_HARD_REG_SET (temps, *live_regs_mask);
5634 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
5635 temp = scavenge_reg (&temps);
5639 rtx adj_reg, tmp_reg, mem;
5641 /* If we reached here, the most likely case is the (sibcall)
5642 epilogue for non SHmedia. Put a special push/pop sequence
5643 for such case as the last resort. This looks lengthy but
5644 would not be problem because it seems to be very
5647 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
5650 /* ??? There is still the slight possibility that r4 or
5651 r5 have been reserved as fixed registers or assigned
5652 as global registers, and they change during an
5653 interrupt. There are possible ways to handle this:
5655 - If we are adjusting the frame pointer (r14), we can do
5656 with a single temp register and an ordinary push / pop
5658 - Grab any call-used or call-saved registers (i.e. not
5659 fixed or globals) for the temps we need. We might
5660 also grab r14 if we are adjusting the stack pointer.
5661 If we can't find enough available registers, issue
5662 a diagnostic and die - the user must have reserved
5663 way too many registers.
5664 But since all this is rather unlikely to happen and
5665 would require extra testing, we just die if r4 / r5
5666 are not available. */
5667 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
5668 && !global_regs[4] && !global_regs[5]);
5670 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
5671 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
5672 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
5673 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
5674 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
5675 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5676 emit_move_insn (mem, tmp_reg);
5677 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
5678 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5679 emit_move_insn (mem, tmp_reg);
5680 emit_move_insn (reg, adj_reg);
5681 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5682 emit_move_insn (adj_reg, mem);
5683 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5684 emit_move_insn (tmp_reg, mem);
5685 /* Tell flow the insns that pop r4/r5 aren't dead. */
5690 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
5692 /* If SIZE is negative, subtract the positive value.
5693 This sometimes allows a constant pool entry to be shared
5694 between prologue and epilogue code. */
5697 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
5698 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
5702 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
5703 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
5706 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
5707 gen_rtx_SET (VOIDmode, reg,
5708 gen_rtx_PLUS (SImode, reg,
5718 RTX_FRAME_RELATED_P (x) = 1;
5722 /* Output RTL to push register RN onto the stack. */
5729 x = gen_push_fpul ();
5730 else if (rn == FPSCR_REG)
5731 x = gen_push_fpscr ();
5732 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5733 && FP_OR_XD_REGISTER_P (rn))
5735 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5737 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
5739 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5740 x = gen_push_e (gen_rtx_REG (SFmode, rn));
5742 x = gen_push (gen_rtx_REG (SImode, rn));
5745 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
5749 /* Output RTL to pop register RN from the stack. */
5756 x = gen_pop_fpul ();
5757 else if (rn == FPSCR_REG)
5758 x = gen_pop_fpscr ();
5759 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5760 && FP_OR_XD_REGISTER_P (rn))
5762 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5764 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
5766 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5767 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
5769 x = gen_pop (gen_rtx_REG (SImode, rn));
5772 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
5775 /* Generate code to push the regs specified in the mask. */
5778 push_regs (HARD_REG_SET *mask, int interrupt_handler)
5780 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
5783 /* Push PR last; this gives better latencies after the prologue, and
5784 candidates for the return delay slot when there are no general
5785 registers pushed. */
5786 for (; i < FIRST_PSEUDO_REGISTER; i++)
5788 /* If this is an interrupt handler, and the SZ bit varies,
5789 and we have to push any floating point register, we need
5790 to switch to the correct precision first. */
5791 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
5792 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
5794 HARD_REG_SET unsaved;
5797 COMPL_HARD_REG_SET (unsaved, *mask);
5798 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
5802 && (i != FPSCR_REG || ! skip_fpscr)
5803 && TEST_HARD_REG_BIT (*mask, i))
5805 /* If the ISR has RESBANK attribute assigned, don't push any of
5806 the following registers - R0-R14, MACH, MACL and GBR. */
5807 if (! (sh_cfun_resbank_handler_p ()
5808 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
5816 /* Push banked registers last to improve delay slot opportunities. */
5817 if (interrupt_handler)
5818 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
5819 if (TEST_HARD_REG_BIT (*mask, i))
5822 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
5823 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
5827 /* Calculate how much extra space is needed to save all callee-saved
5829 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5832 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
5835 int stack_space = 0;
5836 int interrupt_handler = sh_cfun_interrupt_handler_p ();
5838 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
5839 if ((! call_really_used_regs[reg] || interrupt_handler)
5840 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
5841 /* Leave space to save this target register on the stack,
5842 in case target register allocation wants to use it. */
5843 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5847 /* Decide whether we should reserve space for callee-save target registers,
5848 in case target register allocation wants to use them. REGS_SAVED is
5849 the space, in bytes, that is already required for register saves.
5850 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5853 shmedia_reserve_space_for_target_registers_p (int regs_saved,
5854 HARD_REG_SET *live_regs_mask)
5858 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
5861 /* Decide how much space to reserve for callee-save target registers
5862 in case target register allocation wants to use them.
5863 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5866 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
5868 if (shmedia_space_reserved_for_target_registers)
5869 return shmedia_target_regs_stack_space (live_regs_mask);
5874 /* Work out the registers which need to be saved, both as a mask and a
5875 count of saved words. Return the count.
5877 If doing a pragma interrupt function, then push all regs used by the
5878 function, and if we call another function (we can tell by looking at PR),
5879 make sure that all the regs it clobbers are safe too. */
5882 calc_live_regs (HARD_REG_SET *live_regs_mask)
5887 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
5888 bool nosave_low_regs;
5889 int pr_live, has_call;
5891 attrs = DECL_ATTRIBUTES (current_function_decl);
5892 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
5893 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
5894 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
5895 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
5897 CLEAR_HARD_REG_SET (*live_regs_mask);
5898 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
5899 && df_regs_ever_live_p (FPSCR_REG))
5900 target_flags &= ~MASK_FPU_SINGLE;
5901 /* If we can save a lot of saves by switching to double mode, do that. */
5902 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
5903 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
5904 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
5905 && (! call_really_used_regs[reg]
5906 || interrupt_handler)
5909 target_flags &= ~MASK_FPU_SINGLE;
5912 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
5913 knows how to use it. That means the pseudo originally allocated for
5914 the initial value can become the PR_MEDIA_REG hard register, as seen for
5915 execute/20010122-1.c:test9. */
5917 /* ??? this function is called from initial_elimination_offset, hence we
5918 can't use the result of sh_media_register_for_return here. */
5919 pr_live = sh_pr_n_sets ();
5922 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
5923 pr_live = (pr_initial
5924 ? (GET_CODE (pr_initial) != REG
5925 || REGNO (pr_initial) != (PR_REG))
5926 : df_regs_ever_live_p (PR_REG));
5927 /* For Shcompact, if not optimizing, we end up with a memory reference
5928 using the return address pointer for __builtin_return_address even
5929 though there is no actual need to put the PR register on the stack. */
5930 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
5932 /* Force PR to be live if the prologue has to call the SHmedia
5933 argument decoder or register saver. */
5934 if (TARGET_SHCOMPACT
5935 && ((crtl->args.info.call_cookie
5936 & ~ CALL_COOKIE_RET_TRAMP (1))
5937 || crtl->saves_all_registers))
5939 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
5940 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
5942 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
5945 ? (/* Need to save all the regs ever live. */
5946 (df_regs_ever_live_p (reg)
5947 || (call_really_used_regs[reg]
5948 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
5949 || reg == PIC_OFFSET_TABLE_REGNUM)
5951 || (TARGET_SHMEDIA && has_call
5952 && REGISTER_NATURAL_MODE (reg) == SImode
5953 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
5954 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
5955 && reg != RETURN_ADDRESS_POINTER_REGNUM
5956 && reg != T_REG && reg != GBR_REG
5957 /* Push fpscr only on targets which have FPU */
5958 && (reg != FPSCR_REG || TARGET_FPU_ANY))
5959 : (/* Only push those regs which are used and need to be saved. */
5962 && crtl->args.info.call_cookie
5963 && reg == PIC_OFFSET_TABLE_REGNUM)
5964 || (df_regs_ever_live_p (reg)
5965 && ((!call_really_used_regs[reg]
5966 && !(reg != PIC_OFFSET_TABLE_REGNUM
5967 && fixed_regs[reg] && call_used_regs[reg]))
5968 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
5969 || (crtl->calls_eh_return
5970 && (reg == EH_RETURN_DATA_REGNO (0)
5971 || reg == EH_RETURN_DATA_REGNO (1)
5972 || reg == EH_RETURN_DATA_REGNO (2)
5973 || reg == EH_RETURN_DATA_REGNO (3)))
5974 || ((reg == MACL_REG || reg == MACH_REG)
5975 && df_regs_ever_live_p (reg)
5976 && sh_cfun_attr_renesas_p ())
5979 SET_HARD_REG_BIT (*live_regs_mask, reg);
5980 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5982 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
5983 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
5985 if (FP_REGISTER_P (reg))
5987 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
5989 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
5990 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
5993 else if (XD_REGISTER_P (reg))
5995 /* Must switch to double mode to access these registers. */
5996 target_flags &= ~MASK_FPU_SINGLE;
6000 if (nosave_low_regs && reg == R8_REG)
6003 /* If we have a target register optimization pass after prologue / epilogue
6004 threading, we need to assume all target registers will be live even if
6006 if (flag_branch_target_load_optimize2
6007 && TARGET_SAVE_ALL_TARGET_REGS
6008 && shmedia_space_reserved_for_target_registers)
6009 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6010 if ((! call_really_used_regs[reg] || interrupt_handler)
6011 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6013 SET_HARD_REG_BIT (*live_regs_mask, reg);
6014 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6016 /* If this is an interrupt handler, we don't have any call-clobbered
6017 registers we can conveniently use for target register save/restore.
6018 Make sure we save at least one general purpose register when we need
6019 to save target registers. */
6020 if (interrupt_handler
6021 && hard_reg_set_intersect_p (*live_regs_mask,
6022 reg_class_contents[TARGET_REGS])
6023 && ! hard_reg_set_intersect_p (*live_regs_mask,
6024 reg_class_contents[GENERAL_REGS]))
6026 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6027 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6033 /* Code to generate prologue and epilogue sequences */
6035 /* PUSHED is the number of bytes that are being pushed on the
6036 stack for register saves. Return the frame size, padded
6037 appropriately so that the stack stays properly aligned. */
6038 static HOST_WIDE_INT
6039 rounded_frame_size (int pushed)
6041 HOST_WIDE_INT size = get_frame_size ();
6042 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6044 return ((size + pushed + align - 1) & -align) - pushed;
6047 /* Choose a call-clobbered target-branch register that remains
6048 unchanged along the whole function. We set it up as the return
6049 value in the prologue. */
6051 sh_media_register_for_return (void)
6056 if (! current_function_is_leaf)
6058 if (lookup_attribute ("interrupt_handler",
6059 DECL_ATTRIBUTES (current_function_decl)))
6061 if (sh_cfun_interrupt_handler_p ())
6064 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6066 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6067 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6073 /* The maximum registers we need to save are:
6074 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6075 - 32 floating point registers (for each pair, we save none,
6076 one single precision value, or a double precision value).
6077 - 8 target registers
6078 - add 1 entry for a delimiter. */
6079 #define MAX_SAVED_REGS (62+32+8)
6081 typedef struct save_entry_s
6090 /* There will be a delimiter entry with VOIDmode both at the start and the
6091 end of a filled in schedule. The end delimiter has the offset of the
6092 save with the smallest (i.e. most negative) offset. */
6093 typedef struct save_schedule_s
6095 save_entry entries[MAX_SAVED_REGS + 2];
6096 int temps[MAX_TEMPS+1];
6099 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6100 use reverse order. Returns the last entry written to (not counting
6101 the delimiter). OFFSET_BASE is a number to be added to all offset
6105 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6109 save_entry *entry = schedule->entries;
6113 if (! current_function_interrupt)
6114 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6115 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6116 && ! FUNCTION_ARG_REGNO_P (i)
6117 && i != FIRST_RET_REG
6118 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6119 && ! (crtl->calls_eh_return
6120 && (i == EH_RETURN_STACKADJ_REGNO
6121 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6122 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6123 schedule->temps[tmpx++] = i;
6125 entry->mode = VOIDmode;
6126 entry->offset = offset_base;
6128 /* We loop twice: first, we save 8-byte aligned registers in the
6129 higher addresses, that are known to be aligned. Then, we
6130 proceed to saving 32-bit registers that don't need 8-byte
6132 If this is an interrupt function, all registers that need saving
6133 need to be saved in full. moreover, we need to postpone saving
6134 target registers till we have saved some general purpose registers
6135 we can then use as scratch registers. */
6136 offset = offset_base;
6137 for (align = 1; align >= 0; align--)
6139 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6140 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6142 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6145 if (current_function_interrupt)
6147 if (TARGET_REGISTER_P (i))
6149 if (GENERAL_REGISTER_P (i))
6152 if (mode == SFmode && (i % 2) == 1
6153 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6154 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6161 /* If we're doing the aligned pass and this is not aligned,
6162 or we're doing the unaligned pass and this is aligned,
6164 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6168 if (current_function_interrupt
6169 && GENERAL_REGISTER_P (i)
6170 && tmpx < MAX_TEMPS)
6171 schedule->temps[tmpx++] = i;
6173 offset -= GET_MODE_SIZE (mode);
6176 entry->offset = offset;
6179 if (align && current_function_interrupt)
6180 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6181 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6183 offset -= GET_MODE_SIZE (DImode);
6185 entry->mode = DImode;
6186 entry->offset = offset;
6191 entry->mode = VOIDmode;
6192 entry->offset = offset;
6193 schedule->temps[tmpx] = -1;
6198 sh_expand_prologue (void)
6200 HARD_REG_SET live_regs_mask;
6203 int save_flags = target_flags;
6206 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6208 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6210 /* We have pretend args if we had an object sent partially in registers
6211 and partially on the stack, e.g. a large structure. */
6212 pretend_args = crtl->args.pretend_args_size;
6213 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6214 && (NPARM_REGS(SImode)
6215 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
6217 output_stack_adjust (-pretend_args
6218 - crtl->args.info.stack_regs * 8,
6219 stack_pointer_rtx, 0, NULL);
6221 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
6222 /* We're going to use the PIC register to load the address of the
6223 incoming-argument decoder and/or of the return trampoline from
6224 the GOT, so make sure the PIC register is preserved and
6226 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6228 if (TARGET_SHCOMPACT
6229 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6233 /* First, make all registers with incoming arguments that will
6234 be pushed onto the stack live, so that register renaming
6235 doesn't overwrite them. */
6236 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6237 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
6238 >= NPARM_REGS (SImode) - reg)
6239 for (; reg < NPARM_REGS (SImode); reg++)
6240 emit_insn (gen_shcompact_preserve_incoming_args
6241 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6242 else if (CALL_COOKIE_INT_REG_GET
6243 (crtl->args.info.call_cookie, reg) == 1)
6244 emit_insn (gen_shcompact_preserve_incoming_args
6245 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6247 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6249 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6250 GEN_INT (crtl->args.info.call_cookie));
6251 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6252 gen_rtx_REG (SImode, R0_REG));
6254 else if (TARGET_SHMEDIA)
6256 int tr = sh_media_register_for_return ();
6259 emit_move_insn (gen_rtx_REG (DImode, tr),
6260 gen_rtx_REG (DImode, PR_MEDIA_REG));
6263 /* Emit the code for SETUP_VARARGS. */
6266 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6268 /* Push arg regs as if they'd been provided by caller in stack. */
6269 for (i = 0; i < NPARM_REGS(SImode); i++)
6271 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6274 if (i >= (NPARM_REGS(SImode)
6275 - crtl->args.info.arg_count[(int) SH_ARG_INT]
6283 /* If we're supposed to switch stacks at function entry, do so now. */
6286 /* The argument specifies a variable holding the address of the
6287 stack the interrupt function should switch to/from at entry/exit. */
6289 = ggc_strdup (TREE_STRING_POINTER (TREE_VALUE (sp_switch_attr)));
6290 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6292 emit_insn (gen_sp_switch_1 (sp_switch));
6295 d = calc_live_regs (&live_regs_mask);
6296 /* ??? Maybe we could save some switching if we can move a mode switch
6297 that already happens to be at the function start into the prologue. */
6298 if (target_flags != save_flags && ! current_function_interrupt)
6299 emit_insn (gen_toggle_sz ());
6303 int offset_base, offset;
6305 int offset_in_r0 = -1;
6307 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6308 int total_size, save_size;
6309 save_schedule schedule;
6313 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6314 && ! current_function_interrupt)
6315 r0 = gen_rtx_REG (Pmode, R0_REG);
6317 /* D is the actual number of bytes that we need for saving registers,
6318 however, in initial_elimination_offset we have committed to using
6319 an additional TREGS_SPACE amount of bytes - in order to keep both
6320 addresses to arguments supplied by the caller and local variables
6321 valid, we must keep this gap. Place it between the incoming
6322 arguments and the actually saved registers in a bid to optimize
6323 locality of reference. */
6324 total_size = d + tregs_space;
6325 total_size += rounded_frame_size (total_size);
6326 save_size = total_size - rounded_frame_size (d);
6327 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6328 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6329 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6331 /* If adjusting the stack in a single step costs nothing extra, do so.
6332 I.e. either if a single addi is enough, or we need a movi anyway,
6333 and we don't exceed the maximum offset range (the test for the
6334 latter is conservative for simplicity). */
6336 && (CONST_OK_FOR_I10 (-total_size)
6337 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6338 && total_size <= 2044)))
6339 d_rounding = total_size - save_size;
6341 offset_base = d + d_rounding;
6343 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
6346 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6347 tmp_pnt = schedule.temps;
6348 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6350 enum machine_mode mode = entry->mode;
6351 unsigned int reg = entry->reg;
6352 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
6355 offset = entry->offset;
6357 reg_rtx = gen_rtx_REG (mode, reg);
6359 mem_rtx = gen_frame_mem (mode,
6360 gen_rtx_PLUS (Pmode,
6364 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
6371 if (HAVE_PRE_DECREMENT
6372 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6373 || mem_rtx == NULL_RTX
6374 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6376 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
6378 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
6387 offset += GET_MODE_SIZE (mode);
6391 if (mem_rtx != NULL_RTX)
6394 if (offset_in_r0 == -1)
6396 emit_move_insn (r0, GEN_INT (offset));
6397 offset_in_r0 = offset;
6399 else if (offset != offset_in_r0)
6404 GEN_INT (offset - offset_in_r0)));
6405 offset_in_r0 += offset - offset_in_r0;
6408 if (pre_dec != NULL_RTX)
6414 (Pmode, r0, stack_pointer_rtx));
6418 offset -= GET_MODE_SIZE (mode);
6419 offset_in_r0 -= GET_MODE_SIZE (mode);
6424 mem_rtx = gen_frame_mem (mode, r0);
6426 mem_rtx = gen_frame_mem (mode,
6427 gen_rtx_PLUS (Pmode,
6431 /* We must not use an r0-based address for target-branch
6432 registers or for special registers without pre-dec
6433 memory addresses, since we store their values in r0
6435 gcc_assert (!TARGET_REGISTER_P (reg)
6436 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6437 || mem_rtx == pre_dec));
6440 orig_reg_rtx = reg_rtx;
6441 if (TARGET_REGISTER_P (reg)
6442 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6443 && mem_rtx != pre_dec))
6445 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
6447 emit_move_insn (tmp_reg, reg_rtx);
6449 if (REGNO (tmp_reg) == R0_REG)
6453 gcc_assert (!refers_to_regno_p
6454 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
6457 if (*++tmp_pnt <= 0)
6458 tmp_pnt = schedule.temps;
6465 /* Mark as interesting for dwarf cfi generator */
6466 insn = emit_move_insn (mem_rtx, reg_rtx);
6467 RTX_FRAME_RELATED_P (insn) = 1;
6468 /* If we use an intermediate register for the save, we can't
6469 describe this exactly in cfi as a copy of the to-be-saved
6470 register into the temporary register and then the temporary
6471 register on the stack, because the temporary register can
6472 have a different natural size than the to-be-saved register.
6473 Thus, we gloss over the intermediate copy and pretend we do
6474 a direct save from the to-be-saved register. */
6475 if (REGNO (reg_rtx) != reg)
6479 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
6480 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6483 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
6485 rtx reg_rtx = gen_rtx_REG (mode, reg);
6487 rtx mem_rtx = gen_frame_mem (mode,
6488 gen_rtx_PLUS (Pmode,
6492 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
6493 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6498 gcc_assert (entry->offset == d_rounding);
6501 push_regs (&live_regs_mask, current_function_interrupt);
6503 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
6504 emit_insn (gen_GOTaddr2picreg ());
6506 if (SHMEDIA_REGS_STACK_ADJUST ())
6508 /* This must NOT go through the PLT, otherwise mach and macl
6509 may be clobbered. */
6510 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6512 ? "__GCC_push_shmedia_regs"
6513 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
6514 emit_insn (gen_shmedia_save_restore_regs_compact
6515 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
6518 if (target_flags != save_flags && ! current_function_interrupt)
6519 emit_insn (gen_toggle_sz ());
6521 target_flags = save_flags;
6523 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
6524 stack_pointer_rtx, 0, NULL);
6526 if (frame_pointer_needed)
6527 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
6529 if (TARGET_SHCOMPACT
6530 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6532 /* This must NOT go through the PLT, otherwise mach and macl
6533 may be clobbered. */
6534 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6535 "__GCC_shcompact_incoming_args", SFUNC_GOT);
6536 emit_insn (gen_shcompact_incoming_args ());
6541 sh_expand_epilogue (bool sibcall_p)
6543 HARD_REG_SET live_regs_mask;
6547 int save_flags = target_flags;
6548 int frame_size, save_size;
6549 int fpscr_deferred = 0;
6550 int e = sibcall_p ? -1 : 1;
6552 d = calc_live_regs (&live_regs_mask);
6555 frame_size = rounded_frame_size (d);
6559 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6561 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
6562 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6563 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
6565 total_size = d + tregs_space;
6566 total_size += rounded_frame_size (total_size);
6567 save_size = total_size - frame_size;
6569 /* If adjusting the stack in a single step costs nothing extra, do so.
6570 I.e. either if a single addi is enough, or we need a movi anyway,
6571 and we don't exceed the maximum offset range (the test for the
6572 latter is conservative for simplicity). */
6574 && ! frame_pointer_needed
6575 && (CONST_OK_FOR_I10 (total_size)
6576 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
6577 && total_size <= 2044)))
6578 d_rounding = frame_size;
6580 frame_size -= d_rounding;
6583 if (frame_pointer_needed)
6585 /* We must avoid scheduling the epilogue with previous basic blocks
6586 when exception handling is enabled. See PR/18032. */
6587 if (flag_exceptions)
6588 emit_insn (gen_blockage ());
6589 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
6592 /* We must avoid moving the stack pointer adjustment past code
6593 which reads from the local frame, else an interrupt could
6594 occur after the SP adjustment and clobber data in the local
6596 emit_insn (gen_blockage ());
6597 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
6599 else if (frame_size)
6601 /* We must avoid moving the stack pointer adjustment past code
6602 which reads from the local frame, else an interrupt could
6603 occur after the SP adjustment and clobber data in the local
6605 emit_insn (gen_blockage ());
6606 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
6609 if (SHMEDIA_REGS_STACK_ADJUST ())
6611 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6613 ? "__GCC_pop_shmedia_regs"
6614 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
6615 /* This must NOT go through the PLT, otherwise mach and macl
6616 may be clobbered. */
6617 emit_insn (gen_shmedia_save_restore_regs_compact
6618 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
6621 /* Pop all the registers. */
6623 if (target_flags != save_flags && ! current_function_interrupt)
6624 emit_insn (gen_toggle_sz ());
6627 int offset_base, offset;
6628 int offset_in_r0 = -1;
6630 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
6631 save_schedule schedule;
6635 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
6636 offset_base = -entry[1].offset + d_rounding;
6637 tmp_pnt = schedule.temps;
6638 for (; entry->mode != VOIDmode; entry--)
6640 enum machine_mode mode = entry->mode;
6641 int reg = entry->reg;
6642 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
6644 offset = offset_base + entry->offset;
6645 reg_rtx = gen_rtx_REG (mode, reg);
6647 mem_rtx = gen_frame_mem (mode,
6648 gen_rtx_PLUS (Pmode,
6652 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
6658 if (HAVE_POST_INCREMENT
6659 && (offset == offset_in_r0
6660 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
6661 && mem_rtx == NULL_RTX)
6662 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6664 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
6666 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
6669 post_inc = NULL_RTX;
6678 if (mem_rtx != NULL_RTX)
6681 if (offset_in_r0 == -1)
6683 emit_move_insn (r0, GEN_INT (offset));
6684 offset_in_r0 = offset;
6686 else if (offset != offset_in_r0)
6691 GEN_INT (offset - offset_in_r0)));
6692 offset_in_r0 += offset - offset_in_r0;
6695 if (post_inc != NULL_RTX)
6701 (Pmode, r0, stack_pointer_rtx));
6707 offset_in_r0 += GET_MODE_SIZE (mode);
6710 mem_rtx = gen_frame_mem (mode, r0);
6712 mem_rtx = gen_frame_mem (mode,
6713 gen_rtx_PLUS (Pmode,
6717 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6718 || mem_rtx == post_inc);
6721 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6722 && mem_rtx != post_inc)
6724 insn = emit_move_insn (r0, mem_rtx);
6727 else if (TARGET_REGISTER_P (reg))
6729 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
6731 /* Give the scheduler a bit of freedom by using up to
6732 MAX_TEMPS registers in a round-robin fashion. */
6733 insn = emit_move_insn (tmp_reg, mem_rtx);
6736 tmp_pnt = schedule.temps;
6739 insn = emit_move_insn (reg_rtx, mem_rtx);
6742 gcc_assert (entry->offset + offset_base == d + d_rounding);
6744 else /* ! TARGET_SH5 */
6749 /* For an ISR with RESBANK attribute assigned, don't pop PR
6751 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
6752 && !sh_cfun_resbank_handler_p ())
6754 if (!frame_pointer_needed)
6755 emit_insn (gen_blockage ());
6759 /* Banked registers are poped first to avoid being scheduled in the
6760 delay slot. RTE switches banks before the ds instruction. */
6761 if (current_function_interrupt)
6763 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6764 if (TEST_HARD_REG_BIT (live_regs_mask, i))
6765 pop (LAST_BANKED_REG - i);
6767 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
6770 last_reg = FIRST_PSEUDO_REGISTER;
6772 for (i = 0; i < last_reg; i++)
6774 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
6776 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
6777 && hard_reg_set_intersect_p (live_regs_mask,
6778 reg_class_contents[DF_REGS]))
6780 /* For an ISR with RESBANK attribute assigned, don't pop
6781 following registers, R0-R14, MACH, MACL and GBR. */
6782 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
6783 && ! (sh_cfun_resbank_handler_p ()
6784 && ((j >= FIRST_GENERAL_REG
6785 && j < LAST_GENERAL_REG)
6791 if (j == FIRST_FP_REG && fpscr_deferred)
6795 if (target_flags != save_flags && ! current_function_interrupt)
6796 emit_insn (gen_toggle_sz ());
6797 target_flags = save_flags;
6799 output_stack_adjust (crtl->args.pretend_args_size
6800 + save_size + d_rounding
6801 + crtl->args.info.stack_regs * 8,
6802 stack_pointer_rtx, e, NULL);
6804 if (crtl->calls_eh_return)
6805 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
6806 EH_RETURN_STACKADJ_RTX));
6808 /* Switch back to the normal stack if necessary. */
6809 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
6810 emit_insn (gen_sp_switch_2 ());
6812 /* Tell flow the insn that pops PR isn't dead. */
6813 /* PR_REG will never be live in SHmedia mode, and we don't need to
6814 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
6815 by the return pattern. */
6816 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
6817 emit_use (gen_rtx_REG (SImode, PR_REG));
6820 static int sh_need_epilogue_known = 0;
6823 sh_need_epilogue (void)
6825 if (! sh_need_epilogue_known)
6830 sh_expand_epilogue (0);
6831 epilogue = get_insns ();
6833 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
6835 return sh_need_epilogue_known > 0;
6838 /* Emit code to change the current function's return address to RA.
6839 TEMP is available as a scratch register, if needed. */
6842 sh_set_return_address (rtx ra, rtx tmp)
6844 HARD_REG_SET live_regs_mask;
6846 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
6849 d = calc_live_regs (&live_regs_mask);
6851 /* If pr_reg isn't life, we can set it (or the register given in
6852 sh_media_register_for_return) directly. */
6853 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
6859 int rr_regno = sh_media_register_for_return ();
6864 rr = gen_rtx_REG (DImode, rr_regno);
6867 rr = gen_rtx_REG (SImode, pr_reg);
6869 emit_insn (GEN_MOV (rr, ra));
6870 /* Tell flow the register for return isn't dead. */
6878 save_schedule schedule;
6881 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
6882 offset = entry[1].offset;
6883 for (; entry->mode != VOIDmode; entry--)
6884 if (entry->reg == pr_reg)
6887 /* We can't find pr register. */
6891 offset = entry->offset - offset;
6892 pr_offset = (rounded_frame_size (d) + offset
6893 + SHMEDIA_REGS_STACK_ADJUST ());
6896 pr_offset = rounded_frame_size (d);
6898 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
6899 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
6901 tmp = gen_frame_mem (Pmode, tmp);
6902 emit_insn (GEN_MOV (tmp, ra));
6905 /* Clear variables at function end. */
6908 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6909 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6911 sh_need_epilogue_known = 0;
6915 sh_builtin_saveregs (void)
6917 /* First unnamed integer register. */
6918 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
6919 /* Number of integer registers we need to save. */
6920 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
6921 /* First unnamed SFmode float reg */
6922 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
6923 /* Number of SFmode float regs to save. */
6924 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
6927 alias_set_type alias_set;
6933 int pushregs = n_intregs;
6935 while (pushregs < NPARM_REGS (SImode) - 1
6936 && (CALL_COOKIE_INT_REG_GET
6937 (crtl->args.info.call_cookie,
6938 NPARM_REGS (SImode) - pushregs)
6941 crtl->args.info.call_cookie
6942 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
6947 if (pushregs == NPARM_REGS (SImode))
6948 crtl->args.info.call_cookie
6949 |= (CALL_COOKIE_INT_REG (0, 1)
6950 | CALL_COOKIE_STACKSEQ (pushregs - 1));
6952 crtl->args.info.call_cookie
6953 |= CALL_COOKIE_STACKSEQ (pushregs);
6955 crtl->args.pretend_args_size += 8 * n_intregs;
6957 if (TARGET_SHCOMPACT)
6961 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
6963 error ("__builtin_saveregs not supported by this subtarget");
6970 /* Allocate block of memory for the regs. */
6971 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
6972 Or can assign_stack_local accept a 0 SIZE argument? */
6973 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
6976 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
6977 else if (n_floatregs & 1)
6981 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
6982 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
6983 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
6984 regbuf = change_address (regbuf, BLKmode, addr);
6986 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
6990 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
6991 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
6992 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
6993 emit_insn (gen_andsi3 (addr, addr, mask));
6994 regbuf = change_address (regbuf, BLKmode, addr);
6997 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
6998 alias_set = get_varargs_alias_set ();
6999 set_mem_alias_set (regbuf, alias_set);
7002 This is optimized to only save the regs that are necessary. Explicitly
7003 named args need not be saved. */
7005 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7006 adjust_address (regbuf, BLKmode,
7007 n_floatregs * UNITS_PER_WORD),
7011 /* Return the address of the regbuf. */
7012 return XEXP (regbuf, 0);
7015 This is optimized to only save the regs that are necessary. Explicitly
7016 named args need not be saved.
7017 We explicitly build a pointer to the buffer because it halves the insn
7018 count when not optimizing (otherwise the pointer is built for each reg
7020 We emit the moves in reverse order so that we can use predecrement. */
7022 fpregs = copy_to_mode_reg (Pmode,
7023 plus_constant (XEXP (regbuf, 0),
7024 n_floatregs * UNITS_PER_WORD));
7025 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7028 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7030 emit_insn (gen_addsi3 (fpregs, fpregs,
7031 GEN_INT (-2 * UNITS_PER_WORD)));
7032 mem = change_address (regbuf, DFmode, fpregs);
7033 emit_move_insn (mem,
7034 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7036 regno = first_floatreg;
7039 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7040 mem = change_address (regbuf, SFmode, fpregs);
7041 emit_move_insn (mem,
7042 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7043 - (TARGET_LITTLE_ENDIAN != 0)));
7047 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7051 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7052 mem = change_address (regbuf, SFmode, fpregs);
7053 emit_move_insn (mem,
7054 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7057 /* Return the address of the regbuf. */
7058 return XEXP (regbuf, 0);
7061 /* Define the `__builtin_va_list' type for the ABI. */
7064 sh_build_builtin_va_list (void)
7066 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7069 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7070 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7071 return ptr_type_node;
7073 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7075 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
7077 f_next_o_limit = build_decl (FIELD_DECL,
7078 get_identifier ("__va_next_o_limit"),
7080 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
7082 f_next_fp_limit = build_decl (FIELD_DECL,
7083 get_identifier ("__va_next_fp_limit"),
7085 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
7088 DECL_FIELD_CONTEXT (f_next_o) = record;
7089 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7090 DECL_FIELD_CONTEXT (f_next_fp) = record;
7091 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7092 DECL_FIELD_CONTEXT (f_next_stack) = record;
7094 TYPE_FIELDS (record) = f_next_o;
7095 TREE_CHAIN (f_next_o) = f_next_o_limit;
7096 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7097 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7098 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7100 layout_type (record);
7105 /* Implement `va_start' for varargs and stdarg. */
7108 sh_va_start (tree valist, rtx nextarg)
7110 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7111 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7117 expand_builtin_saveregs ();
7118 std_expand_builtin_va_start (valist, nextarg);
7122 if ((! TARGET_SH2E && ! TARGET_SH4)
7123 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7125 std_expand_builtin_va_start (valist, nextarg);
7129 f_next_o = TYPE_FIELDS (va_list_type_node);
7130 f_next_o_limit = TREE_CHAIN (f_next_o);
7131 f_next_fp = TREE_CHAIN (f_next_o_limit);
7132 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7133 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7135 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7137 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7138 valist, f_next_o_limit, NULL_TREE);
7139 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7141 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7142 valist, f_next_fp_limit, NULL_TREE);
7143 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7144 valist, f_next_stack, NULL_TREE);
7146 /* Call __builtin_saveregs. */
7147 u = make_tree (sizetype, expand_builtin_saveregs ());
7148 u = fold_convert (ptr_type_node, u);
7149 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7150 TREE_SIDE_EFFECTS (t) = 1;
7151 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7153 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7158 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7159 size_int (UNITS_PER_WORD * nfp));
7160 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7161 TREE_SIDE_EFFECTS (t) = 1;
7162 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7164 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7165 TREE_SIDE_EFFECTS (t) = 1;
7166 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7168 nint = crtl->args.info.arg_count[SH_ARG_INT];
7173 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7174 size_int (UNITS_PER_WORD * nint));
7175 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7176 TREE_SIDE_EFFECTS (t) = 1;
7177 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7179 u = make_tree (ptr_type_node, nextarg);
7180 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7181 TREE_SIDE_EFFECTS (t) = 1;
7182 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7185 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7186 member, return it. */
7188 find_sole_member (tree type)
7190 tree field, member = NULL_TREE;
7192 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7194 if (TREE_CODE (field) != FIELD_DECL)
7196 if (!DECL_SIZE (field))
7198 if (integer_zerop (DECL_SIZE (field)))
7206 /* Implement `va_arg'. */
7209 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7210 gimple_seq *post_p ATTRIBUTE_UNUSED)
7212 HOST_WIDE_INT size, rsize;
7213 tree tmp, pptr_type_node;
7214 tree addr, lab_over = NULL, result = NULL;
7215 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7219 type = build_pointer_type (type);
7221 size = int_size_in_bytes (type);
7222 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7223 pptr_type_node = build_pointer_type (ptr_type_node);
7225 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7226 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7228 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7229 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7234 f_next_o = TYPE_FIELDS (va_list_type_node);
7235 f_next_o_limit = TREE_CHAIN (f_next_o);
7236 f_next_fp = TREE_CHAIN (f_next_o_limit);
7237 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7238 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7240 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7242 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7243 valist, f_next_o_limit, NULL_TREE);
7244 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7245 valist, f_next_fp, NULL_TREE);
7246 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7247 valist, f_next_fp_limit, NULL_TREE);
7248 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7249 valist, f_next_stack, NULL_TREE);
7251 /* Structures with a single member with a distinct mode are passed
7252 like their member. This is relevant if the latter has a REAL_TYPE
7253 or COMPLEX_TYPE type. */
7255 while (TREE_CODE (eff_type) == RECORD_TYPE
7256 && (member = find_sole_member (eff_type))
7257 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7258 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7259 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7261 tree field_type = TREE_TYPE (member);
7263 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7264 eff_type = field_type;
7267 gcc_assert ((TYPE_ALIGN (eff_type)
7268 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7269 || (TYPE_ALIGN (eff_type)
7270 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7275 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7277 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7278 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7279 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7284 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7287 addr = create_tmp_var (pptr_type_node, NULL);
7288 lab_false = create_artificial_label ();
7289 lab_over = create_artificial_label ();
7291 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
7295 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7297 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7299 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
7300 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7302 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
7303 tmp = next_fp_limit;
7304 if (size > 4 && !is_double)
7305 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp),
7306 unshare_expr (tmp), size_int (4 - size));
7307 tmp = build2 (GE_EXPR, boolean_type_node,
7308 unshare_expr (next_fp_tmp), unshare_expr (tmp));
7309 cmp = build3 (COND_EXPR, void_type_node, tmp,
7310 build1 (GOTO_EXPR, void_type_node,
7311 unshare_expr (lab_false)), NULL_TREE);
7313 gimplify_and_add (cmp, pre_p);
7315 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7316 || (is_double || size == 16))
7318 tmp = fold_convert (sizetype, next_fp_tmp);
7319 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7320 size_int (UNITS_PER_WORD));
7321 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7322 unshare_expr (next_fp_tmp), tmp);
7323 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
7326 gimplify_and_add (cmp, pre_p);
7328 #ifdef FUNCTION_ARG_SCmode_WART
7329 if (TYPE_MODE (eff_type) == SCmode
7330 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7332 tree subtype = TREE_TYPE (eff_type);
7336 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7337 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7340 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7341 real = get_initialized_tmp_var (real, pre_p, NULL);
7343 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
7344 if (type != eff_type)
7345 result = build1 (VIEW_CONVERT_EXPR, type, result);
7346 result = get_initialized_tmp_var (result, pre_p, NULL);
7348 #endif /* FUNCTION_ARG_SCmode_WART */
7350 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7351 gimplify_and_add (tmp, pre_p);
7353 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7354 gimplify_and_add (tmp, pre_p);
7356 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7357 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7358 gimplify_assign (unshare_expr (next_fp_tmp),
7359 unshare_expr (valist), pre_p);
7361 gimplify_assign (unshare_expr (valist),
7362 unshare_expr (next_fp_tmp), post_p);
7363 valist = next_fp_tmp;
7367 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7368 unshare_expr (next_o), size_int (rsize));
7369 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
7370 unshare_expr (next_o_limit));
7371 tmp = build3 (COND_EXPR, void_type_node, tmp,
7372 build1 (GOTO_EXPR, void_type_node,
7373 unshare_expr (lab_false)),
7375 gimplify_and_add (tmp, pre_p);
7377 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
7378 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7380 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7381 gimplify_and_add (tmp, pre_p);
7383 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7384 gimplify_and_add (tmp, pre_p);
7386 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7387 gimplify_assign (unshare_expr (next_o),
7388 unshare_expr (next_o_limit), pre_p);
7390 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7391 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7396 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7397 gimplify_and_add (tmp, pre_p);
7401 /* ??? In va-sh.h, there had been code to make values larger than
7402 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7404 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7407 gimplify_assign (result, tmp, pre_p);
7409 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7410 gimplify_and_add (tmp, pre_p);
7416 result = build_va_arg_indirect_ref (result);
7421 /* 64 bit floating points memory transfers are paired single precision loads
7422 or store. So DWARF information needs fixing in little endian (unless
7423 PR=SZ=1 in FPSCR). */
7425 sh_dwarf_register_span (rtx reg)
7427 unsigned regno = REGNO (reg);
7429 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
7433 gen_rtx_PARALLEL (VOIDmode,
7435 gen_rtx_REG (SFmode,
7436 DBX_REGISTER_NUMBER (regno+1)),
7437 gen_rtx_REG (SFmode,
7438 DBX_REGISTER_NUMBER (regno))));
7442 sh_promote_prototypes (const_tree type)
7448 return ! sh_attr_renesas_p (type);
7451 /* Whether an argument must be passed by reference. On SHcompact, we
7452 pretend arguments wider than 32-bits that would have been passed in
7453 registers are passed by reference, so that an SHmedia trampoline
7454 loads them into the full 64-bits registers. */
7457 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
7458 const_tree type, bool named)
7460 unsigned HOST_WIDE_INT size;
7463 size = int_size_in_bytes (type);
7465 size = GET_MODE_SIZE (mode);
7467 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
7469 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
7470 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
7471 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
7473 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
7474 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7481 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7482 const_tree type, bool named)
7484 if (targetm.calls.must_pass_in_stack (mode, type))
7487 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7488 wants to know about pass-by-reference semantics for incoming
7493 if (TARGET_SHCOMPACT)
7495 cum->byref = shcompact_byref (cum, mode, type, named);
7496 return cum->byref != 0;
7503 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7504 const_tree type, bool named ATTRIBUTE_UNUSED)
7506 /* ??? How can it possibly be correct to return true only on the
7507 caller side of the equation? Is there someplace else in the
7508 sh backend that's magically producing the copies? */
7509 return (cum->outgoing
7510 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
7511 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
7515 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7516 tree type, bool named ATTRIBUTE_UNUSED)
7521 && PASS_IN_REG_P (*cum, mode, type)
7522 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7523 && (ROUND_REG (*cum, mode)
7525 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
7526 : ROUND_ADVANCE (int_size_in_bytes (type)))
7527 > NPARM_REGS (mode)))
7528 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
7530 else if (!TARGET_SHCOMPACT
7531 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7532 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
7534 return words * UNITS_PER_WORD;
7538 /* Define where to put the arguments to a function.
7539 Value is zero to push the argument on the stack,
7540 or a hard register in which to store the argument.
7542 MODE is the argument's machine mode.
7543 TYPE is the data type of the argument (as a tree).
7544 This is null for libcalls where that information may
7546 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7547 the preceding args and about the function being called.
7548 NAMED is nonzero if this argument is a named parameter
7549 (otherwise it is an extra parameter matching an ellipsis).
7551 On SH the first args are normally in registers
7552 and the rest are pushed. Any arg that starts within the first
7553 NPARM_REGS words is at least partially passed in a register unless
7554 its data type forbids. */
7558 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7559 tree type, int named)
7561 if (! TARGET_SH5 && mode == VOIDmode)
7562 return GEN_INT (ca->renesas_abi ? 1 : 0);
7565 && PASS_IN_REG_P (*ca, mode, type)
7566 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
7570 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
7571 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
7573 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
7574 gen_rtx_REG (SFmode,
7576 + (ROUND_REG (*ca, mode) ^ 1)),
7578 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
7579 gen_rtx_REG (SFmode,
7581 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
7583 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
7586 /* If the alignment of a DF value causes an SF register to be
7587 skipped, we will use that skipped register for the next SF
7589 if ((TARGET_HITACHI || ca->renesas_abi)
7590 && ca->free_single_fp_reg
7592 return gen_rtx_REG (mode, ca->free_single_fp_reg);
7594 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
7595 ^ (mode == SFmode && TARGET_SH4
7596 && TARGET_LITTLE_ENDIAN != 0
7597 && ! TARGET_HITACHI && ! ca->renesas_abi);
7598 return gen_rtx_REG (mode, regno);
7604 if (mode == VOIDmode && TARGET_SHCOMPACT)
7605 return GEN_INT (ca->call_cookie);
7607 /* The following test assumes unnamed arguments are promoted to
7609 if (mode == SFmode && ca->free_single_fp_reg)
7610 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
7612 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
7613 && (named || ! ca->prototype_p)
7614 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
7616 if (! ca->prototype_p && TARGET_SHMEDIA)
7617 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
7619 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
7621 + ca->arg_count[(int) SH_ARG_FLOAT]);
7624 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
7625 && (! TARGET_SHCOMPACT
7626 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
7627 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
7630 return gen_rtx_REG (mode, (FIRST_PARM_REG
7631 + ca->arg_count[(int) SH_ARG_INT]));
7640 /* Update the data in CUM to advance over an argument
7641 of mode MODE and data type TYPE.
7642 (TYPE is null for libcalls where that information may not be
7646 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7647 tree type, int named)
7651 else if (TARGET_SH5)
7653 tree type2 = (ca->byref && type
7656 enum machine_mode mode2 = (ca->byref && type
7659 int dwords = ((ca->byref
7662 ? int_size_in_bytes (type2)
7663 : GET_MODE_SIZE (mode2)) + 7) / 8;
7664 int numregs = MIN (dwords, NPARM_REGS (SImode)
7665 - ca->arg_count[(int) SH_ARG_INT]);
7669 ca->arg_count[(int) SH_ARG_INT] += numregs;
7670 if (TARGET_SHCOMPACT
7671 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
7674 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7676 /* N.B. We want this also for outgoing. */
7677 ca->stack_regs += numregs;
7682 ca->stack_regs += numregs;
7683 ca->byref_regs += numregs;
7687 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7691 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7694 else if (dwords > numregs)
7696 int pushregs = numregs;
7698 if (TARGET_SHCOMPACT)
7699 ca->stack_regs += numregs;
7700 while (pushregs < NPARM_REGS (SImode) - 1
7701 && (CALL_COOKIE_INT_REG_GET
7703 NPARM_REGS (SImode) - pushregs)
7707 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7711 if (numregs == NPARM_REGS (SImode))
7713 |= CALL_COOKIE_INT_REG (0, 1)
7714 | CALL_COOKIE_STACKSEQ (numregs - 1);
7717 |= CALL_COOKIE_STACKSEQ (numregs);
7720 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
7721 && (named || ! ca->prototype_p))
7723 if (mode2 == SFmode && ca->free_single_fp_reg)
7724 ca->free_single_fp_reg = 0;
7725 else if (ca->arg_count[(int) SH_ARG_FLOAT]
7726 < NPARM_REGS (SFmode))
7729 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
7731 - ca->arg_count[(int) SH_ARG_FLOAT]);
7733 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
7735 if (TARGET_SHCOMPACT && ! ca->prototype_p)
7737 if (ca->outgoing && numregs > 0)
7741 |= (CALL_COOKIE_INT_REG
7742 (ca->arg_count[(int) SH_ARG_INT]
7743 - numregs + ((numfpregs - 2) / 2),
7744 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
7747 while (numfpregs -= 2);
7749 else if (mode2 == SFmode && (named)
7750 && (ca->arg_count[(int) SH_ARG_FLOAT]
7751 < NPARM_REGS (SFmode)))
7752 ca->free_single_fp_reg
7753 = FIRST_FP_PARM_REG - numfpregs
7754 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
7760 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
7762 /* Note that we've used the skipped register. */
7763 if (mode == SFmode && ca->free_single_fp_reg)
7765 ca->free_single_fp_reg = 0;
7768 /* When we have a DF after an SF, there's an SF register that get
7769 skipped in order to align the DF value. We note this skipped
7770 register, because the next SF value will use it, and not the
7771 SF that follows the DF. */
7773 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
7775 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
7776 + BASE_ARG_REG (mode));
7780 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
7781 || PASS_IN_REG_P (*ca, mode, type))
7782 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
7783 = (ROUND_REG (*ca, mode)
7785 ? ROUND_ADVANCE (int_size_in_bytes (type))
7786 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
7789 /* The Renesas calling convention doesn't quite fit into this scheme since
7790 the address is passed like an invisible argument, but one that is always
7791 passed in memory. */
7793 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
7795 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7797 return gen_rtx_REG (Pmode, 2);
7800 /* Worker function for TARGET_RETURN_IN_MEMORY. */
7803 sh_return_in_memory (const_tree type, const_tree fndecl)
7807 if (TYPE_MODE (type) == BLKmode)
7808 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
7810 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
7814 return (TYPE_MODE (type) == BLKmode
7815 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7816 && TREE_CODE (type) == RECORD_TYPE));
7820 /* We actually emit the code in sh_expand_prologue. We used to use
7821 a static variable to flag that we need to emit this code, but that
7822 doesn't when inlining, when functions are deferred and then emitted
7823 later. Fortunately, we already have two flags that are part of struct
7824 function that tell if a function uses varargs or stdarg. */
7826 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
7827 enum machine_mode mode,
7829 int *pretend_arg_size,
7830 int second_time ATTRIBUTE_UNUSED)
7832 gcc_assert (cfun->stdarg);
7833 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
7835 int named_parm_regs, anon_parm_regs;
7837 named_parm_regs = (ROUND_REG (*ca, mode)
7839 ? ROUND_ADVANCE (int_size_in_bytes (type))
7840 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
7841 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
7842 if (anon_parm_regs > 0)
7843 *pretend_arg_size = anon_parm_regs * 4;
7848 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
7854 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
7856 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
7860 /* Define the offset between two registers, one to be eliminated, and
7861 the other its replacement, at the start of a routine. */
7864 initial_elimination_offset (int from, int to)
7867 int regs_saved_rounding = 0;
7868 int total_saved_regs_space;
7869 int total_auto_space;
7870 int save_flags = target_flags;
7872 HARD_REG_SET live_regs_mask;
7874 shmedia_space_reserved_for_target_registers = false;
7875 regs_saved = calc_live_regs (&live_regs_mask);
7876 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
7878 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
7880 shmedia_space_reserved_for_target_registers = true;
7881 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
7884 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
7885 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7886 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
7888 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
7889 copy_flags = target_flags;
7890 target_flags = save_flags;
7892 total_saved_regs_space = regs_saved + regs_saved_rounding;
7894 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7895 return total_saved_regs_space + total_auto_space
7896 + crtl->args.info.byref_regs * 8;
7898 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7899 return total_saved_regs_space + total_auto_space
7900 + crtl->args.info.byref_regs * 8;
7902 /* Initial gap between fp and sp is 0. */
7903 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7906 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7907 return rounded_frame_size (0);
7909 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7910 return rounded_frame_size (0);
7912 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
7913 && (to == HARD_FRAME_POINTER_REGNUM
7914 || to == STACK_POINTER_REGNUM));
7917 int n = total_saved_regs_space;
7918 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7919 save_schedule schedule;
7922 n += total_auto_space;
7924 /* If it wasn't saved, there's not much we can do. */
7925 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7928 target_flags = copy_flags;
7930 sh5_schedule_saves (&live_regs_mask, &schedule, n);
7931 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
7932 if (entry->reg == pr_reg)
7934 target_flags = save_flags;
7935 return entry->offset;
7940 return total_auto_space;
7943 /* Parse the -mfixed-range= option string. */
7945 sh_fix_range (const char *const_str)
7948 char *str, *dash, *comma;
7950 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
7951 REG2 are either register names or register numbers. The effect
7952 of this option is to mark the registers in the range from REG1 to
7953 REG2 as ``fixed'' so they won't be used by the compiler. */
7955 i = strlen (const_str);
7956 str = (char *) alloca (i + 1);
7957 memcpy (str, const_str, i + 1);
7961 dash = strchr (str, '-');
7964 warning (0, "value of -mfixed-range must have form REG1-REG2");
7968 comma = strchr (dash + 1, ',');
7972 first = decode_reg_name (str);
7975 warning (0, "unknown register name: %s", str);
7979 last = decode_reg_name (dash + 1);
7982 warning (0, "unknown register name: %s", dash + 1);
7990 warning (0, "%s-%s is an empty range", str, dash + 1);
7994 for (i = first; i <= last; ++i)
7995 fixed_regs[i] = call_used_regs[i] = 1;
8005 /* Insert any deferred function attributes from earlier pragmas. */
8007 sh_insert_attributes (tree node, tree *attributes)
8011 if (TREE_CODE (node) != FUNCTION_DECL)
8014 /* We are only interested in fields. */
8018 /* Append the attributes to the deferred attributes. */
8019 *sh_deferred_function_attributes_tail = *attributes;
8020 attrs = sh_deferred_function_attributes;
8024 /* Some attributes imply or require the interrupt attribute. */
8025 if (!lookup_attribute ("interrupt_handler", attrs)
8026 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8028 /* If we have a trapa_handler, but no interrupt_handler attribute,
8029 insert an interrupt_handler attribute. */
8030 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8031 /* We can't use sh_pr_interrupt here because that's not in the
8034 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8035 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8036 if the interrupt attribute is missing, we ignore the attribute
8038 else if (lookup_attribute ("sp_switch", attrs)
8039 || lookup_attribute ("trap_exit", attrs)
8040 || lookup_attribute ("nosave_low_regs", attrs)
8041 || lookup_attribute ("resbank", attrs))
8045 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8047 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8048 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8049 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8050 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8051 warning (OPT_Wattributes,
8052 "%qs attribute only applies to interrupt functions",
8053 IDENTIFIER_POINTER (TREE_PURPOSE (attrs)));
8056 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8058 tail = &TREE_CHAIN (*tail);
8061 attrs = *attributes;
8065 /* Install the processed list. */
8066 *attributes = attrs;
8068 /* Clear deferred attributes. */
8069 sh_deferred_function_attributes = NULL_TREE;
8070 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8075 /* Supported attributes:
8077 interrupt_handler -- specifies this function is an interrupt handler.
8079 trapa_handler - like above, but don't save all registers.
8081 sp_switch -- specifies an alternate stack for an interrupt handler
8084 trap_exit -- use a trapa to exit an interrupt function instead of
8087 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8088 This is useful on the SH3 and upwards,
8089 which has a separate set of low regs for User and Supervisor modes.
8090 This should only be used for the lowest level of interrupts. Higher levels
8091 of interrupts must save the registers in case they themselves are
8094 renesas -- use Renesas calling/layout conventions (functions and
8097 resbank -- In case of an ISR, use a register bank to save registers
8098 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8101 const struct attribute_spec sh_attribute_table[] =
8103 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8104 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8105 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
8106 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
8107 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
8108 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8109 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8110 { "resbank", 0, 0, true, false, false, sh_handle_resbank_handler_attribute },
8111 { "function_vector", 1, 1, true, false, false, sh2a_handle_function_vector_handler_attribute },
8113 /* Symbian support adds three new attributes:
8114 dllexport - for exporting a function/variable that will live in a dll
8115 dllimport - for importing a function/variable from a dll
8117 Microsoft allows multiple declspecs in one __declspec, separating
8118 them with spaces. We do NOT support this. Instead, use __declspec
8120 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8121 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8123 { NULL, 0, 0, false, false, false, NULL }
8126 /* Handle a 'resbank' attribute. */
8128 sh_handle_resbank_handler_attribute (tree * node, tree name,
8129 tree args ATTRIBUTE_UNUSED,
8130 int flags ATTRIBUTE_UNUSED,
8131 bool * no_add_attrs)
8135 warning (OPT_Wattributes, "%qs attribute is supported only for SH2A",
8136 IDENTIFIER_POINTER (name));
8137 *no_add_attrs = true;
8139 if (TREE_CODE (*node) != FUNCTION_DECL)
8141 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8142 IDENTIFIER_POINTER (name));
8143 *no_add_attrs = true;
8149 /* Handle an "interrupt_handler" attribute; arguments as in
8150 struct attribute_spec.handler. */
8152 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8153 tree args ATTRIBUTE_UNUSED,
8154 int flags ATTRIBUTE_UNUSED,
8157 if (TREE_CODE (*node) != FUNCTION_DECL)
8159 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8160 IDENTIFIER_POINTER (name));
8161 *no_add_attrs = true;
8163 else if (TARGET_SHCOMPACT)
8165 error ("attribute interrupt_handler is not compatible with -m5-compact");
8166 *no_add_attrs = true;
8172 /* Handle an 'function_vector' attribute; arguments as in
8173 struct attribute_spec.handler. */
8175 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8176 tree args ATTRIBUTE_UNUSED,
8177 int flags ATTRIBUTE_UNUSED,
8178 bool * no_add_attrs)
8182 warning (OPT_Wattributes, "%qs attribute only applies to SH2A",
8183 IDENTIFIER_POINTER (name));
8184 *no_add_attrs = true;
8186 else if (TREE_CODE (*node) != FUNCTION_DECL)
8188 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8189 IDENTIFIER_POINTER (name));
8190 *no_add_attrs = true;
8192 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8194 /* The argument must be a constant integer. */
8195 warning (OPT_Wattributes,
8196 "`%s' attribute argument not an integer constant",
8197 IDENTIFIER_POINTER (name));
8198 *no_add_attrs = true;
8200 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8202 /* The argument value must be between 0 to 255. */
8203 warning (OPT_Wattributes,
8204 "`%s' attribute argument should be between 0 to 255",
8205 IDENTIFIER_POINTER (name));
8206 *no_add_attrs = true;
8211 /* Returns 1 if current function has been assigned the attribute
8212 'function_vector'. */
8214 sh2a_is_function_vector_call (rtx x)
8216 if (GET_CODE (x) == SYMBOL_REF
8217 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8219 tree tr = SYMBOL_REF_DECL (x);
8221 if (sh2a_function_vector_p (tr))
8228 /* Returns the function vector number, if the the attribute
8229 'function_vector' is assigned, otherwise returns zero. */
8231 sh2a_get_function_vector_number (rtx x)
8236 if ((GET_CODE (x) == SYMBOL_REF)
8237 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8239 t = SYMBOL_REF_DECL (x);
8241 if (TREE_CODE (t) != FUNCTION_DECL)
8244 list = SH_ATTRIBUTES (t);
8247 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8249 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8253 list = TREE_CHAIN (list);
8262 /* Handle an "sp_switch" attribute; arguments as in
8263 struct attribute_spec.handler. */
8265 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8266 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8268 if (TREE_CODE (*node) != FUNCTION_DECL)
8270 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8271 IDENTIFIER_POINTER (name));
8272 *no_add_attrs = true;
8274 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8276 /* The argument must be a constant string. */
8277 warning (OPT_Wattributes, "%qs attribute argument not a string constant",
8278 IDENTIFIER_POINTER (name));
8279 *no_add_attrs = true;
8285 /* Handle an "trap_exit" attribute; arguments as in
8286 struct attribute_spec.handler. */
8288 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8289 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8291 if (TREE_CODE (*node) != FUNCTION_DECL)
8293 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8294 IDENTIFIER_POINTER (name));
8295 *no_add_attrs = true;
8297 /* The argument specifies a trap number to be used in a trapa instruction
8298 at function exit (instead of an rte instruction). */
8299 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8301 /* The argument must be a constant integer. */
8302 warning (OPT_Wattributes, "%qs attribute argument not an "
8303 "integer constant", IDENTIFIER_POINTER (name));
8304 *no_add_attrs = true;
8311 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8312 tree name ATTRIBUTE_UNUSED,
8313 tree args ATTRIBUTE_UNUSED,
8314 int flags ATTRIBUTE_UNUSED,
8315 bool *no_add_attrs ATTRIBUTE_UNUSED)
8320 /* True if __attribute__((renesas)) or -mrenesas. */
8322 sh_attr_renesas_p (const_tree td)
8329 td = TREE_TYPE (td);
8330 if (td == error_mark_node)
8332 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8336 /* True if __attribute__((renesas)) or -mrenesas, for the current
8339 sh_cfun_attr_renesas_p (void)
8341 return sh_attr_renesas_p (current_function_decl);
8345 sh_cfun_interrupt_handler_p (void)
8347 return (lookup_attribute ("interrupt_handler",
8348 DECL_ATTRIBUTES (current_function_decl))
8352 /* Returns 1 if FUNC has been assigned the attribute
8353 "function_vector". */
8355 sh2a_function_vector_p (tree func)
8358 if (TREE_CODE (func) != FUNCTION_DECL)
8361 list = SH_ATTRIBUTES (func);
8364 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8367 list = TREE_CHAIN (list);
8372 /* Returns TRUE if given tree has the "resbank" attribute. */
8375 sh_cfun_resbank_handler_p (void)
8377 return ((lookup_attribute ("resbank",
8378 DECL_ATTRIBUTES (current_function_decl))
8380 && (lookup_attribute ("interrupt_handler",
8381 DECL_ATTRIBUTES (current_function_decl))
8382 != NULL_TREE) && TARGET_SH2A);
8385 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8388 sh_check_pch_target_flags (int old_flags)
8390 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8391 | MASK_SH_E | MASK_HARD_SH4
8392 | MASK_FPU_SINGLE | MASK_SH4))
8393 return _("created and used with different architectures / ABIs");
8394 if ((old_flags ^ target_flags) & MASK_HITACHI)
8395 return _("created and used with different ABIs");
8396 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8397 return _("created and used with different endianness");
8401 /* Predicates used by the templates. */
8403 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
8404 Used only in general_movsrc_operand. */
8407 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8419 /* Nonzero if OP is a floating point value with value 0.0. */
8422 fp_zero_operand (rtx op)
8426 if (GET_MODE (op) != SFmode)
8429 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8430 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
8433 /* Nonzero if OP is a floating point value with value 1.0. */
8436 fp_one_operand (rtx op)
8440 if (GET_MODE (op) != SFmode)
8443 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8444 return REAL_VALUES_EQUAL (r, dconst1);
8447 /* For -m4 and -m4-single-only, mode switching is used. If we are
8448 compiling without -mfmovd, movsf_ie isn't taken into account for
8449 mode switching. We could check in machine_dependent_reorg for
8450 cases where we know we are in single precision mode, but there is
8451 interface to find that out during reload, so we must avoid
8452 choosing an fldi alternative during reload and thus failing to
8453 allocate a scratch register for the constant loading. */
8457 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
8461 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8463 enum rtx_code code = GET_CODE (op);
8464 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
8467 /* Return the TLS type for TLS symbols, 0 for otherwise. */
8469 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8471 if (GET_CODE (op) != SYMBOL_REF)
8473 return SYMBOL_REF_TLS_MODEL (op);
8476 /* Return the destination address of a branch. */
8479 branch_dest (rtx branch)
8481 rtx dest = SET_SRC (PATTERN (branch));
8484 if (GET_CODE (dest) == IF_THEN_ELSE)
8485 dest = XEXP (dest, 1);
8486 dest = XEXP (dest, 0);
8487 dest_uid = INSN_UID (dest);
8488 return INSN_ADDRESSES (dest_uid);
8491 /* Return nonzero if REG is not used after INSN.
8492 We assume REG is a reload reg, and therefore does
8493 not live past labels. It may live past calls or jumps though. */
8495 reg_unused_after (rtx reg, rtx insn)
8500 /* If the reg is set by this instruction, then it is safe for our
8501 case. Disregard the case where this is a store to memory, since
8502 we are checking a register used in the store address. */
8503 set = single_set (insn);
8504 if (set && GET_CODE (SET_DEST (set)) != MEM
8505 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8508 while ((insn = NEXT_INSN (insn)))
8514 code = GET_CODE (insn);
8517 /* If this is a label that existed before reload, then the register
8518 if dead here. However, if this is a label added by reorg, then
8519 the register may still be live here. We can't tell the difference,
8520 so we just ignore labels completely. */
8521 if (code == CODE_LABEL)
8526 if (code == JUMP_INSN)
8529 /* If this is a sequence, we must handle them all at once.
8530 We could have for instance a call that sets the target register,
8531 and an insn in a delay slot that uses the register. In this case,
8532 we must return 0. */
8533 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
8538 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8540 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
8541 rtx set = single_set (this_insn);
8543 if (GET_CODE (this_insn) == CALL_INSN)
8545 else if (GET_CODE (this_insn) == JUMP_INSN)
8547 if (INSN_ANNULLED_BRANCH_P (this_insn))
8552 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8554 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8556 if (GET_CODE (SET_DEST (set)) != MEM)
8562 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
8567 else if (code == JUMP_INSN)
8571 set = single_set (insn);
8572 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8574 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8575 return GET_CODE (SET_DEST (set)) != MEM;
8576 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
8579 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
8587 static GTY(()) rtx fpscr_rtx;
8589 get_fpscr_rtx (void)
8593 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
8594 REG_USERVAR_P (fpscr_rtx) = 1;
8595 mark_user_reg (fpscr_rtx);
8597 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
8598 mark_user_reg (fpscr_rtx);
8602 static GTY(()) tree fpscr_values;
8605 emit_fpu_switch (rtx scratch, int index)
8609 if (fpscr_values == NULL)
8613 t = build_index_type (integer_one_node);
8614 t = build_array_type (integer_type_node, t);
8615 t = build_decl (VAR_DECL, get_identifier ("__fpscr_values"), t);
8616 DECL_ARTIFICIAL (t) = 1;
8617 DECL_IGNORED_P (t) = 1;
8618 DECL_EXTERNAL (t) = 1;
8619 TREE_STATIC (t) = 1;
8620 TREE_PUBLIC (t) = 1;
8626 src = DECL_RTL (fpscr_values);
8627 if (!can_create_pseudo_p ())
8629 emit_move_insn (scratch, XEXP (src, 0));
8631 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
8632 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
8635 src = adjust_address (src, PSImode, index * 4);
8637 dst = get_fpscr_rtx ();
8638 emit_move_insn (dst, src);
8642 emit_sf_insn (rtx pat)
8648 emit_df_insn (rtx pat)
8654 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8656 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8660 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8662 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
8667 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8669 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8673 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8675 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
8679 static rtx get_free_reg (HARD_REG_SET);
8681 /* This function returns a register to use to load the address to load
8682 the fpscr from. Currently it always returns r1 or r7, but when we are
8683 able to use pseudo registers after combine, or have a better mechanism
8684 for choosing a register, it should be done here. */
8685 /* REGS_LIVE is the liveness information for the point for which we
8686 need this allocation. In some bare-bones exit blocks, r1 is live at the
8687 start. We can even have all of r0..r3 being live:
8688 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
8689 INSN before which new insns are placed with will clobber the register
8690 we return. If a basic block consists only of setting the return value
8691 register to a pseudo and using that register, the return value is not
8692 live before or after this block, yet we we'll insert our insns right in
8696 get_free_reg (HARD_REG_SET regs_live)
8698 if (! TEST_HARD_REG_BIT (regs_live, 1))
8699 return gen_rtx_REG (Pmode, 1);
8701 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
8702 there shouldn't be anything but a jump before the function end. */
8703 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
8704 return gen_rtx_REG (Pmode, 7);
8707 /* This function will set the fpscr from memory.
8708 MODE is the mode we are setting it to. */
8710 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
8712 enum attr_fp_mode fp_mode = mode;
8713 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
8716 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
8717 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
8720 /* Is the given character a logical line separator for the assembler? */
8721 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
8722 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
8726 sh_insn_length_adjustment (rtx insn)
8728 /* Instructions with unfilled delay slots take up an extra two bytes for
8729 the nop in the delay slot. */
8730 if (((GET_CODE (insn) == INSN
8731 && GET_CODE (PATTERN (insn)) != USE
8732 && GET_CODE (PATTERN (insn)) != CLOBBER)
8733 || GET_CODE (insn) == CALL_INSN
8734 || (GET_CODE (insn) == JUMP_INSN
8735 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8736 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
8737 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
8738 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
8741 /* SH2e has a bug that prevents the use of annulled branches, so if
8742 the delay slot is not filled, we'll have to put a NOP in it. */
8743 if (sh_cpu_attr == CPU_SH2E
8744 && GET_CODE (insn) == JUMP_INSN
8745 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8746 && GET_CODE (PATTERN (insn)) != ADDR_VEC
8747 && get_attr_type (insn) == TYPE_CBRANCH
8748 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
8751 /* sh-dsp parallel processing insn take four bytes instead of two. */
8753 if (GET_CODE (insn) == INSN)
8756 rtx body = PATTERN (insn);
8759 int maybe_label = 1;
8761 if (GET_CODE (body) == ASM_INPUT)
8762 templ = XSTR (body, 0);
8763 else if (asm_noperands (body) >= 0)
8765 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
8774 while (c == ' ' || c == '\t');
8775 /* all sh-dsp parallel-processing insns start with p.
8776 The only non-ppi sh insn starting with p is pref.
8777 The only ppi starting with pr is prnd. */
8778 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
8780 /* The repeat pseudo-insn expands two three insns, a total of
8781 six bytes in size. */
8782 else if ((c == 'r' || c == 'R')
8783 && ! strncasecmp ("epeat", templ, 5))
8785 while (c && c != '\n'
8786 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
8788 /* If this is a label, it is obviously not a ppi insn. */
8789 if (c == ':' && maybe_label)
8794 else if (c == '\'' || c == '"')
8799 maybe_label = c != ':';
8807 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
8808 isn't protected by a PIC unspec. */
8810 nonpic_symbol_mentioned_p (rtx x)
8812 register const char *fmt;
8815 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
8816 || GET_CODE (x) == PC)
8819 /* We don't want to look into the possible MEM location of a
8820 CONST_DOUBLE, since we're not going to use it, in general. */
8821 if (GET_CODE (x) == CONST_DOUBLE)
8824 if (GET_CODE (x) == UNSPEC
8825 && (XINT (x, 1) == UNSPEC_PIC
8826 || XINT (x, 1) == UNSPEC_GOT
8827 || XINT (x, 1) == UNSPEC_GOTOFF
8828 || XINT (x, 1) == UNSPEC_GOTPLT
8829 || XINT (x, 1) == UNSPEC_GOTTPOFF
8830 || XINT (x, 1) == UNSPEC_DTPOFF
8831 || XINT (x, 1) == UNSPEC_PLT
8832 || XINT (x, 1) == UNSPEC_SYMOFF
8833 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
8836 fmt = GET_RTX_FORMAT (GET_CODE (x));
8837 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8843 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8844 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
8847 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
8854 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
8855 @GOTOFF in `reg'. */
8857 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
8860 if (tls_symbolic_operand (orig, Pmode))
8863 if (GET_CODE (orig) == LABEL_REF
8864 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
8867 reg = gen_reg_rtx (Pmode);
8869 emit_insn (gen_symGOTOFF2reg (reg, orig));
8872 else if (GET_CODE (orig) == SYMBOL_REF)
8875 reg = gen_reg_rtx (Pmode);
8877 emit_insn (gen_symGOT2reg (reg, orig));
8883 /* Mark the use of a constant in the literal table. If the constant
8884 has multiple labels, make it unique. */
8886 mark_constant_pool_use (rtx x)
8888 rtx insn, lab, pattern;
8893 switch (GET_CODE (x))
8903 /* Get the first label in the list of labels for the same constant
8904 and delete another labels in the list. */
8906 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
8908 if (GET_CODE (insn) != CODE_LABEL
8909 || LABEL_REFS (insn) != NEXT_INSN (insn))
8914 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
8915 INSN_DELETED_P (insn) = 1;
8917 /* Mark constants in a window. */
8918 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
8920 if (GET_CODE (insn) != INSN)
8923 pattern = PATTERN (insn);
8924 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
8927 switch (XINT (pattern, 1))
8929 case UNSPECV_CONST2:
8930 case UNSPECV_CONST4:
8931 case UNSPECV_CONST8:
8932 XVECEXP (pattern, 0, 1) = const1_rtx;
8934 case UNSPECV_WINDOW_END:
8935 if (XVECEXP (pattern, 0, 0) == x)
8938 case UNSPECV_CONST_END:
8948 /* Return true if it's possible to redirect BRANCH1 to the destination
8949 of an unconditional jump BRANCH2. We only want to do this if the
8950 resulting branch will have a short displacement. */
8952 sh_can_redirect_branch (rtx branch1, rtx branch2)
8954 if (flag_expensive_optimizations && simplejump_p (branch2))
8956 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
8960 for (distance = 0, insn = NEXT_INSN (branch1);
8961 insn && distance < 256;
8962 insn = PREV_INSN (insn))
8967 distance += get_attr_length (insn);
8969 for (distance = 0, insn = NEXT_INSN (branch1);
8970 insn && distance < 256;
8971 insn = NEXT_INSN (insn))
8976 distance += get_attr_length (insn);
8982 /* Return nonzero if register old_reg can be renamed to register new_reg. */
8984 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
8985 unsigned int new_reg)
8987 /* Interrupt functions can only use registers that have already been
8988 saved by the prologue, even if they would normally be
8991 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
8997 /* Function to update the integer COST
8998 based on the relationship between INSN that is dependent on
8999 DEP_INSN through the dependence LINK. The default is to make no
9000 adjustment to COST. This can be used for example to specify to
9001 the scheduler that an output- or anti-dependence does not incur
9002 the same cost as a data-dependence. The return value should be
9003 the new value for COST. */
9005 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
9011 /* On SHmedia, if the dependence is an anti-dependence or
9012 output-dependence, there is no cost. */
9013 if (REG_NOTE_KIND (link) != 0)
9015 /* However, dependencies between target register loads and
9016 uses of the register in a subsequent block that are separated
9017 by a conditional branch are not modelled - we have to do with
9018 the anti-dependency between the target register load and the
9019 conditional branch that ends the current block. */
9020 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
9021 && GET_CODE (PATTERN (dep_insn)) == SET
9022 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
9023 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
9024 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
9026 int orig_cost = cost;
9027 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
9028 rtx target = ((! note
9029 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
9030 ? insn : JUMP_LABEL (insn));
9031 /* On the likely path, the branch costs 1, on the unlikely path,
9035 target = next_active_insn (target);
9036 while (target && ! flow_dependent_p (target, dep_insn)
9038 /* If two branches are executed in immediate succession, with the
9039 first branch properly predicted, this causes a stall at the
9040 second branch, hence we won't need the target for the
9041 second branch for two cycles after the launch of the first
9043 if (cost > orig_cost - 2)
9044 cost = orig_cost - 2;
9050 else if (get_attr_is_mac_media (insn)
9051 && get_attr_is_mac_media (dep_insn))
9054 else if (! reload_completed
9055 && GET_CODE (PATTERN (insn)) == SET
9056 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
9057 && GET_CODE (PATTERN (dep_insn)) == SET
9058 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
9061 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
9062 that is needed at the target. */
9063 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
9064 && ! flow_dependent_p (insn, dep_insn))
9067 else if (REG_NOTE_KIND (link) == 0)
9069 enum attr_type type;
9072 if (recog_memoized (insn) < 0
9073 || recog_memoized (dep_insn) < 0)
9076 dep_set = single_set (dep_insn);
9078 /* The latency that we specify in the scheduling description refers
9079 to the actual output, not to an auto-increment register; for that,
9080 the latency is one. */
9081 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9083 rtx set = single_set (insn);
9086 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9087 && (!MEM_P (SET_DEST (set))
9088 || !reg_mentioned_p (SET_DEST (dep_set),
9089 XEXP (SET_DEST (set), 0))))
9092 /* The only input for a call that is timing-critical is the
9093 function's address. */
9094 if (GET_CODE (insn) == CALL_INSN)
9096 rtx call = PATTERN (insn);
9098 if (GET_CODE (call) == PARALLEL)
9099 call = XVECEXP (call, 0 ,0);
9100 if (GET_CODE (call) == SET)
9101 call = SET_SRC (call);
9102 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
9103 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9104 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9105 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9106 cost -= TARGET_SH4_300 ? 3 : 6;
9108 /* Likewise, the most timing critical input for an sfuncs call
9109 is the function address. However, sfuncs typically start
9110 using their arguments pretty quickly.
9111 Assume a four cycle delay for SH4 before they are needed.
9112 Cached ST40-300 calls are quicker, so assume only a one
9114 ??? Maybe we should encode the delays till input registers
9115 are needed by sfuncs into the sfunc call insn. */
9116 /* All sfunc calls are parallels with at least four components.
9117 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9118 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9119 && XVECLEN (PATTERN (insn), 0) >= 4
9120 && (reg = sfunc_uses_reg (insn)))
9122 if (! reg_set_p (reg, dep_insn))
9123 cost -= TARGET_SH4_300 ? 1 : 4;
9125 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9127 enum attr_type dep_type = get_attr_type (dep_insn);
9129 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9131 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9132 && (type = get_attr_type (insn)) != TYPE_CALL
9133 && type != TYPE_SFUNC)
9135 /* When the preceding instruction loads the shift amount of
9136 the following SHAD/SHLD, the latency of the load is increased
9138 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9139 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
9140 && reg_overlap_mentioned_p (SET_DEST (dep_set),
9141 XEXP (SET_SRC (single_set (insn)),
9144 /* When an LS group instruction with a latency of less than
9145 3 cycles is followed by a double-precision floating-point
9146 instruction, FIPR, or FTRV, the latency of the first
9147 instruction is increased to 3 cycles. */
9149 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9150 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9152 /* The lsw register of a double-precision computation is ready one
9154 else if (reload_completed
9155 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9156 && (use_pat = single_set (insn))
9157 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9161 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9162 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9165 else if (TARGET_SH4_300)
9167 /* Stores need their input register two cycles later. */
9168 if (dep_set && cost >= 1
9169 && ((type = get_attr_type (insn)) == TYPE_STORE
9170 || type == TYPE_PSTORE
9171 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9173 rtx set = single_set (insn);
9175 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9176 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9179 /* But don't reduce the cost below 1 if the address depends
9180 on a side effect of dep_insn. */
9182 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9188 /* An anti-dependence penalty of two applies if the first insn is a double
9189 precision fadd / fsub / fmul. */
9190 else if (!TARGET_SH4_300
9191 && REG_NOTE_KIND (link) == REG_DEP_ANTI
9192 && recog_memoized (dep_insn) >= 0
9193 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9194 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9195 /* A lot of alleged anti-flow dependences are fake,
9196 so check this one is real. */
9197 && flow_dependent_p (dep_insn, insn))
9203 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9204 if DEP_INSN is anti-flow dependent on INSN. */
9206 flow_dependent_p (rtx insn, rtx dep_insn)
9208 rtx tmp = PATTERN (insn);
9210 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9211 return tmp == NULL_RTX;
9214 /* A helper function for flow_dependent_p called through note_stores. */
9216 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9218 rtx * pinsn = (rtx *) data;
9220 if (*pinsn && reg_referenced_p (x, *pinsn))
9224 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9225 'special function' patterns (type sfunc) that clobber pr, but that
9226 do not look like function calls to leaf_function_p. Hence we must
9227 do this extra check. */
9231 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9234 /* Return where to allocate pseudo for a given hard register initial
9237 sh_allocate_initial_value (rtx hard_reg)
9241 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
9243 if (current_function_is_leaf
9244 && ! sh_pr_n_sets ()
9245 && ! (TARGET_SHCOMPACT
9246 && ((crtl->args.info.call_cookie
9247 & ~ CALL_COOKIE_RET_TRAMP (1))
9248 || crtl->saves_all_registers)))
9251 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
9259 /* This function returns "2" to indicate dual issue for the SH4
9260 processor. To be used by the DFA pipeline description. */
9262 sh_issue_rate (void)
9264 if (TARGET_SUPERSCALAR)
9270 /* Functions for ready queue reordering for sched1. */
9272 /* Get weight for mode for a set x. */
9274 find_set_regmode_weight (rtx x, enum machine_mode mode)
9276 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9278 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9280 if (GET_CODE (SET_DEST (x)) == REG)
9282 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9292 /* Get regmode weight for insn. */
9294 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
9296 short reg_weight = 0;
9299 /* Increment weight for each register born here. */
9301 reg_weight += find_set_regmode_weight (x, mode);
9302 if (GET_CODE (x) == PARALLEL)
9305 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9307 x = XVECEXP (PATTERN (insn), 0, j);
9308 reg_weight += find_set_regmode_weight (x, mode);
9311 /* Decrement weight for each register that dies here. */
9312 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9314 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9316 rtx note = XEXP (x, 0);
9317 if (GET_CODE (note) == REG && GET_MODE (note) == mode)
9324 /* Calculate regmode weights for all insns of a basic block. */
9326 find_regmode_weight (basic_block b, enum machine_mode mode)
9328 rtx insn, next_tail, head, tail;
9330 get_ebb_head_tail (b, b, &head, &tail);
9331 next_tail = NEXT_INSN (tail);
9333 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9335 /* Handle register life information. */
9340 INSN_REGMODE_WEIGHT (insn, mode) =
9341 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
9342 else if (mode == SImode)
9343 INSN_REGMODE_WEIGHT (insn, mode) =
9344 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
9348 /* Comparison function for ready queue sorting. */
9350 rank_for_reorder (const void *x, const void *y)
9352 rtx tmp = *(const rtx *) y;
9353 rtx tmp2 = *(const rtx *) x;
9355 /* The insn in a schedule group should be issued the first. */
9356 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
9357 return SCHED_GROUP_P (tmp2) ? 1 : -1;
9359 /* If insns are equally good, sort by INSN_LUID (original insn order), This
9360 minimizes instruction movement, thus minimizing sched's effect on
9361 register pressure. */
9362 return INSN_LUID (tmp) - INSN_LUID (tmp2);
9365 /* Resort the array A in which only element at index N may be out of order. */
9367 swap_reorder (rtx *a, int n)
9369 rtx insn = a[n - 1];
9372 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
9380 #define SCHED_REORDER(READY, N_READY) \
9383 if ((N_READY) == 2) \
9384 swap_reorder (READY, N_READY); \
9385 else if ((N_READY) > 2) \
9386 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
9390 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
9393 ready_reorder (rtx *ready, int nready)
9395 SCHED_REORDER (ready, nready);
9398 /* Count life regions of r0 for a block. */
9400 find_r0_life_regions (basic_block b)
9409 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
9422 r0_reg = gen_rtx_REG (SImode, R0_REG);
9427 if (find_regno_note (insn, REG_DEAD, R0_REG))
9433 && (pset = single_set (insn))
9434 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
9435 && !find_regno_note (insn, REG_UNUSED, R0_REG))
9443 insn = NEXT_INSN (insn);
9448 /* Calculate regmode weights for all insns of all basic block. */
9450 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
9451 int verbose ATTRIBUTE_UNUSED,
9456 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
9457 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
9458 r0_life_regions = 0;
9460 FOR_EACH_BB_REVERSE (b)
9462 find_regmode_weight (b, SImode);
9463 find_regmode_weight (b, SFmode);
9464 if (!reload_completed)
9465 r0_life_regions += find_r0_life_regions (b);
9468 CURR_REGMODE_PRESSURE (SImode) = 0;
9469 CURR_REGMODE_PRESSURE (SFmode) = 0;
9475 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
9476 int verbose ATTRIBUTE_UNUSED)
9478 if (regmode_weight[0])
9480 free (regmode_weight[0]);
9481 regmode_weight[0] = NULL;
9483 if (regmode_weight[1])
9485 free (regmode_weight[1]);
9486 regmode_weight[1] = NULL;
9490 /* The scalar modes supported differs from the default version in TImode
9491 for 32-bit SHMEDIA. */
9493 sh_scalar_mode_supported_p (enum machine_mode mode)
9495 if (TARGET_SHMEDIA32 && mode == TImode)
9498 return default_scalar_mode_supported_p (mode);
9501 /* Cache the can_issue_more so that we can return it from reorder2. Also,
9502 keep count of register pressures on SImode and SFmode. */
9504 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
9505 int sched_verbose ATTRIBUTE_UNUSED,
9509 if (GET_CODE (PATTERN (insn)) != USE
9510 && GET_CODE (PATTERN (insn)) != CLOBBER)
9511 cached_can_issue_more = can_issue_more - 1;
9513 cached_can_issue_more = can_issue_more;
9515 if (reload_completed)
9516 return cached_can_issue_more;
9518 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
9519 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
9521 return cached_can_issue_more;
9525 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
9526 int verbose ATTRIBUTE_UNUSED,
9527 int veclen ATTRIBUTE_UNUSED)
9529 CURR_REGMODE_PRESSURE (SImode) = 0;
9530 CURR_REGMODE_PRESSURE (SFmode) = 0;
9533 /* Some magic numbers. */
9534 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9535 functions that already have high pressure on r0. */
9536 #define R0_MAX_LIFE_REGIONS 2
9537 /* Register Pressure thresholds for SImode and SFmode registers. */
9538 #define SIMODE_MAX_WEIGHT 5
9539 #define SFMODE_MAX_WEIGHT 10
9541 /* Return true if the pressure is high for MODE. */
9543 high_pressure (enum machine_mode mode)
9545 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9546 functions that already have high pressure on r0. */
9547 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
9551 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
9553 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
9556 /* Reorder ready queue if register pressure is high. */
9558 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
9559 int sched_verbose ATTRIBUTE_UNUSED,
9562 int clock_var ATTRIBUTE_UNUSED)
9564 if (reload_completed)
9565 return sh_issue_rate ();
9567 if (high_pressure (SFmode) || high_pressure (SImode))
9569 ready_reorder (ready, *n_readyp);
9572 return sh_issue_rate ();
9575 /* Skip cycles if the current register pressure is high. */
9577 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
9578 int sched_verbose ATTRIBUTE_UNUSED,
9579 rtx *ready ATTRIBUTE_UNUSED,
9580 int *n_readyp ATTRIBUTE_UNUSED,
9581 int clock_var ATTRIBUTE_UNUSED)
9583 if (reload_completed)
9584 return cached_can_issue_more;
9586 if (high_pressure(SFmode) || high_pressure (SImode))
9589 return cached_can_issue_more;
9592 /* Skip cycles without sorting the ready queue. This will move insn from
9593 Q->R. If this is the last cycle we are skipping; allow sorting of ready
9594 queue by sh_reorder. */
9596 /* Generally, skipping these many cycles are sufficient for all insns to move
9601 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
9602 int sched_verbose ATTRIBUTE_UNUSED,
9603 rtx insn ATTRIBUTE_UNUSED,
9608 if (reload_completed)
9613 if ((clock_var - last_clock_var) < MAX_SKIPS)
9618 /* If this is the last cycle we are skipping, allow reordering of R. */
9619 if ((clock_var - last_clock_var) == MAX_SKIPS)
9631 /* SHmedia requires registers for branches, so we can't generate new
9632 branches past reload. */
9634 sh_cannot_modify_jumps_p (void)
9636 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
9640 sh_target_reg_class (void)
9642 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
9646 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
9653 if (! shmedia_space_reserved_for_target_registers)
9655 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
9657 if (calc_live_regs (&dummy) >= 6 * 8)
9663 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
9665 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
9669 On the SH1..SH4, the trampoline looks like
9670 2 0002 D202 mov.l l2,r2
9671 1 0000 D301 mov.l l1,r3
9674 5 0008 00000000 l1: .long area
9675 6 000c 00000000 l2: .long function
9677 SH5 (compact) uses r1 instead of r3 for the static chain. */
9680 /* Emit RTL insns to initialize the variable parts of a trampoline.
9681 FNADDR is an RTX for the address of the function's pure code.
9682 CXT is an RTX for the static chain value for the function. */
9685 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
9687 rtx tramp_mem = gen_frame_mem (BLKmode, tramp);
9689 if (TARGET_SHMEDIA64)
9694 rtx movi1 = GEN_INT (0xcc000010);
9695 rtx shori1 = GEN_INT (0xc8000010);
9698 /* The following trampoline works within a +- 128 KB range for cxt:
9699 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
9700 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
9701 gettr tr1,r1; blink tr0,r63 */
9702 /* Address rounding makes it hard to compute the exact bounds of the
9703 offset for this trampoline, but we have a rather generous offset
9704 range, so frame_offset should do fine as an upper bound. */
9705 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
9707 /* ??? could optimize this trampoline initialization
9708 by writing DImode words with two insns each. */
9709 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
9710 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
9711 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
9712 insn = gen_rtx_AND (DImode, insn, mask);
9713 /* Or in ptb/u .,tr1 pattern */
9714 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
9715 insn = force_operand (insn, NULL_RTX);
9716 insn = gen_lowpart (SImode, insn);
9717 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
9718 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
9719 insn = gen_rtx_AND (DImode, insn, mask);
9720 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
9721 insn = gen_lowpart (SImode, insn);
9722 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
9723 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
9724 insn = gen_rtx_AND (DImode, insn, mask);
9725 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9726 insn = gen_lowpart (SImode, insn);
9727 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
9728 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
9729 insn = gen_rtx_AND (DImode, insn, mask);
9730 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9731 insn = gen_lowpart (SImode, insn);
9732 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
9733 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
9734 insn = gen_rtx_AND (DImode, insn, mask);
9735 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9736 insn = gen_lowpart (SImode, insn);
9737 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
9738 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
9739 GEN_INT (0x6bf10600));
9740 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
9741 GEN_INT (0x4415fc10));
9742 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
9743 GEN_INT (0x4401fff0));
9744 emit_insn (gen_ic_invalidate_line (tramp));
9747 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
9748 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
9750 tramp_templ = gen_datalabel_ref (tramp_templ);
9752 src = gen_const_mem (BLKmode, tramp_templ);
9753 set_mem_align (dst, 256);
9754 set_mem_align (src, 64);
9755 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
9757 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
9758 emit_move_insn (adjust_address (tramp_mem, Pmode,
9759 fixed_len + GET_MODE_SIZE (Pmode)),
9761 emit_insn (gen_ic_invalidate_line (tramp));
9764 else if (TARGET_SHMEDIA)
9766 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
9767 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
9768 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
9769 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
9770 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
9771 rotated 10 right, and higher 16 bit of every 32 selected. */
9773 = force_reg (V2HImode, (simplify_gen_subreg
9774 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
9775 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
9776 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
9778 tramp = force_reg (Pmode, tramp);
9779 fnaddr = force_reg (SImode, fnaddr);
9780 cxt = force_reg (SImode, cxt);
9781 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
9782 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
9784 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
9785 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
9786 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
9787 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
9788 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
9789 gen_rtx_SUBREG (V2HImode, cxt, 0),
9791 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
9792 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
9793 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
9794 if (TARGET_LITTLE_ENDIAN)
9796 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
9797 emit_insn (gen_mextr4 (quad2, cxtload, blink));
9801 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
9802 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
9804 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
9805 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
9806 emit_insn (gen_ic_invalidate_line (tramp));
9809 else if (TARGET_SHCOMPACT)
9811 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
9814 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
9815 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
9817 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
9818 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
9820 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
9821 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
9824 if (!TARGET_INLINE_IC_INVALIDATE
9825 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
9826 emit_library_call (function_symbol (NULL, "__ic_invalidate",
9828 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
9830 emit_insn (gen_ic_invalidate_line (tramp));
9834 /* FIXME: This is overly conservative. A SHcompact function that
9835 receives arguments ``by reference'' will have them stored in its
9836 own stack frame, so it must not pass pointers or references to
9837 these arguments to other functions by means of sibling calls. */
9838 /* If PIC, we cannot make sibling calls to global functions
9839 because the PLT requires r12 to be live. */
9841 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
9844 && (! TARGET_SHCOMPACT
9845 || crtl->args.info.stack_regs == 0)
9846 && ! sh_cfun_interrupt_handler_p ()
9848 || (decl && ! TREE_PUBLIC (decl))
9849 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
9852 /* Machine specific built-in functions. */
9854 struct builtin_description
9856 const enum insn_code icode;
9857 const char *const name;
9861 /* describe number and signedness of arguments; arg[0] == result
9862 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
9863 /* 9: 64-bit pointer, 10: 32-bit pointer */
9864 static const char signature_args[][4] =
9866 #define SH_BLTIN_V2SI2 0
9868 #define SH_BLTIN_V4HI2 1
9870 #define SH_BLTIN_V2SI3 2
9872 #define SH_BLTIN_V4HI3 3
9874 #define SH_BLTIN_V8QI3 4
9876 #define SH_BLTIN_MAC_HISI 5
9878 #define SH_BLTIN_SH_HI 6
9880 #define SH_BLTIN_SH_SI 7
9882 #define SH_BLTIN_V4HI2V2SI 8
9884 #define SH_BLTIN_V4HI2V8QI 9
9886 #define SH_BLTIN_SISF 10
9888 #define SH_BLTIN_LDUA_L 11
9890 #define SH_BLTIN_LDUA_Q 12
9892 #define SH_BLTIN_STUA_L 13
9894 #define SH_BLTIN_STUA_Q 14
9896 #define SH_BLTIN_LDUA_L64 15
9898 #define SH_BLTIN_LDUA_Q64 16
9900 #define SH_BLTIN_STUA_L64 17
9902 #define SH_BLTIN_STUA_Q64 18
9904 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
9905 #define SH_BLTIN_2 19
9906 #define SH_BLTIN_SU 19
9908 #define SH_BLTIN_3 20
9909 #define SH_BLTIN_SUS 20
9911 #define SH_BLTIN_PSSV 21
9913 #define SH_BLTIN_XXUU 22
9914 #define SH_BLTIN_UUUU 22
9916 #define SH_BLTIN_PV 23
9919 /* mcmv: operands considered unsigned. */
9920 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
9921 /* mperm: control value considered unsigned int. */
9922 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
9923 /* mshards_q: returns signed short. */
9924 /* nsb: takes long long arg, returns unsigned char. */
9925 static const struct builtin_description bdesc[] =
9927 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
9928 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
9929 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
9930 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
9931 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
9932 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
9933 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
9934 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
9935 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
9936 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
9937 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
9938 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
9939 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
9940 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
9941 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
9942 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
9943 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
9944 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
9945 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 },
9946 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 },
9947 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 },
9948 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 },
9949 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 },
9950 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 },
9951 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 },
9952 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
9953 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
9954 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
9955 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
9956 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
9957 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
9958 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
9959 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
9960 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
9961 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
9962 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
9963 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
9964 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
9965 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
9966 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
9967 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
9968 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
9969 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
9970 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
9971 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
9972 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
9973 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
9974 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
9975 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
9976 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
9977 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
9978 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
9979 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
9980 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
9981 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
9982 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
9983 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
9984 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
9985 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
9986 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
9987 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
9988 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 },
9989 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 },
9990 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 },
9991 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
9992 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
9993 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
9994 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
9995 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
9996 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
9997 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
9998 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
9999 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
10000 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 },
10001 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 },
10002 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 },
10003 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 },
10004 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 },
10005 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 },
10006 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 },
10007 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 },
10008 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
10009 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
10010 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
10014 sh_media_init_builtins (void)
10016 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
10017 const struct builtin_description *d;
10019 memset (shared, 0, sizeof shared);
10020 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
10022 tree type, arg_type = 0;
10023 int signature = d->signature;
10026 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
10027 type = shared[signature];
10030 int has_result = signature_args[signature][0] != 0;
10032 if ((signature_args[signature][1] & 8)
10033 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
10034 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
10036 if (! TARGET_FPU_ANY
10037 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
10039 type = void_list_node;
10042 int arg = signature_args[signature][i];
10043 int opno = i - 1 + has_result;
10046 arg_type = ptr_type_node;
10048 arg_type = (*lang_hooks.types.type_for_mode)
10049 (insn_data[d->icode].operand[opno].mode,
10054 arg_type = void_type_node;
10057 type = tree_cons (NULL_TREE, arg_type, type);
10059 type = build_function_type (arg_type, type);
10060 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10061 shared[signature] = type;
10063 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10068 /* Implements target hook vector_mode_supported_p. */
10070 sh_vector_mode_supported_p (enum machine_mode mode)
10073 && ((mode == V2SFmode)
10074 || (mode == V4SFmode)
10075 || (mode == V16SFmode)))
10078 else if (TARGET_SHMEDIA
10079 && ((mode == V8QImode)
10080 || (mode == V2HImode)
10081 || (mode == V4HImode)
10082 || (mode == V2SImode)))
10088 /* Implements target hook dwarf_calling_convention. Return an enum
10089 of dwarf_calling_convention. */
10091 sh_dwarf_calling_convention (const_tree func)
10093 if (sh_attr_renesas_p (func))
10094 return DW_CC_GNU_renesas_sh;
10096 return DW_CC_normal;
10100 sh_init_builtins (void)
10102 if (TARGET_SHMEDIA)
10103 sh_media_init_builtins ();
10106 /* Expand an expression EXP that calls a built-in function,
10107 with result going to TARGET if that's convenient
10108 (and in mode MODE if that's convenient).
10109 SUBTARGET may be used as the target for computing one of EXP's operands.
10110 IGNORE is nonzero if the value is to be ignored. */
10113 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10114 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
10116 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10117 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10118 const struct builtin_description *d = &bdesc[fcode];
10119 enum insn_code icode = d->icode;
10120 int signature = d->signature;
10121 enum machine_mode tmode = VOIDmode;
10126 if (signature_args[signature][0])
10131 tmode = insn_data[icode].operand[0].mode;
10133 || GET_MODE (target) != tmode
10134 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10135 target = gen_reg_rtx (tmode);
10136 op[nop++] = target;
10141 for (i = 1; i <= 3; i++, nop++)
10144 enum machine_mode opmode, argmode;
10147 if (! signature_args[signature][i])
10149 arg = CALL_EXPR_ARG (exp, i - 1);
10150 if (arg == error_mark_node)
10152 if (signature_args[signature][i] & 8)
10155 optype = ptr_type_node;
10159 opmode = insn_data[icode].operand[nop].mode;
10160 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10162 argmode = TYPE_MODE (TREE_TYPE (arg));
10163 if (argmode != opmode)
10164 arg = build1 (NOP_EXPR, optype, arg);
10165 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
10166 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10167 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10173 pat = (*insn_data[d->icode].genfun) (op[0]);
10176 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10179 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10182 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10185 gcc_unreachable ();
10194 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
10196 rtx sel0 = const0_rtx;
10197 rtx sel1 = const1_rtx;
10198 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
10199 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
10201 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
10202 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
10206 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
10208 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
10210 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
10211 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
10214 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
10215 We can allow any mode in any general register. The special registers
10216 only allow SImode. Don't allow any mode in the PR.
10218 We cannot hold DCmode values in the XD registers because alter_reg
10219 handles subregs of them incorrectly. We could work around this by
10220 spacing the XD registers like the DR registers, but this would require
10221 additional memory in every compilation to hold larger register vectors.
10222 We could hold SFmode / SCmode values in XD registers, but that
10223 would require a tertiary reload when reloading from / to memory,
10224 and a secondary reload to reload from / to general regs; that
10225 seems to be a loosing proposition.
10227 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
10228 it won't be ferried through GP registers first. */
10231 sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
10233 if (SPECIAL_REGISTER_P (regno))
10234 return mode == SImode;
10236 if (regno == FPUL_REG)
10237 return (mode == SImode || mode == SFmode);
10239 if (FP_REGISTER_P (regno) && mode == SFmode)
10242 if (mode == V2SFmode)
10244 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
10245 || GENERAL_REGISTER_P (regno)))
10251 if (mode == V4SFmode)
10253 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
10254 || GENERAL_REGISTER_P (regno))
10260 if (mode == V16SFmode)
10262 if (TARGET_SHMEDIA)
10264 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
10270 return regno == FIRST_XD_REG;
10273 if (FP_REGISTER_P (regno))
10277 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
10278 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
10281 && (mode == DFmode || mode == DImode
10282 || mode == V2SFmode || mode == TImode)))
10283 && ((regno - FIRST_FP_REG) & 1) == 0)
10284 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
10285 && ((regno - FIRST_FP_REG) & 3) == 0))
10291 if (XD_REGISTER_P (regno))
10292 return mode == DFmode;
10294 if (TARGET_REGISTER_P (regno))
10295 return (mode == DImode || mode == SImode || mode == PDImode);
10297 if (regno == PR_REG)
10298 return mode == SImode;
10300 if (regno == FPSCR_REG)
10301 return mode == PSImode;
10303 /* FIXME. This works around PR target/37633 for -O0. */
10304 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
10306 unsigned int n = GET_MODE_SIZE (mode) / 8;
10308 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
10309 && regno <= FIRST_GENERAL_REG + 14)
10316 /* Return the class of registers for which a mode change from FROM to TO
10319 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
10320 enum reg_class rclass)
10322 /* We want to enable the use of SUBREGs as a means to
10323 VEC_SELECT a single element of a vector. */
10324 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
10325 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
10327 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10329 if (TARGET_LITTLE_ENDIAN)
10331 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
10332 return reg_classes_intersect_p (DF_REGS, rclass);
10336 if (GET_MODE_SIZE (from) < 8)
10337 return reg_classes_intersect_p (DF_HI_REGS, rclass);
10344 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10345 that label is used. */
10348 sh_mark_label (rtx address, int nuses)
10350 if (GOTOFF_P (address))
10352 /* Extract the label or symbol. */
10353 address = XEXP (address, 0);
10354 if (GET_CODE (address) == PLUS)
10355 address = XEXP (address, 0);
10356 address = XVECEXP (address, 0, 0);
10358 if (GET_CODE (address) == LABEL_REF
10359 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
10360 LABEL_NUSES (XEXP (address, 0)) += nuses;
10363 /* Compute extra cost of moving data between one register class
10366 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10367 uses this information. Hence, the general register <-> floating point
10368 register information here is not used for SFmode. */
10371 sh_register_move_cost (enum machine_mode mode,
10372 enum reg_class srcclass, enum reg_class dstclass)
10374 if (dstclass == T_REGS || dstclass == PR_REGS)
10377 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
10380 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
10381 && REGCLASS_HAS_FP_REG (srcclass)
10382 && REGCLASS_HAS_FP_REG (dstclass))
10385 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
10386 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
10388 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
10389 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
10392 if ((REGCLASS_HAS_FP_REG (dstclass)
10393 && REGCLASS_HAS_GENERAL_REG (srcclass))
10394 || (REGCLASS_HAS_GENERAL_REG (dstclass)
10395 && REGCLASS_HAS_FP_REG (srcclass)))
10396 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
10397 * ((GET_MODE_SIZE (mode) + 7) / 8U));
10399 if ((dstclass == FPUL_REGS
10400 && REGCLASS_HAS_GENERAL_REG (srcclass))
10401 || (srcclass == FPUL_REGS
10402 && REGCLASS_HAS_GENERAL_REG (dstclass)))
10405 if ((dstclass == FPUL_REGS
10406 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
10407 || (srcclass == FPUL_REGS
10408 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
10411 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10412 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10415 /* ??? ptabs faults on (value & 0x3) == 0x3 */
10417 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
10419 if (sh_gettrcost >= 0)
10420 return sh_gettrcost;
10421 else if (!TARGET_PT_FIXED)
10425 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10426 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10431 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
10432 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
10433 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
10435 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
10438 static rtx emit_load_ptr (rtx, rtx);
10441 emit_load_ptr (rtx reg, rtx addr)
10443 rtx mem = gen_const_mem (ptr_mode, addr);
10445 if (Pmode != ptr_mode)
10446 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
10447 return emit_move_insn (reg, mem);
10451 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
10452 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10455 CUMULATIVE_ARGS cum;
10456 int structure_value_byref = 0;
10457 rtx this_rtx, this_value, sibcall, insns, funexp;
10458 tree funtype = TREE_TYPE (function);
10459 int simple_add = CONST_OK_FOR_ADD (delta);
10461 rtx scratch0, scratch1, scratch2;
10464 reload_completed = 1;
10465 epilogue_completed = 1;
10466 current_function_uses_only_leaf_regs = 1;
10468 emit_note (NOTE_INSN_PROLOGUE_END);
10470 /* Find the "this" pointer. We have such a wide range of ABIs for the
10471 SH that it's best to do this completely machine independently.
10472 "this" is passed as first argument, unless a structure return pointer
10473 comes first, in which case "this" comes second. */
10474 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
10475 #ifndef PCC_STATIC_STRUCT_RETURN
10476 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10477 structure_value_byref = 1;
10478 #endif /* not PCC_STATIC_STRUCT_RETURN */
10479 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
10481 tree ptype = build_pointer_type (TREE_TYPE (funtype));
10483 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
10485 this_rtx = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
10487 /* For SHcompact, we only have r0 for a scratch register: r1 is the
10488 static chain pointer (even if you can't have nested virtual functions
10489 right now, someone might implement them sometime), and the rest of the
10490 registers are used for argument passing, are callee-saved, or reserved. */
10491 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
10492 -ffixed-reg has been used. */
10493 if (! call_used_regs[0] || fixed_regs[0])
10494 error ("r0 needs to be available as a call-clobbered register");
10495 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
10498 if (call_used_regs[1] && ! fixed_regs[1])
10499 scratch1 = gen_rtx_REG (ptr_mode, 1);
10500 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
10501 pointing where to return struct values. */
10502 if (call_used_regs[3] && ! fixed_regs[3])
10503 scratch2 = gen_rtx_REG (Pmode, 3);
10505 else if (TARGET_SHMEDIA)
10507 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
10508 if (i != REGNO (scratch0) &&
10509 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
10511 scratch1 = gen_rtx_REG (ptr_mode, i);
10514 if (scratch1 == scratch0)
10515 error ("Need a second call-clobbered general purpose register");
10516 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
10517 if (call_used_regs[i] && ! fixed_regs[i])
10519 scratch2 = gen_rtx_REG (Pmode, i);
10522 if (scratch2 == scratch0)
10523 error ("Need a call-clobbered target register");
10526 this_value = plus_constant (this_rtx, delta);
10528 && (simple_add || scratch0 != scratch1)
10529 && strict_memory_address_p (ptr_mode, this_value))
10531 emit_load_ptr (scratch0, this_value);
10536 ; /* Do nothing. */
10537 else if (simple_add)
10538 emit_move_insn (this_rtx, this_value);
10541 emit_move_insn (scratch1, GEN_INT (delta));
10542 emit_insn (gen_add2_insn (this_rtx, scratch1));
10550 emit_load_ptr (scratch0, this_rtx);
10552 offset_addr = plus_constant (scratch0, vcall_offset);
10553 if (strict_memory_address_p (ptr_mode, offset_addr))
10554 ; /* Do nothing. */
10555 else if (! TARGET_SH5 && scratch0 != scratch1)
10557 /* scratch0 != scratch1, and we have indexed loads. Get better
10558 schedule by loading the offset into r1 and using an indexed
10559 load - then the load of r1 can issue before the load from
10560 (this_rtx + delta) finishes. */
10561 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10562 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
10564 else if (CONST_OK_FOR_ADD (vcall_offset))
10566 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
10567 offset_addr = scratch0;
10569 else if (scratch0 != scratch1)
10571 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10572 emit_insn (gen_add2_insn (scratch0, scratch1));
10573 offset_addr = scratch0;
10576 gcc_unreachable (); /* FIXME */
10577 emit_load_ptr (scratch0, offset_addr);
10579 if (Pmode != ptr_mode)
10580 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
10581 emit_insn (gen_add2_insn (this_rtx, scratch0));
10584 /* Generate a tail call to the target function. */
10585 if (! TREE_USED (function))
10587 assemble_external (function);
10588 TREE_USED (function) = 1;
10590 funexp = XEXP (DECL_RTL (function), 0);
10591 /* If the function is overridden, so is the thunk, hence we don't
10592 need GOT addressing even if this is a public symbol. */
10594 if (TARGET_SH1 && ! flag_weak)
10595 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
10598 if (TARGET_SH2 && flag_pic)
10600 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
10601 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
10605 if (TARGET_SHMEDIA && flag_pic)
10607 funexp = gen_sym2PIC (funexp);
10608 PUT_MODE (funexp, Pmode);
10610 emit_move_insn (scratch2, funexp);
10611 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
10612 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
10614 sibcall = emit_call_insn (sibcall);
10615 SIBLING_CALL_P (sibcall) = 1;
10616 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
10619 /* Run just enough of rest_of_compilation to do scheduling and get
10620 the insns emitted. Note that use_thunk calls
10621 assemble_start_function and assemble_end_function. */
10623 insn_locators_alloc ();
10624 insns = get_insns ();
10629 /* Initialize the bitmap obstacks. */
10630 bitmap_obstack_initialize (NULL);
10631 bitmap_obstack_initialize (®_obstack);
10634 rtl_register_cfg_hooks ();
10635 init_rtl_bb_info (ENTRY_BLOCK_PTR);
10636 init_rtl_bb_info (EXIT_BLOCK_PTR);
10637 ENTRY_BLOCK_PTR->flags |= BB_RTL;
10638 EXIT_BLOCK_PTR->flags |= BB_RTL;
10639 find_basic_blocks (insns);
10641 if (flag_schedule_insns_after_reload)
10643 life_analysis (PROP_FINAL);
10645 split_all_insns (1);
10649 /* We must split jmp insn in PIC case. */
10651 split_all_insns_noflow ();
10658 split_all_insns_noflow ();
10664 if (optimize > 0 && flag_delayed_branch)
10665 dbr_schedule (insns);
10667 shorten_branches (insns);
10668 final_start_function (insns, file, 1);
10669 final (insns, file, 1);
10670 final_end_function ();
10671 free_after_compilation (cfun);
10673 reload_completed = 0;
10674 epilogue_completed = 0;
10678 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
10682 /* If this is not an ordinary function, the name usually comes from a
10683 string literal or an sprintf buffer. Make sure we use the same
10684 string consistently, so that cse will be able to unify address loads. */
10685 if (kind != FUNCTION_ORDINARY)
10686 name = IDENTIFIER_POINTER (get_identifier (name));
10687 sym = gen_rtx_SYMBOL_REF (Pmode, name);
10688 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
10692 case FUNCTION_ORDINARY:
10696 rtx reg = target ? target : gen_reg_rtx (Pmode);
10698 emit_insn (gen_symGOT2reg (reg, sym));
10704 /* ??? To allow cse to work, we use GOTOFF relocations.
10705 we could add combiner patterns to transform this into
10706 straight pc-relative calls with sym2PIC / bsrf when
10707 label load and function call are still 1:1 and in the
10708 same basic block during combine. */
10709 rtx reg = target ? target : gen_reg_rtx (Pmode);
10711 emit_insn (gen_symGOTOFF2reg (reg, sym));
10716 if (target && sym != target)
10718 emit_move_insn (target, sym);
10724 /* Find the number of a general purpose register in S. */
10726 scavenge_reg (HARD_REG_SET *s)
10729 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
10730 if (TEST_HARD_REG_BIT (*s, r))
10736 sh_get_pr_initial_val (void)
10740 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
10741 PR register on SHcompact, because it might be clobbered by the prologue.
10742 We check first if that is known to be the case. */
10743 if (TARGET_SHCOMPACT
10744 && ((crtl->args.info.call_cookie
10745 & ~ CALL_COOKIE_RET_TRAMP (1))
10746 || crtl->saves_all_registers))
10747 return gen_frame_mem (SImode, return_address_pointer_rtx);
10749 /* If we haven't finished rtl generation, there might be a nonlocal label
10750 that we haven't seen yet.
10751 ??? get_hard_reg_initial_val fails if it is called after register
10752 allocation has started, unless it has been called before for the
10753 same register. And even then, we end in trouble if we didn't use
10754 the register in the same basic block before. So call
10755 get_hard_reg_initial_val now and wrap it in an unspec if we might
10756 need to replace it. */
10757 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
10758 combine can put the pseudo returned by get_hard_reg_initial_val into
10759 instructions that need a general purpose registers, which will fail to
10760 be recognized when the pseudo becomes allocated to PR. */
10762 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
10764 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
10769 sh_expand_t_scc (enum rtx_code code, rtx target)
10771 rtx result = target;
10774 if (GET_CODE (sh_compare_op0) != REG || REGNO (sh_compare_op0) != T_REG
10775 || GET_CODE (sh_compare_op1) != CONST_INT)
10777 if (GET_CODE (result) != REG)
10778 result = gen_reg_rtx (SImode);
10779 val = INTVAL (sh_compare_op1);
10780 if ((code == EQ && val == 1) || (code == NE && val == 0))
10781 emit_insn (gen_movt (result));
10782 else if (TARGET_SH2A && ((code == EQ && val == 0)
10783 || (code == NE && val == 1)))
10784 emit_insn (gen_movrt (result));
10785 else if ((code == EQ && val == 0) || (code == NE && val == 1))
10787 emit_clobber (result);
10788 emit_insn (gen_subc (result, result, result));
10789 emit_insn (gen_addsi3 (result, result, const1_rtx));
10791 else if (code == EQ || code == NE)
10792 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
10795 if (result != target)
10796 emit_move_insn (target, result);
10800 /* INSN is an sfunc; return the rtx that describes the address used. */
10802 extract_sfunc_addr (rtx insn)
10804 rtx pattern, part = NULL_RTX;
10807 pattern = PATTERN (insn);
10808 len = XVECLEN (pattern, 0);
10809 for (i = 0; i < len; i++)
10811 part = XVECEXP (pattern, 0, i);
10812 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
10813 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
10814 return XEXP (part, 0);
10816 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
10817 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
10820 /* Verify that the register in use_sfunc_addr still agrees with the address
10821 used in the sfunc. This prevents fill_slots_from_thread from changing
10823 INSN is the use_sfunc_addr instruction, and REG is the register it
10826 check_use_sfunc_addr (rtx insn, rtx reg)
10828 /* Search for the sfunc. It should really come right after INSN. */
10829 while ((insn = NEXT_INSN (insn)))
10831 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN)
10833 if (! INSN_P (insn))
10836 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
10837 insn = XVECEXP (PATTERN (insn), 0, 0);
10838 if (GET_CODE (PATTERN (insn)) != PARALLEL
10839 || get_attr_type (insn) != TYPE_SFUNC)
10841 return rtx_equal_p (extract_sfunc_addr (insn), reg);
10843 gcc_unreachable ();
10846 /* This function returns a constant rtx that represents pi / 2**15 in
10847 SFmode. it's used to scale SFmode angles, in radians, to a
10848 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
10849 maps to 0x10000). */
10851 static GTY(()) rtx sh_fsca_sf2int_rtx;
10854 sh_fsca_sf2int (void)
10856 if (! sh_fsca_sf2int_rtx)
10858 REAL_VALUE_TYPE rv;
10860 real_from_string (&rv, "10430.378350470453");
10861 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
10864 return sh_fsca_sf2int_rtx;
10867 /* This function returns a constant rtx that represents pi / 2**15 in
10868 DFmode. it's used to scale DFmode angles, in radians, to a
10869 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
10870 maps to 0x10000). */
10872 static GTY(()) rtx sh_fsca_df2int_rtx;
10875 sh_fsca_df2int (void)
10877 if (! sh_fsca_df2int_rtx)
10879 REAL_VALUE_TYPE rv;
10881 real_from_string (&rv, "10430.378350470453");
10882 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
10885 return sh_fsca_df2int_rtx;
10888 /* This function returns a constant rtx that represents 2**15 / pi in
10889 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
10890 of a full circle back to a SFmode value, i.e., 0x10000 maps to
10893 static GTY(()) rtx sh_fsca_int2sf_rtx;
10896 sh_fsca_int2sf (void)
10898 if (! sh_fsca_int2sf_rtx)
10900 REAL_VALUE_TYPE rv;
10902 real_from_string (&rv, "9.587379924285257e-5");
10903 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
10906 return sh_fsca_int2sf_rtx;
10909 /* Initialize the CUMULATIVE_ARGS structure. */
10912 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
10914 rtx libname ATTRIBUTE_UNUSED,
10916 signed int n_named_args,
10917 enum machine_mode mode)
10919 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
10920 pcum->free_single_fp_reg = 0;
10921 pcum->stack_regs = 0;
10922 pcum->byref_regs = 0;
10924 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
10926 /* XXX - Should we check TARGET_HITACHI here ??? */
10927 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
10931 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
10932 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
10933 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
10934 pcum->arg_count [(int) SH_ARG_INT]
10935 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
10938 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
10939 && pcum->arg_count [(int) SH_ARG_INT] == 0
10940 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
10941 ? int_size_in_bytes (TREE_TYPE (fntype))
10942 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
10943 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
10944 == FIRST_RET_REG));
10948 pcum->arg_count [(int) SH_ARG_INT] = 0;
10949 pcum->prototype_p = FALSE;
10950 if (mode != VOIDmode)
10952 pcum->call_cookie =
10953 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
10954 && GET_MODE_SIZE (mode) > 4
10955 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
10957 /* If the default ABI is the Renesas ABI then all library
10958 calls must assume that the library will be using the
10959 Renesas ABI. So if the function would return its result
10960 in memory then we must force the address of this memory
10961 block onto the stack. Ideally we would like to call
10962 targetm.calls.return_in_memory() here but we do not have
10963 the TYPE or the FNDECL available so we synthesize the
10964 contents of that function as best we can. */
10966 (TARGET_DEFAULT & MASK_HITACHI)
10967 && (mode == BLKmode
10968 || (GET_MODE_SIZE (mode) > 4
10969 && !(mode == DFmode
10970 && TARGET_FPU_DOUBLE)));
10974 pcum->call_cookie = 0;
10975 pcum->force_mem = FALSE;
10980 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
10981 not enter into CONST_DOUBLE for the replace.
10983 Note that copying is not done so X must not be shared unless all copies
10984 are to be modified.
10986 This is like replace_rtx, except that we operate on N_REPLACEMENTS
10987 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
10988 replacements[n*2+1] - and that we take mode changes into account.
10990 If a replacement is ambiguous, return NULL_RTX.
10992 If MODIFY is zero, don't modify any rtl in place,
10993 just return zero or nonzero for failure / success. */
10996 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
11001 /* The following prevents loops occurrence when we change MEM in
11002 CONST_DOUBLE onto the same CONST_DOUBLE. */
11003 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
11006 for (i = n_replacements - 1; i >= 0 ; i--)
11007 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
11008 return replacements[i*2+1];
11010 /* Allow this function to make replacements in EXPR_LISTs. */
11014 if (GET_CODE (x) == SUBREG)
11016 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
11017 n_replacements, modify);
11019 if (GET_CODE (new_rtx) == CONST_INT)
11021 x = simplify_subreg (GET_MODE (x), new_rtx,
11022 GET_MODE (SUBREG_REG (x)),
11028 SUBREG_REG (x) = new_rtx;
11032 else if (GET_CODE (x) == REG)
11034 unsigned regno = REGNO (x);
11035 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
11036 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11037 rtx result = NULL_RTX;
11039 for (i = n_replacements - 1; i >= 0; i--)
11041 rtx from = replacements[i*2];
11042 rtx to = replacements[i*2+1];
11043 unsigned from_regno, from_nregs, to_regno, new_regno;
11045 if (GET_CODE (from) != REG)
11047 from_regno = REGNO (from);
11048 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
11049 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
11050 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
11052 if (regno < from_regno
11053 || regno + nregs > from_regno + nregs
11054 || GET_CODE (to) != REG
11057 to_regno = REGNO (to);
11058 if (to_regno < FIRST_PSEUDO_REGISTER)
11060 new_regno = regno + to_regno - from_regno;
11061 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
11064 result = gen_rtx_REG (GET_MODE (x), new_regno);
11066 else if (GET_MODE (x) <= GET_MODE (to))
11067 result = gen_lowpart_common (GET_MODE (x), to);
11069 result = gen_lowpart_SUBREG (GET_MODE (x), to);
11072 return result ? result : x;
11074 else if (GET_CODE (x) == ZERO_EXTEND)
11076 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
11077 n_replacements, modify);
11079 if (GET_CODE (new_rtx) == CONST_INT)
11081 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
11082 new_rtx, GET_MODE (XEXP (x, 0)));
11087 XEXP (x, 0) = new_rtx;
11092 fmt = GET_RTX_FORMAT (GET_CODE (x));
11093 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
11099 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
11100 n_replacements, modify);
11104 XEXP (x, i) = new_rtx;
11106 else if (fmt[i] == 'E')
11107 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11109 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
11110 n_replacements, modify);
11114 XVECEXP (x, i, j) = new_rtx;
11122 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
11124 enum rtx_code code = TRUNCATE;
11126 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
11128 rtx inner = XEXP (x, 0);
11129 enum machine_mode inner_mode = GET_MODE (inner);
11131 if (inner_mode == mode)
11133 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
11135 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
11136 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
11138 code = GET_CODE (x);
11142 return gen_rtx_fmt_e (code, mode, x);
11145 /* called via for_each_rtx after reload, to clean up truncates of
11146 registers that span multiple actual hard registers. */
11148 shmedia_cleanup_truncate (rtx *p, void *n_changes)
11152 if (GET_CODE (x) != TRUNCATE)
11155 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && GET_CODE (reg) == REG)
11157 enum machine_mode reg_mode = GET_MODE (reg);
11158 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
11159 subreg_lowpart_offset (DImode, reg_mode));
11160 *(int*) n_changes += 1;
11166 /* Load and store depend on the highpart of the address. However,
11167 set_attr_alternative does not give well-defined results before reload,
11168 so we must look at the rtl ourselves to see if any of the feeding
11169 registers is used in a memref. */
11171 /* Called by sh_contains_memref_p via for_each_rtx. */
11173 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
11175 return (GET_CODE (*loc) == MEM);
11178 /* Return nonzero iff INSN contains a MEM. */
11180 sh_contains_memref_p (rtx insn)
11182 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
11185 /* Return nonzero iff INSN loads a banked register. */
11187 sh_loads_bankedreg_p (rtx insn)
11189 if (GET_CODE (PATTERN (insn)) == SET)
11191 rtx op = SET_DEST (PATTERN(insn));
11192 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11199 /* FNADDR is the MEM expression from a call expander. Return an address
11200 to use in an SHmedia insn pattern. */
11202 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
11206 fnaddr = XEXP (fnaddr, 0);
11207 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
11208 if (flag_pic && is_sym)
11210 if (! SYMBOL_REF_LOCAL_P (fnaddr))
11212 rtx reg = gen_reg_rtx (Pmode);
11214 /* We must not use GOTPLT for sibcalls, because PIC_REG
11215 must be restored before the PLT code gets to run. */
11217 emit_insn (gen_symGOT2reg (reg, fnaddr));
11219 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
11224 fnaddr = gen_sym2PIC (fnaddr);
11225 PUT_MODE (fnaddr, Pmode);
11228 /* If ptabs might trap, make this visible to the rest of the compiler.
11229 We generally assume that symbols pertain to valid locations, but
11230 it is possible to generate invalid symbols with asm or linker tricks.
11231 In a list of functions where each returns its successor, an invalid
11232 symbol might denote an empty list. */
11233 if (!TARGET_PT_FIXED
11234 && (!is_sym || TARGET_INVALID_SYMBOLS)
11235 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
11237 rtx tr = gen_reg_rtx (PDImode);
11239 emit_insn (gen_ptabs (tr, fnaddr));
11242 else if (! target_reg_operand (fnaddr, Pmode))
11243 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
11248 sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
11249 enum machine_mode mode, secondary_reload_info *sri)
11253 if (REGCLASS_HAS_FP_REG (rclass)
11254 && ! TARGET_SHMEDIA
11255 && immediate_operand ((x), mode)
11256 && ! ((fp_zero_operand (x) || fp_one_operand (x))
11257 && mode == SFmode && fldi_ok ()))
11261 sri->icode = CODE_FOR_reload_insf__frn;
11264 sri->icode = CODE_FOR_reload_indf__frn;
11267 /* ??? If we knew that we are in the appropriate mode -
11268 single precision - we could use a reload pattern directly. */
11273 if (rclass == FPUL_REGS
11274 && ((GET_CODE (x) == REG
11275 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11276 || REGNO (x) == T_REG))
11277 || GET_CODE (x) == PLUS))
11278 return GENERAL_REGS;
11279 if (rclass == FPUL_REGS && immediate_operand (x, mode))
11281 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
11282 return GENERAL_REGS;
11283 else if (mode == SFmode)
11285 sri->icode = CODE_FOR_reload_insi__i_fpul;
11288 if (rclass == FPSCR_REGS
11289 && ((GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11290 || (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PLUS)))
11291 return GENERAL_REGS;
11292 if (REGCLASS_HAS_FP_REG (rclass)
11294 && immediate_operand (x, mode)
11295 && x != CONST0_RTX (GET_MODE (x))
11296 && GET_MODE (x) != V4SFmode)
11297 return GENERAL_REGS;
11298 if ((mode == QImode || mode == HImode)
11299 && TARGET_SHMEDIA && inqhi_operand (x, mode))
11301 sri->icode = ((mode == QImode)
11302 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
11305 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
11306 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
11307 return TARGET_REGS;
11308 } /* end of input-only processing. */
11310 if (((REGCLASS_HAS_FP_REG (rclass)
11311 && (GET_CODE (x) == REG
11312 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11313 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11314 && TARGET_FMOVD))))
11315 || (REGCLASS_HAS_GENERAL_REG (rclass)
11316 && GET_CODE (x) == REG
11317 && FP_REGISTER_P (REGNO (x))))
11318 && ! TARGET_SHMEDIA
11319 && (mode == SFmode || mode == SImode))
11321 if ((rclass == FPUL_REGS
11322 || (REGCLASS_HAS_FP_REG (rclass)
11323 && ! TARGET_SHMEDIA && mode == SImode))
11324 && (GET_CODE (x) == MEM
11325 || (GET_CODE (x) == REG
11326 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11327 || REGNO (x) == T_REG
11328 || system_reg_operand (x, VOIDmode)))))
11330 if (rclass == FPUL_REGS)
11331 return GENERAL_REGS;
11334 if ((rclass == TARGET_REGS
11335 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
11336 && !satisfies_constraint_Csy (x)
11337 && (GET_CODE (x) != REG || ! GENERAL_REGISTER_P (REGNO (x))))
11338 return GENERAL_REGS;
11339 if ((rclass == MAC_REGS || rclass == PR_REGS)
11340 && GET_CODE (x) == REG && ! GENERAL_REGISTER_P (REGNO (x))
11341 && rclass != REGNO_REG_CLASS (REGNO (x)))
11342 return GENERAL_REGS;
11343 if (rclass != GENERAL_REGS && GET_CODE (x) == REG
11344 && TARGET_REGISTER_P (REGNO (x)))
11345 return GENERAL_REGS;
11349 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;