1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
28 #include "insn-config.h"
36 #include "hard-reg-set.h"
38 #include "insn-attr.h"
42 #include "integrate.h"
45 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
52 #include "sched-int.h"
55 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
57 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
58 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
60 /* These are some macros to abstract register modes. */
61 #define CONST_OK_FOR_ADD(size) \
62 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
63 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
64 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
65 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
67 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
68 int current_function_interrupt;
70 /* ??? The pragma interrupt support will not work for SH3. */
71 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
72 output code for the next function appropriate for an interrupt handler. */
75 /* This is set by the trap_exit attribute for functions. It specifies
76 a trap number to be used in a trapa instruction at function exit
77 (instead of an rte instruction). */
80 /* This is used by the sp_switch attribute for functions. It specifies
81 a variable holding the address of the stack the interrupt function
82 should switch to/from at entry/exit. */
85 /* This is set by #pragma trapa, and is similar to the above, except that
86 the compiler doesn't emit code to preserve all registers. */
87 static int pragma_trapa;
89 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
90 which has a separate set of low regs for User and Supervisor modes.
91 This should only be used for the lowest level of interrupts. Higher levels
92 of interrupts must save the registers in case they themselves are
94 int pragma_nosave_low_regs;
96 /* This is used for communication between TARGET_SETUP_INCOMING_VARARGS and
97 sh_expand_prologue. */
98 int current_function_anonymous_args;
100 /* Global variables for machine-dependent things. */
102 /* Which cpu are we scheduling for. */
103 enum processor_type sh_cpu;
105 /* Definitions used in ready queue reordering for first scheduling pass. */
107 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
108 static short *regmode_weight[2];
110 /* Total SFmode and SImode weights of scheduled insns. */
111 static int curr_regmode_pressure[2];
113 /* If true, skip cycles for Q -> R movement. */
114 static int skip_cycles = 0;
116 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
117 and returned from sh_reorder2. */
118 static short cached_can_issue_more;
120 /* Saved operands from the last compare to use when we generate an scc
126 /* Provides the class number of the smallest class containing
129 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
131 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
132 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
133 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
135 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
136 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
137 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
138 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
139 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
140 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
141 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
142 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
143 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
144 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
145 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
146 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
147 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
148 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
149 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
152 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
153 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
154 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
155 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
156 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
157 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
158 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
159 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
160 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
161 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
162 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
163 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
164 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
165 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
166 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
167 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
168 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
172 char sh_register_names[FIRST_PSEUDO_REGISTER] \
173 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
175 char sh_additional_register_names[ADDREGNAMES_SIZE] \
176 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
177 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
179 /* Provide reg_class from a letter such as appears in the machine
180 description. *: target independently reserved letter.
181 reg_class_from_letter['e' - 'a'] is set to NO_REGS for TARGET_FMOVD. */
183 enum reg_class reg_class_from_letter[] =
185 /* a */ ALL_REGS, /* b */ TARGET_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
186 /* e */ FP_REGS, /* f */ FP_REGS, /* g **/ NO_REGS, /* h */ NO_REGS,
187 /* i **/ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
188 /* m **/ NO_REGS, /* n **/ NO_REGS, /* o **/ NO_REGS, /* p **/ NO_REGS,
189 /* q */ NO_REGS, /* r **/ NO_REGS, /* s **/ NO_REGS, /* t */ T_REGS,
190 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
191 /* y */ FPUL_REGS, /* z */ R0_REGS
194 int assembler_dialect;
196 static bool shmedia_space_reserved_for_target_registers;
198 static void split_branches (rtx);
199 static int branch_dest (rtx);
200 static void force_into (rtx, rtx);
201 static void print_slot (rtx);
202 static rtx add_constant (rtx, enum machine_mode, rtx);
203 static void dump_table (rtx);
204 static int hi_const (rtx);
205 static int broken_move (rtx);
206 static int mova_p (rtx);
207 static rtx find_barrier (int, rtx, rtx);
208 static int noncall_uses_reg (rtx, rtx, rtx *);
209 static rtx gen_block_redirect (rtx, int, int);
210 static void sh_reorg (void);
211 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
212 static rtx frame_insn (rtx);
213 static rtx push (int);
214 static void pop (int);
215 static void push_regs (HARD_REG_SET *, int);
216 static int calc_live_regs (HARD_REG_SET *);
217 static void mark_use (rtx, rtx *);
218 static HOST_WIDE_INT rounded_frame_size (int);
219 static rtx mark_constant_pool_use (rtx);
220 const struct attribute_spec sh_attribute_table[];
221 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
222 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
223 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
224 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
225 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
226 static void sh_insert_attributes (tree, tree *);
227 static int sh_adjust_cost (rtx, rtx, rtx, int);
228 static int sh_use_dfa_interface (void);
229 static int sh_issue_rate (void);
230 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
231 static short find_set_regmode_weight (rtx, enum machine_mode);
232 static short find_insn_regmode_weight (rtx, enum machine_mode);
233 static void find_regmode_weight (int, enum machine_mode);
234 static void sh_md_init_global (FILE *, int, int);
235 static void sh_md_finish_global (FILE *, int);
236 static int rank_for_reorder (const void *, const void *);
237 static void swap_reorder (rtx *, int);
238 static void ready_reorder (rtx *, int);
239 static short high_pressure (enum machine_mode);
240 static int sh_reorder (FILE *, int, rtx *, int *, int);
241 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
242 static void sh_md_init (FILE *, int, int);
243 static int sh_variable_issue (FILE *, int, rtx, int);
245 static bool sh_function_ok_for_sibcall (tree, tree);
247 static bool sh_cannot_modify_jumps_p (void);
248 static int sh_target_reg_class (void);
249 static bool sh_optimize_target_register_callee_saved (bool);
250 static bool sh_ms_bitfield_layout_p (tree);
252 static void sh_init_builtins (void);
253 static void sh_media_init_builtins (void);
254 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
255 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
256 static void sh_file_start (void);
257 static int flow_dependent_p (rtx, rtx);
258 static void flow_dependent_p_1 (rtx, rtx, void *);
259 static int shiftcosts (rtx);
260 static int andcosts (rtx);
261 static int addsubcosts (rtx);
262 static int multcosts (rtx);
263 static bool unspec_caller_rtx_p (rtx);
264 static bool sh_cannot_copy_insn_p (rtx);
265 static bool sh_rtx_costs (rtx, int, int, int *);
266 static int sh_address_cost (rtx);
267 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
268 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
269 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
270 static int scavenge_reg (HARD_REG_SET *s);
271 struct save_schedule_s;
272 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
273 struct save_schedule_s *, int);
275 static rtx sh_struct_value_rtx (tree, int);
276 static bool sh_return_in_memory (tree, tree);
277 static rtx sh_builtin_saveregs (void);
278 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
279 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
280 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
281 static tree sh_build_builtin_va_list (void);
284 /* Initialize the GCC target structure. */
285 #undef TARGET_ATTRIBUTE_TABLE
286 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
288 /* The next two are used for debug info when compiling with -gdwarf. */
289 #undef TARGET_ASM_UNALIGNED_HI_OP
290 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
291 #undef TARGET_ASM_UNALIGNED_SI_OP
292 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
294 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
295 #undef TARGET_ASM_UNALIGNED_DI_OP
296 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
297 #undef TARGET_ASM_ALIGNED_DI_OP
298 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
300 #undef TARGET_ASM_FUNCTION_EPILOGUE
301 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
303 #undef TARGET_ASM_OUTPUT_MI_THUNK
304 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
306 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
307 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
309 #undef TARGET_ASM_FILE_START
310 #define TARGET_ASM_FILE_START sh_file_start
311 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
312 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
314 #undef TARGET_INSERT_ATTRIBUTES
315 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
317 #undef TARGET_SCHED_ADJUST_COST
318 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
320 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
321 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
323 #undef TARGET_SCHED_ISSUE_RATE
324 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
326 /* The next 5 hooks have been implemented for reenabling sched1. With the
327 help of these macros we are limiting the movement of insns in sched1 to
328 reduce the register pressure. The overall idea is to keep count of SImode
329 and SFmode regs required by already scheduled insns. When these counts
330 cross some threshold values; give priority to insns that free registers.
331 The insn that frees registers is most likely to be the insn with lowest
332 LUID (original insn order); but such an insn might be there in the stalled
333 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
334 upto a max of 8 cycles so that such insns may move from Q -> R.
336 The description of the hooks are as below:
338 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
339 scheduler; it is called inside the sched_init function just after
340 find_insn_reg_weights function call. It is used to calculate the SImode
341 and SFmode weights of insns of basic blocks; much similar to what
342 find_insn_reg_weights does.
343 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
345 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
346 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
349 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
350 high; reorder the ready queue so that the insn with lowest LUID will be
353 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
354 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
356 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
357 can be returned from TARGET_SCHED_REORDER2.
359 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
361 #undef TARGET_SCHED_DFA_NEW_CYCLE
362 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
364 #undef TARGET_SCHED_INIT_GLOBAL
365 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
367 #undef TARGET_SCHED_FINISH_GLOBAL
368 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
370 #undef TARGET_SCHED_VARIABLE_ISSUE
371 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
373 #undef TARGET_SCHED_REORDER
374 #define TARGET_SCHED_REORDER sh_reorder
376 #undef TARGET_SCHED_REORDER2
377 #define TARGET_SCHED_REORDER2 sh_reorder2
379 #undef TARGET_SCHED_INIT
380 #define TARGET_SCHED_INIT sh_md_init
382 #undef TARGET_CANNOT_MODIFY_JUMPS_P
383 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
384 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
385 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
386 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
387 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
388 sh_optimize_target_register_callee_saved
390 #undef TARGET_MS_BITFIELD_LAYOUT_P
391 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
393 #undef TARGET_INIT_BUILTINS
394 #define TARGET_INIT_BUILTINS sh_init_builtins
395 #undef TARGET_EXPAND_BUILTIN
396 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
398 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
399 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
401 #undef TARGET_CANNOT_COPY_INSN_P
402 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
403 #undef TARGET_RTX_COSTS
404 #define TARGET_RTX_COSTS sh_rtx_costs
405 #undef TARGET_ADDRESS_COST
406 #define TARGET_ADDRESS_COST sh_address_cost
408 #undef TARGET_MACHINE_DEPENDENT_REORG
409 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
412 #undef TARGET_HAVE_TLS
413 #define TARGET_HAVE_TLS true
416 #undef TARGET_PROMOTE_PROTOTYPES
417 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
418 #undef TARGET_PROMOTE_FUNCTION_ARGS
419 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
420 #undef TARGET_PROMOTE_FUNCTION_RETURN
421 #define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
423 #undef TARGET_STRUCT_VALUE_RTX
424 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
425 #undef TARGET_RETURN_IN_MEMORY
426 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
428 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
429 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
430 #undef TARGET_SETUP_INCOMING_VARARGS
431 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
432 #undef TARGET_STRICT_ARGUMENT_NAMING
433 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
434 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
435 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
437 #undef TARGET_BUILD_BUILTIN_VA_LIST
438 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
440 #undef TARGET_PCH_VALID_P
441 #define TARGET_PCH_VALID_P sh_pch_valid_p
443 /* Return regmode weight for insn. */
444 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
446 /* Return current register pressure for regmode. */
447 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
449 struct gcc_target targetm = TARGET_INITIALIZER;
451 /* Print the operand address in x to the stream. */
454 print_operand_address (FILE *stream, rtx x)
456 switch (GET_CODE (x))
460 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
465 rtx base = XEXP (x, 0);
466 rtx index = XEXP (x, 1);
468 switch (GET_CODE (index))
471 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
472 reg_names[true_regnum (base)]);
478 int base_num = true_regnum (base);
479 int index_num = true_regnum (index);
481 fprintf (stream, "@(r0,%s)",
482 reg_names[MAX (base_num, index_num)]);
494 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
498 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
502 x = mark_constant_pool_use (x);
503 output_addr_const (stream, x);
508 /* Print operand x (an rtx) in assembler syntax to file stream
509 according to modifier code.
511 '.' print a .s if insn needs delay slot
512 ',' print LOCAL_LABEL_PREFIX
513 '@' print trap, rte or rts depending upon pragma interruptness
514 '#' output a nop if there is nothing to put in the delay slot
515 ''' print likelihood suffix (/u for unlikely).
516 'O' print a constant without the #
517 'R' print the LSW of a dp value - changes if in little endian
518 'S' print the MSW of a dp value - changes if in little endian
519 'T' print the next word of a dp value - same as 'R' in big endian mode.
520 'M' print an `x' if `m' will print `base,index'.
521 'N' print 'r63' if the operand is (const_int 0).
522 'm' print a pair `base,offset' or `base,index', for LD and ST.
523 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
524 'o' output an operator. */
527 print_operand (FILE *stream, rtx x, int code)
533 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
534 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
535 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
538 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
542 fprintf (stream, "trapa #%d", trap_exit);
543 else if (sh_cfun_interrupt_handler_p ())
544 fprintf (stream, "rte");
546 fprintf (stream, "rts");
549 /* Output a nop if there's nothing in the delay slot. */
550 if (dbr_sequence_length () == 0)
551 fprintf (stream, "\n\tnop");
555 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
557 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
558 fputs ("/u", stream);
562 x = mark_constant_pool_use (x);
563 output_addr_const (stream, x);
566 fputs (reg_names[REGNO (x) + LSW], (stream));
569 fputs (reg_names[REGNO (x) + MSW], (stream));
572 /* Next word of a double. */
573 switch (GET_CODE (x))
576 fputs (reg_names[REGNO (x) + 1], (stream));
579 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
580 && GET_CODE (XEXP (x, 0)) != POST_INC)
581 x = adjust_address (x, SImode, 4);
582 print_operand_address (stream, XEXP (x, 0));
589 switch (GET_CODE (x))
591 case PLUS: fputs ("add", stream); break;
592 case MINUS: fputs ("sub", stream); break;
593 case MULT: fputs ("mul", stream); break;
594 case DIV: fputs ("div", stream); break;
595 case EQ: fputs ("eq", stream); break;
596 case NE: fputs ("ne", stream); break;
597 case GT: case LT: fputs ("gt", stream); break;
598 case GE: case LE: fputs ("ge", stream); break;
599 case GTU: case LTU: fputs ("gtu", stream); break;
600 case GEU: case LEU: fputs ("geu", stream); break;
606 if (GET_CODE (x) == MEM
607 && GET_CODE (XEXP (x, 0)) == PLUS
608 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
609 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
614 if (GET_CODE (x) != MEM)
617 switch (GET_CODE (x))
621 print_operand (stream, x, 0);
622 fputs (", 0", stream);
626 print_operand (stream, XEXP (x, 0), 0);
627 fputs (", ", stream);
628 print_operand (stream, XEXP (x, 1), 0);
637 if (x == CONST0_RTX (GET_MODE (x)))
639 fprintf ((stream), "r63");
644 if (GET_CODE (x) == CONST_INT)
646 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
653 switch (GET_CODE (x))
655 /* FIXME: We need this on SHmedia32 because reload generates
656 some sign-extended HI or QI loads into DImode registers
657 but, because Pmode is SImode, the address ends up with a
658 subreg:SI of the DImode register. Maybe reload should be
659 fixed so as to apply alter_subreg to such loads? */
661 if (SUBREG_BYTE (x) != 0
662 || GET_CODE (SUBREG_REG (x)) != REG)
669 if (FP_REGISTER_P (REGNO (x))
670 && GET_MODE (x) == V16SFmode)
671 fprintf ((stream), "mtrx%s", reg_names[REGNO (x)] + 2);
672 else if (FP_REGISTER_P (REGNO (x))
673 && GET_MODE (x) == V4SFmode)
674 fprintf ((stream), "fv%s", reg_names[REGNO (x)] + 2);
675 else if (GET_CODE (x) == REG
676 && GET_MODE (x) == V2SFmode)
677 fprintf ((stream), "fp%s", reg_names[REGNO (x)] + 2);
678 else if (FP_REGISTER_P (REGNO (x))
679 && GET_MODE_SIZE (GET_MODE (x)) > 4)
680 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
682 fputs (reg_names[REGNO (x)], (stream));
686 output_address (XEXP (x, 0));
691 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
692 && GET_MODE (XEXP (x, 0)) == DImode
693 && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE
694 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)
696 rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0);
699 if (GET_CODE (val) == ASHIFTRT)
702 if (GET_CODE (XEXP (val, 0)) == CONST)
704 output_addr_const (stream, XEXP (val, 0));
705 if (GET_CODE (XEXP (val, 0)) == CONST)
707 fputs (" >> ", stream);
708 output_addr_const (stream, XEXP (val, 1));
713 if (GET_CODE (val) == CONST)
715 output_addr_const (stream, val);
716 if (GET_CODE (val) == CONST)
719 fputs (" & 65535)", stream);
727 output_addr_const (stream, x);
734 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
736 force_into (rtx value, rtx target)
738 value = force_operand (value, target);
739 if (! rtx_equal_p (value, target))
740 emit_insn (gen_move_insn (target, value));
743 /* Emit code to perform a block move. Choose the best method.
745 OPERANDS[0] is the destination.
746 OPERANDS[1] is the source.
747 OPERANDS[2] is the size.
748 OPERANDS[3] is the alignment safe to use. */
751 expand_block_move (rtx *operands)
753 int align = INTVAL (operands[3]);
754 int constp = (GET_CODE (operands[2]) == CONST_INT);
755 int bytes = (constp ? INTVAL (operands[2]) : 0);
757 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
758 alignment, or if it isn't a multiple of 4 bytes, then fail. */
759 if (! constp || align < 4 || (bytes % 4 != 0))
766 else if (bytes == 12)
771 rtx r4 = gen_rtx_REG (SImode, 4);
772 rtx r5 = gen_rtx_REG (SImode, 5);
774 entry_name = get_identifier ("__movstrSI12_i4");
776 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
777 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
778 force_into (XEXP (operands[0], 0), r4);
779 force_into (XEXP (operands[1], 0), r5);
780 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
783 else if (! TARGET_SMALLCODE)
789 rtx r4 = gen_rtx_REG (SImode, 4);
790 rtx r5 = gen_rtx_REG (SImode, 5);
791 rtx r6 = gen_rtx_REG (SImode, 6);
793 entry_name = get_identifier (bytes & 4
795 : "__movstr_i4_even");
796 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
797 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
798 force_into (XEXP (operands[0], 0), r4);
799 force_into (XEXP (operands[1], 0), r5);
802 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
803 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
815 rtx r4 = gen_rtx_REG (SImode, 4);
816 rtx r5 = gen_rtx_REG (SImode, 5);
818 sprintf (entry, "__movstrSI%d", bytes);
819 entry_name = get_identifier (entry);
820 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
821 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
822 force_into (XEXP (operands[0], 0), r4);
823 force_into (XEXP (operands[1], 0), r5);
824 emit_insn (gen_block_move_real (func_addr_rtx));
828 /* This is the same number of bytes as a memcpy call, but to a different
829 less common function name, so this will occasionally use more space. */
830 if (! TARGET_SMALLCODE)
835 int final_switch, while_loop;
836 rtx r4 = gen_rtx_REG (SImode, 4);
837 rtx r5 = gen_rtx_REG (SImode, 5);
838 rtx r6 = gen_rtx_REG (SImode, 6);
840 entry_name = get_identifier ("__movstr");
841 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
842 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
843 force_into (XEXP (operands[0], 0), r4);
844 force_into (XEXP (operands[1], 0), r5);
846 /* r6 controls the size of the move. 16 is decremented from it
847 for each 64 bytes moved. Then the negative bit left over is used
848 as an index into a list of move instructions. e.g., a 72 byte move
849 would be set up with size(r6) = 14, for one iteration through the
850 big while loop, and a switch of -2 for the last part. */
852 final_switch = 16 - ((bytes / 4) % 16);
853 while_loop = ((bytes / 4) / 16 - 1) * 16;
854 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
855 emit_insn (gen_block_lump_real (func_addr_rtx));
862 /* Prepare operands for a move define_expand; specifically, one of the
863 operands must be in a register. */
866 prepare_move_operands (rtx operands[], enum machine_mode mode)
868 if ((mode == SImode || mode == DImode)
870 && ! ((mode == Pmode || mode == ptr_mode)
871 && tls_symbolic_operand (operands[1], Pmode) != 0))
874 if (SYMBOLIC_CONST_P (operands[1]))
876 if (GET_CODE (operands[0]) == MEM)
877 operands[1] = force_reg (Pmode, operands[1]);
878 else if (TARGET_SHMEDIA
879 && GET_CODE (operands[1]) == LABEL_REF
880 && target_reg_operand (operands[0], mode))
884 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
885 operands[1] = legitimize_pic_address (operands[1], mode, temp);
888 else if (GET_CODE (operands[1]) == CONST
889 && GET_CODE (XEXP (operands[1], 0)) == PLUS
890 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
892 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
893 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
895 operands[1] = expand_binop (mode, add_optab, temp,
896 XEXP (XEXP (operands[1], 0), 1),
897 no_new_pseudos ? temp
898 : gen_reg_rtx (Pmode),
903 if (! reload_in_progress && ! reload_completed)
905 /* Copy the source to a register if both operands aren't registers. */
906 if (! register_operand (operands[0], mode)
907 && ! sh_register_operand (operands[1], mode))
908 operands[1] = copy_to_mode_reg (mode, operands[1]);
910 if (GET_CODE (operands[0]) == MEM && ! memory_operand (operands[0], mode))
912 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
913 except that we can't use that function because it is static. */
914 rtx new = change_address (operands[0], mode, 0);
915 MEM_COPY_ATTRIBUTES (new, operands[0]);
919 /* This case can happen while generating code to move the result
920 of a library call to the target. Reject `st r0,@(rX,rY)' because
921 reload will fail to find a spill register for rX, since r0 is already
922 being used for the source. */
923 else if (refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
924 && GET_CODE (operands[0]) == MEM
925 && GET_CODE (XEXP (operands[0], 0)) == PLUS
926 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
927 operands[1] = copy_to_mode_reg (mode, operands[1]);
930 if (mode == Pmode || mode == ptr_mode)
933 enum tls_model tls_kind;
937 if ((tls_kind = tls_symbolic_operand (op1, Pmode)))
939 rtx tga_op1, tga_ret, tmp, tmp2;
944 case TLS_MODEL_GLOBAL_DYNAMIC:
945 tga_ret = gen_rtx_REG (Pmode, R0_REG);
946 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
950 case TLS_MODEL_LOCAL_DYNAMIC:
951 tga_ret = gen_rtx_REG (Pmode, R0_REG);
952 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
954 tmp = gen_reg_rtx (Pmode);
955 emit_move_insn (tmp, tga_ret);
957 if (register_operand (op0, Pmode))
960 tmp2 = gen_reg_rtx (Pmode);
962 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
966 case TLS_MODEL_INITIAL_EXEC:
968 emit_insn (gen_GOTaddr2picreg ());
969 tga_op1 = gen_reg_rtx (Pmode);
970 tmp = gen_sym2GOTTPOFF (op1);
971 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
975 case TLS_MODEL_LOCAL_EXEC:
976 tmp2 = gen_reg_rtx (Pmode);
977 emit_insn (gen_load_gbr (tmp2));
978 tmp = gen_reg_rtx (Pmode);
979 emit_insn (gen_symTPOFF2reg (tmp, op1));
980 RTX_UNCHANGING_P (tmp) = 1;
982 if (register_operand (op0, Pmode))
985 op1 = gen_reg_rtx (Pmode);
987 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1000 /* Prepare the operands for an scc instruction; make sure that the
1001 compare has been done. */
1003 prepare_scc_operands (enum rtx_code code)
1005 rtx t_reg = gen_rtx_REG (SImode, T_REG);
1006 enum rtx_code oldcode = code;
1007 enum machine_mode mode;
1009 /* First need a compare insn. */
1013 /* It isn't possible to handle this case. */
1030 if (code != oldcode)
1032 rtx tmp = sh_compare_op0;
1033 sh_compare_op0 = sh_compare_op1;
1034 sh_compare_op1 = tmp;
1037 mode = GET_MODE (sh_compare_op0);
1038 if (mode == VOIDmode)
1039 mode = GET_MODE (sh_compare_op1);
1041 sh_compare_op0 = force_reg (mode, sh_compare_op0);
1042 if ((code != EQ && code != NE
1043 && (sh_compare_op1 != const0_rtx
1044 || code == GTU || code == GEU || code == LTU || code == LEU))
1045 || (mode == DImode && sh_compare_op1 != const0_rtx)
1046 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1047 sh_compare_op1 = force_reg (mode, sh_compare_op1);
1049 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
1050 (mode == SFmode ? emit_sf_insn : emit_df_insn)
1051 (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
1052 gen_rtx_SET (VOIDmode, t_reg,
1053 gen_rtx_fmt_ee (code, SImode,
1054 sh_compare_op0, sh_compare_op1)),
1055 gen_rtx_USE (VOIDmode, get_fpscr_rtx ()))));
1057 emit_insn (gen_rtx_SET (VOIDmode, t_reg,
1058 gen_rtx_fmt_ee (code, SImode,
1059 sh_compare_op0, sh_compare_op1)));
1064 /* Called from the md file, set up the operands of a compare instruction. */
1067 from_compare (rtx *operands, int code)
1069 enum machine_mode mode = GET_MODE (sh_compare_op0);
1071 if (mode == VOIDmode)
1072 mode = GET_MODE (sh_compare_op1);
1075 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1077 /* Force args into regs, since we can't use constants here. */
1078 sh_compare_op0 = force_reg (mode, sh_compare_op0);
1079 if (sh_compare_op1 != const0_rtx
1080 || code == GTU || code == GEU
1081 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1082 sh_compare_op1 = force_reg (mode, sh_compare_op1);
1084 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
1086 from_compare (operands, GT);
1087 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
1090 insn = gen_rtx_SET (VOIDmode,
1091 gen_rtx_REG (SImode, T_REG),
1092 gen_rtx_fmt_ee (code, SImode,
1093 sh_compare_op0, sh_compare_op1));
1094 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
1096 insn = gen_rtx_PARALLEL (VOIDmode,
1098 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
1099 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1105 /* Functions to output assembly code. */
1107 /* Return a sequence of instructions to perform DI or DF move.
1109 Since the SH cannot move a DI or DF in one instruction, we have
1110 to take care when we see overlapping source and dest registers. */
1113 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1114 enum machine_mode mode)
1116 rtx dst = operands[0];
1117 rtx src = operands[1];
1119 if (GET_CODE (dst) == MEM
1120 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
1121 return "mov.l %T1,%0\n\tmov.l %1,%0";
1123 if (register_operand (dst, mode)
1124 && register_operand (src, mode))
1126 if (REGNO (src) == MACH_REG)
1127 return "sts mach,%S0\n\tsts macl,%R0";
1129 /* When mov.d r1,r2 do r2->r3 then r1->r2;
1130 when mov.d r1,r0 do r1->r0 then r2->r1. */
1132 if (REGNO (src) + 1 == REGNO (dst))
1133 return "mov %T1,%T0\n\tmov %1,%0";
1135 return "mov %1,%0\n\tmov %T1,%T0";
1137 else if (GET_CODE (src) == CONST_INT)
1139 if (INTVAL (src) < 0)
1140 output_asm_insn ("mov #-1,%S0", operands);
1142 output_asm_insn ("mov #0,%S0", operands);
1144 return "mov %1,%R0";
1146 else if (GET_CODE (src) == MEM)
1149 int dreg = REGNO (dst);
1150 rtx inside = XEXP (src, 0);
1152 if (GET_CODE (inside) == REG)
1153 ptrreg = REGNO (inside);
1154 else if (GET_CODE (inside) == SUBREG)
1155 ptrreg = subreg_regno (inside);
1156 else if (GET_CODE (inside) == PLUS)
1158 ptrreg = REGNO (XEXP (inside, 0));
1159 /* ??? A r0+REG address shouldn't be possible here, because it isn't
1160 an offsettable address. Unfortunately, offsettable addresses use
1161 QImode to check the offset, and a QImode offsettable address
1162 requires r0 for the other operand, which is not currently
1163 supported, so we can't use the 'o' constraint.
1164 Thus we must check for and handle r0+REG addresses here.
1165 We punt for now, since this is likely very rare. */
1166 if (GET_CODE (XEXP (inside, 1)) == REG)
1169 else if (GET_CODE (inside) == LABEL_REF)
1170 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
1171 else if (GET_CODE (inside) == POST_INC)
1172 return "mov.l %1,%0\n\tmov.l %1,%T0";
1176 /* Work out the safe way to copy. Copy into the second half first. */
1178 return "mov.l %T1,%T0\n\tmov.l %1,%0";
1181 return "mov.l %1,%0\n\tmov.l %T1,%T0";
1184 /* Print an instruction which would have gone into a delay slot after
1185 another instruction, but couldn't because the other instruction expanded
1186 into a sequence where putting the slot insn at the end wouldn't work. */
1189 print_slot (rtx insn)
1191 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1, NULL);
1193 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
1197 output_far_jump (rtx insn, rtx op)
1199 struct { rtx lab, reg, op; } this;
1200 rtx braf_base_lab = NULL_RTX;
1203 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
1206 this.lab = gen_label_rtx ();
1210 && offset - get_attr_length (insn) <= 32766)
1213 jump = "mov.w %O0,%1; braf %1";
1221 jump = "mov.l %O0,%1; braf %1";
1223 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1226 jump = "mov.l %O0,%1; jmp @%1";
1228 /* If we have a scratch register available, use it. */
1229 if (GET_CODE ((prev = prev_nonnote_insn (insn))) == INSN
1230 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
1232 this.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
1233 if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2)
1234 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1235 output_asm_insn (jump, &this.lab);
1236 if (dbr_sequence_length ())
1237 print_slot (final_sequence);
1239 output_asm_insn ("nop", 0);
1243 /* Output the delay slot insn first if any. */
1244 if (dbr_sequence_length ())
1245 print_slot (final_sequence);
1247 this.reg = gen_rtx_REG (SImode, 13);
1248 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1249 Fortunately, MACL is fixed and call-clobbered, and we never
1250 need its value across jumps, so save r13 in it instead of in
1253 output_asm_insn ("lds r13, macl", 0);
1255 output_asm_insn ("mov.l r13,@-r15", 0);
1256 output_asm_insn (jump, &this.lab);
1258 output_asm_insn ("sts macl, r13", 0);
1260 output_asm_insn ("mov.l @r15+,r13", 0);
1262 if (far && flag_pic && TARGET_SH2)
1264 braf_base_lab = gen_label_rtx ();
1265 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1266 CODE_LABEL_NUMBER (braf_base_lab));
1269 output_asm_insn (".align 2", 0);
1270 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
1272 if (far && flag_pic)
1275 this.lab = braf_base_lab;
1276 output_asm_insn (".long %O2-%O0", &this.lab);
1279 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
1283 /* Local label counter, used for constants in the pool and inside
1284 pattern branches. */
1286 static int lf = 100;
1288 /* Output code for ordinary branches. */
1291 output_branch (int logic, rtx insn, rtx *operands)
1293 switch (get_attr_length (insn))
1296 /* This can happen if filling the delay slot has caused a forward
1297 branch to exceed its range (we could reverse it, but only
1298 when we know we won't overextend other branches; this should
1299 best be handled by relaxation).
1300 It can also happen when other condbranches hoist delay slot insn
1301 from their destination, thus leading to code size increase.
1302 But the branch will still be in the range -4092..+4098 bytes. */
1307 /* The call to print_slot will clobber the operands. */
1308 rtx op0 = operands[0];
1310 /* If the instruction in the delay slot is annulled (true), then
1311 there is no delay slot where we can put it now. The only safe
1312 place for it is after the label. final will do that by default. */
1315 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1317 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
1318 ASSEMBLER_DIALECT ? "/" : ".", label);
1319 print_slot (final_sequence);
1322 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
1324 output_asm_insn ("bra\t%l0", &op0);
1325 fprintf (asm_out_file, "\tnop\n");
1326 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
1330 /* When relaxing, handle this like a short branch. The linker
1331 will fix it up if it still doesn't fit after relaxation. */
1333 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
1335 /* These are for SH2e, in which we have to account for the
1336 extra nop because of the hardware bug in annulled branches. */
1343 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1345 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
1347 ASSEMBLER_DIALECT ? "/" : ".", label);
1348 fprintf (asm_out_file, "\tnop\n");
1349 output_asm_insn ("bra\t%l0", operands);
1350 fprintf (asm_out_file, "\tnop\n");
1351 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
1355 /* When relaxing, fall through. */
1360 sprintf (buffer, "b%s%ss\t%%l0",
1362 ASSEMBLER_DIALECT ? "/" : ".");
1363 output_asm_insn (buffer, &operands[0]);
1368 /* There should be no longer branches now - that would
1369 indicate that something has destroyed the branches set
1370 up in machine_dependent_reorg. */
1376 output_branchy_insn (enum rtx_code code, const char *template,
1377 rtx insn, rtx *operands)
1379 rtx next_insn = NEXT_INSN (insn);
1381 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
1383 rtx src = SET_SRC (PATTERN (next_insn));
1384 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
1386 /* Following branch not taken */
1387 operands[9] = gen_label_rtx ();
1388 emit_label_after (operands[9], next_insn);
1389 INSN_ADDRESSES_NEW (operands[9],
1390 INSN_ADDRESSES (INSN_UID (next_insn))
1391 + get_attr_length (next_insn));
1396 int offset = (branch_dest (next_insn)
1397 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
1398 if (offset >= -252 && offset <= 258)
1400 if (GET_CODE (src) == IF_THEN_ELSE)
1402 src = XEXP (src, 1);
1408 operands[9] = gen_label_rtx ();
1409 emit_label_after (operands[9], insn);
1410 INSN_ADDRESSES_NEW (operands[9],
1411 INSN_ADDRESSES (INSN_UID (insn))
1412 + get_attr_length (insn));
1417 output_ieee_ccmpeq (rtx insn, rtx *operands)
1419 return output_branchy_insn (NE, "bt\t%l9\\;fcmp/eq\t%1,%0", insn, operands);
1422 /* Output the start of the assembler file. */
1425 sh_file_start (void)
1427 default_file_start ();
1430 /* We need to show the text section with the proper
1431 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
1432 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
1433 will complain. We can teach GAS specifically about the
1434 default attributes for our choice of text section, but
1435 then we would have to change GAS again if/when we change
1436 the text section name. */
1437 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
1439 /* Switch to the data section so that the coffsem symbol
1440 isn't in the text section. */
1443 if (TARGET_LITTLE_ENDIAN)
1444 fputs ("\t.little\n", asm_out_file);
1448 if (TARGET_SHCOMPACT)
1449 fputs ("\t.mode\tSHcompact\n", asm_out_file);
1450 else if (TARGET_SHMEDIA)
1451 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1452 TARGET_SHMEDIA64 ? 64 : 32);
1456 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
1459 unspec_caller_rtx_p (rtx pat)
1461 switch (GET_CODE (pat))
1464 return unspec_caller_rtx_p (XEXP (pat, 0));
1467 if (unspec_caller_rtx_p (XEXP (pat, 0)))
1469 return unspec_caller_rtx_p (XEXP (pat, 1));
1471 if (XINT (pat, 1) == UNSPEC_CALLER)
1480 /* Indicate that INSN cannot be duplicated. This is true for insn
1481 that generates an unique label. */
1484 sh_cannot_copy_insn_p (rtx insn)
1488 if (!reload_completed || !flag_pic)
1491 if (GET_CODE (insn) != INSN)
1493 if (asm_noperands (insn) >= 0)
1496 pat = PATTERN (insn);
1497 if (GET_CODE (pat) != SET)
1499 pat = SET_SRC (pat);
1501 if (unspec_caller_rtx_p (pat))
1507 /* Actual number of instructions used to make a shift by N. */
1508 static const char ashiftrt_insns[] =
1509 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1511 /* Left shift and logical right shift are the same. */
1512 static const char shift_insns[] =
1513 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1515 /* Individual shift amounts needed to get the above length sequences.
1516 One bit right shifts clobber the T bit, so when possible, put one bit
1517 shifts in the middle of the sequence, so the ends are eligible for
1518 branch delay slots. */
1519 static const short shift_amounts[32][5] = {
1520 {0}, {1}, {2}, {2, 1},
1521 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1522 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1523 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1524 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1525 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1526 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1527 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1529 /* Likewise, but for shift amounts < 16, up to three highmost bits
1530 might be clobbered. This is typically used when combined with some
1531 kind of sign or zero extension. */
1533 static const char ext_shift_insns[] =
1534 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1536 static const short ext_shift_amounts[32][4] = {
1537 {0}, {1}, {2}, {2, 1},
1538 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1539 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1540 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1541 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1542 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1543 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1544 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1546 /* Assuming we have a value that has been sign-extended by at least one bit,
1547 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1548 to shift it by N without data loss, and quicker than by other means? */
1549 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1551 /* This is used in length attributes in sh.md to help compute the length
1552 of arbitrary constant shift instructions. */
1555 shift_insns_rtx (rtx insn)
1557 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1558 int shift_count = INTVAL (XEXP (set_src, 1));
1559 enum rtx_code shift_code = GET_CODE (set_src);
1564 return ashiftrt_insns[shift_count];
1567 return shift_insns[shift_count];
1573 /* Return the cost of a shift. */
1583 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
1585 if (GET_MODE (x) == DImode
1586 && GET_CODE (XEXP (x, 1)) == CONST_INT
1587 && INTVAL (XEXP (x, 1)) == 1)
1590 /* Everything else is invalid, because there is no pattern for it. */
1593 /* If shift by a non constant, then this will be expensive. */
1594 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1595 return SH_DYNAMIC_SHIFT_COST;
1597 value = INTVAL (XEXP (x, 1));
1599 /* Otherwise, return the true cost in instructions. */
1600 if (GET_CODE (x) == ASHIFTRT)
1602 int cost = ashiftrt_insns[value];
1603 /* If SH3, then we put the constant in a reg and use shad. */
1604 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
1605 cost = 1 + SH_DYNAMIC_SHIFT_COST;
1609 return shift_insns[value];
1612 /* Return the cost of an AND operation. */
1619 /* Anding with a register is a single cycle and instruction. */
1620 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1623 i = INTVAL (XEXP (x, 1));
1627 if ((GET_CODE (XEXP (x, 1)) == CONST_INT
1628 && CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
1629 || EXTRA_CONSTRAINT_C16 (XEXP (x, 1)))
1635 /* These constants are single cycle extu.[bw] instructions. */
1636 if (i == 0xff || i == 0xffff)
1638 /* Constants that can be used in an and immediate instruction in a single
1639 cycle, but this requires r0, so make it a little more expensive. */
1640 if (CONST_OK_FOR_K08 (i))
1642 /* Constants that can be loaded with a mov immediate and an and.
1643 This case is probably unnecessary. */
1644 if (CONST_OK_FOR_I08 (i))
1646 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1647 This case is probably unnecessary. */
1651 /* Return the cost of an addition or a subtraction. */
1656 /* Adding a register is a single cycle insn. */
1657 if (GET_CODE (XEXP (x, 1)) == REG
1658 || GET_CODE (XEXP (x, 1)) == SUBREG)
1661 /* Likewise for small constants. */
1662 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1663 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
1667 switch (GET_CODE (XEXP (x, 1)))
1672 return TARGET_SHMEDIA64 ? 5 : 3;
1675 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
1677 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
1679 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
1687 /* Any other constant requires a 2 cycle pc-relative load plus an
1692 /* Return the cost of a multiply. */
1694 multcosts (rtx x ATTRIBUTE_UNUSED)
1701 /* We have a mul insn, so we can never take more than the mul and the
1702 read of the mac reg, but count more because of the latency and extra
1704 if (TARGET_SMALLCODE)
1709 /* If we're aiming at small code, then just count the number of
1710 insns in a multiply call sequence. */
1711 if (TARGET_SMALLCODE)
1714 /* Otherwise count all the insns in the routine we'd be calling too. */
1718 /* Compute a (partial) cost for rtx X. Return true if the complete
1719 cost has been computed, and false if subexpressions should be
1720 scanned. In either case, *TOTAL contains the cost result. */
1723 sh_rtx_costs (rtx x, int code, int outer_code, int *total)
1730 if (INTVAL (x) == 0)
1732 else if (outer_code == AND && and_operand ((x), DImode))
1734 else if ((outer_code == IOR || outer_code == XOR
1735 || outer_code == PLUS)
1736 && CONST_OK_FOR_I10 (INTVAL (x)))
1738 else if (CONST_OK_FOR_I16 (INTVAL (x)))
1739 *total = COSTS_N_INSNS (outer_code != SET);
1740 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
1741 *total = COSTS_N_INSNS (2);
1742 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
1743 *total = COSTS_N_INSNS (3);
1745 *total = COSTS_N_INSNS (4);
1748 if (CONST_OK_FOR_I08 (INTVAL (x)))
1750 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
1751 && CONST_OK_FOR_K08 (INTVAL (x)))
1760 if (TARGET_SHMEDIA64)
1761 *total = COSTS_N_INSNS (4);
1762 else if (TARGET_SHMEDIA32)
1763 *total = COSTS_N_INSNS (2);
1770 *total = COSTS_N_INSNS (4);
1776 *total = COSTS_N_INSNS (addsubcosts (x));
1780 *total = COSTS_N_INSNS (andcosts (x));
1784 *total = COSTS_N_INSNS (multcosts (x));
1790 *total = COSTS_N_INSNS (shiftcosts (x));
1797 *total = COSTS_N_INSNS (20);
1810 /* Compute the cost of an address. For the SH, all valid addresses are
1811 the same cost. Use a slightly higher cost for reg + reg addressing,
1812 since it increases pressure on r0. */
1815 sh_address_cost (rtx X)
1817 return (GET_CODE (X) == PLUS
1818 && ! CONSTANT_P (XEXP (X, 1))
1819 && ! TARGET_SHMEDIA ? 1 : 0);
1822 /* Code to expand a shift. */
1825 gen_ashift (int type, int n, rtx reg)
1827 /* Negative values here come from the shift_amounts array. */
1840 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
1844 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
1846 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
1849 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
1854 /* Same for HImode */
1857 gen_ashift_hi (int type, int n, rtx reg)
1859 /* Negative values here come from the shift_amounts array. */
1873 /* We don't have HImode right shift operations because using the
1874 ordinary 32 bit shift instructions for that doesn't generate proper
1875 zero/sign extension.
1876 gen_ashift_hi is only called in contexts where we know that the
1877 sign extension works out correctly. */
1880 if (GET_CODE (reg) == SUBREG)
1882 offset = SUBREG_BYTE (reg);
1883 reg = SUBREG_REG (reg);
1885 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
1889 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
1894 /* Output RTL to split a constant shift into its component SH constant
1895 shift instructions. */
1898 gen_shifty_op (int code, rtx *operands)
1900 int value = INTVAL (operands[2]);
1903 /* Truncate the shift count in case it is out of bounds. */
1904 value = value & 0x1f;
1908 if (code == LSHIFTRT)
1910 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1911 emit_insn (gen_movt (operands[0]));
1914 else if (code == ASHIFT)
1916 /* There is a two instruction sequence for 31 bit left shifts,
1917 but it requires r0. */
1918 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
1920 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
1921 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1926 else if (value == 0)
1928 /* This can happen when not optimizing. We must output something here
1929 to prevent the compiler from aborting in final.c after the try_split
1931 emit_insn (gen_nop ());
1935 max = shift_insns[value];
1936 for (i = 0; i < max; i++)
1937 gen_ashift (code, shift_amounts[value][i], operands[0]);
1940 /* Same as above, but optimized for values where the topmost bits don't
1944 gen_shifty_hi_op (int code, rtx *operands)
1946 int value = INTVAL (operands[2]);
1948 void (*gen_fun) (int, int, rtx);
1950 /* This operation is used by and_shl for SImode values with a few
1951 high bits known to be cleared. */
1955 emit_insn (gen_nop ());
1959 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
1962 max = ext_shift_insns[value];
1963 for (i = 0; i < max; i++)
1964 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1967 /* When shifting right, emit the shifts in reverse order, so that
1968 solitary negative values come first. */
1969 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
1970 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1973 /* Output RTL for an arithmetic right shift. */
1975 /* ??? Rewrite to use super-optimizer sequences. */
1978 expand_ashiftrt (rtx *operands)
1988 if (GET_CODE (operands[2]) != CONST_INT)
1990 rtx count = copy_to_mode_reg (SImode, operands[2]);
1991 emit_insn (gen_negsi2 (count, count));
1992 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1995 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
1996 > 1 + SH_DYNAMIC_SHIFT_COST)
1999 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
2000 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2004 if (GET_CODE (operands[2]) != CONST_INT)
2007 value = INTVAL (operands[2]) & 31;
2011 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
2014 else if (value >= 16 && value <= 19)
2016 wrk = gen_reg_rtx (SImode);
2017 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
2020 gen_ashift (ASHIFTRT, 1, wrk);
2021 emit_move_insn (operands[0], wrk);
2024 /* Expand a short sequence inline, longer call a magic routine. */
2025 else if (value <= 5)
2027 wrk = gen_reg_rtx (SImode);
2028 emit_move_insn (wrk, operands[1]);
2030 gen_ashift (ASHIFTRT, 1, wrk);
2031 emit_move_insn (operands[0], wrk);
2035 wrk = gen_reg_rtx (Pmode);
2037 /* Load the value into an arg reg and call a helper. */
2038 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2039 sprintf (func, "__ashiftrt_r4_%d", value);
2040 func_name = get_identifier (func);
2041 sym = function_symbol (IDENTIFIER_POINTER (func_name));
2042 emit_move_insn (wrk, sym);
2043 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
2044 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
2049 sh_dynamicalize_shift_p (rtx count)
2051 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
2054 /* Try to find a good way to implement the combiner pattern
2055 [(set (match_operand:SI 0 "register_operand" "r")
2056 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2057 (match_operand:SI 2 "const_int_operand" "n"))
2058 (match_operand:SI 3 "const_int_operand" "n"))) .
2059 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
2060 return 0 for simple right / left or left/right shift combination.
2061 return 1 for a combination of shifts with zero_extend.
2062 return 2 for a combination of shifts with an AND that needs r0.
2063 return 3 for a combination of shifts with an AND that needs an extra
2064 scratch register, when the three highmost bits of the AND mask are clear.
2065 return 4 for a combination of shifts with an AND that needs an extra
2066 scratch register, when any of the three highmost bits of the AND mask
2068 If ATTRP is set, store an initial right shift width in ATTRP[0],
2069 and the instruction length in ATTRP[1] . These values are not valid
2071 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
2072 shift_amounts for the last shift value that is to be used before the
2075 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
2077 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
2078 int left = INTVAL (left_rtx), right;
2080 int cost, best_cost = 10000;
2081 int best_right = 0, best_len = 0;
2085 if (left < 0 || left > 31)
2087 if (GET_CODE (mask_rtx) == CONST_INT)
2088 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
2090 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
2091 /* Can this be expressed as a right shift / left shift pair? */
2092 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
2093 right = exact_log2 (lsb);
2094 mask2 = ~(mask + lsb - 1);
2095 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
2096 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
2098 best_cost = shift_insns[right] + shift_insns[right + left];
2099 /* mask has no trailing zeroes <==> ! right */
2100 else if (! right && mask2 == ~(lsb2 - 1))
2102 int late_right = exact_log2 (lsb2);
2103 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
2105 /* Try to use zero extend. */
2106 if (mask2 == ~(lsb2 - 1))
2110 for (width = 8; width <= 16; width += 8)
2112 /* Can we zero-extend right away? */
2113 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
2116 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
2117 if (cost < best_cost)
2128 /* ??? Could try to put zero extend into initial right shift,
2129 or even shift a bit left before the right shift. */
2130 /* Determine value of first part of left shift, to get to the
2131 zero extend cut-off point. */
2132 first = width - exact_log2 (lsb2) + right;
2133 if (first >= 0 && right + left - first >= 0)
2135 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
2136 + ext_shift_insns[right + left - first];
2137 if (cost < best_cost)
2149 /* Try to use r0 AND pattern */
2150 for (i = 0; i <= 2; i++)
2154 if (! CONST_OK_FOR_K08 (mask >> i))
2156 cost = (i != 0) + 2 + ext_shift_insns[left + i];
2157 if (cost < best_cost)
2162 best_len = cost - 1;
2165 /* Try to use a scratch register to hold the AND operand. */
2166 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
2167 for (i = 0; i <= 2; i++)
2171 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
2172 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
2173 if (cost < best_cost)
2178 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
2184 attrp[0] = best_right;
2185 attrp[1] = best_len;
2190 /* This is used in length attributes of the unnamed instructions
2191 corresponding to shl_and_kind return values of 1 and 2. */
2193 shl_and_length (rtx insn)
2195 rtx set_src, left_rtx, mask_rtx;
2198 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2199 left_rtx = XEXP (XEXP (set_src, 0), 1);
2200 mask_rtx = XEXP (set_src, 1);
2201 shl_and_kind (left_rtx, mask_rtx, attributes);
2202 return attributes[1];
2205 /* This is used in length attribute of the and_shl_scratch instruction. */
2208 shl_and_scr_length (rtx insn)
2210 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2211 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
2212 rtx op = XEXP (set_src, 0);
2213 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
2214 op = XEXP (XEXP (op, 0), 0);
2215 return len + shift_insns[INTVAL (XEXP (op, 1))];
2218 /* Generating rtl? */
2219 extern int rtx_equal_function_value_matters;
2221 /* Generate rtl for instructions for which shl_and_kind advised a particular
2222 method of generating them, i.e. returned zero. */
2225 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
2228 unsigned HOST_WIDE_INT mask;
2229 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
2230 int right, total_shift;
2231 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
2233 right = attributes[0];
2234 total_shift = INTVAL (left_rtx) + right;
2235 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
2242 int first = attributes[2];
2247 emit_insn ((mask << right) <= 0xff
2248 ? gen_zero_extendqisi2 (dest,
2249 gen_lowpart (QImode, source))
2250 : gen_zero_extendhisi2 (dest,
2251 gen_lowpart (HImode, source)));
2255 emit_insn (gen_movsi (dest, source));
2259 operands[2] = GEN_INT (right);
2260 gen_shifty_hi_op (LSHIFTRT, operands);
2264 operands[2] = GEN_INT (first);
2265 gen_shifty_hi_op (ASHIFT, operands);
2266 total_shift -= first;
2270 emit_insn (mask <= 0xff
2271 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
2272 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2273 if (total_shift > 0)
2275 operands[2] = GEN_INT (total_shift);
2276 gen_shifty_hi_op (ASHIFT, operands);
2281 shift_gen_fun = gen_shifty_op;
2283 /* If the topmost bit that matters is set, set the topmost bits
2284 that don't matter. This way, we might be able to get a shorter
2286 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
2287 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
2289 /* Don't expand fine-grained when combining, because that will
2290 make the pattern fail. */
2291 if (rtx_equal_function_value_matters
2292 || reload_in_progress || reload_completed)
2296 /* Cases 3 and 4 should be handled by this split
2297 only while combining */
2302 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
2305 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
2310 operands[2] = GEN_INT (total_shift);
2311 shift_gen_fun (ASHIFT, operands);
2318 if (kind != 4 && total_shift < 16)
2320 neg = -ext_shift_amounts[total_shift][1];
2322 neg -= ext_shift_amounts[total_shift][2];
2326 emit_insn (gen_and_shl_scratch (dest, source,
2329 GEN_INT (total_shift + neg),
2331 emit_insn (gen_movsi (dest, dest));
2338 /* Try to find a good way to implement the combiner pattern
2339 [(set (match_operand:SI 0 "register_operand" "=r")
2340 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2341 (match_operand:SI 2 "const_int_operand" "n")
2342 (match_operand:SI 3 "const_int_operand" "n")
2344 (clobber (reg:SI T_REG))]
2345 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
2346 return 0 for simple left / right shift combination.
2347 return 1 for left shift / 8 bit sign extend / left shift.
2348 return 2 for left shift / 16 bit sign extend / left shift.
2349 return 3 for left shift / 8 bit sign extend / shift / sign extend.
2350 return 4 for left shift / 16 bit sign extend / shift / sign extend.
2351 return 5 for left shift / 16 bit sign extend / right shift
2352 return 6 for < 8 bit sign extend / left shift.
2353 return 7 for < 8 bit sign extend / left shift / single right shift.
2354 If COSTP is nonzero, assign the calculated cost to *COSTP. */
2357 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
2359 int left, size, insize, ext;
2360 int cost = 0, best_cost;
2363 left = INTVAL (left_rtx);
2364 size = INTVAL (size_rtx);
2365 insize = size - left;
2368 /* Default to left / right shift. */
2370 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
2373 /* 16 bit shift / sign extend / 16 bit shift */
2374 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
2375 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
2376 below, by alternative 3 or something even better. */
2377 if (cost < best_cost)
2383 /* Try a plain sign extend between two shifts. */
2384 for (ext = 16; ext >= insize; ext -= 8)
2388 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
2389 if (cost < best_cost)
2391 kind = ext / (unsigned) 8;
2395 /* Check if we can do a sloppy shift with a final signed shift
2396 restoring the sign. */
2397 if (EXT_SHIFT_SIGNED (size - ext))
2398 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
2399 /* If not, maybe it's still cheaper to do the second shift sloppy,
2400 and do a final sign extend? */
2401 else if (size <= 16)
2402 cost = ext_shift_insns[ext - insize] + 1
2403 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
2406 if (cost < best_cost)
2408 kind = ext / (unsigned) 8 + 2;
2412 /* Check if we can sign extend in r0 */
2415 cost = 3 + shift_insns[left];
2416 if (cost < best_cost)
2421 /* Try the same with a final signed shift. */
2424 cost = 3 + ext_shift_insns[left + 1] + 1;
2425 if (cost < best_cost)
2434 /* Try to use a dynamic shift. */
2435 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
2436 if (cost < best_cost)
2447 /* Function to be used in the length attribute of the instructions
2448 implementing this pattern. */
2451 shl_sext_length (rtx insn)
2453 rtx set_src, left_rtx, size_rtx;
2456 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2457 left_rtx = XEXP (XEXP (set_src, 0), 1);
2458 size_rtx = XEXP (set_src, 1);
2459 shl_sext_kind (left_rtx, size_rtx, &cost);
2463 /* Generate rtl for this pattern */
2466 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
2469 int left, size, insize, cost;
2472 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
2473 left = INTVAL (left_rtx);
2474 size = INTVAL (size_rtx);
2475 insize = size - left;
2483 int ext = kind & 1 ? 8 : 16;
2484 int shift2 = size - ext;
2486 /* Don't expand fine-grained when combining, because that will
2487 make the pattern fail. */
2488 if (! rtx_equal_function_value_matters
2489 && ! reload_in_progress && ! reload_completed)
2491 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2492 emit_insn (gen_movsi (dest, source));
2496 emit_insn (gen_movsi (dest, source));
2500 operands[2] = GEN_INT (ext - insize);
2501 gen_shifty_hi_op (ASHIFT, operands);
2504 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
2505 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2510 operands[2] = GEN_INT (shift2);
2511 gen_shifty_op (ASHIFT, operands);
2518 if (EXT_SHIFT_SIGNED (shift2))
2520 operands[2] = GEN_INT (shift2 + 1);
2521 gen_shifty_op (ASHIFT, operands);
2522 operands[2] = const1_rtx;
2523 gen_shifty_op (ASHIFTRT, operands);
2526 operands[2] = GEN_INT (shift2);
2527 gen_shifty_hi_op (ASHIFT, operands);
2531 operands[2] = GEN_INT (-shift2);
2532 gen_shifty_hi_op (LSHIFTRT, operands);
2534 emit_insn (size <= 8
2535 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
2536 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2543 if (! rtx_equal_function_value_matters
2544 && ! reload_in_progress && ! reload_completed)
2545 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2549 operands[2] = GEN_INT (16 - insize);
2550 gen_shifty_hi_op (ASHIFT, operands);
2551 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2553 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2555 gen_ashift (ASHIFTRT, 1, dest);
2560 /* Don't expand fine-grained when combining, because that will
2561 make the pattern fail. */
2562 if (! rtx_equal_function_value_matters
2563 && ! reload_in_progress && ! reload_completed)
2565 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2566 emit_insn (gen_movsi (dest, source));
2569 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
2570 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
2571 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
2573 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
2574 gen_shifty_op (ASHIFT, operands);
2576 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
2584 /* Prefix a symbol_ref name with "datalabel". */
2587 gen_datalabel_ref (rtx sym)
2589 if (GET_CODE (sym) == LABEL_REF)
2590 return gen_rtx_CONST (GET_MODE (sym),
2591 gen_rtx_UNSPEC (GET_MODE (sym),
2595 if (GET_CODE (sym) != SYMBOL_REF)
2602 /* The SH cannot load a large constant into a register, constants have to
2603 come from a pc relative load. The reference of a pc relative load
2604 instruction must be less than 1k infront of the instruction. This
2605 means that we often have to dump a constant inside a function, and
2606 generate code to branch around it.
2608 It is important to minimize this, since the branches will slow things
2609 down and make things bigger.
2611 Worst case code looks like:
2629 We fix this by performing a scan before scheduling, which notices which
2630 instructions need to have their operands fetched from the constant table
2631 and builds the table.
2635 scan, find an instruction which needs a pcrel move. Look forward, find the
2636 last barrier which is within MAX_COUNT bytes of the requirement.
2637 If there isn't one, make one. Process all the instructions between
2638 the find and the barrier.
2640 In the above example, we can tell that L3 is within 1k of L1, so
2641 the first move can be shrunk from the 3 insn+constant sequence into
2642 just 1 insn, and the constant moved to L3 to make:
2653 Then the second move becomes the target for the shortening process. */
2657 rtx value; /* Value in table. */
2658 rtx label; /* Label of value. */
2659 rtx wend; /* End of window. */
2660 enum machine_mode mode; /* Mode of value. */
2662 /* True if this constant is accessed as part of a post-increment
2663 sequence. Note that HImode constants are never accessed in this way. */
2664 bool part_of_sequence_p;
2667 /* The maximum number of constants that can fit into one pool, since
2668 the pc relative range is 0...1020 bytes and constants are at least 4
2671 #define MAX_POOL_SIZE (1020/4)
2672 static pool_node pool_vector[MAX_POOL_SIZE];
2673 static int pool_size;
2674 static rtx pool_window_label;
2675 static int pool_window_last;
2677 /* ??? If we need a constant in HImode which is the truncated value of a
2678 constant we need in SImode, we could combine the two entries thus saving
2679 two bytes. Is this common enough to be worth the effort of implementing
2682 /* ??? This stuff should be done at the same time that we shorten branches.
2683 As it is now, we must assume that all branches are the maximum size, and
2684 this causes us to almost always output constant pools sooner than
2687 /* Add a constant to the pool and return its label. */
2690 add_constant (rtx x, enum machine_mode mode, rtx last_value)
2693 rtx lab, new, ref, newref;
2695 /* First see if we've already got it. */
2696 for (i = 0; i < pool_size; i++)
2698 if (x->code == pool_vector[i].value->code
2699 && mode == pool_vector[i].mode)
2701 if (x->code == CODE_LABEL)
2703 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
2706 if (rtx_equal_p (x, pool_vector[i].value))
2711 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
2713 new = gen_label_rtx ();
2714 LABEL_REFS (new) = pool_vector[i].label;
2715 pool_vector[i].label = lab = new;
2717 if (lab && pool_window_label)
2719 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2720 ref = pool_vector[pool_window_last].wend;
2721 LABEL_NEXTREF (newref) = ref;
2722 pool_vector[pool_window_last].wend = newref;
2725 pool_window_label = new;
2726 pool_window_last = i;
2732 /* Need a new one. */
2733 pool_vector[pool_size].value = x;
2734 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
2737 pool_vector[pool_size - 1].part_of_sequence_p = true;
2740 lab = gen_label_rtx ();
2741 pool_vector[pool_size].mode = mode;
2742 pool_vector[pool_size].label = lab;
2743 pool_vector[pool_size].wend = NULL_RTX;
2744 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
2745 if (lab && pool_window_label)
2747 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2748 ref = pool_vector[pool_window_last].wend;
2749 LABEL_NEXTREF (newref) = ref;
2750 pool_vector[pool_window_last].wend = newref;
2753 pool_window_label = lab;
2754 pool_window_last = pool_size;
2759 /* Output the literal table. */
2762 dump_table (rtx scan)
2769 /* Do two passes, first time dump out the HI sized constants. */
2771 for (i = 0; i < pool_size; i++)
2773 pool_node *p = &pool_vector[i];
2775 if (p->mode == HImode)
2779 scan = emit_insn_after (gen_align_2 (), scan);
2782 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2783 scan = emit_label_after (lab, scan);
2784 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
2786 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2788 lab = XEXP (ref, 0);
2789 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2792 else if (p->mode == DFmode)
2798 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
2800 rtx align_insn = NULL_RTX;
2802 scan = emit_label_after (gen_label_rtx (), scan);
2803 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2806 for (i = 0; i < pool_size; i++)
2808 pool_node *p = &pool_vector[i];
2816 if (align_insn && !p->part_of_sequence_p)
2818 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2819 emit_label_before (lab, align_insn);
2820 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
2822 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2824 lab = XEXP (ref, 0);
2825 emit_insn_before (gen_consttable_window_end (lab),
2828 delete_insn (align_insn);
2829 align_insn = NULL_RTX;
2834 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2835 scan = emit_label_after (lab, scan);
2836 scan = emit_insn_after (gen_consttable_4 (p->value,
2838 need_align = ! need_align;
2844 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2849 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2850 scan = emit_label_after (lab, scan);
2851 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2859 if (p->mode != HImode)
2861 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2863 lab = XEXP (ref, 0);
2864 scan = emit_insn_after (gen_consttable_window_end (lab),
2873 for (i = 0; i < pool_size; i++)
2875 pool_node *p = &pool_vector[i];
2886 scan = emit_label_after (gen_label_rtx (), scan);
2887 scan = emit_insn_after (gen_align_4 (), scan);
2889 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2890 scan = emit_label_after (lab, scan);
2891 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
2899 scan = emit_label_after (gen_label_rtx (), scan);
2900 scan = emit_insn_after (gen_align_4 (), scan);
2902 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2903 scan = emit_label_after (lab, scan);
2904 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2912 if (p->mode != HImode)
2914 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2916 lab = XEXP (ref, 0);
2917 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2922 scan = emit_insn_after (gen_consttable_end (), scan);
2923 scan = emit_barrier_after (scan);
2925 pool_window_label = NULL_RTX;
2926 pool_window_last = 0;
2929 /* Return nonzero if constant would be an ok source for a
2930 mov.w instead of a mov.l. */
2935 return (GET_CODE (src) == CONST_INT
2936 && INTVAL (src) >= -32768
2937 && INTVAL (src) <= 32767);
2940 /* Nonzero if the insn is a move instruction which needs to be fixed. */
2942 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2943 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
2944 need to fix it if the input value is CONST_OK_FOR_I08. */
2947 broken_move (rtx insn)
2949 if (GET_CODE (insn) == INSN)
2951 rtx pat = PATTERN (insn);
2952 if (GET_CODE (pat) == PARALLEL)
2953 pat = XVECEXP (pat, 0, 0);
2954 if (GET_CODE (pat) == SET
2955 /* We can load any 8 bit value if we don't care what the high
2956 order bits end up as. */
2957 && GET_MODE (SET_DEST (pat)) != QImode
2958 && (CONSTANT_P (SET_SRC (pat))
2959 /* Match mova_const. */
2960 || (GET_CODE (SET_SRC (pat)) == UNSPEC
2961 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
2962 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
2964 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
2965 && (fp_zero_operand (SET_SRC (pat))
2966 || fp_one_operand (SET_SRC (pat)))
2967 /* ??? If this is a -m4 or -m4-single compilation, in general
2968 we don't know the current setting of fpscr, so disable fldi.
2969 There is an exception if this was a register-register move
2970 before reload - and hence it was ascertained that we have
2971 single precision setting - and in a post-reload optimization
2972 we changed this to do a constant load. In that case
2973 we don't have an r0 clobber, hence we must use fldi. */
2974 && (! TARGET_SH4 || TARGET_FMOVD
2975 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
2977 && GET_CODE (SET_DEST (pat)) == REG
2978 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
2979 && (GET_CODE (SET_SRC (pat)) != CONST_INT
2980 || ! CONST_OK_FOR_I08 (INTVAL (SET_SRC (pat)))))
2990 return (GET_CODE (insn) == INSN
2991 && GET_CODE (PATTERN (insn)) == SET
2992 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
2993 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
2994 /* Don't match mova_const. */
2995 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn)), 0, 0)) == LABEL_REF);
2998 /* Find the last barrier from insn FROM which is close enough to hold the
2999 constant pool. If we can't find one, then create one near the end of
3003 find_barrier (int num_mova, rtx mova, rtx from)
3012 int leading_mova = num_mova;
3013 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
3017 /* For HImode: range is 510, add 4 because pc counts from address of
3018 second instruction after this one, subtract 2 for the jump instruction
3019 that we may need to emit before the table, subtract 2 for the instruction
3020 that fills the jump delay slot (in very rare cases, reorg will take an
3021 instruction from after the constant pool or will leave the delay slot
3022 empty). This gives 510.
3023 For SImode: range is 1020, add 4 because pc counts from address of
3024 second instruction after this one, subtract 2 in case pc is 2 byte
3025 aligned, subtract 2 for the jump instruction that we may need to emit
3026 before the table, subtract 2 for the instruction that fills the jump
3027 delay slot. This gives 1018. */
3029 /* The branch will always be shortened now that the reference address for
3030 forward branches is the successor address, thus we need no longer make
3031 adjustments to the [sh]i_limit for -O0. */
3036 while (from && count_si < si_limit && count_hi < hi_limit)
3038 int inc = get_attr_length (from);
3041 if (GET_CODE (from) == CODE_LABEL)
3044 new_align = 1 << label_to_alignment (from);
3045 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
3046 new_align = 1 << barrier_align (from);
3052 if (GET_CODE (from) == BARRIER)
3055 found_barrier = from;
3057 /* If we are at the end of the function, or in front of an alignment
3058 instruction, we need not insert an extra alignment. We prefer
3059 this kind of barrier. */
3060 if (barrier_align (from) > 2)
3061 good_barrier = from;
3064 if (broken_move (from))
3067 enum machine_mode mode;
3069 pat = PATTERN (from);
3070 if (GET_CODE (pat) == PARALLEL)
3071 pat = XVECEXP (pat, 0, 0);
3072 src = SET_SRC (pat);
3073 dst = SET_DEST (pat);
3074 mode = GET_MODE (dst);
3076 /* We must explicitly check the mode, because sometimes the
3077 front end will generate code to load unsigned constants into
3078 HImode targets without properly sign extending them. */
3080 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
3083 /* We put the short constants before the long constants, so
3084 we must count the length of short constants in the range
3085 for the long constants. */
3086 /* ??? This isn't optimal, but is easy to do. */
3091 /* We dump DF/DI constants before SF/SI ones, because
3092 the limit is the same, but the alignment requirements
3093 are higher. We may waste up to 4 additional bytes
3094 for alignment, and the DF/DI constant may have
3095 another SF/SI constant placed before it. */
3096 if (TARGET_SHCOMPACT
3098 && (mode == DFmode || mode == DImode))
3103 while (si_align > 2 && found_si + si_align - 2 > count_si)
3105 if (found_si > count_si)
3106 count_si = found_si;
3107 found_si += GET_MODE_SIZE (mode);
3109 si_limit -= GET_MODE_SIZE (mode);
3112 /* See the code in machine_dependent_reorg, which has a similar if
3113 statement that generates a new mova insn in many cases. */
3114 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
3124 barrier_before_mova = good_barrier ? good_barrier : found_barrier;
3126 if (found_si > count_si)
3127 count_si = found_si;
3129 else if (GET_CODE (from) == JUMP_INSN
3130 && (GET_CODE (PATTERN (from)) == ADDR_VEC
3131 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
3135 if (barrier_align (next_real_insn (from)) == align_jumps_log)
3137 /* We have just passed the barrier in front of the
3138 ADDR_DIFF_VEC, which is stored in found_barrier. Since
3139 the ADDR_DIFF_VEC is accessed as data, just like our pool
3140 constants, this is a good opportunity to accommodate what
3141 we have gathered so far.
3142 If we waited any longer, we could end up at a barrier in
3143 front of code, which gives worse cache usage for separated
3144 instruction / data caches. */
3145 good_barrier = found_barrier;
3150 rtx body = PATTERN (from);
3151 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
3154 /* For the SH1, we generate alignments even after jumps-around-jumps. */
3155 else if (GET_CODE (from) == JUMP_INSN
3157 && ! TARGET_SMALLCODE)
3163 if (new_align > si_align)
3165 si_limit -= (count_si - 1) & (new_align - si_align);
3166 si_align = new_align;
3168 count_si = (count_si + new_align - 1) & -new_align;
3173 if (new_align > hi_align)
3175 hi_limit -= (count_hi - 1) & (new_align - hi_align);
3176 hi_align = new_align;
3178 count_hi = (count_hi + new_align - 1) & -new_align;
3180 from = NEXT_INSN (from);
3187 /* Try as we might, the leading mova is out of range. Change
3188 it into a load (which will become a pcload) and retry. */
3189 SET_SRC (PATTERN (mova)) = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3190 INSN_CODE (mova) = -1;
3191 return find_barrier (0, 0, mova);
3195 /* Insert the constant pool table before the mova instruction,
3196 to prevent the mova label reference from going out of range. */
3198 good_barrier = found_barrier = barrier_before_mova;
3204 if (good_barrier && next_real_insn (found_barrier))
3205 found_barrier = good_barrier;
3209 /* We didn't find a barrier in time to dump our stuff,
3210 so we'll make one. */
3211 rtx label = gen_label_rtx ();
3213 /* If we exceeded the range, then we must back up over the last
3214 instruction we looked at. Otherwise, we just need to undo the
3215 NEXT_INSN at the end of the loop. */
3216 if (count_hi > hi_limit || count_si > si_limit)
3217 from = PREV_INSN (PREV_INSN (from));
3219 from = PREV_INSN (from);
3221 /* Walk back to be just before any jump or label.
3222 Putting it before a label reduces the number of times the branch
3223 around the constant pool table will be hit. Putting it before
3224 a jump makes it more likely that the bra delay slot will be
3226 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
3227 || GET_CODE (from) == CODE_LABEL)
3228 from = PREV_INSN (from);
3230 from = emit_jump_insn_after (gen_jump (label), from);
3231 JUMP_LABEL (from) = label;
3232 LABEL_NUSES (label) = 1;
3233 found_barrier = emit_barrier_after (from);
3234 emit_label_after (label, found_barrier);
3237 return found_barrier;
3240 /* If the instruction INSN is implemented by a special function, and we can
3241 positively find the register that is used to call the sfunc, and this
3242 register is not used anywhere else in this instruction - except as the
3243 destination of a set, return this register; else, return 0. */
3245 sfunc_uses_reg (rtx insn)
3248 rtx pattern, part, reg_part, reg;
3250 if (GET_CODE (insn) != INSN)
3252 pattern = PATTERN (insn);
3253 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
3256 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
3258 part = XVECEXP (pattern, 0, i);
3259 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
3264 reg = XEXP (reg_part, 0);
3265 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
3267 part = XVECEXP (pattern, 0, i);
3268 if (part == reg_part || GET_CODE (part) == CLOBBER)
3270 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
3271 && GET_CODE (SET_DEST (part)) == REG)
3272 ? SET_SRC (part) : part)))
3278 /* See if the only way in which INSN uses REG is by calling it, or by
3279 setting it while calling it. Set *SET to a SET rtx if the register
3283 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
3289 reg2 = sfunc_uses_reg (insn);
3290 if (reg2 && REGNO (reg2) == REGNO (reg))
3292 pattern = single_set (insn);
3294 && GET_CODE (SET_DEST (pattern)) == REG
3295 && REGNO (reg) == REGNO (SET_DEST (pattern)))
3299 if (GET_CODE (insn) != CALL_INSN)
3301 /* We don't use rtx_equal_p because we don't care if the mode is
3303 pattern = single_set (insn);
3305 && GET_CODE (SET_DEST (pattern)) == REG
3306 && REGNO (reg) == REGNO (SET_DEST (pattern)))
3312 par = PATTERN (insn);
3313 if (GET_CODE (par) == PARALLEL)
3314 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
3316 part = XVECEXP (par, 0, i);
3317 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
3320 return reg_mentioned_p (reg, SET_SRC (pattern));
3326 pattern = PATTERN (insn);
3328 if (GET_CODE (pattern) == PARALLEL)
3332 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
3333 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
3335 pattern = XVECEXP (pattern, 0, 0);
3338 if (GET_CODE (pattern) == SET)
3340 if (reg_mentioned_p (reg, SET_DEST (pattern)))
3342 /* We don't use rtx_equal_p, because we don't care if the
3343 mode is different. */
3344 if (GET_CODE (SET_DEST (pattern)) != REG
3345 || REGNO (reg) != REGNO (SET_DEST (pattern)))
3351 pattern = SET_SRC (pattern);
3354 if (GET_CODE (pattern) != CALL
3355 || GET_CODE (XEXP (pattern, 0)) != MEM
3356 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
3362 /* Given a X, a pattern of an insn or a part of it, return a mask of used
3363 general registers. Bits 0..15 mean that the respective registers
3364 are used as inputs in the instruction. Bits 16..31 mean that the
3365 registers 0..15, respectively, are used as outputs, or are clobbered.
3366 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
3368 regs_used (rtx x, int is_dest)
3376 code = GET_CODE (x);
3381 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3382 << (REGNO (x) + is_dest));
3386 rtx y = SUBREG_REG (x);
3388 if (GET_CODE (y) != REG)
3391 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3393 subreg_regno_offset (REGNO (y),
3396 GET_MODE (x)) + is_dest));
3400 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
3402 /* If there was a return value, it must have been indicated with USE. */
3417 fmt = GET_RTX_FORMAT (code);
3419 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3424 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3425 used |= regs_used (XVECEXP (x, i, j), is_dest);
3427 else if (fmt[i] == 'e')
3428 used |= regs_used (XEXP (x, i), is_dest);
3433 /* Create an instruction that prevents redirection of a conditional branch
3434 to the destination of the JUMP with address ADDR.
3435 If the branch needs to be implemented as an indirect jump, try to find
3436 a scratch register for it.
3437 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
3438 If any preceding insn that doesn't fit into a delay slot is good enough,
3439 pass 1. Pass 2 if a definite blocking insn is needed.
3440 -1 is used internally to avoid deep recursion.
3441 If a blocking instruction is made or recognized, return it. */
3444 gen_block_redirect (rtx jump, int addr, int need_block)
3447 rtx prev = prev_nonnote_insn (jump);
3450 /* First, check if we already have an instruction that satisfies our need. */
3451 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
3453 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
3455 if (GET_CODE (PATTERN (prev)) == USE
3456 || GET_CODE (PATTERN (prev)) == CLOBBER
3457 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3459 else if ((need_block &= ~1) < 0)
3461 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
3464 if (GET_CODE (PATTERN (jump)) == RETURN)
3468 /* Reorg even does nasty things with return insns that cause branches
3469 to go out of range - see find_end_label and callers. */
3470 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
3472 /* We can't use JUMP_LABEL here because it might be undefined
3473 when not optimizing. */
3474 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
3475 /* If the branch is out of range, try to find a scratch register for it. */
3477 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3481 /* Don't look for the stack pointer as a scratch register,
3482 it would cause trouble if an interrupt occurred. */
3483 unsigned try = 0x7fff, used;
3484 int jump_left = flag_expensive_optimizations + 1;
3486 /* It is likely that the most recent eligible instruction is wanted for
3487 the delay slot. Therefore, find out which registers it uses, and
3488 try to avoid using them. */
3490 for (scan = jump; (scan = PREV_INSN (scan)); )
3494 if (INSN_DELETED_P (scan))
3496 code = GET_CODE (scan);
3497 if (code == CODE_LABEL || code == JUMP_INSN)
3500 && GET_CODE (PATTERN (scan)) != USE
3501 && GET_CODE (PATTERN (scan)) != CLOBBER
3502 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
3504 try &= ~regs_used (PATTERN (scan), 0);
3508 for (used = dead = 0, scan = JUMP_LABEL (jump);
3509 (scan = NEXT_INSN (scan)); )
3513 if (INSN_DELETED_P (scan))
3515 code = GET_CODE (scan);
3518 used |= regs_used (PATTERN (scan), 0);
3519 if (code == CALL_INSN)
3520 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
3521 dead |= (used >> 16) & ~used;
3527 if (code == JUMP_INSN)
3529 if (jump_left-- && simplejump_p (scan))
3530 scan = JUMP_LABEL (scan);
3536 /* Mask out the stack pointer again, in case it was
3537 the only 'free' register we have found. */
3540 /* If the immediate destination is still in range, check for possible
3541 threading with a jump beyond the delay slot insn.
3542 Don't check if we are called recursively; the jump has been or will be
3543 checked in a different invocation then. */
3545 else if (optimize && need_block >= 0)
3547 rtx next = next_active_insn (next_active_insn (dest));
3548 if (next && GET_CODE (next) == JUMP_INSN
3549 && GET_CODE (PATTERN (next)) == SET
3550 && recog_memoized (next) == CODE_FOR_jump_compact)
3552 dest = JUMP_LABEL (next);
3554 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3556 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
3562 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
3564 /* It would be nice if we could convert the jump into an indirect
3565 jump / far branch right now, and thus exposing all constituent
3566 instructions to further optimization. However, reorg uses
3567 simplejump_p to determine if there is an unconditional jump where
3568 it should try to schedule instructions from the target of the
3569 branch; simplejump_p fails for indirect jumps even if they have
3571 rtx insn = emit_insn_before (gen_indirect_jump_scratch
3572 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
3574 /* ??? We would like this to have the scope of the jump, but that
3575 scope will change when a delay slot insn of an inner scope is added.
3576 Hence, after delay slot scheduling, we'll have to expect
3577 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
3580 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
3581 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
3584 else if (need_block)
3585 /* We can't use JUMP_LABEL here because it might be undefined
3586 when not optimizing. */
3587 return emit_insn_before (gen_block_branch_redirect
3588 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
3593 #define CONDJUMP_MIN -252
3594 #define CONDJUMP_MAX 262
3597 /* A label (to be placed) in front of the jump
3598 that jumps to our ultimate destination. */
3600 /* Where we are going to insert it if we cannot move the jump any farther,
3601 or the jump itself if we have picked up an existing jump. */
3603 /* The ultimate destination. */
3605 struct far_branch *prev;
3606 /* If the branch has already been created, its address;
3607 else the address of its first prospective user. */
3611 static void gen_far_branch (struct far_branch *);
3612 enum mdep_reorg_phase_e mdep_reorg_phase;
3614 gen_far_branch (struct far_branch *bp)
3616 rtx insn = bp->insert_place;
3618 rtx label = gen_label_rtx ();
3620 emit_label_after (label, insn);
3623 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
3624 LABEL_NUSES (bp->far_label)++;
3627 jump = emit_jump_insn_after (gen_return (), insn);
3628 /* Emit a barrier so that reorg knows that any following instructions
3629 are not reachable via a fall-through path.
3630 But don't do this when not optimizing, since we wouldn't suppress the
3631 alignment for the barrier then, and could end up with out-of-range
3632 pc-relative loads. */
3634 emit_barrier_after (jump);
3635 emit_label_after (bp->near_label, insn);
3636 JUMP_LABEL (jump) = bp->far_label;
3637 if (! invert_jump (insn, label, 1))
3639 /* If we are branching around a jump (rather than a return), prevent
3640 reorg from using an insn from the jump target as the delay slot insn -
3641 when reorg did this, it pessimized code (we rather hide the delay slot)
3642 and it could cause branches to go out of range. */
3645 (gen_stuff_delay_slot
3646 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
3647 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
3649 /* Prevent reorg from undoing our splits. */
3650 gen_block_redirect (jump, bp->address += 2, 2);
3653 /* Fix up ADDR_DIFF_VECs. */
3655 fixup_addr_diff_vecs (rtx first)
3659 for (insn = first; insn; insn = NEXT_INSN (insn))
3661 rtx vec_lab, pat, prev, prevpat, x, braf_label;
3663 if (GET_CODE (insn) != JUMP_INSN
3664 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
3666 pat = PATTERN (insn);
3667 vec_lab = XEXP (XEXP (pat, 0), 0);
3669 /* Search the matching casesi_jump_2. */
3670 for (prev = vec_lab; ; prev = PREV_INSN (prev))
3672 if (GET_CODE (prev) != JUMP_INSN)
3674 prevpat = PATTERN (prev);
3675 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
3677 x = XVECEXP (prevpat, 0, 1);
3678 if (GET_CODE (x) != USE)
3681 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
3685 /* Emit the reference label of the braf where it belongs, right after
3686 the casesi_jump_2 (i.e. braf). */
3687 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
3688 emit_label_after (braf_label, prev);
3690 /* Fix up the ADDR_DIF_VEC to be relative
3691 to the reference address of the braf. */
3692 XEXP (XEXP (pat, 0), 0) = braf_label;
3696 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3697 a barrier. Return the base 2 logarithm of the desired alignment. */
3699 barrier_align (rtx barrier_or_label)
3701 rtx next = next_real_insn (barrier_or_label), pat, prev;
3702 int slot, credit, jump_to_next = 0;
3707 pat = PATTERN (next);
3709 if (GET_CODE (pat) == ADDR_DIFF_VEC)
3712 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
3713 /* This is a barrier in front of a constant table. */
3716 prev = prev_real_insn (barrier_or_label);
3717 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
3719 pat = PATTERN (prev);
3720 /* If this is a very small table, we want to keep the alignment after
3721 the table to the minimum for proper code alignment. */
3722 return ((TARGET_SMALLCODE
3723 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
3724 <= (unsigned) 1 << (CACHE_LOG - 2)))
3725 ? 1 << TARGET_SHMEDIA : align_jumps_log);
3728 if (TARGET_SMALLCODE)
3731 if (! TARGET_SH2 || ! optimize)
3732 return align_jumps_log;
3734 /* When fixing up pcloads, a constant table might be inserted just before
3735 the basic block that ends with the barrier. Thus, we can't trust the
3736 instruction lengths before that. */
3737 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
3739 /* Check if there is an immediately preceding branch to the insn beyond
3740 the barrier. We must weight the cost of discarding useful information
3741 from the current cache line when executing this branch and there is
3742 an alignment, against that of fetching unneeded insn in front of the
3743 branch target when there is no alignment. */
3745 /* There are two delay_slot cases to consider. One is the simple case
3746 where the preceding branch is to the insn beyond the barrier (simple
3747 delay slot filling), and the other is where the preceding branch has
3748 a delay slot that is a duplicate of the insn after the barrier
3749 (fill_eager_delay_slots) and the branch is to the insn after the insn
3750 after the barrier. */
3752 /* PREV is presumed to be the JUMP_INSN for the barrier under
3753 investigation. Skip to the insn before it. */
3754 prev = prev_real_insn (prev);
3756 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
3757 credit >= 0 && prev && GET_CODE (prev) == INSN;
3758 prev = prev_real_insn (prev))
3761 if (GET_CODE (PATTERN (prev)) == USE
3762 || GET_CODE (PATTERN (prev)) == CLOBBER)
3764 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
3766 prev = XVECEXP (PATTERN (prev), 0, 1);
3767 if (INSN_UID (prev) == INSN_UID (next))
3769 /* Delay slot was filled with insn at jump target. */
3776 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3778 credit -= get_attr_length (prev);
3781 && GET_CODE (prev) == JUMP_INSN
3782 && JUMP_LABEL (prev))
3786 || next_real_insn (JUMP_LABEL (prev)) == next
3787 /* If relax_delay_slots() decides NEXT was redundant
3788 with some previous instruction, it will have
3789 redirected PREV's jump to the following insn. */
3790 || JUMP_LABEL (prev) == next_nonnote_insn (next)
3791 /* There is no upper bound on redundant instructions
3792 that might have been skipped, but we must not put an
3793 alignment where none had been before. */
3794 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
3796 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
3797 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
3798 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
3800 rtx pat = PATTERN (prev);
3801 if (GET_CODE (pat) == PARALLEL)
3802 pat = XVECEXP (pat, 0, 0);
3803 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
3809 return align_jumps_log;
3812 /* If we are inside a phony loop, almost any kind of label can turn up as the
3813 first one in the loop. Aligning a braf label causes incorrect switch
3814 destination addresses; we can detect braf labels because they are
3815 followed by a BARRIER.
3816 Applying loop alignment to small constant or switch tables is a waste
3817 of space, so we suppress this too. */
3819 sh_loop_align (rtx label)
3824 next = next_nonnote_insn (next);
3825 while (next && GET_CODE (next) == CODE_LABEL);
3829 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
3830 || recog_memoized (next) == CODE_FOR_consttable_2)
3833 return align_loops_log;
3836 /* Do a final pass over the function, just before delayed branch
3842 rtx first, insn, mova = NULL_RTX;
3844 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
3845 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
3847 first = get_insns ();
3849 /* We must split call insns before introducing `mova's. If we're
3850 optimizing, they'll have already been split. Otherwise, make
3851 sure we don't split them too late. */
3853 split_all_insns_noflow ();
3858 /* If relaxing, generate pseudo-ops to associate function calls with
3859 the symbols they call. It does no harm to not generate these
3860 pseudo-ops. However, when we can generate them, it enables to
3861 linker to potentially relax the jsr to a bsr, and eliminate the
3862 register load and, possibly, the constant pool entry. */
3864 mdep_reorg_phase = SH_INSERT_USES_LABELS;
3867 /* Remove all REG_LABEL notes. We want to use them for our own
3868 purposes. This works because none of the remaining passes
3869 need to look at them.
3871 ??? But it may break in the future. We should use a machine
3872 dependent REG_NOTE, or some other approach entirely. */
3873 for (insn = first; insn; insn = NEXT_INSN (insn))
3879 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
3880 remove_note (insn, note);
3884 for (insn = first; insn; insn = NEXT_INSN (insn))
3886 rtx pattern, reg, link, set, scan, dies, label;
3887 int rescan = 0, foundinsn = 0;
3889 if (GET_CODE (insn) == CALL_INSN)
3891 pattern = PATTERN (insn);
3893 if (GET_CODE (pattern) == PARALLEL)
3894 pattern = XVECEXP (pattern, 0, 0);
3895 if (GET_CODE (pattern) == SET)
3896 pattern = SET_SRC (pattern);
3898 if (GET_CODE (pattern) != CALL
3899 || GET_CODE (XEXP (pattern, 0)) != MEM)
3902 reg = XEXP (XEXP (pattern, 0), 0);
3906 reg = sfunc_uses_reg (insn);
3911 if (GET_CODE (reg) != REG)
3914 /* This is a function call via REG. If the only uses of REG
3915 between the time that it is set and the time that it dies
3916 are in function calls, then we can associate all the
3917 function calls with the setting of REG. */
3919 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
3921 if (REG_NOTE_KIND (link) != 0)
3923 set = single_set (XEXP (link, 0));
3924 if (set && rtx_equal_p (reg, SET_DEST (set)))
3926 link = XEXP (link, 0);
3933 /* ??? Sometimes global register allocation will have
3934 deleted the insn pointed to by LOG_LINKS. Try
3935 scanning backward to find where the register is set. */
3936 for (scan = PREV_INSN (insn);
3937 scan && GET_CODE (scan) != CODE_LABEL;
3938 scan = PREV_INSN (scan))
3940 if (! INSN_P (scan))
3943 if (! reg_mentioned_p (reg, scan))
3946 if (noncall_uses_reg (reg, scan, &set))
3960 /* The register is set at LINK. */
3962 /* We can only optimize the function call if the register is
3963 being set to a symbol. In theory, we could sometimes
3964 optimize calls to a constant location, but the assembler
3965 and linker do not support that at present. */
3966 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
3967 && GET_CODE (SET_SRC (set)) != LABEL_REF)
3970 /* Scan forward from LINK to the place where REG dies, and
3971 make sure that the only insns which use REG are
3972 themselves function calls. */
3974 /* ??? This doesn't work for call targets that were allocated
3975 by reload, since there may not be a REG_DEAD note for the
3979 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
3983 /* Don't try to trace forward past a CODE_LABEL if we haven't
3984 seen INSN yet. Ordinarily, we will only find the setting insn
3985 in LOG_LINKS if it is in the same basic block. However,
3986 cross-jumping can insert code labels in between the load and
3987 the call, and can result in situations where a single call
3988 insn may have two targets depending on where we came from. */
3990 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
3993 if (! INSN_P (scan))
3996 /* Don't try to trace forward past a JUMP. To optimize
3997 safely, we would have to check that all the
3998 instructions at the jump destination did not use REG. */
4000 if (GET_CODE (scan) == JUMP_INSN)
4003 if (! reg_mentioned_p (reg, scan))
4006 if (noncall_uses_reg (reg, scan, &scanset))
4013 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
4015 /* There is a function call to this register other
4016 than the one we are checking. If we optimize
4017 this call, we need to rescan again below. */
4021 /* ??? We shouldn't have to worry about SCANSET here.
4022 We should just be able to check for a REG_DEAD note
4023 on a function call. However, the REG_DEAD notes are
4024 apparently not dependable around libcalls; c-torture
4025 execute/920501-2 is a test case. If SCANSET is set,
4026 then this insn sets the register, so it must have
4027 died earlier. Unfortunately, this will only handle
4028 the cases in which the register is, in fact, set in a
4031 /* ??? We shouldn't have to use FOUNDINSN here.
4032 However, the LOG_LINKS fields are apparently not
4033 entirely reliable around libcalls;
4034 newlib/libm/math/e_pow.c is a test case. Sometimes
4035 an insn will appear in LOG_LINKS even though it is
4036 not the most recent insn which sets the register. */
4040 || find_reg_note (scan, REG_DEAD, reg)))
4049 /* Either there was a branch, or some insn used REG
4050 other than as a function call address. */
4054 /* Create a code label, and put it in a REG_LABEL note on
4055 the insn which sets the register, and on each call insn
4056 which uses the register. In final_prescan_insn we look
4057 for the REG_LABEL notes, and output the appropriate label
4060 label = gen_label_rtx ();
4061 REG_NOTES (link) = gen_rtx_INSN_LIST (REG_LABEL, label,
4063 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, label,
4072 scan = NEXT_INSN (scan);
4074 && ((GET_CODE (scan) == CALL_INSN
4075 && reg_mentioned_p (reg, scan))
4076 || ((reg2 = sfunc_uses_reg (scan))
4077 && REGNO (reg2) == REGNO (reg))))
4079 = gen_rtx_INSN_LIST (REG_LABEL, label, REG_NOTES (scan));
4081 while (scan != dies);
4087 fixup_addr_diff_vecs (first);
4091 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
4092 shorten_branches (first);
4094 /* Scan the function looking for move instructions which have to be
4095 changed to pc-relative loads and insert the literal tables. */
4097 mdep_reorg_phase = SH_FIXUP_PCLOAD;
4098 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
4105 else if (GET_CODE (insn) == JUMP_INSN
4106 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
4114 /* Some code might have been inserted between the mova and
4115 its ADDR_DIFF_VEC. Check if the mova is still in range. */
4116 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
4117 total += get_attr_length (scan);
4119 /* range of mova is 1020, add 4 because pc counts from address of
4120 second instruction after this one, subtract 2 in case pc is 2
4121 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
4122 cancels out with alignment effects of the mova itself. */
4125 /* Change the mova into a load, and restart scanning
4126 there. broken_move will then return true for mova. */
4127 SET_SRC (PATTERN (mova))
4128 = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4129 INSN_CODE (mova) = -1;
4133 if (broken_move (insn))
4136 /* Scan ahead looking for a barrier to stick the constant table
4138 rtx barrier = find_barrier (num_mova, mova, insn);
4139 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
4141 if (num_mova && ! mova_p (mova))
4143 /* find_barrier had to change the first mova into a
4144 pcload; thus, we have to start with this new pcload. */
4148 /* Now find all the moves between the points and modify them. */
4149 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
4151 if (GET_CODE (scan) == CODE_LABEL)
4153 if (broken_move (scan))
4155 rtx *patp = &PATTERN (scan), pat = *patp;
4159 enum machine_mode mode;
4161 if (GET_CODE (pat) == PARALLEL)
4162 patp = &XVECEXP (pat, 0, 0), pat = *patp;
4163 src = SET_SRC (pat);
4164 dst = SET_DEST (pat);
4165 mode = GET_MODE (dst);
4167 if (mode == SImode && hi_const (src)
4168 && REGNO (dst) != FPUL_REG)
4173 while (GET_CODE (dst) == SUBREG)
4175 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
4176 GET_MODE (SUBREG_REG (dst)),
4179 dst = SUBREG_REG (dst);
4181 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
4184 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
4186 /* This must be an insn that clobbers r0. */
4187 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
4188 XVECLEN (PATTERN (scan), 0)
4190 rtx clobber = *clobberp;
4192 if (GET_CODE (clobber) != CLOBBER
4193 || ! rtx_equal_p (XEXP (clobber, 0), r0_rtx))
4197 && reg_set_between_p (r0_rtx, last_float_move, scan))
4201 && GET_MODE_SIZE (mode) != 4
4202 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
4204 lab = add_constant (src, mode, last_float);
4206 emit_insn_before (gen_mova (lab), scan);
4209 /* There will be a REG_UNUSED note for r0 on
4210 LAST_FLOAT_MOVE; we have to change it to REG_INC,
4211 lest reorg:mark_target_live_regs will not
4212 consider r0 to be used, and we end up with delay
4213 slot insn in front of SCAN that clobbers r0. */
4215 = find_regno_note (last_float_move, REG_UNUSED, 0);
4217 /* If we are not optimizing, then there may not be
4220 PUT_MODE (note, REG_INC);
4222 *last_float_addr = r0_inc_rtx;
4224 last_float_move = scan;
4226 newsrc = gen_rtx_MEM (mode,
4227 (((TARGET_SH4 && ! TARGET_FMOVD)
4228 || REGNO (dst) == FPUL_REG)
4231 last_float_addr = &XEXP (newsrc, 0);
4233 /* Remove the clobber of r0. */
4234 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
4235 gen_rtx_SCRATCH (Pmode));
4236 RTX_UNCHANGING_P (newsrc) = 1;
4238 /* This is a mova needing a label. Create it. */
4239 else if (GET_CODE (src) == UNSPEC
4240 && XINT (src, 1) == UNSPEC_MOVA
4241 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
4243 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
4244 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
4245 newsrc = gen_rtx_UNSPEC (SImode,
4246 gen_rtvec (1, newsrc),
4251 lab = add_constant (src, mode, 0);
4252 newsrc = gen_rtx_MEM (mode,
4253 gen_rtx_LABEL_REF (VOIDmode, lab));
4254 RTX_UNCHANGING_P (newsrc) = 1;
4256 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
4257 INSN_CODE (scan) = -1;
4260 dump_table (barrier);
4265 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
4266 INSN_ADDRESSES_FREE ();
4267 split_branches (first);
4269 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
4270 also has an effect on the register that holds the address of the sfunc.
4271 Insert an extra dummy insn in front of each sfunc that pretends to
4272 use this register. */
4273 if (flag_delayed_branch)
4275 for (insn = first; insn; insn = NEXT_INSN (insn))
4277 rtx reg = sfunc_uses_reg (insn);
4281 emit_insn_before (gen_use_sfunc_addr (reg), insn);
4285 /* fpscr is not actually a user variable, but we pretend it is for the
4286 sake of the previous optimization passes, since we want it handled like
4287 one. However, we don't have any debugging information for it, so turn
4288 it into a non-user variable now. */
4290 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
4292 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
4296 get_dest_uid (rtx label, int max_uid)
4298 rtx dest = next_real_insn (label);
4301 /* This can happen for an undefined label. */
4303 dest_uid = INSN_UID (dest);
4304 /* If this is a newly created branch redirection blocking instruction,
4305 we cannot index the branch_uid or insn_addresses arrays with its
4306 uid. But then, we won't need to, because the actual destination is
4307 the following branch. */
4308 while (dest_uid >= max_uid)
4310 dest = NEXT_INSN (dest);
4311 dest_uid = INSN_UID (dest);
4313 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
4318 /* Split condbranches that are out of range. Also add clobbers for
4319 scratch registers that are needed in far jumps.
4320 We do this before delay slot scheduling, so that it can take our
4321 newly created instructions into account. It also allows us to
4322 find branches with common targets more easily. */
4325 split_branches (rtx first)
4328 struct far_branch **uid_branch, *far_branch_list = 0;
4329 int max_uid = get_max_uid ();
4331 /* Find out which branches are out of range. */
4332 shorten_branches (first);
4334 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
4335 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
4337 for (insn = first; insn; insn = NEXT_INSN (insn))
4338 if (! INSN_P (insn))
4340 else if (INSN_DELETED_P (insn))
4342 /* Shorten_branches would split this instruction again,
4343 so transform it into a note. */
4344 PUT_CODE (insn, NOTE);
4345 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4346 NOTE_SOURCE_FILE (insn) = 0;
4348 else if (GET_CODE (insn) == JUMP_INSN
4349 /* Don't mess with ADDR_DIFF_VEC */
4350 && (GET_CODE (PATTERN (insn)) == SET
4351 || GET_CODE (PATTERN (insn)) == RETURN))
4353 enum attr_type type = get_attr_type (insn);
4354 if (type == TYPE_CBRANCH)
4358 if (get_attr_length (insn) > 4)
4360 rtx src = SET_SRC (PATTERN (insn));
4361 rtx olabel = XEXP (XEXP (src, 1), 0);
4362 int addr = INSN_ADDRESSES (INSN_UID (insn));
4364 int dest_uid = get_dest_uid (olabel, max_uid);
4365 struct far_branch *bp = uid_branch[dest_uid];
4367 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
4368 the label if the LABEL_NUSES count drops to zero. There is
4369 always a jump_optimize pass that sets these values, but it
4370 proceeds to delete unreferenced code, and then if not
4371 optimizing, to un-delete the deleted instructions, thus
4372 leaving labels with too low uses counts. */
4375 JUMP_LABEL (insn) = olabel;
4376 LABEL_NUSES (olabel)++;
4380 bp = (struct far_branch *) alloca (sizeof *bp);
4381 uid_branch[dest_uid] = bp;
4382 bp->prev = far_branch_list;
4383 far_branch_list = bp;
4385 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
4386 LABEL_NUSES (bp->far_label)++;
4390 label = bp->near_label;
4391 if (! label && bp->address - addr >= CONDJUMP_MIN)
4393 rtx block = bp->insert_place;
4395 if (GET_CODE (PATTERN (block)) == RETURN)
4396 block = PREV_INSN (block);
4398 block = gen_block_redirect (block,
4400 label = emit_label_after (gen_label_rtx (),
4402 bp->near_label = label;
4404 else if (label && ! NEXT_INSN (label))
4406 if (addr + 2 - bp->address <= CONDJUMP_MAX)
4407 bp->insert_place = insn;
4409 gen_far_branch (bp);
4413 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
4415 bp->near_label = label = gen_label_rtx ();
4416 bp->insert_place = insn;
4419 if (! redirect_jump (insn, label, 1))
4424 /* get_attr_length (insn) == 2 */
4425 /* Check if we have a pattern where reorg wants to redirect
4426 the branch to a label from an unconditional branch that
4428 /* We can't use JUMP_LABEL here because it might be undefined
4429 when not optimizing. */
4430 /* A syntax error might cause beyond to be NULL_RTX. */
4432 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
4436 && (GET_CODE (beyond) == JUMP_INSN
4437 || ((beyond = next_active_insn (beyond))
4438 && GET_CODE (beyond) == JUMP_INSN))
4439 && GET_CODE (PATTERN (beyond)) == SET
4440 && recog_memoized (beyond) == CODE_FOR_jump_compact
4442 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
4443 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4445 gen_block_redirect (beyond,
4446 INSN_ADDRESSES (INSN_UID (beyond)), 1);
4449 next = next_active_insn (insn);
4451 if ((GET_CODE (next) == JUMP_INSN
4452 || GET_CODE (next = next_active_insn (next)) == JUMP_INSN)
4453 && GET_CODE (PATTERN (next)) == SET
4454 && recog_memoized (next) == CODE_FOR_jump_compact
4456 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
4457 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4459 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
4461 else if (type == TYPE_JUMP || type == TYPE_RETURN)
4463 int addr = INSN_ADDRESSES (INSN_UID (insn));
4466 struct far_branch *bp;
4468 if (type == TYPE_JUMP)
4470 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
4471 dest_uid = get_dest_uid (far_label, max_uid);
4474 /* Parse errors can lead to labels outside
4476 if (! NEXT_INSN (far_label))
4481 JUMP_LABEL (insn) = far_label;
4482 LABEL_NUSES (far_label)++;
4484 redirect_jump (insn, NULL_RTX, 1);
4488 bp = uid_branch[dest_uid];
4491 bp = (struct far_branch *) alloca (sizeof *bp);
4492 uid_branch[dest_uid] = bp;
4493 bp->prev = far_branch_list;
4494 far_branch_list = bp;
4496 bp->far_label = far_label;
4498 LABEL_NUSES (far_label)++;
4500 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
4501 if (addr - bp->address <= CONDJUMP_MAX)
4502 emit_label_after (bp->near_label, PREV_INSN (insn));
4505 gen_far_branch (bp);
4511 bp->insert_place = insn;
4513 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
4515 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
4518 /* Generate all pending far branches,
4519 and free our references to the far labels. */
4520 while (far_branch_list)
4522 if (far_branch_list->near_label
4523 && ! NEXT_INSN (far_branch_list->near_label))
4524 gen_far_branch (far_branch_list);
4526 && far_branch_list->far_label
4527 && ! --LABEL_NUSES (far_branch_list->far_label))
4528 delete_insn (far_branch_list->far_label);
4529 far_branch_list = far_branch_list->prev;
4532 /* Instruction length information is no longer valid due to the new
4533 instructions that have been generated. */
4534 init_insn_lengths ();
4537 /* Dump out instruction addresses, which is useful for debugging the
4538 constant pool table stuff.
4540 If relaxing, output the label and pseudo-ops used to link together
4541 calls and the instruction which set the registers. */
4543 /* ??? The addresses printed by this routine for insns are nonsense for
4544 insns which are inside of a sequence where none of the inner insns have
4545 variable length. This is because the second pass of shorten_branches
4546 does not bother to update them. */
4549 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
4550 int noperands ATTRIBUTE_UNUSED)
4552 if (TARGET_DUMPISIZE)
4553 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
4559 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
4564 pattern = PATTERN (insn);
4565 if (GET_CODE (pattern) == PARALLEL)
4566 pattern = XVECEXP (pattern, 0, 0);
4567 if (GET_CODE (pattern) == CALL
4568 || (GET_CODE (pattern) == SET
4569 && (GET_CODE (SET_SRC (pattern)) == CALL
4570 || get_attr_type (insn) == TYPE_SFUNC)))
4571 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
4572 CODE_LABEL_NUMBER (XEXP (note, 0)));
4573 else if (GET_CODE (pattern) == SET)
4574 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4575 CODE_LABEL_NUMBER (XEXP (note, 0)));
4582 /* Dump out any constants accumulated in the final pass. These will
4586 output_jump_label_table (void)
4592 fprintf (asm_out_file, "\t.align 2\n");
4593 for (i = 0; i < pool_size; i++)
4595 pool_node *p = &pool_vector[i];
4597 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4598 CODE_LABEL_NUMBER (p->label));
4599 output_asm_insn (".long %O0", &p->value);
4607 /* A full frame looks like:
4611 [ if current_function_anonymous_args
4624 local-0 <- fp points here. */
4626 /* Number of bytes pushed for anonymous args, used to pass information
4627 between expand_prologue and expand_epilogue. */
4629 static int extra_push;
4631 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
4632 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
4633 for an epilogue and a negative value means that it's for a sibcall
4634 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
4635 all the registers that are about to be restored, and hence dead. */
4638 output_stack_adjust (int size, rtx reg, int epilogue_p,
4639 HARD_REG_SET *live_regs_mask)
4641 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
4644 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4649 if (CONST_OK_FOR_ADD (size))
4650 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
4651 /* Try to do it with two partial adjustments; however, we must make
4652 sure that the stack is properly aligned at all times, in case
4653 an interrupt occurs between the two partial adjustments. */
4654 else if (CONST_OK_FOR_ADD (size / 2 & -align)
4655 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
4657 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
4658 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
4664 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
4667 /* If TEMP is invalid, we could temporarily save a general
4668 register to MACL. However, there is currently no need
4669 to handle this case, so just abort when we see it. */
4671 || current_function_interrupt
4672 || ! call_used_regs[temp] || fixed_regs[temp])
4674 if (temp < 0 && ! current_function_interrupt
4675 && (TARGET_SHMEDIA || epilogue_p >= 0))
4678 COPY_HARD_REG_SET (temps, call_used_reg_set);
4679 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
4683 if (current_function_return_rtx)
4685 enum machine_mode mode;
4686 mode = GET_MODE (current_function_return_rtx);
4687 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
4688 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
4690 for (i = 0; i < nreg; i++)
4691 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
4692 if (current_function_calls_eh_return)
4694 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
4695 for (i = 0; i <= 3; i++)
4696 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
4699 if (TARGET_SHMEDIA && epilogue_p < 0)
4700 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
4701 CLEAR_HARD_REG_BIT (temps, i);
4702 if (epilogue_p <= 0)
4704 for (i = FIRST_PARM_REG;
4705 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
4706 CLEAR_HARD_REG_BIT (temps, i);
4707 if (cfun->static_chain_decl != NULL)
4708 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
4710 temp = scavenge_reg (&temps);
4712 if (temp < 0 && live_regs_mask)
4713 temp = scavenge_reg (live_regs_mask);
4716 /* If we reached here, the most likely case is the (sibcall)
4717 epilogue for non SHmedia. Put a special push/pop sequence
4718 for such case as the last resort. This looks lengthy but
4719 would not be problem because it seems to be very rare. */
4720 if (! TARGET_SHMEDIA && epilogue_p)
4722 rtx adj_reg, tmp_reg, mem;
4724 /* ??? There is still the slight possibility that r4 or r5
4725 have been reserved as fixed registers or assigned as
4726 global registers, and they change during an interrupt.
4727 There are possible ways to handle this:
4728 - If we are adjusting the frame pointer (r14), we can do
4729 with a single temp register and an ordinary push / pop
4731 - Grab any call-used or call-saved registers (i.e. not
4732 fixed or globals) for the temps we need. We might
4733 also grab r14 if we are adjusting the stack pointer.
4734 If we can't find enough available registers, issue
4735 a diagnostic and abort - the user must have reserved
4736 way too many registers.
4737 But since all this is rather unlikely to happen and
4738 would require extra testing, we just abort if r4 / r5
4739 are not available. */
4740 if (fixed_regs[4] || fixed_regs[5]
4741 || global_regs[4] || global_regs[5])
4744 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
4745 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
4746 emit_move_insn (gen_rtx_MEM (Pmode, reg), adj_reg);
4747 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
4748 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
4749 mem = gen_rtx_MEM (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
4750 emit_move_insn (mem, tmp_reg);
4751 emit_move_insn (tmp_reg, gen_rtx_MEM (Pmode, reg));
4752 mem = gen_rtx_MEM (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
4753 emit_move_insn (mem, tmp_reg);
4754 emit_move_insn (reg, adj_reg);
4755 mem = gen_rtx_MEM (Pmode, gen_rtx_POST_INC (Pmode, reg));
4756 emit_move_insn (adj_reg, mem);
4757 mem = gen_rtx_MEM (Pmode, gen_rtx_POST_INC (Pmode, reg));
4758 emit_move_insn (tmp_reg, mem);
4764 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
4766 /* If SIZE is negative, subtract the positive value.
4767 This sometimes allows a constant pool entry to be shared
4768 between prologue and epilogue code. */
4771 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
4772 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
4776 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
4777 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
4781 = (gen_rtx_EXPR_LIST
4782 (REG_FRAME_RELATED_EXPR,
4783 gen_rtx_SET (VOIDmode, reg,
4784 gen_rtx_PLUS (SImode, reg, GEN_INT (size))),
4794 RTX_FRAME_RELATED_P (x) = 1;
4798 /* Output RTL to push register RN onto the stack. */
4805 x = gen_push_fpul ();
4806 else if (rn == FPSCR_REG)
4807 x = gen_push_fpscr ();
4808 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4809 && FP_OR_XD_REGISTER_P (rn))
4811 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4813 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
4815 else if (TARGET_SH2E && FP_REGISTER_P (rn))
4816 x = gen_push_e (gen_rtx_REG (SFmode, rn));
4818 x = gen_push (gen_rtx_REG (SImode, rn));
4822 = gen_rtx_EXPR_LIST (REG_INC,
4823 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4827 /* Output RTL to pop register RN from the stack. */
4834 x = gen_pop_fpul ();
4835 else if (rn == FPSCR_REG)
4836 x = gen_pop_fpscr ();
4837 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4838 && FP_OR_XD_REGISTER_P (rn))
4840 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4842 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
4844 else if (TARGET_SH2E && FP_REGISTER_P (rn))
4845 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
4847 x = gen_pop (gen_rtx_REG (SImode, rn));
4851 = gen_rtx_EXPR_LIST (REG_INC,
4852 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4855 /* Generate code to push the regs specified in the mask. */
4858 push_regs (HARD_REG_SET *mask, int interrupt_handler)
4863 /* Push PR last; this gives better latencies after the prologue, and
4864 candidates for the return delay slot when there are no general
4865 registers pushed. */
4866 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4868 /* If this is an interrupt handler, and the SZ bit varies,
4869 and we have to push any floating point register, we need
4870 to switch to the correct precision first. */
4871 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
4872 && hard_regs_intersect_p (mask, ®_class_contents[DF_REGS]))
4874 HARD_REG_SET unsaved;
4877 COMPL_HARD_REG_SET (unsaved, *mask);
4878 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
4882 && (i != FPSCR_REG || ! skip_fpscr)
4883 && TEST_HARD_REG_BIT (*mask, i))
4886 if (TEST_HARD_REG_BIT (*mask, PR_REG))
4890 /* Calculate how much extra space is needed to save all callee-saved
4892 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4895 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
4898 int stack_space = 0;
4899 int interrupt_handler = sh_cfun_interrupt_handler_p ();
4901 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
4902 if ((! call_used_regs[reg] || interrupt_handler)
4903 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
4904 /* Leave space to save this target register on the stack,
4905 in case target register allocation wants to use it. */
4906 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4910 /* Decide whether we should reserve space for callee-save target registers,
4911 in case target register allocation wants to use them. REGS_SAVED is
4912 the space, in bytes, that is already required for register saves.
4913 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4916 shmedia_reserve_space_for_target_registers_p (int regs_saved,
4917 HARD_REG_SET *live_regs_mask)
4921 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
4924 /* Decide how much space to reserve for callee-save target registers
4925 in case target register allocation wants to use them.
4926 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4929 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
4931 if (shmedia_space_reserved_for_target_registers)
4932 return shmedia_target_regs_stack_space (live_regs_mask);
4937 /* Work out the registers which need to be saved, both as a mask and a
4938 count of saved words. Return the count.
4940 If doing a pragma interrupt function, then push all regs used by the
4941 function, and if we call another function (we can tell by looking at PR),
4942 make sure that all the regs it clobbers are safe too. */
4945 calc_live_regs (HARD_REG_SET *live_regs_mask)
4949 int interrupt_handler;
4950 int pr_live, has_call;
4952 interrupt_handler = sh_cfun_interrupt_handler_p ();
4954 CLEAR_HARD_REG_SET (*live_regs_mask);
4955 if (TARGET_SH4 && TARGET_FMOVD && interrupt_handler
4956 && regs_ever_live[FPSCR_REG])
4957 target_flags &= ~FPU_SINGLE_BIT;
4958 /* If we can save a lot of saves by switching to double mode, do that. */
4959 else if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE)
4960 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
4961 if (regs_ever_live[reg] && regs_ever_live[reg+1]
4962 && (! call_used_regs[reg] || (interrupt_handler && ! pragma_trapa))
4965 target_flags &= ~FPU_SINGLE_BIT;
4968 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
4969 knows how to use it. That means the pseudo originally allocated for
4970 the initial value can become the PR_MEDIA_REG hard register, as seen for
4971 execute/20010122-1.c:test9. */
4973 /* ??? this function is called from initial_elimination_offset, hence we
4974 can't use the result of sh_media_register_for_return here. */
4975 pr_live = sh_pr_n_sets ();
4978 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
4979 pr_live = (pr_initial
4980 ? (GET_CODE (pr_initial) != REG
4981 || REGNO (pr_initial) != (PR_REG))
4982 : regs_ever_live[PR_REG]);
4983 /* For Shcompact, if not optimizing, we end up with a memory reference
4984 using the return address pointer for __builtin_return_address even
4985 though there is no actual need to put the PR register on the stack. */
4986 pr_live |= regs_ever_live[RETURN_ADDRESS_POINTER_REGNUM];
4988 /* Force PR to be live if the prologue has to call the SHmedia
4989 argument decoder or register saver. */
4990 if (TARGET_SHCOMPACT
4991 && ((current_function_args_info.call_cookie
4992 & ~ CALL_COOKIE_RET_TRAMP (1))
4993 || current_function_has_nonlocal_label))
4995 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
4996 for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--)
4998 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
5000 : (interrupt_handler && ! pragma_trapa)
5001 ? (/* Need to save all the regs ever live. */
5002 (regs_ever_live[reg]
5003 || (call_used_regs[reg]
5004 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
5006 || (has_call && REGISTER_NATURAL_MODE (reg) == SImode
5007 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
5008 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
5009 && reg != RETURN_ADDRESS_POINTER_REGNUM
5010 && reg != T_REG && reg != GBR_REG
5011 /* Push fpscr only on targets which have FPU */
5012 && (reg != FPSCR_REG || TARGET_FPU_ANY))
5013 : (/* Only push those regs which are used and need to be saved. */
5016 && current_function_args_info.call_cookie
5017 && reg == (int) PIC_OFFSET_TABLE_REGNUM)
5018 || (regs_ever_live[reg] && ! call_used_regs[reg])
5019 || (current_function_calls_eh_return
5020 && (reg == (int) EH_RETURN_DATA_REGNO (0)
5021 || reg == (int) EH_RETURN_DATA_REGNO (1)
5022 || reg == (int) EH_RETURN_DATA_REGNO (2)
5023 || reg == (int) EH_RETURN_DATA_REGNO (3)))
5024 || ((reg == MACL_REG || reg == MACH_REG)
5025 && regs_ever_live[reg]
5026 && sh_cfun_attr_renesas_p ())
5029 SET_HARD_REG_BIT (*live_regs_mask, reg);
5030 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5032 if ((TARGET_SH4 || TARGET_SH5) && TARGET_FMOVD
5033 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
5035 if (FP_REGISTER_P (reg))
5037 if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
5039 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
5040 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
5043 else if (XD_REGISTER_P (reg))
5045 /* Must switch to double mode to access these registers. */
5046 target_flags &= ~FPU_SINGLE_BIT;
5051 /* If we have a target register optimization pass after prologue / epilogue
5052 threading, we need to assume all target registers will be live even if
5054 if (flag_branch_target_load_optimize2
5055 && TARGET_SAVE_ALL_TARGET_REGS
5056 && shmedia_space_reserved_for_target_registers)
5057 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
5058 if ((! call_used_regs[reg] || interrupt_handler)
5059 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
5061 SET_HARD_REG_BIT (*live_regs_mask, reg);
5062 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5064 /* If this is an interrupt handler, we don't have any call-clobbered
5065 registers we can conveniently use for target register save/restore.
5066 Make sure we save at least one general purpose register when we need
5067 to save target registers. */
5068 if (interrupt_handler
5069 && hard_regs_intersect_p (live_regs_mask,
5070 ®_class_contents[TARGET_REGS])
5071 && ! hard_regs_intersect_p (live_regs_mask,
5072 ®_class_contents[GENERAL_REGS]))
5074 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
5075 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
5081 /* Code to generate prologue and epilogue sequences */
5083 /* PUSHED is the number of bytes that are being pushed on the
5084 stack for register saves. Return the frame size, padded
5085 appropriately so that the stack stays properly aligned. */
5086 static HOST_WIDE_INT
5087 rounded_frame_size (int pushed)
5089 HOST_WIDE_INT size = get_frame_size ();
5090 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
5092 return ((size + pushed + align - 1) & -align) - pushed;
5095 /* Choose a call-clobbered target-branch register that remains
5096 unchanged along the whole function. We set it up as the return
5097 value in the prologue. */
5099 sh_media_register_for_return (void)
5104 if (! current_function_is_leaf)
5106 if (lookup_attribute ("interrupt_handler",
5107 DECL_ATTRIBUTES (current_function_decl)))
5110 tr0_used = flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
5112 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
5113 if (call_used_regs[regno] && ! regs_ever_live[regno])
5119 /* The maximum registers we need to save are:
5120 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
5121 - 32 floating point registers (for each pair, we save none,
5122 one single precision value, or a double precision value).
5123 - 8 target registers
5124 - add 1 entry for a delimiter. */
5125 #define MAX_SAVED_REGS (62+32+8)
5127 typedef struct save_entry_s
5136 /* There will be a delimiter entry with VOIDmode both at the start and the
5137 end of a filled in schedule. The end delimiter has the offset of the
5138 save with the smallest (i.e. most negative) offset. */
5139 typedef struct save_schedule_s
5141 save_entry entries[MAX_SAVED_REGS + 2];
5142 int temps[MAX_TEMPS+1];
5145 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
5146 use reverse order. Returns the last entry written to (not counting
5147 the delimiter). OFFSET_BASE is a number to be added to all offset
5151 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
5155 save_entry *entry = schedule->entries;
5159 if (! current_function_interrupt)
5160 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
5161 if (call_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
5162 && ! FUNCTION_ARG_REGNO_P (i)
5163 && i != FIRST_RET_REG
5164 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
5165 && ! (current_function_calls_eh_return
5166 && (i == EH_RETURN_STACKADJ_REGNO
5167 || ((unsigned) i <= EH_RETURN_DATA_REGNO (0)
5168 && (unsigned) i >= EH_RETURN_DATA_REGNO (3)))))
5169 schedule->temps[tmpx++] = i;
5171 entry->mode = VOIDmode;
5172 entry->offset = offset_base;
5174 /* We loop twice: first, we save 8-byte aligned registers in the
5175 higher addresses, that are known to be aligned. Then, we
5176 proceed to saving 32-bit registers that don't need 8-byte
5178 If this is an interrupt function, all registers that need saving
5179 need to be saved in full. moreover, we need to postpone saving
5180 target registers till we have saved some general purpose registers
5181 we can then use as scratch registers. */
5182 offset = offset_base;
5183 for (align = 1; align >= 0; align--)
5185 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
5186 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
5188 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5191 if (current_function_interrupt)
5193 if (TARGET_REGISTER_P (i))
5195 if (GENERAL_REGISTER_P (i))
5198 if (mode == SFmode && (i % 2) == 1
5199 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5200 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
5207 /* If we're doing the aligned pass and this is not aligned,
5208 or we're doing the unaligned pass and this is aligned,
5210 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
5214 if (current_function_interrupt
5215 && GENERAL_REGISTER_P (i)
5216 && tmpx < MAX_TEMPS)
5217 schedule->temps[tmpx++] = i;
5219 offset -= GET_MODE_SIZE (mode);
5222 entry->offset = offset;
5225 if (align && current_function_interrupt)
5226 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
5227 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
5229 offset -= GET_MODE_SIZE (DImode);
5231 entry->mode = DImode;
5232 entry->offset = offset;
5237 entry->mode = VOIDmode;
5238 entry->offset = offset;
5239 schedule->temps[tmpx] = -1;
5244 sh_expand_prologue (void)
5246 HARD_REG_SET live_regs_mask;
5249 int save_flags = target_flags;
5251 current_function_interrupt = sh_cfun_interrupt_handler_p ();
5253 /* We have pretend args if we had an object sent partially in registers
5254 and partially on the stack, e.g. a large structure. */
5255 output_stack_adjust (-current_function_pretend_args_size
5256 - current_function_args_info.stack_regs * 8,
5257 stack_pointer_rtx, 0, NULL);
5261 if (TARGET_SHCOMPACT && flag_pic && current_function_args_info.call_cookie)
5262 /* We're going to use the PIC register to load the address of the
5263 incoming-argument decoder and/or of the return trampoline from
5264 the GOT, so make sure the PIC register is preserved and
5266 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
5268 if (TARGET_SHCOMPACT
5269 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
5273 /* First, make all registers with incoming arguments that will
5274 be pushed onto the stack live, so that register renaming
5275 doesn't overwrite them. */
5276 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
5277 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info.call_cookie)
5278 >= NPARM_REGS (SImode) - reg)
5279 for (; reg < NPARM_REGS (SImode); reg++)
5280 emit_insn (gen_shcompact_preserve_incoming_args
5281 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
5282 else if (CALL_COOKIE_INT_REG_GET
5283 (current_function_args_info.call_cookie, reg) == 1)
5284 emit_insn (gen_shcompact_preserve_incoming_args
5285 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
5287 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
5289 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
5290 GEN_INT (current_function_args_info.call_cookie));
5291 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
5292 gen_rtx_REG (SImode, R0_REG));
5294 else if (TARGET_SHMEDIA)
5296 int tr = sh_media_register_for_return ();
5300 rtx insn = emit_move_insn (gen_rtx_REG (DImode, tr),
5301 gen_rtx_REG (DImode, PR_MEDIA_REG));
5303 /* ??? We should suppress saving pr when we don't need it, but this
5304 is tricky because of builtin_return_address. */
5306 /* If this function only exits with sibcalls, this copy
5307 will be flagged as dead. */
5308 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5314 /* Emit the code for SETUP_VARARGS. */
5315 if (current_function_stdarg)
5317 /* This is not used by the SH2E calling convention */
5318 if (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5
5319 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
5321 /* Push arg regs as if they'd been provided by caller in stack. */
5322 for (i = 0; i < NPARM_REGS(SImode); i++)
5324 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
5327 if (i >= (NPARM_REGS(SImode)
5328 - current_function_args_info.arg_count[(int) SH_ARG_INT]
5332 RTX_FRAME_RELATED_P (insn) = 0;
5338 /* If we're supposed to switch stacks at function entry, do so now. */
5340 emit_insn (gen_sp_switch_1 ());
5342 d = calc_live_regs (&live_regs_mask);
5343 /* ??? Maybe we could save some switching if we can move a mode switch
5344 that already happens to be at the function start into the prologue. */
5345 if (target_flags != save_flags && ! current_function_interrupt)
5346 emit_insn (gen_toggle_sz ());
5350 int offset_base, offset;
5352 int offset_in_r0 = -1;
5354 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
5355 int total_size, save_size;
5356 save_schedule schedule;
5360 if (call_used_regs[R0_REG] && ! fixed_regs[R0_REG]
5361 && ! current_function_interrupt)
5362 r0 = gen_rtx_REG (Pmode, R0_REG);
5364 /* D is the actual number of bytes that we need for saving registers,
5365 however, in initial_elimination_offset we have committed to using
5366 an additional TREGS_SPACE amount of bytes - in order to keep both
5367 addresses to arguments supplied by the caller and local variables
5368 valid, we must keep this gap. Place it between the incoming
5369 arguments and the actually saved registers in a bid to optimize
5370 locality of reference. */
5371 total_size = d + tregs_space;
5372 total_size += rounded_frame_size (total_size);
5373 save_size = total_size - rounded_frame_size (d);
5374 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
5375 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5376 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
5378 /* If adjusting the stack in a single step costs nothing extra, do so.
5379 I.e. either if a single addi is enough, or we need a movi anyway,
5380 and we don't exceed the maximum offset range (the test for the
5381 latter is conservative for simplicity). */
5383 && (CONST_OK_FOR_I10 (-total_size)
5384 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
5385 && total_size <= 2044)))
5386 d_rounding = total_size - save_size;
5388 offset_base = d + d_rounding;
5390 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
5393 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
5394 tmp_pnt = schedule.temps;
5395 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
5397 enum machine_mode mode = entry->mode;
5398 int reg = entry->reg;
5399 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
5401 offset = entry->offset;
5403 reg_rtx = gen_rtx_REG (mode, reg);
5405 mem_rtx = gen_rtx_MEM (mode,
5406 gen_rtx_PLUS (Pmode,
5410 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
5418 if (HAVE_PRE_DECREMENT
5419 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
5420 || mem_rtx == NULL_RTX
5421 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
5423 pre_dec = gen_rtx_MEM (mode,
5424 gen_rtx_PRE_DEC (Pmode, r0));
5426 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
5435 offset += GET_MODE_SIZE (mode);
5439 if (mem_rtx != NULL_RTX)
5442 if (offset_in_r0 == -1)
5444 emit_move_insn (r0, GEN_INT (offset));
5445 offset_in_r0 = offset;
5447 else if (offset != offset_in_r0)
5452 GEN_INT (offset - offset_in_r0)));
5453 offset_in_r0 += offset - offset_in_r0;
5456 if (pre_dec != NULL_RTX)
5462 (Pmode, r0, stack_pointer_rtx));
5466 offset -= GET_MODE_SIZE (mode);
5467 offset_in_r0 -= GET_MODE_SIZE (mode);
5472 mem_rtx = gen_rtx_MEM (mode, r0);
5474 mem_rtx = gen_rtx_MEM (mode,
5475 gen_rtx_PLUS (Pmode,
5479 /* We must not use an r0-based address for target-branch
5480 registers or for special registers without pre-dec
5481 memory addresses, since we store their values in r0
5483 if (TARGET_REGISTER_P (reg)
5484 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5485 && mem_rtx != pre_dec))
5489 if (TARGET_REGISTER_P (reg)
5490 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5491 && mem_rtx != pre_dec))
5493 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
5495 emit_move_insn (tmp_reg, reg_rtx);
5497 if (REGNO (tmp_reg) == R0_REG)
5501 if (refers_to_regno_p (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0))
5505 if (*++tmp_pnt <= 0)
5506 tmp_pnt = schedule.temps;
5513 /* Mark as interesting for dwarf cfi generator */
5514 insn = emit_move_insn (mem_rtx, reg_rtx);
5515 RTX_FRAME_RELATED_P (insn) = 1;
5517 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
5519 rtx reg_rtx = gen_rtx_REG (mode, reg);
5521 rtx mem_rtx = gen_rtx_MEM (mode,
5522 gen_rtx_PLUS (Pmode,
5526 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
5527 note_rtx = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set,
5529 REG_NOTES (insn) = note_rtx;
5534 if (entry->offset != d_rounding)
5538 push_regs (&live_regs_mask, current_function_interrupt);
5540 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5542 rtx insn = get_last_insn ();
5543 rtx last = emit_insn (gen_GOTaddr2picreg ());
5545 /* Mark these insns as possibly dead. Sometimes, flow2 may
5546 delete all uses of the PIC register. In this case, let it
5547 delete the initialization too. */
5550 insn = NEXT_INSN (insn);
5552 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5556 while (insn != last);
5559 if (SHMEDIA_REGS_STACK_ADJUST ())
5561 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5562 function_symbol (TARGET_FPU_ANY
5563 ? "__GCC_push_shmedia_regs"
5564 : "__GCC_push_shmedia_regs_nofpu"));
5565 /* This must NOT go through the PLT, otherwise mach and macl
5566 may be clobbered. */
5567 emit_insn (gen_shmedia_save_restore_regs_compact
5568 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
5571 if (target_flags != save_flags && ! current_function_interrupt)
5573 rtx insn = emit_insn (gen_toggle_sz ());
5575 /* If we're lucky, a mode switch in the function body will
5576 overwrite fpscr, turning this insn dead. Tell flow this
5577 insn is ok to delete. */
5578 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5583 target_flags = save_flags;
5585 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
5586 stack_pointer_rtx, 0, NULL);
5588 if (frame_pointer_needed)
5589 frame_insn (GEN_MOV (frame_pointer_rtx, stack_pointer_rtx));
5591 if (TARGET_SHCOMPACT
5592 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
5594 /* This must NOT go through the PLT, otherwise mach and macl
5595 may be clobbered. */
5596 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5597 function_symbol ("__GCC_shcompact_incoming_args"));
5598 emit_insn (gen_shcompact_incoming_args ());
5603 sh_expand_epilogue (bool sibcall_p)
5605 HARD_REG_SET live_regs_mask;
5609 int save_flags = target_flags;
5610 int frame_size, save_size;
5611 int fpscr_deferred = 0;
5612 int e = sibcall_p ? -1 : 1;
5614 d = calc_live_regs (&live_regs_mask);
5617 frame_size = rounded_frame_size (d);
5621 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
5623 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
5624 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5625 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
5627 total_size = d + tregs_space;
5628 total_size += rounded_frame_size (total_size);
5629 save_size = total_size - frame_size;
5631 /* If adjusting the stack in a single step costs nothing extra, do so.
5632 I.e. either if a single addi is enough, or we need a movi anyway,
5633 and we don't exceed the maximum offset range (the test for the
5634 latter is conservative for simplicity). */
5636 && ! frame_pointer_needed
5637 && (CONST_OK_FOR_I10 (total_size)
5638 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
5639 && total_size <= 2044)))
5640 d_rounding = frame_size;
5642 frame_size -= d_rounding;
5645 if (frame_pointer_needed)
5647 output_stack_adjust (frame_size, frame_pointer_rtx, e, &live_regs_mask);
5649 /* We must avoid moving the stack pointer adjustment past code
5650 which reads from the local frame, else an interrupt could
5651 occur after the SP adjustment and clobber data in the local
5653 emit_insn (gen_blockage ());
5654 emit_insn (GEN_MOV (stack_pointer_rtx, frame_pointer_rtx));
5656 else if (frame_size)
5658 /* We must avoid moving the stack pointer adjustment past code
5659 which reads from the local frame, else an interrupt could
5660 occur after the SP adjustment and clobber data in the local
5662 emit_insn (gen_blockage ());
5663 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
5666 if (SHMEDIA_REGS_STACK_ADJUST ())
5668 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5669 function_symbol (TARGET_FPU_ANY
5670 ? "__GCC_pop_shmedia_regs"
5671 : "__GCC_pop_shmedia_regs_nofpu"));
5672 /* This must NOT go through the PLT, otherwise mach and macl
5673 may be clobbered. */
5674 emit_insn (gen_shmedia_save_restore_regs_compact
5675 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
5678 /* Pop all the registers. */
5680 if (target_flags != save_flags && ! current_function_interrupt)
5681 emit_insn (gen_toggle_sz ());
5684 int offset_base, offset;
5685 int offset_in_r0 = -1;
5687 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
5688 save_schedule schedule;
5692 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
5693 offset_base = -entry[1].offset + d_rounding;
5694 tmp_pnt = schedule.temps;
5695 for (; entry->mode != VOIDmode; entry--)
5697 enum machine_mode mode = entry->mode;
5698 int reg = entry->reg;
5699 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
5701 offset = offset_base + entry->offset;
5702 reg_rtx = gen_rtx_REG (mode, reg);
5704 mem_rtx = gen_rtx_MEM (mode,
5705 gen_rtx_PLUS (Pmode,
5709 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
5715 if (HAVE_POST_INCREMENT
5716 && (offset == offset_in_r0
5717 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
5718 && mem_rtx == NULL_RTX)
5719 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
5721 post_inc = gen_rtx_MEM (mode,
5722 gen_rtx_POST_INC (Pmode, r0));
5724 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
5727 post_inc = NULL_RTX;
5736 if (mem_rtx != NULL_RTX)
5739 if (offset_in_r0 == -1)
5741 emit_move_insn (r0, GEN_INT (offset));
5742 offset_in_r0 = offset;
5744 else if (offset != offset_in_r0)
5749 GEN_INT (offset - offset_in_r0)));
5750 offset_in_r0 += offset - offset_in_r0;
5753 if (post_inc != NULL_RTX)
5759 (Pmode, r0, stack_pointer_rtx));
5765 offset_in_r0 += GET_MODE_SIZE (mode);
5768 mem_rtx = gen_rtx_MEM (mode, r0);
5770 mem_rtx = gen_rtx_MEM (mode,
5771 gen_rtx_PLUS (Pmode,
5775 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5776 && mem_rtx != post_inc)
5780 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5781 && mem_rtx != post_inc)
5783 insn = emit_move_insn (r0, mem_rtx);
5786 else if (TARGET_REGISTER_P (reg))
5788 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
5790 /* Give the scheduler a bit of freedom by using up to
5791 MAX_TEMPS registers in a round-robin fashion. */
5792 insn = emit_move_insn (tmp_reg, mem_rtx);
5795 tmp_pnt = schedule.temps;
5798 insn = emit_move_insn (reg_rtx, mem_rtx);
5799 if (reg == PR_MEDIA_REG && sh_media_register_for_return () >= 0)
5800 /* This is dead, unless we return with a sibcall. */
5801 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5806 if (entry->offset + offset_base != d + d_rounding)
5809 else /* ! TARGET_SH5 */
5812 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
5814 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5816 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
5818 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
5819 && hard_regs_intersect_p (&live_regs_mask,
5820 ®_class_contents[DF_REGS]))
5822 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j))
5824 if (j == FIRST_FP_REG && fpscr_deferred)
5829 if (target_flags != save_flags && ! current_function_interrupt)
5830 emit_insn (gen_toggle_sz ());
5831 target_flags = save_flags;
5833 output_stack_adjust (extra_push + current_function_pretend_args_size
5834 + save_size + d_rounding
5835 + current_function_args_info.stack_regs * 8,
5836 stack_pointer_rtx, e, NULL);
5838 if (current_function_calls_eh_return)
5839 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
5840 EH_RETURN_STACKADJ_RTX));
5842 /* Switch back to the normal stack if necessary. */
5844 emit_insn (gen_sp_switch_2 ());
5846 /* Tell flow the insn that pops PR isn't dead. */
5847 /* PR_REG will never be live in SHmedia mode, and we don't need to
5848 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
5849 by the return pattern. */
5850 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
5851 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
5854 static int sh_need_epilogue_known = 0;
5857 sh_need_epilogue (void)
5859 if (! sh_need_epilogue_known)
5864 sh_expand_epilogue (0);
5865 epilogue = get_insns ();
5867 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
5869 return sh_need_epilogue_known > 0;
5872 /* Emit code to change the current function's return address to RA.
5873 TEMP is available as a scratch register, if needed. */
5876 sh_set_return_address (rtx ra, rtx tmp)
5878 HARD_REG_SET live_regs_mask;
5880 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
5883 d = calc_live_regs (&live_regs_mask);
5885 /* If pr_reg isn't life, we can set it (or the register given in
5886 sh_media_register_for_return) directly. */
5887 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
5893 int rr_regno = sh_media_register_for_return ();
5898 rr = gen_rtx_REG (DImode, rr_regno);
5901 rr = gen_rtx_REG (SImode, pr_reg);
5903 emit_insn (GEN_MOV (rr, ra));
5904 /* Tell flow the register for return isn't dead. */
5905 emit_insn (gen_rtx_USE (VOIDmode, rr));
5912 save_schedule schedule;
5915 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
5916 offset = entry[1].offset;
5917 for (; entry->mode != VOIDmode; entry--)
5918 if (entry->reg == pr_reg)
5921 /* We can't find pr register. */
5925 offset = entry->offset - offset;
5926 pr_offset = (rounded_frame_size (d) + offset
5927 + SHMEDIA_REGS_STACK_ADJUST ());
5930 pr_offset = rounded_frame_size (d);
5932 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
5933 emit_insn (GEN_ADD3 (tmp, tmp, frame_pointer_rtx));
5935 tmp = gen_rtx_MEM (Pmode, tmp);
5936 emit_insn (GEN_MOV (tmp, ra));
5939 /* Clear variables at function end. */
5942 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
5943 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5945 trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
5946 sh_need_epilogue_known = 0;
5947 sp_switch = NULL_RTX;
5951 sh_builtin_saveregs (void)
5953 /* First unnamed integer register. */
5954 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
5955 /* Number of integer registers we need to save. */
5956 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
5957 /* First unnamed SFmode float reg */
5958 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
5959 /* Number of SFmode float regs to save. */
5960 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
5963 HOST_WIDE_INT alias_set;
5969 int pushregs = n_intregs;
5971 while (pushregs < NPARM_REGS (SImode) - 1
5972 && (CALL_COOKIE_INT_REG_GET
5973 (current_function_args_info.call_cookie,
5974 NPARM_REGS (SImode) - pushregs)
5977 current_function_args_info.call_cookie
5978 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
5983 if (pushregs == NPARM_REGS (SImode))
5984 current_function_args_info.call_cookie
5985 |= (CALL_COOKIE_INT_REG (0, 1)
5986 | CALL_COOKIE_STACKSEQ (pushregs - 1));
5988 current_function_args_info.call_cookie
5989 |= CALL_COOKIE_STACKSEQ (pushregs);
5991 current_function_pretend_args_size += 8 * n_intregs;
5993 if (TARGET_SHCOMPACT)
5997 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
5999 error ("__builtin_saveregs not supported by this subtarget");
6006 /* Allocate block of memory for the regs. */
6007 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
6008 Or can assign_stack_local accept a 0 SIZE argument? */
6009 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
6012 regbuf = gen_rtx_MEM (BLKmode,
6013 gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
6014 else if (n_floatregs & 1)
6018 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
6019 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
6020 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
6021 regbuf = change_address (regbuf, BLKmode, addr);
6024 regbuf = assign_stack_local (BLKmode, bufsize, 0);
6025 alias_set = get_varargs_alias_set ();
6026 set_mem_alias_set (regbuf, alias_set);
6029 This is optimized to only save the regs that are necessary. Explicitly
6030 named args need not be saved. */
6032 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
6033 adjust_address (regbuf, BLKmode,
6034 n_floatregs * UNITS_PER_WORD),
6038 /* Return the address of the regbuf. */
6039 return XEXP (regbuf, 0);
6042 This is optimized to only save the regs that are necessary. Explicitly
6043 named args need not be saved.
6044 We explicitly build a pointer to the buffer because it halves the insn
6045 count when not optimizing (otherwise the pointer is built for each reg
6047 We emit the moves in reverse order so that we can use predecrement. */
6049 fpregs = gen_reg_rtx (Pmode);
6050 emit_move_insn (fpregs, XEXP (regbuf, 0));
6051 emit_insn (gen_addsi3 (fpregs, fpregs,
6052 GEN_INT (n_floatregs * UNITS_PER_WORD)));
6056 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
6058 emit_insn (gen_addsi3 (fpregs, fpregs,
6059 GEN_INT (-2 * UNITS_PER_WORD)));
6060 mem = gen_rtx_MEM (DFmode, fpregs);
6061 set_mem_alias_set (mem, alias_set);
6062 emit_move_insn (mem,
6063 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
6065 regno = first_floatreg;
6068 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
6069 mem = gen_rtx_MEM (SFmode, fpregs);
6070 set_mem_alias_set (mem, alias_set);
6071 emit_move_insn (mem,
6072 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
6073 - (TARGET_LITTLE_ENDIAN != 0)));
6077 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
6081 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
6082 mem = gen_rtx_MEM (SFmode, fpregs);
6083 set_mem_alias_set (mem, alias_set);
6084 emit_move_insn (mem,
6085 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
6088 /* Return the address of the regbuf. */
6089 return XEXP (regbuf, 0);
6092 /* Define the `__builtin_va_list' type for the ABI. */
6095 sh_build_builtin_va_list (void)
6097 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
6100 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
6101 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
6102 return ptr_type_node;
6104 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6106 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
6108 f_next_o_limit = build_decl (FIELD_DECL,
6109 get_identifier ("__va_next_o_limit"),
6111 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
6113 f_next_fp_limit = build_decl (FIELD_DECL,
6114 get_identifier ("__va_next_fp_limit"),
6116 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
6119 DECL_FIELD_CONTEXT (f_next_o) = record;
6120 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
6121 DECL_FIELD_CONTEXT (f_next_fp) = record;
6122 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
6123 DECL_FIELD_CONTEXT (f_next_stack) = record;
6125 TYPE_FIELDS (record) = f_next_o;
6126 TREE_CHAIN (f_next_o) = f_next_o_limit;
6127 TREE_CHAIN (f_next_o_limit) = f_next_fp;
6128 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
6129 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
6131 layout_type (record);
6136 /* Implement `va_start' for varargs and stdarg. */
6139 sh_va_start (tree valist, rtx nextarg)
6141 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
6142 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
6148 expand_builtin_saveregs ();
6149 std_expand_builtin_va_start (valist, nextarg);
6153 if ((! TARGET_SH2E && ! TARGET_SH4)
6154 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
6156 std_expand_builtin_va_start (valist, nextarg);
6160 f_next_o = TYPE_FIELDS (va_list_type_node);
6161 f_next_o_limit = TREE_CHAIN (f_next_o);
6162 f_next_fp = TREE_CHAIN (f_next_o_limit);
6163 f_next_fp_limit = TREE_CHAIN (f_next_fp);
6164 f_next_stack = TREE_CHAIN (f_next_fp_limit);
6166 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
6167 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
6168 valist, f_next_o_limit);
6169 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp);
6170 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
6171 valist, f_next_fp_limit);
6172 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
6173 valist, f_next_stack);
6175 /* Call __builtin_saveregs. */
6176 u = make_tree (ptr_type_node, expand_builtin_saveregs ());
6177 t = build (MODIFY_EXPR, ptr_type_node, next_fp, u);
6178 TREE_SIDE_EFFECTS (t) = 1;
6179 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6181 nfp = current_function_args_info.arg_count[SH_ARG_FLOAT];
6186 u = fold (build (PLUS_EXPR, ptr_type_node, u,
6187 build_int_2 (UNITS_PER_WORD * nfp, 0)));
6188 t = build (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
6189 TREE_SIDE_EFFECTS (t) = 1;
6190 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6192 t = build (MODIFY_EXPR, ptr_type_node, next_o, u);
6193 TREE_SIDE_EFFECTS (t) = 1;
6194 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6196 nint = current_function_args_info.arg_count[SH_ARG_INT];
6201 u = fold (build (PLUS_EXPR, ptr_type_node, u,
6202 build_int_2 (UNITS_PER_WORD * nint, 0)));
6203 t = build (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
6204 TREE_SIDE_EFFECTS (t) = 1;
6205 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6207 u = make_tree (ptr_type_node, nextarg);
6208 t = build (MODIFY_EXPR, ptr_type_node, next_stack, u);
6209 TREE_SIDE_EFFECTS (t) = 1;
6210 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6213 /* Implement `va_arg'. */
6216 sh_va_arg (tree valist, tree type)
6218 HOST_WIDE_INT size, rsize;
6219 tree tmp, pptr_type_node;
6221 rtx result_ptr, result = NULL_RTX;
6222 int pass_by_ref = MUST_PASS_IN_STACK (TYPE_MODE (type), type);
6225 size = int_size_in_bytes (type);
6226 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6227 pptr_type_node = build_pointer_type (ptr_type_node);
6230 type = build_pointer_type (type);
6232 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
6233 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
6235 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
6236 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
6240 f_next_o = TYPE_FIELDS (va_list_type_node);
6241 f_next_o_limit = TREE_CHAIN (f_next_o);
6242 f_next_fp = TREE_CHAIN (f_next_o_limit);
6243 f_next_fp_limit = TREE_CHAIN (f_next_fp);
6244 f_next_stack = TREE_CHAIN (f_next_fp_limit);
6246 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
6247 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
6248 valist, f_next_o_limit);
6249 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp),
6251 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
6252 valist, f_next_fp_limit);
6253 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
6254 valist, f_next_stack);
6256 /* Structures with a single member with a distinct mode are passed
6257 like their member. This is relevant if the latter has a REAL_TYPE
6258 or COMPLEX_TYPE type. */
6259 if (TREE_CODE (type) == RECORD_TYPE
6260 && TYPE_FIELDS (type)
6261 && TREE_CODE (TYPE_FIELDS (type)) == FIELD_DECL
6262 && (TREE_CODE (TREE_TYPE (TYPE_FIELDS (type))) == REAL_TYPE
6263 || TREE_CODE (TREE_TYPE (TYPE_FIELDS (type))) == COMPLEX_TYPE)
6264 && TREE_CHAIN (TYPE_FIELDS (type)) == NULL_TREE)
6265 type = TREE_TYPE (TYPE_FIELDS (type));
6268 pass_as_float = ((TREE_CODE (type) == REAL_TYPE && size <= 8)
6269 || (TREE_CODE (type) == COMPLEX_TYPE
6270 && TREE_CODE (TREE_TYPE (type)) == REAL_TYPE
6275 pass_as_float = (TREE_CODE (type) == REAL_TYPE && size == 4);
6278 addr_rtx = gen_reg_rtx (Pmode);
6279 lab_false = gen_label_rtx ();
6280 lab_over = gen_label_rtx ();
6282 tmp = make_tree (pptr_type_node, addr_rtx);
6283 valist = build1 (INDIRECT_REF, ptr_type_node, tmp);
6288 = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
6289 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
6291 emit_cmp_and_jump_insns (expand_expr (next_fp, NULL_RTX, Pmode,
6293 expand_expr (next_fp_limit, NULL_RTX,
6294 Pmode, EXPAND_NORMAL),
6295 GE, const1_rtx, Pmode, 1, lab_false);
6297 if (TYPE_ALIGN (type) > BITS_PER_WORD
6298 || (((TREE_CODE (type) == REAL_TYPE && size == 8) || size == 16)
6299 && (n_floatregs & 1)))
6301 tmp = build (BIT_AND_EXPR, ptr_type_node, next_fp,
6302 build_int_2 (UNITS_PER_WORD, 0));
6303 tmp = build (PLUS_EXPR, ptr_type_node, next_fp, tmp);
6304 tmp = build (MODIFY_EXPR, ptr_type_node, next_fp, tmp);
6305 TREE_SIDE_EFFECTS (tmp) = 1;
6306 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
6309 tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp);
6310 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6312 emit_move_insn (addr_rtx, r);
6314 #ifdef FUNCTION_ARG_SCmode_WART
6315 if (TYPE_MODE (type) == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
6317 rtx addr, real, imag, result_value, slot;
6318 tree subtype = TREE_TYPE (type);
6320 addr = std_expand_builtin_va_arg (valist, subtype);
6321 #ifdef POINTERS_EXTEND_UNSIGNED
6322 if (GET_MODE (addr) != Pmode)
6323 addr = convert_memory_address (Pmode, addr);
6325 imag = gen_rtx_MEM (TYPE_MODE (type), addr);
6326 set_mem_alias_set (imag, get_varargs_alias_set ());
6328 addr = std_expand_builtin_va_arg (valist, subtype);
6329 #ifdef POINTERS_EXTEND_UNSIGNED
6330 if (GET_MODE (addr) != Pmode)
6331 addr = convert_memory_address (Pmode, addr);
6333 real = gen_rtx_MEM (TYPE_MODE (type), addr);
6334 set_mem_alias_set (real, get_varargs_alias_set ());
6336 result_value = gen_rtx_CONCAT (SCmode, real, imag);
6337 /* ??? this interface is stupid - why require a pointer? */
6338 result = gen_reg_rtx (Pmode);
6339 slot = assign_stack_temp (SCmode, 8, 0);
6340 emit_move_insn (slot, result_value);
6341 emit_move_insn (result, XEXP (slot, 0));
6343 #endif /* FUNCTION_ARG_SCmode_WART */
6345 emit_jump_insn (gen_jump (lab_over));
6347 emit_label (lab_false);
6349 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
6350 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6352 emit_move_insn (addr_rtx, r);
6356 tmp = build (PLUS_EXPR, ptr_type_node, next_o,
6357 build_int_2 (rsize, 0));
6359 emit_cmp_and_jump_insns (expand_expr (tmp, NULL_RTX, Pmode,
6361 expand_expr (next_o_limit, NULL_RTX,
6362 Pmode, EXPAND_NORMAL),
6363 GT, const1_rtx, Pmode, 1, lab_false);
6365 tmp = build1 (ADDR_EXPR, pptr_type_node, next_o);
6366 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6368 emit_move_insn (addr_rtx, r);
6370 emit_jump_insn (gen_jump (lab_over));
6372 emit_label (lab_false);
6374 if (size > 4 && ! TARGET_SH4)
6376 tmp = build (MODIFY_EXPR, ptr_type_node, next_o, next_o_limit);
6377 TREE_SIDE_EFFECTS (tmp) = 1;
6378 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
6381 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
6382 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
6384 emit_move_insn (addr_rtx, r);
6388 emit_label (lab_over);
6391 /* ??? In va-sh.h, there had been code to make values larger than
6392 size 8 indirect. This does not match the FUNCTION_ARG macros. */
6394 result_ptr = std_expand_builtin_va_arg (valist, type);
6397 emit_move_insn (result, result_ptr);
6398 emit_label (lab_over);
6401 result = result_ptr;
6405 #ifdef POINTERS_EXTEND_UNSIGNED
6406 if (GET_MODE (addr) != Pmode)
6407 addr = convert_memory_address (Pmode, result);
6409 result = gen_rtx_MEM (ptr_mode, force_reg (Pmode, result));
6410 set_mem_alias_set (result, get_varargs_alias_set ());
6412 /* ??? expand_builtin_va_arg will also set the alias set of the dereferenced
6413 argument to the varargs alias set. */
6418 sh_promote_prototypes (tree type)
6424 return ! sh_attr_renesas_p (type);
6427 /* Define where to put the arguments to a function.
6428 Value is zero to push the argument on the stack,
6429 or a hard register in which to store the argument.
6431 MODE is the argument's machine mode.
6432 TYPE is the data type of the argument (as a tree).
6433 This is null for libcalls where that information may
6435 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6436 the preceding args and about the function being called.
6437 NAMED is nonzero if this argument is a named parameter
6438 (otherwise it is an extra parameter matching an ellipsis).
6440 On SH the first args are normally in registers
6441 and the rest are pushed. Any arg that starts within the first
6442 NPARM_REGS words is at least partially passed in a register unless
6443 its data type forbids. */
6447 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
6448 tree type, int named)
6450 if (! TARGET_SH5 && mode == VOIDmode)
6451 return GEN_INT (ca->renesas_abi ? 1 : 0);
6454 && PASS_IN_REG_P (*ca, mode, type)
6455 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
6459 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
6460 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
6462 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
6463 gen_rtx_REG (SFmode,
6465 + (ROUND_REG (*ca, mode) ^ 1)),
6467 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
6468 gen_rtx_REG (SFmode,
6470 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
6472 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
6475 /* If the alignment of a DF value causes an SF register to be
6476 skipped, we will use that skipped register for the next SF
6478 if ((TARGET_HITACHI || ca->renesas_abi)
6479 && ca->free_single_fp_reg
6481 return gen_rtx_REG (mode, ca->free_single_fp_reg);
6483 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
6484 ^ (mode == SFmode && TARGET_SH4
6485 && TARGET_LITTLE_ENDIAN != 0
6486 && ! TARGET_HITACHI && ! ca->renesas_abi);
6487 return gen_rtx_REG (mode, regno);
6493 if (mode == VOIDmode && TARGET_SHCOMPACT)
6494 return GEN_INT (ca->call_cookie);
6496 /* The following test assumes unnamed arguments are promoted to
6498 if (mode == SFmode && ca->free_single_fp_reg)
6499 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
6501 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
6502 && (named || ! ca->prototype_p)
6503 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
6505 if (! ca->prototype_p && TARGET_SHMEDIA)
6506 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
6508 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
6510 + ca->arg_count[(int) SH_ARG_FLOAT]);
6513 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
6514 && (! TARGET_SHCOMPACT
6515 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
6516 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
6519 return gen_rtx_REG (mode, (FIRST_PARM_REG
6520 + ca->arg_count[(int) SH_ARG_INT]));
6529 /* Update the data in CUM to advance over an argument
6530 of mode MODE and data type TYPE.
6531 (TYPE is null for libcalls where that information may not be
6535 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
6536 tree type, int named)
6540 else if (TARGET_SH5)
6542 tree type2 = (ca->byref && type
6545 enum machine_mode mode2 = (ca->byref && type
6548 int dwords = ((ca->byref
6551 ? int_size_in_bytes (type2)
6552 : GET_MODE_SIZE (mode2)) + 7) / 8;
6553 int numregs = MIN (dwords, NPARM_REGS (SImode)
6554 - ca->arg_count[(int) SH_ARG_INT]);
6558 ca->arg_count[(int) SH_ARG_INT] += numregs;
6559 if (TARGET_SHCOMPACT
6560 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
6563 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
6565 /* N.B. We want this also for outgoing. */
6566 ca->stack_regs += numregs;
6571 ca->stack_regs += numregs;
6572 ca->byref_regs += numregs;
6576 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
6580 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
6583 else if (dwords > numregs)
6585 int pushregs = numregs;
6587 if (TARGET_SHCOMPACT)
6588 ca->stack_regs += numregs;
6589 while (pushregs < NPARM_REGS (SImode) - 1
6590 && (CALL_COOKIE_INT_REG_GET
6592 NPARM_REGS (SImode) - pushregs)
6596 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
6600 if (numregs == NPARM_REGS (SImode))
6602 |= CALL_COOKIE_INT_REG (0, 1)
6603 | CALL_COOKIE_STACKSEQ (numregs - 1);
6606 |= CALL_COOKIE_STACKSEQ (numregs);
6609 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
6610 && (named || ! ca->prototype_p))
6612 if (mode2 == SFmode && ca->free_single_fp_reg)
6613 ca->free_single_fp_reg = 0;
6614 else if (ca->arg_count[(int) SH_ARG_FLOAT]
6615 < NPARM_REGS (SFmode))
6618 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
6620 - ca->arg_count[(int) SH_ARG_FLOAT]);
6622 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
6624 if (TARGET_SHCOMPACT && ! ca->prototype_p)
6626 if (ca->outgoing && numregs > 0)
6630 |= (CALL_COOKIE_INT_REG
6631 (ca->arg_count[(int) SH_ARG_INT]
6632 - numregs + ((numfpregs - 2) / 2),
6633 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
6636 while (numfpregs -= 2);
6638 else if (mode2 == SFmode && (named)
6639 && (ca->arg_count[(int) SH_ARG_FLOAT]
6640 < NPARM_REGS (SFmode)))
6641 ca->free_single_fp_reg
6642 = FIRST_FP_PARM_REG - numfpregs
6643 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
6649 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
6651 /* Note that we've used the skipped register. */
6652 if (mode == SFmode && ca->free_single_fp_reg)
6654 ca->free_single_fp_reg = 0;
6657 /* When we have a DF after an SF, there's an SF register that get
6658 skipped in order to align the DF value. We note this skipped
6659 register, because the next SF value will use it, and not the
6660 SF that follows the DF. */
6662 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
6664 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
6665 + BASE_ARG_REG (mode));
6669 if (! (TARGET_SH4 || ca->renesas_abi)
6670 || PASS_IN_REG_P (*ca, mode, type))
6671 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
6672 = (ROUND_REG (*ca, mode)
6674 ? ROUND_ADVANCE (int_size_in_bytes (type))
6675 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
6678 /* The Renesas calling convention doesn't quite fit into this scheme since
6679 the address is passed like an invisible argument, but one that is always
6680 passed in memory. */
6682 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
6684 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
6686 return gen_rtx_REG (Pmode, 2);
6689 /* Worker function for TARGET_RETURN_IN_MEMORY. */
6692 sh_return_in_memory (tree type, tree fndecl)
6696 if (TYPE_MODE (type) == BLKmode)
6697 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
6699 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
6703 return (TYPE_MODE (type) == BLKmode
6704 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
6705 && TREE_CODE (type) == RECORD_TYPE));
6709 /* We actually emit the code in sh_expand_prologue. We used to use
6710 a static variable to flag that we need to emit this code, but that
6711 doesn't when inlining, when functions are deferred and then emitted
6712 later. Fortunately, we already have two flags that are part of struct
6713 function that tell if a function uses varargs or stdarg. */
6715 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
6716 enum machine_mode mode ATTRIBUTE_UNUSED,
6717 tree type ATTRIBUTE_UNUSED,
6718 int *pretend_arg_size ATTRIBUTE_UNUSED,
6719 int second_time ATTRIBUTE_UNUSED)
6721 if (! current_function_stdarg)
6726 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
6732 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
6734 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
6738 /* Define the offset between two registers, one to be eliminated, and
6739 the other its replacement, at the start of a routine. */
6742 initial_elimination_offset (int from, int to)
6745 int regs_saved_rounding = 0;
6746 int total_saved_regs_space;
6747 int total_auto_space;
6748 int save_flags = target_flags;
6750 HARD_REG_SET live_regs_mask;
6752 shmedia_space_reserved_for_target_registers = false;
6753 regs_saved = calc_live_regs (&live_regs_mask);
6754 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
6756 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
6758 shmedia_space_reserved_for_target_registers = true;
6759 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
6762 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
6763 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6764 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
6766 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
6767 copy_flags = target_flags;
6768 target_flags = save_flags;
6770 total_saved_regs_space = regs_saved + regs_saved_rounding;
6772 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
6773 return total_saved_regs_space + total_auto_space
6774 + current_function_args_info.byref_regs * 8;
6776 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
6777 return total_saved_regs_space + total_auto_space
6778 + current_function_args_info.byref_regs * 8;
6780 /* Initial gap between fp and sp is 0. */
6781 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
6784 if (from == RETURN_ADDRESS_POINTER_REGNUM
6785 && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
6789 int n = total_saved_regs_space;
6790 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
6791 save_schedule schedule;
6794 n += total_auto_space;
6796 /* If it wasn't saved, there's not much we can do. */
6797 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
6800 target_flags = copy_flags;
6802 sh5_schedule_saves (&live_regs_mask, &schedule, n);
6803 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6804 if (entry->reg == pr_reg)
6806 target_flags = save_flags;
6807 return entry->offset;
6812 return total_auto_space;
6818 /* Handle machine specific pragmas to be semi-compatible with Renesas
6822 sh_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
6824 pragma_interrupt = 1;
6828 sh_pr_trapa (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
6830 pragma_interrupt = pragma_trapa = 1;
6834 sh_pr_nosave_low_regs (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
6836 pragma_nosave_low_regs = 1;
6839 /* Generate 'handle_interrupt' attribute for decls */
6842 sh_insert_attributes (tree node, tree *attributes)
6844 if (! pragma_interrupt
6845 || TREE_CODE (node) != FUNCTION_DECL)
6848 /* We are only interested in fields. */
6849 if (TREE_CODE_CLASS (TREE_CODE (node)) != 'd')
6852 /* Add a 'handle_interrupt' attribute. */
6853 * attributes = tree_cons (get_identifier ("interrupt_handler"), NULL, * attributes);
6858 /* Supported attributes:
6860 interrupt_handler -- specifies this function is an interrupt handler.
6862 sp_switch -- specifies an alternate stack for an interrupt handler
6865 trap_exit -- use a trapa to exit an interrupt function instead of
6868 renesas -- use Renesas calling/layout conventions (functions and
6873 const struct attribute_spec sh_attribute_table[] =
6875 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6876 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
6877 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
6878 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
6879 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
6880 { NULL, 0, 0, false, false, false, NULL }
6883 /* Handle an "interrupt_handler" attribute; arguments as in
6884 struct attribute_spec.handler. */
6886 sh_handle_interrupt_handler_attribute (tree *node, tree name,
6887 tree args ATTRIBUTE_UNUSED,
6888 int flags ATTRIBUTE_UNUSED,
6891 if (TREE_CODE (*node) != FUNCTION_DECL)
6893 warning ("`%s' attribute only applies to functions",
6894 IDENTIFIER_POINTER (name));
6895 *no_add_attrs = true;
6897 else if (TARGET_SHCOMPACT)
6899 error ("attribute interrupt_handler is not compatible with -m5-compact");
6900 *no_add_attrs = true;
6906 /* Handle an "sp_switch" attribute; arguments as in
6907 struct attribute_spec.handler. */
6909 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
6910 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
6912 if (TREE_CODE (*node) != FUNCTION_DECL)
6914 warning ("`%s' attribute only applies to functions",
6915 IDENTIFIER_POINTER (name));
6916 *no_add_attrs = true;
6918 else if (!pragma_interrupt)
6920 /* The sp_switch attribute only has meaning for interrupt functions. */
6921 warning ("`%s' attribute only applies to interrupt functions",
6922 IDENTIFIER_POINTER (name));
6923 *no_add_attrs = true;
6925 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
6927 /* The argument must be a constant string. */
6928 warning ("`%s' attribute argument not a string constant",
6929 IDENTIFIER_POINTER (name));
6930 *no_add_attrs = true;
6934 sp_switch = gen_rtx_SYMBOL_REF (VOIDmode,
6935 TREE_STRING_POINTER (TREE_VALUE (args)));
6941 /* Handle an "trap_exit" attribute; arguments as in
6942 struct attribute_spec.handler. */
6944 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
6945 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
6947 if (TREE_CODE (*node) != FUNCTION_DECL)
6949 warning ("`%s' attribute only applies to functions",
6950 IDENTIFIER_POINTER (name));
6951 *no_add_attrs = true;
6953 else if (!pragma_interrupt)
6955 /* The trap_exit attribute only has meaning for interrupt functions. */
6956 warning ("`%s' attribute only applies to interrupt functions",
6957 IDENTIFIER_POINTER (name));
6958 *no_add_attrs = true;
6960 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
6962 /* The argument must be a constant integer. */
6963 warning ("`%s' attribute argument not an integer constant",
6964 IDENTIFIER_POINTER (name));
6965 *no_add_attrs = true;
6969 trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args));
6976 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
6977 tree name ATTRIBUTE_UNUSED,
6978 tree args ATTRIBUTE_UNUSED,
6979 int flags ATTRIBUTE_UNUSED,
6980 bool *no_add_attrs ATTRIBUTE_UNUSED)
6985 /* True if __attribute__((renesas)) or -mrenesas. */
6987 sh_attr_renesas_p (tree td)
6994 td = TREE_TYPE (td);
6995 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
6999 /* True if __attribute__((renesas)) or -mrenesas, for the current
7002 sh_cfun_attr_renesas_p (void)
7004 return sh_attr_renesas_p (current_function_decl);
7008 sh_cfun_interrupt_handler_p (void)
7010 return (lookup_attribute ("interrupt_handler",
7011 DECL_ATTRIBUTES (current_function_decl))
7015 /* ??? target_switches in toplev.c is static, hence we have to duplicate it. */
7018 const char *const name;
7020 const char *const description;
7022 sh_target_switches[] = TARGET_SWITCHES;
7023 #define target_switches sh_target_switches
7025 /* Like default_pch_valid_p, but take flag_mask into account. */
7027 sh_pch_valid_p (const void *data_p, size_t len)
7029 const char *data = (const char *)data_p;
7030 const char *flag_that_differs = NULL;
7034 = (SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | HARD_SH4_BIT | FPU_SINGLE_BIT
7035 | SH4_BIT | HITACHI_BIT | LITTLE_ENDIAN_BIT);
7037 /* -fpic and -fpie also usually make a PCH invalid. */
7038 if (data[0] != flag_pic)
7039 return _("created and used with different settings of -fpic");
7040 if (data[1] != flag_pie)
7041 return _("created and used with different settings of -fpie");
7044 /* Check target_flags. */
7045 memcpy (&old_flags, data, sizeof (target_flags));
7046 if (((old_flags ^ target_flags) & flag_mask) != 0)
7048 for (i = 0; i < ARRAY_SIZE (target_switches); i++)
7052 bits = target_switches[i].value;
7056 if ((target_flags & bits) != (old_flags & bits))
7058 flag_that_differs = target_switches[i].name;
7064 data += sizeof (target_flags);
7065 len -= sizeof (target_flags);
7067 /* Check string options. */
7068 #ifdef TARGET_OPTIONS
7069 for (i = 0; i < ARRAY_SIZE (target_options); i++)
7071 const char *str = *target_options[i].variable;
7075 l = strlen (str) + 1;
7076 if (len < l || memcmp (data, str, l) != 0)
7078 flag_that_differs = target_options[i].prefix;
7091 asprintf (&r, _("created and used with differing settings of `-m%s'"),
7094 return _("out of memory");
7099 /* Predicates used by the templates. */
7101 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
7102 Used only in general_movsrc_operand. */
7105 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7117 /* Returns 1 if OP can be source of a simple move operation.
7118 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
7119 invalid as are subregs of system registers. */
7122 general_movsrc_operand (rtx op, enum machine_mode mode)
7124 if (GET_CODE (op) == MEM)
7126 rtx inside = XEXP (op, 0);
7127 if (GET_CODE (inside) == CONST)
7128 inside = XEXP (inside, 0);
7130 if (GET_CODE (inside) == LABEL_REF)
7133 if (GET_CODE (inside) == PLUS
7134 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
7135 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
7138 /* Only post inc allowed. */
7139 if (GET_CODE (inside) == PRE_DEC)
7143 if ((mode == QImode || mode == HImode)
7144 && (GET_CODE (op) == SUBREG
7145 && GET_CODE (XEXP (op, 0)) == REG
7146 && system_reg_operand (XEXP (op, 0), mode)))
7149 return general_operand (op, mode);
7152 /* Returns 1 if OP can be a destination of a move.
7153 Same as general_operand, but no preinc allowed. */
7156 general_movdst_operand (rtx op, enum machine_mode mode)
7158 /* Only pre dec allowed. */
7159 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
7162 return general_operand (op, mode);
7165 /* Returns 1 if OP is a normal arithmetic register. */
7168 arith_reg_operand (rtx op, enum machine_mode mode)
7170 if (register_operand (op, mode))
7174 if (GET_CODE (op) == REG)
7176 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
7177 regno = REGNO (SUBREG_REG (op));
7181 return (regno != T_REG && regno != PR_REG
7182 && ! TARGET_REGISTER_P (regno)
7183 && (regno != FPUL_REG || TARGET_SH4)
7184 && regno != MACH_REG && regno != MACL_REG);
7189 /* Like above, but for DImode destinations: forbid paradoxical DImode subregs,
7190 because this would lead to missing sign extensions when truncating from
7191 DImode to SImode. */
7193 arith_reg_dest (rtx op, enum machine_mode mode)
7195 if (mode == DImode && GET_CODE (op) == SUBREG
7196 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
7198 return arith_reg_operand (op, mode);
7202 int_gpr_dest (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7204 enum machine_mode op_mode = GET_MODE (op);
7206 if (GET_MODE_CLASS (op_mode) != MODE_INT
7207 || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
7209 if (! reload_completed)
7211 return true_regnum (op) <= LAST_GENERAL_REG;
7215 fp_arith_reg_operand (rtx op, enum machine_mode mode)
7217 if (register_operand (op, mode))
7221 if (GET_CODE (op) == REG)
7223 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
7224 regno = REGNO (SUBREG_REG (op));
7228 return (regno >= FIRST_PSEUDO_REGISTER
7229 || FP_REGISTER_P (regno));
7234 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
7237 arith_operand (rtx op, enum machine_mode mode)
7239 if (arith_reg_operand (op, mode))
7244 /* FIXME: We should be checking whether the CONST_INT fits in a
7245 CONST_OK_FOR_I16 here, but this causes reload_cse to crash when
7246 attempting to transform a sequence of two 64-bit sets of the
7247 same register from literal constants into a set and an add,
7248 when the difference is too wide for an add. */
7249 if (GET_CODE (op) == CONST_INT
7250 || EXTRA_CONSTRAINT_C16 (op))
7255 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (op)))
7261 /* Returns 1 if OP is a valid source operand for a compare insn. */
7264 arith_reg_or_0_operand (rtx op, enum machine_mode mode)
7266 if (arith_reg_operand (op, mode))
7269 if (EXTRA_CONSTRAINT_Z (op))
7275 /* Return 1 if OP is a valid source operand for an SHmedia operation
7276 that takes either a register or a 6-bit immediate. */
7279 shmedia_6bit_operand (rtx op, enum machine_mode mode)
7281 return (arith_reg_operand (op, mode)
7282 || (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I06 (INTVAL (op))));
7285 /* Returns 1 if OP is a valid source operand for a logical operation. */
7288 logical_operand (rtx op, enum machine_mode mode)
7290 if (arith_reg_operand (op, mode))
7295 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I10 (INTVAL (op)))
7300 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K08 (INTVAL (op)))
7307 and_operand (rtx op, enum machine_mode mode)
7309 if (logical_operand (op, mode))
7312 /* Check mshflo.l / mshflhi.l opportunities. */
7315 && GET_CODE (op) == CONST_INT
7316 && CONST_OK_FOR_J16 (INTVAL (op)))
7322 /* Nonzero if OP is a floating point value with value 0.0. */
7325 fp_zero_operand (rtx op)
7329 if (GET_MODE (op) != SFmode)
7332 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
7333 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
7336 /* Nonzero if OP is a floating point value with value 1.0. */
7339 fp_one_operand (rtx op)
7343 if (GET_MODE (op) != SFmode)
7346 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
7347 return REAL_VALUES_EQUAL (r, dconst1);
7350 /* For -m4 and -m4-single-only, mode switching is used. If we are
7351 compiling without -mfmovd, movsf_ie isn't taken into account for
7352 mode switching. We could check in machine_dependent_reorg for
7353 cases where we know we are in single precision mode, but there is
7354 interface to find that out during reload, so we must avoid
7355 choosing an fldi alternative during reload and thus failing to
7356 allocate a scratch register for the constant loading. */
7360 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
7364 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7366 enum rtx_code code = GET_CODE (op);
7367 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
7371 fpscr_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7373 return (GET_CODE (op) == REG && REGNO (op) == FPSCR_REG
7374 && GET_MODE (op) == PSImode);
7378 fpul_operand (rtx op, enum machine_mode mode)
7381 return fp_arith_reg_operand (op, mode);
7383 return (GET_CODE (op) == REG
7384 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
7385 && GET_MODE (op) == mode);
7389 symbol_ref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7391 return (GET_CODE (op) == SYMBOL_REF);
7394 /* Return the TLS type for TLS symbols, 0 for otherwise. */
7396 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7398 if (GET_CODE (op) != SYMBOL_REF)
7400 return SYMBOL_REF_TLS_MODEL (op);
7404 commutative_float_operator (rtx op, enum machine_mode mode)
7406 if (GET_MODE (op) != mode)
7408 switch (GET_CODE (op))
7420 noncommutative_float_operator (rtx op, enum machine_mode mode)
7422 if (GET_MODE (op) != mode)
7424 switch (GET_CODE (op))
7436 unary_float_operator (rtx op, enum machine_mode mode)
7438 if (GET_MODE (op) != mode)
7440 switch (GET_CODE (op))
7453 binary_float_operator (rtx op, enum machine_mode mode)
7455 if (GET_MODE (op) != mode)
7457 switch (GET_CODE (op))
7471 binary_logical_operator (rtx op, enum machine_mode mode)
7473 if (GET_MODE (op) != mode)
7475 switch (GET_CODE (op))
7488 equality_comparison_operator (rtx op, enum machine_mode mode)
7490 return ((mode == VOIDmode || GET_MODE (op) == mode)
7491 && (GET_CODE (op) == EQ || GET_CODE (op) == NE));
7495 greater_comparison_operator (rtx op, enum machine_mode mode)
7497 if (mode != VOIDmode && GET_MODE (op) == mode)
7499 switch (GET_CODE (op))
7512 less_comparison_operator (rtx op, enum machine_mode mode)
7514 if (mode != VOIDmode && GET_MODE (op) == mode)
7516 switch (GET_CODE (op))
7528 /* Accept pseudos and branch target registers. */
7530 target_reg_operand (rtx op, enum machine_mode mode)
7533 || GET_MODE (op) != DImode)
7536 if (GET_CODE (op) == SUBREG)
7539 if (GET_CODE (op) != REG)
7542 /* We must protect ourselves from matching pseudos that are virtual
7543 register, because they will eventually be replaced with hardware
7544 registers that aren't branch-target registers. */
7545 if (REGNO (op) > LAST_VIRTUAL_REGISTER
7546 || TARGET_REGISTER_P (REGNO (op)))
7552 /* Same as target_reg_operand, except that label_refs and symbol_refs
7553 are accepted before reload. */
7555 target_operand (rtx op, enum machine_mode mode)
7560 if ((GET_MODE (op) == DImode || GET_MODE (op) == VOIDmode)
7561 && EXTRA_CONSTRAINT_Csy (op))
7562 return ! reload_completed;
7564 return target_reg_operand (op, mode);
7568 mextr_bit_offset (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7572 if (GET_CODE (op) != CONST_INT)
7575 return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
7579 extend_reg_operand (rtx op, enum machine_mode mode)
7581 return (GET_CODE (op) == TRUNCATE
7583 : arith_reg_operand) (op, mode);
7587 trunc_hi_operand (rtx op, enum machine_mode mode)
7589 enum machine_mode op_mode = GET_MODE (op);
7591 if (op_mode != SImode && op_mode != DImode
7592 && op_mode != V4HImode && op_mode != V2SImode)
7594 return extend_reg_operand (op, mode);
7598 extend_reg_or_0_operand (rtx op, enum machine_mode mode)
7600 return (GET_CODE (op) == TRUNCATE
7602 : arith_reg_or_0_operand) (op, mode);
7606 general_extend_operand (rtx op, enum machine_mode mode)
7608 return (GET_CODE (op) == TRUNCATE
7610 : nonimmediate_operand) (op, mode);
7614 inqhi_operand (rtx op, enum machine_mode mode)
7616 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
7619 /* Can't use true_regnum here because copy_cost wants to know about
7620 SECONDARY_INPUT_RELOAD_CLASS. */
7621 return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op));
7625 sh_rep_vec (rtx v, enum machine_mode mode)
7630 if ((GET_CODE (v) != CONST_VECTOR && GET_CODE (v) != PARALLEL)
7631 || (GET_MODE (v) != mode && mode != VOIDmode))
7633 i = XVECLEN (v, 0) - 2;
7634 x = XVECEXP (v, 0, i + 1);
7635 if (GET_MODE_UNIT_SIZE (mode) == 1)
7637 y = XVECEXP (v, 0, i);
7638 for (i -= 2; i >= 0; i -= 2)
7639 if (! rtx_equal_p (XVECEXP (v, 0, i + 1), x)
7640 || ! rtx_equal_p (XVECEXP (v, 0, i), y))
7645 if (XVECEXP (v, 0, i) != x)
7650 /* Determine if V is a constant vector matching MODE with only one element
7651 that is not a sign extension. Two byte-sized elements count as one. */
7653 sh_1el_vec (rtx v, enum machine_mode mode)
7656 int i, last, least, sign_ix;
7659 if (GET_CODE (v) != CONST_VECTOR
7660 || (GET_MODE (v) != mode && mode != VOIDmode))
7662 /* Determine numbers of last and of least significant elements. */
7663 last = XVECLEN (v, 0) - 1;
7664 least = TARGET_LITTLE_ENDIAN ? 0 : last;
7665 if (GET_CODE (XVECEXP (v, 0, least)) != CONST_INT)
7668 if (GET_MODE_UNIT_SIZE (mode) == 1)
7669 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
7670 if (GET_CODE (XVECEXP (v, 0, sign_ix)) != CONST_INT)
7672 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (v));
7673 sign = (INTVAL (XVECEXP (v, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
7674 ? constm1_rtx : const0_rtx);
7675 i = XVECLEN (v, 0) - 1;
7677 if (i != least && i != sign_ix && XVECEXP (v, 0, i) != sign)
7684 sh_const_vec (rtx v, enum machine_mode mode)
7688 if (GET_CODE (v) != CONST_VECTOR
7689 || (GET_MODE (v) != mode && mode != VOIDmode))
7691 i = XVECLEN (v, 0) - 1;
7693 if (GET_CODE (XVECEXP (v, 0, i)) != CONST_INT)
7698 /* Return the destination address of a branch. */
7701 branch_dest (rtx branch)
7703 rtx dest = SET_SRC (PATTERN (branch));
7706 if (GET_CODE (dest) == IF_THEN_ELSE)
7707 dest = XEXP (dest, 1);
7708 dest = XEXP (dest, 0);
7709 dest_uid = INSN_UID (dest);
7710 return INSN_ADDRESSES (dest_uid);
7713 /* Return nonzero if REG is not used after INSN.
7714 We assume REG is a reload reg, and therefore does
7715 not live past labels. It may live past calls or jumps though. */
7717 reg_unused_after (rtx reg, rtx insn)
7722 /* If the reg is set by this instruction, then it is safe for our
7723 case. Disregard the case where this is a store to memory, since
7724 we are checking a register used in the store address. */
7725 set = single_set (insn);
7726 if (set && GET_CODE (SET_DEST (set)) != MEM
7727 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7730 while ((insn = NEXT_INSN (insn)))
7736 code = GET_CODE (insn);
7739 /* If this is a label that existed before reload, then the register
7740 if dead here. However, if this is a label added by reorg, then
7741 the register may still be live here. We can't tell the difference,
7742 so we just ignore labels completely. */
7743 if (code == CODE_LABEL)
7748 if (code == JUMP_INSN)
7751 /* If this is a sequence, we must handle them all at once.
7752 We could have for instance a call that sets the target register,
7753 and an insn in a delay slot that uses the register. In this case,
7754 we must return 0. */
7755 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
7760 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7762 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
7763 rtx set = single_set (this_insn);
7765 if (GET_CODE (this_insn) == CALL_INSN)
7767 else if (GET_CODE (this_insn) == JUMP_INSN)
7769 if (INSN_ANNULLED_BRANCH_P (this_insn))
7774 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
7776 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7778 if (GET_CODE (SET_DEST (set)) != MEM)
7784 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
7789 else if (code == JUMP_INSN)
7793 set = single_set (insn);
7794 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
7796 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7797 return GET_CODE (SET_DEST (set)) != MEM;
7798 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
7801 if (code == CALL_INSN && call_used_regs[REGNO (reg)])
7809 static GTY(()) rtx fpscr_rtx;
7811 get_fpscr_rtx (void)
7815 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
7816 REG_USERVAR_P (fpscr_rtx) = 1;
7817 mark_user_reg (fpscr_rtx);
7819 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
7820 mark_user_reg (fpscr_rtx);
7825 emit_sf_insn (rtx pat)
7831 emit_df_insn (rtx pat)
7837 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
7839 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
7843 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
7845 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
7850 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
7852 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
7856 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
7858 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
7862 /* ??? gcc does flow analysis strictly after common subexpression
7863 elimination. As a result, common subexpression elimination fails
7864 when there are some intervening statements setting the same register.
7865 If we did nothing about this, this would hurt the precision switching
7866 for SH4 badly. There is some cse after reload, but it is unable to
7867 undo the extra register pressure from the unused instructions, and
7868 it cannot remove auto-increment loads.
7870 A C code example that shows this flow/cse weakness for (at least) SH
7871 and sparc (as of gcc ss-970706) is this:
7885 So we add another pass before common subexpression elimination, to
7886 remove assignments that are dead due to a following assignment in the
7887 same basic block. */
7890 mark_use (rtx x, rtx *reg_set_block)
7896 code = GET_CODE (x);
7901 int regno = REGNO (x);
7902 int nregs = (regno < FIRST_PSEUDO_REGISTER
7903 ? HARD_REGNO_NREGS (regno, GET_MODE (x))
7907 reg_set_block[regno + nregs - 1] = 0;
7914 rtx dest = SET_DEST (x);
7916 if (GET_CODE (dest) == SUBREG)
7917 dest = SUBREG_REG (dest);
7918 if (GET_CODE (dest) != REG)
7919 mark_use (dest, reg_set_block);
7920 mark_use (SET_SRC (x), reg_set_block);
7927 const char *fmt = GET_RTX_FORMAT (code);
7929 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7932 mark_use (XEXP (x, i), reg_set_block);
7933 else if (fmt[i] == 'E')
7934 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7935 mark_use (XVECEXP (x, i, j), reg_set_block);
7942 static rtx get_free_reg (HARD_REG_SET);
7944 /* This function returns a register to use to load the address to load
7945 the fpscr from. Currently it always returns r1 or r7, but when we are
7946 able to use pseudo registers after combine, or have a better mechanism
7947 for choosing a register, it should be done here. */
7948 /* REGS_LIVE is the liveness information for the point for which we
7949 need this allocation. In some bare-bones exit blocks, r1 is live at the
7950 start. We can even have all of r0..r3 being live:
7951 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
7952 INSN before which new insns are placed with will clobber the register
7953 we return. If a basic block consists only of setting the return value
7954 register to a pseudo and using that register, the return value is not
7955 live before or after this block, yet we we'll insert our insns right in
7959 get_free_reg (HARD_REG_SET regs_live)
7961 if (! TEST_HARD_REG_BIT (regs_live, 1))
7962 return gen_rtx_REG (Pmode, 1);
7964 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
7965 there shouldn't be anything but a jump before the function end. */
7966 if (! TEST_HARD_REG_BIT (regs_live, 7))
7967 return gen_rtx_REG (Pmode, 7);
7972 /* This function will set the fpscr from memory.
7973 MODE is the mode we are setting it to. */
7975 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
7977 enum attr_fp_mode fp_mode = mode;
7978 rtx addr_reg = get_free_reg (regs_live);
7980 if (fp_mode == (enum attr_fp_mode) ACTUAL_NORMAL_MODE (FP_MODE))
7981 emit_insn (gen_fpu_switch1 (addr_reg));
7983 emit_insn (gen_fpu_switch0 (addr_reg));
7986 /* Is the given character a logical line separator for the assembler? */
7987 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
7988 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
7992 sh_insn_length_adjustment (rtx insn)
7994 /* Instructions with unfilled delay slots take up an extra two bytes for
7995 the nop in the delay slot. */
7996 if (((GET_CODE (insn) == INSN
7997 && GET_CODE (PATTERN (insn)) != USE
7998 && GET_CODE (PATTERN (insn)) != CLOBBER)
7999 || GET_CODE (insn) == CALL_INSN
8000 || (GET_CODE (insn) == JUMP_INSN
8001 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8002 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
8003 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
8004 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
8007 /* SH2e has a bug that prevents the use of annulled branches, so if
8008 the delay slot is not filled, we'll have to put a NOP in it. */
8009 if (sh_cpu == CPU_SH2E
8010 && GET_CODE (insn) == JUMP_INSN
8011 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8012 && GET_CODE (PATTERN (insn)) != ADDR_VEC
8013 && get_attr_type (insn) == TYPE_CBRANCH
8014 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
8017 /* sh-dsp parallel processing insn take four bytes instead of two. */
8019 if (GET_CODE (insn) == INSN)
8022 rtx body = PATTERN (insn);
8023 const char *template;
8025 int maybe_label = 1;
8027 if (GET_CODE (body) == ASM_INPUT)
8028 template = XSTR (body, 0);
8029 else if (asm_noperands (body) >= 0)
8031 = decode_asm_operands (body, NULL, NULL, NULL, NULL);
8040 while (c == ' ' || c == '\t');
8041 /* all sh-dsp parallel-processing insns start with p.
8042 The only non-ppi sh insn starting with p is pref.
8043 The only ppi starting with pr is prnd. */
8044 if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2))
8046 /* The repeat pseudo-insn expands two three insns, a total of
8047 six bytes in size. */
8048 else if ((c == 'r' || c == 'R')
8049 && ! strncasecmp ("epeat", template, 5))
8051 while (c && c != '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c))
8053 /* If this is a label, it is obviously not a ppi insn. */
8054 if (c == ':' && maybe_label)
8059 else if (c == '\'' || c == '"')
8064 maybe_label = c != ':';
8072 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
8073 isn't protected by a PIC unspec. */
8075 nonpic_symbol_mentioned_p (rtx x)
8077 register const char *fmt;
8080 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
8081 || GET_CODE (x) == PC)
8084 /* We don't want to look into the possible MEM location of a
8085 CONST_DOUBLE, since we're not going to use it, in general. */
8086 if (GET_CODE (x) == CONST_DOUBLE)
8089 if (GET_CODE (x) == UNSPEC
8090 && (XINT (x, 1) == UNSPEC_PIC
8091 || XINT (x, 1) == UNSPEC_GOT
8092 || XINT (x, 1) == UNSPEC_GOTOFF
8093 || XINT (x, 1) == UNSPEC_GOTPLT
8094 || XINT (x, 1) == UNSPEC_GOTTPOFF
8095 || XINT (x, 1) == UNSPEC_DTPOFF
8096 || XINT (x, 1) == UNSPEC_PLT))
8099 fmt = GET_RTX_FORMAT (GET_CODE (x));
8100 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8106 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8107 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
8110 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
8117 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
8118 @GOTOFF in `reg'. */
8120 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
8123 if (tls_symbolic_operand (orig, Pmode))
8126 if (GET_CODE (orig) == LABEL_REF
8127 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
8130 reg = gen_reg_rtx (Pmode);
8132 emit_insn (gen_symGOTOFF2reg (reg, orig));
8135 else if (GET_CODE (orig) == SYMBOL_REF)
8138 reg = gen_reg_rtx (Pmode);
8140 emit_insn (gen_symGOT2reg (reg, orig));
8146 /* Mark the use of a constant in the literal table. If the constant
8147 has multiple labels, make it unique. */
8149 mark_constant_pool_use (rtx x)
8151 rtx insn, lab, pattern;
8156 switch (GET_CODE (x))
8166 /* Get the first label in the list of labels for the same constant
8167 and delete another labels in the list. */
8169 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
8171 if (GET_CODE (insn) != CODE_LABEL
8172 || LABEL_REFS (insn) != NEXT_INSN (insn))
8177 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
8178 INSN_DELETED_P (insn) = 1;
8180 /* Mark constants in a window. */
8181 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
8183 if (GET_CODE (insn) != INSN)
8186 pattern = PATTERN (insn);
8187 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
8190 switch (XINT (pattern, 1))
8192 case UNSPECV_CONST2:
8193 case UNSPECV_CONST4:
8194 case UNSPECV_CONST8:
8195 XVECEXP (pattern, 0, 1) = const1_rtx;
8197 case UNSPECV_WINDOW_END:
8198 if (XVECEXP (pattern, 0, 0) == x)
8201 case UNSPECV_CONST_END:
8211 /* Return true if it's possible to redirect BRANCH1 to the destination
8212 of an unconditional jump BRANCH2. We only want to do this if the
8213 resulting branch will have a short displacement. */
8215 sh_can_redirect_branch (rtx branch1, rtx branch2)
8217 if (flag_expensive_optimizations && simplejump_p (branch2))
8219 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
8223 for (distance = 0, insn = NEXT_INSN (branch1);
8224 insn && distance < 256;
8225 insn = PREV_INSN (insn))
8230 distance += get_attr_length (insn);
8232 for (distance = 0, insn = NEXT_INSN (branch1);
8233 insn && distance < 256;
8234 insn = NEXT_INSN (insn))
8239 distance += get_attr_length (insn);
8245 /* Return nonzero if register old_reg can be renamed to register new_reg. */
8247 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
8248 unsigned int new_reg)
8250 /* Interrupt functions can only use registers that have already been
8251 saved by the prologue, even if they would normally be
8254 if (sh_cfun_interrupt_handler_p () && !regs_ever_live[new_reg])
8260 /* Function to update the integer COST
8261 based on the relationship between INSN that is dependent on
8262 DEP_INSN through the dependence LINK. The default is to make no
8263 adjustment to COST. This can be used for example to specify to
8264 the scheduler that an output- or anti-dependence does not incur
8265 the same cost as a data-dependence. The return value should be
8266 the new value for COST. */
8268 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
8274 /* On SHmedia, if the dependence is an anti-dependence or
8275 output-dependence, there is no cost. */
8276 if (REG_NOTE_KIND (link) != 0)
8279 if (get_attr_is_mac_media (insn)
8280 && get_attr_is_mac_media (dep_insn))
8283 else if (REG_NOTE_KIND (link) == 0)
8285 enum attr_type dep_type, type;
8287 if (recog_memoized (insn) < 0
8288 || recog_memoized (dep_insn) < 0)
8291 dep_type = get_attr_type (dep_insn);
8292 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
8294 if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
8295 && (type = get_attr_type (insn)) != TYPE_CALL
8296 && type != TYPE_SFUNC)
8299 /* The only input for a call that is timing-critical is the
8300 function's address. */
8301 if (GET_CODE(insn) == CALL_INSN)
8303 rtx call = PATTERN (insn);
8305 if (GET_CODE (call) == PARALLEL)
8306 call = XVECEXP (call, 0 ,0);
8307 if (GET_CODE (call) == SET)
8308 call = SET_SRC (call);
8309 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
8310 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))
8313 /* Likewise, the most timing critical input for an sfuncs call
8314 is the function address. However, sfuncs typically start
8315 using their arguments pretty quickly.
8316 Assume a four cycle delay before they are needed. */
8317 /* All sfunc calls are parallels with at least four components.
8318 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
8319 else if (GET_CODE (PATTERN (insn)) == PARALLEL
8320 && XVECLEN (PATTERN (insn), 0) >= 4
8321 && (reg = sfunc_uses_reg (insn)))
8323 if (! reg_set_p (reg, dep_insn))
8326 /* When the preceding instruction loads the shift amount of
8327 the following SHAD/SHLD, the latency of the load is increased
8330 && get_attr_type (insn) == TYPE_DYN_SHIFT
8331 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
8332 && reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
8333 XEXP (SET_SRC (single_set (insn)),
8336 /* When an LS group instruction with a latency of less than
8337 3 cycles is followed by a double-precision floating-point
8338 instruction, FIPR, or FTRV, the latency of the first
8339 instruction is increased to 3 cycles. */
8341 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
8342 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
8344 /* The lsw register of a double-precision computation is ready one
8346 else if (reload_completed
8347 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
8348 && (use_pat = single_set (insn))
8349 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
8353 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
8354 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
8357 /* An anti-dependence penalty of two applies if the first insn is a double
8358 precision fadd / fsub / fmul. */
8359 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI
8360 && recog_memoized (dep_insn) >= 0
8361 && get_attr_type (dep_insn) == TYPE_DFP_ARITH
8362 /* A lot of alleged anti-flow dependences are fake,
8363 so check this one is real. */
8364 && flow_dependent_p (dep_insn, insn))
8371 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
8372 if DEP_INSN is anti-flow dependent on INSN. */
8374 flow_dependent_p (rtx insn, rtx dep_insn)
8376 rtx tmp = PATTERN (insn);
8378 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
8379 return tmp == NULL_RTX;
8382 /* A helper function for flow_dependent_p called through note_stores. */
8384 flow_dependent_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8386 rtx * pinsn = (rtx *) data;
8388 if (*pinsn && reg_referenced_p (x, *pinsn))
8392 /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
8393 'special function' patterns (type sfunc) that clobber pr, but that
8394 do not look like function calls to leaf_function_p. Hence we must
8395 do this extra check. */
8399 return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
8402 /* This Function returns nonzero if the DFA based scheduler interface
8403 is to be used. At present this is supported for the SH4 only. */
8405 sh_use_dfa_interface (void)
8407 if (TARGET_HARD_SH4)
8413 /* This function returns "2" to indicate dual issue for the SH4
8414 processor. To be used by the DFA pipeline description. */
8416 sh_issue_rate (void)
8418 if (TARGET_SUPERSCALAR)
8424 /* Functions for ready queue reordering for sched1. */
8426 /* Get weight for mode for a set x. */
8428 find_set_regmode_weight (rtx x, enum machine_mode mode)
8430 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
8432 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
8434 if (GET_CODE (SET_DEST (x)) == REG)
8436 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
8446 /* Get regmode weight for insn. */
8448 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
8450 short reg_weight = 0;
8453 /* Increment weight for each register born here. */
8455 reg_weight += find_set_regmode_weight (x, mode);
8456 if (GET_CODE (x) == PARALLEL)
8459 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
8461 x = XVECEXP (PATTERN (insn), 0, j);
8462 reg_weight += find_set_regmode_weight (x, mode);
8465 /* Decrement weight for each register that dies here. */
8466 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8468 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
8470 rtx note = XEXP (x, 0);
8471 if (GET_CODE (note) == REG && GET_MODE (note) == mode)
8478 /* Calculate regmode weights for all insns of a basic block. */
8480 find_regmode_weight (int b, enum machine_mode mode)
8482 rtx insn, next_tail, head, tail;
8484 get_block_head_tail (b, &head, &tail);
8485 next_tail = NEXT_INSN (tail);
8487 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
8489 /* Handle register life information. */
8494 INSN_REGMODE_WEIGHT (insn, mode) =
8495 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
8496 else if (mode == SImode)
8497 INSN_REGMODE_WEIGHT (insn, mode) =
8498 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
8502 /* Comparison function for ready queue sorting. */
8504 rank_for_reorder (const void *x, const void *y)
8506 rtx tmp = *(const rtx *) y;
8507 rtx tmp2 = *(const rtx *) x;
8509 /* The insn in a schedule group should be issued the first. */
8510 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
8511 return SCHED_GROUP_P (tmp2) ? 1 : -1;
8513 /* If insns are equally good, sort by INSN_LUID (original insn order), This
8514 minimizes instruction movement, thus minimizing sched's effect on
8515 register pressure. */
8516 return INSN_LUID (tmp) - INSN_LUID (tmp2);
8519 /* Resort the array A in which only element at index N may be out of order. */
8521 swap_reorder (rtx *a, int n)
8523 rtx insn = a[n - 1];
8526 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
8534 #define SCHED_REORDER(READY, N_READY) \
8537 if ((N_READY) == 2) \
8538 swap_reorder (READY, N_READY); \
8539 else if ((N_READY) > 2) \
8540 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
8544 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
8547 ready_reorder (rtx *ready, int nready)
8549 SCHED_REORDER (ready, nready);
8552 /* Calculate regmode weights for all insns of all basic block. */
8554 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
8555 int verbose ATTRIBUTE_UNUSED,
8560 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
8561 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
8563 FOR_EACH_BB_REVERSE (b)
8565 find_regmode_weight (b->index, SImode);
8566 find_regmode_weight (b->index, SFmode);
8569 CURR_REGMODE_PRESSURE (SImode) = 0;
8570 CURR_REGMODE_PRESSURE (SFmode) = 0;
8576 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
8577 int verbose ATTRIBUTE_UNUSED)
8579 if (regmode_weight[0])
8581 free (regmode_weight[0]);
8582 regmode_weight[0] = NULL;
8584 if (regmode_weight[1])
8586 free (regmode_weight[1]);
8587 regmode_weight[1] = NULL;
8591 /* Cache the can_issue_more so that we can return it from reorder2. Also,
8592 keep count of register pressures on SImode and SFmode. */
8594 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
8595 int sched_verbose ATTRIBUTE_UNUSED,
8599 if (GET_CODE (PATTERN (insn)) != USE
8600 && GET_CODE (PATTERN (insn)) != CLOBBER)
8601 cached_can_issue_more = can_issue_more - 1;
8603 cached_can_issue_more = can_issue_more;
8605 if (reload_completed)
8606 return cached_can_issue_more;
8608 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
8609 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
8611 return cached_can_issue_more;
8615 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
8616 int verbose ATTRIBUTE_UNUSED,
8617 int veclen ATTRIBUTE_UNUSED)
8619 CURR_REGMODE_PRESSURE (SImode) = 0;
8620 CURR_REGMODE_PRESSURE (SFmode) = 0;
8623 /* Some magic numbers. */
8624 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
8625 functions that already have high pressure on r0. */
8626 #define R0_MAX_LIFE_REGIONS 2
8627 #define R0_MAX_LIVE_LENGTH 12
8628 /* Register Pressure thresholds for SImode and SFmode registers. */
8629 #define SIMODE_MAX_WEIGHT 5
8630 #define SFMODE_MAX_WEIGHT 10
8632 /* Return true if the pressure is high for MODE. */
8634 high_pressure (enum machine_mode mode)
8636 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
8637 functions that already have high pressure on r0. */
8638 if ((REG_N_SETS (0) - REG_N_DEATHS (0)) >= R0_MAX_LIFE_REGIONS
8639 && REG_LIVE_LENGTH (0) >= R0_MAX_LIVE_LENGTH)
8643 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
8645 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
8648 /* Reorder ready queue if register pressure is high. */
8650 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
8651 int sched_verbose ATTRIBUTE_UNUSED,
8654 int clock_var ATTRIBUTE_UNUSED)
8656 if (reload_completed)
8657 return sh_issue_rate ();
8659 if (high_pressure (SFmode) || high_pressure (SImode))
8661 ready_reorder (ready, *n_readyp);
8664 return sh_issue_rate ();
8667 /* Skip cycles if the current register pressure is high. */
8669 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
8670 int sched_verbose ATTRIBUTE_UNUSED,
8671 rtx *ready ATTRIBUTE_UNUSED,
8672 int *n_readyp ATTRIBUTE_UNUSED,
8673 int clock_var ATTRIBUTE_UNUSED)
8675 if (reload_completed)
8676 return cached_can_issue_more;
8678 if (high_pressure(SFmode) || high_pressure (SImode))
8681 return cached_can_issue_more;
8684 /* Skip cycles without sorting the ready queue. This will move insn from
8685 Q->R. If this is the last cycle we are skipping; allow sorting of ready
8686 queue by sh_reorder. */
8688 /* Generally, skipping these many cycles are sufficient for all insns to move
8693 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
8694 int sched_verbose ATTRIBUTE_UNUSED,
8695 rtx insn ATTRIBUTE_UNUSED,
8700 if (reload_completed)
8705 if ((clock_var - last_clock_var) < MAX_SKIPS)
8710 /* If this is the last cycle we are skipping, allow reordering of R. */
8711 if ((clock_var - last_clock_var) == MAX_SKIPS)
8723 /* SHmedia requires registers for branches, so we can't generate new
8724 branches past reload. */
8726 sh_cannot_modify_jumps_p (void)
8728 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
8732 sh_target_reg_class (void)
8734 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
8738 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
8740 return (shmedia_space_reserved_for_target_registers
8741 && (! after_prologue_epilogue_gen || TARGET_SAVE_ALL_TARGET_REGS));
8745 sh_ms_bitfield_layout_p (tree record_type ATTRIBUTE_UNUSED)
8747 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
8751 On the SH1..SH4, the trampoline looks like
8752 2 0002 D202 mov.l l2,r2
8753 1 0000 D301 mov.l l1,r3
8756 5 0008 00000000 l1: .long area
8757 6 000c 00000000 l2: .long function
8759 SH5 (compact) uses r1 instead of r3 for the static chain. */
8762 /* Emit RTL insns to initialize the variable parts of a trampoline.
8763 FNADDR is an RTX for the address of the function's pure code.
8764 CXT is an RTX for the static chain value for the function. */
8767 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
8769 if (TARGET_SHMEDIA64)
8774 rtx movi1 = GEN_INT (0xcc000010);
8775 rtx shori1 = GEN_INT (0xc8000010);
8778 /* The following trampoline works within a +- 128 KB range for cxt:
8779 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
8780 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
8781 gettr tr1,r1; blink tr0,r63 */
8782 /* Address rounding makes it hard to compute the exact bounds of the
8783 offset for this trampoline, but we have a rather generous offset
8784 range, so frame_offset should do fine as an upper bound. */
8785 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
8787 /* ??? could optimize this trampoline initialization
8788 by writing DImode words with two insns each. */
8789 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
8790 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
8791 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
8792 insn = gen_rtx_AND (DImode, insn, mask);
8793 /* Or in ptb/u .,tr1 pattern */
8794 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
8795 insn = force_operand (insn, NULL_RTX);
8796 insn = gen_lowpart (SImode, insn);
8797 emit_move_insn (gen_rtx_MEM (SImode, tramp), insn);
8798 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
8799 insn = gen_rtx_AND (DImode, insn, mask);
8800 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
8801 insn = gen_lowpart (SImode, insn);
8802 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), insn);
8803 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
8804 insn = gen_rtx_AND (DImode, insn, mask);
8805 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8806 insn = gen_lowpart (SImode, insn);
8807 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), insn);
8808 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
8809 insn = gen_rtx_AND (DImode, insn, mask);
8810 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8811 insn = gen_lowpart (SImode, insn);
8812 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
8814 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
8815 insn = gen_rtx_AND (DImode, insn, mask);
8816 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8817 insn = gen_lowpart (SImode, insn);
8818 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 16)),
8820 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 20)),
8821 GEN_INT (0x6bf10600));
8822 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 24)),
8823 GEN_INT (0x4415fc10));
8824 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 28)),
8825 GEN_INT (0x4401fff0));
8826 emit_insn (gen_ic_invalidate_line (tramp));
8829 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
8830 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
8832 tramp_templ = gen_datalabel_ref (tramp_templ);
8833 dst = gen_rtx_MEM (BLKmode, tramp);
8834 src = gen_rtx_MEM (BLKmode, tramp_templ);
8835 set_mem_align (dst, 256);
8836 set_mem_align (src, 64);
8837 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
8839 emit_move_insn (gen_rtx_MEM (Pmode, plus_constant (tramp, fixed_len)),
8841 emit_move_insn (gen_rtx_MEM (Pmode,
8842 plus_constant (tramp,
8844 + GET_MODE_SIZE (Pmode))),
8846 emit_insn (gen_ic_invalidate_line (tramp));
8849 else if (TARGET_SHMEDIA)
8851 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
8852 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
8853 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
8854 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
8855 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
8856 rotated 10 right, and higher 16 bit of every 32 selected. */
8858 = force_reg (V2HImode, (simplify_gen_subreg
8859 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
8860 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
8861 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
8863 tramp = force_reg (Pmode, tramp);
8864 fnaddr = force_reg (SImode, fnaddr);
8865 cxt = force_reg (SImode, cxt);
8866 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
8867 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
8869 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
8870 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
8871 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
8872 emit_move_insn (gen_rtx_MEM (DImode, tramp), quad0);
8873 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
8874 gen_rtx_SUBREG (V2HImode, cxt, 0),
8876 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
8877 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
8878 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
8879 if (TARGET_LITTLE_ENDIAN)
8881 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
8882 emit_insn (gen_mextr4 (quad2, cxtload, blink));
8886 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
8887 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
8889 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 8)), quad1);
8890 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), quad2);
8891 emit_insn (gen_ic_invalidate_line (tramp));
8894 else if (TARGET_SHCOMPACT)
8896 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
8899 emit_move_insn (gen_rtx_MEM (SImode, tramp),
8900 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
8902 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
8903 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
8905 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
8907 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
8911 if (TARGET_USERMODE)
8912 emit_library_call (function_symbol ("__ic_invalidate"),
8913 0, VOIDmode, 1, tramp, SImode);
8915 emit_insn (gen_ic_invalidate_line (tramp));
8919 /* FIXME: This is overly conservative. A SHcompact function that
8920 receives arguments ``by reference'' will have them stored in its
8921 own stack frame, so it must not pass pointers or references to
8922 these arguments to other functions by means of sibling calls. */
8924 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8927 && (! TARGET_SHCOMPACT
8928 || current_function_args_info.stack_regs == 0)
8929 && ! sh_cfun_interrupt_handler_p ());
8932 /* Machine specific built-in functions. */
8934 struct builtin_description
8936 const enum insn_code icode;
8937 const char *const name;
8941 /* describe number and signedness of arguments; arg[0] == result
8942 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
8943 static const char signature_args[][4] =
8945 #define SH_BLTIN_V2SI2 0
8947 #define SH_BLTIN_V4HI2 1
8949 #define SH_BLTIN_V2SI3 2
8951 #define SH_BLTIN_V4HI3 3
8953 #define SH_BLTIN_V8QI3 4
8955 #define SH_BLTIN_MAC_HISI 5
8957 #define SH_BLTIN_SH_HI 6
8959 #define SH_BLTIN_SH_SI 7
8961 #define SH_BLTIN_V4HI2V2SI 8
8963 #define SH_BLTIN_V4HI2V8QI 9
8965 #define SH_BLTIN_SISF 10
8967 #define SH_BLTIN_LDUA_L 11
8969 #define SH_BLTIN_LDUA_Q 12
8971 #define SH_BLTIN_STUA_L 13
8973 #define SH_BLTIN_STUA_Q 14
8975 #define SH_BLTIN_UDI 15
8977 #define SH_BLTIN_NUM_SHARED_SIGNATURES 16
8978 #define SH_BLTIN_2 16
8979 #define SH_BLTIN_SU 16
8981 #define SH_BLTIN_3 17
8982 #define SH_BLTIN_SUS 17
8984 #define SH_BLTIN_PSSV 18
8986 #define SH_BLTIN_XXUU 19
8987 #define SH_BLTIN_UUUU 19
8989 #define SH_BLTIN_PV 20
8992 /* mcmv: operands considered unsigned. */
8993 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
8994 /* mperm: control value considered unsigned int. */
8995 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
8996 /* mshards_q: returns signed short. */
8997 /* nsb: takes long long arg, returns unsigned char. */
8998 static const struct builtin_description bdesc[] =
9000 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
9001 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
9002 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
9003 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
9004 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
9005 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
9006 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
9008 { CODE_FOR_alloco32, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
9009 { CODE_FOR_alloco64, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
9011 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
9012 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
9013 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
9014 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
9015 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
9016 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
9017 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
9018 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
9019 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
9020 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
9021 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_UDI },
9022 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_UDI },
9023 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_UDI },
9024 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_UDI },
9025 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_UDI },
9026 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_UDI },
9027 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_UDI },
9028 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
9029 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
9030 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
9031 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
9032 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
9033 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
9034 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
9035 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
9036 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
9037 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
9038 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
9039 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
9040 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
9041 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
9042 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
9043 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
9044 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
9045 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
9046 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
9047 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
9048 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
9049 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
9050 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
9051 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
9052 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
9053 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
9054 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
9055 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
9056 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
9057 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
9058 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
9059 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
9060 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
9061 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
9062 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
9063 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
9064 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
9066 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
9067 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
9068 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
9069 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
9070 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
9071 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
9072 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
9073 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
9074 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
9075 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
9076 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
9077 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
9078 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
9079 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
9080 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
9081 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
9083 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
9084 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
9086 { CODE_FOR_prefetch32,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
9087 { CODE_FOR_prefetch64,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV }
9092 sh_media_init_builtins (void)
9094 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
9095 const struct builtin_description *d;
9097 memset (shared, 0, sizeof shared);
9098 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
9100 tree type, arg_type;
9101 int signature = d->signature;
9104 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
9105 type = shared[signature];
9108 int has_result = signature_args[signature][0] != 0;
9110 if (signature_args[signature][1] == 8
9111 && (insn_data[d->icode].operand[has_result].mode != Pmode))
9113 if (! TARGET_FPU_ANY
9114 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
9116 type = void_list_node;
9119 int arg = signature_args[signature][i];
9120 int opno = i - 1 + has_result;
9123 arg_type = ptr_type_node;
9125 arg_type = ((*lang_hooks.types.type_for_mode)
9126 (insn_data[d->icode].operand[opno].mode,
9131 arg_type = void_type_node;
9134 type = tree_cons (NULL_TREE, arg_type, type);
9136 type = build_function_type (arg_type, type);
9137 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
9138 shared[signature] = type;
9140 builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
9146 sh_init_builtins (void)
9149 sh_media_init_builtins ();
9152 /* Expand an expression EXP that calls a built-in function,
9153 with result going to TARGET if that's convenient
9154 (and in mode MODE if that's convenient).
9155 SUBTARGET may be used as the target for computing one of EXP's operands.
9156 IGNORE is nonzero if the value is to be ignored. */
9159 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9160 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
9162 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9163 tree arglist = TREE_OPERAND (exp, 1);
9164 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9165 const struct builtin_description *d = &bdesc[fcode];
9166 enum insn_code icode = d->icode;
9167 int signature = d->signature;
9168 enum machine_mode tmode = VOIDmode;
9173 if (signature_args[signature][0])
9178 tmode = insn_data[icode].operand[0].mode;
9180 || GET_MODE (target) != tmode
9181 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9182 target = gen_reg_rtx (tmode);
9188 for (i = 1; i <= 3; i++, nop++)
9191 enum machine_mode opmode, argmode;
9193 if (! signature_args[signature][i])
9195 arg = TREE_VALUE (arglist);
9196 if (arg == error_mark_node)
9198 arglist = TREE_CHAIN (arglist);
9199 opmode = insn_data[icode].operand[nop].mode;
9200 argmode = TYPE_MODE (TREE_TYPE (arg));
9201 if (argmode != opmode)
9202 arg = build1 (NOP_EXPR,
9203 (*lang_hooks.types.type_for_mode) (opmode, 0), arg);
9204 op[nop] = expand_expr (arg, NULL_RTX, opmode, 0);
9205 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
9206 op[nop] = copy_to_mode_reg (opmode, op[nop]);
9212 pat = (*insn_data[d->icode].genfun) (op[0]);
9215 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
9218 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
9221 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
9233 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
9235 rtx sel0 = const0_rtx;
9236 rtx sel1 = const1_rtx;
9237 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
9238 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
9240 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
9241 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
9245 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
9247 rtx sel0 = const0_rtx;
9248 rtx sel1 = const1_rtx;
9249 rtx (*fn) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx)
9251 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
9253 emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0, sel1));
9254 emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1, sel0));
9257 /* Return the class of registers for which a mode change from FROM to TO
9260 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
9261 enum reg_class class)
9263 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
9265 if (TARGET_LITTLE_ENDIAN)
9267 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
9268 return reg_classes_intersect_p (DF_REGS, class);
9272 if (GET_MODE_SIZE (from) < 8)
9273 return reg_classes_intersect_p (DF_HI_REGS, class);
9280 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
9281 that label is used. */
9284 sh_mark_label (rtx address, int nuses)
9286 if (GOTOFF_P (address))
9288 /* Extract the label or symbol. */
9289 address = XEXP (address, 0);
9290 if (GET_CODE (address) == PLUS)
9291 address = XEXP (address, 0);
9292 address = XVECEXP (address, 0, 0);
9294 if (GET_CODE (address) == LABEL_REF
9295 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
9296 LABEL_NUSES (XEXP (address, 0)) += nuses;
9299 /* Compute extra cost of moving data between one register class
9302 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
9303 uses this information. Hence, the general register <-> floating point
9304 register information here is not used for SFmode. */
9307 sh_register_move_cost (enum machine_mode mode,
9308 enum reg_class srcclass, enum reg_class dstclass)
9310 if (dstclass == T_REGS || dstclass == PR_REGS)
9313 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
9316 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
9317 && REGCLASS_HAS_FP_REG (srcclass)
9318 && REGCLASS_HAS_FP_REG (dstclass))
9321 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
9322 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
9325 if ((REGCLASS_HAS_FP_REG (dstclass)
9326 && REGCLASS_HAS_GENERAL_REG (srcclass))
9327 || (REGCLASS_HAS_GENERAL_REG (dstclass)
9328 && REGCLASS_HAS_FP_REG (srcclass)))
9329 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
9330 * ((GET_MODE_SIZE (mode) + 7) / 8U));
9332 if ((dstclass == FPUL_REGS
9333 && REGCLASS_HAS_GENERAL_REG (srcclass))
9334 || (srcclass == FPUL_REGS
9335 && REGCLASS_HAS_GENERAL_REG (dstclass)))
9338 if ((dstclass == FPUL_REGS
9339 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
9340 || (srcclass == FPUL_REGS
9341 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
9344 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
9345 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
9348 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
9349 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
9354 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
9355 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
9356 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
9358 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
9361 /* Like register_operand, but take into account that SHMEDIA can use
9362 the constant zero like a general register. */
9364 sh_register_operand (rtx op, enum machine_mode mode)
9366 if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
9368 return register_operand (op, mode);
9372 cmpsi_operand (rtx op, enum machine_mode mode)
9374 if (GET_CODE (op) == REG && REGNO (op) == T_REG
9375 && GET_MODE (op) == SImode)
9377 return arith_operand (op, mode);
9380 static rtx emit_load_ptr (rtx, rtx);
9383 emit_load_ptr (rtx reg, rtx addr)
9385 rtx mem = gen_rtx_MEM (ptr_mode, addr);
9387 if (Pmode != ptr_mode)
9388 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
9389 return emit_move_insn (reg, mem);
9393 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
9394 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9397 CUMULATIVE_ARGS cum;
9398 int structure_value_byref = 0;
9399 rtx this, this_value, sibcall, insns, funexp;
9400 tree funtype = TREE_TYPE (function);
9401 int simple_add = CONST_OK_FOR_ADD (delta);
9403 rtx scratch0, scratch1, scratch2;
9405 reload_completed = 1;
9406 epilogue_completed = 1;
9408 current_function_uses_only_leaf_regs = 1;
9410 emit_note (NOTE_INSN_PROLOGUE_END);
9412 /* Find the "this" pointer. We have such a wide range of ABIs for the
9413 SH that it's best to do this completely machine independently.
9414 "this" is passed as first argument, unless a structure return pointer
9415 comes first, in which case "this" comes second. */
9416 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
9417 #ifndef PCC_STATIC_STRUCT_RETURN
9418 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9419 structure_value_byref = 1;
9420 #endif /* not PCC_STATIC_STRUCT_RETURN */
9421 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
9423 tree ptype = build_pointer_type (TREE_TYPE (funtype));
9425 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
9427 this = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
9429 /* For SHcompact, we only have r0 for a scratch register: r1 is the
9430 static chain pointer (even if you can't have nested virtual functions
9431 right now, someone might implement them sometime), and the rest of the
9432 registers are used for argument passing, are callee-saved, or reserved. */
9433 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
9436 scratch1 = gen_rtx_REG (ptr_mode, 1);
9437 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
9438 pointing where to return struct values. */
9439 scratch2 = gen_rtx_REG (Pmode, 3);
9441 else if (TARGET_SHMEDIA)
9443 scratch1 = gen_rtx_REG (ptr_mode, 21);
9444 scratch2 = gen_rtx_REG (Pmode, TR0_REG);
9447 this_value = plus_constant (this, delta);
9449 && (simple_add || scratch0 != scratch1)
9450 && strict_memory_address_p (ptr_mode, this_value))
9452 emit_load_ptr (scratch0, this_value);
9458 else if (simple_add)
9459 emit_move_insn (this, this_value);
9462 emit_move_insn (scratch1, GEN_INT (delta));
9463 emit_insn (gen_add2_insn (this, scratch1));
9471 emit_load_ptr (scratch0, this);
9473 offset_addr = plus_constant (scratch0, vcall_offset);
9474 if (strict_memory_address_p (ptr_mode, offset_addr))
9476 else if (! TARGET_SH5)
9478 /* scratch0 != scratch1, and we have indexed loads. Get better
9479 schedule by loading the offset into r1 and using an indexed
9480 load - then the load of r1 can issue before the load from
9481 (this + delta) finishes. */
9482 emit_move_insn (scratch1, GEN_INT (vcall_offset));
9483 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
9485 else if (CONST_OK_FOR_ADD (vcall_offset))
9487 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
9488 offset_addr = scratch0;
9490 else if (scratch0 != scratch1)
9492 emit_move_insn (scratch1, GEN_INT (vcall_offset));
9493 emit_insn (gen_add2_insn (scratch0, scratch1));
9494 offset_addr = scratch0;
9497 abort (); /* FIXME */
9498 emit_load_ptr (scratch0, offset_addr);
9500 if (Pmode != ptr_mode)
9501 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
9502 emit_insn (gen_add2_insn (this, scratch0));
9505 /* Generate a tail call to the target function. */
9506 if (! TREE_USED (function))
9508 assemble_external (function);
9509 TREE_USED (function) = 1;
9511 funexp = XEXP (DECL_RTL (function), 0);
9512 emit_move_insn (scratch2, funexp);
9513 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
9514 sibcall = emit_call_insn (gen_sibcall (funexp, const0_rtx, NULL_RTX));
9515 SIBLING_CALL_P (sibcall) = 1;
9516 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this);
9519 /* Run just enough of rest_of_compilation to do scheduling and get
9520 the insns emitted. Note that use_thunk calls
9521 assemble_start_function and assemble_end_function. */
9523 insn_locators_initialize ();
9524 insns = get_insns ();
9526 if (optimize > 0 && flag_schedule_insns_after_reload)
9528 find_basic_blocks (insns, max_reg_num (), dump_file);
9529 life_analysis (insns, dump_file, PROP_FINAL);
9531 split_all_insns (1);
9533 schedule_insns (dump_file);
9538 if (optimize > 0 && flag_delayed_branch)
9539 dbr_schedule (insns, dump_file);
9540 shorten_branches (insns);
9541 final_start_function (insns, file, 1);
9542 final (insns, file, 1, 0);
9543 final_end_function ();
9545 if (optimize > 0 && flag_schedule_insns_after_reload)
9547 /* Release all memory allocated by flow. */
9548 free_basic_block_vars ();
9550 /* Release all memory held by regsets now. */
9551 regset_release_memory ();
9554 reload_completed = 0;
9555 epilogue_completed = 0;
9560 function_symbol (const char *name)
9562 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
9563 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
9567 /* Find the number of a general purpose register in S. */
9569 scavenge_reg (HARD_REG_SET *s)
9572 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
9573 if (TEST_HARD_REG_BIT (*s, r))
9579 sh_get_pr_initial_val (void)
9583 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
9584 PR register on SHcompact, because it might be clobbered by the prologue.
9585 We check first if that is known to be the case. */
9586 if (TARGET_SHCOMPACT
9587 && ((current_function_args_info.call_cookie
9588 & ~ CALL_COOKIE_RET_TRAMP (1))
9589 || current_function_has_nonlocal_label))
9590 return gen_rtx_MEM (SImode, return_address_pointer_rtx);
9592 /* If we haven't finished rtl generation, there might be a nonlocal label
9593 that we haven't seen yet.
9594 ??? get_hard_reg_initial_val fails if it is called while no_new_pseudos
9595 is set, unless it has been called before for the same register. And even
9596 then, we end in trouble if we didn't use the register in the same
9597 basic block before. So call get_hard_reg_initial_val now and wrap it
9598 in an unspec if we might need to replace it. */
9599 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
9600 combine can put the pseudo returned by get_hard_reg_initial_val into
9601 instructions that need a general purpose registers, which will fail to
9602 be recognized when the pseudo becomes allocated to PR. */
9604 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9606 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
9611 sh_expand_t_scc (enum rtx_code code, rtx target)
9613 rtx result = target;
9616 if (GET_CODE (sh_compare_op0) != REG || REGNO (sh_compare_op0) != T_REG
9617 || GET_CODE (sh_compare_op1) != CONST_INT)
9619 if (GET_CODE (result) != REG)
9620 result = gen_reg_rtx (SImode);
9621 val = INTVAL (sh_compare_op1);
9622 if ((code == EQ && val == 1) || (code == NE && val == 0))
9623 emit_insn (gen_movt (result));
9624 else if ((code == EQ && val == 0) || (code == NE && val == 1))
9626 emit_insn (gen_rtx_CLOBBER (VOIDmode, result));
9627 emit_insn (gen_subc (result, result, result));
9628 emit_insn (gen_addsi3 (result, result, const1_rtx));
9630 else if (code == EQ || code == NE)
9631 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
9634 if (result != target)
9635 emit_move_insn (target, result);
9639 /* INSN is an sfunc; return the rtx that describes the address used. */
9641 extract_sfunc_addr (rtx insn)
9643 rtx pattern, part = NULL_RTX;
9646 pattern = PATTERN (insn);
9647 len = XVECLEN (pattern, 0);
9648 for (i = 0; i < len; i++)
9650 part = XVECEXP (pattern, 0, i);
9651 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
9652 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
9653 return XEXP (part, 0);
9655 if (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE)
9656 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
9660 /* Verify that the register in use_sfunc_addr still agrees with the address
9661 used in the sfunc. This prevents fill_slots_from_thread from changing
9663 INSN is the use_sfunc_addr instruction, and REG is the register it
9666 check_use_sfunc_addr (rtx insn, rtx reg)
9668 /* Search for the sfunc. It should really come right after INSN. */
9669 while ((insn = NEXT_INSN (insn)))
9671 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN)
9673 if (! INSN_P (insn))
9676 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
9677 insn = XVECEXP (PATTERN (insn), 0, 0);
9678 if (GET_CODE (PATTERN (insn)) != PARALLEL
9679 || get_attr_type (insn) != TYPE_SFUNC)
9681 return rtx_equal_p (extract_sfunc_addr (insn), reg);