1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "insn-config.h"
35 #include "hard-reg-set.h"
37 #include "insn-attr.h"
41 #include "integrate.h"
45 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
52 #include "sched-int.h"
54 #include "tree-gimple.h"
56 #include "alloc-pool.h"
57 #include "tm-constrs.h"
60 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
62 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
63 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
65 /* These are some macros to abstract register modes. */
66 #define CONST_OK_FOR_ADD(size) \
67 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
68 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
69 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
70 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
72 /* Used to simplify the logic below. Find the attributes wherever
74 #define SH_ATTRIBUTES(decl) \
75 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
76 : DECL_ATTRIBUTES (decl) \
77 ? (DECL_ATTRIBUTES (decl)) \
78 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
80 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
81 int current_function_interrupt;
83 tree sh_deferred_function_attributes;
84 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
86 /* Global variables for machine-dependent things. */
88 /* Which cpu are we scheduling for. */
89 enum processor_type sh_cpu;
91 /* Definitions used in ready queue reordering for first scheduling pass. */
93 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
94 static short *regmode_weight[2];
96 /* Total SFmode and SImode weights of scheduled insns. */
97 static int curr_regmode_pressure[2];
99 /* Number of r0 life regions. */
100 static int r0_life_regions;
102 /* If true, skip cycles for Q -> R movement. */
103 static int skip_cycles = 0;
105 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
106 and returned from sh_reorder2. */
107 static short cached_can_issue_more;
109 /* Saved operands from the last compare to use when we generate an scc
115 /* Provides the class number of the smallest class containing
118 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
120 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
131 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
132 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
133 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
135 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
136 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
147 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
148 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
149 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
152 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
153 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
154 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
155 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
156 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
157 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
158 GENERAL_REGS, GENERAL_REGS,
161 char sh_register_names[FIRST_PSEUDO_REGISTER] \
162 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
164 char sh_additional_register_names[ADDREGNAMES_SIZE] \
165 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
166 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
168 int assembler_dialect;
170 static bool shmedia_space_reserved_for_target_registers;
172 static bool sh_handle_option (size_t, const char *, int);
173 static void split_branches (rtx);
174 static int branch_dest (rtx);
175 static void force_into (rtx, rtx);
176 static void print_slot (rtx);
177 static rtx add_constant (rtx, enum machine_mode, rtx);
178 static void dump_table (rtx, rtx);
179 static int hi_const (rtx);
180 static int broken_move (rtx);
181 static int mova_p (rtx);
182 static rtx find_barrier (int, rtx, rtx);
183 static int noncall_uses_reg (rtx, rtx, rtx *);
184 static rtx gen_block_redirect (rtx, int, int);
185 static void sh_reorg (void);
186 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
187 static rtx frame_insn (rtx);
188 static rtx push (int);
189 static void pop (int);
190 static void push_regs (HARD_REG_SET *, int);
191 static int calc_live_regs (HARD_REG_SET *);
192 static HOST_WIDE_INT rounded_frame_size (int);
193 static rtx mark_constant_pool_use (rtx);
194 const struct attribute_spec sh_attribute_table[];
195 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
196 static tree sh_handle_resbank_handler_attribute (tree *, tree,
198 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
200 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
201 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
202 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
203 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
204 static void sh_insert_attributes (tree, tree *);
205 static const char *sh_check_pch_target_flags (int);
206 static int sh_adjust_cost (rtx, rtx, rtx, int);
207 static int sh_issue_rate (void);
208 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
209 static short find_set_regmode_weight (rtx, enum machine_mode);
210 static short find_insn_regmode_weight (rtx, enum machine_mode);
211 static void find_regmode_weight (basic_block, enum machine_mode);
212 static int find_r0_life_regions (basic_block);
213 static void sh_md_init_global (FILE *, int, int);
214 static void sh_md_finish_global (FILE *, int);
215 static int rank_for_reorder (const void *, const void *);
216 static void swap_reorder (rtx *, int);
217 static void ready_reorder (rtx *, int);
218 static short high_pressure (enum machine_mode);
219 static int sh_reorder (FILE *, int, rtx *, int *, int);
220 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
221 static void sh_md_init (FILE *, int, int);
222 static int sh_variable_issue (FILE *, int, rtx, int);
224 static bool sh_function_ok_for_sibcall (tree, tree);
226 static bool sh_cannot_modify_jumps_p (void);
227 static int sh_target_reg_class (void);
228 static bool sh_optimize_target_register_callee_saved (bool);
229 static bool sh_ms_bitfield_layout_p (const_tree);
231 static void sh_init_builtins (void);
232 static void sh_media_init_builtins (void);
233 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
234 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
235 static void sh_file_start (void);
236 static int flow_dependent_p (rtx, rtx);
237 static void flow_dependent_p_1 (rtx, const_rtx, void *);
238 static int shiftcosts (rtx);
239 static int andcosts (rtx);
240 static int addsubcosts (rtx);
241 static int multcosts (rtx);
242 static bool unspec_caller_rtx_p (rtx);
243 static bool sh_cannot_copy_insn_p (rtx);
244 static bool sh_rtx_costs (rtx, int, int, int *);
245 static int sh_address_cost (rtx);
246 static int sh_pr_n_sets (void);
247 static rtx sh_allocate_initial_value (rtx);
248 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
249 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
250 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
251 static int scavenge_reg (HARD_REG_SET *s);
252 struct save_schedule_s;
253 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
254 struct save_schedule_s *, int);
256 static rtx sh_struct_value_rtx (tree, int);
257 static bool sh_return_in_memory (const_tree, const_tree);
258 static rtx sh_builtin_saveregs (void);
259 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
260 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
261 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
262 static tree sh_build_builtin_va_list (void);
263 static void sh_va_start (tree, rtx);
264 static tree sh_gimplify_va_arg_expr (tree, tree, tree *, tree *);
265 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
267 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
269 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
271 static bool sh_scalar_mode_supported_p (enum machine_mode);
272 static int sh_dwarf_calling_convention (const_tree);
273 static void sh_encode_section_info (tree, rtx, int);
274 static int sh2a_function_vector_p (tree);
277 /* Initialize the GCC target structure. */
278 #undef TARGET_ATTRIBUTE_TABLE
279 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
281 /* The next two are used for debug info when compiling with -gdwarf. */
282 #undef TARGET_ASM_UNALIGNED_HI_OP
283 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
284 #undef TARGET_ASM_UNALIGNED_SI_OP
285 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
287 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
288 #undef TARGET_ASM_UNALIGNED_DI_OP
289 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
290 #undef TARGET_ASM_ALIGNED_DI_OP
291 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
293 #undef TARGET_ASM_FUNCTION_EPILOGUE
294 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
296 #undef TARGET_ASM_OUTPUT_MI_THUNK
297 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
299 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
300 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
302 #undef TARGET_ASM_FILE_START
303 #define TARGET_ASM_FILE_START sh_file_start
304 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
305 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
307 #undef TARGET_DEFAULT_TARGET_FLAGS
308 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
309 #undef TARGET_HANDLE_OPTION
310 #define TARGET_HANDLE_OPTION sh_handle_option
312 #undef TARGET_INSERT_ATTRIBUTES
313 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
315 #undef TARGET_SCHED_ADJUST_COST
316 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
318 #undef TARGET_SCHED_ISSUE_RATE
319 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
321 /* The next 5 hooks have been implemented for reenabling sched1. With the
322 help of these macros we are limiting the movement of insns in sched1 to
323 reduce the register pressure. The overall idea is to keep count of SImode
324 and SFmode regs required by already scheduled insns. When these counts
325 cross some threshold values; give priority to insns that free registers.
326 The insn that frees registers is most likely to be the insn with lowest
327 LUID (original insn order); but such an insn might be there in the stalled
328 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
329 upto a max of 8 cycles so that such insns may move from Q -> R.
331 The description of the hooks are as below:
333 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
334 scheduler; it is called inside the sched_init function just after
335 find_insn_reg_weights function call. It is used to calculate the SImode
336 and SFmode weights of insns of basic blocks; much similar to what
337 find_insn_reg_weights does.
338 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
340 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
341 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
344 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
345 high; reorder the ready queue so that the insn with lowest LUID will be
348 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
349 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
351 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
352 can be returned from TARGET_SCHED_REORDER2.
354 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
356 #undef TARGET_SCHED_DFA_NEW_CYCLE
357 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
359 #undef TARGET_SCHED_INIT_GLOBAL
360 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
362 #undef TARGET_SCHED_FINISH_GLOBAL
363 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
365 #undef TARGET_SCHED_VARIABLE_ISSUE
366 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
368 #undef TARGET_SCHED_REORDER
369 #define TARGET_SCHED_REORDER sh_reorder
371 #undef TARGET_SCHED_REORDER2
372 #define TARGET_SCHED_REORDER2 sh_reorder2
374 #undef TARGET_SCHED_INIT
375 #define TARGET_SCHED_INIT sh_md_init
377 #undef TARGET_CANNOT_MODIFY_JUMPS_P
378 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
379 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
380 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
381 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
382 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
383 sh_optimize_target_register_callee_saved
385 #undef TARGET_MS_BITFIELD_LAYOUT_P
386 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
388 #undef TARGET_INIT_BUILTINS
389 #define TARGET_INIT_BUILTINS sh_init_builtins
390 #undef TARGET_EXPAND_BUILTIN
391 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
393 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
394 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
396 #undef TARGET_CANNOT_COPY_INSN_P
397 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
398 #undef TARGET_RTX_COSTS
399 #define TARGET_RTX_COSTS sh_rtx_costs
400 #undef TARGET_ADDRESS_COST
401 #define TARGET_ADDRESS_COST sh_address_cost
402 #undef TARGET_ALLOCATE_INITIAL_VALUE
403 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
405 #undef TARGET_MACHINE_DEPENDENT_REORG
406 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
409 #undef TARGET_HAVE_TLS
410 #define TARGET_HAVE_TLS true
413 #undef TARGET_PROMOTE_PROTOTYPES
414 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
415 #undef TARGET_PROMOTE_FUNCTION_ARGS
416 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
417 #undef TARGET_PROMOTE_FUNCTION_RETURN
418 #define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
420 #undef TARGET_STRUCT_VALUE_RTX
421 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
422 #undef TARGET_RETURN_IN_MEMORY
423 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
425 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
426 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
427 #undef TARGET_SETUP_INCOMING_VARARGS
428 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
429 #undef TARGET_STRICT_ARGUMENT_NAMING
430 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
431 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
432 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
433 #undef TARGET_MUST_PASS_IN_STACK
434 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
435 #undef TARGET_PASS_BY_REFERENCE
436 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
437 #undef TARGET_CALLEE_COPIES
438 #define TARGET_CALLEE_COPIES sh_callee_copies
439 #undef TARGET_ARG_PARTIAL_BYTES
440 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
442 #undef TARGET_BUILD_BUILTIN_VA_LIST
443 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
444 #undef TARGET_EXPAND_BUILTIN_VA_START
445 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
446 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
447 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
449 #undef TARGET_SCALAR_MODE_SUPPORTED_P
450 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
451 #undef TARGET_VECTOR_MODE_SUPPORTED_P
452 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
454 #undef TARGET_CHECK_PCH_TARGET_FLAGS
455 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
457 #undef TARGET_DWARF_CALLING_CONVENTION
458 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
460 /* Return regmode weight for insn. */
461 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
463 /* Return current register pressure for regmode. */
464 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
466 #undef TARGET_ENCODE_SECTION_INFO
467 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
471 #undef TARGET_ENCODE_SECTION_INFO
472 #define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
473 #undef TARGET_STRIP_NAME_ENCODING
474 #define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
475 #undef TARGET_CXX_IMPORT_EXPORT_CLASS
476 #define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
480 #undef TARGET_SECONDARY_RELOAD
481 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
483 /* Machine-specific symbol_ref flags. */
484 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
486 struct gcc_target targetm = TARGET_INITIALIZER;
488 /* Implement TARGET_HANDLE_OPTION. */
491 sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
492 int value ATTRIBUTE_UNUSED)
497 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
501 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
505 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
509 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
513 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
516 case OPT_m2a_single_only:
517 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
521 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
525 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
529 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
536 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
540 case OPT_m4_100_nofpu:
541 case OPT_m4_200_nofpu:
542 case OPT_m4_300_nofpu:
546 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
550 case OPT_m4_100_single:
551 case OPT_m4_200_single:
552 case OPT_m4_300_single:
553 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
556 case OPT_m4_single_only:
557 case OPT_m4_100_single_only:
558 case OPT_m4_200_single_only:
559 case OPT_m4_300_single_only:
560 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
564 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
569 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
573 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
576 case OPT_m4a_single_only:
577 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
581 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
584 case OPT_m5_32media_nofpu:
585 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
589 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
592 case OPT_m5_64media_nofpu:
593 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
597 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
600 case OPT_m5_compact_nofpu:
601 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
609 /* Print the operand address in x to the stream. */
612 print_operand_address (FILE *stream, rtx x)
614 switch (GET_CODE (x))
618 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
623 rtx base = XEXP (x, 0);
624 rtx index = XEXP (x, 1);
626 switch (GET_CODE (index))
629 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
630 reg_names[true_regnum (base)]);
636 int base_num = true_regnum (base);
637 int index_num = true_regnum (index);
639 fprintf (stream, "@(r0,%s)",
640 reg_names[MAX (base_num, index_num)]);
651 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
655 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
659 x = mark_constant_pool_use (x);
660 output_addr_const (stream, x);
665 /* Print operand x (an rtx) in assembler syntax to file stream
666 according to modifier code.
668 '.' print a .s if insn needs delay slot
669 ',' print LOCAL_LABEL_PREFIX
670 '@' print trap, rte or rts depending upon pragma interruptness
671 '#' output a nop if there is nothing to put in the delay slot
672 ''' print likelihood suffix (/u for unlikely).
673 '>' print branch target if -fverbose-asm
674 'O' print a constant without the #
675 'R' print the LSW of a dp value - changes if in little endian
676 'S' print the MSW of a dp value - changes if in little endian
677 'T' print the next word of a dp value - same as 'R' in big endian mode.
678 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
679 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
680 'N' print 'r63' if the operand is (const_int 0).
681 'd' print a V2SF reg as dN instead of fpN.
682 'm' print a pair `base,offset' or `base,index', for LD and ST.
683 'U' Likewise for {LD,ST}{HI,LO}.
684 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
685 'o' output an operator. */
688 print_operand (FILE *stream, rtx x, int code)
691 enum machine_mode mode;
699 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
700 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
701 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
704 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
707 trapa_attr = lookup_attribute ("trap_exit",
708 DECL_ATTRIBUTES (current_function_decl));
710 fprintf (stream, "trapa #%ld",
711 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
712 else if (sh_cfun_interrupt_handler_p ())
714 if (sh_cfun_resbank_handler_p ())
715 fprintf (stream, "resbank\n");
716 fprintf (stream, "rte");
719 fprintf (stream, "rts");
722 /* Output a nop if there's nothing in the delay slot. */
723 if (dbr_sequence_length () == 0)
724 fprintf (stream, "\n\tnop");
728 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
730 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
731 fputs ("/u", stream);
735 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
737 fputs ("\t! target: ", stream);
738 output_addr_const (stream, JUMP_LABEL (current_output_insn));
742 x = mark_constant_pool_use (x);
743 output_addr_const (stream, x);
745 /* N.B.: %R / %S / %T adjust memory addresses by four.
746 For SHMEDIA, that means they can be used to access the first and
747 second 32 bit part of a 64 bit (or larger) value that
748 might be held in floating point registers or memory.
749 While they can be used to access 64 bit parts of a larger value
750 held in general purpose registers, that won't work with memory -
751 neither for fp registers, since the frxx names are used. */
753 if (REG_P (x) || GET_CODE (x) == SUBREG)
755 regno = true_regnum (x);
756 regno += FP_REGISTER_P (regno) ? 1 : LSW;
757 fputs (reg_names[regno], (stream));
761 x = adjust_address (x, SImode, 4 * LSW);
762 print_operand_address (stream, XEXP (x, 0));
769 if (mode == VOIDmode)
771 if (GET_MODE_SIZE (mode) >= 8)
772 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
774 print_operand (stream, sub, 0);
776 output_operand_lossage ("invalid operand to %%R");
780 if (REG_P (x) || GET_CODE (x) == SUBREG)
782 regno = true_regnum (x);
783 regno += FP_REGISTER_P (regno) ? 0 : MSW;
784 fputs (reg_names[regno], (stream));
788 x = adjust_address (x, SImode, 4 * MSW);
789 print_operand_address (stream, XEXP (x, 0));
796 if (mode == VOIDmode)
798 if (GET_MODE_SIZE (mode) >= 8)
799 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
801 print_operand (stream, sub, 0);
803 output_operand_lossage ("invalid operand to %%S");
807 /* Next word of a double. */
808 switch (GET_CODE (x))
811 fputs (reg_names[REGNO (x) + 1], (stream));
814 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
815 && GET_CODE (XEXP (x, 0)) != POST_INC)
816 x = adjust_address (x, SImode, 4);
817 print_operand_address (stream, XEXP (x, 0));
824 switch (GET_CODE (x))
826 case PLUS: fputs ("add", stream); break;
827 case MINUS: fputs ("sub", stream); break;
828 case MULT: fputs ("mul", stream); break;
829 case DIV: fputs ("div", stream); break;
830 case EQ: fputs ("eq", stream); break;
831 case NE: fputs ("ne", stream); break;
832 case GT: case LT: fputs ("gt", stream); break;
833 case GE: case LE: fputs ("ge", stream); break;
834 case GTU: case LTU: fputs ("gtu", stream); break;
835 case GEU: case LEU: fputs ("geu", stream); break;
843 if (GET_CODE (x) == MEM
844 && GET_CODE (XEXP (x, 0)) == PLUS
845 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
846 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
851 if (GET_CODE (x) == MEM)
853 switch (GET_MODE (x))
855 case QImode: fputs (".b", stream); break;
856 case HImode: fputs (".w", stream); break;
857 case SImode: fputs (".l", stream); break;
858 case SFmode: fputs (".s", stream); break;
859 case DFmode: fputs (".d", stream); break;
860 default: gcc_unreachable ();
867 gcc_assert (GET_CODE (x) == MEM);
871 switch (GET_CODE (x))
875 print_operand (stream, x, 0);
876 fputs (", 0", stream);
880 print_operand (stream, XEXP (x, 0), 0);
881 fputs (", ", stream);
882 print_operand (stream, XEXP (x, 1), 0);
891 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == V2SFmode);
893 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
897 if (x == CONST0_RTX (GET_MODE (x)))
899 fprintf ((stream), "r63");
904 if (GET_CODE (x) == CONST_INT)
906 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
916 switch (GET_CODE (x))
920 rtx inner = XEXP (x, 0);
922 enum machine_mode inner_mode;
924 /* We might see SUBREGs with vector mode registers inside. */
925 if (GET_CODE (inner) == SUBREG
926 && (GET_MODE_SIZE (GET_MODE (inner))
927 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
928 && subreg_lowpart_p (inner))
929 inner = SUBREG_REG (inner);
930 if (GET_CODE (inner) == CONST_INT)
932 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
935 inner_mode = GET_MODE (inner);
936 if (GET_CODE (inner) == SUBREG
937 && (GET_MODE_SIZE (GET_MODE (inner))
938 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
939 && GET_CODE (SUBREG_REG (inner)) == REG)
941 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
942 GET_MODE (SUBREG_REG (inner)),
945 inner = SUBREG_REG (inner);
947 if (GET_CODE (inner) != REG || GET_MODE_SIZE (inner_mode) > 8)
949 /* Floating point register pairs are always big endian;
950 general purpose registers are 64 bit wide. */
951 regno = REGNO (inner);
952 regno = (HARD_REGNO_NREGS (regno, inner_mode)
953 - HARD_REGNO_NREGS (regno, mode))
961 /* FIXME: We need this on SHmedia32 because reload generates
962 some sign-extended HI or QI loads into DImode registers
963 but, because Pmode is SImode, the address ends up with a
964 subreg:SI of the DImode register. Maybe reload should be
965 fixed so as to apply alter_subreg to such loads? */
967 gcc_assert (trapping_target_operand (x, VOIDmode));
968 x = XEXP (XEXP (x, 2), 0);
971 gcc_assert (SUBREG_BYTE (x) == 0
972 && GET_CODE (SUBREG_REG (x)) == REG);
980 if (FP_REGISTER_P (regno)
981 && mode == V16SFmode)
982 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
983 else if (FP_REGISTER_P (REGNO (x))
985 fprintf ((stream), "fv%s", reg_names[regno] + 2);
986 else if (GET_CODE (x) == REG
988 fprintf ((stream), "fp%s", reg_names[regno] + 2);
989 else if (FP_REGISTER_P (REGNO (x))
990 && GET_MODE_SIZE (mode) > 4)
991 fprintf ((stream), "d%s", reg_names[regno] + 1);
993 fputs (reg_names[regno], (stream));
997 output_address (XEXP (x, 0));
1002 && (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
1003 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
1004 && (GET_MODE (XEXP (x, 0)) == DImode
1005 || GET_MODE (XEXP (x, 0)) == SImode)
1006 && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE
1007 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)
1009 rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0);
1011 bool nested_expr = false;
1013 fputc ('(', stream);
1014 if (GET_CODE (val) == ASHIFTRT)
1016 fputc ('(', stream);
1017 val2 = XEXP (val, 0);
1019 if (GET_CODE (val2) == CONST
1020 || GET_RTX_CLASS (GET_CODE (val2)) != RTX_OBJ)
1022 fputc ('(', stream);
1025 output_addr_const (stream, val2);
1027 fputc (')', stream);
1028 if (GET_CODE (val) == ASHIFTRT)
1030 fputs (" >> ", stream);
1031 output_addr_const (stream, XEXP (val, 1));
1032 fputc (')', stream);
1034 fputs (" & 65535)", stream);
1041 fputc ('#', stream);
1042 output_addr_const (stream, x);
1050 /* Encode symbol attributes of a SYMBOL_REF into its
1051 SYMBOL_REF_FLAGS. */
1053 sh_encode_section_info (tree decl, rtx rtl, int first)
1055 default_encode_section_info (decl, rtl, first);
1057 if (TREE_CODE (decl) == FUNCTION_DECL
1058 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1059 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1062 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1064 force_into (rtx value, rtx target)
1066 value = force_operand (value, target);
1067 if (! rtx_equal_p (value, target))
1068 emit_insn (gen_move_insn (target, value));
1071 /* Emit code to perform a block move. Choose the best method.
1073 OPERANDS[0] is the destination.
1074 OPERANDS[1] is the source.
1075 OPERANDS[2] is the size.
1076 OPERANDS[3] is the alignment safe to use. */
1079 expand_block_move (rtx *operands)
1081 int align = INTVAL (operands[3]);
1082 int constp = (GET_CODE (operands[2]) == CONST_INT);
1083 int bytes = (constp ? INTVAL (operands[2]) : 0);
1088 /* If we could use mov.l to move words and dest is word-aligned, we
1089 can use movua.l for loads and still generate a relatively short
1090 and efficient sequence. */
1091 if (TARGET_SH4A_ARCH && align < 4
1092 && MEM_ALIGN (operands[0]) >= 32
1093 && can_move_by_pieces (bytes, 32))
1095 rtx dest = copy_rtx (operands[0]);
1096 rtx src = copy_rtx (operands[1]);
1097 /* We could use different pseudos for each copied word, but
1098 since movua can only load into r0, it's kind of
1100 rtx temp = gen_reg_rtx (SImode);
1101 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1104 while (copied + 4 <= bytes)
1106 rtx to = adjust_address (dest, SImode, copied);
1107 rtx from = adjust_automodify_address (src, BLKmode,
1110 set_mem_size (from, GEN_INT (4));
1111 emit_insn (gen_movua (temp, from));
1112 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1113 emit_move_insn (to, temp);
1118 move_by_pieces (adjust_address (dest, BLKmode, copied),
1119 adjust_automodify_address (src, BLKmode,
1121 bytes - copied, align, 0);
1126 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1127 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1128 if (align < 4 || (bytes % 4 != 0))
1131 if (TARGET_HARD_SH4)
1135 else if (bytes == 12)
1137 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1138 rtx r4 = gen_rtx_REG (SImode, 4);
1139 rtx r5 = gen_rtx_REG (SImode, 5);
1141 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1142 force_into (XEXP (operands[0], 0), r4);
1143 force_into (XEXP (operands[1], 0), r5);
1144 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1147 else if (! TARGET_SMALLCODE)
1149 const char *entry_name;
1150 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1152 rtx r4 = gen_rtx_REG (SImode, 4);
1153 rtx r5 = gen_rtx_REG (SImode, 5);
1154 rtx r6 = gen_rtx_REG (SImode, 6);
1156 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1157 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1158 force_into (XEXP (operands[0], 0), r4);
1159 force_into (XEXP (operands[1], 0), r5);
1161 dwords = bytes >> 3;
1162 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1163 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1172 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1173 rtx r4 = gen_rtx_REG (SImode, 4);
1174 rtx r5 = gen_rtx_REG (SImode, 5);
1176 sprintf (entry, "__movmemSI%d", bytes);
1177 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1178 force_into (XEXP (operands[0], 0), r4);
1179 force_into (XEXP (operands[1], 0), r5);
1180 emit_insn (gen_block_move_real (func_addr_rtx));
1184 /* This is the same number of bytes as a memcpy call, but to a different
1185 less common function name, so this will occasionally use more space. */
1186 if (! TARGET_SMALLCODE)
1188 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1189 int final_switch, while_loop;
1190 rtx r4 = gen_rtx_REG (SImode, 4);
1191 rtx r5 = gen_rtx_REG (SImode, 5);
1192 rtx r6 = gen_rtx_REG (SImode, 6);
1194 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1195 force_into (XEXP (operands[0], 0), r4);
1196 force_into (XEXP (operands[1], 0), r5);
1198 /* r6 controls the size of the move. 16 is decremented from it
1199 for each 64 bytes moved. Then the negative bit left over is used
1200 as an index into a list of move instructions. e.g., a 72 byte move
1201 would be set up with size(r6) = 14, for one iteration through the
1202 big while loop, and a switch of -2 for the last part. */
1204 final_switch = 16 - ((bytes / 4) % 16);
1205 while_loop = ((bytes / 4) / 16 - 1) * 16;
1206 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1207 emit_insn (gen_block_lump_real (func_addr_rtx));
1214 /* Prepare operands for a move define_expand; specifically, one of the
1215 operands must be in a register. */
1218 prepare_move_operands (rtx operands[], enum machine_mode mode)
1220 if ((mode == SImode || mode == DImode)
1222 && ! ((mode == Pmode || mode == ptr_mode)
1223 && tls_symbolic_operand (operands[1], Pmode) != 0))
1226 if (SYMBOLIC_CONST_P (operands[1]))
1228 if (GET_CODE (operands[0]) == MEM)
1229 operands[1] = force_reg (Pmode, operands[1]);
1230 else if (TARGET_SHMEDIA
1231 && GET_CODE (operands[1]) == LABEL_REF
1232 && target_reg_operand (operands[0], mode))
1236 temp = (!can_create_pseudo_p ()
1238 : gen_reg_rtx (Pmode));
1239 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1242 else if (GET_CODE (operands[1]) == CONST
1243 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1244 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1246 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1247 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1249 operands[1] = expand_binop (mode, add_optab, temp,
1250 XEXP (XEXP (operands[1], 0), 1),
1251 (!can_create_pseudo_p ()
1253 : gen_reg_rtx (Pmode)),
1254 0, OPTAB_LIB_WIDEN);
1258 if (! reload_in_progress && ! reload_completed)
1260 /* Copy the source to a register if both operands aren't registers. */
1261 if (! register_operand (operands[0], mode)
1262 && ! sh_register_operand (operands[1], mode))
1263 operands[1] = copy_to_mode_reg (mode, operands[1]);
1265 if (GET_CODE (operands[0]) == MEM && ! memory_operand (operands[0], mode))
1267 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1268 except that we can't use that function because it is static. */
1269 rtx new = change_address (operands[0], mode, 0);
1270 MEM_COPY_ATTRIBUTES (new, operands[0]);
1274 /* This case can happen while generating code to move the result
1275 of a library call to the target. Reject `st r0,@(rX,rY)' because
1276 reload will fail to find a spill register for rX, since r0 is already
1277 being used for the source. */
1279 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1280 && GET_CODE (operands[0]) == MEM
1281 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1282 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
1283 operands[1] = copy_to_mode_reg (mode, operands[1]);
1286 if (mode == Pmode || mode == ptr_mode)
1289 enum tls_model tls_kind;
1293 if (GET_CODE (op1) == CONST
1294 && GET_CODE (XEXP (op1, 0)) == PLUS
1295 && tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode))
1297 opc = XEXP (XEXP (op1, 0), 1);
1298 op1 = XEXP (XEXP (op1, 0), 0);
1303 if ((tls_kind = tls_symbolic_operand (op1, Pmode)))
1305 rtx tga_op1, tga_ret, tmp, tmp2;
1309 case TLS_MODEL_GLOBAL_DYNAMIC:
1310 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1311 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1315 case TLS_MODEL_LOCAL_DYNAMIC:
1316 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1317 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1319 tmp = gen_reg_rtx (Pmode);
1320 emit_move_insn (tmp, tga_ret);
1322 if (register_operand (op0, Pmode))
1325 tmp2 = gen_reg_rtx (Pmode);
1327 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1331 case TLS_MODEL_INITIAL_EXEC:
1334 /* Don't schedule insns for getting GOT address when
1335 the first scheduling is enabled, to avoid spill
1337 if (flag_schedule_insns)
1338 emit_insn (gen_blockage ());
1339 emit_insn (gen_GOTaddr2picreg ());
1340 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode,
1342 if (flag_schedule_insns)
1343 emit_insn (gen_blockage ());
1345 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1346 tmp = gen_sym2GOTTPOFF (op1);
1347 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1351 case TLS_MODEL_LOCAL_EXEC:
1352 tmp2 = gen_reg_rtx (Pmode);
1353 emit_insn (gen_load_gbr (tmp2));
1354 tmp = gen_reg_rtx (Pmode);
1355 emit_insn (gen_symTPOFF2reg (tmp, op1));
1357 if (register_operand (op0, Pmode))
1360 op1 = gen_reg_rtx (Pmode);
1362 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1369 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1378 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1379 enum rtx_code comparison)
1382 rtx scratch = NULL_RTX;
1384 if (comparison == CODE_FOR_nothing)
1385 comparison = GET_CODE (operands[0]);
1387 scratch = operands[4];
1388 if (GET_CODE (operands[1]) == CONST_INT
1389 && GET_CODE (operands[2]) != CONST_INT)
1391 rtx tmp = operands[1];
1393 operands[1] = operands[2];
1395 comparison = swap_condition (comparison);
1397 if (GET_CODE (operands[2]) == CONST_INT)
1399 HOST_WIDE_INT val = INTVAL (operands[2]);
1400 if ((val == -1 || val == -0x81)
1401 && (comparison == GT || comparison == LE))
1403 comparison = (comparison == GT) ? GE : LT;
1404 operands[2] = gen_int_mode (val + 1, mode);
1406 else if ((val == 1 || val == 0x80)
1407 && (comparison == GE || comparison == LT))
1409 comparison = (comparison == GE) ? GT : LE;
1410 operands[2] = gen_int_mode (val - 1, mode);
1412 else if (val == 1 && (comparison == GEU || comparison == LTU))
1414 comparison = (comparison == GEU) ? NE : EQ;
1415 operands[2] = CONST0_RTX (mode);
1417 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1419 comparison = (comparison == GEU) ? GTU : LEU;
1420 operands[2] = gen_int_mode (val - 1, mode);
1422 else if (val == 0 && (comparison == GTU || comparison == LEU))
1423 comparison = (comparison == GTU) ? NE : EQ;
1424 else if (mode == SImode
1425 && ((val == 0x7fffffff
1426 && (comparison == GTU || comparison == LEU))
1427 || ((unsigned HOST_WIDE_INT) val
1428 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1429 && (comparison == GEU || comparison == LTU))))
1431 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1432 operands[2] = CONST0_RTX (mode);
1436 if (can_create_pseudo_p ())
1437 operands[1] = force_reg (mode, op1);
1438 /* When we are handling DImode comparisons, we want to keep constants so
1439 that we can optimize the component comparisons; however, memory loads
1440 are better issued as a whole so that they can be scheduled well.
1441 SImode equality comparisons allow I08 constants, but only when they
1442 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1443 into a register, that register might as well be r0, and we allow the
1444 constant. If it is already in a register, this is likely to be
1445 allocated to a different hard register, thus we load the constant into
1446 a register unless it is zero. */
1447 if (!REG_P (operands[2])
1448 && (GET_CODE (operands[2]) != CONST_INT
1449 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1450 && ((comparison != EQ && comparison != NE)
1451 || (REG_P (op1) && REGNO (op1) != R0_REG)
1452 || !satisfies_constraint_I08 (operands[2])))))
1454 if (scratch && GET_MODE (scratch) == mode)
1456 emit_move_insn (scratch, operands[2]);
1457 operands[2] = scratch;
1459 else if (can_create_pseudo_p ())
1460 operands[2] = force_reg (mode, operands[2]);
1466 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1468 rtx (*branch_expander) (rtx) = gen_branch_true;
1471 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1474 case NE: case LT: case LE: case LTU: case LEU:
1475 comparison = reverse_condition (comparison);
1476 branch_expander = gen_branch_false;
1479 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1480 gen_rtx_fmt_ee (comparison, SImode,
1481 operands[1], operands[2])));
1482 jump = emit_jump_insn (branch_expander (operands[3]));
1483 if (probability >= 0)
1485 = gen_rtx_EXPR_LIST (REG_BR_PROB, GEN_INT (probability),
1490 /* ??? How should we distribute probabilities when more than one branch
1491 is generated. So far we only have soem ad-hoc observations:
1492 - If the operands are random, they are likely to differ in both parts.
1493 - If comparing items in a hash chain, the operands are random or equal;
1494 operation should be EQ or NE.
1495 - If items are searched in an ordered tree from the root, we can expect
1496 the highpart to be unequal about half of the time; operation should be
1497 an inequality comparison, operands non-constant, and overall probability
1498 about 50%. Likewise for quicksort.
1499 - Range checks will be often made against constants. Even if we assume for
1500 simplicity an even distribution of the non-constant operand over a
1501 sub-range here, the same probability could be generated with differently
1502 wide sub-ranges - as long as the ratio of the part of the subrange that
1503 is before the threshold to the part that comes after the threshold stays
1504 the same. Thus, we can't really tell anything here;
1505 assuming random distribution is at least simple.
1509 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1511 enum rtx_code msw_taken, msw_skip, lsw_taken;
1512 rtx skip_label = NULL_RTX;
1513 rtx op1h, op1l, op2h, op2l;
1516 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1517 rtx scratch = operands[4];
1519 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1520 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1521 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1522 op1l = gen_lowpart (SImode, operands[1]);
1523 op2l = gen_lowpart (SImode, operands[2]);
1524 msw_taken = msw_skip = lsw_taken = CODE_FOR_nothing;
1525 prob = split_branch_probability;
1526 rev_prob = REG_BR_PROB_BASE - prob;
1529 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1530 That costs 1 cycle more when the first branch can be predicted taken,
1531 but saves us mispredicts because only one branch needs prediction.
1532 It also enables generating the cmpeqdi_t-1 pattern. */
1534 if (TARGET_CMPEQDI_T)
1536 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1537 emit_jump_insn (gen_branch_true (operands[3]));
1544 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1546 msw_skip_prob = rev_prob;
1547 if (REG_BR_PROB_BASE <= 65535)
1548 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1551 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1555 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1556 / ((HOST_WIDEST_INT) prob << 32)))
1562 if (TARGET_CMPEQDI_T)
1564 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1565 emit_jump_insn (gen_branch_false (operands[3]));
1569 msw_taken_prob = prob;
1574 msw_taken = comparison;
1575 if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1)
1577 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1578 msw_skip = swap_condition (msw_taken);
1582 if (op2l == CONST0_RTX (SImode))
1583 msw_taken = comparison;
1586 msw_taken = comparison == GE ? GT : GTU;
1587 msw_skip = swap_condition (msw_taken);
1592 msw_taken = comparison;
1593 if (op2l == CONST0_RTX (SImode))
1595 msw_skip = swap_condition (msw_taken);
1599 if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1)
1600 msw_taken = comparison;
1604 if (comparison == LE)
1606 else if (op2h != CONST0_RTX (SImode))
1610 msw_skip = swap_condition (msw_taken);
1613 default: return false;
1615 num_branches = ((msw_taken != CODE_FOR_nothing)
1616 + (msw_skip != CODE_FOR_nothing)
1617 + (lsw_taken != CODE_FOR_nothing));
1618 if (comparison != EQ && comparison != NE && num_branches > 1)
1620 if (!CONSTANT_P (operands[2])
1621 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1622 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1624 msw_taken_prob = prob / 2U;
1626 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1627 lsw_taken_prob = prob;
1631 msw_taken_prob = prob;
1632 msw_skip_prob = REG_BR_PROB_BASE;
1633 /* ??? If we have a constant op2h, should we use that when
1634 calculating lsw_taken_prob? */
1635 lsw_taken_prob = prob;
1640 operands[4] = NULL_RTX;
1641 if (reload_completed
1642 && ! arith_reg_or_0_operand (op2h, SImode) && true_regnum (op1h)
1643 && (msw_taken != CODE_FOR_nothing || msw_skip != CODE_FOR_nothing))
1645 emit_move_insn (scratch, operands[2]);
1646 operands[2] = scratch;
1648 if (msw_taken != CODE_FOR_nothing)
1649 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
1650 if (msw_skip != CODE_FOR_nothing)
1652 rtx taken_label = operands[3];
1654 operands[3] = skip_label = gen_label_rtx ();
1655 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
1656 operands[3] = taken_label;
1660 if (lsw_taken != CODE_FOR_nothing)
1662 if (reload_completed
1663 && ! arith_reg_or_0_operand (op2l, SImode) && true_regnum (op1l))
1664 operands[4] = scratch;
1665 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
1667 if (msw_skip != CODE_FOR_nothing)
1668 emit_label (skip_label);
1672 /* Prepare the operands for an scc instruction; make sure that the
1673 compare has been done. */
1675 prepare_scc_operands (enum rtx_code code)
1677 rtx t_reg = gen_rtx_REG (SImode, T_REG);
1678 enum rtx_code oldcode = code;
1679 enum machine_mode mode;
1681 /* First need a compare insn. */
1685 /* It isn't possible to handle this case. */
1702 if (code != oldcode)
1704 rtx tmp = sh_compare_op0;
1705 sh_compare_op0 = sh_compare_op1;
1706 sh_compare_op1 = tmp;
1709 mode = GET_MODE (sh_compare_op0);
1710 if (mode == VOIDmode)
1711 mode = GET_MODE (sh_compare_op1);
1713 sh_compare_op0 = force_reg (mode, sh_compare_op0);
1714 if ((code != EQ && code != NE
1715 && (sh_compare_op1 != const0_rtx
1716 || code == GTU || code == GEU || code == LTU || code == LEU))
1717 || (mode == DImode && sh_compare_op1 != const0_rtx)
1718 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1719 sh_compare_op1 = force_reg (mode, sh_compare_op1);
1721 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1722 (mode == SFmode ? emit_sf_insn : emit_df_insn)
1723 (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
1724 gen_rtx_SET (VOIDmode, t_reg,
1725 gen_rtx_fmt_ee (code, SImode,
1726 sh_compare_op0, sh_compare_op1)),
1727 gen_rtx_USE (VOIDmode, get_fpscr_rtx ()))));
1729 emit_insn (gen_rtx_SET (VOIDmode, t_reg,
1730 gen_rtx_fmt_ee (code, SImode,
1731 sh_compare_op0, sh_compare_op1)));
1736 /* Called from the md file, set up the operands of a compare instruction. */
1739 from_compare (rtx *operands, int code)
1741 enum machine_mode mode = GET_MODE (sh_compare_op0);
1743 if (mode == VOIDmode)
1744 mode = GET_MODE (sh_compare_op1);
1747 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1749 /* Force args into regs, since we can't use constants here. */
1750 sh_compare_op0 = force_reg (mode, sh_compare_op0);
1751 if (sh_compare_op1 != const0_rtx
1752 || code == GTU || code == GEU
1753 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1754 sh_compare_op1 = force_reg (mode, sh_compare_op1);
1756 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
1758 from_compare (operands, GT);
1759 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
1762 insn = gen_rtx_SET (VOIDmode,
1763 gen_rtx_REG (SImode, T_REG),
1764 gen_rtx_fmt_ee (code, SImode,
1765 sh_compare_op0, sh_compare_op1));
1766 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1768 insn = gen_rtx_PARALLEL (VOIDmode,
1770 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
1771 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1777 /* Functions to output assembly code. */
1779 /* Return a sequence of instructions to perform DI or DF move.
1781 Since the SH cannot move a DI or DF in one instruction, we have
1782 to take care when we see overlapping source and dest registers. */
1785 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1786 enum machine_mode mode)
1788 rtx dst = operands[0];
1789 rtx src = operands[1];
1791 if (GET_CODE (dst) == MEM
1792 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
1793 return "mov.l %T1,%0\n\tmov.l %1,%0";
1795 if (register_operand (dst, mode)
1796 && register_operand (src, mode))
1798 if (REGNO (src) == MACH_REG)
1799 return "sts mach,%S0\n\tsts macl,%R0";
1801 /* When mov.d r1,r2 do r2->r3 then r1->r2;
1802 when mov.d r1,r0 do r1->r0 then r2->r1. */
1804 if (REGNO (src) + 1 == REGNO (dst))
1805 return "mov %T1,%T0\n\tmov %1,%0";
1807 return "mov %1,%0\n\tmov %T1,%T0";
1809 else if (GET_CODE (src) == CONST_INT)
1811 if (INTVAL (src) < 0)
1812 output_asm_insn ("mov #-1,%S0", operands);
1814 output_asm_insn ("mov #0,%S0", operands);
1816 return "mov %1,%R0";
1818 else if (GET_CODE (src) == MEM)
1821 int dreg = REGNO (dst);
1822 rtx inside = XEXP (src, 0);
1824 switch (GET_CODE (inside))
1827 ptrreg = REGNO (inside);
1831 ptrreg = subreg_regno (inside);
1835 ptrreg = REGNO (XEXP (inside, 0));
1836 /* ??? A r0+REG address shouldn't be possible here, because it isn't
1837 an offsettable address. Unfortunately, offsettable addresses use
1838 QImode to check the offset, and a QImode offsettable address
1839 requires r0 for the other operand, which is not currently
1840 supported, so we can't use the 'o' constraint.
1841 Thus we must check for and handle r0+REG addresses here.
1842 We punt for now, since this is likely very rare. */
1843 gcc_assert (GET_CODE (XEXP (inside, 1)) != REG);
1847 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
1849 return "mov.l %1,%0\n\tmov.l %1,%T0";
1854 /* Work out the safe way to copy. Copy into the second half first. */
1856 return "mov.l %T1,%T0\n\tmov.l %1,%0";
1859 return "mov.l %1,%0\n\tmov.l %T1,%T0";
1862 /* Print an instruction which would have gone into a delay slot after
1863 another instruction, but couldn't because the other instruction expanded
1864 into a sequence where putting the slot insn at the end wouldn't work. */
1867 print_slot (rtx insn)
1869 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
1871 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
1875 output_far_jump (rtx insn, rtx op)
1877 struct { rtx lab, reg, op; } this;
1878 rtx braf_base_lab = NULL_RTX;
1881 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
1884 this.lab = gen_label_rtx ();
1888 && offset - get_attr_length (insn) <= 32766)
1891 jump = "mov.w %O0,%1; braf %1";
1899 jump = "mov.l %O0,%1; braf %1";
1901 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1904 jump = "mov.l %O0,%1; jmp @%1";
1906 /* If we have a scratch register available, use it. */
1907 if (GET_CODE ((prev = prev_nonnote_insn (insn))) == INSN
1908 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
1910 this.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
1911 if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2)
1912 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1913 output_asm_insn (jump, &this.lab);
1914 if (dbr_sequence_length ())
1915 print_slot (final_sequence);
1917 output_asm_insn ("nop", 0);
1921 /* Output the delay slot insn first if any. */
1922 if (dbr_sequence_length ())
1923 print_slot (final_sequence);
1925 this.reg = gen_rtx_REG (SImode, 13);
1926 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1927 Fortunately, MACL is fixed and call-clobbered, and we never
1928 need its value across jumps, so save r13 in it instead of in
1931 output_asm_insn ("lds r13, macl", 0);
1933 output_asm_insn ("mov.l r13,@-r15", 0);
1934 output_asm_insn (jump, &this.lab);
1936 output_asm_insn ("sts macl, r13", 0);
1938 output_asm_insn ("mov.l @r15+,r13", 0);
1940 if (far && flag_pic && TARGET_SH2)
1942 braf_base_lab = gen_label_rtx ();
1943 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1944 CODE_LABEL_NUMBER (braf_base_lab));
1947 output_asm_insn (".align 2", 0);
1948 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
1950 if (far && flag_pic)
1953 this.lab = braf_base_lab;
1954 output_asm_insn (".long %O2-%O0", &this.lab);
1957 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
1961 /* Local label counter, used for constants in the pool and inside
1962 pattern branches. */
1964 static int lf = 100;
1966 /* Output code for ordinary branches. */
1969 output_branch (int logic, rtx insn, rtx *operands)
1971 switch (get_attr_length (insn))
1974 /* This can happen if filling the delay slot has caused a forward
1975 branch to exceed its range (we could reverse it, but only
1976 when we know we won't overextend other branches; this should
1977 best be handled by relaxation).
1978 It can also happen when other condbranches hoist delay slot insn
1979 from their destination, thus leading to code size increase.
1980 But the branch will still be in the range -4092..+4098 bytes. */
1985 /* The call to print_slot will clobber the operands. */
1986 rtx op0 = operands[0];
1988 /* If the instruction in the delay slot is annulled (true), then
1989 there is no delay slot where we can put it now. The only safe
1990 place for it is after the label. final will do that by default. */
1993 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
1994 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
1996 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
1997 ASSEMBLER_DIALECT ? "/" : ".", label);
1998 print_slot (final_sequence);
2001 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2003 output_asm_insn ("bra\t%l0", &op0);
2004 fprintf (asm_out_file, "\tnop\n");
2005 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2009 /* When relaxing, handle this like a short branch. The linker
2010 will fix it up if it still doesn't fit after relaxation. */
2012 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2014 /* These are for SH2e, in which we have to account for the
2015 extra nop because of the hardware bug in annulled branches. */
2021 gcc_assert (!final_sequence
2022 || !(INSN_ANNULLED_BRANCH_P
2023 (XVECEXP (final_sequence, 0, 0))));
2024 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2026 ASSEMBLER_DIALECT ? "/" : ".", label);
2027 fprintf (asm_out_file, "\tnop\n");
2028 output_asm_insn ("bra\t%l0", operands);
2029 fprintf (asm_out_file, "\tnop\n");
2030 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2034 /* When relaxing, fall through. */
2039 sprintf (buffer, "b%s%ss\t%%l0",
2041 ASSEMBLER_DIALECT ? "/" : ".");
2042 output_asm_insn (buffer, &operands[0]);
2047 /* There should be no longer branches now - that would
2048 indicate that something has destroyed the branches set
2049 up in machine_dependent_reorg. */
2054 /* Output a code sequence for INSN using TEMPLATE with OPERANDS; but before,
2055 fill in operands 9 as a label to the successor insn.
2056 We try to use jump threading where possible.
2057 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2058 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2059 follow jmp and bt, if the address is in range. */
2061 output_branchy_insn (enum rtx_code code, const char *template,
2062 rtx insn, rtx *operands)
2064 rtx next_insn = NEXT_INSN (insn);
2066 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
2068 rtx src = SET_SRC (PATTERN (next_insn));
2069 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2071 /* Following branch not taken */
2072 operands[9] = gen_label_rtx ();
2073 emit_label_after (operands[9], next_insn);
2074 INSN_ADDRESSES_NEW (operands[9],
2075 INSN_ADDRESSES (INSN_UID (next_insn))
2076 + get_attr_length (next_insn));
2081 int offset = (branch_dest (next_insn)
2082 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2083 if (offset >= -252 && offset <= 258)
2085 if (GET_CODE (src) == IF_THEN_ELSE)
2087 src = XEXP (src, 1);
2093 operands[9] = gen_label_rtx ();
2094 emit_label_after (operands[9], insn);
2095 INSN_ADDRESSES_NEW (operands[9],
2096 INSN_ADDRESSES (INSN_UID (insn))
2097 + get_attr_length (insn));
2102 output_ieee_ccmpeq (rtx insn, rtx *operands)
2104 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2108 /* Output the start of the assembler file. */
2111 sh_file_start (void)
2113 default_file_start ();
2116 /* Declare the .directive section before it is used. */
2117 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2118 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2122 /* We need to show the text section with the proper
2123 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2124 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2125 will complain. We can teach GAS specifically about the
2126 default attributes for our choice of text section, but
2127 then we would have to change GAS again if/when we change
2128 the text section name. */
2129 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2131 /* Switch to the data section so that the coffsem symbol
2132 isn't in the text section. */
2133 switch_to_section (data_section);
2135 if (TARGET_LITTLE_ENDIAN)
2136 fputs ("\t.little\n", asm_out_file);
2140 if (TARGET_SHCOMPACT)
2141 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2142 else if (TARGET_SHMEDIA)
2143 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2144 TARGET_SHMEDIA64 ? 64 : 32);
2148 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2151 unspec_caller_rtx_p (rtx pat)
2153 switch (GET_CODE (pat))
2156 return unspec_caller_rtx_p (XEXP (pat, 0));
2159 if (unspec_caller_rtx_p (XEXP (pat, 0)))
2161 return unspec_caller_rtx_p (XEXP (pat, 1));
2163 if (XINT (pat, 1) == UNSPEC_CALLER)
2172 /* Indicate that INSN cannot be duplicated. This is true for insn
2173 that generates a unique label. */
2176 sh_cannot_copy_insn_p (rtx insn)
2180 if (!reload_completed || !flag_pic)
2183 if (GET_CODE (insn) != INSN)
2185 if (asm_noperands (insn) >= 0)
2188 pat = PATTERN (insn);
2189 if (GET_CODE (pat) != SET)
2191 pat = SET_SRC (pat);
2193 if (unspec_caller_rtx_p (pat))
2199 /* Actual number of instructions used to make a shift by N. */
2200 static const char ashiftrt_insns[] =
2201 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2203 /* Left shift and logical right shift are the same. */
2204 static const char shift_insns[] =
2205 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2207 /* Individual shift amounts needed to get the above length sequences.
2208 One bit right shifts clobber the T bit, so when possible, put one bit
2209 shifts in the middle of the sequence, so the ends are eligible for
2210 branch delay slots. */
2211 static const short shift_amounts[32][5] = {
2212 {0}, {1}, {2}, {2, 1},
2213 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2214 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2215 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2216 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2217 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2218 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2219 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2221 /* Likewise, but for shift amounts < 16, up to three highmost bits
2222 might be clobbered. This is typically used when combined with some
2223 kind of sign or zero extension. */
2225 static const char ext_shift_insns[] =
2226 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2228 static const short ext_shift_amounts[32][4] = {
2229 {0}, {1}, {2}, {2, 1},
2230 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2231 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2232 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2233 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2234 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2235 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2236 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2238 /* Assuming we have a value that has been sign-extended by at least one bit,
2239 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2240 to shift it by N without data loss, and quicker than by other means? */
2241 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2243 /* This is used in length attributes in sh.md to help compute the length
2244 of arbitrary constant shift instructions. */
2247 shift_insns_rtx (rtx insn)
2249 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2250 int shift_count = INTVAL (XEXP (set_src, 1));
2251 enum rtx_code shift_code = GET_CODE (set_src);
2256 return ashiftrt_insns[shift_count];
2259 return shift_insns[shift_count];
2265 /* Return the cost of a shift. */
2275 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2277 if (GET_MODE (x) == DImode
2278 && GET_CODE (XEXP (x, 1)) == CONST_INT
2279 && INTVAL (XEXP (x, 1)) == 1)
2282 /* Everything else is invalid, because there is no pattern for it. */
2285 /* If shift by a non constant, then this will be expensive. */
2286 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2287 return SH_DYNAMIC_SHIFT_COST;
2289 value = INTVAL (XEXP (x, 1));
2291 /* Otherwise, return the true cost in instructions. */
2292 if (GET_CODE (x) == ASHIFTRT)
2294 int cost = ashiftrt_insns[value];
2295 /* If SH3, then we put the constant in a reg and use shad. */
2296 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2297 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2301 return shift_insns[value];
2304 /* Return the cost of an AND operation. */
2311 /* Anding with a register is a single cycle and instruction. */
2312 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2315 i = INTVAL (XEXP (x, 1));
2319 if (satisfies_constraint_I10 (XEXP (x, 1))
2320 || satisfies_constraint_J16 (XEXP (x, 1)))
2323 return 1 + rtx_cost (XEXP (x, 1), AND);
2326 /* These constants are single cycle extu.[bw] instructions. */
2327 if (i == 0xff || i == 0xffff)
2329 /* Constants that can be used in an and immediate instruction in a single
2330 cycle, but this requires r0, so make it a little more expensive. */
2331 if (CONST_OK_FOR_K08 (i))
2333 /* Constants that can be loaded with a mov immediate and an and.
2334 This case is probably unnecessary. */
2335 if (CONST_OK_FOR_I08 (i))
2337 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2338 This case is probably unnecessary. */
2342 /* Return the cost of an addition or a subtraction. */
2347 /* Adding a register is a single cycle insn. */
2348 if (GET_CODE (XEXP (x, 1)) == REG
2349 || GET_CODE (XEXP (x, 1)) == SUBREG)
2352 /* Likewise for small constants. */
2353 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2354 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2358 switch (GET_CODE (XEXP (x, 1)))
2363 return TARGET_SHMEDIA64 ? 5 : 3;
2366 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2368 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2370 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2378 /* Any other constant requires a 2 cycle pc-relative load plus an
2383 /* Return the cost of a multiply. */
2385 multcosts (rtx x ATTRIBUTE_UNUSED)
2387 if (sh_multcost >= 0)
2390 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2391 accept constants. Ideally, we would use a cost of one or two and
2392 add the cost of the operand, but disregard the latter when inside loops
2393 and loop invariant code motion is still to follow.
2394 Using a multiply first and splitting it later if it's a loss
2395 doesn't work because of different sign / zero extension semantics
2396 of multiplies vs. shifts. */
2397 return TARGET_SMALLCODE ? 2 : 3;
2401 /* We have a mul insn, so we can never take more than the mul and the
2402 read of the mac reg, but count more because of the latency and extra
2404 if (TARGET_SMALLCODE)
2409 /* If we're aiming at small code, then just count the number of
2410 insns in a multiply call sequence. */
2411 if (TARGET_SMALLCODE)
2414 /* Otherwise count all the insns in the routine we'd be calling too. */
2418 /* Compute a (partial) cost for rtx X. Return true if the complete
2419 cost has been computed, and false if subexpressions should be
2420 scanned. In either case, *TOTAL contains the cost result. */
2423 sh_rtx_costs (rtx x, int code, int outer_code, int *total)
2430 if (INTVAL (x) == 0)
2432 else if (outer_code == AND && and_operand ((x), DImode))
2434 else if ((outer_code == IOR || outer_code == XOR
2435 || outer_code == PLUS)
2436 && CONST_OK_FOR_I10 (INTVAL (x)))
2438 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2439 *total = COSTS_N_INSNS (outer_code != SET);
2440 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2441 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2442 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2443 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2445 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2448 if (CONST_OK_FOR_I08 (INTVAL (x)))
2450 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2451 && CONST_OK_FOR_K08 (INTVAL (x)))
2453 /* prepare_cmp_insn will force costly constants int registers before
2454 the cbranch[sd]i4 patterns can see them, so preserve potentially
2455 interesting ones not covered by I08 above. */
2456 else if (outer_code == COMPARE
2457 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2458 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2459 || INTVAL (x) == 0x7fffffff
2460 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2469 if (TARGET_SHMEDIA64)
2470 *total = COSTS_N_INSNS (4);
2471 else if (TARGET_SHMEDIA32)
2472 *total = COSTS_N_INSNS (2);
2479 *total = COSTS_N_INSNS (4);
2480 /* prepare_cmp_insn will force costly constants int registers before
2481 the cbranchdi4 pattern can see them, so preserve potentially
2482 interesting ones. */
2483 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
2489 if (x == CONST0_RTX (GET_MODE (x)))
2491 else if (sh_1el_vec (x, VOIDmode))
2492 *total = outer_code != SET;
2493 if (sh_rep_vec (x, VOIDmode))
2494 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2495 + (outer_code != SET));
2496 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2501 *total = COSTS_N_INSNS (addsubcosts (x));
2505 *total = COSTS_N_INSNS (andcosts (x));
2509 *total = COSTS_N_INSNS (multcosts (x));
2515 *total = COSTS_N_INSNS (shiftcosts (x));
2522 *total = COSTS_N_INSNS (20);
2526 if (sh_1el_vec (x, VOIDmode))
2527 *total = outer_code != SET;
2528 if (sh_rep_vec (x, VOIDmode))
2529 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2530 + (outer_code != SET));
2531 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2544 /* Compute the cost of an address. For the SH, all valid addresses are
2545 the same cost. Use a slightly higher cost for reg + reg addressing,
2546 since it increases pressure on r0. */
2549 sh_address_cost (rtx X)
2551 return (GET_CODE (X) == PLUS
2552 && ! CONSTANT_P (XEXP (X, 1))
2553 && ! TARGET_SHMEDIA ? 1 : 0);
2556 /* Code to expand a shift. */
2559 gen_ashift (int type, int n, rtx reg)
2561 /* Negative values here come from the shift_amounts array. */
2574 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
2578 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
2580 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
2583 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
2588 /* Same for HImode */
2591 gen_ashift_hi (int type, int n, rtx reg)
2593 /* Negative values here come from the shift_amounts array. */
2607 /* We don't have HImode right shift operations because using the
2608 ordinary 32 bit shift instructions for that doesn't generate proper
2609 zero/sign extension.
2610 gen_ashift_hi is only called in contexts where we know that the
2611 sign extension works out correctly. */
2614 if (GET_CODE (reg) == SUBREG)
2616 offset = SUBREG_BYTE (reg);
2617 reg = SUBREG_REG (reg);
2619 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
2623 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
2628 /* Output RTL to split a constant shift into its component SH constant
2629 shift instructions. */
2632 gen_shifty_op (int code, rtx *operands)
2634 int value = INTVAL (operands[2]);
2637 /* Truncate the shift count in case it is out of bounds. */
2638 value = value & 0x1f;
2642 if (code == LSHIFTRT)
2644 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2645 emit_insn (gen_movt (operands[0]));
2648 else if (code == ASHIFT)
2650 /* There is a two instruction sequence for 31 bit left shifts,
2651 but it requires r0. */
2652 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
2654 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
2655 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2660 else if (value == 0)
2662 /* This can happen even when optimizing, if there were subregs before
2663 reload. Don't output a nop here, as this is never optimized away;
2664 use a no-op move instead. */
2665 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
2669 max = shift_insns[value];
2670 for (i = 0; i < max; i++)
2671 gen_ashift (code, shift_amounts[value][i], operands[0]);
2674 /* Same as above, but optimized for values where the topmost bits don't
2678 gen_shifty_hi_op (int code, rtx *operands)
2680 int value = INTVAL (operands[2]);
2682 void (*gen_fun) (int, int, rtx);
2684 /* This operation is used by and_shl for SImode values with a few
2685 high bits known to be cleared. */
2689 emit_insn (gen_nop ());
2693 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
2696 max = ext_shift_insns[value];
2697 for (i = 0; i < max; i++)
2698 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2701 /* When shifting right, emit the shifts in reverse order, so that
2702 solitary negative values come first. */
2703 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
2704 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2707 /* Output RTL for an arithmetic right shift. */
2709 /* ??? Rewrite to use super-optimizer sequences. */
2712 expand_ashiftrt (rtx *operands)
2720 if (GET_CODE (operands[2]) != CONST_INT)
2722 rtx count = copy_to_mode_reg (SImode, operands[2]);
2723 emit_insn (gen_negsi2 (count, count));
2724 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2727 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
2728 > 1 + SH_DYNAMIC_SHIFT_COST)
2731 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
2732 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2736 if (GET_CODE (operands[2]) != CONST_INT)
2739 value = INTVAL (operands[2]) & 31;
2743 /* If we are called from abs expansion, arrange things so that we
2744 we can use a single MT instruction that doesn't clobber the source,
2745 if LICM can hoist out the load of the constant zero. */
2746 if (currently_expanding_to_rtl)
2748 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
2750 emit_insn (gen_mov_neg_si_t (operands[0]));
2753 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
2756 else if (value >= 16 && value <= 19)
2758 wrk = gen_reg_rtx (SImode);
2759 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
2762 gen_ashift (ASHIFTRT, 1, wrk);
2763 emit_move_insn (operands[0], wrk);
2766 /* Expand a short sequence inline, longer call a magic routine. */
2767 else if (value <= 5)
2769 wrk = gen_reg_rtx (SImode);
2770 emit_move_insn (wrk, operands[1]);
2772 gen_ashift (ASHIFTRT, 1, wrk);
2773 emit_move_insn (operands[0], wrk);
2777 wrk = gen_reg_rtx (Pmode);
2779 /* Load the value into an arg reg and call a helper. */
2780 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2781 sprintf (func, "__ashiftrt_r4_%d", value);
2782 function_symbol (wrk, func, SFUNC_STATIC);
2783 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
2784 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
2789 sh_dynamicalize_shift_p (rtx count)
2791 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
2794 /* Try to find a good way to implement the combiner pattern
2795 [(set (match_operand:SI 0 "register_operand" "r")
2796 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2797 (match_operand:SI 2 "const_int_operand" "n"))
2798 (match_operand:SI 3 "const_int_operand" "n"))) .
2799 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
2800 return 0 for simple right / left or left/right shift combination.
2801 return 1 for a combination of shifts with zero_extend.
2802 return 2 for a combination of shifts with an AND that needs r0.
2803 return 3 for a combination of shifts with an AND that needs an extra
2804 scratch register, when the three highmost bits of the AND mask are clear.
2805 return 4 for a combination of shifts with an AND that needs an extra
2806 scratch register, when any of the three highmost bits of the AND mask
2808 If ATTRP is set, store an initial right shift width in ATTRP[0],
2809 and the instruction length in ATTRP[1] . These values are not valid
2811 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
2812 shift_amounts for the last shift value that is to be used before the
2815 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
2817 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
2818 int left = INTVAL (left_rtx), right;
2820 int cost, best_cost = 10000;
2821 int best_right = 0, best_len = 0;
2825 if (left < 0 || left > 31)
2827 if (GET_CODE (mask_rtx) == CONST_INT)
2828 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
2830 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
2831 /* Can this be expressed as a right shift / left shift pair? */
2832 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
2833 right = exact_log2 (lsb);
2834 mask2 = ~(mask + lsb - 1);
2835 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
2836 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
2838 best_cost = shift_insns[right] + shift_insns[right + left];
2839 /* mask has no trailing zeroes <==> ! right */
2840 else if (! right && mask2 == ~(lsb2 - 1))
2842 int late_right = exact_log2 (lsb2);
2843 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
2845 /* Try to use zero extend. */
2846 if (mask2 == ~(lsb2 - 1))
2850 for (width = 8; width <= 16; width += 8)
2852 /* Can we zero-extend right away? */
2853 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
2856 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
2857 if (cost < best_cost)
2868 /* ??? Could try to put zero extend into initial right shift,
2869 or even shift a bit left before the right shift. */
2870 /* Determine value of first part of left shift, to get to the
2871 zero extend cut-off point. */
2872 first = width - exact_log2 (lsb2) + right;
2873 if (first >= 0 && right + left - first >= 0)
2875 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
2876 + ext_shift_insns[right + left - first];
2877 if (cost < best_cost)
2889 /* Try to use r0 AND pattern */
2890 for (i = 0; i <= 2; i++)
2894 if (! CONST_OK_FOR_K08 (mask >> i))
2896 cost = (i != 0) + 2 + ext_shift_insns[left + i];
2897 if (cost < best_cost)
2902 best_len = cost - 1;
2905 /* Try to use a scratch register to hold the AND operand. */
2906 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
2907 for (i = 0; i <= 2; i++)
2911 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
2912 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
2913 if (cost < best_cost)
2918 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
2924 attrp[0] = best_right;
2925 attrp[1] = best_len;
2930 /* This is used in length attributes of the unnamed instructions
2931 corresponding to shl_and_kind return values of 1 and 2. */
2933 shl_and_length (rtx insn)
2935 rtx set_src, left_rtx, mask_rtx;
2938 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2939 left_rtx = XEXP (XEXP (set_src, 0), 1);
2940 mask_rtx = XEXP (set_src, 1);
2941 shl_and_kind (left_rtx, mask_rtx, attributes);
2942 return attributes[1];
2945 /* This is used in length attribute of the and_shl_scratch instruction. */
2948 shl_and_scr_length (rtx insn)
2950 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2951 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
2952 rtx op = XEXP (set_src, 0);
2953 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
2954 op = XEXP (XEXP (op, 0), 0);
2955 return len + shift_insns[INTVAL (XEXP (op, 1))];
2958 /* Generate rtl for instructions for which shl_and_kind advised a particular
2959 method of generating them, i.e. returned zero. */
2962 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
2965 unsigned HOST_WIDE_INT mask;
2966 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
2967 int right, total_shift;
2968 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
2970 right = attributes[0];
2971 total_shift = INTVAL (left_rtx) + right;
2972 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
2979 int first = attributes[2];
2984 emit_insn ((mask << right) <= 0xff
2985 ? gen_zero_extendqisi2 (dest,
2986 gen_lowpart (QImode, source))
2987 : gen_zero_extendhisi2 (dest,
2988 gen_lowpart (HImode, source)));
2992 emit_insn (gen_movsi (dest, source));
2996 operands[2] = GEN_INT (right);
2997 gen_shifty_hi_op (LSHIFTRT, operands);
3001 operands[2] = GEN_INT (first);
3002 gen_shifty_hi_op (ASHIFT, operands);
3003 total_shift -= first;
3007 emit_insn (mask <= 0xff
3008 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3009 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3010 if (total_shift > 0)
3012 operands[2] = GEN_INT (total_shift);
3013 gen_shifty_hi_op (ASHIFT, operands);
3018 shift_gen_fun = gen_shifty_op;
3020 /* If the topmost bit that matters is set, set the topmost bits
3021 that don't matter. This way, we might be able to get a shorter
3023 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3024 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3026 /* Don't expand fine-grained when combining, because that will
3027 make the pattern fail. */
3028 if (currently_expanding_to_rtl
3029 || reload_in_progress || reload_completed)
3033 /* Cases 3 and 4 should be handled by this split
3034 only while combining */
3035 gcc_assert (kind <= 2);
3038 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3041 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3046 operands[2] = GEN_INT (total_shift);
3047 shift_gen_fun (ASHIFT, operands);
3054 if (kind != 4 && total_shift < 16)
3056 neg = -ext_shift_amounts[total_shift][1];
3058 neg -= ext_shift_amounts[total_shift][2];
3062 emit_insn (gen_and_shl_scratch (dest, source,
3065 GEN_INT (total_shift + neg),
3067 emit_insn (gen_movsi (dest, dest));
3074 /* Try to find a good way to implement the combiner pattern
3075 [(set (match_operand:SI 0 "register_operand" "=r")
3076 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3077 (match_operand:SI 2 "const_int_operand" "n")
3078 (match_operand:SI 3 "const_int_operand" "n")
3080 (clobber (reg:SI T_REG))]
3081 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3082 return 0 for simple left / right shift combination.
3083 return 1 for left shift / 8 bit sign extend / left shift.
3084 return 2 for left shift / 16 bit sign extend / left shift.
3085 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3086 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3087 return 5 for left shift / 16 bit sign extend / right shift
3088 return 6 for < 8 bit sign extend / left shift.
3089 return 7 for < 8 bit sign extend / left shift / single right shift.
3090 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3093 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3095 int left, size, insize, ext;
3096 int cost = 0, best_cost;
3099 left = INTVAL (left_rtx);
3100 size = INTVAL (size_rtx);
3101 insize = size - left;
3102 gcc_assert (insize > 0);
3103 /* Default to left / right shift. */
3105 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3108 /* 16 bit shift / sign extend / 16 bit shift */
3109 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3110 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3111 below, by alternative 3 or something even better. */
3112 if (cost < best_cost)
3118 /* Try a plain sign extend between two shifts. */
3119 for (ext = 16; ext >= insize; ext -= 8)
3123 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3124 if (cost < best_cost)
3126 kind = ext / (unsigned) 8;
3130 /* Check if we can do a sloppy shift with a final signed shift
3131 restoring the sign. */
3132 if (EXT_SHIFT_SIGNED (size - ext))
3133 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3134 /* If not, maybe it's still cheaper to do the second shift sloppy,
3135 and do a final sign extend? */
3136 else if (size <= 16)
3137 cost = ext_shift_insns[ext - insize] + 1
3138 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3141 if (cost < best_cost)
3143 kind = ext / (unsigned) 8 + 2;
3147 /* Check if we can sign extend in r0 */
3150 cost = 3 + shift_insns[left];
3151 if (cost < best_cost)
3156 /* Try the same with a final signed shift. */
3159 cost = 3 + ext_shift_insns[left + 1] + 1;
3160 if (cost < best_cost)
3169 /* Try to use a dynamic shift. */
3170 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3171 if (cost < best_cost)
3182 /* Function to be used in the length attribute of the instructions
3183 implementing this pattern. */
3186 shl_sext_length (rtx insn)
3188 rtx set_src, left_rtx, size_rtx;
3191 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3192 left_rtx = XEXP (XEXP (set_src, 0), 1);
3193 size_rtx = XEXP (set_src, 1);
3194 shl_sext_kind (left_rtx, size_rtx, &cost);
3198 /* Generate rtl for this pattern */
3201 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3204 int left, size, insize, cost;
3207 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3208 left = INTVAL (left_rtx);
3209 size = INTVAL (size_rtx);
3210 insize = size - left;
3218 int ext = kind & 1 ? 8 : 16;
3219 int shift2 = size - ext;
3221 /* Don't expand fine-grained when combining, because that will
3222 make the pattern fail. */
3223 if (! currently_expanding_to_rtl
3224 && ! reload_in_progress && ! reload_completed)
3226 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3227 emit_insn (gen_movsi (dest, source));
3231 emit_insn (gen_movsi (dest, source));
3235 operands[2] = GEN_INT (ext - insize);
3236 gen_shifty_hi_op (ASHIFT, operands);
3239 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3240 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3245 operands[2] = GEN_INT (shift2);
3246 gen_shifty_op (ASHIFT, operands);
3253 if (EXT_SHIFT_SIGNED (shift2))
3255 operands[2] = GEN_INT (shift2 + 1);
3256 gen_shifty_op (ASHIFT, operands);
3257 operands[2] = const1_rtx;
3258 gen_shifty_op (ASHIFTRT, operands);
3261 operands[2] = GEN_INT (shift2);
3262 gen_shifty_hi_op (ASHIFT, operands);
3266 operands[2] = GEN_INT (-shift2);
3267 gen_shifty_hi_op (LSHIFTRT, operands);
3269 emit_insn (size <= 8
3270 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3271 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3278 if (! currently_expanding_to_rtl
3279 && ! reload_in_progress && ! reload_completed)
3280 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3284 operands[2] = GEN_INT (16 - insize);
3285 gen_shifty_hi_op (ASHIFT, operands);
3286 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3288 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3290 gen_ashift (ASHIFTRT, 1, dest);
3295 /* Don't expand fine-grained when combining, because that will
3296 make the pattern fail. */
3297 if (! currently_expanding_to_rtl
3298 && ! reload_in_progress && ! reload_completed)
3300 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3301 emit_insn (gen_movsi (dest, source));
3304 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3305 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3306 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3308 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3309 gen_shifty_op (ASHIFT, operands);
3311 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3319 /* Prefix a symbol_ref name with "datalabel". */
3322 gen_datalabel_ref (rtx sym)
3326 if (GET_CODE (sym) == LABEL_REF)
3327 return gen_rtx_CONST (GET_MODE (sym),
3328 gen_rtx_UNSPEC (GET_MODE (sym),
3332 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3334 str = XSTR (sym, 0);
3335 /* Share all SYMBOL_REF strings with the same value - that is important
3337 str = IDENTIFIER_POINTER (get_identifier (str));
3338 XSTR (sym, 0) = str;
3344 static alloc_pool label_ref_list_pool;
3346 typedef struct label_ref_list_d
3349 struct label_ref_list_d *next;
3350 } *label_ref_list_t;
3352 /* The SH cannot load a large constant into a register, constants have to
3353 come from a pc relative load. The reference of a pc relative load
3354 instruction must be less than 1k in front of the instruction. This
3355 means that we often have to dump a constant inside a function, and
3356 generate code to branch around it.
3358 It is important to minimize this, since the branches will slow things
3359 down and make things bigger.
3361 Worst case code looks like:
3379 We fix this by performing a scan before scheduling, which notices which
3380 instructions need to have their operands fetched from the constant table
3381 and builds the table.
3385 scan, find an instruction which needs a pcrel move. Look forward, find the
3386 last barrier which is within MAX_COUNT bytes of the requirement.
3387 If there isn't one, make one. Process all the instructions between
3388 the find and the barrier.
3390 In the above example, we can tell that L3 is within 1k of L1, so
3391 the first move can be shrunk from the 3 insn+constant sequence into
3392 just 1 insn, and the constant moved to L3 to make:
3403 Then the second move becomes the target for the shortening process. */
3407 rtx value; /* Value in table. */
3408 rtx label; /* Label of value. */
3409 label_ref_list_t wend; /* End of window. */
3410 enum machine_mode mode; /* Mode of value. */
3412 /* True if this constant is accessed as part of a post-increment
3413 sequence. Note that HImode constants are never accessed in this way. */
3414 bool part_of_sequence_p;
3417 /* The maximum number of constants that can fit into one pool, since
3418 constants in the range 0..510 are at least 2 bytes long, and in the
3419 range from there to 1018 at least 4 bytes. */
3421 #define MAX_POOL_SIZE 372
3422 static pool_node pool_vector[MAX_POOL_SIZE];
3423 static int pool_size;
3424 static rtx pool_window_label;
3425 static int pool_window_last;
3427 static int max_labelno_before_reorg;
3429 /* ??? If we need a constant in HImode which is the truncated value of a
3430 constant we need in SImode, we could combine the two entries thus saving
3431 two bytes. Is this common enough to be worth the effort of implementing
3434 /* ??? This stuff should be done at the same time that we shorten branches.
3435 As it is now, we must assume that all branches are the maximum size, and
3436 this causes us to almost always output constant pools sooner than
3439 /* Add a constant to the pool and return its label. */
3442 add_constant (rtx x, enum machine_mode mode, rtx last_value)
3446 label_ref_list_t ref, newref;
3448 /* First see if we've already got it. */
3449 for (i = 0; i < pool_size; i++)
3451 if (x->code == pool_vector[i].value->code
3452 && mode == pool_vector[i].mode)
3454 if (x->code == CODE_LABEL)
3456 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3459 if (rtx_equal_p (x, pool_vector[i].value))
3464 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3466 new = gen_label_rtx ();
3467 LABEL_REFS (new) = pool_vector[i].label;
3468 pool_vector[i].label = lab = new;
3470 if (lab && pool_window_label)
3472 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3473 newref->label = pool_window_label;
3474 ref = pool_vector[pool_window_last].wend;
3476 pool_vector[pool_window_last].wend = newref;
3479 pool_window_label = new;
3480 pool_window_last = i;
3486 /* Need a new one. */
3487 pool_vector[pool_size].value = x;
3488 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3491 pool_vector[pool_size - 1].part_of_sequence_p = true;
3494 lab = gen_label_rtx ();
3495 pool_vector[pool_size].mode = mode;
3496 pool_vector[pool_size].label = lab;
3497 pool_vector[pool_size].wend = NULL;
3498 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
3499 if (lab && pool_window_label)
3501 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3502 newref->label = pool_window_label;
3503 ref = pool_vector[pool_window_last].wend;
3505 pool_vector[pool_window_last].wend = newref;
3508 pool_window_label = lab;
3509 pool_window_last = pool_size;
3514 /* Output the literal table. START, if nonzero, is the first instruction
3515 this table is needed for, and also indicates that there is at least one
3516 casesi_worker_2 instruction; We have to emit the operand3 labels from
3517 these insns at a 4-byte aligned position. BARRIER is the barrier
3518 after which we are to place the table. */
3521 dump_table (rtx start, rtx barrier)
3527 label_ref_list_t ref;
3530 /* Do two passes, first time dump out the HI sized constants. */
3532 for (i = 0; i < pool_size; i++)
3534 pool_node *p = &pool_vector[i];
3536 if (p->mode == HImode)
3540 scan = emit_insn_after (gen_align_2 (), scan);
3543 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3544 scan = emit_label_after (lab, scan);
3545 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
3547 for (ref = p->wend; ref; ref = ref->next)
3550 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3553 else if (p->mode == DFmode)
3561 scan = emit_insn_after (gen_align_4 (), scan);
3563 for (; start != barrier; start = NEXT_INSN (start))
3564 if (GET_CODE (start) == INSN
3565 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
3567 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
3568 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
3570 scan = emit_label_after (lab, scan);
3573 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
3575 rtx align_insn = NULL_RTX;
3577 scan = emit_label_after (gen_label_rtx (), scan);
3578 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3581 for (i = 0; i < pool_size; i++)
3583 pool_node *p = &pool_vector[i];
3591 if (align_insn && !p->part_of_sequence_p)
3593 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3594 emit_label_before (lab, align_insn);
3595 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
3597 for (ref = p->wend; ref; ref = ref->next)
3600 emit_insn_before (gen_consttable_window_end (lab),
3603 delete_insn (align_insn);
3604 align_insn = NULL_RTX;
3609 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3610 scan = emit_label_after (lab, scan);
3611 scan = emit_insn_after (gen_consttable_4 (p->value,
3613 need_align = ! need_align;
3619 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3624 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3625 scan = emit_label_after (lab, scan);
3626 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3633 if (p->mode != HImode)
3635 for (ref = p->wend; ref; ref = ref->next)
3638 scan = emit_insn_after (gen_consttable_window_end (lab),
3647 for (i = 0; i < pool_size; i++)
3649 pool_node *p = &pool_vector[i];
3660 scan = emit_label_after (gen_label_rtx (), scan);
3661 scan = emit_insn_after (gen_align_4 (), scan);
3663 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3664 scan = emit_label_after (lab, scan);
3665 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
3673 scan = emit_label_after (gen_label_rtx (), scan);
3674 scan = emit_insn_after (gen_align_4 (), scan);
3676 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3677 scan = emit_label_after (lab, scan);
3678 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3685 if (p->mode != HImode)
3687 for (ref = p->wend; ref; ref = ref->next)
3690 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3695 scan = emit_insn_after (gen_consttable_end (), scan);
3696 scan = emit_barrier_after (scan);
3698 pool_window_label = NULL_RTX;
3699 pool_window_last = 0;
3702 /* Return nonzero if constant would be an ok source for a
3703 mov.w instead of a mov.l. */
3708 return (GET_CODE (src) == CONST_INT
3709 && INTVAL (src) >= -32768
3710 && INTVAL (src) <= 32767);
3713 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
3715 /* Nonzero if the insn is a move instruction which needs to be fixed. */
3717 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
3718 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
3719 need to fix it if the input value is CONST_OK_FOR_I08. */
3722 broken_move (rtx insn)
3724 if (GET_CODE (insn) == INSN)
3726 rtx pat = PATTERN (insn);
3727 if (GET_CODE (pat) == PARALLEL)
3728 pat = XVECEXP (pat, 0, 0);
3729 if (GET_CODE (pat) == SET
3730 /* We can load any 8-bit value if we don't care what the high
3731 order bits end up as. */
3732 && GET_MODE (SET_DEST (pat)) != QImode
3733 && (CONSTANT_P (SET_SRC (pat))
3734 /* Match mova_const. */
3735 || (GET_CODE (SET_SRC (pat)) == UNSPEC
3736 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
3737 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
3739 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
3740 && (fp_zero_operand (SET_SRC (pat))
3741 || fp_one_operand (SET_SRC (pat)))
3742 /* ??? If this is a -m4 or -m4-single compilation, in general
3743 we don't know the current setting of fpscr, so disable fldi.
3744 There is an exception if this was a register-register move
3745 before reload - and hence it was ascertained that we have
3746 single precision setting - and in a post-reload optimization
3747 we changed this to do a constant load. In that case
3748 we don't have an r0 clobber, hence we must use fldi. */
3749 && (! TARGET_SH4 || TARGET_FMOVD
3750 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
3752 && GET_CODE (SET_DEST (pat)) == REG
3753 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
3755 && GET_MODE (SET_DEST (pat)) == SImode
3756 && (satisfies_constraint_I20 (SET_SRC (pat))
3757 || satisfies_constraint_I28 (SET_SRC (pat))))
3758 && ! satisfies_constraint_I08 (SET_SRC (pat)))
3768 return (GET_CODE (insn) == INSN
3769 && GET_CODE (PATTERN (insn)) == SET
3770 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
3771 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
3772 /* Don't match mova_const. */
3773 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
3776 /* Fix up a mova from a switch that went out of range. */
3778 fixup_mova (rtx mova)
3780 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
3783 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
3784 INSN_CODE (mova) = -1;
3789 rtx lab = gen_label_rtx ();
3790 rtx wpat, wpat0, wpat1, wsrc, diff;
3794 worker = NEXT_INSN (worker);
3796 && GET_CODE (worker) != CODE_LABEL
3797 && GET_CODE (worker) != JUMP_INSN);
3798 } while (GET_CODE (worker) == NOTE
3799 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
3800 wpat = PATTERN (worker);
3801 wpat0 = XVECEXP (wpat, 0, 0);
3802 wpat1 = XVECEXP (wpat, 0, 1);
3803 wsrc = SET_SRC (wpat0);
3804 PATTERN (worker) = (gen_casesi_worker_2
3805 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
3806 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
3808 INSN_CODE (worker) = -1;
3809 diff = gen_rtx_MINUS (Pmode, XVECEXP (SET_SRC (PATTERN (mova)), 0, 0),
3810 gen_rtx_LABEL_REF (Pmode, lab));
3811 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, diff), UNSPEC_PIC);
3812 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
3813 INSN_CODE (mova) = -1;
3817 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
3818 *num_mova, and check if the new mova is not nested within the first one.
3819 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
3820 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
3822 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
3824 int n_addr = 0; /* Initialization to shut up spurious warning. */
3825 int f_target, n_target = 0; /* Likewise. */
3829 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
3830 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
3831 if (n_addr > n_target || n_addr + 1022 < n_target)
3833 /* Change the mova into a load.
3834 broken_move will then return true for it. */
3835 fixup_mova (new_mova);
3841 *first_mova = new_mova;
3846 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
3851 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
3852 > n_target - n_addr)
3854 fixup_mova (*first_mova);
3859 fixup_mova (new_mova);
3864 /* Find the last barrier from insn FROM which is close enough to hold the
3865 constant pool. If we can't find one, then create one near the end of
3869 find_barrier (int num_mova, rtx mova, rtx from)
3878 int leading_mova = num_mova;
3879 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
3884 /* For HImode: range is 510, add 4 because pc counts from address of
3885 second instruction after this one, subtract 2 for the jump instruction
3886 that we may need to emit before the table, subtract 2 for the instruction
3887 that fills the jump delay slot (in very rare cases, reorg will take an
3888 instruction from after the constant pool or will leave the delay slot
3889 empty). This gives 510.
3890 For SImode: range is 1020, add 4 because pc counts from address of
3891 second instruction after this one, subtract 2 in case pc is 2 byte
3892 aligned, subtract 2 for the jump instruction that we may need to emit
3893 before the table, subtract 2 for the instruction that fills the jump
3894 delay slot. This gives 1018. */
3896 /* The branch will always be shortened now that the reference address for
3897 forward branches is the successor address, thus we need no longer make
3898 adjustments to the [sh]i_limit for -O0. */
3903 while (from && count_si < si_limit && count_hi < hi_limit)
3905 int inc = get_attr_length (from);
3908 /* If this is a label that existed at the time of the compute_alignments
3909 call, determine the alignment. N.B. When find_barrier recurses for
3910 an out-of-reach mova, we might see labels at the start of previously
3911 inserted constant tables. */
3912 if (GET_CODE (from) == CODE_LABEL
3913 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
3916 new_align = 1 << label_to_alignment (from);
3917 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
3918 new_align = 1 << barrier_align (from);
3923 /* In case we are scanning a constant table because of recursion, check
3924 for explicit alignments. If the table is long, we might be forced
3925 to emit the new table in front of it; the length of the alignment
3926 might be the last straw. */
3927 else if (GET_CODE (from) == INSN
3928 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
3929 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
3930 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
3931 /* When we find the end of a constant table, paste the new constant
3932 at the end. That is better than putting it in front because
3933 this way, we don't need extra alignment for adding a 4-byte-aligned
3934 mov(a) label to a 2/4 or 8/4 byte aligned table. */
3935 else if (GET_CODE (from) == INSN
3936 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
3937 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
3940 if (GET_CODE (from) == BARRIER)
3944 found_barrier = from;
3946 /* If we are at the end of the function, or in front of an alignment
3947 instruction, we need not insert an extra alignment. We prefer
3948 this kind of barrier. */
3949 if (barrier_align (from) > 2)
3950 good_barrier = from;
3952 /* If we are at the end of a hot/cold block, dump the constants
3954 next = NEXT_INSN (from);
3957 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
3961 if (broken_move (from))
3964 enum machine_mode mode;
3966 pat = PATTERN (from);
3967 if (GET_CODE (pat) == PARALLEL)
3968 pat = XVECEXP (pat, 0, 0);
3969 src = SET_SRC (pat);
3970 dst = SET_DEST (pat);
3971 mode = GET_MODE (dst);
3973 /* We must explicitly check the mode, because sometimes the
3974 front end will generate code to load unsigned constants into
3975 HImode targets without properly sign extending them. */
3977 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
3980 /* We put the short constants before the long constants, so
3981 we must count the length of short constants in the range
3982 for the long constants. */
3983 /* ??? This isn't optimal, but is easy to do. */
3988 /* We dump DF/DI constants before SF/SI ones, because
3989 the limit is the same, but the alignment requirements
3990 are higher. We may waste up to 4 additional bytes
3991 for alignment, and the DF/DI constant may have
3992 another SF/SI constant placed before it. */
3993 if (TARGET_SHCOMPACT
3995 && (mode == DFmode || mode == DImode))
4000 while (si_align > 2 && found_si + si_align - 2 > count_si)
4002 if (found_si > count_si)
4003 count_si = found_si;
4004 found_si += GET_MODE_SIZE (mode);
4006 si_limit -= GET_MODE_SIZE (mode);
4012 switch (untangle_mova (&num_mova, &mova, from))
4014 case 0: return find_barrier (0, 0, mova);
4019 = good_barrier ? good_barrier : found_barrier;
4023 if (found_si > count_si)
4024 count_si = found_si;
4026 else if (GET_CODE (from) == JUMP_INSN
4027 && (GET_CODE (PATTERN (from)) == ADDR_VEC
4028 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
4030 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4032 && (prev_nonnote_insn (from)
4033 == XEXP (MOVA_LABELREF (mova), 0))))
4035 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4037 /* We have just passed the barrier in front of the
4038 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4039 the ADDR_DIFF_VEC is accessed as data, just like our pool
4040 constants, this is a good opportunity to accommodate what
4041 we have gathered so far.
4042 If we waited any longer, we could end up at a barrier in
4043 front of code, which gives worse cache usage for separated
4044 instruction / data caches. */
4045 good_barrier = found_barrier;
4050 rtx body = PATTERN (from);
4051 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4054 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4055 else if (GET_CODE (from) == JUMP_INSN
4057 && ! TARGET_SMALLCODE)
4063 if (new_align > si_align)
4065 si_limit -= (count_si - 1) & (new_align - si_align);
4066 si_align = new_align;
4068 count_si = (count_si + new_align - 1) & -new_align;
4073 if (new_align > hi_align)
4075 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4076 hi_align = new_align;
4078 count_hi = (count_hi + new_align - 1) & -new_align;
4080 from = NEXT_INSN (from);
4087 /* Try as we might, the leading mova is out of range. Change
4088 it into a load (which will become a pcload) and retry. */
4090 return find_barrier (0, 0, mova);
4094 /* Insert the constant pool table before the mova instruction,
4095 to prevent the mova label reference from going out of range. */
4097 good_barrier = found_barrier = barrier_before_mova;
4103 if (good_barrier && next_real_insn (found_barrier))
4104 found_barrier = good_barrier;
4108 /* We didn't find a barrier in time to dump our stuff,
4109 so we'll make one. */
4110 rtx label = gen_label_rtx ();
4112 /* If we exceeded the range, then we must back up over the last
4113 instruction we looked at. Otherwise, we just need to undo the
4114 NEXT_INSN at the end of the loop. */
4115 if (PREV_INSN (from) != orig
4116 && (count_hi > hi_limit || count_si > si_limit))
4117 from = PREV_INSN (PREV_INSN (from));
4119 from = PREV_INSN (from);
4121 /* Walk back to be just before any jump or label.
4122 Putting it before a label reduces the number of times the branch
4123 around the constant pool table will be hit. Putting it before
4124 a jump makes it more likely that the bra delay slot will be
4126 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
4127 || GET_CODE (from) == CODE_LABEL)
4128 from = PREV_INSN (from);
4130 from = emit_jump_insn_after (gen_jump (label), from);
4131 JUMP_LABEL (from) = label;
4132 LABEL_NUSES (label) = 1;
4133 found_barrier = emit_barrier_after (from);
4134 emit_label_after (label, found_barrier);
4137 return found_barrier;
4140 /* If the instruction INSN is implemented by a special function, and we can
4141 positively find the register that is used to call the sfunc, and this
4142 register is not used anywhere else in this instruction - except as the
4143 destination of a set, return this register; else, return 0. */
4145 sfunc_uses_reg (rtx insn)
4148 rtx pattern, part, reg_part, reg;
4150 if (GET_CODE (insn) != INSN)
4152 pattern = PATTERN (insn);
4153 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4156 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4158 part = XVECEXP (pattern, 0, i);
4159 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4164 reg = XEXP (reg_part, 0);
4165 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4167 part = XVECEXP (pattern, 0, i);
4168 if (part == reg_part || GET_CODE (part) == CLOBBER)
4170 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4171 && GET_CODE (SET_DEST (part)) == REG)
4172 ? SET_SRC (part) : part)))
4178 /* See if the only way in which INSN uses REG is by calling it, or by
4179 setting it while calling it. Set *SET to a SET rtx if the register
4183 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4189 reg2 = sfunc_uses_reg (insn);
4190 if (reg2 && REGNO (reg2) == REGNO (reg))
4192 pattern = single_set (insn);
4194 && GET_CODE (SET_DEST (pattern)) == REG
4195 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4199 if (GET_CODE (insn) != CALL_INSN)
4201 /* We don't use rtx_equal_p because we don't care if the mode is
4203 pattern = single_set (insn);
4205 && GET_CODE (SET_DEST (pattern)) == REG
4206 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4212 par = PATTERN (insn);
4213 if (GET_CODE (par) == PARALLEL)
4214 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4216 part = XVECEXP (par, 0, i);
4217 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4220 return reg_mentioned_p (reg, SET_SRC (pattern));
4226 pattern = PATTERN (insn);
4228 if (GET_CODE (pattern) == PARALLEL)
4232 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4233 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4235 pattern = XVECEXP (pattern, 0, 0);
4238 if (GET_CODE (pattern) == SET)
4240 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4242 /* We don't use rtx_equal_p, because we don't care if the
4243 mode is different. */
4244 if (GET_CODE (SET_DEST (pattern)) != REG
4245 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4251 pattern = SET_SRC (pattern);
4254 if (GET_CODE (pattern) != CALL
4255 || GET_CODE (XEXP (pattern, 0)) != MEM
4256 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4262 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4263 general registers. Bits 0..15 mean that the respective registers
4264 are used as inputs in the instruction. Bits 16..31 mean that the
4265 registers 0..15, respectively, are used as outputs, or are clobbered.
4266 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4268 regs_used (rtx x, int is_dest)
4276 code = GET_CODE (x);
4281 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4282 << (REGNO (x) + is_dest));
4286 rtx y = SUBREG_REG (x);
4288 if (GET_CODE (y) != REG)
4291 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4293 subreg_regno_offset (REGNO (y),
4296 GET_MODE (x)) + is_dest));
4300 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4302 /* If there was a return value, it must have been indicated with USE. */
4317 fmt = GET_RTX_FORMAT (code);
4319 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4324 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4325 used |= regs_used (XVECEXP (x, i, j), is_dest);
4327 else if (fmt[i] == 'e')
4328 used |= regs_used (XEXP (x, i), is_dest);
4333 /* Create an instruction that prevents redirection of a conditional branch
4334 to the destination of the JUMP with address ADDR.
4335 If the branch needs to be implemented as an indirect jump, try to find
4336 a scratch register for it.
4337 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4338 If any preceding insn that doesn't fit into a delay slot is good enough,
4339 pass 1. Pass 2 if a definite blocking insn is needed.
4340 -1 is used internally to avoid deep recursion.
4341 If a blocking instruction is made or recognized, return it. */
4344 gen_block_redirect (rtx jump, int addr, int need_block)
4347 rtx prev = prev_nonnote_insn (jump);
4350 /* First, check if we already have an instruction that satisfies our need. */
4351 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
4353 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4355 if (GET_CODE (PATTERN (prev)) == USE
4356 || GET_CODE (PATTERN (prev)) == CLOBBER
4357 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4359 else if ((need_block &= ~1) < 0)
4361 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4364 if (GET_CODE (PATTERN (jump)) == RETURN)
4368 /* Reorg even does nasty things with return insns that cause branches
4369 to go out of range - see find_end_label and callers. */
4370 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4372 /* We can't use JUMP_LABEL here because it might be undefined
4373 when not optimizing. */
4374 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4375 /* If the branch is out of range, try to find a scratch register for it. */
4377 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4381 /* Don't look for the stack pointer as a scratch register,
4382 it would cause trouble if an interrupt occurred. */
4383 unsigned try = 0x7fff, used;
4384 int jump_left = flag_expensive_optimizations + 1;
4386 /* It is likely that the most recent eligible instruction is wanted for
4387 the delay slot. Therefore, find out which registers it uses, and
4388 try to avoid using them. */
4390 for (scan = jump; (scan = PREV_INSN (scan)); )
4394 if (INSN_DELETED_P (scan))
4396 code = GET_CODE (scan);
4397 if (code == CODE_LABEL || code == JUMP_INSN)
4400 && GET_CODE (PATTERN (scan)) != USE
4401 && GET_CODE (PATTERN (scan)) != CLOBBER
4402 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4404 try &= ~regs_used (PATTERN (scan), 0);
4408 for (used = dead = 0, scan = JUMP_LABEL (jump);
4409 (scan = NEXT_INSN (scan)); )
4413 if (INSN_DELETED_P (scan))
4415 code = GET_CODE (scan);
4418 used |= regs_used (PATTERN (scan), 0);
4419 if (code == CALL_INSN)
4420 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4421 dead |= (used >> 16) & ~used;
4427 if (code == JUMP_INSN)
4429 if (jump_left-- && simplejump_p (scan))
4430 scan = JUMP_LABEL (scan);
4436 /* Mask out the stack pointer again, in case it was
4437 the only 'free' register we have found. */
4440 /* If the immediate destination is still in range, check for possible
4441 threading with a jump beyond the delay slot insn.
4442 Don't check if we are called recursively; the jump has been or will be
4443 checked in a different invocation then. */
4445 else if (optimize && need_block >= 0)
4447 rtx next = next_active_insn (next_active_insn (dest));
4448 if (next && GET_CODE (next) == JUMP_INSN
4449 && GET_CODE (PATTERN (next)) == SET
4450 && recog_memoized (next) == CODE_FOR_jump_compact)
4452 dest = JUMP_LABEL (next);
4454 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4456 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
4462 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
4464 /* It would be nice if we could convert the jump into an indirect
4465 jump / far branch right now, and thus exposing all constituent
4466 instructions to further optimization. However, reorg uses
4467 simplejump_p to determine if there is an unconditional jump where
4468 it should try to schedule instructions from the target of the
4469 branch; simplejump_p fails for indirect jumps even if they have
4471 rtx insn = emit_insn_before (gen_indirect_jump_scratch
4472 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
4474 /* ??? We would like this to have the scope of the jump, but that
4475 scope will change when a delay slot insn of an inner scope is added.
4476 Hence, after delay slot scheduling, we'll have to expect
4477 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
4480 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
4481 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
4484 else if (need_block)
4485 /* We can't use JUMP_LABEL here because it might be undefined
4486 when not optimizing. */
4487 return emit_insn_before (gen_block_branch_redirect
4488 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
4493 #define CONDJUMP_MIN -252
4494 #define CONDJUMP_MAX 262
4497 /* A label (to be placed) in front of the jump
4498 that jumps to our ultimate destination. */
4500 /* Where we are going to insert it if we cannot move the jump any farther,
4501 or the jump itself if we have picked up an existing jump. */
4503 /* The ultimate destination. */
4505 struct far_branch *prev;
4506 /* If the branch has already been created, its address;
4507 else the address of its first prospective user. */
4511 static void gen_far_branch (struct far_branch *);
4512 enum mdep_reorg_phase_e mdep_reorg_phase;
4514 gen_far_branch (struct far_branch *bp)
4516 rtx insn = bp->insert_place;
4518 rtx label = gen_label_rtx ();
4521 emit_label_after (label, insn);
4524 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
4525 LABEL_NUSES (bp->far_label)++;
4528 jump = emit_jump_insn_after (gen_return (), insn);
4529 /* Emit a barrier so that reorg knows that any following instructions
4530 are not reachable via a fall-through path.
4531 But don't do this when not optimizing, since we wouldn't suppress the
4532 alignment for the barrier then, and could end up with out-of-range
4533 pc-relative loads. */
4535 emit_barrier_after (jump);
4536 emit_label_after (bp->near_label, insn);
4537 JUMP_LABEL (jump) = bp->far_label;
4538 ok = invert_jump (insn, label, 1);
4541 /* If we are branching around a jump (rather than a return), prevent
4542 reorg from using an insn from the jump target as the delay slot insn -
4543 when reorg did this, it pessimized code (we rather hide the delay slot)
4544 and it could cause branches to go out of range. */
4547 (gen_stuff_delay_slot
4548 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
4549 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
4551 /* Prevent reorg from undoing our splits. */
4552 gen_block_redirect (jump, bp->address += 2, 2);
4555 /* Fix up ADDR_DIFF_VECs. */
4557 fixup_addr_diff_vecs (rtx first)
4561 for (insn = first; insn; insn = NEXT_INSN (insn))
4563 rtx vec_lab, pat, prev, prevpat, x, braf_label;
4565 if (GET_CODE (insn) != JUMP_INSN
4566 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
4568 pat = PATTERN (insn);
4569 vec_lab = XEXP (XEXP (pat, 0), 0);
4571 /* Search the matching casesi_jump_2. */
4572 for (prev = vec_lab; ; prev = PREV_INSN (prev))
4574 if (GET_CODE (prev) != JUMP_INSN)
4576 prevpat = PATTERN (prev);
4577 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
4579 x = XVECEXP (prevpat, 0, 1);
4580 if (GET_CODE (x) != USE)
4583 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
4586 /* FIXME: This is a bug in the optimizer, but it seems harmless
4587 to just avoid panicing. */
4591 /* Emit the reference label of the braf where it belongs, right after
4592 the casesi_jump_2 (i.e. braf). */
4593 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
4594 emit_label_after (braf_label, prev);
4596 /* Fix up the ADDR_DIF_VEC to be relative
4597 to the reference address of the braf. */
4598 XEXP (XEXP (pat, 0), 0) = braf_label;
4602 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
4603 a barrier. Return the base 2 logarithm of the desired alignment. */
4605 barrier_align (rtx barrier_or_label)
4607 rtx next = next_real_insn (barrier_or_label), pat, prev;
4608 int slot, credit, jump_to_next = 0;
4613 pat = PATTERN (next);
4615 if (GET_CODE (pat) == ADDR_DIFF_VEC)
4618 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
4619 /* This is a barrier in front of a constant table. */
4622 prev = prev_real_insn (barrier_or_label);
4623 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
4625 pat = PATTERN (prev);
4626 /* If this is a very small table, we want to keep the alignment after
4627 the table to the minimum for proper code alignment. */
4628 return ((TARGET_SMALLCODE
4629 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
4630 <= (unsigned) 1 << (CACHE_LOG - 2)))
4631 ? 1 << TARGET_SHMEDIA : align_jumps_log);
4634 if (TARGET_SMALLCODE)
4637 if (! TARGET_SH2 || ! optimize)
4638 return align_jumps_log;
4640 /* When fixing up pcloads, a constant table might be inserted just before
4641 the basic block that ends with the barrier. Thus, we can't trust the
4642 instruction lengths before that. */
4643 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
4645 /* Check if there is an immediately preceding branch to the insn beyond
4646 the barrier. We must weight the cost of discarding useful information
4647 from the current cache line when executing this branch and there is
4648 an alignment, against that of fetching unneeded insn in front of the
4649 branch target when there is no alignment. */
4651 /* There are two delay_slot cases to consider. One is the simple case
4652 where the preceding branch is to the insn beyond the barrier (simple
4653 delay slot filling), and the other is where the preceding branch has
4654 a delay slot that is a duplicate of the insn after the barrier
4655 (fill_eager_delay_slots) and the branch is to the insn after the insn
4656 after the barrier. */
4658 /* PREV is presumed to be the JUMP_INSN for the barrier under
4659 investigation. Skip to the insn before it. */
4660 prev = prev_real_insn (prev);
4662 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
4663 credit >= 0 && prev && GET_CODE (prev) == INSN;
4664 prev = prev_real_insn (prev))
4667 if (GET_CODE (PATTERN (prev)) == USE
4668 || GET_CODE (PATTERN (prev)) == CLOBBER)
4670 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
4672 prev = XVECEXP (PATTERN (prev), 0, 1);
4673 if (INSN_UID (prev) == INSN_UID (next))
4675 /* Delay slot was filled with insn at jump target. */
4682 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4684 credit -= get_attr_length (prev);
4687 && GET_CODE (prev) == JUMP_INSN
4688 && JUMP_LABEL (prev))
4692 || next_real_insn (JUMP_LABEL (prev)) == next
4693 /* If relax_delay_slots() decides NEXT was redundant
4694 with some previous instruction, it will have
4695 redirected PREV's jump to the following insn. */
4696 || JUMP_LABEL (prev) == next_nonnote_insn (next)
4697 /* There is no upper bound on redundant instructions
4698 that might have been skipped, but we must not put an
4699 alignment where none had been before. */
4700 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
4702 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
4703 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
4704 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
4706 rtx pat = PATTERN (prev);
4707 if (GET_CODE (pat) == PARALLEL)
4708 pat = XVECEXP (pat, 0, 0);
4709 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
4715 return align_jumps_log;
4718 /* If we are inside a phony loop, almost any kind of label can turn up as the
4719 first one in the loop. Aligning a braf label causes incorrect switch
4720 destination addresses; we can detect braf labels because they are
4721 followed by a BARRIER.
4722 Applying loop alignment to small constant or switch tables is a waste
4723 of space, so we suppress this too. */
4725 sh_loop_align (rtx label)
4730 next = next_nonnote_insn (next);
4731 while (next && GET_CODE (next) == CODE_LABEL);
4735 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
4736 || recog_memoized (next) == CODE_FOR_consttable_2)
4739 return align_loops_log;
4742 /* Do a final pass over the function, just before delayed branch
4748 rtx first, insn, mova = NULL_RTX;
4750 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
4751 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
4753 first = get_insns ();
4754 max_labelno_before_reorg = max_label_num ();
4756 /* We must split call insns before introducing `mova's. If we're
4757 optimizing, they'll have already been split. Otherwise, make
4758 sure we don't split them too late. */
4760 split_all_insns_noflow ();
4765 /* If relaxing, generate pseudo-ops to associate function calls with
4766 the symbols they call. It does no harm to not generate these
4767 pseudo-ops. However, when we can generate them, it enables to
4768 linker to potentially relax the jsr to a bsr, and eliminate the
4769 register load and, possibly, the constant pool entry. */
4771 mdep_reorg_phase = SH_INSERT_USES_LABELS;
4774 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
4775 own purposes. This works because none of the remaining passes
4776 need to look at them.
4778 ??? But it may break in the future. We should use a machine
4779 dependent REG_NOTE, or some other approach entirely. */
4780 for (insn = first; insn; insn = NEXT_INSN (insn))
4786 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
4788 remove_note (insn, note);
4792 for (insn = first; insn; insn = NEXT_INSN (insn))
4794 rtx pattern, reg, link, set, scan, dies, label;
4795 int rescan = 0, foundinsn = 0;
4797 if (GET_CODE (insn) == CALL_INSN)
4799 pattern = PATTERN (insn);
4801 if (GET_CODE (pattern) == PARALLEL)
4802 pattern = XVECEXP (pattern, 0, 0);
4803 if (GET_CODE (pattern) == SET)
4804 pattern = SET_SRC (pattern);
4806 if (GET_CODE (pattern) != CALL
4807 || GET_CODE (XEXP (pattern, 0)) != MEM)
4810 reg = XEXP (XEXP (pattern, 0), 0);
4814 reg = sfunc_uses_reg (insn);
4819 if (GET_CODE (reg) != REG)
4822 /* Try scanning backward to find where the register is set. */
4824 for (scan = PREV_INSN (insn);
4825 scan && GET_CODE (scan) != CODE_LABEL;
4826 scan = PREV_INSN (scan))
4828 if (! INSN_P (scan))
4831 if (! reg_mentioned_p (reg, scan))
4834 if (noncall_uses_reg (reg, scan, &set))
4847 /* The register is set at LINK. */
4849 /* We can only optimize the function call if the register is
4850 being set to a symbol. In theory, we could sometimes
4851 optimize calls to a constant location, but the assembler
4852 and linker do not support that at present. */
4853 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
4854 && GET_CODE (SET_SRC (set)) != LABEL_REF)
4857 /* Scan forward from LINK to the place where REG dies, and
4858 make sure that the only insns which use REG are
4859 themselves function calls. */
4861 /* ??? This doesn't work for call targets that were allocated
4862 by reload, since there may not be a REG_DEAD note for the
4866 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
4870 /* Don't try to trace forward past a CODE_LABEL if we haven't
4871 seen INSN yet. Ordinarily, we will only find the setting insn
4872 if it is in the same basic block. However,
4873 cross-jumping can insert code labels in between the load and
4874 the call, and can result in situations where a single call
4875 insn may have two targets depending on where we came from. */
4877 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
4880 if (! INSN_P (scan))
4883 /* Don't try to trace forward past a JUMP. To optimize
4884 safely, we would have to check that all the
4885 instructions at the jump destination did not use REG. */
4887 if (GET_CODE (scan) == JUMP_INSN)
4890 if (! reg_mentioned_p (reg, scan))
4893 if (noncall_uses_reg (reg, scan, &scanset))
4900 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
4902 /* There is a function call to this register other
4903 than the one we are checking. If we optimize
4904 this call, we need to rescan again below. */
4908 /* ??? We shouldn't have to worry about SCANSET here.
4909 We should just be able to check for a REG_DEAD note
4910 on a function call. However, the REG_DEAD notes are
4911 apparently not dependable around libcalls; c-torture
4912 execute/920501-2 is a test case. If SCANSET is set,
4913 then this insn sets the register, so it must have
4914 died earlier. Unfortunately, this will only handle
4915 the cases in which the register is, in fact, set in a
4918 /* ??? We shouldn't have to use FOUNDINSN here.
4919 This dates back to when we used LOG_LINKS to find
4920 the most recent insn which sets the register. */
4924 || find_reg_note (scan, REG_DEAD, reg)))
4933 /* Either there was a branch, or some insn used REG
4934 other than as a function call address. */
4938 /* Create a code label, and put it in a REG_LABEL_OPERAND note
4939 on the insn which sets the register, and on each call insn
4940 which uses the register. In final_prescan_insn we look for
4941 the REG_LABEL_OPERAND notes, and output the appropriate label
4944 label = gen_label_rtx ();
4945 REG_NOTES (link) = gen_rtx_INSN_LIST (REG_LABEL_OPERAND, label,
4947 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL_OPERAND, label,
4956 scan = NEXT_INSN (scan);
4958 && ((GET_CODE (scan) == CALL_INSN
4959 && reg_mentioned_p (reg, scan))
4960 || ((reg2 = sfunc_uses_reg (scan))
4961 && REGNO (reg2) == REGNO (reg))))
4963 = gen_rtx_INSN_LIST (REG_LABEL_OPERAND, label,
4966 while (scan != dies);
4972 fixup_addr_diff_vecs (first);
4976 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
4977 shorten_branches (first);
4980 /* Scan the function looking for move instructions which have to be
4981 changed to pc-relative loads and insert the literal tables. */
4982 label_ref_list_pool = create_alloc_pool ("label references list",
4983 sizeof (struct label_ref_list_d),
4985 mdep_reorg_phase = SH_FIXUP_PCLOAD;
4986 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
4990 /* ??? basic block reordering can move a switch table dispatch
4991 below the switch table. Check if that has happened.
4992 We only have the addresses available when optimizing; but then,
4993 this check shouldn't be needed when not optimizing. */
4994 if (!untangle_mova (&num_mova, &mova, insn))
5000 else if (GET_CODE (insn) == JUMP_INSN
5001 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5003 /* ??? loop invariant motion can also move a mova out of a
5004 loop. Since loop does this code motion anyway, maybe we
5005 should wrap UNSPEC_MOVA into a CONST, so that reload can
5008 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5009 || (prev_nonnote_insn (insn)
5010 == XEXP (MOVA_LABELREF (mova), 0))))
5017 /* Some code might have been inserted between the mova and
5018 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5019 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5020 total += get_attr_length (scan);
5022 /* range of mova is 1020, add 4 because pc counts from address of
5023 second instruction after this one, subtract 2 in case pc is 2
5024 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5025 cancels out with alignment effects of the mova itself. */
5028 /* Change the mova into a load, and restart scanning
5029 there. broken_move will then return true for mova. */
5034 if (broken_move (insn)
5035 || (GET_CODE (insn) == INSN
5036 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5039 /* Scan ahead looking for a barrier to stick the constant table
5041 rtx barrier = find_barrier (num_mova, mova, insn);
5042 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5043 int need_aligned_label = 0;
5045 if (num_mova && ! mova_p (mova))
5047 /* find_barrier had to change the first mova into a
5048 pcload; thus, we have to start with this new pcload. */
5052 /* Now find all the moves between the points and modify them. */
5053 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5055 if (GET_CODE (scan) == CODE_LABEL)
5057 if (GET_CODE (scan) == INSN
5058 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5059 need_aligned_label = 1;
5060 if (broken_move (scan))
5062 rtx *patp = &PATTERN (scan), pat = *patp;
5066 enum machine_mode mode;
5068 if (GET_CODE (pat) == PARALLEL)
5069 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5070 src = SET_SRC (pat);
5071 dst = SET_DEST (pat);
5072 mode = GET_MODE (dst);
5074 if (mode == SImode && hi_const (src)
5075 && REGNO (dst) != FPUL_REG)
5080 while (GET_CODE (dst) == SUBREG)
5082 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5083 GET_MODE (SUBREG_REG (dst)),
5086 dst = SUBREG_REG (dst);
5088 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5090 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
5092 /* This must be an insn that clobbers r0. */
5093 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5094 XVECLEN (PATTERN (scan), 0)
5096 rtx clobber = *clobberp;
5098 gcc_assert (GET_CODE (clobber) == CLOBBER
5099 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5102 && reg_set_between_p (r0_rtx, last_float_move, scan))
5106 && GET_MODE_SIZE (mode) != 4
5107 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5109 lab = add_constant (src, mode, last_float);
5111 emit_insn_before (gen_mova (lab), scan);
5114 /* There will be a REG_UNUSED note for r0 on
5115 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5116 lest reorg:mark_target_live_regs will not
5117 consider r0 to be used, and we end up with delay
5118 slot insn in front of SCAN that clobbers r0. */
5120 = find_regno_note (last_float_move, REG_UNUSED, 0);
5122 /* If we are not optimizing, then there may not be
5125 PUT_MODE (note, REG_INC);
5127 *last_float_addr = r0_inc_rtx;
5129 last_float_move = scan;
5131 newsrc = gen_const_mem (mode,
5132 (((TARGET_SH4 && ! TARGET_FMOVD)
5133 || REGNO (dst) == FPUL_REG)
5136 last_float_addr = &XEXP (newsrc, 0);
5138 /* Remove the clobber of r0. */
5139 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5140 gen_rtx_SCRATCH (Pmode));
5142 /* This is a mova needing a label. Create it. */
5143 else if (GET_CODE (src) == UNSPEC
5144 && XINT (src, 1) == UNSPEC_MOVA
5145 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5147 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5148 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5149 newsrc = gen_rtx_UNSPEC (SImode,
5150 gen_rtvec (1, newsrc),
5155 lab = add_constant (src, mode, 0);
5156 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5157 newsrc = gen_const_mem (mode, newsrc);
5159 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5160 INSN_CODE (scan) = -1;
5163 dump_table (need_aligned_label ? insn : 0, barrier);
5167 free_alloc_pool (label_ref_list_pool);
5168 for (insn = first; insn; insn = NEXT_INSN (insn))
5169 PUT_MODE (insn, VOIDmode);
5171 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5172 INSN_ADDRESSES_FREE ();
5173 split_branches (first);
5175 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5176 also has an effect on the register that holds the address of the sfunc.
5177 Insert an extra dummy insn in front of each sfunc that pretends to
5178 use this register. */
5179 if (flag_delayed_branch)
5181 for (insn = first; insn; insn = NEXT_INSN (insn))
5183 rtx reg = sfunc_uses_reg (insn);
5187 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5191 /* fpscr is not actually a user variable, but we pretend it is for the
5192 sake of the previous optimization passes, since we want it handled like
5193 one. However, we don't have any debugging information for it, so turn
5194 it into a non-user variable now. */
5196 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5198 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5202 get_dest_uid (rtx label, int max_uid)
5204 rtx dest = next_real_insn (label);
5207 /* This can happen for an undefined label. */
5209 dest_uid = INSN_UID (dest);
5210 /* If this is a newly created branch redirection blocking instruction,
5211 we cannot index the branch_uid or insn_addresses arrays with its
5212 uid. But then, we won't need to, because the actual destination is
5213 the following branch. */
5214 while (dest_uid >= max_uid)
5216 dest = NEXT_INSN (dest);
5217 dest_uid = INSN_UID (dest);
5219 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
5224 /* Split condbranches that are out of range. Also add clobbers for
5225 scratch registers that are needed in far jumps.
5226 We do this before delay slot scheduling, so that it can take our
5227 newly created instructions into account. It also allows us to
5228 find branches with common targets more easily. */
5231 split_branches (rtx first)
5234 struct far_branch **uid_branch, *far_branch_list = 0;
5235 int max_uid = get_max_uid ();
5238 /* Find out which branches are out of range. */
5239 shorten_branches (first);
5241 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5242 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5244 for (insn = first; insn; insn = NEXT_INSN (insn))
5245 if (! INSN_P (insn))
5247 else if (INSN_DELETED_P (insn))
5249 /* Shorten_branches would split this instruction again,
5250 so transform it into a note. */
5251 SET_INSN_DELETED (insn);
5253 else if (GET_CODE (insn) == JUMP_INSN
5254 /* Don't mess with ADDR_DIFF_VEC */
5255 && (GET_CODE (PATTERN (insn)) == SET
5256 || GET_CODE (PATTERN (insn)) == RETURN))
5258 enum attr_type type = get_attr_type (insn);
5259 if (type == TYPE_CBRANCH)
5263 if (get_attr_length (insn) > 4)
5265 rtx src = SET_SRC (PATTERN (insn));
5266 rtx olabel = XEXP (XEXP (src, 1), 0);
5267 int addr = INSN_ADDRESSES (INSN_UID (insn));
5269 int dest_uid = get_dest_uid (olabel, max_uid);
5270 struct far_branch *bp = uid_branch[dest_uid];
5272 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5273 the label if the LABEL_NUSES count drops to zero. There is
5274 always a jump_optimize pass that sets these values, but it
5275 proceeds to delete unreferenced code, and then if not
5276 optimizing, to un-delete the deleted instructions, thus
5277 leaving labels with too low uses counts. */
5280 JUMP_LABEL (insn) = olabel;
5281 LABEL_NUSES (olabel)++;
5285 bp = (struct far_branch *) alloca (sizeof *bp);
5286 uid_branch[dest_uid] = bp;
5287 bp->prev = far_branch_list;
5288 far_branch_list = bp;
5290 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5291 LABEL_NUSES (bp->far_label)++;
5295 label = bp->near_label;
5296 if (! label && bp->address - addr >= CONDJUMP_MIN)
5298 rtx block = bp->insert_place;
5300 if (GET_CODE (PATTERN (block)) == RETURN)
5301 block = PREV_INSN (block);
5303 block = gen_block_redirect (block,
5305 label = emit_label_after (gen_label_rtx (),
5307 bp->near_label = label;
5309 else if (label && ! NEXT_INSN (label))
5311 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5312 bp->insert_place = insn;
5314 gen_far_branch (bp);
5318 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5320 bp->near_label = label = gen_label_rtx ();
5321 bp->insert_place = insn;
5324 ok = redirect_jump (insn, label, 0);
5329 /* get_attr_length (insn) == 2 */
5330 /* Check if we have a pattern where reorg wants to redirect
5331 the branch to a label from an unconditional branch that
5333 /* We can't use JUMP_LABEL here because it might be undefined
5334 when not optimizing. */
5335 /* A syntax error might cause beyond to be NULL_RTX. */
5337 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5341 && (GET_CODE (beyond) == JUMP_INSN
5342 || ((beyond = next_active_insn (beyond))
5343 && GET_CODE (beyond) == JUMP_INSN))
5344 && GET_CODE (PATTERN (beyond)) == SET
5345 && recog_memoized (beyond) == CODE_FOR_jump_compact
5347 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5348 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5350 gen_block_redirect (beyond,
5351 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5354 next = next_active_insn (insn);
5356 if ((GET_CODE (next) == JUMP_INSN
5357 || ((next = next_active_insn (next))
5358 && GET_CODE (next) == JUMP_INSN))
5359 && GET_CODE (PATTERN (next)) == SET
5360 && recog_memoized (next) == CODE_FOR_jump_compact
5362 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5363 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5365 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5367 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5369 int addr = INSN_ADDRESSES (INSN_UID (insn));
5372 struct far_branch *bp;
5374 if (type == TYPE_JUMP)
5376 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5377 dest_uid = get_dest_uid (far_label, max_uid);
5380 /* Parse errors can lead to labels outside
5382 if (! NEXT_INSN (far_label))
5387 JUMP_LABEL (insn) = far_label;
5388 LABEL_NUSES (far_label)++;
5390 redirect_jump (insn, NULL_RTX, 1);
5394 bp = uid_branch[dest_uid];
5397 bp = (struct far_branch *) alloca (sizeof *bp);
5398 uid_branch[dest_uid] = bp;
5399 bp->prev = far_branch_list;
5400 far_branch_list = bp;
5402 bp->far_label = far_label;
5404 LABEL_NUSES (far_label)++;
5406 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5407 if (addr - bp->address <= CONDJUMP_MAX)
5408 emit_label_after (bp->near_label, PREV_INSN (insn));
5411 gen_far_branch (bp);
5417 bp->insert_place = insn;
5419 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5421 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5424 /* Generate all pending far branches,
5425 and free our references to the far labels. */
5426 while (far_branch_list)
5428 if (far_branch_list->near_label
5429 && ! NEXT_INSN (far_branch_list->near_label))
5430 gen_far_branch (far_branch_list);
5432 && far_branch_list->far_label
5433 && ! --LABEL_NUSES (far_branch_list->far_label))
5434 delete_insn (far_branch_list->far_label);
5435 far_branch_list = far_branch_list->prev;
5438 /* Instruction length information is no longer valid due to the new
5439 instructions that have been generated. */
5440 init_insn_lengths ();
5443 /* Dump out instruction addresses, which is useful for debugging the
5444 constant pool table stuff.
5446 If relaxing, output the label and pseudo-ops used to link together
5447 calls and the instruction which set the registers. */
5449 /* ??? The addresses printed by this routine for insns are nonsense for
5450 insns which are inside of a sequence where none of the inner insns have
5451 variable length. This is because the second pass of shorten_branches
5452 does not bother to update them. */
5455 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
5456 int noperands ATTRIBUTE_UNUSED)
5458 if (TARGET_DUMPISIZE)
5459 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
5465 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
5470 pattern = PATTERN (insn);
5471 if (GET_CODE (pattern) == PARALLEL)
5472 pattern = XVECEXP (pattern, 0, 0);
5473 switch (GET_CODE (pattern))
5476 if (GET_CODE (SET_SRC (pattern)) != CALL
5477 && get_attr_type (insn) != TYPE_SFUNC)
5479 targetm.asm_out.internal_label
5480 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
5483 /* else FALLTHROUGH */
5485 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
5486 CODE_LABEL_NUMBER (XEXP (note, 0)));
5496 /* Dump out any constants accumulated in the final pass. These will
5500 output_jump_label_table (void)
5506 fprintf (asm_out_file, "\t.align 2\n");
5507 for (i = 0; i < pool_size; i++)
5509 pool_node *p = &pool_vector[i];
5511 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5512 CODE_LABEL_NUMBER (p->label));
5513 output_asm_insn (".long %O0", &p->value);
5521 /* A full frame looks like:
5525 [ if current_function_anonymous_args
5538 local-0 <- fp points here. */
5540 /* Number of bytes pushed for anonymous args, used to pass information
5541 between expand_prologue and expand_epilogue. */
5543 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
5544 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
5545 for an epilogue and a negative value means that it's for a sibcall
5546 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
5547 all the registers that are about to be restored, and hence dead. */
5550 output_stack_adjust (int size, rtx reg, int epilogue_p,
5551 HARD_REG_SET *live_regs_mask)
5553 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
5556 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
5558 /* This test is bogus, as output_stack_adjust is used to re-align the
5561 gcc_assert (!(size % align));
5564 if (CONST_OK_FOR_ADD (size))
5565 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
5566 /* Try to do it with two partial adjustments; however, we must make
5567 sure that the stack is properly aligned at all times, in case
5568 an interrupt occurs between the two partial adjustments. */
5569 else if (CONST_OK_FOR_ADD (size / 2 & -align)
5570 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
5572 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
5573 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
5579 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
5582 /* If TEMP is invalid, we could temporarily save a general
5583 register to MACL. However, there is currently no need
5584 to handle this case, so just die when we see it. */
5586 || current_function_interrupt
5587 || ! call_really_used_regs[temp] || fixed_regs[temp])
5589 if (temp < 0 && ! current_function_interrupt
5590 && (TARGET_SHMEDIA || epilogue_p >= 0))
5593 COPY_HARD_REG_SET (temps, call_used_reg_set);
5594 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
5598 if (current_function_return_rtx)
5600 enum machine_mode mode;
5601 mode = GET_MODE (current_function_return_rtx);
5602 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
5603 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
5605 for (i = 0; i < nreg; i++)
5606 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
5607 if (current_function_calls_eh_return)
5609 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
5610 for (i = 0; i <= 3; i++)
5611 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
5614 if (TARGET_SHMEDIA && epilogue_p < 0)
5615 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
5616 CLEAR_HARD_REG_BIT (temps, i);
5617 if (epilogue_p <= 0)
5619 for (i = FIRST_PARM_REG;
5620 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
5621 CLEAR_HARD_REG_BIT (temps, i);
5622 if (cfun->static_chain_decl != NULL)
5623 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
5625 temp = scavenge_reg (&temps);
5627 if (temp < 0 && live_regs_mask)
5631 COPY_HARD_REG_SET (temps, *live_regs_mask);
5632 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
5633 temp = scavenge_reg (&temps);
5637 rtx adj_reg, tmp_reg, mem;
5639 /* If we reached here, the most likely case is the (sibcall)
5640 epilogue for non SHmedia. Put a special push/pop sequence
5641 for such case as the last resort. This looks lengthy but
5642 would not be problem because it seems to be very
5645 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
5648 /* ??? There is still the slight possibility that r4 or
5649 r5 have been reserved as fixed registers or assigned
5650 as global registers, and they change during an
5651 interrupt. There are possible ways to handle this:
5653 - If we are adjusting the frame pointer (r14), we can do
5654 with a single temp register and an ordinary push / pop
5656 - Grab any call-used or call-saved registers (i.e. not
5657 fixed or globals) for the temps we need. We might
5658 also grab r14 if we are adjusting the stack pointer.
5659 If we can't find enough available registers, issue
5660 a diagnostic and die - the user must have reserved
5661 way too many registers.
5662 But since all this is rather unlikely to happen and
5663 would require extra testing, we just die if r4 / r5
5664 are not available. */
5665 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
5666 && !global_regs[4] && !global_regs[5]);
5668 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
5669 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
5670 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
5671 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
5672 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
5673 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5674 emit_move_insn (mem, tmp_reg);
5675 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
5676 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5677 emit_move_insn (mem, tmp_reg);
5678 emit_move_insn (reg, adj_reg);
5679 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5680 emit_move_insn (adj_reg, mem);
5681 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5682 emit_move_insn (tmp_reg, mem);
5683 /* Tell flow the insns that pop r4/r5 aren't dead. */
5684 emit_insn (gen_rtx_USE (VOIDmode, tmp_reg));
5685 emit_insn (gen_rtx_USE (VOIDmode, adj_reg));
5688 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
5690 /* If SIZE is negative, subtract the positive value.
5691 This sometimes allows a constant pool entry to be shared
5692 between prologue and epilogue code. */
5695 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
5696 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
5700 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
5701 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
5705 = (gen_rtx_EXPR_LIST
5706 (REG_FRAME_RELATED_EXPR,
5707 gen_rtx_SET (VOIDmode, reg,
5708 gen_rtx_PLUS (SImode, reg, GEN_INT (size))),
5718 RTX_FRAME_RELATED_P (x) = 1;
5722 /* Output RTL to push register RN onto the stack. */
5729 x = gen_push_fpul ();
5730 else if (rn == FPSCR_REG)
5731 x = gen_push_fpscr ();
5732 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5733 && FP_OR_XD_REGISTER_P (rn))
5735 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5737 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
5739 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5740 x = gen_push_e (gen_rtx_REG (SFmode, rn));
5742 x = gen_push (gen_rtx_REG (SImode, rn));
5746 = gen_rtx_EXPR_LIST (REG_INC,
5747 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
5751 /* Output RTL to pop register RN from the stack. */
5758 x = gen_pop_fpul ();
5759 else if (rn == FPSCR_REG)
5760 x = gen_pop_fpscr ();
5761 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5762 && FP_OR_XD_REGISTER_P (rn))
5764 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5766 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
5768 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5769 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
5771 x = gen_pop (gen_rtx_REG (SImode, rn));
5775 = gen_rtx_EXPR_LIST (REG_INC,
5776 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
5779 /* Generate code to push the regs specified in the mask. */
5782 push_regs (HARD_REG_SET *mask, int interrupt_handler)
5784 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
5787 /* Push PR last; this gives better latencies after the prologue, and
5788 candidates for the return delay slot when there are no general
5789 registers pushed. */
5790 for (; i < FIRST_PSEUDO_REGISTER; i++)
5792 /* If this is an interrupt handler, and the SZ bit varies,
5793 and we have to push any floating point register, we need
5794 to switch to the correct precision first. */
5795 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
5796 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
5798 HARD_REG_SET unsaved;
5801 COMPL_HARD_REG_SET (unsaved, *mask);
5802 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
5806 && (i != FPSCR_REG || ! skip_fpscr)
5807 && TEST_HARD_REG_BIT (*mask, i))
5809 /* If the ISR has RESBANK attribute assigned, don't push any of
5810 the following registers - R0-R14, MACH, MACL and GBR. */
5811 if (! (sh_cfun_resbank_handler_p ()
5812 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
5820 /* Push banked registers last to improve delay slot opportunities. */
5821 if (interrupt_handler)
5822 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
5823 if (TEST_HARD_REG_BIT (*mask, i))
5826 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
5827 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
5831 /* Calculate how much extra space is needed to save all callee-saved
5833 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5836 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
5839 int stack_space = 0;
5840 int interrupt_handler = sh_cfun_interrupt_handler_p ();
5842 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
5843 if ((! call_really_used_regs[reg] || interrupt_handler)
5844 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
5845 /* Leave space to save this target register on the stack,
5846 in case target register allocation wants to use it. */
5847 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5851 /* Decide whether we should reserve space for callee-save target registers,
5852 in case target register allocation wants to use them. REGS_SAVED is
5853 the space, in bytes, that is already required for register saves.
5854 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5857 shmedia_reserve_space_for_target_registers_p (int regs_saved,
5858 HARD_REG_SET *live_regs_mask)
5862 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
5865 /* Decide how much space to reserve for callee-save target registers
5866 in case target register allocation wants to use them.
5867 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5870 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
5872 if (shmedia_space_reserved_for_target_registers)
5873 return shmedia_target_regs_stack_space (live_regs_mask);
5878 /* Work out the registers which need to be saved, both as a mask and a
5879 count of saved words. Return the count.
5881 If doing a pragma interrupt function, then push all regs used by the
5882 function, and if we call another function (we can tell by looking at PR),
5883 make sure that all the regs it clobbers are safe too. */
5886 calc_live_regs (HARD_REG_SET *live_regs_mask)
5891 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
5892 bool nosave_low_regs;
5893 int pr_live, has_call;
5895 attrs = DECL_ATTRIBUTES (current_function_decl);
5896 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
5897 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
5898 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
5899 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
5901 CLEAR_HARD_REG_SET (*live_regs_mask);
5902 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
5903 && df_regs_ever_live_p (FPSCR_REG))
5904 target_flags &= ~MASK_FPU_SINGLE;
5905 /* If we can save a lot of saves by switching to double mode, do that. */
5906 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
5907 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
5908 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
5909 && (! call_really_used_regs[reg]
5910 || interrupt_handler)
5913 target_flags &= ~MASK_FPU_SINGLE;
5916 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
5917 knows how to use it. That means the pseudo originally allocated for
5918 the initial value can become the PR_MEDIA_REG hard register, as seen for
5919 execute/20010122-1.c:test9. */
5921 /* ??? this function is called from initial_elimination_offset, hence we
5922 can't use the result of sh_media_register_for_return here. */
5923 pr_live = sh_pr_n_sets ();
5926 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
5927 pr_live = (pr_initial
5928 ? (GET_CODE (pr_initial) != REG
5929 || REGNO (pr_initial) != (PR_REG))
5930 : df_regs_ever_live_p (PR_REG));
5931 /* For Shcompact, if not optimizing, we end up with a memory reference
5932 using the return address pointer for __builtin_return_address even
5933 though there is no actual need to put the PR register on the stack. */
5934 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
5936 /* Force PR to be live if the prologue has to call the SHmedia
5937 argument decoder or register saver. */
5938 if (TARGET_SHCOMPACT
5939 && ((current_function_args_info.call_cookie
5940 & ~ CALL_COOKIE_RET_TRAMP (1))
5941 || current_function_saves_all_registers))
5943 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
5944 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
5946 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
5949 ? (/* Need to save all the regs ever live. */
5950 (df_regs_ever_live_p (reg)
5951 || (call_really_used_regs[reg]
5952 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
5953 || reg == PIC_OFFSET_TABLE_REGNUM)
5955 || (TARGET_SHMEDIA && has_call
5956 && REGISTER_NATURAL_MODE (reg) == SImode
5957 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
5958 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
5959 && reg != RETURN_ADDRESS_POINTER_REGNUM
5960 && reg != T_REG && reg != GBR_REG
5961 /* Push fpscr only on targets which have FPU */
5962 && (reg != FPSCR_REG || TARGET_FPU_ANY))
5963 : (/* Only push those regs which are used and need to be saved. */
5966 && current_function_args_info.call_cookie
5967 && reg == PIC_OFFSET_TABLE_REGNUM)
5968 || (df_regs_ever_live_p (reg)
5969 && (!call_really_used_regs[reg]
5970 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
5971 || (current_function_calls_eh_return
5972 && (reg == EH_RETURN_DATA_REGNO (0)
5973 || reg == EH_RETURN_DATA_REGNO (1)
5974 || reg == EH_RETURN_DATA_REGNO (2)
5975 || reg == EH_RETURN_DATA_REGNO (3)))
5976 || ((reg == MACL_REG || reg == MACH_REG)
5977 && df_regs_ever_live_p (reg)
5978 && sh_cfun_attr_renesas_p ())
5981 SET_HARD_REG_BIT (*live_regs_mask, reg);
5982 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5984 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
5985 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
5987 if (FP_REGISTER_P (reg))
5989 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
5991 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
5992 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
5995 else if (XD_REGISTER_P (reg))
5997 /* Must switch to double mode to access these registers. */
5998 target_flags &= ~MASK_FPU_SINGLE;
6002 if (nosave_low_regs && reg == R8_REG)
6005 /* If we have a target register optimization pass after prologue / epilogue
6006 threading, we need to assume all target registers will be live even if
6008 if (flag_branch_target_load_optimize2
6009 && TARGET_SAVE_ALL_TARGET_REGS
6010 && shmedia_space_reserved_for_target_registers)
6011 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6012 if ((! call_really_used_regs[reg] || interrupt_handler)
6013 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6015 SET_HARD_REG_BIT (*live_regs_mask, reg);
6016 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6018 /* If this is an interrupt handler, we don't have any call-clobbered
6019 registers we can conveniently use for target register save/restore.
6020 Make sure we save at least one general purpose register when we need
6021 to save target registers. */
6022 if (interrupt_handler
6023 && hard_reg_set_intersect_p (*live_regs_mask,
6024 reg_class_contents[TARGET_REGS])
6025 && ! hard_reg_set_intersect_p (*live_regs_mask,
6026 reg_class_contents[GENERAL_REGS]))
6028 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6029 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6035 /* Code to generate prologue and epilogue sequences */
6037 /* PUSHED is the number of bytes that are being pushed on the
6038 stack for register saves. Return the frame size, padded
6039 appropriately so that the stack stays properly aligned. */
6040 static HOST_WIDE_INT
6041 rounded_frame_size (int pushed)
6043 HOST_WIDE_INT size = get_frame_size ();
6044 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6046 return ((size + pushed + align - 1) & -align) - pushed;
6049 /* Choose a call-clobbered target-branch register that remains
6050 unchanged along the whole function. We set it up as the return
6051 value in the prologue. */
6053 sh_media_register_for_return (void)
6058 if (! current_function_is_leaf)
6060 if (lookup_attribute ("interrupt_handler",
6061 DECL_ATTRIBUTES (current_function_decl)))
6063 if (sh_cfun_interrupt_handler_p ())
6066 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6068 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6069 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6075 /* The maximum registers we need to save are:
6076 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6077 - 32 floating point registers (for each pair, we save none,
6078 one single precision value, or a double precision value).
6079 - 8 target registers
6080 - add 1 entry for a delimiter. */
6081 #define MAX_SAVED_REGS (62+32+8)
6083 typedef struct save_entry_s
6092 /* There will be a delimiter entry with VOIDmode both at the start and the
6093 end of a filled in schedule. The end delimiter has the offset of the
6094 save with the smallest (i.e. most negative) offset. */
6095 typedef struct save_schedule_s
6097 save_entry entries[MAX_SAVED_REGS + 2];
6098 int temps[MAX_TEMPS+1];
6101 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6102 use reverse order. Returns the last entry written to (not counting
6103 the delimiter). OFFSET_BASE is a number to be added to all offset
6107 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6111 save_entry *entry = schedule->entries;
6115 if (! current_function_interrupt)
6116 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6117 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6118 && ! FUNCTION_ARG_REGNO_P (i)
6119 && i != FIRST_RET_REG
6120 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6121 && ! (current_function_calls_eh_return
6122 && (i == EH_RETURN_STACKADJ_REGNO
6123 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6124 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6125 schedule->temps[tmpx++] = i;
6127 entry->mode = VOIDmode;
6128 entry->offset = offset_base;
6130 /* We loop twice: first, we save 8-byte aligned registers in the
6131 higher addresses, that are known to be aligned. Then, we
6132 proceed to saving 32-bit registers that don't need 8-byte
6134 If this is an interrupt function, all registers that need saving
6135 need to be saved in full. moreover, we need to postpone saving
6136 target registers till we have saved some general purpose registers
6137 we can then use as scratch registers. */
6138 offset = offset_base;
6139 for (align = 1; align >= 0; align--)
6141 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6142 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6144 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6147 if (current_function_interrupt)
6149 if (TARGET_REGISTER_P (i))
6151 if (GENERAL_REGISTER_P (i))
6154 if (mode == SFmode && (i % 2) == 1
6155 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6156 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6163 /* If we're doing the aligned pass and this is not aligned,
6164 or we're doing the unaligned pass and this is aligned,
6166 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6170 if (current_function_interrupt
6171 && GENERAL_REGISTER_P (i)
6172 && tmpx < MAX_TEMPS)
6173 schedule->temps[tmpx++] = i;
6175 offset -= GET_MODE_SIZE (mode);
6178 entry->offset = offset;
6181 if (align && current_function_interrupt)
6182 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6183 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6185 offset -= GET_MODE_SIZE (DImode);
6187 entry->mode = DImode;
6188 entry->offset = offset;
6193 entry->mode = VOIDmode;
6194 entry->offset = offset;
6195 schedule->temps[tmpx] = -1;
6200 sh_expand_prologue (void)
6202 HARD_REG_SET live_regs_mask;
6205 int save_flags = target_flags;
6208 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6210 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6212 /* We have pretend args if we had an object sent partially in registers
6213 and partially on the stack, e.g. a large structure. */
6214 pretend_args = current_function_pretend_args_size;
6215 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6216 && (NPARM_REGS(SImode)
6217 > current_function_args_info.arg_count[(int) SH_ARG_INT]))
6219 output_stack_adjust (-pretend_args
6220 - current_function_args_info.stack_regs * 8,
6221 stack_pointer_rtx, 0, NULL);
6223 if (TARGET_SHCOMPACT && flag_pic && current_function_args_info.call_cookie)
6224 /* We're going to use the PIC register to load the address of the
6225 incoming-argument decoder and/or of the return trampoline from
6226 the GOT, so make sure the PIC register is preserved and
6228 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6230 if (TARGET_SHCOMPACT
6231 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6235 /* First, make all registers with incoming arguments that will
6236 be pushed onto the stack live, so that register renaming
6237 doesn't overwrite them. */
6238 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6239 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info.call_cookie)
6240 >= NPARM_REGS (SImode) - reg)
6241 for (; reg < NPARM_REGS (SImode); reg++)
6242 emit_insn (gen_shcompact_preserve_incoming_args
6243 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6244 else if (CALL_COOKIE_INT_REG_GET
6245 (current_function_args_info.call_cookie, reg) == 1)
6246 emit_insn (gen_shcompact_preserve_incoming_args
6247 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6249 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6251 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6252 GEN_INT (current_function_args_info.call_cookie));
6253 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6254 gen_rtx_REG (SImode, R0_REG));
6256 else if (TARGET_SHMEDIA)
6258 int tr = sh_media_register_for_return ();
6261 emit_move_insn (gen_rtx_REG (DImode, tr),
6262 gen_rtx_REG (DImode, PR_MEDIA_REG));
6265 /* Emit the code for SETUP_VARARGS. */
6266 if (current_function_stdarg)
6268 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6270 /* Push arg regs as if they'd been provided by caller in stack. */
6271 for (i = 0; i < NPARM_REGS(SImode); i++)
6273 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6276 if (i >= (NPARM_REGS(SImode)
6277 - current_function_args_info.arg_count[(int) SH_ARG_INT]
6281 RTX_FRAME_RELATED_P (insn) = 0;
6286 /* If we're supposed to switch stacks at function entry, do so now. */
6289 /* The argument specifies a variable holding the address of the
6290 stack the interrupt function should switch to/from at entry/exit. */
6292 = ggc_strdup (TREE_STRING_POINTER (TREE_VALUE (sp_switch_attr)));
6293 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6295 emit_insn (gen_sp_switch_1 (sp_switch));
6298 d = calc_live_regs (&live_regs_mask);
6299 /* ??? Maybe we could save some switching if we can move a mode switch
6300 that already happens to be at the function start into the prologue. */
6301 if (target_flags != save_flags && ! current_function_interrupt)
6302 emit_insn (gen_toggle_sz ());
6306 int offset_base, offset;
6308 int offset_in_r0 = -1;
6310 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6311 int total_size, save_size;
6312 save_schedule schedule;
6316 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6317 && ! current_function_interrupt)
6318 r0 = gen_rtx_REG (Pmode, R0_REG);
6320 /* D is the actual number of bytes that we need for saving registers,
6321 however, in initial_elimination_offset we have committed to using
6322 an additional TREGS_SPACE amount of bytes - in order to keep both
6323 addresses to arguments supplied by the caller and local variables
6324 valid, we must keep this gap. Place it between the incoming
6325 arguments and the actually saved registers in a bid to optimize
6326 locality of reference. */
6327 total_size = d + tregs_space;
6328 total_size += rounded_frame_size (total_size);
6329 save_size = total_size - rounded_frame_size (d);
6330 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6331 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6332 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6334 /* If adjusting the stack in a single step costs nothing extra, do so.
6335 I.e. either if a single addi is enough, or we need a movi anyway,
6336 and we don't exceed the maximum offset range (the test for the
6337 latter is conservative for simplicity). */
6339 && (CONST_OK_FOR_I10 (-total_size)
6340 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6341 && total_size <= 2044)))
6342 d_rounding = total_size - save_size;
6344 offset_base = d + d_rounding;
6346 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
6349 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6350 tmp_pnt = schedule.temps;
6351 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6353 enum machine_mode mode = entry->mode;
6354 unsigned int reg = entry->reg;
6355 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
6358 offset = entry->offset;
6360 reg_rtx = gen_rtx_REG (mode, reg);
6362 mem_rtx = gen_frame_mem (mode,
6363 gen_rtx_PLUS (Pmode,
6367 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
6374 if (HAVE_PRE_DECREMENT
6375 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6376 || mem_rtx == NULL_RTX
6377 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6379 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
6381 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
6390 offset += GET_MODE_SIZE (mode);
6394 if (mem_rtx != NULL_RTX)
6397 if (offset_in_r0 == -1)
6399 emit_move_insn (r0, GEN_INT (offset));
6400 offset_in_r0 = offset;
6402 else if (offset != offset_in_r0)
6407 GEN_INT (offset - offset_in_r0)));
6408 offset_in_r0 += offset - offset_in_r0;
6411 if (pre_dec != NULL_RTX)
6417 (Pmode, r0, stack_pointer_rtx));
6421 offset -= GET_MODE_SIZE (mode);
6422 offset_in_r0 -= GET_MODE_SIZE (mode);
6427 mem_rtx = gen_frame_mem (mode, r0);
6429 mem_rtx = gen_frame_mem (mode,
6430 gen_rtx_PLUS (Pmode,
6434 /* We must not use an r0-based address for target-branch
6435 registers or for special registers without pre-dec
6436 memory addresses, since we store their values in r0
6438 gcc_assert (!TARGET_REGISTER_P (reg)
6439 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6440 || mem_rtx == pre_dec));
6443 orig_reg_rtx = reg_rtx;
6444 if (TARGET_REGISTER_P (reg)
6445 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6446 && mem_rtx != pre_dec))
6448 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
6450 emit_move_insn (tmp_reg, reg_rtx);
6452 if (REGNO (tmp_reg) == R0_REG)
6456 gcc_assert (!refers_to_regno_p
6457 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
6460 if (*++tmp_pnt <= 0)
6461 tmp_pnt = schedule.temps;
6468 /* Mark as interesting for dwarf cfi generator */
6469 insn = emit_move_insn (mem_rtx, reg_rtx);
6470 RTX_FRAME_RELATED_P (insn) = 1;
6471 /* If we use an intermediate register for the save, we can't
6472 describe this exactly in cfi as a copy of the to-be-saved
6473 register into the temporary register and then the temporary
6474 register on the stack, because the temporary register can
6475 have a different natural size than the to-be-saved register.
6476 Thus, we gloss over the intermediate copy and pretend we do
6477 a direct save from the to-be-saved register. */
6478 if (REGNO (reg_rtx) != reg)
6482 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
6483 note_rtx = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set,
6485 REG_NOTES (insn) = note_rtx;
6488 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
6490 rtx reg_rtx = gen_rtx_REG (mode, reg);
6492 rtx mem_rtx = gen_frame_mem (mode,
6493 gen_rtx_PLUS (Pmode,
6497 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
6498 note_rtx = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set,
6500 REG_NOTES (insn) = note_rtx;
6505 gcc_assert (entry->offset == d_rounding);
6508 push_regs (&live_regs_mask, current_function_interrupt);
6510 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
6511 emit_insn (gen_GOTaddr2picreg ());
6513 if (SHMEDIA_REGS_STACK_ADJUST ())
6515 /* This must NOT go through the PLT, otherwise mach and macl
6516 may be clobbered. */
6517 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6519 ? "__GCC_push_shmedia_regs"
6520 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
6521 emit_insn (gen_shmedia_save_restore_regs_compact
6522 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
6525 if (target_flags != save_flags && ! current_function_interrupt)
6526 emit_insn (gen_toggle_sz ());
6528 target_flags = save_flags;
6530 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
6531 stack_pointer_rtx, 0, NULL);
6533 if (frame_pointer_needed)
6534 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
6536 if (TARGET_SHCOMPACT
6537 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6539 /* This must NOT go through the PLT, otherwise mach and macl
6540 may be clobbered. */
6541 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6542 "__GCC_shcompact_incoming_args", SFUNC_GOT);
6543 emit_insn (gen_shcompact_incoming_args ());
6548 sh_expand_epilogue (bool sibcall_p)
6550 HARD_REG_SET live_regs_mask;
6554 int save_flags = target_flags;
6555 int frame_size, save_size;
6556 int fpscr_deferred = 0;
6557 int e = sibcall_p ? -1 : 1;
6559 d = calc_live_regs (&live_regs_mask);
6562 frame_size = rounded_frame_size (d);
6566 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6568 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
6569 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6570 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
6572 total_size = d + tregs_space;
6573 total_size += rounded_frame_size (total_size);
6574 save_size = total_size - frame_size;
6576 /* If adjusting the stack in a single step costs nothing extra, do so.
6577 I.e. either if a single addi is enough, or we need a movi anyway,
6578 and we don't exceed the maximum offset range (the test for the
6579 latter is conservative for simplicity). */
6581 && ! frame_pointer_needed
6582 && (CONST_OK_FOR_I10 (total_size)
6583 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
6584 && total_size <= 2044)))
6585 d_rounding = frame_size;
6587 frame_size -= d_rounding;
6590 if (frame_pointer_needed)
6592 /* We must avoid scheduling the epilogue with previous basic blocks
6593 when exception handling is enabled. See PR/18032. */
6594 if (flag_exceptions)
6595 emit_insn (gen_blockage ());
6596 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
6599 /* We must avoid moving the stack pointer adjustment past code
6600 which reads from the local frame, else an interrupt could
6601 occur after the SP adjustment and clobber data in the local
6603 emit_insn (gen_blockage ());
6604 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
6606 else if (frame_size)
6608 /* We must avoid moving the stack pointer adjustment past code
6609 which reads from the local frame, else an interrupt could
6610 occur after the SP adjustment and clobber data in the local
6612 emit_insn (gen_blockage ());
6613 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
6616 if (SHMEDIA_REGS_STACK_ADJUST ())
6618 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6620 ? "__GCC_pop_shmedia_regs"
6621 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
6622 /* This must NOT go through the PLT, otherwise mach and macl
6623 may be clobbered. */
6624 emit_insn (gen_shmedia_save_restore_regs_compact
6625 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
6628 /* Pop all the registers. */
6630 if (target_flags != save_flags && ! current_function_interrupt)
6631 emit_insn (gen_toggle_sz ());
6634 int offset_base, offset;
6635 int offset_in_r0 = -1;
6637 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
6638 save_schedule schedule;
6642 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
6643 offset_base = -entry[1].offset + d_rounding;
6644 tmp_pnt = schedule.temps;
6645 for (; entry->mode != VOIDmode; entry--)
6647 enum machine_mode mode = entry->mode;
6648 int reg = entry->reg;
6649 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
6651 offset = offset_base + entry->offset;
6652 reg_rtx = gen_rtx_REG (mode, reg);
6654 mem_rtx = gen_frame_mem (mode,
6655 gen_rtx_PLUS (Pmode,
6659 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
6665 if (HAVE_POST_INCREMENT
6666 && (offset == offset_in_r0
6667 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
6668 && mem_rtx == NULL_RTX)
6669 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6671 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
6673 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
6676 post_inc = NULL_RTX;
6685 if (mem_rtx != NULL_RTX)
6688 if (offset_in_r0 == -1)
6690 emit_move_insn (r0, GEN_INT (offset));
6691 offset_in_r0 = offset;
6693 else if (offset != offset_in_r0)
6698 GEN_INT (offset - offset_in_r0)));
6699 offset_in_r0 += offset - offset_in_r0;
6702 if (post_inc != NULL_RTX)
6708 (Pmode, r0, stack_pointer_rtx));
6714 offset_in_r0 += GET_MODE_SIZE (mode);
6717 mem_rtx = gen_frame_mem (mode, r0);
6719 mem_rtx = gen_frame_mem (mode,
6720 gen_rtx_PLUS (Pmode,
6724 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6725 || mem_rtx == post_inc);
6728 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6729 && mem_rtx != post_inc)
6731 insn = emit_move_insn (r0, mem_rtx);
6734 else if (TARGET_REGISTER_P (reg))
6736 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
6738 /* Give the scheduler a bit of freedom by using up to
6739 MAX_TEMPS registers in a round-robin fashion. */
6740 insn = emit_move_insn (tmp_reg, mem_rtx);
6743 tmp_pnt = schedule.temps;
6746 insn = emit_move_insn (reg_rtx, mem_rtx);
6749 gcc_assert (entry->offset + offset_base == d + d_rounding);
6751 else /* ! TARGET_SH5 */
6756 /* For an ISR with RESBANK attribute assigned, don't pop PR
6758 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
6759 && !sh_cfun_resbank_handler_p ())
6761 if (!frame_pointer_needed)
6762 emit_insn (gen_blockage ());
6766 /* Banked registers are poped first to avoid being scheduled in the
6767 delay slot. RTE switches banks before the ds instruction. */
6768 if (current_function_interrupt)
6770 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6771 if (TEST_HARD_REG_BIT (live_regs_mask, i))
6772 pop (LAST_BANKED_REG - i);
6774 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
6777 last_reg = FIRST_PSEUDO_REGISTER;
6779 for (i = 0; i < last_reg; i++)
6781 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
6783 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
6784 && hard_reg_set_intersect_p (live_regs_mask,
6785 reg_class_contents[DF_REGS]))
6787 /* For an ISR with RESBANK attribute assigned, don't pop
6788 following registers, R0-R14, MACH, MACL and GBR. */
6789 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
6790 && ! (sh_cfun_resbank_handler_p ()
6791 && ((j >= FIRST_GENERAL_REG
6792 && j < LAST_GENERAL_REG)
6798 if (j == FIRST_FP_REG && fpscr_deferred)
6802 if (target_flags != save_flags && ! current_function_interrupt)
6803 emit_insn (gen_toggle_sz ());
6804 target_flags = save_flags;
6806 output_stack_adjust (current_function_pretend_args_size
6807 + save_size + d_rounding
6808 + current_function_args_info.stack_regs * 8,
6809 stack_pointer_rtx, e, NULL);
6811 if (current_function_calls_eh_return)
6812 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
6813 EH_RETURN_STACKADJ_RTX));
6815 /* Switch back to the normal stack if necessary. */
6816 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
6817 emit_insn (gen_sp_switch_2 ());
6819 /* Tell flow the insn that pops PR isn't dead. */
6820 /* PR_REG will never be live in SHmedia mode, and we don't need to
6821 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
6822 by the return pattern. */
6823 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
6824 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
6827 static int sh_need_epilogue_known = 0;
6830 sh_need_epilogue (void)
6832 if (! sh_need_epilogue_known)
6837 sh_expand_epilogue (0);
6838 epilogue = get_insns ();
6840 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
6842 return sh_need_epilogue_known > 0;
6845 /* Emit code to change the current function's return address to RA.
6846 TEMP is available as a scratch register, if needed. */
6849 sh_set_return_address (rtx ra, rtx tmp)
6851 HARD_REG_SET live_regs_mask;
6853 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
6856 d = calc_live_regs (&live_regs_mask);
6858 /* If pr_reg isn't life, we can set it (or the register given in
6859 sh_media_register_for_return) directly. */
6860 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
6866 int rr_regno = sh_media_register_for_return ();
6871 rr = gen_rtx_REG (DImode, rr_regno);
6874 rr = gen_rtx_REG (SImode, pr_reg);
6876 emit_insn (GEN_MOV (rr, ra));
6877 /* Tell flow the register for return isn't dead. */
6878 emit_insn (gen_rtx_USE (VOIDmode, rr));
6885 save_schedule schedule;
6888 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
6889 offset = entry[1].offset;
6890 for (; entry->mode != VOIDmode; entry--)
6891 if (entry->reg == pr_reg)
6894 /* We can't find pr register. */
6898 offset = entry->offset - offset;
6899 pr_offset = (rounded_frame_size (d) + offset
6900 + SHMEDIA_REGS_STACK_ADJUST ());
6903 pr_offset = rounded_frame_size (d);
6905 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
6906 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
6908 tmp = gen_frame_mem (Pmode, tmp);
6909 emit_insn (GEN_MOV (tmp, ra));
6912 /* Clear variables at function end. */
6915 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6916 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6918 sh_need_epilogue_known = 0;
6922 sh_builtin_saveregs (void)
6924 /* First unnamed integer register. */
6925 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
6926 /* Number of integer registers we need to save. */
6927 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
6928 /* First unnamed SFmode float reg */
6929 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
6930 /* Number of SFmode float regs to save. */
6931 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
6934 alias_set_type alias_set;
6940 int pushregs = n_intregs;
6942 while (pushregs < NPARM_REGS (SImode) - 1
6943 && (CALL_COOKIE_INT_REG_GET
6944 (current_function_args_info.call_cookie,
6945 NPARM_REGS (SImode) - pushregs)
6948 current_function_args_info.call_cookie
6949 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
6954 if (pushregs == NPARM_REGS (SImode))
6955 current_function_args_info.call_cookie
6956 |= (CALL_COOKIE_INT_REG (0, 1)
6957 | CALL_COOKIE_STACKSEQ (pushregs - 1));
6959 current_function_args_info.call_cookie
6960 |= CALL_COOKIE_STACKSEQ (pushregs);
6962 current_function_pretend_args_size += 8 * n_intregs;
6964 if (TARGET_SHCOMPACT)
6968 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
6970 error ("__builtin_saveregs not supported by this subtarget");
6977 /* Allocate block of memory for the regs. */
6978 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
6979 Or can assign_stack_local accept a 0 SIZE argument? */
6980 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
6983 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
6984 else if (n_floatregs & 1)
6988 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
6989 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
6990 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
6991 regbuf = change_address (regbuf, BLKmode, addr);
6993 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
6997 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
6998 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
6999 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7000 emit_insn (gen_andsi3 (addr, addr, mask));
7001 regbuf = change_address (regbuf, BLKmode, addr);
7004 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7005 alias_set = get_varargs_alias_set ();
7006 set_mem_alias_set (regbuf, alias_set);
7009 This is optimized to only save the regs that are necessary. Explicitly
7010 named args need not be saved. */
7012 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7013 adjust_address (regbuf, BLKmode,
7014 n_floatregs * UNITS_PER_WORD),
7018 /* Return the address of the regbuf. */
7019 return XEXP (regbuf, 0);
7022 This is optimized to only save the regs that are necessary. Explicitly
7023 named args need not be saved.
7024 We explicitly build a pointer to the buffer because it halves the insn
7025 count when not optimizing (otherwise the pointer is built for each reg
7027 We emit the moves in reverse order so that we can use predecrement. */
7029 fpregs = copy_to_mode_reg (Pmode,
7030 plus_constant (XEXP (regbuf, 0),
7031 n_floatregs * UNITS_PER_WORD));
7032 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7035 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7037 emit_insn (gen_addsi3 (fpregs, fpregs,
7038 GEN_INT (-2 * UNITS_PER_WORD)));
7039 mem = change_address (regbuf, DFmode, fpregs);
7040 emit_move_insn (mem,
7041 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7043 regno = first_floatreg;
7046 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7047 mem = change_address (regbuf, SFmode, fpregs);
7048 emit_move_insn (mem,
7049 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7050 - (TARGET_LITTLE_ENDIAN != 0)));
7054 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7058 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7059 mem = change_address (regbuf, SFmode, fpregs);
7060 emit_move_insn (mem,
7061 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7064 /* Return the address of the regbuf. */
7065 return XEXP (regbuf, 0);
7068 /* Define the `__builtin_va_list' type for the ABI. */
7071 sh_build_builtin_va_list (void)
7073 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7076 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7077 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7078 return ptr_type_node;
7080 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7082 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
7084 f_next_o_limit = build_decl (FIELD_DECL,
7085 get_identifier ("__va_next_o_limit"),
7087 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
7089 f_next_fp_limit = build_decl (FIELD_DECL,
7090 get_identifier ("__va_next_fp_limit"),
7092 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
7095 DECL_FIELD_CONTEXT (f_next_o) = record;
7096 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7097 DECL_FIELD_CONTEXT (f_next_fp) = record;
7098 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7099 DECL_FIELD_CONTEXT (f_next_stack) = record;
7101 TYPE_FIELDS (record) = f_next_o;
7102 TREE_CHAIN (f_next_o) = f_next_o_limit;
7103 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7104 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7105 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7107 layout_type (record);
7112 /* Implement `va_start' for varargs and stdarg. */
7115 sh_va_start (tree valist, rtx nextarg)
7117 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7118 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7124 expand_builtin_saveregs ();
7125 std_expand_builtin_va_start (valist, nextarg);
7129 if ((! TARGET_SH2E && ! TARGET_SH4)
7130 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7132 std_expand_builtin_va_start (valist, nextarg);
7136 f_next_o = TYPE_FIELDS (va_list_type_node);
7137 f_next_o_limit = TREE_CHAIN (f_next_o);
7138 f_next_fp = TREE_CHAIN (f_next_o_limit);
7139 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7140 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7142 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7144 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7145 valist, f_next_o_limit, NULL_TREE);
7146 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7148 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7149 valist, f_next_fp_limit, NULL_TREE);
7150 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7151 valist, f_next_stack, NULL_TREE);
7153 /* Call __builtin_saveregs. */
7154 u = make_tree (sizetype, expand_builtin_saveregs ());
7155 u = fold_convert (ptr_type_node, u);
7156 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_fp, u);
7157 TREE_SIDE_EFFECTS (t) = 1;
7158 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7160 nfp = current_function_args_info.arg_count[SH_ARG_FLOAT];
7165 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7166 size_int (UNITS_PER_WORD * nfp));
7167 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_fp_limit, u);
7168 TREE_SIDE_EFFECTS (t) = 1;
7169 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7171 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_o, u);
7172 TREE_SIDE_EFFECTS (t) = 1;
7173 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7175 nint = current_function_args_info.arg_count[SH_ARG_INT];
7180 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7181 size_int (UNITS_PER_WORD * nint));
7182 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_o_limit, u);
7183 TREE_SIDE_EFFECTS (t) = 1;
7184 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7186 u = make_tree (ptr_type_node, nextarg);
7187 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_stack, u);
7188 TREE_SIDE_EFFECTS (t) = 1;
7189 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7192 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7193 member, return it. */
7195 find_sole_member (tree type)
7197 tree field, member = NULL_TREE;
7199 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7201 if (TREE_CODE (field) != FIELD_DECL)
7203 if (!DECL_SIZE (field))
7205 if (integer_zerop (DECL_SIZE (field)))
7213 /* Implement `va_arg'. */
7216 sh_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p,
7217 tree *post_p ATTRIBUTE_UNUSED)
7219 HOST_WIDE_INT size, rsize;
7220 tree tmp, pptr_type_node;
7221 tree addr, lab_over = NULL, result = NULL;
7222 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7226 type = build_pointer_type (type);
7228 size = int_size_in_bytes (type);
7229 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7230 pptr_type_node = build_pointer_type (ptr_type_node);
7232 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7233 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7235 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7236 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7241 f_next_o = TYPE_FIELDS (va_list_type_node);
7242 f_next_o_limit = TREE_CHAIN (f_next_o);
7243 f_next_fp = TREE_CHAIN (f_next_o_limit);
7244 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7245 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7247 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7249 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7250 valist, f_next_o_limit, NULL_TREE);
7251 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7252 valist, f_next_fp, NULL_TREE);
7253 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7254 valist, f_next_fp_limit, NULL_TREE);
7255 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7256 valist, f_next_stack, NULL_TREE);
7258 /* Structures with a single member with a distinct mode are passed
7259 like their member. This is relevant if the latter has a REAL_TYPE
7260 or COMPLEX_TYPE type. */
7262 while (TREE_CODE (eff_type) == RECORD_TYPE
7263 && (member = find_sole_member (eff_type))
7264 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7265 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7266 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7268 tree field_type = TREE_TYPE (member);
7270 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7271 eff_type = field_type;
7274 gcc_assert ((TYPE_ALIGN (eff_type)
7275 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7276 || (TYPE_ALIGN (eff_type)
7277 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7282 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7284 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7285 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7286 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7291 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7294 addr = create_tmp_var (pptr_type_node, NULL);
7295 lab_false = create_artificial_label ();
7296 lab_over = create_artificial_label ();
7298 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
7302 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7304 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7306 tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp);
7307 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, tmp);
7308 gimplify_and_add (tmp, pre_p);
7310 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_fp_tmp, valist);
7311 gimplify_and_add (tmp, pre_p);
7312 tmp = next_fp_limit;
7313 if (size > 4 && !is_double)
7314 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp), tmp,
7315 size_int (4 - size));
7316 tmp = build2 (GE_EXPR, boolean_type_node, next_fp_tmp, tmp);
7317 cmp = build3 (COND_EXPR, void_type_node, tmp,
7318 build1 (GOTO_EXPR, void_type_node, lab_false),
7321 gimplify_and_add (cmp, pre_p);
7323 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7324 || (is_double || size == 16))
7326 tmp = fold_convert (sizetype, next_fp_tmp);
7327 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7328 size_int (UNITS_PER_WORD));
7329 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7331 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node,
7333 gimplify_and_add (tmp, pre_p);
7336 gimplify_and_add (cmp, pre_p);
7338 #ifdef FUNCTION_ARG_SCmode_WART
7339 if (TYPE_MODE (eff_type) == SCmode
7340 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7342 tree subtype = TREE_TYPE (eff_type);
7346 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7347 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7350 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7351 real = get_initialized_tmp_var (real, pre_p, NULL);
7353 result = build2 (COMPLEX_EXPR, type, real, imag);
7354 result = get_initialized_tmp_var (result, pre_p, NULL);
7356 #endif /* FUNCTION_ARG_SCmode_WART */
7358 tmp = build1 (GOTO_EXPR, void_type_node, lab_over);
7359 gimplify_and_add (tmp, pre_p);
7361 tmp = build1 (LABEL_EXPR, void_type_node, lab_false);
7362 gimplify_and_add (tmp, pre_p);
7364 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
7365 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, tmp);
7366 gimplify_and_add (tmp, pre_p);
7367 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_fp_tmp, valist);
7368 gimplify_and_add (tmp, pre_p);
7370 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, valist, next_fp_tmp);
7371 gimplify_and_add (tmp, post_p);
7372 valist = next_fp_tmp;
7376 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node, next_o,
7378 tmp = build2 (GT_EXPR, boolean_type_node, tmp, next_o_limit);
7379 tmp = build3 (COND_EXPR, void_type_node, tmp,
7380 build1 (GOTO_EXPR, void_type_node, lab_false),
7382 gimplify_and_add (tmp, pre_p);
7384 tmp = build1 (ADDR_EXPR, pptr_type_node, next_o);
7385 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, tmp);
7386 gimplify_and_add (tmp, pre_p);
7388 tmp = build1 (GOTO_EXPR, void_type_node, lab_over);
7389 gimplify_and_add (tmp, pre_p);
7391 tmp = build1 (LABEL_EXPR, void_type_node, lab_false);
7392 gimplify_and_add (tmp, pre_p);
7394 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7396 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node,
7397 next_o, next_o_limit);
7398 gimplify_and_add (tmp, pre_p);
7401 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
7402 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, tmp);
7403 gimplify_and_add (tmp, pre_p);
7408 tmp = build1 (LABEL_EXPR, void_type_node, lab_over);
7409 gimplify_and_add (tmp, pre_p);
7413 /* ??? In va-sh.h, there had been code to make values larger than
7414 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7416 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7419 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, result, tmp);
7420 gimplify_and_add (tmp, pre_p);
7422 tmp = build1 (LABEL_EXPR, void_type_node, lab_over);
7423 gimplify_and_add (tmp, pre_p);
7429 result = build_va_arg_indirect_ref (result);
7435 sh_promote_prototypes (const_tree type)
7441 return ! sh_attr_renesas_p (type);
7444 /* Whether an argument must be passed by reference. On SHcompact, we
7445 pretend arguments wider than 32-bits that would have been passed in
7446 registers are passed by reference, so that an SHmedia trampoline
7447 loads them into the full 64-bits registers. */
7450 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
7451 const_tree type, bool named)
7453 unsigned HOST_WIDE_INT size;
7456 size = int_size_in_bytes (type);
7458 size = GET_MODE_SIZE (mode);
7460 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
7462 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
7463 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
7464 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
7466 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
7467 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7474 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7475 const_tree type, bool named)
7477 if (targetm.calls.must_pass_in_stack (mode, type))
7480 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7481 wants to know about pass-by-reference semantics for incoming
7486 if (TARGET_SHCOMPACT)
7488 cum->byref = shcompact_byref (cum, mode, type, named);
7489 return cum->byref != 0;
7496 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7497 const_tree type, bool named ATTRIBUTE_UNUSED)
7499 /* ??? How can it possibly be correct to return true only on the
7500 caller side of the equation? Is there someplace else in the
7501 sh backend that's magically producing the copies? */
7502 return (cum->outgoing
7503 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
7504 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
7508 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7509 tree type, bool named ATTRIBUTE_UNUSED)
7514 && PASS_IN_REG_P (*cum, mode, type)
7515 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7516 && (ROUND_REG (*cum, mode)
7518 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
7519 : ROUND_ADVANCE (int_size_in_bytes (type)))
7520 > NPARM_REGS (mode)))
7521 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
7523 else if (!TARGET_SHCOMPACT
7524 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7525 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
7527 return words * UNITS_PER_WORD;
7531 /* Define where to put the arguments to a function.
7532 Value is zero to push the argument on the stack,
7533 or a hard register in which to store the argument.
7535 MODE is the argument's machine mode.
7536 TYPE is the data type of the argument (as a tree).
7537 This is null for libcalls where that information may
7539 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7540 the preceding args and about the function being called.
7541 NAMED is nonzero if this argument is a named parameter
7542 (otherwise it is an extra parameter matching an ellipsis).
7544 On SH the first args are normally in registers
7545 and the rest are pushed. Any arg that starts within the first
7546 NPARM_REGS words is at least partially passed in a register unless
7547 its data type forbids. */
7551 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7552 tree type, int named)
7554 if (! TARGET_SH5 && mode == VOIDmode)
7555 return GEN_INT (ca->renesas_abi ? 1 : 0);
7558 && PASS_IN_REG_P (*ca, mode, type)
7559 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
7563 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
7564 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
7566 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
7567 gen_rtx_REG (SFmode,
7569 + (ROUND_REG (*ca, mode) ^ 1)),
7571 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
7572 gen_rtx_REG (SFmode,
7574 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
7576 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
7579 /* If the alignment of a DF value causes an SF register to be
7580 skipped, we will use that skipped register for the next SF
7582 if ((TARGET_HITACHI || ca->renesas_abi)
7583 && ca->free_single_fp_reg
7585 return gen_rtx_REG (mode, ca->free_single_fp_reg);
7587 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
7588 ^ (mode == SFmode && TARGET_SH4
7589 && TARGET_LITTLE_ENDIAN != 0
7590 && ! TARGET_HITACHI && ! ca->renesas_abi);
7591 return gen_rtx_REG (mode, regno);
7597 if (mode == VOIDmode && TARGET_SHCOMPACT)
7598 return GEN_INT (ca->call_cookie);
7600 /* The following test assumes unnamed arguments are promoted to
7602 if (mode == SFmode && ca->free_single_fp_reg)
7603 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
7605 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
7606 && (named || ! ca->prototype_p)
7607 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
7609 if (! ca->prototype_p && TARGET_SHMEDIA)
7610 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
7612 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
7614 + ca->arg_count[(int) SH_ARG_FLOAT]);
7617 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
7618 && (! TARGET_SHCOMPACT
7619 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
7620 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
7623 return gen_rtx_REG (mode, (FIRST_PARM_REG
7624 + ca->arg_count[(int) SH_ARG_INT]));
7633 /* Update the data in CUM to advance over an argument
7634 of mode MODE and data type TYPE.
7635 (TYPE is null for libcalls where that information may not be
7639 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7640 tree type, int named)
7644 else if (TARGET_SH5)
7646 tree type2 = (ca->byref && type
7649 enum machine_mode mode2 = (ca->byref && type
7652 int dwords = ((ca->byref
7655 ? int_size_in_bytes (type2)
7656 : GET_MODE_SIZE (mode2)) + 7) / 8;
7657 int numregs = MIN (dwords, NPARM_REGS (SImode)
7658 - ca->arg_count[(int) SH_ARG_INT]);
7662 ca->arg_count[(int) SH_ARG_INT] += numregs;
7663 if (TARGET_SHCOMPACT
7664 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
7667 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7669 /* N.B. We want this also for outgoing. */
7670 ca->stack_regs += numregs;
7675 ca->stack_regs += numregs;
7676 ca->byref_regs += numregs;
7680 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7684 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7687 else if (dwords > numregs)
7689 int pushregs = numregs;
7691 if (TARGET_SHCOMPACT)
7692 ca->stack_regs += numregs;
7693 while (pushregs < NPARM_REGS (SImode) - 1
7694 && (CALL_COOKIE_INT_REG_GET
7696 NPARM_REGS (SImode) - pushregs)
7700 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7704 if (numregs == NPARM_REGS (SImode))
7706 |= CALL_COOKIE_INT_REG (0, 1)
7707 | CALL_COOKIE_STACKSEQ (numregs - 1);
7710 |= CALL_COOKIE_STACKSEQ (numregs);
7713 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
7714 && (named || ! ca->prototype_p))
7716 if (mode2 == SFmode && ca->free_single_fp_reg)
7717 ca->free_single_fp_reg = 0;
7718 else if (ca->arg_count[(int) SH_ARG_FLOAT]
7719 < NPARM_REGS (SFmode))
7722 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
7724 - ca->arg_count[(int) SH_ARG_FLOAT]);
7726 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
7728 if (TARGET_SHCOMPACT && ! ca->prototype_p)
7730 if (ca->outgoing && numregs > 0)
7734 |= (CALL_COOKIE_INT_REG
7735 (ca->arg_count[(int) SH_ARG_INT]
7736 - numregs + ((numfpregs - 2) / 2),
7737 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
7740 while (numfpregs -= 2);
7742 else if (mode2 == SFmode && (named)
7743 && (ca->arg_count[(int) SH_ARG_FLOAT]
7744 < NPARM_REGS (SFmode)))
7745 ca->free_single_fp_reg
7746 = FIRST_FP_PARM_REG - numfpregs
7747 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
7753 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
7755 /* Note that we've used the skipped register. */
7756 if (mode == SFmode && ca->free_single_fp_reg)
7758 ca->free_single_fp_reg = 0;
7761 /* When we have a DF after an SF, there's an SF register that get
7762 skipped in order to align the DF value. We note this skipped
7763 register, because the next SF value will use it, and not the
7764 SF that follows the DF. */
7766 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
7768 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
7769 + BASE_ARG_REG (mode));
7773 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
7774 || PASS_IN_REG_P (*ca, mode, type))
7775 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
7776 = (ROUND_REG (*ca, mode)
7778 ? ROUND_ADVANCE (int_size_in_bytes (type))
7779 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
7782 /* The Renesas calling convention doesn't quite fit into this scheme since
7783 the address is passed like an invisible argument, but one that is always
7784 passed in memory. */
7786 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
7788 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7790 return gen_rtx_REG (Pmode, 2);
7793 /* Worker function for TARGET_RETURN_IN_MEMORY. */
7796 sh_return_in_memory (const_tree type, const_tree fndecl)
7800 if (TYPE_MODE (type) == BLKmode)
7801 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
7803 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
7807 return (TYPE_MODE (type) == BLKmode
7808 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7809 && TREE_CODE (type) == RECORD_TYPE));
7813 /* We actually emit the code in sh_expand_prologue. We used to use
7814 a static variable to flag that we need to emit this code, but that
7815 doesn't when inlining, when functions are deferred and then emitted
7816 later. Fortunately, we already have two flags that are part of struct
7817 function that tell if a function uses varargs or stdarg. */
7819 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
7820 enum machine_mode mode,
7822 int *pretend_arg_size,
7823 int second_time ATTRIBUTE_UNUSED)
7825 gcc_assert (current_function_stdarg);
7826 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
7828 int named_parm_regs, anon_parm_regs;
7830 named_parm_regs = (ROUND_REG (*ca, mode)
7832 ? ROUND_ADVANCE (int_size_in_bytes (type))
7833 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
7834 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
7835 if (anon_parm_regs > 0)
7836 *pretend_arg_size = anon_parm_regs * 4;
7841 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
7847 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
7849 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
7853 /* Define the offset between two registers, one to be eliminated, and
7854 the other its replacement, at the start of a routine. */
7857 initial_elimination_offset (int from, int to)
7860 int regs_saved_rounding = 0;
7861 int total_saved_regs_space;
7862 int total_auto_space;
7863 int save_flags = target_flags;
7865 HARD_REG_SET live_regs_mask;
7867 shmedia_space_reserved_for_target_registers = false;
7868 regs_saved = calc_live_regs (&live_regs_mask);
7869 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
7871 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
7873 shmedia_space_reserved_for_target_registers = true;
7874 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
7877 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
7878 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7879 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
7881 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
7882 copy_flags = target_flags;
7883 target_flags = save_flags;
7885 total_saved_regs_space = regs_saved + regs_saved_rounding;
7887 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7888 return total_saved_regs_space + total_auto_space
7889 + current_function_args_info.byref_regs * 8;
7891 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7892 return total_saved_regs_space + total_auto_space
7893 + current_function_args_info.byref_regs * 8;
7895 /* Initial gap between fp and sp is 0. */
7896 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7899 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7900 return rounded_frame_size (0);
7902 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7903 return rounded_frame_size (0);
7905 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
7906 && (to == HARD_FRAME_POINTER_REGNUM
7907 || to == STACK_POINTER_REGNUM));
7910 int n = total_saved_regs_space;
7911 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7912 save_schedule schedule;
7915 n += total_auto_space;
7917 /* If it wasn't saved, there's not much we can do. */
7918 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7921 target_flags = copy_flags;
7923 sh5_schedule_saves (&live_regs_mask, &schedule, n);
7924 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
7925 if (entry->reg == pr_reg)
7927 target_flags = save_flags;
7928 return entry->offset;
7933 return total_auto_space;
7936 /* Insert any deferred function attributes from earlier pragmas. */
7938 sh_insert_attributes (tree node, tree *attributes)
7942 if (TREE_CODE (node) != FUNCTION_DECL)
7945 /* We are only interested in fields. */
7949 /* Append the attributes to the deferred attributes. */
7950 *sh_deferred_function_attributes_tail = *attributes;
7951 attrs = sh_deferred_function_attributes;
7955 /* Some attributes imply or require the interrupt attribute. */
7956 if (!lookup_attribute ("interrupt_handler", attrs)
7957 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
7959 /* If we have a trapa_handler, but no interrupt_handler attribute,
7960 insert an interrupt_handler attribute. */
7961 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
7962 /* We can't use sh_pr_interrupt here because that's not in the
7965 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
7966 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
7967 if the interrupt attribute is missing, we ignore the attribute
7969 else if (lookup_attribute ("sp_switch", attrs)
7970 || lookup_attribute ("trap_exit", attrs)
7971 || lookup_attribute ("nosave_low_regs", attrs)
7972 || lookup_attribute ("resbank", attrs))
7976 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
7978 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
7979 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
7980 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
7981 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
7982 warning (OPT_Wattributes,
7983 "%qs attribute only applies to interrupt functions",
7984 IDENTIFIER_POINTER (TREE_PURPOSE (attrs)));
7987 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
7989 tail = &TREE_CHAIN (*tail);
7992 attrs = *attributes;
7996 /* Install the processed list. */
7997 *attributes = attrs;
7999 /* Clear deferred attributes. */
8000 sh_deferred_function_attributes = NULL_TREE;
8001 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8006 /* Supported attributes:
8008 interrupt_handler -- specifies this function is an interrupt handler.
8010 trapa_handler - like above, but don't save all registers.
8012 sp_switch -- specifies an alternate stack for an interrupt handler
8015 trap_exit -- use a trapa to exit an interrupt function instead of
8018 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8019 This is useful on the SH3 and upwards,
8020 which has a separate set of low regs for User and Supervisor modes.
8021 This should only be used for the lowest level of interrupts. Higher levels
8022 of interrupts must save the registers in case they themselves are
8025 renesas -- use Renesas calling/layout conventions (functions and
8028 resbank -- In case of an ISR, use a register bank to save registers
8029 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8032 const struct attribute_spec sh_attribute_table[] =
8034 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8035 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8036 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
8037 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
8038 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
8039 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8040 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8041 { "resbank", 0, 0, true, false, false, sh_handle_resbank_handler_attribute },
8042 { "function_vector", 1, 1, true, false, false, sh2a_handle_function_vector_handler_attribute },
8044 /* Symbian support adds three new attributes:
8045 dllexport - for exporting a function/variable that will live in a dll
8046 dllimport - for importing a function/variable from a dll
8048 Microsoft allows multiple declspecs in one __declspec, separating
8049 them with spaces. We do NOT support this. Instead, use __declspec
8051 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8052 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8054 { NULL, 0, 0, false, false, false, NULL }
8057 /* Handle a 'resbank' attribute. */
8059 sh_handle_resbank_handler_attribute (tree * node, tree name,
8060 tree args ATTRIBUTE_UNUSED,
8061 int flags ATTRIBUTE_UNUSED,
8062 bool * no_add_attrs)
8066 warning (OPT_Wattributes, "%qs attribute is supported only for SH2A",
8067 IDENTIFIER_POINTER (name));
8068 *no_add_attrs = true;
8070 if (TREE_CODE (*node) != FUNCTION_DECL)
8072 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8073 IDENTIFIER_POINTER (name));
8074 *no_add_attrs = true;
8080 /* Handle an "interrupt_handler" attribute; arguments as in
8081 struct attribute_spec.handler. */
8083 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8084 tree args ATTRIBUTE_UNUSED,
8085 int flags ATTRIBUTE_UNUSED,
8088 if (TREE_CODE (*node) != FUNCTION_DECL)
8090 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8091 IDENTIFIER_POINTER (name));
8092 *no_add_attrs = true;
8094 else if (TARGET_SHCOMPACT)
8096 error ("attribute interrupt_handler is not compatible with -m5-compact");
8097 *no_add_attrs = true;
8103 /* Handle an 'function_vector' attribute; arguments as in
8104 struct attribute_spec.handler. */
8106 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8107 tree args ATTRIBUTE_UNUSED,
8108 int flags ATTRIBUTE_UNUSED,
8109 bool * no_add_attrs)
8113 warning (OPT_Wattributes, "%qs attribute only applies to SH2A",
8114 IDENTIFIER_POINTER (name));
8115 *no_add_attrs = true;
8117 else if (TREE_CODE (*node) != FUNCTION_DECL)
8119 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8120 IDENTIFIER_POINTER (name));
8121 *no_add_attrs = true;
8123 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8125 /* The argument must be a constant integer. */
8126 warning (OPT_Wattributes,
8127 "`%s' attribute argument not an integer constant",
8128 IDENTIFIER_POINTER (name));
8129 *no_add_attrs = true;
8131 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8133 /* The argument value must be between 0 to 255. */
8134 warning (OPT_Wattributes,
8135 "`%s' attribute argument should be between 0 to 255",
8136 IDENTIFIER_POINTER (name));
8137 *no_add_attrs = true;
8142 /* Returns 1 if current function has been assigned the attribute
8143 'function_vector'. */
8145 sh2a_is_function_vector_call (rtx x)
8147 if (GET_CODE (x) == SYMBOL_REF
8148 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8150 tree tr = SYMBOL_REF_DECL (x);
8152 if (sh2a_function_vector_p (tr))
8159 /* Returns the function vector number, if the the attribute
8160 'function_vector' is assigned, otherwise returns zero. */
8162 sh2a_get_function_vector_number (rtx x)
8167 if ((GET_CODE (x) == SYMBOL_REF)
8168 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8170 t = SYMBOL_REF_DECL (x);
8172 if (TREE_CODE (t) != FUNCTION_DECL)
8175 list = SH_ATTRIBUTES (t);
8178 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8180 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8184 list = TREE_CHAIN (list);
8193 /* Handle an "sp_switch" attribute; arguments as in
8194 struct attribute_spec.handler. */
8196 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8197 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8199 if (TREE_CODE (*node) != FUNCTION_DECL)
8201 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8202 IDENTIFIER_POINTER (name));
8203 *no_add_attrs = true;
8205 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8207 /* The argument must be a constant string. */
8208 warning (OPT_Wattributes, "%qs attribute argument not a string constant",
8209 IDENTIFIER_POINTER (name));
8210 *no_add_attrs = true;
8216 /* Handle an "trap_exit" attribute; arguments as in
8217 struct attribute_spec.handler. */
8219 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8220 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8222 if (TREE_CODE (*node) != FUNCTION_DECL)
8224 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8225 IDENTIFIER_POINTER (name));
8226 *no_add_attrs = true;
8228 /* The argument specifies a trap number to be used in a trapa instruction
8229 at function exit (instead of an rte instruction). */
8230 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8232 /* The argument must be a constant integer. */
8233 warning (OPT_Wattributes, "%qs attribute argument not an "
8234 "integer constant", IDENTIFIER_POINTER (name));
8235 *no_add_attrs = true;
8242 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8243 tree name ATTRIBUTE_UNUSED,
8244 tree args ATTRIBUTE_UNUSED,
8245 int flags ATTRIBUTE_UNUSED,
8246 bool *no_add_attrs ATTRIBUTE_UNUSED)
8251 /* True if __attribute__((renesas)) or -mrenesas. */
8253 sh_attr_renesas_p (const_tree td)
8260 td = TREE_TYPE (td);
8261 if (td == error_mark_node)
8263 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8267 /* True if __attribute__((renesas)) or -mrenesas, for the current
8270 sh_cfun_attr_renesas_p (void)
8272 return sh_attr_renesas_p (current_function_decl);
8276 sh_cfun_interrupt_handler_p (void)
8278 return (lookup_attribute ("interrupt_handler",
8279 DECL_ATTRIBUTES (current_function_decl))
8283 /* Returns 1 if FUNC has been assigned the attribute
8284 "function_vector". */
8286 sh2a_function_vector_p (tree func)
8289 if (TREE_CODE (func) != FUNCTION_DECL)
8292 list = SH_ATTRIBUTES (func);
8295 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8298 list = TREE_CHAIN (list);
8303 /* Returns TRUE if given tree has the "resbank" attribute. */
8306 sh_cfun_resbank_handler_p (void)
8308 return ((lookup_attribute ("resbank",
8309 DECL_ATTRIBUTES (current_function_decl))
8311 && (lookup_attribute ("interrupt_handler",
8312 DECL_ATTRIBUTES (current_function_decl))
8313 != NULL_TREE) && TARGET_SH2A);
8316 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8319 sh_check_pch_target_flags (int old_flags)
8321 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8322 | MASK_SH_E | MASK_HARD_SH4
8323 | MASK_FPU_SINGLE | MASK_SH4))
8324 return _("created and used with different architectures / ABIs");
8325 if ((old_flags ^ target_flags) & MASK_HITACHI)
8326 return _("created and used with different ABIs");
8327 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8328 return _("created and used with different endianness");
8332 /* Predicates used by the templates. */
8334 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
8335 Used only in general_movsrc_operand. */
8338 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8350 /* Nonzero if OP is a floating point value with value 0.0. */
8353 fp_zero_operand (rtx op)
8357 if (GET_MODE (op) != SFmode)
8360 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8361 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
8364 /* Nonzero if OP is a floating point value with value 1.0. */
8367 fp_one_operand (rtx op)
8371 if (GET_MODE (op) != SFmode)
8374 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8375 return REAL_VALUES_EQUAL (r, dconst1);
8378 /* For -m4 and -m4-single-only, mode switching is used. If we are
8379 compiling without -mfmovd, movsf_ie isn't taken into account for
8380 mode switching. We could check in machine_dependent_reorg for
8381 cases where we know we are in single precision mode, but there is
8382 interface to find that out during reload, so we must avoid
8383 choosing an fldi alternative during reload and thus failing to
8384 allocate a scratch register for the constant loading. */
8388 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
8392 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8394 enum rtx_code code = GET_CODE (op);
8395 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
8398 /* Return the TLS type for TLS symbols, 0 for otherwise. */
8400 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8402 if (GET_CODE (op) != SYMBOL_REF)
8404 return SYMBOL_REF_TLS_MODEL (op);
8407 /* Return the destination address of a branch. */
8410 branch_dest (rtx branch)
8412 rtx dest = SET_SRC (PATTERN (branch));
8415 if (GET_CODE (dest) == IF_THEN_ELSE)
8416 dest = XEXP (dest, 1);
8417 dest = XEXP (dest, 0);
8418 dest_uid = INSN_UID (dest);
8419 return INSN_ADDRESSES (dest_uid);
8422 /* Return nonzero if REG is not used after INSN.
8423 We assume REG is a reload reg, and therefore does
8424 not live past labels. It may live past calls or jumps though. */
8426 reg_unused_after (rtx reg, rtx insn)
8431 /* If the reg is set by this instruction, then it is safe for our
8432 case. Disregard the case where this is a store to memory, since
8433 we are checking a register used in the store address. */
8434 set = single_set (insn);
8435 if (set && GET_CODE (SET_DEST (set)) != MEM
8436 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8439 while ((insn = NEXT_INSN (insn)))
8445 code = GET_CODE (insn);
8448 /* If this is a label that existed before reload, then the register
8449 if dead here. However, if this is a label added by reorg, then
8450 the register may still be live here. We can't tell the difference,
8451 so we just ignore labels completely. */
8452 if (code == CODE_LABEL)
8457 if (code == JUMP_INSN)
8460 /* If this is a sequence, we must handle them all at once.
8461 We could have for instance a call that sets the target register,
8462 and an insn in a delay slot that uses the register. In this case,
8463 we must return 0. */
8464 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
8469 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8471 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
8472 rtx set = single_set (this_insn);
8474 if (GET_CODE (this_insn) == CALL_INSN)
8476 else if (GET_CODE (this_insn) == JUMP_INSN)
8478 if (INSN_ANNULLED_BRANCH_P (this_insn))
8483 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8485 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8487 if (GET_CODE (SET_DEST (set)) != MEM)
8493 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
8498 else if (code == JUMP_INSN)
8502 set = single_set (insn);
8503 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8505 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8506 return GET_CODE (SET_DEST (set)) != MEM;
8507 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
8510 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
8518 static GTY(()) rtx fpscr_rtx;
8520 get_fpscr_rtx (void)
8524 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
8525 REG_USERVAR_P (fpscr_rtx) = 1;
8526 mark_user_reg (fpscr_rtx);
8528 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
8529 mark_user_reg (fpscr_rtx);
8533 static GTY(()) tree fpscr_values;
8536 emit_fpu_switch (rtx scratch, int index)
8540 if (fpscr_values == NULL)
8544 t = build_index_type (integer_one_node);
8545 t = build_array_type (integer_type_node, t);
8546 t = build_decl (VAR_DECL, get_identifier ("__fpscr_values"), t);
8547 DECL_ARTIFICIAL (t) = 1;
8548 DECL_IGNORED_P (t) = 1;
8549 DECL_EXTERNAL (t) = 1;
8550 TREE_STATIC (t) = 1;
8551 TREE_PUBLIC (t) = 1;
8557 src = DECL_RTL (fpscr_values);
8558 if (!can_create_pseudo_p ())
8560 emit_move_insn (scratch, XEXP (src, 0));
8562 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
8563 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
8566 src = adjust_address (src, PSImode, index * 4);
8568 dst = get_fpscr_rtx ();
8569 emit_move_insn (dst, src);
8573 emit_sf_insn (rtx pat)
8579 emit_df_insn (rtx pat)
8585 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8587 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8591 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8593 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
8598 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8600 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8604 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8606 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
8610 static rtx get_free_reg (HARD_REG_SET);
8612 /* This function returns a register to use to load the address to load
8613 the fpscr from. Currently it always returns r1 or r7, but when we are
8614 able to use pseudo registers after combine, or have a better mechanism
8615 for choosing a register, it should be done here. */
8616 /* REGS_LIVE is the liveness information for the point for which we
8617 need this allocation. In some bare-bones exit blocks, r1 is live at the
8618 start. We can even have all of r0..r3 being live:
8619 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
8620 INSN before which new insns are placed with will clobber the register
8621 we return. If a basic block consists only of setting the return value
8622 register to a pseudo and using that register, the return value is not
8623 live before or after this block, yet we we'll insert our insns right in
8627 get_free_reg (HARD_REG_SET regs_live)
8629 if (! TEST_HARD_REG_BIT (regs_live, 1))
8630 return gen_rtx_REG (Pmode, 1);
8632 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
8633 there shouldn't be anything but a jump before the function end. */
8634 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
8635 return gen_rtx_REG (Pmode, 7);
8638 /* This function will set the fpscr from memory.
8639 MODE is the mode we are setting it to. */
8641 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
8643 enum attr_fp_mode fp_mode = mode;
8644 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
8647 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
8648 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
8651 /* Is the given character a logical line separator for the assembler? */
8652 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
8653 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
8657 sh_insn_length_adjustment (rtx insn)
8659 /* Instructions with unfilled delay slots take up an extra two bytes for
8660 the nop in the delay slot. */
8661 if (((GET_CODE (insn) == INSN
8662 && GET_CODE (PATTERN (insn)) != USE
8663 && GET_CODE (PATTERN (insn)) != CLOBBER)
8664 || GET_CODE (insn) == CALL_INSN
8665 || (GET_CODE (insn) == JUMP_INSN
8666 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8667 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
8668 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
8669 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
8672 /* SH2e has a bug that prevents the use of annulled branches, so if
8673 the delay slot is not filled, we'll have to put a NOP in it. */
8674 if (sh_cpu == CPU_SH2E
8675 && GET_CODE (insn) == JUMP_INSN
8676 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8677 && GET_CODE (PATTERN (insn)) != ADDR_VEC
8678 && get_attr_type (insn) == TYPE_CBRANCH
8679 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
8682 /* sh-dsp parallel processing insn take four bytes instead of two. */
8684 if (GET_CODE (insn) == INSN)
8687 rtx body = PATTERN (insn);
8688 const char *template;
8690 int maybe_label = 1;
8692 if (GET_CODE (body) == ASM_INPUT)
8693 template = XSTR (body, 0);
8694 else if (asm_noperands (body) >= 0)
8696 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
8705 while (c == ' ' || c == '\t');
8706 /* all sh-dsp parallel-processing insns start with p.
8707 The only non-ppi sh insn starting with p is pref.
8708 The only ppi starting with pr is prnd. */
8709 if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2))
8711 /* The repeat pseudo-insn expands two three insns, a total of
8712 six bytes in size. */
8713 else if ((c == 'r' || c == 'R')
8714 && ! strncasecmp ("epeat", template, 5))
8716 while (c && c != '\n'
8717 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, template))
8719 /* If this is a label, it is obviously not a ppi insn. */
8720 if (c == ':' && maybe_label)
8725 else if (c == '\'' || c == '"')
8730 maybe_label = c != ':';
8738 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
8739 isn't protected by a PIC unspec. */
8741 nonpic_symbol_mentioned_p (rtx x)
8743 register const char *fmt;
8746 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
8747 || GET_CODE (x) == PC)
8750 /* We don't want to look into the possible MEM location of a
8751 CONST_DOUBLE, since we're not going to use it, in general. */
8752 if (GET_CODE (x) == CONST_DOUBLE)
8755 if (GET_CODE (x) == UNSPEC
8756 && (XINT (x, 1) == UNSPEC_PIC
8757 || XINT (x, 1) == UNSPEC_GOT
8758 || XINT (x, 1) == UNSPEC_GOTOFF
8759 || XINT (x, 1) == UNSPEC_GOTPLT
8760 || XINT (x, 1) == UNSPEC_GOTTPOFF
8761 || XINT (x, 1) == UNSPEC_DTPOFF
8762 || XINT (x, 1) == UNSPEC_PLT))
8765 fmt = GET_RTX_FORMAT (GET_CODE (x));
8766 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8772 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8773 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
8776 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
8783 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
8784 @GOTOFF in `reg'. */
8786 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
8789 if (tls_symbolic_operand (orig, Pmode))
8792 if (GET_CODE (orig) == LABEL_REF
8793 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
8796 reg = gen_reg_rtx (Pmode);
8798 emit_insn (gen_symGOTOFF2reg (reg, orig));
8801 else if (GET_CODE (orig) == SYMBOL_REF)
8804 reg = gen_reg_rtx (Pmode);
8806 emit_insn (gen_symGOT2reg (reg, orig));
8812 /* Mark the use of a constant in the literal table. If the constant
8813 has multiple labels, make it unique. */
8815 mark_constant_pool_use (rtx x)
8817 rtx insn, lab, pattern;
8822 switch (GET_CODE (x))
8832 /* Get the first label in the list of labels for the same constant
8833 and delete another labels in the list. */
8835 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
8837 if (GET_CODE (insn) != CODE_LABEL
8838 || LABEL_REFS (insn) != NEXT_INSN (insn))
8843 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
8844 INSN_DELETED_P (insn) = 1;
8846 /* Mark constants in a window. */
8847 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
8849 if (GET_CODE (insn) != INSN)
8852 pattern = PATTERN (insn);
8853 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
8856 switch (XINT (pattern, 1))
8858 case UNSPECV_CONST2:
8859 case UNSPECV_CONST4:
8860 case UNSPECV_CONST8:
8861 XVECEXP (pattern, 0, 1) = const1_rtx;
8863 case UNSPECV_WINDOW_END:
8864 if (XVECEXP (pattern, 0, 0) == x)
8867 case UNSPECV_CONST_END:
8877 /* Return true if it's possible to redirect BRANCH1 to the destination
8878 of an unconditional jump BRANCH2. We only want to do this if the
8879 resulting branch will have a short displacement. */
8881 sh_can_redirect_branch (rtx branch1, rtx branch2)
8883 if (flag_expensive_optimizations && simplejump_p (branch2))
8885 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
8889 for (distance = 0, insn = NEXT_INSN (branch1);
8890 insn && distance < 256;
8891 insn = PREV_INSN (insn))
8896 distance += get_attr_length (insn);
8898 for (distance = 0, insn = NEXT_INSN (branch1);
8899 insn && distance < 256;
8900 insn = NEXT_INSN (insn))
8905 distance += get_attr_length (insn);
8911 /* Return nonzero if register old_reg can be renamed to register new_reg. */
8913 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
8914 unsigned int new_reg)
8916 /* Interrupt functions can only use registers that have already been
8917 saved by the prologue, even if they would normally be
8920 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
8926 /* Function to update the integer COST
8927 based on the relationship between INSN that is dependent on
8928 DEP_INSN through the dependence LINK. The default is to make no
8929 adjustment to COST. This can be used for example to specify to
8930 the scheduler that an output- or anti-dependence does not incur
8931 the same cost as a data-dependence. The return value should be
8932 the new value for COST. */
8934 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
8940 /* On SHmedia, if the dependence is an anti-dependence or
8941 output-dependence, there is no cost. */
8942 if (REG_NOTE_KIND (link) != 0)
8944 /* However, dependencies between target register loads and
8945 uses of the register in a subsequent block that are separated
8946 by a conditional branch are not modelled - we have to do with
8947 the anti-dependency between the target register load and the
8948 conditional branch that ends the current block. */
8949 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
8950 && GET_CODE (PATTERN (dep_insn)) == SET
8951 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
8952 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
8953 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
8955 int orig_cost = cost;
8956 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
8957 rtx target = ((! note
8958 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
8959 ? insn : JUMP_LABEL (insn));
8960 /* On the likely path, the branch costs 1, on the unlikely path,
8964 target = next_active_insn (target);
8965 while (target && ! flow_dependent_p (target, dep_insn)
8967 /* If two branches are executed in immediate succession, with the
8968 first branch properly predicted, this causes a stall at the
8969 second branch, hence we won't need the target for the
8970 second branch for two cycles after the launch of the first
8972 if (cost > orig_cost - 2)
8973 cost = orig_cost - 2;
8979 else if (get_attr_is_mac_media (insn)
8980 && get_attr_is_mac_media (dep_insn))
8983 else if (! reload_completed
8984 && GET_CODE (PATTERN (insn)) == SET
8985 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
8986 && GET_CODE (PATTERN (dep_insn)) == SET
8987 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
8990 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
8991 that is needed at the target. */
8992 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
8993 && ! flow_dependent_p (insn, dep_insn))
8996 else if (REG_NOTE_KIND (link) == 0)
8998 enum attr_type type;
9001 if (recog_memoized (insn) < 0
9002 || recog_memoized (dep_insn) < 0)
9005 dep_set = single_set (dep_insn);
9007 /* The latency that we specify in the scheduling description refers
9008 to the actual output, not to an auto-increment register; for that,
9009 the latency is one. */
9010 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9012 rtx set = single_set (insn);
9015 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9016 && (!MEM_P (SET_DEST (set))
9017 || !reg_mentioned_p (SET_DEST (dep_set),
9018 XEXP (SET_DEST (set), 0))))
9021 /* The only input for a call that is timing-critical is the
9022 function's address. */
9023 if (GET_CODE (insn) == CALL_INSN)
9025 rtx call = PATTERN (insn);
9027 if (GET_CODE (call) == PARALLEL)
9028 call = XVECEXP (call, 0 ,0);
9029 if (GET_CODE (call) == SET)
9030 call = SET_SRC (call);
9031 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
9032 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9033 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9034 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9035 cost -= TARGET_SH4_300 ? 3 : 6;
9037 /* Likewise, the most timing critical input for an sfuncs call
9038 is the function address. However, sfuncs typically start
9039 using their arguments pretty quickly.
9040 Assume a four cycle delay for SH4 before they are needed.
9041 Cached ST40-300 calls are quicker, so assume only a one
9043 ??? Maybe we should encode the delays till input registers
9044 are needed by sfuncs into the sfunc call insn. */
9045 /* All sfunc calls are parallels with at least four components.
9046 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9047 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9048 && XVECLEN (PATTERN (insn), 0) >= 4
9049 && (reg = sfunc_uses_reg (insn)))
9051 if (! reg_set_p (reg, dep_insn))
9052 cost -= TARGET_SH4_300 ? 1 : 4;
9054 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9056 enum attr_type dep_type = get_attr_type (dep_insn);
9058 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9060 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9061 && (type = get_attr_type (insn)) != TYPE_CALL
9062 && type != TYPE_SFUNC)
9064 /* When the preceding instruction loads the shift amount of
9065 the following SHAD/SHLD, the latency of the load is increased
9067 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9068 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
9069 && reg_overlap_mentioned_p (SET_DEST (dep_set),
9070 XEXP (SET_SRC (single_set (insn)),
9073 /* When an LS group instruction with a latency of less than
9074 3 cycles is followed by a double-precision floating-point
9075 instruction, FIPR, or FTRV, the latency of the first
9076 instruction is increased to 3 cycles. */
9078 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9079 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9081 /* The lsw register of a double-precision computation is ready one
9083 else if (reload_completed
9084 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9085 && (use_pat = single_set (insn))
9086 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9090 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9091 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9094 else if (TARGET_SH4_300)
9096 /* Stores need their input register two cycles later. */
9097 if (dep_set && cost >= 1
9098 && ((type = get_attr_type (insn)) == TYPE_STORE
9099 || type == TYPE_PSTORE
9100 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9102 rtx set = single_set (insn);
9104 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9105 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9108 /* But don't reduce the cost below 1 if the address depends
9109 on a side effect of dep_insn. */
9111 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9117 /* An anti-dependence penalty of two applies if the first insn is a double
9118 precision fadd / fsub / fmul. */
9119 else if (!TARGET_SH4_300
9120 && REG_NOTE_KIND (link) == REG_DEP_ANTI
9121 && recog_memoized (dep_insn) >= 0
9122 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9123 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9124 /* A lot of alleged anti-flow dependences are fake,
9125 so check this one is real. */
9126 && flow_dependent_p (dep_insn, insn))
9132 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9133 if DEP_INSN is anti-flow dependent on INSN. */
9135 flow_dependent_p (rtx insn, rtx dep_insn)
9137 rtx tmp = PATTERN (insn);
9139 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9140 return tmp == NULL_RTX;
9143 /* A helper function for flow_dependent_p called through note_stores. */
9145 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9147 rtx * pinsn = (rtx *) data;
9149 if (*pinsn && reg_referenced_p (x, *pinsn))
9153 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9154 'special function' patterns (type sfunc) that clobber pr, but that
9155 do not look like function calls to leaf_function_p. Hence we must
9156 do this extra check. */
9160 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9163 /* Return where to allocate pseudo for a given hard register initial
9166 sh_allocate_initial_value (rtx hard_reg)
9170 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
9172 if (current_function_is_leaf
9173 && ! sh_pr_n_sets ()
9174 && ! (TARGET_SHCOMPACT
9175 && ((current_function_args_info.call_cookie
9176 & ~ CALL_COOKIE_RET_TRAMP (1))
9177 || current_function_saves_all_registers)))
9180 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
9188 /* This function returns "2" to indicate dual issue for the SH4
9189 processor. To be used by the DFA pipeline description. */
9191 sh_issue_rate (void)
9193 if (TARGET_SUPERSCALAR)
9199 /* Functions for ready queue reordering for sched1. */
9201 /* Get weight for mode for a set x. */
9203 find_set_regmode_weight (rtx x, enum machine_mode mode)
9205 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9207 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9209 if (GET_CODE (SET_DEST (x)) == REG)
9211 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9221 /* Get regmode weight for insn. */
9223 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
9225 short reg_weight = 0;
9228 /* Increment weight for each register born here. */
9230 reg_weight += find_set_regmode_weight (x, mode);
9231 if (GET_CODE (x) == PARALLEL)
9234 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9236 x = XVECEXP (PATTERN (insn), 0, j);
9237 reg_weight += find_set_regmode_weight (x, mode);
9240 /* Decrement weight for each register that dies here. */
9241 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9243 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9245 rtx note = XEXP (x, 0);
9246 if (GET_CODE (note) == REG && GET_MODE (note) == mode)
9253 /* Calculate regmode weights for all insns of a basic block. */
9255 find_regmode_weight (basic_block b, enum machine_mode mode)
9257 rtx insn, next_tail, head, tail;
9259 get_ebb_head_tail (b, b, &head, &tail);
9260 next_tail = NEXT_INSN (tail);
9262 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9264 /* Handle register life information. */
9269 INSN_REGMODE_WEIGHT (insn, mode) =
9270 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
9271 else if (mode == SImode)
9272 INSN_REGMODE_WEIGHT (insn, mode) =
9273 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
9277 /* Comparison function for ready queue sorting. */
9279 rank_for_reorder (const void *x, const void *y)
9281 rtx tmp = *(const rtx *) y;
9282 rtx tmp2 = *(const rtx *) x;
9284 /* The insn in a schedule group should be issued the first. */
9285 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
9286 return SCHED_GROUP_P (tmp2) ? 1 : -1;
9288 /* If insns are equally good, sort by INSN_LUID (original insn order), This
9289 minimizes instruction movement, thus minimizing sched's effect on
9290 register pressure. */
9291 return INSN_LUID (tmp) - INSN_LUID (tmp2);
9294 /* Resort the array A in which only element at index N may be out of order. */
9296 swap_reorder (rtx *a, int n)
9298 rtx insn = a[n - 1];
9301 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
9309 #define SCHED_REORDER(READY, N_READY) \
9312 if ((N_READY) == 2) \
9313 swap_reorder (READY, N_READY); \
9314 else if ((N_READY) > 2) \
9315 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
9319 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
9322 ready_reorder (rtx *ready, int nready)
9324 SCHED_REORDER (ready, nready);
9327 /* Count life regions of r0 for a block. */
9329 find_r0_life_regions (basic_block b)
9338 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
9351 r0_reg = gen_rtx_REG (SImode, R0_REG);
9356 if (find_regno_note (insn, REG_DEAD, R0_REG))
9362 && (pset = single_set (insn))
9363 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
9364 && !find_regno_note (insn, REG_UNUSED, R0_REG))
9372 insn = NEXT_INSN (insn);
9377 /* Calculate regmode weights for all insns of all basic block. */
9379 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
9380 int verbose ATTRIBUTE_UNUSED,
9385 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
9386 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
9387 r0_life_regions = 0;
9389 FOR_EACH_BB_REVERSE (b)
9391 find_regmode_weight (b, SImode);
9392 find_regmode_weight (b, SFmode);
9393 if (!reload_completed)
9394 r0_life_regions += find_r0_life_regions (b);
9397 CURR_REGMODE_PRESSURE (SImode) = 0;
9398 CURR_REGMODE_PRESSURE (SFmode) = 0;
9404 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
9405 int verbose ATTRIBUTE_UNUSED)
9407 if (regmode_weight[0])
9409 free (regmode_weight[0]);
9410 regmode_weight[0] = NULL;
9412 if (regmode_weight[1])
9414 free (regmode_weight[1]);
9415 regmode_weight[1] = NULL;
9419 /* The scalar modes supported differs from the default version in TImode
9420 for 32-bit SHMEDIA. */
9422 sh_scalar_mode_supported_p (enum machine_mode mode)
9424 if (TARGET_SHMEDIA32 && mode == TImode)
9427 return default_scalar_mode_supported_p (mode);
9430 /* Cache the can_issue_more so that we can return it from reorder2. Also,
9431 keep count of register pressures on SImode and SFmode. */
9433 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
9434 int sched_verbose ATTRIBUTE_UNUSED,
9438 if (GET_CODE (PATTERN (insn)) != USE
9439 && GET_CODE (PATTERN (insn)) != CLOBBER)
9440 cached_can_issue_more = can_issue_more - 1;
9442 cached_can_issue_more = can_issue_more;
9444 if (reload_completed)
9445 return cached_can_issue_more;
9447 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
9448 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
9450 return cached_can_issue_more;
9454 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
9455 int verbose ATTRIBUTE_UNUSED,
9456 int veclen ATTRIBUTE_UNUSED)
9458 CURR_REGMODE_PRESSURE (SImode) = 0;
9459 CURR_REGMODE_PRESSURE (SFmode) = 0;
9462 /* Some magic numbers. */
9463 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9464 functions that already have high pressure on r0. */
9465 #define R0_MAX_LIFE_REGIONS 2
9466 /* Register Pressure thresholds for SImode and SFmode registers. */
9467 #define SIMODE_MAX_WEIGHT 5
9468 #define SFMODE_MAX_WEIGHT 10
9470 /* Return true if the pressure is high for MODE. */
9472 high_pressure (enum machine_mode mode)
9474 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9475 functions that already have high pressure on r0. */
9476 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
9480 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
9482 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
9485 /* Reorder ready queue if register pressure is high. */
9487 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
9488 int sched_verbose ATTRIBUTE_UNUSED,
9491 int clock_var ATTRIBUTE_UNUSED)
9493 if (reload_completed)
9494 return sh_issue_rate ();
9496 if (high_pressure (SFmode) || high_pressure (SImode))
9498 ready_reorder (ready, *n_readyp);
9501 return sh_issue_rate ();
9504 /* Skip cycles if the current register pressure is high. */
9506 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
9507 int sched_verbose ATTRIBUTE_UNUSED,
9508 rtx *ready ATTRIBUTE_UNUSED,
9509 int *n_readyp ATTRIBUTE_UNUSED,
9510 int clock_var ATTRIBUTE_UNUSED)
9512 if (reload_completed)
9513 return cached_can_issue_more;
9515 if (high_pressure(SFmode) || high_pressure (SImode))
9518 return cached_can_issue_more;
9521 /* Skip cycles without sorting the ready queue. This will move insn from
9522 Q->R. If this is the last cycle we are skipping; allow sorting of ready
9523 queue by sh_reorder. */
9525 /* Generally, skipping these many cycles are sufficient for all insns to move
9530 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
9531 int sched_verbose ATTRIBUTE_UNUSED,
9532 rtx insn ATTRIBUTE_UNUSED,
9537 if (reload_completed)
9542 if ((clock_var - last_clock_var) < MAX_SKIPS)
9547 /* If this is the last cycle we are skipping, allow reordering of R. */
9548 if ((clock_var - last_clock_var) == MAX_SKIPS)
9560 /* SHmedia requires registers for branches, so we can't generate new
9561 branches past reload. */
9563 sh_cannot_modify_jumps_p (void)
9565 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
9569 sh_target_reg_class (void)
9571 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
9575 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
9582 if (! shmedia_space_reserved_for_target_registers)
9584 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
9586 if (calc_live_regs (&dummy) >= 6 * 8)
9592 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
9594 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
9598 On the SH1..SH4, the trampoline looks like
9599 2 0002 D202 mov.l l2,r2
9600 1 0000 D301 mov.l l1,r3
9603 5 0008 00000000 l1: .long area
9604 6 000c 00000000 l2: .long function
9606 SH5 (compact) uses r1 instead of r3 for the static chain. */
9609 /* Emit RTL insns to initialize the variable parts of a trampoline.
9610 FNADDR is an RTX for the address of the function's pure code.
9611 CXT is an RTX for the static chain value for the function. */
9614 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
9616 rtx tramp_mem = gen_frame_mem (BLKmode, tramp);
9618 if (TARGET_SHMEDIA64)
9623 rtx movi1 = GEN_INT (0xcc000010);
9624 rtx shori1 = GEN_INT (0xc8000010);
9627 /* The following trampoline works within a +- 128 KB range for cxt:
9628 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
9629 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
9630 gettr tr1,r1; blink tr0,r63 */
9631 /* Address rounding makes it hard to compute the exact bounds of the
9632 offset for this trampoline, but we have a rather generous offset
9633 range, so frame_offset should do fine as an upper bound. */
9634 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
9636 /* ??? could optimize this trampoline initialization
9637 by writing DImode words with two insns each. */
9638 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
9639 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
9640 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
9641 insn = gen_rtx_AND (DImode, insn, mask);
9642 /* Or in ptb/u .,tr1 pattern */
9643 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
9644 insn = force_operand (insn, NULL_RTX);
9645 insn = gen_lowpart (SImode, insn);
9646 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
9647 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
9648 insn = gen_rtx_AND (DImode, insn, mask);
9649 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
9650 insn = gen_lowpart (SImode, insn);
9651 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
9652 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
9653 insn = gen_rtx_AND (DImode, insn, mask);
9654 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9655 insn = gen_lowpart (SImode, insn);
9656 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
9657 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
9658 insn = gen_rtx_AND (DImode, insn, mask);
9659 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9660 insn = gen_lowpart (SImode, insn);
9661 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
9662 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
9663 insn = gen_rtx_AND (DImode, insn, mask);
9664 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9665 insn = gen_lowpart (SImode, insn);
9666 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
9667 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
9668 GEN_INT (0x6bf10600));
9669 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
9670 GEN_INT (0x4415fc10));
9671 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
9672 GEN_INT (0x4401fff0));
9673 emit_insn (gen_ic_invalidate_line (tramp));
9676 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
9677 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
9679 tramp_templ = gen_datalabel_ref (tramp_templ);
9681 src = gen_const_mem (BLKmode, tramp_templ);
9682 set_mem_align (dst, 256);
9683 set_mem_align (src, 64);
9684 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
9686 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
9687 emit_move_insn (adjust_address (tramp_mem, Pmode,
9688 fixed_len + GET_MODE_SIZE (Pmode)),
9690 emit_insn (gen_ic_invalidate_line (tramp));
9693 else if (TARGET_SHMEDIA)
9695 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
9696 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
9697 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
9698 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
9699 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
9700 rotated 10 right, and higher 16 bit of every 32 selected. */
9702 = force_reg (V2HImode, (simplify_gen_subreg
9703 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
9704 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
9705 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
9707 tramp = force_reg (Pmode, tramp);
9708 fnaddr = force_reg (SImode, fnaddr);
9709 cxt = force_reg (SImode, cxt);
9710 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
9711 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
9713 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
9714 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
9715 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
9716 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
9717 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
9718 gen_rtx_SUBREG (V2HImode, cxt, 0),
9720 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
9721 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
9722 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
9723 if (TARGET_LITTLE_ENDIAN)
9725 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
9726 emit_insn (gen_mextr4 (quad2, cxtload, blink));
9730 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
9731 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
9733 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
9734 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
9735 emit_insn (gen_ic_invalidate_line (tramp));
9738 else if (TARGET_SHCOMPACT)
9740 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
9743 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
9744 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
9746 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
9747 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
9749 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
9750 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
9753 if (!TARGET_INLINE_IC_INVALIDATE
9754 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
9755 emit_library_call (function_symbol (NULL, "__ic_invalidate",
9757 0, VOIDmode, 1, tramp, SImode);
9759 emit_insn (gen_ic_invalidate_line (tramp));
9763 /* FIXME: This is overly conservative. A SHcompact function that
9764 receives arguments ``by reference'' will have them stored in its
9765 own stack frame, so it must not pass pointers or references to
9766 these arguments to other functions by means of sibling calls. */
9767 /* If PIC, we cannot make sibling calls to global functions
9768 because the PLT requires r12 to be live. */
9770 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
9773 && (! TARGET_SHCOMPACT
9774 || current_function_args_info.stack_regs == 0)
9775 && ! sh_cfun_interrupt_handler_p ()
9777 || (decl && ! TREE_PUBLIC (decl))
9778 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
9781 /* Machine specific built-in functions. */
9783 struct builtin_description
9785 const enum insn_code icode;
9786 const char *const name;
9790 /* describe number and signedness of arguments; arg[0] == result
9791 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
9792 /* 9: 64-bit pointer, 10: 32-bit pointer */
9793 static const char signature_args[][4] =
9795 #define SH_BLTIN_V2SI2 0
9797 #define SH_BLTIN_V4HI2 1
9799 #define SH_BLTIN_V2SI3 2
9801 #define SH_BLTIN_V4HI3 3
9803 #define SH_BLTIN_V8QI3 4
9805 #define SH_BLTIN_MAC_HISI 5
9807 #define SH_BLTIN_SH_HI 6
9809 #define SH_BLTIN_SH_SI 7
9811 #define SH_BLTIN_V4HI2V2SI 8
9813 #define SH_BLTIN_V4HI2V8QI 9
9815 #define SH_BLTIN_SISF 10
9817 #define SH_BLTIN_LDUA_L 11
9819 #define SH_BLTIN_LDUA_Q 12
9821 #define SH_BLTIN_STUA_L 13
9823 #define SH_BLTIN_STUA_Q 14
9825 #define SH_BLTIN_LDUA_L64 15
9827 #define SH_BLTIN_LDUA_Q64 16
9829 #define SH_BLTIN_STUA_L64 17
9831 #define SH_BLTIN_STUA_Q64 18
9833 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
9834 #define SH_BLTIN_2 19
9835 #define SH_BLTIN_SU 19
9837 #define SH_BLTIN_3 20
9838 #define SH_BLTIN_SUS 20
9840 #define SH_BLTIN_PSSV 21
9842 #define SH_BLTIN_XXUU 22
9843 #define SH_BLTIN_UUUU 22
9845 #define SH_BLTIN_PV 23
9848 /* mcmv: operands considered unsigned. */
9849 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
9850 /* mperm: control value considered unsigned int. */
9851 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
9852 /* mshards_q: returns signed short. */
9853 /* nsb: takes long long arg, returns unsigned char. */
9854 static const struct builtin_description bdesc[] =
9856 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
9857 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
9858 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
9859 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
9860 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
9861 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
9862 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
9863 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
9864 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
9865 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
9866 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
9867 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
9868 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
9869 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
9870 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
9871 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
9872 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
9873 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
9874 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 },
9875 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 },
9876 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 },
9877 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 },
9878 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 },
9879 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 },
9880 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 },
9881 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
9882 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
9883 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
9884 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
9885 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
9886 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
9887 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
9888 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
9889 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
9890 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
9891 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
9892 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
9893 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
9894 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
9895 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
9896 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
9897 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
9898 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
9899 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
9900 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
9901 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
9902 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
9903 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
9904 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
9905 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
9906 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
9907 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
9908 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
9909 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
9910 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
9911 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
9912 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
9913 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
9914 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
9915 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
9916 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
9917 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 },
9918 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 },
9919 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 },
9920 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
9921 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
9922 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
9923 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
9924 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
9925 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
9926 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
9927 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
9928 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
9929 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 },
9930 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 },
9931 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 },
9932 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 },
9933 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 },
9934 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 },
9935 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 },
9936 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 },
9937 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
9938 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
9939 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
9943 sh_media_init_builtins (void)
9945 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
9946 const struct builtin_description *d;
9948 memset (shared, 0, sizeof shared);
9949 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
9951 tree type, arg_type = 0;
9952 int signature = d->signature;
9955 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
9956 type = shared[signature];
9959 int has_result = signature_args[signature][0] != 0;
9961 if ((signature_args[signature][1] & 8)
9962 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
9963 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
9965 if (! TARGET_FPU_ANY
9966 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
9968 type = void_list_node;
9971 int arg = signature_args[signature][i];
9972 int opno = i - 1 + has_result;
9975 arg_type = ptr_type_node;
9977 arg_type = (*lang_hooks.types.type_for_mode)
9978 (insn_data[d->icode].operand[opno].mode,
9983 arg_type = void_type_node;
9986 type = tree_cons (NULL_TREE, arg_type, type);
9988 type = build_function_type (arg_type, type);
9989 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
9990 shared[signature] = type;
9992 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
9997 /* Implements target hook vector_mode_supported_p. */
9999 sh_vector_mode_supported_p (enum machine_mode mode)
10002 && ((mode == V2SFmode)
10003 || (mode == V4SFmode)
10004 || (mode == V16SFmode)))
10007 else if (TARGET_SHMEDIA
10008 && ((mode == V8QImode)
10009 || (mode == V2HImode)
10010 || (mode == V4HImode)
10011 || (mode == V2SImode)))
10017 /* Implements target hook dwarf_calling_convention. Return an enum
10018 of dwarf_calling_convention. */
10020 sh_dwarf_calling_convention (const_tree func)
10022 if (sh_attr_renesas_p (func))
10023 return DW_CC_GNU_renesas_sh;
10025 return DW_CC_normal;
10029 sh_init_builtins (void)
10031 if (TARGET_SHMEDIA)
10032 sh_media_init_builtins ();
10035 /* Expand an expression EXP that calls a built-in function,
10036 with result going to TARGET if that's convenient
10037 (and in mode MODE if that's convenient).
10038 SUBTARGET may be used as the target for computing one of EXP's operands.
10039 IGNORE is nonzero if the value is to be ignored. */
10042 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10043 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
10045 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10046 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10047 const struct builtin_description *d = &bdesc[fcode];
10048 enum insn_code icode = d->icode;
10049 int signature = d->signature;
10050 enum machine_mode tmode = VOIDmode;
10055 if (signature_args[signature][0])
10060 tmode = insn_data[icode].operand[0].mode;
10062 || GET_MODE (target) != tmode
10063 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10064 target = gen_reg_rtx (tmode);
10065 op[nop++] = target;
10070 for (i = 1; i <= 3; i++, nop++)
10073 enum machine_mode opmode, argmode;
10076 if (! signature_args[signature][i])
10078 arg = CALL_EXPR_ARG (exp, i - 1);
10079 if (arg == error_mark_node)
10081 if (signature_args[signature][i] & 8)
10084 optype = ptr_type_node;
10088 opmode = insn_data[icode].operand[nop].mode;
10089 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10091 argmode = TYPE_MODE (TREE_TYPE (arg));
10092 if (argmode != opmode)
10093 arg = build1 (NOP_EXPR, optype, arg);
10094 op[nop] = expand_expr (arg, NULL_RTX, opmode, 0);
10095 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10096 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10102 pat = (*insn_data[d->icode].genfun) (op[0]);
10105 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10108 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10111 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10114 gcc_unreachable ();
10123 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
10125 rtx sel0 = const0_rtx;
10126 rtx sel1 = const1_rtx;
10127 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
10128 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
10130 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
10131 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
10135 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
10137 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
10139 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
10140 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
10143 /* Return the class of registers for which a mode change from FROM to TO
10146 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
10147 enum reg_class class)
10149 /* We want to enable the use of SUBREGs as a means to
10150 VEC_SELECT a single element of a vector. */
10151 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
10152 return (reg_classes_intersect_p (GENERAL_REGS, class));
10154 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10156 if (TARGET_LITTLE_ENDIAN)
10158 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
10159 return reg_classes_intersect_p (DF_REGS, class);
10163 if (GET_MODE_SIZE (from) < 8)
10164 return reg_classes_intersect_p (DF_HI_REGS, class);
10171 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10172 that label is used. */
10175 sh_mark_label (rtx address, int nuses)
10177 if (GOTOFF_P (address))
10179 /* Extract the label or symbol. */
10180 address = XEXP (address, 0);
10181 if (GET_CODE (address) == PLUS)
10182 address = XEXP (address, 0);
10183 address = XVECEXP (address, 0, 0);
10185 if (GET_CODE (address) == LABEL_REF
10186 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
10187 LABEL_NUSES (XEXP (address, 0)) += nuses;
10190 /* Compute extra cost of moving data between one register class
10193 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10194 uses this information. Hence, the general register <-> floating point
10195 register information here is not used for SFmode. */
10198 sh_register_move_cost (enum machine_mode mode,
10199 enum reg_class srcclass, enum reg_class dstclass)
10201 if (dstclass == T_REGS || dstclass == PR_REGS)
10204 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
10207 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
10208 && REGCLASS_HAS_FP_REG (srcclass)
10209 && REGCLASS_HAS_FP_REG (dstclass))
10212 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
10213 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
10215 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
10216 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
10219 if ((REGCLASS_HAS_FP_REG (dstclass)
10220 && REGCLASS_HAS_GENERAL_REG (srcclass))
10221 || (REGCLASS_HAS_GENERAL_REG (dstclass)
10222 && REGCLASS_HAS_FP_REG (srcclass)))
10223 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
10224 * ((GET_MODE_SIZE (mode) + 7) / 8U));
10226 if ((dstclass == FPUL_REGS
10227 && REGCLASS_HAS_GENERAL_REG (srcclass))
10228 || (srcclass == FPUL_REGS
10229 && REGCLASS_HAS_GENERAL_REG (dstclass)))
10232 if ((dstclass == FPUL_REGS
10233 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
10234 || (srcclass == FPUL_REGS
10235 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
10238 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10239 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10242 /* ??? ptabs faults on (value & 0x3) == 0x3 */
10244 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
10246 if (sh_gettrcost >= 0)
10247 return sh_gettrcost;
10248 else if (!TARGET_PT_FIXED)
10252 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10253 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10258 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
10259 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
10260 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
10262 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
10265 static rtx emit_load_ptr (rtx, rtx);
10268 emit_load_ptr (rtx reg, rtx addr)
10270 rtx mem = gen_const_mem (ptr_mode, addr);
10272 if (Pmode != ptr_mode)
10273 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
10274 return emit_move_insn (reg, mem);
10278 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
10279 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10282 CUMULATIVE_ARGS cum;
10283 int structure_value_byref = 0;
10284 rtx this, this_value, sibcall, insns, funexp;
10285 tree funtype = TREE_TYPE (function);
10286 int simple_add = CONST_OK_FOR_ADD (delta);
10288 rtx scratch0, scratch1, scratch2;
10291 reload_completed = 1;
10292 epilogue_completed = 1;
10293 current_function_uses_only_leaf_regs = 1;
10295 emit_note (NOTE_INSN_PROLOGUE_END);
10297 /* Find the "this" pointer. We have such a wide range of ABIs for the
10298 SH that it's best to do this completely machine independently.
10299 "this" is passed as first argument, unless a structure return pointer
10300 comes first, in which case "this" comes second. */
10301 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
10302 #ifndef PCC_STATIC_STRUCT_RETURN
10303 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10304 structure_value_byref = 1;
10305 #endif /* not PCC_STATIC_STRUCT_RETURN */
10306 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
10308 tree ptype = build_pointer_type (TREE_TYPE (funtype));
10310 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
10312 this = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
10314 /* For SHcompact, we only have r0 for a scratch register: r1 is the
10315 static chain pointer (even if you can't have nested virtual functions
10316 right now, someone might implement them sometime), and the rest of the
10317 registers are used for argument passing, are callee-saved, or reserved. */
10318 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
10319 -ffixed-reg has been used. */
10320 if (! call_used_regs[0] || fixed_regs[0])
10321 error ("r0 needs to be available as a call-clobbered register");
10322 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
10325 if (call_used_regs[1] && ! fixed_regs[1])
10326 scratch1 = gen_rtx_REG (ptr_mode, 1);
10327 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
10328 pointing where to return struct values. */
10329 if (call_used_regs[3] && ! fixed_regs[3])
10330 scratch2 = gen_rtx_REG (Pmode, 3);
10332 else if (TARGET_SHMEDIA)
10334 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
10335 if (i != REGNO (scratch0) &&
10336 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
10338 scratch1 = gen_rtx_REG (ptr_mode, i);
10341 if (scratch1 == scratch0)
10342 error ("Need a second call-clobbered general purpose register");
10343 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
10344 if (call_used_regs[i] && ! fixed_regs[i])
10346 scratch2 = gen_rtx_REG (Pmode, i);
10349 if (scratch2 == scratch0)
10350 error ("Need a call-clobbered target register");
10353 this_value = plus_constant (this, delta);
10355 && (simple_add || scratch0 != scratch1)
10356 && strict_memory_address_p (ptr_mode, this_value))
10358 emit_load_ptr (scratch0, this_value);
10363 ; /* Do nothing. */
10364 else if (simple_add)
10365 emit_move_insn (this, this_value);
10368 emit_move_insn (scratch1, GEN_INT (delta));
10369 emit_insn (gen_add2_insn (this, scratch1));
10377 emit_load_ptr (scratch0, this);
10379 offset_addr = plus_constant (scratch0, vcall_offset);
10380 if (strict_memory_address_p (ptr_mode, offset_addr))
10381 ; /* Do nothing. */
10382 else if (! TARGET_SH5 && scratch0 != scratch1)
10384 /* scratch0 != scratch1, and we have indexed loads. Get better
10385 schedule by loading the offset into r1 and using an indexed
10386 load - then the load of r1 can issue before the load from
10387 (this + delta) finishes. */
10388 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10389 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
10391 else if (CONST_OK_FOR_ADD (vcall_offset))
10393 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
10394 offset_addr = scratch0;
10396 else if (scratch0 != scratch1)
10398 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10399 emit_insn (gen_add2_insn (scratch0, scratch1));
10400 offset_addr = scratch0;
10403 gcc_unreachable (); /* FIXME */
10404 emit_load_ptr (scratch0, offset_addr);
10406 if (Pmode != ptr_mode)
10407 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
10408 emit_insn (gen_add2_insn (this, scratch0));
10411 /* Generate a tail call to the target function. */
10412 if (! TREE_USED (function))
10414 assemble_external (function);
10415 TREE_USED (function) = 1;
10417 funexp = XEXP (DECL_RTL (function), 0);
10418 /* If the function is overridden, so is the thunk, hence we don't
10419 need GOT addressing even if this is a public symbol. */
10421 if (TARGET_SH1 && ! flag_weak)
10422 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
10425 if (TARGET_SH2 && flag_pic)
10427 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
10428 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
10432 if (TARGET_SHMEDIA && flag_pic)
10434 funexp = gen_sym2PIC (funexp);
10435 PUT_MODE (funexp, Pmode);
10437 emit_move_insn (scratch2, funexp);
10438 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
10439 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
10441 sibcall = emit_call_insn (sibcall);
10442 SIBLING_CALL_P (sibcall) = 1;
10443 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this);
10446 /* Run just enough of rest_of_compilation to do scheduling and get
10447 the insns emitted. Note that use_thunk calls
10448 assemble_start_function and assemble_end_function. */
10450 insn_locators_alloc ();
10451 insns = get_insns ();
10456 /* Initialize the bitmap obstacks. */
10457 bitmap_obstack_initialize (NULL);
10458 bitmap_obstack_initialize (®_obstack);
10461 rtl_register_cfg_hooks ();
10462 init_rtl_bb_info (ENTRY_BLOCK_PTR);
10463 init_rtl_bb_info (EXIT_BLOCK_PTR);
10464 ENTRY_BLOCK_PTR->flags |= BB_RTL;
10465 EXIT_BLOCK_PTR->flags |= BB_RTL;
10466 find_basic_blocks (insns);
10468 if (flag_schedule_insns_after_reload)
10470 life_analysis (PROP_FINAL);
10472 split_all_insns (1);
10476 /* We must split jmp insn in PIC case. */
10478 split_all_insns_noflow ();
10485 split_all_insns_noflow ();
10491 if (optimize > 0 && flag_delayed_branch)
10492 dbr_schedule (insns);
10494 shorten_branches (insns);
10495 final_start_function (insns, file, 1);
10496 final (insns, file, 1);
10497 final_end_function ();
10499 reload_completed = 0;
10500 epilogue_completed = 0;
10504 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
10508 /* If this is not an ordinary function, the name usually comes from a
10509 string literal or an sprintf buffer. Make sure we use the same
10510 string consistently, so that cse will be able to unify address loads. */
10511 if (kind != FUNCTION_ORDINARY)
10512 name = IDENTIFIER_POINTER (get_identifier (name));
10513 sym = gen_rtx_SYMBOL_REF (Pmode, name);
10514 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
10518 case FUNCTION_ORDINARY:
10522 rtx reg = target ? target : gen_reg_rtx (Pmode);
10524 emit_insn (gen_symGOT2reg (reg, sym));
10530 /* ??? To allow cse to work, we use GOTOFF relocations.
10531 we could add combiner patterns to transform this into
10532 straight pc-relative calls with sym2PIC / bsrf when
10533 label load and function call are still 1:1 and in the
10534 same basic block during combine. */
10535 rtx reg = target ? target : gen_reg_rtx (Pmode);
10537 emit_insn (gen_symGOTOFF2reg (reg, sym));
10542 if (target && sym != target)
10544 emit_move_insn (target, sym);
10550 /* Find the number of a general purpose register in S. */
10552 scavenge_reg (HARD_REG_SET *s)
10555 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
10556 if (TEST_HARD_REG_BIT (*s, r))
10562 sh_get_pr_initial_val (void)
10566 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
10567 PR register on SHcompact, because it might be clobbered by the prologue.
10568 We check first if that is known to be the case. */
10569 if (TARGET_SHCOMPACT
10570 && ((current_function_args_info.call_cookie
10571 & ~ CALL_COOKIE_RET_TRAMP (1))
10572 || current_function_saves_all_registers))
10573 return gen_frame_mem (SImode, return_address_pointer_rtx);
10575 /* If we haven't finished rtl generation, there might be a nonlocal label
10576 that we haven't seen yet.
10577 ??? get_hard_reg_initial_val fails if it is called after register
10578 allocation has started, unless it has been called before for the
10579 same register. And even then, we end in trouble if we didn't use
10580 the register in the same basic block before. So call
10581 get_hard_reg_initial_val now and wrap it in an unspec if we might
10582 need to replace it. */
10583 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
10584 combine can put the pseudo returned by get_hard_reg_initial_val into
10585 instructions that need a general purpose registers, which will fail to
10586 be recognized when the pseudo becomes allocated to PR. */
10588 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
10590 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
10595 sh_expand_t_scc (enum rtx_code code, rtx target)
10597 rtx result = target;
10600 if (GET_CODE (sh_compare_op0) != REG || REGNO (sh_compare_op0) != T_REG
10601 || GET_CODE (sh_compare_op1) != CONST_INT)
10603 if (GET_CODE (result) != REG)
10604 result = gen_reg_rtx (SImode);
10605 val = INTVAL (sh_compare_op1);
10606 if ((code == EQ && val == 1) || (code == NE && val == 0))
10607 emit_insn (gen_movt (result));
10608 else if ((code == EQ && val == 0) || (code == NE && val == 1))
10610 emit_insn (gen_rtx_CLOBBER (VOIDmode, result));
10611 emit_insn (gen_subc (result, result, result));
10612 emit_insn (gen_addsi3 (result, result, const1_rtx));
10614 else if (code == EQ || code == NE)
10615 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
10618 if (result != target)
10619 emit_move_insn (target, result);
10623 /* INSN is an sfunc; return the rtx that describes the address used. */
10625 extract_sfunc_addr (rtx insn)
10627 rtx pattern, part = NULL_RTX;
10630 pattern = PATTERN (insn);
10631 len = XVECLEN (pattern, 0);
10632 for (i = 0; i < len; i++)
10634 part = XVECEXP (pattern, 0, i);
10635 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
10636 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
10637 return XEXP (part, 0);
10639 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
10640 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
10643 /* Verify that the register in use_sfunc_addr still agrees with the address
10644 used in the sfunc. This prevents fill_slots_from_thread from changing
10646 INSN is the use_sfunc_addr instruction, and REG is the register it
10649 check_use_sfunc_addr (rtx insn, rtx reg)
10651 /* Search for the sfunc. It should really come right after INSN. */
10652 while ((insn = NEXT_INSN (insn)))
10654 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN)
10656 if (! INSN_P (insn))
10659 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
10660 insn = XVECEXP (PATTERN (insn), 0, 0);
10661 if (GET_CODE (PATTERN (insn)) != PARALLEL
10662 || get_attr_type (insn) != TYPE_SFUNC)
10664 return rtx_equal_p (extract_sfunc_addr (insn), reg);
10666 gcc_unreachable ();
10669 /* This function returns a constant rtx that represents pi / 2**15 in
10670 SFmode. it's used to scale SFmode angles, in radians, to a
10671 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
10672 maps to 0x10000). */
10674 static GTY(()) rtx sh_fsca_sf2int_rtx;
10677 sh_fsca_sf2int (void)
10679 if (! sh_fsca_sf2int_rtx)
10681 REAL_VALUE_TYPE rv;
10683 real_from_string (&rv, "10430.378350470453");
10684 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
10687 return sh_fsca_sf2int_rtx;
10690 /* This function returns a constant rtx that represents pi / 2**15 in
10691 DFmode. it's used to scale DFmode angles, in radians, to a
10692 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
10693 maps to 0x10000). */
10695 static GTY(()) rtx sh_fsca_df2int_rtx;
10698 sh_fsca_df2int (void)
10700 if (! sh_fsca_df2int_rtx)
10702 REAL_VALUE_TYPE rv;
10704 real_from_string (&rv, "10430.378350470453");
10705 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
10708 return sh_fsca_df2int_rtx;
10711 /* This function returns a constant rtx that represents 2**15 / pi in
10712 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
10713 of a full circle back to a SFmode value, i.e., 0x10000 maps to
10716 static GTY(()) rtx sh_fsca_int2sf_rtx;
10719 sh_fsca_int2sf (void)
10721 if (! sh_fsca_int2sf_rtx)
10723 REAL_VALUE_TYPE rv;
10725 real_from_string (&rv, "9.587379924285257e-5");
10726 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
10729 return sh_fsca_int2sf_rtx;
10732 /* Initialize the CUMULATIVE_ARGS structure. */
10735 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
10737 rtx libname ATTRIBUTE_UNUSED,
10739 signed int n_named_args,
10740 enum machine_mode mode)
10742 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
10743 pcum->free_single_fp_reg = 0;
10744 pcum->stack_regs = 0;
10745 pcum->byref_regs = 0;
10747 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
10749 /* XXX - Should we check TARGET_HITACHI here ??? */
10750 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
10754 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
10755 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
10756 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
10757 pcum->arg_count [(int) SH_ARG_INT]
10758 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
10761 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
10762 && pcum->arg_count [(int) SH_ARG_INT] == 0
10763 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
10764 ? int_size_in_bytes (TREE_TYPE (fntype))
10765 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
10766 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
10767 == FIRST_RET_REG));
10771 pcum->arg_count [(int) SH_ARG_INT] = 0;
10772 pcum->prototype_p = FALSE;
10773 if (mode != VOIDmode)
10775 pcum->call_cookie =
10776 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
10777 && GET_MODE_SIZE (mode) > 4
10778 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
10780 /* If the default ABI is the Renesas ABI then all library
10781 calls must assume that the library will be using the
10782 Renesas ABI. So if the function would return its result
10783 in memory then we must force the address of this memory
10784 block onto the stack. Ideally we would like to call
10785 targetm.calls.return_in_memory() here but we do not have
10786 the TYPE or the FNDECL available so we synthesize the
10787 contents of that function as best we can. */
10789 (TARGET_DEFAULT & MASK_HITACHI)
10790 && (mode == BLKmode
10791 || (GET_MODE_SIZE (mode) > 4
10792 && !(mode == DFmode
10793 && TARGET_FPU_DOUBLE)));
10797 pcum->call_cookie = 0;
10798 pcum->force_mem = FALSE;
10803 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
10804 not enter into CONST_DOUBLE for the replace.
10806 Note that copying is not done so X must not be shared unless all copies
10807 are to be modified.
10809 This is like replace_rtx, except that we operate on N_REPLACEMENTS
10810 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
10811 replacements[n*2+1] - and that we take mode changes into account.
10813 If a replacement is ambiguous, return NULL_RTX.
10815 If MODIFY is zero, don't modify any rtl in place,
10816 just return zero or nonzero for failure / success. */
10819 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
10824 /* The following prevents loops occurrence when we change MEM in
10825 CONST_DOUBLE onto the same CONST_DOUBLE. */
10826 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
10829 for (i = n_replacements - 1; i >= 0 ; i--)
10830 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
10831 return replacements[i*2+1];
10833 /* Allow this function to make replacements in EXPR_LISTs. */
10837 if (GET_CODE (x) == SUBREG)
10839 rtx new = replace_n_hard_rtx (SUBREG_REG (x), replacements,
10840 n_replacements, modify);
10842 if (GET_CODE (new) == CONST_INT)
10844 x = simplify_subreg (GET_MODE (x), new,
10845 GET_MODE (SUBREG_REG (x)),
10851 SUBREG_REG (x) = new;
10855 else if (GET_CODE (x) == REG)
10857 unsigned regno = REGNO (x);
10858 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
10859 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10860 rtx result = NULL_RTX;
10862 for (i = n_replacements - 1; i >= 0; i--)
10864 rtx from = replacements[i*2];
10865 rtx to = replacements[i*2+1];
10866 unsigned from_regno, from_nregs, to_regno, new_regno;
10868 if (GET_CODE (from) != REG)
10870 from_regno = REGNO (from);
10871 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
10872 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
10873 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
10875 if (regno < from_regno
10876 || regno + nregs > from_regno + nregs
10877 || GET_CODE (to) != REG
10880 to_regno = REGNO (to);
10881 if (to_regno < FIRST_PSEUDO_REGISTER)
10883 new_regno = regno + to_regno - from_regno;
10884 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
10887 result = gen_rtx_REG (GET_MODE (x), new_regno);
10889 else if (GET_MODE (x) <= GET_MODE (to))
10890 result = gen_lowpart_common (GET_MODE (x), to);
10892 result = gen_lowpart_SUBREG (GET_MODE (x), to);
10895 return result ? result : x;
10897 else if (GET_CODE (x) == ZERO_EXTEND)
10899 rtx new = replace_n_hard_rtx (XEXP (x, 0), replacements,
10900 n_replacements, modify);
10902 if (GET_CODE (new) == CONST_INT)
10904 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
10905 new, GET_MODE (XEXP (x, 0)));
10915 fmt = GET_RTX_FORMAT (GET_CODE (x));
10916 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
10922 new = replace_n_hard_rtx (XEXP (x, i), replacements,
10923 n_replacements, modify);
10929 else if (fmt[i] == 'E')
10930 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10932 new = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
10933 n_replacements, modify);
10937 XVECEXP (x, i, j) = new;
10945 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
10947 enum rtx_code code = TRUNCATE;
10949 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
10951 rtx inner = XEXP (x, 0);
10952 enum machine_mode inner_mode = GET_MODE (inner);
10954 if (inner_mode == mode)
10956 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
10958 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
10959 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
10961 code = GET_CODE (x);
10965 return gen_rtx_fmt_e (code, mode, x);
10968 /* called via for_each_rtx after reload, to clean up truncates of
10969 registers that span multiple actual hard registers. */
10971 shmedia_cleanup_truncate (rtx *p, void *n_changes)
10975 if (GET_CODE (x) != TRUNCATE)
10978 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && GET_CODE (reg) == REG)
10980 enum machine_mode reg_mode = GET_MODE (reg);
10981 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
10982 subreg_lowpart_offset (DImode, reg_mode));
10983 *(int*) n_changes += 1;
10989 /* Load and store depend on the highpart of the address. However,
10990 set_attr_alternative does not give well-defined results before reload,
10991 so we must look at the rtl ourselves to see if any of the feeding
10992 registers is used in a memref. */
10994 /* Called by sh_contains_memref_p via for_each_rtx. */
10996 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
10998 return (GET_CODE (*loc) == MEM);
11001 /* Return nonzero iff INSN contains a MEM. */
11003 sh_contains_memref_p (rtx insn)
11005 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
11008 /* Return nonzero iff INSN loads a banked register. */
11010 sh_loads_bankedreg_p (rtx insn)
11012 if (GET_CODE (PATTERN (insn)) == SET)
11014 rtx op = SET_DEST (PATTERN(insn));
11015 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11022 /* FNADDR is the MEM expression from a call expander. Return an address
11023 to use in an SHmedia insn pattern. */
11025 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
11029 fnaddr = XEXP (fnaddr, 0);
11030 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
11031 if (flag_pic && is_sym)
11033 if (! SYMBOL_REF_LOCAL_P (fnaddr))
11035 rtx reg = gen_reg_rtx (Pmode);
11037 /* We must not use GOTPLT for sibcalls, because PIC_REG
11038 must be restored before the PLT code gets to run. */
11040 emit_insn (gen_symGOT2reg (reg, fnaddr));
11042 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
11047 fnaddr = gen_sym2PIC (fnaddr);
11048 PUT_MODE (fnaddr, Pmode);
11051 /* If ptabs might trap, make this visible to the rest of the compiler.
11052 We generally assume that symbols pertain to valid locations, but
11053 it is possible to generate invalid symbols with asm or linker tricks.
11054 In a list of functions where each returns its successor, an invalid
11055 symbol might denote an empty list. */
11056 if (!TARGET_PT_FIXED
11057 && (!is_sym || TARGET_INVALID_SYMBOLS)
11058 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
11060 rtx tr = gen_reg_rtx (PDImode);
11062 emit_insn (gen_ptabs (tr, fnaddr));
11065 else if (! target_reg_operand (fnaddr, Pmode))
11066 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
11071 sh_secondary_reload (bool in_p, rtx x, enum reg_class class,
11072 enum machine_mode mode, secondary_reload_info *sri)
11076 if (REGCLASS_HAS_FP_REG (class)
11077 && ! TARGET_SHMEDIA
11078 && immediate_operand ((x), mode)
11079 && ! ((fp_zero_operand (x) || fp_one_operand (x))
11080 && mode == SFmode && fldi_ok ()))
11084 sri->icode = CODE_FOR_reload_insf__frn;
11087 sri->icode = CODE_FOR_reload_indf__frn;
11090 /* ??? If we knew that we are in the appropriate mode -
11091 single precision - we could use a reload pattern directly. */
11096 if (class == FPUL_REGS
11097 && ((GET_CODE (x) == REG
11098 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11099 || REGNO (x) == T_REG))
11100 || GET_CODE (x) == PLUS))
11101 return GENERAL_REGS;
11102 if (class == FPUL_REGS && immediate_operand (x, mode))
11104 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
11105 return GENERAL_REGS;
11106 else if (mode == SFmode)
11108 sri->icode = CODE_FOR_reload_insi__i_fpul;
11111 if (class == FPSCR_REGS
11112 && ((GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11113 || (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PLUS)))
11114 return GENERAL_REGS;
11115 if (REGCLASS_HAS_FP_REG (class)
11117 && immediate_operand (x, mode)
11118 && x != CONST0_RTX (GET_MODE (x))
11119 && GET_MODE (x) != V4SFmode)
11120 return GENERAL_REGS;
11121 if ((mode == QImode || mode == HImode)
11122 && TARGET_SHMEDIA && inqhi_operand (x, mode))
11124 sri->icode = ((mode == QImode)
11125 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
11128 if (TARGET_SHMEDIA && class == GENERAL_REGS
11129 && (GET_CODE (x) == LABEL_REF || PIC_DIRECT_ADDR_P (x)))
11130 return TARGET_REGS;
11131 } /* end of input-only processing. */
11133 if (((REGCLASS_HAS_FP_REG (class)
11134 && (GET_CODE (x) == REG
11135 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11136 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11137 && TARGET_FMOVD))))
11138 || (REGCLASS_HAS_GENERAL_REG (class)
11139 && GET_CODE (x) == REG
11140 && FP_REGISTER_P (REGNO (x))))
11141 && ! TARGET_SHMEDIA
11142 && (mode == SFmode || mode == SImode))
11144 if ((class == FPUL_REGS
11145 || (REGCLASS_HAS_FP_REG (class)
11146 && ! TARGET_SHMEDIA && mode == SImode))
11147 && (GET_CODE (x) == MEM
11148 || (GET_CODE (x) == REG
11149 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11150 || REGNO (x) == T_REG
11151 || system_reg_operand (x, VOIDmode)))))
11153 if (class == FPUL_REGS)
11154 return GENERAL_REGS;
11157 if ((class == TARGET_REGS
11158 || (TARGET_SHMEDIA && class == SIBCALL_REGS))
11159 && !satisfies_constraint_Csy (x)
11160 && (GET_CODE (x) != REG || ! GENERAL_REGISTER_P (REGNO (x))))
11161 return GENERAL_REGS;
11162 if ((class == MAC_REGS || class == PR_REGS)
11163 && GET_CODE (x) == REG && ! GENERAL_REGISTER_P (REGNO (x))
11164 && class != REGNO_REG_CLASS (REGNO (x)))
11165 return GENERAL_REGS;
11166 if (class != GENERAL_REGS && GET_CODE (x) == REG
11167 && TARGET_REGISTER_P (REGNO (x)))
11168 return GENERAL_REGS;
11172 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;