1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "insn-config.h"
35 #include "hard-reg-set.h"
37 #include "insn-attr.h"
41 #include "integrate.h"
45 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
52 #include "sched-int.h"
56 #include "alloc-pool.h"
57 #include "tm-constrs.h"
60 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
62 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
63 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
65 /* These are some macros to abstract register modes. */
66 #define CONST_OK_FOR_ADD(size) \
67 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
68 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
69 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
70 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
72 /* Used to simplify the logic below. Find the attributes wherever
74 #define SH_ATTRIBUTES(decl) \
75 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
76 : DECL_ATTRIBUTES (decl) \
77 ? (DECL_ATTRIBUTES (decl)) \
78 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
80 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
81 int current_function_interrupt;
83 tree sh_deferred_function_attributes;
84 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
86 /* Global variables for machine-dependent things. */
88 /* Which cpu are we scheduling for. */
89 enum processor_type sh_cpu;
91 /* Definitions used in ready queue reordering for first scheduling pass. */
93 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
94 static short *regmode_weight[2];
96 /* Total SFmode and SImode weights of scheduled insns. */
97 static int curr_regmode_pressure[2];
99 /* Number of r0 life regions. */
100 static int r0_life_regions;
102 /* If true, skip cycles for Q -> R movement. */
103 static int skip_cycles = 0;
105 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
106 and returned from sh_reorder2. */
107 static short cached_can_issue_more;
109 /* Saved operands from the last compare to use when we generate an scc
115 /* Provides the class number of the smallest class containing
118 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
120 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
131 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
132 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
133 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
135 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
136 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
147 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
148 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
149 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
152 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
153 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
154 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
155 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
156 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
157 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
158 GENERAL_REGS, GENERAL_REGS,
161 char sh_register_names[FIRST_PSEUDO_REGISTER] \
162 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
164 char sh_additional_register_names[ADDREGNAMES_SIZE] \
165 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
166 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
168 int assembler_dialect;
170 static bool shmedia_space_reserved_for_target_registers;
172 static bool sh_handle_option (size_t, const char *, int);
173 static void split_branches (rtx);
174 static int branch_dest (rtx);
175 static void force_into (rtx, rtx);
176 static void print_slot (rtx);
177 static rtx add_constant (rtx, enum machine_mode, rtx);
178 static void dump_table (rtx, rtx);
179 static int hi_const (rtx);
180 static int broken_move (rtx);
181 static int mova_p (rtx);
182 static rtx find_barrier (int, rtx, rtx);
183 static int noncall_uses_reg (rtx, rtx, rtx *);
184 static rtx gen_block_redirect (rtx, int, int);
185 static void sh_reorg (void);
186 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
187 static rtx frame_insn (rtx);
188 static rtx push (int);
189 static void pop (int);
190 static void push_regs (HARD_REG_SET *, int);
191 static int calc_live_regs (HARD_REG_SET *);
192 static HOST_WIDE_INT rounded_frame_size (int);
193 static rtx mark_constant_pool_use (rtx);
194 const struct attribute_spec sh_attribute_table[];
195 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
196 static tree sh_handle_resbank_handler_attribute (tree *, tree,
198 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
200 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
201 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
202 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
203 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
204 static void sh_insert_attributes (tree, tree *);
205 static const char *sh_check_pch_target_flags (int);
206 static int sh_adjust_cost (rtx, rtx, rtx, int);
207 static int sh_issue_rate (void);
208 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
209 static short find_set_regmode_weight (rtx, enum machine_mode);
210 static short find_insn_regmode_weight (rtx, enum machine_mode);
211 static void find_regmode_weight (basic_block, enum machine_mode);
212 static int find_r0_life_regions (basic_block);
213 static void sh_md_init_global (FILE *, int, int);
214 static void sh_md_finish_global (FILE *, int);
215 static int rank_for_reorder (const void *, const void *);
216 static void swap_reorder (rtx *, int);
217 static void ready_reorder (rtx *, int);
218 static short high_pressure (enum machine_mode);
219 static int sh_reorder (FILE *, int, rtx *, int *, int);
220 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
221 static void sh_md_init (FILE *, int, int);
222 static int sh_variable_issue (FILE *, int, rtx, int);
224 static bool sh_function_ok_for_sibcall (tree, tree);
226 static bool sh_cannot_modify_jumps_p (void);
227 static int sh_target_reg_class (void);
228 static bool sh_optimize_target_register_callee_saved (bool);
229 static bool sh_ms_bitfield_layout_p (const_tree);
231 static void sh_init_builtins (void);
232 static void sh_media_init_builtins (void);
233 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
234 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
235 static void sh_file_start (void);
236 static int flow_dependent_p (rtx, rtx);
237 static void flow_dependent_p_1 (rtx, const_rtx, void *);
238 static int shiftcosts (rtx);
239 static int andcosts (rtx);
240 static int addsubcosts (rtx);
241 static int multcosts (rtx);
242 static bool unspec_caller_rtx_p (rtx);
243 static bool sh_cannot_copy_insn_p (rtx);
244 static bool sh_rtx_costs (rtx, int, int, int *, bool);
245 static int sh_address_cost (rtx, bool);
246 static int sh_pr_n_sets (void);
247 static rtx sh_allocate_initial_value (rtx);
248 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
249 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
250 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
251 static int scavenge_reg (HARD_REG_SET *s);
252 struct save_schedule_s;
253 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
254 struct save_schedule_s *, int);
256 static rtx sh_struct_value_rtx (tree, int);
257 static bool sh_return_in_memory (const_tree, const_tree);
258 static rtx sh_builtin_saveregs (void);
259 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
260 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
261 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
262 static tree sh_build_builtin_va_list (void);
263 static void sh_va_start (tree, rtx);
264 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
265 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
267 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
269 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
271 static bool sh_scalar_mode_supported_p (enum machine_mode);
272 static int sh_dwarf_calling_convention (const_tree);
273 static void sh_encode_section_info (tree, rtx, int);
274 static int sh2a_function_vector_p (tree);
277 /* Initialize the GCC target structure. */
278 #undef TARGET_ATTRIBUTE_TABLE
279 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
281 /* The next two are used for debug info when compiling with -gdwarf. */
282 #undef TARGET_ASM_UNALIGNED_HI_OP
283 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
284 #undef TARGET_ASM_UNALIGNED_SI_OP
285 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
287 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
288 #undef TARGET_ASM_UNALIGNED_DI_OP
289 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
290 #undef TARGET_ASM_ALIGNED_DI_OP
291 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
293 #undef TARGET_ASM_FUNCTION_EPILOGUE
294 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
296 #undef TARGET_ASM_OUTPUT_MI_THUNK
297 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
299 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
300 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
302 #undef TARGET_ASM_FILE_START
303 #define TARGET_ASM_FILE_START sh_file_start
304 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
305 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
307 #undef TARGET_DEFAULT_TARGET_FLAGS
308 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
309 #undef TARGET_HANDLE_OPTION
310 #define TARGET_HANDLE_OPTION sh_handle_option
312 #undef TARGET_INSERT_ATTRIBUTES
313 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
315 #undef TARGET_SCHED_ADJUST_COST
316 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
318 #undef TARGET_SCHED_ISSUE_RATE
319 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
321 /* The next 5 hooks have been implemented for reenabling sched1. With the
322 help of these macros we are limiting the movement of insns in sched1 to
323 reduce the register pressure. The overall idea is to keep count of SImode
324 and SFmode regs required by already scheduled insns. When these counts
325 cross some threshold values; give priority to insns that free registers.
326 The insn that frees registers is most likely to be the insn with lowest
327 LUID (original insn order); but such an insn might be there in the stalled
328 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
329 upto a max of 8 cycles so that such insns may move from Q -> R.
331 The description of the hooks are as below:
333 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
334 scheduler; it is called inside the sched_init function just after
335 find_insn_reg_weights function call. It is used to calculate the SImode
336 and SFmode weights of insns of basic blocks; much similar to what
337 find_insn_reg_weights does.
338 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
340 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
341 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
344 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
345 high; reorder the ready queue so that the insn with lowest LUID will be
348 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
349 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
351 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
352 can be returned from TARGET_SCHED_REORDER2.
354 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
356 #undef TARGET_SCHED_DFA_NEW_CYCLE
357 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
359 #undef TARGET_SCHED_INIT_GLOBAL
360 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
362 #undef TARGET_SCHED_FINISH_GLOBAL
363 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
365 #undef TARGET_SCHED_VARIABLE_ISSUE
366 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
368 #undef TARGET_SCHED_REORDER
369 #define TARGET_SCHED_REORDER sh_reorder
371 #undef TARGET_SCHED_REORDER2
372 #define TARGET_SCHED_REORDER2 sh_reorder2
374 #undef TARGET_SCHED_INIT
375 #define TARGET_SCHED_INIT sh_md_init
377 #undef TARGET_CANNOT_MODIFY_JUMPS_P
378 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
379 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
380 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
381 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
382 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
383 sh_optimize_target_register_callee_saved
385 #undef TARGET_MS_BITFIELD_LAYOUT_P
386 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
388 #undef TARGET_INIT_BUILTINS
389 #define TARGET_INIT_BUILTINS sh_init_builtins
390 #undef TARGET_EXPAND_BUILTIN
391 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
393 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
394 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
396 #undef TARGET_CANNOT_COPY_INSN_P
397 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
398 #undef TARGET_RTX_COSTS
399 #define TARGET_RTX_COSTS sh_rtx_costs
400 #undef TARGET_ADDRESS_COST
401 #define TARGET_ADDRESS_COST sh_address_cost
402 #undef TARGET_ALLOCATE_INITIAL_VALUE
403 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
405 #undef TARGET_MACHINE_DEPENDENT_REORG
406 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
409 #undef TARGET_HAVE_TLS
410 #define TARGET_HAVE_TLS true
413 #undef TARGET_PROMOTE_PROTOTYPES
414 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
415 #undef TARGET_PROMOTE_FUNCTION_ARGS
416 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
417 #undef TARGET_PROMOTE_FUNCTION_RETURN
418 #define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
420 #undef TARGET_STRUCT_VALUE_RTX
421 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
422 #undef TARGET_RETURN_IN_MEMORY
423 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
425 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
426 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
427 #undef TARGET_SETUP_INCOMING_VARARGS
428 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
429 #undef TARGET_STRICT_ARGUMENT_NAMING
430 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
431 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
432 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
433 #undef TARGET_MUST_PASS_IN_STACK
434 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
435 #undef TARGET_PASS_BY_REFERENCE
436 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
437 #undef TARGET_CALLEE_COPIES
438 #define TARGET_CALLEE_COPIES sh_callee_copies
439 #undef TARGET_ARG_PARTIAL_BYTES
440 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
442 #undef TARGET_BUILD_BUILTIN_VA_LIST
443 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
444 #undef TARGET_EXPAND_BUILTIN_VA_START
445 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
446 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
447 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
449 #undef TARGET_SCALAR_MODE_SUPPORTED_P
450 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
451 #undef TARGET_VECTOR_MODE_SUPPORTED_P
452 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
454 #undef TARGET_CHECK_PCH_TARGET_FLAGS
455 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
457 #undef TARGET_DWARF_CALLING_CONVENTION
458 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
460 /* Return regmode weight for insn. */
461 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
463 /* Return current register pressure for regmode. */
464 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
466 #undef TARGET_ENCODE_SECTION_INFO
467 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
471 #undef TARGET_ENCODE_SECTION_INFO
472 #define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
473 #undef TARGET_STRIP_NAME_ENCODING
474 #define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
475 #undef TARGET_CXX_IMPORT_EXPORT_CLASS
476 #define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
480 #undef TARGET_SECONDARY_RELOAD
481 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
483 /* Machine-specific symbol_ref flags. */
484 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
486 struct gcc_target targetm = TARGET_INITIALIZER;
488 /* Implement TARGET_HANDLE_OPTION. */
491 sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
492 int value ATTRIBUTE_UNUSED)
497 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
501 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
505 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
509 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
513 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
516 case OPT_m2a_single_only:
517 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
521 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
525 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
529 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
536 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
540 case OPT_m4_100_nofpu:
541 case OPT_m4_200_nofpu:
542 case OPT_m4_300_nofpu:
546 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
550 case OPT_m4_100_single:
551 case OPT_m4_200_single:
552 case OPT_m4_300_single:
553 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
556 case OPT_m4_single_only:
557 case OPT_m4_100_single_only:
558 case OPT_m4_200_single_only:
559 case OPT_m4_300_single_only:
560 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
564 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
569 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
573 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
576 case OPT_m4a_single_only:
577 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
581 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
584 case OPT_m5_32media_nofpu:
585 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
589 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
592 case OPT_m5_64media_nofpu:
593 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
597 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
600 case OPT_m5_compact_nofpu:
601 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
609 /* Print the operand address in x to the stream. */
612 print_operand_address (FILE *stream, rtx x)
614 switch (GET_CODE (x))
618 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
623 rtx base = XEXP (x, 0);
624 rtx index = XEXP (x, 1);
626 switch (GET_CODE (index))
629 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
630 reg_names[true_regnum (base)]);
636 int base_num = true_regnum (base);
637 int index_num = true_regnum (index);
639 fprintf (stream, "@(r0,%s)",
640 reg_names[MAX (base_num, index_num)]);
651 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
655 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
659 x = mark_constant_pool_use (x);
660 output_addr_const (stream, x);
665 /* Print operand x (an rtx) in assembler syntax to file stream
666 according to modifier code.
668 '.' print a .s if insn needs delay slot
669 ',' print LOCAL_LABEL_PREFIX
670 '@' print trap, rte or rts depending upon pragma interruptness
671 '#' output a nop if there is nothing to put in the delay slot
672 ''' print likelihood suffix (/u for unlikely).
673 '>' print branch target if -fverbose-asm
674 'O' print a constant without the #
675 'R' print the LSW of a dp value - changes if in little endian
676 'S' print the MSW of a dp value - changes if in little endian
677 'T' print the next word of a dp value - same as 'R' in big endian mode.
678 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
679 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
680 'N' print 'r63' if the operand is (const_int 0).
681 'd' print a V2SF reg as dN instead of fpN.
682 'm' print a pair `base,offset' or `base,index', for LD and ST.
683 'U' Likewise for {LD,ST}{HI,LO}.
684 'V' print the position of a single bit set.
685 'W' print the position of a single bit cleared.
686 't' print a memory address which is a register.
687 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
688 'o' output an operator. */
691 print_operand (FILE *stream, rtx x, int code)
694 enum machine_mode mode;
702 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
703 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
704 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
707 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
710 trapa_attr = lookup_attribute ("trap_exit",
711 DECL_ATTRIBUTES (current_function_decl));
713 fprintf (stream, "trapa #%ld",
714 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
715 else if (sh_cfun_interrupt_handler_p ())
717 if (sh_cfun_resbank_handler_p ())
718 fprintf (stream, "resbank\n");
719 fprintf (stream, "rte");
722 fprintf (stream, "rts");
725 /* Output a nop if there's nothing in the delay slot. */
726 if (dbr_sequence_length () == 0)
727 fprintf (stream, "\n\tnop");
731 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
733 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
734 fputs ("/u", stream);
738 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
740 fputs ("\t! target: ", stream);
741 output_addr_const (stream, JUMP_LABEL (current_output_insn));
745 x = mark_constant_pool_use (x);
746 output_addr_const (stream, x);
748 /* N.B.: %R / %S / %T adjust memory addresses by four.
749 For SHMEDIA, that means they can be used to access the first and
750 second 32 bit part of a 64 bit (or larger) value that
751 might be held in floating point registers or memory.
752 While they can be used to access 64 bit parts of a larger value
753 held in general purpose registers, that won't work with memory -
754 neither for fp registers, since the frxx names are used. */
756 if (REG_P (x) || GET_CODE (x) == SUBREG)
758 regno = true_regnum (x);
759 regno += FP_REGISTER_P (regno) ? 1 : LSW;
760 fputs (reg_names[regno], (stream));
764 x = adjust_address (x, SImode, 4 * LSW);
765 print_operand_address (stream, XEXP (x, 0));
772 if (mode == VOIDmode)
774 if (GET_MODE_SIZE (mode) >= 8)
775 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
777 print_operand (stream, sub, 0);
779 output_operand_lossage ("invalid operand to %%R");
783 if (REG_P (x) || GET_CODE (x) == SUBREG)
785 regno = true_regnum (x);
786 regno += FP_REGISTER_P (regno) ? 0 : MSW;
787 fputs (reg_names[regno], (stream));
791 x = adjust_address (x, SImode, 4 * MSW);
792 print_operand_address (stream, XEXP (x, 0));
799 if (mode == VOIDmode)
801 if (GET_MODE_SIZE (mode) >= 8)
802 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
804 print_operand (stream, sub, 0);
806 output_operand_lossage ("invalid operand to %%S");
810 /* Next word of a double. */
811 switch (GET_CODE (x))
814 fputs (reg_names[REGNO (x) + 1], (stream));
817 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
818 && GET_CODE (XEXP (x, 0)) != POST_INC)
819 x = adjust_address (x, SImode, 4);
820 print_operand_address (stream, XEXP (x, 0));
828 gcc_assert (GET_CODE (x) == MEM);
830 switch (GET_CODE (x))
834 print_operand (stream, x, 0);
842 switch (GET_CODE (x))
844 case PLUS: fputs ("add", stream); break;
845 case MINUS: fputs ("sub", stream); break;
846 case MULT: fputs ("mul", stream); break;
847 case DIV: fputs ("div", stream); break;
848 case EQ: fputs ("eq", stream); break;
849 case NE: fputs ("ne", stream); break;
850 case GT: case LT: fputs ("gt", stream); break;
851 case GE: case LE: fputs ("ge", stream); break;
852 case GTU: case LTU: fputs ("gtu", stream); break;
853 case GEU: case LEU: fputs ("geu", stream); break;
861 if (GET_CODE (x) == MEM
862 && GET_CODE (XEXP (x, 0)) == PLUS
863 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
864 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
869 if (GET_CODE (x) == MEM)
871 switch (GET_MODE (x))
873 case QImode: fputs (".b", stream); break;
874 case HImode: fputs (".w", stream); break;
875 case SImode: fputs (".l", stream); break;
876 case SFmode: fputs (".s", stream); break;
877 case DFmode: fputs (".d", stream); break;
878 default: gcc_unreachable ();
885 gcc_assert (GET_CODE (x) == MEM);
889 switch (GET_CODE (x))
893 print_operand (stream, x, 0);
894 fputs (", 0", stream);
898 print_operand (stream, XEXP (x, 0), 0);
899 fputs (", ", stream);
900 print_operand (stream, XEXP (x, 1), 0);
910 int num = exact_log2 (INTVAL (x));
911 gcc_assert (num >= 0);
912 fprintf (stream, "#%d", num);
918 int num = exact_log2 (~INTVAL (x));
919 gcc_assert (num >= 0);
920 fprintf (stream, "#%d", num);
925 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == V2SFmode);
927 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
931 if (x == CONST0_RTX (GET_MODE (x)))
933 fprintf ((stream), "r63");
938 if (GET_CODE (x) == CONST_INT)
940 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
950 switch (GET_CODE (x))
954 rtx inner = XEXP (x, 0);
956 enum machine_mode inner_mode;
958 /* We might see SUBREGs with vector mode registers inside. */
959 if (GET_CODE (inner) == SUBREG
960 && (GET_MODE_SIZE (GET_MODE (inner))
961 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
962 && subreg_lowpart_p (inner))
963 inner = SUBREG_REG (inner);
964 if (GET_CODE (inner) == CONST_INT)
966 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
969 inner_mode = GET_MODE (inner);
970 if (GET_CODE (inner) == SUBREG
971 && (GET_MODE_SIZE (GET_MODE (inner))
972 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
973 && GET_CODE (SUBREG_REG (inner)) == REG)
975 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
976 GET_MODE (SUBREG_REG (inner)),
979 inner = SUBREG_REG (inner);
981 if (GET_CODE (inner) != REG || GET_MODE_SIZE (inner_mode) > 8)
983 /* Floating point register pairs are always big endian;
984 general purpose registers are 64 bit wide. */
985 regno = REGNO (inner);
986 regno = (HARD_REGNO_NREGS (regno, inner_mode)
987 - HARD_REGNO_NREGS (regno, mode))
995 /* FIXME: We need this on SHmedia32 because reload generates
996 some sign-extended HI or QI loads into DImode registers
997 but, because Pmode is SImode, the address ends up with a
998 subreg:SI of the DImode register. Maybe reload should be
999 fixed so as to apply alter_subreg to such loads? */
1001 gcc_assert (trapping_target_operand (x, VOIDmode));
1002 x = XEXP (XEXP (x, 2), 0);
1003 goto default_output;
1005 gcc_assert (SUBREG_BYTE (x) == 0
1006 && GET_CODE (SUBREG_REG (x)) == REG);
1014 if (FP_REGISTER_P (regno)
1015 && mode == V16SFmode)
1016 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1017 else if (FP_REGISTER_P (REGNO (x))
1018 && mode == V4SFmode)
1019 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1020 else if (GET_CODE (x) == REG
1021 && mode == V2SFmode)
1022 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1023 else if (FP_REGISTER_P (REGNO (x))
1024 && GET_MODE_SIZE (mode) > 4)
1025 fprintf ((stream), "d%s", reg_names[regno] + 1);
1027 fputs (reg_names[regno], (stream));
1031 output_address (XEXP (x, 0));
1036 && (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
1037 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
1038 && (GET_MODE (XEXP (x, 0)) == DImode
1039 || GET_MODE (XEXP (x, 0)) == SImode)
1040 && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE
1041 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)
1043 rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0);
1045 bool nested_expr = false;
1047 fputc ('(', stream);
1048 if (GET_CODE (val) == ASHIFTRT)
1050 fputc ('(', stream);
1051 val2 = XEXP (val, 0);
1053 if (GET_CODE (val2) == CONST
1054 || GET_RTX_CLASS (GET_CODE (val2)) != RTX_OBJ)
1056 fputc ('(', stream);
1059 output_addr_const (stream, val2);
1061 fputc (')', stream);
1062 if (GET_CODE (val) == ASHIFTRT)
1064 fputs (" >> ", stream);
1065 output_addr_const (stream, XEXP (val, 1));
1066 fputc (')', stream);
1068 fputs (" & 65535)", stream);
1075 fputc ('#', stream);
1076 output_addr_const (stream, x);
1084 /* Encode symbol attributes of a SYMBOL_REF into its
1085 SYMBOL_REF_FLAGS. */
1087 sh_encode_section_info (tree decl, rtx rtl, int first)
1089 default_encode_section_info (decl, rtl, first);
1091 if (TREE_CODE (decl) == FUNCTION_DECL
1092 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1093 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1096 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1098 force_into (rtx value, rtx target)
1100 value = force_operand (value, target);
1101 if (! rtx_equal_p (value, target))
1102 emit_insn (gen_move_insn (target, value));
1105 /* Emit code to perform a block move. Choose the best method.
1107 OPERANDS[0] is the destination.
1108 OPERANDS[1] is the source.
1109 OPERANDS[2] is the size.
1110 OPERANDS[3] is the alignment safe to use. */
1113 expand_block_move (rtx *operands)
1115 int align = INTVAL (operands[3]);
1116 int constp = (GET_CODE (operands[2]) == CONST_INT);
1117 int bytes = (constp ? INTVAL (operands[2]) : 0);
1122 /* If we could use mov.l to move words and dest is word-aligned, we
1123 can use movua.l for loads and still generate a relatively short
1124 and efficient sequence. */
1125 if (TARGET_SH4A_ARCH && align < 4
1126 && MEM_ALIGN (operands[0]) >= 32
1127 && can_move_by_pieces (bytes, 32))
1129 rtx dest = copy_rtx (operands[0]);
1130 rtx src = copy_rtx (operands[1]);
1131 /* We could use different pseudos for each copied word, but
1132 since movua can only load into r0, it's kind of
1134 rtx temp = gen_reg_rtx (SImode);
1135 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1138 while (copied + 4 <= bytes)
1140 rtx to = adjust_address (dest, SImode, copied);
1141 rtx from = adjust_automodify_address (src, BLKmode,
1144 set_mem_size (from, GEN_INT (4));
1145 emit_insn (gen_movua (temp, from));
1146 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1147 emit_move_insn (to, temp);
1152 move_by_pieces (adjust_address (dest, BLKmode, copied),
1153 adjust_automodify_address (src, BLKmode,
1155 bytes - copied, align, 0);
1160 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1161 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1162 if (align < 4 || (bytes % 4 != 0))
1165 if (TARGET_HARD_SH4)
1169 else if (bytes == 12)
1171 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1172 rtx r4 = gen_rtx_REG (SImode, 4);
1173 rtx r5 = gen_rtx_REG (SImode, 5);
1175 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1176 force_into (XEXP (operands[0], 0), r4);
1177 force_into (XEXP (operands[1], 0), r5);
1178 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1181 else if (! TARGET_SMALLCODE)
1183 const char *entry_name;
1184 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1186 rtx r4 = gen_rtx_REG (SImode, 4);
1187 rtx r5 = gen_rtx_REG (SImode, 5);
1188 rtx r6 = gen_rtx_REG (SImode, 6);
1190 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1191 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1192 force_into (XEXP (operands[0], 0), r4);
1193 force_into (XEXP (operands[1], 0), r5);
1195 dwords = bytes >> 3;
1196 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1197 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1206 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1207 rtx r4 = gen_rtx_REG (SImode, 4);
1208 rtx r5 = gen_rtx_REG (SImode, 5);
1210 sprintf (entry, "__movmemSI%d", bytes);
1211 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1212 force_into (XEXP (operands[0], 0), r4);
1213 force_into (XEXP (operands[1], 0), r5);
1214 emit_insn (gen_block_move_real (func_addr_rtx));
1218 /* This is the same number of bytes as a memcpy call, but to a different
1219 less common function name, so this will occasionally use more space. */
1220 if (! TARGET_SMALLCODE)
1222 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1223 int final_switch, while_loop;
1224 rtx r4 = gen_rtx_REG (SImode, 4);
1225 rtx r5 = gen_rtx_REG (SImode, 5);
1226 rtx r6 = gen_rtx_REG (SImode, 6);
1228 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1229 force_into (XEXP (operands[0], 0), r4);
1230 force_into (XEXP (operands[1], 0), r5);
1232 /* r6 controls the size of the move. 16 is decremented from it
1233 for each 64 bytes moved. Then the negative bit left over is used
1234 as an index into a list of move instructions. e.g., a 72 byte move
1235 would be set up with size(r6) = 14, for one iteration through the
1236 big while loop, and a switch of -2 for the last part. */
1238 final_switch = 16 - ((bytes / 4) % 16);
1239 while_loop = ((bytes / 4) / 16 - 1) * 16;
1240 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1241 emit_insn (gen_block_lump_real (func_addr_rtx));
1248 /* Prepare operands for a move define_expand; specifically, one of the
1249 operands must be in a register. */
1252 prepare_move_operands (rtx operands[], enum machine_mode mode)
1254 if ((mode == SImode || mode == DImode)
1256 && ! ((mode == Pmode || mode == ptr_mode)
1257 && tls_symbolic_operand (operands[1], Pmode) != 0))
1260 if (SYMBOLIC_CONST_P (operands[1]))
1262 if (GET_CODE (operands[0]) == MEM)
1263 operands[1] = force_reg (Pmode, operands[1]);
1264 else if (TARGET_SHMEDIA
1265 && GET_CODE (operands[1]) == LABEL_REF
1266 && target_reg_operand (operands[0], mode))
1270 temp = (!can_create_pseudo_p ()
1272 : gen_reg_rtx (Pmode));
1273 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1276 else if (GET_CODE (operands[1]) == CONST
1277 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1278 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1280 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1281 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1283 operands[1] = expand_binop (mode, add_optab, temp,
1284 XEXP (XEXP (operands[1], 0), 1),
1285 (!can_create_pseudo_p ()
1287 : gen_reg_rtx (Pmode)),
1288 0, OPTAB_LIB_WIDEN);
1292 if (! reload_in_progress && ! reload_completed)
1294 /* Copy the source to a register if both operands aren't registers. */
1295 if (! register_operand (operands[0], mode)
1296 && ! sh_register_operand (operands[1], mode))
1297 operands[1] = copy_to_mode_reg (mode, operands[1]);
1299 if (GET_CODE (operands[0]) == MEM && ! memory_operand (operands[0], mode))
1301 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1302 except that we can't use that function because it is static. */
1303 rtx new_rtx = change_address (operands[0], mode, 0);
1304 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1305 operands[0] = new_rtx;
1308 /* This case can happen while generating code to move the result
1309 of a library call to the target. Reject `st r0,@(rX,rY)' because
1310 reload will fail to find a spill register for rX, since r0 is already
1311 being used for the source. */
1313 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1314 && GET_CODE (operands[0]) == MEM
1315 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1316 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
1317 operands[1] = copy_to_mode_reg (mode, operands[1]);
1320 if (mode == Pmode || mode == ptr_mode)
1323 enum tls_model tls_kind;
1327 if (GET_CODE (op1) == CONST
1328 && GET_CODE (XEXP (op1, 0)) == PLUS
1329 && tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode))
1331 opc = XEXP (XEXP (op1, 0), 1);
1332 op1 = XEXP (XEXP (op1, 0), 0);
1337 if ((tls_kind = tls_symbolic_operand (op1, Pmode)))
1339 rtx tga_op1, tga_ret, tmp, tmp2;
1343 case TLS_MODEL_GLOBAL_DYNAMIC:
1344 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1345 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1349 case TLS_MODEL_LOCAL_DYNAMIC:
1350 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1351 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1353 tmp = gen_reg_rtx (Pmode);
1354 emit_move_insn (tmp, tga_ret);
1356 if (register_operand (op0, Pmode))
1359 tmp2 = gen_reg_rtx (Pmode);
1361 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1365 case TLS_MODEL_INITIAL_EXEC:
1368 /* Don't schedule insns for getting GOT address when
1369 the first scheduling is enabled, to avoid spill
1371 if (flag_schedule_insns)
1372 emit_insn (gen_blockage ());
1373 emit_insn (gen_GOTaddr2picreg ());
1374 emit_use (gen_rtx_REG (SImode, PIC_REG));
1375 if (flag_schedule_insns)
1376 emit_insn (gen_blockage ());
1378 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1379 tmp = gen_sym2GOTTPOFF (op1);
1380 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1384 case TLS_MODEL_LOCAL_EXEC:
1385 tmp2 = gen_reg_rtx (Pmode);
1386 emit_insn (gen_load_gbr (tmp2));
1387 tmp = gen_reg_rtx (Pmode);
1388 emit_insn (gen_symTPOFF2reg (tmp, op1));
1390 if (register_operand (op0, Pmode))
1393 op1 = gen_reg_rtx (Pmode);
1395 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1402 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1411 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1412 enum rtx_code comparison)
1415 rtx scratch = NULL_RTX;
1417 if (comparison == CODE_FOR_nothing)
1418 comparison = GET_CODE (operands[0]);
1420 scratch = operands[4];
1421 if (GET_CODE (operands[1]) == CONST_INT
1422 && GET_CODE (operands[2]) != CONST_INT)
1424 rtx tmp = operands[1];
1426 operands[1] = operands[2];
1428 comparison = swap_condition (comparison);
1430 if (GET_CODE (operands[2]) == CONST_INT)
1432 HOST_WIDE_INT val = INTVAL (operands[2]);
1433 if ((val == -1 || val == -0x81)
1434 && (comparison == GT || comparison == LE))
1436 comparison = (comparison == GT) ? GE : LT;
1437 operands[2] = gen_int_mode (val + 1, mode);
1439 else if ((val == 1 || val == 0x80)
1440 && (comparison == GE || comparison == LT))
1442 comparison = (comparison == GE) ? GT : LE;
1443 operands[2] = gen_int_mode (val - 1, mode);
1445 else if (val == 1 && (comparison == GEU || comparison == LTU))
1447 comparison = (comparison == GEU) ? NE : EQ;
1448 operands[2] = CONST0_RTX (mode);
1450 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1452 comparison = (comparison == GEU) ? GTU : LEU;
1453 operands[2] = gen_int_mode (val - 1, mode);
1455 else if (val == 0 && (comparison == GTU || comparison == LEU))
1456 comparison = (comparison == GTU) ? NE : EQ;
1457 else if (mode == SImode
1458 && ((val == 0x7fffffff
1459 && (comparison == GTU || comparison == LEU))
1460 || ((unsigned HOST_WIDE_INT) val
1461 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1462 && (comparison == GEU || comparison == LTU))))
1464 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1465 operands[2] = CONST0_RTX (mode);
1469 if (can_create_pseudo_p ())
1470 operands[1] = force_reg (mode, op1);
1471 /* When we are handling DImode comparisons, we want to keep constants so
1472 that we can optimize the component comparisons; however, memory loads
1473 are better issued as a whole so that they can be scheduled well.
1474 SImode equality comparisons allow I08 constants, but only when they
1475 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1476 into a register, that register might as well be r0, and we allow the
1477 constant. If it is already in a register, this is likely to be
1478 allocated to a different hard register, thus we load the constant into
1479 a register unless it is zero. */
1480 if (!REG_P (operands[2])
1481 && (GET_CODE (operands[2]) != CONST_INT
1482 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1483 && ((comparison != EQ && comparison != NE)
1484 || (REG_P (op1) && REGNO (op1) != R0_REG)
1485 || !satisfies_constraint_I08 (operands[2])))))
1487 if (scratch && GET_MODE (scratch) == mode)
1489 emit_move_insn (scratch, operands[2]);
1490 operands[2] = scratch;
1492 else if (can_create_pseudo_p ())
1493 operands[2] = force_reg (mode, operands[2]);
1499 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1501 rtx (*branch_expander) (rtx) = gen_branch_true;
1504 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1507 case NE: case LT: case LE: case LTU: case LEU:
1508 comparison = reverse_condition (comparison);
1509 branch_expander = gen_branch_false;
1512 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1513 gen_rtx_fmt_ee (comparison, SImode,
1514 operands[1], operands[2])));
1515 jump = emit_jump_insn (branch_expander (operands[3]));
1516 if (probability >= 0)
1518 = gen_rtx_EXPR_LIST (REG_BR_PROB, GEN_INT (probability),
1523 /* ??? How should we distribute probabilities when more than one branch
1524 is generated. So far we only have soem ad-hoc observations:
1525 - If the operands are random, they are likely to differ in both parts.
1526 - If comparing items in a hash chain, the operands are random or equal;
1527 operation should be EQ or NE.
1528 - If items are searched in an ordered tree from the root, we can expect
1529 the highpart to be unequal about half of the time; operation should be
1530 an inequality comparison, operands non-constant, and overall probability
1531 about 50%. Likewise for quicksort.
1532 - Range checks will be often made against constants. Even if we assume for
1533 simplicity an even distribution of the non-constant operand over a
1534 sub-range here, the same probability could be generated with differently
1535 wide sub-ranges - as long as the ratio of the part of the subrange that
1536 is before the threshold to the part that comes after the threshold stays
1537 the same. Thus, we can't really tell anything here;
1538 assuming random distribution is at least simple.
1542 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1544 enum rtx_code msw_taken, msw_skip, lsw_taken;
1545 rtx skip_label = NULL_RTX;
1546 rtx op1h, op1l, op2h, op2l;
1549 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1550 rtx scratch = operands[4];
1552 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1553 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1554 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1555 op1l = gen_lowpart (SImode, operands[1]);
1556 op2l = gen_lowpart (SImode, operands[2]);
1557 msw_taken = msw_skip = lsw_taken = CODE_FOR_nothing;
1558 prob = split_branch_probability;
1559 rev_prob = REG_BR_PROB_BASE - prob;
1562 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1563 That costs 1 cycle more when the first branch can be predicted taken,
1564 but saves us mispredicts because only one branch needs prediction.
1565 It also enables generating the cmpeqdi_t-1 pattern. */
1567 if (TARGET_CMPEQDI_T)
1569 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1570 emit_jump_insn (gen_branch_true (operands[3]));
1577 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1579 msw_skip_prob = rev_prob;
1580 if (REG_BR_PROB_BASE <= 65535)
1581 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1584 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1588 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1589 / ((HOST_WIDEST_INT) prob << 32)))
1595 if (TARGET_CMPEQDI_T)
1597 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1598 emit_jump_insn (gen_branch_false (operands[3]));
1602 msw_taken_prob = prob;
1607 msw_taken = comparison;
1608 if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1)
1610 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1611 msw_skip = swap_condition (msw_taken);
1615 if (op2l == CONST0_RTX (SImode))
1616 msw_taken = comparison;
1619 msw_taken = comparison == GE ? GT : GTU;
1620 msw_skip = swap_condition (msw_taken);
1625 msw_taken = comparison;
1626 if (op2l == CONST0_RTX (SImode))
1628 msw_skip = swap_condition (msw_taken);
1632 if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1)
1633 msw_taken = comparison;
1637 if (comparison == LE)
1639 else if (op2h != CONST0_RTX (SImode))
1643 msw_skip = swap_condition (msw_taken);
1646 default: return false;
1648 num_branches = ((msw_taken != CODE_FOR_nothing)
1649 + (msw_skip != CODE_FOR_nothing)
1650 + (lsw_taken != CODE_FOR_nothing));
1651 if (comparison != EQ && comparison != NE && num_branches > 1)
1653 if (!CONSTANT_P (operands[2])
1654 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1655 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1657 msw_taken_prob = prob / 2U;
1659 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1660 lsw_taken_prob = prob;
1664 msw_taken_prob = prob;
1665 msw_skip_prob = REG_BR_PROB_BASE;
1666 /* ??? If we have a constant op2h, should we use that when
1667 calculating lsw_taken_prob? */
1668 lsw_taken_prob = prob;
1673 operands[4] = NULL_RTX;
1674 if (reload_completed
1675 && ! arith_reg_or_0_operand (op2h, SImode) && true_regnum (op1h)
1676 && (msw_taken != CODE_FOR_nothing || msw_skip != CODE_FOR_nothing))
1678 emit_move_insn (scratch, operands[2]);
1679 operands[2] = scratch;
1681 if (msw_taken != CODE_FOR_nothing)
1682 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
1683 if (msw_skip != CODE_FOR_nothing)
1685 rtx taken_label = operands[3];
1687 /* Operands were possibly modified, but msw_skip doesn't expect this.
1688 Always use the original ones. */
1689 if (msw_taken != CODE_FOR_nothing)
1695 operands[3] = skip_label = gen_label_rtx ();
1696 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
1697 operands[3] = taken_label;
1701 if (lsw_taken != CODE_FOR_nothing)
1703 if (reload_completed
1704 && ! arith_reg_or_0_operand (op2l, SImode) && true_regnum (op1l))
1705 operands[4] = scratch;
1706 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
1708 if (msw_skip != CODE_FOR_nothing)
1709 emit_label (skip_label);
1713 /* Prepare the operands for an scc instruction; make sure that the
1714 compare has been done. */
1716 prepare_scc_operands (enum rtx_code code)
1718 rtx t_reg = gen_rtx_REG (SImode, T_REG);
1719 enum rtx_code oldcode = code;
1720 enum machine_mode mode;
1722 /* First need a compare insn. */
1726 /* It isn't possible to handle this case. */
1743 if (code != oldcode)
1745 rtx tmp = sh_compare_op0;
1746 sh_compare_op0 = sh_compare_op1;
1747 sh_compare_op1 = tmp;
1750 mode = GET_MODE (sh_compare_op0);
1751 if (mode == VOIDmode)
1752 mode = GET_MODE (sh_compare_op1);
1754 sh_compare_op0 = force_reg (mode, sh_compare_op0);
1755 if ((code != EQ && code != NE
1756 && (sh_compare_op1 != const0_rtx
1757 || code == GTU || code == GEU || code == LTU || code == LEU))
1758 || (mode == DImode && sh_compare_op1 != const0_rtx)
1759 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1760 sh_compare_op1 = force_reg (mode, sh_compare_op1);
1762 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1763 (mode == SFmode ? emit_sf_insn : emit_df_insn)
1764 (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
1765 gen_rtx_SET (VOIDmode, t_reg,
1766 gen_rtx_fmt_ee (code, SImode,
1767 sh_compare_op0, sh_compare_op1)),
1768 gen_rtx_USE (VOIDmode, get_fpscr_rtx ()))));
1770 emit_insn (gen_rtx_SET (VOIDmode, t_reg,
1771 gen_rtx_fmt_ee (code, SImode,
1772 sh_compare_op0, sh_compare_op1)));
1777 /* Called from the md file, set up the operands of a compare instruction. */
1780 from_compare (rtx *operands, int code)
1782 enum machine_mode mode = GET_MODE (sh_compare_op0);
1784 if (mode == VOIDmode)
1785 mode = GET_MODE (sh_compare_op1);
1788 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1790 /* Force args into regs, since we can't use constants here. */
1791 sh_compare_op0 = force_reg (mode, sh_compare_op0);
1792 if (sh_compare_op1 != const0_rtx
1793 || code == GTU || code == GEU
1794 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1795 sh_compare_op1 = force_reg (mode, sh_compare_op1);
1797 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
1799 from_compare (operands, GT);
1800 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
1803 insn = gen_rtx_SET (VOIDmode,
1804 gen_rtx_REG (SImode, T_REG),
1805 gen_rtx_fmt_ee (code, SImode,
1806 sh_compare_op0, sh_compare_op1));
1807 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1809 insn = gen_rtx_PARALLEL (VOIDmode,
1811 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
1812 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1818 /* Functions to output assembly code. */
1820 /* Return a sequence of instructions to perform DI or DF move.
1822 Since the SH cannot move a DI or DF in one instruction, we have
1823 to take care when we see overlapping source and dest registers. */
1826 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1827 enum machine_mode mode)
1829 rtx dst = operands[0];
1830 rtx src = operands[1];
1832 if (GET_CODE (dst) == MEM
1833 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
1834 return "mov.l %T1,%0\n\tmov.l %1,%0";
1836 if (register_operand (dst, mode)
1837 && register_operand (src, mode))
1839 if (REGNO (src) == MACH_REG)
1840 return "sts mach,%S0\n\tsts macl,%R0";
1842 /* When mov.d r1,r2 do r2->r3 then r1->r2;
1843 when mov.d r1,r0 do r1->r0 then r2->r1. */
1845 if (REGNO (src) + 1 == REGNO (dst))
1846 return "mov %T1,%T0\n\tmov %1,%0";
1848 return "mov %1,%0\n\tmov %T1,%T0";
1850 else if (GET_CODE (src) == CONST_INT)
1852 if (INTVAL (src) < 0)
1853 output_asm_insn ("mov #-1,%S0", operands);
1855 output_asm_insn ("mov #0,%S0", operands);
1857 return "mov %1,%R0";
1859 else if (GET_CODE (src) == MEM)
1862 int dreg = REGNO (dst);
1863 rtx inside = XEXP (src, 0);
1865 switch (GET_CODE (inside))
1868 ptrreg = REGNO (inside);
1872 ptrreg = subreg_regno (inside);
1876 ptrreg = REGNO (XEXP (inside, 0));
1877 /* ??? A r0+REG address shouldn't be possible here, because it isn't
1878 an offsettable address. Unfortunately, offsettable addresses use
1879 QImode to check the offset, and a QImode offsettable address
1880 requires r0 for the other operand, which is not currently
1881 supported, so we can't use the 'o' constraint.
1882 Thus we must check for and handle r0+REG addresses here.
1883 We punt for now, since this is likely very rare. */
1884 gcc_assert (GET_CODE (XEXP (inside, 1)) != REG);
1888 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
1890 return "mov.l %1,%0\n\tmov.l %1,%T0";
1895 /* Work out the safe way to copy. Copy into the second half first. */
1897 return "mov.l %T1,%T0\n\tmov.l %1,%0";
1900 return "mov.l %1,%0\n\tmov.l %T1,%T0";
1903 /* Print an instruction which would have gone into a delay slot after
1904 another instruction, but couldn't because the other instruction expanded
1905 into a sequence where putting the slot insn at the end wouldn't work. */
1908 print_slot (rtx insn)
1910 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
1912 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
1916 output_far_jump (rtx insn, rtx op)
1918 struct { rtx lab, reg, op; } this_jmp;
1919 rtx braf_base_lab = NULL_RTX;
1922 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
1925 this_jmp.lab = gen_label_rtx ();
1929 && offset - get_attr_length (insn) <= 32766)
1932 jump = "mov.w %O0,%1; braf %1";
1940 jump = "mov.l %O0,%1; braf %1";
1942 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1945 jump = "mov.l %O0,%1; jmp @%1";
1947 /* If we have a scratch register available, use it. */
1948 if (GET_CODE ((prev = prev_nonnote_insn (insn))) == INSN
1949 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
1951 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
1952 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
1953 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1954 output_asm_insn (jump, &this_jmp.lab);
1955 if (dbr_sequence_length ())
1956 print_slot (final_sequence);
1958 output_asm_insn ("nop", 0);
1962 /* Output the delay slot insn first if any. */
1963 if (dbr_sequence_length ())
1964 print_slot (final_sequence);
1966 this_jmp.reg = gen_rtx_REG (SImode, 13);
1967 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1968 Fortunately, MACL is fixed and call-clobbered, and we never
1969 need its value across jumps, so save r13 in it instead of in
1972 output_asm_insn ("lds r13, macl", 0);
1974 output_asm_insn ("mov.l r13,@-r15", 0);
1975 output_asm_insn (jump, &this_jmp.lab);
1977 output_asm_insn ("sts macl, r13", 0);
1979 output_asm_insn ("mov.l @r15+,r13", 0);
1981 if (far && flag_pic && TARGET_SH2)
1983 braf_base_lab = gen_label_rtx ();
1984 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1985 CODE_LABEL_NUMBER (braf_base_lab));
1988 output_asm_insn (".align 2", 0);
1989 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
1991 if (far && flag_pic)
1994 this_jmp.lab = braf_base_lab;
1995 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
1998 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2002 /* Local label counter, used for constants in the pool and inside
2003 pattern branches. */
2005 static int lf = 100;
2007 /* Output code for ordinary branches. */
2010 output_branch (int logic, rtx insn, rtx *operands)
2012 switch (get_attr_length (insn))
2015 /* This can happen if filling the delay slot has caused a forward
2016 branch to exceed its range (we could reverse it, but only
2017 when we know we won't overextend other branches; this should
2018 best be handled by relaxation).
2019 It can also happen when other condbranches hoist delay slot insn
2020 from their destination, thus leading to code size increase.
2021 But the branch will still be in the range -4092..+4098 bytes. */
2026 /* The call to print_slot will clobber the operands. */
2027 rtx op0 = operands[0];
2029 /* If the instruction in the delay slot is annulled (true), then
2030 there is no delay slot where we can put it now. The only safe
2031 place for it is after the label. final will do that by default. */
2034 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2035 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2037 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2038 ASSEMBLER_DIALECT ? "/" : ".", label);
2039 print_slot (final_sequence);
2042 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2044 output_asm_insn ("bra\t%l0", &op0);
2045 fprintf (asm_out_file, "\tnop\n");
2046 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2050 /* When relaxing, handle this like a short branch. The linker
2051 will fix it up if it still doesn't fit after relaxation. */
2053 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2055 /* These are for SH2e, in which we have to account for the
2056 extra nop because of the hardware bug in annulled branches. */
2062 gcc_assert (!final_sequence
2063 || !(INSN_ANNULLED_BRANCH_P
2064 (XVECEXP (final_sequence, 0, 0))));
2065 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2067 ASSEMBLER_DIALECT ? "/" : ".", label);
2068 fprintf (asm_out_file, "\tnop\n");
2069 output_asm_insn ("bra\t%l0", operands);
2070 fprintf (asm_out_file, "\tnop\n");
2071 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2075 /* When relaxing, fall through. */
2080 sprintf (buffer, "b%s%ss\t%%l0",
2082 ASSEMBLER_DIALECT ? "/" : ".");
2083 output_asm_insn (buffer, &operands[0]);
2088 /* There should be no longer branches now - that would
2089 indicate that something has destroyed the branches set
2090 up in machine_dependent_reorg. */
2095 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2096 fill in operands 9 as a label to the successor insn.
2097 We try to use jump threading where possible.
2098 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2099 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2100 follow jmp and bt, if the address is in range. */
2102 output_branchy_insn (enum rtx_code code, const char *templ,
2103 rtx insn, rtx *operands)
2105 rtx next_insn = NEXT_INSN (insn);
2107 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
2109 rtx src = SET_SRC (PATTERN (next_insn));
2110 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2112 /* Following branch not taken */
2113 operands[9] = gen_label_rtx ();
2114 emit_label_after (operands[9], next_insn);
2115 INSN_ADDRESSES_NEW (operands[9],
2116 INSN_ADDRESSES (INSN_UID (next_insn))
2117 + get_attr_length (next_insn));
2122 int offset = (branch_dest (next_insn)
2123 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2124 if (offset >= -252 && offset <= 258)
2126 if (GET_CODE (src) == IF_THEN_ELSE)
2128 src = XEXP (src, 1);
2134 operands[9] = gen_label_rtx ();
2135 emit_label_after (operands[9], insn);
2136 INSN_ADDRESSES_NEW (operands[9],
2137 INSN_ADDRESSES (INSN_UID (insn))
2138 + get_attr_length (insn));
2143 output_ieee_ccmpeq (rtx insn, rtx *operands)
2145 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2149 /* Output the start of the assembler file. */
2152 sh_file_start (void)
2154 default_file_start ();
2157 /* Declare the .directive section before it is used. */
2158 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2159 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2163 /* We need to show the text section with the proper
2164 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2165 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2166 will complain. We can teach GAS specifically about the
2167 default attributes for our choice of text section, but
2168 then we would have to change GAS again if/when we change
2169 the text section name. */
2170 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2172 /* Switch to the data section so that the coffsem symbol
2173 isn't in the text section. */
2174 switch_to_section (data_section);
2176 if (TARGET_LITTLE_ENDIAN)
2177 fputs ("\t.little\n", asm_out_file);
2181 if (TARGET_SHCOMPACT)
2182 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2183 else if (TARGET_SHMEDIA)
2184 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2185 TARGET_SHMEDIA64 ? 64 : 32);
2189 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2192 unspec_caller_rtx_p (rtx pat)
2194 switch (GET_CODE (pat))
2197 return unspec_caller_rtx_p (XEXP (pat, 0));
2200 if (unspec_caller_rtx_p (XEXP (pat, 0)))
2202 return unspec_caller_rtx_p (XEXP (pat, 1));
2204 if (XINT (pat, 1) == UNSPEC_CALLER)
2213 /* Indicate that INSN cannot be duplicated. This is true for insn
2214 that generates a unique label. */
2217 sh_cannot_copy_insn_p (rtx insn)
2221 if (!reload_completed || !flag_pic)
2224 if (GET_CODE (insn) != INSN)
2226 if (asm_noperands (insn) >= 0)
2229 pat = PATTERN (insn);
2230 if (GET_CODE (pat) != SET)
2232 pat = SET_SRC (pat);
2234 if (unspec_caller_rtx_p (pat))
2240 /* Actual number of instructions used to make a shift by N. */
2241 static const char ashiftrt_insns[] =
2242 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2244 /* Left shift and logical right shift are the same. */
2245 static const char shift_insns[] =
2246 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2248 /* Individual shift amounts needed to get the above length sequences.
2249 One bit right shifts clobber the T bit, so when possible, put one bit
2250 shifts in the middle of the sequence, so the ends are eligible for
2251 branch delay slots. */
2252 static const short shift_amounts[32][5] = {
2253 {0}, {1}, {2}, {2, 1},
2254 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2255 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2256 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2257 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2258 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2259 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2260 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2262 /* Likewise, but for shift amounts < 16, up to three highmost bits
2263 might be clobbered. This is typically used when combined with some
2264 kind of sign or zero extension. */
2266 static const char ext_shift_insns[] =
2267 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2269 static const short ext_shift_amounts[32][4] = {
2270 {0}, {1}, {2}, {2, 1},
2271 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2272 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2273 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2274 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2275 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2276 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2277 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2279 /* Assuming we have a value that has been sign-extended by at least one bit,
2280 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2281 to shift it by N without data loss, and quicker than by other means? */
2282 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2284 /* This is used in length attributes in sh.md to help compute the length
2285 of arbitrary constant shift instructions. */
2288 shift_insns_rtx (rtx insn)
2290 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2291 int shift_count = INTVAL (XEXP (set_src, 1));
2292 enum rtx_code shift_code = GET_CODE (set_src);
2297 return ashiftrt_insns[shift_count];
2300 return shift_insns[shift_count];
2306 /* Return the cost of a shift. */
2316 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2318 if (GET_MODE (x) == DImode
2319 && GET_CODE (XEXP (x, 1)) == CONST_INT
2320 && INTVAL (XEXP (x, 1)) == 1)
2323 /* Everything else is invalid, because there is no pattern for it. */
2326 /* If shift by a non constant, then this will be expensive. */
2327 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2328 return SH_DYNAMIC_SHIFT_COST;
2330 value = INTVAL (XEXP (x, 1));
2332 /* Otherwise, return the true cost in instructions. */
2333 if (GET_CODE (x) == ASHIFTRT)
2335 int cost = ashiftrt_insns[value];
2336 /* If SH3, then we put the constant in a reg and use shad. */
2337 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2338 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2342 return shift_insns[value];
2345 /* Return the cost of an AND operation. */
2352 /* Anding with a register is a single cycle and instruction. */
2353 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2356 i = INTVAL (XEXP (x, 1));
2360 if (satisfies_constraint_I10 (XEXP (x, 1))
2361 || satisfies_constraint_J16 (XEXP (x, 1)))
2364 return 1 + rtx_cost (XEXP (x, 1), AND, !optimize_size);
2367 /* These constants are single cycle extu.[bw] instructions. */
2368 if (i == 0xff || i == 0xffff)
2370 /* Constants that can be used in an and immediate instruction in a single
2371 cycle, but this requires r0, so make it a little more expensive. */
2372 if (CONST_OK_FOR_K08 (i))
2374 /* Constants that can be loaded with a mov immediate and an and.
2375 This case is probably unnecessary. */
2376 if (CONST_OK_FOR_I08 (i))
2378 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2379 This case is probably unnecessary. */
2383 /* Return the cost of an addition or a subtraction. */
2388 /* Adding a register is a single cycle insn. */
2389 if (GET_CODE (XEXP (x, 1)) == REG
2390 || GET_CODE (XEXP (x, 1)) == SUBREG)
2393 /* Likewise for small constants. */
2394 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2395 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2399 switch (GET_CODE (XEXP (x, 1)))
2404 return TARGET_SHMEDIA64 ? 5 : 3;
2407 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2409 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2411 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2419 /* Any other constant requires a 2 cycle pc-relative load plus an
2424 /* Return the cost of a multiply. */
2426 multcosts (rtx x ATTRIBUTE_UNUSED)
2428 if (sh_multcost >= 0)
2431 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2432 accept constants. Ideally, we would use a cost of one or two and
2433 add the cost of the operand, but disregard the latter when inside loops
2434 and loop invariant code motion is still to follow.
2435 Using a multiply first and splitting it later if it's a loss
2436 doesn't work because of different sign / zero extension semantics
2437 of multiplies vs. shifts. */
2438 return TARGET_SMALLCODE ? 2 : 3;
2442 /* We have a mul insn, so we can never take more than the mul and the
2443 read of the mac reg, but count more because of the latency and extra
2445 if (TARGET_SMALLCODE)
2450 /* If we're aiming at small code, then just count the number of
2451 insns in a multiply call sequence. */
2452 if (TARGET_SMALLCODE)
2455 /* Otherwise count all the insns in the routine we'd be calling too. */
2459 /* Compute a (partial) cost for rtx X. Return true if the complete
2460 cost has been computed, and false if subexpressions should be
2461 scanned. In either case, *TOTAL contains the cost result. */
2464 sh_rtx_costs (rtx x, int code, int outer_code, int *total,
2465 bool speed ATTRIBUTE_UNUSED)
2472 if (INTVAL (x) == 0)
2474 else if (outer_code == AND && and_operand ((x), DImode))
2476 else if ((outer_code == IOR || outer_code == XOR
2477 || outer_code == PLUS)
2478 && CONST_OK_FOR_I10 (INTVAL (x)))
2480 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2481 *total = COSTS_N_INSNS (outer_code != SET);
2482 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2483 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2484 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2485 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2487 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2490 if (CONST_OK_FOR_I08 (INTVAL (x)))
2492 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2493 && CONST_OK_FOR_K08 (INTVAL (x)))
2495 /* prepare_cmp_insn will force costly constants int registers before
2496 the cbranch[sd]i4 patterns can see them, so preserve potentially
2497 interesting ones not covered by I08 above. */
2498 else if (outer_code == COMPARE
2499 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2500 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2501 || INTVAL (x) == 0x7fffffff
2502 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2511 if (TARGET_SHMEDIA64)
2512 *total = COSTS_N_INSNS (4);
2513 else if (TARGET_SHMEDIA32)
2514 *total = COSTS_N_INSNS (2);
2521 *total = COSTS_N_INSNS (4);
2522 /* prepare_cmp_insn will force costly constants int registers before
2523 the cbranchdi4 pattern can see them, so preserve potentially
2524 interesting ones. */
2525 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
2531 if (x == CONST0_RTX (GET_MODE (x)))
2533 else if (sh_1el_vec (x, VOIDmode))
2534 *total = outer_code != SET;
2535 if (sh_rep_vec (x, VOIDmode))
2536 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2537 + (outer_code != SET));
2538 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2543 *total = COSTS_N_INSNS (addsubcosts (x));
2547 *total = COSTS_N_INSNS (andcosts (x));
2551 *total = COSTS_N_INSNS (multcosts (x));
2557 *total = COSTS_N_INSNS (shiftcosts (x));
2564 *total = COSTS_N_INSNS (20);
2568 if (sh_1el_vec (x, VOIDmode))
2569 *total = outer_code != SET;
2570 if (sh_rep_vec (x, VOIDmode))
2571 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2572 + (outer_code != SET));
2573 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2586 /* Compute the cost of an address. For the SH, all valid addresses are
2587 the same cost. Use a slightly higher cost for reg + reg addressing,
2588 since it increases pressure on r0. */
2591 sh_address_cost (rtx X,
2592 bool speed ATTRIBUTE_UNUSED)
2594 return (GET_CODE (X) == PLUS
2595 && ! CONSTANT_P (XEXP (X, 1))
2596 && ! TARGET_SHMEDIA ? 1 : 0);
2599 /* Code to expand a shift. */
2602 gen_ashift (int type, int n, rtx reg)
2604 /* Negative values here come from the shift_amounts array. */
2617 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
2621 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
2623 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
2626 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
2631 /* Same for HImode */
2634 gen_ashift_hi (int type, int n, rtx reg)
2636 /* Negative values here come from the shift_amounts array. */
2650 /* We don't have HImode right shift operations because using the
2651 ordinary 32 bit shift instructions for that doesn't generate proper
2652 zero/sign extension.
2653 gen_ashift_hi is only called in contexts where we know that the
2654 sign extension works out correctly. */
2657 if (GET_CODE (reg) == SUBREG)
2659 offset = SUBREG_BYTE (reg);
2660 reg = SUBREG_REG (reg);
2662 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
2666 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
2671 /* Output RTL to split a constant shift into its component SH constant
2672 shift instructions. */
2675 gen_shifty_op (int code, rtx *operands)
2677 int value = INTVAL (operands[2]);
2680 /* Truncate the shift count in case it is out of bounds. */
2681 value = value & 0x1f;
2685 if (code == LSHIFTRT)
2687 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2688 emit_insn (gen_movt (operands[0]));
2691 else if (code == ASHIFT)
2693 /* There is a two instruction sequence for 31 bit left shifts,
2694 but it requires r0. */
2695 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
2697 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
2698 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2703 else if (value == 0)
2705 /* This can happen even when optimizing, if there were subregs before
2706 reload. Don't output a nop here, as this is never optimized away;
2707 use a no-op move instead. */
2708 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
2712 max = shift_insns[value];
2713 for (i = 0; i < max; i++)
2714 gen_ashift (code, shift_amounts[value][i], operands[0]);
2717 /* Same as above, but optimized for values where the topmost bits don't
2721 gen_shifty_hi_op (int code, rtx *operands)
2723 int value = INTVAL (operands[2]);
2725 void (*gen_fun) (int, int, rtx);
2727 /* This operation is used by and_shl for SImode values with a few
2728 high bits known to be cleared. */
2732 emit_insn (gen_nop ());
2736 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
2739 max = ext_shift_insns[value];
2740 for (i = 0; i < max; i++)
2741 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2744 /* When shifting right, emit the shifts in reverse order, so that
2745 solitary negative values come first. */
2746 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
2747 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2750 /* Output RTL for an arithmetic right shift. */
2752 /* ??? Rewrite to use super-optimizer sequences. */
2755 expand_ashiftrt (rtx *operands)
2763 if (GET_CODE (operands[2]) != CONST_INT)
2765 rtx count = copy_to_mode_reg (SImode, operands[2]);
2766 emit_insn (gen_negsi2 (count, count));
2767 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2770 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
2771 > 1 + SH_DYNAMIC_SHIFT_COST)
2774 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
2775 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2779 if (GET_CODE (operands[2]) != CONST_INT)
2782 value = INTVAL (operands[2]) & 31;
2786 /* If we are called from abs expansion, arrange things so that we
2787 we can use a single MT instruction that doesn't clobber the source,
2788 if LICM can hoist out the load of the constant zero. */
2789 if (currently_expanding_to_rtl)
2791 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
2793 emit_insn (gen_mov_neg_si_t (operands[0]));
2796 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
2799 else if (value >= 16 && value <= 19)
2801 wrk = gen_reg_rtx (SImode);
2802 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
2805 gen_ashift (ASHIFTRT, 1, wrk);
2806 emit_move_insn (operands[0], wrk);
2809 /* Expand a short sequence inline, longer call a magic routine. */
2810 else if (value <= 5)
2812 wrk = gen_reg_rtx (SImode);
2813 emit_move_insn (wrk, operands[1]);
2815 gen_ashift (ASHIFTRT, 1, wrk);
2816 emit_move_insn (operands[0], wrk);
2820 wrk = gen_reg_rtx (Pmode);
2822 /* Load the value into an arg reg and call a helper. */
2823 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2824 sprintf (func, "__ashiftrt_r4_%d", value);
2825 function_symbol (wrk, func, SFUNC_STATIC);
2826 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
2827 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
2832 sh_dynamicalize_shift_p (rtx count)
2834 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
2837 /* Try to find a good way to implement the combiner pattern
2838 [(set (match_operand:SI 0 "register_operand" "r")
2839 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2840 (match_operand:SI 2 "const_int_operand" "n"))
2841 (match_operand:SI 3 "const_int_operand" "n"))) .
2842 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
2843 return 0 for simple right / left or left/right shift combination.
2844 return 1 for a combination of shifts with zero_extend.
2845 return 2 for a combination of shifts with an AND that needs r0.
2846 return 3 for a combination of shifts with an AND that needs an extra
2847 scratch register, when the three highmost bits of the AND mask are clear.
2848 return 4 for a combination of shifts with an AND that needs an extra
2849 scratch register, when any of the three highmost bits of the AND mask
2851 If ATTRP is set, store an initial right shift width in ATTRP[0],
2852 and the instruction length in ATTRP[1] . These values are not valid
2854 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
2855 shift_amounts for the last shift value that is to be used before the
2858 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
2860 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
2861 int left = INTVAL (left_rtx), right;
2863 int cost, best_cost = 10000;
2864 int best_right = 0, best_len = 0;
2868 if (left < 0 || left > 31)
2870 if (GET_CODE (mask_rtx) == CONST_INT)
2871 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
2873 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
2874 /* Can this be expressed as a right shift / left shift pair? */
2875 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
2876 right = exact_log2 (lsb);
2877 mask2 = ~(mask + lsb - 1);
2878 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
2879 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
2881 best_cost = shift_insns[right] + shift_insns[right + left];
2882 /* mask has no trailing zeroes <==> ! right */
2883 else if (! right && mask2 == ~(lsb2 - 1))
2885 int late_right = exact_log2 (lsb2);
2886 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
2888 /* Try to use zero extend. */
2889 if (mask2 == ~(lsb2 - 1))
2893 for (width = 8; width <= 16; width += 8)
2895 /* Can we zero-extend right away? */
2896 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
2899 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
2900 if (cost < best_cost)
2911 /* ??? Could try to put zero extend into initial right shift,
2912 or even shift a bit left before the right shift. */
2913 /* Determine value of first part of left shift, to get to the
2914 zero extend cut-off point. */
2915 first = width - exact_log2 (lsb2) + right;
2916 if (first >= 0 && right + left - first >= 0)
2918 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
2919 + ext_shift_insns[right + left - first];
2920 if (cost < best_cost)
2932 /* Try to use r0 AND pattern */
2933 for (i = 0; i <= 2; i++)
2937 if (! CONST_OK_FOR_K08 (mask >> i))
2939 cost = (i != 0) + 2 + ext_shift_insns[left + i];
2940 if (cost < best_cost)
2945 best_len = cost - 1;
2948 /* Try to use a scratch register to hold the AND operand. */
2949 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
2950 for (i = 0; i <= 2; i++)
2954 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
2955 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
2956 if (cost < best_cost)
2961 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
2967 attrp[0] = best_right;
2968 attrp[1] = best_len;
2973 /* This is used in length attributes of the unnamed instructions
2974 corresponding to shl_and_kind return values of 1 and 2. */
2976 shl_and_length (rtx insn)
2978 rtx set_src, left_rtx, mask_rtx;
2981 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2982 left_rtx = XEXP (XEXP (set_src, 0), 1);
2983 mask_rtx = XEXP (set_src, 1);
2984 shl_and_kind (left_rtx, mask_rtx, attributes);
2985 return attributes[1];
2988 /* This is used in length attribute of the and_shl_scratch instruction. */
2991 shl_and_scr_length (rtx insn)
2993 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2994 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
2995 rtx op = XEXP (set_src, 0);
2996 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
2997 op = XEXP (XEXP (op, 0), 0);
2998 return len + shift_insns[INTVAL (XEXP (op, 1))];
3001 /* Generate rtl for instructions for which shl_and_kind advised a particular
3002 method of generating them, i.e. returned zero. */
3005 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
3008 unsigned HOST_WIDE_INT mask;
3009 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3010 int right, total_shift;
3011 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
3013 right = attributes[0];
3014 total_shift = INTVAL (left_rtx) + right;
3015 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3022 int first = attributes[2];
3027 emit_insn ((mask << right) <= 0xff
3028 ? gen_zero_extendqisi2 (dest,
3029 gen_lowpart (QImode, source))
3030 : gen_zero_extendhisi2 (dest,
3031 gen_lowpart (HImode, source)));
3035 emit_insn (gen_movsi (dest, source));
3039 operands[2] = GEN_INT (right);
3040 gen_shifty_hi_op (LSHIFTRT, operands);
3044 operands[2] = GEN_INT (first);
3045 gen_shifty_hi_op (ASHIFT, operands);
3046 total_shift -= first;
3050 emit_insn (mask <= 0xff
3051 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3052 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3053 if (total_shift > 0)
3055 operands[2] = GEN_INT (total_shift);
3056 gen_shifty_hi_op (ASHIFT, operands);
3061 shift_gen_fun = gen_shifty_op;
3063 /* If the topmost bit that matters is set, set the topmost bits
3064 that don't matter. This way, we might be able to get a shorter
3066 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3067 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3069 /* Don't expand fine-grained when combining, because that will
3070 make the pattern fail. */
3071 if (currently_expanding_to_rtl
3072 || reload_in_progress || reload_completed)
3076 /* Cases 3 and 4 should be handled by this split
3077 only while combining */
3078 gcc_assert (kind <= 2);
3081 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3084 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3089 operands[2] = GEN_INT (total_shift);
3090 shift_gen_fun (ASHIFT, operands);
3097 if (kind != 4 && total_shift < 16)
3099 neg = -ext_shift_amounts[total_shift][1];
3101 neg -= ext_shift_amounts[total_shift][2];
3105 emit_insn (gen_and_shl_scratch (dest, source,
3108 GEN_INT (total_shift + neg),
3110 emit_insn (gen_movsi (dest, dest));
3117 /* Try to find a good way to implement the combiner pattern
3118 [(set (match_operand:SI 0 "register_operand" "=r")
3119 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3120 (match_operand:SI 2 "const_int_operand" "n")
3121 (match_operand:SI 3 "const_int_operand" "n")
3123 (clobber (reg:SI T_REG))]
3124 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3125 return 0 for simple left / right shift combination.
3126 return 1 for left shift / 8 bit sign extend / left shift.
3127 return 2 for left shift / 16 bit sign extend / left shift.
3128 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3129 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3130 return 5 for left shift / 16 bit sign extend / right shift
3131 return 6 for < 8 bit sign extend / left shift.
3132 return 7 for < 8 bit sign extend / left shift / single right shift.
3133 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3136 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3138 int left, size, insize, ext;
3139 int cost = 0, best_cost;
3142 left = INTVAL (left_rtx);
3143 size = INTVAL (size_rtx);
3144 insize = size - left;
3145 gcc_assert (insize > 0);
3146 /* Default to left / right shift. */
3148 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3151 /* 16 bit shift / sign extend / 16 bit shift */
3152 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3153 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3154 below, by alternative 3 or something even better. */
3155 if (cost < best_cost)
3161 /* Try a plain sign extend between two shifts. */
3162 for (ext = 16; ext >= insize; ext -= 8)
3166 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3167 if (cost < best_cost)
3169 kind = ext / (unsigned) 8;
3173 /* Check if we can do a sloppy shift with a final signed shift
3174 restoring the sign. */
3175 if (EXT_SHIFT_SIGNED (size - ext))
3176 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3177 /* If not, maybe it's still cheaper to do the second shift sloppy,
3178 and do a final sign extend? */
3179 else if (size <= 16)
3180 cost = ext_shift_insns[ext - insize] + 1
3181 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3184 if (cost < best_cost)
3186 kind = ext / (unsigned) 8 + 2;
3190 /* Check if we can sign extend in r0 */
3193 cost = 3 + shift_insns[left];
3194 if (cost < best_cost)
3199 /* Try the same with a final signed shift. */
3202 cost = 3 + ext_shift_insns[left + 1] + 1;
3203 if (cost < best_cost)
3212 /* Try to use a dynamic shift. */
3213 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3214 if (cost < best_cost)
3225 /* Function to be used in the length attribute of the instructions
3226 implementing this pattern. */
3229 shl_sext_length (rtx insn)
3231 rtx set_src, left_rtx, size_rtx;
3234 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3235 left_rtx = XEXP (XEXP (set_src, 0), 1);
3236 size_rtx = XEXP (set_src, 1);
3237 shl_sext_kind (left_rtx, size_rtx, &cost);
3241 /* Generate rtl for this pattern */
3244 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3247 int left, size, insize, cost;
3250 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3251 left = INTVAL (left_rtx);
3252 size = INTVAL (size_rtx);
3253 insize = size - left;
3261 int ext = kind & 1 ? 8 : 16;
3262 int shift2 = size - ext;
3264 /* Don't expand fine-grained when combining, because that will
3265 make the pattern fail. */
3266 if (! currently_expanding_to_rtl
3267 && ! reload_in_progress && ! reload_completed)
3269 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3270 emit_insn (gen_movsi (dest, source));
3274 emit_insn (gen_movsi (dest, source));
3278 operands[2] = GEN_INT (ext - insize);
3279 gen_shifty_hi_op (ASHIFT, operands);
3282 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3283 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3288 operands[2] = GEN_INT (shift2);
3289 gen_shifty_op (ASHIFT, operands);
3296 if (EXT_SHIFT_SIGNED (shift2))
3298 operands[2] = GEN_INT (shift2 + 1);
3299 gen_shifty_op (ASHIFT, operands);
3300 operands[2] = const1_rtx;
3301 gen_shifty_op (ASHIFTRT, operands);
3304 operands[2] = GEN_INT (shift2);
3305 gen_shifty_hi_op (ASHIFT, operands);
3309 operands[2] = GEN_INT (-shift2);
3310 gen_shifty_hi_op (LSHIFTRT, operands);
3312 emit_insn (size <= 8
3313 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3314 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3321 if (! currently_expanding_to_rtl
3322 && ! reload_in_progress && ! reload_completed)
3323 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3327 operands[2] = GEN_INT (16 - insize);
3328 gen_shifty_hi_op (ASHIFT, operands);
3329 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3331 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3333 gen_ashift (ASHIFTRT, 1, dest);
3338 /* Don't expand fine-grained when combining, because that will
3339 make the pattern fail. */
3340 if (! currently_expanding_to_rtl
3341 && ! reload_in_progress && ! reload_completed)
3343 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3344 emit_insn (gen_movsi (dest, source));
3347 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3348 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3349 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3351 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3352 gen_shifty_op (ASHIFT, operands);
3354 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3362 /* Prefix a symbol_ref name with "datalabel". */
3365 gen_datalabel_ref (rtx sym)
3369 if (GET_CODE (sym) == LABEL_REF)
3370 return gen_rtx_CONST (GET_MODE (sym),
3371 gen_rtx_UNSPEC (GET_MODE (sym),
3375 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3377 str = XSTR (sym, 0);
3378 /* Share all SYMBOL_REF strings with the same value - that is important
3380 str = IDENTIFIER_POINTER (get_identifier (str));
3381 XSTR (sym, 0) = str;
3387 static alloc_pool label_ref_list_pool;
3389 typedef struct label_ref_list_d
3392 struct label_ref_list_d *next;
3393 } *label_ref_list_t;
3395 /* The SH cannot load a large constant into a register, constants have to
3396 come from a pc relative load. The reference of a pc relative load
3397 instruction must be less than 1k in front of the instruction. This
3398 means that we often have to dump a constant inside a function, and
3399 generate code to branch around it.
3401 It is important to minimize this, since the branches will slow things
3402 down and make things bigger.
3404 Worst case code looks like:
3422 We fix this by performing a scan before scheduling, which notices which
3423 instructions need to have their operands fetched from the constant table
3424 and builds the table.
3428 scan, find an instruction which needs a pcrel move. Look forward, find the
3429 last barrier which is within MAX_COUNT bytes of the requirement.
3430 If there isn't one, make one. Process all the instructions between
3431 the find and the barrier.
3433 In the above example, we can tell that L3 is within 1k of L1, so
3434 the first move can be shrunk from the 3 insn+constant sequence into
3435 just 1 insn, and the constant moved to L3 to make:
3446 Then the second move becomes the target for the shortening process. */
3450 rtx value; /* Value in table. */
3451 rtx label; /* Label of value. */
3452 label_ref_list_t wend; /* End of window. */
3453 enum machine_mode mode; /* Mode of value. */
3455 /* True if this constant is accessed as part of a post-increment
3456 sequence. Note that HImode constants are never accessed in this way. */
3457 bool part_of_sequence_p;
3460 /* The maximum number of constants that can fit into one pool, since
3461 constants in the range 0..510 are at least 2 bytes long, and in the
3462 range from there to 1018 at least 4 bytes. */
3464 #define MAX_POOL_SIZE 372
3465 static pool_node pool_vector[MAX_POOL_SIZE];
3466 static int pool_size;
3467 static rtx pool_window_label;
3468 static int pool_window_last;
3470 static int max_labelno_before_reorg;
3472 /* ??? If we need a constant in HImode which is the truncated value of a
3473 constant we need in SImode, we could combine the two entries thus saving
3474 two bytes. Is this common enough to be worth the effort of implementing
3477 /* ??? This stuff should be done at the same time that we shorten branches.
3478 As it is now, we must assume that all branches are the maximum size, and
3479 this causes us to almost always output constant pools sooner than
3482 /* Add a constant to the pool and return its label. */
3485 add_constant (rtx x, enum machine_mode mode, rtx last_value)
3489 label_ref_list_t ref, newref;
3491 /* First see if we've already got it. */
3492 for (i = 0; i < pool_size; i++)
3494 if (x->code == pool_vector[i].value->code
3495 && mode == pool_vector[i].mode)
3497 if (x->code == CODE_LABEL)
3499 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3502 if (rtx_equal_p (x, pool_vector[i].value))
3507 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3509 new_rtx = gen_label_rtx ();
3510 LABEL_REFS (new_rtx) = pool_vector[i].label;
3511 pool_vector[i].label = lab = new_rtx;
3513 if (lab && pool_window_label)
3515 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3516 newref->label = pool_window_label;
3517 ref = pool_vector[pool_window_last].wend;
3519 pool_vector[pool_window_last].wend = newref;
3522 pool_window_label = new_rtx;
3523 pool_window_last = i;
3529 /* Need a new one. */
3530 pool_vector[pool_size].value = x;
3531 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3534 pool_vector[pool_size - 1].part_of_sequence_p = true;
3537 lab = gen_label_rtx ();
3538 pool_vector[pool_size].mode = mode;
3539 pool_vector[pool_size].label = lab;
3540 pool_vector[pool_size].wend = NULL;
3541 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
3542 if (lab && pool_window_label)
3544 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3545 newref->label = pool_window_label;
3546 ref = pool_vector[pool_window_last].wend;
3548 pool_vector[pool_window_last].wend = newref;
3551 pool_window_label = lab;
3552 pool_window_last = pool_size;
3557 /* Output the literal table. START, if nonzero, is the first instruction
3558 this table is needed for, and also indicates that there is at least one
3559 casesi_worker_2 instruction; We have to emit the operand3 labels from
3560 these insns at a 4-byte aligned position. BARRIER is the barrier
3561 after which we are to place the table. */
3564 dump_table (rtx start, rtx barrier)
3570 label_ref_list_t ref;
3573 /* Do two passes, first time dump out the HI sized constants. */
3575 for (i = 0; i < pool_size; i++)
3577 pool_node *p = &pool_vector[i];
3579 if (p->mode == HImode)
3583 scan = emit_insn_after (gen_align_2 (), scan);
3586 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3587 scan = emit_label_after (lab, scan);
3588 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
3590 for (ref = p->wend; ref; ref = ref->next)
3593 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3596 else if (p->mode == DFmode)
3604 scan = emit_insn_after (gen_align_4 (), scan);
3606 for (; start != barrier; start = NEXT_INSN (start))
3607 if (GET_CODE (start) == INSN
3608 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
3610 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
3611 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
3613 scan = emit_label_after (lab, scan);
3616 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
3618 rtx align_insn = NULL_RTX;
3620 scan = emit_label_after (gen_label_rtx (), scan);
3621 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3624 for (i = 0; i < pool_size; i++)
3626 pool_node *p = &pool_vector[i];
3634 if (align_insn && !p->part_of_sequence_p)
3636 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3637 emit_label_before (lab, align_insn);
3638 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
3640 for (ref = p->wend; ref; ref = ref->next)
3643 emit_insn_before (gen_consttable_window_end (lab),
3646 delete_insn (align_insn);
3647 align_insn = NULL_RTX;
3652 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3653 scan = emit_label_after (lab, scan);
3654 scan = emit_insn_after (gen_consttable_4 (p->value,
3656 need_align = ! need_align;
3662 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3667 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3668 scan = emit_label_after (lab, scan);
3669 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3676 if (p->mode != HImode)
3678 for (ref = p->wend; ref; ref = ref->next)
3681 scan = emit_insn_after (gen_consttable_window_end (lab),
3690 for (i = 0; i < pool_size; i++)
3692 pool_node *p = &pool_vector[i];
3703 scan = emit_label_after (gen_label_rtx (), scan);
3704 scan = emit_insn_after (gen_align_4 (), scan);
3706 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3707 scan = emit_label_after (lab, scan);
3708 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
3716 scan = emit_label_after (gen_label_rtx (), scan);
3717 scan = emit_insn_after (gen_align_4 (), scan);
3719 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3720 scan = emit_label_after (lab, scan);
3721 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3728 if (p->mode != HImode)
3730 for (ref = p->wend; ref; ref = ref->next)
3733 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3738 scan = emit_insn_after (gen_consttable_end (), scan);
3739 scan = emit_barrier_after (scan);
3741 pool_window_label = NULL_RTX;
3742 pool_window_last = 0;
3745 /* Return nonzero if constant would be an ok source for a
3746 mov.w instead of a mov.l. */
3751 return (GET_CODE (src) == CONST_INT
3752 && INTVAL (src) >= -32768
3753 && INTVAL (src) <= 32767);
3756 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
3758 /* Nonzero if the insn is a move instruction which needs to be fixed. */
3760 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
3761 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
3762 need to fix it if the input value is CONST_OK_FOR_I08. */
3765 broken_move (rtx insn)
3767 if (GET_CODE (insn) == INSN)
3769 rtx pat = PATTERN (insn);
3770 if (GET_CODE (pat) == PARALLEL)
3771 pat = XVECEXP (pat, 0, 0);
3772 if (GET_CODE (pat) == SET
3773 /* We can load any 8-bit value if we don't care what the high
3774 order bits end up as. */
3775 && GET_MODE (SET_DEST (pat)) != QImode
3776 && (CONSTANT_P (SET_SRC (pat))
3777 /* Match mova_const. */
3778 || (GET_CODE (SET_SRC (pat)) == UNSPEC
3779 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
3780 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
3782 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
3783 && (fp_zero_operand (SET_SRC (pat))
3784 || fp_one_operand (SET_SRC (pat)))
3785 /* ??? If this is a -m4 or -m4-single compilation, in general
3786 we don't know the current setting of fpscr, so disable fldi.
3787 There is an exception if this was a register-register move
3788 before reload - and hence it was ascertained that we have
3789 single precision setting - and in a post-reload optimization
3790 we changed this to do a constant load. In that case
3791 we don't have an r0 clobber, hence we must use fldi. */
3792 && (! TARGET_SH4 || TARGET_FMOVD
3793 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
3795 && GET_CODE (SET_DEST (pat)) == REG
3796 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
3798 && GET_MODE (SET_DEST (pat)) == SImode
3799 && (satisfies_constraint_I20 (SET_SRC (pat))
3800 || satisfies_constraint_I28 (SET_SRC (pat))))
3801 && ! satisfies_constraint_I08 (SET_SRC (pat)))
3811 return (GET_CODE (insn) == INSN
3812 && GET_CODE (PATTERN (insn)) == SET
3813 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
3814 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
3815 /* Don't match mova_const. */
3816 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
3819 /* Fix up a mova from a switch that went out of range. */
3821 fixup_mova (rtx mova)
3823 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
3826 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
3827 INSN_CODE (mova) = -1;
3832 rtx lab = gen_label_rtx ();
3833 rtx wpat, wpat0, wpat1, wsrc, diff;
3837 worker = NEXT_INSN (worker);
3839 && GET_CODE (worker) != CODE_LABEL
3840 && GET_CODE (worker) != JUMP_INSN);
3841 } while (GET_CODE (worker) == NOTE
3842 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
3843 wpat = PATTERN (worker);
3844 wpat0 = XVECEXP (wpat, 0, 0);
3845 wpat1 = XVECEXP (wpat, 0, 1);
3846 wsrc = SET_SRC (wpat0);
3847 PATTERN (worker) = (gen_casesi_worker_2
3848 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
3849 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
3851 INSN_CODE (worker) = -1;
3852 diff = gen_rtx_MINUS (Pmode, XVECEXP (SET_SRC (PATTERN (mova)), 0, 0),
3853 gen_rtx_LABEL_REF (Pmode, lab));
3854 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, diff), UNSPEC_PIC);
3855 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
3856 INSN_CODE (mova) = -1;
3860 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
3861 *num_mova, and check if the new mova is not nested within the first one.
3862 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
3863 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
3865 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
3867 int n_addr = 0; /* Initialization to shut up spurious warning. */
3868 int f_target, n_target = 0; /* Likewise. */
3872 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
3873 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
3874 if (n_addr > n_target || n_addr + 1022 < n_target)
3876 /* Change the mova into a load.
3877 broken_move will then return true for it. */
3878 fixup_mova (new_mova);
3884 *first_mova = new_mova;
3889 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
3894 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
3895 > n_target - n_addr)
3897 fixup_mova (*first_mova);
3902 fixup_mova (new_mova);
3907 /* Find the last barrier from insn FROM which is close enough to hold the
3908 constant pool. If we can't find one, then create one near the end of
3912 find_barrier (int num_mova, rtx mova, rtx from)
3921 int leading_mova = num_mova;
3922 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
3927 /* For HImode: range is 510, add 4 because pc counts from address of
3928 second instruction after this one, subtract 2 for the jump instruction
3929 that we may need to emit before the table, subtract 2 for the instruction
3930 that fills the jump delay slot (in very rare cases, reorg will take an
3931 instruction from after the constant pool or will leave the delay slot
3932 empty). This gives 510.
3933 For SImode: range is 1020, add 4 because pc counts from address of
3934 second instruction after this one, subtract 2 in case pc is 2 byte
3935 aligned, subtract 2 for the jump instruction that we may need to emit
3936 before the table, subtract 2 for the instruction that fills the jump
3937 delay slot. This gives 1018. */
3939 /* The branch will always be shortened now that the reference address for
3940 forward branches is the successor address, thus we need no longer make
3941 adjustments to the [sh]i_limit for -O0. */
3946 while (from && count_si < si_limit && count_hi < hi_limit)
3948 int inc = get_attr_length (from);
3951 /* If this is a label that existed at the time of the compute_alignments
3952 call, determine the alignment. N.B. When find_barrier recurses for
3953 an out-of-reach mova, we might see labels at the start of previously
3954 inserted constant tables. */
3955 if (GET_CODE (from) == CODE_LABEL
3956 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
3959 new_align = 1 << label_to_alignment (from);
3960 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
3961 new_align = 1 << barrier_align (from);
3966 /* In case we are scanning a constant table because of recursion, check
3967 for explicit alignments. If the table is long, we might be forced
3968 to emit the new table in front of it; the length of the alignment
3969 might be the last straw. */
3970 else if (GET_CODE (from) == INSN
3971 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
3972 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
3973 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
3974 /* When we find the end of a constant table, paste the new constant
3975 at the end. That is better than putting it in front because
3976 this way, we don't need extra alignment for adding a 4-byte-aligned
3977 mov(a) label to a 2/4 or 8/4 byte aligned table. */
3978 else if (GET_CODE (from) == INSN
3979 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
3980 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
3983 if (GET_CODE (from) == BARRIER)
3987 found_barrier = from;
3989 /* If we are at the end of the function, or in front of an alignment
3990 instruction, we need not insert an extra alignment. We prefer
3991 this kind of barrier. */
3992 if (barrier_align (from) > 2)
3993 good_barrier = from;
3995 /* If we are at the end of a hot/cold block, dump the constants
3997 next = NEXT_INSN (from);
4000 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4004 if (broken_move (from))
4007 enum machine_mode mode;
4009 pat = PATTERN (from);
4010 if (GET_CODE (pat) == PARALLEL)
4011 pat = XVECEXP (pat, 0, 0);
4012 src = SET_SRC (pat);
4013 dst = SET_DEST (pat);
4014 mode = GET_MODE (dst);
4016 /* We must explicitly check the mode, because sometimes the
4017 front end will generate code to load unsigned constants into
4018 HImode targets without properly sign extending them. */
4020 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
4023 /* We put the short constants before the long constants, so
4024 we must count the length of short constants in the range
4025 for the long constants. */
4026 /* ??? This isn't optimal, but is easy to do. */
4031 /* We dump DF/DI constants before SF/SI ones, because
4032 the limit is the same, but the alignment requirements
4033 are higher. We may waste up to 4 additional bytes
4034 for alignment, and the DF/DI constant may have
4035 another SF/SI constant placed before it. */
4036 if (TARGET_SHCOMPACT
4038 && (mode == DFmode || mode == DImode))
4043 while (si_align > 2 && found_si + si_align - 2 > count_si)
4045 if (found_si > count_si)
4046 count_si = found_si;
4047 found_si += GET_MODE_SIZE (mode);
4049 si_limit -= GET_MODE_SIZE (mode);
4055 switch (untangle_mova (&num_mova, &mova, from))
4057 case 0: return find_barrier (0, 0, mova);
4062 = good_barrier ? good_barrier : found_barrier;
4066 if (found_si > count_si)
4067 count_si = found_si;
4069 else if (GET_CODE (from) == JUMP_INSN
4070 && (GET_CODE (PATTERN (from)) == ADDR_VEC
4071 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
4073 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4075 && (prev_nonnote_insn (from)
4076 == XEXP (MOVA_LABELREF (mova), 0))))
4078 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4080 /* We have just passed the barrier in front of the
4081 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4082 the ADDR_DIFF_VEC is accessed as data, just like our pool
4083 constants, this is a good opportunity to accommodate what
4084 we have gathered so far.
4085 If we waited any longer, we could end up at a barrier in
4086 front of code, which gives worse cache usage for separated
4087 instruction / data caches. */
4088 good_barrier = found_barrier;
4093 rtx body = PATTERN (from);
4094 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4097 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4098 else if (GET_CODE (from) == JUMP_INSN
4100 && ! TARGET_SMALLCODE)
4106 if (new_align > si_align)
4108 si_limit -= (count_si - 1) & (new_align - si_align);
4109 si_align = new_align;
4111 count_si = (count_si + new_align - 1) & -new_align;
4116 if (new_align > hi_align)
4118 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4119 hi_align = new_align;
4121 count_hi = (count_hi + new_align - 1) & -new_align;
4123 from = NEXT_INSN (from);
4130 /* Try as we might, the leading mova is out of range. Change
4131 it into a load (which will become a pcload) and retry. */
4133 return find_barrier (0, 0, mova);
4137 /* Insert the constant pool table before the mova instruction,
4138 to prevent the mova label reference from going out of range. */
4140 good_barrier = found_barrier = barrier_before_mova;
4146 if (good_barrier && next_real_insn (found_barrier))
4147 found_barrier = good_barrier;
4151 /* We didn't find a barrier in time to dump our stuff,
4152 so we'll make one. */
4153 rtx label = gen_label_rtx ();
4155 /* If we exceeded the range, then we must back up over the last
4156 instruction we looked at. Otherwise, we just need to undo the
4157 NEXT_INSN at the end of the loop. */
4158 if (PREV_INSN (from) != orig
4159 && (count_hi > hi_limit || count_si > si_limit))
4160 from = PREV_INSN (PREV_INSN (from));
4162 from = PREV_INSN (from);
4164 /* Walk back to be just before any jump or label.
4165 Putting it before a label reduces the number of times the branch
4166 around the constant pool table will be hit. Putting it before
4167 a jump makes it more likely that the bra delay slot will be
4169 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
4170 || GET_CODE (from) == CODE_LABEL)
4171 from = PREV_INSN (from);
4173 from = emit_jump_insn_after (gen_jump (label), from);
4174 JUMP_LABEL (from) = label;
4175 LABEL_NUSES (label) = 1;
4176 found_barrier = emit_barrier_after (from);
4177 emit_label_after (label, found_barrier);
4180 return found_barrier;
4183 /* If the instruction INSN is implemented by a special function, and we can
4184 positively find the register that is used to call the sfunc, and this
4185 register is not used anywhere else in this instruction - except as the
4186 destination of a set, return this register; else, return 0. */
4188 sfunc_uses_reg (rtx insn)
4191 rtx pattern, part, reg_part, reg;
4193 if (GET_CODE (insn) != INSN)
4195 pattern = PATTERN (insn);
4196 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4199 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4201 part = XVECEXP (pattern, 0, i);
4202 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4207 reg = XEXP (reg_part, 0);
4208 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4210 part = XVECEXP (pattern, 0, i);
4211 if (part == reg_part || GET_CODE (part) == CLOBBER)
4213 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4214 && GET_CODE (SET_DEST (part)) == REG)
4215 ? SET_SRC (part) : part)))
4221 /* See if the only way in which INSN uses REG is by calling it, or by
4222 setting it while calling it. Set *SET to a SET rtx if the register
4226 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4232 reg2 = sfunc_uses_reg (insn);
4233 if (reg2 && REGNO (reg2) == REGNO (reg))
4235 pattern = single_set (insn);
4237 && GET_CODE (SET_DEST (pattern)) == REG
4238 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4242 if (GET_CODE (insn) != CALL_INSN)
4244 /* We don't use rtx_equal_p because we don't care if the mode is
4246 pattern = single_set (insn);
4248 && GET_CODE (SET_DEST (pattern)) == REG
4249 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4255 par = PATTERN (insn);
4256 if (GET_CODE (par) == PARALLEL)
4257 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4259 part = XVECEXP (par, 0, i);
4260 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4263 return reg_mentioned_p (reg, SET_SRC (pattern));
4269 pattern = PATTERN (insn);
4271 if (GET_CODE (pattern) == PARALLEL)
4275 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4276 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4278 pattern = XVECEXP (pattern, 0, 0);
4281 if (GET_CODE (pattern) == SET)
4283 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4285 /* We don't use rtx_equal_p, because we don't care if the
4286 mode is different. */
4287 if (GET_CODE (SET_DEST (pattern)) != REG
4288 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4294 pattern = SET_SRC (pattern);
4297 if (GET_CODE (pattern) != CALL
4298 || GET_CODE (XEXP (pattern, 0)) != MEM
4299 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4305 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4306 general registers. Bits 0..15 mean that the respective registers
4307 are used as inputs in the instruction. Bits 16..31 mean that the
4308 registers 0..15, respectively, are used as outputs, or are clobbered.
4309 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4311 regs_used (rtx x, int is_dest)
4319 code = GET_CODE (x);
4324 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4325 << (REGNO (x) + is_dest));
4329 rtx y = SUBREG_REG (x);
4331 if (GET_CODE (y) != REG)
4334 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4336 subreg_regno_offset (REGNO (y),
4339 GET_MODE (x)) + is_dest));
4343 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4345 /* If there was a return value, it must have been indicated with USE. */
4360 fmt = GET_RTX_FORMAT (code);
4362 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4367 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4368 used |= regs_used (XVECEXP (x, i, j), is_dest);
4370 else if (fmt[i] == 'e')
4371 used |= regs_used (XEXP (x, i), is_dest);
4376 /* Create an instruction that prevents redirection of a conditional branch
4377 to the destination of the JUMP with address ADDR.
4378 If the branch needs to be implemented as an indirect jump, try to find
4379 a scratch register for it.
4380 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4381 If any preceding insn that doesn't fit into a delay slot is good enough,
4382 pass 1. Pass 2 if a definite blocking insn is needed.
4383 -1 is used internally to avoid deep recursion.
4384 If a blocking instruction is made or recognized, return it. */
4387 gen_block_redirect (rtx jump, int addr, int need_block)
4390 rtx prev = prev_nonnote_insn (jump);
4393 /* First, check if we already have an instruction that satisfies our need. */
4394 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
4396 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4398 if (GET_CODE (PATTERN (prev)) == USE
4399 || GET_CODE (PATTERN (prev)) == CLOBBER
4400 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4402 else if ((need_block &= ~1) < 0)
4404 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4407 if (GET_CODE (PATTERN (jump)) == RETURN)
4411 /* Reorg even does nasty things with return insns that cause branches
4412 to go out of range - see find_end_label and callers. */
4413 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4415 /* We can't use JUMP_LABEL here because it might be undefined
4416 when not optimizing. */
4417 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4418 /* If the branch is out of range, try to find a scratch register for it. */
4420 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4424 /* Don't look for the stack pointer as a scratch register,
4425 it would cause trouble if an interrupt occurred. */
4426 unsigned attempt = 0x7fff, used;
4427 int jump_left = flag_expensive_optimizations + 1;
4429 /* It is likely that the most recent eligible instruction is wanted for
4430 the delay slot. Therefore, find out which registers it uses, and
4431 try to avoid using them. */
4433 for (scan = jump; (scan = PREV_INSN (scan)); )
4437 if (INSN_DELETED_P (scan))
4439 code = GET_CODE (scan);
4440 if (code == CODE_LABEL || code == JUMP_INSN)
4443 && GET_CODE (PATTERN (scan)) != USE
4444 && GET_CODE (PATTERN (scan)) != CLOBBER
4445 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4447 attempt &= ~regs_used (PATTERN (scan), 0);
4451 for (used = dead = 0, scan = JUMP_LABEL (jump);
4452 (scan = NEXT_INSN (scan)); )
4456 if (INSN_DELETED_P (scan))
4458 code = GET_CODE (scan);
4461 used |= regs_used (PATTERN (scan), 0);
4462 if (code == CALL_INSN)
4463 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4464 dead |= (used >> 16) & ~used;
4470 if (code == JUMP_INSN)
4472 if (jump_left-- && simplejump_p (scan))
4473 scan = JUMP_LABEL (scan);
4479 /* Mask out the stack pointer again, in case it was
4480 the only 'free' register we have found. */
4483 /* If the immediate destination is still in range, check for possible
4484 threading with a jump beyond the delay slot insn.
4485 Don't check if we are called recursively; the jump has been or will be
4486 checked in a different invocation then. */
4488 else if (optimize && need_block >= 0)
4490 rtx next = next_active_insn (next_active_insn (dest));
4491 if (next && GET_CODE (next) == JUMP_INSN
4492 && GET_CODE (PATTERN (next)) == SET
4493 && recog_memoized (next) == CODE_FOR_jump_compact)
4495 dest = JUMP_LABEL (next);
4497 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4499 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
4505 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
4507 /* It would be nice if we could convert the jump into an indirect
4508 jump / far branch right now, and thus exposing all constituent
4509 instructions to further optimization. However, reorg uses
4510 simplejump_p to determine if there is an unconditional jump where
4511 it should try to schedule instructions from the target of the
4512 branch; simplejump_p fails for indirect jumps even if they have
4514 rtx insn = emit_insn_before (gen_indirect_jump_scratch
4515 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
4517 /* ??? We would like this to have the scope of the jump, but that
4518 scope will change when a delay slot insn of an inner scope is added.
4519 Hence, after delay slot scheduling, we'll have to expect
4520 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
4523 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
4524 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
4527 else if (need_block)
4528 /* We can't use JUMP_LABEL here because it might be undefined
4529 when not optimizing. */
4530 return emit_insn_before (gen_block_branch_redirect
4531 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
4536 #define CONDJUMP_MIN -252
4537 #define CONDJUMP_MAX 262
4540 /* A label (to be placed) in front of the jump
4541 that jumps to our ultimate destination. */
4543 /* Where we are going to insert it if we cannot move the jump any farther,
4544 or the jump itself if we have picked up an existing jump. */
4546 /* The ultimate destination. */
4548 struct far_branch *prev;
4549 /* If the branch has already been created, its address;
4550 else the address of its first prospective user. */
4554 static void gen_far_branch (struct far_branch *);
4555 enum mdep_reorg_phase_e mdep_reorg_phase;
4557 gen_far_branch (struct far_branch *bp)
4559 rtx insn = bp->insert_place;
4561 rtx label = gen_label_rtx ();
4564 emit_label_after (label, insn);
4567 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
4568 LABEL_NUSES (bp->far_label)++;
4571 jump = emit_jump_insn_after (gen_return (), insn);
4572 /* Emit a barrier so that reorg knows that any following instructions
4573 are not reachable via a fall-through path.
4574 But don't do this when not optimizing, since we wouldn't suppress the
4575 alignment for the barrier then, and could end up with out-of-range
4576 pc-relative loads. */
4578 emit_barrier_after (jump);
4579 emit_label_after (bp->near_label, insn);
4580 JUMP_LABEL (jump) = bp->far_label;
4581 ok = invert_jump (insn, label, 1);
4584 /* If we are branching around a jump (rather than a return), prevent
4585 reorg from using an insn from the jump target as the delay slot insn -
4586 when reorg did this, it pessimized code (we rather hide the delay slot)
4587 and it could cause branches to go out of range. */
4590 (gen_stuff_delay_slot
4591 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
4592 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
4594 /* Prevent reorg from undoing our splits. */
4595 gen_block_redirect (jump, bp->address += 2, 2);
4598 /* Fix up ADDR_DIFF_VECs. */
4600 fixup_addr_diff_vecs (rtx first)
4604 for (insn = first; insn; insn = NEXT_INSN (insn))
4606 rtx vec_lab, pat, prev, prevpat, x, braf_label;
4608 if (GET_CODE (insn) != JUMP_INSN
4609 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
4611 pat = PATTERN (insn);
4612 vec_lab = XEXP (XEXP (pat, 0), 0);
4614 /* Search the matching casesi_jump_2. */
4615 for (prev = vec_lab; ; prev = PREV_INSN (prev))
4617 if (GET_CODE (prev) != JUMP_INSN)
4619 prevpat = PATTERN (prev);
4620 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
4622 x = XVECEXP (prevpat, 0, 1);
4623 if (GET_CODE (x) != USE)
4626 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
4629 /* FIXME: This is a bug in the optimizer, but it seems harmless
4630 to just avoid panicing. */
4634 /* Emit the reference label of the braf where it belongs, right after
4635 the casesi_jump_2 (i.e. braf). */
4636 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
4637 emit_label_after (braf_label, prev);
4639 /* Fix up the ADDR_DIF_VEC to be relative
4640 to the reference address of the braf. */
4641 XEXP (XEXP (pat, 0), 0) = braf_label;
4645 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
4646 a barrier. Return the base 2 logarithm of the desired alignment. */
4648 barrier_align (rtx barrier_or_label)
4650 rtx next = next_real_insn (barrier_or_label), pat, prev;
4651 int slot, credit, jump_to_next = 0;
4656 pat = PATTERN (next);
4658 if (GET_CODE (pat) == ADDR_DIFF_VEC)
4661 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
4662 /* This is a barrier in front of a constant table. */
4665 prev = prev_real_insn (barrier_or_label);
4666 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
4668 pat = PATTERN (prev);
4669 /* If this is a very small table, we want to keep the alignment after
4670 the table to the minimum for proper code alignment. */
4671 return ((TARGET_SMALLCODE
4672 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
4673 <= (unsigned) 1 << (CACHE_LOG - 2)))
4674 ? 1 << TARGET_SHMEDIA : align_jumps_log);
4677 if (TARGET_SMALLCODE)
4680 if (! TARGET_SH2 || ! optimize)
4681 return align_jumps_log;
4683 /* When fixing up pcloads, a constant table might be inserted just before
4684 the basic block that ends with the barrier. Thus, we can't trust the
4685 instruction lengths before that. */
4686 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
4688 /* Check if there is an immediately preceding branch to the insn beyond
4689 the barrier. We must weight the cost of discarding useful information
4690 from the current cache line when executing this branch and there is
4691 an alignment, against that of fetching unneeded insn in front of the
4692 branch target when there is no alignment. */
4694 /* There are two delay_slot cases to consider. One is the simple case
4695 where the preceding branch is to the insn beyond the barrier (simple
4696 delay slot filling), and the other is where the preceding branch has
4697 a delay slot that is a duplicate of the insn after the barrier
4698 (fill_eager_delay_slots) and the branch is to the insn after the insn
4699 after the barrier. */
4701 /* PREV is presumed to be the JUMP_INSN for the barrier under
4702 investigation. Skip to the insn before it. */
4703 prev = prev_real_insn (prev);
4705 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
4706 credit >= 0 && prev && GET_CODE (prev) == INSN;
4707 prev = prev_real_insn (prev))
4710 if (GET_CODE (PATTERN (prev)) == USE
4711 || GET_CODE (PATTERN (prev)) == CLOBBER)
4713 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
4715 prev = XVECEXP (PATTERN (prev), 0, 1);
4716 if (INSN_UID (prev) == INSN_UID (next))
4718 /* Delay slot was filled with insn at jump target. */
4725 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4727 credit -= get_attr_length (prev);
4730 && GET_CODE (prev) == JUMP_INSN
4731 && JUMP_LABEL (prev))
4735 || next_real_insn (JUMP_LABEL (prev)) == next
4736 /* If relax_delay_slots() decides NEXT was redundant
4737 with some previous instruction, it will have
4738 redirected PREV's jump to the following insn. */
4739 || JUMP_LABEL (prev) == next_nonnote_insn (next)
4740 /* There is no upper bound on redundant instructions
4741 that might have been skipped, but we must not put an
4742 alignment where none had been before. */
4743 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
4745 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
4746 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
4747 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
4749 rtx pat = PATTERN (prev);
4750 if (GET_CODE (pat) == PARALLEL)
4751 pat = XVECEXP (pat, 0, 0);
4752 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
4758 return align_jumps_log;
4761 /* If we are inside a phony loop, almost any kind of label can turn up as the
4762 first one in the loop. Aligning a braf label causes incorrect switch
4763 destination addresses; we can detect braf labels because they are
4764 followed by a BARRIER.
4765 Applying loop alignment to small constant or switch tables is a waste
4766 of space, so we suppress this too. */
4768 sh_loop_align (rtx label)
4773 next = next_nonnote_insn (next);
4774 while (next && GET_CODE (next) == CODE_LABEL);
4778 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
4779 || recog_memoized (next) == CODE_FOR_consttable_2)
4782 return align_loops_log;
4785 /* Do a final pass over the function, just before delayed branch
4791 rtx first, insn, mova = NULL_RTX;
4793 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
4794 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
4796 first = get_insns ();
4797 max_labelno_before_reorg = max_label_num ();
4799 /* We must split call insns before introducing `mova's. If we're
4800 optimizing, they'll have already been split. Otherwise, make
4801 sure we don't split them too late. */
4803 split_all_insns_noflow ();
4808 /* If relaxing, generate pseudo-ops to associate function calls with
4809 the symbols they call. It does no harm to not generate these
4810 pseudo-ops. However, when we can generate them, it enables to
4811 linker to potentially relax the jsr to a bsr, and eliminate the
4812 register load and, possibly, the constant pool entry. */
4814 mdep_reorg_phase = SH_INSERT_USES_LABELS;
4817 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
4818 own purposes. This works because none of the remaining passes
4819 need to look at them.
4821 ??? But it may break in the future. We should use a machine
4822 dependent REG_NOTE, or some other approach entirely. */
4823 for (insn = first; insn; insn = NEXT_INSN (insn))
4829 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
4831 remove_note (insn, note);
4835 for (insn = first; insn; insn = NEXT_INSN (insn))
4837 rtx pattern, reg, link, set, scan, dies, label;
4838 int rescan = 0, foundinsn = 0;
4840 if (GET_CODE (insn) == CALL_INSN)
4842 pattern = PATTERN (insn);
4844 if (GET_CODE (pattern) == PARALLEL)
4845 pattern = XVECEXP (pattern, 0, 0);
4846 if (GET_CODE (pattern) == SET)
4847 pattern = SET_SRC (pattern);
4849 if (GET_CODE (pattern) != CALL
4850 || GET_CODE (XEXP (pattern, 0)) != MEM)
4853 reg = XEXP (XEXP (pattern, 0), 0);
4857 reg = sfunc_uses_reg (insn);
4862 if (GET_CODE (reg) != REG)
4865 /* Try scanning backward to find where the register is set. */
4867 for (scan = PREV_INSN (insn);
4868 scan && GET_CODE (scan) != CODE_LABEL;
4869 scan = PREV_INSN (scan))
4871 if (! INSN_P (scan))
4874 if (! reg_mentioned_p (reg, scan))
4877 if (noncall_uses_reg (reg, scan, &set))
4890 /* The register is set at LINK. */
4892 /* We can only optimize the function call if the register is
4893 being set to a symbol. In theory, we could sometimes
4894 optimize calls to a constant location, but the assembler
4895 and linker do not support that at present. */
4896 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
4897 && GET_CODE (SET_SRC (set)) != LABEL_REF)
4900 /* Scan forward from LINK to the place where REG dies, and
4901 make sure that the only insns which use REG are
4902 themselves function calls. */
4904 /* ??? This doesn't work for call targets that were allocated
4905 by reload, since there may not be a REG_DEAD note for the
4909 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
4913 /* Don't try to trace forward past a CODE_LABEL if we haven't
4914 seen INSN yet. Ordinarily, we will only find the setting insn
4915 if it is in the same basic block. However,
4916 cross-jumping can insert code labels in between the load and
4917 the call, and can result in situations where a single call
4918 insn may have two targets depending on where we came from. */
4920 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
4923 if (! INSN_P (scan))
4926 /* Don't try to trace forward past a JUMP. To optimize
4927 safely, we would have to check that all the
4928 instructions at the jump destination did not use REG. */
4930 if (GET_CODE (scan) == JUMP_INSN)
4933 if (! reg_mentioned_p (reg, scan))
4936 if (noncall_uses_reg (reg, scan, &scanset))
4943 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
4945 /* There is a function call to this register other
4946 than the one we are checking. If we optimize
4947 this call, we need to rescan again below. */
4951 /* ??? We shouldn't have to worry about SCANSET here.
4952 We should just be able to check for a REG_DEAD note
4953 on a function call. However, the REG_DEAD notes are
4954 apparently not dependable around libcalls; c-torture
4955 execute/920501-2 is a test case. If SCANSET is set,
4956 then this insn sets the register, so it must have
4957 died earlier. Unfortunately, this will only handle
4958 the cases in which the register is, in fact, set in a
4961 /* ??? We shouldn't have to use FOUNDINSN here.
4962 This dates back to when we used LOG_LINKS to find
4963 the most recent insn which sets the register. */
4967 || find_reg_note (scan, REG_DEAD, reg)))
4976 /* Either there was a branch, or some insn used REG
4977 other than as a function call address. */
4981 /* Create a code label, and put it in a REG_LABEL_OPERAND note
4982 on the insn which sets the register, and on each call insn
4983 which uses the register. In final_prescan_insn we look for
4984 the REG_LABEL_OPERAND notes, and output the appropriate label
4987 label = gen_label_rtx ();
4988 add_reg_note (link, REG_LABEL_OPERAND, label);
4989 add_reg_note (insn, REG_LABEL_OPERAND, label);
4997 scan = NEXT_INSN (scan);
4999 && ((GET_CODE (scan) == CALL_INSN
5000 && reg_mentioned_p (reg, scan))
5001 || ((reg2 = sfunc_uses_reg (scan))
5002 && REGNO (reg2) == REGNO (reg))))
5003 add_reg_note (scan, REG_LABEL_OPERAND, label);
5005 while (scan != dies);
5011 fixup_addr_diff_vecs (first);
5015 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5016 shorten_branches (first);
5019 /* Scan the function looking for move instructions which have to be
5020 changed to pc-relative loads and insert the literal tables. */
5021 label_ref_list_pool = create_alloc_pool ("label references list",
5022 sizeof (struct label_ref_list_d),
5024 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5025 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
5029 /* ??? basic block reordering can move a switch table dispatch
5030 below the switch table. Check if that has happened.
5031 We only have the addresses available when optimizing; but then,
5032 this check shouldn't be needed when not optimizing. */
5033 if (!untangle_mova (&num_mova, &mova, insn))
5039 else if (GET_CODE (insn) == JUMP_INSN
5040 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5042 /* ??? loop invariant motion can also move a mova out of a
5043 loop. Since loop does this code motion anyway, maybe we
5044 should wrap UNSPEC_MOVA into a CONST, so that reload can
5047 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5048 || (prev_nonnote_insn (insn)
5049 == XEXP (MOVA_LABELREF (mova), 0))))
5056 /* Some code might have been inserted between the mova and
5057 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5058 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5059 total += get_attr_length (scan);
5061 /* range of mova is 1020, add 4 because pc counts from address of
5062 second instruction after this one, subtract 2 in case pc is 2
5063 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5064 cancels out with alignment effects of the mova itself. */
5067 /* Change the mova into a load, and restart scanning
5068 there. broken_move will then return true for mova. */
5073 if (broken_move (insn)
5074 || (GET_CODE (insn) == INSN
5075 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5078 /* Scan ahead looking for a barrier to stick the constant table
5080 rtx barrier = find_barrier (num_mova, mova, insn);
5081 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5082 int need_aligned_label = 0;
5084 if (num_mova && ! mova_p (mova))
5086 /* find_barrier had to change the first mova into a
5087 pcload; thus, we have to start with this new pcload. */
5091 /* Now find all the moves between the points and modify them. */
5092 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5094 if (GET_CODE (scan) == CODE_LABEL)
5096 if (GET_CODE (scan) == INSN
5097 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5098 need_aligned_label = 1;
5099 if (broken_move (scan))
5101 rtx *patp = &PATTERN (scan), pat = *patp;
5105 enum machine_mode mode;
5107 if (GET_CODE (pat) == PARALLEL)
5108 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5109 src = SET_SRC (pat);
5110 dst = SET_DEST (pat);
5111 mode = GET_MODE (dst);
5113 if (mode == SImode && hi_const (src)
5114 && REGNO (dst) != FPUL_REG)
5119 while (GET_CODE (dst) == SUBREG)
5121 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5122 GET_MODE (SUBREG_REG (dst)),
5125 dst = SUBREG_REG (dst);
5127 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5129 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
5131 /* This must be an insn that clobbers r0. */
5132 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5133 XVECLEN (PATTERN (scan), 0)
5135 rtx clobber = *clobberp;
5137 gcc_assert (GET_CODE (clobber) == CLOBBER
5138 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5141 && reg_set_between_p (r0_rtx, last_float_move, scan))
5145 && GET_MODE_SIZE (mode) != 4
5146 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5148 lab = add_constant (src, mode, last_float);
5150 emit_insn_before (gen_mova (lab), scan);
5153 /* There will be a REG_UNUSED note for r0 on
5154 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5155 lest reorg:mark_target_live_regs will not
5156 consider r0 to be used, and we end up with delay
5157 slot insn in front of SCAN that clobbers r0. */
5159 = find_regno_note (last_float_move, REG_UNUSED, 0);
5161 /* If we are not optimizing, then there may not be
5164 PUT_MODE (note, REG_INC);
5166 *last_float_addr = r0_inc_rtx;
5168 last_float_move = scan;
5170 newsrc = gen_const_mem (mode,
5171 (((TARGET_SH4 && ! TARGET_FMOVD)
5172 || REGNO (dst) == FPUL_REG)
5175 last_float_addr = &XEXP (newsrc, 0);
5177 /* Remove the clobber of r0. */
5178 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5179 gen_rtx_SCRATCH (Pmode));
5181 /* This is a mova needing a label. Create it. */
5182 else if (GET_CODE (src) == UNSPEC
5183 && XINT (src, 1) == UNSPEC_MOVA
5184 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5186 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5187 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5188 newsrc = gen_rtx_UNSPEC (SImode,
5189 gen_rtvec (1, newsrc),
5194 lab = add_constant (src, mode, 0);
5195 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5196 newsrc = gen_const_mem (mode, newsrc);
5198 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5199 INSN_CODE (scan) = -1;
5202 dump_table (need_aligned_label ? insn : 0, barrier);
5206 free_alloc_pool (label_ref_list_pool);
5207 for (insn = first; insn; insn = NEXT_INSN (insn))
5208 PUT_MODE (insn, VOIDmode);
5210 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5211 INSN_ADDRESSES_FREE ();
5212 split_branches (first);
5214 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5215 also has an effect on the register that holds the address of the sfunc.
5216 Insert an extra dummy insn in front of each sfunc that pretends to
5217 use this register. */
5218 if (flag_delayed_branch)
5220 for (insn = first; insn; insn = NEXT_INSN (insn))
5222 rtx reg = sfunc_uses_reg (insn);
5226 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5230 /* fpscr is not actually a user variable, but we pretend it is for the
5231 sake of the previous optimization passes, since we want it handled like
5232 one. However, we don't have any debugging information for it, so turn
5233 it into a non-user variable now. */
5235 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5237 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5241 get_dest_uid (rtx label, int max_uid)
5243 rtx dest = next_real_insn (label);
5246 /* This can happen for an undefined label. */
5248 dest_uid = INSN_UID (dest);
5249 /* If this is a newly created branch redirection blocking instruction,
5250 we cannot index the branch_uid or insn_addresses arrays with its
5251 uid. But then, we won't need to, because the actual destination is
5252 the following branch. */
5253 while (dest_uid >= max_uid)
5255 dest = NEXT_INSN (dest);
5256 dest_uid = INSN_UID (dest);
5258 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
5263 /* Split condbranches that are out of range. Also add clobbers for
5264 scratch registers that are needed in far jumps.
5265 We do this before delay slot scheduling, so that it can take our
5266 newly created instructions into account. It also allows us to
5267 find branches with common targets more easily. */
5270 split_branches (rtx first)
5273 struct far_branch **uid_branch, *far_branch_list = 0;
5274 int max_uid = get_max_uid ();
5277 /* Find out which branches are out of range. */
5278 shorten_branches (first);
5280 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5281 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5283 for (insn = first; insn; insn = NEXT_INSN (insn))
5284 if (! INSN_P (insn))
5286 else if (INSN_DELETED_P (insn))
5288 /* Shorten_branches would split this instruction again,
5289 so transform it into a note. */
5290 SET_INSN_DELETED (insn);
5292 else if (GET_CODE (insn) == JUMP_INSN
5293 /* Don't mess with ADDR_DIFF_VEC */
5294 && (GET_CODE (PATTERN (insn)) == SET
5295 || GET_CODE (PATTERN (insn)) == RETURN))
5297 enum attr_type type = get_attr_type (insn);
5298 if (type == TYPE_CBRANCH)
5302 if (get_attr_length (insn) > 4)
5304 rtx src = SET_SRC (PATTERN (insn));
5305 rtx olabel = XEXP (XEXP (src, 1), 0);
5306 int addr = INSN_ADDRESSES (INSN_UID (insn));
5308 int dest_uid = get_dest_uid (olabel, max_uid);
5309 struct far_branch *bp = uid_branch[dest_uid];
5311 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5312 the label if the LABEL_NUSES count drops to zero. There is
5313 always a jump_optimize pass that sets these values, but it
5314 proceeds to delete unreferenced code, and then if not
5315 optimizing, to un-delete the deleted instructions, thus
5316 leaving labels with too low uses counts. */
5319 JUMP_LABEL (insn) = olabel;
5320 LABEL_NUSES (olabel)++;
5324 bp = (struct far_branch *) alloca (sizeof *bp);
5325 uid_branch[dest_uid] = bp;
5326 bp->prev = far_branch_list;
5327 far_branch_list = bp;
5329 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5330 LABEL_NUSES (bp->far_label)++;
5334 label = bp->near_label;
5335 if (! label && bp->address - addr >= CONDJUMP_MIN)
5337 rtx block = bp->insert_place;
5339 if (GET_CODE (PATTERN (block)) == RETURN)
5340 block = PREV_INSN (block);
5342 block = gen_block_redirect (block,
5344 label = emit_label_after (gen_label_rtx (),
5346 bp->near_label = label;
5348 else if (label && ! NEXT_INSN (label))
5350 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5351 bp->insert_place = insn;
5353 gen_far_branch (bp);
5357 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5359 bp->near_label = label = gen_label_rtx ();
5360 bp->insert_place = insn;
5363 ok = redirect_jump (insn, label, 0);
5368 /* get_attr_length (insn) == 2 */
5369 /* Check if we have a pattern where reorg wants to redirect
5370 the branch to a label from an unconditional branch that
5372 /* We can't use JUMP_LABEL here because it might be undefined
5373 when not optimizing. */
5374 /* A syntax error might cause beyond to be NULL_RTX. */
5376 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5380 && (GET_CODE (beyond) == JUMP_INSN
5381 || ((beyond = next_active_insn (beyond))
5382 && GET_CODE (beyond) == JUMP_INSN))
5383 && GET_CODE (PATTERN (beyond)) == SET
5384 && recog_memoized (beyond) == CODE_FOR_jump_compact
5386 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5387 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5389 gen_block_redirect (beyond,
5390 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5393 next = next_active_insn (insn);
5395 if ((GET_CODE (next) == JUMP_INSN
5396 || ((next = next_active_insn (next))
5397 && GET_CODE (next) == JUMP_INSN))
5398 && GET_CODE (PATTERN (next)) == SET
5399 && recog_memoized (next) == CODE_FOR_jump_compact
5401 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5402 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5404 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5406 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5408 int addr = INSN_ADDRESSES (INSN_UID (insn));
5411 struct far_branch *bp;
5413 if (type == TYPE_JUMP)
5415 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5416 dest_uid = get_dest_uid (far_label, max_uid);
5419 /* Parse errors can lead to labels outside
5421 if (! NEXT_INSN (far_label))
5426 JUMP_LABEL (insn) = far_label;
5427 LABEL_NUSES (far_label)++;
5429 redirect_jump (insn, NULL_RTX, 1);
5433 bp = uid_branch[dest_uid];
5436 bp = (struct far_branch *) alloca (sizeof *bp);
5437 uid_branch[dest_uid] = bp;
5438 bp->prev = far_branch_list;
5439 far_branch_list = bp;
5441 bp->far_label = far_label;
5443 LABEL_NUSES (far_label)++;
5445 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5446 if (addr - bp->address <= CONDJUMP_MAX)
5447 emit_label_after (bp->near_label, PREV_INSN (insn));
5450 gen_far_branch (bp);
5456 bp->insert_place = insn;
5458 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5460 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5463 /* Generate all pending far branches,
5464 and free our references to the far labels. */
5465 while (far_branch_list)
5467 if (far_branch_list->near_label
5468 && ! NEXT_INSN (far_branch_list->near_label))
5469 gen_far_branch (far_branch_list);
5471 && far_branch_list->far_label
5472 && ! --LABEL_NUSES (far_branch_list->far_label))
5473 delete_insn (far_branch_list->far_label);
5474 far_branch_list = far_branch_list->prev;
5477 /* Instruction length information is no longer valid due to the new
5478 instructions that have been generated. */
5479 init_insn_lengths ();
5482 /* Dump out instruction addresses, which is useful for debugging the
5483 constant pool table stuff.
5485 If relaxing, output the label and pseudo-ops used to link together
5486 calls and the instruction which set the registers. */
5488 /* ??? The addresses printed by this routine for insns are nonsense for
5489 insns which are inside of a sequence where none of the inner insns have
5490 variable length. This is because the second pass of shorten_branches
5491 does not bother to update them. */
5494 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
5495 int noperands ATTRIBUTE_UNUSED)
5497 if (TARGET_DUMPISIZE)
5498 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
5504 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
5509 pattern = PATTERN (insn);
5510 if (GET_CODE (pattern) == PARALLEL)
5511 pattern = XVECEXP (pattern, 0, 0);
5512 switch (GET_CODE (pattern))
5515 if (GET_CODE (SET_SRC (pattern)) != CALL
5516 && get_attr_type (insn) != TYPE_SFUNC)
5518 targetm.asm_out.internal_label
5519 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
5522 /* else FALLTHROUGH */
5524 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
5525 CODE_LABEL_NUMBER (XEXP (note, 0)));
5535 /* Dump out any constants accumulated in the final pass. These will
5539 output_jump_label_table (void)
5545 fprintf (asm_out_file, "\t.align 2\n");
5546 for (i = 0; i < pool_size; i++)
5548 pool_node *p = &pool_vector[i];
5550 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5551 CODE_LABEL_NUMBER (p->label));
5552 output_asm_insn (".long %O0", &p->value);
5560 /* A full frame looks like:
5564 [ if current_function_anonymous_args
5577 local-0 <- fp points here. */
5579 /* Number of bytes pushed for anonymous args, used to pass information
5580 between expand_prologue and expand_epilogue. */
5582 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
5583 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
5584 for an epilogue and a negative value means that it's for a sibcall
5585 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
5586 all the registers that are about to be restored, and hence dead. */
5589 output_stack_adjust (int size, rtx reg, int epilogue_p,
5590 HARD_REG_SET *live_regs_mask)
5592 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
5595 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
5597 /* This test is bogus, as output_stack_adjust is used to re-align the
5600 gcc_assert (!(size % align));
5603 if (CONST_OK_FOR_ADD (size))
5604 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
5605 /* Try to do it with two partial adjustments; however, we must make
5606 sure that the stack is properly aligned at all times, in case
5607 an interrupt occurs between the two partial adjustments. */
5608 else if (CONST_OK_FOR_ADD (size / 2 & -align)
5609 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
5611 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
5612 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
5618 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
5621 /* If TEMP is invalid, we could temporarily save a general
5622 register to MACL. However, there is currently no need
5623 to handle this case, so just die when we see it. */
5625 || current_function_interrupt
5626 || ! call_really_used_regs[temp] || fixed_regs[temp])
5628 if (temp < 0 && ! current_function_interrupt
5629 && (TARGET_SHMEDIA || epilogue_p >= 0))
5632 COPY_HARD_REG_SET (temps, call_used_reg_set);
5633 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
5637 if (crtl->return_rtx)
5639 enum machine_mode mode;
5640 mode = GET_MODE (crtl->return_rtx);
5641 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
5642 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
5644 for (i = 0; i < nreg; i++)
5645 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
5646 if (crtl->calls_eh_return)
5648 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
5649 for (i = 0; i <= 3; i++)
5650 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
5653 if (TARGET_SHMEDIA && epilogue_p < 0)
5654 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
5655 CLEAR_HARD_REG_BIT (temps, i);
5656 if (epilogue_p <= 0)
5658 for (i = FIRST_PARM_REG;
5659 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
5660 CLEAR_HARD_REG_BIT (temps, i);
5661 if (cfun->static_chain_decl != NULL)
5662 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
5664 temp = scavenge_reg (&temps);
5666 if (temp < 0 && live_regs_mask)
5670 COPY_HARD_REG_SET (temps, *live_regs_mask);
5671 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
5672 temp = scavenge_reg (&temps);
5676 rtx adj_reg, tmp_reg, mem;
5678 /* If we reached here, the most likely case is the (sibcall)
5679 epilogue for non SHmedia. Put a special push/pop sequence
5680 for such case as the last resort. This looks lengthy but
5681 would not be problem because it seems to be very
5684 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
5687 /* ??? There is still the slight possibility that r4 or
5688 r5 have been reserved as fixed registers or assigned
5689 as global registers, and they change during an
5690 interrupt. There are possible ways to handle this:
5692 - If we are adjusting the frame pointer (r14), we can do
5693 with a single temp register and an ordinary push / pop
5695 - Grab any call-used or call-saved registers (i.e. not
5696 fixed or globals) for the temps we need. We might
5697 also grab r14 if we are adjusting the stack pointer.
5698 If we can't find enough available registers, issue
5699 a diagnostic and die - the user must have reserved
5700 way too many registers.
5701 But since all this is rather unlikely to happen and
5702 would require extra testing, we just die if r4 / r5
5703 are not available. */
5704 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
5705 && !global_regs[4] && !global_regs[5]);
5707 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
5708 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
5709 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
5710 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
5711 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
5712 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5713 emit_move_insn (mem, tmp_reg);
5714 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
5715 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5716 emit_move_insn (mem, tmp_reg);
5717 emit_move_insn (reg, adj_reg);
5718 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5719 emit_move_insn (adj_reg, mem);
5720 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5721 emit_move_insn (tmp_reg, mem);
5722 /* Tell flow the insns that pop r4/r5 aren't dead. */
5727 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
5729 /* If SIZE is negative, subtract the positive value.
5730 This sometimes allows a constant pool entry to be shared
5731 between prologue and epilogue code. */
5734 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
5735 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
5739 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
5740 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
5744 = (gen_rtx_EXPR_LIST
5745 (REG_FRAME_RELATED_EXPR,
5746 gen_rtx_SET (VOIDmode, reg,
5747 gen_rtx_PLUS (SImode, reg, GEN_INT (size))),
5757 RTX_FRAME_RELATED_P (x) = 1;
5761 /* Output RTL to push register RN onto the stack. */
5768 x = gen_push_fpul ();
5769 else if (rn == FPSCR_REG)
5770 x = gen_push_fpscr ();
5771 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5772 && FP_OR_XD_REGISTER_P (rn))
5774 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5776 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
5778 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5779 x = gen_push_e (gen_rtx_REG (SFmode, rn));
5781 x = gen_push (gen_rtx_REG (SImode, rn));
5785 = gen_rtx_EXPR_LIST (REG_INC,
5786 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
5790 /* Output RTL to pop register RN from the stack. */
5797 x = gen_pop_fpul ();
5798 else if (rn == FPSCR_REG)
5799 x = gen_pop_fpscr ();
5800 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5801 && FP_OR_XD_REGISTER_P (rn))
5803 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5805 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
5807 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5808 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
5810 x = gen_pop (gen_rtx_REG (SImode, rn));
5814 = gen_rtx_EXPR_LIST (REG_INC,
5815 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
5818 /* Generate code to push the regs specified in the mask. */
5821 push_regs (HARD_REG_SET *mask, int interrupt_handler)
5823 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
5826 /* Push PR last; this gives better latencies after the prologue, and
5827 candidates for the return delay slot when there are no general
5828 registers pushed. */
5829 for (; i < FIRST_PSEUDO_REGISTER; i++)
5831 /* If this is an interrupt handler, and the SZ bit varies,
5832 and we have to push any floating point register, we need
5833 to switch to the correct precision first. */
5834 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
5835 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
5837 HARD_REG_SET unsaved;
5840 COMPL_HARD_REG_SET (unsaved, *mask);
5841 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
5845 && (i != FPSCR_REG || ! skip_fpscr)
5846 && TEST_HARD_REG_BIT (*mask, i))
5848 /* If the ISR has RESBANK attribute assigned, don't push any of
5849 the following registers - R0-R14, MACH, MACL and GBR. */
5850 if (! (sh_cfun_resbank_handler_p ()
5851 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
5859 /* Push banked registers last to improve delay slot opportunities. */
5860 if (interrupt_handler)
5861 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
5862 if (TEST_HARD_REG_BIT (*mask, i))
5865 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
5866 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
5870 /* Calculate how much extra space is needed to save all callee-saved
5872 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5875 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
5878 int stack_space = 0;
5879 int interrupt_handler = sh_cfun_interrupt_handler_p ();
5881 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
5882 if ((! call_really_used_regs[reg] || interrupt_handler)
5883 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
5884 /* Leave space to save this target register on the stack,
5885 in case target register allocation wants to use it. */
5886 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5890 /* Decide whether we should reserve space for callee-save target registers,
5891 in case target register allocation wants to use them. REGS_SAVED is
5892 the space, in bytes, that is already required for register saves.
5893 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5896 shmedia_reserve_space_for_target_registers_p (int regs_saved,
5897 HARD_REG_SET *live_regs_mask)
5901 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
5904 /* Decide how much space to reserve for callee-save target registers
5905 in case target register allocation wants to use them.
5906 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5909 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
5911 if (shmedia_space_reserved_for_target_registers)
5912 return shmedia_target_regs_stack_space (live_regs_mask);
5917 /* Work out the registers which need to be saved, both as a mask and a
5918 count of saved words. Return the count.
5920 If doing a pragma interrupt function, then push all regs used by the
5921 function, and if we call another function (we can tell by looking at PR),
5922 make sure that all the regs it clobbers are safe too. */
5925 calc_live_regs (HARD_REG_SET *live_regs_mask)
5930 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
5931 bool nosave_low_regs;
5932 int pr_live, has_call;
5934 attrs = DECL_ATTRIBUTES (current_function_decl);
5935 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
5936 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
5937 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
5938 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
5940 CLEAR_HARD_REG_SET (*live_regs_mask);
5941 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
5942 && df_regs_ever_live_p (FPSCR_REG))
5943 target_flags &= ~MASK_FPU_SINGLE;
5944 /* If we can save a lot of saves by switching to double mode, do that. */
5945 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
5946 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
5947 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
5948 && (! call_really_used_regs[reg]
5949 || interrupt_handler)
5952 target_flags &= ~MASK_FPU_SINGLE;
5955 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
5956 knows how to use it. That means the pseudo originally allocated for
5957 the initial value can become the PR_MEDIA_REG hard register, as seen for
5958 execute/20010122-1.c:test9. */
5960 /* ??? this function is called from initial_elimination_offset, hence we
5961 can't use the result of sh_media_register_for_return here. */
5962 pr_live = sh_pr_n_sets ();
5965 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
5966 pr_live = (pr_initial
5967 ? (GET_CODE (pr_initial) != REG
5968 || REGNO (pr_initial) != (PR_REG))
5969 : df_regs_ever_live_p (PR_REG));
5970 /* For Shcompact, if not optimizing, we end up with a memory reference
5971 using the return address pointer for __builtin_return_address even
5972 though there is no actual need to put the PR register on the stack. */
5973 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
5975 /* Force PR to be live if the prologue has to call the SHmedia
5976 argument decoder or register saver. */
5977 if (TARGET_SHCOMPACT
5978 && ((crtl->args.info.call_cookie
5979 & ~ CALL_COOKIE_RET_TRAMP (1))
5980 || crtl->saves_all_registers))
5982 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
5983 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
5985 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
5988 ? (/* Need to save all the regs ever live. */
5989 (df_regs_ever_live_p (reg)
5990 || (call_really_used_regs[reg]
5991 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
5992 || reg == PIC_OFFSET_TABLE_REGNUM)
5994 || (TARGET_SHMEDIA && has_call
5995 && REGISTER_NATURAL_MODE (reg) == SImode
5996 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
5997 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
5998 && reg != RETURN_ADDRESS_POINTER_REGNUM
5999 && reg != T_REG && reg != GBR_REG
6000 /* Push fpscr only on targets which have FPU */
6001 && (reg != FPSCR_REG || TARGET_FPU_ANY))
6002 : (/* Only push those regs which are used and need to be saved. */
6005 && crtl->args.info.call_cookie
6006 && reg == PIC_OFFSET_TABLE_REGNUM)
6007 || (df_regs_ever_live_p (reg)
6008 && (!call_really_used_regs[reg]
6009 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
6010 || (crtl->calls_eh_return
6011 && (reg == EH_RETURN_DATA_REGNO (0)
6012 || reg == EH_RETURN_DATA_REGNO (1)
6013 || reg == EH_RETURN_DATA_REGNO (2)
6014 || reg == EH_RETURN_DATA_REGNO (3)))
6015 || ((reg == MACL_REG || reg == MACH_REG)
6016 && df_regs_ever_live_p (reg)
6017 && sh_cfun_attr_renesas_p ())
6020 SET_HARD_REG_BIT (*live_regs_mask, reg);
6021 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6023 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
6024 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
6026 if (FP_REGISTER_P (reg))
6028 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
6030 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
6031 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
6034 else if (XD_REGISTER_P (reg))
6036 /* Must switch to double mode to access these registers. */
6037 target_flags &= ~MASK_FPU_SINGLE;
6041 if (nosave_low_regs && reg == R8_REG)
6044 /* If we have a target register optimization pass after prologue / epilogue
6045 threading, we need to assume all target registers will be live even if
6047 if (flag_branch_target_load_optimize2
6048 && TARGET_SAVE_ALL_TARGET_REGS
6049 && shmedia_space_reserved_for_target_registers)
6050 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6051 if ((! call_really_used_regs[reg] || interrupt_handler)
6052 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6054 SET_HARD_REG_BIT (*live_regs_mask, reg);
6055 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6057 /* If this is an interrupt handler, we don't have any call-clobbered
6058 registers we can conveniently use for target register save/restore.
6059 Make sure we save at least one general purpose register when we need
6060 to save target registers. */
6061 if (interrupt_handler
6062 && hard_reg_set_intersect_p (*live_regs_mask,
6063 reg_class_contents[TARGET_REGS])
6064 && ! hard_reg_set_intersect_p (*live_regs_mask,
6065 reg_class_contents[GENERAL_REGS]))
6067 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6068 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6074 /* Code to generate prologue and epilogue sequences */
6076 /* PUSHED is the number of bytes that are being pushed on the
6077 stack for register saves. Return the frame size, padded
6078 appropriately so that the stack stays properly aligned. */
6079 static HOST_WIDE_INT
6080 rounded_frame_size (int pushed)
6082 HOST_WIDE_INT size = get_frame_size ();
6083 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6085 return ((size + pushed + align - 1) & -align) - pushed;
6088 /* Choose a call-clobbered target-branch register that remains
6089 unchanged along the whole function. We set it up as the return
6090 value in the prologue. */
6092 sh_media_register_for_return (void)
6097 if (! current_function_is_leaf)
6099 if (lookup_attribute ("interrupt_handler",
6100 DECL_ATTRIBUTES (current_function_decl)))
6102 if (sh_cfun_interrupt_handler_p ())
6105 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6107 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6108 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6114 /* The maximum registers we need to save are:
6115 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6116 - 32 floating point registers (for each pair, we save none,
6117 one single precision value, or a double precision value).
6118 - 8 target registers
6119 - add 1 entry for a delimiter. */
6120 #define MAX_SAVED_REGS (62+32+8)
6122 typedef struct save_entry_s
6131 /* There will be a delimiter entry with VOIDmode both at the start and the
6132 end of a filled in schedule. The end delimiter has the offset of the
6133 save with the smallest (i.e. most negative) offset. */
6134 typedef struct save_schedule_s
6136 save_entry entries[MAX_SAVED_REGS + 2];
6137 int temps[MAX_TEMPS+1];
6140 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6141 use reverse order. Returns the last entry written to (not counting
6142 the delimiter). OFFSET_BASE is a number to be added to all offset
6146 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6150 save_entry *entry = schedule->entries;
6154 if (! current_function_interrupt)
6155 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6156 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6157 && ! FUNCTION_ARG_REGNO_P (i)
6158 && i != FIRST_RET_REG
6159 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6160 && ! (crtl->calls_eh_return
6161 && (i == EH_RETURN_STACKADJ_REGNO
6162 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6163 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6164 schedule->temps[tmpx++] = i;
6166 entry->mode = VOIDmode;
6167 entry->offset = offset_base;
6169 /* We loop twice: first, we save 8-byte aligned registers in the
6170 higher addresses, that are known to be aligned. Then, we
6171 proceed to saving 32-bit registers that don't need 8-byte
6173 If this is an interrupt function, all registers that need saving
6174 need to be saved in full. moreover, we need to postpone saving
6175 target registers till we have saved some general purpose registers
6176 we can then use as scratch registers. */
6177 offset = offset_base;
6178 for (align = 1; align >= 0; align--)
6180 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6181 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6183 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6186 if (current_function_interrupt)
6188 if (TARGET_REGISTER_P (i))
6190 if (GENERAL_REGISTER_P (i))
6193 if (mode == SFmode && (i % 2) == 1
6194 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6195 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6202 /* If we're doing the aligned pass and this is not aligned,
6203 or we're doing the unaligned pass and this is aligned,
6205 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6209 if (current_function_interrupt
6210 && GENERAL_REGISTER_P (i)
6211 && tmpx < MAX_TEMPS)
6212 schedule->temps[tmpx++] = i;
6214 offset -= GET_MODE_SIZE (mode);
6217 entry->offset = offset;
6220 if (align && current_function_interrupt)
6221 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6222 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6224 offset -= GET_MODE_SIZE (DImode);
6226 entry->mode = DImode;
6227 entry->offset = offset;
6232 entry->mode = VOIDmode;
6233 entry->offset = offset;
6234 schedule->temps[tmpx] = -1;
6239 sh_expand_prologue (void)
6241 HARD_REG_SET live_regs_mask;
6244 int save_flags = target_flags;
6247 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6249 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6251 /* We have pretend args if we had an object sent partially in registers
6252 and partially on the stack, e.g. a large structure. */
6253 pretend_args = crtl->args.pretend_args_size;
6254 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6255 && (NPARM_REGS(SImode)
6256 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
6258 output_stack_adjust (-pretend_args
6259 - crtl->args.info.stack_regs * 8,
6260 stack_pointer_rtx, 0, NULL);
6262 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
6263 /* We're going to use the PIC register to load the address of the
6264 incoming-argument decoder and/or of the return trampoline from
6265 the GOT, so make sure the PIC register is preserved and
6267 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6269 if (TARGET_SHCOMPACT
6270 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6274 /* First, make all registers with incoming arguments that will
6275 be pushed onto the stack live, so that register renaming
6276 doesn't overwrite them. */
6277 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6278 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
6279 >= NPARM_REGS (SImode) - reg)
6280 for (; reg < NPARM_REGS (SImode); reg++)
6281 emit_insn (gen_shcompact_preserve_incoming_args
6282 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6283 else if (CALL_COOKIE_INT_REG_GET
6284 (crtl->args.info.call_cookie, reg) == 1)
6285 emit_insn (gen_shcompact_preserve_incoming_args
6286 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6288 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6290 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6291 GEN_INT (crtl->args.info.call_cookie));
6292 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6293 gen_rtx_REG (SImode, R0_REG));
6295 else if (TARGET_SHMEDIA)
6297 int tr = sh_media_register_for_return ();
6300 emit_move_insn (gen_rtx_REG (DImode, tr),
6301 gen_rtx_REG (DImode, PR_MEDIA_REG));
6304 /* Emit the code for SETUP_VARARGS. */
6307 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6309 /* Push arg regs as if they'd been provided by caller in stack. */
6310 for (i = 0; i < NPARM_REGS(SImode); i++)
6312 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6315 if (i >= (NPARM_REGS(SImode)
6316 - crtl->args.info.arg_count[(int) SH_ARG_INT]
6324 /* If we're supposed to switch stacks at function entry, do so now. */
6327 /* The argument specifies a variable holding the address of the
6328 stack the interrupt function should switch to/from at entry/exit. */
6330 = ggc_strdup (TREE_STRING_POINTER (TREE_VALUE (sp_switch_attr)));
6331 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6333 emit_insn (gen_sp_switch_1 (sp_switch));
6336 d = calc_live_regs (&live_regs_mask);
6337 /* ??? Maybe we could save some switching if we can move a mode switch
6338 that already happens to be at the function start into the prologue. */
6339 if (target_flags != save_flags && ! current_function_interrupt)
6340 emit_insn (gen_toggle_sz ());
6344 int offset_base, offset;
6346 int offset_in_r0 = -1;
6348 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6349 int total_size, save_size;
6350 save_schedule schedule;
6354 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6355 && ! current_function_interrupt)
6356 r0 = gen_rtx_REG (Pmode, R0_REG);
6358 /* D is the actual number of bytes that we need for saving registers,
6359 however, in initial_elimination_offset we have committed to using
6360 an additional TREGS_SPACE amount of bytes - in order to keep both
6361 addresses to arguments supplied by the caller and local variables
6362 valid, we must keep this gap. Place it between the incoming
6363 arguments and the actually saved registers in a bid to optimize
6364 locality of reference. */
6365 total_size = d + tregs_space;
6366 total_size += rounded_frame_size (total_size);
6367 save_size = total_size - rounded_frame_size (d);
6368 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6369 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6370 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6372 /* If adjusting the stack in a single step costs nothing extra, do so.
6373 I.e. either if a single addi is enough, or we need a movi anyway,
6374 and we don't exceed the maximum offset range (the test for the
6375 latter is conservative for simplicity). */
6377 && (CONST_OK_FOR_I10 (-total_size)
6378 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6379 && total_size <= 2044)))
6380 d_rounding = total_size - save_size;
6382 offset_base = d + d_rounding;
6384 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
6387 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6388 tmp_pnt = schedule.temps;
6389 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6391 enum machine_mode mode = entry->mode;
6392 unsigned int reg = entry->reg;
6393 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
6396 offset = entry->offset;
6398 reg_rtx = gen_rtx_REG (mode, reg);
6400 mem_rtx = gen_frame_mem (mode,
6401 gen_rtx_PLUS (Pmode,
6405 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
6412 if (HAVE_PRE_DECREMENT
6413 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6414 || mem_rtx == NULL_RTX
6415 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6417 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
6419 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
6428 offset += GET_MODE_SIZE (mode);
6432 if (mem_rtx != NULL_RTX)
6435 if (offset_in_r0 == -1)
6437 emit_move_insn (r0, GEN_INT (offset));
6438 offset_in_r0 = offset;
6440 else if (offset != offset_in_r0)
6445 GEN_INT (offset - offset_in_r0)));
6446 offset_in_r0 += offset - offset_in_r0;
6449 if (pre_dec != NULL_RTX)
6455 (Pmode, r0, stack_pointer_rtx));
6459 offset -= GET_MODE_SIZE (mode);
6460 offset_in_r0 -= GET_MODE_SIZE (mode);
6465 mem_rtx = gen_frame_mem (mode, r0);
6467 mem_rtx = gen_frame_mem (mode,
6468 gen_rtx_PLUS (Pmode,
6472 /* We must not use an r0-based address for target-branch
6473 registers or for special registers without pre-dec
6474 memory addresses, since we store their values in r0
6476 gcc_assert (!TARGET_REGISTER_P (reg)
6477 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6478 || mem_rtx == pre_dec));
6481 orig_reg_rtx = reg_rtx;
6482 if (TARGET_REGISTER_P (reg)
6483 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6484 && mem_rtx != pre_dec))
6486 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
6488 emit_move_insn (tmp_reg, reg_rtx);
6490 if (REGNO (tmp_reg) == R0_REG)
6494 gcc_assert (!refers_to_regno_p
6495 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
6498 if (*++tmp_pnt <= 0)
6499 tmp_pnt = schedule.temps;
6506 /* Mark as interesting for dwarf cfi generator */
6507 insn = emit_move_insn (mem_rtx, reg_rtx);
6508 RTX_FRAME_RELATED_P (insn) = 1;
6509 /* If we use an intermediate register for the save, we can't
6510 describe this exactly in cfi as a copy of the to-be-saved
6511 register into the temporary register and then the temporary
6512 register on the stack, because the temporary register can
6513 have a different natural size than the to-be-saved register.
6514 Thus, we gloss over the intermediate copy and pretend we do
6515 a direct save from the to-be-saved register. */
6516 if (REGNO (reg_rtx) != reg)
6520 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
6521 note_rtx = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set,
6523 REG_NOTES (insn) = note_rtx;
6526 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
6528 rtx reg_rtx = gen_rtx_REG (mode, reg);
6530 rtx mem_rtx = gen_frame_mem (mode,
6531 gen_rtx_PLUS (Pmode,
6535 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
6536 note_rtx = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set,
6538 REG_NOTES (insn) = note_rtx;
6543 gcc_assert (entry->offset == d_rounding);
6546 push_regs (&live_regs_mask, current_function_interrupt);
6548 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
6549 emit_insn (gen_GOTaddr2picreg ());
6551 if (SHMEDIA_REGS_STACK_ADJUST ())
6553 /* This must NOT go through the PLT, otherwise mach and macl
6554 may be clobbered. */
6555 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6557 ? "__GCC_push_shmedia_regs"
6558 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
6559 emit_insn (gen_shmedia_save_restore_regs_compact
6560 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
6563 if (target_flags != save_flags && ! current_function_interrupt)
6564 emit_insn (gen_toggle_sz ());
6566 target_flags = save_flags;
6568 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
6569 stack_pointer_rtx, 0, NULL);
6571 if (frame_pointer_needed)
6572 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
6574 if (TARGET_SHCOMPACT
6575 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6577 /* This must NOT go through the PLT, otherwise mach and macl
6578 may be clobbered. */
6579 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6580 "__GCC_shcompact_incoming_args", SFUNC_GOT);
6581 emit_insn (gen_shcompact_incoming_args ());
6586 sh_expand_epilogue (bool sibcall_p)
6588 HARD_REG_SET live_regs_mask;
6592 int save_flags = target_flags;
6593 int frame_size, save_size;
6594 int fpscr_deferred = 0;
6595 int e = sibcall_p ? -1 : 1;
6597 d = calc_live_regs (&live_regs_mask);
6600 frame_size = rounded_frame_size (d);
6604 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6606 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
6607 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6608 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
6610 total_size = d + tregs_space;
6611 total_size += rounded_frame_size (total_size);
6612 save_size = total_size - frame_size;
6614 /* If adjusting the stack in a single step costs nothing extra, do so.
6615 I.e. either if a single addi is enough, or we need a movi anyway,
6616 and we don't exceed the maximum offset range (the test for the
6617 latter is conservative for simplicity). */
6619 && ! frame_pointer_needed
6620 && (CONST_OK_FOR_I10 (total_size)
6621 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
6622 && total_size <= 2044)))
6623 d_rounding = frame_size;
6625 frame_size -= d_rounding;
6628 if (frame_pointer_needed)
6630 /* We must avoid scheduling the epilogue with previous basic blocks
6631 when exception handling is enabled. See PR/18032. */
6632 if (flag_exceptions)
6633 emit_insn (gen_blockage ());
6634 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
6637 /* We must avoid moving the stack pointer adjustment past code
6638 which reads from the local frame, else an interrupt could
6639 occur after the SP adjustment and clobber data in the local
6641 emit_insn (gen_blockage ());
6642 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
6644 else if (frame_size)
6646 /* We must avoid moving the stack pointer adjustment past code
6647 which reads from the local frame, else an interrupt could
6648 occur after the SP adjustment and clobber data in the local
6650 emit_insn (gen_blockage ());
6651 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
6654 if (SHMEDIA_REGS_STACK_ADJUST ())
6656 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6658 ? "__GCC_pop_shmedia_regs"
6659 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
6660 /* This must NOT go through the PLT, otherwise mach and macl
6661 may be clobbered. */
6662 emit_insn (gen_shmedia_save_restore_regs_compact
6663 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
6666 /* Pop all the registers. */
6668 if (target_flags != save_flags && ! current_function_interrupt)
6669 emit_insn (gen_toggle_sz ());
6672 int offset_base, offset;
6673 int offset_in_r0 = -1;
6675 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
6676 save_schedule schedule;
6680 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
6681 offset_base = -entry[1].offset + d_rounding;
6682 tmp_pnt = schedule.temps;
6683 for (; entry->mode != VOIDmode; entry--)
6685 enum machine_mode mode = entry->mode;
6686 int reg = entry->reg;
6687 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
6689 offset = offset_base + entry->offset;
6690 reg_rtx = gen_rtx_REG (mode, reg);
6692 mem_rtx = gen_frame_mem (mode,
6693 gen_rtx_PLUS (Pmode,
6697 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
6703 if (HAVE_POST_INCREMENT
6704 && (offset == offset_in_r0
6705 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
6706 && mem_rtx == NULL_RTX)
6707 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6709 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
6711 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
6714 post_inc = NULL_RTX;
6723 if (mem_rtx != NULL_RTX)
6726 if (offset_in_r0 == -1)
6728 emit_move_insn (r0, GEN_INT (offset));
6729 offset_in_r0 = offset;
6731 else if (offset != offset_in_r0)
6736 GEN_INT (offset - offset_in_r0)));
6737 offset_in_r0 += offset - offset_in_r0;
6740 if (post_inc != NULL_RTX)
6746 (Pmode, r0, stack_pointer_rtx));
6752 offset_in_r0 += GET_MODE_SIZE (mode);
6755 mem_rtx = gen_frame_mem (mode, r0);
6757 mem_rtx = gen_frame_mem (mode,
6758 gen_rtx_PLUS (Pmode,
6762 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6763 || mem_rtx == post_inc);
6766 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6767 && mem_rtx != post_inc)
6769 insn = emit_move_insn (r0, mem_rtx);
6772 else if (TARGET_REGISTER_P (reg))
6774 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
6776 /* Give the scheduler a bit of freedom by using up to
6777 MAX_TEMPS registers in a round-robin fashion. */
6778 insn = emit_move_insn (tmp_reg, mem_rtx);
6781 tmp_pnt = schedule.temps;
6784 insn = emit_move_insn (reg_rtx, mem_rtx);
6787 gcc_assert (entry->offset + offset_base == d + d_rounding);
6789 else /* ! TARGET_SH5 */
6794 /* For an ISR with RESBANK attribute assigned, don't pop PR
6796 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
6797 && !sh_cfun_resbank_handler_p ())
6799 if (!frame_pointer_needed)
6800 emit_insn (gen_blockage ());
6804 /* Banked registers are poped first to avoid being scheduled in the
6805 delay slot. RTE switches banks before the ds instruction. */
6806 if (current_function_interrupt)
6808 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6809 if (TEST_HARD_REG_BIT (live_regs_mask, i))
6810 pop (LAST_BANKED_REG - i);
6812 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
6815 last_reg = FIRST_PSEUDO_REGISTER;
6817 for (i = 0; i < last_reg; i++)
6819 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
6821 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
6822 && hard_reg_set_intersect_p (live_regs_mask,
6823 reg_class_contents[DF_REGS]))
6825 /* For an ISR with RESBANK attribute assigned, don't pop
6826 following registers, R0-R14, MACH, MACL and GBR. */
6827 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
6828 && ! (sh_cfun_resbank_handler_p ()
6829 && ((j >= FIRST_GENERAL_REG
6830 && j < LAST_GENERAL_REG)
6836 if (j == FIRST_FP_REG && fpscr_deferred)
6840 if (target_flags != save_flags && ! current_function_interrupt)
6841 emit_insn (gen_toggle_sz ());
6842 target_flags = save_flags;
6844 output_stack_adjust (crtl->args.pretend_args_size
6845 + save_size + d_rounding
6846 + crtl->args.info.stack_regs * 8,
6847 stack_pointer_rtx, e, NULL);
6849 if (crtl->calls_eh_return)
6850 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
6851 EH_RETURN_STACKADJ_RTX));
6853 /* Switch back to the normal stack if necessary. */
6854 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
6855 emit_insn (gen_sp_switch_2 ());
6857 /* Tell flow the insn that pops PR isn't dead. */
6858 /* PR_REG will never be live in SHmedia mode, and we don't need to
6859 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
6860 by the return pattern. */
6861 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
6862 emit_use (gen_rtx_REG (SImode, PR_REG));
6865 static int sh_need_epilogue_known = 0;
6868 sh_need_epilogue (void)
6870 if (! sh_need_epilogue_known)
6875 sh_expand_epilogue (0);
6876 epilogue = get_insns ();
6878 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
6880 return sh_need_epilogue_known > 0;
6883 /* Emit code to change the current function's return address to RA.
6884 TEMP is available as a scratch register, if needed. */
6887 sh_set_return_address (rtx ra, rtx tmp)
6889 HARD_REG_SET live_regs_mask;
6891 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
6894 d = calc_live_regs (&live_regs_mask);
6896 /* If pr_reg isn't life, we can set it (or the register given in
6897 sh_media_register_for_return) directly. */
6898 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
6904 int rr_regno = sh_media_register_for_return ();
6909 rr = gen_rtx_REG (DImode, rr_regno);
6912 rr = gen_rtx_REG (SImode, pr_reg);
6914 emit_insn (GEN_MOV (rr, ra));
6915 /* Tell flow the register for return isn't dead. */
6923 save_schedule schedule;
6926 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
6927 offset = entry[1].offset;
6928 for (; entry->mode != VOIDmode; entry--)
6929 if (entry->reg == pr_reg)
6932 /* We can't find pr register. */
6936 offset = entry->offset - offset;
6937 pr_offset = (rounded_frame_size (d) + offset
6938 + SHMEDIA_REGS_STACK_ADJUST ());
6941 pr_offset = rounded_frame_size (d);
6943 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
6944 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
6946 tmp = gen_frame_mem (Pmode, tmp);
6947 emit_insn (GEN_MOV (tmp, ra));
6950 /* Clear variables at function end. */
6953 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6954 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6956 sh_need_epilogue_known = 0;
6960 sh_builtin_saveregs (void)
6962 /* First unnamed integer register. */
6963 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
6964 /* Number of integer registers we need to save. */
6965 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
6966 /* First unnamed SFmode float reg */
6967 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
6968 /* Number of SFmode float regs to save. */
6969 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
6972 alias_set_type alias_set;
6978 int pushregs = n_intregs;
6980 while (pushregs < NPARM_REGS (SImode) - 1
6981 && (CALL_COOKIE_INT_REG_GET
6982 (crtl->args.info.call_cookie,
6983 NPARM_REGS (SImode) - pushregs)
6986 crtl->args.info.call_cookie
6987 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
6992 if (pushregs == NPARM_REGS (SImode))
6993 crtl->args.info.call_cookie
6994 |= (CALL_COOKIE_INT_REG (0, 1)
6995 | CALL_COOKIE_STACKSEQ (pushregs - 1));
6997 crtl->args.info.call_cookie
6998 |= CALL_COOKIE_STACKSEQ (pushregs);
7000 crtl->args.pretend_args_size += 8 * n_intregs;
7002 if (TARGET_SHCOMPACT)
7006 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
7008 error ("__builtin_saveregs not supported by this subtarget");
7015 /* Allocate block of memory for the regs. */
7016 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7017 Or can assign_stack_local accept a 0 SIZE argument? */
7018 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7021 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
7022 else if (n_floatregs & 1)
7026 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7027 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7028 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7029 regbuf = change_address (regbuf, BLKmode, addr);
7031 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7035 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7036 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7037 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7038 emit_insn (gen_andsi3 (addr, addr, mask));
7039 regbuf = change_address (regbuf, BLKmode, addr);
7042 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7043 alias_set = get_varargs_alias_set ();
7044 set_mem_alias_set (regbuf, alias_set);
7047 This is optimized to only save the regs that are necessary. Explicitly
7048 named args need not be saved. */
7050 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7051 adjust_address (regbuf, BLKmode,
7052 n_floatregs * UNITS_PER_WORD),
7056 /* Return the address of the regbuf. */
7057 return XEXP (regbuf, 0);
7060 This is optimized to only save the regs that are necessary. Explicitly
7061 named args need not be saved.
7062 We explicitly build a pointer to the buffer because it halves the insn
7063 count when not optimizing (otherwise the pointer is built for each reg
7065 We emit the moves in reverse order so that we can use predecrement. */
7067 fpregs = copy_to_mode_reg (Pmode,
7068 plus_constant (XEXP (regbuf, 0),
7069 n_floatregs * UNITS_PER_WORD));
7070 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7073 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7075 emit_insn (gen_addsi3 (fpregs, fpregs,
7076 GEN_INT (-2 * UNITS_PER_WORD)));
7077 mem = change_address (regbuf, DFmode, fpregs);
7078 emit_move_insn (mem,
7079 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7081 regno = first_floatreg;
7084 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7085 mem = change_address (regbuf, SFmode, fpregs);
7086 emit_move_insn (mem,
7087 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7088 - (TARGET_LITTLE_ENDIAN != 0)));
7092 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7096 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7097 mem = change_address (regbuf, SFmode, fpregs);
7098 emit_move_insn (mem,
7099 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7102 /* Return the address of the regbuf. */
7103 return XEXP (regbuf, 0);
7106 /* Define the `__builtin_va_list' type for the ABI. */
7109 sh_build_builtin_va_list (void)
7111 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7114 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7115 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7116 return ptr_type_node;
7118 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7120 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
7122 f_next_o_limit = build_decl (FIELD_DECL,
7123 get_identifier ("__va_next_o_limit"),
7125 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
7127 f_next_fp_limit = build_decl (FIELD_DECL,
7128 get_identifier ("__va_next_fp_limit"),
7130 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
7133 DECL_FIELD_CONTEXT (f_next_o) = record;
7134 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7135 DECL_FIELD_CONTEXT (f_next_fp) = record;
7136 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7137 DECL_FIELD_CONTEXT (f_next_stack) = record;
7139 TYPE_FIELDS (record) = f_next_o;
7140 TREE_CHAIN (f_next_o) = f_next_o_limit;
7141 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7142 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7143 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7145 layout_type (record);
7150 /* Implement `va_start' for varargs and stdarg. */
7153 sh_va_start (tree valist, rtx nextarg)
7155 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7156 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7162 expand_builtin_saveregs ();
7163 std_expand_builtin_va_start (valist, nextarg);
7167 if ((! TARGET_SH2E && ! TARGET_SH4)
7168 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7170 std_expand_builtin_va_start (valist, nextarg);
7174 f_next_o = TYPE_FIELDS (va_list_type_node);
7175 f_next_o_limit = TREE_CHAIN (f_next_o);
7176 f_next_fp = TREE_CHAIN (f_next_o_limit);
7177 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7178 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7180 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7182 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7183 valist, f_next_o_limit, NULL_TREE);
7184 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7186 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7187 valist, f_next_fp_limit, NULL_TREE);
7188 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7189 valist, f_next_stack, NULL_TREE);
7191 /* Call __builtin_saveregs. */
7192 u = make_tree (sizetype, expand_builtin_saveregs ());
7193 u = fold_convert (ptr_type_node, u);
7194 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7195 TREE_SIDE_EFFECTS (t) = 1;
7196 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7198 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7203 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7204 size_int (UNITS_PER_WORD * nfp));
7205 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7206 TREE_SIDE_EFFECTS (t) = 1;
7207 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7209 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7210 TREE_SIDE_EFFECTS (t) = 1;
7211 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7213 nint = crtl->args.info.arg_count[SH_ARG_INT];
7218 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7219 size_int (UNITS_PER_WORD * nint));
7220 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7221 TREE_SIDE_EFFECTS (t) = 1;
7222 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7224 u = make_tree (ptr_type_node, nextarg);
7225 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7226 TREE_SIDE_EFFECTS (t) = 1;
7227 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7230 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7231 member, return it. */
7233 find_sole_member (tree type)
7235 tree field, member = NULL_TREE;
7237 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7239 if (TREE_CODE (field) != FIELD_DECL)
7241 if (!DECL_SIZE (field))
7243 if (integer_zerop (DECL_SIZE (field)))
7251 /* Implement `va_arg'. */
7254 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7255 gimple_seq *post_p ATTRIBUTE_UNUSED)
7257 HOST_WIDE_INT size, rsize;
7258 tree tmp, pptr_type_node;
7259 tree addr, lab_over = NULL, result = NULL;
7260 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7264 type = build_pointer_type (type);
7266 size = int_size_in_bytes (type);
7267 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7268 pptr_type_node = build_pointer_type (ptr_type_node);
7270 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7271 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7273 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7274 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7279 f_next_o = TYPE_FIELDS (va_list_type_node);
7280 f_next_o_limit = TREE_CHAIN (f_next_o);
7281 f_next_fp = TREE_CHAIN (f_next_o_limit);
7282 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7283 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7285 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7287 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7288 valist, f_next_o_limit, NULL_TREE);
7289 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7290 valist, f_next_fp, NULL_TREE);
7291 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7292 valist, f_next_fp_limit, NULL_TREE);
7293 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7294 valist, f_next_stack, NULL_TREE);
7296 /* Structures with a single member with a distinct mode are passed
7297 like their member. This is relevant if the latter has a REAL_TYPE
7298 or COMPLEX_TYPE type. */
7300 while (TREE_CODE (eff_type) == RECORD_TYPE
7301 && (member = find_sole_member (eff_type))
7302 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7303 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7304 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7306 tree field_type = TREE_TYPE (member);
7308 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7309 eff_type = field_type;
7312 gcc_assert ((TYPE_ALIGN (eff_type)
7313 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7314 || (TYPE_ALIGN (eff_type)
7315 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7320 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7322 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7323 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7324 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7329 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7332 addr = create_tmp_var (pptr_type_node, NULL);
7333 lab_false = create_artificial_label ();
7334 lab_over = create_artificial_label ();
7336 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
7340 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7342 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7344 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
7345 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7347 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
7348 tmp = next_fp_limit;
7349 if (size > 4 && !is_double)
7350 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp),
7351 unshare_expr (tmp), size_int (4 - size));
7352 tmp = build2 (GE_EXPR, boolean_type_node,
7353 unshare_expr (next_fp_tmp), unshare_expr (tmp));
7354 cmp = build3 (COND_EXPR, void_type_node, tmp,
7355 build1 (GOTO_EXPR, void_type_node,
7356 unshare_expr (lab_false)), NULL_TREE);
7358 gimplify_and_add (cmp, pre_p);
7360 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7361 || (is_double || size == 16))
7363 tmp = fold_convert (sizetype, next_fp_tmp);
7364 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7365 size_int (UNITS_PER_WORD));
7366 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7367 unshare_expr (next_fp_tmp), tmp);
7368 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
7371 gimplify_and_add (cmp, pre_p);
7373 #ifdef FUNCTION_ARG_SCmode_WART
7374 if (TYPE_MODE (eff_type) == SCmode
7375 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7377 tree subtype = TREE_TYPE (eff_type);
7381 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7382 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7385 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7386 real = get_initialized_tmp_var (real, pre_p, NULL);
7388 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
7389 if (type != eff_type)
7390 result = build1 (VIEW_CONVERT_EXPR, type, result);
7391 result = get_initialized_tmp_var (result, pre_p, NULL);
7393 #endif /* FUNCTION_ARG_SCmode_WART */
7395 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7396 gimplify_and_add (tmp, pre_p);
7398 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7399 gimplify_and_add (tmp, pre_p);
7401 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7402 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7403 gimplify_assign (unshare_expr (next_fp_tmp),
7404 unshare_expr (valist), pre_p);
7406 gimplify_assign (unshare_expr (valist),
7407 unshare_expr (next_fp_tmp), post_p);
7408 valist = next_fp_tmp;
7412 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7413 unshare_expr (next_o), size_int (rsize));
7414 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
7415 unshare_expr (next_o_limit));
7416 tmp = build3 (COND_EXPR, void_type_node, tmp,
7417 build1 (GOTO_EXPR, void_type_node,
7418 unshare_expr (lab_false)),
7420 gimplify_and_add (tmp, pre_p);
7422 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
7423 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7425 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7426 gimplify_and_add (tmp, pre_p);
7428 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7429 gimplify_and_add (tmp, pre_p);
7431 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7432 gimplify_assign (unshare_expr (next_o),
7433 unshare_expr (next_o_limit), pre_p);
7435 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7436 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7441 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7442 gimplify_and_add (tmp, pre_p);
7446 /* ??? In va-sh.h, there had been code to make values larger than
7447 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7449 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7452 gimplify_assign (result, tmp, pre_p);
7454 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7455 gimplify_and_add (tmp, pre_p);
7461 result = build_va_arg_indirect_ref (result);
7467 sh_promote_prototypes (const_tree type)
7473 return ! sh_attr_renesas_p (type);
7476 /* Whether an argument must be passed by reference. On SHcompact, we
7477 pretend arguments wider than 32-bits that would have been passed in
7478 registers are passed by reference, so that an SHmedia trampoline
7479 loads them into the full 64-bits registers. */
7482 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
7483 const_tree type, bool named)
7485 unsigned HOST_WIDE_INT size;
7488 size = int_size_in_bytes (type);
7490 size = GET_MODE_SIZE (mode);
7492 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
7494 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
7495 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
7496 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
7498 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
7499 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7506 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7507 const_tree type, bool named)
7509 if (targetm.calls.must_pass_in_stack (mode, type))
7512 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7513 wants to know about pass-by-reference semantics for incoming
7518 if (TARGET_SHCOMPACT)
7520 cum->byref = shcompact_byref (cum, mode, type, named);
7521 return cum->byref != 0;
7528 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7529 const_tree type, bool named ATTRIBUTE_UNUSED)
7531 /* ??? How can it possibly be correct to return true only on the
7532 caller side of the equation? Is there someplace else in the
7533 sh backend that's magically producing the copies? */
7534 return (cum->outgoing
7535 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
7536 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
7540 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7541 tree type, bool named ATTRIBUTE_UNUSED)
7546 && PASS_IN_REG_P (*cum, mode, type)
7547 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7548 && (ROUND_REG (*cum, mode)
7550 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
7551 : ROUND_ADVANCE (int_size_in_bytes (type)))
7552 > NPARM_REGS (mode)))
7553 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
7555 else if (!TARGET_SHCOMPACT
7556 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7557 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
7559 return words * UNITS_PER_WORD;
7563 /* Define where to put the arguments to a function.
7564 Value is zero to push the argument on the stack,
7565 or a hard register in which to store the argument.
7567 MODE is the argument's machine mode.
7568 TYPE is the data type of the argument (as a tree).
7569 This is null for libcalls where that information may
7571 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7572 the preceding args and about the function being called.
7573 NAMED is nonzero if this argument is a named parameter
7574 (otherwise it is an extra parameter matching an ellipsis).
7576 On SH the first args are normally in registers
7577 and the rest are pushed. Any arg that starts within the first
7578 NPARM_REGS words is at least partially passed in a register unless
7579 its data type forbids. */
7583 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7584 tree type, int named)
7586 if (! TARGET_SH5 && mode == VOIDmode)
7587 return GEN_INT (ca->renesas_abi ? 1 : 0);
7590 && PASS_IN_REG_P (*ca, mode, type)
7591 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
7595 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
7596 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
7598 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
7599 gen_rtx_REG (SFmode,
7601 + (ROUND_REG (*ca, mode) ^ 1)),
7603 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
7604 gen_rtx_REG (SFmode,
7606 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
7608 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
7611 /* If the alignment of a DF value causes an SF register to be
7612 skipped, we will use that skipped register for the next SF
7614 if ((TARGET_HITACHI || ca->renesas_abi)
7615 && ca->free_single_fp_reg
7617 return gen_rtx_REG (mode, ca->free_single_fp_reg);
7619 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
7620 ^ (mode == SFmode && TARGET_SH4
7621 && TARGET_LITTLE_ENDIAN != 0
7622 && ! TARGET_HITACHI && ! ca->renesas_abi);
7623 return gen_rtx_REG (mode, regno);
7629 if (mode == VOIDmode && TARGET_SHCOMPACT)
7630 return GEN_INT (ca->call_cookie);
7632 /* The following test assumes unnamed arguments are promoted to
7634 if (mode == SFmode && ca->free_single_fp_reg)
7635 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
7637 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
7638 && (named || ! ca->prototype_p)
7639 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
7641 if (! ca->prototype_p && TARGET_SHMEDIA)
7642 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
7644 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
7646 + ca->arg_count[(int) SH_ARG_FLOAT]);
7649 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
7650 && (! TARGET_SHCOMPACT
7651 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
7652 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
7655 return gen_rtx_REG (mode, (FIRST_PARM_REG
7656 + ca->arg_count[(int) SH_ARG_INT]));
7665 /* Update the data in CUM to advance over an argument
7666 of mode MODE and data type TYPE.
7667 (TYPE is null for libcalls where that information may not be
7671 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7672 tree type, int named)
7676 else if (TARGET_SH5)
7678 tree type2 = (ca->byref && type
7681 enum machine_mode mode2 = (ca->byref && type
7684 int dwords = ((ca->byref
7687 ? int_size_in_bytes (type2)
7688 : GET_MODE_SIZE (mode2)) + 7) / 8;
7689 int numregs = MIN (dwords, NPARM_REGS (SImode)
7690 - ca->arg_count[(int) SH_ARG_INT]);
7694 ca->arg_count[(int) SH_ARG_INT] += numregs;
7695 if (TARGET_SHCOMPACT
7696 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
7699 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7701 /* N.B. We want this also for outgoing. */
7702 ca->stack_regs += numregs;
7707 ca->stack_regs += numregs;
7708 ca->byref_regs += numregs;
7712 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7716 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7719 else if (dwords > numregs)
7721 int pushregs = numregs;
7723 if (TARGET_SHCOMPACT)
7724 ca->stack_regs += numregs;
7725 while (pushregs < NPARM_REGS (SImode) - 1
7726 && (CALL_COOKIE_INT_REG_GET
7728 NPARM_REGS (SImode) - pushregs)
7732 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7736 if (numregs == NPARM_REGS (SImode))
7738 |= CALL_COOKIE_INT_REG (0, 1)
7739 | CALL_COOKIE_STACKSEQ (numregs - 1);
7742 |= CALL_COOKIE_STACKSEQ (numregs);
7745 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
7746 && (named || ! ca->prototype_p))
7748 if (mode2 == SFmode && ca->free_single_fp_reg)
7749 ca->free_single_fp_reg = 0;
7750 else if (ca->arg_count[(int) SH_ARG_FLOAT]
7751 < NPARM_REGS (SFmode))
7754 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
7756 - ca->arg_count[(int) SH_ARG_FLOAT]);
7758 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
7760 if (TARGET_SHCOMPACT && ! ca->prototype_p)
7762 if (ca->outgoing && numregs > 0)
7766 |= (CALL_COOKIE_INT_REG
7767 (ca->arg_count[(int) SH_ARG_INT]
7768 - numregs + ((numfpregs - 2) / 2),
7769 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
7772 while (numfpregs -= 2);
7774 else if (mode2 == SFmode && (named)
7775 && (ca->arg_count[(int) SH_ARG_FLOAT]
7776 < NPARM_REGS (SFmode)))
7777 ca->free_single_fp_reg
7778 = FIRST_FP_PARM_REG - numfpregs
7779 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
7785 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
7787 /* Note that we've used the skipped register. */
7788 if (mode == SFmode && ca->free_single_fp_reg)
7790 ca->free_single_fp_reg = 0;
7793 /* When we have a DF after an SF, there's an SF register that get
7794 skipped in order to align the DF value. We note this skipped
7795 register, because the next SF value will use it, and not the
7796 SF that follows the DF. */
7798 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
7800 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
7801 + BASE_ARG_REG (mode));
7805 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
7806 || PASS_IN_REG_P (*ca, mode, type))
7807 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
7808 = (ROUND_REG (*ca, mode)
7810 ? ROUND_ADVANCE (int_size_in_bytes (type))
7811 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
7814 /* The Renesas calling convention doesn't quite fit into this scheme since
7815 the address is passed like an invisible argument, but one that is always
7816 passed in memory. */
7818 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
7820 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7822 return gen_rtx_REG (Pmode, 2);
7825 /* Worker function for TARGET_RETURN_IN_MEMORY. */
7828 sh_return_in_memory (const_tree type, const_tree fndecl)
7832 if (TYPE_MODE (type) == BLKmode)
7833 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
7835 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
7839 return (TYPE_MODE (type) == BLKmode
7840 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7841 && TREE_CODE (type) == RECORD_TYPE));
7845 /* We actually emit the code in sh_expand_prologue. We used to use
7846 a static variable to flag that we need to emit this code, but that
7847 doesn't when inlining, when functions are deferred and then emitted
7848 later. Fortunately, we already have two flags that are part of struct
7849 function that tell if a function uses varargs or stdarg. */
7851 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
7852 enum machine_mode mode,
7854 int *pretend_arg_size,
7855 int second_time ATTRIBUTE_UNUSED)
7857 gcc_assert (cfun->stdarg);
7858 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
7860 int named_parm_regs, anon_parm_regs;
7862 named_parm_regs = (ROUND_REG (*ca, mode)
7864 ? ROUND_ADVANCE (int_size_in_bytes (type))
7865 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
7866 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
7867 if (anon_parm_regs > 0)
7868 *pretend_arg_size = anon_parm_regs * 4;
7873 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
7879 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
7881 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
7885 /* Define the offset between two registers, one to be eliminated, and
7886 the other its replacement, at the start of a routine. */
7889 initial_elimination_offset (int from, int to)
7892 int regs_saved_rounding = 0;
7893 int total_saved_regs_space;
7894 int total_auto_space;
7895 int save_flags = target_flags;
7897 HARD_REG_SET live_regs_mask;
7899 shmedia_space_reserved_for_target_registers = false;
7900 regs_saved = calc_live_regs (&live_regs_mask);
7901 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
7903 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
7905 shmedia_space_reserved_for_target_registers = true;
7906 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
7909 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
7910 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7911 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
7913 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
7914 copy_flags = target_flags;
7915 target_flags = save_flags;
7917 total_saved_regs_space = regs_saved + regs_saved_rounding;
7919 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7920 return total_saved_regs_space + total_auto_space
7921 + crtl->args.info.byref_regs * 8;
7923 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7924 return total_saved_regs_space + total_auto_space
7925 + crtl->args.info.byref_regs * 8;
7927 /* Initial gap between fp and sp is 0. */
7928 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7931 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7932 return rounded_frame_size (0);
7934 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7935 return rounded_frame_size (0);
7937 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
7938 && (to == HARD_FRAME_POINTER_REGNUM
7939 || to == STACK_POINTER_REGNUM));
7942 int n = total_saved_regs_space;
7943 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7944 save_schedule schedule;
7947 n += total_auto_space;
7949 /* If it wasn't saved, there's not much we can do. */
7950 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7953 target_flags = copy_flags;
7955 sh5_schedule_saves (&live_regs_mask, &schedule, n);
7956 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
7957 if (entry->reg == pr_reg)
7959 target_flags = save_flags;
7960 return entry->offset;
7965 return total_auto_space;
7968 /* Parse the -mfixed-range= option string. */
7970 sh_fix_range (const char *const_str)
7973 char *str, *dash, *comma;
7975 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
7976 REG2 are either register names or register numbers. The effect
7977 of this option is to mark the registers in the range from REG1 to
7978 REG2 as ``fixed'' so they won't be used by the compiler. */
7980 i = strlen (const_str);
7981 str = (char *) alloca (i + 1);
7982 memcpy (str, const_str, i + 1);
7986 dash = strchr (str, '-');
7989 warning (0, "value of -mfixed-range must have form REG1-REG2");
7993 comma = strchr (dash + 1, ',');
7997 first = decode_reg_name (str);
8000 warning (0, "unknown register name: %s", str);
8004 last = decode_reg_name (dash + 1);
8007 warning (0, "unknown register name: %s", dash + 1);
8015 warning (0, "%s-%s is an empty range", str, dash + 1);
8019 for (i = first; i <= last; ++i)
8020 fixed_regs[i] = call_used_regs[i] = 1;
8030 /* Insert any deferred function attributes from earlier pragmas. */
8032 sh_insert_attributes (tree node, tree *attributes)
8036 if (TREE_CODE (node) != FUNCTION_DECL)
8039 /* We are only interested in fields. */
8043 /* Append the attributes to the deferred attributes. */
8044 *sh_deferred_function_attributes_tail = *attributes;
8045 attrs = sh_deferred_function_attributes;
8049 /* Some attributes imply or require the interrupt attribute. */
8050 if (!lookup_attribute ("interrupt_handler", attrs)
8051 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8053 /* If we have a trapa_handler, but no interrupt_handler attribute,
8054 insert an interrupt_handler attribute. */
8055 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8056 /* We can't use sh_pr_interrupt here because that's not in the
8059 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8060 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8061 if the interrupt attribute is missing, we ignore the attribute
8063 else if (lookup_attribute ("sp_switch", attrs)
8064 || lookup_attribute ("trap_exit", attrs)
8065 || lookup_attribute ("nosave_low_regs", attrs)
8066 || lookup_attribute ("resbank", attrs))
8070 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8072 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8073 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8074 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8075 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8076 warning (OPT_Wattributes,
8077 "%qs attribute only applies to interrupt functions",
8078 IDENTIFIER_POINTER (TREE_PURPOSE (attrs)));
8081 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8083 tail = &TREE_CHAIN (*tail);
8086 attrs = *attributes;
8090 /* Install the processed list. */
8091 *attributes = attrs;
8093 /* Clear deferred attributes. */
8094 sh_deferred_function_attributes = NULL_TREE;
8095 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8100 /* Supported attributes:
8102 interrupt_handler -- specifies this function is an interrupt handler.
8104 trapa_handler - like above, but don't save all registers.
8106 sp_switch -- specifies an alternate stack for an interrupt handler
8109 trap_exit -- use a trapa to exit an interrupt function instead of
8112 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8113 This is useful on the SH3 and upwards,
8114 which has a separate set of low regs for User and Supervisor modes.
8115 This should only be used for the lowest level of interrupts. Higher levels
8116 of interrupts must save the registers in case they themselves are
8119 renesas -- use Renesas calling/layout conventions (functions and
8122 resbank -- In case of an ISR, use a register bank to save registers
8123 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8126 const struct attribute_spec sh_attribute_table[] =
8128 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8129 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8130 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
8131 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
8132 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
8133 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8134 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8135 { "resbank", 0, 0, true, false, false, sh_handle_resbank_handler_attribute },
8136 { "function_vector", 1, 1, true, false, false, sh2a_handle_function_vector_handler_attribute },
8138 /* Symbian support adds three new attributes:
8139 dllexport - for exporting a function/variable that will live in a dll
8140 dllimport - for importing a function/variable from a dll
8142 Microsoft allows multiple declspecs in one __declspec, separating
8143 them with spaces. We do NOT support this. Instead, use __declspec
8145 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8146 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8148 { NULL, 0, 0, false, false, false, NULL }
8151 /* Handle a 'resbank' attribute. */
8153 sh_handle_resbank_handler_attribute (tree * node, tree name,
8154 tree args ATTRIBUTE_UNUSED,
8155 int flags ATTRIBUTE_UNUSED,
8156 bool * no_add_attrs)
8160 warning (OPT_Wattributes, "%qs attribute is supported only for SH2A",
8161 IDENTIFIER_POINTER (name));
8162 *no_add_attrs = true;
8164 if (TREE_CODE (*node) != FUNCTION_DECL)
8166 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8167 IDENTIFIER_POINTER (name));
8168 *no_add_attrs = true;
8174 /* Handle an "interrupt_handler" attribute; arguments as in
8175 struct attribute_spec.handler. */
8177 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8178 tree args ATTRIBUTE_UNUSED,
8179 int flags ATTRIBUTE_UNUSED,
8182 if (TREE_CODE (*node) != FUNCTION_DECL)
8184 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8185 IDENTIFIER_POINTER (name));
8186 *no_add_attrs = true;
8188 else if (TARGET_SHCOMPACT)
8190 error ("attribute interrupt_handler is not compatible with -m5-compact");
8191 *no_add_attrs = true;
8197 /* Handle an 'function_vector' attribute; arguments as in
8198 struct attribute_spec.handler. */
8200 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8201 tree args ATTRIBUTE_UNUSED,
8202 int flags ATTRIBUTE_UNUSED,
8203 bool * no_add_attrs)
8207 warning (OPT_Wattributes, "%qs attribute only applies to SH2A",
8208 IDENTIFIER_POINTER (name));
8209 *no_add_attrs = true;
8211 else if (TREE_CODE (*node) != FUNCTION_DECL)
8213 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8214 IDENTIFIER_POINTER (name));
8215 *no_add_attrs = true;
8217 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8219 /* The argument must be a constant integer. */
8220 warning (OPT_Wattributes,
8221 "`%s' attribute argument not an integer constant",
8222 IDENTIFIER_POINTER (name));
8223 *no_add_attrs = true;
8225 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8227 /* The argument value must be between 0 to 255. */
8228 warning (OPT_Wattributes,
8229 "`%s' attribute argument should be between 0 to 255",
8230 IDENTIFIER_POINTER (name));
8231 *no_add_attrs = true;
8236 /* Returns 1 if current function has been assigned the attribute
8237 'function_vector'. */
8239 sh2a_is_function_vector_call (rtx x)
8241 if (GET_CODE (x) == SYMBOL_REF
8242 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8244 tree tr = SYMBOL_REF_DECL (x);
8246 if (sh2a_function_vector_p (tr))
8253 /* Returns the function vector number, if the the attribute
8254 'function_vector' is assigned, otherwise returns zero. */
8256 sh2a_get_function_vector_number (rtx x)
8261 if ((GET_CODE (x) == SYMBOL_REF)
8262 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8264 t = SYMBOL_REF_DECL (x);
8266 if (TREE_CODE (t) != FUNCTION_DECL)
8269 list = SH_ATTRIBUTES (t);
8272 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8274 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8278 list = TREE_CHAIN (list);
8287 /* Handle an "sp_switch" attribute; arguments as in
8288 struct attribute_spec.handler. */
8290 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8291 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8293 if (TREE_CODE (*node) != FUNCTION_DECL)
8295 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8296 IDENTIFIER_POINTER (name));
8297 *no_add_attrs = true;
8299 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8301 /* The argument must be a constant string. */
8302 warning (OPT_Wattributes, "%qs attribute argument not a string constant",
8303 IDENTIFIER_POINTER (name));
8304 *no_add_attrs = true;
8310 /* Handle an "trap_exit" attribute; arguments as in
8311 struct attribute_spec.handler. */
8313 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8314 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8316 if (TREE_CODE (*node) != FUNCTION_DECL)
8318 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8319 IDENTIFIER_POINTER (name));
8320 *no_add_attrs = true;
8322 /* The argument specifies a trap number to be used in a trapa instruction
8323 at function exit (instead of an rte instruction). */
8324 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8326 /* The argument must be a constant integer. */
8327 warning (OPT_Wattributes, "%qs attribute argument not an "
8328 "integer constant", IDENTIFIER_POINTER (name));
8329 *no_add_attrs = true;
8336 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8337 tree name ATTRIBUTE_UNUSED,
8338 tree args ATTRIBUTE_UNUSED,
8339 int flags ATTRIBUTE_UNUSED,
8340 bool *no_add_attrs ATTRIBUTE_UNUSED)
8345 /* True if __attribute__((renesas)) or -mrenesas. */
8347 sh_attr_renesas_p (const_tree td)
8354 td = TREE_TYPE (td);
8355 if (td == error_mark_node)
8357 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8361 /* True if __attribute__((renesas)) or -mrenesas, for the current
8364 sh_cfun_attr_renesas_p (void)
8366 return sh_attr_renesas_p (current_function_decl);
8370 sh_cfun_interrupt_handler_p (void)
8372 return (lookup_attribute ("interrupt_handler",
8373 DECL_ATTRIBUTES (current_function_decl))
8377 /* Returns 1 if FUNC has been assigned the attribute
8378 "function_vector". */
8380 sh2a_function_vector_p (tree func)
8383 if (TREE_CODE (func) != FUNCTION_DECL)
8386 list = SH_ATTRIBUTES (func);
8389 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8392 list = TREE_CHAIN (list);
8397 /* Returns TRUE if given tree has the "resbank" attribute. */
8400 sh_cfun_resbank_handler_p (void)
8402 return ((lookup_attribute ("resbank",
8403 DECL_ATTRIBUTES (current_function_decl))
8405 && (lookup_attribute ("interrupt_handler",
8406 DECL_ATTRIBUTES (current_function_decl))
8407 != NULL_TREE) && TARGET_SH2A);
8410 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8413 sh_check_pch_target_flags (int old_flags)
8415 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8416 | MASK_SH_E | MASK_HARD_SH4
8417 | MASK_FPU_SINGLE | MASK_SH4))
8418 return _("created and used with different architectures / ABIs");
8419 if ((old_flags ^ target_flags) & MASK_HITACHI)
8420 return _("created and used with different ABIs");
8421 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8422 return _("created and used with different endianness");
8426 /* Predicates used by the templates. */
8428 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
8429 Used only in general_movsrc_operand. */
8432 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8444 /* Nonzero if OP is a floating point value with value 0.0. */
8447 fp_zero_operand (rtx op)
8451 if (GET_MODE (op) != SFmode)
8454 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8455 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
8458 /* Nonzero if OP is a floating point value with value 1.0. */
8461 fp_one_operand (rtx op)
8465 if (GET_MODE (op) != SFmode)
8468 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8469 return REAL_VALUES_EQUAL (r, dconst1);
8472 /* For -m4 and -m4-single-only, mode switching is used. If we are
8473 compiling without -mfmovd, movsf_ie isn't taken into account for
8474 mode switching. We could check in machine_dependent_reorg for
8475 cases where we know we are in single precision mode, but there is
8476 interface to find that out during reload, so we must avoid
8477 choosing an fldi alternative during reload and thus failing to
8478 allocate a scratch register for the constant loading. */
8482 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
8486 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8488 enum rtx_code code = GET_CODE (op);
8489 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
8492 /* Return the TLS type for TLS symbols, 0 for otherwise. */
8494 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8496 if (GET_CODE (op) != SYMBOL_REF)
8498 return SYMBOL_REF_TLS_MODEL (op);
8501 /* Return the destination address of a branch. */
8504 branch_dest (rtx branch)
8506 rtx dest = SET_SRC (PATTERN (branch));
8509 if (GET_CODE (dest) == IF_THEN_ELSE)
8510 dest = XEXP (dest, 1);
8511 dest = XEXP (dest, 0);
8512 dest_uid = INSN_UID (dest);
8513 return INSN_ADDRESSES (dest_uid);
8516 /* Return nonzero if REG is not used after INSN.
8517 We assume REG is a reload reg, and therefore does
8518 not live past labels. It may live past calls or jumps though. */
8520 reg_unused_after (rtx reg, rtx insn)
8525 /* If the reg is set by this instruction, then it is safe for our
8526 case. Disregard the case where this is a store to memory, since
8527 we are checking a register used in the store address. */
8528 set = single_set (insn);
8529 if (set && GET_CODE (SET_DEST (set)) != MEM
8530 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8533 while ((insn = NEXT_INSN (insn)))
8539 code = GET_CODE (insn);
8542 /* If this is a label that existed before reload, then the register
8543 if dead here. However, if this is a label added by reorg, then
8544 the register may still be live here. We can't tell the difference,
8545 so we just ignore labels completely. */
8546 if (code == CODE_LABEL)
8551 if (code == JUMP_INSN)
8554 /* If this is a sequence, we must handle them all at once.
8555 We could have for instance a call that sets the target register,
8556 and an insn in a delay slot that uses the register. In this case,
8557 we must return 0. */
8558 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
8563 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8565 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
8566 rtx set = single_set (this_insn);
8568 if (GET_CODE (this_insn) == CALL_INSN)
8570 else if (GET_CODE (this_insn) == JUMP_INSN)
8572 if (INSN_ANNULLED_BRANCH_P (this_insn))
8577 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8579 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8581 if (GET_CODE (SET_DEST (set)) != MEM)
8587 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
8592 else if (code == JUMP_INSN)
8596 set = single_set (insn);
8597 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8599 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8600 return GET_CODE (SET_DEST (set)) != MEM;
8601 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
8604 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
8612 static GTY(()) rtx fpscr_rtx;
8614 get_fpscr_rtx (void)
8618 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
8619 REG_USERVAR_P (fpscr_rtx) = 1;
8620 mark_user_reg (fpscr_rtx);
8622 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
8623 mark_user_reg (fpscr_rtx);
8627 static GTY(()) tree fpscr_values;
8630 emit_fpu_switch (rtx scratch, int index)
8634 if (fpscr_values == NULL)
8638 t = build_index_type (integer_one_node);
8639 t = build_array_type (integer_type_node, t);
8640 t = build_decl (VAR_DECL, get_identifier ("__fpscr_values"), t);
8641 DECL_ARTIFICIAL (t) = 1;
8642 DECL_IGNORED_P (t) = 1;
8643 DECL_EXTERNAL (t) = 1;
8644 TREE_STATIC (t) = 1;
8645 TREE_PUBLIC (t) = 1;
8651 src = DECL_RTL (fpscr_values);
8652 if (!can_create_pseudo_p ())
8654 emit_move_insn (scratch, XEXP (src, 0));
8656 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
8657 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
8660 src = adjust_address (src, PSImode, index * 4);
8662 dst = get_fpscr_rtx ();
8663 emit_move_insn (dst, src);
8667 emit_sf_insn (rtx pat)
8673 emit_df_insn (rtx pat)
8679 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8681 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8685 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8687 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
8692 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8694 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8698 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8700 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
8704 static rtx get_free_reg (HARD_REG_SET);
8706 /* This function returns a register to use to load the address to load
8707 the fpscr from. Currently it always returns r1 or r7, but when we are
8708 able to use pseudo registers after combine, or have a better mechanism
8709 for choosing a register, it should be done here. */
8710 /* REGS_LIVE is the liveness information for the point for which we
8711 need this allocation. In some bare-bones exit blocks, r1 is live at the
8712 start. We can even have all of r0..r3 being live:
8713 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
8714 INSN before which new insns are placed with will clobber the register
8715 we return. If a basic block consists only of setting the return value
8716 register to a pseudo and using that register, the return value is not
8717 live before or after this block, yet we we'll insert our insns right in
8721 get_free_reg (HARD_REG_SET regs_live)
8723 if (! TEST_HARD_REG_BIT (regs_live, 1))
8724 return gen_rtx_REG (Pmode, 1);
8726 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
8727 there shouldn't be anything but a jump before the function end. */
8728 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
8729 return gen_rtx_REG (Pmode, 7);
8732 /* This function will set the fpscr from memory.
8733 MODE is the mode we are setting it to. */
8735 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
8737 enum attr_fp_mode fp_mode = mode;
8738 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
8741 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
8742 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
8745 /* Is the given character a logical line separator for the assembler? */
8746 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
8747 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
8751 sh_insn_length_adjustment (rtx insn)
8753 /* Instructions with unfilled delay slots take up an extra two bytes for
8754 the nop in the delay slot. */
8755 if (((GET_CODE (insn) == INSN
8756 && GET_CODE (PATTERN (insn)) != USE
8757 && GET_CODE (PATTERN (insn)) != CLOBBER)
8758 || GET_CODE (insn) == CALL_INSN
8759 || (GET_CODE (insn) == JUMP_INSN
8760 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8761 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
8762 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
8763 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
8766 /* SH2e has a bug that prevents the use of annulled branches, so if
8767 the delay slot is not filled, we'll have to put a NOP in it. */
8768 if (sh_cpu == CPU_SH2E
8769 && GET_CODE (insn) == JUMP_INSN
8770 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8771 && GET_CODE (PATTERN (insn)) != ADDR_VEC
8772 && get_attr_type (insn) == TYPE_CBRANCH
8773 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
8776 /* sh-dsp parallel processing insn take four bytes instead of two. */
8778 if (GET_CODE (insn) == INSN)
8781 rtx body = PATTERN (insn);
8784 int maybe_label = 1;
8786 if (GET_CODE (body) == ASM_INPUT)
8787 templ = XSTR (body, 0);
8788 else if (asm_noperands (body) >= 0)
8790 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
8799 while (c == ' ' || c == '\t');
8800 /* all sh-dsp parallel-processing insns start with p.
8801 The only non-ppi sh insn starting with p is pref.
8802 The only ppi starting with pr is prnd. */
8803 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
8805 /* The repeat pseudo-insn expands two three insns, a total of
8806 six bytes in size. */
8807 else if ((c == 'r' || c == 'R')
8808 && ! strncasecmp ("epeat", templ, 5))
8810 while (c && c != '\n'
8811 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
8813 /* If this is a label, it is obviously not a ppi insn. */
8814 if (c == ':' && maybe_label)
8819 else if (c == '\'' || c == '"')
8824 maybe_label = c != ':';
8832 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
8833 isn't protected by a PIC unspec. */
8835 nonpic_symbol_mentioned_p (rtx x)
8837 register const char *fmt;
8840 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
8841 || GET_CODE (x) == PC)
8844 /* We don't want to look into the possible MEM location of a
8845 CONST_DOUBLE, since we're not going to use it, in general. */
8846 if (GET_CODE (x) == CONST_DOUBLE)
8849 if (GET_CODE (x) == UNSPEC
8850 && (XINT (x, 1) == UNSPEC_PIC
8851 || XINT (x, 1) == UNSPEC_GOT
8852 || XINT (x, 1) == UNSPEC_GOTOFF
8853 || XINT (x, 1) == UNSPEC_GOTPLT
8854 || XINT (x, 1) == UNSPEC_GOTTPOFF
8855 || XINT (x, 1) == UNSPEC_DTPOFF
8856 || XINT (x, 1) == UNSPEC_PLT))
8859 fmt = GET_RTX_FORMAT (GET_CODE (x));
8860 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8866 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8867 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
8870 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
8877 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
8878 @GOTOFF in `reg'. */
8880 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
8883 if (tls_symbolic_operand (orig, Pmode))
8886 if (GET_CODE (orig) == LABEL_REF
8887 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
8890 reg = gen_reg_rtx (Pmode);
8892 emit_insn (gen_symGOTOFF2reg (reg, orig));
8895 else if (GET_CODE (orig) == SYMBOL_REF)
8898 reg = gen_reg_rtx (Pmode);
8900 emit_insn (gen_symGOT2reg (reg, orig));
8906 /* Mark the use of a constant in the literal table. If the constant
8907 has multiple labels, make it unique. */
8909 mark_constant_pool_use (rtx x)
8911 rtx insn, lab, pattern;
8916 switch (GET_CODE (x))
8926 /* Get the first label in the list of labels for the same constant
8927 and delete another labels in the list. */
8929 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
8931 if (GET_CODE (insn) != CODE_LABEL
8932 || LABEL_REFS (insn) != NEXT_INSN (insn))
8937 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
8938 INSN_DELETED_P (insn) = 1;
8940 /* Mark constants in a window. */
8941 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
8943 if (GET_CODE (insn) != INSN)
8946 pattern = PATTERN (insn);
8947 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
8950 switch (XINT (pattern, 1))
8952 case UNSPECV_CONST2:
8953 case UNSPECV_CONST4:
8954 case UNSPECV_CONST8:
8955 XVECEXP (pattern, 0, 1) = const1_rtx;
8957 case UNSPECV_WINDOW_END:
8958 if (XVECEXP (pattern, 0, 0) == x)
8961 case UNSPECV_CONST_END:
8971 /* Return true if it's possible to redirect BRANCH1 to the destination
8972 of an unconditional jump BRANCH2. We only want to do this if the
8973 resulting branch will have a short displacement. */
8975 sh_can_redirect_branch (rtx branch1, rtx branch2)
8977 if (flag_expensive_optimizations && simplejump_p (branch2))
8979 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
8983 for (distance = 0, insn = NEXT_INSN (branch1);
8984 insn && distance < 256;
8985 insn = PREV_INSN (insn))
8990 distance += get_attr_length (insn);
8992 for (distance = 0, insn = NEXT_INSN (branch1);
8993 insn && distance < 256;
8994 insn = NEXT_INSN (insn))
8999 distance += get_attr_length (insn);
9005 /* Return nonzero if register old_reg can be renamed to register new_reg. */
9007 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
9008 unsigned int new_reg)
9010 /* Interrupt functions can only use registers that have already been
9011 saved by the prologue, even if they would normally be
9014 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
9020 /* Function to update the integer COST
9021 based on the relationship between INSN that is dependent on
9022 DEP_INSN through the dependence LINK. The default is to make no
9023 adjustment to COST. This can be used for example to specify to
9024 the scheduler that an output- or anti-dependence does not incur
9025 the same cost as a data-dependence. The return value should be
9026 the new value for COST. */
9028 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
9034 /* On SHmedia, if the dependence is an anti-dependence or
9035 output-dependence, there is no cost. */
9036 if (REG_NOTE_KIND (link) != 0)
9038 /* However, dependencies between target register loads and
9039 uses of the register in a subsequent block that are separated
9040 by a conditional branch are not modelled - we have to do with
9041 the anti-dependency between the target register load and the
9042 conditional branch that ends the current block. */
9043 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
9044 && GET_CODE (PATTERN (dep_insn)) == SET
9045 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
9046 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
9047 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
9049 int orig_cost = cost;
9050 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
9051 rtx target = ((! note
9052 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
9053 ? insn : JUMP_LABEL (insn));
9054 /* On the likely path, the branch costs 1, on the unlikely path,
9058 target = next_active_insn (target);
9059 while (target && ! flow_dependent_p (target, dep_insn)
9061 /* If two branches are executed in immediate succession, with the
9062 first branch properly predicted, this causes a stall at the
9063 second branch, hence we won't need the target for the
9064 second branch for two cycles after the launch of the first
9066 if (cost > orig_cost - 2)
9067 cost = orig_cost - 2;
9073 else if (get_attr_is_mac_media (insn)
9074 && get_attr_is_mac_media (dep_insn))
9077 else if (! reload_completed
9078 && GET_CODE (PATTERN (insn)) == SET
9079 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
9080 && GET_CODE (PATTERN (dep_insn)) == SET
9081 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
9084 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
9085 that is needed at the target. */
9086 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
9087 && ! flow_dependent_p (insn, dep_insn))
9090 else if (REG_NOTE_KIND (link) == 0)
9092 enum attr_type type;
9095 if (recog_memoized (insn) < 0
9096 || recog_memoized (dep_insn) < 0)
9099 dep_set = single_set (dep_insn);
9101 /* The latency that we specify in the scheduling description refers
9102 to the actual output, not to an auto-increment register; for that,
9103 the latency is one. */
9104 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9106 rtx set = single_set (insn);
9109 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9110 && (!MEM_P (SET_DEST (set))
9111 || !reg_mentioned_p (SET_DEST (dep_set),
9112 XEXP (SET_DEST (set), 0))))
9115 /* The only input for a call that is timing-critical is the
9116 function's address. */
9117 if (GET_CODE (insn) == CALL_INSN)
9119 rtx call = PATTERN (insn);
9121 if (GET_CODE (call) == PARALLEL)
9122 call = XVECEXP (call, 0 ,0);
9123 if (GET_CODE (call) == SET)
9124 call = SET_SRC (call);
9125 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
9126 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9127 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9128 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9129 cost -= TARGET_SH4_300 ? 3 : 6;
9131 /* Likewise, the most timing critical input for an sfuncs call
9132 is the function address. However, sfuncs typically start
9133 using their arguments pretty quickly.
9134 Assume a four cycle delay for SH4 before they are needed.
9135 Cached ST40-300 calls are quicker, so assume only a one
9137 ??? Maybe we should encode the delays till input registers
9138 are needed by sfuncs into the sfunc call insn. */
9139 /* All sfunc calls are parallels with at least four components.
9140 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9141 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9142 && XVECLEN (PATTERN (insn), 0) >= 4
9143 && (reg = sfunc_uses_reg (insn)))
9145 if (! reg_set_p (reg, dep_insn))
9146 cost -= TARGET_SH4_300 ? 1 : 4;
9148 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9150 enum attr_type dep_type = get_attr_type (dep_insn);
9152 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9154 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9155 && (type = get_attr_type (insn)) != TYPE_CALL
9156 && type != TYPE_SFUNC)
9158 /* When the preceding instruction loads the shift amount of
9159 the following SHAD/SHLD, the latency of the load is increased
9161 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9162 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
9163 && reg_overlap_mentioned_p (SET_DEST (dep_set),
9164 XEXP (SET_SRC (single_set (insn)),
9167 /* When an LS group instruction with a latency of less than
9168 3 cycles is followed by a double-precision floating-point
9169 instruction, FIPR, or FTRV, the latency of the first
9170 instruction is increased to 3 cycles. */
9172 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9173 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9175 /* The lsw register of a double-precision computation is ready one
9177 else if (reload_completed
9178 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9179 && (use_pat = single_set (insn))
9180 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9184 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9185 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9188 else if (TARGET_SH4_300)
9190 /* Stores need their input register two cycles later. */
9191 if (dep_set && cost >= 1
9192 && ((type = get_attr_type (insn)) == TYPE_STORE
9193 || type == TYPE_PSTORE
9194 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9196 rtx set = single_set (insn);
9198 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9199 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9202 /* But don't reduce the cost below 1 if the address depends
9203 on a side effect of dep_insn. */
9205 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9211 /* An anti-dependence penalty of two applies if the first insn is a double
9212 precision fadd / fsub / fmul. */
9213 else if (!TARGET_SH4_300
9214 && REG_NOTE_KIND (link) == REG_DEP_ANTI
9215 && recog_memoized (dep_insn) >= 0
9216 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9217 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9218 /* A lot of alleged anti-flow dependences are fake,
9219 so check this one is real. */
9220 && flow_dependent_p (dep_insn, insn))
9226 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9227 if DEP_INSN is anti-flow dependent on INSN. */
9229 flow_dependent_p (rtx insn, rtx dep_insn)
9231 rtx tmp = PATTERN (insn);
9233 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9234 return tmp == NULL_RTX;
9237 /* A helper function for flow_dependent_p called through note_stores. */
9239 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9241 rtx * pinsn = (rtx *) data;
9243 if (*pinsn && reg_referenced_p (x, *pinsn))
9247 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9248 'special function' patterns (type sfunc) that clobber pr, but that
9249 do not look like function calls to leaf_function_p. Hence we must
9250 do this extra check. */
9254 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9257 /* Return where to allocate pseudo for a given hard register initial
9260 sh_allocate_initial_value (rtx hard_reg)
9264 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
9266 if (current_function_is_leaf
9267 && ! sh_pr_n_sets ()
9268 && ! (TARGET_SHCOMPACT
9269 && ((crtl->args.info.call_cookie
9270 & ~ CALL_COOKIE_RET_TRAMP (1))
9271 || crtl->saves_all_registers)))
9274 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
9282 /* This function returns "2" to indicate dual issue for the SH4
9283 processor. To be used by the DFA pipeline description. */
9285 sh_issue_rate (void)
9287 if (TARGET_SUPERSCALAR)
9293 /* Functions for ready queue reordering for sched1. */
9295 /* Get weight for mode for a set x. */
9297 find_set_regmode_weight (rtx x, enum machine_mode mode)
9299 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9301 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9303 if (GET_CODE (SET_DEST (x)) == REG)
9305 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9315 /* Get regmode weight for insn. */
9317 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
9319 short reg_weight = 0;
9322 /* Increment weight for each register born here. */
9324 reg_weight += find_set_regmode_weight (x, mode);
9325 if (GET_CODE (x) == PARALLEL)
9328 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9330 x = XVECEXP (PATTERN (insn), 0, j);
9331 reg_weight += find_set_regmode_weight (x, mode);
9334 /* Decrement weight for each register that dies here. */
9335 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9337 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9339 rtx note = XEXP (x, 0);
9340 if (GET_CODE (note) == REG && GET_MODE (note) == mode)
9347 /* Calculate regmode weights for all insns of a basic block. */
9349 find_regmode_weight (basic_block b, enum machine_mode mode)
9351 rtx insn, next_tail, head, tail;
9353 get_ebb_head_tail (b, b, &head, &tail);
9354 next_tail = NEXT_INSN (tail);
9356 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9358 /* Handle register life information. */
9363 INSN_REGMODE_WEIGHT (insn, mode) =
9364 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
9365 else if (mode == SImode)
9366 INSN_REGMODE_WEIGHT (insn, mode) =
9367 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
9371 /* Comparison function for ready queue sorting. */
9373 rank_for_reorder (const void *x, const void *y)
9375 rtx tmp = *(const rtx *) y;
9376 rtx tmp2 = *(const rtx *) x;
9378 /* The insn in a schedule group should be issued the first. */
9379 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
9380 return SCHED_GROUP_P (tmp2) ? 1 : -1;
9382 /* If insns are equally good, sort by INSN_LUID (original insn order), This
9383 minimizes instruction movement, thus minimizing sched's effect on
9384 register pressure. */
9385 return INSN_LUID (tmp) - INSN_LUID (tmp2);
9388 /* Resort the array A in which only element at index N may be out of order. */
9390 swap_reorder (rtx *a, int n)
9392 rtx insn = a[n - 1];
9395 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
9403 #define SCHED_REORDER(READY, N_READY) \
9406 if ((N_READY) == 2) \
9407 swap_reorder (READY, N_READY); \
9408 else if ((N_READY) > 2) \
9409 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
9413 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
9416 ready_reorder (rtx *ready, int nready)
9418 SCHED_REORDER (ready, nready);
9421 /* Count life regions of r0 for a block. */
9423 find_r0_life_regions (basic_block b)
9432 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
9445 r0_reg = gen_rtx_REG (SImode, R0_REG);
9450 if (find_regno_note (insn, REG_DEAD, R0_REG))
9456 && (pset = single_set (insn))
9457 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
9458 && !find_regno_note (insn, REG_UNUSED, R0_REG))
9466 insn = NEXT_INSN (insn);
9471 /* Calculate regmode weights for all insns of all basic block. */
9473 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
9474 int verbose ATTRIBUTE_UNUSED,
9479 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
9480 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
9481 r0_life_regions = 0;
9483 FOR_EACH_BB_REVERSE (b)
9485 find_regmode_weight (b, SImode);
9486 find_regmode_weight (b, SFmode);
9487 if (!reload_completed)
9488 r0_life_regions += find_r0_life_regions (b);
9491 CURR_REGMODE_PRESSURE (SImode) = 0;
9492 CURR_REGMODE_PRESSURE (SFmode) = 0;
9498 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
9499 int verbose ATTRIBUTE_UNUSED)
9501 if (regmode_weight[0])
9503 free (regmode_weight[0]);
9504 regmode_weight[0] = NULL;
9506 if (regmode_weight[1])
9508 free (regmode_weight[1]);
9509 regmode_weight[1] = NULL;
9513 /* The scalar modes supported differs from the default version in TImode
9514 for 32-bit SHMEDIA. */
9516 sh_scalar_mode_supported_p (enum machine_mode mode)
9518 if (TARGET_SHMEDIA32 && mode == TImode)
9521 return default_scalar_mode_supported_p (mode);
9524 /* Cache the can_issue_more so that we can return it from reorder2. Also,
9525 keep count of register pressures on SImode and SFmode. */
9527 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
9528 int sched_verbose ATTRIBUTE_UNUSED,
9532 if (GET_CODE (PATTERN (insn)) != USE
9533 && GET_CODE (PATTERN (insn)) != CLOBBER)
9534 cached_can_issue_more = can_issue_more - 1;
9536 cached_can_issue_more = can_issue_more;
9538 if (reload_completed)
9539 return cached_can_issue_more;
9541 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
9542 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
9544 return cached_can_issue_more;
9548 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
9549 int verbose ATTRIBUTE_UNUSED,
9550 int veclen ATTRIBUTE_UNUSED)
9552 CURR_REGMODE_PRESSURE (SImode) = 0;
9553 CURR_REGMODE_PRESSURE (SFmode) = 0;
9556 /* Some magic numbers. */
9557 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9558 functions that already have high pressure on r0. */
9559 #define R0_MAX_LIFE_REGIONS 2
9560 /* Register Pressure thresholds for SImode and SFmode registers. */
9561 #define SIMODE_MAX_WEIGHT 5
9562 #define SFMODE_MAX_WEIGHT 10
9564 /* Return true if the pressure is high for MODE. */
9566 high_pressure (enum machine_mode mode)
9568 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9569 functions that already have high pressure on r0. */
9570 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
9574 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
9576 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
9579 /* Reorder ready queue if register pressure is high. */
9581 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
9582 int sched_verbose ATTRIBUTE_UNUSED,
9585 int clock_var ATTRIBUTE_UNUSED)
9587 if (reload_completed)
9588 return sh_issue_rate ();
9590 if (high_pressure (SFmode) || high_pressure (SImode))
9592 ready_reorder (ready, *n_readyp);
9595 return sh_issue_rate ();
9598 /* Skip cycles if the current register pressure is high. */
9600 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
9601 int sched_verbose ATTRIBUTE_UNUSED,
9602 rtx *ready ATTRIBUTE_UNUSED,
9603 int *n_readyp ATTRIBUTE_UNUSED,
9604 int clock_var ATTRIBUTE_UNUSED)
9606 if (reload_completed)
9607 return cached_can_issue_more;
9609 if (high_pressure(SFmode) || high_pressure (SImode))
9612 return cached_can_issue_more;
9615 /* Skip cycles without sorting the ready queue. This will move insn from
9616 Q->R. If this is the last cycle we are skipping; allow sorting of ready
9617 queue by sh_reorder. */
9619 /* Generally, skipping these many cycles are sufficient for all insns to move
9624 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
9625 int sched_verbose ATTRIBUTE_UNUSED,
9626 rtx insn ATTRIBUTE_UNUSED,
9631 if (reload_completed)
9636 if ((clock_var - last_clock_var) < MAX_SKIPS)
9641 /* If this is the last cycle we are skipping, allow reordering of R. */
9642 if ((clock_var - last_clock_var) == MAX_SKIPS)
9654 /* SHmedia requires registers for branches, so we can't generate new
9655 branches past reload. */
9657 sh_cannot_modify_jumps_p (void)
9659 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
9663 sh_target_reg_class (void)
9665 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
9669 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
9676 if (! shmedia_space_reserved_for_target_registers)
9678 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
9680 if (calc_live_regs (&dummy) >= 6 * 8)
9686 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
9688 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
9692 On the SH1..SH4, the trampoline looks like
9693 2 0002 D202 mov.l l2,r2
9694 1 0000 D301 mov.l l1,r3
9697 5 0008 00000000 l1: .long area
9698 6 000c 00000000 l2: .long function
9700 SH5 (compact) uses r1 instead of r3 for the static chain. */
9703 /* Emit RTL insns to initialize the variable parts of a trampoline.
9704 FNADDR is an RTX for the address of the function's pure code.
9705 CXT is an RTX for the static chain value for the function. */
9708 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
9710 rtx tramp_mem = gen_frame_mem (BLKmode, tramp);
9712 if (TARGET_SHMEDIA64)
9717 rtx movi1 = GEN_INT (0xcc000010);
9718 rtx shori1 = GEN_INT (0xc8000010);
9721 /* The following trampoline works within a +- 128 KB range for cxt:
9722 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
9723 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
9724 gettr tr1,r1; blink tr0,r63 */
9725 /* Address rounding makes it hard to compute the exact bounds of the
9726 offset for this trampoline, but we have a rather generous offset
9727 range, so frame_offset should do fine as an upper bound. */
9728 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
9730 /* ??? could optimize this trampoline initialization
9731 by writing DImode words with two insns each. */
9732 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
9733 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
9734 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
9735 insn = gen_rtx_AND (DImode, insn, mask);
9736 /* Or in ptb/u .,tr1 pattern */
9737 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
9738 insn = force_operand (insn, NULL_RTX);
9739 insn = gen_lowpart (SImode, insn);
9740 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
9741 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
9742 insn = gen_rtx_AND (DImode, insn, mask);
9743 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
9744 insn = gen_lowpart (SImode, insn);
9745 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
9746 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
9747 insn = gen_rtx_AND (DImode, insn, mask);
9748 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9749 insn = gen_lowpart (SImode, insn);
9750 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
9751 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
9752 insn = gen_rtx_AND (DImode, insn, mask);
9753 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9754 insn = gen_lowpart (SImode, insn);
9755 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
9756 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
9757 insn = gen_rtx_AND (DImode, insn, mask);
9758 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9759 insn = gen_lowpart (SImode, insn);
9760 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
9761 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
9762 GEN_INT (0x6bf10600));
9763 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
9764 GEN_INT (0x4415fc10));
9765 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
9766 GEN_INT (0x4401fff0));
9767 emit_insn (gen_ic_invalidate_line (tramp));
9770 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
9771 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
9773 tramp_templ = gen_datalabel_ref (tramp_templ);
9775 src = gen_const_mem (BLKmode, tramp_templ);
9776 set_mem_align (dst, 256);
9777 set_mem_align (src, 64);
9778 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
9780 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
9781 emit_move_insn (adjust_address (tramp_mem, Pmode,
9782 fixed_len + GET_MODE_SIZE (Pmode)),
9784 emit_insn (gen_ic_invalidate_line (tramp));
9787 else if (TARGET_SHMEDIA)
9789 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
9790 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
9791 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
9792 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
9793 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
9794 rotated 10 right, and higher 16 bit of every 32 selected. */
9796 = force_reg (V2HImode, (simplify_gen_subreg
9797 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
9798 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
9799 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
9801 tramp = force_reg (Pmode, tramp);
9802 fnaddr = force_reg (SImode, fnaddr);
9803 cxt = force_reg (SImode, cxt);
9804 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
9805 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
9807 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
9808 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
9809 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
9810 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
9811 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
9812 gen_rtx_SUBREG (V2HImode, cxt, 0),
9814 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
9815 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
9816 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
9817 if (TARGET_LITTLE_ENDIAN)
9819 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
9820 emit_insn (gen_mextr4 (quad2, cxtload, blink));
9824 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
9825 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
9827 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
9828 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
9829 emit_insn (gen_ic_invalidate_line (tramp));
9832 else if (TARGET_SHCOMPACT)
9834 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
9837 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
9838 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
9840 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
9841 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
9843 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
9844 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
9847 if (!TARGET_INLINE_IC_INVALIDATE
9848 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
9849 emit_library_call (function_symbol (NULL, "__ic_invalidate",
9851 0, VOIDmode, 1, tramp, SImode);
9853 emit_insn (gen_ic_invalidate_line (tramp));
9857 /* FIXME: This is overly conservative. A SHcompact function that
9858 receives arguments ``by reference'' will have them stored in its
9859 own stack frame, so it must not pass pointers or references to
9860 these arguments to other functions by means of sibling calls. */
9861 /* If PIC, we cannot make sibling calls to global functions
9862 because the PLT requires r12 to be live. */
9864 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
9867 && (! TARGET_SHCOMPACT
9868 || crtl->args.info.stack_regs == 0)
9869 && ! sh_cfun_interrupt_handler_p ()
9871 || (decl && ! TREE_PUBLIC (decl))
9872 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
9875 /* Machine specific built-in functions. */
9877 struct builtin_description
9879 const enum insn_code icode;
9880 const char *const name;
9884 /* describe number and signedness of arguments; arg[0] == result
9885 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
9886 /* 9: 64-bit pointer, 10: 32-bit pointer */
9887 static const char signature_args[][4] =
9889 #define SH_BLTIN_V2SI2 0
9891 #define SH_BLTIN_V4HI2 1
9893 #define SH_BLTIN_V2SI3 2
9895 #define SH_BLTIN_V4HI3 3
9897 #define SH_BLTIN_V8QI3 4
9899 #define SH_BLTIN_MAC_HISI 5
9901 #define SH_BLTIN_SH_HI 6
9903 #define SH_BLTIN_SH_SI 7
9905 #define SH_BLTIN_V4HI2V2SI 8
9907 #define SH_BLTIN_V4HI2V8QI 9
9909 #define SH_BLTIN_SISF 10
9911 #define SH_BLTIN_LDUA_L 11
9913 #define SH_BLTIN_LDUA_Q 12
9915 #define SH_BLTIN_STUA_L 13
9917 #define SH_BLTIN_STUA_Q 14
9919 #define SH_BLTIN_LDUA_L64 15
9921 #define SH_BLTIN_LDUA_Q64 16
9923 #define SH_BLTIN_STUA_L64 17
9925 #define SH_BLTIN_STUA_Q64 18
9927 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
9928 #define SH_BLTIN_2 19
9929 #define SH_BLTIN_SU 19
9931 #define SH_BLTIN_3 20
9932 #define SH_BLTIN_SUS 20
9934 #define SH_BLTIN_PSSV 21
9936 #define SH_BLTIN_XXUU 22
9937 #define SH_BLTIN_UUUU 22
9939 #define SH_BLTIN_PV 23
9942 /* mcmv: operands considered unsigned. */
9943 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
9944 /* mperm: control value considered unsigned int. */
9945 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
9946 /* mshards_q: returns signed short. */
9947 /* nsb: takes long long arg, returns unsigned char. */
9948 static const struct builtin_description bdesc[] =
9950 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
9951 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
9952 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
9953 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
9954 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
9955 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
9956 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
9957 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
9958 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
9959 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
9960 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
9961 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
9962 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
9963 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
9964 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
9965 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
9966 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
9967 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
9968 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 },
9969 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 },
9970 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 },
9971 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 },
9972 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 },
9973 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 },
9974 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 },
9975 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
9976 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
9977 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
9978 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
9979 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
9980 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
9981 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
9982 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
9983 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
9984 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
9985 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
9986 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
9987 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
9988 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
9989 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
9990 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
9991 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
9992 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
9993 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
9994 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
9995 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
9996 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
9997 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
9998 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
9999 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
10000 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
10001 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
10002 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
10003 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
10004 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
10005 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
10006 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
10007 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
10008 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
10009 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
10010 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
10011 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 },
10012 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 },
10013 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 },
10014 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
10015 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
10016 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
10017 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
10018 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
10019 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
10020 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
10021 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
10022 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
10023 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 },
10024 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 },
10025 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 },
10026 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 },
10027 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 },
10028 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 },
10029 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 },
10030 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 },
10031 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
10032 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
10033 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
10037 sh_media_init_builtins (void)
10039 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
10040 const struct builtin_description *d;
10042 memset (shared, 0, sizeof shared);
10043 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
10045 tree type, arg_type = 0;
10046 int signature = d->signature;
10049 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
10050 type = shared[signature];
10053 int has_result = signature_args[signature][0] != 0;
10055 if ((signature_args[signature][1] & 8)
10056 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
10057 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
10059 if (! TARGET_FPU_ANY
10060 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
10062 type = void_list_node;
10065 int arg = signature_args[signature][i];
10066 int opno = i - 1 + has_result;
10069 arg_type = ptr_type_node;
10071 arg_type = (*lang_hooks.types.type_for_mode)
10072 (insn_data[d->icode].operand[opno].mode,
10077 arg_type = void_type_node;
10080 type = tree_cons (NULL_TREE, arg_type, type);
10082 type = build_function_type (arg_type, type);
10083 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10084 shared[signature] = type;
10086 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10091 /* Implements target hook vector_mode_supported_p. */
10093 sh_vector_mode_supported_p (enum machine_mode mode)
10096 && ((mode == V2SFmode)
10097 || (mode == V4SFmode)
10098 || (mode == V16SFmode)))
10101 else if (TARGET_SHMEDIA
10102 && ((mode == V8QImode)
10103 || (mode == V2HImode)
10104 || (mode == V4HImode)
10105 || (mode == V2SImode)))
10111 /* Implements target hook dwarf_calling_convention. Return an enum
10112 of dwarf_calling_convention. */
10114 sh_dwarf_calling_convention (const_tree func)
10116 if (sh_attr_renesas_p (func))
10117 return DW_CC_GNU_renesas_sh;
10119 return DW_CC_normal;
10123 sh_init_builtins (void)
10125 if (TARGET_SHMEDIA)
10126 sh_media_init_builtins ();
10129 /* Expand an expression EXP that calls a built-in function,
10130 with result going to TARGET if that's convenient
10131 (and in mode MODE if that's convenient).
10132 SUBTARGET may be used as the target for computing one of EXP's operands.
10133 IGNORE is nonzero if the value is to be ignored. */
10136 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10137 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
10139 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10140 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10141 const struct builtin_description *d = &bdesc[fcode];
10142 enum insn_code icode = d->icode;
10143 int signature = d->signature;
10144 enum machine_mode tmode = VOIDmode;
10149 if (signature_args[signature][0])
10154 tmode = insn_data[icode].operand[0].mode;
10156 || GET_MODE (target) != tmode
10157 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10158 target = gen_reg_rtx (tmode);
10159 op[nop++] = target;
10164 for (i = 1; i <= 3; i++, nop++)
10167 enum machine_mode opmode, argmode;
10170 if (! signature_args[signature][i])
10172 arg = CALL_EXPR_ARG (exp, i - 1);
10173 if (arg == error_mark_node)
10175 if (signature_args[signature][i] & 8)
10178 optype = ptr_type_node;
10182 opmode = insn_data[icode].operand[nop].mode;
10183 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10185 argmode = TYPE_MODE (TREE_TYPE (arg));
10186 if (argmode != opmode)
10187 arg = build1 (NOP_EXPR, optype, arg);
10188 op[nop] = expand_expr (arg, NULL_RTX, opmode, 0);
10189 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10190 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10196 pat = (*insn_data[d->icode].genfun) (op[0]);
10199 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10202 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10205 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10208 gcc_unreachable ();
10217 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
10219 rtx sel0 = const0_rtx;
10220 rtx sel1 = const1_rtx;
10221 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
10222 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
10224 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
10225 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
10229 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
10231 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
10233 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
10234 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
10237 /* Return the class of registers for which a mode change from FROM to TO
10240 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
10241 enum reg_class rclass)
10243 /* We want to enable the use of SUBREGs as a means to
10244 VEC_SELECT a single element of a vector. */
10245 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
10246 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
10248 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10250 if (TARGET_LITTLE_ENDIAN)
10252 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
10253 return reg_classes_intersect_p (DF_REGS, rclass);
10257 if (GET_MODE_SIZE (from) < 8)
10258 return reg_classes_intersect_p (DF_HI_REGS, rclass);
10265 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10266 that label is used. */
10269 sh_mark_label (rtx address, int nuses)
10271 if (GOTOFF_P (address))
10273 /* Extract the label or symbol. */
10274 address = XEXP (address, 0);
10275 if (GET_CODE (address) == PLUS)
10276 address = XEXP (address, 0);
10277 address = XVECEXP (address, 0, 0);
10279 if (GET_CODE (address) == LABEL_REF
10280 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
10281 LABEL_NUSES (XEXP (address, 0)) += nuses;
10284 /* Compute extra cost of moving data between one register class
10287 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10288 uses this information. Hence, the general register <-> floating point
10289 register information here is not used for SFmode. */
10292 sh_register_move_cost (enum machine_mode mode,
10293 enum reg_class srcclass, enum reg_class dstclass)
10295 if (dstclass == T_REGS || dstclass == PR_REGS)
10298 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
10301 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
10302 && REGCLASS_HAS_FP_REG (srcclass)
10303 && REGCLASS_HAS_FP_REG (dstclass))
10306 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
10307 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
10309 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
10310 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
10313 if ((REGCLASS_HAS_FP_REG (dstclass)
10314 && REGCLASS_HAS_GENERAL_REG (srcclass))
10315 || (REGCLASS_HAS_GENERAL_REG (dstclass)
10316 && REGCLASS_HAS_FP_REG (srcclass)))
10317 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
10318 * ((GET_MODE_SIZE (mode) + 7) / 8U));
10320 if ((dstclass == FPUL_REGS
10321 && REGCLASS_HAS_GENERAL_REG (srcclass))
10322 || (srcclass == FPUL_REGS
10323 && REGCLASS_HAS_GENERAL_REG (dstclass)))
10326 if ((dstclass == FPUL_REGS
10327 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
10328 || (srcclass == FPUL_REGS
10329 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
10332 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10333 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10336 /* ??? ptabs faults on (value & 0x3) == 0x3 */
10338 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
10340 if (sh_gettrcost >= 0)
10341 return sh_gettrcost;
10342 else if (!TARGET_PT_FIXED)
10346 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10347 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10352 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
10353 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
10354 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
10356 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
10359 static rtx emit_load_ptr (rtx, rtx);
10362 emit_load_ptr (rtx reg, rtx addr)
10364 rtx mem = gen_const_mem (ptr_mode, addr);
10366 if (Pmode != ptr_mode)
10367 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
10368 return emit_move_insn (reg, mem);
10372 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
10373 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10376 CUMULATIVE_ARGS cum;
10377 int structure_value_byref = 0;
10378 rtx this_rtx, this_value, sibcall, insns, funexp;
10379 tree funtype = TREE_TYPE (function);
10380 int simple_add = CONST_OK_FOR_ADD (delta);
10382 rtx scratch0, scratch1, scratch2;
10385 reload_completed = 1;
10386 epilogue_completed = 1;
10387 current_function_uses_only_leaf_regs = 1;
10389 emit_note (NOTE_INSN_PROLOGUE_END);
10391 /* Find the "this" pointer. We have such a wide range of ABIs for the
10392 SH that it's best to do this completely machine independently.
10393 "this" is passed as first argument, unless a structure return pointer
10394 comes first, in which case "this" comes second. */
10395 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
10396 #ifndef PCC_STATIC_STRUCT_RETURN
10397 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10398 structure_value_byref = 1;
10399 #endif /* not PCC_STATIC_STRUCT_RETURN */
10400 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
10402 tree ptype = build_pointer_type (TREE_TYPE (funtype));
10404 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
10406 this_rtx = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
10408 /* For SHcompact, we only have r0 for a scratch register: r1 is the
10409 static chain pointer (even if you can't have nested virtual functions
10410 right now, someone might implement them sometime), and the rest of the
10411 registers are used for argument passing, are callee-saved, or reserved. */
10412 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
10413 -ffixed-reg has been used. */
10414 if (! call_used_regs[0] || fixed_regs[0])
10415 error ("r0 needs to be available as a call-clobbered register");
10416 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
10419 if (call_used_regs[1] && ! fixed_regs[1])
10420 scratch1 = gen_rtx_REG (ptr_mode, 1);
10421 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
10422 pointing where to return struct values. */
10423 if (call_used_regs[3] && ! fixed_regs[3])
10424 scratch2 = gen_rtx_REG (Pmode, 3);
10426 else if (TARGET_SHMEDIA)
10428 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
10429 if (i != REGNO (scratch0) &&
10430 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
10432 scratch1 = gen_rtx_REG (ptr_mode, i);
10435 if (scratch1 == scratch0)
10436 error ("Need a second call-clobbered general purpose register");
10437 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
10438 if (call_used_regs[i] && ! fixed_regs[i])
10440 scratch2 = gen_rtx_REG (Pmode, i);
10443 if (scratch2 == scratch0)
10444 error ("Need a call-clobbered target register");
10447 this_value = plus_constant (this_rtx, delta);
10449 && (simple_add || scratch0 != scratch1)
10450 && strict_memory_address_p (ptr_mode, this_value))
10452 emit_load_ptr (scratch0, this_value);
10457 ; /* Do nothing. */
10458 else if (simple_add)
10459 emit_move_insn (this_rtx, this_value);
10462 emit_move_insn (scratch1, GEN_INT (delta));
10463 emit_insn (gen_add2_insn (this_rtx, scratch1));
10471 emit_load_ptr (scratch0, this_rtx);
10473 offset_addr = plus_constant (scratch0, vcall_offset);
10474 if (strict_memory_address_p (ptr_mode, offset_addr))
10475 ; /* Do nothing. */
10476 else if (! TARGET_SH5 && scratch0 != scratch1)
10478 /* scratch0 != scratch1, and we have indexed loads. Get better
10479 schedule by loading the offset into r1 and using an indexed
10480 load - then the load of r1 can issue before the load from
10481 (this_rtx + delta) finishes. */
10482 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10483 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
10485 else if (CONST_OK_FOR_ADD (vcall_offset))
10487 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
10488 offset_addr = scratch0;
10490 else if (scratch0 != scratch1)
10492 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10493 emit_insn (gen_add2_insn (scratch0, scratch1));
10494 offset_addr = scratch0;
10497 gcc_unreachable (); /* FIXME */
10498 emit_load_ptr (scratch0, offset_addr);
10500 if (Pmode != ptr_mode)
10501 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
10502 emit_insn (gen_add2_insn (this_rtx, scratch0));
10505 /* Generate a tail call to the target function. */
10506 if (! TREE_USED (function))
10508 assemble_external (function);
10509 TREE_USED (function) = 1;
10511 funexp = XEXP (DECL_RTL (function), 0);
10512 /* If the function is overridden, so is the thunk, hence we don't
10513 need GOT addressing even if this is a public symbol. */
10515 if (TARGET_SH1 && ! flag_weak)
10516 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
10519 if (TARGET_SH2 && flag_pic)
10521 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
10522 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
10526 if (TARGET_SHMEDIA && flag_pic)
10528 funexp = gen_sym2PIC (funexp);
10529 PUT_MODE (funexp, Pmode);
10531 emit_move_insn (scratch2, funexp);
10532 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
10533 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
10535 sibcall = emit_call_insn (sibcall);
10536 SIBLING_CALL_P (sibcall) = 1;
10537 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
10540 /* Run just enough of rest_of_compilation to do scheduling and get
10541 the insns emitted. Note that use_thunk calls
10542 assemble_start_function and assemble_end_function. */
10544 insn_locators_alloc ();
10545 insns = get_insns ();
10550 /* Initialize the bitmap obstacks. */
10551 bitmap_obstack_initialize (NULL);
10552 bitmap_obstack_initialize (®_obstack);
10555 rtl_register_cfg_hooks ();
10556 init_rtl_bb_info (ENTRY_BLOCK_PTR);
10557 init_rtl_bb_info (EXIT_BLOCK_PTR);
10558 ENTRY_BLOCK_PTR->flags |= BB_RTL;
10559 EXIT_BLOCK_PTR->flags |= BB_RTL;
10560 find_basic_blocks (insns);
10562 if (flag_schedule_insns_after_reload)
10564 life_analysis (PROP_FINAL);
10566 split_all_insns (1);
10570 /* We must split jmp insn in PIC case. */
10572 split_all_insns_noflow ();
10579 split_all_insns_noflow ();
10585 if (optimize > 0 && flag_delayed_branch)
10586 dbr_schedule (insns);
10588 shorten_branches (insns);
10589 final_start_function (insns, file, 1);
10590 final (insns, file, 1);
10591 final_end_function ();
10592 free_after_compilation (cfun);
10594 reload_completed = 0;
10595 epilogue_completed = 0;
10599 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
10603 /* If this is not an ordinary function, the name usually comes from a
10604 string literal or an sprintf buffer. Make sure we use the same
10605 string consistently, so that cse will be able to unify address loads. */
10606 if (kind != FUNCTION_ORDINARY)
10607 name = IDENTIFIER_POINTER (get_identifier (name));
10608 sym = gen_rtx_SYMBOL_REF (Pmode, name);
10609 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
10613 case FUNCTION_ORDINARY:
10617 rtx reg = target ? target : gen_reg_rtx (Pmode);
10619 emit_insn (gen_symGOT2reg (reg, sym));
10625 /* ??? To allow cse to work, we use GOTOFF relocations.
10626 we could add combiner patterns to transform this into
10627 straight pc-relative calls with sym2PIC / bsrf when
10628 label load and function call are still 1:1 and in the
10629 same basic block during combine. */
10630 rtx reg = target ? target : gen_reg_rtx (Pmode);
10632 emit_insn (gen_symGOTOFF2reg (reg, sym));
10637 if (target && sym != target)
10639 emit_move_insn (target, sym);
10645 /* Find the number of a general purpose register in S. */
10647 scavenge_reg (HARD_REG_SET *s)
10650 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
10651 if (TEST_HARD_REG_BIT (*s, r))
10657 sh_get_pr_initial_val (void)
10661 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
10662 PR register on SHcompact, because it might be clobbered by the prologue.
10663 We check first if that is known to be the case. */
10664 if (TARGET_SHCOMPACT
10665 && ((crtl->args.info.call_cookie
10666 & ~ CALL_COOKIE_RET_TRAMP (1))
10667 || crtl->saves_all_registers))
10668 return gen_frame_mem (SImode, return_address_pointer_rtx);
10670 /* If we haven't finished rtl generation, there might be a nonlocal label
10671 that we haven't seen yet.
10672 ??? get_hard_reg_initial_val fails if it is called after register
10673 allocation has started, unless it has been called before for the
10674 same register. And even then, we end in trouble if we didn't use
10675 the register in the same basic block before. So call
10676 get_hard_reg_initial_val now and wrap it in an unspec if we might
10677 need to replace it. */
10678 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
10679 combine can put the pseudo returned by get_hard_reg_initial_val into
10680 instructions that need a general purpose registers, which will fail to
10681 be recognized when the pseudo becomes allocated to PR. */
10683 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
10685 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
10690 sh_expand_t_scc (enum rtx_code code, rtx target)
10692 rtx result = target;
10695 if (GET_CODE (sh_compare_op0) != REG || REGNO (sh_compare_op0) != T_REG
10696 || GET_CODE (sh_compare_op1) != CONST_INT)
10698 if (GET_CODE (result) != REG)
10699 result = gen_reg_rtx (SImode);
10700 val = INTVAL (sh_compare_op1);
10701 if ((code == EQ && val == 1) || (code == NE && val == 0))
10702 emit_insn (gen_movt (result));
10703 else if (TARGET_SH2A && ((code == EQ && val == 0)
10704 || (code == NE && val == 1)))
10705 emit_insn (gen_movrt (result));
10706 else if ((code == EQ && val == 0) || (code == NE && val == 1))
10708 emit_clobber (result);
10709 emit_insn (gen_subc (result, result, result));
10710 emit_insn (gen_addsi3 (result, result, const1_rtx));
10712 else if (code == EQ || code == NE)
10713 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
10716 if (result != target)
10717 emit_move_insn (target, result);
10721 /* INSN is an sfunc; return the rtx that describes the address used. */
10723 extract_sfunc_addr (rtx insn)
10725 rtx pattern, part = NULL_RTX;
10728 pattern = PATTERN (insn);
10729 len = XVECLEN (pattern, 0);
10730 for (i = 0; i < len; i++)
10732 part = XVECEXP (pattern, 0, i);
10733 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
10734 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
10735 return XEXP (part, 0);
10737 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
10738 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
10741 /* Verify that the register in use_sfunc_addr still agrees with the address
10742 used in the sfunc. This prevents fill_slots_from_thread from changing
10744 INSN is the use_sfunc_addr instruction, and REG is the register it
10747 check_use_sfunc_addr (rtx insn, rtx reg)
10749 /* Search for the sfunc. It should really come right after INSN. */
10750 while ((insn = NEXT_INSN (insn)))
10752 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN)
10754 if (! INSN_P (insn))
10757 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
10758 insn = XVECEXP (PATTERN (insn), 0, 0);
10759 if (GET_CODE (PATTERN (insn)) != PARALLEL
10760 || get_attr_type (insn) != TYPE_SFUNC)
10762 return rtx_equal_p (extract_sfunc_addr (insn), reg);
10764 gcc_unreachable ();
10767 /* This function returns a constant rtx that represents pi / 2**15 in
10768 SFmode. it's used to scale SFmode angles, in radians, to a
10769 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
10770 maps to 0x10000). */
10772 static GTY(()) rtx sh_fsca_sf2int_rtx;
10775 sh_fsca_sf2int (void)
10777 if (! sh_fsca_sf2int_rtx)
10779 REAL_VALUE_TYPE rv;
10781 real_from_string (&rv, "10430.378350470453");
10782 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
10785 return sh_fsca_sf2int_rtx;
10788 /* This function returns a constant rtx that represents pi / 2**15 in
10789 DFmode. it's used to scale DFmode angles, in radians, to a
10790 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
10791 maps to 0x10000). */
10793 static GTY(()) rtx sh_fsca_df2int_rtx;
10796 sh_fsca_df2int (void)
10798 if (! sh_fsca_df2int_rtx)
10800 REAL_VALUE_TYPE rv;
10802 real_from_string (&rv, "10430.378350470453");
10803 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
10806 return sh_fsca_df2int_rtx;
10809 /* This function returns a constant rtx that represents 2**15 / pi in
10810 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
10811 of a full circle back to a SFmode value, i.e., 0x10000 maps to
10814 static GTY(()) rtx sh_fsca_int2sf_rtx;
10817 sh_fsca_int2sf (void)
10819 if (! sh_fsca_int2sf_rtx)
10821 REAL_VALUE_TYPE rv;
10823 real_from_string (&rv, "9.587379924285257e-5");
10824 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
10827 return sh_fsca_int2sf_rtx;
10830 /* Initialize the CUMULATIVE_ARGS structure. */
10833 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
10835 rtx libname ATTRIBUTE_UNUSED,
10837 signed int n_named_args,
10838 enum machine_mode mode)
10840 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
10841 pcum->free_single_fp_reg = 0;
10842 pcum->stack_regs = 0;
10843 pcum->byref_regs = 0;
10845 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
10847 /* XXX - Should we check TARGET_HITACHI here ??? */
10848 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
10852 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
10853 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
10854 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
10855 pcum->arg_count [(int) SH_ARG_INT]
10856 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
10859 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
10860 && pcum->arg_count [(int) SH_ARG_INT] == 0
10861 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
10862 ? int_size_in_bytes (TREE_TYPE (fntype))
10863 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
10864 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
10865 == FIRST_RET_REG));
10869 pcum->arg_count [(int) SH_ARG_INT] = 0;
10870 pcum->prototype_p = FALSE;
10871 if (mode != VOIDmode)
10873 pcum->call_cookie =
10874 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
10875 && GET_MODE_SIZE (mode) > 4
10876 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
10878 /* If the default ABI is the Renesas ABI then all library
10879 calls must assume that the library will be using the
10880 Renesas ABI. So if the function would return its result
10881 in memory then we must force the address of this memory
10882 block onto the stack. Ideally we would like to call
10883 targetm.calls.return_in_memory() here but we do not have
10884 the TYPE or the FNDECL available so we synthesize the
10885 contents of that function as best we can. */
10887 (TARGET_DEFAULT & MASK_HITACHI)
10888 && (mode == BLKmode
10889 || (GET_MODE_SIZE (mode) > 4
10890 && !(mode == DFmode
10891 && TARGET_FPU_DOUBLE)));
10895 pcum->call_cookie = 0;
10896 pcum->force_mem = FALSE;
10901 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
10902 not enter into CONST_DOUBLE for the replace.
10904 Note that copying is not done so X must not be shared unless all copies
10905 are to be modified.
10907 This is like replace_rtx, except that we operate on N_REPLACEMENTS
10908 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
10909 replacements[n*2+1] - and that we take mode changes into account.
10911 If a replacement is ambiguous, return NULL_RTX.
10913 If MODIFY is zero, don't modify any rtl in place,
10914 just return zero or nonzero for failure / success. */
10917 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
10922 /* The following prevents loops occurrence when we change MEM in
10923 CONST_DOUBLE onto the same CONST_DOUBLE. */
10924 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
10927 for (i = n_replacements - 1; i >= 0 ; i--)
10928 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
10929 return replacements[i*2+1];
10931 /* Allow this function to make replacements in EXPR_LISTs. */
10935 if (GET_CODE (x) == SUBREG)
10937 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
10938 n_replacements, modify);
10940 if (GET_CODE (new_rtx) == CONST_INT)
10942 x = simplify_subreg (GET_MODE (x), new_rtx,
10943 GET_MODE (SUBREG_REG (x)),
10949 SUBREG_REG (x) = new_rtx;
10953 else if (GET_CODE (x) == REG)
10955 unsigned regno = REGNO (x);
10956 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
10957 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10958 rtx result = NULL_RTX;
10960 for (i = n_replacements - 1; i >= 0; i--)
10962 rtx from = replacements[i*2];
10963 rtx to = replacements[i*2+1];
10964 unsigned from_regno, from_nregs, to_regno, new_regno;
10966 if (GET_CODE (from) != REG)
10968 from_regno = REGNO (from);
10969 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
10970 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
10971 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
10973 if (regno < from_regno
10974 || regno + nregs > from_regno + nregs
10975 || GET_CODE (to) != REG
10978 to_regno = REGNO (to);
10979 if (to_regno < FIRST_PSEUDO_REGISTER)
10981 new_regno = regno + to_regno - from_regno;
10982 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
10985 result = gen_rtx_REG (GET_MODE (x), new_regno);
10987 else if (GET_MODE (x) <= GET_MODE (to))
10988 result = gen_lowpart_common (GET_MODE (x), to);
10990 result = gen_lowpart_SUBREG (GET_MODE (x), to);
10993 return result ? result : x;
10995 else if (GET_CODE (x) == ZERO_EXTEND)
10997 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
10998 n_replacements, modify);
11000 if (GET_CODE (new_rtx) == CONST_INT)
11002 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
11003 new_rtx, GET_MODE (XEXP (x, 0)));
11008 XEXP (x, 0) = new_rtx;
11013 fmt = GET_RTX_FORMAT (GET_CODE (x));
11014 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
11020 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
11021 n_replacements, modify);
11025 XEXP (x, i) = new_rtx;
11027 else if (fmt[i] == 'E')
11028 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11030 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
11031 n_replacements, modify);
11035 XVECEXP (x, i, j) = new_rtx;
11043 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
11045 enum rtx_code code = TRUNCATE;
11047 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
11049 rtx inner = XEXP (x, 0);
11050 enum machine_mode inner_mode = GET_MODE (inner);
11052 if (inner_mode == mode)
11054 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
11056 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
11057 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
11059 code = GET_CODE (x);
11063 return gen_rtx_fmt_e (code, mode, x);
11066 /* called via for_each_rtx after reload, to clean up truncates of
11067 registers that span multiple actual hard registers. */
11069 shmedia_cleanup_truncate (rtx *p, void *n_changes)
11073 if (GET_CODE (x) != TRUNCATE)
11076 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && GET_CODE (reg) == REG)
11078 enum machine_mode reg_mode = GET_MODE (reg);
11079 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
11080 subreg_lowpart_offset (DImode, reg_mode));
11081 *(int*) n_changes += 1;
11087 /* Load and store depend on the highpart of the address. However,
11088 set_attr_alternative does not give well-defined results before reload,
11089 so we must look at the rtl ourselves to see if any of the feeding
11090 registers is used in a memref. */
11092 /* Called by sh_contains_memref_p via for_each_rtx. */
11094 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
11096 return (GET_CODE (*loc) == MEM);
11099 /* Return nonzero iff INSN contains a MEM. */
11101 sh_contains_memref_p (rtx insn)
11103 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
11106 /* Return nonzero iff INSN loads a banked register. */
11108 sh_loads_bankedreg_p (rtx insn)
11110 if (GET_CODE (PATTERN (insn)) == SET)
11112 rtx op = SET_DEST (PATTERN(insn));
11113 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11120 /* FNADDR is the MEM expression from a call expander. Return an address
11121 to use in an SHmedia insn pattern. */
11123 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
11127 fnaddr = XEXP (fnaddr, 0);
11128 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
11129 if (flag_pic && is_sym)
11131 if (! SYMBOL_REF_LOCAL_P (fnaddr))
11133 rtx reg = gen_reg_rtx (Pmode);
11135 /* We must not use GOTPLT for sibcalls, because PIC_REG
11136 must be restored before the PLT code gets to run. */
11138 emit_insn (gen_symGOT2reg (reg, fnaddr));
11140 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
11145 fnaddr = gen_sym2PIC (fnaddr);
11146 PUT_MODE (fnaddr, Pmode);
11149 /* If ptabs might trap, make this visible to the rest of the compiler.
11150 We generally assume that symbols pertain to valid locations, but
11151 it is possible to generate invalid symbols with asm or linker tricks.
11152 In a list of functions where each returns its successor, an invalid
11153 symbol might denote an empty list. */
11154 if (!TARGET_PT_FIXED
11155 && (!is_sym || TARGET_INVALID_SYMBOLS)
11156 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
11158 rtx tr = gen_reg_rtx (PDImode);
11160 emit_insn (gen_ptabs (tr, fnaddr));
11163 else if (! target_reg_operand (fnaddr, Pmode))
11164 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
11169 sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
11170 enum machine_mode mode, secondary_reload_info *sri)
11174 if (REGCLASS_HAS_FP_REG (rclass)
11175 && ! TARGET_SHMEDIA
11176 && immediate_operand ((x), mode)
11177 && ! ((fp_zero_operand (x) || fp_one_operand (x))
11178 && mode == SFmode && fldi_ok ()))
11182 sri->icode = CODE_FOR_reload_insf__frn;
11185 sri->icode = CODE_FOR_reload_indf__frn;
11188 /* ??? If we knew that we are in the appropriate mode -
11189 single precision - we could use a reload pattern directly. */
11194 if (rclass == FPUL_REGS
11195 && ((GET_CODE (x) == REG
11196 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11197 || REGNO (x) == T_REG))
11198 || GET_CODE (x) == PLUS))
11199 return GENERAL_REGS;
11200 if (rclass == FPUL_REGS && immediate_operand (x, mode))
11202 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
11203 return GENERAL_REGS;
11204 else if (mode == SFmode)
11206 sri->icode = CODE_FOR_reload_insi__i_fpul;
11209 if (rclass == FPSCR_REGS
11210 && ((GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11211 || (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PLUS)))
11212 return GENERAL_REGS;
11213 if (REGCLASS_HAS_FP_REG (rclass)
11215 && immediate_operand (x, mode)
11216 && x != CONST0_RTX (GET_MODE (x))
11217 && GET_MODE (x) != V4SFmode)
11218 return GENERAL_REGS;
11219 if ((mode == QImode || mode == HImode)
11220 && TARGET_SHMEDIA && inqhi_operand (x, mode))
11222 sri->icode = ((mode == QImode)
11223 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
11226 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
11227 && (GET_CODE (x) == LABEL_REF || PIC_DIRECT_ADDR_P (x)))
11228 return TARGET_REGS;
11229 } /* end of input-only processing. */
11231 if (((REGCLASS_HAS_FP_REG (rclass)
11232 && (GET_CODE (x) == REG
11233 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11234 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11235 && TARGET_FMOVD))))
11236 || (REGCLASS_HAS_GENERAL_REG (rclass)
11237 && GET_CODE (x) == REG
11238 && FP_REGISTER_P (REGNO (x))))
11239 && ! TARGET_SHMEDIA
11240 && (mode == SFmode || mode == SImode))
11242 if ((rclass == FPUL_REGS
11243 || (REGCLASS_HAS_FP_REG (rclass)
11244 && ! TARGET_SHMEDIA && mode == SImode))
11245 && (GET_CODE (x) == MEM
11246 || (GET_CODE (x) == REG
11247 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11248 || REGNO (x) == T_REG
11249 || system_reg_operand (x, VOIDmode)))))
11251 if (rclass == FPUL_REGS)
11252 return GENERAL_REGS;
11255 if ((rclass == TARGET_REGS
11256 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
11257 && !satisfies_constraint_Csy (x)
11258 && (GET_CODE (x) != REG || ! GENERAL_REGISTER_P (REGNO (x))))
11259 return GENERAL_REGS;
11260 if ((rclass == MAC_REGS || rclass == PR_REGS)
11261 && GET_CODE (x) == REG && ! GENERAL_REGISTER_P (REGNO (x))
11262 && rclass != REGNO_REG_CLASS (REGNO (x)))
11263 return GENERAL_REGS;
11264 if (rclass != GENERAL_REGS && GET_CODE (x) == REG
11265 && TARGET_REGISTER_P (REGNO (x)))
11266 return GENERAL_REGS;
11270 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;