1 /* Output routines for GCC for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
21 /* Contributed by Steve Chamberlain (sac@cygnus.com).
22 Improved by Jim Wilson (wilson@cygnus.com). */
31 #include "insn-flags.h"
34 #include "hard-reg-set.h"
36 #include "insn-attr.h"
38 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
40 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
41 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
43 /* ??? The pragma interrupt support will not work for SH3. */
44 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
45 output code for the next function appropriate for an interrupt handler. */
48 /* This is set by the trap_exit attribute for functions. It specifies
49 a trap number to be used in a trapa instruction at function exit
50 (instead of an rte instruction). */
53 /* This is used by the sp_switch attribute for functions. It specifies
54 a variable holding the address of the stack the interrupt function
55 should switch to/from at entry/exit. */
58 /* This is set by #pragma trapa, and is similar to the above, except that
59 the compiler doesn't emit code to preserve all registers. */
60 static int pragma_trapa;
62 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
63 which has a separate set of low regs for User and Supervisor modes.
64 This should only be used for the lowest level of interrupts. Higher levels
65 of interrupts must save the registers in case they themselves are
67 int pragma_nosave_low_regs;
69 /* This is used for communication between SETUP_INCOMING_VARARGS and
70 sh_expand_prologue. */
71 int current_function_anonymous_args;
73 /* Global variables from toplev.c and final.c that are used within, but
74 not declared in any header file. */
75 extern char *version_string;
76 extern int *insn_addresses;
78 /* Global variables for machine-dependent things. */
80 /* Which cpu are we scheduling for. */
81 enum processor_type sh_cpu;
83 /* Saved operands from the last compare to use when we generate an scc
89 enum machine_mode sh_addr_diff_vec_mode;
91 /* Provides the class number of the smallest class containing
94 int regno_reg_class[FIRST_PSEUDO_REGISTER] =
96 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
97 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
98 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
99 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
100 GENERAL_REGS, PR_REGS, T_REGS, NO_REGS,
101 MAC_REGS, MAC_REGS, FPUL_REGS, GENERAL_REGS,
102 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
103 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
104 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
105 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
108 /* Provide reg_class from a letter such as appears in the machine
111 enum reg_class reg_class_from_letter[] =
113 /* a */ NO_REGS, /* b */ NO_REGS, /* c */ NO_REGS, /* d */ NO_REGS,
114 /* e */ NO_REGS, /* f */ FP_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
115 /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ PR_REGS,
116 /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
117 /* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
118 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
119 /* y */ FPUL_REGS, /* z */ R0_REGS
122 static void split_branches PROTO ((rtx));
124 /* Print the operand address in x to the stream. */
127 print_operand_address (stream, x)
131 switch (GET_CODE (x))
134 fprintf (stream, "@%s", reg_names[REGNO (x)]);
139 rtx base = XEXP (x, 0);
140 rtx index = XEXP (x, 1);
142 switch (GET_CODE (index))
145 fprintf (stream, "@(%d,%s)", INTVAL (index),
146 reg_names[REGNO (base)]);
150 fprintf (stream, "@(r0,%s)",
151 reg_names[MAX (REGNO (base), REGNO (index))]);
162 fprintf (stream, "@-%s", reg_names[REGNO (XEXP (x, 0))]);
166 fprintf (stream, "@%s+", reg_names[REGNO (XEXP (x, 0))]);
170 output_addr_const (stream, x);
175 /* Print operand x (an rtx) in assembler syntax to file stream
176 according to modifier code.
178 '.' print a .s if insn needs delay slot
179 ',' print LOCAL_LABEL_PREFIX
180 '@' print trap, rte or rts depending upon pragma interruptness
181 '#' output a nop if there is nothing to put in the delay slot
182 'O' print a constant without the #
183 'R' print the LSW of a dp value - changes if in little endian
184 'S' print the MSW of a dp value - changes if in little endian
185 'T' print the next word of a dp value - same as 'R' in big endian mode. */
188 print_operand (stream, x, code)
197 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
198 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
201 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
205 fprintf (stream, "trapa #%d", trap_exit);
206 else if (pragma_interrupt)
207 fprintf (stream, "rte");
209 fprintf (stream, "rts");
212 /* Output a nop if there's nothing in the delay slot. */
213 if (dbr_sequence_length () == 0)
214 fprintf (stream, "\n\tnop");
217 output_addr_const (stream, x);
220 fputs (reg_names[REGNO (x) + LSW], (stream));
223 fputs (reg_names[REGNO (x) + MSW], (stream));
226 /* Next word of a double. */
227 switch (GET_CODE (x))
230 fputs (reg_names[REGNO (x) + 1], (stream));
233 print_operand_address (stream,
234 XEXP (adj_offsettable_operand (x, 4), 0));
239 switch (GET_CODE (x))
242 fputs (reg_names[REGNO (x)], (stream));
245 output_address (XEXP (x, 0));
249 output_addr_const (stream, x);
256 /* Emit code to perform a block move. Choose the best method.
258 OPERANDS[0] is the destination.
259 OPERANDS[1] is the source.
260 OPERANDS[2] is the size.
261 OPERANDS[3] is the alignment safe to use. */
264 expand_block_move (operands)
267 int align = INTVAL (operands[3]);
268 int constp = (GET_CODE (operands[2]) == CONST_INT);
269 int bytes = (constp ? INTVAL (operands[2]) : 0);
271 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
272 alignment, or if it isn't a multiple of 4 bytes, then fail. */
273 if (! constp || align < 4 || (bytes % 4 != 0))
281 rtx r4 = gen_rtx (REG, SImode, 4);
282 rtx r5 = gen_rtx (REG, SImode, 5);
284 sprintf (entry, "__movstrSI%d", bytes);
285 entry_name = get_identifier (entry);
288 = copy_to_mode_reg (Pmode,
289 gen_rtx (SYMBOL_REF, Pmode,
290 IDENTIFIER_POINTER (entry_name)));
291 emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
292 emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
293 emit_insn (gen_block_move_real (func_addr_rtx));
297 /* This is the same number of bytes as a memcpy call, but to a different
298 less common function name, so this will occasionally use more space. */
299 if (! TARGET_SMALLCODE)
303 int final_switch, while_loop;
304 rtx r4 = gen_rtx (REG, SImode, 4);
305 rtx r5 = gen_rtx (REG, SImode, 5);
306 rtx r6 = gen_rtx (REG, SImode, 6);
308 entry_name = get_identifier ("__movstr");
310 = copy_to_mode_reg (Pmode,
311 gen_rtx (SYMBOL_REF, Pmode,
312 IDENTIFIER_POINTER (entry_name)));
313 emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
314 emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
316 /* r6 controls the size of the move. 16 is decremented from it
317 for each 64 bytes moved. Then the negative bit left over is used
318 as an index into a list of move instructions. e.g., a 72 byte move
319 would be set up with size(r6) = 14, for one iteration through the
320 big while loop, and a switch of -2 for the last part. */
322 final_switch = 16 - ((bytes / 4) % 16);
323 while_loop = ((bytes / 4) / 16 - 1) * 16;
324 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
325 emit_insn (gen_block_lump_real (func_addr_rtx));
332 /* Prepare operands for a move define_expand; specifically, one of the
333 operands must be in a register. */
336 prepare_move_operands (operands, mode)
338 enum machine_mode mode;
340 if (! reload_in_progress && ! reload_completed)
342 /* Copy the source to a register if both operands aren't registers. */
343 if (! register_operand (operands[0], mode)
344 && ! register_operand (operands[1], mode))
345 operands[1] = copy_to_mode_reg (mode, operands[1]);
347 /* This case can happen while generating code to move the result
348 of a library call to the target. Reject `st r0,@(rX,rY)' because
349 reload will fail to find a spill register for rX, since r0 is already
350 being used for the source. */
351 else if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 0
352 && GET_CODE (operands[0]) == MEM
353 && GET_CODE (XEXP (operands[0], 0)) == PLUS
354 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
355 operands[1] = copy_to_mode_reg (mode, operands[1]);
361 /* Prepare the operands for an scc instruction; make sure that the
362 compare has been done. */
364 prepare_scc_operands (code)
367 rtx t_reg = gen_rtx (REG, SImode, T_REG);
368 enum rtx_code oldcode = code;
369 enum machine_mode mode;
371 /* First need a compare insn. */
375 /* It isn't possible to handle this case. */
392 rtx tmp = sh_compare_op0;
393 sh_compare_op0 = sh_compare_op1;
394 sh_compare_op1 = tmp;
397 mode = GET_MODE (sh_compare_op0);
398 if (mode == VOIDmode)
399 mode = GET_MODE (sh_compare_op1);
401 sh_compare_op0 = force_reg (mode, sh_compare_op0);
402 if ((code != EQ && code != NE
403 && (sh_compare_op1 != const0_rtx
404 || code == GTU || code == GEU || code == LTU || code == LEU))
405 || TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT)
406 sh_compare_op1 = force_reg (mode, sh_compare_op1);
408 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
409 gen_rtx (code, SImode, sh_compare_op0,
415 /* Called from the md file, set up the operands of a compare instruction. */
418 from_compare (operands, code)
422 enum machine_mode mode = GET_MODE (sh_compare_op0);
424 if (mode == VOIDmode)
425 mode = GET_MODE (sh_compare_op1);
428 || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
430 /* Force args into regs, since we can't use constants here. */
431 sh_compare_op0 = force_reg (mode, sh_compare_op0);
432 if (sh_compare_op1 != const0_rtx
433 || code == GTU || code == GEU
434 || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
435 sh_compare_op1 = force_reg (mode, sh_compare_op1);
437 if (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
439 from_compare (operands, GT);
440 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
443 insn = gen_rtx (SET, VOIDmode,
444 gen_rtx (REG, SImode, 18),
445 gen_rtx (code, SImode, sh_compare_op0, sh_compare_op1));
449 /* Functions to output assembly code. */
451 /* Return a sequence of instructions to perform DI or DF move.
453 Since the SH cannot move a DI or DF in one instruction, we have
454 to take care when we see overlapping source and dest registers. */
457 output_movedouble (insn, operands, mode)
460 enum machine_mode mode;
462 rtx dst = operands[0];
463 rtx src = operands[1];
465 if (GET_CODE (dst) == MEM
466 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
467 return "mov.l %T1,%0\n\tmov.l %1,%0";
469 if (register_operand (dst, mode)
470 && register_operand (src, mode))
472 if (REGNO (src) == MACH_REG)
473 return "sts mach,%S0\n\tsts macl,%R0";
475 /* When mov.d r1,r2 do r2->r3 then r1->r2;
476 when mov.d r1,r0 do r1->r0 then r2->r1. */
478 if (REGNO (src) + 1 == REGNO (dst))
479 return "mov %T1,%T0\n\tmov %1,%0";
481 return "mov %1,%0\n\tmov %T1,%T0";
483 else if (GET_CODE (src) == CONST_INT)
485 if (INTVAL (src) < 0)
486 output_asm_insn ("mov #-1,%S0", operands);
488 output_asm_insn ("mov #0,%S0", operands);
492 else if (GET_CODE (src) == MEM)
495 int dreg = REGNO (dst);
496 rtx inside = XEXP (src, 0);
498 if (GET_CODE (inside) == REG)
499 ptrreg = REGNO (inside);
500 else if (GET_CODE (inside) == SUBREG)
501 ptrreg = REGNO (SUBREG_REG (inside)) + SUBREG_WORD (inside);
502 else if (GET_CODE (inside) == PLUS)
504 ptrreg = REGNO (XEXP (inside, 0));
505 /* ??? A r0+REG address shouldn't be possible here, because it isn't
506 an offsettable address. Unfortunately, offsettable addresses use
507 QImode to check the offset, and a QImode offsettable address
508 requires r0 for the other operand, which is not currently
509 supported, so we can't use the 'o' constraint.
510 Thus we must check for and handle r0+REG addresses here.
511 We punt for now, since this is likely very rare. */
512 if (GET_CODE (XEXP (inside, 1)) == REG)
515 else if (GET_CODE (inside) == LABEL_REF)
516 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
517 else if (GET_CODE (inside) == POST_INC)
518 return "mov.l %1,%0\n\tmov.l %1,%T0";
522 /* Work out the safe way to copy. Copy into the second half first. */
524 return "mov.l %T1,%T0\n\tmov.l %1,%0";
527 return "mov.l %1,%0\n\tmov.l %T1,%T0";
530 /* Print an instruction which would have gone into a delay slot after
531 another instruction, but couldn't because the other instruction expanded
532 into a sequence where putting the slot insn at the end wouldn't work. */
538 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
540 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
544 output_far_jump (insn, op)
548 struct { rtx lab, reg, op; } this;
551 int offset = branch_dest (insn) - insn_addresses[INSN_UID (insn)];
553 this.lab = gen_label_rtx ();
555 if (offset >= -32764 && offset - get_attr_length (insn) <= 32766)
558 jump = "mov.w %O0,%1;braf %1";
563 jump = "mov.l %O0,%1;jmp @%1";
565 /* If we have a scratch register available, use it. */
566 if (GET_CODE (PREV_INSN (insn)) == INSN
567 && INSN_CODE (PREV_INSN (insn)) == CODE_FOR_indirect_jump_scratch)
569 this.reg = SET_DEST (PATTERN (PREV_INSN (insn)));
570 output_asm_insn (jump, &this.lab);
571 if (dbr_sequence_length ())
572 print_slot (final_sequence);
574 output_asm_insn ("nop", 0);
578 /* Output the delay slot insn first if any. */
579 if (dbr_sequence_length ())
580 print_slot (final_sequence);
582 this.reg = gen_rtx (REG, SImode, 13);
583 output_asm_insn ("mov.l r13,@-r15", 0);
584 output_asm_insn (jump, &this.lab);
585 output_asm_insn ("mov.l @r15+,r13", 0);
588 output_asm_insn (".align 2", 0);
589 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
591 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
595 /* Local label counter, used for constants in the pool and inside
600 /* Output code for ordinary branches. */
603 output_branch (logic, insn, operands)
608 switch (get_attr_length (insn))
611 /* This can happen if filling the delay slot has caused a forward
612 branch to exceed its range (we could reverse it, but only
613 when we know we won't overextend other branches; this should
614 best be handled by relaxation).
615 It can also happen when other condbranches hoist delay slot insn
616 from their destination, thus leading to code size increase.
617 But the branch will still be in the range -4092..+4098 bytes. */
622 /* The call to print_slot will clobber the operands. */
623 rtx op0 = operands[0];
625 /* If the instruction in the delay slot is annulled (true), then
626 there is no delay slot where we can put it now. The only safe
627 place for it is after the label. final will do that by default. */
630 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
632 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
633 ASSEMBLER_DIALECT ? "/" : ".", label);
634 print_slot (final_sequence);
637 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
639 output_asm_insn ("bra\t%l0", &op0);
640 fprintf (asm_out_file, "\tnop\n");
641 ASM_OUTPUT_INTERNAL_LABEL(asm_out_file, "LF", label);
645 /* When relaxing, handle this like a short branch. The linker
646 will fix it up if it still doesn't fit after relaxation. */
648 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
655 output_branchy_insn (code, template, insn, operands)
661 rtx next_insn = NEXT_INSN (insn);
664 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
666 rtx src = SET_SRC (PATTERN (next_insn));
667 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
669 /* Following branch not taken */
670 operands[9] = gen_label_rtx ();
671 emit_label_after (operands[9], next_insn);
676 int offset = (branch_dest (next_insn)
677 - insn_addresses[INSN_UID (next_insn)] + 4);
678 if (offset >= -252 && offset <= 258)
680 if (GET_CODE (src) == IF_THEN_ELSE)
688 operands[9] = gen_label_rtx ();
689 emit_label_after (operands[9], insn);
694 output_ieee_ccmpeq (insn, operands)
697 output_branchy_insn (NE, "bt\t%l9\\;fcmp/eq\t%1,%0", insn, operands);
700 /* Output to FILE the start of the assembler file. */
703 output_file_start (file)
708 output_file_directive (file, main_input_filename);
710 /* Switch to the data section so that the coffsem symbol and the
711 gcc2_compiled. symbol aren't in the text section. */
714 if (TARGET_LITTLE_ENDIAN)
715 fprintf (file, "\t.little\n");
718 /* Actual number of instructions used to make a shift by N. */
719 static char ashiftrt_insns[] =
720 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
722 /* Left shift and logical right shift are the same. */
723 static char shift_insns[] =
724 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
726 /* Individual shift amounts needed to get the above length sequences.
727 One bit right shifts clobber the T bit, so when possible, put one bit
728 shifts in the middle of the sequence, so the ends are eligible for
729 branch delay slots. */
730 static short shift_amounts[32][5] = {
731 {0}, {1}, {2}, {2, 1},
732 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
733 {8}, {8, 1}, {8, 2}, {8, 1, 2},
734 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
735 {16}, {16, 1}, {16, 2}, {16, 1, 2},
736 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
737 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
738 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
740 /* Likewise, but for shift amounts < 16, up to three highmost bits
741 might be clobbered. This is typically used when combined with some
742 kind of sign or zero extension. */
744 static char ext_shift_insns[] =
745 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
747 static short ext_shift_amounts[32][4] = {
748 {0}, {1}, {2}, {2, 1},
749 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
750 {8}, {8, 1}, {8, 2}, {8, 1, 2},
751 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
752 {16}, {16, 1}, {16, 2}, {16, 1, 2},
753 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
754 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
755 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
757 /* Assuming we have a value that has been sign-extended by at least one bit,
758 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
759 to shift it by N without data loss, and quicker than by other means? */
760 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
762 /* This is used in length attributes in sh.md to help compute the length
763 of arbitrary constant shift instructions. */
766 shift_insns_rtx (insn)
769 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
770 int shift_count = INTVAL (XEXP (set_src, 1));
771 enum rtx_code shift_code = GET_CODE (set_src);
776 return ashiftrt_insns[shift_count];
779 return shift_insns[shift_count];
785 /* Return the cost of a shift. */
791 int value = INTVAL (XEXP (x, 1));
793 /* If shift by a non constant, then this will be expensive. */
794 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
795 return SH_DYNAMIC_SHIFT_COST;
797 /* Otherwise, return the true cost in instructions. */
798 if (GET_CODE (x) == ASHIFTRT)
800 int cost = ashiftrt_insns[value];
801 /* If SH3, then we put the constant in a reg and use shad. */
802 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
803 cost = 1 + SH_DYNAMIC_SHIFT_COST;
807 return shift_insns[value];
810 /* Return the cost of an AND operation. */
818 /* Anding with a register is a single cycle and instruction. */
819 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
822 i = INTVAL (XEXP (x, 1));
823 /* These constants are single cycle extu.[bw] instructions. */
824 if (i == 0xff || i == 0xffff)
826 /* Constants that can be used in an and immediate instruction is a single
827 cycle, but this requires r0, so make it a little more expensive. */
828 if (CONST_OK_FOR_L (i))
830 /* Constants that can be loaded with a mov immediate and an and.
831 This case is probably unnecessary. */
832 if (CONST_OK_FOR_I (i))
834 /* Any other constants requires a 2 cycle pc-relative load plus an and.
835 This case is probably unnecessary. */
839 /* Return the cost of a multiply. */
846 /* We have a mul insn, so we can never take more than the mul and the
847 read of the mac reg, but count more because of the latency and extra
849 if (TARGET_SMALLCODE)
854 /* If we're aiming at small code, then just count the number of
855 insns in a multiply call sequence. */
856 if (TARGET_SMALLCODE)
859 /* Otherwise count all the insns in the routine we'd be calling too. */
863 /* Code to expand a shift. */
866 gen_ashift (type, n, reg)
871 /* Negative values here come from the shift_amounts array. */
884 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
888 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
890 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
893 emit_insn (gen_ashlsi3_k (reg, reg, GEN_INT (n)));
898 /* Same for HImode */
901 gen_ashift_hi (type, n, reg)
906 /* Negative values here come from the shift_amounts array. */
920 /* We don't have HImode right shift operations because using the
921 ordinary 32 bit shift instructions for that doesn't generate proper
923 gen_ashift_hi is only called in contexts where we know that the
924 sign extension works out correctly. */
925 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, 0));
928 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
933 /* Output RTL to split a constant shift into its component SH constant
934 shift instructions. */
937 gen_shifty_op (code, operands)
941 int value = INTVAL (operands[2]);
944 /* Truncate the shift count in case it is out of bounds. */
945 value = value & 0x1f;
949 if (code == LSHIFTRT)
951 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
952 emit_insn (gen_movt (operands[0]));
955 else if (code == ASHIFT)
957 /* There is a two instruction sequence for 31 bit left shifts,
958 but it requires r0. */
959 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
961 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
962 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
969 /* This can happen when not optimizing. We must output something here
970 to prevent the compiler from aborting in final.c after the try_split
972 emit_insn (gen_nop ());
976 max = shift_insns[value];
977 for (i = 0; i < max; i++)
978 gen_ashift (code, shift_amounts[value][i], operands[0]);
981 /* Same as above, but optimized for values where the topmost bits don't
985 gen_shifty_hi_op (code, operands)
989 int value = INTVAL (operands[2]);
993 /* This operation is used by and_shl for SImode values with a few
994 high bits known to be cleared. */
998 emit_insn (gen_nop ());
1002 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
1005 max = ext_shift_insns[value];
1006 for (i = 0; i < max; i++)
1007 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1010 /* When shifting right, emit the shifts in reverse order, so that
1011 solitary negative values come first. */
1012 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
1013 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1016 /* Output RTL for an arithmetic right shift. */
1018 /* ??? Rewrite to use super-optimizer sequences. */
1021 expand_ashiftrt (operands)
1031 if (GET_CODE (operands[2]) != CONST_INT)
1033 rtx count = copy_to_mode_reg (SImode, operands[2]);
1034 emit_insn (gen_negsi2 (count, count));
1035 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1038 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
1039 > 1 + SH_DYNAMIC_SHIFT_COST)
1042 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
1043 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1047 if (GET_CODE (operands[2]) != CONST_INT)
1050 value = INTVAL (operands[2]) & 31;
1054 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
1057 else if (value >= 16 && value <= 19)
1059 wrk = gen_reg_rtx (SImode);
1060 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
1063 gen_ashift (ASHIFTRT, 1, wrk);
1064 emit_move_insn (operands[0], wrk);
1067 /* Expand a short sequence inline, longer call a magic routine. */
1068 else if (value <= 5)
1070 wrk = gen_reg_rtx (SImode);
1071 emit_move_insn (wrk, operands[1]);
1073 gen_ashift (ASHIFTRT, 1, wrk);
1074 emit_move_insn (operands[0], wrk);
1078 wrk = gen_reg_rtx (Pmode);
1080 /* Load the value into an arg reg and call a helper. */
1081 emit_move_insn (gen_rtx (REG, SImode, 4), operands[1]);
1082 sprintf (func, "__ashiftrt_r4_%d", value);
1083 func_name = get_identifier (func);
1084 emit_move_insn (wrk, gen_rtx (SYMBOL_REF, Pmode,
1085 IDENTIFIER_POINTER (func_name)));
1086 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
1087 emit_move_insn (operands[0], gen_rtx (REG, SImode, 4));
1091 int sh_dynamicalize_shift_p (count)
1094 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
1097 /* Try to find a good way to implement the combiner pattern
1098 [(set (match_operand:SI 0 "register_operand" "r")
1099 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1100 (match_operand:SI 2 "const_int_operand" "n"))
1101 (match_operand:SI 3 "const_int_operand" "n"))) .
1102 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1103 return 0 for simple right / left or left/right shift combination.
1104 return 1 for a combination of shifts with zero_extend.
1105 return 2 for a combination of shifts with an AND that needs r0.
1106 return 3 for a combination of shifts with an AND that needs an extra
1107 scratch register, when the three highmost bits of the AND mask are clear.
1108 return 4 for a combination of shifts with an AND that needs an extra
1109 scratch register, when any of the three highmost bits of the AND mask
1111 If ATTRP is set, store an initial right shift width in ATTRP[0],
1112 and the instruction length in ATTRP[1] . These values are not valid
1114 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1115 shift_amounts for the last shift value that is to be used before the
1118 shl_and_kind (left_rtx, mask_rtx, attrp)
1119 rtx left_rtx, mask_rtx;
1122 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
1123 int left = INTVAL (left_rtx), right;
1125 int cost, best_cost = 10000;
1126 int best_right = 0, best_len = 0;
1130 if (left < 0 || left > 31)
1132 if (GET_CODE (mask_rtx) == CONST_INT)
1133 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
1135 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
1136 /* Can this be expressed as a right shift / left shift pair ? */
1137 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
1138 right = exact_log2 (lsb);
1139 mask2 = ~(mask + lsb - 1);
1140 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
1141 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1143 best_cost = shift_insns[right] + shift_insns[right + left];
1144 /* mask has no trailing zeroes <==> ! right */
1145 else if (! right && mask2 == ~(lsb2 - 1))
1147 int late_right = exact_log2 (lsb2);
1148 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
1150 /* Try to use zero extend */
1151 if (mask2 == ~(lsb2 - 1))
1155 for (width = 8; width <= 16; width += 8)
1157 /* Can we zero-extend right away? */
1158 if (lsb2 == (HOST_WIDE_INT)1 << width)
1161 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
1162 if (cost < best_cost)
1173 /* ??? Could try to put zero extend into initial right shift,
1174 or even shift a bit left before the right shift. */
1175 /* Determine value of first part of left shift, to get to the
1176 zero extend cut-off point. */
1177 first = width - exact_log2 (lsb2) + right;
1178 if (first >= 0 && right + left - first >= 0)
1180 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
1181 + ext_shift_insns[right + left - first];
1182 if (cost < best_cost)
1194 /* Try to use r0 AND pattern */
1195 for (i = 0; i <= 2; i++)
1199 if (! CONST_OK_FOR_L (mask >> i))
1201 cost = (i != 0) + 2 + ext_shift_insns[left + i];
1202 if (cost < best_cost)
1207 best_len = cost - 1;
1210 /* Try to use a scratch register to hold the AND operand. */
1211 can_ext = ((mask << left) & 0xe0000000) == 0;
1212 for (i = 0; i <= 2; i++)
1216 cost = (i != 0) + (CONST_OK_FOR_I (mask >> i) ? 2 : 3)
1217 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
1218 if (cost < best_cost)
1223 best_len = cost - 1 - ! CONST_OK_FOR_I (mask >> i);
1229 attrp[0] = best_right;
1230 attrp[1] = best_len;
1235 /* This is used in length attributes of the unnamed instructions
1236 corresponding to shl_and_kind return values of 1 and 2. */
1238 shl_and_length (insn)
1241 rtx set_src, left_rtx, mask_rtx;
1244 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1245 left_rtx = XEXP (XEXP (set_src, 0), 1);
1246 mask_rtx = XEXP (set_src, 1);
1247 shl_and_kind (left_rtx, mask_rtx, attributes);
1248 return attributes[1];
1251 /* This is used in length attribute of the and_shl_scratch instruction. */
1254 shl_and_scr_length (insn)
1257 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1258 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
1259 rtx op = XEXP (set_src, 0);
1260 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
1261 op = XEXP (XEXP (op, 0), 0);
1262 return len + shift_insns[INTVAL (XEXP (op, 1))];
1265 /* Generating rtl? */
1266 extern int rtx_equal_function_value_matters;
1268 /* Generate rtl for instructions for which shl_and_kind advised a particular
1269 method of generating them, i.e. returned zero. */
1272 gen_shl_and (dest, left_rtx, mask_rtx, source)
1273 rtx dest, left_rtx, mask_rtx, source;
1276 unsigned HOST_WIDE_INT mask;
1277 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
1278 int right, total_shift;
1279 int (*shift_gen_fun) PROTO((int, rtx*)) = gen_shifty_hi_op;
1281 right = attributes[0];
1282 total_shift = INTVAL (left_rtx) + right;
1283 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
1290 int first = attributes[2];
1295 emit_insn ((mask << right) <= 0xff
1296 ? gen_zero_extendqisi2(dest,
1297 gen_lowpart (QImode, source))
1298 : gen_zero_extendhisi2(dest,
1299 gen_lowpart (HImode, source)));
1303 emit_insn (gen_movsi (dest, source));
1307 operands[2] = GEN_INT (right);
1308 gen_shifty_hi_op (LSHIFTRT, operands);
1312 operands[2] = GEN_INT (first);
1313 gen_shifty_hi_op (ASHIFT, operands);
1314 total_shift -= first;
1318 emit_insn (mask <= 0xff
1319 ? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest))
1320 : gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest)));
1321 if (total_shift > 0)
1323 operands[2] = GEN_INT (total_shift);
1324 gen_shifty_hi_op (ASHIFT, operands);
1329 shift_gen_fun = gen_shifty_op;
1332 /* If the topmost bit that matters is set, set the topmost bits
1333 that don't matter. This way, we might be able to get a shorter
1335 if (mask & ((HOST_WIDE_INT)1 << 31 - total_shift))
1336 mask |= (HOST_WIDE_INT)~0 << (31 - total_shift);
1337 /* Don't expand fine-grained when combining, because that will
1338 make the pattern fail. */
1339 if (rtx_equal_function_value_matters
1340 || reload_in_progress || reload_completed)
1346 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
1349 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
1354 operands[2] = GEN_INT (total_shift);
1355 shift_gen_fun (ASHIFT, operands);
1362 if (kind != 4 && total_shift < 16)
1364 neg = -ext_shift_amounts[total_shift][1];
1366 neg -= ext_shift_amounts[total_shift][2];
1370 emit_insn (gen_and_shl_scratch (dest, source,
1373 GEN_INT (total_shift + neg),
1375 emit_insn (gen_movsi (dest, dest));
1382 /* Try to find a good way to implement the combiner pattern
1383 [(set (match_operand:SI 0 "register_operand" "=r")
1384 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1385 (match_operand:SI 2 "const_int_operand" "n")
1386 (match_operand:SI 3 "const_int_operand" "n")
1388 (clobber (reg:SI 18))]
1389 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
1390 return 0 for simple left / right shift combination.
1391 return 1 for left shift / 8 bit sign extend / left shift.
1392 return 2 for left shift / 16 bit sign extend / left shift.
1393 return 3 for left shift / 8 bit sign extend / shift / sign extend.
1394 return 4 for left shift / 16 bit sign extend / shift / sign extend.
1395 return 5 for left shift / 16 bit sign extend / right shift
1396 return 6 for < 8 bit sign extend / left shift.
1397 return 7 for < 8 bit sign extend / left shift / single right shift.
1398 If COSTP is nonzero, assign the calculated cost to *COSTP. */
1401 shl_sext_kind (left_rtx, size_rtx, costp)
1402 rtx left_rtx, size_rtx;
1405 int left, size, insize, ext;
1406 int cost, best_cost;
1409 left = INTVAL (left_rtx);
1410 size = INTVAL (size_rtx);
1411 insize = size - left;
1414 /* Default to left / right shift. */
1416 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
1419 /* 16 bit shift / sign extend / 16 bit shift */
1420 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
1421 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
1422 below, by alternative 3 or something even better. */
1423 if (cost < best_cost)
1429 /* Try a plain sign extend between two shifts. */
1430 for (ext = 16; ext >= insize; ext -= 8)
1434 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
1435 if (cost < best_cost)
1441 /* Check if we can do a sloppy shift with a final signed shift
1442 restoring the sign. */
1443 if (EXT_SHIFT_SIGNED (size - ext))
1444 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
1445 /* If not, maybe it's still cheaper to do the second shift sloppy,
1446 and do a final sign extend? */
1447 else if (size <= 16)
1448 cost = ext_shift_insns[ext - insize] + 1
1449 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
1452 if (cost < best_cost)
1454 kind = ext / 8U + 2;
1458 /* Check if we can sign extend in r0 */
1461 cost = 3 + shift_insns[left];
1462 if (cost < best_cost)
1467 /* Try the same with a final signed shift. */
1470 cost = 3 + ext_shift_insns[left + 1] + 1;
1471 if (cost < best_cost)
1480 /* Try to use a dynamic shift. */
1481 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
1482 if (cost < best_cost)
1493 /* Function to be used in the length attribute of the instructions
1494 implementing this pattern. */
1497 shl_sext_length (insn)
1500 rtx set_src, left_rtx, size_rtx;
1503 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1504 left_rtx = XEXP (XEXP (set_src, 0), 1);
1505 size_rtx = XEXP (set_src, 1);
1506 shl_sext_kind (left_rtx, size_rtx, &cost);
1510 /* Generate rtl for this pattern */
1513 gen_shl_sext (dest, left_rtx, size_rtx, source)
1514 rtx dest, left_rtx, size_rtx, source;
1517 int left, size, insize, cost;
1520 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
1521 left = INTVAL (left_rtx);
1522 size = INTVAL (size_rtx);
1523 insize = size - left;
1531 int ext = kind & 1 ? 8 : 16;
1532 int shift2 = size - ext;
1534 /* Don't expand fine-grained when combining, because that will
1535 make the pattern fail. */
1536 if (! rtx_equal_function_value_matters
1537 && ! reload_in_progress && ! reload_completed)
1539 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
1540 emit_insn (gen_movsi (dest, source));
1544 emit_insn (gen_movsi (dest, source));
1548 operands[2] = GEN_INT (ext - insize);
1549 gen_shifty_hi_op (ASHIFT, operands);
1552 ? gen_extendqisi2(dest, gen_lowpart (QImode, dest))
1553 : gen_extendhisi2(dest, gen_lowpart (HImode, dest)));
1558 operands[2] = GEN_INT (shift2);
1559 gen_shifty_op (ASHIFT, operands);
1566 if (EXT_SHIFT_SIGNED (shift2))
1568 operands[2] = GEN_INT (shift2 + 1);
1569 gen_shifty_op (ASHIFT, operands);
1570 operands[2] = GEN_INT (1);
1571 gen_shifty_op (ASHIFTRT, operands);
1574 operands[2] = GEN_INT (shift2);
1575 gen_shifty_hi_op (ASHIFT, operands);
1579 operands[2] = GEN_INT (-shift2);
1580 gen_shifty_hi_op (LSHIFTRT, operands);
1582 emit_insn (size <= 8
1583 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
1584 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
1591 emit_insn (gen_shl_sext_ext (dest, source, GEN_INT (16 - insize),
1593 /* Don't use gen_ashrsi3 because it generates new pseudos. */
1595 gen_ashift (ASHIFTRT, 1, dest);
1600 /* Don't expand fine-grained when combining, because that will
1601 make the pattern fail. */
1602 if (! rtx_equal_function_value_matters
1603 && ! reload_in_progress && ! reload_completed)
1605 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
1606 emit_insn (gen_movsi (dest, source));
1609 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
1610 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
1611 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
1613 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
1614 gen_shifty_op (ASHIFT, operands);
1616 emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
1624 /* The SH cannot load a large constant into a register, constants have to
1625 come from a pc relative load. The reference of a pc relative load
1626 instruction must be less than 1k infront of the instruction. This
1627 means that we often have to dump a constant inside a function, and
1628 generate code to branch around it.
1630 It is important to minimize this, since the branches will slow things
1631 down and make things bigger.
1633 Worst case code looks like:
1651 We fix this by performing a scan before scheduling, which notices which
1652 instructions need to have their operands fetched from the constant table
1653 and builds the table.
1657 scan, find an instruction which needs a pcrel move. Look forward, find the
1658 last barrier which is within MAX_COUNT bytes of the requirement.
1659 If there isn't one, make one. Process all the instructions between
1660 the find and the barrier.
1662 In the above example, we can tell that L3 is within 1k of L1, so
1663 the first move can be shrunk from the 3 insn+constant sequence into
1664 just 1 insn, and the constant moved to L3 to make:
1675 Then the second move becomes the target for the shortening process. */
1679 rtx value; /* Value in table. */
1680 rtx label; /* Label of value. */
1681 enum machine_mode mode; /* Mode of value. */
1684 /* The maximum number of constants that can fit into one pool, since
1685 the pc relative range is 0...1020 bytes and constants are at least 4
1688 #define MAX_POOL_SIZE (1020/4)
1689 static pool_node pool_vector[MAX_POOL_SIZE];
1690 static int pool_size;
1692 /* ??? If we need a constant in HImode which is the truncated value of a
1693 constant we need in SImode, we could combine the two entries thus saving
1694 two bytes. Is this common enough to be worth the effort of implementing
1697 /* ??? This stuff should be done at the same time that we shorten branches.
1698 As it is now, we must assume that all branches are the maximum size, and
1699 this causes us to almost always output constant pools sooner than
1702 /* Add a constant to the pool and return its label. */
1705 add_constant (x, mode)
1707 enum machine_mode mode;
1712 /* First see if we've already got it. */
1713 for (i = 0; i < pool_size; i++)
1715 if (x->code == pool_vector[i].value->code
1716 && mode == pool_vector[i].mode)
1718 if (x->code == CODE_LABEL)
1720 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
1723 if (rtx_equal_p (x, pool_vector[i].value))
1724 return pool_vector[i].label;
1728 /* Need a new one. */
1729 pool_vector[pool_size].value = x;
1730 lab = gen_label_rtx ();
1731 pool_vector[pool_size].mode = mode;
1732 pool_vector[pool_size].label = lab;
1737 /* Output the literal table. */
1746 /* Do two passes, first time dump out the HI sized constants. */
1748 for (i = 0; i < pool_size; i++)
1750 pool_node *p = &pool_vector[i];
1752 if (p->mode == HImode)
1756 scan = emit_insn_after (gen_align_2 (), scan);
1759 scan = emit_label_after (p->label, scan);
1760 scan = emit_insn_after (gen_consttable_2 (p->value), scan);
1766 for (i = 0; i < pool_size; i++)
1768 pool_node *p = &pool_vector[i];
1779 scan = emit_label_after (gen_label_rtx (), scan);
1780 scan = emit_insn_after (gen_align_4 (), scan);
1783 scan = emit_label_after (p->label, scan);
1784 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
1791 scan = emit_label_after (gen_label_rtx (), scan);
1792 scan = emit_insn_after (gen_align_4 (), scan);
1795 scan = emit_label_after (p->label, scan);
1796 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
1804 scan = emit_insn_after (gen_consttable_end (), scan);
1805 scan = emit_barrier_after (scan);
1809 /* Return non-zero if constant would be an ok source for a
1810 mov.w instead of a mov.l. */
1816 return (GET_CODE (src) == CONST_INT
1817 && INTVAL (src) >= -32768
1818 && INTVAL (src) <= 32767);
1821 /* Non-zero if the insn is a move instruction which needs to be fixed. */
1823 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
1824 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
1825 need to fix it if the input value is CONST_OK_FOR_I. */
1831 if (GET_CODE (insn) == INSN)
1833 rtx pat = PATTERN (insn);
1834 if (GET_CODE (pat) == PARALLEL)
1835 pat = XVECEXP (pat, 0, 0);
1836 if (GET_CODE (pat) == SET
1837 /* We can load any 8 bit value if we don't care what the high
1838 order bits end up as. */
1839 && GET_MODE (SET_DEST (pat)) != QImode
1840 && CONSTANT_P (SET_SRC (pat))
1842 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
1843 && (fp_zero_operand (SET_SRC (pat))
1844 || fp_one_operand (SET_SRC (pat)))
1845 && GET_CODE (SET_DEST (pat)) == REG
1846 && REGNO (SET_DEST (pat)) >= FIRST_FP_REG
1847 && REGNO (SET_DEST (pat)) <= LAST_FP_REG)
1848 && (GET_CODE (SET_SRC (pat)) != CONST_INT
1849 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat)))))
1860 return (GET_CODE (insn) == INSN
1861 && GET_CODE (PATTERN (insn)) == SET
1862 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
1863 && XINT (SET_SRC (PATTERN (insn)), 1) == 1);
1866 /* Find the last barrier from insn FROM which is close enough to hold the
1867 constant pool. If we can't find one, then create one near the end of
1871 find_barrier (num_mova, mova, from)
1881 int leading_mova = num_mova;
1882 rtx barrier_before_mova, found_barrier = 0, good_barrier = 0;
1886 /* For HImode: range is 510, add 4 because pc counts from address of
1887 second instruction after this one, subtract 2 for the jump instruction
1888 that we may need to emit before the table, subtract 2 for the instruction
1889 that fills the jump delay slot (in very rare cases, reorg will take an
1890 instruction from after the constant pool or will leave the delay slot
1891 empty). This gives 510.
1892 For SImode: range is 1020, add 4 because pc counts from address of
1893 second instruction after this one, subtract 2 in case pc is 2 byte
1894 aligned, subtract 2 for the jump instruction that we may need to emit
1895 before the table, subtract 2 for the instruction that fills the jump
1896 delay slot. This gives 1018. */
1898 /* The branch will always be shortened now that the reference address for
1899 forward branches is the successor address, thus we need no longer make
1900 adjustments to the [sh]i_limit for -O0. */
1905 while (from && count_si < si_limit && count_hi < hi_limit)
1907 int inc = get_attr_length (from);
1910 if (GET_CODE (from) == CODE_LABEL)
1913 new_align = 1 << label_to_alignment (from);
1914 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
1915 new_align = 1 << barrier_align (from);
1921 if (GET_CODE (from) == BARRIER)
1924 found_barrier = from;
1926 /* If we are at the end of the function, or in front of an alignment
1927 instruction, we need not insert an extra alignment. We prefer
1928 this kind of barrier. */
1929 if (barrier_align (from) > 2)
1930 good_barrier = from;
1933 if (broken_move (from))
1936 enum machine_mode mode;
1938 pat = PATTERN (from);
1939 if (GET_CODE (pat) == PARALLEL)
1940 pat = XVECEXP (pat, 0, 0);
1941 src = SET_SRC (pat);
1942 dst = SET_DEST (pat);
1943 mode = GET_MODE (dst);
1945 /* We must explicitly check the mode, because sometimes the
1946 front end will generate code to load unsigned constants into
1947 HImode targets without properly sign extending them. */
1948 if (mode == HImode || (mode == SImode && hi_const (src)))
1951 /* We put the short constants before the long constants, so
1952 we must count the length of short constants in the range
1953 for the long constants. */
1954 /* ??? This isn't optimal, but is easy to do. */
1959 while (si_align > 2 && found_si + si_align - 2 > count_si)
1961 if (found_si > count_si)
1962 count_si = found_si;
1963 found_si += GET_MODE_SIZE (mode);
1965 si_limit -= GET_MODE_SIZE (mode);
1975 barrier_before_mova = good_barrier ? good_barrier : found_barrier;
1977 if (found_si > count_si)
1978 count_si = found_si;
1980 else if (GET_CODE (from) == JUMP_INSN
1981 && (GET_CODE (PATTERN (from)) == ADDR_VEC
1982 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
1986 if (barrier_align (next_real_insn (from)) == CACHE_LOG)
1988 /* We have just passed the barrier in front front of the
1989 ADDR_DIFF_VEC, which is stored in found_barrier. Since
1990 the ADDR_DIFF_VEC is accessed as data, just like our pool
1991 constants, this is a good opportunity to accommodate what
1992 we have gathered so far.
1993 If we waited any longer, we could end up at a barrier in
1994 front of code, which gives worse cache usage for separated
1995 instruction / data caches. */
1996 good_barrier = found_barrier;
2001 rtx body = PATTERN (from);
2002 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
2008 if (new_align > si_align)
2010 si_limit -= count_si - 1 & new_align - si_align;
2011 si_align = new_align;
2013 count_si = count_si + new_align - 1 & -new_align;
2018 if (new_align > hi_align)
2020 hi_limit -= count_hi - 1 & new_align - hi_align;
2021 hi_align = new_align;
2023 count_hi = count_hi + new_align - 1 & -new_align;
2026 from = NEXT_INSN (from);
2032 /* Try as we might, the leading mova is out of range. Change
2033 it into a load (which will become a pcload) and retry. */
2034 SET_SRC (PATTERN (mova)) = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
2035 INSN_CODE (mova) = -1;
2036 return find_barrier (0, 0, mova);
2040 /* Insert the constant pool table before the mova instruction,
2041 to prevent the mova label reference from going out of range. */
2043 good_barrier = found_barrier = barrier_before_mova;
2048 if (good_barrier && next_real_insn (found_barrier))
2049 found_barrier = good_barrier;
2053 /* We didn't find a barrier in time to dump our stuff,
2054 so we'll make one. */
2055 rtx label = gen_label_rtx ();
2057 /* If we exceeded the range, then we must back up over the last
2058 instruction we looked at. Otherwise, we just need to undo the
2059 NEXT_INSN at the end of the loop. */
2060 if (count_hi > hi_limit || count_si > si_limit)
2061 from = PREV_INSN (PREV_INSN (from));
2063 from = PREV_INSN (from);
2065 /* Walk back to be just before any jump or label.
2066 Putting it before a label reduces the number of times the branch
2067 around the constant pool table will be hit. Putting it before
2068 a jump makes it more likely that the bra delay slot will be
2070 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
2071 || GET_CODE (from) == CODE_LABEL)
2072 from = PREV_INSN (from);
2074 from = emit_jump_insn_after (gen_jump (label), from);
2075 JUMP_LABEL (from) = label;
2076 LABEL_NUSES (label) = 1;
2077 found_barrier = emit_barrier_after (from);
2078 emit_label_after (label, found_barrier);
2081 return found_barrier;
2084 /* If the instruction INSN is implemented by a special function, and we can
2085 positively find the register that is used to call the sfunc, and this
2086 register is not used anywhere else in this instruction - except as the
2087 destination of a set, return this register; else, return 0. */
2089 sfunc_uses_reg (insn)
2093 rtx pattern, part, reg_part, reg;
2095 if (GET_CODE (insn) != INSN)
2097 pattern = PATTERN (insn);
2098 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
2101 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
2103 part = XVECEXP (pattern, 0, i);
2104 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
2109 reg = XEXP (reg_part, 0);
2110 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
2112 part = XVECEXP (pattern, 0, i);
2113 if (part == reg_part)
2115 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
2116 && GET_CODE (SET_DEST (part)) == REG)
2117 ? SET_SRC (part) : part)))
2123 /* See if the only way in which INSN uses REG is by calling it, or by
2124 setting it while calling it. Set *SET to a SET rtx if the register
2128 noncall_uses_reg (reg, insn, set)
2137 reg2 = sfunc_uses_reg (insn);
2138 if (reg2 && REGNO (reg2) == REGNO (reg))
2140 pattern = single_set (insn);
2142 && GET_CODE (SET_DEST (pattern)) == REG
2143 && REGNO (reg) == REGNO (SET_DEST (pattern)))
2147 if (GET_CODE (insn) != CALL_INSN)
2149 /* We don't use rtx_equal_p because we don't care if the mode is
2151 pattern = single_set (insn);
2153 && GET_CODE (SET_DEST (pattern)) == REG
2154 && REGNO (reg) == REGNO (SET_DEST (pattern)))
2160 par = PATTERN (insn);
2161 if (GET_CODE (par) == PARALLEL)
2162 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
2164 part = XVECEXP (par, 0, i);
2165 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
2168 return reg_mentioned_p (reg, SET_SRC (pattern));
2174 pattern = PATTERN (insn);
2176 if (GET_CODE (pattern) == PARALLEL)
2180 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
2181 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
2183 pattern = XVECEXP (pattern, 0, 0);
2186 if (GET_CODE (pattern) == SET)
2188 if (reg_mentioned_p (reg, SET_DEST (pattern)))
2190 /* We don't use rtx_equal_p, because we don't care if the
2191 mode is different. */
2192 if (GET_CODE (SET_DEST (pattern)) != REG
2193 || REGNO (reg) != REGNO (SET_DEST (pattern)))
2199 pattern = SET_SRC (pattern);
2202 if (GET_CODE (pattern) != CALL
2203 || GET_CODE (XEXP (pattern, 0)) != MEM
2204 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
2210 /* Given a X, a pattern of an insn or a part of it, return a mask of used
2211 general registers. Bits 0..15 mean that the respective registers
2212 are used as inputs in the instruction. Bits 16..31 mean that the
2213 registers 0..15, respectively, are used as outputs, or are clobbered.
2214 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
2216 regs_used (x, is_dest)
2225 code = GET_CODE (x);
2230 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
2231 << (REGNO (x) + is_dest));
2235 rtx y = SUBREG_REG (x);
2237 if (GET_CODE (y) != REG)
2240 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
2241 << (REGNO (y) + SUBREG_WORD (x) + is_dest));
2245 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
2247 /* If there was a return value, it must have been indicated with USE. */
2260 fmt = GET_RTX_FORMAT (code);
2262 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2267 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2268 used |= regs_used (XVECEXP (x, i, j), is_dest);
2270 else if (fmt[i] == 'e')
2271 used |= regs_used (XEXP (x, i), is_dest);
2276 /* Create an instruction that prevents redirection of a conditional branch
2277 to the destination of the JUMP with address ADDR.
2278 If the branch needs to be implemented as an indirect jump, try to find
2279 a scratch register for it.
2280 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
2281 If any preceding insn that doesn't fit into a delay slot is good enough,
2282 pass 1. Pass 2 if a definite blocking insn is needed.
2283 -1 is used internally to avoid deep recursion.
2284 If a blocking instruction is made or recognized, return it. */
2287 gen_block_redirect (jump, addr, need_block)
2289 int addr, need_block;
2292 rtx prev = prev_nonnote_insn (jump);
2295 /* First, check if we already have an instruction that satisfies our need. */
2296 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
2298 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2300 if (GET_CODE (PATTERN (prev)) == USE
2301 || GET_CODE (PATTERN (prev)) == CLOBBER
2302 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
2304 else if ((need_block &= ~1) < 0)
2306 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
2309 /* We can't use JUMP_LABEL here because it might be undefined
2310 when not optimizing. */
2311 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
2312 /* If the branch is out of range, try to find a scratch register for it. */
2314 && (insn_addresses[INSN_UID (dest)] - addr + 4092U > 4092 + 4098))
2317 /* Don't look for the stack pointer as a scratch register,
2318 it would cause trouble if an interrupt occurred. */
2319 unsigned try = 0x7fff, used;
2320 int jump_left = flag_expensive_optimizations + 1;
2322 /* It is likely that the most recent eligible instruction is wanted for
2323 the delay slot. Therefore, find out which registers it uses, and
2324 try to avoid using them. */
2326 for (scan = jump; scan = PREV_INSN (scan); )
2330 if (INSN_DELETED_P (scan))
2332 code = GET_CODE (scan);
2333 if (code == CODE_LABEL || code == JUMP_INSN)
2336 && GET_CODE (PATTERN (scan)) != USE
2337 && GET_CODE (PATTERN (scan)) != CLOBBER
2338 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
2340 try &= ~regs_used (PATTERN (scan), 0);
2344 for (used = dead = 0, scan = JUMP_LABEL (jump); scan = NEXT_INSN (scan); )
2348 if (INSN_DELETED_P (scan))
2350 code = GET_CODE (scan);
2351 if (GET_RTX_CLASS (code) == 'i')
2353 used |= regs_used (PATTERN (scan), 0);
2354 if (code == CALL_INSN)
2355 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
2356 dead |= (used >> 16) & ~used;
2362 if (code == JUMP_INSN)
2363 if (jump_left-- && simplejump_p (scan))
2364 scan = JUMP_LABEL (scan);
2369 /* Mask out the stack pointer again, in case it was
2370 the only 'free' register we have found. */
2373 /* If the immediate destination is still in range, check for possible
2374 threading with a jump beyond the delay slot insn.
2375 Don't check if we are called recursively; the jump has been or will be
2376 checked in a different invocation then. */
2378 else if (optimize && need_block >= 0)
2380 rtx next = next_active_insn (next_active_insn (dest));
2381 if (next && GET_CODE (next) == JUMP_INSN
2382 && GET_CODE (PATTERN (next)) == SET
2383 && recog_memoized (next) == CODE_FOR_jump)
2385 dest = JUMP_LABEL (next);
2387 && insn_addresses[INSN_UID (dest)] - addr + 4092U > 4092 + 4098)
2388 gen_block_redirect (next, insn_addresses[INSN_UID (next)], -1);
2394 rtx reg = gen_rtx (REG, SImode, exact_log2 (dead & -dead));
2396 /* It would be nice if we could convert the jump into an indirect
2397 jump / far branch right now, and thus exposing all constituent
2398 instructions to further optimization. However, reorg uses
2399 simplejump_p to determine if there is an unconditional jump where
2400 it should try to schedule instructions from the target of the
2401 branch; simplejump_p fails for indirect jumps even if they have
2403 rtx insn = emit_insn_before (gen_indirect_jump_scratch
2404 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
2406 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
2409 else if (need_block)
2410 /* We can't use JUMP_LABEL here because it might be undefined
2411 when not optimizing. */
2412 return emit_insn_before (gen_block_branch_redirect
2413 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
2418 #define CONDJUMP_MIN -252
2419 #define CONDJUMP_MAX 262
2422 /* A label (to be placed) in front of the jump
2423 that jumps to our ultimate destination. */
2425 /* Where we are going to insert it if we cannot move the jump any farther,
2426 or the jump itself if we have picked up an existing jump. */
2428 /* The ultimate destination. */
2430 struct far_branch *prev;
2431 /* If the branch has already been created, its address;
2432 else the address of its first prospective user. */
2436 enum mdep_reorg_phase_e mdep_reorg_phase;
2439 struct far_branch *bp;
2441 rtx insn = bp->insert_place;
2443 rtx label = gen_label_rtx ();
2445 emit_label_after (label, insn);
2448 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
2449 LABEL_NUSES (bp->far_label)++;
2452 jump = emit_jump_insn_after (gen_return (), insn);
2453 emit_label_after (bp->near_label, insn);
2454 JUMP_LABEL (jump) = bp->far_label;
2455 if (! invert_jump (insn, label))
2457 /* Prevent reorg from undoing our splits. */
2458 gen_block_redirect (jump, bp->address += 2, 2);
2461 /* Fix up ADDR_DIFF_VECs. */
2463 fixup_addr_diff_vecs (first)
2468 for (insn = first; insn; insn = NEXT_INSN (insn))
2470 rtx vec_lab, pat, prev, prevpat, x;
2472 if (GET_CODE (insn) != JUMP_INSN
2473 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
2475 pat = PATTERN (insn);
2476 vec_lab = XEXP (XEXP (pat, 0), 0);
2478 /* Search the matching casesi_jump_2. */
2479 for (prev = vec_lab; ; prev = PREV_INSN (prev))
2481 if (GET_CODE (prev) != JUMP_INSN)
2483 prevpat = PATTERN (prev);
2484 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
2486 x = XVECEXP (prevpat, 0, 1);
2487 if (GET_CODE (x) != USE)
2490 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
2493 /* Fix up the ADDR_DIF_VEC to be relative
2494 to the reference address of the braf. */
2495 XEXP (XEXP (pat, 0), 0)
2496 = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
2500 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
2501 a barrier. Return the base 2 logarithm of the desired alignment. */
2503 barrier_align (barrier_or_label)
2504 rtx barrier_or_label;
2506 rtx next = next_real_insn (barrier_or_label), pat, prev;
2512 pat = PATTERN (next);
2514 if (GET_CODE (pat) == ADDR_DIFF_VEC)
2517 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == 1)
2518 /* This is a barrier in front of a constant table. */
2521 prev = prev_real_insn (barrier_or_label);
2522 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
2524 pat = PATTERN (prev);
2525 /* If this is a very small table, we want to keep the alignment after
2526 the table to the minimum for proper code alignment. */
2527 return ((TARGET_SMALLCODE
2528 || (XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
2529 <= 1 << (CACHE_LOG - 2)))
2533 if (TARGET_SMALLCODE)
2536 if (! TARGET_SH3 || ! optimize)
2539 /* Check if there is an immediately preceding branch to the insn beyond
2540 the barrier. We must weight the cost of discarding useful information
2541 from the current cache line when executing this branch and there is
2542 an alignment, against that of fetching unneeded insn in front of the
2543 branch target when there is no alignment. */
2545 /* PREV is presumed to be the JUMP_INSN for the barrier under
2546 investigation. Skip to the insn before it. */
2547 prev = prev_real_insn (prev);
2549 for (slot = 2, credit = 1 << (CACHE_LOG - 2) + 2;
2550 credit >= 0 && prev && GET_CODE (prev) == INSN;
2551 prev = prev_real_insn (prev))
2553 if (GET_CODE (PATTERN (prev)) == USE
2554 || GET_CODE (PATTERN (prev)) == CLOBBER)
2556 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
2557 prev = XVECEXP (PATTERN (prev), 0, 1);
2559 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
2561 credit -= get_attr_length (prev);
2564 && GET_CODE (prev) == JUMP_INSN
2565 && JUMP_LABEL (prev)
2566 && next_real_insn (JUMP_LABEL (prev)) == next_real_insn (barrier_or_label)
2567 && (credit - slot >= (GET_CODE (SET_SRC (PATTERN (prev))) == PC ? 2 : 0)))
2573 /* Exported to toplev.c.
2575 Do a final pass over the function, just before delayed branch
2579 machine_dependent_reorg (first)
2584 rtx r0_rtx = gen_rtx (REG, Pmode, 0);
2585 rtx r0_inc_rtx = gen_rtx (POST_INC, Pmode, r0_rtx);
2587 /* If relaxing, generate pseudo-ops to associate function calls with
2588 the symbols they call. It does no harm to not generate these
2589 pseudo-ops. However, when we can generate them, it enables to
2590 linker to potentially relax the jsr to a bsr, and eliminate the
2591 register load and, possibly, the constant pool entry. */
2593 mdep_reorg_phase = SH_INSERT_USES_LABELS;
2596 /* Remove all REG_LABEL notes. We want to use them for our own
2597 purposes. This works because none of the remaining passes
2598 need to look at them.
2600 ??? But it may break in the future. We should use a machine
2601 dependent REG_NOTE, or some other approach entirely. */
2602 for (insn = first; insn; insn = NEXT_INSN (insn))
2604 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2608 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
2609 remove_note (insn, note);
2613 for (insn = first; insn; insn = NEXT_INSN (insn))
2615 rtx pattern, reg, link, set, scan, dies, label;
2616 int rescan = 0, foundinsn = 0;
2618 if (GET_CODE (insn) == CALL_INSN)
2620 pattern = PATTERN (insn);
2622 if (GET_CODE (pattern) == PARALLEL)
2623 pattern = XVECEXP (pattern, 0, 0);
2624 if (GET_CODE (pattern) == SET)
2625 pattern = SET_SRC (pattern);
2627 if (GET_CODE (pattern) != CALL
2628 || GET_CODE (XEXP (pattern, 0)) != MEM)
2631 reg = XEXP (XEXP (pattern, 0), 0);
2635 reg = sfunc_uses_reg (insn);
2640 if (GET_CODE (reg) != REG)
2643 /* This is a function call via REG. If the only uses of REG
2644 between the time that it is set and the time that it dies
2645 are in function calls, then we can associate all the
2646 function calls with the setting of REG. */
2648 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
2650 if (REG_NOTE_KIND (link) != 0)
2652 set = single_set (XEXP (link, 0));
2653 if (set && rtx_equal_p (reg, SET_DEST (set)))
2655 link = XEXP (link, 0);
2662 /* ??? Sometimes global register allocation will have
2663 deleted the insn pointed to by LOG_LINKS. Try
2664 scanning backward to find where the register is set. */
2665 for (scan = PREV_INSN (insn);
2666 scan && GET_CODE (scan) != CODE_LABEL;
2667 scan = PREV_INSN (scan))
2669 if (GET_RTX_CLASS (GET_CODE (scan)) != 'i')
2672 if (! reg_mentioned_p (reg, scan))
2675 if (noncall_uses_reg (reg, scan, &set))
2689 /* The register is set at LINK. */
2691 /* We can only optimize the function call if the register is
2692 being set to a symbol. In theory, we could sometimes
2693 optimize calls to a constant location, but the assembler
2694 and linker do not support that at present. */
2695 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
2696 && GET_CODE (SET_SRC (set)) != LABEL_REF)
2699 /* Scan forward from LINK to the place where REG dies, and
2700 make sure that the only insns which use REG are
2701 themselves function calls. */
2703 /* ??? This doesn't work for call targets that were allocated
2704 by reload, since there may not be a REG_DEAD note for the
2708 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
2712 /* Don't try to trace forward past a CODE_LABEL if we haven't
2713 seen INSN yet. Ordinarily, we will only find the setting insn
2714 in LOG_LINKS if it is in the same basic block. However,
2715 cross-jumping can insert code labels in between the load and
2716 the call, and can result in situations where a single call
2717 insn may have two targets depending on where we came from. */
2719 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
2722 if (GET_RTX_CLASS (GET_CODE (scan)) != 'i')
2725 /* Don't try to trace forward past a JUMP. To optimize
2726 safely, we would have to check that all the
2727 instructions at the jump destination did not use REG. */
2729 if (GET_CODE (scan) == JUMP_INSN)
2732 if (! reg_mentioned_p (reg, scan))
2735 if (noncall_uses_reg (reg, scan, &scanset))
2742 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
2744 /* There is a function call to this register other
2745 than the one we are checking. If we optimize
2746 this call, we need to rescan again below. */
2750 /* ??? We shouldn't have to worry about SCANSET here.
2751 We should just be able to check for a REG_DEAD note
2752 on a function call. However, the REG_DEAD notes are
2753 apparently not dependable around libcalls; c-torture
2754 execute/920501-2 is a test case. If SCANSET is set,
2755 then this insn sets the register, so it must have
2756 died earlier. Unfortunately, this will only handle
2757 the cases in which the register is, in fact, set in a
2760 /* ??? We shouldn't have to use FOUNDINSN here.
2761 However, the LOG_LINKS fields are apparently not
2762 entirely reliable around libcalls;
2763 newlib/libm/math/e_pow.c is a test case. Sometimes
2764 an insn will appear in LOG_LINKS even though it is
2765 not the most recent insn which sets the register. */
2769 || find_reg_note (scan, REG_DEAD, reg)))
2778 /* Either there was a branch, or some insn used REG
2779 other than as a function call address. */
2783 /* Create a code label, and put it in a REG_LABEL note on
2784 the insn which sets the register, and on each call insn
2785 which uses the register. In final_prescan_insn we look
2786 for the REG_LABEL notes, and output the appropriate label
2789 label = gen_label_rtx ();
2790 REG_NOTES (link) = gen_rtx (EXPR_LIST, REG_LABEL, label,
2792 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_LABEL, label,
2801 scan = NEXT_INSN (scan);
2803 && ((GET_CODE (scan) == CALL_INSN
2804 && reg_mentioned_p (reg, scan))
2805 || ((reg2 = sfunc_uses_reg (scan))
2806 && REGNO (reg2) == REGNO (reg))))
2807 REG_NOTES (scan) = gen_rtx (EXPR_LIST, REG_LABEL,
2808 label, REG_NOTES (scan));
2810 while (scan != dies);
2816 fixup_addr_diff_vecs (first);
2820 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
2821 shorten_branches (first);
2823 /* Scan the function looking for move instructions which have to be
2824 changed to pc-relative loads and insert the literal tables. */
2826 mdep_reorg_phase = SH_FIXUP_PCLOAD;
2827 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
2834 else if (GET_CODE (insn) == JUMP_INSN
2835 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2843 /* Some code might have been inserted between the mova and
2844 its ADDR_DIFF_VEC. Check if the mova is still in range. */
2845 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
2846 total += get_attr_length (scan);
2848 /* range of mova is 1020, add 4 because pc counts from address of
2849 second instruction after this one, subtract 2 in case pc is 2
2850 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
2851 cancels out with alignment effects of the mova itself. */
2854 /* Change the mova into a load, and restart scanning
2855 there. broken_move will then return true for mova. */
2856 SET_SRC (PATTERN (mova))
2857 = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
2858 INSN_CODE (mova) = -1;
2862 if (broken_move (insn))
2865 /* Scan ahead looking for a barrier to stick the constant table
2867 rtx barrier = find_barrier (num_mova, mova, insn);
2868 rtx last_float_move, last_float = 0, *last_float_addr;
2870 if (num_mova && ! mova_p (mova))
2872 /* find_barrier had to change the first mova into a
2873 pcload; thus, we have to start with this new pcload. */
2877 /* Now find all the moves between the points and modify them. */
2878 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
2880 if (GET_CODE (scan) == CODE_LABEL)
2882 if (broken_move (scan))
2884 rtx *patp = &PATTERN (scan), pat = *patp;
2889 enum machine_mode mode;
2891 if (GET_CODE (pat) == PARALLEL)
2892 patp = &XVECEXP (pat, 0, 0), pat = *patp;
2893 src = SET_SRC (pat);
2894 dst = SET_DEST (pat);
2895 mode = GET_MODE (dst);
2897 if (mode == SImode && hi_const (src))
2902 while (GET_CODE (dst) == SUBREG)
2904 offset += SUBREG_WORD (dst);
2905 dst = SUBREG_REG (dst);
2907 dst = gen_rtx (REG, HImode, REGNO (dst) + offset);
2910 if (GET_CODE (dst) == REG
2911 && ((REGNO (dst) >= FIRST_FP_REG
2912 && REGNO (dst) <= LAST_FP_REG)
2913 || REGNO (dst) == FPUL_REG))
2916 && reg_set_between_p (r0_rtx, last_float_move, scan))
2918 lab = add_constant (src, mode, last_float);
2920 emit_insn_before (gen_mova (lab), scan);
2922 *last_float_addr = r0_inc_rtx;
2923 last_float_move = scan;
2925 newsrc = gen_rtx (MEM, mode,
2926 (REGNO (dst) == FPUL_REG
2929 last_float_addr = &XEXP (newsrc, 0);
2933 lab = add_constant (src, mode, 0);
2934 newsrc = gen_rtx (MEM, mode,
2935 gen_rtx (LABEL_REF, VOIDmode, lab));
2937 RTX_UNCHANGING_P (newsrc) = 1;
2938 *patp = gen_rtx (SET, VOIDmode, dst, newsrc);
2939 INSN_CODE (scan) = -1;
2942 dump_table (barrier);
2947 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
2949 split_branches (first);
2951 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
2952 also has an effect on the register that holds the addres of the sfunc.
2953 Insert an extra dummy insn in front of each sfunc that pretends to
2954 use this register. */
2955 if (flag_delayed_branch)
2957 for (insn = first; insn; insn = NEXT_INSN (insn))
2959 rtx reg = sfunc_uses_reg (insn);
2963 emit_insn_before (gen_use_sfunc_addr (reg), insn);
2966 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
2970 get_dest_uid (label, max_uid)
2974 rtx dest = next_real_insn (label);
2977 /* This can happen for an undefined label. */
2979 dest_uid = INSN_UID (dest);
2980 /* If this is a newly created branch redirection blocking instruction,
2981 we cannot index the branch_uid or insn_addresses arrays with its
2982 uid. But then, we won't need to, because the actual destination is
2983 the following branch. */
2984 while (dest_uid >= max_uid)
2986 dest = NEXT_INSN (dest);
2987 dest_uid = INSN_UID (dest);
2989 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
2994 /* Split condbranches that are out of range. Also add clobbers for
2995 scratch registers that are needed in far jumps.
2996 We do this before delay slot scheduling, so that it can take our
2997 newly created instructions into account. It also allows us to
2998 find branches with common targets more easily. */
3001 split_branches (first)
3005 struct far_branch **uid_branch, *far_branch_list = 0;
3006 int max_uid = get_max_uid ();
3008 /* Find out which branches are out of range. */
3009 shorten_branches (first);
3011 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
3012 bzero ((char *) uid_branch, max_uid * sizeof *uid_branch);
3014 for (insn = first; insn; insn = NEXT_INSN (insn))
3015 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
3017 else if (INSN_DELETED_P (insn))
3019 /* Shorten_branches would split this instruction again,
3020 so transform it into a note. */
3021 PUT_CODE (insn, NOTE);
3022 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
3023 NOTE_SOURCE_FILE (insn) = 0;
3025 else if (GET_CODE (insn) == JUMP_INSN
3026 /* Don't mess with ADDR_DIFF_VEC */
3027 && (GET_CODE (PATTERN (insn)) == SET
3028 || GET_CODE (PATTERN (insn)) == RETURN))
3030 enum attr_type type = get_attr_type (insn);
3031 if (type == TYPE_CBRANCH)
3035 if (get_attr_length (insn) > 4)
3037 rtx src = SET_SRC (PATTERN (insn));
3038 rtx cond = XEXP (src, 0);
3039 rtx olabel = XEXP (XEXP (src, 1), 0);
3041 int addr = insn_addresses[INSN_UID (insn)];
3043 int dest_uid = get_dest_uid (olabel, max_uid);
3044 struct far_branch *bp = uid_branch[dest_uid];
3046 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
3047 the label if the LABEL_NUSES count drops to zero. There is
3048 always a jump_optimize pass that sets these values, but it
3049 proceeds to delete unreferenced code, and then if not
3050 optimizing, to un-delete the deleted instructions, thus
3051 leaving labels with too low uses counts. */
3054 JUMP_LABEL (insn) = olabel;
3055 LABEL_NUSES (olabel)++;
3059 bp = (struct far_branch *) alloca (sizeof *bp);
3060 uid_branch[dest_uid] = bp;
3061 bp->prev = far_branch_list;
3062 far_branch_list = bp;
3064 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
3065 LABEL_NUSES (bp->far_label)++;
3069 label = bp->near_label;
3070 if (! label && bp->address - addr >= CONDJUMP_MIN)
3072 rtx block = bp->insert_place;
3074 if (GET_CODE (PATTERN (block)) == RETURN)
3075 block = PREV_INSN (block);
3077 block = gen_block_redirect (block,
3079 label = emit_label_after (gen_label_rtx (),
3081 bp->near_label = label;
3083 else if (label && ! NEXT_INSN (label))
3084 if (addr + 2 - bp->address <= CONDJUMP_MAX)
3085 bp->insert_place = insn;
3087 gen_far_branch (bp);
3090 || NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN)
3092 bp->near_label = label = gen_label_rtx ();
3093 bp->insert_place = insn;
3096 if (! redirect_jump (insn, label))
3101 /* get_attr_length (insn) == 2 */
3102 /* Check if we have a pattern where reorg wants to redirect
3103 the branch to a label from an unconditional branch that
3105 /* We can't use JUMP_LABEL here because it might be undefined
3106 when not optimizing. */
3107 /* A syntax error might cause beyond to be NULL_RTX. */
3109 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
3113 && (GET_CODE (beyond) == JUMP_INSN
3114 || (GET_CODE (beyond = next_active_insn (beyond))
3116 && GET_CODE (PATTERN (beyond)) == SET
3117 && recog_memoized (beyond) == CODE_FOR_jump
3118 && ((insn_addresses[INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0))]
3119 - insn_addresses[INSN_UID (insn)] + 252U)
3121 gen_block_redirect (beyond,
3122 insn_addresses[INSN_UID (beyond)], 1);
3125 next = next_active_insn (insn);
3127 if ((GET_CODE (next) == JUMP_INSN
3128 || GET_CODE (next = next_active_insn (next)) == JUMP_INSN)
3129 && GET_CODE (PATTERN (next)) == SET
3130 && recog_memoized (next) == CODE_FOR_jump
3131 && ((insn_addresses[INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0))]
3132 - insn_addresses[INSN_UID (insn)] + 252U)
3134 gen_block_redirect (next, insn_addresses[INSN_UID (next)], 1);
3136 else if (type == TYPE_JUMP || type == TYPE_RETURN)
3138 int addr = insn_addresses[INSN_UID (insn)];
3141 struct far_branch *bp;
3143 if (type == TYPE_JUMP)
3145 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
3146 dest_uid = get_dest_uid (far_label, max_uid);
3149 /* Parse errors can lead to labels outside
3151 if (! NEXT_INSN (far_label))
3156 JUMP_LABEL (insn) = far_label;
3157 LABEL_NUSES (far_label)++;
3159 redirect_jump (insn, NULL_RTX);
3163 bp = uid_branch[dest_uid];
3166 bp = (struct far_branch *) alloca (sizeof *bp);
3167 uid_branch[dest_uid] = bp;
3168 bp->prev = far_branch_list;
3169 far_branch_list = bp;
3171 bp->far_label = far_label;
3173 LABEL_NUSES (far_label)++;
3175 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
3176 if (addr - bp->address <= CONDJUMP_MAX)
3177 emit_label_after (bp->near_label, PREV_INSN (insn));
3180 gen_far_branch (bp);
3186 bp->insert_place = insn;
3188 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
3190 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
3193 /* Generate all pending far branches,
3194 and free our references to the far labels. */
3195 while (far_branch_list)
3197 if (far_branch_list->near_label
3198 && ! NEXT_INSN (far_branch_list->near_label))
3199 gen_far_branch (far_branch_list);
3201 && far_branch_list->far_label
3202 && ! --LABEL_NUSES (far_branch_list->far_label))
3203 delete_insn (far_branch_list->far_label);
3204 far_branch_list = far_branch_list->prev;
3207 /* Instruction length information is no longer valid due to the new
3208 instructions that have been generated. */
3209 init_insn_lengths ();
3212 /* Dump out instruction addresses, which is useful for debugging the
3213 constant pool table stuff.
3215 If relaxing, output the label and pseudo-ops used to link together
3216 calls and the instruction which set the registers. */
3218 /* ??? This is unnecessary, and probably should be deleted. This makes
3219 the insn_addresses declaration above unnecessary. */
3221 /* ??? The addresses printed by this routine for insns are nonsense for
3222 insns which are inside of a sequence where none of the inner insns have
3223 variable length. This is because the second pass of shorten_branches
3224 does not bother to update them. */
3227 final_prescan_insn (insn, opvec, noperands)
3232 if (TARGET_DUMPISIZE)
3233 fprintf (asm_out_file, "\n! at %04x\n", insn_addresses[INSN_UID (insn)]);
3239 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
3244 pattern = PATTERN (insn);
3245 if (GET_CODE (pattern) == PARALLEL)
3246 pattern = XVECEXP (pattern, 0, 0);
3247 if (GET_CODE (pattern) == CALL
3248 || (GET_CODE (pattern) == SET
3249 && (GET_CODE (SET_SRC (pattern)) == CALL
3250 || get_attr_type (insn) == TYPE_SFUNC)))
3251 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
3252 CODE_LABEL_NUMBER (XEXP (note, 0)));
3253 else if (GET_CODE (pattern) == SET)
3254 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
3255 CODE_LABEL_NUMBER (XEXP (note, 0)));
3262 /* Dump out any constants accumulated in the final pass. These will
3263 will only be labels. */
3266 output_jump_label_table ()
3272 fprintf (asm_out_file, "\t.align 2\n");
3273 for (i = 0; i < pool_size; i++)
3275 pool_node *p = &pool_vector[i];
3277 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
3278 CODE_LABEL_NUMBER (p->label));
3279 output_asm_insn (".long %O0", &p->value);
3287 /* A full frame looks like:
3291 [ if current_function_anonymous_args
3304 local-0 <- fp points here. */
3306 /* Number of bytes pushed for anonymous args, used to pass information
3307 between expand_prologue and expand_epilogue. */
3309 static int extra_push;
3311 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register
3312 to be adjusted, and TEMP, if nonnegative, holds the register number
3313 of a general register that we may clobber. */
3316 output_stack_adjust (size, reg, temp)
3323 if (CONST_OK_FOR_I (size))
3324 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
3325 /* Try to do it with two partial adjustments; however, we must make
3326 sure that the stack is properly aligned at all times, in case
3327 an interrupt occurs between the two partial adjustments. */
3328 else if (CONST_OK_FOR_I (size / 2 & -4)
3329 && CONST_OK_FOR_I (size - (size / 2 & -4)))
3331 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size / 2 & -4)));
3332 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size - (size / 2 & -4))));
3338 /* If TEMP is invalid, we could temporarily save a general
3339 register to MACL. However, there is currently no need
3340 to handle this case, so just abort when we see it. */
3343 const_reg = gen_rtx (REG, SImode, temp);
3345 /* If SIZE is negative, subtract the positive value.
3346 This sometimes allows a constant pool entry to be shared
3347 between prologue and epilogue code. */
3350 emit_insn (gen_movsi (const_reg, GEN_INT (-size)));
3351 emit_insn (gen_subsi3 (reg, reg, const_reg));
3355 emit_insn (gen_movsi (const_reg, GEN_INT (size)));
3356 emit_insn (gen_addsi3 (reg, reg, const_reg));
3362 /* Output RTL to push register RN onto the stack. */
3369 if ((rn >= FIRST_FP_REG && rn <= LAST_FP_REG)
3371 x = gen_push_e (gen_rtx (REG, SFmode, rn));
3373 x = gen_push (gen_rtx (REG, SImode, rn));
3376 REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
3377 gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
3380 /* Output RTL to pop register RN from the stack. */
3387 if ((rn >= FIRST_FP_REG && rn <= LAST_FP_REG)
3389 x = gen_pop_e (gen_rtx (REG, SFmode, rn));
3391 x = gen_pop (gen_rtx (REG, SImode, rn));
3394 REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
3395 gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
3398 /* Generate code to push the regs specified in the mask. */
3401 push_regs (mask, mask2)
3406 /* Push PR last; this gives better latencies after the prologue, and
3407 candidates for the return delay slot when there are no general
3408 registers pushed. */
3409 for (i = 0; i < 32; i++)
3410 if (mask & (1 << i) && i != PR_REG)
3412 for (i = 32; i < FIRST_PSEUDO_REGISTER; i++)
3413 if (mask2 & (1 << (i - 32)))
3415 if (mask & (1 << PR_REG))
3419 /* Work out the registers which need to be saved, both as a mask and a
3420 count of saved words.
3422 If doing a pragma interrupt function, then push all regs used by the
3423 function, and if we call another function (we can tell by looking at PR),
3424 make sure that all the regs it clobbers are safe too. */
3427 calc_live_regs (count_ptr, live_regs_mask2)
3429 int *live_regs_mask2;
3432 int live_regs_mask = 0;
3435 *live_regs_mask2 = 0;
3436 for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--)
3438 if ((pragma_interrupt && ! pragma_trapa)
3439 ? (/* Need to save all the regs ever live. */
3440 (regs_ever_live[reg]
3441 || (call_used_regs[reg]
3442 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
3443 && regs_ever_live[PR_REG]))
3444 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
3445 && reg != RETURN_ADDRESS_POINTER_REGNUM
3446 && reg != T_REG && reg != GBR_REG)
3447 : (/* Only push those regs which are used and need to be saved. */
3448 regs_ever_live[reg] && ! call_used_regs[reg]))
3451 *live_regs_mask2 |= 1 << (reg - 32);
3453 live_regs_mask |= 1 << reg;
3459 return live_regs_mask;
3462 /* Code to generate prologue and epilogue sequences */
3465 sh_expand_prologue ()
3469 int live_regs_mask2;
3471 /* We have pretend args if we had an object sent partially in registers
3472 and partially on the stack, e.g. a large structure. */
3473 output_stack_adjust (-current_function_pretend_args_size,
3474 stack_pointer_rtx, 3);
3478 /* This is set by SETUP_VARARGS to indicate that this is a varargs
3479 routine. Clear it here so that the next function isn't affected. */
3480 if (current_function_anonymous_args)
3482 current_function_anonymous_args = 0;
3484 /* This is not used by the SH3E calling convention */
3487 /* Push arg regs as if they'd been provided by caller in stack. */
3488 for (i = 0; i < NPARM_REGS(SImode); i++)
3490 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
3491 if (i >= (NPARM_REGS(SImode)
3492 - current_function_args_info.arg_count[(int) SH_ARG_INT]
3501 /* If we're supposed to switch stacks at function entry, do so now. */
3503 emit_insn (gen_sp_switch_1 ());
3505 live_regs_mask = calc_live_regs (&d, &live_regs_mask2);
3506 push_regs (live_regs_mask, live_regs_mask2);
3508 output_stack_adjust (-get_frame_size (), stack_pointer_rtx, 3);
3510 if (frame_pointer_needed)
3511 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
3515 sh_expand_epilogue ()
3520 int live_regs_mask2;
3522 if (frame_pointer_needed)
3524 output_stack_adjust (get_frame_size (), frame_pointer_rtx, 7);
3526 /* We must avoid moving the stack pointer adjustment past code
3527 which reads from the local frame, else an interrupt could
3528 occur after the SP adjustment and clobber data in the local
3530 emit_insn (gen_blockage ());
3531 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
3533 else if (get_frame_size ())
3535 /* We must avoid moving the stack pointer adjustment past code
3536 which reads from the local frame, else an interrupt could
3537 occur after the SP adjustment and clobber data in the local
3539 emit_insn (gen_blockage ());
3540 output_stack_adjust (get_frame_size (), stack_pointer_rtx, 7);
3543 /* Pop all the registers. */
3545 live_regs_mask = calc_live_regs (&d, &live_regs_mask2);
3546 if (live_regs_mask & (1 << PR_REG))
3548 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3550 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
3551 if (j < 32 && (live_regs_mask & (1 << j)) && j != PR_REG)
3553 else if (j >= 32 && (live_regs_mask2 & (1 << (j - 32))))
3557 output_stack_adjust (extra_push + current_function_pretend_args_size,
3558 stack_pointer_rtx, 7);
3560 /* Switch back to the normal stack if necessary. */
3562 emit_insn (gen_sp_switch_2 ());
3565 /* Clear variables at function end. */
3568 function_epilogue (stream, size)
3572 trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
3573 sp_switch = NULL_RTX;
3577 sh_builtin_saveregs (arglist)
3580 tree fntype = TREE_TYPE (current_function_decl);
3581 /* First unnamed integer register. */
3582 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
3583 /* Number of integer registers we need to save. */
3584 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
3585 /* First unnamed SFmode float reg */
3586 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
3587 /* Number of SFmode float regs to save. */
3588 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
3589 int ptrsize = GET_MODE_SIZE (Pmode);
3590 rtx valist, regbuf, fpregs;
3593 /* Allocate block of memory for the regs. */
3594 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
3595 Or can assign_stack_local accept a 0 SIZE argument? */
3596 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
3598 regbuf = assign_stack_local (BLKmode, bufsize, 0);
3599 MEM_IN_STRUCT_P (regbuf) = 1;
3602 This is optimized to only save the regs that are necessary. Explicitly
3603 named args need not be saved. */
3605 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
3606 gen_rtx (MEM, BLKmode,
3607 plus_constant (XEXP (regbuf, 0),
3608 n_floatregs * UNITS_PER_WORD)),
3609 n_intregs, n_intregs * UNITS_PER_WORD);
3612 This is optimized to only save the regs that are necessary. Explicitly
3613 named args need not be saved.
3614 We explicitly build a pointer to the buffer because it halves the insn
3615 count when not optimizing (otherwise the pointer is built for each reg
3617 We emit the moves in reverse order so that we can use predecrement. */
3619 fpregs = gen_reg_rtx (Pmode);
3620 emit_move_insn (fpregs, XEXP (regbuf, 0));
3621 emit_insn (gen_addsi3 (fpregs, fpregs,
3622 GEN_INT (n_floatregs * UNITS_PER_WORD)));
3623 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
3625 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
3626 emit_move_insn (gen_rtx (MEM, SFmode, fpregs),
3627 gen_rtx (REG, SFmode, BASE_ARG_REG (SFmode) + regno));
3630 /* Return the address of the regbuf. */
3631 return XEXP (regbuf, 0);
3634 /* Define the offset between two registers, one to be eliminated, and
3635 the other its replacement, at the start of a routine. */
3638 initial_elimination_offset (from, to)
3643 int total_saved_regs_space;
3644 int total_auto_space = get_frame_size ();
3645 int save_flags = target_flags;
3647 int live_regs_mask, live_regs_mask2;
3648 live_regs_mask = calc_live_regs (®s_saved, &live_regs_mask2);
3649 target_flags = save_flags;
3651 total_saved_regs_space = (regs_saved) * 4;
3653 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
3654 return total_saved_regs_space + total_auto_space;
3656 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
3657 return total_saved_regs_space + total_auto_space;
3659 /* Initial gap between fp and sp is 0. */
3660 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
3663 if (from == RETURN_ADDRESS_POINTER_REGNUM
3664 && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
3666 int i, n = total_saved_regs_space;
3667 for (i = PR_REG-1; i >= 0; i--)
3668 if (live_regs_mask & (1 << i))
3670 return n + total_auto_space;
3676 /* Handle machine specific pragmas to be semi-compatible with Hitachi
3680 handle_pragma (file, t)
3685 register char *pname;
3687 if (TREE_CODE (t) != IDENTIFIER_NODE)
3690 pname = IDENTIFIER_POINTER (t);
3691 if (strcmp (pname, "interrupt") == 0)
3692 pragma_interrupt = retval = 1;
3693 else if (strcmp (pname, "trapa") == 0)
3694 pragma_interrupt = pragma_trapa = retval = 1;
3695 else if (strcmp (pname, "nosave_low_regs") == 0)
3696 pragma_nosave_low_regs = retval = 1;
3700 /* Return nonzero if ATTR is a valid attribute for DECL.
3701 ATTRIBUTES are any existing attributes and ARGS are the arguments
3704 Supported attributes:
3706 interrupt_handler -- specifies this function is an interrupt handler.
3708 sp_switch -- specifies an alternate stack for an interrupt handler
3711 trap_exit -- use a trapa to exit an interrupt function instead of
3712 an rte instruction. */
3715 sh_valid_machine_decl_attribute (decl, attributes, attr, args)
3723 if (TREE_CODE (decl) != FUNCTION_DECL)
3726 if (is_attribute_p ("interrupt_handler", attr))
3728 pragma_interrupt = 1;
3732 if (is_attribute_p ("sp_switch", attr))
3734 /* The sp_switch attribute only has meaning for interrupt functions. */
3735 if (!pragma_interrupt)
3738 /* sp_switch must have an argument. */
3739 if (!args || TREE_CODE (args) != TREE_LIST)
3742 /* The argument must be a constant string. */
3743 if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
3746 sp_switch = gen_rtx (SYMBOL_REF, VOIDmode,
3747 TREE_STRING_POINTER (TREE_VALUE (args)));
3751 if (is_attribute_p ("trap_exit", attr))
3753 /* The trap_exit attribute only has meaning for interrupt functions. */
3754 if (!pragma_interrupt)
3757 /* trap_exit must have an argument. */
3758 if (!args || TREE_CODE (args) != TREE_LIST)
3761 /* The argument must be a constant integer. */
3762 if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
3765 trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args));
3771 /* Predicates used by the templates. */
3773 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
3774 Used only in general_movsrc_operand. */
3777 system_reg_operand (op, mode)
3779 enum machine_mode mode;
3791 /* Returns 1 if OP can be source of a simple move operation.
3792 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
3793 invalid as are subregs of system registers. */
3796 general_movsrc_operand (op, mode)
3798 enum machine_mode mode;
3800 if (GET_CODE (op) == MEM)
3802 rtx inside = XEXP (op, 0);
3803 if (GET_CODE (inside) == CONST)
3804 inside = XEXP (inside, 0);
3806 if (GET_CODE (inside) == LABEL_REF)
3809 if (GET_CODE (inside) == PLUS
3810 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
3811 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
3814 /* Only post inc allowed. */
3815 if (GET_CODE (inside) == PRE_DEC)
3819 if ((mode == QImode || mode == HImode)
3820 && (GET_CODE (op) == SUBREG
3821 && GET_CODE (XEXP (op, 0)) == REG
3822 && system_reg_operand (XEXP (op, 0), mode)))
3825 return general_operand (op, mode);
3828 /* Returns 1 if OP can be a destination of a move.
3829 Same as general_operand, but no preinc allowed. */
3832 general_movdst_operand (op, mode)
3834 enum machine_mode mode;
3836 /* Only pre dec allowed. */
3837 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
3840 return general_operand (op, mode);
3843 /* Returns 1 if OP is a normal arithmetic register. */
3846 arith_reg_operand (op, mode)
3848 enum machine_mode mode;
3850 if (register_operand (op, mode))
3854 if (GET_CODE (op) == REG)
3856 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
3857 regno = REGNO (SUBREG_REG (op));
3861 return (regno != T_REG && regno != PR_REG && regno != FPUL_REG
3862 && regno != MACH_REG && regno != MACL_REG);
3867 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
3870 arith_operand (op, mode)
3872 enum machine_mode mode;
3874 if (arith_reg_operand (op, mode))
3877 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
3883 /* Returns 1 if OP is a valid source operand for a compare insn. */
3886 arith_reg_or_0_operand (op, mode)
3888 enum machine_mode mode;
3890 if (arith_reg_operand (op, mode))
3893 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_N (INTVAL (op)))
3899 /* Returns 1 if OP is a valid source operand for a logical operation. */
3902 logical_operand (op, mode)
3904 enum machine_mode mode;
3906 if (arith_reg_operand (op, mode))
3909 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
3915 /* Nonzero if OP is a floating point value with value 0.0. */
3918 fp_zero_operand (op)
3923 if (GET_MODE (op) != SFmode)
3926 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3927 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
3930 /* Nonzero if OP is a floating point value with value 1.0. */
3938 if (GET_MODE (op) != SFmode)
3941 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3942 return REAL_VALUES_EQUAL (r, dconst1);
3946 braf_label_ref_operand(op, mode)
3948 enum machine_mode mode;
3952 if (GET_CODE (op) != LABEL_REF)
3954 prev = prev_real_insn (XEXP (op, 0));
3955 if (GET_CODE (prev) != JUMP_INSN)
3957 prev = PATTERN (prev);
3958 if (GET_CODE (prev) != PARALLEL || XVECLEN (prev, 0) != 2)
3960 prev = XVECEXP (prev, 0, 0);
3961 if (GET_CODE (prev) != SET)
3963 prev = SET_SRC (prev);
3964 if (GET_CODE (prev) != PLUS || XEXP (prev, 1) != op)
3968 /* Return the destination address of a branch. */
3971 branch_dest (branch)
3974 rtx dest = SET_SRC (PATTERN (branch));
3977 if (GET_CODE (dest) == IF_THEN_ELSE)
3978 dest = XEXP (dest, 1);
3979 dest = XEXP (dest, 0);
3980 dest_uid = INSN_UID (dest);
3981 return insn_addresses[dest_uid];
3984 /* Return non-zero if REG is not used after INSN.
3985 We assume REG is a reload reg, and therefore does
3986 not live past labels. It may live past calls or jumps though. */
3988 reg_unused_after (reg, insn)
3995 /* If the reg is set by this instruction, then it is safe for our
3996 case. Disregard the case where this is a store to memory, since
3997 we are checking a register used in the store address. */
3998 set = single_set (insn);
3999 if (set && GET_CODE (SET_DEST (set)) != MEM
4000 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
4003 while (insn = NEXT_INSN (insn))
4005 code = GET_CODE (insn);
4008 /* If this is a label that existed before reload, then the register
4009 if dead here. However, if this is a label added by reorg, then
4010 the register may still be live here. We can't tell the difference,
4011 so we just ignore labels completely. */
4012 if (code == CODE_LABEL)
4017 if (code == JUMP_INSN)
4020 /* If this is a sequence, we must handle them all at once.
4021 We could have for instance a call that sets the target register,
4022 and a insn in a delay slot that uses the register. In this case,
4023 we must return 0. */
4024 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4029 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
4031 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
4032 rtx set = single_set (this_insn);
4034 if (GET_CODE (this_insn) == CALL_INSN)
4036 else if (GET_CODE (this_insn) == JUMP_INSN)
4038 if (INSN_ANNULLED_BRANCH_P (this_insn))
4043 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
4045 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
4047 if (GET_CODE (SET_DEST (set)) != MEM)
4053 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
4058 else if (code == JUMP_INSN)
4061 else if (GET_RTX_CLASS (code) == 'i')
4063 rtx set = single_set (insn);
4065 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
4067 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
4068 return GET_CODE (SET_DEST (set)) != MEM;
4069 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
4073 if (code == CALL_INSN && call_used_regs[REGNO (reg)])