1 /* Output routines for GCC for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
21 /* Contributed by Steve Chamberlain (sac@cygnus.com).
22 Improved by Jim Wilson (wilson@cygnus.com). */
31 #include "insn-flags.h"
34 #include "hard-reg-set.h"
36 #include "insn-attr.h"
38 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
39 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
41 /* ??? The pragma interrupt support will not work for SH3. */
42 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
43 output code for the next function appropriate for an interrupt handler. */
46 /* This is set by #pragma trapa, and is similar to the above, except that
47 the compiler doesn't emit code to preserve all registers. */
48 static int pragma_trapa;
50 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
51 which has a separate set of low regs for User and Supervisor modes.
52 This should only be used for the lowest level of interrupts. Higher levels
53 of interrupts must save the registers in case they themselves are
55 int pragma_nosave_low_regs;
57 /* This is used for communication between SETUP_INCOMING_VARARGS and
58 sh_expand_prologue. */
59 int current_function_anonymous_args;
61 /* Global variables from toplev.c and final.c that are used within, but
62 not declared in any header file. */
63 extern char *version_string;
64 extern int *insn_addresses;
66 /* Global variables for machine-dependent things. */
68 /* Which cpu are we scheduling for. */
69 enum processor_type sh_cpu;
71 /* Saved operands from the last compare to use when we generate an scc
77 /* Provides the class number of the smallest class containing
80 int regno_reg_class[FIRST_PSEUDO_REGISTER] =
82 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
83 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
84 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
85 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
86 GENERAL_REGS, PR_REGS, T_REGS, NO_REGS,
87 MAC_REGS, MAC_REGS, FPUL_REGS, NO_REGS,
88 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
89 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
90 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
91 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
94 /* Provide reg_class from a letter such as appears in the machine
97 enum reg_class reg_class_from_letter[] =
99 /* a */ NO_REGS, /* b */ NO_REGS, /* c */ NO_REGS, /* d */ NO_REGS,
100 /* e */ NO_REGS, /* f */ FP_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
101 /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ PR_REGS,
102 /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
103 /* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
104 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
105 /* y */ FPUL_REGS, /* z */ R0_REGS
108 /* Print the operand address in x to the stream. */
111 print_operand_address (stream, x)
115 switch (GET_CODE (x))
118 fprintf (stream, "@%s", reg_names[REGNO (x)]);
123 rtx base = XEXP (x, 0);
124 rtx index = XEXP (x, 1);
126 switch (GET_CODE (index))
129 fprintf (stream, "@(%d,%s)", INTVAL (index),
130 reg_names[REGNO (base)]);
134 fprintf (stream, "@(r0,%s)",
135 reg_names[MAX (REGNO (base), REGNO (index))]);
146 fprintf (stream, "@-%s", reg_names[REGNO (XEXP (x, 0))]);
150 fprintf (stream, "@%s+", reg_names[REGNO (XEXP (x, 0))]);
154 output_addr_const (stream, x);
159 /* Print operand x (an rtx) in assembler syntax to file stream
160 according to modifier code.
162 '.' print a .s if insn needs delay slot
163 '@' print rte or rts depending upon pragma interruptness
164 '#' output a nop if there is nothing to put in the delay slot
165 'O' print a constant without the #
166 'R' print the LSW of a dp value - changes if in little endian
167 'S' print the MSW of a dp value - changes if in little endian
168 'T' print the next word of a dp value - same as 'R' in big endian mode. */
171 print_operand (stream, x, code)
180 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
181 fprintf (stream, ".s");
184 if (pragma_interrupt)
185 fprintf (stream, "rte");
187 fprintf (stream, "rts");
190 /* Output a nop if there's nothing in the delay slot. */
191 if (dbr_sequence_length () == 0)
192 fprintf (stream, "\n\tnop");
195 output_addr_const (stream, x);
198 fputs (reg_names[REGNO (x) + LSW], (stream));
201 fputs (reg_names[REGNO (x) + MSW], (stream));
204 /* Next word of a double. */
205 switch (GET_CODE (x))
208 fputs (reg_names[REGNO (x) + 1], (stream));
211 print_operand_address (stream,
212 XEXP (adj_offsettable_operand (x, 4), 0));
217 switch (GET_CODE (x))
220 fputs (reg_names[REGNO (x)], (stream));
223 output_address (XEXP (x, 0));
227 output_addr_const (stream, x);
234 /* Emit code to perform a block move. Choose the best method.
236 OPERANDS[0] is the destination.
237 OPERANDS[1] is the source.
238 OPERANDS[2] is the size.
239 OPERANDS[3] is the alignment safe to use. */
242 expand_block_move (operands)
245 int align = INTVAL (operands[3]);
246 int constp = (GET_CODE (operands[2]) == CONST_INT);
247 int bytes = (constp ? INTVAL (operands[2]) : 0);
249 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
250 alignment, or if it isn't a multiple of 4 bytes, then fail. */
251 if (! constp || align < 4 || (bytes % 4 != 0))
259 rtx r4 = gen_rtx (REG, SImode, 4);
260 rtx r5 = gen_rtx (REG, SImode, 5);
262 sprintf (entry, "__movstrSI%d", bytes);
263 entry_name = get_identifier (entry);
266 = copy_to_mode_reg (Pmode,
267 gen_rtx (SYMBOL_REF, Pmode,
268 IDENTIFIER_POINTER (entry_name)));
269 emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
270 emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
271 emit_insn (gen_block_move_real (func_addr_rtx));
275 /* This is the same number of bytes as a memcpy call, but to a different
276 less common function name, so this will occasionally use more space. */
277 if (! TARGET_SMALLCODE)
281 int final_switch, while_loop;
282 rtx r4 = gen_rtx (REG, SImode, 4);
283 rtx r5 = gen_rtx (REG, SImode, 5);
284 rtx r6 = gen_rtx (REG, SImode, 6);
286 entry_name = get_identifier ("__movstr");
288 = copy_to_mode_reg (Pmode,
289 gen_rtx (SYMBOL_REF, Pmode,
290 IDENTIFIER_POINTER (entry_name)));
291 emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
292 emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
294 /* r6 controls the size of the move. 16 is decremented from it
295 for each 64 bytes moved. Then the negative bit left over is used
296 as an index into a list of move instructions. e.g., a 72 byte move
297 would be set up with size(r6) = 14, for one iteration through the
298 big while loop, and a switch of -2 for the last part. */
300 final_switch = 16 - ((bytes / 4) % 16);
301 while_loop = ((bytes / 4) / 16 - 1) * 16;
302 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
303 emit_insn (gen_block_lump_real (func_addr_rtx));
310 /* Prepare operands for a move define_expand; specifically, one of the
311 operands must be in a register. */
314 prepare_move_operands (operands, mode)
316 enum machine_mode mode;
318 if (! reload_in_progress && ! reload_completed)
320 /* Copy the source to a register if both operands aren't registers. */
321 if (! register_operand (operands[0], mode)
322 && ! register_operand (operands[1], mode))
323 operands[1] = copy_to_mode_reg (mode, operands[1]);
325 /* This case can happen while generating code to move the result
326 of a library call to the target. Reject `st r0,@(rX,rY)' because
327 reload will fail to find a spill register for rX, since r0 is already
328 being used for the source. */
329 else if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 0
330 && GET_CODE (operands[0]) == MEM
331 && GET_CODE (XEXP (operands[0], 0)) == PLUS
332 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
333 operands[1] = copy_to_mode_reg (mode, operands[1]);
339 /* Prepare the operands for an scc instruction; make sure that the
340 compare has been done. */
342 prepare_scc_operands (code)
345 rtx t_reg = gen_rtx (REG, SImode, T_REG);
346 enum rtx_code oldcode = code;
347 enum machine_mode mode;
349 /* First need a compare insn. */
353 /* It isn't possible to handle this case. */
370 rtx tmp = sh_compare_op0;
371 sh_compare_op0 = sh_compare_op1;
372 sh_compare_op1 = tmp;
375 mode = GET_MODE (sh_compare_op0);
376 if (mode == VOIDmode)
377 mode = GET_MODE (sh_compare_op1);
379 sh_compare_op0 = force_reg (mode, sh_compare_op0);
380 if (code != EQ && code != NE
381 && (sh_compare_op1 != const0_rtx
382 || code == GTU || code == GEU || code == LTU || code == LEU))
383 sh_compare_op1 = force_reg (mode, sh_compare_op1);
385 /* ??? This should be `mode' not `SImode' in the compare, but that would
386 require fixing the branch patterns too. */
387 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
388 gen_rtx (code, SImode, sh_compare_op0,
394 /* Called from the md file, set up the operands of a compare instruction. */
397 from_compare (operands, code)
401 if (code != EQ && code != NE)
403 enum machine_mode mode = GET_MODE (sh_compare_op0);
404 if (mode == VOIDmode)
405 mode = GET_MODE (sh_compare_op1);
407 /* Force args into regs, since we can't use constants here. */
408 sh_compare_op0 = force_reg (mode, sh_compare_op0);
409 if (sh_compare_op1 != const0_rtx
410 || code == GTU || code == GEU || code == LTU || code == LEU)
411 sh_compare_op1 = force_reg (mode, sh_compare_op1);
413 operands[1] = sh_compare_op0;
414 operands[2] = sh_compare_op1;
417 /* Functions to output assembly code. */
419 /* Return a sequence of instructions to perform DI or DF move.
421 Since the SH cannot move a DI or DF in one instruction, we have
422 to take care when we see overlapping source and dest registers. */
425 output_movedouble (insn, operands, mode)
428 enum machine_mode mode;
430 rtx dst = operands[0];
431 rtx src = operands[1];
433 if (GET_CODE (dst) == MEM
434 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
435 return "mov.l %T1,%0\n\tmov.l %1,%0";
437 if (register_operand (dst, mode)
438 && register_operand (src, mode))
440 if (REGNO (src) == MACH_REG)
441 return "sts mach,%S0\n\tsts macl,%R0";
443 /* When mov.d r1,r2 do r2->r3 then r1->r2;
444 when mov.d r1,r0 do r1->r0 then r2->r1. */
446 if (REGNO (src) + 1 == REGNO (dst))
447 return "mov %T1,%T0\n\tmov %1,%0";
449 return "mov %1,%0\n\tmov %T1,%T0";
451 else if (GET_CODE (src) == CONST_INT)
453 if (INTVAL (src) < 0)
454 output_asm_insn ("mov #-1,%S0", operands);
456 output_asm_insn ("mov #0,%S0", operands);
460 else if (GET_CODE (src) == MEM)
463 int dreg = REGNO (dst);
464 rtx inside = XEXP (src, 0);
466 if (GET_CODE (inside) == REG)
467 ptrreg = REGNO (inside);
468 else if (GET_CODE (inside) == SUBREG)
469 ptrreg = REGNO (SUBREG_REG (inside)) + SUBREG_WORD (inside);
470 else if (GET_CODE (inside) == PLUS)
472 ptrreg = REGNO (XEXP (inside, 0));
473 /* ??? A r0+REG address shouldn't be possible here, because it isn't
474 an offsettable address. Unfortunately, offsettable addresses use
475 QImode to check the offset, and a QImode offsettable address
476 requires r0 for the other operand, which is not currently
477 supported, so we can't use the 'o' constraint.
478 Thus we must check for and handle r0+REG addresses here.
479 We punt for now, since this is likely very rare. */
480 if (GET_CODE (XEXP (inside, 1)) == REG)
483 else if (GET_CODE (inside) == LABEL_REF)
484 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
485 else if (GET_CODE (inside) == POST_INC)
486 return "mov.l %1,%0\n\tmov.l %1,%T0";
490 /* Work out the safe way to copy. Copy into the second half first. */
492 return "mov.l %T1,%T0\n\tmov.l %1,%0";
495 return "mov.l %1,%0\n\tmov.l %T1,%T0";
498 /* Print an instruction which would have gone into a delay slot after
499 another instruction, but couldn't because the other instruction expanded
500 into a sequence where putting the slot insn at the end wouldn't work. */
506 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
508 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
511 /* We can't tell if we need a register as a scratch for the jump
512 until after branch shortening, and then it's too late to allocate a
513 register the 'proper' way. These instruction sequences are rare
514 anyway, so to avoid always using a reg up from our limited set, we'll
515 grab one when we need one on output. */
517 /* ??? Should fix compiler so that using a clobber scratch in jump
518 instructions works, and then this will be unnecessary. */
521 output_far_jump (insn, op)
525 rtx thislab = gen_label_rtx ();
527 /* Output the delay slot insn first if any. */
528 if (dbr_sequence_length ())
529 print_slot (final_sequence);
531 output_asm_insn ("mov.l r13,@-r15", 0);
532 output_asm_insn ("mov.l %O0,r13", &thislab);
533 output_asm_insn ("jmp @r13", 0);
534 output_asm_insn ("mov.l @r15+,r13", 0);
535 output_asm_insn (".align 2", 0);
536 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (thislab));
537 output_asm_insn (".long %O0", &op);
541 /* Local label counter, used for constants in the pool and inside
546 /* Output code for ordinary branches. */
549 output_branch (logic, insn, operands)
555 int length = get_attr_length (insn);
558 /* Undo the effects of ADJUST_INSN_LENGTH, so that we get the real
560 adjusted_length = length;
561 ADJUST_INSN_LENGTH (insn, adjusted_length);
562 length -= (adjusted_length - length);
567 /* A branch with an unfilled delay slot. */
569 /* Simple branch in range -252..+258 bytes */
570 return logic ? "bt%. %l0" : "bf%. %l0";
573 /* A branch with an unfilled delay slot. */
575 /* Branch in range -4092..+4098 bytes. */
577 /* The call to print_slot will clobber the operands. */
578 rtx op0 = operands[0];
580 /* If the instruction in the delay slot is annulled (true), then
581 there is no delay slot where we can put it now. The only safe
582 place for it is after the label. */
586 fprintf (asm_out_file, "\tb%c%s\tLF%d\n", logic ? 'f' : 't',
587 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
589 if (! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
590 print_slot (final_sequence);
593 fprintf (asm_out_file, "\tb%c\tLF%d\n", logic ? 'f' : 't', label);
595 output_asm_insn ("bra %l0", &op0);
596 fprintf (asm_out_file, "\tnop\n");
597 fprintf (asm_out_file, "LF%d:\n", label);
600 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
601 print_slot (final_sequence);
606 /* A branch with an unfilled delay slot. */
608 /* Branches a long way away. */
610 /* The call to print_slot will clobber the operands. */
611 rtx op0 = operands[0];
613 /* If the instruction in the delay slot is annulled (true), then
614 there is no delay slot where we can put it now. The only safe
615 place for it is after the label. */
619 fprintf (asm_out_file, "\tb%c%s\tLF%d\n", logic ? 'f' : 't',
620 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
622 if (! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
623 print_slot (final_sequence);
626 fprintf (asm_out_file, "\tb%c\tLF%d\n", logic ? 'f' : 't', label);
628 output_far_jump (insn, op0);
629 fprintf (asm_out_file, "LF%d:\n", label);
632 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
633 print_slot (final_sequence);
641 /* Output to FILE the start of the assembler file. */
644 output_file_start (file)
649 output_file_directive (file, main_input_filename);
651 /* Switch to the data section so that the coffsem symbol and the
652 gcc2_compiled. symbol aren't in the text section. */
655 if (TARGET_LITTLE_ENDIAN)
656 fprintf (file, "\t.little\n");
659 /* Actual number of instructions used to make a shift by N. */
660 static char ashiftrt_insns[] =
661 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
663 /* Left shift and logical right shift are the same. */
664 static char shift_insns[] =
665 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
667 /* Individual shift amounts needed to get the above length sequences.
668 One bit right shifts clobber the T bit, so when possible, put one bit
669 shifts in the middle of the sequence, so the ends are eligible for
670 branch delay slots. */
671 static short shift_amounts[32][5] = {
672 {0}, {1}, {2}, {2, 1},
673 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
674 {8}, {8, 1}, {8, 2}, {8, 1, 2},
675 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
676 {16}, {16, 1}, {16, 2}, {16, 1, 2},
677 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
678 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
679 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
681 /* This is used in length attributes in sh.md to help compute the length
682 of arbitrary constant shift instructions. */
685 shift_insns_rtx (insn)
688 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
689 int shift_count = INTVAL (XEXP (set_src, 1));
690 enum rtx_code shift_code = GET_CODE (set_src);
695 return ashiftrt_insns[shift_count];
698 return shift_insns[shift_count];
704 /* Return the cost of a shift. */
710 int value = INTVAL (XEXP (x, 1));
712 /* If shift by a non constant, then this will be expensive. */
713 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
717 /* If not an sh3 then we don't even have an instruction for it. */
721 /* Otherwise, return the true cost in instructions. */
722 if (GET_CODE (x) == ASHIFTRT)
724 int cost = ashiftrt_insns[value];
725 /* If SH3, then we put the constant in a reg and use shad. */
726 if (TARGET_SH3 && cost > 3)
731 return shift_insns[value];
734 /* Return the cost of an AND operation. */
742 /* Anding with a register is a single cycle and instruction. */
743 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
746 i = INTVAL (XEXP (x, 1));
747 /* These constants are single cycle extu.[bw] instructions. */
748 if (i == 0xff || i == 0xffff)
750 /* Constants that can be used in an and immediate instruction is a single
751 cycle, but this requires r0, so make it a little more expensive. */
752 if (CONST_OK_FOR_L (i))
754 /* Constants that can be loaded with a mov immediate and an and.
755 This case is probably unnecessary. */
756 if (CONST_OK_FOR_I (i))
758 /* Any other constants requires a 2 cycle pc-relative load plus an and.
759 This case is probably unnecessary. */
763 /* Return the cost of a multiply. */
770 /* We have a mul insn, so we can never take more than the mul and the
771 read of the mac reg, but count more because of the latency and extra
773 if (TARGET_SMALLCODE)
778 /* If we're aiming at small code, then just count the number of
779 insns in a multiply call sequence. */
780 if (TARGET_SMALLCODE)
783 /* Otherwise count all the insns in the routine we'd be calling too. */
787 /* Code to expand a shift. */
790 gen_ashift (type, n, reg)
795 /* Negative values here come from the shift_amounts array. */
808 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
812 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
814 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
817 emit_insn (gen_ashlsi3_k (reg, reg, GEN_INT (n)));
822 /* Output RTL to split a constant shift into its component SH constant
823 shift instructions. */
826 gen_shifty_op (code, operands)
830 int value = INTVAL (operands[2]);
833 /* Truncate the shift count in case it is out of bounds. */
834 value = value & 0x1f;
838 if (code == LSHIFTRT)
840 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
841 emit_insn (gen_movt (operands[0]));
844 else if (code == ASHIFT)
846 /* There is a two instruction sequence for 31 bit left shifts,
847 but it requires r0. */
848 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
850 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
851 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
858 /* This can happen when not optimizing. We must output something here
859 to prevent the compiler from aborting in final.c after the try_split
861 emit_insn (gen_nop ());
865 max = shift_insns[value];
866 for (i = 0; i < max; i++)
867 gen_ashift (code, shift_amounts[value][i], operands[0]);
870 /* Output RTL for an arithmetic right shift. */
872 /* ??? Rewrite to use super-optimizer sequences. */
875 expand_ashiftrt (operands)
885 if (GET_CODE (operands[2]) != CONST_INT)
887 rtx count = copy_to_mode_reg (SImode, operands[2]);
888 emit_insn (gen_negsi2 (count, count));
889 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
892 else if (ashiftrt_insns[INTVAL (operands[2])] > 3)
894 rtx count = force_reg (SImode, GEN_INT (- INTVAL (operands[2])));
895 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
899 if (GET_CODE (operands[2]) != CONST_INT)
902 value = INTVAL (operands[2]);
906 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
909 else if (value >= 16 && value <= 19)
911 wrk = gen_reg_rtx (SImode);
912 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
915 gen_ashift (ASHIFTRT, 1, wrk);
916 emit_move_insn (operands[0], wrk);
919 /* Expand a short sequence inline, longer call a magic routine. */
922 wrk = gen_reg_rtx (SImode);
923 emit_move_insn (wrk, operands[1]);
925 gen_ashift (ASHIFTRT, 1, wrk);
926 emit_move_insn (operands[0], wrk);
930 wrk = gen_reg_rtx (Pmode);
932 /* Load the value into an arg reg and call a helper. */
933 emit_move_insn (gen_rtx (REG, SImode, 4), operands[1]);
934 sprintf (func, "__ashiftrt_r4_%d", value);
935 func_name = get_identifier (func);
936 emit_move_insn (wrk, gen_rtx (SYMBOL_REF, Pmode,
937 IDENTIFIER_POINTER (func_name)));
938 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
939 emit_move_insn (operands[0], gen_rtx (REG, SImode, 4));
943 /* The SH cannot load a large constant into a register, constants have to
944 come from a pc relative load. The reference of a pc relative load
945 instruction must be less than 1k infront of the instruction. This
946 means that we often have to dump a constant inside a function, and
947 generate code to branch around it.
949 It is important to minimize this, since the branches will slow things
950 down and make things bigger.
952 Worst case code looks like:
970 We fix this by performing a scan before scheduling, which notices which
971 instructions need to have their operands fetched from the constant table
972 and builds the table.
976 scan, find an instruction which needs a pcrel move. Look forward, find the
977 last barrier which is within MAX_COUNT bytes of the requirement.
978 If there isn't one, make one. Process all the instructions between
979 the find and the barrier.
981 In the above example, we can tell that L3 is within 1k of L1, so
982 the first move can be shrunk from the 3 insn+constant sequence into
983 just 1 insn, and the constant moved to L3 to make:
994 Then the second move becomes the target for the shortening process. */
998 rtx value; /* Value in table. */
999 rtx label; /* Label of value. */
1000 enum machine_mode mode; /* Mode of value. */
1003 /* The maximum number of constants that can fit into one pool, since
1004 the pc relative range is 0...1020 bytes and constants are at least 4
1007 #define MAX_POOL_SIZE (1020/4)
1008 static pool_node pool_vector[MAX_POOL_SIZE];
1009 static int pool_size;
1011 /* ??? If we need a constant in HImode which is the truncated value of a
1012 constant we need in SImode, we could combine the two entries thus saving
1013 two bytes. Is this common enough to be worth the effort of implementing
1016 /* ??? This stuff should be done at the same time that we shorten branches.
1017 As it is now, we must assume that all branches are the maximum size, and
1018 this causes us to almost always output constant pools sooner than
1021 /* Add a constant to the pool and return its label. */
1024 add_constant (x, mode)
1026 enum machine_mode mode;
1031 /* First see if we've already got it. */
1032 for (i = 0; i < pool_size; i++)
1034 if (x->code == pool_vector[i].value->code
1035 && mode == pool_vector[i].mode)
1037 if (x->code == CODE_LABEL)
1039 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
1042 if (rtx_equal_p (x, pool_vector[i].value))
1043 return pool_vector[i].label;
1047 /* Need a new one. */
1048 pool_vector[pool_size].value = x;
1049 lab = gen_label_rtx ();
1050 pool_vector[pool_size].mode = mode;
1051 pool_vector[pool_size].label = lab;
1056 /* Output the literal table. */
1065 /* Do two passes, first time dump out the HI sized constants. */
1067 for (i = 0; i < pool_size; i++)
1069 pool_node *p = &pool_vector[i];
1071 if (p->mode == HImode)
1075 scan = emit_insn_after (gen_align_2 (), scan);
1078 scan = emit_label_after (p->label, scan);
1079 scan = emit_insn_after (gen_consttable_2 (p->value), scan);
1085 for (i = 0; i < pool_size; i++)
1087 pool_node *p = &pool_vector[i];
1097 scan = emit_label_after (gen_label_rtx (), scan);
1098 scan = emit_insn_after (gen_align_4 (), scan);
1100 scan = emit_label_after (p->label, scan);
1101 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
1107 scan = emit_label_after (gen_label_rtx (), scan);
1108 scan = emit_insn_after (gen_align_4 (), scan);
1110 scan = emit_label_after (p->label, scan);
1111 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
1119 scan = emit_insn_after (gen_consttable_end (), scan);
1120 scan = emit_barrier_after (scan);
1124 /* Return non-zero if constant would be an ok source for a
1125 mov.w instead of a mov.l. */
1131 return (GET_CODE (src) == CONST_INT
1132 && INTVAL (src) >= -32768
1133 && INTVAL (src) <= 32767);
1136 /* Non-zero if the insn is a move instruction which needs to be fixed. */
1138 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
1139 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
1140 need to fix it if the input value is CONST_OK_FOR_I. */
1146 if (GET_CODE (insn) == INSN
1147 && GET_CODE (PATTERN (insn)) == SET
1148 /* We can load any 8 bit value if we don't care what the high
1149 order bits end up as. */
1150 && GET_MODE (SET_DEST (PATTERN (insn))) != QImode
1151 && CONSTANT_P (SET_SRC (PATTERN (insn)))
1152 && ! (GET_CODE (SET_SRC (PATTERN (insn))) == CONST_DOUBLE
1153 && (fp_zero_operand (SET_SRC (PATTERN (insn)))
1154 || fp_one_operand (SET_SRC (PATTERN (insn))))
1155 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
1156 && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_FP_REG
1157 && REGNO (SET_DEST (PATTERN (insn))) <= LAST_FP_REG)
1158 && (GET_CODE (SET_SRC (PATTERN (insn))) != CONST_INT
1159 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (PATTERN (insn))))))
1165 /* Find the last barrier from insn FROM which is close enough to hold the
1166 constant pool. If we can't find one, then create one near the end of
1169 /* ??? It would be good to put constant pool tables between a case jump and
1170 the jump table. This fails for two reasons. First, there is no
1171 barrier after the case jump. This is a bug in the casesi pattern.
1172 Second, inserting the table here may break the mova instruction that
1173 loads the jump table address, by moving the jump table too far away.
1174 We fix that problem by never outputting the constant pool between a mova
1185 rtx found_barrier = 0;
1190 /* For HImode: range is 510, add 4 because pc counts from address of
1191 second instruction after this one, subtract 2 for the jump instruction
1192 that we may need to emit before the table, subtract 2 for the instruction
1193 that fills the jump delay slot (in very rare cases, reorg will take an
1194 instruction from after the constant pool or will leave the delay slot
1195 empty). This gives 510.
1196 For SImode: range is 1020, add 4 because pc counts from address of
1197 second instruction after this one, subtract 2 in case pc is 2 byte
1198 aligned, subtract 2 for the jump instruction that we may need to emit
1199 before the table, subtract 2 for the instruction that fills the jump
1200 delay slot. This gives 1018. */
1202 /* If not optimizing, then it is possible that the jump instruction we add
1203 won't be shortened, and thus will have a length of 14 instead of 2.
1204 We must adjust the limits downwards to account for this, giving a limit
1205 of 1008 for SImode and 500 for HImode. */
1218 /* If not optimizing for space, then the constant pool will be
1219 aligned to a 4 to 16 byte boundary. We must make room for that
1220 alignment that by reducing the limits.
1221 ??? It would be better to not align the constant pool, but
1222 ASM_OUTPUT_ALIGN_CODE does not make any provision for basing the
1223 alignment on the instruction. */
1225 if (! TARGET_SMALLCODE)
1227 if (TARGET_SH3 || TARGET_SH3E)
1239 while (from && count_si < si_limit && count_hi < hi_limit)
1241 int inc = get_attr_length (from);
1243 if (GET_CODE (from) == BARRIER)
1244 found_barrier = from;
1246 if (broken_move (from))
1248 rtx pat = PATTERN (from);
1249 rtx src = SET_SRC (pat);
1250 rtx dst = SET_DEST (pat);
1251 enum machine_mode mode = GET_MODE (dst);
1253 /* We must explicitly check the mode, because sometimes the
1254 front end will generate code to load unsigned constants into
1255 HImode targets without properly sign extending them. */
1256 if (mode == HImode || (mode == SImode && hi_const (src)))
1259 /* We put the short constants before the long constants, so
1260 we must count the length of short constants in the range
1261 for the long constants. */
1262 /* ??? This isn't optimal, but is easy to do. */
1270 if (GET_CODE (from) == INSN
1271 && GET_CODE (PATTERN (from)) == SET
1272 && GET_CODE (SET_SRC (PATTERN (from))) == UNSPEC
1273 && XINT (SET_SRC (PATTERN (from)), 1) == 1)
1275 else if (GET_CODE (from) == JUMP_INSN
1276 && (GET_CODE (PATTERN (from)) == ADDR_VEC
1277 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
1284 from = NEXT_INSN (from);
1287 /* Insert the constant pool table before the mova instruction, to prevent
1288 the mova label reference from going out of range. */
1292 if (! found_barrier)
1294 /* We didn't find a barrier in time to dump our stuff,
1295 so we'll make one. */
1296 rtx label = gen_label_rtx ();
1298 /* If we exceeded the range, then we must back up over the last
1299 instruction we looked at. Otherwise, we just need to undo the
1300 NEXT_INSN at the end of the loop. */
1301 if (count_hi > hi_limit || count_si > si_limit)
1302 from = PREV_INSN (PREV_INSN (from));
1304 from = PREV_INSN (from);
1306 /* Walk back to be just before any jump or label.
1307 Putting it before a label reduces the number of times the branch
1308 around the constant pool table will be hit. Putting it before
1309 a jump makes it more likely that the bra delay slot will be
1311 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
1312 || GET_CODE (from) == CODE_LABEL)
1313 from = PREV_INSN (from);
1315 from = emit_jump_insn_after (gen_jump (label), from);
1316 JUMP_LABEL (from) = label;
1317 LABEL_NUSES (label) = 1;
1318 found_barrier = emit_barrier_after (from);
1319 emit_label_after (label, found_barrier);
1322 return found_barrier;
1325 /* See if the only way in which INSN uses REG is by calling it, or by
1326 setting it while calling it. Set *SET to a SET rtx if the register
1330 noncall_uses_reg (reg, insn, set)
1339 if (GET_CODE (insn) != CALL_INSN)
1341 /* We don't use rtx_equal_p because we don't care if the mode is
1343 pattern = single_set (insn);
1345 && GET_CODE (SET_DEST (pattern)) == REG
1346 && REGNO (reg) == REGNO (SET_DEST (pattern)))
1355 pattern = PATTERN (insn);
1357 if (GET_CODE (pattern) == PARALLEL)
1361 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
1362 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
1364 pattern = XVECEXP (pattern, 0, 0);
1367 if (GET_CODE (pattern) == SET)
1369 if (reg_mentioned_p (reg, SET_DEST (pattern)))
1371 /* We don't use rtx_equal_p, because we don't care if the
1372 mode is different. */
1373 if (GET_CODE (SET_DEST (pattern)) != REG
1374 || REGNO (reg) != REGNO (SET_DEST (pattern)))
1380 pattern = SET_SRC (pattern);
1383 if (GET_CODE (pattern) != CALL
1384 || GET_CODE (XEXP (pattern, 0)) != MEM
1385 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
1391 /* Exported to toplev.c.
1393 Do a final pass over the function, just before delayed branch
1397 machine_dependent_reorg (first)
1402 /* If relaxing, generate pseudo-ops to associate function calls with
1403 the symbols they call. It does no harm to not generate these
1404 pseudo-ops. However, when we can generate them, it enables to
1405 linker to potentially relax the jsr to a bsr, and eliminate the
1406 register load and, possibly, the constant pool entry. */
1410 /* Remove all REG_LABEL notes. We want to use them for our own
1411 purposes. This works because none of the remaining passes
1412 need to look at them.
1414 ??? But it may break in the future. We should use a machine
1415 dependent REG_NOTE, or some other approach entirely. */
1416 for (insn = first; insn; insn = NEXT_INSN (insn))
1418 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1422 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
1423 remove_note (insn, note);
1427 for (insn = first; insn; insn = NEXT_INSN (insn))
1429 rtx pattern, reg, link, set, scan, dies, label;
1430 int rescan = 0, foundinsn = 0;
1432 if (GET_CODE (insn) != CALL_INSN)
1435 pattern = PATTERN (insn);
1437 if (GET_CODE (pattern) == PARALLEL)
1438 pattern = XVECEXP (pattern, 0, 0);
1439 if (GET_CODE (pattern) == SET)
1440 pattern = SET_SRC (pattern);
1442 if (GET_CODE (pattern) != CALL
1443 || GET_CODE (XEXP (pattern, 0)) != MEM)
1446 reg = XEXP (XEXP (pattern, 0), 0);
1447 if (GET_CODE (reg) != REG)
1450 /* This is a function call via REG. If the only uses of REG
1451 between the time that it is set and the time that it dies
1452 are in function calls, then we can associate all the
1453 function calls with the setting of REG. */
1455 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1457 set = single_set (XEXP (link, 0));
1458 if (set && rtx_equal_p (reg, SET_DEST (set)))
1460 link = XEXP (link, 0);
1467 /* ??? Sometimes global register allocation will have
1468 deleted the insn pointed to by LOG_LINKS. Try
1469 scanning backward to find where the register is set. */
1470 for (scan = PREV_INSN (insn);
1471 scan && GET_CODE (scan) != CODE_LABEL;
1472 scan = PREV_INSN (scan))
1474 if (GET_RTX_CLASS (GET_CODE (scan)) != 'i')
1477 if (! reg_mentioned_p (reg, scan))
1480 if (noncall_uses_reg (reg, scan, &set))
1494 /* The register is set at LINK. */
1496 /* We can only optimize the function call if the register is
1497 being set to a symbol. In theory, we could sometimes
1498 optimize calls to a constant location, but the assembler
1499 and linker do not support that at present. */
1500 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
1501 && GET_CODE (SET_SRC (set)) != LABEL_REF)
1504 /* Scan forward from LINK to the place where REG dies, and
1505 make sure that the only insns which use REG are
1506 themselves function calls. */
1508 /* ??? This doesn't work for call targets that were allocated
1509 by reload, since there may not be a REG_DEAD note for the
1513 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
1517 /* Don't try to trace forward past a CODE_LABEL if we haven't
1518 seen INSN yet. Ordinarily, we will only find the setting insn
1519 in LOG_LINKS if it is in the same basic block. However,
1520 cross-jumping can insert code labels in between the load and
1521 the call, and can result in situations where a single call
1522 insn may have two targets depending on where we came from. */
1524 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
1527 if (GET_RTX_CLASS (GET_CODE (scan)) != 'i')
1530 /* Don't try to trace forward past a JUMP. To optimize
1531 safely, we would have to check that all the
1532 instructions at the jump destination did not use REG. */
1534 if (GET_CODE (scan) == JUMP_INSN)
1537 if (! reg_mentioned_p (reg, scan))
1540 if (noncall_uses_reg (reg, scan, &scanset))
1546 if (scan != insn && GET_CODE (scan) == CALL_INSN)
1548 /* There is a function call to this register other
1549 than the one we are checking. If we optimize
1550 this call, we need to rescan again below. */
1554 /* ??? We shouldn't have to worry about SCANSET here.
1555 We should just be able to check for a REG_DEAD note
1556 on a function call. However, the REG_DEAD notes are
1557 apparently not dependable around libcalls; c-torture
1558 execute/920501-2 is a test case. If SCANSET is set,
1559 then this insn sets the register, so it must have
1560 died earlier. Unfortunately, this will only handle
1561 the cases in which the register is, in fact, set in a
1564 /* ??? We shouldn't have to use FOUNDINSN here.
1565 However, the LOG_LINKS fields are apparently not
1566 entirely reliable around libcalls;
1567 newlib/libm/math/e_pow.c is a test case. Sometimes
1568 an insn will appear in LOG_LINKS even though it is
1569 not the most recent insn which sets the register. */
1573 || find_reg_note (scan, REG_DEAD, reg)))
1582 /* Either there was a branch, or some insn used REG
1583 other than as a function call address. */
1587 /* Create a code label, and put it in a REG_LABEL note on
1588 the insn which sets the register, and on each call insn
1589 which uses the register. In final_prescan_insn we look
1590 for the REG_LABEL notes, and output the appropriate label
1593 label = gen_label_rtx ();
1594 REG_NOTES (link) = gen_rtx (EXPR_LIST, REG_LABEL, label,
1596 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_LABEL, label,
1603 scan = NEXT_INSN (scan);
1605 && GET_CODE (scan) == CALL_INSN
1606 && reg_mentioned_p (reg, scan))
1607 REG_NOTES (scan) = gen_rtx (EXPR_LIST, REG_LABEL,
1608 label, REG_NOTES (scan));
1610 while (scan != dies);
1615 /* Scan the function looking for move instructions which have to be
1616 changed to pc-relative loads and insert the literal tables. */
1618 for (insn = first; insn; insn = NEXT_INSN (insn))
1620 if (broken_move (insn))
1623 /* Scan ahead looking for a barrier to stick the constant table
1625 rtx barrier = find_barrier (insn);
1627 /* Now find all the moves between the points and modify them. */
1628 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
1630 if (broken_move (scan))
1632 rtx pat = PATTERN (scan);
1633 rtx src = SET_SRC (pat);
1634 rtx dst = SET_DEST (pat);
1635 enum machine_mode mode = GET_MODE (dst);
1640 if (mode == SImode && hi_const (src))
1645 while (GET_CODE (dst) == SUBREG)
1647 offset += SUBREG_WORD (dst);
1648 dst = SUBREG_REG (dst);
1650 dst = gen_rtx (REG, HImode, REGNO (dst) + offset);
1653 lab = add_constant (src, mode);
1654 newsrc = gen_rtx (MEM, mode,
1655 gen_rtx (LABEL_REF, VOIDmode, lab));
1656 RTX_UNCHANGING_P (newsrc) = 1;
1657 newinsn = emit_insn_after (gen_rtx (SET, VOIDmode,
1658 dst, newsrc), scan);
1659 REG_NOTES (newinsn) = REG_NOTES (scan);
1660 REG_NOTES (scan) = NULL_RTX;
1661 /* If not optimizing, then delete_insn doesn't remove the
1662 insn from the chain, and hence is not useful. We
1663 convert the instruction to a NOTE in that case. */
1668 PUT_CODE (scan, NOTE);
1669 NOTE_LINE_NUMBER (scan) = NOTE_INSN_DELETED;
1670 NOTE_SOURCE_FILE (insn) = 0;
1675 dump_table (barrier);
1680 /* Dump out instruction addresses, which is useful for debugging the
1681 constant pool table stuff.
1683 If relaxing, output the label and pseudo-ops used to link together
1684 calls and the instruction which set the registers. */
1686 /* ??? This is unnecessary, and probably should be deleted. This makes
1687 the insn_addresses declaration above unnecessary. */
1689 /* ??? The addresses printed by this routine for insns are nonsense for
1690 insns which are inside of a sequence where none of the inner insns have
1691 variable length. This is because the second pass of shorten_branches
1692 does not bother to update them. */
1695 final_prescan_insn (insn, opvec, noperands)
1700 if (TARGET_DUMPISIZE)
1701 fprintf (asm_out_file, "\n! at %04x\n", insn_addresses[INSN_UID (insn)]);
1707 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
1712 pattern = PATTERN (insn);
1713 if (GET_CODE (pattern) == PARALLEL)
1714 pattern = XVECEXP (pattern, 0, 0);
1715 if (GET_CODE (pattern) == CALL
1716 || (GET_CODE (pattern) == SET
1717 && GET_CODE (SET_SRC (pattern)) == CALL))
1718 fprintf (asm_out_file, "\t.uses L%d\n",
1719 CODE_LABEL_NUMBER (XEXP (note, 0)));
1720 else if (GET_CODE (pattern) == SET)
1721 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1722 CODE_LABEL_NUMBER (XEXP (note, 0)));
1729 /* Dump out any constants accumulated in the final pass. These will
1730 will only be labels. */
1733 output_jump_label_table ()
1739 fprintf (asm_out_file, "\t.align 2\n");
1740 for (i = 0; i < pool_size; i++)
1742 pool_node *p = &pool_vector[i];
1744 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1745 CODE_LABEL_NUMBER (p->label));
1746 output_asm_insn (".long %O0", &p->value);
1754 /* A full frame looks like:
1758 [ if current_function_anonymous_args
1771 local-0 <- fp points here. */
1773 /* Number of bytes pushed for anonymous args, used to pass information
1774 between expand_prologue and expand_epilogue. */
1776 static int extra_push;
1778 /* Adjust the stack and return the number of bytes taken to do it. */
1781 output_stack_adjust (size, reg)
1787 rtx val = GEN_INT (size);
1790 if (! CONST_OK_FOR_I (size))
1792 rtx reg = gen_rtx (REG, SImode, 3);
1793 emit_insn (gen_movsi (reg, val));
1797 insn = gen_addsi3 (reg, reg, val);
1802 /* Output RTL to push register RN onto the stack. */
1809 if ((rn >= FIRST_FP_REG && rn <= LAST_FP_REG)
1811 x = emit_insn (gen_push_e (gen_rtx (REG, SFmode, rn)));
1813 x = emit_insn (gen_push (gen_rtx (REG, SImode, rn)));
1815 REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
1816 gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
1819 /* Output RTL to pop register RN from the stack. */
1826 if ((rn >= FIRST_FP_REG && rn <= LAST_FP_REG)
1828 x = emit_insn (gen_pop_e (gen_rtx (REG, SFmode, rn)));
1830 x = emit_insn (gen_pop (gen_rtx (REG, SImode, rn)));
1832 REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
1833 gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
1836 /* Generate code to push the regs specified in the mask, and return
1837 the number of bytes the insns take. */
1840 push_regs (mask, mask2)
1845 for (i = 0; i < 32; i++)
1846 if (mask & (1 << i))
1848 for (i = 32; i < FIRST_PSEUDO_REGISTER; i++)
1849 if (mask2 & (1 << (i - 32)))
1853 /* Work out the registers which need to be saved, both as a mask and a
1856 If doing a pragma interrupt function, then push all regs used by the
1857 function, and if we call another function (we can tell by looking at PR),
1858 make sure that all the regs it clobbers are safe too. */
1861 calc_live_regs (count_ptr, live_regs_mask2)
1863 int *live_regs_mask2;
1866 int live_regs_mask = 0;
1869 *live_regs_mask2 = 0;
1870 for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
1872 if (pragma_interrupt && ! pragma_trapa)
1874 /* Need to save all the regs ever live. */
1875 if ((regs_ever_live[reg]
1876 || (call_used_regs[reg] && regs_ever_live[PR_REG]))
1877 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
1878 && reg != T_REG && reg != GBR_REG)
1881 *live_regs_mask2 |= 1 << (reg - 32);
1883 live_regs_mask |= 1 << reg;
1889 /* Only push those regs which are used and need to be saved. */
1890 if (regs_ever_live[reg] && ! call_used_regs[reg])
1893 *live_regs_mask2 |= 1 << (reg - 32);
1895 live_regs_mask |= (1 << reg);
1902 return live_regs_mask;
1905 /* Code to generate prologue and epilogue sequences */
1908 sh_expand_prologue ()
1912 int live_regs_mask2;
1913 live_regs_mask = calc_live_regs (&d, &live_regs_mask2);
1915 /* We have pretend args if we had an object sent partially in registers
1916 and partially on the stack, e.g. a large structure. */
1917 output_stack_adjust (-current_function_pretend_args_size, stack_pointer_rtx);
1921 /* This is set by SETUP_VARARGS to indicate that this is a varargs
1922 routine. Clear it here so that the next function isn't affected. */
1923 if (current_function_anonymous_args)
1925 current_function_anonymous_args = 0;
1927 /* This is not used by the SH3E calling convention */
1930 /* Push arg regs as if they'd been provided by caller in stack. */
1931 for (i = 0; i < NPARM_REGS(SImode); i++)
1933 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
1934 if (i > (NPARM_REGS(SImode)
1935 - current_function_args_info.arg_count[(int) SH_ARG_INT]
1936 - current_function_varargs))
1944 push_regs (live_regs_mask, live_regs_mask2);
1946 output_stack_adjust (-get_frame_size (), stack_pointer_rtx);
1948 if (frame_pointer_needed)
1949 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1953 sh_expand_epilogue ()
1958 int live_regs_mask2;
1959 live_regs_mask = calc_live_regs (&d, &live_regs_mask2);
1961 if (frame_pointer_needed)
1963 /* We deliberately make the add dependent on the frame_pointer,
1964 to ensure that instruction scheduling won't move the stack pointer
1965 adjust before instructions reading from the frame. This can fail
1966 if there is an interrupt which then writes to the stack. */
1967 output_stack_adjust (get_frame_size (), frame_pointer_rtx);
1968 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
1971 output_stack_adjust (get_frame_size (), stack_pointer_rtx);
1973 /* Pop all the registers. */
1975 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1977 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
1978 if (j < 32 && (live_regs_mask & (1 << j)))
1980 else if (j >= 32 && (live_regs_mask2 & (1 << (j - 32))))
1984 output_stack_adjust (extra_push + current_function_pretend_args_size,
1988 /* Clear variables at function end. */
1991 function_epilogue (stream, size)
1995 pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
1999 sh_builtin_saveregs (arglist)
2002 tree fntype = TREE_TYPE (current_function_decl);
2003 /* First unnamed integer register. */
2004 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
2005 /* Number of integer registers we need to save. */
2006 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
2007 /* First unnamed SFmode float reg */
2008 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
2009 /* Number of SFmode float regs to save. */
2010 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
2011 int ptrsize = GET_MODE_SIZE (Pmode);
2012 rtx valist, regbuf, fpregs;
2015 /* Allocate block of memory for the regs. */
2016 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
2017 Or can assign_stack_local accept a 0 SIZE argument? */
2018 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
2020 regbuf = assign_stack_local (BLKmode, bufsize, 0);
2021 MEM_IN_STRUCT_P (regbuf) = 1;
2024 This is optimized to only save the regs that are necessary. Explicitly
2025 named args need not be saved. */
2027 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
2028 gen_rtx (MEM, BLKmode,
2029 plus_constant (XEXP (regbuf, 0),
2030 n_floatregs * UNITS_PER_WORD)),
2031 n_intregs, n_intregs * UNITS_PER_WORD);
2034 This is optimized to only save the regs that are necessary. Explicitly
2035 named args need not be saved.
2036 We explicitly build a pointer to the buffer because it halves the insn
2037 count when not optimizing (otherwise the pointer is built for each reg
2040 fpregs = gen_reg_rtx (Pmode);
2041 emit_move_insn (fpregs, XEXP (regbuf, 0));
2042 for (regno = first_floatreg; regno < NPARM_REGS (SFmode); regno ++)
2043 emit_move_insn (gen_rtx (MEM, SFmode,
2044 plus_constant (fpregs,
2045 GET_MODE_SIZE (SFmode)
2046 * (regno - first_floatreg))),
2047 gen_rtx (REG, SFmode,
2048 BASE_ARG_REG (SFmode) + regno));
2050 /* Return the address of the regbuf. */
2051 return XEXP (regbuf, 0);
2054 /* Define the offset between two registers, one to be eliminated, and
2055 the other its replacement, at the start of a routine. */
2058 initial_elimination_offset (from, to)
2063 int total_saved_regs_space;
2064 int total_auto_space = get_frame_size ();
2066 int live_regs_mask2;
2067 calc_live_regs (®s_saved, &live_regs_mask2);
2069 total_saved_regs_space = (regs_saved) * 4;
2071 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
2072 return total_saved_regs_space + total_auto_space;
2074 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2075 return total_saved_regs_space + total_auto_space;
2077 /* Initial gap between fp and sp is 0. */
2078 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2084 /* Handle machine specific pragmas to be semi-compatible with Hitachi
2088 handle_pragma (file, t)
2093 register char *pname;
2095 if (TREE_CODE (t) != IDENTIFIER_NODE)
2098 pname = IDENTIFIER_POINTER (t);
2099 if (strcmp (pname, "interrupt") == 0)
2100 pragma_interrupt = retval = 1;
2101 else if (strcmp (pname, "trapa") == 0)
2102 pragma_interrupt = pragma_trapa = retval = 1;
2103 else if (strcmp (pname, "nosave_low_regs") == 0)
2104 pragma_nosave_low_regs = retval = 1;
2109 /* Predicates used by the templates. */
2111 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
2112 Used only in general_movsrc_operand. */
2115 system_reg_operand (op, mode)
2117 enum machine_mode mode;
2129 /* Returns 1 if OP can be source of a simple move operation.
2130 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
2131 invalid as are subregs of system registers. */
2134 general_movsrc_operand (op, mode)
2136 enum machine_mode mode;
2138 if (GET_CODE (op) == MEM)
2140 rtx inside = XEXP (op, 0);
2141 if (GET_CODE (inside) == CONST)
2142 inside = XEXP (inside, 0);
2144 if (GET_CODE (inside) == LABEL_REF)
2147 if (GET_CODE (inside) == PLUS
2148 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
2149 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
2152 /* Only post inc allowed. */
2153 if (GET_CODE (inside) == PRE_DEC)
2157 if ((mode == QImode || mode == HImode)
2158 && (GET_CODE (op) == SUBREG
2159 && GET_CODE (XEXP (op, 0)) == REG
2160 && system_reg_operand (XEXP (op, 0), mode)))
2163 return general_operand (op, mode);
2166 /* Returns 1 if OP can be a destination of a move.
2167 Same as general_operand, but no preinc allowed. */
2170 general_movdst_operand (op, mode)
2172 enum machine_mode mode;
2174 /* Only pre dec allowed. */
2175 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
2178 return general_operand (op, mode);
2181 /* Returns 1 if OP is a normal arithmetic register. */
2184 arith_reg_operand (op, mode)
2186 enum machine_mode mode;
2188 if (register_operand (op, mode))
2190 if (GET_CODE (op) == REG)
2191 return (REGNO (op) != T_REG
2192 && REGNO (op) != PR_REG
2193 && REGNO (op) != FPUL_REG
2194 && REGNO (op) != MACH_REG
2195 && REGNO (op) != MACL_REG);
2201 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
2204 arith_operand (op, mode)
2206 enum machine_mode mode;
2208 if (arith_reg_operand (op, mode))
2211 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
2217 /* Returns 1 if OP is a valid source operand for a compare insn. */
2220 arith_reg_or_0_operand (op, mode)
2222 enum machine_mode mode;
2224 if (arith_reg_operand (op, mode))
2227 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_N (INTVAL (op)))
2233 /* Returns 1 if OP is a valid source operand for a logical operation. */
2236 logical_operand (op, mode)
2238 enum machine_mode mode;
2240 if (arith_reg_operand (op, mode))
2243 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
2249 /* Nonzero if OP is a floating point value with value 0.0. */
2252 fp_zero_operand (op)
2257 if (GET_MODE (op) != SFmode)
2260 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2261 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
2264 /* Nonzero if OP is a floating point value with value 1.0. */
2272 if (GET_MODE (op) != SFmode)
2275 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2276 return REAL_VALUES_EQUAL (r, dconst1);
2279 /* Return non-zero if REG is not used after INSN.
2280 We assume REG is a reload reg, and therefore does
2281 not live past labels. It may live past calls or jumps though. */
2283 reg_unused_after (reg, insn)
2290 /* If the reg is set by this instruction, then it is safe for our
2291 case. Disregard the case where this is a store to memory, since
2292 we are checking a register used in the store address. */
2293 set = single_set (insn);
2294 if (set && GET_CODE (SET_DEST (set)) != MEM
2295 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2298 while (insn = NEXT_INSN (insn))
2300 code = GET_CODE (insn);
2303 /* If this is a label that existed before reload, then the register
2304 if dead here. However, if this is a label added by reorg, then
2305 the register may still be live here. We can't tell the difference,
2306 so we just ignore labels completely. */
2307 if (code == CODE_LABEL)
2312 if (code == JUMP_INSN)
2315 /* If this is a sequence, we must handle them all at once.
2316 We could have for instance a call that sets the target register,
2317 and a insn in a delay slot that uses the register. In this case,
2318 we must return 0. */
2319 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
2324 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
2326 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
2327 rtx set = single_set (this_insn);
2329 if (GET_CODE (this_insn) == CALL_INSN)
2332 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
2334 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2336 if (GET_CODE (SET_DEST (set)) != MEM)
2342 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
2348 else if (GET_RTX_CLASS (code) == 'i')
2350 rtx set = single_set (insn);
2352 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
2354 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2355 return GET_CODE (SET_DEST (set)) != MEM;
2356 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2360 if (code == CALL_INSN && call_used_regs[REGNO (reg)])