1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "insn-config.h"
35 #include "hard-reg-set.h"
37 #include "insn-attr.h"
40 #include "integrate.h"
44 #include "target-def.h"
46 #include "langhooks.h"
47 #include "basic-block.h"
49 #include "cfglayout.h"
51 #include "sched-int.h"
56 #include "alloc-pool.h"
57 #include "tm-constrs.h"
60 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
62 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
63 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
65 /* These are some macros to abstract register modes. */
66 #define CONST_OK_FOR_ADD(size) \
67 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
68 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
69 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
70 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
72 /* Used to simplify the logic below. Find the attributes wherever
74 #define SH_ATTRIBUTES(decl) \
75 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
76 : DECL_ATTRIBUTES (decl) \
77 ? (DECL_ATTRIBUTES (decl)) \
78 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
80 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
81 int current_function_interrupt;
83 tree sh_deferred_function_attributes;
84 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
86 /* Global variables for machine-dependent things. */
88 /* Which cpu are we scheduling for. */
89 enum processor_type sh_cpu;
91 /* Definitions used in ready queue reordering for first scheduling pass. */
93 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
94 static short *regmode_weight[2];
96 /* Total SFmode and SImode weights of scheduled insns. */
97 static int curr_regmode_pressure[2];
99 /* Number of r0 life regions. */
100 static int r0_life_regions;
102 /* If true, skip cycles for Q -> R movement. */
103 static int skip_cycles = 0;
105 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
106 and returned from sh_reorder2. */
107 static short cached_can_issue_more;
109 /* Provides the class number of the smallest class containing
112 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
114 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
147 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
148 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
149 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
150 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
151 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
152 GENERAL_REGS, GENERAL_REGS,
155 char sh_register_names[FIRST_PSEUDO_REGISTER] \
156 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
158 char sh_additional_register_names[ADDREGNAMES_SIZE] \
159 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
160 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
162 int assembler_dialect;
164 static bool shmedia_space_reserved_for_target_registers;
166 static bool sh_handle_option (size_t, const char *, int);
167 static void split_branches (rtx);
168 static int branch_dest (rtx);
169 static void force_into (rtx, rtx);
170 static void print_slot (rtx);
171 static rtx add_constant (rtx, enum machine_mode, rtx);
172 static void dump_table (rtx, rtx);
173 static int hi_const (rtx);
174 static int broken_move (rtx);
175 static int mova_p (rtx);
176 static rtx find_barrier (int, rtx, rtx);
177 static int noncall_uses_reg (rtx, rtx, rtx *);
178 static rtx gen_block_redirect (rtx, int, int);
179 static void sh_reorg (void);
180 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
181 static rtx frame_insn (rtx);
182 static rtx push (int);
183 static void pop (int);
184 static void push_regs (HARD_REG_SET *, int);
185 static int calc_live_regs (HARD_REG_SET *);
186 static HOST_WIDE_INT rounded_frame_size (int);
187 static rtx mark_constant_pool_use (rtx);
188 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
189 static tree sh_handle_resbank_handler_attribute (tree *, tree,
191 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
193 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
194 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
195 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
196 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
197 static void sh_insert_attributes (tree, tree *);
198 static const char *sh_check_pch_target_flags (int);
199 static int sh_adjust_cost (rtx, rtx, rtx, int);
200 static int sh_issue_rate (void);
201 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
202 static short find_set_regmode_weight (rtx, enum machine_mode);
203 static short find_insn_regmode_weight (rtx, enum machine_mode);
204 static void find_regmode_weight (basic_block, enum machine_mode);
205 static int find_r0_life_regions (basic_block);
206 static void sh_md_init_global (FILE *, int, int);
207 static void sh_md_finish_global (FILE *, int);
208 static int rank_for_reorder (const void *, const void *);
209 static void swap_reorder (rtx *, int);
210 static void ready_reorder (rtx *, int);
211 static short high_pressure (enum machine_mode);
212 static int sh_reorder (FILE *, int, rtx *, int *, int);
213 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
214 static void sh_md_init (FILE *, int, int);
215 static int sh_variable_issue (FILE *, int, rtx, int);
217 static bool sh_function_ok_for_sibcall (tree, tree);
219 static bool sh_cannot_modify_jumps_p (void);
220 static enum reg_class sh_target_reg_class (void);
221 static bool sh_optimize_target_register_callee_saved (bool);
222 static bool sh_ms_bitfield_layout_p (const_tree);
224 static void sh_init_builtins (void);
225 static void sh_media_init_builtins (void);
226 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
227 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
228 static void sh_file_start (void);
229 static int flow_dependent_p (rtx, rtx);
230 static void flow_dependent_p_1 (rtx, const_rtx, void *);
231 static int shiftcosts (rtx);
232 static int andcosts (rtx);
233 static int addsubcosts (rtx);
234 static int multcosts (rtx);
235 static bool unspec_caller_rtx_p (rtx);
236 static bool sh_cannot_copy_insn_p (rtx);
237 static bool sh_rtx_costs (rtx, int, int, int *, bool);
238 static int sh_address_cost (rtx, bool);
239 static int sh_pr_n_sets (void);
240 static rtx sh_allocate_initial_value (rtx);
241 static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);
242 static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
243 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
244 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
245 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
246 static int scavenge_reg (HARD_REG_SET *s);
247 struct save_schedule_s;
248 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
249 struct save_schedule_s *, int);
251 static rtx sh_struct_value_rtx (tree, int);
252 static bool sh_return_in_memory (const_tree, const_tree);
253 static rtx sh_builtin_saveregs (void);
254 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
255 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
256 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
257 static tree sh_build_builtin_va_list (void);
258 static void sh_va_start (tree, rtx);
259 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
260 static enum machine_mode sh_promote_function_mode (const_tree type,
265 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
267 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
269 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
271 static bool sh_scalar_mode_supported_p (enum machine_mode);
272 static int sh_dwarf_calling_convention (const_tree);
273 static void sh_encode_section_info (tree, rtx, int);
274 static int sh2a_function_vector_p (tree);
276 static const struct attribute_spec sh_attribute_table[] =
278 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
279 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
280 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
281 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
282 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
283 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
284 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
285 { "resbank", 0, 0, true, false, false, sh_handle_resbank_handler_attribute },
286 { "function_vector", 1, 1, true, false, false, sh2a_handle_function_vector_handler_attribute },
288 /* Symbian support adds three new attributes:
289 dllexport - for exporting a function/variable that will live in a dll
290 dllimport - for importing a function/variable from a dll
292 Microsoft allows multiple declspecs in one __declspec, separating
293 them with spaces. We do NOT support this. Instead, use __declspec
295 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
296 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
298 { NULL, 0, 0, false, false, false, NULL }
301 /* Initialize the GCC target structure. */
302 #undef TARGET_ATTRIBUTE_TABLE
303 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
305 /* The next two are used for debug info when compiling with -gdwarf. */
306 #undef TARGET_ASM_UNALIGNED_HI_OP
307 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
308 #undef TARGET_ASM_UNALIGNED_SI_OP
309 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
311 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
312 #undef TARGET_ASM_UNALIGNED_DI_OP
313 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
314 #undef TARGET_ASM_ALIGNED_DI_OP
315 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
317 #undef TARGET_ASM_FUNCTION_EPILOGUE
318 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
320 #undef TARGET_ASM_OUTPUT_MI_THUNK
321 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
323 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
324 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
326 #undef TARGET_ASM_FILE_START
327 #define TARGET_ASM_FILE_START sh_file_start
328 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
329 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
331 #undef TARGET_DEFAULT_TARGET_FLAGS
332 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
333 #undef TARGET_HANDLE_OPTION
334 #define TARGET_HANDLE_OPTION sh_handle_option
336 #undef TARGET_INSERT_ATTRIBUTES
337 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
339 #undef TARGET_SCHED_ADJUST_COST
340 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
342 #undef TARGET_SCHED_ISSUE_RATE
343 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
345 /* The next 5 hooks have been implemented for reenabling sched1. With the
346 help of these macros we are limiting the movement of insns in sched1 to
347 reduce the register pressure. The overall idea is to keep count of SImode
348 and SFmode regs required by already scheduled insns. When these counts
349 cross some threshold values; give priority to insns that free registers.
350 The insn that frees registers is most likely to be the insn with lowest
351 LUID (original insn order); but such an insn might be there in the stalled
352 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
353 upto a max of 8 cycles so that such insns may move from Q -> R.
355 The description of the hooks are as below:
357 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
358 scheduler; it is called inside the sched_init function just after
359 find_insn_reg_weights function call. It is used to calculate the SImode
360 and SFmode weights of insns of basic blocks; much similar to what
361 find_insn_reg_weights does.
362 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
364 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
365 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
368 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
369 high; reorder the ready queue so that the insn with lowest LUID will be
372 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
373 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
375 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
376 can be returned from TARGET_SCHED_REORDER2.
378 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
380 #undef TARGET_SCHED_DFA_NEW_CYCLE
381 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
383 #undef TARGET_SCHED_INIT_GLOBAL
384 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
386 #undef TARGET_SCHED_FINISH_GLOBAL
387 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
389 #undef TARGET_SCHED_VARIABLE_ISSUE
390 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
392 #undef TARGET_SCHED_REORDER
393 #define TARGET_SCHED_REORDER sh_reorder
395 #undef TARGET_SCHED_REORDER2
396 #define TARGET_SCHED_REORDER2 sh_reorder2
398 #undef TARGET_SCHED_INIT
399 #define TARGET_SCHED_INIT sh_md_init
401 #undef TARGET_LEGITIMIZE_ADDRESS
402 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
404 #undef TARGET_CANNOT_MODIFY_JUMPS_P
405 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
406 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
407 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
408 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
409 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
410 sh_optimize_target_register_callee_saved
412 #undef TARGET_MS_BITFIELD_LAYOUT_P
413 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
415 #undef TARGET_INIT_BUILTINS
416 #define TARGET_INIT_BUILTINS sh_init_builtins
417 #undef TARGET_EXPAND_BUILTIN
418 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
420 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
421 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
423 #undef TARGET_CANNOT_COPY_INSN_P
424 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
425 #undef TARGET_RTX_COSTS
426 #define TARGET_RTX_COSTS sh_rtx_costs
427 #undef TARGET_ADDRESS_COST
428 #define TARGET_ADDRESS_COST sh_address_cost
429 #undef TARGET_ALLOCATE_INITIAL_VALUE
430 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
432 #undef TARGET_MACHINE_DEPENDENT_REORG
433 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
435 #undef TARGET_DWARF_REGISTER_SPAN
436 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
439 #undef TARGET_HAVE_TLS
440 #define TARGET_HAVE_TLS true
443 #undef TARGET_PROMOTE_PROTOTYPES
444 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
445 #undef TARGET_PROMOTE_FUNCTION_MODE
446 #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode
448 #undef TARGET_STRUCT_VALUE_RTX
449 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
450 #undef TARGET_RETURN_IN_MEMORY
451 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
453 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
454 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
455 #undef TARGET_SETUP_INCOMING_VARARGS
456 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
457 #undef TARGET_STRICT_ARGUMENT_NAMING
458 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
459 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
460 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
461 #undef TARGET_MUST_PASS_IN_STACK
462 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
463 #undef TARGET_PASS_BY_REFERENCE
464 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
465 #undef TARGET_CALLEE_COPIES
466 #define TARGET_CALLEE_COPIES sh_callee_copies
467 #undef TARGET_ARG_PARTIAL_BYTES
468 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
470 #undef TARGET_BUILD_BUILTIN_VA_LIST
471 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
472 #undef TARGET_EXPAND_BUILTIN_VA_START
473 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
474 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
475 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
477 #undef TARGET_SCALAR_MODE_SUPPORTED_P
478 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
479 #undef TARGET_VECTOR_MODE_SUPPORTED_P
480 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
482 #undef TARGET_CHECK_PCH_TARGET_FLAGS
483 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
485 #undef TARGET_DWARF_CALLING_CONVENTION
486 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
488 /* Return regmode weight for insn. */
489 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
491 /* Return current register pressure for regmode. */
492 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
494 #undef TARGET_ENCODE_SECTION_INFO
495 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
499 #undef TARGET_ENCODE_SECTION_INFO
500 #define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
501 #undef TARGET_STRIP_NAME_ENCODING
502 #define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
503 #undef TARGET_CXX_IMPORT_EXPORT_CLASS
504 #define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
508 #undef TARGET_SECONDARY_RELOAD
509 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
511 #undef TARGET_LEGITIMATE_ADDRESS_P
512 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
514 /* Machine-specific symbol_ref flags. */
515 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
517 struct gcc_target targetm = TARGET_INITIALIZER;
519 /* Implement TARGET_HANDLE_OPTION. */
522 sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
523 int value ATTRIBUTE_UNUSED)
528 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
532 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
536 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
540 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
544 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
547 case OPT_m2a_single_only:
548 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
552 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
556 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
560 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
567 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
571 case OPT_m4_100_nofpu:
572 case OPT_m4_200_nofpu:
573 case OPT_m4_300_nofpu:
577 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
581 case OPT_m4_100_single:
582 case OPT_m4_200_single:
583 case OPT_m4_300_single:
584 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
587 case OPT_m4_single_only:
588 case OPT_m4_100_single_only:
589 case OPT_m4_200_single_only:
590 case OPT_m4_300_single_only:
591 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
595 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
600 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
604 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
607 case OPT_m4a_single_only:
608 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
612 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
615 case OPT_m5_32media_nofpu:
616 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
620 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
623 case OPT_m5_64media_nofpu:
624 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
628 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
631 case OPT_m5_compact_nofpu:
632 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
640 /* Set default optimization options. */
642 sh_optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
646 flag_omit_frame_pointer = 2;
648 sh_div_str = "inv:minlat";
652 target_flags |= MASK_SMALLCODE;
653 sh_div_str = SH_DIV_STR_FOR_SIZE ;
656 TARGET_CBRANCHDI4 = 1;
657 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options
658 haven't been parsed yet, hence we'd read only the default.
659 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so
660 it's OK to always set flag_branch_target_load_optimize. */
663 flag_branch_target_load_optimize = 1;
665 target_flags |= MASK_SAVE_ALL_TARGET_REGS;
667 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE
668 here, so leave it to OVERRIDE_OPTIONS to set
669 flag_finite_math_only. We set it to 2 here so we know if the user
670 explicitly requested this to be on or off. */
671 flag_finite_math_only = 2;
672 /* If flag_schedule_insns is 1, we set it to 2 here so we know if
673 the user explicitly requested this to be on or off. */
674 if (flag_schedule_insns > 0)
675 flag_schedule_insns = 2;
677 set_param_value ("simultaneous-prefetches", 2);
680 /* Implement OVERRIDE_OPTIONS macro. Validate and override various
681 options, and do some machine dependent initialization. */
683 sh_override_options (void)
687 SUBTARGET_OVERRIDE_OPTIONS;
688 if (flag_finite_math_only == 2)
689 flag_finite_math_only
690 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;
691 if (TARGET_SH2E && !flag_finite_math_only)
692 target_flags |= MASK_IEEE;
693 sh_cpu = PROCESSOR_SH1;
694 assembler_dialect = 0;
696 sh_cpu = PROCESSOR_SH2;
698 sh_cpu = PROCESSOR_SH2E;
700 sh_cpu = PROCESSOR_SH2A;
702 sh_cpu = PROCESSOR_SH3;
704 sh_cpu = PROCESSOR_SH3E;
707 assembler_dialect = 1;
708 sh_cpu = PROCESSOR_SH4;
710 if (TARGET_SH4A_ARCH)
712 assembler_dialect = 1;
713 sh_cpu = PROCESSOR_SH4A;
717 sh_cpu = PROCESSOR_SH5;
718 target_flags |= MASK_ALIGN_DOUBLE;
719 if (TARGET_SHMEDIA_FPU)
720 target_flags |= MASK_FMOVD;
723 /* There are no delay slots on SHmedia. */
724 flag_delayed_branch = 0;
725 /* Relaxation isn't yet supported for SHmedia */
726 target_flags &= ~MASK_RELAX;
727 /* After reload, if conversion does little good but can cause
729 - find_if_block doesn't do anything for SH because we don't
730 have conditional execution patterns. (We use conditional
731 move patterns, which are handled differently, and only
733 - find_cond_trap doesn't do anything for the SH because we
734 don't have conditional traps.
735 - find_if_case_1 uses redirect_edge_and_branch_force in
736 the only path that does an optimization, and this causes
737 an ICE when branch targets are in registers.
738 - find_if_case_2 doesn't do anything for the SHmedia after
739 reload except when it can redirect a tablejump - and
740 that's rather rare. */
741 flag_if_conversion2 = 0;
742 if (! strcmp (sh_div_str, "call"))
743 sh_div_strategy = SH_DIV_CALL;
744 else if (! strcmp (sh_div_str, "call2"))
745 sh_div_strategy = SH_DIV_CALL2;
746 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)
747 sh_div_strategy = SH_DIV_FP;
748 else if (! strcmp (sh_div_str, "inv"))
749 sh_div_strategy = SH_DIV_INV;
750 else if (! strcmp (sh_div_str, "inv:minlat"))
751 sh_div_strategy = SH_DIV_INV_MINLAT;
752 else if (! strcmp (sh_div_str, "inv20u"))
753 sh_div_strategy = SH_DIV_INV20U;
754 else if (! strcmp (sh_div_str, "inv20l"))
755 sh_div_strategy = SH_DIV_INV20L;
756 else if (! strcmp (sh_div_str, "inv:call2"))
757 sh_div_strategy = SH_DIV_INV_CALL2;
758 else if (! strcmp (sh_div_str, "inv:call"))
759 sh_div_strategy = SH_DIV_INV_CALL;
760 else if (! strcmp (sh_div_str, "inv:fp"))
763 sh_div_strategy = SH_DIV_INV_FP;
765 sh_div_strategy = SH_DIV_INV;
767 TARGET_CBRANCHDI4 = 0;
768 /* Assembler CFI isn't yet fully supported for SHmedia. */
769 flag_dwarf2_cfi_asm = 0;
774 /* Only the sh64-elf assembler fully supports .quad properly. */
775 targetm.asm_out.aligned_op.di = NULL;
776 targetm.asm_out.unaligned_op.di = NULL;
780 if (! strcmp (sh_div_str, "call-div1"))
781 sh_div_strategy = SH_DIV_CALL_DIV1;
782 else if (! strcmp (sh_div_str, "call-fp")
783 && (TARGET_FPU_DOUBLE
784 || (TARGET_HARD_SH4 && TARGET_SH2E)
785 || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))
786 sh_div_strategy = SH_DIV_CALL_FP;
787 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2)
788 sh_div_strategy = SH_DIV_CALL_TABLE;
790 /* Pick one that makes most sense for the target in general.
791 It is not much good to use different functions depending
792 on -Os, since then we'll end up with two different functions
793 when some of the code is compiled for size, and some for
796 /* SH4 tends to emphasize speed. */
798 sh_div_strategy = SH_DIV_CALL_TABLE;
799 /* These have their own way of doing things. */
800 else if (TARGET_SH2A)
801 sh_div_strategy = SH_DIV_INTRINSIC;
802 /* ??? Should we use the integer SHmedia function instead? */
803 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)
804 sh_div_strategy = SH_DIV_CALL_FP;
805 /* SH1 .. SH3 cores often go into small-footprint systems, so
806 default to the smallest implementation available. */
807 else if (TARGET_SH2) /* ??? EXPERIMENTAL */
808 sh_div_strategy = SH_DIV_CALL_TABLE;
810 sh_div_strategy = SH_DIV_CALL_DIV1;
813 TARGET_PRETEND_CMOVE = 0;
814 if (sh_divsi3_libfunc[0])
815 ; /* User supplied - leave it alone. */
816 else if (TARGET_DIVIDE_CALL_FP)
817 sh_divsi3_libfunc = "__sdivsi3_i4";
818 else if (TARGET_DIVIDE_CALL_TABLE)
819 sh_divsi3_libfunc = "__sdivsi3_i4i";
821 sh_divsi3_libfunc = "__sdivsi3_1";
823 sh_divsi3_libfunc = "__sdivsi3";
824 if (sh_branch_cost == -1)
826 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1;
828 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
829 if (! VALID_REGISTER_P (regno))
830 sh_register_names[regno][0] = '\0';
832 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
833 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
834 sh_additional_register_names[regno][0] = '\0';
836 if (flag_omit_frame_pointer == 2)
838 /* The debugging information is sufficient,
839 but gdb doesn't implement this yet */
841 flag_omit_frame_pointer
842 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);
844 flag_omit_frame_pointer = 0;
847 if ((flag_pic && ! TARGET_PREFERGOT)
848 || (TARGET_SHMEDIA && !TARGET_PT_FIXED))
849 flag_no_function_cse = 1;
851 if (SMALL_REGISTER_CLASSES)
853 /* Never run scheduling before reload, since that can
854 break global alloc, and generates slower code anyway due
855 to the pressure on R0. */
856 /* Enable sched1 for SH4 if the user explicitly requests.
857 When sched1 is enabled, the ready queue will be reordered by
858 the target hooks if pressure is high. We can not do this for
859 PIC, SH3 and lower as they give spill failures for R0. */
860 if (!TARGET_HARD_SH4 || flag_pic)
861 flag_schedule_insns = 0;
862 /* ??? Current exception handling places basic block boundaries
863 after call_insns. It causes the high pressure on R0 and gives
864 spill failures for R0 in reload. See PR 22553 and the thread
866 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
867 else if (flag_exceptions)
869 if (flag_schedule_insns == 1)
870 warning (0, "ignoring -fschedule-insns because of exception handling bug");
871 flag_schedule_insns = 0;
873 else if (flag_schedule_insns == 2)
874 flag_schedule_insns = 0;
877 /* Unwinding with -freorder-blocks-and-partition does not work on this
878 architecture, because it requires far jumps to label crossing between
879 hot/cold sections which are rejected on this architecture. */
880 if (flag_reorder_blocks_and_partition)
884 inform (input_location,
885 "-freorder-blocks-and-partition does not work with "
886 "exceptions on this architecture");
887 flag_reorder_blocks_and_partition = 0;
888 flag_reorder_blocks = 1;
890 else if (flag_unwind_tables)
892 inform (input_location,
893 "-freorder-blocks-and-partition does not support unwind "
894 "info on this architecture");
895 flag_reorder_blocks_and_partition = 0;
896 flag_reorder_blocks = 1;
900 if (align_loops == 0)
901 align_loops = 1 << (TARGET_SH5 ? 3 : 2);
902 if (align_jumps == 0)
903 align_jumps = 1 << CACHE_LOG;
904 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))
905 align_jumps = TARGET_SHMEDIA ? 4 : 2;
907 /* Allocation boundary (in *bytes*) for the code of a function.
908 SH1: 32 bit alignment is faster, because instructions are always
909 fetched as a pair from a longword boundary.
910 SH2 .. SH5 : align to cache line start. */
911 if (align_functions == 0)
913 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);
914 /* The linker relaxation code breaks when a function contains
915 alignments that are larger than that at the start of a
920 = align_loops > align_jumps ? align_loops : align_jumps;
922 /* Also take possible .long constants / mova tables int account. */
925 if (align_functions < min_align)
926 align_functions = min_align;
929 if (sh_fixed_range_str)
930 sh_fix_range (sh_fixed_range_str);
933 /* Print the operand address in x to the stream. */
936 print_operand_address (FILE *stream, rtx x)
938 switch (GET_CODE (x))
942 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
947 rtx base = XEXP (x, 0);
948 rtx index = XEXP (x, 1);
950 switch (GET_CODE (index))
953 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
954 reg_names[true_regnum (base)]);
960 int base_num = true_regnum (base);
961 int index_num = true_regnum (index);
963 fprintf (stream, "@(r0,%s)",
964 reg_names[MAX (base_num, index_num)]);
975 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
979 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
983 x = mark_constant_pool_use (x);
984 output_addr_const (stream, x);
989 /* Print operand x (an rtx) in assembler syntax to file stream
990 according to modifier code.
992 '.' print a .s if insn needs delay slot
993 ',' print LOCAL_LABEL_PREFIX
994 '@' print trap, rte or rts depending upon pragma interruptness
995 '#' output a nop if there is nothing to put in the delay slot
996 ''' print likelihood suffix (/u for unlikely).
997 '>' print branch target if -fverbose-asm
998 'O' print a constant without the #
999 'R' print the LSW of a dp value - changes if in little endian
1000 'S' print the MSW of a dp value - changes if in little endian
1001 'T' print the next word of a dp value - same as 'R' in big endian mode.
1002 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
1003 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
1004 'N' print 'r63' if the operand is (const_int 0).
1005 'd' print a V2SF reg as dN instead of fpN.
1006 'm' print a pair `base,offset' or `base,index', for LD and ST.
1007 'U' Likewise for {LD,ST}{HI,LO}.
1008 'V' print the position of a single bit set.
1009 'W' print the position of a single bit cleared.
1010 't' print a memory address which is a register.
1011 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
1012 'o' output an operator. */
1015 print_operand (FILE *stream, rtx x, int code)
1018 enum machine_mode mode;
1026 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
1027 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
1028 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
1031 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
1034 trapa_attr = lookup_attribute ("trap_exit",
1035 DECL_ATTRIBUTES (current_function_decl));
1037 fprintf (stream, "trapa #%ld",
1038 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
1039 else if (sh_cfun_interrupt_handler_p ())
1041 if (sh_cfun_resbank_handler_p ())
1042 fprintf (stream, "resbank\n");
1043 fprintf (stream, "rte");
1046 fprintf (stream, "rts");
1049 /* Output a nop if there's nothing in the delay slot. */
1050 if (dbr_sequence_length () == 0)
1051 fprintf (stream, "\n\tnop");
1055 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
1057 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
1058 fputs ("/u", stream);
1062 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
1064 fputs ("\t! target: ", stream);
1065 output_addr_const (stream, JUMP_LABEL (current_output_insn));
1069 x = mark_constant_pool_use (x);
1070 output_addr_const (stream, x);
1072 /* N.B.: %R / %S / %T adjust memory addresses by four.
1073 For SHMEDIA, that means they can be used to access the first and
1074 second 32 bit part of a 64 bit (or larger) value that
1075 might be held in floating point registers or memory.
1076 While they can be used to access 64 bit parts of a larger value
1077 held in general purpose registers, that won't work with memory -
1078 neither for fp registers, since the frxx names are used. */
1080 if (REG_P (x) || GET_CODE (x) == SUBREG)
1082 regno = true_regnum (x);
1083 regno += FP_REGISTER_P (regno) ? 1 : LSW;
1084 fputs (reg_names[regno], (stream));
1088 x = adjust_address (x, SImode, 4 * LSW);
1089 print_operand_address (stream, XEXP (x, 0));
1095 mode = GET_MODE (x);
1096 if (mode == VOIDmode)
1098 if (GET_MODE_SIZE (mode) >= 8)
1099 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
1101 print_operand (stream, sub, 0);
1103 output_operand_lossage ("invalid operand to %%R");
1107 if (REG_P (x) || GET_CODE (x) == SUBREG)
1109 regno = true_regnum (x);
1110 regno += FP_REGISTER_P (regno) ? 0 : MSW;
1111 fputs (reg_names[regno], (stream));
1115 x = adjust_address (x, SImode, 4 * MSW);
1116 print_operand_address (stream, XEXP (x, 0));
1122 mode = GET_MODE (x);
1123 if (mode == VOIDmode)
1125 if (GET_MODE_SIZE (mode) >= 8)
1126 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
1128 print_operand (stream, sub, 0);
1130 output_operand_lossage ("invalid operand to %%S");
1134 /* Next word of a double. */
1135 switch (GET_CODE (x))
1138 fputs (reg_names[REGNO (x) + 1], (stream));
1141 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
1142 && GET_CODE (XEXP (x, 0)) != POST_INC)
1143 x = adjust_address (x, SImode, 4);
1144 print_operand_address (stream, XEXP (x, 0));
1152 gcc_assert (MEM_P (x));
1154 switch (GET_CODE (x))
1158 print_operand (stream, x, 0);
1166 switch (GET_CODE (x))
1168 case PLUS: fputs ("add", stream); break;
1169 case MINUS: fputs ("sub", stream); break;
1170 case MULT: fputs ("mul", stream); break;
1171 case DIV: fputs ("div", stream); break;
1172 case EQ: fputs ("eq", stream); break;
1173 case NE: fputs ("ne", stream); break;
1174 case GT: case LT: fputs ("gt", stream); break;
1175 case GE: case LE: fputs ("ge", stream); break;
1176 case GTU: case LTU: fputs ("gtu", stream); break;
1177 case GEU: case LEU: fputs ("geu", stream); break;
1186 && GET_CODE (XEXP (x, 0)) == PLUS
1187 && (REG_P (XEXP (XEXP (x, 0), 1))
1188 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
1189 fputc ('x', stream);
1195 switch (GET_MODE (x))
1197 case QImode: fputs (".b", stream); break;
1198 case HImode: fputs (".w", stream); break;
1199 case SImode: fputs (".l", stream); break;
1200 case SFmode: fputs (".s", stream); break;
1201 case DFmode: fputs (".d", stream); break;
1202 default: gcc_unreachable ();
1209 gcc_assert (MEM_P (x));
1213 switch (GET_CODE (x))
1217 print_operand (stream, x, 0);
1218 fputs (", 0", stream);
1222 print_operand (stream, XEXP (x, 0), 0);
1223 fputs (", ", stream);
1224 print_operand (stream, XEXP (x, 1), 0);
1234 int num = exact_log2 (INTVAL (x));
1235 gcc_assert (num >= 0);
1236 fprintf (stream, "#%d", num);
1242 int num = exact_log2 (~INTVAL (x));
1243 gcc_assert (num >= 0);
1244 fprintf (stream, "#%d", num);
1249 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
1251 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1255 if (x == CONST0_RTX (GET_MODE (x)))
1257 fprintf ((stream), "r63");
1260 goto default_output;
1262 if (CONST_INT_P (x))
1264 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
1272 mode = GET_MODE (x);
1274 switch (GET_CODE (x))
1278 rtx inner = XEXP (x, 0);
1280 enum machine_mode inner_mode;
1282 /* We might see SUBREGs with vector mode registers inside. */
1283 if (GET_CODE (inner) == SUBREG
1284 && (GET_MODE_SIZE (GET_MODE (inner))
1285 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1286 && subreg_lowpart_p (inner))
1287 inner = SUBREG_REG (inner);
1288 if (CONST_INT_P (inner))
1290 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
1291 goto default_output;
1293 inner_mode = GET_MODE (inner);
1294 if (GET_CODE (inner) == SUBREG
1295 && (GET_MODE_SIZE (GET_MODE (inner))
1296 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1297 && REG_P (SUBREG_REG (inner)))
1299 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
1300 GET_MODE (SUBREG_REG (inner)),
1301 SUBREG_BYTE (inner),
1303 inner = SUBREG_REG (inner);
1305 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
1307 /* Floating point register pairs are always big endian;
1308 general purpose registers are 64 bit wide. */
1309 regno = REGNO (inner);
1310 regno = (HARD_REGNO_NREGS (regno, inner_mode)
1311 - HARD_REGNO_NREGS (regno, mode))
1319 /* FIXME: We need this on SHmedia32 because reload generates
1320 some sign-extended HI or QI loads into DImode registers
1321 but, because Pmode is SImode, the address ends up with a
1322 subreg:SI of the DImode register. Maybe reload should be
1323 fixed so as to apply alter_subreg to such loads? */
1325 gcc_assert (trapping_target_operand (x, VOIDmode));
1326 x = XEXP (XEXP (x, 2), 0);
1327 goto default_output;
1329 gcc_assert (SUBREG_BYTE (x) == 0
1330 && REG_P (SUBREG_REG (x)));
1338 if (FP_REGISTER_P (regno)
1339 && mode == V16SFmode)
1340 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1341 else if (FP_REGISTER_P (REGNO (x))
1342 && mode == V4SFmode)
1343 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1345 && mode == V2SFmode)
1346 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1347 else if (FP_REGISTER_P (REGNO (x))
1348 && GET_MODE_SIZE (mode) > 4)
1349 fprintf ((stream), "d%s", reg_names[regno] + 1);
1351 fputs (reg_names[regno], (stream));
1355 output_address (XEXP (x, 0));
1360 fputc ('#', stream);
1361 output_addr_const (stream, x);
1369 /* Encode symbol attributes of a SYMBOL_REF into its
1370 SYMBOL_REF_FLAGS. */
1372 sh_encode_section_info (tree decl, rtx rtl, int first)
1374 default_encode_section_info (decl, rtl, first);
1376 if (TREE_CODE (decl) == FUNCTION_DECL
1377 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1378 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1381 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1383 force_into (rtx value, rtx target)
1385 value = force_operand (value, target);
1386 if (! rtx_equal_p (value, target))
1387 emit_insn (gen_move_insn (target, value));
1390 /* Emit code to perform a block move. Choose the best method.
1392 OPERANDS[0] is the destination.
1393 OPERANDS[1] is the source.
1394 OPERANDS[2] is the size.
1395 OPERANDS[3] is the alignment safe to use. */
1398 expand_block_move (rtx *operands)
1400 int align = INTVAL (operands[3]);
1401 int constp = (CONST_INT_P (operands[2]));
1402 int bytes = (constp ? INTVAL (operands[2]) : 0);
1407 /* If we could use mov.l to move words and dest is word-aligned, we
1408 can use movua.l for loads and still generate a relatively short
1409 and efficient sequence. */
1410 if (TARGET_SH4A_ARCH && align < 4
1411 && MEM_ALIGN (operands[0]) >= 32
1412 && can_move_by_pieces (bytes, 32))
1414 rtx dest = copy_rtx (operands[0]);
1415 rtx src = copy_rtx (operands[1]);
1416 /* We could use different pseudos for each copied word, but
1417 since movua can only load into r0, it's kind of
1419 rtx temp = gen_reg_rtx (SImode);
1420 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1423 while (copied + 4 <= bytes)
1425 rtx to = adjust_address (dest, SImode, copied);
1426 rtx from = adjust_automodify_address (src, BLKmode,
1429 set_mem_size (from, GEN_INT (4));
1430 emit_insn (gen_movua (temp, from));
1431 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1432 emit_move_insn (to, temp);
1437 move_by_pieces (adjust_address (dest, BLKmode, copied),
1438 adjust_automodify_address (src, BLKmode,
1440 bytes - copied, align, 0);
1445 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1446 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1447 if (align < 4 || (bytes % 4 != 0))
1450 if (TARGET_HARD_SH4)
1454 else if (bytes == 12)
1456 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1457 rtx r4 = gen_rtx_REG (SImode, 4);
1458 rtx r5 = gen_rtx_REG (SImode, 5);
1460 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1461 force_into (XEXP (operands[0], 0), r4);
1462 force_into (XEXP (operands[1], 0), r5);
1463 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1466 else if (! TARGET_SMALLCODE)
1468 const char *entry_name;
1469 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1471 rtx r4 = gen_rtx_REG (SImode, 4);
1472 rtx r5 = gen_rtx_REG (SImode, 5);
1473 rtx r6 = gen_rtx_REG (SImode, 6);
1475 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1476 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1477 force_into (XEXP (operands[0], 0), r4);
1478 force_into (XEXP (operands[1], 0), r5);
1480 dwords = bytes >> 3;
1481 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1482 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1491 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1492 rtx r4 = gen_rtx_REG (SImode, 4);
1493 rtx r5 = gen_rtx_REG (SImode, 5);
1495 sprintf (entry, "__movmemSI%d", bytes);
1496 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1497 force_into (XEXP (operands[0], 0), r4);
1498 force_into (XEXP (operands[1], 0), r5);
1499 emit_insn (gen_block_move_real (func_addr_rtx));
1503 /* This is the same number of bytes as a memcpy call, but to a different
1504 less common function name, so this will occasionally use more space. */
1505 if (! TARGET_SMALLCODE)
1507 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1508 int final_switch, while_loop;
1509 rtx r4 = gen_rtx_REG (SImode, 4);
1510 rtx r5 = gen_rtx_REG (SImode, 5);
1511 rtx r6 = gen_rtx_REG (SImode, 6);
1513 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1514 force_into (XEXP (operands[0], 0), r4);
1515 force_into (XEXP (operands[1], 0), r5);
1517 /* r6 controls the size of the move. 16 is decremented from it
1518 for each 64 bytes moved. Then the negative bit left over is used
1519 as an index into a list of move instructions. e.g., a 72 byte move
1520 would be set up with size(r6) = 14, for one iteration through the
1521 big while loop, and a switch of -2 for the last part. */
1523 final_switch = 16 - ((bytes / 4) % 16);
1524 while_loop = ((bytes / 4) / 16 - 1) * 16;
1525 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1526 emit_insn (gen_block_lump_real (func_addr_rtx));
1533 /* Prepare operands for a move define_expand; specifically, one of the
1534 operands must be in a register. */
1537 prepare_move_operands (rtx operands[], enum machine_mode mode)
1539 if ((mode == SImode || mode == DImode)
1541 && ! ((mode == Pmode || mode == ptr_mode)
1542 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1545 if (SYMBOLIC_CONST_P (operands[1]))
1547 if (MEM_P (operands[0]))
1548 operands[1] = force_reg (Pmode, operands[1]);
1549 else if (TARGET_SHMEDIA
1550 && GET_CODE (operands[1]) == LABEL_REF
1551 && target_reg_operand (operands[0], mode))
1555 temp = (!can_create_pseudo_p ()
1557 : gen_reg_rtx (Pmode));
1558 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1561 else if (GET_CODE (operands[1]) == CONST
1562 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1563 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1565 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1566 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1568 operands[1] = expand_binop (mode, add_optab, temp,
1569 XEXP (XEXP (operands[1], 0), 1),
1570 (!can_create_pseudo_p ()
1572 : gen_reg_rtx (Pmode)),
1573 0, OPTAB_LIB_WIDEN);
1577 if (! reload_in_progress && ! reload_completed)
1579 /* Copy the source to a register if both operands aren't registers. */
1580 if (! register_operand (operands[0], mode)
1581 && ! sh_register_operand (operands[1], mode))
1582 operands[1] = copy_to_mode_reg (mode, operands[1]);
1584 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
1586 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1587 except that we can't use that function because it is static. */
1588 rtx new_rtx = change_address (operands[0], mode, 0);
1589 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1590 operands[0] = new_rtx;
1593 /* This case can happen while generating code to move the result
1594 of a library call to the target. Reject `st r0,@(rX,rY)' because
1595 reload will fail to find a spill register for rX, since r0 is already
1596 being used for the source. */
1598 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1599 && MEM_P (operands[0])
1600 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1601 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
1602 operands[1] = copy_to_mode_reg (mode, operands[1]);
1605 if (mode == Pmode || mode == ptr_mode)
1608 enum tls_model tls_kind;
1612 if (GET_CODE (op1) == CONST
1613 && GET_CODE (XEXP (op1, 0)) == PLUS
1614 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1617 opc = XEXP (XEXP (op1, 0), 1);
1618 op1 = XEXP (XEXP (op1, 0), 0);
1623 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1625 rtx tga_op1, tga_ret, tmp, tmp2;
1629 case TLS_MODEL_GLOBAL_DYNAMIC:
1630 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1631 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1635 case TLS_MODEL_LOCAL_DYNAMIC:
1636 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1637 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1639 tmp = gen_reg_rtx (Pmode);
1640 emit_move_insn (tmp, tga_ret);
1642 if (register_operand (op0, Pmode))
1645 tmp2 = gen_reg_rtx (Pmode);
1647 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1651 case TLS_MODEL_INITIAL_EXEC:
1654 /* Don't schedule insns for getting GOT address when
1655 the first scheduling is enabled, to avoid spill
1657 if (flag_schedule_insns)
1658 emit_insn (gen_blockage ());
1659 emit_insn (gen_GOTaddr2picreg ());
1660 emit_use (gen_rtx_REG (SImode, PIC_REG));
1661 if (flag_schedule_insns)
1662 emit_insn (gen_blockage ());
1664 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1665 tmp = gen_sym2GOTTPOFF (op1);
1666 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1670 case TLS_MODEL_LOCAL_EXEC:
1671 tmp2 = gen_reg_rtx (Pmode);
1672 emit_insn (gen_load_gbr (tmp2));
1673 tmp = gen_reg_rtx (Pmode);
1674 emit_insn (gen_symTPOFF2reg (tmp, op1));
1676 if (register_operand (op0, Pmode))
1679 op1 = gen_reg_rtx (Pmode);
1681 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1688 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1697 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1698 enum rtx_code comparison)
1701 rtx scratch = NULL_RTX;
1703 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1704 comparison = GET_CODE (operands[0]);
1706 scratch = operands[4];
1707 if (CONST_INT_P (operands[1])
1708 && !CONST_INT_P (operands[2]))
1710 rtx tmp = operands[1];
1712 operands[1] = operands[2];
1714 comparison = swap_condition (comparison);
1716 if (CONST_INT_P (operands[2]))
1718 HOST_WIDE_INT val = INTVAL (operands[2]);
1719 if ((val == -1 || val == -0x81)
1720 && (comparison == GT || comparison == LE))
1722 comparison = (comparison == GT) ? GE : LT;
1723 operands[2] = gen_int_mode (val + 1, mode);
1725 else if ((val == 1 || val == 0x80)
1726 && (comparison == GE || comparison == LT))
1728 comparison = (comparison == GE) ? GT : LE;
1729 operands[2] = gen_int_mode (val - 1, mode);
1731 else if (val == 1 && (comparison == GEU || comparison == LTU))
1733 comparison = (comparison == GEU) ? NE : EQ;
1734 operands[2] = CONST0_RTX (mode);
1736 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1738 comparison = (comparison == GEU) ? GTU : LEU;
1739 operands[2] = gen_int_mode (val - 1, mode);
1741 else if (val == 0 && (comparison == GTU || comparison == LEU))
1742 comparison = (comparison == GTU) ? NE : EQ;
1743 else if (mode == SImode
1744 && ((val == 0x7fffffff
1745 && (comparison == GTU || comparison == LEU))
1746 || ((unsigned HOST_WIDE_INT) val
1747 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1748 && (comparison == GEU || comparison == LTU))))
1750 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1751 operands[2] = CONST0_RTX (mode);
1755 if (can_create_pseudo_p ())
1756 operands[1] = force_reg (mode, op1);
1757 /* When we are handling DImode comparisons, we want to keep constants so
1758 that we can optimize the component comparisons; however, memory loads
1759 are better issued as a whole so that they can be scheduled well.
1760 SImode equality comparisons allow I08 constants, but only when they
1761 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1762 into a register, that register might as well be r0, and we allow the
1763 constant. If it is already in a register, this is likely to be
1764 allocated to a different hard register, thus we load the constant into
1765 a register unless it is zero. */
1766 if (!REG_P (operands[2])
1767 && (!CONST_INT_P (operands[2])
1768 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1769 && ((comparison != EQ && comparison != NE)
1770 || (REG_P (op1) && REGNO (op1) != R0_REG)
1771 || !satisfies_constraint_I08 (operands[2])))))
1773 if (scratch && GET_MODE (scratch) == mode)
1775 emit_move_insn (scratch, operands[2]);
1776 operands[2] = scratch;
1778 else if (can_create_pseudo_p ())
1779 operands[2] = force_reg (mode, operands[2]);
1785 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1787 rtx (*branch_expander) (rtx) = gen_branch_true;
1790 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1793 case NE: case LT: case LE: case LTU: case LEU:
1794 comparison = reverse_condition (comparison);
1795 branch_expander = gen_branch_false;
1798 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1799 gen_rtx_fmt_ee (comparison, SImode,
1800 operands[1], operands[2])));
1801 jump = emit_jump_insn (branch_expander (operands[3]));
1802 if (probability >= 0)
1803 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
1807 /* ??? How should we distribute probabilities when more than one branch
1808 is generated. So far we only have soem ad-hoc observations:
1809 - If the operands are random, they are likely to differ in both parts.
1810 - If comparing items in a hash chain, the operands are random or equal;
1811 operation should be EQ or NE.
1812 - If items are searched in an ordered tree from the root, we can expect
1813 the highpart to be unequal about half of the time; operation should be
1814 an inequality comparison, operands non-constant, and overall probability
1815 about 50%. Likewise for quicksort.
1816 - Range checks will be often made against constants. Even if we assume for
1817 simplicity an even distribution of the non-constant operand over a
1818 sub-range here, the same probability could be generated with differently
1819 wide sub-ranges - as long as the ratio of the part of the subrange that
1820 is before the threshold to the part that comes after the threshold stays
1821 the same. Thus, we can't really tell anything here;
1822 assuming random distribution is at least simple.
1826 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1828 enum rtx_code msw_taken, msw_skip, lsw_taken;
1829 rtx skip_label = NULL_RTX;
1830 rtx op1h, op1l, op2h, op2l;
1833 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1834 rtx scratch = operands[4];
1836 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1837 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1838 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1839 op1l = gen_lowpart (SImode, operands[1]);
1840 op2l = gen_lowpart (SImode, operands[2]);
1841 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
1842 prob = split_branch_probability;
1843 rev_prob = REG_BR_PROB_BASE - prob;
1846 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1847 That costs 1 cycle more when the first branch can be predicted taken,
1848 but saves us mispredicts because only one branch needs prediction.
1849 It also enables generating the cmpeqdi_t-1 pattern. */
1851 if (TARGET_CMPEQDI_T)
1853 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1854 emit_jump_insn (gen_branch_true (operands[3]));
1861 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1863 msw_skip_prob = rev_prob;
1864 if (REG_BR_PROB_BASE <= 65535)
1865 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1868 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1872 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1873 / ((HOST_WIDEST_INT) prob << 32)))
1879 if (TARGET_CMPEQDI_T)
1881 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1882 emit_jump_insn (gen_branch_false (operands[3]));
1886 msw_taken_prob = prob;
1891 msw_taken = comparison;
1892 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1894 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1895 msw_skip = swap_condition (msw_taken);
1899 if (op2l == CONST0_RTX (SImode))
1900 msw_taken = comparison;
1903 msw_taken = comparison == GE ? GT : GTU;
1904 msw_skip = swap_condition (msw_taken);
1909 msw_taken = comparison;
1910 if (op2l == CONST0_RTX (SImode))
1912 msw_skip = swap_condition (msw_taken);
1916 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1917 msw_taken = comparison;
1921 if (comparison == LE)
1923 else if (op2h != CONST0_RTX (SImode))
1927 msw_skip = swap_condition (msw_taken);
1930 default: return false;
1932 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
1933 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1934 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
1935 if (comparison != EQ && comparison != NE && num_branches > 1)
1937 if (!CONSTANT_P (operands[2])
1938 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1939 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1941 msw_taken_prob = prob / 2U;
1943 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1944 lsw_taken_prob = prob;
1948 msw_taken_prob = prob;
1949 msw_skip_prob = REG_BR_PROB_BASE;
1950 /* ??? If we have a constant op2h, should we use that when
1951 calculating lsw_taken_prob? */
1952 lsw_taken_prob = prob;
1957 operands[4] = NULL_RTX;
1958 if (reload_completed
1959 && ! arith_reg_or_0_operand (op2h, SImode)
1960 && (true_regnum (op1h) || (comparison != EQ && comparison != NE))
1961 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
1962 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
1964 emit_move_insn (scratch, operands[2]);
1965 operands[2] = scratch;
1967 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1968 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
1969 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1971 rtx taken_label = operands[3];
1973 /* Operands were possibly modified, but msw_skip doesn't expect this.
1974 Always use the original ones. */
1975 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1981 operands[3] = skip_label = gen_label_rtx ();
1982 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
1983 operands[3] = taken_label;
1987 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
1989 if (reload_completed
1990 && ! arith_reg_or_0_operand (op2l, SImode)
1991 && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE)))
1993 emit_move_insn (scratch, operands[2]);
1994 operands[2] = scratch;
1996 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
1998 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1999 emit_label (skip_label);
2003 /* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
2006 sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
2008 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
2010 insn = gen_rtx_PARALLEL (VOIDmode,
2012 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
2013 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
2019 /* Prepare the operands for an scc instruction; make sure that the
2020 compare has been done and the result is in T_REG. */
2022 sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
2024 rtx t_reg = gen_rtx_REG (SImode, T_REG);
2025 enum rtx_code oldcode = code;
2026 enum machine_mode mode;
2028 /* First need a compare insn. */
2032 /* It isn't possible to handle this case. */
2049 if (code != oldcode)
2056 mode = GET_MODE (op0);
2057 if (mode == VOIDmode)
2058 mode = GET_MODE (op1);
2060 op0 = force_reg (mode, op0);
2061 if ((code != EQ && code != NE
2062 && (op1 != const0_rtx
2063 || code == GTU || code == GEU || code == LTU || code == LEU))
2064 || (mode == DImode && op1 != const0_rtx)
2065 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2066 op1 = force_reg (mode, op1);
2068 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode, t_reg,
2069 gen_rtx_fmt_ee (code, SImode, op0, op1)),
2074 sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
2077 rtx target = gen_reg_rtx (SImode);
2080 gcc_assert (TARGET_SHMEDIA);
2089 tmp = gen_rtx_fmt_ee (code, SImode, op0, op1);
2090 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2100 tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1);
2101 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2119 rtx t2 = gen_reg_rtx (DImode);
2120 emit_insn (gen_extendsidi2 (t2, target));
2124 return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx);
2127 /* Called from the md file, set up the operands of a compare instruction. */
2130 sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
2132 enum rtx_code code = GET_CODE (operands[0]);
2133 enum rtx_code branch_code;
2134 rtx op0 = operands[1];
2135 rtx op1 = operands[2];
2137 bool need_ccmpeq = false;
2139 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
2141 op0 = force_reg (mode, op0);
2142 op1 = force_reg (mode, op1);
2146 if (code != EQ || mode == DImode)
2148 /* Force args into regs, since we can't use constants here. */
2149 op0 = force_reg (mode, op0);
2150 if (op1 != const0_rtx || code == GTU || code == GEU)
2151 op1 = force_reg (mode, op1);
2155 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2158 || (code == LE && TARGET_IEEE && TARGET_SH2E)
2159 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
2161 tem = op0, op0 = op1, op1 = tem;
2162 code = swap_condition (code);
2165 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2168 gcc_assert (TARGET_IEEE && TARGET_SH2E);
2173 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2174 to EQ/GT respectively. */
2175 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
2192 branch_code = reverse_condition (code);
2198 insn = gen_rtx_SET (VOIDmode,
2199 gen_rtx_REG (SImode, T_REG),
2200 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
2202 sh_emit_set_t_insn (insn, mode);
2204 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
2206 if (branch_code == code)
2207 emit_jump_insn (gen_branch_true (operands[3]));
2209 emit_jump_insn (gen_branch_false (operands[3]));
2213 sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
2215 enum rtx_code code = GET_CODE (operands[1]);
2216 rtx op0 = operands[2];
2217 rtx op1 = operands[3];
2219 bool invert = false;
2222 op0 = force_reg (mode, op0);
2223 if ((code != EQ && code != NE
2224 && (op1 != const0_rtx
2225 || code == GTU || code == GEU || code == LTU || code == LEU))
2226 || (mode == DImode && op1 != const0_rtx)
2227 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2228 op1 = force_reg (mode, op1);
2230 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2232 if (code == LT || code == LE)
2234 code = swap_condition (code);
2235 tem = op0, op0 = op1, op1 = tem;
2241 lab = gen_label_rtx ();
2242 sh_emit_scc_to_t (EQ, op0, op1);
2243 emit_jump_insn (gen_branch_true (lab));
2260 sh_emit_scc_to_t (code, op0, op1);
2264 emit_insn (gen_movnegt (operands[0]));
2266 emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
2269 /* Functions to output assembly code. */
2271 /* Return a sequence of instructions to perform DI or DF move.
2273 Since the SH cannot move a DI or DF in one instruction, we have
2274 to take care when we see overlapping source and dest registers. */
2277 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
2278 enum machine_mode mode)
2280 rtx dst = operands[0];
2281 rtx src = operands[1];
2284 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
2285 return "mov.l %T1,%0\n\tmov.l %1,%0";
2287 if (register_operand (dst, mode)
2288 && register_operand (src, mode))
2290 if (REGNO (src) == MACH_REG)
2291 return "sts mach,%S0\n\tsts macl,%R0";
2293 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2294 when mov.d r1,r0 do r1->r0 then r2->r1. */
2296 if (REGNO (src) + 1 == REGNO (dst))
2297 return "mov %T1,%T0\n\tmov %1,%0";
2299 return "mov %1,%0\n\tmov %T1,%T0";
2301 else if (CONST_INT_P (src))
2303 if (INTVAL (src) < 0)
2304 output_asm_insn ("mov #-1,%S0", operands);
2306 output_asm_insn ("mov #0,%S0", operands);
2308 return "mov %1,%R0";
2310 else if (MEM_P (src))
2313 int dreg = REGNO (dst);
2314 rtx inside = XEXP (src, 0);
2316 switch (GET_CODE (inside))
2319 ptrreg = REGNO (inside);
2323 ptrreg = subreg_regno (inside);
2327 ptrreg = REGNO (XEXP (inside, 0));
2328 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2329 an offsettable address. Unfortunately, offsettable addresses use
2330 QImode to check the offset, and a QImode offsettable address
2331 requires r0 for the other operand, which is not currently
2332 supported, so we can't use the 'o' constraint.
2333 Thus we must check for and handle r0+REG addresses here.
2334 We punt for now, since this is likely very rare. */
2335 gcc_assert (!REG_P (XEXP (inside, 1)));
2339 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2341 return "mov.l %1,%0\n\tmov.l %1,%T0";
2346 /* Work out the safe way to copy. Copy into the second half first. */
2348 return "mov.l %T1,%T0\n\tmov.l %1,%0";
2351 return "mov.l %1,%0\n\tmov.l %T1,%T0";
2354 /* Print an instruction which would have gone into a delay slot after
2355 another instruction, but couldn't because the other instruction expanded
2356 into a sequence where putting the slot insn at the end wouldn't work. */
2359 print_slot (rtx insn)
2361 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
2363 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
2367 output_far_jump (rtx insn, rtx op)
2369 struct { rtx lab, reg, op; } this_jmp;
2370 rtx braf_base_lab = NULL_RTX;
2373 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2376 this_jmp.lab = gen_label_rtx ();
2380 && offset - get_attr_length (insn) <= 32766)
2383 jump = "mov.w %O0,%1; braf %1";
2391 jump = "mov.l %O0,%1; braf %1";
2393 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2396 jump = "mov.l %O0,%1; jmp @%1";
2398 /* If we have a scratch register available, use it. */
2399 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
2400 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2402 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2403 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
2404 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
2405 output_asm_insn (jump, &this_jmp.lab);
2406 if (dbr_sequence_length ())
2407 print_slot (final_sequence);
2409 output_asm_insn ("nop", 0);
2413 /* Output the delay slot insn first if any. */
2414 if (dbr_sequence_length ())
2415 print_slot (final_sequence);
2417 this_jmp.reg = gen_rtx_REG (SImode, 13);
2418 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2419 Fortunately, MACL is fixed and call-clobbered, and we never
2420 need its value across jumps, so save r13 in it instead of in
2423 output_asm_insn ("lds r13, macl", 0);
2425 output_asm_insn ("mov.l r13,@-r15", 0);
2426 output_asm_insn (jump, &this_jmp.lab);
2428 output_asm_insn ("sts macl, r13", 0);
2430 output_asm_insn ("mov.l @r15+,r13", 0);
2432 if (far && flag_pic && TARGET_SH2)
2434 braf_base_lab = gen_label_rtx ();
2435 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2436 CODE_LABEL_NUMBER (braf_base_lab));
2439 output_asm_insn (".align 2", 0);
2440 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2442 if (far && flag_pic)
2445 this_jmp.lab = braf_base_lab;
2446 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
2449 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2453 /* Local label counter, used for constants in the pool and inside
2454 pattern branches. */
2456 static int lf = 100;
2458 /* Output code for ordinary branches. */
2461 output_branch (int logic, rtx insn, rtx *operands)
2463 switch (get_attr_length (insn))
2466 /* This can happen if filling the delay slot has caused a forward
2467 branch to exceed its range (we could reverse it, but only
2468 when we know we won't overextend other branches; this should
2469 best be handled by relaxation).
2470 It can also happen when other condbranches hoist delay slot insn
2471 from their destination, thus leading to code size increase.
2472 But the branch will still be in the range -4092..+4098 bytes. */
2477 /* The call to print_slot will clobber the operands. */
2478 rtx op0 = operands[0];
2480 /* If the instruction in the delay slot is annulled (true), then
2481 there is no delay slot where we can put it now. The only safe
2482 place for it is after the label. final will do that by default. */
2485 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2486 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2488 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2489 ASSEMBLER_DIALECT ? "/" : ".", label);
2490 print_slot (final_sequence);
2493 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2495 output_asm_insn ("bra\t%l0", &op0);
2496 fprintf (asm_out_file, "\tnop\n");
2497 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2501 /* When relaxing, handle this like a short branch. The linker
2502 will fix it up if it still doesn't fit after relaxation. */
2504 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2506 /* These are for SH2e, in which we have to account for the
2507 extra nop because of the hardware bug in annulled branches. */
2513 gcc_assert (!final_sequence
2514 || !(INSN_ANNULLED_BRANCH_P
2515 (XVECEXP (final_sequence, 0, 0))));
2516 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2518 ASSEMBLER_DIALECT ? "/" : ".", label);
2519 fprintf (asm_out_file, "\tnop\n");
2520 output_asm_insn ("bra\t%l0", operands);
2521 fprintf (asm_out_file, "\tnop\n");
2522 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2526 /* When relaxing, fall through. */
2531 sprintf (buffer, "b%s%ss\t%%l0",
2533 ASSEMBLER_DIALECT ? "/" : ".");
2534 output_asm_insn (buffer, &operands[0]);
2539 /* There should be no longer branches now - that would
2540 indicate that something has destroyed the branches set
2541 up in machine_dependent_reorg. */
2546 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2547 fill in operands 9 as a label to the successor insn.
2548 We try to use jump threading where possible.
2549 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2550 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2551 follow jmp and bt, if the address is in range. */
2553 output_branchy_insn (enum rtx_code code, const char *templ,
2554 rtx insn, rtx *operands)
2556 rtx next_insn = NEXT_INSN (insn);
2558 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
2560 rtx src = SET_SRC (PATTERN (next_insn));
2561 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2563 /* Following branch not taken */
2564 operands[9] = gen_label_rtx ();
2565 emit_label_after (operands[9], next_insn);
2566 INSN_ADDRESSES_NEW (operands[9],
2567 INSN_ADDRESSES (INSN_UID (next_insn))
2568 + get_attr_length (next_insn));
2573 int offset = (branch_dest (next_insn)
2574 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2575 if (offset >= -252 && offset <= 258)
2577 if (GET_CODE (src) == IF_THEN_ELSE)
2579 src = XEXP (src, 1);
2585 operands[9] = gen_label_rtx ();
2586 emit_label_after (operands[9], insn);
2587 INSN_ADDRESSES_NEW (operands[9],
2588 INSN_ADDRESSES (INSN_UID (insn))
2589 + get_attr_length (insn));
2594 output_ieee_ccmpeq (rtx insn, rtx *operands)
2596 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2600 /* Output the start of the assembler file. */
2603 sh_file_start (void)
2605 default_file_start ();
2608 /* Declare the .directive section before it is used. */
2609 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2610 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2614 /* We need to show the text section with the proper
2615 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2616 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2617 will complain. We can teach GAS specifically about the
2618 default attributes for our choice of text section, but
2619 then we would have to change GAS again if/when we change
2620 the text section name. */
2621 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2623 /* Switch to the data section so that the coffsem symbol
2624 isn't in the text section. */
2625 switch_to_section (data_section);
2627 if (TARGET_LITTLE_ENDIAN)
2628 fputs ("\t.little\n", asm_out_file);
2632 if (TARGET_SHCOMPACT)
2633 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2634 else if (TARGET_SHMEDIA)
2635 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2636 TARGET_SHMEDIA64 ? 64 : 32);
2640 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2643 unspec_caller_rtx_p (rtx pat)
2648 split_const (pat, &base, &offset);
2649 if (GET_CODE (base) == UNSPEC)
2651 if (XINT (base, 1) == UNSPEC_CALLER)
2653 for (i = 0; i < XVECLEN (base, 0); i++)
2654 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2660 /* Indicate that INSN cannot be duplicated. This is true for insn
2661 that generates a unique label. */
2664 sh_cannot_copy_insn_p (rtx insn)
2668 if (!reload_completed || !flag_pic)
2671 if (!NONJUMP_INSN_P (insn))
2673 if (asm_noperands (insn) >= 0)
2676 pat = PATTERN (insn);
2677 if (GET_CODE (pat) != SET)
2679 pat = SET_SRC (pat);
2681 if (unspec_caller_rtx_p (pat))
2687 /* Actual number of instructions used to make a shift by N. */
2688 static const char ashiftrt_insns[] =
2689 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2691 /* Left shift and logical right shift are the same. */
2692 static const char shift_insns[] =
2693 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2695 /* Individual shift amounts needed to get the above length sequences.
2696 One bit right shifts clobber the T bit, so when possible, put one bit
2697 shifts in the middle of the sequence, so the ends are eligible for
2698 branch delay slots. */
2699 static const short shift_amounts[32][5] = {
2700 {0}, {1}, {2}, {2, 1},
2701 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2702 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2703 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2704 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2705 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2706 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2707 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2709 /* Likewise, but for shift amounts < 16, up to three highmost bits
2710 might be clobbered. This is typically used when combined with some
2711 kind of sign or zero extension. */
2713 static const char ext_shift_insns[] =
2714 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2716 static const short ext_shift_amounts[32][4] = {
2717 {0}, {1}, {2}, {2, 1},
2718 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2719 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2720 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2721 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2722 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2723 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2724 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2726 /* Assuming we have a value that has been sign-extended by at least one bit,
2727 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2728 to shift it by N without data loss, and quicker than by other means? */
2729 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2731 /* This is used in length attributes in sh.md to help compute the length
2732 of arbitrary constant shift instructions. */
2735 shift_insns_rtx (rtx insn)
2737 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2738 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
2739 enum rtx_code shift_code = GET_CODE (set_src);
2744 return ashiftrt_insns[shift_count];
2747 return shift_insns[shift_count];
2753 /* Return the cost of a shift. */
2763 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2765 if (GET_MODE (x) == DImode
2766 && CONST_INT_P (XEXP (x, 1))
2767 && INTVAL (XEXP (x, 1)) == 1)
2770 /* Everything else is invalid, because there is no pattern for it. */
2773 /* If shift by a non constant, then this will be expensive. */
2774 if (!CONST_INT_P (XEXP (x, 1)))
2775 return SH_DYNAMIC_SHIFT_COST;
2777 /* Otherwise, return the true cost in instructions. Cope with out of range
2778 shift counts more or less arbitrarily. */
2779 value = INTVAL (XEXP (x, 1)) & 31;
2781 if (GET_CODE (x) == ASHIFTRT)
2783 int cost = ashiftrt_insns[value];
2784 /* If SH3, then we put the constant in a reg and use shad. */
2785 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2786 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2790 return shift_insns[value];
2793 /* Return the cost of an AND operation. */
2800 /* Anding with a register is a single cycle and instruction. */
2801 if (!CONST_INT_P (XEXP (x, 1)))
2804 i = INTVAL (XEXP (x, 1));
2808 if (satisfies_constraint_I10 (XEXP (x, 1))
2809 || satisfies_constraint_J16 (XEXP (x, 1)))
2812 return 1 + rtx_cost (XEXP (x, 1), AND, !optimize_size);
2815 /* These constants are single cycle extu.[bw] instructions. */
2816 if (i == 0xff || i == 0xffff)
2818 /* Constants that can be used in an and immediate instruction in a single
2819 cycle, but this requires r0, so make it a little more expensive. */
2820 if (CONST_OK_FOR_K08 (i))
2822 /* Constants that can be loaded with a mov immediate and an and.
2823 This case is probably unnecessary. */
2824 if (CONST_OK_FOR_I08 (i))
2826 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2827 This case is probably unnecessary. */
2831 /* Return the cost of an addition or a subtraction. */
2836 /* Adding a register is a single cycle insn. */
2837 if (REG_P (XEXP (x, 1))
2838 || GET_CODE (XEXP (x, 1)) == SUBREG)
2841 /* Likewise for small constants. */
2842 if (CONST_INT_P (XEXP (x, 1))
2843 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2847 switch (GET_CODE (XEXP (x, 1)))
2852 return TARGET_SHMEDIA64 ? 5 : 3;
2855 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2857 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2859 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2867 /* Any other constant requires a 2 cycle pc-relative load plus an
2872 /* Return the cost of a multiply. */
2874 multcosts (rtx x ATTRIBUTE_UNUSED)
2876 if (sh_multcost >= 0)
2879 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2880 accept constants. Ideally, we would use a cost of one or two and
2881 add the cost of the operand, but disregard the latter when inside loops
2882 and loop invariant code motion is still to follow.
2883 Using a multiply first and splitting it later if it's a loss
2884 doesn't work because of different sign / zero extension semantics
2885 of multiplies vs. shifts. */
2886 return TARGET_SMALLCODE ? 2 : 3;
2890 /* We have a mul insn, so we can never take more than the mul and the
2891 read of the mac reg, but count more because of the latency and extra
2893 if (TARGET_SMALLCODE)
2898 /* If we're aiming at small code, then just count the number of
2899 insns in a multiply call sequence. */
2900 if (TARGET_SMALLCODE)
2903 /* Otherwise count all the insns in the routine we'd be calling too. */
2907 /* Compute a (partial) cost for rtx X. Return true if the complete
2908 cost has been computed, and false if subexpressions should be
2909 scanned. In either case, *TOTAL contains the cost result. */
2912 sh_rtx_costs (rtx x, int code, int outer_code, int *total,
2913 bool speed ATTRIBUTE_UNUSED)
2920 if (INTVAL (x) == 0)
2922 else if (outer_code == AND && and_operand ((x), DImode))
2924 else if ((outer_code == IOR || outer_code == XOR
2925 || outer_code == PLUS)
2926 && CONST_OK_FOR_I10 (INTVAL (x)))
2928 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2929 *total = COSTS_N_INSNS (outer_code != SET);
2930 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2931 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2932 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2933 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2935 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2938 if (CONST_OK_FOR_I08 (INTVAL (x)))
2940 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2941 && CONST_OK_FOR_K08 (INTVAL (x)))
2943 /* prepare_cmp_insn will force costly constants int registers before
2944 the cbranch[sd]i4 patterns can see them, so preserve potentially
2945 interesting ones not covered by I08 above. */
2946 else if (outer_code == COMPARE
2947 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2948 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2949 || INTVAL (x) == 0x7fffffff
2950 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2959 if (TARGET_SHMEDIA64)
2960 *total = COSTS_N_INSNS (4);
2961 else if (TARGET_SHMEDIA32)
2962 *total = COSTS_N_INSNS (2);
2969 *total = COSTS_N_INSNS (4);
2970 /* prepare_cmp_insn will force costly constants int registers before
2971 the cbranchdi4 pattern can see them, so preserve potentially
2972 interesting ones. */
2973 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
2979 if (x == CONST0_RTX (GET_MODE (x)))
2981 else if (sh_1el_vec (x, VOIDmode))
2982 *total = outer_code != SET;
2983 if (sh_rep_vec (x, VOIDmode))
2984 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2985 + (outer_code != SET));
2986 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2991 *total = COSTS_N_INSNS (addsubcosts (x));
2995 *total = COSTS_N_INSNS (andcosts (x));
2999 *total = COSTS_N_INSNS (multcosts (x));
3005 *total = COSTS_N_INSNS (shiftcosts (x));
3012 *total = COSTS_N_INSNS (20);
3016 if (sh_1el_vec (x, VOIDmode))
3017 *total = outer_code != SET;
3018 if (sh_rep_vec (x, VOIDmode))
3019 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3020 + (outer_code != SET));
3021 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3034 /* Compute the cost of an address. For the SH, all valid addresses are
3035 the same cost. Use a slightly higher cost for reg + reg addressing,
3036 since it increases pressure on r0. */
3039 sh_address_cost (rtx X,
3040 bool speed ATTRIBUTE_UNUSED)
3042 return (GET_CODE (X) == PLUS
3043 && ! CONSTANT_P (XEXP (X, 1))
3044 && ! TARGET_SHMEDIA ? 1 : 0);
3047 /* Code to expand a shift. */
3050 gen_ashift (int type, int n, rtx reg)
3052 /* Negative values here come from the shift_amounts array. */
3065 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
3069 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
3071 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
3074 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
3079 /* Same for HImode */
3082 gen_ashift_hi (int type, int n, rtx reg)
3084 /* Negative values here come from the shift_amounts array. */
3098 /* We don't have HImode right shift operations because using the
3099 ordinary 32 bit shift instructions for that doesn't generate proper
3100 zero/sign extension.
3101 gen_ashift_hi is only called in contexts where we know that the
3102 sign extension works out correctly. */
3105 if (GET_CODE (reg) == SUBREG)
3107 offset = SUBREG_BYTE (reg);
3108 reg = SUBREG_REG (reg);
3110 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
3114 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
3119 /* Output RTL to split a constant shift into its component SH constant
3120 shift instructions. */
3123 gen_shifty_op (int code, rtx *operands)
3125 int value = INTVAL (operands[2]);
3128 /* Truncate the shift count in case it is out of bounds. */
3133 if (code == LSHIFTRT)
3135 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3136 emit_insn (gen_movt (operands[0]));
3139 else if (code == ASHIFT)
3141 /* There is a two instruction sequence for 31 bit left shifts,
3142 but it requires r0. */
3143 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
3145 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
3146 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3151 else if (value == 0)
3153 /* This can happen even when optimizing, if there were subregs before
3154 reload. Don't output a nop here, as this is never optimized away;
3155 use a no-op move instead. */
3156 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
3160 max = shift_insns[value];
3161 for (i = 0; i < max; i++)
3162 gen_ashift (code, shift_amounts[value][i], operands[0]);
3165 /* Same as above, but optimized for values where the topmost bits don't
3169 gen_shifty_hi_op (int code, rtx *operands)
3171 int value = INTVAL (operands[2]);
3173 void (*gen_fun) (int, int, rtx);
3175 /* This operation is used by and_shl for SImode values with a few
3176 high bits known to be cleared. */
3180 emit_insn (gen_nop ());
3184 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
3187 max = ext_shift_insns[value];
3188 for (i = 0; i < max; i++)
3189 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3192 /* When shifting right, emit the shifts in reverse order, so that
3193 solitary negative values come first. */
3194 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
3195 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3198 /* Output RTL for an arithmetic right shift. */
3200 /* ??? Rewrite to use super-optimizer sequences. */
3203 expand_ashiftrt (rtx *operands)
3211 if (!CONST_INT_P (operands[2]))
3213 rtx count = copy_to_mode_reg (SImode, operands[2]);
3214 emit_insn (gen_negsi2 (count, count));
3215 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3218 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
3219 > 1 + SH_DYNAMIC_SHIFT_COST)
3222 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
3223 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3227 if (!CONST_INT_P (operands[2]))
3230 value = INTVAL (operands[2]) & 31;
3234 /* If we are called from abs expansion, arrange things so that we
3235 we can use a single MT instruction that doesn't clobber the source,
3236 if LICM can hoist out the load of the constant zero. */
3237 if (currently_expanding_to_rtl)
3239 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
3241 emit_insn (gen_mov_neg_si_t (operands[0]));
3244 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
3247 else if (value >= 16 && value <= 19)
3249 wrk = gen_reg_rtx (SImode);
3250 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
3253 gen_ashift (ASHIFTRT, 1, wrk);
3254 emit_move_insn (operands[0], wrk);
3257 /* Expand a short sequence inline, longer call a magic routine. */
3258 else if (value <= 5)
3260 wrk = gen_reg_rtx (SImode);
3261 emit_move_insn (wrk, operands[1]);
3263 gen_ashift (ASHIFTRT, 1, wrk);
3264 emit_move_insn (operands[0], wrk);
3268 wrk = gen_reg_rtx (Pmode);
3270 /* Load the value into an arg reg and call a helper. */
3271 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
3272 sprintf (func, "__ashiftrt_r4_%d", value);
3273 function_symbol (wrk, func, SFUNC_STATIC);
3274 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
3275 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
3280 sh_dynamicalize_shift_p (rtx count)
3282 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
3285 /* Try to find a good way to implement the combiner pattern
3286 [(set (match_operand:SI 0 "register_operand" "r")
3287 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3288 (match_operand:SI 2 "const_int_operand" "n"))
3289 (match_operand:SI 3 "const_int_operand" "n"))) .
3290 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3291 return 0 for simple right / left or left/right shift combination.
3292 return 1 for a combination of shifts with zero_extend.
3293 return 2 for a combination of shifts with an AND that needs r0.
3294 return 3 for a combination of shifts with an AND that needs an extra
3295 scratch register, when the three highmost bits of the AND mask are clear.
3296 return 4 for a combination of shifts with an AND that needs an extra
3297 scratch register, when any of the three highmost bits of the AND mask
3299 If ATTRP is set, store an initial right shift width in ATTRP[0],
3300 and the instruction length in ATTRP[1] . These values are not valid
3302 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3303 shift_amounts for the last shift value that is to be used before the
3306 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
3308 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
3309 int left = INTVAL (left_rtx), right;
3311 int cost, best_cost = 10000;
3312 int best_right = 0, best_len = 0;
3316 if (left < 0 || left > 31)
3318 if (CONST_INT_P (mask_rtx))
3319 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3321 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
3322 /* Can this be expressed as a right shift / left shift pair? */
3323 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3324 right = exact_log2 (lsb);
3325 mask2 = ~(mask + lsb - 1);
3326 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3327 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3329 best_cost = shift_insns[right] + shift_insns[right + left];
3330 /* mask has no trailing zeroes <==> ! right */
3331 else if (! right && mask2 == ~(lsb2 - 1))
3333 int late_right = exact_log2 (lsb2);
3334 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
3336 /* Try to use zero extend. */
3337 if (mask2 == ~(lsb2 - 1))
3341 for (width = 8; width <= 16; width += 8)
3343 /* Can we zero-extend right away? */
3344 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
3347 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
3348 if (cost < best_cost)
3359 /* ??? Could try to put zero extend into initial right shift,
3360 or even shift a bit left before the right shift. */
3361 /* Determine value of first part of left shift, to get to the
3362 zero extend cut-off point. */
3363 first = width - exact_log2 (lsb2) + right;
3364 if (first >= 0 && right + left - first >= 0)
3366 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
3367 + ext_shift_insns[right + left - first];
3368 if (cost < best_cost)
3380 /* Try to use r0 AND pattern */
3381 for (i = 0; i <= 2; i++)
3385 if (! CONST_OK_FOR_K08 (mask >> i))
3387 cost = (i != 0) + 2 + ext_shift_insns[left + i];
3388 if (cost < best_cost)
3393 best_len = cost - 1;
3396 /* Try to use a scratch register to hold the AND operand. */
3397 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
3398 for (i = 0; i <= 2; i++)
3402 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
3403 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
3404 if (cost < best_cost)
3409 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
3415 attrp[0] = best_right;
3416 attrp[1] = best_len;
3421 /* This is used in length attributes of the unnamed instructions
3422 corresponding to shl_and_kind return values of 1 and 2. */
3424 shl_and_length (rtx insn)
3426 rtx set_src, left_rtx, mask_rtx;
3429 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3430 left_rtx = XEXP (XEXP (set_src, 0), 1);
3431 mask_rtx = XEXP (set_src, 1);
3432 shl_and_kind (left_rtx, mask_rtx, attributes);
3433 return attributes[1];
3436 /* This is used in length attribute of the and_shl_scratch instruction. */
3439 shl_and_scr_length (rtx insn)
3441 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3442 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
3443 rtx op = XEXP (set_src, 0);
3444 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
3445 op = XEXP (XEXP (op, 0), 0);
3446 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
3449 /* Generate rtl for instructions for which shl_and_kind advised a particular
3450 method of generating them, i.e. returned zero. */
3453 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
3456 unsigned HOST_WIDE_INT mask;
3457 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3458 int right, total_shift;
3459 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
3461 right = attributes[0];
3462 total_shift = INTVAL (left_rtx) + right;
3463 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3470 int first = attributes[2];
3475 emit_insn ((mask << right) <= 0xff
3476 ? gen_zero_extendqisi2 (dest,
3477 gen_lowpart (QImode, source))
3478 : gen_zero_extendhisi2 (dest,
3479 gen_lowpart (HImode, source)));
3483 emit_insn (gen_movsi (dest, source));
3487 operands[2] = GEN_INT (right);
3488 gen_shifty_hi_op (LSHIFTRT, operands);
3492 operands[2] = GEN_INT (first);
3493 gen_shifty_hi_op (ASHIFT, operands);
3494 total_shift -= first;
3498 emit_insn (mask <= 0xff
3499 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3500 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3501 if (total_shift > 0)
3503 operands[2] = GEN_INT (total_shift);
3504 gen_shifty_hi_op (ASHIFT, operands);
3509 shift_gen_fun = gen_shifty_op;
3511 /* If the topmost bit that matters is set, set the topmost bits
3512 that don't matter. This way, we might be able to get a shorter
3514 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3515 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3517 /* Don't expand fine-grained when combining, because that will
3518 make the pattern fail. */
3519 if (currently_expanding_to_rtl
3520 || reload_in_progress || reload_completed)
3524 /* Cases 3 and 4 should be handled by this split
3525 only while combining */
3526 gcc_assert (kind <= 2);
3529 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3532 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3537 operands[2] = GEN_INT (total_shift);
3538 shift_gen_fun (ASHIFT, operands);
3545 if (kind != 4 && total_shift < 16)
3547 neg = -ext_shift_amounts[total_shift][1];
3549 neg -= ext_shift_amounts[total_shift][2];
3553 emit_insn (gen_and_shl_scratch (dest, source,
3556 GEN_INT (total_shift + neg),
3558 emit_insn (gen_movsi (dest, dest));
3565 /* Try to find a good way to implement the combiner pattern
3566 [(set (match_operand:SI 0 "register_operand" "=r")
3567 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3568 (match_operand:SI 2 "const_int_operand" "n")
3569 (match_operand:SI 3 "const_int_operand" "n")
3571 (clobber (reg:SI T_REG))]
3572 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3573 return 0 for simple left / right shift combination.
3574 return 1 for left shift / 8 bit sign extend / left shift.
3575 return 2 for left shift / 16 bit sign extend / left shift.
3576 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3577 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3578 return 5 for left shift / 16 bit sign extend / right shift
3579 return 6 for < 8 bit sign extend / left shift.
3580 return 7 for < 8 bit sign extend / left shift / single right shift.
3581 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3584 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3586 int left, size, insize, ext;
3587 int cost = 0, best_cost;
3590 left = INTVAL (left_rtx);
3591 size = INTVAL (size_rtx);
3592 insize = size - left;
3593 gcc_assert (insize > 0);
3594 /* Default to left / right shift. */
3596 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3599 /* 16 bit shift / sign extend / 16 bit shift */
3600 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3601 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3602 below, by alternative 3 or something even better. */
3603 if (cost < best_cost)
3609 /* Try a plain sign extend between two shifts. */
3610 for (ext = 16; ext >= insize; ext -= 8)
3614 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3615 if (cost < best_cost)
3617 kind = ext / (unsigned) 8;
3621 /* Check if we can do a sloppy shift with a final signed shift
3622 restoring the sign. */
3623 if (EXT_SHIFT_SIGNED (size - ext))
3624 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3625 /* If not, maybe it's still cheaper to do the second shift sloppy,
3626 and do a final sign extend? */
3627 else if (size <= 16)
3628 cost = ext_shift_insns[ext - insize] + 1
3629 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3632 if (cost < best_cost)
3634 kind = ext / (unsigned) 8 + 2;
3638 /* Check if we can sign extend in r0 */
3641 cost = 3 + shift_insns[left];
3642 if (cost < best_cost)
3647 /* Try the same with a final signed shift. */
3650 cost = 3 + ext_shift_insns[left + 1] + 1;
3651 if (cost < best_cost)
3660 /* Try to use a dynamic shift. */
3661 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3662 if (cost < best_cost)
3673 /* Function to be used in the length attribute of the instructions
3674 implementing this pattern. */
3677 shl_sext_length (rtx insn)
3679 rtx set_src, left_rtx, size_rtx;
3682 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3683 left_rtx = XEXP (XEXP (set_src, 0), 1);
3684 size_rtx = XEXP (set_src, 1);
3685 shl_sext_kind (left_rtx, size_rtx, &cost);
3689 /* Generate rtl for this pattern */
3692 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3695 int left, size, insize, cost;
3698 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3699 left = INTVAL (left_rtx);
3700 size = INTVAL (size_rtx);
3701 insize = size - left;
3709 int ext = kind & 1 ? 8 : 16;
3710 int shift2 = size - ext;
3712 /* Don't expand fine-grained when combining, because that will
3713 make the pattern fail. */
3714 if (! currently_expanding_to_rtl
3715 && ! reload_in_progress && ! reload_completed)
3717 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3718 emit_insn (gen_movsi (dest, source));
3722 emit_insn (gen_movsi (dest, source));
3726 operands[2] = GEN_INT (ext - insize);
3727 gen_shifty_hi_op (ASHIFT, operands);
3730 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3731 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3736 operands[2] = GEN_INT (shift2);
3737 gen_shifty_op (ASHIFT, operands);
3744 if (EXT_SHIFT_SIGNED (shift2))
3746 operands[2] = GEN_INT (shift2 + 1);
3747 gen_shifty_op (ASHIFT, operands);
3748 operands[2] = const1_rtx;
3749 gen_shifty_op (ASHIFTRT, operands);
3752 operands[2] = GEN_INT (shift2);
3753 gen_shifty_hi_op (ASHIFT, operands);
3757 operands[2] = GEN_INT (-shift2);
3758 gen_shifty_hi_op (LSHIFTRT, operands);
3760 emit_insn (size <= 8
3761 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3762 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3769 if (! currently_expanding_to_rtl
3770 && ! reload_in_progress && ! reload_completed)
3771 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3775 operands[2] = GEN_INT (16 - insize);
3776 gen_shifty_hi_op (ASHIFT, operands);
3777 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3779 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3781 gen_ashift (ASHIFTRT, 1, dest);
3786 /* Don't expand fine-grained when combining, because that will
3787 make the pattern fail. */
3788 if (! currently_expanding_to_rtl
3789 && ! reload_in_progress && ! reload_completed)
3791 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3792 emit_insn (gen_movsi (dest, source));
3795 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3796 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3797 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3799 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3800 gen_shifty_op (ASHIFT, operands);
3802 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3810 /* Prefix a symbol_ref name with "datalabel". */
3813 gen_datalabel_ref (rtx sym)
3817 if (GET_CODE (sym) == LABEL_REF)
3818 return gen_rtx_CONST (GET_MODE (sym),
3819 gen_rtx_UNSPEC (GET_MODE (sym),
3823 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3825 str = XSTR (sym, 0);
3826 /* Share all SYMBOL_REF strings with the same value - that is important
3828 str = IDENTIFIER_POINTER (get_identifier (str));
3829 XSTR (sym, 0) = str;
3835 static alloc_pool label_ref_list_pool;
3837 typedef struct label_ref_list_d
3840 struct label_ref_list_d *next;
3841 } *label_ref_list_t;
3843 /* The SH cannot load a large constant into a register, constants have to
3844 come from a pc relative load. The reference of a pc relative load
3845 instruction must be less than 1k in front of the instruction. This
3846 means that we often have to dump a constant inside a function, and
3847 generate code to branch around it.
3849 It is important to minimize this, since the branches will slow things
3850 down and make things bigger.
3852 Worst case code looks like:
3870 We fix this by performing a scan before scheduling, which notices which
3871 instructions need to have their operands fetched from the constant table
3872 and builds the table.
3876 scan, find an instruction which needs a pcrel move. Look forward, find the
3877 last barrier which is within MAX_COUNT bytes of the requirement.
3878 If there isn't one, make one. Process all the instructions between
3879 the find and the barrier.
3881 In the above example, we can tell that L3 is within 1k of L1, so
3882 the first move can be shrunk from the 3 insn+constant sequence into
3883 just 1 insn, and the constant moved to L3 to make:
3894 Then the second move becomes the target for the shortening process. */
3898 rtx value; /* Value in table. */
3899 rtx label; /* Label of value. */
3900 label_ref_list_t wend; /* End of window. */
3901 enum machine_mode mode; /* Mode of value. */
3903 /* True if this constant is accessed as part of a post-increment
3904 sequence. Note that HImode constants are never accessed in this way. */
3905 bool part_of_sequence_p;
3908 /* The maximum number of constants that can fit into one pool, since
3909 constants in the range 0..510 are at least 2 bytes long, and in the
3910 range from there to 1018 at least 4 bytes. */
3912 #define MAX_POOL_SIZE 372
3913 static pool_node pool_vector[MAX_POOL_SIZE];
3914 static int pool_size;
3915 static rtx pool_window_label;
3916 static int pool_window_last;
3918 static int max_labelno_before_reorg;
3920 /* ??? If we need a constant in HImode which is the truncated value of a
3921 constant we need in SImode, we could combine the two entries thus saving
3922 two bytes. Is this common enough to be worth the effort of implementing
3925 /* ??? This stuff should be done at the same time that we shorten branches.
3926 As it is now, we must assume that all branches are the maximum size, and
3927 this causes us to almost always output constant pools sooner than
3930 /* Add a constant to the pool and return its label. */
3933 add_constant (rtx x, enum machine_mode mode, rtx last_value)
3937 label_ref_list_t ref, newref;
3939 /* First see if we've already got it. */
3940 for (i = 0; i < pool_size; i++)
3942 if (x->code == pool_vector[i].value->code
3943 && mode == pool_vector[i].mode)
3945 if (x->code == CODE_LABEL)
3947 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3950 if (rtx_equal_p (x, pool_vector[i].value))
3955 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3957 new_rtx = gen_label_rtx ();
3958 LABEL_REFS (new_rtx) = pool_vector[i].label;
3959 pool_vector[i].label = lab = new_rtx;
3961 if (lab && pool_window_label)
3963 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3964 newref->label = pool_window_label;
3965 ref = pool_vector[pool_window_last].wend;
3967 pool_vector[pool_window_last].wend = newref;
3970 pool_window_label = new_rtx;
3971 pool_window_last = i;
3977 /* Need a new one. */
3978 pool_vector[pool_size].value = x;
3979 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3982 pool_vector[pool_size - 1].part_of_sequence_p = true;
3985 lab = gen_label_rtx ();
3986 pool_vector[pool_size].mode = mode;
3987 pool_vector[pool_size].label = lab;
3988 pool_vector[pool_size].wend = NULL;
3989 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
3990 if (lab && pool_window_label)
3992 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3993 newref->label = pool_window_label;
3994 ref = pool_vector[pool_window_last].wend;
3996 pool_vector[pool_window_last].wend = newref;
3999 pool_window_label = lab;
4000 pool_window_last = pool_size;
4005 /* Output the literal table. START, if nonzero, is the first instruction
4006 this table is needed for, and also indicates that there is at least one
4007 casesi_worker_2 instruction; We have to emit the operand3 labels from
4008 these insns at a 4-byte aligned position. BARRIER is the barrier
4009 after which we are to place the table. */
4012 dump_table (rtx start, rtx barrier)
4018 label_ref_list_t ref;
4021 /* Do two passes, first time dump out the HI sized constants. */
4023 for (i = 0; i < pool_size; i++)
4025 pool_node *p = &pool_vector[i];
4027 if (p->mode == HImode)
4031 scan = emit_insn_after (gen_align_2 (), scan);
4034 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4035 scan = emit_label_after (lab, scan);
4036 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
4038 for (ref = p->wend; ref; ref = ref->next)
4041 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4044 else if (p->mode == DFmode)
4052 scan = emit_insn_after (gen_align_4 (), scan);
4054 for (; start != barrier; start = NEXT_INSN (start))
4055 if (NONJUMP_INSN_P (start)
4056 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
4058 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
4059 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
4061 scan = emit_label_after (lab, scan);
4064 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
4066 rtx align_insn = NULL_RTX;
4068 scan = emit_label_after (gen_label_rtx (), scan);
4069 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4072 for (i = 0; i < pool_size; i++)
4074 pool_node *p = &pool_vector[i];
4082 if (align_insn && !p->part_of_sequence_p)
4084 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4085 emit_label_before (lab, align_insn);
4086 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
4088 for (ref = p->wend; ref; ref = ref->next)
4091 emit_insn_before (gen_consttable_window_end (lab),
4094 delete_insn (align_insn);
4095 align_insn = NULL_RTX;
4100 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4101 scan = emit_label_after (lab, scan);
4102 scan = emit_insn_after (gen_consttable_4 (p->value,
4104 need_align = ! need_align;
4110 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4115 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4116 scan = emit_label_after (lab, scan);
4117 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4124 if (p->mode != HImode)
4126 for (ref = p->wend; ref; ref = ref->next)
4129 scan = emit_insn_after (gen_consttable_window_end (lab),
4138 for (i = 0; i < pool_size; i++)
4140 pool_node *p = &pool_vector[i];
4151 scan = emit_label_after (gen_label_rtx (), scan);
4152 scan = emit_insn_after (gen_align_4 (), scan);
4154 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4155 scan = emit_label_after (lab, scan);
4156 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
4164 scan = emit_label_after (gen_label_rtx (), scan);
4165 scan = emit_insn_after (gen_align_4 (), scan);
4167 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4168 scan = emit_label_after (lab, scan);
4169 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4176 if (p->mode != HImode)
4178 for (ref = p->wend; ref; ref = ref->next)
4181 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4186 scan = emit_insn_after (gen_consttable_end (), scan);
4187 scan = emit_barrier_after (scan);
4189 pool_window_label = NULL_RTX;
4190 pool_window_last = 0;
4193 /* Return nonzero if constant would be an ok source for a
4194 mov.w instead of a mov.l. */
4199 return (CONST_INT_P (src)
4200 && INTVAL (src) >= -32768
4201 && INTVAL (src) <= 32767);
4204 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4206 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4208 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4209 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4210 need to fix it if the input value is CONST_OK_FOR_I08. */
4213 broken_move (rtx insn)
4215 if (NONJUMP_INSN_P (insn))
4217 rtx pat = PATTERN (insn);
4218 if (GET_CODE (pat) == PARALLEL)
4219 pat = XVECEXP (pat, 0, 0);
4220 if (GET_CODE (pat) == SET
4221 /* We can load any 8-bit value if we don't care what the high
4222 order bits end up as. */
4223 && GET_MODE (SET_DEST (pat)) != QImode
4224 && (CONSTANT_P (SET_SRC (pat))
4225 /* Match mova_const. */
4226 || (GET_CODE (SET_SRC (pat)) == UNSPEC
4227 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
4228 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
4230 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
4231 && (fp_zero_operand (SET_SRC (pat))
4232 || fp_one_operand (SET_SRC (pat)))
4233 /* In general we don't know the current setting of fpscr, so disable fldi.
4234 There is an exception if this was a register-register move
4235 before reload - and hence it was ascertained that we have
4236 single precision setting - and in a post-reload optimization
4237 we changed this to do a constant load. In that case
4238 we don't have an r0 clobber, hence we must use fldi. */
4240 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
4242 && REG_P (SET_DEST (pat))
4243 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
4245 && GET_MODE (SET_DEST (pat)) == SImode
4246 && (satisfies_constraint_I20 (SET_SRC (pat))
4247 || satisfies_constraint_I28 (SET_SRC (pat))))
4248 && ! satisfies_constraint_I08 (SET_SRC (pat)))
4258 return (NONJUMP_INSN_P (insn)
4259 && GET_CODE (PATTERN (insn)) == SET
4260 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
4261 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
4262 /* Don't match mova_const. */
4263 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
4266 /* Fix up a mova from a switch that went out of range. */
4268 fixup_mova (rtx mova)
4270 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
4273 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
4274 INSN_CODE (mova) = -1;
4279 rtx lab = gen_label_rtx ();
4280 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
4284 worker = NEXT_INSN (worker);
4286 && !LABEL_P (worker)
4287 && !JUMP_P (worker));
4288 } while (NOTE_P (worker)
4289 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
4290 wpat = PATTERN (worker);
4291 wpat0 = XVECEXP (wpat, 0, 0);
4292 wpat1 = XVECEXP (wpat, 0, 1);
4293 wsrc = SET_SRC (wpat0);
4294 PATTERN (worker) = (gen_casesi_worker_2
4295 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
4296 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
4298 INSN_CODE (worker) = -1;
4299 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4300 base = gen_rtx_LABEL_REF (Pmode, lab);
4301 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
4302 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
4303 INSN_CODE (mova) = -1;
4307 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4308 *num_mova, and check if the new mova is not nested within the first one.
4309 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4310 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4312 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
4314 int n_addr = 0; /* Initialization to shut up spurious warning. */
4315 int f_target, n_target = 0; /* Likewise. */
4319 /* If NEW_MOVA has no address yet, it will be handled later. */
4320 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4323 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4324 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4325 if (n_addr > n_target || n_addr + 1022 < n_target)
4327 /* Change the mova into a load.
4328 broken_move will then return true for it. */
4329 fixup_mova (new_mova);
4335 *first_mova = new_mova;
4340 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4345 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4346 > n_target - n_addr)
4348 fixup_mova (*first_mova);
4353 fixup_mova (new_mova);
4358 /* Find the last barrier from insn FROM which is close enough to hold the
4359 constant pool. If we can't find one, then create one near the end of
4363 find_barrier (int num_mova, rtx mova, rtx from)
4372 int leading_mova = num_mova;
4373 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
4378 /* For HImode: range is 510, add 4 because pc counts from address of
4379 second instruction after this one, subtract 2 for the jump instruction
4380 that we may need to emit before the table, subtract 2 for the instruction
4381 that fills the jump delay slot (in very rare cases, reorg will take an
4382 instruction from after the constant pool or will leave the delay slot
4383 empty). This gives 510.
4384 For SImode: range is 1020, add 4 because pc counts from address of
4385 second instruction after this one, subtract 2 in case pc is 2 byte
4386 aligned, subtract 2 for the jump instruction that we may need to emit
4387 before the table, subtract 2 for the instruction that fills the jump
4388 delay slot. This gives 1018. */
4390 /* The branch will always be shortened now that the reference address for
4391 forward branches is the successor address, thus we need no longer make
4392 adjustments to the [sh]i_limit for -O0. */
4397 while (from && count_si < si_limit && count_hi < hi_limit)
4399 int inc = get_attr_length (from);
4402 /* If this is a label that existed at the time of the compute_alignments
4403 call, determine the alignment. N.B. When find_barrier recurses for
4404 an out-of-reach mova, we might see labels at the start of previously
4405 inserted constant tables. */
4407 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
4410 new_align = 1 << label_to_alignment (from);
4411 else if (BARRIER_P (prev_nonnote_insn (from)))
4412 new_align = 1 << barrier_align (from);
4417 /* In case we are scanning a constant table because of recursion, check
4418 for explicit alignments. If the table is long, we might be forced
4419 to emit the new table in front of it; the length of the alignment
4420 might be the last straw. */
4421 else if (NONJUMP_INSN_P (from)
4422 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4423 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4424 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4425 /* When we find the end of a constant table, paste the new constant
4426 at the end. That is better than putting it in front because
4427 this way, we don't need extra alignment for adding a 4-byte-aligned
4428 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4429 else if (NONJUMP_INSN_P (from)
4430 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4431 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4434 if (BARRIER_P (from))
4438 found_barrier = from;
4440 /* If we are at the end of the function, or in front of an alignment
4441 instruction, we need not insert an extra alignment. We prefer
4442 this kind of barrier. */
4443 if (barrier_align (from) > 2)
4444 good_barrier = from;
4446 /* If we are at the end of a hot/cold block, dump the constants
4448 next = NEXT_INSN (from);
4451 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4455 if (broken_move (from))
4458 enum machine_mode mode;
4460 pat = PATTERN (from);
4461 if (GET_CODE (pat) == PARALLEL)
4462 pat = XVECEXP (pat, 0, 0);
4463 src = SET_SRC (pat);
4464 dst = SET_DEST (pat);
4465 mode = GET_MODE (dst);
4467 /* We must explicitly check the mode, because sometimes the
4468 front end will generate code to load unsigned constants into
4469 HImode targets without properly sign extending them. */
4471 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
4474 /* We put the short constants before the long constants, so
4475 we must count the length of short constants in the range
4476 for the long constants. */
4477 /* ??? This isn't optimal, but is easy to do. */
4482 /* We dump DF/DI constants before SF/SI ones, because
4483 the limit is the same, but the alignment requirements
4484 are higher. We may waste up to 4 additional bytes
4485 for alignment, and the DF/DI constant may have
4486 another SF/SI constant placed before it. */
4487 if (TARGET_SHCOMPACT
4489 && (mode == DFmode || mode == DImode))
4494 while (si_align > 2 && found_si + si_align - 2 > count_si)
4496 if (found_si > count_si)
4497 count_si = found_si;
4498 found_si += GET_MODE_SIZE (mode);
4500 si_limit -= GET_MODE_SIZE (mode);
4506 switch (untangle_mova (&num_mova, &mova, from))
4508 case 0: return find_barrier (0, 0, mova);
4513 = good_barrier ? good_barrier : found_barrier;
4517 if (found_si > count_si)
4518 count_si = found_si;
4520 else if (JUMP_TABLE_DATA_P (from))
4522 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4524 && (prev_nonnote_insn (from)
4525 == XEXP (MOVA_LABELREF (mova), 0))))
4527 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4529 /* We have just passed the barrier in front of the
4530 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4531 the ADDR_DIFF_VEC is accessed as data, just like our pool
4532 constants, this is a good opportunity to accommodate what
4533 we have gathered so far.
4534 If we waited any longer, we could end up at a barrier in
4535 front of code, which gives worse cache usage for separated
4536 instruction / data caches. */
4537 good_barrier = found_barrier;
4542 rtx body = PATTERN (from);
4543 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4546 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4547 else if (JUMP_P (from)
4549 && ! TARGET_SMALLCODE)
4555 if (new_align > si_align)
4557 si_limit -= (count_si - 1) & (new_align - si_align);
4558 si_align = new_align;
4560 count_si = (count_si + new_align - 1) & -new_align;
4565 if (new_align > hi_align)
4567 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4568 hi_align = new_align;
4570 count_hi = (count_hi + new_align - 1) & -new_align;
4572 from = NEXT_INSN (from);
4579 /* Try as we might, the leading mova is out of range. Change
4580 it into a load (which will become a pcload) and retry. */
4582 return find_barrier (0, 0, mova);
4586 /* Insert the constant pool table before the mova instruction,
4587 to prevent the mova label reference from going out of range. */
4589 good_barrier = found_barrier = barrier_before_mova;
4595 if (good_barrier && next_real_insn (found_barrier))
4596 found_barrier = good_barrier;
4600 /* We didn't find a barrier in time to dump our stuff,
4601 so we'll make one. */
4602 rtx label = gen_label_rtx ();
4604 /* If we exceeded the range, then we must back up over the last
4605 instruction we looked at. Otherwise, we just need to undo the
4606 NEXT_INSN at the end of the loop. */
4607 if (PREV_INSN (from) != orig
4608 && (count_hi > hi_limit || count_si > si_limit))
4609 from = PREV_INSN (PREV_INSN (from));
4611 from = PREV_INSN (from);
4613 /* Walk back to be just before any jump or label.
4614 Putting it before a label reduces the number of times the branch
4615 around the constant pool table will be hit. Putting it before
4616 a jump makes it more likely that the bra delay slot will be
4618 while (NOTE_P (from) || JUMP_P (from)
4620 from = PREV_INSN (from);
4622 from = emit_jump_insn_after (gen_jump (label), from);
4623 JUMP_LABEL (from) = label;
4624 LABEL_NUSES (label) = 1;
4625 found_barrier = emit_barrier_after (from);
4626 emit_label_after (label, found_barrier);
4629 return found_barrier;
4632 /* If the instruction INSN is implemented by a special function, and we can
4633 positively find the register that is used to call the sfunc, and this
4634 register is not used anywhere else in this instruction - except as the
4635 destination of a set, return this register; else, return 0. */
4637 sfunc_uses_reg (rtx insn)
4640 rtx pattern, part, reg_part, reg;
4642 if (!NONJUMP_INSN_P (insn))
4644 pattern = PATTERN (insn);
4645 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4648 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4650 part = XVECEXP (pattern, 0, i);
4651 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4656 reg = XEXP (reg_part, 0);
4657 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4659 part = XVECEXP (pattern, 0, i);
4660 if (part == reg_part || GET_CODE (part) == CLOBBER)
4662 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4663 && REG_P (SET_DEST (part)))
4664 ? SET_SRC (part) : part)))
4670 /* See if the only way in which INSN uses REG is by calling it, or by
4671 setting it while calling it. Set *SET to a SET rtx if the register
4675 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4681 reg2 = sfunc_uses_reg (insn);
4682 if (reg2 && REGNO (reg2) == REGNO (reg))
4684 pattern = single_set (insn);
4686 && REG_P (SET_DEST (pattern))
4687 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4693 /* We don't use rtx_equal_p because we don't care if the mode is
4695 pattern = single_set (insn);
4697 && REG_P (SET_DEST (pattern))
4698 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4704 par = PATTERN (insn);
4705 if (GET_CODE (par) == PARALLEL)
4706 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4708 part = XVECEXP (par, 0, i);
4709 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4712 return reg_mentioned_p (reg, SET_SRC (pattern));
4718 pattern = PATTERN (insn);
4720 if (GET_CODE (pattern) == PARALLEL)
4724 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4725 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4727 pattern = XVECEXP (pattern, 0, 0);
4730 if (GET_CODE (pattern) == SET)
4732 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4734 /* We don't use rtx_equal_p, because we don't care if the
4735 mode is different. */
4736 if (!REG_P (SET_DEST (pattern))
4737 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4743 pattern = SET_SRC (pattern);
4746 if (GET_CODE (pattern) != CALL
4747 || !MEM_P (XEXP (pattern, 0))
4748 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4754 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4755 general registers. Bits 0..15 mean that the respective registers
4756 are used as inputs in the instruction. Bits 16..31 mean that the
4757 registers 0..15, respectively, are used as outputs, or are clobbered.
4758 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4760 regs_used (rtx x, int is_dest)
4768 code = GET_CODE (x);
4773 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4774 << (REGNO (x) + is_dest));
4778 rtx y = SUBREG_REG (x);
4783 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4785 subreg_regno_offset (REGNO (y),
4788 GET_MODE (x)) + is_dest));
4792 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4794 /* If there was a return value, it must have been indicated with USE. */
4809 fmt = GET_RTX_FORMAT (code);
4811 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4816 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4817 used |= regs_used (XVECEXP (x, i, j), is_dest);
4819 else if (fmt[i] == 'e')
4820 used |= regs_used (XEXP (x, i), is_dest);
4825 /* Create an instruction that prevents redirection of a conditional branch
4826 to the destination of the JUMP with address ADDR.
4827 If the branch needs to be implemented as an indirect jump, try to find
4828 a scratch register for it.
4829 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4830 If any preceding insn that doesn't fit into a delay slot is good enough,
4831 pass 1. Pass 2 if a definite blocking insn is needed.
4832 -1 is used internally to avoid deep recursion.
4833 If a blocking instruction is made or recognized, return it. */
4836 gen_block_redirect (rtx jump, int addr, int need_block)
4839 rtx prev = prev_nonnote_insn (jump);
4842 /* First, check if we already have an instruction that satisfies our need. */
4843 if (prev && NONJUMP_INSN_P (prev) && ! INSN_DELETED_P (prev))
4845 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4847 if (GET_CODE (PATTERN (prev)) == USE
4848 || GET_CODE (PATTERN (prev)) == CLOBBER
4849 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4851 else if ((need_block &= ~1) < 0)
4853 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4856 if (GET_CODE (PATTERN (jump)) == RETURN)
4860 /* Reorg even does nasty things with return insns that cause branches
4861 to go out of range - see find_end_label and callers. */
4862 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4864 /* We can't use JUMP_LABEL here because it might be undefined
4865 when not optimizing. */
4866 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4867 /* If the branch is out of range, try to find a scratch register for it. */
4869 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4873 /* Don't look for the stack pointer as a scratch register,
4874 it would cause trouble if an interrupt occurred. */
4875 unsigned attempt = 0x7fff, used;
4876 int jump_left = flag_expensive_optimizations + 1;
4878 /* It is likely that the most recent eligible instruction is wanted for
4879 the delay slot. Therefore, find out which registers it uses, and
4880 try to avoid using them. */
4882 for (scan = jump; (scan = PREV_INSN (scan)); )
4886 if (INSN_DELETED_P (scan))
4888 code = GET_CODE (scan);
4889 if (code == CODE_LABEL || code == JUMP_INSN)
4892 && GET_CODE (PATTERN (scan)) != USE
4893 && GET_CODE (PATTERN (scan)) != CLOBBER
4894 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4896 attempt &= ~regs_used (PATTERN (scan), 0);
4900 for (used = dead = 0, scan = JUMP_LABEL (jump);
4901 (scan = NEXT_INSN (scan)); )
4905 if (INSN_DELETED_P (scan))
4907 code = GET_CODE (scan);
4910 used |= regs_used (PATTERN (scan), 0);
4911 if (code == CALL_INSN)
4912 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4913 dead |= (used >> 16) & ~used;
4919 if (code == JUMP_INSN)
4921 if (jump_left-- && simplejump_p (scan))
4922 scan = JUMP_LABEL (scan);
4928 /* Mask out the stack pointer again, in case it was
4929 the only 'free' register we have found. */
4932 /* If the immediate destination is still in range, check for possible
4933 threading with a jump beyond the delay slot insn.
4934 Don't check if we are called recursively; the jump has been or will be
4935 checked in a different invocation then. */
4937 else if (optimize && need_block >= 0)
4939 rtx next = next_active_insn (next_active_insn (dest));
4940 if (next && JUMP_P (next)
4941 && GET_CODE (PATTERN (next)) == SET
4942 && recog_memoized (next) == CODE_FOR_jump_compact)
4944 dest = JUMP_LABEL (next);
4946 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4948 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
4954 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
4956 /* It would be nice if we could convert the jump into an indirect
4957 jump / far branch right now, and thus exposing all constituent
4958 instructions to further optimization. However, reorg uses
4959 simplejump_p to determine if there is an unconditional jump where
4960 it should try to schedule instructions from the target of the
4961 branch; simplejump_p fails for indirect jumps even if they have
4963 rtx insn = emit_insn_before (gen_indirect_jump_scratch
4964 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
4966 /* ??? We would like this to have the scope of the jump, but that
4967 scope will change when a delay slot insn of an inner scope is added.
4968 Hence, after delay slot scheduling, we'll have to expect
4969 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
4972 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
4973 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
4976 else if (need_block)
4977 /* We can't use JUMP_LABEL here because it might be undefined
4978 when not optimizing. */
4979 return emit_insn_before (gen_block_branch_redirect
4980 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
4985 #define CONDJUMP_MIN -252
4986 #define CONDJUMP_MAX 262
4989 /* A label (to be placed) in front of the jump
4990 that jumps to our ultimate destination. */
4992 /* Where we are going to insert it if we cannot move the jump any farther,
4993 or the jump itself if we have picked up an existing jump. */
4995 /* The ultimate destination. */
4997 struct far_branch *prev;
4998 /* If the branch has already been created, its address;
4999 else the address of its first prospective user. */
5003 static void gen_far_branch (struct far_branch *);
5004 enum mdep_reorg_phase_e mdep_reorg_phase;
5006 gen_far_branch (struct far_branch *bp)
5008 rtx insn = bp->insert_place;
5010 rtx label = gen_label_rtx ();
5013 emit_label_after (label, insn);
5016 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
5017 LABEL_NUSES (bp->far_label)++;
5020 jump = emit_jump_insn_after (gen_return (), insn);
5021 /* Emit a barrier so that reorg knows that any following instructions
5022 are not reachable via a fall-through path.
5023 But don't do this when not optimizing, since we wouldn't suppress the
5024 alignment for the barrier then, and could end up with out-of-range
5025 pc-relative loads. */
5027 emit_barrier_after (jump);
5028 emit_label_after (bp->near_label, insn);
5029 JUMP_LABEL (jump) = bp->far_label;
5030 ok = invert_jump (insn, label, 1);
5033 /* If we are branching around a jump (rather than a return), prevent
5034 reorg from using an insn from the jump target as the delay slot insn -
5035 when reorg did this, it pessimized code (we rather hide the delay slot)
5036 and it could cause branches to go out of range. */
5039 (gen_stuff_delay_slot
5040 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
5041 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
5043 /* Prevent reorg from undoing our splits. */
5044 gen_block_redirect (jump, bp->address += 2, 2);
5047 /* Fix up ADDR_DIFF_VECs. */
5049 fixup_addr_diff_vecs (rtx first)
5053 for (insn = first; insn; insn = NEXT_INSN (insn))
5055 rtx vec_lab, pat, prev, prevpat, x, braf_label;
5058 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
5060 pat = PATTERN (insn);
5061 vec_lab = XEXP (XEXP (pat, 0), 0);
5063 /* Search the matching casesi_jump_2. */
5064 for (prev = vec_lab; ; prev = PREV_INSN (prev))
5068 prevpat = PATTERN (prev);
5069 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
5071 x = XVECEXP (prevpat, 0, 1);
5072 if (GET_CODE (x) != USE)
5075 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
5078 /* FIXME: This is a bug in the optimizer, but it seems harmless
5079 to just avoid panicing. */
5083 /* Emit the reference label of the braf where it belongs, right after
5084 the casesi_jump_2 (i.e. braf). */
5085 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
5086 emit_label_after (braf_label, prev);
5088 /* Fix up the ADDR_DIF_VEC to be relative
5089 to the reference address of the braf. */
5090 XEXP (XEXP (pat, 0), 0) = braf_label;
5094 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5095 a barrier. Return the base 2 logarithm of the desired alignment. */
5097 barrier_align (rtx barrier_or_label)
5099 rtx next = next_real_insn (barrier_or_label), pat, prev;
5100 int slot, credit, jump_to_next = 0;
5105 pat = PATTERN (next);
5107 if (GET_CODE (pat) == ADDR_DIFF_VEC)
5110 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
5111 /* This is a barrier in front of a constant table. */
5114 prev = prev_real_insn (barrier_or_label);
5115 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
5117 pat = PATTERN (prev);
5118 /* If this is a very small table, we want to keep the alignment after
5119 the table to the minimum for proper code alignment. */
5120 return ((TARGET_SMALLCODE
5121 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
5122 <= (unsigned) 1 << (CACHE_LOG - 2)))
5123 ? 1 << TARGET_SHMEDIA : align_jumps_log);
5126 if (TARGET_SMALLCODE)
5129 if (! TARGET_SH2 || ! optimize)
5130 return align_jumps_log;
5132 /* When fixing up pcloads, a constant table might be inserted just before
5133 the basic block that ends with the barrier. Thus, we can't trust the
5134 instruction lengths before that. */
5135 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
5137 /* Check if there is an immediately preceding branch to the insn beyond
5138 the barrier. We must weight the cost of discarding useful information
5139 from the current cache line when executing this branch and there is
5140 an alignment, against that of fetching unneeded insn in front of the
5141 branch target when there is no alignment. */
5143 /* There are two delay_slot cases to consider. One is the simple case
5144 where the preceding branch is to the insn beyond the barrier (simple
5145 delay slot filling), and the other is where the preceding branch has
5146 a delay slot that is a duplicate of the insn after the barrier
5147 (fill_eager_delay_slots) and the branch is to the insn after the insn
5148 after the barrier. */
5150 /* PREV is presumed to be the JUMP_INSN for the barrier under
5151 investigation. Skip to the insn before it. */
5152 prev = prev_real_insn (prev);
5154 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
5155 credit >= 0 && prev && NONJUMP_INSN_P (prev);
5156 prev = prev_real_insn (prev))
5159 if (GET_CODE (PATTERN (prev)) == USE
5160 || GET_CODE (PATTERN (prev)) == CLOBBER)
5162 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
5164 prev = XVECEXP (PATTERN (prev), 0, 1);
5165 if (INSN_UID (prev) == INSN_UID (next))
5167 /* Delay slot was filled with insn at jump target. */
5174 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5176 credit -= get_attr_length (prev);
5180 && JUMP_LABEL (prev))
5184 || next_real_insn (JUMP_LABEL (prev)) == next
5185 /* If relax_delay_slots() decides NEXT was redundant
5186 with some previous instruction, it will have
5187 redirected PREV's jump to the following insn. */
5188 || JUMP_LABEL (prev) == next_nonnote_insn (next)
5189 /* There is no upper bound on redundant instructions
5190 that might have been skipped, but we must not put an
5191 alignment where none had been before. */
5192 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
5194 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
5195 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
5196 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
5198 rtx pat = PATTERN (prev);
5199 if (GET_CODE (pat) == PARALLEL)
5200 pat = XVECEXP (pat, 0, 0);
5201 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
5207 return align_jumps_log;
5210 /* If we are inside a phony loop, almost any kind of label can turn up as the
5211 first one in the loop. Aligning a braf label causes incorrect switch
5212 destination addresses; we can detect braf labels because they are
5213 followed by a BARRIER.
5214 Applying loop alignment to small constant or switch tables is a waste
5215 of space, so we suppress this too. */
5217 sh_loop_align (rtx label)
5222 next = next_nonnote_insn (next);
5223 while (next && LABEL_P (next));
5227 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
5228 || recog_memoized (next) == CODE_FOR_consttable_2)
5231 return align_loops_log;
5234 /* Do a final pass over the function, just before delayed branch
5240 rtx first, insn, mova = NULL_RTX;
5242 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
5243 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
5245 first = get_insns ();
5246 max_labelno_before_reorg = max_label_num ();
5248 /* We must split call insns before introducing `mova's. If we're
5249 optimizing, they'll have already been split. Otherwise, make
5250 sure we don't split them too late. */
5252 split_all_insns_noflow ();
5257 /* If relaxing, generate pseudo-ops to associate function calls with
5258 the symbols they call. It does no harm to not generate these
5259 pseudo-ops. However, when we can generate them, it enables to
5260 linker to potentially relax the jsr to a bsr, and eliminate the
5261 register load and, possibly, the constant pool entry. */
5263 mdep_reorg_phase = SH_INSERT_USES_LABELS;
5266 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5267 own purposes. This works because none of the remaining passes
5268 need to look at them.
5270 ??? But it may break in the future. We should use a machine
5271 dependent REG_NOTE, or some other approach entirely. */
5272 for (insn = first; insn; insn = NEXT_INSN (insn))
5278 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
5280 remove_note (insn, note);
5284 for (insn = first; insn; insn = NEXT_INSN (insn))
5286 rtx pattern, reg, link, set, scan, dies, label;
5287 int rescan = 0, foundinsn = 0;
5291 pattern = PATTERN (insn);
5293 if (GET_CODE (pattern) == PARALLEL)
5294 pattern = XVECEXP (pattern, 0, 0);
5295 if (GET_CODE (pattern) == SET)
5296 pattern = SET_SRC (pattern);
5298 if (GET_CODE (pattern) != CALL
5299 || !MEM_P (XEXP (pattern, 0)))
5302 reg = XEXP (XEXP (pattern, 0), 0);
5306 reg = sfunc_uses_reg (insn);
5314 /* Try scanning backward to find where the register is set. */
5316 for (scan = PREV_INSN (insn);
5317 scan && !LABEL_P (scan);
5318 scan = PREV_INSN (scan))
5320 if (! INSN_P (scan))
5323 if (! reg_mentioned_p (reg, scan))
5326 if (noncall_uses_reg (reg, scan, &set))
5339 /* The register is set at LINK. */
5341 /* We can only optimize the function call if the register is
5342 being set to a symbol. In theory, we could sometimes
5343 optimize calls to a constant location, but the assembler
5344 and linker do not support that at present. */
5345 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5346 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5349 /* Scan forward from LINK to the place where REG dies, and
5350 make sure that the only insns which use REG are
5351 themselves function calls. */
5353 /* ??? This doesn't work for call targets that were allocated
5354 by reload, since there may not be a REG_DEAD note for the
5358 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5362 /* Don't try to trace forward past a CODE_LABEL if we haven't
5363 seen INSN yet. Ordinarily, we will only find the setting insn
5364 if it is in the same basic block. However,
5365 cross-jumping can insert code labels in between the load and
5366 the call, and can result in situations where a single call
5367 insn may have two targets depending on where we came from. */
5369 if (LABEL_P (scan) && ! foundinsn)
5372 if (! INSN_P (scan))
5375 /* Don't try to trace forward past a JUMP. To optimize
5376 safely, we would have to check that all the
5377 instructions at the jump destination did not use REG. */
5382 if (! reg_mentioned_p (reg, scan))
5385 if (noncall_uses_reg (reg, scan, &scanset))
5392 && (CALL_P (scan) || sfunc_uses_reg (scan)))
5394 /* There is a function call to this register other
5395 than the one we are checking. If we optimize
5396 this call, we need to rescan again below. */
5400 /* ??? We shouldn't have to worry about SCANSET here.
5401 We should just be able to check for a REG_DEAD note
5402 on a function call. However, the REG_DEAD notes are
5403 apparently not dependable around libcalls; c-torture
5404 execute/920501-2 is a test case. If SCANSET is set,
5405 then this insn sets the register, so it must have
5406 died earlier. Unfortunately, this will only handle
5407 the cases in which the register is, in fact, set in a
5410 /* ??? We shouldn't have to use FOUNDINSN here.
5411 This dates back to when we used LOG_LINKS to find
5412 the most recent insn which sets the register. */
5416 || find_reg_note (scan, REG_DEAD, reg)))
5425 /* Either there was a branch, or some insn used REG
5426 other than as a function call address. */
5430 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5431 on the insn which sets the register, and on each call insn
5432 which uses the register. In final_prescan_insn we look for
5433 the REG_LABEL_OPERAND notes, and output the appropriate label
5436 label = gen_label_rtx ();
5437 add_reg_note (link, REG_LABEL_OPERAND, label);
5438 add_reg_note (insn, REG_LABEL_OPERAND, label);
5446 scan = NEXT_INSN (scan);
5449 && reg_mentioned_p (reg, scan))
5450 || ((reg2 = sfunc_uses_reg (scan))
5451 && REGNO (reg2) == REGNO (reg))))
5452 add_reg_note (scan, REG_LABEL_OPERAND, label);
5454 while (scan != dies);
5460 fixup_addr_diff_vecs (first);
5464 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5465 shorten_branches (first);
5468 /* Scan the function looking for move instructions which have to be
5469 changed to pc-relative loads and insert the literal tables. */
5470 label_ref_list_pool = create_alloc_pool ("label references list",
5471 sizeof (struct label_ref_list_d),
5473 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5474 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
5478 /* ??? basic block reordering can move a switch table dispatch
5479 below the switch table. Check if that has happened.
5480 We only have the addresses available when optimizing; but then,
5481 this check shouldn't be needed when not optimizing. */
5482 if (!untangle_mova (&num_mova, &mova, insn))
5488 else if (JUMP_P (insn)
5489 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5491 /* ??? loop invariant motion can also move a mova out of a
5492 loop. Since loop does this code motion anyway, maybe we
5493 should wrap UNSPEC_MOVA into a CONST, so that reload can
5496 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5497 || (prev_nonnote_insn (insn)
5498 == XEXP (MOVA_LABELREF (mova), 0))))
5505 /* Some code might have been inserted between the mova and
5506 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5507 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5508 total += get_attr_length (scan);
5510 /* range of mova is 1020, add 4 because pc counts from address of
5511 second instruction after this one, subtract 2 in case pc is 2
5512 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5513 cancels out with alignment effects of the mova itself. */
5516 /* Change the mova into a load, and restart scanning
5517 there. broken_move will then return true for mova. */
5522 if (broken_move (insn)
5523 || (NONJUMP_INSN_P (insn)
5524 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5527 /* Scan ahead looking for a barrier to stick the constant table
5529 rtx barrier = find_barrier (num_mova, mova, insn);
5530 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5531 int need_aligned_label = 0;
5533 if (num_mova && ! mova_p (mova))
5535 /* find_barrier had to change the first mova into a
5536 pcload; thus, we have to start with this new pcload. */
5540 /* Now find all the moves between the points and modify them. */
5541 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5545 if (NONJUMP_INSN_P (scan)
5546 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5547 need_aligned_label = 1;
5548 if (broken_move (scan))
5550 rtx *patp = &PATTERN (scan), pat = *patp;
5554 enum machine_mode mode;
5556 if (GET_CODE (pat) == PARALLEL)
5557 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5558 src = SET_SRC (pat);
5559 dst = SET_DEST (pat);
5560 mode = GET_MODE (dst);
5562 if (mode == SImode && hi_const (src)
5563 && REGNO (dst) != FPUL_REG)
5568 while (GET_CODE (dst) == SUBREG)
5570 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5571 GET_MODE (SUBREG_REG (dst)),
5574 dst = SUBREG_REG (dst);
5576 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5578 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
5580 /* This must be an insn that clobbers r0. */
5581 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5582 XVECLEN (PATTERN (scan), 0)
5584 rtx clobber = *clobberp;
5586 gcc_assert (GET_CODE (clobber) == CLOBBER
5587 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5590 && reg_set_between_p (r0_rtx, last_float_move, scan))
5594 && GET_MODE_SIZE (mode) != 4
5595 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5597 lab = add_constant (src, mode, last_float);
5599 emit_insn_before (gen_mova (lab), scan);
5602 /* There will be a REG_UNUSED note for r0 on
5603 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5604 lest reorg:mark_target_live_regs will not
5605 consider r0 to be used, and we end up with delay
5606 slot insn in front of SCAN that clobbers r0. */
5608 = find_regno_note (last_float_move, REG_UNUSED, 0);
5610 /* If we are not optimizing, then there may not be
5613 PUT_REG_NOTE_KIND (note, REG_INC);
5615 *last_float_addr = r0_inc_rtx;
5617 last_float_move = scan;
5619 newsrc = gen_const_mem (mode,
5620 (((TARGET_SH4 && ! TARGET_FMOVD)
5621 || REGNO (dst) == FPUL_REG)
5624 last_float_addr = &XEXP (newsrc, 0);
5626 /* Remove the clobber of r0. */
5627 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5628 gen_rtx_SCRATCH (Pmode));
5630 /* This is a mova needing a label. Create it. */
5631 else if (GET_CODE (src) == UNSPEC
5632 && XINT (src, 1) == UNSPEC_MOVA
5633 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5635 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5636 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5637 newsrc = gen_rtx_UNSPEC (SImode,
5638 gen_rtvec (1, newsrc),
5643 lab = add_constant (src, mode, 0);
5644 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5645 newsrc = gen_const_mem (mode, newsrc);
5647 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5648 INSN_CODE (scan) = -1;
5651 dump_table (need_aligned_label ? insn : 0, barrier);
5655 free_alloc_pool (label_ref_list_pool);
5656 for (insn = first; insn; insn = NEXT_INSN (insn))
5657 PUT_MODE (insn, VOIDmode);
5659 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5660 INSN_ADDRESSES_FREE ();
5661 split_branches (first);
5663 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5664 also has an effect on the register that holds the address of the sfunc.
5665 Insert an extra dummy insn in front of each sfunc that pretends to
5666 use this register. */
5667 if (flag_delayed_branch)
5669 for (insn = first; insn; insn = NEXT_INSN (insn))
5671 rtx reg = sfunc_uses_reg (insn);
5675 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5679 /* fpscr is not actually a user variable, but we pretend it is for the
5680 sake of the previous optimization passes, since we want it handled like
5681 one. However, we don't have any debugging information for it, so turn
5682 it into a non-user variable now. */
5684 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5686 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5690 get_dest_uid (rtx label, int max_uid)
5692 rtx dest = next_real_insn (label);
5695 /* This can happen for an undefined label. */
5697 dest_uid = INSN_UID (dest);
5698 /* If this is a newly created branch redirection blocking instruction,
5699 we cannot index the branch_uid or insn_addresses arrays with its
5700 uid. But then, we won't need to, because the actual destination is
5701 the following branch. */
5702 while (dest_uid >= max_uid)
5704 dest = NEXT_INSN (dest);
5705 dest_uid = INSN_UID (dest);
5707 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
5712 /* Split condbranches that are out of range. Also add clobbers for
5713 scratch registers that are needed in far jumps.
5714 We do this before delay slot scheduling, so that it can take our
5715 newly created instructions into account. It also allows us to
5716 find branches with common targets more easily. */
5719 split_branches (rtx first)
5722 struct far_branch **uid_branch, *far_branch_list = 0;
5723 int max_uid = get_max_uid ();
5726 /* Find out which branches are out of range. */
5727 shorten_branches (first);
5729 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5730 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5732 for (insn = first; insn; insn = NEXT_INSN (insn))
5733 if (! INSN_P (insn))
5735 else if (INSN_DELETED_P (insn))
5737 /* Shorten_branches would split this instruction again,
5738 so transform it into a note. */
5739 SET_INSN_DELETED (insn);
5741 else if (JUMP_P (insn)
5742 /* Don't mess with ADDR_DIFF_VEC */
5743 && (GET_CODE (PATTERN (insn)) == SET
5744 || GET_CODE (PATTERN (insn)) == RETURN))
5746 enum attr_type type = get_attr_type (insn);
5747 if (type == TYPE_CBRANCH)
5751 if (get_attr_length (insn) > 4)
5753 rtx src = SET_SRC (PATTERN (insn));
5754 rtx olabel = XEXP (XEXP (src, 1), 0);
5755 int addr = INSN_ADDRESSES (INSN_UID (insn));
5757 int dest_uid = get_dest_uid (olabel, max_uid);
5758 struct far_branch *bp = uid_branch[dest_uid];
5760 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5761 the label if the LABEL_NUSES count drops to zero. There is
5762 always a jump_optimize pass that sets these values, but it
5763 proceeds to delete unreferenced code, and then if not
5764 optimizing, to un-delete the deleted instructions, thus
5765 leaving labels with too low uses counts. */
5768 JUMP_LABEL (insn) = olabel;
5769 LABEL_NUSES (olabel)++;
5773 bp = (struct far_branch *) alloca (sizeof *bp);
5774 uid_branch[dest_uid] = bp;
5775 bp->prev = far_branch_list;
5776 far_branch_list = bp;
5778 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5779 LABEL_NUSES (bp->far_label)++;
5783 label = bp->near_label;
5784 if (! label && bp->address - addr >= CONDJUMP_MIN)
5786 rtx block = bp->insert_place;
5788 if (GET_CODE (PATTERN (block)) == RETURN)
5789 block = PREV_INSN (block);
5791 block = gen_block_redirect (block,
5793 label = emit_label_after (gen_label_rtx (),
5795 bp->near_label = label;
5797 else if (label && ! NEXT_INSN (label))
5799 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5800 bp->insert_place = insn;
5802 gen_far_branch (bp);
5806 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5808 bp->near_label = label = gen_label_rtx ();
5809 bp->insert_place = insn;
5812 ok = redirect_jump (insn, label, 0);
5817 /* get_attr_length (insn) == 2 */
5818 /* Check if we have a pattern where reorg wants to redirect
5819 the branch to a label from an unconditional branch that
5821 /* We can't use JUMP_LABEL here because it might be undefined
5822 when not optimizing. */
5823 /* A syntax error might cause beyond to be NULL_RTX. */
5825 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5830 || ((beyond = next_active_insn (beyond))
5831 && JUMP_P (beyond)))
5832 && GET_CODE (PATTERN (beyond)) == SET
5833 && recog_memoized (beyond) == CODE_FOR_jump_compact
5835 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5836 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5838 gen_block_redirect (beyond,
5839 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5842 next = next_active_insn (insn);
5845 || ((next = next_active_insn (next))
5847 && GET_CODE (PATTERN (next)) == SET
5848 && recog_memoized (next) == CODE_FOR_jump_compact
5850 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5851 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5853 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5855 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5857 int addr = INSN_ADDRESSES (INSN_UID (insn));
5860 struct far_branch *bp;
5862 if (type == TYPE_JUMP)
5864 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5865 dest_uid = get_dest_uid (far_label, max_uid);
5868 /* Parse errors can lead to labels outside
5870 if (! NEXT_INSN (far_label))
5875 JUMP_LABEL (insn) = far_label;
5876 LABEL_NUSES (far_label)++;
5878 redirect_jump (insn, NULL_RTX, 1);
5882 bp = uid_branch[dest_uid];
5885 bp = (struct far_branch *) alloca (sizeof *bp);
5886 uid_branch[dest_uid] = bp;
5887 bp->prev = far_branch_list;
5888 far_branch_list = bp;
5890 bp->far_label = far_label;
5892 LABEL_NUSES (far_label)++;
5894 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5895 if (addr - bp->address <= CONDJUMP_MAX)
5896 emit_label_after (bp->near_label, PREV_INSN (insn));
5899 gen_far_branch (bp);
5905 bp->insert_place = insn;
5907 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5909 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5912 /* Generate all pending far branches,
5913 and free our references to the far labels. */
5914 while (far_branch_list)
5916 if (far_branch_list->near_label
5917 && ! NEXT_INSN (far_branch_list->near_label))
5918 gen_far_branch (far_branch_list);
5920 && far_branch_list->far_label
5921 && ! --LABEL_NUSES (far_branch_list->far_label))
5922 delete_insn (far_branch_list->far_label);
5923 far_branch_list = far_branch_list->prev;
5926 /* Instruction length information is no longer valid due to the new
5927 instructions that have been generated. */
5928 init_insn_lengths ();
5931 /* Dump out instruction addresses, which is useful for debugging the
5932 constant pool table stuff.
5934 If relaxing, output the label and pseudo-ops used to link together
5935 calls and the instruction which set the registers. */
5937 /* ??? The addresses printed by this routine for insns are nonsense for
5938 insns which are inside of a sequence where none of the inner insns have
5939 variable length. This is because the second pass of shorten_branches
5940 does not bother to update them. */
5943 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
5944 int noperands ATTRIBUTE_UNUSED)
5946 if (TARGET_DUMPISIZE)
5947 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
5953 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
5958 pattern = PATTERN (insn);
5959 if (GET_CODE (pattern) == PARALLEL)
5960 pattern = XVECEXP (pattern, 0, 0);
5961 switch (GET_CODE (pattern))
5964 if (GET_CODE (SET_SRC (pattern)) != CALL
5965 && get_attr_type (insn) != TYPE_SFUNC)
5967 targetm.asm_out.internal_label
5968 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
5971 /* else FALLTHROUGH */
5973 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
5974 CODE_LABEL_NUMBER (XEXP (note, 0)));
5984 /* Dump out any constants accumulated in the final pass. These will
5988 output_jump_label_table (void)
5994 fprintf (asm_out_file, "\t.align 2\n");
5995 for (i = 0; i < pool_size; i++)
5997 pool_node *p = &pool_vector[i];
5999 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6000 CODE_LABEL_NUMBER (p->label));
6001 output_asm_insn (".long %O0", &p->value);
6009 /* A full frame looks like:
6013 [ if current_function_anonymous_args
6026 local-0 <- fp points here. */
6028 /* Number of bytes pushed for anonymous args, used to pass information
6029 between expand_prologue and expand_epilogue. */
6031 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6032 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6033 for an epilogue and a negative value means that it's for a sibcall
6034 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6035 all the registers that are about to be restored, and hence dead. */
6038 output_stack_adjust (int size, rtx reg, int epilogue_p,
6039 HARD_REG_SET *live_regs_mask)
6041 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
6044 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6046 /* This test is bogus, as output_stack_adjust is used to re-align the
6049 gcc_assert (!(size % align));
6052 if (CONST_OK_FOR_ADD (size))
6053 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
6054 /* Try to do it with two partial adjustments; however, we must make
6055 sure that the stack is properly aligned at all times, in case
6056 an interrupt occurs between the two partial adjustments. */
6057 else if (CONST_OK_FOR_ADD (size / 2 & -align)
6058 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
6060 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
6061 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
6067 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
6070 /* If TEMP is invalid, we could temporarily save a general
6071 register to MACL. However, there is currently no need
6072 to handle this case, so just die when we see it. */
6074 || current_function_interrupt
6075 || ! call_really_used_regs[temp] || fixed_regs[temp])
6077 if (temp < 0 && ! current_function_interrupt
6078 && (TARGET_SHMEDIA || epilogue_p >= 0))
6081 COPY_HARD_REG_SET (temps, call_used_reg_set);
6082 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
6086 if (crtl->return_rtx)
6088 enum machine_mode mode;
6089 mode = GET_MODE (crtl->return_rtx);
6090 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
6091 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
6093 for (i = 0; i < nreg; i++)
6094 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
6095 if (crtl->calls_eh_return)
6097 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
6098 for (i = 0; i <= 3; i++)
6099 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
6102 if (TARGET_SHMEDIA && epilogue_p < 0)
6103 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
6104 CLEAR_HARD_REG_BIT (temps, i);
6105 if (epilogue_p <= 0)
6107 for (i = FIRST_PARM_REG;
6108 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
6109 CLEAR_HARD_REG_BIT (temps, i);
6110 if (cfun->static_chain_decl != NULL)
6111 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
6113 temp = scavenge_reg (&temps);
6115 if (temp < 0 && live_regs_mask)
6119 COPY_HARD_REG_SET (temps, *live_regs_mask);
6120 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
6121 temp = scavenge_reg (&temps);
6125 rtx adj_reg, tmp_reg, mem;
6127 /* If we reached here, the most likely case is the (sibcall)
6128 epilogue for non SHmedia. Put a special push/pop sequence
6129 for such case as the last resort. This looks lengthy but
6130 would not be problem because it seems to be very
6133 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
6136 /* ??? There is still the slight possibility that r4 or
6137 r5 have been reserved as fixed registers or assigned
6138 as global registers, and they change during an
6139 interrupt. There are possible ways to handle this:
6141 - If we are adjusting the frame pointer (r14), we can do
6142 with a single temp register and an ordinary push / pop
6144 - Grab any call-used or call-saved registers (i.e. not
6145 fixed or globals) for the temps we need. We might
6146 also grab r14 if we are adjusting the stack pointer.
6147 If we can't find enough available registers, issue
6148 a diagnostic and die - the user must have reserved
6149 way too many registers.
6150 But since all this is rather unlikely to happen and
6151 would require extra testing, we just die if r4 / r5
6152 are not available. */
6153 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
6154 && !global_regs[4] && !global_regs[5]);
6156 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
6157 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
6158 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
6159 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
6160 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
6161 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6162 emit_move_insn (mem, tmp_reg);
6163 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
6164 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6165 emit_move_insn (mem, tmp_reg);
6166 emit_move_insn (reg, adj_reg);
6167 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6168 emit_move_insn (adj_reg, mem);
6169 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6170 emit_move_insn (tmp_reg, mem);
6171 /* Tell flow the insns that pop r4/r5 aren't dead. */
6176 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
6178 /* If SIZE is negative, subtract the positive value.
6179 This sometimes allows a constant pool entry to be shared
6180 between prologue and epilogue code. */
6183 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
6184 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
6188 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
6189 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
6192 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
6193 gen_rtx_SET (VOIDmode, reg,
6194 gen_rtx_PLUS (SImode, reg,
6204 RTX_FRAME_RELATED_P (x) = 1;
6208 /* Output RTL to push register RN onto the stack. */
6215 x = gen_push_fpul ();
6216 else if (rn == FPSCR_REG)
6217 x = gen_push_fpscr ();
6218 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6219 && FP_OR_XD_REGISTER_P (rn))
6221 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6223 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
6225 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6226 x = gen_push_e (gen_rtx_REG (SFmode, rn));
6228 x = gen_push (gen_rtx_REG (SImode, rn));
6231 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6235 /* Output RTL to pop register RN from the stack. */
6242 x = gen_pop_fpul ();
6243 else if (rn == FPSCR_REG)
6244 x = gen_pop_fpscr ();
6245 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6246 && FP_OR_XD_REGISTER_P (rn))
6248 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6250 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
6252 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6253 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
6255 x = gen_pop (gen_rtx_REG (SImode, rn));
6258 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6261 /* Generate code to push the regs specified in the mask. */
6264 push_regs (HARD_REG_SET *mask, int interrupt_handler)
6266 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
6269 /* Push PR last; this gives better latencies after the prologue, and
6270 candidates for the return delay slot when there are no general
6271 registers pushed. */
6272 for (; i < FIRST_PSEUDO_REGISTER; i++)
6274 /* If this is an interrupt handler, and the SZ bit varies,
6275 and we have to push any floating point register, we need
6276 to switch to the correct precision first. */
6277 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
6278 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
6280 HARD_REG_SET unsaved;
6283 COMPL_HARD_REG_SET (unsaved, *mask);
6284 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
6288 && (i != FPSCR_REG || ! skip_fpscr)
6289 && TEST_HARD_REG_BIT (*mask, i))
6291 /* If the ISR has RESBANK attribute assigned, don't push any of
6292 the following registers - R0-R14, MACH, MACL and GBR. */
6293 if (! (sh_cfun_resbank_handler_p ()
6294 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
6302 /* Push banked registers last to improve delay slot opportunities. */
6303 if (interrupt_handler)
6304 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6305 if (TEST_HARD_REG_BIT (*mask, i))
6308 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6309 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
6313 /* Calculate how much extra space is needed to save all callee-saved
6315 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6318 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
6321 int stack_space = 0;
6322 int interrupt_handler = sh_cfun_interrupt_handler_p ();
6324 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6325 if ((! call_really_used_regs[reg] || interrupt_handler)
6326 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6327 /* Leave space to save this target register on the stack,
6328 in case target register allocation wants to use it. */
6329 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6333 /* Decide whether we should reserve space for callee-save target registers,
6334 in case target register allocation wants to use them. REGS_SAVED is
6335 the space, in bytes, that is already required for register saves.
6336 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6339 shmedia_reserve_space_for_target_registers_p (int regs_saved,
6340 HARD_REG_SET *live_regs_mask)
6344 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
6347 /* Decide how much space to reserve for callee-save target registers
6348 in case target register allocation wants to use them.
6349 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6352 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
6354 if (shmedia_space_reserved_for_target_registers)
6355 return shmedia_target_regs_stack_space (live_regs_mask);
6360 /* Work out the registers which need to be saved, both as a mask and a
6361 count of saved words. Return the count.
6363 If doing a pragma interrupt function, then push all regs used by the
6364 function, and if we call another function (we can tell by looking at PR),
6365 make sure that all the regs it clobbers are safe too. */
6368 calc_live_regs (HARD_REG_SET *live_regs_mask)
6373 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6374 bool nosave_low_regs;
6375 int pr_live, has_call;
6377 attrs = DECL_ATTRIBUTES (current_function_decl);
6378 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6379 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6380 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6381 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
6383 CLEAR_HARD_REG_SET (*live_regs_mask);
6384 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
6385 && df_regs_ever_live_p (FPSCR_REG))
6386 target_flags &= ~MASK_FPU_SINGLE;
6387 /* If we can save a lot of saves by switching to double mode, do that. */
6388 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
6389 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6390 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
6391 && (! call_really_used_regs[reg]
6392 || interrupt_handler)
6395 target_flags &= ~MASK_FPU_SINGLE;
6398 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6399 knows how to use it. That means the pseudo originally allocated for
6400 the initial value can become the PR_MEDIA_REG hard register, as seen for
6401 execute/20010122-1.c:test9. */
6403 /* ??? this function is called from initial_elimination_offset, hence we
6404 can't use the result of sh_media_register_for_return here. */
6405 pr_live = sh_pr_n_sets ();
6408 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
6409 pr_live = (pr_initial
6410 ? (!REG_P (pr_initial)
6411 || REGNO (pr_initial) != (PR_REG))
6412 : df_regs_ever_live_p (PR_REG));
6413 /* For Shcompact, if not optimizing, we end up with a memory reference
6414 using the return address pointer for __builtin_return_address even
6415 though there is no actual need to put the PR register on the stack. */
6416 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
6418 /* Force PR to be live if the prologue has to call the SHmedia
6419 argument decoder or register saver. */
6420 if (TARGET_SHCOMPACT
6421 && ((crtl->args.info.call_cookie
6422 & ~ CALL_COOKIE_RET_TRAMP (1))
6423 || crtl->saves_all_registers))
6425 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
6426 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
6428 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
6431 ? (/* Need to save all the regs ever live. */
6432 (df_regs_ever_live_p (reg)
6433 || (call_really_used_regs[reg]
6434 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
6435 || reg == PIC_OFFSET_TABLE_REGNUM)
6437 || (TARGET_SHMEDIA && has_call
6438 && REGISTER_NATURAL_MODE (reg) == SImode
6439 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
6440 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
6441 && reg != RETURN_ADDRESS_POINTER_REGNUM
6442 && reg != T_REG && reg != GBR_REG
6443 /* Push fpscr only on targets which have FPU */
6444 && (reg != FPSCR_REG || TARGET_FPU_ANY))
6445 : (/* Only push those regs which are used and need to be saved. */
6448 && crtl->args.info.call_cookie
6449 && reg == PIC_OFFSET_TABLE_REGNUM)
6450 || (df_regs_ever_live_p (reg)
6451 && ((!call_really_used_regs[reg]
6452 && !(reg != PIC_OFFSET_TABLE_REGNUM
6453 && fixed_regs[reg] && call_used_regs[reg]))
6454 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
6455 || (crtl->calls_eh_return
6456 && (reg == EH_RETURN_DATA_REGNO (0)
6457 || reg == EH_RETURN_DATA_REGNO (1)
6458 || reg == EH_RETURN_DATA_REGNO (2)
6459 || reg == EH_RETURN_DATA_REGNO (3)))
6460 || ((reg == MACL_REG || reg == MACH_REG)
6461 && df_regs_ever_live_p (reg)
6462 && sh_cfun_attr_renesas_p ())
6465 SET_HARD_REG_BIT (*live_regs_mask, reg);
6466 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6468 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
6469 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
6471 if (FP_REGISTER_P (reg))
6473 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
6475 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
6476 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
6479 else if (XD_REGISTER_P (reg))
6481 /* Must switch to double mode to access these registers. */
6482 target_flags &= ~MASK_FPU_SINGLE;
6486 if (nosave_low_regs && reg == R8_REG)
6489 /* If we have a target register optimization pass after prologue / epilogue
6490 threading, we need to assume all target registers will be live even if
6492 if (flag_branch_target_load_optimize2
6493 && TARGET_SAVE_ALL_TARGET_REGS
6494 && shmedia_space_reserved_for_target_registers)
6495 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6496 if ((! call_really_used_regs[reg] || interrupt_handler)
6497 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6499 SET_HARD_REG_BIT (*live_regs_mask, reg);
6500 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6502 /* If this is an interrupt handler, we don't have any call-clobbered
6503 registers we can conveniently use for target register save/restore.
6504 Make sure we save at least one general purpose register when we need
6505 to save target registers. */
6506 if (interrupt_handler
6507 && hard_reg_set_intersect_p (*live_regs_mask,
6508 reg_class_contents[TARGET_REGS])
6509 && ! hard_reg_set_intersect_p (*live_regs_mask,
6510 reg_class_contents[GENERAL_REGS]))
6512 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6513 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6519 /* Code to generate prologue and epilogue sequences */
6521 /* PUSHED is the number of bytes that are being pushed on the
6522 stack for register saves. Return the frame size, padded
6523 appropriately so that the stack stays properly aligned. */
6524 static HOST_WIDE_INT
6525 rounded_frame_size (int pushed)
6527 HOST_WIDE_INT size = get_frame_size ();
6528 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6530 return ((size + pushed + align - 1) & -align) - pushed;
6533 /* Choose a call-clobbered target-branch register that remains
6534 unchanged along the whole function. We set it up as the return
6535 value in the prologue. */
6537 sh_media_register_for_return (void)
6542 if (! current_function_is_leaf)
6544 if (lookup_attribute ("interrupt_handler",
6545 DECL_ATTRIBUTES (current_function_decl)))
6547 if (sh_cfun_interrupt_handler_p ())
6550 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6552 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6553 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6559 /* The maximum registers we need to save are:
6560 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6561 - 32 floating point registers (for each pair, we save none,
6562 one single precision value, or a double precision value).
6563 - 8 target registers
6564 - add 1 entry for a delimiter. */
6565 #define MAX_SAVED_REGS (62+32+8)
6567 typedef struct save_entry_s
6576 /* There will be a delimiter entry with VOIDmode both at the start and the
6577 end of a filled in schedule. The end delimiter has the offset of the
6578 save with the smallest (i.e. most negative) offset. */
6579 typedef struct save_schedule_s
6581 save_entry entries[MAX_SAVED_REGS + 2];
6582 int temps[MAX_TEMPS+1];
6585 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6586 use reverse order. Returns the last entry written to (not counting
6587 the delimiter). OFFSET_BASE is a number to be added to all offset
6591 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6595 save_entry *entry = schedule->entries;
6599 if (! current_function_interrupt)
6600 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6601 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6602 && ! FUNCTION_ARG_REGNO_P (i)
6603 && i != FIRST_RET_REG
6604 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6605 && ! (crtl->calls_eh_return
6606 && (i == EH_RETURN_STACKADJ_REGNO
6607 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6608 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6609 schedule->temps[tmpx++] = i;
6611 entry->mode = VOIDmode;
6612 entry->offset = offset_base;
6614 /* We loop twice: first, we save 8-byte aligned registers in the
6615 higher addresses, that are known to be aligned. Then, we
6616 proceed to saving 32-bit registers that don't need 8-byte
6618 If this is an interrupt function, all registers that need saving
6619 need to be saved in full. moreover, we need to postpone saving
6620 target registers till we have saved some general purpose registers
6621 we can then use as scratch registers. */
6622 offset = offset_base;
6623 for (align = 1; align >= 0; align--)
6625 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6626 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6628 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6631 if (current_function_interrupt)
6633 if (TARGET_REGISTER_P (i))
6635 if (GENERAL_REGISTER_P (i))
6638 if (mode == SFmode && (i % 2) == 1
6639 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6640 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6647 /* If we're doing the aligned pass and this is not aligned,
6648 or we're doing the unaligned pass and this is aligned,
6650 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6654 if (current_function_interrupt
6655 && GENERAL_REGISTER_P (i)
6656 && tmpx < MAX_TEMPS)
6657 schedule->temps[tmpx++] = i;
6659 offset -= GET_MODE_SIZE (mode);
6662 entry->offset = offset;
6665 if (align && current_function_interrupt)
6666 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6667 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6669 offset -= GET_MODE_SIZE (DImode);
6671 entry->mode = DImode;
6672 entry->offset = offset;
6677 entry->mode = VOIDmode;
6678 entry->offset = offset;
6679 schedule->temps[tmpx] = -1;
6684 sh_expand_prologue (void)
6686 HARD_REG_SET live_regs_mask;
6689 int save_flags = target_flags;
6692 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6694 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6696 /* We have pretend args if we had an object sent partially in registers
6697 and partially on the stack, e.g. a large structure. */
6698 pretend_args = crtl->args.pretend_args_size;
6699 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6700 && (NPARM_REGS(SImode)
6701 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
6703 output_stack_adjust (-pretend_args
6704 - crtl->args.info.stack_regs * 8,
6705 stack_pointer_rtx, 0, NULL);
6707 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
6708 /* We're going to use the PIC register to load the address of the
6709 incoming-argument decoder and/or of the return trampoline from
6710 the GOT, so make sure the PIC register is preserved and
6712 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6714 if (TARGET_SHCOMPACT
6715 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6719 /* First, make all registers with incoming arguments that will
6720 be pushed onto the stack live, so that register renaming
6721 doesn't overwrite them. */
6722 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6723 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
6724 >= NPARM_REGS (SImode) - reg)
6725 for (; reg < NPARM_REGS (SImode); reg++)
6726 emit_insn (gen_shcompact_preserve_incoming_args
6727 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6728 else if (CALL_COOKIE_INT_REG_GET
6729 (crtl->args.info.call_cookie, reg) == 1)
6730 emit_insn (gen_shcompact_preserve_incoming_args
6731 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6733 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6735 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6736 GEN_INT (crtl->args.info.call_cookie));
6737 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6738 gen_rtx_REG (SImode, R0_REG));
6740 else if (TARGET_SHMEDIA)
6742 int tr = sh_media_register_for_return ();
6745 emit_move_insn (gen_rtx_REG (DImode, tr),
6746 gen_rtx_REG (DImode, PR_MEDIA_REG));
6749 /* Emit the code for SETUP_VARARGS. */
6752 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6754 /* Push arg regs as if they'd been provided by caller in stack. */
6755 for (i = 0; i < NPARM_REGS(SImode); i++)
6757 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6760 if (i >= (NPARM_REGS(SImode)
6761 - crtl->args.info.arg_count[(int) SH_ARG_INT]
6769 /* If we're supposed to switch stacks at function entry, do so now. */
6773 /* The argument specifies a variable holding the address of the
6774 stack the interrupt function should switch to/from at entry/exit. */
6775 tree arg = TREE_VALUE ( TREE_VALUE (sp_switch_attr));
6777 = ggc_strdup (TREE_STRING_POINTER (arg));
6778 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6780 lab = add_constant (sp_switch, SImode, 0);
6781 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
6782 newsrc = gen_const_mem (SImode, newsrc);
6784 emit_insn (gen_sp_switch_1 (newsrc));
6787 d = calc_live_regs (&live_regs_mask);
6788 /* ??? Maybe we could save some switching if we can move a mode switch
6789 that already happens to be at the function start into the prologue. */
6790 if (target_flags != save_flags && ! current_function_interrupt)
6791 emit_insn (gen_toggle_sz ());
6795 int offset_base, offset;
6797 int offset_in_r0 = -1;
6799 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6800 int total_size, save_size;
6801 save_schedule schedule;
6805 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6806 && ! current_function_interrupt)
6807 r0 = gen_rtx_REG (Pmode, R0_REG);
6809 /* D is the actual number of bytes that we need for saving registers,
6810 however, in initial_elimination_offset we have committed to using
6811 an additional TREGS_SPACE amount of bytes - in order to keep both
6812 addresses to arguments supplied by the caller and local variables
6813 valid, we must keep this gap. Place it between the incoming
6814 arguments and the actually saved registers in a bid to optimize
6815 locality of reference. */
6816 total_size = d + tregs_space;
6817 total_size += rounded_frame_size (total_size);
6818 save_size = total_size - rounded_frame_size (d);
6819 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6820 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6821 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6823 /* If adjusting the stack in a single step costs nothing extra, do so.
6824 I.e. either if a single addi is enough, or we need a movi anyway,
6825 and we don't exceed the maximum offset range (the test for the
6826 latter is conservative for simplicity). */
6828 && (CONST_OK_FOR_I10 (-total_size)
6829 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6830 && total_size <= 2044)))
6831 d_rounding = total_size - save_size;
6833 offset_base = d + d_rounding;
6835 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
6838 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6839 tmp_pnt = schedule.temps;
6840 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6842 enum machine_mode mode = (enum machine_mode) entry->mode;
6843 unsigned int reg = entry->reg;
6844 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
6847 offset = entry->offset;
6849 reg_rtx = gen_rtx_REG (mode, reg);
6851 mem_rtx = gen_frame_mem (mode,
6852 gen_rtx_PLUS (Pmode,
6856 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
6862 if (HAVE_PRE_DECREMENT
6863 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6864 || mem_rtx == NULL_RTX
6865 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6867 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
6869 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
6874 offset += GET_MODE_SIZE (mode);
6878 if (mem_rtx != NULL_RTX)
6881 if (offset_in_r0 == -1)
6883 emit_move_insn (r0, GEN_INT (offset));
6884 offset_in_r0 = offset;
6886 else if (offset != offset_in_r0)
6891 GEN_INT (offset - offset_in_r0)));
6892 offset_in_r0 += offset - offset_in_r0;
6895 if (pre_dec != NULL_RTX)
6901 (Pmode, r0, stack_pointer_rtx));
6905 offset -= GET_MODE_SIZE (mode);
6906 offset_in_r0 -= GET_MODE_SIZE (mode);
6911 mem_rtx = gen_frame_mem (mode, r0);
6913 mem_rtx = gen_frame_mem (mode,
6914 gen_rtx_PLUS (Pmode,
6918 /* We must not use an r0-based address for target-branch
6919 registers or for special registers without pre-dec
6920 memory addresses, since we store their values in r0
6922 gcc_assert (!TARGET_REGISTER_P (reg)
6923 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6924 || mem_rtx == pre_dec));
6927 orig_reg_rtx = reg_rtx;
6928 if (TARGET_REGISTER_P (reg)
6929 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6930 && mem_rtx != pre_dec))
6932 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
6934 emit_move_insn (tmp_reg, reg_rtx);
6936 if (REGNO (tmp_reg) == R0_REG)
6940 gcc_assert (!refers_to_regno_p
6941 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
6944 if (*++tmp_pnt <= 0)
6945 tmp_pnt = schedule.temps;
6952 /* Mark as interesting for dwarf cfi generator */
6953 insn = emit_move_insn (mem_rtx, reg_rtx);
6954 RTX_FRAME_RELATED_P (insn) = 1;
6955 /* If we use an intermediate register for the save, we can't
6956 describe this exactly in cfi as a copy of the to-be-saved
6957 register into the temporary register and then the temporary
6958 register on the stack, because the temporary register can
6959 have a different natural size than the to-be-saved register.
6960 Thus, we gloss over the intermediate copy and pretend we do
6961 a direct save from the to-be-saved register. */
6962 if (REGNO (reg_rtx) != reg)
6966 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
6967 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6970 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
6972 rtx reg_rtx = gen_rtx_REG (mode, reg);
6974 rtx mem_rtx = gen_frame_mem (mode,
6975 gen_rtx_PLUS (Pmode,
6979 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
6980 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6985 gcc_assert (entry->offset == d_rounding);
6988 push_regs (&live_regs_mask, current_function_interrupt);
6990 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
6991 emit_insn (gen_GOTaddr2picreg ());
6993 if (SHMEDIA_REGS_STACK_ADJUST ())
6995 /* This must NOT go through the PLT, otherwise mach and macl
6996 may be clobbered. */
6997 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6999 ? "__GCC_push_shmedia_regs"
7000 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
7001 emit_insn (gen_shmedia_save_restore_regs_compact
7002 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
7005 if (target_flags != save_flags && ! current_function_interrupt)
7006 emit_insn (gen_toggle_sz ());
7008 target_flags = save_flags;
7010 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
7011 stack_pointer_rtx, 0, NULL);
7013 if (frame_pointer_needed)
7014 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
7016 if (TARGET_SHCOMPACT
7017 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
7019 /* This must NOT go through the PLT, otherwise mach and macl
7020 may be clobbered. */
7021 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7022 "__GCC_shcompact_incoming_args", SFUNC_GOT);
7023 emit_insn (gen_shcompact_incoming_args ());
7028 sh_expand_epilogue (bool sibcall_p)
7030 HARD_REG_SET live_regs_mask;
7034 int save_flags = target_flags;
7035 int frame_size, save_size;
7036 int fpscr_deferred = 0;
7037 int e = sibcall_p ? -1 : 1;
7039 d = calc_live_regs (&live_regs_mask);
7042 frame_size = rounded_frame_size (d);
7046 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
7048 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
7049 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7050 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
7052 total_size = d + tregs_space;
7053 total_size += rounded_frame_size (total_size);
7054 save_size = total_size - frame_size;
7056 /* If adjusting the stack in a single step costs nothing extra, do so.
7057 I.e. either if a single addi is enough, or we need a movi anyway,
7058 and we don't exceed the maximum offset range (the test for the
7059 latter is conservative for simplicity). */
7061 && ! frame_pointer_needed
7062 && (CONST_OK_FOR_I10 (total_size)
7063 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
7064 && total_size <= 2044)))
7065 d_rounding = frame_size;
7067 frame_size -= d_rounding;
7070 if (frame_pointer_needed)
7072 /* We must avoid scheduling the epilogue with previous basic blocks.
7073 See PR/18032 and PR/40313. */
7074 emit_insn (gen_blockage ());
7075 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
7078 /* We must avoid moving the stack pointer adjustment past code
7079 which reads from the local frame, else an interrupt could
7080 occur after the SP adjustment and clobber data in the local
7082 emit_insn (gen_blockage ());
7083 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
7085 else if (frame_size)
7087 /* We must avoid moving the stack pointer adjustment past code
7088 which reads from the local frame, else an interrupt could
7089 occur after the SP adjustment and clobber data in the local
7091 emit_insn (gen_blockage ());
7092 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
7095 if (SHMEDIA_REGS_STACK_ADJUST ())
7097 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7099 ? "__GCC_pop_shmedia_regs"
7100 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
7101 /* This must NOT go through the PLT, otherwise mach and macl
7102 may be clobbered. */
7103 emit_insn (gen_shmedia_save_restore_regs_compact
7104 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
7107 /* Pop all the registers. */
7109 if (target_flags != save_flags && ! current_function_interrupt)
7110 emit_insn (gen_toggle_sz ());
7113 int offset_base, offset;
7114 int offset_in_r0 = -1;
7116 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
7117 save_schedule schedule;
7121 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
7122 offset_base = -entry[1].offset + d_rounding;
7123 tmp_pnt = schedule.temps;
7124 for (; entry->mode != VOIDmode; entry--)
7126 enum machine_mode mode = (enum machine_mode) entry->mode;
7127 int reg = entry->reg;
7128 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
7130 offset = offset_base + entry->offset;
7131 reg_rtx = gen_rtx_REG (mode, reg);
7133 mem_rtx = gen_frame_mem (mode,
7134 gen_rtx_PLUS (Pmode,
7138 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7141 if (HAVE_POST_INCREMENT
7142 && (offset == offset_in_r0
7143 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
7144 && mem_rtx == NULL_RTX)
7145 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7147 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
7149 if (!memory_address_p (mode, XEXP (post_inc, 0)))
7150 post_inc = NULL_RTX;
7155 if (mem_rtx != NULL_RTX)
7158 if (offset_in_r0 == -1)
7160 emit_move_insn (r0, GEN_INT (offset));
7161 offset_in_r0 = offset;
7163 else if (offset != offset_in_r0)
7168 GEN_INT (offset - offset_in_r0)));
7169 offset_in_r0 += offset - offset_in_r0;
7172 if (post_inc != NULL_RTX)
7178 (Pmode, r0, stack_pointer_rtx));
7184 offset_in_r0 += GET_MODE_SIZE (mode);
7187 mem_rtx = gen_frame_mem (mode, r0);
7189 mem_rtx = gen_frame_mem (mode,
7190 gen_rtx_PLUS (Pmode,
7194 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7195 || mem_rtx == post_inc);
7198 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7199 && mem_rtx != post_inc)
7201 insn = emit_move_insn (r0, mem_rtx);
7204 else if (TARGET_REGISTER_P (reg))
7206 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
7208 /* Give the scheduler a bit of freedom by using up to
7209 MAX_TEMPS registers in a round-robin fashion. */
7210 insn = emit_move_insn (tmp_reg, mem_rtx);
7213 tmp_pnt = schedule.temps;
7216 insn = emit_move_insn (reg_rtx, mem_rtx);
7219 gcc_assert (entry->offset + offset_base == d + d_rounding);
7221 else /* ! TARGET_SH5 */
7226 /* For an ISR with RESBANK attribute assigned, don't pop PR
7228 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
7229 && !sh_cfun_resbank_handler_p ())
7231 if (!frame_pointer_needed)
7232 emit_insn (gen_blockage ());
7236 /* Banked registers are poped first to avoid being scheduled in the
7237 delay slot. RTE switches banks before the ds instruction. */
7238 if (current_function_interrupt)
7240 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
7241 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7242 pop (LAST_BANKED_REG - i);
7244 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
7247 last_reg = FIRST_PSEUDO_REGISTER;
7249 for (i = 0; i < last_reg; i++)
7251 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
7253 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
7254 && hard_reg_set_intersect_p (live_regs_mask,
7255 reg_class_contents[DF_REGS]))
7257 /* For an ISR with RESBANK attribute assigned, don't pop
7258 following registers, R0-R14, MACH, MACL and GBR. */
7259 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
7260 && ! (sh_cfun_resbank_handler_p ()
7261 && ((j >= FIRST_GENERAL_REG
7262 && j < LAST_GENERAL_REG)
7268 if (j == FIRST_FP_REG && fpscr_deferred)
7272 if (target_flags != save_flags && ! current_function_interrupt)
7273 emit_insn (gen_toggle_sz ());
7274 target_flags = save_flags;
7276 output_stack_adjust (crtl->args.pretend_args_size
7277 + save_size + d_rounding
7278 + crtl->args.info.stack_regs * 8,
7279 stack_pointer_rtx, e, NULL);
7281 if (crtl->calls_eh_return)
7282 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
7283 EH_RETURN_STACKADJ_RTX));
7285 /* Switch back to the normal stack if necessary. */
7286 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
7287 emit_insn (gen_sp_switch_2 ());
7289 /* Tell flow the insn that pops PR isn't dead. */
7290 /* PR_REG will never be live in SHmedia mode, and we don't need to
7291 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
7292 by the return pattern. */
7293 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
7294 emit_use (gen_rtx_REG (SImode, PR_REG));
7297 static int sh_need_epilogue_known = 0;
7300 sh_need_epilogue (void)
7302 if (! sh_need_epilogue_known)
7307 sh_expand_epilogue (0);
7308 epilogue = get_insns ();
7310 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
7312 return sh_need_epilogue_known > 0;
7315 /* Emit code to change the current function's return address to RA.
7316 TEMP is available as a scratch register, if needed. */
7319 sh_set_return_address (rtx ra, rtx tmp)
7321 HARD_REG_SET live_regs_mask;
7323 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7326 d = calc_live_regs (&live_regs_mask);
7328 /* If pr_reg isn't life, we can set it (or the register given in
7329 sh_media_register_for_return) directly. */
7330 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7336 int rr_regno = sh_media_register_for_return ();
7341 rr = gen_rtx_REG (DImode, rr_regno);
7344 rr = gen_rtx_REG (SImode, pr_reg);
7346 emit_insn (GEN_MOV (rr, ra));
7347 /* Tell flow the register for return isn't dead. */
7355 save_schedule schedule;
7358 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
7359 offset = entry[1].offset;
7360 for (; entry->mode != VOIDmode; entry--)
7361 if (entry->reg == pr_reg)
7364 /* We can't find pr register. */
7368 offset = entry->offset - offset;
7369 pr_offset = (rounded_frame_size (d) + offset
7370 + SHMEDIA_REGS_STACK_ADJUST ());
7373 pr_offset = rounded_frame_size (d);
7375 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7376 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7378 tmp = gen_frame_mem (Pmode, tmp);
7379 emit_insn (GEN_MOV (tmp, ra));
7380 /* Tell this store isn't dead. */
7384 /* Clear variables at function end. */
7387 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7388 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7390 sh_need_epilogue_known = 0;
7394 sh_builtin_saveregs (void)
7396 /* First unnamed integer register. */
7397 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
7398 /* Number of integer registers we need to save. */
7399 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7400 /* First unnamed SFmode float reg */
7401 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
7402 /* Number of SFmode float regs to save. */
7403 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
7406 alias_set_type alias_set;
7412 int pushregs = n_intregs;
7414 while (pushregs < NPARM_REGS (SImode) - 1
7415 && (CALL_COOKIE_INT_REG_GET
7416 (crtl->args.info.call_cookie,
7417 NPARM_REGS (SImode) - pushregs)
7420 crtl->args.info.call_cookie
7421 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7426 if (pushregs == NPARM_REGS (SImode))
7427 crtl->args.info.call_cookie
7428 |= (CALL_COOKIE_INT_REG (0, 1)
7429 | CALL_COOKIE_STACKSEQ (pushregs - 1));
7431 crtl->args.info.call_cookie
7432 |= CALL_COOKIE_STACKSEQ (pushregs);
7434 crtl->args.pretend_args_size += 8 * n_intregs;
7436 if (TARGET_SHCOMPACT)
7440 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
7442 error ("__builtin_saveregs not supported by this subtarget");
7449 /* Allocate block of memory for the regs. */
7450 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7451 Or can assign_stack_local accept a 0 SIZE argument? */
7452 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7455 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
7456 else if (n_floatregs & 1)
7460 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7461 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7462 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7463 regbuf = change_address (regbuf, BLKmode, addr);
7465 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7469 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7470 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7471 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7472 emit_insn (gen_andsi3 (addr, addr, mask));
7473 regbuf = change_address (regbuf, BLKmode, addr);
7476 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7477 alias_set = get_varargs_alias_set ();
7478 set_mem_alias_set (regbuf, alias_set);
7481 This is optimized to only save the regs that are necessary. Explicitly
7482 named args need not be saved. */
7484 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7485 adjust_address (regbuf, BLKmode,
7486 n_floatregs * UNITS_PER_WORD),
7490 /* Return the address of the regbuf. */
7491 return XEXP (regbuf, 0);
7494 This is optimized to only save the regs that are necessary. Explicitly
7495 named args need not be saved.
7496 We explicitly build a pointer to the buffer because it halves the insn
7497 count when not optimizing (otherwise the pointer is built for each reg
7499 We emit the moves in reverse order so that we can use predecrement. */
7501 fpregs = copy_to_mode_reg (Pmode,
7502 plus_constant (XEXP (regbuf, 0),
7503 n_floatregs * UNITS_PER_WORD));
7504 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7507 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7509 emit_insn (gen_addsi3 (fpregs, fpregs,
7510 GEN_INT (-2 * UNITS_PER_WORD)));
7511 mem = change_address (regbuf, DFmode, fpregs);
7512 emit_move_insn (mem,
7513 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7515 regno = first_floatreg;
7518 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7519 mem = change_address (regbuf, SFmode, fpregs);
7520 emit_move_insn (mem,
7521 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7522 - (TARGET_LITTLE_ENDIAN != 0)));
7526 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7530 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7531 mem = change_address (regbuf, SFmode, fpregs);
7532 emit_move_insn (mem,
7533 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7536 /* Return the address of the regbuf. */
7537 return XEXP (regbuf, 0);
7540 /* Define the `__builtin_va_list' type for the ABI. */
7543 sh_build_builtin_va_list (void)
7545 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7548 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7549 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7550 return ptr_type_node;
7552 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7554 f_next_o = build_decl (BUILTINS_LOCATION,
7555 FIELD_DECL, get_identifier ("__va_next_o"),
7557 f_next_o_limit = build_decl (BUILTINS_LOCATION,
7559 get_identifier ("__va_next_o_limit"),
7561 f_next_fp = build_decl (BUILTINS_LOCATION,
7562 FIELD_DECL, get_identifier ("__va_next_fp"),
7564 f_next_fp_limit = build_decl (BUILTINS_LOCATION,
7566 get_identifier ("__va_next_fp_limit"),
7568 f_next_stack = build_decl (BUILTINS_LOCATION,
7569 FIELD_DECL, get_identifier ("__va_next_stack"),
7572 DECL_FIELD_CONTEXT (f_next_o) = record;
7573 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7574 DECL_FIELD_CONTEXT (f_next_fp) = record;
7575 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7576 DECL_FIELD_CONTEXT (f_next_stack) = record;
7578 TYPE_FIELDS (record) = f_next_o;
7579 TREE_CHAIN (f_next_o) = f_next_o_limit;
7580 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7581 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7582 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7584 layout_type (record);
7589 /* Implement `va_start' for varargs and stdarg. */
7592 sh_va_start (tree valist, rtx nextarg)
7594 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7595 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7601 expand_builtin_saveregs ();
7602 std_expand_builtin_va_start (valist, nextarg);
7606 if ((! TARGET_SH2E && ! TARGET_SH4)
7607 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7609 std_expand_builtin_va_start (valist, nextarg);
7613 f_next_o = TYPE_FIELDS (va_list_type_node);
7614 f_next_o_limit = TREE_CHAIN (f_next_o);
7615 f_next_fp = TREE_CHAIN (f_next_o_limit);
7616 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7617 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7619 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7621 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7622 valist, f_next_o_limit, NULL_TREE);
7623 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7625 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7626 valist, f_next_fp_limit, NULL_TREE);
7627 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7628 valist, f_next_stack, NULL_TREE);
7630 /* Call __builtin_saveregs. */
7631 u = make_tree (sizetype, expand_builtin_saveregs ());
7632 u = fold_convert (ptr_type_node, u);
7633 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7634 TREE_SIDE_EFFECTS (t) = 1;
7635 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7637 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7642 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7643 size_int (UNITS_PER_WORD * nfp));
7644 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7645 TREE_SIDE_EFFECTS (t) = 1;
7646 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7648 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7649 TREE_SIDE_EFFECTS (t) = 1;
7650 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7652 nint = crtl->args.info.arg_count[SH_ARG_INT];
7657 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7658 size_int (UNITS_PER_WORD * nint));
7659 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7660 TREE_SIDE_EFFECTS (t) = 1;
7661 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7663 u = make_tree (ptr_type_node, nextarg);
7664 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7665 TREE_SIDE_EFFECTS (t) = 1;
7666 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7669 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7670 member, return it. */
7672 find_sole_member (tree type)
7674 tree field, member = NULL_TREE;
7676 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7678 if (TREE_CODE (field) != FIELD_DECL)
7680 if (!DECL_SIZE (field))
7682 if (integer_zerop (DECL_SIZE (field)))
7690 /* Implement `va_arg'. */
7693 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7694 gimple_seq *post_p ATTRIBUTE_UNUSED)
7696 HOST_WIDE_INT size, rsize;
7697 tree tmp, pptr_type_node;
7698 tree addr, lab_over = NULL, result = NULL;
7699 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7703 type = build_pointer_type (type);
7705 size = int_size_in_bytes (type);
7706 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7707 pptr_type_node = build_pointer_type (ptr_type_node);
7709 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7710 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7712 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7713 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7718 f_next_o = TYPE_FIELDS (va_list_type_node);
7719 f_next_o_limit = TREE_CHAIN (f_next_o);
7720 f_next_fp = TREE_CHAIN (f_next_o_limit);
7721 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7722 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7724 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7726 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7727 valist, f_next_o_limit, NULL_TREE);
7728 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7729 valist, f_next_fp, NULL_TREE);
7730 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7731 valist, f_next_fp_limit, NULL_TREE);
7732 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7733 valist, f_next_stack, NULL_TREE);
7735 /* Structures with a single member with a distinct mode are passed
7736 like their member. This is relevant if the latter has a REAL_TYPE
7737 or COMPLEX_TYPE type. */
7739 while (TREE_CODE (eff_type) == RECORD_TYPE
7740 && (member = find_sole_member (eff_type))
7741 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7742 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7743 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7745 tree field_type = TREE_TYPE (member);
7747 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7748 eff_type = field_type;
7751 gcc_assert ((TYPE_ALIGN (eff_type)
7752 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7753 || (TYPE_ALIGN (eff_type)
7754 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7759 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7761 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7762 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7763 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7768 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7771 addr = create_tmp_var (pptr_type_node, NULL);
7772 lab_false = create_artificial_label (UNKNOWN_LOCATION);
7773 lab_over = create_artificial_label (UNKNOWN_LOCATION);
7775 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
7779 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7781 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7783 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
7784 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7786 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
7787 tmp = next_fp_limit;
7788 if (size > 4 && !is_double)
7789 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp),
7790 unshare_expr (tmp), size_int (4 - size));
7791 tmp = build2 (GE_EXPR, boolean_type_node,
7792 unshare_expr (next_fp_tmp), unshare_expr (tmp));
7793 cmp = build3 (COND_EXPR, void_type_node, tmp,
7794 build1 (GOTO_EXPR, void_type_node,
7795 unshare_expr (lab_false)), NULL_TREE);
7797 gimplify_and_add (cmp, pre_p);
7799 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7800 || (is_double || size == 16))
7802 tmp = fold_convert (sizetype, next_fp_tmp);
7803 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7804 size_int (UNITS_PER_WORD));
7805 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7806 unshare_expr (next_fp_tmp), tmp);
7807 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
7810 gimplify_and_add (cmp, pre_p);
7812 #ifdef FUNCTION_ARG_SCmode_WART
7813 if (TYPE_MODE (eff_type) == SCmode
7814 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7816 tree subtype = TREE_TYPE (eff_type);
7820 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7821 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7824 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7825 real = get_initialized_tmp_var (real, pre_p, NULL);
7827 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
7828 if (type != eff_type)
7829 result = build1 (VIEW_CONVERT_EXPR, type, result);
7830 result = get_initialized_tmp_var (result, pre_p, NULL);
7832 #endif /* FUNCTION_ARG_SCmode_WART */
7834 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7835 gimplify_and_add (tmp, pre_p);
7837 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7838 gimplify_and_add (tmp, pre_p);
7840 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7841 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7842 gimplify_assign (unshare_expr (next_fp_tmp),
7843 unshare_expr (valist), pre_p);
7845 gimplify_assign (unshare_expr (valist),
7846 unshare_expr (next_fp_tmp), post_p);
7847 valist = next_fp_tmp;
7851 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7852 unshare_expr (next_o), size_int (rsize));
7853 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
7854 unshare_expr (next_o_limit));
7855 tmp = build3 (COND_EXPR, void_type_node, tmp,
7856 build1 (GOTO_EXPR, void_type_node,
7857 unshare_expr (lab_false)),
7859 gimplify_and_add (tmp, pre_p);
7861 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
7862 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7864 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7865 gimplify_and_add (tmp, pre_p);
7867 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7868 gimplify_and_add (tmp, pre_p);
7870 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7871 gimplify_assign (unshare_expr (next_o),
7872 unshare_expr (next_o_limit), pre_p);
7874 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7875 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7880 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7881 gimplify_and_add (tmp, pre_p);
7885 /* ??? In va-sh.h, there had been code to make values larger than
7886 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7888 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7891 gimplify_assign (result, tmp, pre_p);
7892 result = build1 (NOP_EXPR, TREE_TYPE (result), result);
7893 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7894 gimplify_and_add (tmp, pre_p);
7900 result = build_va_arg_indirect_ref (result);
7905 /* 64 bit floating points memory transfers are paired single precision loads
7906 or store. So DWARF information needs fixing in little endian (unless
7907 PR=SZ=1 in FPSCR). */
7909 sh_dwarf_register_span (rtx reg)
7911 unsigned regno = REGNO (reg);
7913 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
7917 gen_rtx_PARALLEL (VOIDmode,
7919 gen_rtx_REG (SFmode,
7920 DBX_REGISTER_NUMBER (regno+1)),
7921 gen_rtx_REG (SFmode,
7922 DBX_REGISTER_NUMBER (regno))));
7925 static enum machine_mode
7926 sh_promote_function_mode (const_tree type, enum machine_mode mode,
7927 int *punsignedp, const_tree funtype,
7928 int for_return ATTRIBUTE_UNUSED)
7930 if (sh_promote_prototypes (funtype))
7931 return promote_mode (type, mode, punsignedp);
7937 sh_promote_prototypes (const_tree type)
7943 return ! sh_attr_renesas_p (type);
7946 /* Whether an argument must be passed by reference. On SHcompact, we
7947 pretend arguments wider than 32-bits that would have been passed in
7948 registers are passed by reference, so that an SHmedia trampoline
7949 loads them into the full 64-bits registers. */
7952 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
7953 const_tree type, bool named)
7955 unsigned HOST_WIDE_INT size;
7958 size = int_size_in_bytes (type);
7960 size = GET_MODE_SIZE (mode);
7962 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
7964 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
7965 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
7966 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
7968 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
7969 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7976 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7977 const_tree type, bool named)
7979 if (targetm.calls.must_pass_in_stack (mode, type))
7982 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7983 wants to know about pass-by-reference semantics for incoming
7988 if (TARGET_SHCOMPACT)
7990 cum->byref = shcompact_byref (cum, mode, type, named);
7991 return cum->byref != 0;
7998 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7999 const_tree type, bool named ATTRIBUTE_UNUSED)
8001 /* ??? How can it possibly be correct to return true only on the
8002 caller side of the equation? Is there someplace else in the
8003 sh backend that's magically producing the copies? */
8004 return (cum->outgoing
8005 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
8006 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
8010 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8011 tree type, bool named ATTRIBUTE_UNUSED)
8016 && PASS_IN_REG_P (*cum, mode, type)
8017 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
8018 && (ROUND_REG (*cum, mode)
8020 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
8021 : ROUND_ADVANCE (int_size_in_bytes (type)))
8022 > NPARM_REGS (mode)))
8023 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
8025 else if (!TARGET_SHCOMPACT
8026 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
8027 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
8029 return words * UNITS_PER_WORD;
8033 /* Define where to put the arguments to a function.
8034 Value is zero to push the argument on the stack,
8035 or a hard register in which to store the argument.
8037 MODE is the argument's machine mode.
8038 TYPE is the data type of the argument (as a tree).
8039 This is null for libcalls where that information may
8041 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8042 the preceding args and about the function being called.
8043 NAMED is nonzero if this argument is a named parameter
8044 (otherwise it is an extra parameter matching an ellipsis).
8046 On SH the first args are normally in registers
8047 and the rest are pushed. Any arg that starts within the first
8048 NPARM_REGS words is at least partially passed in a register unless
8049 its data type forbids. */
8053 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8054 tree type, int named)
8056 if (! TARGET_SH5 && mode == VOIDmode)
8057 return GEN_INT (ca->renesas_abi ? 1 : 0);
8060 && PASS_IN_REG_P (*ca, mode, type)
8061 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
8065 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
8066 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
8068 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
8069 gen_rtx_REG (SFmode,
8071 + (ROUND_REG (*ca, mode) ^ 1)),
8073 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
8074 gen_rtx_REG (SFmode,
8076 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
8078 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
8081 /* If the alignment of a DF value causes an SF register to be
8082 skipped, we will use that skipped register for the next SF
8084 if ((TARGET_HITACHI || ca->renesas_abi)
8085 && ca->free_single_fp_reg
8087 return gen_rtx_REG (mode, ca->free_single_fp_reg);
8089 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
8090 ^ (mode == SFmode && TARGET_SH4
8091 && TARGET_LITTLE_ENDIAN != 0
8092 && ! TARGET_HITACHI && ! ca->renesas_abi);
8093 return gen_rtx_REG (mode, regno);
8099 if (mode == VOIDmode && TARGET_SHCOMPACT)
8100 return GEN_INT (ca->call_cookie);
8102 /* The following test assumes unnamed arguments are promoted to
8104 if (mode == SFmode && ca->free_single_fp_reg)
8105 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
8107 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
8108 && (named || ! ca->prototype_p)
8109 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
8111 if (! ca->prototype_p && TARGET_SHMEDIA)
8112 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
8114 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
8116 + ca->arg_count[(int) SH_ARG_FLOAT]);
8119 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
8120 && (! TARGET_SHCOMPACT
8121 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
8122 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
8125 return gen_rtx_REG (mode, (FIRST_PARM_REG
8126 + ca->arg_count[(int) SH_ARG_INT]));
8135 /* Update the data in CUM to advance over an argument
8136 of mode MODE and data type TYPE.
8137 (TYPE is null for libcalls where that information may not be
8141 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8142 tree type, int named)
8146 else if (TARGET_SH5)
8148 tree type2 = (ca->byref && type
8151 enum machine_mode mode2 = (ca->byref && type
8154 int dwords = ((ca->byref
8157 ? int_size_in_bytes (type2)
8158 : GET_MODE_SIZE (mode2)) + 7) / 8;
8159 int numregs = MIN (dwords, NPARM_REGS (SImode)
8160 - ca->arg_count[(int) SH_ARG_INT]);
8164 ca->arg_count[(int) SH_ARG_INT] += numregs;
8165 if (TARGET_SHCOMPACT
8166 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
8169 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8171 /* N.B. We want this also for outgoing. */
8172 ca->stack_regs += numregs;
8177 ca->stack_regs += numregs;
8178 ca->byref_regs += numregs;
8182 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8186 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8189 else if (dwords > numregs)
8191 int pushregs = numregs;
8193 if (TARGET_SHCOMPACT)
8194 ca->stack_regs += numregs;
8195 while (pushregs < NPARM_REGS (SImode) - 1
8196 && (CALL_COOKIE_INT_REG_GET
8198 NPARM_REGS (SImode) - pushregs)
8202 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
8206 if (numregs == NPARM_REGS (SImode))
8208 |= CALL_COOKIE_INT_REG (0, 1)
8209 | CALL_COOKIE_STACKSEQ (numregs - 1);
8212 |= CALL_COOKIE_STACKSEQ (numregs);
8215 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
8216 && (named || ! ca->prototype_p))
8218 if (mode2 == SFmode && ca->free_single_fp_reg)
8219 ca->free_single_fp_reg = 0;
8220 else if (ca->arg_count[(int) SH_ARG_FLOAT]
8221 < NPARM_REGS (SFmode))
8224 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
8226 - ca->arg_count[(int) SH_ARG_FLOAT]);
8228 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
8230 if (TARGET_SHCOMPACT && ! ca->prototype_p)
8232 if (ca->outgoing && numregs > 0)
8236 |= (CALL_COOKIE_INT_REG
8237 (ca->arg_count[(int) SH_ARG_INT]
8238 - numregs + ((numfpregs - 2) / 2),
8239 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
8242 while (numfpregs -= 2);
8244 else if (mode2 == SFmode && (named)
8245 && (ca->arg_count[(int) SH_ARG_FLOAT]
8246 < NPARM_REGS (SFmode)))
8247 ca->free_single_fp_reg
8248 = FIRST_FP_PARM_REG - numfpregs
8249 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
8255 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
8257 /* Note that we've used the skipped register. */
8258 if (mode == SFmode && ca->free_single_fp_reg)
8260 ca->free_single_fp_reg = 0;
8263 /* When we have a DF after an SF, there's an SF register that get
8264 skipped in order to align the DF value. We note this skipped
8265 register, because the next SF value will use it, and not the
8266 SF that follows the DF. */
8268 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
8270 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
8271 + BASE_ARG_REG (mode));
8275 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
8276 || PASS_IN_REG_P (*ca, mode, type))
8277 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
8278 = (ROUND_REG (*ca, mode)
8280 ? ROUND_ADVANCE (int_size_in_bytes (type))
8281 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
8284 /* The Renesas calling convention doesn't quite fit into this scheme since
8285 the address is passed like an invisible argument, but one that is always
8286 passed in memory. */
8288 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
8290 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8292 return gen_rtx_REG (Pmode, 2);
8295 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8298 sh_return_in_memory (const_tree type, const_tree fndecl)
8302 if (TYPE_MODE (type) == BLKmode)
8303 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
8305 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
8309 return (TYPE_MODE (type) == BLKmode
8310 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8311 && TREE_CODE (type) == RECORD_TYPE));
8315 /* We actually emit the code in sh_expand_prologue. We used to use
8316 a static variable to flag that we need to emit this code, but that
8317 doesn't when inlining, when functions are deferred and then emitted
8318 later. Fortunately, we already have two flags that are part of struct
8319 function that tell if a function uses varargs or stdarg. */
8321 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
8322 enum machine_mode mode,
8324 int *pretend_arg_size,
8325 int second_time ATTRIBUTE_UNUSED)
8327 gcc_assert (cfun->stdarg);
8328 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8330 int named_parm_regs, anon_parm_regs;
8332 named_parm_regs = (ROUND_REG (*ca, mode)
8334 ? ROUND_ADVANCE (int_size_in_bytes (type))
8335 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
8336 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
8337 if (anon_parm_regs > 0)
8338 *pretend_arg_size = anon_parm_regs * 4;
8343 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
8349 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
8351 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
8355 /* Define the offset between two registers, one to be eliminated, and
8356 the other its replacement, at the start of a routine. */
8359 initial_elimination_offset (int from, int to)
8362 int regs_saved_rounding = 0;
8363 int total_saved_regs_space;
8364 int total_auto_space;
8365 int save_flags = target_flags;
8367 HARD_REG_SET live_regs_mask;
8369 shmedia_space_reserved_for_target_registers = false;
8370 regs_saved = calc_live_regs (&live_regs_mask);
8371 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
8373 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
8375 shmedia_space_reserved_for_target_registers = true;
8376 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
8379 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
8380 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8381 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
8383 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8384 copy_flags = target_flags;
8385 target_flags = save_flags;
8387 total_saved_regs_space = regs_saved + regs_saved_rounding;
8389 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8390 return total_saved_regs_space + total_auto_space
8391 + crtl->args.info.byref_regs * 8;
8393 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8394 return total_saved_regs_space + total_auto_space
8395 + crtl->args.info.byref_regs * 8;
8397 /* Initial gap between fp and sp is 0. */
8398 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8401 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8402 return rounded_frame_size (0);
8404 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8405 return rounded_frame_size (0);
8407 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
8408 && (to == HARD_FRAME_POINTER_REGNUM
8409 || to == STACK_POINTER_REGNUM));
8412 int n = total_saved_regs_space;
8413 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
8414 save_schedule schedule;
8417 n += total_auto_space;
8419 /* If it wasn't saved, there's not much we can do. */
8420 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
8423 target_flags = copy_flags;
8425 sh5_schedule_saves (&live_regs_mask, &schedule, n);
8426 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
8427 if (entry->reg == pr_reg)
8429 target_flags = save_flags;
8430 return entry->offset;
8435 return total_auto_space;
8438 /* Parse the -mfixed-range= option string. */
8440 sh_fix_range (const char *const_str)
8443 char *str, *dash, *comma;
8445 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8446 REG2 are either register names or register numbers. The effect
8447 of this option is to mark the registers in the range from REG1 to
8448 REG2 as ``fixed'' so they won't be used by the compiler. */
8450 i = strlen (const_str);
8451 str = (char *) alloca (i + 1);
8452 memcpy (str, const_str, i + 1);
8456 dash = strchr (str, '-');
8459 warning (0, "value of -mfixed-range must have form REG1-REG2");
8463 comma = strchr (dash + 1, ',');
8467 first = decode_reg_name (str);
8470 warning (0, "unknown register name: %s", str);
8474 last = decode_reg_name (dash + 1);
8477 warning (0, "unknown register name: %s", dash + 1);
8485 warning (0, "%s-%s is an empty range", str, dash + 1);
8489 for (i = first; i <= last; ++i)
8490 fixed_regs[i] = call_used_regs[i] = 1;
8500 /* Insert any deferred function attributes from earlier pragmas. */
8502 sh_insert_attributes (tree node, tree *attributes)
8506 if (TREE_CODE (node) != FUNCTION_DECL)
8509 /* We are only interested in fields. */
8513 /* Append the attributes to the deferred attributes. */
8514 *sh_deferred_function_attributes_tail = *attributes;
8515 attrs = sh_deferred_function_attributes;
8519 /* Some attributes imply or require the interrupt attribute. */
8520 if (!lookup_attribute ("interrupt_handler", attrs)
8521 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8523 /* If we have a trapa_handler, but no interrupt_handler attribute,
8524 insert an interrupt_handler attribute. */
8525 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8526 /* We can't use sh_pr_interrupt here because that's not in the
8529 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8530 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8531 if the interrupt attribute is missing, we ignore the attribute
8533 else if (lookup_attribute ("sp_switch", attrs)
8534 || lookup_attribute ("trap_exit", attrs)
8535 || lookup_attribute ("nosave_low_regs", attrs)
8536 || lookup_attribute ("resbank", attrs))
8540 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8542 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8543 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8544 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8545 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8546 warning (OPT_Wattributes,
8547 "%qE attribute only applies to interrupt functions",
8548 TREE_PURPOSE (attrs));
8551 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8553 tail = &TREE_CHAIN (*tail);
8556 attrs = *attributes;
8560 /* Install the processed list. */
8561 *attributes = attrs;
8563 /* Clear deferred attributes. */
8564 sh_deferred_function_attributes = NULL_TREE;
8565 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8570 /* Supported attributes:
8572 interrupt_handler -- specifies this function is an interrupt handler.
8574 trapa_handler - like above, but don't save all registers.
8576 sp_switch -- specifies an alternate stack for an interrupt handler
8579 trap_exit -- use a trapa to exit an interrupt function instead of
8582 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8583 This is useful on the SH3 and upwards,
8584 which has a separate set of low regs for User and Supervisor modes.
8585 This should only be used for the lowest level of interrupts. Higher levels
8586 of interrupts must save the registers in case they themselves are
8589 renesas -- use Renesas calling/layout conventions (functions and
8592 resbank -- In case of an ISR, use a register bank to save registers
8593 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8596 /* Handle a 'resbank' attribute. */
8598 sh_handle_resbank_handler_attribute (tree * node, tree name,
8599 tree args ATTRIBUTE_UNUSED,
8600 int flags ATTRIBUTE_UNUSED,
8601 bool * no_add_attrs)
8605 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8607 *no_add_attrs = true;
8609 if (TREE_CODE (*node) != FUNCTION_DECL)
8611 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8613 *no_add_attrs = true;
8619 /* Handle an "interrupt_handler" attribute; arguments as in
8620 struct attribute_spec.handler. */
8622 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8623 tree args ATTRIBUTE_UNUSED,
8624 int flags ATTRIBUTE_UNUSED,
8627 if (TREE_CODE (*node) != FUNCTION_DECL)
8629 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8631 *no_add_attrs = true;
8633 else if (TARGET_SHCOMPACT)
8635 error ("attribute interrupt_handler is not compatible with -m5-compact");
8636 *no_add_attrs = true;
8642 /* Handle an 'function_vector' attribute; arguments as in
8643 struct attribute_spec.handler. */
8645 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8646 tree args ATTRIBUTE_UNUSED,
8647 int flags ATTRIBUTE_UNUSED,
8648 bool * no_add_attrs)
8652 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8654 *no_add_attrs = true;
8656 else if (TREE_CODE (*node) != FUNCTION_DECL)
8658 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8660 *no_add_attrs = true;
8662 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8664 /* The argument must be a constant integer. */
8665 warning (OPT_Wattributes,
8666 "%qE attribute argument not an integer constant",
8668 *no_add_attrs = true;
8670 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8672 /* The argument value must be between 0 to 255. */
8673 warning (OPT_Wattributes,
8674 "%qE attribute argument should be between 0 to 255",
8676 *no_add_attrs = true;
8681 /* Returns 1 if current function has been assigned the attribute
8682 'function_vector'. */
8684 sh2a_is_function_vector_call (rtx x)
8686 if (GET_CODE (x) == SYMBOL_REF
8687 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8689 tree tr = SYMBOL_REF_DECL (x);
8691 if (sh2a_function_vector_p (tr))
8698 /* Returns the function vector number, if the the attribute
8699 'function_vector' is assigned, otherwise returns zero. */
8701 sh2a_get_function_vector_number (rtx x)
8706 if ((GET_CODE (x) == SYMBOL_REF)
8707 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8709 t = SYMBOL_REF_DECL (x);
8711 if (TREE_CODE (t) != FUNCTION_DECL)
8714 list = SH_ATTRIBUTES (t);
8717 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8719 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8723 list = TREE_CHAIN (list);
8732 /* Handle an "sp_switch" attribute; arguments as in
8733 struct attribute_spec.handler. */
8735 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8736 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8738 if (TREE_CODE (*node) != FUNCTION_DECL)
8740 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8742 *no_add_attrs = true;
8744 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8746 /* The argument must be a constant string. */
8747 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
8749 *no_add_attrs = true;
8755 /* Handle an "trap_exit" attribute; arguments as in
8756 struct attribute_spec.handler. */
8758 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8759 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8761 if (TREE_CODE (*node) != FUNCTION_DECL)
8763 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8765 *no_add_attrs = true;
8767 /* The argument specifies a trap number to be used in a trapa instruction
8768 at function exit (instead of an rte instruction). */
8769 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8771 /* The argument must be a constant integer. */
8772 warning (OPT_Wattributes, "%qE attribute argument not an "
8773 "integer constant", name);
8774 *no_add_attrs = true;
8781 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8782 tree name ATTRIBUTE_UNUSED,
8783 tree args ATTRIBUTE_UNUSED,
8784 int flags ATTRIBUTE_UNUSED,
8785 bool *no_add_attrs ATTRIBUTE_UNUSED)
8790 /* True if __attribute__((renesas)) or -mrenesas. */
8792 sh_attr_renesas_p (const_tree td)
8799 td = TREE_TYPE (td);
8800 if (td == error_mark_node)
8802 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8806 /* True if __attribute__((renesas)) or -mrenesas, for the current
8809 sh_cfun_attr_renesas_p (void)
8811 return sh_attr_renesas_p (current_function_decl);
8815 sh_cfun_interrupt_handler_p (void)
8817 return (lookup_attribute ("interrupt_handler",
8818 DECL_ATTRIBUTES (current_function_decl))
8822 /* Returns 1 if FUNC has been assigned the attribute
8823 "function_vector". */
8825 sh2a_function_vector_p (tree func)
8828 if (TREE_CODE (func) != FUNCTION_DECL)
8831 list = SH_ATTRIBUTES (func);
8834 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8837 list = TREE_CHAIN (list);
8842 /* Returns TRUE if given tree has the "resbank" attribute. */
8845 sh_cfun_resbank_handler_p (void)
8847 return ((lookup_attribute ("resbank",
8848 DECL_ATTRIBUTES (current_function_decl))
8850 && (lookup_attribute ("interrupt_handler",
8851 DECL_ATTRIBUTES (current_function_decl))
8852 != NULL_TREE) && TARGET_SH2A);
8855 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8858 sh_check_pch_target_flags (int old_flags)
8860 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8861 | MASK_SH_E | MASK_HARD_SH4
8862 | MASK_FPU_SINGLE | MASK_SH4))
8863 return _("created and used with different architectures / ABIs");
8864 if ((old_flags ^ target_flags) & MASK_HITACHI)
8865 return _("created and used with different ABIs");
8866 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8867 return _("created and used with different endianness");
8871 /* Predicates used by the templates. */
8873 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
8874 Used only in general_movsrc_operand. */
8877 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8889 /* Nonzero if OP is a floating point value with value 0.0. */
8892 fp_zero_operand (rtx op)
8896 if (GET_MODE (op) != SFmode)
8899 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8900 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
8903 /* Nonzero if OP is a floating point value with value 1.0. */
8906 fp_one_operand (rtx op)
8910 if (GET_MODE (op) != SFmode)
8913 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8914 return REAL_VALUES_EQUAL (r, dconst1);
8917 /* In general mode switching is used. If we are
8918 compiling without -mfmovd, movsf_ie isn't taken into account for
8919 mode switching. We could check in machine_dependent_reorg for
8920 cases where we know we are in single precision mode, but there is
8921 interface to find that out during reload, so we must avoid
8922 choosing an fldi alternative during reload and thus failing to
8923 allocate a scratch register for the constant loading. */
8931 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8933 enum rtx_code code = GET_CODE (op);
8934 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
8937 /* Return the TLS type for TLS symbols, 0 for otherwise. */
8939 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8941 if (GET_CODE (op) != SYMBOL_REF)
8942 return TLS_MODEL_NONE;
8943 return SYMBOL_REF_TLS_MODEL (op);
8946 /* Return the destination address of a branch. */
8949 branch_dest (rtx branch)
8951 rtx dest = SET_SRC (PATTERN (branch));
8954 if (GET_CODE (dest) == IF_THEN_ELSE)
8955 dest = XEXP (dest, 1);
8956 dest = XEXP (dest, 0);
8957 dest_uid = INSN_UID (dest);
8958 return INSN_ADDRESSES (dest_uid);
8961 /* Return nonzero if REG is not used after INSN.
8962 We assume REG is a reload reg, and therefore does
8963 not live past labels. It may live past calls or jumps though. */
8965 reg_unused_after (rtx reg, rtx insn)
8970 /* If the reg is set by this instruction, then it is safe for our
8971 case. Disregard the case where this is a store to memory, since
8972 we are checking a register used in the store address. */
8973 set = single_set (insn);
8974 if (set && !MEM_P (SET_DEST (set))
8975 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8978 while ((insn = NEXT_INSN (insn)))
8984 code = GET_CODE (insn);
8987 /* If this is a label that existed before reload, then the register
8988 if dead here. However, if this is a label added by reorg, then
8989 the register may still be live here. We can't tell the difference,
8990 so we just ignore labels completely. */
8991 if (code == CODE_LABEL)
8996 if (code == JUMP_INSN)
8999 /* If this is a sequence, we must handle them all at once.
9000 We could have for instance a call that sets the target register,
9001 and an insn in a delay slot that uses the register. In this case,
9002 we must return 0. */
9003 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
9008 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9010 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
9011 rtx set = single_set (this_insn);
9013 if (CALL_P (this_insn))
9015 else if (JUMP_P (this_insn))
9017 if (INSN_ANNULLED_BRANCH_P (this_insn))
9022 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9024 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9026 if (!MEM_P (SET_DEST (set)))
9032 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
9037 else if (code == JUMP_INSN)
9041 set = single_set (insn);
9042 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9044 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9045 return !MEM_P (SET_DEST (set));
9046 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9049 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
9057 static GTY(()) rtx fpscr_rtx;
9059 get_fpscr_rtx (void)
9063 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
9064 REG_USERVAR_P (fpscr_rtx) = 1;
9065 mark_user_reg (fpscr_rtx);
9067 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
9068 mark_user_reg (fpscr_rtx);
9072 static GTY(()) tree fpscr_values;
9075 emit_fpu_switch (rtx scratch, int index)
9079 if (fpscr_values == NULL)
9083 t = build_index_type (integer_one_node);
9084 t = build_array_type (integer_type_node, t);
9085 t = build_decl (BUILTINS_LOCATION,
9086 VAR_DECL, get_identifier ("__fpscr_values"), t);
9087 DECL_ARTIFICIAL (t) = 1;
9088 DECL_IGNORED_P (t) = 1;
9089 DECL_EXTERNAL (t) = 1;
9090 TREE_STATIC (t) = 1;
9091 TREE_PUBLIC (t) = 1;
9097 src = DECL_RTL (fpscr_values);
9098 if (!can_create_pseudo_p ())
9100 emit_move_insn (scratch, XEXP (src, 0));
9102 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
9103 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
9106 src = adjust_address (src, PSImode, index * 4);
9108 dst = get_fpscr_rtx ();
9109 emit_move_insn (dst, src);
9113 emit_sf_insn (rtx pat)
9119 emit_df_insn (rtx pat)
9125 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9127 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9131 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9133 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
9138 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9140 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9144 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9146 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
9150 static rtx get_free_reg (HARD_REG_SET);
9152 /* This function returns a register to use to load the address to load
9153 the fpscr from. Currently it always returns r1 or r7, but when we are
9154 able to use pseudo registers after combine, or have a better mechanism
9155 for choosing a register, it should be done here. */
9156 /* REGS_LIVE is the liveness information for the point for which we
9157 need this allocation. In some bare-bones exit blocks, r1 is live at the
9158 start. We can even have all of r0..r3 being live:
9159 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
9160 INSN before which new insns are placed with will clobber the register
9161 we return. If a basic block consists only of setting the return value
9162 register to a pseudo and using that register, the return value is not
9163 live before or after this block, yet we we'll insert our insns right in
9167 get_free_reg (HARD_REG_SET regs_live)
9169 if (! TEST_HARD_REG_BIT (regs_live, 1))
9170 return gen_rtx_REG (Pmode, 1);
9172 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
9173 there shouldn't be anything but a jump before the function end. */
9174 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
9175 return gen_rtx_REG (Pmode, 7);
9178 /* This function will set the fpscr from memory.
9179 MODE is the mode we are setting it to. */
9181 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
9183 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
9184 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
9187 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
9188 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
9191 /* Is the given character a logical line separator for the assembler? */
9192 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
9193 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
9197 sh_insn_length_adjustment (rtx insn)
9199 /* Instructions with unfilled delay slots take up an extra two bytes for
9200 the nop in the delay slot. */
9201 if (((NONJUMP_INSN_P (insn)
9202 && GET_CODE (PATTERN (insn)) != USE
9203 && GET_CODE (PATTERN (insn)) != CLOBBER)
9206 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9207 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
9208 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
9209 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
9212 /* SH2e has a bug that prevents the use of annulled branches, so if
9213 the delay slot is not filled, we'll have to put a NOP in it. */
9214 if (sh_cpu_attr == CPU_SH2E
9216 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9217 && GET_CODE (PATTERN (insn)) != ADDR_VEC
9218 && get_attr_type (insn) == TYPE_CBRANCH
9219 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
9222 /* sh-dsp parallel processing insn take four bytes instead of two. */
9224 if (NONJUMP_INSN_P (insn))
9227 rtx body = PATTERN (insn);
9230 int maybe_label = 1;
9232 if (GET_CODE (body) == ASM_INPUT)
9233 templ = XSTR (body, 0);
9234 else if (asm_noperands (body) >= 0)
9236 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
9245 while (c == ' ' || c == '\t');
9246 /* all sh-dsp parallel-processing insns start with p.
9247 The only non-ppi sh insn starting with p is pref.
9248 The only ppi starting with pr is prnd. */
9249 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
9251 /* The repeat pseudo-insn expands two three insns, a total of
9252 six bytes in size. */
9253 else if ((c == 'r' || c == 'R')
9254 && ! strncasecmp ("epeat", templ, 5))
9256 while (c && c != '\n'
9257 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
9259 /* If this is a label, it is obviously not a ppi insn. */
9260 if (c == ':' && maybe_label)
9265 else if (c == '\'' || c == '"')
9270 maybe_label = c != ':';
9278 /* Return TRUE for a valid displacement for the REG+disp addressing
9281 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
9282 into the FRx registers. We implement this by setting the maximum offset
9283 to zero when the value is SFmode. This also restricts loading of SFmode
9284 values into the integer registers, but that can't be helped. */
9286 /* The SH allows a displacement in a QI or HI amode, but only when the
9287 other operand is R0. GCC doesn't handle this very well, so we forgot
9290 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
9291 DI can be any number 0..60. */
9294 sh_legitimate_index_p (enum machine_mode mode, rtx op)
9296 if (CONST_INT_P (op))
9302 /* Check if this the address of an unaligned load / store. */
9303 if (mode == VOIDmode)
9304 return CONST_OK_FOR_I06 (INTVAL (op));
9306 size = GET_MODE_SIZE (mode);
9307 return (!(INTVAL (op) & (size - 1))
9308 && INTVAL (op) >= -512 * size
9309 && INTVAL (op) < 512 * size);
9314 if (GET_MODE_SIZE (mode) == 1
9315 && (unsigned) INTVAL (op) < 4096)
9319 if ((GET_MODE_SIZE (mode) == 4
9320 && (unsigned) INTVAL (op) < 64
9321 && !(INTVAL (op) & 3)
9322 && !(TARGET_SH2E && mode == SFmode))
9323 || (GET_MODE_SIZE (mode) == 4
9324 && (unsigned) INTVAL (op) < 16383
9325 && !(INTVAL (op) & 3) && TARGET_SH2A))
9328 if ((GET_MODE_SIZE (mode) == 8
9329 && (unsigned) INTVAL (op) < 60
9330 && !(INTVAL (op) & 3)
9331 && !((TARGET_SH4 || TARGET_SH2A) && mode == DFmode))
9332 || ((GET_MODE_SIZE (mode)==8)
9333 && (unsigned) INTVAL (op) < 8192
9334 && !(INTVAL (op) & (TARGET_SH2A_DOUBLE ? 7 : 3))
9335 && (TARGET_SH2A && mode == DFmode)))
9342 /* Recognize an RTL expression that is a valid memory address for
9344 The MODE argument is the machine mode for the MEM expression
9345 that wants to use this address.
9353 sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9355 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9357 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9359 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9361 else if (GET_CODE (x) == PLUS
9362 && (mode != PSImode || reload_completed))
9364 rtx xop0 = XEXP (x, 0);
9365 rtx xop1 = XEXP (x, 1);
9367 if (GET_MODE_SIZE (mode) <= 8
9368 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9369 && sh_legitimate_index_p (mode, xop1))
9372 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode
9373 || ((xop0 == stack_pointer_rtx
9374 || xop0 == hard_frame_pointer_rtx)
9375 && REG_P (xop1) && REGNO (xop1) == R0_REG)
9376 || ((xop1 == stack_pointer_rtx
9377 || xop1 == hard_frame_pointer_rtx)
9378 && REG_P (xop0) && REGNO (xop0) == R0_REG))
9379 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4)
9380 || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8)
9381 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
9382 && TARGET_FMOVD && mode == DFmode)))
9384 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9385 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9387 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9388 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9396 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9397 isn't protected by a PIC unspec. */
9399 nonpic_symbol_mentioned_p (rtx x)
9401 register const char *fmt;
9404 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9405 || GET_CODE (x) == PC)
9408 /* We don't want to look into the possible MEM location of a
9409 CONST_DOUBLE, since we're not going to use it, in general. */
9410 if (GET_CODE (x) == CONST_DOUBLE)
9413 if (GET_CODE (x) == UNSPEC
9414 && (XINT (x, 1) == UNSPEC_PIC
9415 || XINT (x, 1) == UNSPEC_GOT
9416 || XINT (x, 1) == UNSPEC_GOTOFF
9417 || XINT (x, 1) == UNSPEC_GOTPLT
9418 || XINT (x, 1) == UNSPEC_GOTTPOFF
9419 || XINT (x, 1) == UNSPEC_DTPOFF
9420 || XINT (x, 1) == UNSPEC_PLT
9421 || XINT (x, 1) == UNSPEC_SYMOFF
9422 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
9425 fmt = GET_RTX_FORMAT (GET_CODE (x));
9426 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9432 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9433 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9436 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9443 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9444 @GOTOFF in `reg'. */
9446 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
9449 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
9452 if (GET_CODE (orig) == LABEL_REF
9453 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
9456 reg = gen_reg_rtx (Pmode);
9458 emit_insn (gen_symGOTOFF2reg (reg, orig));
9461 else if (GET_CODE (orig) == SYMBOL_REF)
9464 reg = gen_reg_rtx (Pmode);
9466 emit_insn (gen_symGOT2reg (reg, orig));
9472 /* Try machine-dependent ways of modifying an illegitimate address
9473 to be legitimate. If we find one, return the new, valid address.
9474 Otherwise, return X.
9476 For the SH, if X is almost suitable for indexing, but the offset is
9477 out of range, convert it into a normal form so that CSE has a chance
9478 of reducing the number of address registers used. */
9481 sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
9484 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9486 if (GET_CODE (x) == PLUS
9487 && (GET_MODE_SIZE (mode) == 4
9488 || GET_MODE_SIZE (mode) == 8)
9489 && CONST_INT_P (XEXP (x, 1))
9490 && BASE_REGISTER_RTX_P (XEXP (x, 0))
9492 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
9493 && ! (TARGET_SH2E && mode == SFmode))
9495 rtx index_rtx = XEXP (x, 1);
9496 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9499 /* On rare occasions, we might get an unaligned pointer
9500 that is indexed in a way to give an aligned address.
9501 Therefore, keep the lower two bits in offset_base. */
9502 /* Instead of offset_base 128..131 use 124..127, so that
9503 simple add suffices. */
9505 offset_base = ((offset + 4) & ~60) - 4;
9507 offset_base = offset & ~60;
9509 /* Sometimes the normal form does not suit DImode. We
9510 could avoid that by using smaller ranges, but that
9511 would give less optimized code when SImode is
9513 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9515 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9516 GEN_INT (offset_base), NULL_RTX, 0,
9519 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9526 /* Mark the use of a constant in the literal table. If the constant
9527 has multiple labels, make it unique. */
9529 mark_constant_pool_use (rtx x)
9531 rtx insn, lab, pattern;
9536 switch (GET_CODE (x))
9546 /* Get the first label in the list of labels for the same constant
9547 and delete another labels in the list. */
9549 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
9552 || LABEL_REFS (insn) != NEXT_INSN (insn))
9557 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
9558 INSN_DELETED_P (insn) = 1;
9560 /* Mark constants in a window. */
9561 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
9563 if (!NONJUMP_INSN_P (insn))
9566 pattern = PATTERN (insn);
9567 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
9570 switch (XINT (pattern, 1))
9572 case UNSPECV_CONST2:
9573 case UNSPECV_CONST4:
9574 case UNSPECV_CONST8:
9575 XVECEXP (pattern, 0, 1) = const1_rtx;
9577 case UNSPECV_WINDOW_END:
9578 if (XVECEXP (pattern, 0, 0) == x)
9581 case UNSPECV_CONST_END:
9591 /* Return true if it's possible to redirect BRANCH1 to the destination
9592 of an unconditional jump BRANCH2. We only want to do this if the
9593 resulting branch will have a short displacement. */
9595 sh_can_redirect_branch (rtx branch1, rtx branch2)
9597 if (flag_expensive_optimizations && simplejump_p (branch2))
9599 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
9603 for (distance = 0, insn = NEXT_INSN (branch1);
9604 insn && distance < 256;
9605 insn = PREV_INSN (insn))
9610 distance += get_attr_length (insn);
9612 for (distance = 0, insn = NEXT_INSN (branch1);
9613 insn && distance < 256;
9614 insn = NEXT_INSN (insn))
9619 distance += get_attr_length (insn);
9625 /* Return nonzero if register old_reg can be renamed to register new_reg. */
9627 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
9628 unsigned int new_reg)
9630 /* Interrupt functions can only use registers that have already been
9631 saved by the prologue, even if they would normally be
9634 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
9640 /* Function to update the integer COST
9641 based on the relationship between INSN that is dependent on
9642 DEP_INSN through the dependence LINK. The default is to make no
9643 adjustment to COST. This can be used for example to specify to
9644 the scheduler that an output- or anti-dependence does not incur
9645 the same cost as a data-dependence. The return value should be
9646 the new value for COST. */
9648 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
9654 /* On SHmedia, if the dependence is an anti-dependence or
9655 output-dependence, there is no cost. */
9656 if (REG_NOTE_KIND (link) != 0)
9658 /* However, dependencies between target register loads and
9659 uses of the register in a subsequent block that are separated
9660 by a conditional branch are not modelled - we have to do with
9661 the anti-dependency between the target register load and the
9662 conditional branch that ends the current block. */
9663 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
9664 && GET_CODE (PATTERN (dep_insn)) == SET
9665 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
9666 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
9667 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
9669 int orig_cost = cost;
9670 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
9671 rtx target = ((! note
9672 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
9673 ? insn : JUMP_LABEL (insn));
9674 /* On the likely path, the branch costs 1, on the unlikely path,
9678 target = next_active_insn (target);
9679 while (target && ! flow_dependent_p (target, dep_insn)
9681 /* If two branches are executed in immediate succession, with the
9682 first branch properly predicted, this causes a stall at the
9683 second branch, hence we won't need the target for the
9684 second branch for two cycles after the launch of the first
9686 if (cost > orig_cost - 2)
9687 cost = orig_cost - 2;
9693 else if (get_attr_is_mac_media (insn)
9694 && get_attr_is_mac_media (dep_insn))
9697 else if (! reload_completed
9698 && GET_CODE (PATTERN (insn)) == SET
9699 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
9700 && GET_CODE (PATTERN (dep_insn)) == SET
9701 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
9704 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
9705 that is needed at the target. */
9706 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
9707 && ! flow_dependent_p (insn, dep_insn))
9710 else if (REG_NOTE_KIND (link) == 0)
9712 enum attr_type type;
9715 if (recog_memoized (insn) < 0
9716 || recog_memoized (dep_insn) < 0)
9719 dep_set = single_set (dep_insn);
9721 /* The latency that we specify in the scheduling description refers
9722 to the actual output, not to an auto-increment register; for that,
9723 the latency is one. */
9724 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9726 rtx set = single_set (insn);
9729 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9730 && (!MEM_P (SET_DEST (set))
9731 || !reg_mentioned_p (SET_DEST (dep_set),
9732 XEXP (SET_DEST (set), 0))))
9735 /* The only input for a call that is timing-critical is the
9736 function's address. */
9739 rtx call = PATTERN (insn);
9741 if (GET_CODE (call) == PARALLEL)
9742 call = XVECEXP (call, 0 ,0);
9743 if (GET_CODE (call) == SET)
9744 call = SET_SRC (call);
9745 if (GET_CODE (call) == CALL && MEM_P (XEXP (call, 0))
9746 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9747 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9748 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9749 cost -= TARGET_SH4_300 ? 3 : 6;
9751 /* Likewise, the most timing critical input for an sfuncs call
9752 is the function address. However, sfuncs typically start
9753 using their arguments pretty quickly.
9754 Assume a four cycle delay for SH4 before they are needed.
9755 Cached ST40-300 calls are quicker, so assume only a one
9757 ??? Maybe we should encode the delays till input registers
9758 are needed by sfuncs into the sfunc call insn. */
9759 /* All sfunc calls are parallels with at least four components.
9760 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9761 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9762 && XVECLEN (PATTERN (insn), 0) >= 4
9763 && (reg = sfunc_uses_reg (insn)))
9765 if (! reg_set_p (reg, dep_insn))
9766 cost -= TARGET_SH4_300 ? 1 : 4;
9768 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9770 enum attr_type dep_type = get_attr_type (dep_insn);
9772 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9774 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9775 && (type = get_attr_type (insn)) != TYPE_CALL
9776 && type != TYPE_SFUNC)
9778 /* When the preceding instruction loads the shift amount of
9779 the following SHAD/SHLD, the latency of the load is increased
9781 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9782 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
9783 && reg_overlap_mentioned_p (SET_DEST (dep_set),
9784 XEXP (SET_SRC (single_set (insn)),
9787 /* When an LS group instruction with a latency of less than
9788 3 cycles is followed by a double-precision floating-point
9789 instruction, FIPR, or FTRV, the latency of the first
9790 instruction is increased to 3 cycles. */
9792 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9793 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9795 /* The lsw register of a double-precision computation is ready one
9797 else if (reload_completed
9798 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9799 && (use_pat = single_set (insn))
9800 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9804 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9805 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9808 else if (TARGET_SH4_300)
9810 /* Stores need their input register two cycles later. */
9811 if (dep_set && cost >= 1
9812 && ((type = get_attr_type (insn)) == TYPE_STORE
9813 || type == TYPE_PSTORE
9814 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9816 rtx set = single_set (insn);
9818 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9819 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9822 /* But don't reduce the cost below 1 if the address depends
9823 on a side effect of dep_insn. */
9825 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9831 /* An anti-dependence penalty of two applies if the first insn is a double
9832 precision fadd / fsub / fmul. */
9833 else if (!TARGET_SH4_300
9834 && REG_NOTE_KIND (link) == REG_DEP_ANTI
9835 && recog_memoized (dep_insn) >= 0
9836 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9837 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9838 /* A lot of alleged anti-flow dependences are fake,
9839 so check this one is real. */
9840 && flow_dependent_p (dep_insn, insn))
9846 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9847 if DEP_INSN is anti-flow dependent on INSN. */
9849 flow_dependent_p (rtx insn, rtx dep_insn)
9851 rtx tmp = PATTERN (insn);
9853 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9854 return tmp == NULL_RTX;
9857 /* A helper function for flow_dependent_p called through note_stores. */
9859 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9861 rtx * pinsn = (rtx *) data;
9863 if (*pinsn && reg_referenced_p (x, *pinsn))
9867 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9868 'special function' patterns (type sfunc) that clobber pr, but that
9869 do not look like function calls to leaf_function_p. Hence we must
9870 do this extra check. */
9874 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9877 /* Return where to allocate pseudo for a given hard register initial
9880 sh_allocate_initial_value (rtx hard_reg)
9884 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
9886 if (current_function_is_leaf
9887 && ! sh_pr_n_sets ()
9888 && ! (TARGET_SHCOMPACT
9889 && ((crtl->args.info.call_cookie
9890 & ~ CALL_COOKIE_RET_TRAMP (1))
9891 || crtl->saves_all_registers)))
9894 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
9902 /* This function returns "2" to indicate dual issue for the SH4
9903 processor. To be used by the DFA pipeline description. */
9905 sh_issue_rate (void)
9907 if (TARGET_SUPERSCALAR)
9913 /* Functions for ready queue reordering for sched1. */
9915 /* Get weight for mode for a set x. */
9917 find_set_regmode_weight (rtx x, enum machine_mode mode)
9919 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9921 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9923 if (REG_P (SET_DEST (x)))
9925 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9935 /* Get regmode weight for insn. */
9937 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
9939 short reg_weight = 0;
9942 /* Increment weight for each register born here. */
9944 reg_weight += find_set_regmode_weight (x, mode);
9945 if (GET_CODE (x) == PARALLEL)
9948 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9950 x = XVECEXP (PATTERN (insn), 0, j);
9951 reg_weight += find_set_regmode_weight (x, mode);
9954 /* Decrement weight for each register that dies here. */
9955 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9957 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9959 rtx note = XEXP (x, 0);
9960 if (REG_P (note) && GET_MODE (note) == mode)
9967 /* Calculate regmode weights for all insns of a basic block. */
9969 find_regmode_weight (basic_block b, enum machine_mode mode)
9971 rtx insn, next_tail, head, tail;
9973 get_ebb_head_tail (b, b, &head, &tail);
9974 next_tail = NEXT_INSN (tail);
9976 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9978 /* Handle register life information. */
9983 INSN_REGMODE_WEIGHT (insn, mode) =
9984 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
9985 else if (mode == SImode)
9986 INSN_REGMODE_WEIGHT (insn, mode) =
9987 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
9991 /* Comparison function for ready queue sorting. */
9993 rank_for_reorder (const void *x, const void *y)
9995 rtx tmp = *(const rtx *) y;
9996 rtx tmp2 = *(const rtx *) x;
9998 /* The insn in a schedule group should be issued the first. */
9999 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
10000 return SCHED_GROUP_P (tmp2) ? 1 : -1;
10002 /* If insns are equally good, sort by INSN_LUID (original insn order), This
10003 minimizes instruction movement, thus minimizing sched's effect on
10004 register pressure. */
10005 return INSN_LUID (tmp) - INSN_LUID (tmp2);
10008 /* Resort the array A in which only element at index N may be out of order. */
10010 swap_reorder (rtx *a, int n)
10012 rtx insn = a[n - 1];
10015 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
10023 #define SCHED_REORDER(READY, N_READY) \
10026 if ((N_READY) == 2) \
10027 swap_reorder (READY, N_READY); \
10028 else if ((N_READY) > 2) \
10029 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
10033 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
10036 ready_reorder (rtx *ready, int nready)
10038 SCHED_REORDER (ready, nready);
10041 /* Count life regions of r0 for a block. */
10043 find_r0_life_regions (basic_block b)
10052 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
10063 insn = BB_HEAD (b);
10065 r0_reg = gen_rtx_REG (SImode, R0_REG);
10070 if (find_regno_note (insn, REG_DEAD, R0_REG))
10076 && (pset = single_set (insn))
10077 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
10078 && !find_regno_note (insn, REG_UNUSED, R0_REG))
10086 insn = NEXT_INSN (insn);
10088 return set - death;
10091 /* Calculate regmode weights for all insns of all basic block. */
10093 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
10094 int verbose ATTRIBUTE_UNUSED,
10099 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
10100 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
10101 r0_life_regions = 0;
10103 FOR_EACH_BB_REVERSE (b)
10105 find_regmode_weight (b, SImode);
10106 find_regmode_weight (b, SFmode);
10107 if (!reload_completed)
10108 r0_life_regions += find_r0_life_regions (b);
10111 CURR_REGMODE_PRESSURE (SImode) = 0;
10112 CURR_REGMODE_PRESSURE (SFmode) = 0;
10118 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
10119 int verbose ATTRIBUTE_UNUSED)
10121 if (regmode_weight[0])
10123 free (regmode_weight[0]);
10124 regmode_weight[0] = NULL;
10126 if (regmode_weight[1])
10128 free (regmode_weight[1]);
10129 regmode_weight[1] = NULL;
10133 /* The scalar modes supported differs from the default version in TImode
10134 for 32-bit SHMEDIA. */
10136 sh_scalar_mode_supported_p (enum machine_mode mode)
10138 if (TARGET_SHMEDIA32 && mode == TImode)
10141 return default_scalar_mode_supported_p (mode);
10144 /* Cache the can_issue_more so that we can return it from reorder2. Also,
10145 keep count of register pressures on SImode and SFmode. */
10147 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
10148 int sched_verbose ATTRIBUTE_UNUSED,
10150 int can_issue_more)
10152 if (GET_CODE (PATTERN (insn)) != USE
10153 && GET_CODE (PATTERN (insn)) != CLOBBER)
10154 cached_can_issue_more = can_issue_more - 1;
10156 cached_can_issue_more = can_issue_more;
10158 if (reload_completed)
10159 return cached_can_issue_more;
10161 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
10162 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
10164 return cached_can_issue_more;
10168 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
10169 int verbose ATTRIBUTE_UNUSED,
10170 int veclen ATTRIBUTE_UNUSED)
10172 CURR_REGMODE_PRESSURE (SImode) = 0;
10173 CURR_REGMODE_PRESSURE (SFmode) = 0;
10176 /* Some magic numbers. */
10177 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10178 functions that already have high pressure on r0. */
10179 #define R0_MAX_LIFE_REGIONS 2
10180 /* Register Pressure thresholds for SImode and SFmode registers. */
10181 #define SIMODE_MAX_WEIGHT 5
10182 #define SFMODE_MAX_WEIGHT 10
10184 /* Return true if the pressure is high for MODE. */
10186 high_pressure (enum machine_mode mode)
10188 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10189 functions that already have high pressure on r0. */
10190 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
10193 if (mode == SFmode)
10194 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
10196 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
10199 /* Reorder ready queue if register pressure is high. */
10201 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
10202 int sched_verbose ATTRIBUTE_UNUSED,
10205 int clock_var ATTRIBUTE_UNUSED)
10207 if (reload_completed)
10208 return sh_issue_rate ();
10210 if (high_pressure (SFmode) || high_pressure (SImode))
10212 ready_reorder (ready, *n_readyp);
10215 return sh_issue_rate ();
10218 /* Skip cycles if the current register pressure is high. */
10220 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
10221 int sched_verbose ATTRIBUTE_UNUSED,
10222 rtx *ready ATTRIBUTE_UNUSED,
10223 int *n_readyp ATTRIBUTE_UNUSED,
10224 int clock_var ATTRIBUTE_UNUSED)
10226 if (reload_completed)
10227 return cached_can_issue_more;
10229 if (high_pressure(SFmode) || high_pressure (SImode))
10232 return cached_can_issue_more;
10235 /* Skip cycles without sorting the ready queue. This will move insn from
10236 Q->R. If this is the last cycle we are skipping; allow sorting of ready
10237 queue by sh_reorder. */
10239 /* Generally, skipping these many cycles are sufficient for all insns to move
10241 #define MAX_SKIPS 8
10244 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
10245 int sched_verbose ATTRIBUTE_UNUSED,
10246 rtx insn ATTRIBUTE_UNUSED,
10247 int last_clock_var,
10251 if (reload_completed)
10256 if ((clock_var - last_clock_var) < MAX_SKIPS)
10261 /* If this is the last cycle we are skipping, allow reordering of R. */
10262 if ((clock_var - last_clock_var) == MAX_SKIPS)
10274 /* SHmedia requires registers for branches, so we can't generate new
10275 branches past reload. */
10277 sh_cannot_modify_jumps_p (void)
10279 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
10282 static enum reg_class
10283 sh_target_reg_class (void)
10285 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
10289 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
10291 HARD_REG_SET dummy;
10296 if (! shmedia_space_reserved_for_target_registers)
10298 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
10300 if (calc_live_regs (&dummy) >= 6 * 8)
10306 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
10308 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
10312 On the SH1..SH4, the trampoline looks like
10313 2 0002 D202 mov.l l2,r2
10314 1 0000 D301 mov.l l1,r3
10315 3 0004 422B jmp @r2
10317 5 0008 00000000 l1: .long area
10318 6 000c 00000000 l2: .long function
10320 SH5 (compact) uses r1 instead of r3 for the static chain. */
10323 /* Emit RTL insns to initialize the variable parts of a trampoline.
10324 FNADDR is an RTX for the address of the function's pure code.
10325 CXT is an RTX for the static chain value for the function. */
10328 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
10330 rtx tramp_mem = gen_frame_mem (BLKmode, tramp);
10332 if (TARGET_SHMEDIA64)
10337 rtx movi1 = GEN_INT (0xcc000010);
10338 rtx shori1 = GEN_INT (0xc8000010);
10341 /* The following trampoline works within a +- 128 KB range for cxt:
10342 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10343 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10344 gettr tr1,r1; blink tr0,r63 */
10345 /* Address rounding makes it hard to compute the exact bounds of the
10346 offset for this trampoline, but we have a rather generous offset
10347 range, so frame_offset should do fine as an upper bound. */
10348 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
10350 /* ??? could optimize this trampoline initialization
10351 by writing DImode words with two insns each. */
10352 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
10353 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
10354 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
10355 insn = gen_rtx_AND (DImode, insn, mask);
10356 /* Or in ptb/u .,tr1 pattern */
10357 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
10358 insn = force_operand (insn, NULL_RTX);
10359 insn = gen_lowpart (SImode, insn);
10360 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
10361 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
10362 insn = gen_rtx_AND (DImode, insn, mask);
10363 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
10364 insn = gen_lowpart (SImode, insn);
10365 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
10366 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
10367 insn = gen_rtx_AND (DImode, insn, mask);
10368 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10369 insn = gen_lowpart (SImode, insn);
10370 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
10371 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
10372 insn = gen_rtx_AND (DImode, insn, mask);
10373 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10374 insn = gen_lowpart (SImode, insn);
10375 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
10376 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
10377 insn = gen_rtx_AND (DImode, insn, mask);
10378 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10379 insn = gen_lowpart (SImode, insn);
10380 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
10381 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
10382 GEN_INT (0x6bf10600));
10383 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
10384 GEN_INT (0x4415fc10));
10385 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
10386 GEN_INT (0x4401fff0));
10387 emit_insn (gen_ic_invalidate_line (tramp));
10390 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
10391 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
10393 tramp_templ = gen_datalabel_ref (tramp_templ);
10395 src = gen_const_mem (BLKmode, tramp_templ);
10396 set_mem_align (dst, 256);
10397 set_mem_align (src, 64);
10398 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
10400 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
10401 emit_move_insn (adjust_address (tramp_mem, Pmode,
10402 fixed_len + GET_MODE_SIZE (Pmode)),
10404 emit_insn (gen_ic_invalidate_line (tramp));
10407 else if (TARGET_SHMEDIA)
10409 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10410 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10411 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
10412 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
10413 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
10414 rotated 10 right, and higher 16 bit of every 32 selected. */
10416 = force_reg (V2HImode, (simplify_gen_subreg
10417 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
10418 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
10419 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
10421 tramp = force_reg (Pmode, tramp);
10422 fnaddr = force_reg (SImode, fnaddr);
10423 cxt = force_reg (SImode, cxt);
10424 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
10425 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
10427 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
10428 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10429 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
10430 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
10431 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
10432 gen_rtx_SUBREG (V2HImode, cxt, 0),
10434 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
10435 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10436 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
10437 if (TARGET_LITTLE_ENDIAN)
10439 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
10440 emit_insn (gen_mextr4 (quad2, cxtload, blink));
10444 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
10445 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
10447 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
10448 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
10449 emit_insn (gen_ic_invalidate_line (tramp));
10452 else if (TARGET_SHCOMPACT)
10454 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
10457 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
10458 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
10460 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
10461 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
10463 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
10464 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
10465 if (TARGET_HARVARD)
10467 if (!TARGET_INLINE_IC_INVALIDATE
10468 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
10469 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10470 FUNCTION_ORDINARY),
10471 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
10473 emit_insn (gen_ic_invalidate_line (tramp));
10477 /* FIXME: This is overly conservative. A SHcompact function that
10478 receives arguments ``by reference'' will have them stored in its
10479 own stack frame, so it must not pass pointers or references to
10480 these arguments to other functions by means of sibling calls. */
10481 /* If PIC, we cannot make sibling calls to global functions
10482 because the PLT requires r12 to be live. */
10484 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10487 && (! TARGET_SHCOMPACT
10488 || crtl->args.info.stack_regs == 0)
10489 && ! sh_cfun_interrupt_handler_p ()
10491 || (decl && ! TREE_PUBLIC (decl))
10492 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
10495 /* Machine specific built-in functions. */
10497 struct builtin_description
10499 const enum insn_code icode;
10500 const char *const name;
10504 /* describe number and signedness of arguments; arg[0] == result
10505 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
10506 /* 9: 64-bit pointer, 10: 32-bit pointer */
10507 static const char signature_args[][4] =
10509 #define SH_BLTIN_V2SI2 0
10511 #define SH_BLTIN_V4HI2 1
10513 #define SH_BLTIN_V2SI3 2
10515 #define SH_BLTIN_V4HI3 3
10517 #define SH_BLTIN_V8QI3 4
10519 #define SH_BLTIN_MAC_HISI 5
10521 #define SH_BLTIN_SH_HI 6
10523 #define SH_BLTIN_SH_SI 7
10525 #define SH_BLTIN_V4HI2V2SI 8
10527 #define SH_BLTIN_V4HI2V8QI 9
10529 #define SH_BLTIN_SISF 10
10531 #define SH_BLTIN_LDUA_L 11
10533 #define SH_BLTIN_LDUA_Q 12
10535 #define SH_BLTIN_STUA_L 13
10537 #define SH_BLTIN_STUA_Q 14
10539 #define SH_BLTIN_LDUA_L64 15
10541 #define SH_BLTIN_LDUA_Q64 16
10543 #define SH_BLTIN_STUA_L64 17
10545 #define SH_BLTIN_STUA_Q64 18
10547 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10548 #define SH_BLTIN_2 19
10549 #define SH_BLTIN_SU 19
10551 #define SH_BLTIN_3 20
10552 #define SH_BLTIN_SUS 20
10554 #define SH_BLTIN_PSSV 21
10556 #define SH_BLTIN_XXUU 22
10557 #define SH_BLTIN_UUUU 22
10559 #define SH_BLTIN_PV 23
10562 /* mcmv: operands considered unsigned. */
10563 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
10564 /* mperm: control value considered unsigned int. */
10565 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
10566 /* mshards_q: returns signed short. */
10567 /* nsb: takes long long arg, returns unsigned char. */
10568 static const struct builtin_description bdesc[] =
10570 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
10571 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
10572 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
10573 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
10574 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
10575 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
10576 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
10577 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
10578 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
10579 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
10580 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
10581 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
10582 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
10583 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
10584 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
10585 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
10586 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
10587 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
10588 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 },
10589 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 },
10590 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 },
10591 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 },
10592 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 },
10593 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 },
10594 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 },
10595 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
10596 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
10597 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
10598 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
10599 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
10600 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
10601 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
10602 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
10603 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
10604 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
10605 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
10606 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
10607 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
10608 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
10609 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
10610 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
10611 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
10612 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
10613 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
10614 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
10615 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
10616 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
10617 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
10618 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
10619 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
10620 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
10621 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
10622 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
10623 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
10624 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
10625 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
10626 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
10627 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
10628 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
10629 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
10630 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
10631 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 },
10632 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 },
10633 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 },
10634 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
10635 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
10636 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
10637 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
10638 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
10639 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
10640 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
10641 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
10642 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
10643 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 },
10644 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 },
10645 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 },
10646 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 },
10647 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 },
10648 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 },
10649 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 },
10650 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 },
10651 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
10652 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
10653 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
10657 sh_media_init_builtins (void)
10659 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
10660 const struct builtin_description *d;
10662 memset (shared, 0, sizeof shared);
10663 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
10665 tree type, arg_type = 0;
10666 int signature = d->signature;
10669 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
10670 type = shared[signature];
10673 int has_result = signature_args[signature][0] != 0;
10675 if ((signature_args[signature][1] & 8)
10676 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
10677 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
10679 if (! TARGET_FPU_ANY
10680 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
10682 type = void_list_node;
10685 int arg = signature_args[signature][i];
10686 int opno = i - 1 + has_result;
10689 arg_type = ptr_type_node;
10691 arg_type = (*lang_hooks.types.type_for_mode)
10692 (insn_data[d->icode].operand[opno].mode,
10697 arg_type = void_type_node;
10700 type = tree_cons (NULL_TREE, arg_type, type);
10702 type = build_function_type (arg_type, type);
10703 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10704 shared[signature] = type;
10706 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10711 /* Implements target hook vector_mode_supported_p. */
10713 sh_vector_mode_supported_p (enum machine_mode mode)
10716 && ((mode == V2SFmode)
10717 || (mode == V4SFmode)
10718 || (mode == V16SFmode)))
10721 else if (TARGET_SHMEDIA
10722 && ((mode == V8QImode)
10723 || (mode == V2HImode)
10724 || (mode == V4HImode)
10725 || (mode == V2SImode)))
10731 /* Implements target hook dwarf_calling_convention. Return an enum
10732 of dwarf_calling_convention. */
10734 sh_dwarf_calling_convention (const_tree func)
10736 if (sh_attr_renesas_p (func))
10737 return DW_CC_GNU_renesas_sh;
10739 return DW_CC_normal;
10743 sh_init_builtins (void)
10745 if (TARGET_SHMEDIA)
10746 sh_media_init_builtins ();
10749 /* Expand an expression EXP that calls a built-in function,
10750 with result going to TARGET if that's convenient
10751 (and in mode MODE if that's convenient).
10752 SUBTARGET may be used as the target for computing one of EXP's operands.
10753 IGNORE is nonzero if the value is to be ignored. */
10756 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10757 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
10759 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10760 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10761 const struct builtin_description *d = &bdesc[fcode];
10762 enum insn_code icode = d->icode;
10763 int signature = d->signature;
10764 enum machine_mode tmode = VOIDmode;
10769 if (signature_args[signature][0])
10774 tmode = insn_data[icode].operand[0].mode;
10776 || GET_MODE (target) != tmode
10777 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10778 target = gen_reg_rtx (tmode);
10779 op[nop++] = target;
10784 for (i = 1; i <= 3; i++, nop++)
10787 enum machine_mode opmode, argmode;
10790 if (! signature_args[signature][i])
10792 arg = CALL_EXPR_ARG (exp, i - 1);
10793 if (arg == error_mark_node)
10795 if (signature_args[signature][i] & 8)
10798 optype = ptr_type_node;
10802 opmode = insn_data[icode].operand[nop].mode;
10803 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10805 argmode = TYPE_MODE (TREE_TYPE (arg));
10806 if (argmode != opmode)
10807 arg = build1 (NOP_EXPR, optype, arg);
10808 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
10809 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10810 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10816 pat = (*insn_data[d->icode].genfun) (op[0]);
10819 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10822 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10825 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10828 gcc_unreachable ();
10837 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
10839 rtx sel0 = const0_rtx;
10840 rtx sel1 = const1_rtx;
10841 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
10842 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
10844 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
10845 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
10849 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
10851 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
10853 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
10854 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
10857 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
10858 We can allow any mode in any general register. The special registers
10859 only allow SImode. Don't allow any mode in the PR.
10861 We cannot hold DCmode values in the XD registers because alter_reg
10862 handles subregs of them incorrectly. We could work around this by
10863 spacing the XD registers like the DR registers, but this would require
10864 additional memory in every compilation to hold larger register vectors.
10865 We could hold SFmode / SCmode values in XD registers, but that
10866 would require a tertiary reload when reloading from / to memory,
10867 and a secondary reload to reload from / to general regs; that
10868 seems to be a loosing proposition.
10870 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
10871 it won't be ferried through GP registers first. */
10874 sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
10876 if (SPECIAL_REGISTER_P (regno))
10877 return mode == SImode;
10879 if (regno == FPUL_REG)
10880 return (mode == SImode || mode == SFmode);
10882 if (FP_REGISTER_P (regno) && mode == SFmode)
10885 if (mode == V2SFmode)
10887 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
10888 || GENERAL_REGISTER_P (regno)))
10894 if (mode == V4SFmode)
10896 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
10897 || GENERAL_REGISTER_P (regno))
10903 if (mode == V16SFmode)
10905 if (TARGET_SHMEDIA)
10907 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
10913 return regno == FIRST_XD_REG;
10916 if (FP_REGISTER_P (regno))
10920 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
10921 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
10924 && (mode == DFmode || mode == DImode
10925 || mode == V2SFmode || mode == TImode)))
10926 && ((regno - FIRST_FP_REG) & 1) == 0)
10927 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
10928 && ((regno - FIRST_FP_REG) & 3) == 0))
10934 if (XD_REGISTER_P (regno))
10935 return mode == DFmode;
10937 if (TARGET_REGISTER_P (regno))
10938 return (mode == DImode || mode == SImode || mode == PDImode);
10940 if (regno == PR_REG)
10941 return mode == SImode;
10943 if (regno == FPSCR_REG)
10944 return mode == PSImode;
10946 /* FIXME. This works around PR target/37633 for -O0. */
10947 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
10949 unsigned int n = GET_MODE_SIZE (mode) / 8;
10951 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
10952 && regno <= FIRST_GENERAL_REG + 14)
10959 /* Return the class of registers for which a mode change from FROM to TO
10962 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
10963 enum reg_class rclass)
10965 /* We want to enable the use of SUBREGs as a means to
10966 VEC_SELECT a single element of a vector. */
10967 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
10968 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
10970 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10972 if (TARGET_LITTLE_ENDIAN)
10974 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
10975 return reg_classes_intersect_p (DF_REGS, rclass);
10979 if (GET_MODE_SIZE (from) < 8)
10980 return reg_classes_intersect_p (DF_HI_REGS, rclass);
10987 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10988 that label is used. */
10991 sh_mark_label (rtx address, int nuses)
10993 if (GOTOFF_P (address))
10995 /* Extract the label or symbol. */
10996 address = XEXP (address, 0);
10997 if (GET_CODE (address) == PLUS)
10998 address = XEXP (address, 0);
10999 address = XVECEXP (address, 0, 0);
11001 if (GET_CODE (address) == LABEL_REF
11002 && LABEL_P (XEXP (address, 0)))
11003 LABEL_NUSES (XEXP (address, 0)) += nuses;
11006 /* Compute extra cost of moving data between one register class
11009 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
11010 uses this information. Hence, the general register <-> floating point
11011 register information here is not used for SFmode. */
11014 sh_register_move_cost (enum machine_mode mode,
11015 enum reg_class srcclass, enum reg_class dstclass)
11017 if (dstclass == T_REGS || dstclass == PR_REGS)
11020 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
11023 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
11024 && REGCLASS_HAS_FP_REG (srcclass)
11025 && REGCLASS_HAS_FP_REG (dstclass))
11028 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
11029 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
11031 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
11032 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
11035 if ((REGCLASS_HAS_FP_REG (dstclass)
11036 && REGCLASS_HAS_GENERAL_REG (srcclass))
11037 || (REGCLASS_HAS_GENERAL_REG (dstclass)
11038 && REGCLASS_HAS_FP_REG (srcclass)))
11039 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
11040 * ((GET_MODE_SIZE (mode) + 7) / 8U));
11042 if ((dstclass == FPUL_REGS
11043 && REGCLASS_HAS_GENERAL_REG (srcclass))
11044 || (srcclass == FPUL_REGS
11045 && REGCLASS_HAS_GENERAL_REG (dstclass)))
11048 if ((dstclass == FPUL_REGS
11049 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
11050 || (srcclass == FPUL_REGS
11051 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
11054 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11055 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11058 /* ??? ptabs faults on (value & 0x3) == 0x3 */
11060 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
11062 if (sh_gettrcost >= 0)
11063 return sh_gettrcost;
11064 else if (!TARGET_PT_FIXED)
11068 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11069 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11074 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
11075 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
11076 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
11078 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
11081 static rtx emit_load_ptr (rtx, rtx);
11084 emit_load_ptr (rtx reg, rtx addr)
11086 rtx mem = gen_const_mem (ptr_mode, addr);
11088 if (Pmode != ptr_mode)
11089 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
11090 return emit_move_insn (reg, mem);
11094 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11095 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11098 CUMULATIVE_ARGS cum;
11099 int structure_value_byref = 0;
11100 rtx this_rtx, this_value, sibcall, insns, funexp;
11101 tree funtype = TREE_TYPE (function);
11102 int simple_add = CONST_OK_FOR_ADD (delta);
11104 rtx scratch0, scratch1, scratch2;
11107 reload_completed = 1;
11108 epilogue_completed = 1;
11109 current_function_uses_only_leaf_regs = 1;
11111 emit_note (NOTE_INSN_PROLOGUE_END);
11113 /* Find the "this" pointer. We have such a wide range of ABIs for the
11114 SH that it's best to do this completely machine independently.
11115 "this" is passed as first argument, unless a structure return pointer
11116 comes first, in which case "this" comes second. */
11117 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
11118 #ifndef PCC_STATIC_STRUCT_RETURN
11119 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11120 structure_value_byref = 1;
11121 #endif /* not PCC_STATIC_STRUCT_RETURN */
11122 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
11124 tree ptype = build_pointer_type (TREE_TYPE (funtype));
11126 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
11128 this_rtx = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
11130 /* For SHcompact, we only have r0 for a scratch register: r1 is the
11131 static chain pointer (even if you can't have nested virtual functions
11132 right now, someone might implement them sometime), and the rest of the
11133 registers are used for argument passing, are callee-saved, or reserved. */
11134 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
11135 -ffixed-reg has been used. */
11136 if (! call_used_regs[0] || fixed_regs[0])
11137 error ("r0 needs to be available as a call-clobbered register");
11138 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
11141 if (call_used_regs[1] && ! fixed_regs[1])
11142 scratch1 = gen_rtx_REG (ptr_mode, 1);
11143 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
11144 pointing where to return struct values. */
11145 if (call_used_regs[3] && ! fixed_regs[3])
11146 scratch2 = gen_rtx_REG (Pmode, 3);
11148 else if (TARGET_SHMEDIA)
11150 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
11151 if (i != REGNO (scratch0) &&
11152 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
11154 scratch1 = gen_rtx_REG (ptr_mode, i);
11157 if (scratch1 == scratch0)
11158 error ("Need a second call-clobbered general purpose register");
11159 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
11160 if (call_used_regs[i] && ! fixed_regs[i])
11162 scratch2 = gen_rtx_REG (Pmode, i);
11165 if (scratch2 == scratch0)
11166 error ("Need a call-clobbered target register");
11169 this_value = plus_constant (this_rtx, delta);
11171 && (simple_add || scratch0 != scratch1)
11172 && strict_memory_address_p (ptr_mode, this_value))
11174 emit_load_ptr (scratch0, this_value);
11179 ; /* Do nothing. */
11180 else if (simple_add)
11181 emit_move_insn (this_rtx, this_value);
11184 emit_move_insn (scratch1, GEN_INT (delta));
11185 emit_insn (gen_add2_insn (this_rtx, scratch1));
11193 emit_load_ptr (scratch0, this_rtx);
11195 offset_addr = plus_constant (scratch0, vcall_offset);
11196 if (strict_memory_address_p (ptr_mode, offset_addr))
11197 ; /* Do nothing. */
11198 else if (! TARGET_SH5 && scratch0 != scratch1)
11200 /* scratch0 != scratch1, and we have indexed loads. Get better
11201 schedule by loading the offset into r1 and using an indexed
11202 load - then the load of r1 can issue before the load from
11203 (this_rtx + delta) finishes. */
11204 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11205 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
11207 else if (CONST_OK_FOR_ADD (vcall_offset))
11209 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
11210 offset_addr = scratch0;
11212 else if (scratch0 != scratch1)
11214 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11215 emit_insn (gen_add2_insn (scratch0, scratch1));
11216 offset_addr = scratch0;
11219 gcc_unreachable (); /* FIXME */
11220 emit_load_ptr (scratch0, offset_addr);
11222 if (Pmode != ptr_mode)
11223 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
11224 emit_insn (gen_add2_insn (this_rtx, scratch0));
11227 /* Generate a tail call to the target function. */
11228 if (! TREE_USED (function))
11230 assemble_external (function);
11231 TREE_USED (function) = 1;
11233 funexp = XEXP (DECL_RTL (function), 0);
11234 /* If the function is overridden, so is the thunk, hence we don't
11235 need GOT addressing even if this is a public symbol. */
11237 if (TARGET_SH1 && ! flag_weak)
11238 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
11241 if (TARGET_SH2 && flag_pic)
11243 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
11244 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
11248 if (TARGET_SHMEDIA && flag_pic)
11250 funexp = gen_sym2PIC (funexp);
11251 PUT_MODE (funexp, Pmode);
11253 emit_move_insn (scratch2, funexp);
11254 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
11255 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
11257 sibcall = emit_call_insn (sibcall);
11258 SIBLING_CALL_P (sibcall) = 1;
11259 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
11262 /* Run just enough of rest_of_compilation to do scheduling and get
11263 the insns emitted. Note that use_thunk calls
11264 assemble_start_function and assemble_end_function. */
11266 insn_locators_alloc ();
11267 insns = get_insns ();
11273 split_all_insns_noflow ();
11278 if (optimize > 0 && flag_delayed_branch)
11279 dbr_schedule (insns);
11281 shorten_branches (insns);
11282 final_start_function (insns, file, 1);
11283 final (insns, file, 1);
11284 final_end_function ();
11285 free_after_compilation (cfun);
11287 reload_completed = 0;
11288 epilogue_completed = 0;
11292 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
11296 /* If this is not an ordinary function, the name usually comes from a
11297 string literal or an sprintf buffer. Make sure we use the same
11298 string consistently, so that cse will be able to unify address loads. */
11299 if (kind != FUNCTION_ORDINARY)
11300 name = IDENTIFIER_POINTER (get_identifier (name));
11301 sym = gen_rtx_SYMBOL_REF (Pmode, name);
11302 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
11306 case FUNCTION_ORDINARY:
11310 rtx reg = target ? target : gen_reg_rtx (Pmode);
11312 emit_insn (gen_symGOT2reg (reg, sym));
11318 /* ??? To allow cse to work, we use GOTOFF relocations.
11319 we could add combiner patterns to transform this into
11320 straight pc-relative calls with sym2PIC / bsrf when
11321 label load and function call are still 1:1 and in the
11322 same basic block during combine. */
11323 rtx reg = target ? target : gen_reg_rtx (Pmode);
11325 emit_insn (gen_symGOTOFF2reg (reg, sym));
11330 if (target && sym != target)
11332 emit_move_insn (target, sym);
11338 /* Find the number of a general purpose register in S. */
11340 scavenge_reg (HARD_REG_SET *s)
11343 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11344 if (TEST_HARD_REG_BIT (*s, r))
11350 sh_get_pr_initial_val (void)
11354 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11355 PR register on SHcompact, because it might be clobbered by the prologue.
11356 We check first if that is known to be the case. */
11357 if (TARGET_SHCOMPACT
11358 && ((crtl->args.info.call_cookie
11359 & ~ CALL_COOKIE_RET_TRAMP (1))
11360 || crtl->saves_all_registers))
11361 return gen_frame_mem (SImode, return_address_pointer_rtx);
11363 /* If we haven't finished rtl generation, there might be a nonlocal label
11364 that we haven't seen yet.
11365 ??? get_hard_reg_initial_val fails if it is called after register
11366 allocation has started, unless it has been called before for the
11367 same register. And even then, we end in trouble if we didn't use
11368 the register in the same basic block before. So call
11369 get_hard_reg_initial_val now and wrap it in an unspec if we might
11370 need to replace it. */
11371 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11372 combine can put the pseudo returned by get_hard_reg_initial_val into
11373 instructions that need a general purpose registers, which will fail to
11374 be recognized when the pseudo becomes allocated to PR. */
11376 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
11378 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11383 sh_expand_t_scc (rtx operands[])
11385 enum rtx_code code = GET_CODE (operands[1]);
11386 rtx target = operands[0];
11387 rtx op0 = operands[2];
11388 rtx op1 = operands[3];
11389 rtx result = target;
11392 if (!REG_P (op0) || REGNO (op0) != T_REG
11393 || !CONST_INT_P (op1))
11395 if (!REG_P (result))
11396 result = gen_reg_rtx (SImode);
11397 val = INTVAL (op1);
11398 if ((code == EQ && val == 1) || (code == NE && val == 0))
11399 emit_insn (gen_movt (result));
11400 else if (TARGET_SH2A && ((code == EQ && val == 0)
11401 || (code == NE && val == 1)))
11402 emit_insn (gen_xorsi3_movrt (result));
11403 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11405 emit_clobber (result);
11406 emit_insn (gen_subc (result, result, result));
11407 emit_insn (gen_addsi3 (result, result, const1_rtx));
11409 else if (code == EQ || code == NE)
11410 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11413 if (result != target)
11414 emit_move_insn (target, result);
11418 /* INSN is an sfunc; return the rtx that describes the address used. */
11420 extract_sfunc_addr (rtx insn)
11422 rtx pattern, part = NULL_RTX;
11425 pattern = PATTERN (insn);
11426 len = XVECLEN (pattern, 0);
11427 for (i = 0; i < len; i++)
11429 part = XVECEXP (pattern, 0, i);
11430 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
11431 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
11432 return XEXP (part, 0);
11434 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
11435 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
11438 /* Verify that the register in use_sfunc_addr still agrees with the address
11439 used in the sfunc. This prevents fill_slots_from_thread from changing
11441 INSN is the use_sfunc_addr instruction, and REG is the register it
11444 check_use_sfunc_addr (rtx insn, rtx reg)
11446 /* Search for the sfunc. It should really come right after INSN. */
11447 while ((insn = NEXT_INSN (insn)))
11449 if (LABEL_P (insn) || JUMP_P (insn))
11451 if (! INSN_P (insn))
11454 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11455 insn = XVECEXP (PATTERN (insn), 0, 0);
11456 if (GET_CODE (PATTERN (insn)) != PARALLEL
11457 || get_attr_type (insn) != TYPE_SFUNC)
11459 return rtx_equal_p (extract_sfunc_addr (insn), reg);
11461 gcc_unreachable ();
11464 /* This function returns a constant rtx that represents pi / 2**15 in
11465 SFmode. it's used to scale SFmode angles, in radians, to a
11466 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11467 maps to 0x10000). */
11469 static GTY(()) rtx sh_fsca_sf2int_rtx;
11472 sh_fsca_sf2int (void)
11474 if (! sh_fsca_sf2int_rtx)
11476 REAL_VALUE_TYPE rv;
11478 real_from_string (&rv, "10430.378350470453");
11479 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
11482 return sh_fsca_sf2int_rtx;
11485 /* This function returns a constant rtx that represents pi / 2**15 in
11486 DFmode. it's used to scale DFmode angles, in radians, to a
11487 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11488 maps to 0x10000). */
11490 static GTY(()) rtx sh_fsca_df2int_rtx;
11493 sh_fsca_df2int (void)
11495 if (! sh_fsca_df2int_rtx)
11497 REAL_VALUE_TYPE rv;
11499 real_from_string (&rv, "10430.378350470453");
11500 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
11503 return sh_fsca_df2int_rtx;
11506 /* This function returns a constant rtx that represents 2**15 / pi in
11507 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
11508 of a full circle back to a SFmode value, i.e., 0x10000 maps to
11511 static GTY(()) rtx sh_fsca_int2sf_rtx;
11514 sh_fsca_int2sf (void)
11516 if (! sh_fsca_int2sf_rtx)
11518 REAL_VALUE_TYPE rv;
11520 real_from_string (&rv, "9.587379924285257e-5");
11521 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
11524 return sh_fsca_int2sf_rtx;
11527 /* Initialize the CUMULATIVE_ARGS structure. */
11530 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
11532 rtx libname ATTRIBUTE_UNUSED,
11534 signed int n_named_args,
11535 enum machine_mode mode)
11537 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
11538 pcum->free_single_fp_reg = 0;
11539 pcum->stack_regs = 0;
11540 pcum->byref_regs = 0;
11542 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
11544 /* XXX - Should we check TARGET_HITACHI here ??? */
11545 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
11549 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
11550 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
11551 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
11552 pcum->arg_count [(int) SH_ARG_INT]
11553 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
11556 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11557 && pcum->arg_count [(int) SH_ARG_INT] == 0
11558 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
11559 ? int_size_in_bytes (TREE_TYPE (fntype))
11560 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
11561 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
11562 == FIRST_RET_REG));
11566 pcum->arg_count [(int) SH_ARG_INT] = 0;
11567 pcum->prototype_p = FALSE;
11568 if (mode != VOIDmode)
11570 pcum->call_cookie =
11571 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11572 && GET_MODE_SIZE (mode) > 4
11573 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
11575 /* If the default ABI is the Renesas ABI then all library
11576 calls must assume that the library will be using the
11577 Renesas ABI. So if the function would return its result
11578 in memory then we must force the address of this memory
11579 block onto the stack. Ideally we would like to call
11580 targetm.calls.return_in_memory() here but we do not have
11581 the TYPE or the FNDECL available so we synthesize the
11582 contents of that function as best we can. */
11584 (TARGET_DEFAULT & MASK_HITACHI)
11585 && (mode == BLKmode
11586 || (GET_MODE_SIZE (mode) > 4
11587 && !(mode == DFmode
11588 && TARGET_FPU_DOUBLE)));
11592 pcum->call_cookie = 0;
11593 pcum->force_mem = FALSE;
11598 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
11599 not enter into CONST_DOUBLE for the replace.
11601 Note that copying is not done so X must not be shared unless all copies
11602 are to be modified.
11604 This is like replace_rtx, except that we operate on N_REPLACEMENTS
11605 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
11606 replacements[n*2+1] - and that we take mode changes into account.
11608 If a replacement is ambiguous, return NULL_RTX.
11610 If MODIFY is zero, don't modify any rtl in place,
11611 just return zero or nonzero for failure / success. */
11614 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
11619 /* The following prevents loops occurrence when we change MEM in
11620 CONST_DOUBLE onto the same CONST_DOUBLE. */
11621 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
11624 for (i = n_replacements - 1; i >= 0 ; i--)
11625 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
11626 return replacements[i*2+1];
11628 /* Allow this function to make replacements in EXPR_LISTs. */
11632 if (GET_CODE (x) == SUBREG)
11634 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
11635 n_replacements, modify);
11637 if (CONST_INT_P (new_rtx))
11639 x = simplify_subreg (GET_MODE (x), new_rtx,
11640 GET_MODE (SUBREG_REG (x)),
11646 SUBREG_REG (x) = new_rtx;
11650 else if (REG_P (x))
11652 unsigned regno = REGNO (x);
11653 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
11654 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11655 rtx result = NULL_RTX;
11657 for (i = n_replacements - 1; i >= 0; i--)
11659 rtx from = replacements[i*2];
11660 rtx to = replacements[i*2+1];
11661 unsigned from_regno, from_nregs, to_regno, new_regno;
11665 from_regno = REGNO (from);
11666 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
11667 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
11668 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
11670 if (regno < from_regno
11671 || regno + nregs > from_regno + nregs
11675 to_regno = REGNO (to);
11676 if (to_regno < FIRST_PSEUDO_REGISTER)
11678 new_regno = regno + to_regno - from_regno;
11679 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
11682 result = gen_rtx_REG (GET_MODE (x), new_regno);
11684 else if (GET_MODE (x) <= GET_MODE (to))
11685 result = gen_lowpart_common (GET_MODE (x), to);
11687 result = gen_lowpart_SUBREG (GET_MODE (x), to);
11690 return result ? result : x;
11692 else if (GET_CODE (x) == ZERO_EXTEND)
11694 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
11695 n_replacements, modify);
11697 if (CONST_INT_P (new_rtx))
11699 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
11700 new_rtx, GET_MODE (XEXP (x, 0)));
11705 XEXP (x, 0) = new_rtx;
11710 fmt = GET_RTX_FORMAT (GET_CODE (x));
11711 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
11717 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
11718 n_replacements, modify);
11722 XEXP (x, i) = new_rtx;
11724 else if (fmt[i] == 'E')
11725 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11727 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
11728 n_replacements, modify);
11732 XVECEXP (x, i, j) = new_rtx;
11740 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
11742 enum rtx_code code = TRUNCATE;
11744 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
11746 rtx inner = XEXP (x, 0);
11747 enum machine_mode inner_mode = GET_MODE (inner);
11749 if (inner_mode == mode)
11751 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
11753 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
11754 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
11756 code = GET_CODE (x);
11760 return gen_rtx_fmt_e (code, mode, x);
11763 /* called via for_each_rtx after reload, to clean up truncates of
11764 registers that span multiple actual hard registers. */
11766 shmedia_cleanup_truncate (rtx *p, void *n_changes)
11770 if (GET_CODE (x) != TRUNCATE)
11773 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && REG_P (reg))
11775 enum machine_mode reg_mode = GET_MODE (reg);
11776 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
11777 subreg_lowpart_offset (DImode, reg_mode));
11778 *(int*) n_changes += 1;
11784 /* Load and store depend on the highpart of the address. However,
11785 set_attr_alternative does not give well-defined results before reload,
11786 so we must look at the rtl ourselves to see if any of the feeding
11787 registers is used in a memref. */
11789 /* Called by sh_contains_memref_p via for_each_rtx. */
11791 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
11793 return (MEM_P (*loc));
11796 /* Return nonzero iff INSN contains a MEM. */
11798 sh_contains_memref_p (rtx insn)
11800 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
11803 /* Return nonzero iff INSN loads a banked register. */
11805 sh_loads_bankedreg_p (rtx insn)
11807 if (GET_CODE (PATTERN (insn)) == SET)
11809 rtx op = SET_DEST (PATTERN(insn));
11810 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11817 /* FNADDR is the MEM expression from a call expander. Return an address
11818 to use in an SHmedia insn pattern. */
11820 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
11824 fnaddr = XEXP (fnaddr, 0);
11825 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
11826 if (flag_pic && is_sym)
11828 if (! SYMBOL_REF_LOCAL_P (fnaddr))
11830 rtx reg = gen_reg_rtx (Pmode);
11832 /* We must not use GOTPLT for sibcalls, because PIC_REG
11833 must be restored before the PLT code gets to run. */
11835 emit_insn (gen_symGOT2reg (reg, fnaddr));
11837 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
11842 fnaddr = gen_sym2PIC (fnaddr);
11843 PUT_MODE (fnaddr, Pmode);
11846 /* If ptabs might trap, make this visible to the rest of the compiler.
11847 We generally assume that symbols pertain to valid locations, but
11848 it is possible to generate invalid symbols with asm or linker tricks.
11849 In a list of functions where each returns its successor, an invalid
11850 symbol might denote an empty list. */
11851 if (!TARGET_PT_FIXED
11852 && (!is_sym || TARGET_INVALID_SYMBOLS)
11853 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
11855 rtx tr = gen_reg_rtx (PDImode);
11857 emit_insn (gen_ptabs (tr, fnaddr));
11860 else if (! target_reg_operand (fnaddr, Pmode))
11861 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
11866 sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
11867 enum machine_mode mode, secondary_reload_info *sri)
11871 if (REGCLASS_HAS_FP_REG (rclass)
11872 && ! TARGET_SHMEDIA
11873 && immediate_operand ((x), mode)
11874 && ! ((fp_zero_operand (x) || fp_one_operand (x))
11875 && mode == SFmode && fldi_ok ()))
11879 sri->icode = CODE_FOR_reload_insf__frn;
11882 sri->icode = CODE_FOR_reload_indf__frn;
11885 /* ??? If we knew that we are in the appropriate mode -
11886 single precision - we could use a reload pattern directly. */
11891 if (rclass == FPUL_REGS
11893 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11894 || REGNO (x) == T_REG))
11895 || GET_CODE (x) == PLUS))
11896 return GENERAL_REGS;
11897 if (rclass == FPUL_REGS && immediate_operand (x, mode))
11899 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
11900 return GENERAL_REGS;
11901 else if (mode == SFmode)
11903 sri->icode = CODE_FOR_reload_insi__i_fpul;
11906 if (rclass == FPSCR_REGS
11907 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11908 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
11909 return GENERAL_REGS;
11910 if (REGCLASS_HAS_FP_REG (rclass)
11912 && immediate_operand (x, mode)
11913 && x != CONST0_RTX (GET_MODE (x))
11914 && GET_MODE (x) != V4SFmode)
11915 return GENERAL_REGS;
11916 if ((mode == QImode || mode == HImode)
11917 && TARGET_SHMEDIA && inqhi_operand (x, mode))
11919 sri->icode = ((mode == QImode)
11920 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
11923 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
11924 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
11925 return TARGET_REGS;
11926 } /* end of input-only processing. */
11928 if (((REGCLASS_HAS_FP_REG (rclass)
11930 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11931 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11932 && TARGET_FMOVD))))
11933 || (REGCLASS_HAS_GENERAL_REG (rclass)
11935 && FP_REGISTER_P (REGNO (x))))
11936 && ! TARGET_SHMEDIA
11937 && (mode == SFmode || mode == SImode))
11939 if ((rclass == FPUL_REGS
11940 || (REGCLASS_HAS_FP_REG (rclass)
11941 && ! TARGET_SHMEDIA && mode == SImode))
11944 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11945 || REGNO (x) == T_REG
11946 || system_reg_operand (x, VOIDmode)))))
11948 if (rclass == FPUL_REGS)
11949 return GENERAL_REGS;
11952 if ((rclass == TARGET_REGS
11953 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
11954 && !satisfies_constraint_Csy (x)
11955 && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
11956 return GENERAL_REGS;
11957 if ((rclass == MAC_REGS || rclass == PR_REGS)
11958 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
11959 && rclass != REGNO_REG_CLASS (REGNO (x)))
11960 return GENERAL_REGS;
11961 if (rclass != GENERAL_REGS && REG_P (x)
11962 && TARGET_REGISTER_P (REGNO (x)))
11963 return GENERAL_REGS;
11967 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;
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