1 /* Output routines for GCC for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
21 /* Contributed by Steve Chamberlain (sac@cygnus.com).
22 Improved by Jim Wilson (wilson@cygnus.com). */
32 #include "insn-flags.h"
35 #include "hard-reg-set.h"
37 #include "insn-attr.h"
39 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
40 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
42 /* ??? The pragma interrupt support will not work for SH3. */
43 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
44 output code for the next function appropriate for an interrupt handler. */
47 /* This is set by #pragma trapa, and is similar to the above, except that
48 the compiler doesn't emit code to preserve all registers. */
49 static int pragma_trapa;
51 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
52 which has a separate set of low regs for User and Supervisor modes.
53 This should only be used for the lowest level of interrupts. Higher levels
54 of interrupts must save the registers in case they themselves are
56 int pragma_nosave_low_regs;
58 /* This is used for communication between SETUP_INCOMING_VARARGS and
59 sh_expand_prologue. */
60 int current_function_anonymous_args;
62 /* Global variables from toplev.c and final.c that are used within, but
63 not declared in any header file. */
64 extern char *version_string;
65 extern int *insn_addresses;
67 /* Global variables for machine-dependent things. */
69 /* Which cpu are we scheduling for. */
70 enum processor_type sh_cpu;
72 /* Saved operands from the last compare to use when we generate an scc
78 /* Provides the class number of the smallest class containing
81 int regno_reg_class[FIRST_PSEUDO_REGISTER] =
83 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
84 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
85 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
86 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
87 GENERAL_REGS, PR_REGS, T_REGS, NO_REGS,
91 /* Provide reg_class from a letter such as appears in the machine
94 enum reg_class reg_class_from_letter[] =
96 /* a */ NO_REGS, /* b */ NO_REGS, /* c */ NO_REGS, /* d */ NO_REGS,
97 /* e */ NO_REGS, /* f */ NO_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
98 /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ PR_REGS,
99 /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
100 /* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
101 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ NO_REGS, /* x */ MAC_REGS,
102 /* y */ NO_REGS, /* z */ R0_REGS
105 /* Print the operand address in x to the stream. */
108 print_operand_address (stream, x)
112 switch (GET_CODE (x))
115 fprintf (stream, "@%s", reg_names[REGNO (x)]);
120 rtx base = XEXP (x, 0);
121 rtx index = XEXP (x, 1);
123 switch (GET_CODE (index))
126 fprintf (stream, "@(%d,%s)", INTVAL (index),
127 reg_names[REGNO (base)]);
131 fprintf (stream, "@(r0,%s)",
132 reg_names[MAX (REGNO (base), REGNO (index))]);
143 fprintf (stream, "@-%s", reg_names[REGNO (XEXP (x, 0))]);
147 fprintf (stream, "@%s+", reg_names[REGNO (XEXP (x, 0))]);
151 output_addr_const (stream, x);
156 /* Print operand x (an rtx) in assembler syntax to file stream
157 according to modifier code.
159 '.' print a .s if insn needs delay slot
160 '@' print rte or rts depending upon pragma interruptness
161 '#' output a nop if there is nothing to put in the delay slot
162 'O' print a constant without the #
163 'R' print the LSW of a dp value - changes if in little endian
164 'S' print the MSW of a dp value - changes if in little endian
165 'T' print the next word of a dp value - same as 'R' in big endian mode. */
168 print_operand (stream, x, code)
177 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
178 fprintf (stream, ".s");
181 if (pragma_interrupt)
182 fprintf (stream, "rte");
184 fprintf (stream, "rts");
187 /* Output a nop if there's nothing in the delay slot. */
188 if (dbr_sequence_length () == 0)
189 fprintf (stream, "\n\tnop");
192 output_addr_const (stream, x);
195 fputs (reg_names[REGNO (x) + LSW], (stream));
198 fputs (reg_names[REGNO (x) + MSW], (stream));
201 /* Next word of a double. */
202 switch (GET_CODE (x))
205 fputs (reg_names[REGNO (x) + 1], (stream));
208 print_operand_address (stream,
209 XEXP (adj_offsettable_operand (x, 4), 0));
214 switch (GET_CODE (x))
217 fputs (reg_names[REGNO (x)], (stream));
220 output_address (XEXP (x, 0));
224 output_addr_const (stream, x);
231 /* Emit code to perform a block move. Choose the best method.
233 OPERANDS[0] is the destination.
234 OPERANDS[1] is the source.
235 OPERANDS[2] is the size.
236 OPERANDS[3] is the alignment safe to use. */
239 expand_block_move (operands)
242 int align = INTVAL (operands[3]);
243 int constp = (GET_CODE (operands[2]) == CONST_INT);
244 int bytes = (constp ? INTVAL (operands[2]) : 0);
246 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
247 alignment, or if it isn't a multiple of 4 bytes, then fail. */
248 if (! constp || align < 4 || (bytes % 4 != 0))
256 rtx r4 = gen_rtx (REG, SImode, 4);
257 rtx r5 = gen_rtx (REG, SImode, 5);
259 sprintf (entry, "__movstrSI%d", bytes);
260 entry_name = get_identifier (entry);
263 = copy_to_mode_reg (Pmode,
264 gen_rtx (SYMBOL_REF, Pmode,
265 IDENTIFIER_POINTER (entry_name)));
266 emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
267 emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
268 emit_insn (gen_block_move_real (func_addr_rtx));
272 /* This is the same number of bytes as a memcpy call, but to a different
273 less common function name, so this will occasionally use more space. */
274 if (! TARGET_SMALLCODE)
278 int final_switch, while_loop;
279 rtx r4 = gen_rtx (REG, SImode, 4);
280 rtx r5 = gen_rtx (REG, SImode, 5);
281 rtx r6 = gen_rtx (REG, SImode, 6);
283 entry_name = get_identifier ("__movstr");
285 = copy_to_mode_reg (Pmode,
286 gen_rtx (SYMBOL_REF, Pmode,
287 IDENTIFIER_POINTER (entry_name)));
288 emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
289 emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
291 /* r6 controls the size of the move. 16 is decremented from it
292 for each 64 bytes moved. Then the negative bit left over is used
293 as an index into a list of move instructions. e.g., a 72 byte move
294 would be set up with size(r6) = 14, for one iteration through the
295 big while loop, and a switch of -2 for the last part. */
297 final_switch = 16 - ((bytes / 4) % 16);
298 while_loop = ((bytes / 4) / 16 - 1) * 16;
299 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
300 emit_insn (gen_block_lump_real (func_addr_rtx));
307 /* Prepare operands for a move define_expand; specifically, one of the
308 operands must be in a register. */
311 prepare_move_operands (operands, mode)
313 enum machine_mode mode;
315 /* Copy the source to a register if both operands aren't registers. */
316 if (! reload_in_progress && ! reload_completed
317 && ! register_operand (operands[0], mode)
318 && ! register_operand (operands[1], mode))
319 operands[1] = copy_to_mode_reg (mode, operands[1]);
324 /* Prepare the operands for an scc instruction; make sure that the
325 compare has been done. */
327 prepare_scc_operands (code)
330 rtx t_reg = gen_rtx (REG, SImode, T_REG);
331 enum rtx_code oldcode = code;
332 enum machine_mode mode;
334 /* First need a compare insn. */
338 /* It isn't possible to handle this case. */
355 rtx tmp = sh_compare_op0;
356 sh_compare_op0 = sh_compare_op1;
357 sh_compare_op1 = tmp;
360 mode = GET_MODE (sh_compare_op0);
361 if (mode == VOIDmode)
362 mode = GET_MODE (sh_compare_op1);
364 sh_compare_op0 = force_reg (mode, sh_compare_op0);
365 if (code != EQ && code != NE
366 && (sh_compare_op1 != const0_rtx
367 || code == GTU || code == GEU || code == LTU || code == LEU))
368 sh_compare_op1 = force_reg (mode, sh_compare_op1);
370 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
371 gen_rtx (code, SImode, sh_compare_op0,
377 /* Called from the md file, set up the operands of a compare instruction. */
380 from_compare (operands, code)
384 if (code != EQ && code != NE)
386 enum machine_mode mode = GET_MODE (sh_compare_op0);
387 if (mode == VOIDmode)
388 mode = GET_MODE (sh_compare_op1);
390 /* Force args into regs, since we can't use constants here. */
391 sh_compare_op0 = force_reg (mode, sh_compare_op0);
392 if (sh_compare_op1 != const0_rtx
393 || code == GTU || code == GEU || code == LTU || code == LEU)
394 sh_compare_op1 = force_reg (mode, sh_compare_op1);
396 operands[1] = sh_compare_op0;
397 operands[2] = sh_compare_op1;
400 /* Functions to output assembly code. */
402 /* Return a sequence of instructions to perform DI or DF move.
404 Since the SH cannot move a DI or DF in one instruction, we have
405 to take care when we see overlapping source and dest registers. */
408 output_movedouble (insn, operands, mode)
411 enum machine_mode mode;
413 rtx dst = operands[0];
414 rtx src = operands[1];
416 if (GET_CODE (dst) == MEM
417 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
418 return "mov.l %T1,%0\n\tmov.l %1,%0";
420 if (register_operand (dst, mode)
421 && register_operand (src, mode))
423 if (REGNO (src) == MACH_REG)
424 return "sts mach,%S0\n\tsts macl,%R0";
426 /* When mov.d r1,r2 do r2->r3 then r1->r2;
427 when mov.d r1,r0 do r1->r0 then r2->r1. */
429 if (REGNO (src) + 1 == REGNO (dst))
430 return "mov %T1,%T0\n\tmov %1,%0";
432 return "mov %1,%0\n\tmov %T1,%T0";
434 else if (GET_CODE (src) == CONST_INT)
436 if (INTVAL (src) < 0)
437 output_asm_insn ("mov #-1,%S0", operands);
439 output_asm_insn ("mov #0,%S0", operands);
443 else if (GET_CODE (src) == MEM)
446 int dreg = REGNO (dst);
447 rtx inside = XEXP (src, 0);
449 if (GET_CODE (inside) == REG)
450 ptrreg = REGNO (inside);
451 else if (GET_CODE (inside) == SUBREG)
452 ptrreg = REGNO (SUBREG_REG (inside)) + SUBREG_WORD (inside);
453 else if (GET_CODE (inside) == PLUS)
455 ptrreg = REGNO (XEXP (inside, 0));
456 /* ??? A r0+REG address shouldn't be possible here, because it isn't
457 an offsettable address. Unfortunately, offsettable addresses use
458 QImode to check the offset, and a QImode offsettable address
459 requires r0 for the other operand, which is not currently
460 supported, so we can't use the 'o' constraint.
461 Thus we must check for and handle r0+REG addresses here.
462 We punt for now, since this is likely very rare. */
463 if (GET_CODE (XEXP (inside, 1)) == REG)
466 else if (GET_CODE (inside) == LABEL_REF)
467 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
468 else if (GET_CODE (inside) == POST_INC)
469 return "mov.l %1,%0\n\tmov.l %1,%T0";
473 /* Work out the safe way to copy. Copy into the second half first. */
475 return "mov.l %T1,%T0\n\tmov.l %1,%0";
478 return "mov.l %1,%0\n\tmov.l %T1,%T0";
481 /* Print an instruction which would have gone into a delay slot after
482 another instruction, but couldn't because the other instruction expanded
483 into a sequence where putting the slot insn at the end wouldn't work. */
489 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
491 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
494 /* We can't tell if we need a register as a scratch for the jump
495 until after branch shortening, and then it's too late to allocate a
496 register the 'proper' way. These instruction sequences are rare
497 anyway, so to avoid always using a reg up from our limited set, we'll
498 grab one when we need one on output. */
500 /* ??? Should fix compiler so that using a clobber scratch in jump
501 instructions works, and then this will be unnecessary. */
504 output_far_jump (insn, op)
508 rtx thislab = gen_label_rtx ();
510 /* Output the delay slot insn first if any. */
511 if (dbr_sequence_length ())
512 print_slot (final_sequence);
514 output_asm_insn ("mov.l r13,@-r15", 0);
515 output_asm_insn ("mov.l %O0,r13", &thislab);
516 output_asm_insn ("jmp @r13", 0);
517 output_asm_insn ("mov.l @r15+,r13", 0);
518 output_asm_insn (".align 2", 0);
519 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (thislab));
520 output_asm_insn (".long %O0", &op);
524 /* Local label counter, used for constants in the pool and inside
529 /* Output code for ordinary branches. */
532 output_branch (logic, insn, operands)
539 switch (get_attr_length (insn))
542 /* A branch with an unfilled delay slot. */
544 /* Simple branch in range -252..+258 bytes */
545 return logic ? "bt%. %l0" : "bf%. %l0";
548 /* A branch with an unfilled delay slot. */
550 /* Branch in range -4092..+4098 bytes. */
552 /* The call to print_slot will clobber the operands. */
553 rtx op0 = operands[0];
555 /* If the instruction in the delay slot is annulled (true), then
556 there is no delay slot where we can put it now. The only safe
557 place for it is after the label. */
561 fprintf (asm_out_file, "\tb%c%s\tLF%d\n", logic ? 'f' : 't',
562 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
564 if (! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
565 print_slot (final_sequence);
568 fprintf (asm_out_file, "\tb%c\tLF%d\n", logic ? 'f' : 't', label);
570 output_asm_insn ("bra %l0", &op0);
571 fprintf (asm_out_file, "\tnop\n");
572 fprintf (asm_out_file, "LF%d:\n", label);
575 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
576 print_slot (final_sequence);
581 /* A branch with an unfilled delay slot. */
583 /* Branches a long way away. */
585 /* The call to print_slot will clobber the operands. */
586 rtx op0 = operands[0];
588 /* If the instruction in the delay slot is annulled (true), then
589 there is no delay slot where we can put it now. The only safe
590 place for it is after the label. */
594 fprintf (asm_out_file, "\tb%c%s\tLF%d\n", logic ? 'f' : 't',
595 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
597 if (! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
598 print_slot (final_sequence);
601 fprintf (asm_out_file, "\tb%c\tLF%d\n", logic ? 'f' : 't', label);
603 output_far_jump (insn, op0);
604 fprintf (asm_out_file, "LF%d:\n", label);
607 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
608 print_slot (final_sequence);
615 /* A copy of the option structure defined in toplev.c. */
624 /* Output a single output option string NAME to FILE, without generating
625 lines longer than MAX. */
628 output_option (file, sep, type, name, indent, pos, max)
637 if (strlen (sep) + strlen (type) + strlen (name) + pos > max)
639 fprintf (file, indent);
640 return fprintf (file, "%s%s", type, name);
642 return pos + fprintf (file, "%s%s%s", sep, type, name);
645 /* A copy of the target_switches variable in toplev.c. */
651 } m_options[] = TARGET_SWITCHES;
653 /* Output all options to the assembly language file. */
656 output_options (file, f_options, f_len, W_options, W_len,
657 pos, max, sep, indent, term)
659 struct option *f_options;
660 struct option *W_options;
671 pos = output_option (file, sep, "-O", "", indent, pos, max);
672 if (write_symbols != NO_DEBUG)
673 pos = output_option (file, sep, "-g", "", indent, pos, max);
675 pos = output_option (file, sep, "-p", "", indent, pos, max);
676 if (profile_block_flag)
677 pos = output_option (file, sep, "-a", "", indent, pos, max);
679 for (j = 0; j < f_len; j++)
680 if (*f_options[j].variable == f_options[j].on_value)
681 pos = output_option (file, sep, "-f", f_options[j].string,
684 for (j = 0; j < W_len; j++)
685 if (*W_options[j].variable == W_options[j].on_value)
686 pos = output_option (file, sep, "-W", W_options[j].string,
689 for (j = 0; j < sizeof m_options / sizeof m_options[0]; j++)
690 if (m_options[j].name[0] != '\0'
691 && m_options[j].value > 0
692 && ((m_options[j].value & target_flags)
693 == m_options[j].value))
694 pos = output_option (file, sep, "-m", m_options[j].name,
697 fprintf (file, term);
700 /* Output to FILE the start of the assembler file. */
703 output_file_start (file, f_options, f_len, W_options, W_len)
705 struct option *f_options;
706 struct option *W_options;
711 output_file_directive (file, main_input_filename);
713 /* Switch to the data section so that the coffsem symbol and the
714 gcc2_compiled. symbol aren't in the text section. */
717 pos = fprintf (file, "\n! Hitachi SH cc1 (%s) arguments:", version_string);
718 output_options (file, f_options, f_len, W_options, W_len,
719 pos, 75, " ", "\n! ", "\n\n");
721 if (TARGET_LITTLE_ENDIAN)
722 fprintf (file, "\t.little\n");
725 /* Actual number of instructions used to make a shift by N. */
726 static char ashiftrt_insns[] =
727 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
729 /* Left shift and logical right shift are the same. */
730 static char shift_insns[] =
731 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
733 /* Individual shift amounts needed to get the above length sequences.
734 One bit right shifts clobber the T bit, so when possible, put one bit
735 shifts in the middle of the sequence, so the ends are eligible for
736 branch delay slots. */
737 static short shift_amounts[32][5] = {
738 {0}, {1}, {2}, {2, 1},
739 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
740 {8}, {8, 1}, {8, 2}, {8, 1, 2},
741 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
742 {16}, {16, 1}, {16, 2}, {16, 1, 2},
743 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
744 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
745 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
747 /* This is used in length attributes in sh.md to help compute the length
748 of arbitrary constant shift instructions. */
751 shift_insns_rtx (insn)
754 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
755 int shift_count = INTVAL (XEXP (set_src, 1));
756 enum rtx_code shift_code = GET_CODE (set_src);
761 return ashiftrt_insns[shift_count];
764 return shift_insns[shift_count];
770 /* Return the cost of a shift. */
776 int value = INTVAL (XEXP (x, 1));
778 /* If shift by a non constant, then this will be expensive. */
779 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
783 /* If not an sh3 then we don't even have an instruction for it. */
787 /* Otherwise, return the true cost in instructions. */
788 if (GET_CODE (x) == ASHIFTRT)
790 int cost = ashiftrt_insns[value];
791 /* If SH3, then we put the constant in a reg and use shad. */
792 if (TARGET_SH3 && cost > 3)
797 return shift_insns[value];
800 /* Return the cost of an AND operation. */
808 /* Anding with a register is a single cycle and instruction. */
809 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
812 i = INTVAL (XEXP (x, 1));
813 /* These constants are single cycle extu.[bw] instructions. */
814 if (i == 0xff || i == 0xffff)
816 /* Constants that can be used in an and immediate instruction is a single
817 cycle, but this requires r0, so make it a little more expensive. */
818 if (CONST_OK_FOR_L (i))
820 /* Constants that can be loaded with a mov immediate and an and.
821 This case is probably unnecessary. */
822 if (CONST_OK_FOR_I (i))
824 /* Any other constants requires a 2 cycle pc-relative load plus an and.
825 This case is probably unnecessary. */
829 /* Return the cost of a multiply. */
836 /* We have a mul insn, so we can never take more than the mul and the
837 read of the mac reg, but count more because of the latency and extra
839 if (TARGET_SMALLCODE)
844 /* If we're aiming at small code, then just count the number of
845 insns in a multiply call sequence. */
846 if (TARGET_SMALLCODE)
849 /* Otherwise count all the insns in the routine we'd be calling too. */
853 /* Code to expand a shift. */
856 gen_ashift (type, n, reg)
861 /* Negative values here come from the shift_amounts array. */
874 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
878 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
880 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
883 emit_insn (gen_ashlsi3_k (reg, reg, GEN_INT (n)));
888 /* Output RTL to split a constant shift into its component SH constant
889 shift instructions. */
892 gen_shifty_op (code, operands)
896 int value = INTVAL (operands[2]);
901 if (code == LSHIFTRT)
903 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
904 emit_insn (gen_movt (operands[0]));
907 else if (code == ASHIFT)
909 /* There is a two instruction sequence for 31 bit left shifts,
910 but it requires r0. */
911 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
913 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
914 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
921 /* This can happen when not optimizing. We must output something here
922 to prevent the compiler from aborting in final.c after the try_split
924 emit_insn (gen_nop ());
928 max = shift_insns[value];
929 for (i = 0; i < max; i++)
930 gen_ashift (code, shift_amounts[value][i], operands[0]);
933 /* Output RTL for an arithmetic right shift. */
935 /* ??? Rewrite to use super-optimizer sequences. */
938 expand_ashiftrt (operands)
948 if (GET_CODE (operands[2]) != CONST_INT)
950 rtx count = copy_to_mode_reg (SImode, operands[2]);
951 emit_insn (gen_negsi2 (count, count));
952 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
955 else if (ashiftrt_insns[INTVAL (operands[2])] > 3)
957 rtx count = force_reg (SImode, GEN_INT (- INTVAL (operands[2])));
958 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
962 if (GET_CODE (operands[2]) != CONST_INT)
965 value = INTVAL (operands[2]);
969 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
972 else if (value >= 16 && value <= 19)
974 wrk = gen_reg_rtx (SImode);
975 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
978 gen_ashift (ASHIFTRT, 1, wrk);
979 emit_move_insn (operands[0], wrk);
982 /* Expand a short sequence inline, longer call a magic routine. */
985 wrk = gen_reg_rtx (SImode);
986 emit_move_insn (wrk, operands[1]);
988 gen_ashift (ASHIFTRT, 1, wrk);
989 emit_move_insn (operands[0], wrk);
993 wrk = gen_reg_rtx (Pmode);
995 /* Load the value into an arg reg and call a helper. */
996 emit_move_insn (gen_rtx (REG, SImode, 4), operands[1]);
997 sprintf (func, "__ashiftrt_r4_%d", value);
998 func_name = get_identifier (func);
999 emit_move_insn (wrk, gen_rtx (SYMBOL_REF, Pmode,
1000 IDENTIFIER_POINTER (func_name)));
1001 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
1002 emit_move_insn (operands[0], gen_rtx (REG, SImode, 4));
1006 /* The SH cannot load a large constant into a register, constants have to
1007 come from a pc relative load. The reference of a pc relative load
1008 instruction must be less than 1k infront of the instruction. This
1009 means that we often have to dump a constant inside a function, and
1010 generate code to branch around it.
1012 It is important to minimize this, since the branches will slow things
1013 down and make things bigger.
1015 Worst case code looks like:
1033 We fix this by performing a scan before scheduling, which notices which
1034 instructions need to have their operands fetched from the constant table
1035 and builds the table.
1039 scan, find an instruction which needs a pcrel move. Look forward, find the
1040 last barrier which is within MAX_COUNT bytes of the requirement.
1041 If there isn't one, make one. Process all the instructions between
1042 the find and the barrier.
1044 In the above example, we can tell that L3 is within 1k of L1, so
1045 the first move can be shrunk from the 3 insn+constant sequence into
1046 just 1 insn, and the constant moved to L3 to make:
1057 Then the second move becomes the target for the shortening process. */
1061 rtx value; /* Value in table. */
1062 rtx label; /* Label of value. */
1063 enum machine_mode mode; /* Mode of value. */
1066 /* The maximum number of constants that can fit into one pool, since
1067 the pc relative range is 0...1020 bytes and constants are at least 4
1070 #define MAX_POOL_SIZE (1020/4)
1071 static pool_node pool_vector[MAX_POOL_SIZE];
1072 static int pool_size;
1074 /* ??? If we need a constant in HImode which is the truncated value of a
1075 constant we need in SImode, we could combine the two entries thus saving
1076 two bytes. Is this common enough to be worth the effort of implementing
1079 /* ??? This stuff should be done at the same time that we shorten branches.
1080 As it is now, we must assume that all branches are the maximum size, and
1081 this causes us to almost always output constant pools sooner than
1084 /* Add a constant to the pool and return its label. */
1087 add_constant (x, mode)
1089 enum machine_mode mode;
1094 /* First see if we've already got it. */
1095 for (i = 0; i < pool_size; i++)
1097 if (x->code == pool_vector[i].value->code
1098 && mode == pool_vector[i].mode)
1100 if (x->code == CODE_LABEL)
1102 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
1105 if (rtx_equal_p (x, pool_vector[i].value))
1106 return pool_vector[i].label;
1110 /* Need a new one. */
1111 pool_vector[pool_size].value = x;
1112 lab = gen_label_rtx ();
1113 pool_vector[pool_size].mode = mode;
1114 pool_vector[pool_size].label = lab;
1119 /* Output the literal table. */
1128 /* Do two passes, first time dump out the HI sized constants. */
1130 for (i = 0; i < pool_size; i++)
1132 pool_node *p = &pool_vector[i];
1134 if (p->mode == HImode)
1138 scan = emit_insn_after (gen_align_2 (), scan);
1141 scan = emit_label_after (p->label, scan);
1142 scan = emit_insn_after (gen_consttable_2 (p->value), scan);
1148 for (i = 0; i < pool_size; i++)
1150 pool_node *p = &pool_vector[i];
1160 scan = emit_label_after (gen_label_rtx (), scan);
1161 scan = emit_insn_after (gen_align_4 (), scan);
1163 scan = emit_label_after (p->label, scan);
1164 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
1170 scan = emit_label_after (gen_label_rtx (), scan);
1171 scan = emit_insn_after (gen_align_4 (), scan);
1173 scan = emit_label_after (p->label, scan);
1174 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
1182 scan = emit_insn_after (gen_consttable_end (), scan);
1183 scan = emit_barrier_after (scan);
1187 /* Return non-zero if constant would be an ok source for a
1188 mov.w instead of a mov.l. */
1194 return (GET_CODE (src) == CONST_INT
1195 && INTVAL (src) >= -32768
1196 && INTVAL (src) <= 32767);
1199 /* Non-zero if the insn is a move instruction which needs to be fixed. */
1201 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
1202 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
1203 need to fix it if the input value is CONST_OK_FOR_I. */
1209 if (GET_CODE (insn) == INSN
1210 && GET_CODE (PATTERN (insn)) == SET
1211 /* We can load any 8 bit value if we don't care what the high
1212 order bits end up as. */
1213 && GET_MODE (SET_DEST (PATTERN (insn))) != QImode
1214 && CONSTANT_P (SET_SRC (PATTERN (insn)))
1215 && (GET_CODE (SET_SRC (PATTERN (insn))) != CONST_INT
1216 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (PATTERN (insn))))))
1222 /* Find the last barrier from insn FROM which is close enough to hold the
1223 constant pool. If we can't find one, then create one near the end of
1226 /* ??? It would be good to put constant pool tables between a case jump and
1227 the jump table. This fails for two reasons. First, there is no
1228 barrier after the case jump. This is a bug in the casesi pattern.
1229 Second, inserting the table here may break the mova instruction that
1230 loads the jump table address, by moving the jump table too far away.
1231 We fix that problem by never outputting the constant pool between a mova
1242 rtx found_barrier = 0;
1247 /* For HImode: range is 510, add 4 because pc counts from address of
1248 second instruction after this one, subtract 2 for the jump instruction
1249 that we may need to emit before the table. This gives 512.
1250 For SImode: range is 1020, add 4 because pc counts from address of
1251 second instruction after this one, subtract 2 in case pc is 2 byte
1252 aligned, subtract 2 for the jump instruction that we may need to emit
1253 before the table. This gives 1020. */
1255 /* If not optimizing, then it is possible that the jump instruction we add
1256 won't be shortened, and thus will have a length of 14 instead of 2.
1257 We must adjust the limits downwards to account for this, giving a limit
1258 of 1008 for SImode and 500 for HImode. */
1271 while (from && count_si < si_limit && count_hi < hi_limit)
1273 int inc = get_attr_length (from);
1275 if (GET_CODE (from) == BARRIER)
1276 found_barrier = from;
1278 if (broken_move (from))
1280 rtx pat = PATTERN (from);
1281 rtx src = SET_SRC (pat);
1282 rtx dst = SET_DEST (pat);
1283 enum machine_mode mode = GET_MODE (dst);
1285 /* We must explicitly check the mode, because sometimes the
1286 front end will generate code to load unsigned constants into
1287 HImode targets without properly sign extending them. */
1288 if (mode == HImode || (mode == SImode && hi_const (src)))
1291 /* We put the short constants before the long constants, so
1292 we must count the length of short constants in the range
1293 for the long constants. */
1294 /* ??? This isn't optimal, but is easy to do. */
1302 if (GET_CODE (from) == INSN
1303 && GET_CODE (PATTERN (from)) == SET
1304 && GET_CODE (SET_SRC (PATTERN (from))) == UNSPEC
1305 && XINT (SET_SRC (PATTERN (from)), 1) == 1)
1307 else if (GET_CODE (from) == JUMP_INSN
1308 && (GET_CODE (PATTERN (from)) == ADDR_VEC
1309 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
1316 from = NEXT_INSN (from);
1319 /* Insert the constant pool table before the mova instruction, to prevent
1320 the mova label reference from going out of range. */
1324 if (! found_barrier)
1326 /* We didn't find a barrier in time to dump our stuff,
1327 so we'll make one. */
1328 rtx label = gen_label_rtx ();
1330 /* If we exceeded the range, then we must back up over the last
1331 instruction we looked at. Otherwise, we just need to undo the
1332 NEXT_INSN at the end of the loop. */
1333 if (count_hi > hi_limit || count_si > si_limit)
1334 from = PREV_INSN (PREV_INSN (from));
1336 from = PREV_INSN (from);
1338 /* Walk back to be just before any jump or label.
1339 Putting it before a label reduces the number of times the branch
1340 around the constant pool table will be hit. Putting it before
1341 a jump makes it more likely that the bra delay slot will be
1343 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
1344 || GET_CODE (from) == CODE_LABEL)
1345 from = PREV_INSN (from);
1347 from = emit_jump_insn_after (gen_jump (label), from);
1348 JUMP_LABEL (from) = label;
1349 LABEL_NUSES (label) = 1;
1350 found_barrier = emit_barrier_after (from);
1351 emit_label_after (label, found_barrier);
1354 return found_barrier;
1357 /* See if the only way in which INSN uses REG is by calling it, or by
1358 setting it while calling it. Set *SET to a SET rtx if the register
1362 noncall_uses_reg (reg, insn, set)
1371 if (GET_CODE (insn) != CALL_INSN)
1373 /* We don't use rtx_equal_p because we don't care if the mode is
1375 pattern = single_set (insn);
1377 && GET_CODE (SET_DEST (pattern)) == REG
1378 && REGNO (reg) == REGNO (SET_DEST (pattern)))
1387 pattern = PATTERN (insn);
1389 if (GET_CODE (pattern) == PARALLEL)
1393 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
1394 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
1396 pattern = XVECEXP (pattern, 0, 0);
1399 if (GET_CODE (pattern) == SET)
1401 if (reg_mentioned_p (reg, SET_DEST (pattern)))
1403 /* We don't use rtx_equal_p, because we don't care if the
1404 mode is different. */
1405 if (GET_CODE (SET_DEST (pattern)) != REG
1406 || REGNO (reg) != REGNO (SET_DEST (pattern)))
1412 pattern = SET_SRC (pattern);
1415 if (GET_CODE (pattern) != CALL
1416 || GET_CODE (XEXP (pattern, 0)) != MEM
1417 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
1423 /* Exported to toplev.c.
1425 Do a final pass over the function, just before delayed branch
1429 machine_dependent_reorg (first)
1434 /* If relaxing, generate pseudo-ops to associate function calls with
1435 the symbols they call. It does no harm to not generate these
1436 pseudo-ops. However, when we can generate them, it enables to
1437 linker to potentially relax the jsr to a bsr, and eliminate the
1438 register load and, possibly, the constant pool entry. */
1442 /* Remove all REG_LABEL notes. We want to use them for our own
1443 purposes. This works because none of the remaining passes
1444 need to look at them.
1446 ??? But it may break in the future. We should use a machine
1447 dependent REG_NOTE, or some other approach entirely. */
1448 for (insn = first; insn; insn = NEXT_INSN (insn))
1450 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1454 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
1455 remove_note (insn, note);
1459 for (insn = first; insn; insn = NEXT_INSN (insn))
1461 rtx pattern, reg, link, set, scan, dies, label;
1462 int rescan = 0, foundinsn = 0;
1464 if (GET_CODE (insn) != CALL_INSN)
1467 pattern = PATTERN (insn);
1469 if (GET_CODE (pattern) == PARALLEL)
1470 pattern = XVECEXP (pattern, 0, 0);
1471 if (GET_CODE (pattern) == SET)
1472 pattern = SET_SRC (pattern);
1474 if (GET_CODE (pattern) != CALL
1475 || GET_CODE (XEXP (pattern, 0)) != MEM)
1478 reg = XEXP (XEXP (pattern, 0), 0);
1479 if (GET_CODE (reg) != REG)
1482 /* This is a function call via REG. If the only uses of REG
1483 between the time that it is set and the time that it dies
1484 are in function calls, then we can associate all the
1485 function calls with the setting of REG. */
1487 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1489 set = single_set (XEXP (link, 0));
1490 if (set && rtx_equal_p (reg, SET_DEST (set)))
1492 link = XEXP (link, 0);
1499 /* ??? Sometimes global register allocation will have
1500 deleted the insn pointed to by LOG_LINKS. Try
1501 scanning backward to find where the register is set. */
1502 for (scan = PREV_INSN (insn);
1503 scan && GET_CODE (scan) != CODE_LABEL;
1504 scan = PREV_INSN (scan))
1506 if (GET_RTX_CLASS (GET_CODE (scan)) != 'i')
1509 if (! reg_mentioned_p (reg, scan))
1512 if (noncall_uses_reg (reg, scan, &set))
1526 /* The register is set at LINK. */
1528 /* We can only optimize the function call if the register is
1529 being set to a symbol. In theory, we could sometimes
1530 optimize calls to a constant location, but the assembler
1531 and linker do not support that at present. */
1532 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
1533 && GET_CODE (SET_SRC (set)) != LABEL_REF)
1536 /* Scan forward from LINK to the place where REG dies, and
1537 make sure that the only insns which use REG are
1538 themselves function calls. */
1541 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
1545 if (GET_RTX_CLASS (GET_CODE (scan)) != 'i')
1548 /* Don't try to trace forward past a JUMP. To optimize
1549 safely, we would have to check that all the
1550 instructions at the jump destination did not use REG.
1551 It should be safe to trace past a CODE_LABEL, because
1552 we will only find the setting insn in LOG_LINKS if it
1553 is in the same basic block (so probably we should
1554 never find a CODE_LABEL anyhow). */
1556 if (GET_CODE (insn) == JUMP_INSN)
1559 if (! reg_mentioned_p (reg, scan))
1562 if (noncall_uses_reg (reg, scan, &scanset))
1568 if (scan != insn && GET_CODE (scan) == CALL_INSN)
1570 /* There is a function call to this register other
1571 than the one we are checking. If we optimize
1572 this call, we need to rescan again below. */
1576 /* ??? We shouldn't have to worry about SCANSET here.
1577 We should just be able to check for a REG_DEAD note
1578 on a function call. However, the REG_DEAD notes are
1579 apparently not dependable around libcalls; c-torture
1580 execute/920501-2 is a test case. If SCANSET is set,
1581 then this insn sets the register, so it must have
1582 died earlier. Unfortunately, this will only handle
1583 the cases in which the register is, in fact, set in a
1586 /* ??? We shouldn't have to use FOUNDINSN here.
1587 However, the LOG_LINKS fields are apparently not
1588 entirely reliable around libcalls;
1589 newlib/libm/math/e_pow.c is a test case. Sometimes
1590 an insn will appear in LOG_LINKS even though it is
1591 not the most recent insn which sets the register. */
1595 || find_reg_note (scan, REG_DEAD, reg)))
1604 /* Either there was a branch, or some insn used REG
1605 other than as a function call address. */
1609 /* Create a code label, and put it in a REG_LABEL note on
1610 the insn which sets the register, and on each call insn
1611 which uses the register. In final_prescan_insn we look
1612 for the REG_LABEL notes, and output the appropriate label
1615 label = gen_label_rtx ();
1616 REG_NOTES (link) = gen_rtx (EXPR_LIST, REG_LABEL, label,
1618 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_LABEL, label,
1625 scan = NEXT_INSN (scan);
1627 && GET_CODE (scan) == CALL_INSN
1628 && reg_mentioned_p (reg, scan))
1629 REG_NOTES (scan) = gen_rtx (EXPR_LIST, REG_LABEL,
1630 label, REG_NOTES (scan));
1632 while (scan != dies);
1637 /* Scan the function looking for move instructions which have to be
1638 changed to pc-relative loads and insert the literal tables. */
1640 for (insn = first; insn; insn = NEXT_INSN (insn))
1642 if (broken_move (insn))
1645 /* Scan ahead looking for a barrier to stick the constant table
1647 rtx barrier = find_barrier (insn);
1649 /* Now find all the moves between the points and modify them. */
1650 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
1652 if (broken_move (scan))
1654 rtx pat = PATTERN (scan);
1655 rtx src = SET_SRC (pat);
1656 rtx dst = SET_DEST (pat);
1657 enum machine_mode mode = GET_MODE (dst);
1662 if (mode == SImode && hi_const (src))
1667 while (GET_CODE (dst) == SUBREG)
1669 offset += SUBREG_WORD (dst);
1670 dst = SUBREG_REG (dst);
1672 dst = gen_rtx (REG, HImode, REGNO (dst) + offset);
1675 lab = add_constant (src, mode);
1676 newsrc = gen_rtx (MEM, mode,
1677 gen_rtx (LABEL_REF, VOIDmode, lab));
1678 RTX_UNCHANGING_P (newsrc) = 1;
1679 newinsn = emit_insn_after (gen_rtx (SET, VOIDmode,
1680 dst, newsrc), scan);
1681 REG_NOTES (newinsn) = REG_NOTES (scan);
1682 REG_NOTES (scan) = NULL_RTX;
1683 /* If not optimizing, then delete_insn doesn't remove the
1684 insn from the chain, and hence is not useful. We
1685 convert the instruction to a NOTE in that case. */
1690 PUT_CODE (scan, NOTE);
1691 NOTE_LINE_NUMBER (scan) = NOTE_INSN_DELETED;
1692 NOTE_SOURCE_FILE (insn) = 0;
1697 dump_table (barrier);
1702 /* Dump out instruction addresses, which is useful for debugging the
1703 constant pool table stuff.
1705 If relaxing, output the label and pseudo-ops used to link together
1706 calls and the instruction which set the registers. */
1708 /* ??? This is unnecessary, and probably should be deleted. This makes
1709 the insn_addresses declaration above unnecessary. */
1711 /* ??? The addresses printed by this routine for insns are nonsense for
1712 insns which are inside of a sequence where none of the inner insns have
1713 variable length. This is because the second pass of shorten_branches
1714 does not bother to update them. */
1717 final_prescan_insn (insn, opvec, noperands)
1722 if (TARGET_DUMPISIZE)
1723 fprintf (asm_out_file, "\n! at %04x\n", insn_addresses[INSN_UID (insn)]);
1729 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
1734 pattern = PATTERN (insn);
1735 if (GET_CODE (pattern) == PARALLEL)
1736 pattern = XVECEXP (pattern, 0, 0);
1737 if (GET_CODE (pattern) == CALL
1738 || (GET_CODE (pattern) == SET
1739 && GET_CODE (SET_SRC (pattern)) == CALL))
1740 fprintf (asm_out_file, "\t.uses L%d\n",
1741 CODE_LABEL_NUMBER (XEXP (note, 0)));
1742 else if (GET_CODE (pattern) == SET)
1743 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1744 CODE_LABEL_NUMBER (XEXP (note, 0)));
1751 /* Dump out any constants accumulated in the final pass. These will
1752 will only be labels. */
1755 output_jump_label_table ()
1761 fprintf (asm_out_file, "\t.align 2\n");
1762 for (i = 0; i < pool_size; i++)
1764 pool_node *p = &pool_vector[i];
1766 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1767 CODE_LABEL_NUMBER (p->label));
1768 output_asm_insn (".long %O0", &p->value);
1776 /* A full frame looks like:
1780 [ if current_function_anonymous_args
1793 local-0 <- fp points here. */
1795 /* Number of bytes pushed for anonymous args, used to pass information
1796 between expand_prologue and expand_epilogue. */
1798 static int extra_push;
1800 /* Adjust the stack and return the number of bytes taken to do it. */
1803 output_stack_adjust (size, reg)
1809 rtx val = GEN_INT (size);
1812 if (! CONST_OK_FOR_I (size))
1814 rtx reg = gen_rtx (REG, SImode, 3);
1815 emit_insn (gen_movsi (reg, val));
1819 insn = gen_addsi3 (reg, reg, val);
1824 /* Output RTL to push register RN onto the stack. */
1831 x = emit_insn (gen_push (gen_rtx (REG, SImode, rn)));
1832 REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
1833 gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
1836 /* Output RTL to pop register RN from the stack. */
1843 x = emit_insn (gen_pop (gen_rtx (REG, SImode, rn)));
1844 REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
1845 gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
1848 /* Generate code to push the regs specified in the mask, and return
1849 the number of bytes the insns take. */
1857 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1858 if (mask & (1 << i))
1862 /* Work out the registers which need to be saved, both as a mask and a
1865 If doing a pragma interrupt function, then push all regs used by the
1866 function, and if we call another function (we can tell by looking at PR),
1867 make sure that all the regs it clobbers are safe too. */
1870 calc_live_regs (count_ptr)
1874 int live_regs_mask = 0;
1877 for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
1879 if (pragma_interrupt && ! pragma_trapa)
1881 /* Normally, we must save all the regs ever live.
1882 If pragma_nosave_low_regs, then don't save any of the
1883 registers which are banked on the SH3. */
1884 if ((regs_ever_live[reg]
1885 || (call_used_regs[reg] && regs_ever_live[PR_REG]))
1886 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
1887 && reg != T_REG && reg != GBR_REG
1888 && ! (sh_cpu == CPU_SH3 && pragma_nosave_low_regs && reg < 8))
1890 live_regs_mask |= 1 << reg;
1896 /* Only push those regs which are used and need to be saved. */
1897 if (regs_ever_live[reg] && ! call_used_regs[reg])
1899 live_regs_mask |= (1 << reg);
1906 return live_regs_mask;
1909 /* Code to generate prologue and epilogue sequences */
1912 sh_expand_prologue ()
1916 live_regs_mask = calc_live_regs (&d);
1918 /* We have pretend args if we had an object sent partially in registers
1919 and partially on the stack, e.g. a large structure. */
1920 output_stack_adjust (-current_function_pretend_args_size, stack_pointer_rtx);
1924 /* This is set by SETUP_VARARGS to indicate that this is a varargs
1925 routine. Clear it here so that the next function isn't affected. */
1926 if (current_function_anonymous_args)
1928 current_function_anonymous_args = 0;
1930 /* Push arg regs as if they'd been provided by caller in stack. */
1931 for (i = 0; i < NPARM_REGS; i++)
1933 int rn = NPARM_REGS + FIRST_PARM_REG - i - 1;
1934 if (i > (NPARM_REGS - current_function_args_info
1935 - current_function_varargs))
1941 push_regs (live_regs_mask);
1942 output_stack_adjust (-get_frame_size (), stack_pointer_rtx);
1944 if (frame_pointer_needed)
1945 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1949 sh_expand_epilogue ()
1954 live_regs_mask = calc_live_regs (&d);
1956 if (frame_pointer_needed)
1958 /* We deliberately make the add dependent on the frame_pointer,
1959 to ensure that instruction scheduling won't move the stack pointer
1960 adjust before instructions reading from the frame. This can fail
1961 if there is an interrupt which then writes to the stack. */
1962 output_stack_adjust (get_frame_size (), frame_pointer_rtx);
1963 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
1966 output_stack_adjust (get_frame_size (), stack_pointer_rtx);
1968 /* Pop all the registers. */
1970 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1972 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
1973 if (live_regs_mask & (1 << j))
1977 output_stack_adjust (extra_push + current_function_pretend_args_size,
1981 /* Clear variables at function end. */
1984 function_epilogue (stream, size)
1988 pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
1991 /* Define the offset between two registers, one to be eliminated, and
1992 the other its replacement, at the start of a routine. */
1995 initial_elimination_offset (from, to)
2000 int total_saved_regs_space;
2001 int total_auto_space = get_frame_size ();
2003 calc_live_regs (®s_saved);
2004 total_saved_regs_space = (regs_saved) * 4;
2006 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
2007 return total_saved_regs_space + total_auto_space;
2009 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2010 return total_saved_regs_space + total_auto_space;
2012 /* Initial gap between fp and sp is 0. */
2013 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2019 /* Handle machine specific pragmas to be semi-compatible with Hitachi
2023 handle_pragma (file, c)
2030 while (c == ' ' || c == '\t')
2033 if (c != '\n' & c != EOF)
2035 while (psize < sizeof (pbuf) - 1
2036 && (isalpha (c) || c == '_'))
2043 if (strcmp (pbuf, "interrupt") == 0)
2044 pragma_interrupt = 1;
2045 else if (strcmp (pbuf, "trapa") == 0)
2046 pragma_interrupt = pragma_trapa = 1;
2047 else if (strcmp (pbuf, "nosave_low_regs") == 0)
2048 pragma_nosave_low_regs = 1;
2050 while (c != '\n' && c != EOF)
2057 /* Predicates used by the templates. */
2059 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
2060 Used only in general_movsrc_operand. */
2063 system_reg_operand (op, mode)
2065 enum machine_mode mode;
2077 /* Returns 1 if OP can be source of a simple move operation.
2078 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
2079 invalid as are subregs of system registers. */
2082 general_movsrc_operand (op, mode)
2084 enum machine_mode mode;
2086 if (GET_CODE (op) == MEM)
2088 rtx inside = XEXP (op, 0);
2089 if (GET_CODE (inside) == CONST)
2090 inside = XEXP (inside, 0);
2092 if (GET_CODE (inside) == LABEL_REF)
2095 if (GET_CODE (inside) == PLUS
2096 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
2097 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
2100 /* Only post inc allowed. */
2101 if (GET_CODE (inside) == PRE_DEC)
2105 if ((mode == QImode || mode == HImode)
2106 && (GET_CODE (op) == SUBREG
2107 && GET_CODE (XEXP (op, 0)) == REG
2108 && system_reg_operand (XEXP (op, 0), mode)))
2111 return general_operand (op, mode);
2114 /* Returns 1 if OP can be a destination of a move.
2115 Same as general_operand, but no preinc allowed. */
2118 general_movdst_operand (op, mode)
2120 enum machine_mode mode;
2122 /* Only pre dec allowed. */
2123 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
2126 return general_operand (op, mode);
2129 /* Returns 1 if OP is a normal arithmetic register. */
2132 arith_reg_operand (op, mode)
2134 enum machine_mode mode;
2136 if (register_operand (op, mode))
2138 if (GET_CODE (op) == REG)
2139 return (REGNO (op) != T_REG
2140 && REGNO (op) != PR_REG
2141 && REGNO (op) != MACH_REG
2142 && REGNO (op) != MACL_REG);
2148 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
2151 arith_operand (op, mode)
2153 enum machine_mode mode;
2155 if (arith_reg_operand (op, mode))
2158 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
2164 /* Returns 1 if OP is a valid source operand for a compare insn. */
2167 arith_reg_or_0_operand (op, mode)
2169 enum machine_mode mode;
2171 if (arith_reg_operand (op, mode))
2174 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_N (INTVAL (op)))
2180 /* Returns 1 if OP is a valid source operand for a logical operation. */
2183 logical_operand (op, mode)
2185 enum machine_mode mode;
2187 if (arith_reg_operand (op, mode))
2190 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
2196 /* Determine where to put an argument to a function.
2197 Value is zero to push the argument on the stack,
2198 or a hard register in which to store the argument.
2200 MODE is the argument's machine mode.
2201 TYPE is the data type of the argument (as a tree).
2202 This is null for libcalls where that information may
2204 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2205 the preceding args and about the function being called.
2206 NAMED is nonzero if this argument is a named parameter
2207 (otherwise it is an extra parameter matching an ellipsis). */
2210 sh_function_arg (cum, mode, type, named)
2211 CUMULATIVE_ARGS cum;
2212 enum machine_mode mode;
2218 int rr = (ROUND_REG (cum, mode));
2220 if (rr < NPARM_REGS)
2221 return ((type == 0 || ! TREE_ADDRESSABLE (type))
2222 ? gen_rtx (REG, mode, FIRST_PARM_REG + rr) : 0);
2227 /* For an arg passed partly in registers and partly in memory,
2228 this is the number of registers used.
2229 For args passed entirely in registers or entirely in memory, zero.
2230 Any arg that starts in the first 4 regs but won't entirely fit in them
2231 needs partial registers on the SH. */
2234 sh_function_arg_partial_nregs (cum, mode, type, named)
2235 CUMULATIVE_ARGS cum;
2236 enum machine_mode mode;
2240 if (cum < NPARM_REGS)
2242 if ((type == 0 || ! TREE_ADDRESSABLE (type))
2243 && (cum + (mode == BLKmode
2244 ? ROUND_ADVANCE (int_size_in_bytes (type))
2245 : ROUND_ADVANCE (GET_MODE_SIZE (mode))) - NPARM_REGS > 0))
2246 return NPARM_REGS - cum;
2251 /* Return non-zero if REG is not used after INSN.
2252 We assume REG is a reload reg, and therefore does
2253 not live past labels or calls or jumps. */
2255 reg_unused_after (reg, insn)
2262 /* If the reg is set by this instruction, then it is safe for our
2263 case. Disregard the case where this is a store to memory, since
2264 we are checking a register used in the store address. */
2265 set = single_set (insn);
2266 if (set && GET_CODE (SET_DEST (set)) != MEM
2267 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2270 while (insn = NEXT_INSN (insn))
2272 code = GET_CODE (insn);
2275 /* If this is a label that existed before reload, then the register
2276 if dead here. However, if this is a label added by reorg, then
2277 the register may still be live here. We can't tell the difference,
2278 so we just ignore labels completely. */
2279 if (code == CODE_LABEL)
2284 /* If this is a sequence, we must handle them all at once.
2285 We could have for instance a call that sets the target register,
2286 and a insn in a delay slot that uses the register. In this case,
2287 we must return 0. */
2288 if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
2293 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
2295 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
2296 rtx set = single_set (this_insn);
2298 if (GET_CODE (this_insn) == CALL_INSN)
2301 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
2303 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2305 if (GET_CODE (SET_DEST (set)) != MEM)
2311 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
2317 else if (GET_RTX_CLASS (code) == 'i')
2319 rtx set = single_set (insn);
2321 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
2323 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2324 return GET_CODE (SET_DEST (set)) != MEM;
2325 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2329 if (code == CALL_INSN && call_used_regs[REGNO (reg)])