1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; f -- Floating point registers.
31 ;; t -- Access registers 36 and 37.
32 ;; G -- Const double zero operand
33 ;; I -- An 8-bit constant (0..255).
34 ;; J -- A 12-bit constant (0..4095).
35 ;; K -- A 16-bit constant (-32768..32767).
36 ;; L -- Value appropriate as displacement.
37 ;; (0..4095) for short displacement
38 ;; (-524288..524287) for long displacement
39 ;; M -- Constant integer with a value of 0x7fffffff.
40 ;; N -- Multiple letter constraint followed by 4 parameter letters.
41 ;; 0..9,x: number of the part counting from most to least significant
42 ;; H,Q: mode of the part
43 ;; D,S,H: mode of the containing operand
44 ;; 0,F: value of the other parts (F - all bits set)
46 ;; The constraint matches if the specified part of a constant
47 ;; has a value different from its other parts. If the letter x
48 ;; is specified instead of a part number, the constraint matches
49 ;; if there is any single part with non-default value.
50 ;; O -- Multiple letter constraint followed by 1 parameter.
51 ;; s: Signed extended immediate value (-2G .. 2G-1).
52 ;; p: Positive extended immediate value (0 .. 4G-1).
53 ;; n: Negative extended immediate value (-4G .. -1).
54 ;; These constraints do not accept any operand if the machine does
55 ;; not provide the extended-immediate facility.
56 ;; P -- Any integer constant that can be loaded without literal pool.
57 ;; Q -- Memory reference without index register and with short displacement.
58 ;; R -- Memory reference with index register and short displacement.
59 ;; S -- Memory reference without index register but with long displacement.
60 ;; T -- Memory reference with index register and long displacement.
61 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
62 ;; Offsettable memory reference of type specified by second letter.
63 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
64 ;; Memory reference of the type specified by second letter that
65 ;; does *not* refer to a literal pool entry.
66 ;; U -- Pointer with short displacement.
67 ;; W -- Pointer with long displacement.
68 ;; Y -- Shift count operand.
70 ;; Special formats used for outputting 390 instructions.
72 ;; %C: print opcode suffix for branch condition.
73 ;; %D: print opcode suffix for inverse branch condition.
74 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
75 ;; %G: print the size of the operand in bytes.
76 ;; %O: print only the displacement of a memory reference.
77 ;; %R: print only the base register of a memory reference.
78 ;; %S: print S-type memory reference (base+displacement).
79 ;; %N: print the second word of a DImode operand.
80 ;; %M: print the second word of a TImode operand.
81 ;; %Y: print shift count operand.
83 ;; %b: print integer X as if it's an unsigned byte.
84 ;; %x: print integer X as if it's an unsigned halfword.
85 ;; %h: print integer X as if it's a signed halfword.
86 ;; %i: print the first nonzero HImode part of X.
87 ;; %j: print the first HImode part unequal to -1 of X.
88 ;; %k: print the first nonzero SImode part of X.
89 ;; %m: print the first SImode part unequal to -1 of X.
90 ;; %o: print integer X as if it's an unsigned 32bit word.
92 ;; We have a special constraint for pattern matching.
94 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
107 ; GOT/PLT and lt-relative accesses
108 (UNSPEC_LTREL_OFFSET 100)
109 (UNSPEC_LTREL_BASE 101)
117 (UNSPEC_RELOAD_BASE 210)
118 (UNSPEC_MAIN_BASE 211)
123 ; TLS relocation specifiers
128 (UNSPEC_GOTNTPOFF 504)
129 (UNSPEC_INDNTPOFF 505)
132 (UNSPEC_TLSLDM_NTPOFF 511)
133 (UNSPEC_TLS_LOAD 512)
139 ; Stack Smashing Protector
145 ;; UNSPEC_VOLATILE usage
153 (UNSPECV_TPF_PROLOGUE 20)
154 (UNSPECV_TPF_EPILOGUE 21)
158 (UNSPECV_POOL_SECTION 201)
159 (UNSPECV_POOL_ALIGN 202)
160 (UNSPECV_POOL_ENTRY 203)
161 (UNSPECV_MAIN_POOL 300)
177 ; Sibling call register.
179 ; Literal pool base register.
181 ; Return address register.
183 ; Condition code register.
185 ; Thread local storage pointer register.
190 ;; Instruction operand type as used in the Principles of Operation.
191 ;; Used to determine defaults for length and other attribute values.
193 (define_attr "op_type"
194 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
197 ;; Instruction type attribute used for scheduling.
199 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
200 cs,vs,store,sem,idiv,
201 imulhi,imulsi,imuldi,
202 branch,jsr,fsimpdf,fsimpsf,
203 floaddf,floadsf,fstoredf,fstoresf,
204 fmuldf,fmulsf,fdivdf,fdivsf,
205 ftoi,itof,fsqrtdf,fsqrtsf,
207 (cond [(eq_attr "op_type" "NN") (const_string "other")
208 (eq_attr "op_type" "SS") (const_string "cs")]
209 (const_string "integer")))
211 ;; Another attribute used for scheduling purposes:
212 ;; agen: Instruction uses the address generation unit
213 ;; reg: Instruction does not use the agen unit
215 (define_attr "atype" "agen,reg"
216 (cond [(eq_attr "op_type" "E") (const_string "reg")
217 (eq_attr "op_type" "RR") (const_string "reg")
218 (eq_attr "op_type" "RX") (const_string "agen")
219 (eq_attr "op_type" "RI") (const_string "reg")
220 (eq_attr "op_type" "RRE") (const_string "reg")
221 (eq_attr "op_type" "RS") (const_string "agen")
222 (eq_attr "op_type" "RSI") (const_string "agen")
223 (eq_attr "op_type" "S") (const_string "agen")
224 (eq_attr "op_type" "SI") (const_string "agen")
225 (eq_attr "op_type" "SS") (const_string "agen")
226 (eq_attr "op_type" "SSE") (const_string "agen")
227 (eq_attr "op_type" "RXE") (const_string "agen")
228 (eq_attr "op_type" "RSE") (const_string "agen")
229 (eq_attr "op_type" "RIL") (const_string "agen")
230 (eq_attr "op_type" "RXY") (const_string "agen")
231 (eq_attr "op_type" "RSY") (const_string "agen")
232 (eq_attr "op_type" "SIY") (const_string "agen")]
233 (const_string "agen")))
237 (define_attr "length" ""
238 (cond [(eq_attr "op_type" "E") (const_int 2)
239 (eq_attr "op_type" "RR") (const_int 2)
240 (eq_attr "op_type" "RX") (const_int 4)
241 (eq_attr "op_type" "RI") (const_int 4)
242 (eq_attr "op_type" "RRE") (const_int 4)
243 (eq_attr "op_type" "RS") (const_int 4)
244 (eq_attr "op_type" "RSI") (const_int 4)
245 (eq_attr "op_type" "S") (const_int 4)
246 (eq_attr "op_type" "SI") (const_int 4)
247 (eq_attr "op_type" "SS") (const_int 6)
248 (eq_attr "op_type" "SSE") (const_int 6)
249 (eq_attr "op_type" "RXE") (const_int 6)
250 (eq_attr "op_type" "RSE") (const_int 6)
251 (eq_attr "op_type" "RIL") (const_int 6)
252 (eq_attr "op_type" "RXY") (const_int 6)
253 (eq_attr "op_type" "RSY") (const_int 6)
254 (eq_attr "op_type" "SIY") (const_int 6)]
258 ;; Processor type. This attribute must exactly match the processor_type
259 ;; enumeration in s390.h. The current machine description does not
260 ;; distinguish between g5 and g6, but there are differences between the two
261 ;; CPUs could in theory be modeled.
263 (define_attr "cpu" "g5,g6,z900,z990,z9_109"
264 (const (symbol_ref "s390_tune")))
266 ;; Pipeline description for z900. For lack of anything better,
267 ;; this description is also used for the g5 and g6.
270 ;; Pipeline description for z990.
274 (include "predicates.md")
281 ;; This mode macro allows DF and SF patterns to be generated from the
283 (define_mode_macro FPR [DF SF])
285 ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
286 ;; from the same template.
287 (define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
289 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
290 ;; from the same template.
291 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
292 (define_mode_macro DSI [DI SI])
294 ;; This mode macro allows :P to be used for patterns that operate on
295 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
296 (define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
297 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
299 ;; This mode macro allows the QI and HI patterns to be defined from
300 ;; the same template.
301 (define_mode_macro HQI [HI QI])
303 ;; This mode macro allows the integer patterns to be defined from the
305 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
307 ;; This macro allows to unify all 'bCOND' expander patterns.
308 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
309 ordered uneq unlt ungt unle unge ltgt])
311 ;; This macro allows to unify all 'sCOND' patterns.
312 (define_code_macro SCOND [ltu gtu leu geu])
314 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
315 ;; the same template.
316 (define_code_macro SHIFT [ashift lshiftrt])
319 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
320 ;; and "ltebr" in SFmode.
321 (define_mode_attr de [(DF "d") (SF "e")])
323 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
324 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
325 (define_mode_attr dee [(DF "d") (SF "ee")])
327 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
328 ;; 'ashift' and "srdl" in 'lshiftrt'.
329 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
331 ;; In SHIFT templates, this attribute holds the correct standard name for the
332 ;; pattern itself and the corresponding function calls.
333 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
335 ;; This attribute handles differences in the instruction 'type' and will result
336 ;; in "RRE" for DImode and "RR" for SImode.
337 (define_mode_attr E [(DI "E") (SI "")])
339 ;; This attribute handles differences in the instruction 'type' and will result
340 ;; in "RSE" for TImode and "RS" for DImode.
341 (define_mode_attr TE [(TI "E") (DI "")])
343 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
344 ;; and "lcr" in SImode.
345 (define_mode_attr g [(DI "g") (SI "")])
347 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
348 ;; and "cds" in DImode.
349 (define_mode_attr tg [(TI "g") (DI "")])
351 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
352 ;; and "cfdbr" in SImode.
353 (define_mode_attr gf [(DI "g") (SI "f")])
355 ;; ICM mask required to load MODE value into the lowest subreg
356 ;; of a SImode register.
357 (define_mode_attr icm_lo [(HI "3") (QI "1")])
359 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
360 ;; HImode and "llgc" in QImode.
361 (define_mode_attr hc [(HI "h") (QI "c")])
363 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
365 (define_mode_attr DBL [(DI "TI") (SI "DI")])
367 ;; Maximum unsigned integer that fits in MODE.
368 (define_mode_attr max_uint [(HI "65535") (QI "255")])
372 ;;- Compare instructions.
375 (define_expand "cmp<mode>"
376 [(set (reg:CC CC_REGNUM)
377 (compare:CC (match_operand:GPR 0 "register_operand" "")
378 (match_operand:GPR 1 "general_operand" "")))]
381 s390_compare_op0 = operands[0];
382 s390_compare_op1 = operands[1];
386 (define_expand "cmp<mode>"
387 [(set (reg:CC CC_REGNUM)
388 (compare:CC (match_operand:FPR 0 "register_operand" "")
389 (match_operand:FPR 1 "general_operand" "")))]
392 s390_compare_op0 = operands[0];
393 s390_compare_op1 = operands[1];
398 ; Test-under-Mask instructions
400 (define_insn "*tmqi_mem"
401 [(set (reg CC_REGNUM)
402 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
403 (match_operand:QI 1 "immediate_operand" "n,n"))
404 (match_operand:QI 2 "immediate_operand" "n,n")))]
405 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
409 [(set_attr "op_type" "SI,SIY")])
411 (define_insn "*tmdi_reg"
412 [(set (reg CC_REGNUM)
413 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
414 (match_operand:DI 1 "immediate_operand"
415 "N0HD0,N1HD0,N2HD0,N3HD0"))
416 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
418 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
419 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
425 [(set_attr "op_type" "RI")])
427 (define_insn "*tmsi_reg"
428 [(set (reg CC_REGNUM)
429 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
430 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
431 (match_operand:SI 2 "immediate_operand" "n,n")))]
432 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
433 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
437 [(set_attr "op_type" "RI")])
439 (define_insn "*tm<mode>_full"
440 [(set (reg CC_REGNUM)
441 (compare (match_operand:HQI 0 "register_operand" "d")
442 (match_operand:HQI 1 "immediate_operand" "n")))]
443 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
445 [(set_attr "op_type" "RI")])
448 ; Load-and-Test instructions
450 (define_insn "*tstdi_sign"
451 [(set (reg CC_REGNUM)
452 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
453 (const_int 32)) (const_int 32))
454 (match_operand:DI 1 "const0_operand" "")))
455 (set (match_operand:DI 2 "register_operand" "=d")
456 (sign_extend:DI (match_dup 0)))]
457 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
459 [(set_attr "op_type" "RRE")])
461 (define_insn "*tstdi_extimm"
462 [(set (reg CC_REGNUM)
463 (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
464 (match_operand:DI 1 "const0_operand" "")))
465 (set (match_operand:DI 2 "register_operand" "=d,d")
467 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
471 [(set_attr "op_type" "RRE,RXY")])
473 (define_insn "*tstdi_cconly_extimm"
474 [(set (reg CC_REGNUM)
475 (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
476 (match_operand:DI 1 "const0_operand" "")))
477 (clobber (match_scratch:DI 2 "=X,d"))]
478 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
482 [(set_attr "op_type" "RRE,RXY")])
484 (define_insn "*tstdi"
485 [(set (reg CC_REGNUM)
486 (compare (match_operand:DI 0 "register_operand" "d")
487 (match_operand:DI 1 "const0_operand" "")))
488 (set (match_operand:DI 2 "register_operand" "=d")
490 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
492 [(set_attr "op_type" "RRE")])
494 (define_insn "*tstdi_cconly"
495 [(set (reg CC_REGNUM)
496 (compare (match_operand:DI 0 "register_operand" "d")
497 (match_operand:DI 1 "const0_operand" "")))]
498 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
500 [(set_attr "op_type" "RRE")])
502 (define_insn "*tstdi_cconly_31"
503 [(set (reg CC_REGNUM)
504 (compare (match_operand:DI 0 "register_operand" "d")
505 (match_operand:DI 1 "const0_operand" "")))]
506 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
508 [(set_attr "op_type" "RS")
509 (set_attr "atype" "reg")])
511 (define_insn "*tstsi_extimm"
512 [(set (reg CC_REGNUM)
513 (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
514 (match_operand:SI 1 "const0_operand" "")))
515 (set (match_operand:SI 2 "register_operand" "=d,d")
517 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
521 [(set_attr "op_type" "RR,RXY")])
523 (define_insn "*tstsi_cconly_extimm"
524 [(set (reg CC_REGNUM)
525 (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
526 (match_operand:SI 1 "const0_operand" "")))
527 (clobber (match_scratch:SI 2 "=X,d"))]
528 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
532 [(set_attr "op_type" "RR,RXY")])
534 (define_insn "*tstsi"
535 [(set (reg CC_REGNUM)
536 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
537 (match_operand:SI 1 "const0_operand" "")))
538 (set (match_operand:SI 2 "register_operand" "=d,d,d")
540 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
545 [(set_attr "op_type" "RR,RS,RSY")])
547 (define_insn "*tstsi_cconly"
548 [(set (reg CC_REGNUM)
549 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
550 (match_operand:SI 1 "const0_operand" "")))
551 (clobber (match_scratch:SI 2 "=X,d,d"))]
552 "s390_match_ccmode(insn, CCSmode)"
557 [(set_attr "op_type" "RR,RS,RSY")])
559 (define_insn "*tstsi_cconly2"
560 [(set (reg CC_REGNUM)
561 (compare (match_operand:SI 0 "register_operand" "d")
562 (match_operand:SI 1 "const0_operand" "")))]
563 "s390_match_ccmode(insn, CCSmode)"
565 [(set_attr "op_type" "RR")])
567 (define_insn "*tst<mode>CCT"
568 [(set (reg CC_REGNUM)
569 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
570 (match_operand:HQI 1 "const0_operand" "")))
571 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
573 "s390_match_ccmode(insn, CCTmode)"
576 icmy\t%2,<icm_lo>,%S0
578 [(set_attr "op_type" "RS,RSY,RI")])
580 (define_insn "*tsthiCCT_cconly"
581 [(set (reg CC_REGNUM)
582 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
583 (match_operand:HI 1 "const0_operand" "")))
584 (clobber (match_scratch:HI 2 "=d,d,X"))]
585 "s390_match_ccmode(insn, CCTmode)"
590 [(set_attr "op_type" "RS,RSY,RI")])
592 (define_insn "*tstqiCCT_cconly"
593 [(set (reg CC_REGNUM)
594 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
595 (match_operand:QI 1 "const0_operand" "")))]
596 "s390_match_ccmode(insn, CCTmode)"
601 [(set_attr "op_type" "SI,SIY,RI")])
603 (define_insn "*tst<mode>"
604 [(set (reg CC_REGNUM)
605 (compare (match_operand:HQI 0 "s_operand" "Q,S")
606 (match_operand:HQI 1 "const0_operand" "")))
607 (set (match_operand:HQI 2 "register_operand" "=d,d")
609 "s390_match_ccmode(insn, CCSmode)"
612 icmy\t%2,<icm_lo>,%S0"
613 [(set_attr "op_type" "RS,RSY")])
615 (define_insn "*tst<mode>_cconly"
616 [(set (reg CC_REGNUM)
617 (compare (match_operand:HQI 0 "s_operand" "Q,S")
618 (match_operand:HQI 1 "const0_operand" "")))
619 (clobber (match_scratch:HQI 2 "=d,d"))]
620 "s390_match_ccmode(insn, CCSmode)"
623 icmy\t%2,<icm_lo>,%S0"
624 [(set_attr "op_type" "RS,RSY")])
627 ; Compare (equality) instructions
629 (define_insn "*cmpdi_cct"
630 [(set (reg CC_REGNUM)
631 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
632 (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
633 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
640 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
642 (define_insn "*cmpsi_cct"
643 [(set (reg CC_REGNUM)
644 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
645 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
646 "s390_match_ccmode (insn, CCTmode)"
654 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
657 ; Compare (signed) instructions
659 (define_insn "*cmpdi_ccs_sign"
660 [(set (reg CC_REGNUM)
661 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
662 (match_operand:DI 0 "register_operand" "d,d")))]
663 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
667 [(set_attr "op_type" "RRE,RXY")])
669 (define_insn "*cmpdi_ccs"
670 [(set (reg CC_REGNUM)
671 (compare (match_operand:DI 0 "register_operand" "d,d,d,d")
672 (match_operand:DI 1 "general_operand" "d,K,Os,m")))]
673 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
679 [(set_attr "op_type" "RRE,RI,RIL,RXY")])
681 (define_insn "*cmpsi_ccs_sign"
682 [(set (reg CC_REGNUM)
683 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
684 (match_operand:SI 0 "register_operand" "d,d")))]
685 "s390_match_ccmode(insn, CCSRmode)"
689 [(set_attr "op_type" "RX,RXY")])
691 (define_insn "*cmpsi_ccs"
692 [(set (reg CC_REGNUM)
693 (compare (match_operand:SI 0 "register_operand" "d,d,d,d,d")
694 (match_operand:SI 1 "general_operand" "d,K,Os,R,T")))]
695 "s390_match_ccmode(insn, CCSmode)"
702 [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
705 ; Compare (unsigned) instructions
707 (define_insn "*cmpdi_ccu_zero"
708 [(set (reg CC_REGNUM)
709 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
710 (match_operand:DI 0 "register_operand" "d,d")))]
711 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
715 [(set_attr "op_type" "RRE,RXY")])
717 (define_insn "*cmpdi_ccu"
718 [(set (reg CC_REGNUM)
719 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
720 (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
721 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
728 [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
730 (define_insn "*cmpsi_ccu"
731 [(set (reg CC_REGNUM)
732 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
733 (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
734 "s390_match_ccmode (insn, CCUmode)"
742 [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
744 (define_insn "*cmphi_ccu"
745 [(set (reg CC_REGNUM)
746 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
747 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
748 "s390_match_ccmode (insn, CCUmode)
749 && !register_operand (operands[1], HImode)"
755 [(set_attr "op_type" "RS,RSY,SS,SS")])
757 (define_insn "*cmpqi_ccu"
758 [(set (reg CC_REGNUM)
759 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
760 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
761 "s390_match_ccmode (insn, CCUmode)
762 && !register_operand (operands[1], QImode)"
770 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
773 ; Block compare (CLC) instruction patterns.
776 [(set (reg CC_REGNUM)
777 (compare (match_operand:BLK 0 "memory_operand" "Q")
778 (match_operand:BLK 1 "memory_operand" "Q")))
779 (use (match_operand 2 "const_int_operand" "n"))]
780 "s390_match_ccmode (insn, CCUmode)
781 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
782 "clc\t%O0(%2,%R0),%S1"
783 [(set_attr "op_type" "SS")])
786 [(set (reg CC_REGNUM)
787 (compare (match_operand 0 "memory_operand" "")
788 (match_operand 1 "memory_operand" "")))]
790 && s390_match_ccmode (insn, CCUmode)
791 && GET_MODE (operands[0]) == GET_MODE (operands[1])
792 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
794 [(set (match_dup 0) (match_dup 1))
795 (use (match_dup 2))])]
797 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
798 operands[0] = adjust_address (operands[0], BLKmode, 0);
799 operands[1] = adjust_address (operands[1], BLKmode, 0);
801 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
802 operands[0], operands[1]);
803 operands[0] = SET_DEST (PATTERN (curr_insn));
807 ; (DF|SF) instructions
809 (define_insn "*cmp<mode>_ccs_0"
810 [(set (reg CC_REGNUM)
811 (compare (match_operand:FPR 0 "register_operand" "f")
812 (match_operand:FPR 1 "const0_operand" "")))]
813 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
815 [(set_attr "op_type" "RRE")
816 (set_attr "type" "fsimp<mode>")])
818 (define_insn "*cmp<mode>_ccs_0_ibm"
819 [(set (reg CC_REGNUM)
820 (compare (match_operand:FPR 0 "register_operand" "f")
821 (match_operand:FPR 1 "const0_operand" "")))]
822 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
824 [(set_attr "op_type" "RR")
825 (set_attr "type" "fsimp<mode>")])
827 (define_insn "*cmp<mode>_ccs"
828 [(set (reg CC_REGNUM)
829 (compare (match_operand:FPR 0 "register_operand" "f,f")
830 (match_operand:FPR 1 "general_operand" "f,R")))]
831 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
835 [(set_attr "op_type" "RRE,RXE")
836 (set_attr "type" "fsimp<mode>")])
838 (define_insn "*cmp<mode>_ccs_ibm"
839 [(set (reg CC_REGNUM)
840 (compare (match_operand:FPR 0 "register_operand" "f,f")
841 (match_operand:FPR 1 "general_operand" "f,R")))]
842 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
846 [(set_attr "op_type" "RR,RX")
847 (set_attr "type" "fsimp<mode>")])
851 ;;- Move instructions.
855 ; movti instruction pattern(s).
859 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
860 (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
868 [(set_attr "op_type" "RSY,RSY,*,*,SS")
869 (set_attr "type" "lm,stm,*,*,*")])
872 [(set (match_operand:TI 0 "nonimmediate_operand" "")
873 (match_operand:TI 1 "general_operand" ""))]
874 "TARGET_64BIT && reload_completed
875 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
876 [(set (match_dup 2) (match_dup 4))
877 (set (match_dup 3) (match_dup 5))]
879 operands[2] = operand_subword (operands[0], 0, 0, TImode);
880 operands[3] = operand_subword (operands[0], 1, 0, TImode);
881 operands[4] = operand_subword (operands[1], 0, 0, TImode);
882 operands[5] = operand_subword (operands[1], 1, 0, TImode);
886 [(set (match_operand:TI 0 "nonimmediate_operand" "")
887 (match_operand:TI 1 "general_operand" ""))]
888 "TARGET_64BIT && reload_completed
889 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
890 [(set (match_dup 2) (match_dup 4))
891 (set (match_dup 3) (match_dup 5))]
893 operands[2] = operand_subword (operands[0], 1, 0, TImode);
894 operands[3] = operand_subword (operands[0], 0, 0, TImode);
895 operands[4] = operand_subword (operands[1], 1, 0, TImode);
896 operands[5] = operand_subword (operands[1], 0, 0, TImode);
900 [(set (match_operand:TI 0 "register_operand" "")
901 (match_operand:TI 1 "memory_operand" ""))]
902 "TARGET_64BIT && reload_completed
903 && !s_operand (operands[1], VOIDmode)"
904 [(set (match_dup 0) (match_dup 1))]
906 rtx addr = operand_subword (operands[0], 1, 0, TImode);
907 s390_load_address (addr, XEXP (operands[1], 0));
908 operands[1] = replace_equiv_address (operands[1], addr);
911 (define_expand "reload_outti"
912 [(parallel [(match_operand:TI 0 "" "")
913 (match_operand:TI 1 "register_operand" "d")
914 (match_operand:DI 2 "register_operand" "=&a")])]
917 gcc_assert (MEM_P (operands[0]));
918 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
919 operands[0] = replace_equiv_address (operands[0], operands[2]);
920 emit_move_insn (operands[0], operands[1]);
925 ; movdi instruction pattern(s).
928 (define_expand "movdi"
929 [(set (match_operand:DI 0 "general_operand" "")
930 (match_operand:DI 1 "general_operand" ""))]
933 /* Handle symbolic constants. */
934 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
935 emit_symbolic_move (operands);
938 (define_insn "*movdi_larl"
939 [(set (match_operand:DI 0 "register_operand" "=d")
940 (match_operand:DI 1 "larl_operand" "X"))]
942 && !FP_REG_P (operands[0])"
944 [(set_attr "op_type" "RIL")
945 (set_attr "type" "larl")])
947 (define_insn "*movdi_64extimm"
948 [(set (match_operand:DI 0 "nonimmediate_operand"
949 "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
950 (match_operand:DI 1 "general_operand"
951 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
952 "TARGET_64BIT && TARGET_EXTIMM"
976 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
977 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
978 (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
979 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
981 (define_insn "*movdi_64"
982 [(set (match_operand:DI 0 "nonimmediate_operand"
983 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
984 (match_operand:DI 1 "general_operand"
985 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
986 "TARGET_64BIT && !TARGET_EXTIMM"
1007 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
1008 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
1009 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
1010 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
1013 [(set (match_operand:DI 0 "register_operand" "")
1014 (match_operand:DI 1 "register_operand" ""))]
1015 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
1016 [(set (match_dup 2) (match_dup 3))
1017 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1018 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1019 "operands[2] = gen_lowpart (SImode, operands[0]);
1020 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1023 [(set (match_operand:DI 0 "register_operand" "")
1024 (match_operand:DI 1 "register_operand" ""))]
1025 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1026 && dead_or_set_p (insn, operands[1])"
1027 [(set (match_dup 3) (match_dup 2))
1028 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1029 (set (match_dup 4) (match_dup 2))]
1030 "operands[2] = gen_lowpart (SImode, operands[1]);
1031 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1034 [(set (match_operand:DI 0 "register_operand" "")
1035 (match_operand:DI 1 "register_operand" ""))]
1036 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1037 && !dead_or_set_p (insn, operands[1])"
1038 [(set (match_dup 3) (match_dup 2))
1039 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1040 (set (match_dup 4) (match_dup 2))
1041 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1042 "operands[2] = gen_lowpart (SImode, operands[1]);
1043 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1045 (define_insn "*movdi_31"
1046 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
1047 (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
1062 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
1063 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
1066 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1067 (match_operand:DI 1 "general_operand" ""))]
1068 "!TARGET_64BIT && reload_completed
1069 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1070 [(set (match_dup 2) (match_dup 4))
1071 (set (match_dup 3) (match_dup 5))]
1073 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1074 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1075 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1076 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1080 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1081 (match_operand:DI 1 "general_operand" ""))]
1082 "!TARGET_64BIT && reload_completed
1083 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1084 [(set (match_dup 2) (match_dup 4))
1085 (set (match_dup 3) (match_dup 5))]
1087 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1088 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1089 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1090 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1094 [(set (match_operand:DI 0 "register_operand" "")
1095 (match_operand:DI 1 "memory_operand" ""))]
1096 "!TARGET_64BIT && reload_completed
1097 && !FP_REG_P (operands[0])
1098 && !s_operand (operands[1], VOIDmode)"
1099 [(set (match_dup 0) (match_dup 1))]
1101 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1102 s390_load_address (addr, XEXP (operands[1], 0));
1103 operands[1] = replace_equiv_address (operands[1], addr);
1106 (define_expand "reload_outdi"
1107 [(parallel [(match_operand:DI 0 "" "")
1108 (match_operand:DI 1 "register_operand" "d")
1109 (match_operand:SI 2 "register_operand" "=&a")])]
1112 gcc_assert (MEM_P (operands[0]));
1113 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1114 operands[0] = replace_equiv_address (operands[0], operands[2]);
1115 emit_move_insn (operands[0], operands[1]);
1120 [(set (match_operand:DI 0 "register_operand" "")
1121 (mem:DI (match_operand 1 "address_operand" "")))]
1123 && !FP_REG_P (operands[0])
1124 && GET_CODE (operands[1]) == SYMBOL_REF
1125 && CONSTANT_POOL_ADDRESS_P (operands[1])
1126 && get_pool_mode (operands[1]) == DImode
1127 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1128 [(set (match_dup 0) (match_dup 2))]
1129 "operands[2] = get_pool_constant (operands[1]);")
1131 (define_insn "*la_64"
1132 [(set (match_operand:DI 0 "register_operand" "=d,d")
1133 (match_operand:QI 1 "address_operand" "U,W"))]
1138 [(set_attr "op_type" "RX,RXY")
1139 (set_attr "type" "la")])
1143 [(set (match_operand:DI 0 "register_operand" "")
1144 (match_operand:QI 1 "address_operand" ""))
1145 (clobber (reg:CC CC_REGNUM))])]
1147 && preferred_la_operand_p (operands[1], const0_rtx)"
1148 [(set (match_dup 0) (match_dup 1))]
1152 [(set (match_operand:DI 0 "register_operand" "")
1153 (match_operand:DI 1 "register_operand" ""))
1156 (plus:DI (match_dup 0)
1157 (match_operand:DI 2 "nonmemory_operand" "")))
1158 (clobber (reg:CC CC_REGNUM))])]
1160 && !reg_overlap_mentioned_p (operands[0], operands[2])
1161 && preferred_la_operand_p (operands[1], operands[2])"
1162 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1165 (define_expand "reload_indi"
1166 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1167 (match_operand:DI 1 "s390_plus_operand" "")
1168 (match_operand:DI 2 "register_operand" "=&a")])]
1171 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1176 ; movsi instruction pattern(s).
1179 (define_expand "movsi"
1180 [(set (match_operand:SI 0 "general_operand" "")
1181 (match_operand:SI 1 "general_operand" ""))]
1184 /* Handle symbolic constants. */
1185 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1186 emit_symbolic_move (operands);
1189 (define_insn "*movsi_larl"
1190 [(set (match_operand:SI 0 "register_operand" "=d")
1191 (match_operand:SI 1 "larl_operand" "X"))]
1192 "!TARGET_64BIT && TARGET_CPU_ZARCH
1193 && !FP_REG_P (operands[0])"
1195 [(set_attr "op_type" "RIL")
1196 (set_attr "type" "larl")])
1198 (define_insn "*movsi_zarch"
1199 [(set (match_operand:SI 0 "nonimmediate_operand"
1200 "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1201 (match_operand:SI 1 "general_operand"
1202 "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1225 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
1226 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1227 (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
1228 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1230 (define_insn "*movsi_esa"
1231 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1232 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1247 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1248 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1251 [(set (match_operand:SI 0 "register_operand" "")
1252 (mem:SI (match_operand 1 "address_operand" "")))]
1253 "!FP_REG_P (operands[0])
1254 && GET_CODE (operands[1]) == SYMBOL_REF
1255 && CONSTANT_POOL_ADDRESS_P (operands[1])
1256 && get_pool_mode (operands[1]) == SImode
1257 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1258 [(set (match_dup 0) (match_dup 2))]
1259 "operands[2] = get_pool_constant (operands[1]);")
1261 (define_insn "*la_31"
1262 [(set (match_operand:SI 0 "register_operand" "=d,d")
1263 (match_operand:QI 1 "address_operand" "U,W"))]
1264 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1268 [(set_attr "op_type" "RX,RXY")
1269 (set_attr "type" "la")])
1273 [(set (match_operand:SI 0 "register_operand" "")
1274 (match_operand:QI 1 "address_operand" ""))
1275 (clobber (reg:CC CC_REGNUM))])]
1277 && preferred_la_operand_p (operands[1], const0_rtx)"
1278 [(set (match_dup 0) (match_dup 1))]
1282 [(set (match_operand:SI 0 "register_operand" "")
1283 (match_operand:SI 1 "register_operand" ""))
1286 (plus:SI (match_dup 0)
1287 (match_operand:SI 2 "nonmemory_operand" "")))
1288 (clobber (reg:CC CC_REGNUM))])]
1290 && !reg_overlap_mentioned_p (operands[0], operands[2])
1291 && preferred_la_operand_p (operands[1], operands[2])"
1292 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1295 (define_insn "*la_31_and"
1296 [(set (match_operand:SI 0 "register_operand" "=d,d")
1297 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1298 (const_int 2147483647)))]
1303 [(set_attr "op_type" "RX,RXY")
1304 (set_attr "type" "la")])
1306 (define_insn_and_split "*la_31_and_cc"
1307 [(set (match_operand:SI 0 "register_operand" "=d")
1308 (and:SI (match_operand:QI 1 "address_operand" "p")
1309 (const_int 2147483647)))
1310 (clobber (reg:CC CC_REGNUM))]
1313 "&& reload_completed"
1315 (and:SI (match_dup 1) (const_int 2147483647)))]
1317 [(set_attr "op_type" "RX")
1318 (set_attr "type" "la")])
1320 (define_insn "force_la_31"
1321 [(set (match_operand:SI 0 "register_operand" "=d,d")
1322 (match_operand:QI 1 "address_operand" "U,W"))
1323 (use (const_int 0))]
1328 [(set_attr "op_type" "RX")
1329 (set_attr "type" "la")])
1331 (define_expand "reload_insi"
1332 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1333 (match_operand:SI 1 "s390_plus_operand" "")
1334 (match_operand:SI 2 "register_operand" "=&a")])]
1337 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1342 ; movhi instruction pattern(s).
1345 (define_expand "movhi"
1346 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1347 (match_operand:HI 1 "general_operand" ""))]
1350 /* Make it explicit that loading a register from memory
1351 always sign-extends (at least) to SImode. */
1352 if (optimize && !no_new_pseudos
1353 && register_operand (operands[0], VOIDmode)
1354 && GET_CODE (operands[1]) == MEM)
1356 rtx tmp = gen_reg_rtx (SImode);
1357 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1358 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1359 operands[1] = gen_lowpart (HImode, tmp);
1363 (define_insn "*movhi"
1364 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1365 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1375 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1376 (set_attr "type" "lr,*,*,*,store,store,*")])
1379 [(set (match_operand:HI 0 "register_operand" "")
1380 (mem:HI (match_operand 1 "address_operand" "")))]
1381 "GET_CODE (operands[1]) == SYMBOL_REF
1382 && CONSTANT_POOL_ADDRESS_P (operands[1])
1383 && get_pool_mode (operands[1]) == HImode
1384 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1385 [(set (match_dup 0) (match_dup 2))]
1386 "operands[2] = get_pool_constant (operands[1]);")
1389 ; movqi instruction pattern(s).
1392 (define_expand "movqi"
1393 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1394 (match_operand:QI 1 "general_operand" ""))]
1397 /* On z/Architecture, zero-extending from memory to register
1398 is just as fast as a QImode load. */
1399 if (TARGET_ZARCH && optimize && !no_new_pseudos
1400 && register_operand (operands[0], VOIDmode)
1401 && GET_CODE (operands[1]) == MEM)
1403 rtx tmp = gen_reg_rtx (word_mode);
1404 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1405 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1406 operands[1] = gen_lowpart (QImode, tmp);
1410 (define_insn "*movqi"
1411 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1412 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1424 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1425 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1428 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1429 (mem:QI (match_operand 1 "address_operand" "")))]
1430 "GET_CODE (operands[1]) == SYMBOL_REF
1431 && CONSTANT_POOL_ADDRESS_P (operands[1])
1432 && get_pool_mode (operands[1]) == QImode
1433 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1434 [(set (match_dup 0) (match_dup 2))]
1435 "operands[2] = get_pool_constant (operands[1]);")
1438 ; movstrictqi instruction pattern(s).
1441 (define_insn "*movstrictqi"
1442 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1443 (match_operand:QI 1 "memory_operand" "R,T"))]
1448 [(set_attr "op_type" "RX,RXY")])
1451 ; movstricthi instruction pattern(s).
1454 (define_insn "*movstricthi"
1455 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1456 (match_operand:HI 1 "memory_operand" "Q,S"))
1457 (clobber (reg:CC CC_REGNUM))]
1462 [(set_attr "op_type" "RS,RSY")])
1465 ; movstrictsi instruction pattern(s).
1468 (define_insn "movstrictsi"
1469 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1470 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1477 [(set_attr "op_type" "RR,RX,RXY,RRE")
1478 (set_attr "type" "lr,load,load,*")])
1481 ; movdf instruction pattern(s).
1484 (define_expand "movdf"
1485 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1486 (match_operand:DF 1 "general_operand" ""))]
1490 (define_insn "*movdf_64"
1491 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1492 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1505 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1506 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1508 (define_insn "*movdf_31"
1509 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
1510 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
1526 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1527 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
1528 lm,lm,stm,stm,*,*,*")])
1531 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1532 (match_operand:DF 1 "general_operand" ""))]
1533 "!TARGET_64BIT && reload_completed
1534 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1535 [(set (match_dup 2) (match_dup 4))
1536 (set (match_dup 3) (match_dup 5))]
1538 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1539 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1540 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1541 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1545 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1546 (match_operand:DF 1 "general_operand" ""))]
1547 "!TARGET_64BIT && reload_completed
1548 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1549 [(set (match_dup 2) (match_dup 4))
1550 (set (match_dup 3) (match_dup 5))]
1552 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1553 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1554 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1555 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1559 [(set (match_operand:DF 0 "register_operand" "")
1560 (match_operand:DF 1 "memory_operand" ""))]
1561 "!TARGET_64BIT && reload_completed
1562 && !FP_REG_P (operands[0])
1563 && !s_operand (operands[1], VOIDmode)"
1564 [(set (match_dup 0) (match_dup 1))]
1566 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1567 s390_load_address (addr, XEXP (operands[1], 0));
1568 operands[1] = replace_equiv_address (operands[1], addr);
1571 (define_expand "reload_outdf"
1572 [(parallel [(match_operand:DF 0 "" "")
1573 (match_operand:DF 1 "register_operand" "d")
1574 (match_operand:SI 2 "register_operand" "=&a")])]
1577 gcc_assert (MEM_P (operands[0]));
1578 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1579 operands[0] = replace_equiv_address (operands[0], operands[2]);
1580 emit_move_insn (operands[0], operands[1]);
1585 ; movsf instruction pattern(s).
1588 (define_insn "movsf"
1589 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1590 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1605 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1606 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1607 lr,load,load,store,store,*")])
1610 ; movcc instruction pattern
1613 (define_insn "movcc"
1614 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1615 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1625 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1626 (set_attr "type" "lr,*,*,store,store,load,load")])
1629 ; Block move (MVC) patterns.
1633 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1634 (match_operand:BLK 1 "memory_operand" "Q"))
1635 (use (match_operand 2 "const_int_operand" "n"))]
1636 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1637 "mvc\t%O0(%2,%R0),%S1"
1638 [(set_attr "op_type" "SS")])
1641 [(set (match_operand 0 "memory_operand" "")
1642 (match_operand 1 "memory_operand" ""))]
1644 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1645 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1647 [(set (match_dup 0) (match_dup 1))
1648 (use (match_dup 2))])]
1650 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1651 operands[0] = adjust_address (operands[0], BLKmode, 0);
1652 operands[1] = adjust_address (operands[1], BLKmode, 0);
1657 [(set (match_operand:BLK 0 "memory_operand" "")
1658 (match_operand:BLK 1 "memory_operand" ""))
1659 (use (match_operand 2 "const_int_operand" ""))])
1661 [(set (match_operand:BLK 3 "memory_operand" "")
1662 (match_operand:BLK 4 "memory_operand" ""))
1663 (use (match_operand 5 "const_int_operand" ""))])]
1664 "s390_offset_p (operands[0], operands[3], operands[2])
1665 && s390_offset_p (operands[1], operands[4], operands[2])
1666 && !s390_overlap_p (operands[0], operands[1],
1667 INTVAL (operands[2]) + INTVAL (operands[5]))
1668 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1670 [(set (match_dup 6) (match_dup 7))
1671 (use (match_dup 8))])]
1672 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1673 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1674 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1678 ; load_multiple pattern(s).
1680 ; ??? Due to reload problems with replacing registers inside match_parallel
1681 ; we currently support load_multiple/store_multiple only after reload.
1684 (define_expand "load_multiple"
1685 [(match_par_dup 3 [(set (match_operand 0 "" "")
1686 (match_operand 1 "" ""))
1687 (use (match_operand 2 "" ""))])]
1690 enum machine_mode mode;
1696 /* Support only loading a constant number of fixed-point registers from
1697 memory and only bother with this if more than two */
1698 if (GET_CODE (operands[2]) != CONST_INT
1699 || INTVAL (operands[2]) < 2
1700 || INTVAL (operands[2]) > 16
1701 || GET_CODE (operands[1]) != MEM
1702 || GET_CODE (operands[0]) != REG
1703 || REGNO (operands[0]) >= 16)
1706 count = INTVAL (operands[2]);
1707 regno = REGNO (operands[0]);
1708 mode = GET_MODE (operands[0]);
1709 if (mode != SImode && mode != word_mode)
1712 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1715 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1717 from = XEXP (operands[1], 0);
1720 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1721 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1722 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1724 from = XEXP (XEXP (operands[1], 0), 0);
1725 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1732 from = force_reg (Pmode, XEXP (operands[1], 0));
1736 for (i = 0; i < count; i++)
1737 XVECEXP (operands[3], 0, i)
1738 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1739 change_address (operands[1], mode,
1740 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1743 (define_insn "*load_multiple_di"
1744 [(match_parallel 0 "load_multiple_operation"
1745 [(set (match_operand:DI 1 "register_operand" "=r")
1746 (match_operand:DI 2 "s_operand" "QS"))])]
1747 "reload_completed && word_mode == DImode"
1749 int words = XVECLEN (operands[0], 0);
1750 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1751 return "lmg\t%1,%0,%S2";
1753 [(set_attr "op_type" "RSY")
1754 (set_attr "type" "lm")])
1756 (define_insn "*load_multiple_si"
1757 [(match_parallel 0 "load_multiple_operation"
1758 [(set (match_operand:SI 1 "register_operand" "=r,r")
1759 (match_operand:SI 2 "s_operand" "Q,S"))])]
1762 int words = XVECLEN (operands[0], 0);
1763 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1764 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1766 [(set_attr "op_type" "RS,RSY")
1767 (set_attr "type" "lm")])
1770 ; store multiple pattern(s).
1773 (define_expand "store_multiple"
1774 [(match_par_dup 3 [(set (match_operand 0 "" "")
1775 (match_operand 1 "" ""))
1776 (use (match_operand 2 "" ""))])]
1779 enum machine_mode mode;
1785 /* Support only storing a constant number of fixed-point registers to
1786 memory and only bother with this if more than two. */
1787 if (GET_CODE (operands[2]) != CONST_INT
1788 || INTVAL (operands[2]) < 2
1789 || INTVAL (operands[2]) > 16
1790 || GET_CODE (operands[0]) != MEM
1791 || GET_CODE (operands[1]) != REG
1792 || REGNO (operands[1]) >= 16)
1795 count = INTVAL (operands[2]);
1796 regno = REGNO (operands[1]);
1797 mode = GET_MODE (operands[1]);
1798 if (mode != SImode && mode != word_mode)
1801 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1805 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1807 to = XEXP (operands[0], 0);
1810 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1811 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1812 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1814 to = XEXP (XEXP (operands[0], 0), 0);
1815 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1822 to = force_reg (Pmode, XEXP (operands[0], 0));
1826 for (i = 0; i < count; i++)
1827 XVECEXP (operands[3], 0, i)
1828 = gen_rtx_SET (VOIDmode,
1829 change_address (operands[0], mode,
1830 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1831 gen_rtx_REG (mode, regno + i));
1834 (define_insn "*store_multiple_di"
1835 [(match_parallel 0 "store_multiple_operation"
1836 [(set (match_operand:DI 1 "s_operand" "=QS")
1837 (match_operand:DI 2 "register_operand" "r"))])]
1838 "reload_completed && word_mode == DImode"
1840 int words = XVECLEN (operands[0], 0);
1841 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1842 return "stmg\t%2,%0,%S1";
1844 [(set_attr "op_type" "RSY")
1845 (set_attr "type" "stm")])
1848 (define_insn "*store_multiple_si"
1849 [(match_parallel 0 "store_multiple_operation"
1850 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1851 (match_operand:SI 2 "register_operand" "r,r"))])]
1854 int words = XVECLEN (operands[0], 0);
1855 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1856 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1858 [(set_attr "op_type" "RS,RSY")
1859 (set_attr "type" "stm")])
1862 ;; String instructions.
1865 (define_insn "*execute"
1866 [(match_parallel 0 ""
1867 [(unspec [(match_operand 1 "register_operand" "a")
1868 (match_operand:BLK 2 "memory_operand" "R")
1869 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1870 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1871 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1873 [(set_attr "op_type" "RX")
1874 (set_attr "type" "cs")])
1878 ; strlenM instruction pattern(s).
1881 (define_expand "strlen<mode>"
1882 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
1885 (unspec:P [(const_int 0)
1886 (match_operand:BLK 1 "memory_operand" "")
1888 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1889 (clobber (scratch:P))
1890 (clobber (reg:CC CC_REGNUM))])
1892 [(set (match_operand:P 0 "register_operand" "")
1893 (minus:P (match_dup 4) (match_dup 5)))
1894 (clobber (reg:CC CC_REGNUM))])]
1897 operands[4] = gen_reg_rtx (Pmode);
1898 operands[5] = gen_reg_rtx (Pmode);
1899 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1900 operands[1] = replace_equiv_address (operands[1], operands[5]);
1903 (define_insn "*strlen<mode>"
1904 [(set (match_operand:P 0 "register_operand" "=a")
1905 (unspec:P [(match_operand:P 2 "general_operand" "0")
1906 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1908 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1909 (clobber (match_scratch:P 1 "=a"))
1910 (clobber (reg:CC CC_REGNUM))]
1912 "srst\t%0,%1\;jo\t.-4"
1913 [(set_attr "length" "8")
1914 (set_attr "type" "vs")])
1917 ; cmpstrM instruction pattern(s).
1920 (define_expand "cmpstrsi"
1921 [(set (reg:SI 0) (const_int 0))
1923 [(clobber (match_operand 3 "" ""))
1924 (clobber (match_dup 4))
1925 (set (reg:CCU CC_REGNUM)
1926 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
1927 (match_operand:BLK 2 "memory_operand" "")))
1930 [(set (match_operand:SI 0 "register_operand" "=d")
1931 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
1932 (clobber (reg:CC CC_REGNUM))])]
1935 /* As the result of CMPINT is inverted compared to what we need,
1936 we have to swap the operands. */
1937 rtx op1 = operands[2];
1938 rtx op2 = operands[1];
1939 rtx addr1 = gen_reg_rtx (Pmode);
1940 rtx addr2 = gen_reg_rtx (Pmode);
1942 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
1943 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
1944 operands[1] = replace_equiv_address_nv (op1, addr1);
1945 operands[2] = replace_equiv_address_nv (op2, addr2);
1946 operands[3] = addr1;
1947 operands[4] = addr2;
1950 (define_insn "*cmpstr<mode>"
1951 [(clobber (match_operand:P 0 "register_operand" "=d"))
1952 (clobber (match_operand:P 1 "register_operand" "=d"))
1953 (set (reg:CCU CC_REGNUM)
1954 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
1955 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
1958 "clst\t%0,%1\;jo\t.-4"
1959 [(set_attr "length" "8")
1960 (set_attr "type" "vs")])
1963 ; movstr instruction pattern.
1966 (define_expand "movstr"
1967 [(set (reg:SI 0) (const_int 0))
1969 [(clobber (match_dup 3))
1970 (set (match_operand:BLK 1 "memory_operand" "")
1971 (match_operand:BLK 2 "memory_operand" ""))
1972 (set (match_operand 0 "register_operand" "")
1973 (unspec [(match_dup 1)
1975 (reg:SI 0)] UNSPEC_MVST))
1976 (clobber (reg:CC CC_REGNUM))])]
1979 rtx addr1 = gen_reg_rtx (Pmode);
1980 rtx addr2 = gen_reg_rtx (Pmode);
1982 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1983 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
1984 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1985 operands[2] = replace_equiv_address_nv (operands[2], addr2);
1986 operands[3] = addr2;
1989 (define_insn "*movstr"
1990 [(clobber (match_operand:P 2 "register_operand" "=d"))
1991 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
1992 (mem:BLK (match_operand:P 3 "register_operand" "2")))
1993 (set (match_operand:P 0 "register_operand" "=d")
1994 (unspec [(mem:BLK (match_dup 1))
1995 (mem:BLK (match_dup 3))
1996 (reg:SI 0)] UNSPEC_MVST))
1997 (clobber (reg:CC CC_REGNUM))]
1999 "mvst\t%1,%2\;jo\t.-4"
2000 [(set_attr "length" "8")
2001 (set_attr "type" "vs")])
2005 ; movmemM instruction pattern(s).
2008 (define_expand "movmem<mode>"
2009 [(set (match_operand:BLK 0 "memory_operand" "")
2010 (match_operand:BLK 1 "memory_operand" ""))
2011 (use (match_operand:GPR 2 "general_operand" ""))
2012 (match_operand 3 "" "")]
2014 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2016 ; Move a block that is up to 256 bytes in length.
2017 ; The block length is taken as (operands[2] % 256) + 1.
2019 (define_expand "movmem_short"
2021 [(set (match_operand:BLK 0 "memory_operand" "")
2022 (match_operand:BLK 1 "memory_operand" ""))
2023 (use (match_operand 2 "nonmemory_operand" ""))
2024 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2025 (clobber (match_dup 3))])]
2027 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2029 (define_insn "*movmem_short"
2030 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2031 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
2032 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2033 (use (match_operand 3 "immediate_operand" "X,R,X"))
2034 (clobber (match_scratch 4 "=X,X,&a"))]
2035 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2036 && GET_MODE (operands[4]) == Pmode"
2038 [(set_attr "type" "cs")])
2041 [(set (match_operand:BLK 0 "memory_operand" "")
2042 (match_operand:BLK 1 "memory_operand" ""))
2043 (use (match_operand 2 "const_int_operand" ""))
2044 (use (match_operand 3 "immediate_operand" ""))
2045 (clobber (scratch))]
2048 [(set (match_dup 0) (match_dup 1))
2049 (use (match_dup 2))])]
2050 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2053 [(set (match_operand:BLK 0 "memory_operand" "")
2054 (match_operand:BLK 1 "memory_operand" ""))
2055 (use (match_operand 2 "register_operand" ""))
2056 (use (match_operand 3 "memory_operand" ""))
2057 (clobber (scratch))]
2060 [(unspec [(match_dup 2) (match_dup 3)
2061 (const_int 0)] UNSPEC_EXECUTE)
2062 (set (match_dup 0) (match_dup 1))
2063 (use (const_int 1))])]
2067 [(set (match_operand:BLK 0 "memory_operand" "")
2068 (match_operand:BLK 1 "memory_operand" ""))
2069 (use (match_operand 2 "register_operand" ""))
2070 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2071 (clobber (match_operand 3 "register_operand" ""))]
2072 "reload_completed && TARGET_CPU_ZARCH"
2073 [(set (match_dup 3) (label_ref (match_dup 4)))
2075 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2076 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2077 (set (match_dup 0) (match_dup 1))
2078 (use (const_int 1))])]
2079 "operands[4] = gen_label_rtx ();")
2081 ; Move a block of arbitrary length.
2083 (define_expand "movmem_long"
2085 [(clobber (match_dup 2))
2086 (clobber (match_dup 3))
2087 (set (match_operand:BLK 0 "memory_operand" "")
2088 (match_operand:BLK 1 "memory_operand" ""))
2089 (use (match_operand 2 "general_operand" ""))
2091 (clobber (reg:CC CC_REGNUM))])]
2094 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2095 rtx reg0 = gen_reg_rtx (dword_mode);
2096 rtx reg1 = gen_reg_rtx (dword_mode);
2097 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2098 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2099 rtx len0 = gen_lowpart (Pmode, reg0);
2100 rtx len1 = gen_lowpart (Pmode, reg1);
2102 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2103 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2104 emit_move_insn (len0, operands[2]);
2106 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2107 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2108 emit_move_insn (len1, operands[2]);
2110 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2111 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2116 (define_insn "*movmem_long"
2117 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2118 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2119 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2120 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2123 (clobber (reg:CC CC_REGNUM))]
2125 "mvcle\t%0,%1,0\;jo\t.-4"
2126 [(set_attr "length" "8")
2127 (set_attr "type" "vs")])
2130 ; setmemM instruction pattern(s).
2133 (define_expand "setmem<mode>"
2134 [(set (match_operand:BLK 0 "memory_operand" "")
2135 (match_operand:QI 2 "general_operand" ""))
2136 (use (match_operand:GPR 1 "general_operand" ""))
2137 (match_operand 3 "" "")]
2139 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2141 ; Clear a block that is up to 256 bytes in length.
2142 ; The block length is taken as (operands[1] % 256) + 1.
2144 (define_expand "clrmem_short"
2146 [(set (match_operand:BLK 0 "memory_operand" "")
2148 (use (match_operand 1 "nonmemory_operand" ""))
2149 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2150 (clobber (match_dup 2))
2151 (clobber (reg:CC CC_REGNUM))])]
2153 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2155 (define_insn "*clrmem_short"
2156 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2158 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2159 (use (match_operand 2 "immediate_operand" "X,R,X"))
2160 (clobber (match_scratch 3 "=X,X,&a"))
2161 (clobber (reg:CC CC_REGNUM))]
2162 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2163 && GET_MODE (operands[3]) == Pmode"
2165 [(set_attr "type" "cs")])
2168 [(set (match_operand:BLK 0 "memory_operand" "")
2170 (use (match_operand 1 "const_int_operand" ""))
2171 (use (match_operand 2 "immediate_operand" ""))
2173 (clobber (reg:CC CC_REGNUM))]
2176 [(set (match_dup 0) (const_int 0))
2178 (clobber (reg:CC CC_REGNUM))])]
2179 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2182 [(set (match_operand:BLK 0 "memory_operand" "")
2184 (use (match_operand 1 "register_operand" ""))
2185 (use (match_operand 2 "memory_operand" ""))
2187 (clobber (reg:CC CC_REGNUM))]
2190 [(unspec [(match_dup 1) (match_dup 2)
2191 (const_int 0)] UNSPEC_EXECUTE)
2192 (set (match_dup 0) (const_int 0))
2194 (clobber (reg:CC CC_REGNUM))])]
2198 [(set (match_operand:BLK 0 "memory_operand" "")
2200 (use (match_operand 1 "register_operand" ""))
2201 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2202 (clobber (match_operand 2 "register_operand" ""))
2203 (clobber (reg:CC CC_REGNUM))]
2204 "reload_completed && TARGET_CPU_ZARCH"
2205 [(set (match_dup 2) (label_ref (match_dup 3)))
2207 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2208 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2209 (set (match_dup 0) (const_int 0))
2211 (clobber (reg:CC CC_REGNUM))])]
2212 "operands[3] = gen_label_rtx ();")
2214 ; Initialize a block of arbitrary length with (operands[2] % 256).
2216 (define_expand "setmem_long"
2218 [(clobber (match_dup 1))
2219 (set (match_operand:BLK 0 "memory_operand" "")
2220 (match_operand 2 "setmem_operand" ""))
2221 (use (match_operand 1 "general_operand" ""))
2223 (clobber (reg:CC CC_REGNUM))])]
2226 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2227 rtx reg0 = gen_reg_rtx (dword_mode);
2228 rtx reg1 = gen_reg_rtx (dword_mode);
2229 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2230 rtx len0 = gen_lowpart (Pmode, reg0);
2232 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2233 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2234 emit_move_insn (len0, operands[1]);
2236 emit_move_insn (reg1, const0_rtx);
2238 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2243 (define_insn "*setmem_long"
2244 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2245 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2246 (match_operand 2 "setmem_operand" "Y"))
2248 (use (match_operand:<DBL> 1 "register_operand" "d"))
2249 (clobber (reg:CC CC_REGNUM))]
2251 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2252 [(set_attr "length" "8")
2253 (set_attr "type" "vs")])
2256 ; cmpmemM instruction pattern(s).
2259 (define_expand "cmpmemsi"
2260 [(set (match_operand:SI 0 "register_operand" "")
2261 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2262 (match_operand:BLK 2 "memory_operand" "") ) )
2263 (use (match_operand:SI 3 "general_operand" ""))
2264 (use (match_operand:SI 4 "" ""))]
2266 "s390_expand_cmpmem (operands[0], operands[1],
2267 operands[2], operands[3]); DONE;")
2269 ; Compare a block that is up to 256 bytes in length.
2270 ; The block length is taken as (operands[2] % 256) + 1.
2272 (define_expand "cmpmem_short"
2274 [(set (reg:CCU CC_REGNUM)
2275 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2276 (match_operand:BLK 1 "memory_operand" "")))
2277 (use (match_operand 2 "nonmemory_operand" ""))
2278 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2279 (clobber (match_dup 3))])]
2281 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2283 (define_insn "*cmpmem_short"
2284 [(set (reg:CCU CC_REGNUM)
2285 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2286 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2287 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2288 (use (match_operand 3 "immediate_operand" "X,R,X"))
2289 (clobber (match_scratch 4 "=X,X,&a"))]
2290 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2291 && GET_MODE (operands[4]) == Pmode"
2293 [(set_attr "type" "cs")])
2296 [(set (reg:CCU CC_REGNUM)
2297 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2298 (match_operand:BLK 1 "memory_operand" "")))
2299 (use (match_operand 2 "const_int_operand" ""))
2300 (use (match_operand 3 "immediate_operand" ""))
2301 (clobber (scratch))]
2304 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2305 (use (match_dup 2))])]
2306 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2309 [(set (reg:CCU CC_REGNUM)
2310 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2311 (match_operand:BLK 1 "memory_operand" "")))
2312 (use (match_operand 2 "register_operand" ""))
2313 (use (match_operand 3 "memory_operand" ""))
2314 (clobber (scratch))]
2317 [(unspec [(match_dup 2) (match_dup 3)
2318 (const_int 0)] UNSPEC_EXECUTE)
2319 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2320 (use (const_int 1))])]
2324 [(set (reg:CCU CC_REGNUM)
2325 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2326 (match_operand:BLK 1 "memory_operand" "")))
2327 (use (match_operand 2 "register_operand" ""))
2328 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2329 (clobber (match_operand 3 "register_operand" ""))]
2330 "reload_completed && TARGET_CPU_ZARCH"
2331 [(set (match_dup 3) (label_ref (match_dup 4)))
2333 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2334 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2335 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2336 (use (const_int 1))])]
2337 "operands[4] = gen_label_rtx ();")
2339 ; Compare a block of arbitrary length.
2341 (define_expand "cmpmem_long"
2343 [(clobber (match_dup 2))
2344 (clobber (match_dup 3))
2345 (set (reg:CCU CC_REGNUM)
2346 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2347 (match_operand:BLK 1 "memory_operand" "")))
2348 (use (match_operand 2 "general_operand" ""))
2349 (use (match_dup 3))])]
2352 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2353 rtx reg0 = gen_reg_rtx (dword_mode);
2354 rtx reg1 = gen_reg_rtx (dword_mode);
2355 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2356 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2357 rtx len0 = gen_lowpart (Pmode, reg0);
2358 rtx len1 = gen_lowpart (Pmode, reg1);
2360 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2361 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2362 emit_move_insn (len0, operands[2]);
2364 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2365 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2366 emit_move_insn (len1, operands[2]);
2368 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2369 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2374 (define_insn "*cmpmem_long"
2375 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2376 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2377 (set (reg:CCU CC_REGNUM)
2378 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2379 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2381 (use (match_dup 3))]
2383 "clcle\t%0,%1,0\;jo\t.-4"
2384 [(set_attr "length" "8")
2385 (set_attr "type" "vs")])
2387 ; Convert CCUmode condition code to integer.
2388 ; Result is zero if EQ, positive if LTU, negative if GTU.
2390 (define_insn_and_split "cmpint"
2391 [(set (match_operand:SI 0 "register_operand" "=d")
2392 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2394 (clobber (reg:CC CC_REGNUM))]
2398 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2400 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2401 (clobber (reg:CC CC_REGNUM))])])
2403 (define_insn_and_split "*cmpint_cc"
2404 [(set (reg CC_REGNUM)
2405 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2408 (set (match_operand:SI 0 "register_operand" "=d")
2409 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2410 "s390_match_ccmode (insn, CCSmode)"
2412 "&& reload_completed"
2413 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2415 [(set (match_dup 2) (match_dup 3))
2416 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2418 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2419 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2420 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2423 (define_insn_and_split "*cmpint_sign"
2424 [(set (match_operand:DI 0 "register_operand" "=d")
2425 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2427 (clobber (reg:CC CC_REGNUM))]
2430 "&& reload_completed"
2431 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2433 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2434 (clobber (reg:CC CC_REGNUM))])])
2436 (define_insn_and_split "*cmpint_sign_cc"
2437 [(set (reg CC_REGNUM)
2438 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2439 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2441 (const_int 32)) (const_int 32))
2443 (set (match_operand:DI 0 "register_operand" "=d")
2444 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2445 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2447 "&& reload_completed"
2448 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2450 [(set (match_dup 2) (match_dup 3))
2451 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2453 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2454 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2455 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2460 ;;- Conversion instructions.
2463 (define_insn "*sethighpartsi"
2464 [(set (match_operand:SI 0 "register_operand" "=d,d")
2465 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
2466 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2467 (clobber (reg:CC CC_REGNUM))]
2472 [(set_attr "op_type" "RS,RSY")])
2474 (define_insn "*sethighpartdi_64"
2475 [(set (match_operand:DI 0 "register_operand" "=d")
2476 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
2477 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
2478 (clobber (reg:CC CC_REGNUM))]
2481 [(set_attr "op_type" "RSY")])
2483 (define_insn "*sethighpartdi_31"
2484 [(set (match_operand:DI 0 "register_operand" "=d,d")
2485 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
2486 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2487 (clobber (reg:CC CC_REGNUM))]
2492 [(set_attr "op_type" "RS,RSY")])
2494 (define_insn_and_split "*extzv<mode>"
2495 [(set (match_operand:GPR 0 "register_operand" "=d")
2496 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2497 (match_operand 2 "const_int_operand" "n")
2499 (clobber (reg:CC CC_REGNUM))]
2500 "INTVAL (operands[2]) > 0
2501 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2503 "&& reload_completed"
2505 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2506 (clobber (reg:CC CC_REGNUM))])
2507 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
2509 int bitsize = INTVAL (operands[2]);
2510 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2511 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2513 operands[1] = adjust_address (operands[1], BLKmode, 0);
2514 set_mem_size (operands[1], GEN_INT (size));
2515 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2516 operands[3] = GEN_INT (mask);
2519 (define_insn_and_split "*extv<mode>"
2520 [(set (match_operand:GPR 0 "register_operand" "=d")
2521 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2522 (match_operand 2 "const_int_operand" "n")
2524 (clobber (reg:CC CC_REGNUM))]
2525 "INTVAL (operands[2]) > 0
2526 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2528 "&& reload_completed"
2530 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2531 (clobber (reg:CC CC_REGNUM))])
2533 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2534 (clobber (reg:CC CC_REGNUM))])]
2536 int bitsize = INTVAL (operands[2]);
2537 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2538 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2540 operands[1] = adjust_address (operands[1], BLKmode, 0);
2541 set_mem_size (operands[1], GEN_INT (size));
2542 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2543 operands[3] = GEN_INT (mask);
2547 ; insv instruction patterns
2550 (define_expand "insv"
2551 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
2552 (match_operand 1 "const_int_operand" "")
2553 (match_operand 2 "const_int_operand" ""))
2554 (match_operand 3 "general_operand" ""))]
2557 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
2562 (define_insn "*insv<mode>_mem_reg"
2563 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
2564 (match_operand 1 "const_int_operand" "n,n")
2566 (match_operand:P 2 "register_operand" "d,d"))]
2567 "INTVAL (operands[1]) > 0
2568 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2569 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2571 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2573 operands[1] = GEN_INT ((1ul << size) - 1);
2574 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
2575 : "stcmy\t%2,%1,%S0";
2577 [(set_attr "op_type" "RS,RSY")])
2579 (define_insn "*insvdi_mem_reghigh"
2580 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
2581 (match_operand 1 "const_int_operand" "n")
2583 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
2586 && INTVAL (operands[1]) > 0
2587 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2588 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2590 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2592 operands[1] = GEN_INT ((1ul << size) - 1);
2593 return "stcmh\t%2,%1,%S0";
2595 [(set_attr "op_type" "RSY")])
2597 (define_insn "*insv<mode>_reg_imm"
2598 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2600 (match_operand 1 "const_int_operand" "n"))
2601 (match_operand 2 "const_int_operand" "n"))]
2603 && INTVAL (operands[1]) >= 0
2604 && INTVAL (operands[1]) < BITS_PER_WORD
2605 && INTVAL (operands[1]) % 16 == 0"
2607 switch (BITS_PER_WORD - INTVAL (operands[1]))
2609 case 64: return "iihh\t%0,%x2"; break;
2610 case 48: return "iihl\t%0,%x2"; break;
2611 case 32: return "iilh\t%0,%x2"; break;
2612 case 16: return "iill\t%0,%x2"; break;
2613 default: gcc_unreachable();
2616 [(set_attr "op_type" "RI")])
2618 (define_insn "*insv<mode>_reg_extimm"
2619 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2621 (match_operand 1 "const_int_operand" "n"))
2622 (match_operand 2 "const_int_operand" "n"))]
2624 && INTVAL (operands[1]) >= 0
2625 && INTVAL (operands[1]) < BITS_PER_WORD
2626 && INTVAL (operands[1]) % 32 == 0"
2628 switch (BITS_PER_WORD - INTVAL (operands[1]))
2630 case 64: return "iihf\t%0,%o2"; break;
2631 case 32: return "iilf\t%0,%o2"; break;
2632 default: gcc_unreachable();
2635 [(set_attr "op_type" "RIL")])
2638 ; extendsidi2 instruction pattern(s).
2641 (define_expand "extendsidi2"
2642 [(set (match_operand:DI 0 "register_operand" "")
2643 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2648 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2649 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2650 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2651 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2656 (define_insn "*extendsidi2"
2657 [(set (match_operand:DI 0 "register_operand" "=d,d")
2658 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2663 [(set_attr "op_type" "RRE,RXY")])
2666 ; extend(hi|qi)di2 instruction pattern(s).
2669 (define_expand "extend<mode>di2"
2670 [(set (match_operand:DI 0 "register_operand" "")
2671 (sign_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2676 rtx tmp = gen_reg_rtx (SImode);
2677 emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
2678 emit_insn (gen_extendsidi2 (operands[0], tmp));
2681 else if (!TARGET_EXTIMM)
2683 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
2684 GET_MODE_BITSIZE (<MODE>mode));
2685 operands[1] = gen_lowpart (DImode, operands[1]);
2686 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2687 emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
2692 (define_insn "*extendhidi2_extimm"
2693 [(set (match_operand:DI 0 "register_operand" "=d,d")
2694 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2695 "TARGET_64BIT && TARGET_EXTIMM"
2699 [(set_attr "op_type" "RRE,RXY")])
2701 (define_insn "*extendhidi2"
2702 [(set (match_operand:DI 0 "register_operand" "=d")
2703 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2706 [(set_attr "op_type" "RXY")])
2708 (define_insn "*extendqidi2_extimm"
2709 [(set (match_operand:DI 0 "register_operand" "=d,d")
2710 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2711 "TARGET_64BIT && TARGET_EXTIMM"
2715 [(set_attr "op_type" "RRE,RXY")])
2717 (define_insn "*extendqidi2"
2718 [(set (match_operand:DI 0 "register_operand" "=d")
2719 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2720 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2722 [(set_attr "op_type" "RXY")])
2724 (define_insn_and_split "*extendqidi2_short_displ"
2725 [(set (match_operand:DI 0 "register_operand" "=d")
2726 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2727 (clobber (reg:CC CC_REGNUM))]
2728 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2730 "&& reload_completed"
2732 [(set (match_dup 0) (unspec:DI [(match_dup 1) (const_int 8)] UNSPEC_ICM))
2733 (clobber (reg:CC CC_REGNUM))])
2735 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2736 (clobber (reg:CC CC_REGNUM))])]
2738 operands[1] = adjust_address (operands[1], BLKmode, 0);
2739 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
2743 ; extend(hi|qi)si2 instruction pattern(s).
2746 (define_expand "extend<mode>si2"
2747 [(set (match_operand:SI 0 "register_operand" "")
2748 (sign_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2753 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
2754 GET_MODE_BITSIZE(<MODE>mode));
2755 operands[1] = gen_lowpart (SImode, operands[1]);
2756 emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
2757 emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
2762 (define_insn "*extendhisi2_extimm"
2763 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2764 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
2770 [(set_attr "op_type" "RRE,RX,RXY")])
2772 (define_insn "*extendhisi2"
2773 [(set (match_operand:SI 0 "register_operand" "=d,d")
2774 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2779 [(set_attr "op_type" "RX,RXY")])
2781 (define_insn "*extendqisi2_extimm"
2782 [(set (match_operand:SI 0 "register_operand" "=d,d")
2783 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2788 [(set_attr "op_type" "RRE,RXY")])
2790 (define_insn "*extendqisi2"
2791 [(set (match_operand:SI 0 "register_operand" "=d")
2792 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2793 "TARGET_LONG_DISPLACEMENT && !TARGET_EXTIMM"
2795 [(set_attr "op_type" "RXY")])
2797 (define_insn_and_split "*extendqisi2_short_displ"
2798 [(set (match_operand:SI 0 "register_operand" "=d")
2799 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2800 (clobber (reg:CC CC_REGNUM))]
2801 "!TARGET_LONG_DISPLACEMENT"
2803 "&& reload_completed"
2805 [(set (match_dup 0) (unspec:SI [(match_dup 1) (const_int 8)] UNSPEC_ICM))
2806 (clobber (reg:CC CC_REGNUM))])
2808 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2809 (clobber (reg:CC CC_REGNUM))])]
2811 operands[1] = adjust_address (operands[1], BLKmode, 0);
2812 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
2816 ; extendqihi2 instruction pattern(s).
2821 ; zero_extendsidi2 instruction pattern(s).
2824 (define_expand "zero_extendsidi2"
2825 [(set (match_operand:DI 0 "register_operand" "")
2826 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2831 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2832 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2833 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2838 (define_insn "*zero_extendsidi2"
2839 [(set (match_operand:DI 0 "register_operand" "=d,d")
2840 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2845 [(set_attr "op_type" "RRE,RXY")])
2848 ; zero_extend(hi|qi)di2 instruction pattern(s).
2851 (define_expand "zero_extend<mode>di2"
2852 [(set (match_operand:DI 0 "register_operand" "")
2853 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2858 rtx tmp = gen_reg_rtx (SImode);
2859 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2860 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2863 else if (!TARGET_EXTIMM)
2865 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2866 GET_MODE_BITSIZE(<MODE>mode));
2867 operands[1] = gen_lowpart (DImode, operands[1]);
2868 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2869 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2874 (define_insn "*zero_extend<mode>di2_extimm"
2875 [(set (match_operand:DI 0 "register_operand" "=d,d")
2876 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
2877 "TARGET_64BIT && TARGET_EXTIMM"
2881 [(set_attr "op_type" "RRE,RXY")])
2883 (define_insn "*zero_extend<mode>di2"
2884 [(set (match_operand:DI 0 "register_operand" "=d")
2885 (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
2886 "TARGET_64BIT && !TARGET_EXTIMM"
2888 [(set_attr "op_type" "RXY")])
2891 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2894 (define_insn "*llgt_sidi"
2895 [(set (match_operand:DI 0 "register_operand" "=d")
2896 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2897 (const_int 2147483647)))]
2900 [(set_attr "op_type" "RXE")])
2902 (define_insn_and_split "*llgt_sidi_split"
2903 [(set (match_operand:DI 0 "register_operand" "=d")
2904 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2905 (const_int 2147483647)))
2906 (clobber (reg:CC CC_REGNUM))]
2909 "&& reload_completed"
2911 (and:DI (subreg:DI (match_dup 1) 0)
2912 (const_int 2147483647)))]
2915 (define_insn "*llgt_sisi"
2916 [(set (match_operand:SI 0 "register_operand" "=d,d")
2917 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2918 (const_int 2147483647)))]
2923 [(set_attr "op_type" "RRE,RXE")])
2925 (define_insn "*llgt_didi"
2926 [(set (match_operand:DI 0 "register_operand" "=d,d")
2927 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2928 (const_int 2147483647)))]
2933 [(set_attr "op_type" "RRE,RXE")])
2936 [(set (match_operand:GPR 0 "register_operand" "")
2937 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2938 (const_int 2147483647)))
2939 (clobber (reg:CC CC_REGNUM))]
2940 "TARGET_ZARCH && reload_completed"
2942 (and:GPR (match_dup 1)
2943 (const_int 2147483647)))]
2947 ; zero_extend(hi|qi)si2 instruction pattern(s).
2950 (define_expand "zero_extend<mode>si2"
2951 [(set (match_operand:SI 0 "register_operand" "")
2952 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2957 operands[1] = gen_lowpart (SImode, operands[1]);
2958 emit_insn (gen_andsi3 (operands[0], operands[1],
2959 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2964 (define_insn "*zero_extend<mode>si2_extimm"
2965 [(set (match_operand:SI 0 "register_operand" "=d,d")
2966 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
2971 [(set_attr "op_type" "RRE,RXY")])
2973 (define_insn "*zero_extend<mode>si2_64"
2974 [(set (match_operand:SI 0 "register_operand" "=d")
2975 (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
2976 "TARGET_ZARCH && !TARGET_EXTIMM"
2978 [(set_attr "op_type" "RXY")])
2980 (define_insn_and_split "*zero_extendhisi2_31"
2981 [(set (match_operand:SI 0 "register_operand" "=&d")
2982 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2983 (clobber (reg:CC CC_REGNUM))]
2986 "&& reload_completed"
2987 [(set (match_dup 0) (const_int 0))
2989 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2990 (clobber (reg:CC CC_REGNUM))])]
2991 "operands[2] = gen_lowpart (HImode, operands[0]);")
2993 (define_insn_and_split "*zero_extendqisi2_31"
2994 [(set (match_operand:SI 0 "register_operand" "=&d")
2995 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2998 "&& reload_completed"
2999 [(set (match_dup 0) (const_int 0))
3000 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3001 "operands[2] = gen_lowpart (QImode, operands[0]);")
3004 ; zero_extendqihi2 instruction pattern(s).
3007 (define_expand "zero_extendqihi2"
3008 [(set (match_operand:HI 0 "register_operand" "")
3009 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3010 "TARGET_ZARCH && !TARGET_EXTIMM"
3012 operands[1] = gen_lowpart (HImode, operands[1]);
3013 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3017 (define_insn "*zero_extendqihi2_64"
3018 [(set (match_operand:HI 0 "register_operand" "=d")
3019 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3020 "TARGET_ZARCH && !TARGET_EXTIMM"
3022 [(set_attr "op_type" "RXY")])
3024 (define_insn_and_split "*zero_extendqihi2_31"
3025 [(set (match_operand:HI 0 "register_operand" "=&d")
3026 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3029 "&& reload_completed"
3030 [(set (match_dup 0) (const_int 0))
3031 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3032 "operands[2] = gen_lowpart (QImode, operands[0]);")
3036 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
3039 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
3040 [(set (match_operand:GPR 0 "register_operand" "")
3041 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
3042 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3044 rtx label1 = gen_label_rtx ();
3045 rtx label2 = gen_label_rtx ();
3046 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
3047 REAL_VALUE_TYPE cmp, sub;
3049 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
3050 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
3051 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
3053 emit_insn (gen_cmp<FPR:mode> (operands[1],
3054 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
3055 emit_jump_insn (gen_blt (label1));
3056 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
3057 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
3058 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
3062 emit_label (label1);
3063 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
3064 operands[1], GEN_INT(5)));
3065 emit_label (label2);
3069 (define_expand "fix_trunc<FPR:mode>di2"
3070 [(set (match_operand:DI 0 "register_operand" "")
3071 (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
3072 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3074 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
3075 emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
3080 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
3081 [(set (match_operand:GPR 0 "register_operand" "=d")
3082 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
3083 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3084 (clobber (reg:CC CC_REGNUM))]
3085 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3086 "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
3087 [(set_attr "op_type" "RRE")
3088 (set_attr "type" "ftoi")])
3091 ; fix_truncdfsi2 instruction pattern(s).
3094 (define_expand "fix_truncdfsi2"
3095 [(set (match_operand:SI 0 "register_operand" "")
3096 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
3099 if (TARGET_IBM_FLOAT)
3101 /* This is the algorithm from POP chapter A.5.7.2. */
3103 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3104 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
3105 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
3107 operands[1] = force_reg (DFmode, operands[1]);
3108 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
3109 two31r, two32, temp));
3113 operands[1] = force_reg (DFmode, operands[1]);
3114 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3120 (define_insn "fix_truncdfsi2_ibm"
3121 [(set (match_operand:SI 0 "register_operand" "=d")
3122 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
3123 (use (match_operand:DI 2 "immediate_operand" "m"))
3124 (use (match_operand:DI 3 "immediate_operand" "m"))
3125 (use (match_operand:BLK 4 "memory_operand" "m"))
3126 (clobber (reg:CC CC_REGNUM))]
3127 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3129 output_asm_insn ("sd\t%1,%2", operands);
3130 output_asm_insn ("aw\t%1,%3", operands);
3131 output_asm_insn ("std\t%1,%4", operands);
3132 output_asm_insn ("xi\t%N4,128", operands);
3135 [(set_attr "length" "20")])
3138 ; fix_truncsfsi2 instruction pattern(s).
3141 (define_expand "fix_truncsfsi2"
3142 [(set (match_operand:SI 0 "register_operand" "")
3143 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
3146 if (TARGET_IBM_FLOAT)
3148 /* Convert to DFmode and then use the POP algorithm. */
3149 rtx temp = gen_reg_rtx (DFmode);
3150 emit_insn (gen_extendsfdf2 (temp, operands[1]));
3151 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3155 operands[1] = force_reg (SFmode, operands[1]);
3156 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3163 ; floatdi(df|sf)2 instruction pattern(s).
3166 (define_insn "floatdi<mode>2"
3167 [(set (match_operand:FPR 0 "register_operand" "=f")
3168 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
3169 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3171 [(set_attr "op_type" "RRE")
3172 (set_attr "type" "itof" )])
3175 ; floatsidf2 instruction pattern(s).
3178 (define_expand "floatsidf2"
3179 [(set (match_operand:DF 0 "register_operand" "")
3180 (float:DF (match_operand:SI 1 "register_operand" "")))]
3183 if (TARGET_IBM_FLOAT)
3185 /* This is the algorithm from POP chapter A.5.7.1. */
3187 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3188 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3190 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3195 (define_insn "floatsidf2_ieee"
3196 [(set (match_operand:DF 0 "register_operand" "=f")
3197 (float:DF (match_operand:SI 1 "register_operand" "d")))]
3198 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3200 [(set_attr "op_type" "RRE")
3201 (set_attr "type" "itof" )])
3203 (define_insn "floatsidf2_ibm"
3204 [(set (match_operand:DF 0 "register_operand" "=f")
3205 (float:DF (match_operand:SI 1 "register_operand" "d")))
3206 (use (match_operand:DI 2 "immediate_operand" "m"))
3207 (use (match_operand:BLK 3 "memory_operand" "m"))
3208 (clobber (reg:CC CC_REGNUM))]
3209 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3211 output_asm_insn ("st\t%1,%N3", operands);
3212 output_asm_insn ("xi\t%N3,128", operands);
3213 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3214 output_asm_insn ("ld\t%0,%3", operands);
3217 [(set_attr "length" "20")])
3220 ; floatsisf2 instruction pattern(s).
3223 (define_expand "floatsisf2"
3224 [(set (match_operand:SF 0 "register_operand" "")
3225 (float:SF (match_operand:SI 1 "register_operand" "")))]
3228 if (TARGET_IBM_FLOAT)
3230 /* Use the POP algorithm to convert to DFmode and then truncate. */
3231 rtx temp = gen_reg_rtx (DFmode);
3232 emit_insn (gen_floatsidf2 (temp, operands[1]));
3233 emit_insn (gen_truncdfsf2 (operands[0], temp));
3238 (define_insn "floatsisf2_ieee"
3239 [(set (match_operand:SF 0 "register_operand" "=f")
3240 (float:SF (match_operand:SI 1 "register_operand" "d")))]
3241 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3243 [(set_attr "op_type" "RRE")
3244 (set_attr "type" "itof" )])
3247 ; truncdfsf2 instruction pattern(s).
3250 (define_expand "truncdfsf2"
3251 [(set (match_operand:SF 0 "register_operand" "")
3252 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3256 (define_insn "truncdfsf2_ieee"
3257 [(set (match_operand:SF 0 "register_operand" "=f")
3258 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3259 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3261 [(set_attr "op_type" "RRE")])
3263 (define_insn "truncdfsf2_ibm"
3264 [(set (match_operand:SF 0 "register_operand" "=f,f")
3265 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3266 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3270 [(set_attr "op_type" "RR,RX")
3271 (set_attr "type" "floadsf")])
3274 ; extendsfdf2 instruction pattern(s).
3277 (define_expand "extendsfdf2"
3278 [(set (match_operand:DF 0 "register_operand" "")
3279 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3282 if (TARGET_IBM_FLOAT)
3284 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3289 (define_insn "extendsfdf2_ieee"
3290 [(set (match_operand:DF 0 "register_operand" "=f,f")
3291 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3292 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3296 [(set_attr "op_type" "RRE,RXE")
3297 (set_attr "type" "floadsf")])
3299 (define_insn "extendsfdf2_ibm"
3300 [(set (match_operand:DF 0 "register_operand" "=f,f")
3301 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3302 (clobber (reg:CC CC_REGNUM))]
3303 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3305 sdr\t%0,%0\;ler\t%0,%1
3306 sdr\t%0,%0\;le\t%0,%1"
3307 [(set_attr "length" "4,6")
3308 (set_attr "type" "floadsf")])
3312 ;; ARITHMETIC OPERATIONS
3314 ; arithmetic operations set the ConditionCode,
3315 ; because of unpredictable Bits in Register for Halfword and Byte
3316 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3319 ;;- Add instructions.
3323 ; addti3 instruction pattern(s).
3326 (define_insn_and_split "addti3"
3327 [(set (match_operand:TI 0 "register_operand" "=&d")
3328 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3329 (match_operand:TI 2 "general_operand" "do") ) )
3330 (clobber (reg:CC CC_REGNUM))]
3333 "&& reload_completed"
3335 [(set (reg:CCL1 CC_REGNUM)
3336 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3338 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3340 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3341 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3342 (clobber (reg:CC CC_REGNUM))])]
3343 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3344 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3345 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3346 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3347 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3348 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3351 ; adddi3 instruction pattern(s).
3354 (define_insn "*adddi3_sign"
3355 [(set (match_operand:DI 0 "register_operand" "=d,d")
3356 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3357 (match_operand:DI 1 "register_operand" "0,0")))
3358 (clobber (reg:CC CC_REGNUM))]
3363 [(set_attr "op_type" "RRE,RXY")])
3365 (define_insn "*adddi3_zero_cc"
3366 [(set (reg CC_REGNUM)
3367 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3368 (match_operand:DI 1 "register_operand" "0,0"))
3370 (set (match_operand:DI 0 "register_operand" "=d,d")
3371 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3372 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3376 [(set_attr "op_type" "RRE,RXY")])
3378 (define_insn "*adddi3_zero_cconly"
3379 [(set (reg CC_REGNUM)
3380 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3381 (match_operand:DI 1 "register_operand" "0,0"))
3383 (clobber (match_scratch:DI 0 "=d,d"))]
3384 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3388 [(set_attr "op_type" "RRE,RXY")])
3390 (define_insn "*adddi3_zero"
3391 [(set (match_operand:DI 0 "register_operand" "=d,d")
3392 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3393 (match_operand:DI 1 "register_operand" "0,0")))
3394 (clobber (reg:CC CC_REGNUM))]
3399 [(set_attr "op_type" "RRE,RXY")])
3401 (define_insn "*adddi3_imm_cc"
3402 [(set (reg CC_REGNUM)
3403 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
3404 (match_operand:DI 2 "const_int_operand" "K,Os"))
3406 (set (match_operand:DI 0 "register_operand" "=d,d")
3407 (plus:DI (match_dup 1) (match_dup 2)))]
3409 && s390_match_ccmode (insn, CCAmode)
3410 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3411 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))"
3415 [(set_attr "op_type" "RI,RIL")])
3417 (define_insn "*adddi3_carry1_cc"
3418 [(set (reg CC_REGNUM)
3419 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3420 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3422 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3423 (plus:DI (match_dup 1) (match_dup 2)))]
3424 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3430 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3432 (define_insn "*adddi3_carry1_cconly"
3433 [(set (reg CC_REGNUM)
3434 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3435 (match_operand:DI 2 "general_operand" "d,m"))
3437 (clobber (match_scratch:DI 0 "=d,d"))]
3438 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3442 [(set_attr "op_type" "RRE,RXY")])
3444 (define_insn "*adddi3_carry2_cc"
3445 [(set (reg CC_REGNUM)
3446 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3447 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3449 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3450 (plus:DI (match_dup 1) (match_dup 2)))]
3451 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3457 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3459 (define_insn "*adddi3_carry2_cconly"
3460 [(set (reg CC_REGNUM)
3461 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3462 (match_operand:DI 2 "general_operand" "d,m"))
3464 (clobber (match_scratch:DI 0 "=d,d"))]
3465 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3469 [(set_attr "op_type" "RRE,RXY")])
3471 (define_insn "*adddi3_cc"
3472 [(set (reg CC_REGNUM)
3473 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3474 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3476 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3477 (plus:DI (match_dup 1) (match_dup 2)))]
3478 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3484 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3486 (define_insn "*adddi3_cconly"
3487 [(set (reg CC_REGNUM)
3488 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3489 (match_operand:DI 2 "general_operand" "d,m"))
3491 (clobber (match_scratch:DI 0 "=d,d"))]
3492 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3496 [(set_attr "op_type" "RRE,RXY")])
3498 (define_insn "*adddi3_cconly2"
3499 [(set (reg CC_REGNUM)
3500 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3501 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3502 (clobber (match_scratch:DI 0 "=d,d"))]
3503 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3507 [(set_attr "op_type" "RRE,RXY")])
3509 (define_insn "*adddi3_64"
3510 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d")
3511 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0")
3512 (match_operand:DI 2 "general_operand" "d,K,Op,On,m") ) )
3513 (clobber (reg:CC CC_REGNUM))]
3521 [(set_attr "op_type" "RRE,RI,RIL,RIL,RXY")])
3523 (define_insn_and_split "*adddi3_31z"
3524 [(set (match_operand:DI 0 "register_operand" "=&d")
3525 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3526 (match_operand:DI 2 "general_operand" "do") ) )
3527 (clobber (reg:CC CC_REGNUM))]
3528 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3530 "&& reload_completed"
3532 [(set (reg:CCL1 CC_REGNUM)
3533 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3535 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3537 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3538 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3539 (clobber (reg:CC CC_REGNUM))])]
3540 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3541 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3542 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3543 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3544 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3545 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3547 (define_insn_and_split "*adddi3_31"
3548 [(set (match_operand:DI 0 "register_operand" "=&d")
3549 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3550 (match_operand:DI 2 "general_operand" "do") ) )
3551 (clobber (reg:CC CC_REGNUM))]
3554 "&& reload_completed"
3556 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3557 (clobber (reg:CC CC_REGNUM))])
3559 [(set (reg:CCL1 CC_REGNUM)
3560 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3562 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3564 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3566 (label_ref (match_dup 9))))
3568 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3569 (clobber (reg:CC CC_REGNUM))])
3571 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3572 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3573 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3574 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3575 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3576 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3577 operands[9] = gen_label_rtx ();")
3579 (define_expand "adddi3"
3581 [(set (match_operand:DI 0 "register_operand" "")
3582 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3583 (match_operand:DI 2 "general_operand" "")))
3584 (clobber (reg:CC CC_REGNUM))])]
3589 ; addsi3 instruction pattern(s).
3592 (define_insn "*addsi3_imm_cc"
3593 [(set (reg CC_REGNUM)
3594 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
3595 (match_operand:SI 2 "const_int_operand" "K,Os"))
3597 (set (match_operand:SI 0 "register_operand" "=d,d")
3598 (plus:SI (match_dup 1) (match_dup 2)))]
3599 "s390_match_ccmode (insn, CCAmode)
3600 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3601 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
3602 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << 31)"
3606 [(set_attr "op_type" "RI,RIL")])
3608 (define_insn "*addsi3_carry1_cc"
3609 [(set (reg CC_REGNUM)
3610 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3611 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3613 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3614 (plus:SI (match_dup 1) (match_dup 2)))]
3615 "s390_match_ccmode (insn, CCL1mode)"
3621 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3623 (define_insn "*addsi3_carry1_cconly"
3624 [(set (reg CC_REGNUM)
3625 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3626 (match_operand:SI 2 "general_operand" "d,R,T"))
3628 (clobber (match_scratch:SI 0 "=d,d,d"))]
3629 "s390_match_ccmode (insn, CCL1mode)"
3634 [(set_attr "op_type" "RR,RX,RXY")])
3636 (define_insn "*addsi3_carry2_cc"
3637 [(set (reg CC_REGNUM)
3638 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3639 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3641 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3642 (plus:SI (match_dup 1) (match_dup 2)))]
3643 "s390_match_ccmode (insn, CCL1mode)"
3649 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3651 (define_insn "*addsi3_carry2_cconly"
3652 [(set (reg CC_REGNUM)
3653 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3654 (match_operand:SI 2 "general_operand" "d,R,T"))
3656 (clobber (match_scratch:SI 0 "=d,d,d"))]
3657 "s390_match_ccmode (insn, CCL1mode)"
3662 [(set_attr "op_type" "RR,RX,RXY")])
3664 (define_insn "*addsi3_cc"
3665 [(set (reg CC_REGNUM)
3666 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3667 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3669 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3670 (plus:SI (match_dup 1) (match_dup 2)))]
3671 "s390_match_ccmode (insn, CCLmode)"
3677 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3679 (define_insn "*addsi3_cconly"
3680 [(set (reg CC_REGNUM)
3681 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3682 (match_operand:SI 2 "general_operand" "d,R,T"))
3684 (clobber (match_scratch:SI 0 "=d,d,d"))]
3685 "s390_match_ccmode (insn, CCLmode)"
3690 [(set_attr "op_type" "RR,RX,RXY")])
3692 (define_insn "*addsi3_cconly2"
3693 [(set (reg CC_REGNUM)
3694 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3695 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3696 (clobber (match_scratch:SI 0 "=d,d,d"))]
3697 "s390_match_ccmode (insn, CCLmode)"
3702 [(set_attr "op_type" "RR,RX,RXY")])
3704 (define_insn "*addsi3_sign"
3705 [(set (match_operand:SI 0 "register_operand" "=d,d")
3706 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3707 (match_operand:SI 1 "register_operand" "0,0")))
3708 (clobber (reg:CC CC_REGNUM))]
3713 [(set_attr "op_type" "RX,RXY")])
3715 (define_insn "addsi3"
3716 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
3717 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
3718 (match_operand:SI 2 "general_operand" "d,K,Os,R,T")))
3719 (clobber (reg:CC CC_REGNUM))]
3727 [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
3730 ; add(df|sf)3 instruction pattern(s).
3733 (define_expand "add<mode>3"
3735 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3736 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3737 (match_operand:FPR 2 "general_operand" "f,R")))
3738 (clobber (reg:CC CC_REGNUM))])]
3742 (define_insn "*add<mode>3"
3743 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3744 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3745 (match_operand:FPR 2 "general_operand" "f,R")))
3746 (clobber (reg:CC CC_REGNUM))]
3747 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3751 [(set_attr "op_type" "RRE,RXE")
3752 (set_attr "type" "fsimp<mode>")])
3754 (define_insn "*add<mode>3_cc"
3755 [(set (reg CC_REGNUM)
3756 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3757 (match_operand:FPR 2 "general_operand" "f,R"))
3758 (match_operand:FPR 3 "const0_operand" "")))
3759 (set (match_operand:FPR 0 "register_operand" "=f,f")
3760 (plus:FPR (match_dup 1) (match_dup 2)))]
3761 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3765 [(set_attr "op_type" "RRE,RXE")
3766 (set_attr "type" "fsimp<mode>")])
3768 (define_insn "*add<mode>3_cconly"
3769 [(set (reg CC_REGNUM)
3770 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3771 (match_operand:FPR 2 "general_operand" "f,R"))
3772 (match_operand:FPR 3 "const0_operand" "")))
3773 (clobber (match_scratch:FPR 0 "=f,f"))]
3774 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3778 [(set_attr "op_type" "RRE,RXE")
3779 (set_attr "type" "fsimp<mode>")])
3781 (define_insn "*add<mode>3_ibm"
3782 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3783 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3784 (match_operand:FPR 2 "general_operand" "f,R")))
3785 (clobber (reg:CC CC_REGNUM))]
3786 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3790 [(set_attr "op_type" "RR,RX")
3791 (set_attr "type" "fsimp<mode>")])
3795 ;;- Subtract instructions.
3799 ; subti3 instruction pattern(s).
3802 (define_insn_and_split "subti3"
3803 [(set (match_operand:TI 0 "register_operand" "=&d")
3804 (minus:TI (match_operand:TI 1 "register_operand" "0")
3805 (match_operand:TI 2 "general_operand" "do") ) )
3806 (clobber (reg:CC CC_REGNUM))]
3809 "&& reload_completed"
3811 [(set (reg:CCL2 CC_REGNUM)
3812 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3814 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3816 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3817 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3818 (clobber (reg:CC CC_REGNUM))])]
3819 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3820 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3821 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3822 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3823 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3824 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3827 ; subdi3 instruction pattern(s).
3830 (define_insn "*subdi3_sign"
3831 [(set (match_operand:DI 0 "register_operand" "=d,d")
3832 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3833 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3834 (clobber (reg:CC CC_REGNUM))]
3839 [(set_attr "op_type" "RRE,RXY")])
3841 (define_insn "*subdi3_zero_cc"
3842 [(set (reg CC_REGNUM)
3843 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3844 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3846 (set (match_operand:DI 0 "register_operand" "=d,d")
3847 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3848 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3852 [(set_attr "op_type" "RRE,RXY")])
3854 (define_insn "*subdi3_zero_cconly"
3855 [(set (reg CC_REGNUM)
3856 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3857 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3859 (clobber (match_scratch:DI 0 "=d,d"))]
3860 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3864 [(set_attr "op_type" "RRE,RXY")])
3866 (define_insn "*subdi3_zero"
3867 [(set (match_operand:DI 0 "register_operand" "=d,d")
3868 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3869 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3870 (clobber (reg:CC CC_REGNUM))]
3875 [(set_attr "op_type" "RRE,RXY")])
3877 (define_insn "*subdi3_borrow_cc"
3878 [(set (reg CC_REGNUM)
3879 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3880 (match_operand:DI 2 "general_operand" "d,m"))
3882 (set (match_operand:DI 0 "register_operand" "=d,d")
3883 (minus:DI (match_dup 1) (match_dup 2)))]
3884 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3888 [(set_attr "op_type" "RRE,RXY")])
3890 (define_insn "*subdi3_borrow_cconly"
3891 [(set (reg CC_REGNUM)
3892 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3893 (match_operand:DI 2 "general_operand" "d,m"))
3895 (clobber (match_scratch:DI 0 "=d,d"))]
3896 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3900 [(set_attr "op_type" "RRE,RXY")])
3902 (define_insn "*subdi3_cc"
3903 [(set (reg CC_REGNUM)
3904 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3905 (match_operand:DI 2 "general_operand" "d,m"))
3907 (set (match_operand:DI 0 "register_operand" "=d,d")
3908 (minus:DI (match_dup 1) (match_dup 2)))]
3909 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3913 [(set_attr "op_type" "RRE,RXY")])
3915 (define_insn "*subdi3_cc2"
3916 [(set (reg CC_REGNUM)
3917 (compare (match_operand:DI 1 "register_operand" "0,0")
3918 (match_operand:DI 2 "general_operand" "d,m")))
3919 (set (match_operand:DI 0 "register_operand" "=d,d")
3920 (minus:DI (match_dup 1) (match_dup 2)))]
3921 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3925 [(set_attr "op_type" "RRE,RXY")])
3927 (define_insn "*subdi3_cconly"
3928 [(set (reg CC_REGNUM)
3929 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3930 (match_operand:DI 2 "general_operand" "d,m"))
3932 (clobber (match_scratch:DI 0 "=d,d"))]
3933 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3937 [(set_attr "op_type" "RRE,RXY")])
3939 (define_insn "*subdi3_cconly2"
3940 [(set (reg CC_REGNUM)
3941 (compare (match_operand:DI 1 "register_operand" "0,0")
3942 (match_operand:DI 2 "general_operand" "d,m")))
3943 (clobber (match_scratch:DI 0 "=d,d"))]
3944 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3948 [(set_attr "op_type" "RRE,RXY")])
3950 (define_insn "*subdi3_64"
3951 [(set (match_operand:DI 0 "register_operand" "=d,d")
3952 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3953 (match_operand:DI 2 "general_operand" "d,m") ) )
3954 (clobber (reg:CC CC_REGNUM))]
3959 [(set_attr "op_type" "RRE,RRE")])
3961 (define_insn_and_split "*subdi3_31z"
3962 [(set (match_operand:DI 0 "register_operand" "=&d")
3963 (minus:DI (match_operand:DI 1 "register_operand" "0")
3964 (match_operand:DI 2 "general_operand" "do") ) )
3965 (clobber (reg:CC CC_REGNUM))]
3966 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3968 "&& reload_completed"
3970 [(set (reg:CCL2 CC_REGNUM)
3971 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3973 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3975 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3976 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3977 (clobber (reg:CC CC_REGNUM))])]
3978 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3979 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3980 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3981 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3982 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3983 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3985 (define_insn_and_split "*subdi3_31"
3986 [(set (match_operand:DI 0 "register_operand" "=&d")
3987 (minus:DI (match_operand:DI 1 "register_operand" "0")
3988 (match_operand:DI 2 "general_operand" "do") ) )
3989 (clobber (reg:CC CC_REGNUM))]
3992 "&& reload_completed"
3994 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3995 (clobber (reg:CC CC_REGNUM))])
3997 [(set (reg:CCL2 CC_REGNUM)
3998 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4000 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4002 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4004 (label_ref (match_dup 9))))
4006 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4007 (clobber (reg:CC CC_REGNUM))])
4009 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4010 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4011 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4012 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4013 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4014 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4015 operands[9] = gen_label_rtx ();")
4017 (define_expand "subdi3"
4019 [(set (match_operand:DI 0 "register_operand" "")
4020 (minus:DI (match_operand:DI 1 "register_operand" "")
4021 (match_operand:DI 2 "general_operand" "")))
4022 (clobber (reg:CC CC_REGNUM))])]
4027 ; subsi3 instruction pattern(s).
4030 (define_insn "*subsi3_borrow_cc"
4031 [(set (reg CC_REGNUM)
4032 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4033 (match_operand:SI 2 "general_operand" "d,R,T"))
4035 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4036 (minus:SI (match_dup 1) (match_dup 2)))]
4037 "s390_match_ccmode (insn, CCL2mode)"
4042 [(set_attr "op_type" "RR,RX,RXY")])
4044 (define_insn "*subsi3_borrow_cconly"
4045 [(set (reg CC_REGNUM)
4046 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4047 (match_operand:SI 2 "general_operand" "d,R,T"))
4049 (clobber (match_scratch:SI 0 "=d,d,d"))]
4050 "s390_match_ccmode (insn, CCL2mode)"
4055 [(set_attr "op_type" "RR,RX,RXY")])
4057 (define_insn "*subsi3_cc"
4058 [(set (reg CC_REGNUM)
4059 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4060 (match_operand:SI 2 "general_operand" "d,R,T"))
4062 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4063 (minus:SI (match_dup 1) (match_dup 2)))]
4064 "s390_match_ccmode (insn, CCLmode)"
4069 [(set_attr "op_type" "RR,RX,RXY")])
4071 (define_insn "*subsi3_cc2"
4072 [(set (reg CC_REGNUM)
4073 (compare (match_operand:SI 1 "register_operand" "0,0,0")
4074 (match_operand:SI 2 "general_operand" "d,R,T")))
4075 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4076 (minus:SI (match_dup 1) (match_dup 2)))]
4077 "s390_match_ccmode (insn, CCL3mode)"
4082 [(set_attr "op_type" "RR,RX,RXY")])
4084 (define_insn "*subsi3_cconly"
4085 [(set (reg CC_REGNUM)
4086 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4087 (match_operand:SI 2 "general_operand" "d,R,T"))
4089 (clobber (match_scratch:SI 0 "=d,d,d"))]
4090 "s390_match_ccmode (insn, CCLmode)"
4095 [(set_attr "op_type" "RR,RX,RXY")])
4097 (define_insn "*subsi3_cconly2"
4098 [(set (reg CC_REGNUM)
4099 (compare (match_operand:SI 1 "register_operand" "0,0,0")
4100 (match_operand:SI 2 "general_operand" "d,R,T")))
4101 (clobber (match_scratch:SI 0 "=d,d,d"))]
4102 "s390_match_ccmode (insn, CCL3mode)"
4107 [(set_attr "op_type" "RR,RX,RXY")])
4109 (define_insn "*subsi3_sign"
4110 [(set (match_operand:SI 0 "register_operand" "=d,d")
4111 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4112 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4113 (clobber (reg:CC CC_REGNUM))]
4118 [(set_attr "op_type" "RX,RXY")])
4120 (define_insn "subsi3"
4121 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4122 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4123 (match_operand:SI 2 "general_operand" "d,R,T")))
4124 (clobber (reg:CC CC_REGNUM))]
4130 [(set_attr "op_type" "RR,RX,RXY")])
4134 ; sub(df|sf)3 instruction pattern(s).
4137 (define_expand "sub<mode>3"
4139 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4140 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4141 (match_operand:FPR 2 "general_operand" "f,R")))
4142 (clobber (reg:CC CC_REGNUM))])]
4146 (define_insn "*sub<mode>3"
4147 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4148 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4149 (match_operand:FPR 2 "general_operand" "f,R")))
4150 (clobber (reg:CC CC_REGNUM))]
4151 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4155 [(set_attr "op_type" "RRE,RXE")
4156 (set_attr "type" "fsimp<mode>")])
4158 (define_insn "*sub<mode>3_cc"
4159 [(set (reg CC_REGNUM)
4160 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4161 (match_operand:FPR 2 "general_operand" "f,R"))
4162 (match_operand:FPR 3 "const0_operand" "")))
4163 (set (match_operand:FPR 0 "register_operand" "=f,f")
4164 (minus:FPR (match_dup 1) (match_dup 2)))]
4165 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4169 [(set_attr "op_type" "RRE,RXE")
4170 (set_attr "type" "fsimp<mode>")])
4172 (define_insn "*sub<mode>3_cconly"
4173 [(set (reg CC_REGNUM)
4174 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4175 (match_operand:FPR 2 "general_operand" "f,R"))
4176 (match_operand:FPR 3 "const0_operand" "")))
4177 (clobber (match_scratch:FPR 0 "=f,f"))]
4178 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4182 [(set_attr "op_type" "RRE,RXE")
4183 (set_attr "type" "fsimp<mode>")])
4185 (define_insn "*sub<mode>3_ibm"
4186 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4187 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4188 (match_operand:FPR 2 "general_operand" "f,R")))
4189 (clobber (reg:CC CC_REGNUM))]
4190 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4194 [(set_attr "op_type" "RR,RX")
4195 (set_attr "type" "fsimp<mode>")])
4199 ;;- Conditional add/subtract instructions.
4203 ; add(di|si)cc instruction pattern(s).
4206 (define_insn "*add<mode>3_alc_cc"
4207 [(set (reg CC_REGNUM)
4209 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4210 (match_operand:GPR 2 "general_operand" "d,m"))
4211 (match_operand:GPR 3 "s390_alc_comparison" ""))
4213 (set (match_operand:GPR 0 "register_operand" "=d,d")
4214 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4215 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4219 [(set_attr "op_type" "RRE,RXY")])
4221 (define_insn "*add<mode>3_alc"
4222 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4223 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4224 (match_operand:GPR 2 "general_operand" "d,m"))
4225 (match_operand:GPR 3 "s390_alc_comparison" "")))
4226 (clobber (reg:CC CC_REGNUM))]
4231 [(set_attr "op_type" "RRE,RXY")])
4233 (define_insn "*sub<mode>3_slb_cc"
4234 [(set (reg CC_REGNUM)
4236 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4237 (match_operand:GPR 2 "general_operand" "d,m"))
4238 (match_operand:GPR 3 "s390_slb_comparison" ""))
4240 (set (match_operand:GPR 0 "register_operand" "=d,d")
4241 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4242 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4246 [(set_attr "op_type" "RRE,RXY")])
4248 (define_insn "*sub<mode>3_slb"
4249 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4250 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4251 (match_operand:GPR 2 "general_operand" "d,m"))
4252 (match_operand:GPR 3 "s390_slb_comparison" "")))
4253 (clobber (reg:CC CC_REGNUM))]
4258 [(set_attr "op_type" "RRE,RXY")])
4260 (define_expand "add<mode>cc"
4261 [(match_operand:GPR 0 "register_operand" "")
4262 (match_operand 1 "comparison_operator" "")
4263 (match_operand:GPR 2 "register_operand" "")
4264 (match_operand:GPR 3 "const_int_operand" "")]
4266 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4267 s390_compare_op0, s390_compare_op1,
4268 operands[0], operands[2],
4269 operands[3])) FAIL; DONE;")
4272 ; scond instruction pattern(s).
4275 (define_insn_and_split "*scond<mode>"
4276 [(set (match_operand:GPR 0 "register_operand" "=&d")
4277 (match_operand:GPR 1 "s390_alc_comparison" ""))
4278 (clobber (reg:CC CC_REGNUM))]
4281 "&& reload_completed"
4282 [(set (match_dup 0) (const_int 0))
4284 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
4286 (clobber (reg:CC CC_REGNUM))])]
4289 (define_insn_and_split "*scond<mode>_neg"
4290 [(set (match_operand:GPR 0 "register_operand" "=&d")
4291 (match_operand:GPR 1 "s390_slb_comparison" ""))
4292 (clobber (reg:CC CC_REGNUM))]
4295 "&& reload_completed"
4296 [(set (match_dup 0) (const_int 0))
4298 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
4300 (clobber (reg:CC CC_REGNUM))])
4302 [(set (match_dup 0) (neg:GPR (match_dup 0)))
4303 (clobber (reg:CC CC_REGNUM))])]
4307 (define_expand "s<code>"
4308 [(set (match_operand:SI 0 "register_operand" "")
4309 (SCOND (match_dup 0)
4312 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
4313 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4315 (define_expand "seq"
4317 [(set (match_operand:SI 0 "register_operand" "=d")
4319 (clobber (reg:CC CC_REGNUM))])
4321 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
4322 (clobber (reg:CC CC_REGNUM))])]
4325 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
4327 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
4328 PUT_MODE (operands[1], SImode);
4331 (define_insn_and_split "*sne"
4332 [(set (match_operand:SI 0 "register_operand" "=d")
4333 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4335 (clobber (reg:CC CC_REGNUM))]
4340 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4341 (clobber (reg:CC CC_REGNUM))])])
4345 ;;- Multiply instructions.
4349 ; muldi3 instruction pattern(s).
4352 (define_insn "*muldi3_sign"
4353 [(set (match_operand:DI 0 "register_operand" "=d,d")
4354 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4355 (match_operand:DI 1 "register_operand" "0,0")))]
4360 [(set_attr "op_type" "RRE,RXY")
4361 (set_attr "type" "imuldi")])
4363 (define_insn "muldi3"
4364 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4365 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4366 (match_operand:DI 2 "general_operand" "d,K,m")))]
4372 [(set_attr "op_type" "RRE,RI,RXY")
4373 (set_attr "type" "imuldi")])
4376 ; mulsi3 instruction pattern(s).
4379 (define_insn "*mulsi3_sign"
4380 [(set (match_operand:SI 0 "register_operand" "=d")
4381 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4382 (match_operand:SI 1 "register_operand" "0")))]
4385 [(set_attr "op_type" "RX")
4386 (set_attr "type" "imulhi")])
4388 (define_insn "mulsi3"
4389 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4390 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4391 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4398 [(set_attr "op_type" "RRE,RI,RX,RXY")
4399 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4402 ; mulsidi3 instruction pattern(s).
4405 (define_insn "mulsidi3"
4406 [(set (match_operand:DI 0 "register_operand" "=d,d")
4407 (mult:DI (sign_extend:DI
4408 (match_operand:SI 1 "register_operand" "%0,0"))
4410 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4415 [(set_attr "op_type" "RR,RX")
4416 (set_attr "type" "imulsi")])
4419 ; umulsidi3 instruction pattern(s).
4422 (define_insn "umulsidi3"
4423 [(set (match_operand:DI 0 "register_operand" "=d,d")
4424 (mult:DI (zero_extend:DI
4425 (match_operand:SI 1 "register_operand" "%0,0"))
4427 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4428 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4432 [(set_attr "op_type" "RRE,RXY")
4433 (set_attr "type" "imulsi")])
4436 ; mul(df|sf)3 instruction pattern(s).
4439 (define_expand "mul<mode>3"
4440 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4441 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4442 (match_operand:FPR 2 "general_operand" "f,R")))]
4446 (define_insn "*mul<mode>3"
4447 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4448 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4449 (match_operand:FPR 2 "general_operand" "f,R")))]
4450 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4454 [(set_attr "op_type" "RRE,RXE")
4455 (set_attr "type" "fmul<mode>")])
4457 (define_insn "*mul<mode>3_ibm"
4458 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4459 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4460 (match_operand:FPR 2 "general_operand" "f,R")))]
4461 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4465 [(set_attr "op_type" "RR,RX")
4466 (set_attr "type" "fmul<mode>")])
4468 (define_insn "*fmadd<mode>"
4469 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4470 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4471 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4472 (match_operand:FPR 3 "register_operand" "0,0")))]
4473 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4477 [(set_attr "op_type" "RRE,RXE")
4478 (set_attr "type" "fmul<mode>")])
4480 (define_insn "*fmsub<mode>"
4481 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4482 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4483 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4484 (match_operand:FPR 3 "register_operand" "0,0")))]
4485 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4489 [(set_attr "op_type" "RRE,RXE")
4490 (set_attr "type" "fmul<mode>")])
4493 ;;- Divide and modulo instructions.
4497 ; divmoddi4 instruction pattern(s).
4500 (define_expand "divmoddi4"
4501 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4502 (div:DI (match_operand:DI 1 "register_operand" "")
4503 (match_operand:DI 2 "general_operand" "")))
4504 (set (match_operand:DI 3 "general_operand" "")
4505 (mod:DI (match_dup 1) (match_dup 2)))])
4506 (clobber (match_dup 4))]
4509 rtx insn, div_equal, mod_equal;
4511 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4512 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4514 operands[4] = gen_reg_rtx(TImode);
4515 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4517 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4519 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4521 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4523 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4528 (define_insn "divmodtidi3"
4529 [(set (match_operand:TI 0 "register_operand" "=d,d")
4533 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4534 (match_operand:DI 2 "general_operand" "d,m")))
4536 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4541 [(set_attr "op_type" "RRE,RXY")
4542 (set_attr "type" "idiv")])
4544 (define_insn "divmodtisi3"
4545 [(set (match_operand:TI 0 "register_operand" "=d,d")
4549 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4551 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4554 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4559 [(set_attr "op_type" "RRE,RXY")
4560 (set_attr "type" "idiv")])
4563 ; udivmoddi4 instruction pattern(s).
4566 (define_expand "udivmoddi4"
4567 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4568 (udiv:DI (match_operand:DI 1 "general_operand" "")
4569 (match_operand:DI 2 "nonimmediate_operand" "")))
4570 (set (match_operand:DI 3 "general_operand" "")
4571 (umod:DI (match_dup 1) (match_dup 2)))])
4572 (clobber (match_dup 4))]
4575 rtx insn, div_equal, mod_equal, equal;
4577 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4578 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4579 equal = gen_rtx_IOR (TImode,
4580 gen_rtx_ASHIFT (TImode,
4581 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4583 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4585 operands[4] = gen_reg_rtx(TImode);
4586 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4587 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4588 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4589 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4591 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4593 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4595 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4597 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4599 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4604 (define_insn "udivmodtidi3"
4605 [(set (match_operand:TI 0 "register_operand" "=d,d")
4610 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4612 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4616 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4621 [(set_attr "op_type" "RRE,RXY")
4622 (set_attr "type" "idiv")])
4625 ; divmodsi4 instruction pattern(s).
4628 (define_expand "divmodsi4"
4629 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4630 (div:SI (match_operand:SI 1 "general_operand" "")
4631 (match_operand:SI 2 "nonimmediate_operand" "")))
4632 (set (match_operand:SI 3 "general_operand" "")
4633 (mod:SI (match_dup 1) (match_dup 2)))])
4634 (clobber (match_dup 4))]
4637 rtx insn, div_equal, mod_equal, equal;
4639 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4640 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4641 equal = gen_rtx_IOR (DImode,
4642 gen_rtx_ASHIFT (DImode,
4643 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4645 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4647 operands[4] = gen_reg_rtx(DImode);
4648 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4649 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4651 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4653 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4655 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4657 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4659 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4664 (define_insn "divmoddisi3"
4665 [(set (match_operand:DI 0 "register_operand" "=d,d")
4670 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4672 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4676 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4681 [(set_attr "op_type" "RR,RX")
4682 (set_attr "type" "idiv")])
4685 ; udivsi3 and umodsi3 instruction pattern(s).
4688 (define_expand "udivmodsi4"
4689 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4690 (udiv:SI (match_operand:SI 1 "general_operand" "")
4691 (match_operand:SI 2 "nonimmediate_operand" "")))
4692 (set (match_operand:SI 3 "general_operand" "")
4693 (umod:SI (match_dup 1) (match_dup 2)))])
4694 (clobber (match_dup 4))]
4695 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4697 rtx insn, div_equal, mod_equal, equal;
4699 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4700 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4701 equal = gen_rtx_IOR (DImode,
4702 gen_rtx_ASHIFT (DImode,
4703 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4705 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4707 operands[4] = gen_reg_rtx(DImode);
4708 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4709 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4710 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4711 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4713 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4715 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4717 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4719 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4721 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4726 (define_insn "udivmoddisi3"
4727 [(set (match_operand:DI 0 "register_operand" "=d,d")
4732 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4734 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4738 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4739 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4743 [(set_attr "op_type" "RRE,RXY")
4744 (set_attr "type" "idiv")])
4746 (define_expand "udivsi3"
4747 [(set (match_operand:SI 0 "register_operand" "=d")
4748 (udiv:SI (match_operand:SI 1 "general_operand" "")
4749 (match_operand:SI 2 "general_operand" "")))
4750 (clobber (match_dup 3))]
4751 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4753 rtx insn, udiv_equal, umod_equal, equal;
4755 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4756 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4757 equal = gen_rtx_IOR (DImode,
4758 gen_rtx_ASHIFT (DImode,
4759 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4761 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4763 operands[3] = gen_reg_rtx (DImode);
4765 if (CONSTANT_P (operands[2]))
4767 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4769 rtx label1 = gen_label_rtx ();
4771 operands[1] = make_safe_from (operands[1], operands[0]);
4772 emit_move_insn (operands[0], const0_rtx);
4773 emit_insn (gen_cmpsi (operands[1], operands[2]));
4774 emit_jump_insn (gen_bltu (label1));
4775 emit_move_insn (operands[0], const1_rtx);
4776 emit_label (label1);
4780 operands[2] = force_reg (SImode, operands[2]);
4781 operands[2] = make_safe_from (operands[2], operands[0]);
4783 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4784 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4787 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4789 insn = emit_move_insn (operands[0],
4790 gen_lowpart (SImode, operands[3]));
4792 gen_rtx_EXPR_LIST (REG_EQUAL,
4793 udiv_equal, REG_NOTES (insn));
4798 rtx label1 = gen_label_rtx ();
4799 rtx label2 = gen_label_rtx ();
4800 rtx label3 = gen_label_rtx ();
4802 operands[1] = force_reg (SImode, operands[1]);
4803 operands[1] = make_safe_from (operands[1], operands[0]);
4804 operands[2] = force_reg (SImode, operands[2]);
4805 operands[2] = make_safe_from (operands[2], operands[0]);
4807 emit_move_insn (operands[0], const0_rtx);
4808 emit_insn (gen_cmpsi (operands[2], operands[1]));
4809 emit_jump_insn (gen_bgtu (label3));
4810 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4811 emit_jump_insn (gen_blt (label2));
4812 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4813 emit_jump_insn (gen_beq (label1));
4814 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4815 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4818 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4820 insn = emit_move_insn (operands[0],
4821 gen_lowpart (SImode, operands[3]));
4823 gen_rtx_EXPR_LIST (REG_EQUAL,
4824 udiv_equal, REG_NOTES (insn));
4826 emit_label (label1);
4827 emit_move_insn (operands[0], operands[1]);
4829 emit_label (label2);
4830 emit_move_insn (operands[0], const1_rtx);
4831 emit_label (label3);
4833 emit_move_insn (operands[0], operands[0]);
4837 (define_expand "umodsi3"
4838 [(set (match_operand:SI 0 "register_operand" "=d")
4839 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4840 (match_operand:SI 2 "nonimmediate_operand" "")))
4841 (clobber (match_dup 3))]
4842 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4844 rtx insn, udiv_equal, umod_equal, equal;
4846 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4847 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4848 equal = gen_rtx_IOR (DImode,
4849 gen_rtx_ASHIFT (DImode,
4850 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4852 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4854 operands[3] = gen_reg_rtx (DImode);
4856 if (CONSTANT_P (operands[2]))
4858 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4860 rtx label1 = gen_label_rtx ();
4862 operands[1] = make_safe_from (operands[1], operands[0]);
4863 emit_move_insn (operands[0], operands[1]);
4864 emit_insn (gen_cmpsi (operands[0], operands[2]));
4865 emit_jump_insn (gen_bltu (label1));
4866 emit_insn (gen_abssi2 (operands[0], operands[2]));
4867 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4868 emit_label (label1);
4872 operands[2] = force_reg (SImode, operands[2]);
4873 operands[2] = make_safe_from (operands[2], operands[0]);
4875 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4876 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4879 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4881 insn = emit_move_insn (operands[0],
4882 gen_highpart (SImode, operands[3]));
4884 gen_rtx_EXPR_LIST (REG_EQUAL,
4885 umod_equal, REG_NOTES (insn));
4890 rtx label1 = gen_label_rtx ();
4891 rtx label2 = gen_label_rtx ();
4892 rtx label3 = gen_label_rtx ();
4894 operands[1] = force_reg (SImode, operands[1]);
4895 operands[1] = make_safe_from (operands[1], operands[0]);
4896 operands[2] = force_reg (SImode, operands[2]);
4897 operands[2] = make_safe_from (operands[2], operands[0]);
4899 emit_move_insn(operands[0], operands[1]);
4900 emit_insn (gen_cmpsi (operands[2], operands[1]));
4901 emit_jump_insn (gen_bgtu (label3));
4902 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4903 emit_jump_insn (gen_blt (label2));
4904 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4905 emit_jump_insn (gen_beq (label1));
4906 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4907 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4910 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4912 insn = emit_move_insn (operands[0],
4913 gen_highpart (SImode, operands[3]));
4915 gen_rtx_EXPR_LIST (REG_EQUAL,
4916 umod_equal, REG_NOTES (insn));
4918 emit_label (label1);
4919 emit_move_insn (operands[0], const0_rtx);
4921 emit_label (label2);
4922 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4923 emit_label (label3);
4929 ; div(df|sf)3 instruction pattern(s).
4932 (define_expand "div<mode>3"
4933 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4934 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4935 (match_operand:FPR 2 "general_operand" "f,R")))]
4939 (define_insn "*div<mode>3"
4940 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4941 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4942 (match_operand:FPR 2 "general_operand" "f,R")))]
4943 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4947 [(set_attr "op_type" "RRE,RXE")
4948 (set_attr "type" "fdiv<mode>")])
4950 (define_insn "*div<mode>3_ibm"
4951 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4952 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4953 (match_operand:FPR 2 "general_operand" "f,R")))]
4954 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4958 [(set_attr "op_type" "RR,RX")
4959 (set_attr "type" "fdiv<mode>")])
4963 ;;- And instructions.
4966 (define_expand "and<mode>3"
4967 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4968 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4969 (match_operand:INT 2 "general_operand" "")))
4970 (clobber (reg:CC CC_REGNUM))]
4972 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4975 ; anddi3 instruction pattern(s).
4978 (define_insn "*anddi3_cc"
4979 [(set (reg CC_REGNUM)
4980 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4981 (match_operand:DI 2 "general_operand" "d,m"))
4983 (set (match_operand:DI 0 "register_operand" "=d,d")
4984 (and:DI (match_dup 1) (match_dup 2)))]
4985 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4989 [(set_attr "op_type" "RRE,RXY")])
4991 (define_insn "*anddi3_cconly"
4992 [(set (reg CC_REGNUM)
4993 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4994 (match_operand:DI 2 "general_operand" "d,m"))
4996 (clobber (match_scratch:DI 0 "=d,d"))]
4997 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
4998 /* Do not steal TM patterns. */
4999 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5003 [(set_attr "op_type" "RRE,RXY")])
5005 (define_insn "*anddi3_extimm"
5006 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5007 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5008 "%d,o,0,0,0,0,0,0,0,0,0,0")
5009 (match_operand:DI 2 "general_operand"
5010 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
5011 (clobber (reg:CC CC_REGNUM))]
5012 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5026 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5028 (define_insn "*anddi3"
5029 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5030 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5031 "%d,o,0,0,0,0,0,0,0,0")
5032 (match_operand:DI 2 "general_operand"
5033 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
5034 (clobber (reg:CC CC_REGNUM))]
5035 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5047 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
5050 [(set (match_operand:DI 0 "s_operand" "")
5051 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5052 (clobber (reg:CC CC_REGNUM))]
5055 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5056 (clobber (reg:CC CC_REGNUM))])]
5057 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5061 ; andsi3 instruction pattern(s).
5064 (define_insn "*andsi3_cc"
5065 [(set (reg CC_REGNUM)
5066 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5067 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5069 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5070 (and:SI (match_dup 1) (match_dup 2)))]
5071 "s390_match_ccmode(insn, CCTmode)"
5077 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5079 (define_insn "*andsi3_cconly"
5080 [(set (reg CC_REGNUM)
5081 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5082 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5084 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5085 "s390_match_ccmode(insn, CCTmode)
5086 /* Do not steal TM patterns. */
5087 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5093 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5095 (define_insn "*andsi3_zarch"
5096 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5097 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5098 "%d,o,0,0,0,0,0,0,0,0")
5099 (match_operand:SI 2 "general_operand"
5100 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5101 (clobber (reg:CC CC_REGNUM))]
5102 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5114 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
5116 (define_insn "*andsi3_esa"
5117 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5118 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5119 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5120 (clobber (reg:CC CC_REGNUM))]
5121 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5127 [(set_attr "op_type" "RR,RX,SI,SS")])
5130 [(set (match_operand:SI 0 "s_operand" "")
5131 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5132 (clobber (reg:CC CC_REGNUM))]
5135 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5136 (clobber (reg:CC CC_REGNUM))])]
5137 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5140 ; andhi3 instruction pattern(s).
5143 (define_insn "*andhi3_zarch"
5144 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5145 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5146 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5147 (clobber (reg:CC CC_REGNUM))]
5148 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5154 [(set_attr "op_type" "RR,RI,SI,SS")])
5156 (define_insn "*andhi3_esa"
5157 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5158 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5159 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5160 (clobber (reg:CC CC_REGNUM))]
5161 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5166 [(set_attr "op_type" "RR,SI,SS")])
5169 [(set (match_operand:HI 0 "s_operand" "")
5170 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5171 (clobber (reg:CC CC_REGNUM))]
5174 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5175 (clobber (reg:CC CC_REGNUM))])]
5176 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5179 ; andqi3 instruction pattern(s).
5182 (define_insn "*andqi3_zarch"
5183 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5184 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5185 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5186 (clobber (reg:CC CC_REGNUM))]
5187 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5194 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5196 (define_insn "*andqi3_esa"
5197 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5198 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5199 (match_operand:QI 2 "general_operand" "d,n,Q")))
5200 (clobber (reg:CC CC_REGNUM))]
5201 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5206 [(set_attr "op_type" "RR,SI,SS")])
5209 ; Block and (NC) patterns.
5213 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5214 (and:BLK (match_dup 0)
5215 (match_operand:BLK 1 "memory_operand" "Q")))
5216 (use (match_operand 2 "const_int_operand" "n"))
5217 (clobber (reg:CC CC_REGNUM))]
5218 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5219 "nc\t%O0(%2,%R0),%S1"
5220 [(set_attr "op_type" "SS")])
5223 [(set (match_operand 0 "memory_operand" "")
5225 (match_operand 1 "memory_operand" "")))
5226 (clobber (reg:CC CC_REGNUM))]
5228 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5229 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5231 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5233 (clobber (reg:CC CC_REGNUM))])]
5235 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5236 operands[0] = adjust_address (operands[0], BLKmode, 0);
5237 operands[1] = adjust_address (operands[1], BLKmode, 0);
5242 [(set (match_operand:BLK 0 "memory_operand" "")
5243 (and:BLK (match_dup 0)
5244 (match_operand:BLK 1 "memory_operand" "")))
5245 (use (match_operand 2 "const_int_operand" ""))
5246 (clobber (reg:CC CC_REGNUM))])
5248 [(set (match_operand:BLK 3 "memory_operand" "")
5249 (and:BLK (match_dup 3)
5250 (match_operand:BLK 4 "memory_operand" "")))
5251 (use (match_operand 5 "const_int_operand" ""))
5252 (clobber (reg:CC CC_REGNUM))])]
5253 "s390_offset_p (operands[0], operands[3], operands[2])
5254 && s390_offset_p (operands[1], operands[4], operands[2])
5255 && !s390_overlap_p (operands[0], operands[1],
5256 INTVAL (operands[2]) + INTVAL (operands[5]))
5257 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5259 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5261 (clobber (reg:CC CC_REGNUM))])]
5262 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5263 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5264 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5268 ;;- Bit set (inclusive or) instructions.
5271 (define_expand "ior<mode>3"
5272 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5273 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
5274 (match_operand:INT 2 "general_operand" "")))
5275 (clobber (reg:CC CC_REGNUM))]
5277 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
5280 ; iordi3 instruction pattern(s).
5283 (define_insn "*iordi3_cc"
5284 [(set (reg CC_REGNUM)
5285 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5286 (match_operand:DI 2 "general_operand" "d,m"))
5288 (set (match_operand:DI 0 "register_operand" "=d,d")
5289 (ior:DI (match_dup 1) (match_dup 2)))]
5290 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5294 [(set_attr "op_type" "RRE,RXY")])
5296 (define_insn "*iordi3_cconly"
5297 [(set (reg CC_REGNUM)
5298 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5299 (match_operand:DI 2 "general_operand" "d,m"))
5301 (clobber (match_scratch:DI 0 "=d,d"))]
5302 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5306 [(set_attr "op_type" "RRE,RXY")])
5308 (define_insn "*iordi3_extimm"
5309 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5310 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
5311 (match_operand:DI 2 "general_operand"
5312 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
5313 (clobber (reg:CC CC_REGNUM))]
5314 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5326 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5328 (define_insn "*iordi3"
5329 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5330 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5331 (match_operand:DI 2 "general_operand"
5332 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5333 (clobber (reg:CC CC_REGNUM))]
5334 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5344 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5347 [(set (match_operand:DI 0 "s_operand" "")
5348 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5349 (clobber (reg:CC CC_REGNUM))]
5352 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5353 (clobber (reg:CC CC_REGNUM))])]
5354 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5357 ; iorsi3 instruction pattern(s).
5360 (define_insn "*iorsi3_cc"
5361 [(set (reg CC_REGNUM)
5362 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5363 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5365 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5366 (ior:SI (match_dup 1) (match_dup 2)))]
5367 "s390_match_ccmode(insn, CCTmode)"
5373 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5375 (define_insn "*iorsi3_cconly"
5376 [(set (reg CC_REGNUM)
5377 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5378 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5380 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5381 "s390_match_ccmode(insn, CCTmode)"
5387 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5389 (define_insn "*iorsi3_zarch"
5390 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5391 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5392 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
5393 (clobber (reg:CC CC_REGNUM))]
5394 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5404 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
5406 (define_insn "*iorsi3_esa"
5407 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5408 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5409 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5410 (clobber (reg:CC CC_REGNUM))]
5411 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5417 [(set_attr "op_type" "RR,RX,SI,SS")])
5420 [(set (match_operand:SI 0 "s_operand" "")
5421 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5422 (clobber (reg:CC CC_REGNUM))]
5425 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5426 (clobber (reg:CC CC_REGNUM))])]
5427 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5430 ; iorhi3 instruction pattern(s).
5433 (define_insn "*iorhi3_zarch"
5434 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5435 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5436 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5437 (clobber (reg:CC CC_REGNUM))]
5438 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5444 [(set_attr "op_type" "RR,RI,SI,SS")])
5446 (define_insn "*iorhi3_esa"
5447 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5448 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5449 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5450 (clobber (reg:CC CC_REGNUM))]
5451 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5456 [(set_attr "op_type" "RR,SI,SS")])
5459 [(set (match_operand:HI 0 "s_operand" "")
5460 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5461 (clobber (reg:CC CC_REGNUM))]
5464 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5465 (clobber (reg:CC CC_REGNUM))])]
5466 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5469 ; iorqi3 instruction pattern(s).
5472 (define_insn "*iorqi3_zarch"
5473 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5474 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5475 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5476 (clobber (reg:CC CC_REGNUM))]
5477 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5484 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5486 (define_insn "*iorqi3_esa"
5487 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5488 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5489 (match_operand:QI 2 "general_operand" "d,n,Q")))
5490 (clobber (reg:CC CC_REGNUM))]
5491 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5496 [(set_attr "op_type" "RR,SI,SS")])
5499 ; Block inclusive or (OC) patterns.
5503 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5504 (ior:BLK (match_dup 0)
5505 (match_operand:BLK 1 "memory_operand" "Q")))
5506 (use (match_operand 2 "const_int_operand" "n"))
5507 (clobber (reg:CC CC_REGNUM))]
5508 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5509 "oc\t%O0(%2,%R0),%S1"
5510 [(set_attr "op_type" "SS")])
5513 [(set (match_operand 0 "memory_operand" "")
5515 (match_operand 1 "memory_operand" "")))
5516 (clobber (reg:CC CC_REGNUM))]
5518 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5519 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5521 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5523 (clobber (reg:CC CC_REGNUM))])]
5525 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5526 operands[0] = adjust_address (operands[0], BLKmode, 0);
5527 operands[1] = adjust_address (operands[1], BLKmode, 0);
5532 [(set (match_operand:BLK 0 "memory_operand" "")
5533 (ior:BLK (match_dup 0)
5534 (match_operand:BLK 1 "memory_operand" "")))
5535 (use (match_operand 2 "const_int_operand" ""))
5536 (clobber (reg:CC CC_REGNUM))])
5538 [(set (match_operand:BLK 3 "memory_operand" "")
5539 (ior:BLK (match_dup 3)
5540 (match_operand:BLK 4 "memory_operand" "")))
5541 (use (match_operand 5 "const_int_operand" ""))
5542 (clobber (reg:CC CC_REGNUM))])]
5543 "s390_offset_p (operands[0], operands[3], operands[2])
5544 && s390_offset_p (operands[1], operands[4], operands[2])
5545 && !s390_overlap_p (operands[0], operands[1],
5546 INTVAL (operands[2]) + INTVAL (operands[5]))
5547 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5549 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5551 (clobber (reg:CC CC_REGNUM))])]
5552 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5553 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5554 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5558 ;;- Xor instructions.
5561 (define_expand "xor<mode>3"
5562 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5563 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5564 (match_operand:INT 2 "general_operand" "")))
5565 (clobber (reg:CC CC_REGNUM))]
5567 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5570 ; xordi3 instruction pattern(s).
5573 (define_insn "*xordi3_cc"
5574 [(set (reg CC_REGNUM)
5575 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5576 (match_operand:DI 2 "general_operand" "d,m"))
5578 (set (match_operand:DI 0 "register_operand" "=d,d")
5579 (xor:DI (match_dup 1) (match_dup 2)))]
5580 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5584 [(set_attr "op_type" "RRE,RXY")])
5586 (define_insn "*xordi3_cconly"
5587 [(set (reg CC_REGNUM)
5588 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5589 (match_operand:DI 2 "general_operand" "d,m"))
5591 (clobber (match_scratch:DI 0 "=d,d"))]
5592 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5596 [(set_attr "op_type" "RRE,RXY")])
5598 (define_insn "*xordi3_extimm"
5599 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5600 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5601 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
5602 (clobber (reg:CC CC_REGNUM))]
5603 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5611 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
5613 (define_insn "*xordi3"
5614 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5615 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5616 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5617 (clobber (reg:CC CC_REGNUM))]
5618 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5624 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5627 [(set (match_operand:DI 0 "s_operand" "")
5628 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5629 (clobber (reg:CC CC_REGNUM))]
5632 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5633 (clobber (reg:CC CC_REGNUM))])]
5634 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5637 ; xorsi3 instruction pattern(s).
5640 (define_insn "*xorsi3_cc"
5641 [(set (reg CC_REGNUM)
5642 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5643 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5645 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5646 (xor:SI (match_dup 1) (match_dup 2)))]
5647 "s390_match_ccmode(insn, CCTmode)"
5653 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5655 (define_insn "*xorsi3_cconly"
5656 [(set (reg CC_REGNUM)
5657 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5658 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5660 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5661 "s390_match_ccmode(insn, CCTmode)"
5667 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5669 (define_insn "*xorsi3"
5670 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5671 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5672 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
5673 (clobber (reg:CC CC_REGNUM))]
5674 "s390_logical_operator_ok_p (operands)"
5682 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
5685 [(set (match_operand:SI 0 "s_operand" "")
5686 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5687 (clobber (reg:CC CC_REGNUM))]
5690 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5691 (clobber (reg:CC CC_REGNUM))])]
5692 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5695 ; xorhi3 instruction pattern(s).
5698 (define_insn "*xorhi3"
5699 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5700 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5701 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
5702 (clobber (reg:CC CC_REGNUM))]
5703 "s390_logical_operator_ok_p (operands)"
5709 [(set_attr "op_type" "RIL,RR,SI,SS")])
5712 [(set (match_operand:HI 0 "s_operand" "")
5713 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5714 (clobber (reg:CC CC_REGNUM))]
5717 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5718 (clobber (reg:CC CC_REGNUM))])]
5719 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5722 ; xorqi3 instruction pattern(s).
5725 (define_insn "*xorqi3"
5726 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5727 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5728 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
5729 (clobber (reg:CC CC_REGNUM))]
5730 "s390_logical_operator_ok_p (operands)"
5737 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
5740 ; Block exclusive or (XC) patterns.
5744 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5745 (xor:BLK (match_dup 0)
5746 (match_operand:BLK 1 "memory_operand" "Q")))
5747 (use (match_operand 2 "const_int_operand" "n"))
5748 (clobber (reg:CC CC_REGNUM))]
5749 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5750 "xc\t%O0(%2,%R0),%S1"
5751 [(set_attr "op_type" "SS")])
5754 [(set (match_operand 0 "memory_operand" "")
5756 (match_operand 1 "memory_operand" "")))
5757 (clobber (reg:CC CC_REGNUM))]
5759 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5760 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5762 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5764 (clobber (reg:CC CC_REGNUM))])]
5766 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5767 operands[0] = adjust_address (operands[0], BLKmode, 0);
5768 operands[1] = adjust_address (operands[1], BLKmode, 0);
5773 [(set (match_operand:BLK 0 "memory_operand" "")
5774 (xor:BLK (match_dup 0)
5775 (match_operand:BLK 1 "memory_operand" "")))
5776 (use (match_operand 2 "const_int_operand" ""))
5777 (clobber (reg:CC CC_REGNUM))])
5779 [(set (match_operand:BLK 3 "memory_operand" "")
5780 (xor:BLK (match_dup 3)
5781 (match_operand:BLK 4 "memory_operand" "")))
5782 (use (match_operand 5 "const_int_operand" ""))
5783 (clobber (reg:CC CC_REGNUM))])]
5784 "s390_offset_p (operands[0], operands[3], operands[2])
5785 && s390_offset_p (operands[1], operands[4], operands[2])
5786 && !s390_overlap_p (operands[0], operands[1],
5787 INTVAL (operands[2]) + INTVAL (operands[5]))
5788 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5790 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5792 (clobber (reg:CC CC_REGNUM))])]
5793 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5794 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5795 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5798 ; Block xor (XC) patterns with src == dest.
5801 (define_insn "*xc_zero"
5802 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5804 (use (match_operand 1 "const_int_operand" "n"))
5805 (clobber (reg:CC CC_REGNUM))]
5806 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5807 "xc\t%O0(%1,%R0),%S0"
5808 [(set_attr "op_type" "SS")])
5812 [(set (match_operand:BLK 0 "memory_operand" "")
5814 (use (match_operand 1 "const_int_operand" ""))
5815 (clobber (reg:CC CC_REGNUM))])
5817 [(set (match_operand:BLK 2 "memory_operand" "")
5819 (use (match_operand 3 "const_int_operand" ""))
5820 (clobber (reg:CC CC_REGNUM))])]
5821 "s390_offset_p (operands[0], operands[2], operands[1])
5822 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5824 [(set (match_dup 4) (const_int 0))
5826 (clobber (reg:CC CC_REGNUM))])]
5827 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5828 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5832 ;;- Negate instructions.
5836 ; neg(di|si)2 instruction pattern(s).
5839 (define_expand "neg<mode>2"
5841 [(set (match_operand:DSI 0 "register_operand" "=d")
5842 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5843 (clobber (reg:CC CC_REGNUM))])]
5847 (define_insn "*negdi2_sign_cc"
5848 [(set (reg CC_REGNUM)
5849 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5850 (match_operand:SI 1 "register_operand" "d") 0)
5851 (const_int 32)) (const_int 32)))
5853 (set (match_operand:DI 0 "register_operand" "=d")
5854 (neg:DI (sign_extend:DI (match_dup 1))))]
5855 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5857 [(set_attr "op_type" "RRE")])
5859 (define_insn "*negdi2_sign"
5860 [(set (match_operand:DI 0 "register_operand" "=d")
5861 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5862 (clobber (reg:CC CC_REGNUM))]
5865 [(set_attr "op_type" "RRE")])
5867 (define_insn "*neg<mode>2_cc"
5868 [(set (reg CC_REGNUM)
5869 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5871 (set (match_operand:GPR 0 "register_operand" "=d")
5872 (neg:GPR (match_dup 1)))]
5873 "s390_match_ccmode (insn, CCAmode)"
5875 [(set_attr "op_type" "RR<E>")])
5877 (define_insn "*neg<mode>2_cconly"
5878 [(set (reg CC_REGNUM)
5879 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5881 (clobber (match_scratch:GPR 0 "=d"))]
5882 "s390_match_ccmode (insn, CCAmode)"
5884 [(set_attr "op_type" "RR<E>")])
5886 (define_insn "*neg<mode>2"
5887 [(set (match_operand:GPR 0 "register_operand" "=d")
5888 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5889 (clobber (reg:CC CC_REGNUM))]
5892 [(set_attr "op_type" "RR<E>")])
5894 (define_insn_and_split "*negdi2_31"
5895 [(set (match_operand:DI 0 "register_operand" "=d")
5896 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5897 (clobber (reg:CC CC_REGNUM))]
5900 "&& reload_completed"
5902 [(set (match_dup 2) (neg:SI (match_dup 3)))
5903 (clobber (reg:CC CC_REGNUM))])
5905 [(set (reg:CCAP CC_REGNUM)
5906 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5907 (set (match_dup 4) (neg:SI (match_dup 5)))])
5909 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5911 (label_ref (match_dup 6))))
5913 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5914 (clobber (reg:CC CC_REGNUM))])
5916 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5917 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5918 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5919 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5920 operands[6] = gen_label_rtx ();")
5923 ; neg(df|sf)2 instruction pattern(s).
5926 (define_expand "neg<mode>2"
5928 [(set (match_operand:FPR 0 "register_operand" "=f")
5929 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5930 (clobber (reg:CC CC_REGNUM))])]
5934 (define_insn "*neg<mode>2_cc"
5935 [(set (reg CC_REGNUM)
5936 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5937 (match_operand:FPR 2 "const0_operand" "")))
5938 (set (match_operand:FPR 0 "register_operand" "=f")
5939 (neg:FPR (match_dup 1)))]
5940 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5942 [(set_attr "op_type" "RRE")
5943 (set_attr "type" "fsimp<mode>")])
5945 (define_insn "*neg<mode>2_cconly"
5946 [(set (reg CC_REGNUM)
5947 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5948 (match_operand:FPR 2 "const0_operand" "")))
5949 (clobber (match_scratch:FPR 0 "=f"))]
5950 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5952 [(set_attr "op_type" "RRE")
5953 (set_attr "type" "fsimp<mode>")])
5955 (define_insn "*neg<mode>2"
5956 [(set (match_operand:FPR 0 "register_operand" "=f")
5957 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5958 (clobber (reg:CC CC_REGNUM))]
5959 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5961 [(set_attr "op_type" "RRE")
5962 (set_attr "type" "fsimp<mode>")])
5964 (define_insn "*neg<mode>2_ibm"
5965 [(set (match_operand:FPR 0 "register_operand" "=f")
5966 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5967 (clobber (reg:CC CC_REGNUM))]
5968 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5970 [(set_attr "op_type" "RR")
5971 (set_attr "type" "fsimp<mode>")])
5975 ;;- Absolute value instructions.
5979 ; abs(di|si)2 instruction pattern(s).
5982 (define_insn "*absdi2_sign_cc"
5983 [(set (reg CC_REGNUM)
5984 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5985 (match_operand:SI 1 "register_operand" "d") 0)
5986 (const_int 32)) (const_int 32)))
5988 (set (match_operand:DI 0 "register_operand" "=d")
5989 (abs:DI (sign_extend:DI (match_dup 1))))]
5990 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5992 [(set_attr "op_type" "RRE")])
5994 (define_insn "*absdi2_sign"
5995 [(set (match_operand:DI 0 "register_operand" "=d")
5996 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5997 (clobber (reg:CC CC_REGNUM))]
6000 [(set_attr "op_type" "RRE")])
6002 (define_insn "*abs<mode>2_cc"
6003 [(set (reg CC_REGNUM)
6004 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6006 (set (match_operand:GPR 0 "register_operand" "=d")
6007 (abs:GPR (match_dup 1)))]
6008 "s390_match_ccmode (insn, CCAmode)"
6010 [(set_attr "op_type" "RR<E>")])
6012 (define_insn "*abs<mode>2_cconly"
6013 [(set (reg CC_REGNUM)
6014 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6016 (clobber (match_scratch:GPR 0 "=d"))]
6017 "s390_match_ccmode (insn, CCAmode)"
6019 [(set_attr "op_type" "RR<E>")])
6021 (define_insn "abs<mode>2"
6022 [(set (match_operand:GPR 0 "register_operand" "=d")
6023 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6024 (clobber (reg:CC CC_REGNUM))]
6027 [(set_attr "op_type" "RR<E>")])
6030 ; abs(df|sf)2 instruction pattern(s).
6033 (define_expand "abs<mode>2"
6035 [(set (match_operand:FPR 0 "register_operand" "=f")
6036 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6037 (clobber (reg:CC CC_REGNUM))])]
6041 (define_insn "*abs<mode>2_cc"
6042 [(set (reg CC_REGNUM)
6043 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
6044 (match_operand:FPR 2 "const0_operand" "")))
6045 (set (match_operand:FPR 0 "register_operand" "=f")
6046 (abs:FPR (match_dup 1)))]
6047 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6049 [(set_attr "op_type" "RRE")
6050 (set_attr "type" "fsimp<mode>")])
6052 (define_insn "*abs<mode>2_cconly"
6053 [(set (reg CC_REGNUM)
6054 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
6055 (match_operand:FPR 2 "const0_operand" "")))
6056 (clobber (match_scratch:FPR 0 "=f"))]
6057 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6059 [(set_attr "op_type" "RRE")
6060 (set_attr "type" "fsimp<mode>")])
6062 (define_insn "*abs<mode>2"
6063 [(set (match_operand:FPR 0 "register_operand" "=f")
6064 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6065 (clobber (reg:CC CC_REGNUM))]
6066 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6068 [(set_attr "op_type" "RRE")
6069 (set_attr "type" "fsimp<mode>")])
6071 (define_insn "*abs<mode>2_ibm"
6072 [(set (match_operand:FPR 0 "register_operand" "=f")
6073 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6074 (clobber (reg:CC CC_REGNUM))]
6075 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6077 [(set_attr "op_type" "RR")
6078 (set_attr "type" "fsimp<mode>")])
6081 ;;- Negated absolute value instructions
6088 (define_insn "*negabsdi2_sign_cc"
6089 [(set (reg CC_REGNUM)
6090 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6091 (match_operand:SI 1 "register_operand" "d") 0)
6092 (const_int 32)) (const_int 32))))
6094 (set (match_operand:DI 0 "register_operand" "=d")
6095 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6096 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6098 [(set_attr "op_type" "RRE")])
6100 (define_insn "*negabsdi2_sign"
6101 [(set (match_operand:DI 0 "register_operand" "=d")
6102 (neg:DI (abs:DI (sign_extend:DI
6103 (match_operand:SI 1 "register_operand" "d")))))
6104 (clobber (reg:CC CC_REGNUM))]
6107 [(set_attr "op_type" "RRE")])
6109 (define_insn "*negabs<mode>2_cc"
6110 [(set (reg CC_REGNUM)
6111 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6113 (set (match_operand:GPR 0 "register_operand" "=d")
6114 (neg:GPR (abs:GPR (match_dup 1))))]
6115 "s390_match_ccmode (insn, CCAmode)"
6117 [(set_attr "op_type" "RR<E>")])
6119 (define_insn "*negabs<mode>2_cconly"
6120 [(set (reg CC_REGNUM)
6121 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6123 (clobber (match_scratch:GPR 0 "=d"))]
6124 "s390_match_ccmode (insn, CCAmode)"
6126 [(set_attr "op_type" "RR<E>")])
6128 (define_insn "*negabs<mode>2"
6129 [(set (match_operand:GPR 0 "register_operand" "=d")
6130 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6131 (clobber (reg:CC CC_REGNUM))]
6134 [(set_attr "op_type" "RR<E>")])
6140 (define_insn "*negabs<mode>2_cc"
6141 [(set (reg CC_REGNUM)
6142 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6143 (match_operand:FPR 2 "const0_operand" "")))
6144 (set (match_operand:FPR 0 "register_operand" "=f")
6145 (neg:FPR (abs:FPR (match_dup 1))))]
6146 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6148 [(set_attr "op_type" "RRE")
6149 (set_attr "type" "fsimp<mode>")])
6151 (define_insn "*negabs<mode>2_cconly"
6152 [(set (reg CC_REGNUM)
6153 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6154 (match_operand:FPR 2 "const0_operand" "")))
6155 (clobber (match_scratch:FPR 0 "=f"))]
6156 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6158 [(set_attr "op_type" "RRE")
6159 (set_attr "type" "fsimp<mode>")])
6161 (define_insn "*negabs<mode>2"
6162 [(set (match_operand:FPR 0 "register_operand" "=f")
6163 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
6164 (clobber (reg:CC CC_REGNUM))]
6165 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6167 [(set_attr "op_type" "RRE")
6168 (set_attr "type" "fsimp<mode>")])
6171 ;;- Square root instructions.
6175 ; sqrt(df|sf)2 instruction pattern(s).
6178 (define_insn "sqrt<mode>2"
6179 [(set (match_operand:FPR 0 "register_operand" "=f,f")
6180 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
6181 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6185 [(set_attr "op_type" "RRE,RXE")
6186 (set_attr "type" "fsqrt<mode>")])
6190 ;;- One complement instructions.
6194 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
6197 (define_expand "one_cmpl<mode>2"
6199 [(set (match_operand:INT 0 "register_operand" "")
6200 (xor:INT (match_operand:INT 1 "register_operand" "")
6202 (clobber (reg:CC CC_REGNUM))])]
6208 ;; Find leftmost bit instructions.
6211 (define_expand "clzdi2"
6212 [(set (match_operand:DI 0 "register_operand" "=d")
6213 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
6214 "TARGET_EXTIMM && TARGET_64BIT"
6216 rtx insn, clz_equal;
6217 rtx wide_reg = gen_reg_rtx (TImode);
6218 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
6220 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
6222 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
6224 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
6226 gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn));
6231 (define_insn "clztidi2"
6232 [(set (match_operand:TI 0 "register_operand" "=d")
6236 (xor:DI (match_operand:DI 1 "register_operand" "d")
6237 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
6238 (subreg:SI (clz:DI (match_dup 1)) 4))))
6241 (zero_extend:TI (clz:DI (match_dup 1)))))
6242 (clobber (reg:CC CC_REGNUM))]
6243 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
6244 == (unsigned HOST_WIDE_INT) 1 << 63
6245 && TARGET_EXTIMM && TARGET_64BIT"
6247 [(set_attr "op_type" "RRE")])
6251 ;;- Rotate instructions.
6255 ; rotl(di|si)3 instruction pattern(s).
6258 (define_insn "rotl<mode>3"
6259 [(set (match_operand:GPR 0 "register_operand" "=d")
6260 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6261 (match_operand:SI 2 "shift_count_operand" "Y")))]
6264 [(set_attr "op_type" "RSE")
6265 (set_attr "atype" "reg")])
6269 ;;- Shift instructions.
6273 ; (ashl|lshr)di3 instruction pattern(s).
6276 (define_expand "<shift>di3"
6277 [(set (match_operand:DI 0 "register_operand" "")
6278 (SHIFT:DI (match_operand:DI 1 "register_operand" "")
6279 (match_operand:SI 2 "shift_count_operand" "")))]
6283 (define_insn "*<shift>di3_31"
6284 [(set (match_operand:DI 0 "register_operand" "=d")
6285 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6286 (match_operand:SI 2 "shift_count_operand" "Y")))]
6289 [(set_attr "op_type" "RS")
6290 (set_attr "atype" "reg")])
6292 (define_insn "*<shift>di3_64"
6293 [(set (match_operand:DI 0 "register_operand" "=d")
6294 (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
6295 (match_operand:SI 2 "shift_count_operand" "Y")))]
6297 "s<lr>lg\t%0,%1,%Y2"
6298 [(set_attr "op_type" "RSE")
6299 (set_attr "atype" "reg")])
6302 ; ashrdi3 instruction pattern(s).
6305 (define_expand "ashrdi3"
6307 [(set (match_operand:DI 0 "register_operand" "")
6308 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6309 (match_operand:SI 2 "shift_count_operand" "")))
6310 (clobber (reg:CC CC_REGNUM))])]
6314 (define_insn "*ashrdi3_cc_31"
6315 [(set (reg CC_REGNUM)
6316 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6317 (match_operand:SI 2 "shift_count_operand" "Y"))
6319 (set (match_operand:DI 0 "register_operand" "=d")
6320 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6321 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6323 [(set_attr "op_type" "RS")
6324 (set_attr "atype" "reg")])
6326 (define_insn "*ashrdi3_cconly_31"
6327 [(set (reg CC_REGNUM)
6328 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6329 (match_operand:SI 2 "shift_count_operand" "Y"))
6331 (clobber (match_scratch:DI 0 "=d"))]
6332 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6334 [(set_attr "op_type" "RS")
6335 (set_attr "atype" "reg")])
6337 (define_insn "*ashrdi3_31"
6338 [(set (match_operand:DI 0 "register_operand" "=d")
6339 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6340 (match_operand:SI 2 "shift_count_operand" "Y")))
6341 (clobber (reg:CC CC_REGNUM))]
6344 [(set_attr "op_type" "RS")
6345 (set_attr "atype" "reg")])
6347 (define_insn "*ashrdi3_cc_64"
6348 [(set (reg CC_REGNUM)
6349 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6350 (match_operand:SI 2 "shift_count_operand" "Y"))
6352 (set (match_operand:DI 0 "register_operand" "=d")
6353 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6354 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6356 [(set_attr "op_type" "RSE")
6357 (set_attr "atype" "reg")])
6359 (define_insn "*ashrdi3_cconly_64"
6360 [(set (reg CC_REGNUM)
6361 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6362 (match_operand:SI 2 "shift_count_operand" "Y"))
6364 (clobber (match_scratch:DI 0 "=d"))]
6365 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6367 [(set_attr "op_type" "RSE")
6368 (set_attr "atype" "reg")])
6370 (define_insn "*ashrdi3_64"
6371 [(set (match_operand:DI 0 "register_operand" "=d")
6372 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6373 (match_operand:SI 2 "shift_count_operand" "Y")))
6374 (clobber (reg:CC CC_REGNUM))]
6377 [(set_attr "op_type" "RSE")
6378 (set_attr "atype" "reg")])
6382 ; (ashl|lshr)si3 instruction pattern(s).
6385 (define_insn "<shift>si3"
6386 [(set (match_operand:SI 0 "register_operand" "=d")
6387 (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
6388 (match_operand:SI 2 "shift_count_operand" "Y")))]
6391 [(set_attr "op_type" "RS")
6392 (set_attr "atype" "reg")])
6395 ; ashrsi3 instruction pattern(s).
6398 (define_insn "*ashrsi3_cc"
6399 [(set (reg CC_REGNUM)
6400 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6401 (match_operand:SI 2 "shift_count_operand" "Y"))
6403 (set (match_operand:SI 0 "register_operand" "=d")
6404 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
6405 "s390_match_ccmode(insn, CCSmode)"
6407 [(set_attr "op_type" "RS")
6408 (set_attr "atype" "reg")])
6411 (define_insn "*ashrsi3_cconly"
6412 [(set (reg CC_REGNUM)
6413 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6414 (match_operand:SI 2 "shift_count_operand" "Y"))
6416 (clobber (match_scratch:SI 0 "=d"))]
6417 "s390_match_ccmode(insn, CCSmode)"
6419 [(set_attr "op_type" "RS")
6420 (set_attr "atype" "reg")])
6422 (define_insn "ashrsi3"
6423 [(set (match_operand:SI 0 "register_operand" "=d")
6424 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6425 (match_operand:SI 2 "shift_count_operand" "Y")))
6426 (clobber (reg:CC CC_REGNUM))]
6429 [(set_attr "op_type" "RS")
6430 (set_attr "atype" "reg")])
6434 ;; Branch instruction patterns.
6437 (define_expand "b<code>"
6439 (if_then_else (COMPARE (match_operand 0 "" "")
6444 "s390_emit_jump (operands[0],
6445 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
6449 ;;- Conditional jump instructions.
6452 (define_insn "*cjump_64"
6455 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6456 (label_ref (match_operand 0 "" ""))
6460 if (get_attr_length (insn) == 4)
6463 return "jg%C1\t%l0";
6465 [(set_attr "op_type" "RI")
6466 (set_attr "type" "branch")
6467 (set (attr "length")
6468 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6469 (const_int 4) (const_int 6)))])
6471 (define_insn "*cjump_31"
6474 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6475 (label_ref (match_operand 0 "" ""))
6479 gcc_assert (get_attr_length (insn) == 4);
6482 [(set_attr "op_type" "RI")
6483 (set_attr "type" "branch")
6484 (set (attr "length")
6485 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6486 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6487 (const_int 4) (const_int 6))
6488 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6489 (const_int 4) (const_int 8))))])
6491 (define_insn "*cjump_long"
6494 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6495 (match_operand 0 "address_operand" "U")
6499 if (get_attr_op_type (insn) == OP_TYPE_RR)
6504 [(set (attr "op_type")
6505 (if_then_else (match_operand 0 "register_operand" "")
6506 (const_string "RR") (const_string "RX")))
6507 (set_attr "type" "branch")
6508 (set_attr "atype" "agen")])
6512 ;;- Negated conditional jump instructions.
6515 (define_insn "*icjump_64"
6518 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6520 (label_ref (match_operand 0 "" ""))))]
6523 if (get_attr_length (insn) == 4)
6526 return "jg%D1\t%l0";
6528 [(set_attr "op_type" "RI")
6529 (set_attr "type" "branch")
6530 (set (attr "length")
6531 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6532 (const_int 4) (const_int 6)))])
6534 (define_insn "*icjump_31"
6537 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6539 (label_ref (match_operand 0 "" ""))))]
6542 gcc_assert (get_attr_length (insn) == 4);
6545 [(set_attr "op_type" "RI")
6546 (set_attr "type" "branch")
6547 (set (attr "length")
6548 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6549 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6550 (const_int 4) (const_int 6))
6551 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6552 (const_int 4) (const_int 8))))])
6554 (define_insn "*icjump_long"
6557 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6559 (match_operand 0 "address_operand" "U")))]
6562 if (get_attr_op_type (insn) == OP_TYPE_RR)
6567 [(set (attr "op_type")
6568 (if_then_else (match_operand 0 "register_operand" "")
6569 (const_string "RR") (const_string "RX")))
6570 (set_attr "type" "branch")
6571 (set_attr "atype" "agen")])
6574 ;;- Trap instructions.
6578 [(trap_if (const_int 1) (const_int 0))]
6581 [(set_attr "op_type" "RI")
6582 (set_attr "type" "branch")])
6584 (define_expand "conditional_trap"
6585 [(trap_if (match_operand 0 "comparison_operator" "")
6586 (match_operand 1 "general_operand" ""))]
6589 if (operands[1] != const0_rtx) FAIL;
6590 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6591 s390_compare_op0, s390_compare_op1);
6594 (define_insn "*trap"
6595 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6599 [(set_attr "op_type" "RI")
6600 (set_attr "type" "branch")])
6603 ;;- Loop instructions.
6605 ;; This is all complicated by the fact that since this is a jump insn
6606 ;; we must handle our own output reloads.
6608 (define_expand "doloop_end"
6609 [(use (match_operand 0 "" "")) ; loop pseudo
6610 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6611 (use (match_operand 2 "" "")) ; max iterations
6612 (use (match_operand 3 "" "")) ; loop level
6613 (use (match_operand 4 "" ""))] ; label
6616 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6617 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6618 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6619 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6620 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6621 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6628 (define_insn_and_split "doloop_si64"
6631 (ne (match_operand:SI 1 "register_operand" "d,d")
6633 (label_ref (match_operand 0 "" ""))
6635 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6636 (plus:SI (match_dup 1) (const_int -1)))
6637 (clobber (match_scratch:SI 3 "=X,&1"))
6638 (clobber (reg:CC CC_REGNUM))]
6641 if (which_alternative != 0)
6643 else if (get_attr_length (insn) == 4)
6644 return "brct\t%1,%l0";
6646 return "ahi\t%1,-1\;jgne\t%l0";
6648 "&& reload_completed
6649 && (! REG_P (operands[2])
6650 || ! rtx_equal_p (operands[1], operands[2]))"
6651 [(parallel [(set (reg:CCAN CC_REGNUM)
6652 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6654 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6655 (set (match_dup 2) (match_dup 3))
6656 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6657 (label_ref (match_dup 0))
6660 [(set_attr "op_type" "RI")
6661 (set_attr "type" "branch")
6662 (set (attr "length")
6663 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6664 (const_int 4) (const_int 10)))])
6666 (define_insn_and_split "doloop_si31"
6669 (ne (match_operand:SI 1 "register_operand" "d,d")
6671 (label_ref (match_operand 0 "" ""))
6673 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6674 (plus:SI (match_dup 1) (const_int -1)))
6675 (clobber (match_scratch:SI 3 "=X,&1"))
6676 (clobber (reg:CC CC_REGNUM))]
6679 if (which_alternative != 0)
6681 else if (get_attr_length (insn) == 4)
6682 return "brct\t%1,%l0";
6686 "&& reload_completed
6687 && (! REG_P (operands[2])
6688 || ! rtx_equal_p (operands[1], operands[2]))"
6689 [(parallel [(set (reg:CCAN CC_REGNUM)
6690 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6692 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6693 (set (match_dup 2) (match_dup 3))
6694 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6695 (label_ref (match_dup 0))
6698 [(set_attr "op_type" "RI")
6699 (set_attr "type" "branch")
6700 (set (attr "length")
6701 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6702 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6703 (const_int 4) (const_int 6))
6704 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6705 (const_int 4) (const_int 8))))])
6707 (define_insn "*doloop_si_long"
6710 (ne (match_operand:SI 1 "register_operand" "d,d")
6712 (match_operand 0 "address_operand" "U,U")
6714 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6715 (plus:SI (match_dup 1) (const_int -1)))
6716 (clobber (match_scratch:SI 3 "=X,&1"))
6717 (clobber (reg:CC CC_REGNUM))]
6720 if (get_attr_op_type (insn) == OP_TYPE_RR)
6721 return "bctr\t%1,%0";
6723 return "bct\t%1,%a0";
6725 [(set (attr "op_type")
6726 (if_then_else (match_operand 0 "register_operand" "")
6727 (const_string "RR") (const_string "RX")))
6728 (set_attr "type" "branch")
6729 (set_attr "atype" "agen")])
6731 (define_insn_and_split "doloop_di"
6734 (ne (match_operand:DI 1 "register_operand" "d,d")
6736 (label_ref (match_operand 0 "" ""))
6738 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6739 (plus:DI (match_dup 1) (const_int -1)))
6740 (clobber (match_scratch:DI 3 "=X,&1"))
6741 (clobber (reg:CC CC_REGNUM))]
6744 if (which_alternative != 0)
6746 else if (get_attr_length (insn) == 4)
6747 return "brctg\t%1,%l0";
6749 return "aghi\t%1,-1\;jgne\t%l0";
6751 "&& reload_completed
6752 && (! REG_P (operands[2])
6753 || ! rtx_equal_p (operands[1], operands[2]))"
6754 [(parallel [(set (reg:CCAN CC_REGNUM)
6755 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6757 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6758 (set (match_dup 2) (match_dup 3))
6759 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6760 (label_ref (match_dup 0))
6763 [(set_attr "op_type" "RI")
6764 (set_attr "type" "branch")
6765 (set (attr "length")
6766 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6767 (const_int 4) (const_int 10)))])
6770 ;;- Unconditional jump instructions.
6774 ; jump instruction pattern(s).
6777 (define_expand "jump"
6778 [(match_operand 0 "" "")]
6780 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6782 (define_insn "*jump64"
6783 [(set (pc) (label_ref (match_operand 0 "" "")))]
6786 if (get_attr_length (insn) == 4)
6791 [(set_attr "op_type" "RI")
6792 (set_attr "type" "branch")
6793 (set (attr "length")
6794 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6795 (const_int 4) (const_int 6)))])
6797 (define_insn "*jump31"
6798 [(set (pc) (label_ref (match_operand 0 "" "")))]
6801 gcc_assert (get_attr_length (insn) == 4);
6804 [(set_attr "op_type" "RI")
6805 (set_attr "type" "branch")
6806 (set (attr "length")
6807 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6808 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6809 (const_int 4) (const_int 6))
6810 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6811 (const_int 4) (const_int 8))))])
6814 ; indirect-jump instruction pattern(s).
6817 (define_insn "indirect_jump"
6818 [(set (pc) (match_operand 0 "address_operand" "U"))]
6821 if (get_attr_op_type (insn) == OP_TYPE_RR)
6826 [(set (attr "op_type")
6827 (if_then_else (match_operand 0 "register_operand" "")
6828 (const_string "RR") (const_string "RX")))
6829 (set_attr "type" "branch")
6830 (set_attr "atype" "agen")])
6833 ; casesi instruction pattern(s).
6836 (define_insn "casesi_jump"
6837 [(set (pc) (match_operand 0 "address_operand" "U"))
6838 (use (label_ref (match_operand 1 "" "")))]
6841 if (get_attr_op_type (insn) == OP_TYPE_RR)
6846 [(set (attr "op_type")
6847 (if_then_else (match_operand 0 "register_operand" "")
6848 (const_string "RR") (const_string "RX")))
6849 (set_attr "type" "branch")
6850 (set_attr "atype" "agen")])
6852 (define_expand "casesi"
6853 [(match_operand:SI 0 "general_operand" "")
6854 (match_operand:SI 1 "general_operand" "")
6855 (match_operand:SI 2 "general_operand" "")
6856 (label_ref (match_operand 3 "" ""))
6857 (label_ref (match_operand 4 "" ""))]
6860 rtx index = gen_reg_rtx (SImode);
6861 rtx base = gen_reg_rtx (Pmode);
6862 rtx target = gen_reg_rtx (Pmode);
6864 emit_move_insn (index, operands[0]);
6865 emit_insn (gen_subsi3 (index, index, operands[1]));
6866 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6869 if (Pmode != SImode)
6870 index = convert_to_mode (Pmode, index, 1);
6871 if (GET_CODE (index) != REG)
6872 index = copy_to_mode_reg (Pmode, index);
6875 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6877 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6879 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6881 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6882 emit_move_insn (target, index);
6885 target = gen_rtx_PLUS (Pmode, base, target);
6886 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6893 ;;- Jump to subroutine.
6898 ; untyped call instruction pattern(s).
6901 ;; Call subroutine returning any type.
6902 (define_expand "untyped_call"
6903 [(parallel [(call (match_operand 0 "" "")
6905 (match_operand 1 "" "")
6906 (match_operand 2 "" "")])]
6911 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6913 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6915 rtx set = XVECEXP (operands[2], 0, i);
6916 emit_move_insn (SET_DEST (set), SET_SRC (set));
6919 /* The optimizer does not know that the call sets the function value
6920 registers we stored in the result block. We avoid problems by
6921 claiming that all hard registers are used and clobbered at this
6923 emit_insn (gen_blockage ());
6928 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6929 ;; all of memory. This blocks insns from being moved across this point.
6931 (define_insn "blockage"
6932 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6935 [(set_attr "type" "none")
6936 (set_attr "length" "0")])
6942 (define_expand "sibcall"
6943 [(call (match_operand 0 "" "")
6944 (match_operand 1 "" ""))]
6947 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
6951 (define_insn "*sibcall_br"
6952 [(call (mem:QI (reg SIBCALL_REGNUM))
6953 (match_operand 0 "const_int_operand" "n"))]
6954 "SIBLING_CALL_P (insn)
6955 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
6957 [(set_attr "op_type" "RR")
6958 (set_attr "type" "branch")
6959 (set_attr "atype" "agen")])
6961 (define_insn "*sibcall_brc"
6962 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6963 (match_operand 1 "const_int_operand" "n"))]
6964 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6966 [(set_attr "op_type" "RI")
6967 (set_attr "type" "branch")])
6969 (define_insn "*sibcall_brcl"
6970 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6971 (match_operand 1 "const_int_operand" "n"))]
6972 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6974 [(set_attr "op_type" "RIL")
6975 (set_attr "type" "branch")])
6978 ; sibcall_value patterns
6981 (define_expand "sibcall_value"
6982 [(set (match_operand 0 "" "")
6983 (call (match_operand 1 "" "")
6984 (match_operand 2 "" "")))]
6987 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
6991 (define_insn "*sibcall_value_br"
6992 [(set (match_operand 0 "" "")
6993 (call (mem:QI (reg SIBCALL_REGNUM))
6994 (match_operand 1 "const_int_operand" "n")))]
6995 "SIBLING_CALL_P (insn)
6996 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
6998 [(set_attr "op_type" "RR")
6999 (set_attr "type" "branch")
7000 (set_attr "atype" "agen")])
7002 (define_insn "*sibcall_value_brc"
7003 [(set (match_operand 0 "" "")
7004 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7005 (match_operand 2 "const_int_operand" "n")))]
7006 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7008 [(set_attr "op_type" "RI")
7009 (set_attr "type" "branch")])
7011 (define_insn "*sibcall_value_brcl"
7012 [(set (match_operand 0 "" "")
7013 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7014 (match_operand 2 "const_int_operand" "n")))]
7015 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7017 [(set_attr "op_type" "RIL")
7018 (set_attr "type" "branch")])
7022 ; call instruction pattern(s).
7025 (define_expand "call"
7026 [(call (match_operand 0 "" "")
7027 (match_operand 1 "" ""))
7028 (use (match_operand 2 "" ""))]
7031 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7032 gen_rtx_REG (Pmode, RETURN_REGNUM));
7036 (define_insn "*bras"
7037 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7038 (match_operand 1 "const_int_operand" "n"))
7039 (clobber (match_operand 2 "register_operand" "=r"))]
7040 "!SIBLING_CALL_P (insn)
7041 && TARGET_SMALL_EXEC
7042 && GET_MODE (operands[2]) == Pmode"
7044 [(set_attr "op_type" "RI")
7045 (set_attr "type" "jsr")])
7047 (define_insn "*brasl"
7048 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7049 (match_operand 1 "const_int_operand" "n"))
7050 (clobber (match_operand 2 "register_operand" "=r"))]
7051 "!SIBLING_CALL_P (insn)
7053 && GET_MODE (operands[2]) == Pmode"
7055 [(set_attr "op_type" "RIL")
7056 (set_attr "type" "jsr")])
7058 (define_insn "*basr"
7059 [(call (mem:QI (match_operand 0 "address_operand" "U"))
7060 (match_operand 1 "const_int_operand" "n"))
7061 (clobber (match_operand 2 "register_operand" "=r"))]
7062 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
7064 if (get_attr_op_type (insn) == OP_TYPE_RR)
7065 return "basr\t%2,%0";
7067 return "bas\t%2,%a0";
7069 [(set (attr "op_type")
7070 (if_then_else (match_operand 0 "register_operand" "")
7071 (const_string "RR") (const_string "RX")))
7072 (set_attr "type" "jsr")
7073 (set_attr "atype" "agen")])
7076 ; call_value instruction pattern(s).
7079 (define_expand "call_value"
7080 [(set (match_operand 0 "" "")
7081 (call (match_operand 1 "" "")
7082 (match_operand 2 "" "")))
7083 (use (match_operand 3 "" ""))]
7086 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
7087 gen_rtx_REG (Pmode, RETURN_REGNUM));
7091 (define_insn "*bras_r"
7092 [(set (match_operand 0 "" "")
7093 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7094 (match_operand:SI 2 "const_int_operand" "n")))
7095 (clobber (match_operand 3 "register_operand" "=r"))]
7096 "!SIBLING_CALL_P (insn)
7097 && TARGET_SMALL_EXEC
7098 && GET_MODE (operands[3]) == Pmode"
7100 [(set_attr "op_type" "RI")
7101 (set_attr "type" "jsr")])
7103 (define_insn "*brasl_r"
7104 [(set (match_operand 0 "" "")
7105 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7106 (match_operand 2 "const_int_operand" "n")))
7107 (clobber (match_operand 3 "register_operand" "=r"))]
7108 "!SIBLING_CALL_P (insn)
7110 && GET_MODE (operands[3]) == Pmode"
7112 [(set_attr "op_type" "RIL")
7113 (set_attr "type" "jsr")])
7115 (define_insn "*basr_r"
7116 [(set (match_operand 0 "" "")
7117 (call (mem:QI (match_operand 1 "address_operand" "U"))
7118 (match_operand 2 "const_int_operand" "n")))
7119 (clobber (match_operand 3 "register_operand" "=r"))]
7120 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7122 if (get_attr_op_type (insn) == OP_TYPE_RR)
7123 return "basr\t%3,%1";
7125 return "bas\t%3,%a1";
7127 [(set (attr "op_type")
7128 (if_then_else (match_operand 1 "register_operand" "")
7129 (const_string "RR") (const_string "RX")))
7130 (set_attr "type" "jsr")
7131 (set_attr "atype" "agen")])
7134 ;;- Thread-local storage support.
7137 (define_expand "get_tp_64"
7138 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
7142 (define_expand "get_tp_31"
7143 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
7147 (define_expand "set_tp_64"
7148 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
7149 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
7153 (define_expand "set_tp_31"
7154 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
7155 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
7159 (define_insn "*set_tp"
7160 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
7163 [(set_attr "type" "none")
7164 (set_attr "length" "0")])
7166 (define_insn "*tls_load_64"
7167 [(set (match_operand:DI 0 "register_operand" "=d")
7168 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7169 (match_operand:DI 2 "" "")]
7173 [(set_attr "op_type" "RXE")])
7175 (define_insn "*tls_load_31"
7176 [(set (match_operand:SI 0 "register_operand" "=d,d")
7177 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7178 (match_operand:SI 2 "" "")]
7184 [(set_attr "op_type" "RX,RXY")])
7186 (define_insn "*bras_tls"
7187 [(set (match_operand 0 "" "")
7188 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7189 (match_operand 2 "const_int_operand" "n")))
7190 (clobber (match_operand 3 "register_operand" "=r"))
7191 (use (match_operand 4 "" ""))]
7192 "!SIBLING_CALL_P (insn)
7193 && TARGET_SMALL_EXEC
7194 && GET_MODE (operands[3]) == Pmode"
7196 [(set_attr "op_type" "RI")
7197 (set_attr "type" "jsr")])
7199 (define_insn "*brasl_tls"
7200 [(set (match_operand 0 "" "")
7201 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7202 (match_operand 2 "const_int_operand" "n")))
7203 (clobber (match_operand 3 "register_operand" "=r"))
7204 (use (match_operand 4 "" ""))]
7205 "!SIBLING_CALL_P (insn)
7207 && GET_MODE (operands[3]) == Pmode"
7209 [(set_attr "op_type" "RIL")
7210 (set_attr "type" "jsr")])
7212 (define_insn "*basr_tls"
7213 [(set (match_operand 0 "" "")
7214 (call (mem:QI (match_operand 1 "address_operand" "U"))
7215 (match_operand 2 "const_int_operand" "n")))
7216 (clobber (match_operand 3 "register_operand" "=r"))
7217 (use (match_operand 4 "" ""))]
7218 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7220 if (get_attr_op_type (insn) == OP_TYPE_RR)
7221 return "basr\t%3,%1%J4";
7223 return "bas\t%3,%a1%J4";
7225 [(set (attr "op_type")
7226 (if_then_else (match_operand 1 "register_operand" "")
7227 (const_string "RR") (const_string "RX")))
7228 (set_attr "type" "jsr")
7229 (set_attr "atype" "agen")])
7232 ;;- Atomic operations
7236 ; memory barrier pattern.
7239 (define_expand "memory_barrier"
7240 [(set (mem:BLK (match_dup 0))
7241 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
7244 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
7245 MEM_VOLATILE_P (operands[0]) = 1;
7248 (define_insn "*memory_barrier"
7249 [(set (match_operand:BLK 0 "" "")
7250 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
7253 [(set_attr "op_type" "RR")])
7256 ; compare and swap patterns.
7259 (define_expand "sync_compare_and_swap<mode>"
7261 [(set (match_operand:TDSI 0 "register_operand" "")
7262 (match_operand:TDSI 1 "memory_operand" ""))
7264 (unspec_volatile:TDSI
7266 (match_operand:TDSI 2 "register_operand" "")
7267 (match_operand:TDSI 3 "register_operand" "")]
7269 (set (reg:CCZ1 CC_REGNUM)
7270 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7273 (define_expand "sync_compare_and_swap_cc<mode>"
7275 [(set (match_operand:TDSI 0 "register_operand" "")
7276 (match_operand:TDSI 1 "memory_operand" ""))
7278 (unspec_volatile:TDSI
7280 (match_operand:TDSI 2 "register_operand" "")
7281 (match_operand:TDSI 3 "register_operand" "")]
7284 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7287 /* Emulate compare. */
7288 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
7289 s390_compare_op0 = operands[1];
7290 s390_compare_op1 = operands[2];
7291 s390_compare_emitted = operands[4];
7294 (define_insn "*sync_compare_and_swap<mode>"
7295 [(set (match_operand:DP 0 "register_operand" "=r")
7296 (match_operand:DP 1 "memory_operand" "+Q"))
7300 (match_operand:DP 2 "register_operand" "0")
7301 (match_operand:DP 3 "register_operand" "r")]
7303 (set (reg:CCZ1 CC_REGNUM)
7304 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7306 "cds<tg>\t%0,%3,%S1"
7307 [(set_attr "op_type" "RS<TE>")
7308 (set_attr "type" "sem")])
7310 (define_insn "*sync_compare_and_swap<mode>"
7311 [(set (match_operand:GPR 0 "register_operand" "=r")
7312 (match_operand:GPR 1 "memory_operand" "+Q"))
7314 (unspec_volatile:GPR
7316 (match_operand:GPR 2 "register_operand" "0")
7317 (match_operand:GPR 3 "register_operand" "r")]
7319 (set (reg:CCZ1 CC_REGNUM)
7320 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7323 [(set_attr "op_type" "RS<E>")
7324 (set_attr "type" "sem")])
7328 ;;- Miscellaneous instructions.
7332 ; allocate stack instruction pattern(s).
7335 (define_expand "allocate_stack"
7336 [(match_operand 0 "general_operand" "")
7337 (match_operand 1 "general_operand" "")]
7340 rtx temp = gen_reg_rtx (Pmode);
7342 emit_move_insn (temp, s390_back_chain_rtx ());
7343 anti_adjust_stack (operands[1]);
7344 emit_move_insn (s390_back_chain_rtx (), temp);
7346 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7352 ; setjmp instruction pattern.
7355 (define_expand "builtin_setjmp_receiver"
7356 [(match_operand 0 "" "")]
7359 emit_insn (s390_load_got ());
7360 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7364 ;; These patterns say how to save and restore the stack pointer. We need not
7365 ;; save the stack pointer at function level since we are careful to
7366 ;; preserve the backchain. At block level, we have to restore the backchain
7367 ;; when we restore the stack pointer.
7369 ;; For nonlocal gotos, we must save both the stack pointer and its
7370 ;; backchain and restore both. Note that in the nonlocal case, the
7371 ;; save area is a memory location.
7373 (define_expand "save_stack_function"
7374 [(match_operand 0 "general_operand" "")
7375 (match_operand 1 "general_operand" "")]
7379 (define_expand "restore_stack_function"
7380 [(match_operand 0 "general_operand" "")
7381 (match_operand 1 "general_operand" "")]
7385 (define_expand "restore_stack_block"
7386 [(match_operand 0 "register_operand" "")
7387 (match_operand 1 "register_operand" "")]
7390 rtx temp = gen_reg_rtx (Pmode);
7392 emit_move_insn (temp, s390_back_chain_rtx ());
7393 emit_move_insn (operands[0], operands[1]);
7394 emit_move_insn (s390_back_chain_rtx (), temp);
7399 (define_expand "save_stack_nonlocal"
7400 [(match_operand 0 "memory_operand" "")
7401 (match_operand 1 "register_operand" "")]
7404 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7405 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7407 /* Copy the backchain to the first word, sp to the second and the
7408 literal pool base to the third. */
7410 if (TARGET_BACKCHAIN)
7412 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7413 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7416 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7417 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7422 (define_expand "restore_stack_nonlocal"
7423 [(match_operand 0 "register_operand" "")
7424 (match_operand 1 "memory_operand" "")]
7427 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7428 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7429 rtx temp = NULL_RTX;
7431 /* Restore the backchain from the first word, sp from the second and the
7432 literal pool base from the third. */
7434 if (TARGET_BACKCHAIN)
7435 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7437 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7438 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7441 emit_move_insn (s390_back_chain_rtx (), temp);
7443 emit_insn (gen_rtx_USE (VOIDmode, base));
7447 (define_expand "exception_receiver"
7451 s390_set_has_landing_pad_p (true);
7456 ; nop instruction pattern(s).
7463 [(set_attr "op_type" "RR")])
7467 ; Special literal pool access instruction pattern(s).
7470 (define_insn "*pool_entry"
7471 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7472 UNSPECV_POOL_ENTRY)]
7475 enum machine_mode mode = GET_MODE (PATTERN (insn));
7476 unsigned int align = GET_MODE_BITSIZE (mode);
7477 s390_output_pool_entry (operands[0], mode, align);
7480 [(set (attr "length")
7481 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7483 (define_insn "pool_align"
7484 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7485 UNSPECV_POOL_ALIGN)]
7488 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7490 (define_insn "pool_section_start"
7491 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7494 [(set_attr "length" "0")])
7496 (define_insn "pool_section_end"
7497 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7500 [(set_attr "length" "0")])
7502 (define_insn "main_base_31_small"
7503 [(set (match_operand 0 "register_operand" "=a")
7504 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7505 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7507 [(set_attr "op_type" "RR")
7508 (set_attr "type" "la")])
7510 (define_insn "main_base_31_large"
7511 [(set (match_operand 0 "register_operand" "=a")
7512 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7513 (set (pc) (label_ref (match_operand 2 "" "")))]
7514 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7516 [(set_attr "op_type" "RI")])
7518 (define_insn "main_base_64"
7519 [(set (match_operand 0 "register_operand" "=a")
7520 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7521 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7523 [(set_attr "op_type" "RIL")
7524 (set_attr "type" "larl")])
7526 (define_insn "main_pool"
7527 [(set (match_operand 0 "register_operand" "=a")
7528 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7529 "GET_MODE (operands[0]) == Pmode"
7534 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7535 (const_string "larl") (const_string "la")))])
7537 (define_insn "reload_base_31"
7538 [(set (match_operand 0 "register_operand" "=a")
7539 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7540 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7541 "basr\t%0,0\;la\t%0,%1-.(%0)"
7542 [(set_attr "length" "6")
7543 (set_attr "type" "la")])
7545 (define_insn "reload_base_64"
7546 [(set (match_operand 0 "register_operand" "=a")
7547 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7548 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7550 [(set_attr "op_type" "RIL")
7551 (set_attr "type" "larl")])
7554 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7559 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7562 ;; Insns related to generating the function prologue and epilogue.
7566 (define_expand "prologue"
7567 [(use (const_int 0))]
7569 "s390_emit_prologue (); DONE;")
7571 (define_expand "epilogue"
7572 [(use (const_int 1))]
7574 "s390_emit_epilogue (false); DONE;")
7576 (define_expand "sibcall_epilogue"
7577 [(use (const_int 0))]
7579 "s390_emit_epilogue (true); DONE;")
7581 (define_insn "*return"
7583 (use (match_operand 0 "register_operand" "a"))]
7584 "GET_MODE (operands[0]) == Pmode"
7586 [(set_attr "op_type" "RR")
7587 (set_attr "type" "jsr")
7588 (set_attr "atype" "agen")])
7591 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7592 ;; pointer. This is used for compatibility.
7594 (define_expand "ptr_extend"
7595 [(set (match_operand:DI 0 "register_operand" "=r")
7596 (match_operand:SI 1 "register_operand" "r"))]
7599 emit_insn (gen_anddi3 (operands[0],
7600 gen_lowpart (DImode, operands[1]),
7601 GEN_INT (0x7fffffff)));
7605 ;; Instruction definition to expand eh_return macro to support
7606 ;; swapping in special linkage return addresses.
7608 (define_expand "eh_return"
7609 [(use (match_operand 0 "register_operand" ""))]
7612 s390_emit_tpf_eh_return (operands[0]);
7617 ; Stack Protector Patterns
7620 (define_expand "stack_protect_set"
7621 [(set (match_operand 0 "memory_operand" "")
7622 (match_operand 1 "memory_operand" ""))]
7625 #ifdef TARGET_THREAD_SSP_OFFSET
7627 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7628 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7631 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
7633 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
7638 (define_insn "stack_protect_set<mode>"
7639 [(set (match_operand:DSI 0 "memory_operand" "=Q")
7640 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
7642 "mvc\t%O0(%G0,%R0),%S1"
7643 [(set_attr "op_type" "SS")])
7645 (define_expand "stack_protect_test"
7646 [(set (reg:CC CC_REGNUM)
7647 (compare (match_operand 0 "memory_operand" "")
7648 (match_operand 1 "memory_operand" "")))
7649 (match_operand 2 "" "")]
7652 #ifdef TARGET_THREAD_SSP_OFFSET
7654 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7655 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7657 s390_compare_op0 = operands[0];
7658 s390_compare_op1 = operands[1];
7659 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
7662 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
7664 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
7666 emit_jump_insn (gen_beq (operands[2]));
7671 (define_insn "stack_protect_test<mode>"
7672 [(set (reg:CCZ CC_REGNUM)
7673 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
7674 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
7676 "clc\t%O0(%G0,%R0),%S1"
7677 [(set_attr "op_type" "SS")])